; -------------------------------------------------------------------------------- ; @Title: SR6x On-Chip Peripherals ; @Props: Released ; @Author: KRZ ; @Changelog: 2022-01-21 ADR ; 2024-05-22 KRZ ; @Manufacturer: STM - ST Microelectronics N.V. ; @Doc: Generated (TRACE32, build: 169329.), based on: SR6P7G7_svd.xml (Ver. 1.0) ; @Core: Cortex-R52+, Cortex-M4F ; @Chip: SR6P7-G7 ; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; ***************************************************************************\n ; \n ; Copyright (c) 2022-2024 STMicroelectronics - All Rights Reserved \n ; \n ; License terms: STMicroelectronics Proprietary in accordance with licensing\n ; terms SLA0098 at www.st.com. \n ; \n ; THIS SOFTWARE IS DISTRIBUTED "AS IS," AND ALL WARRANTIES ARE DISCLAIMED, \n ; INCLUDING MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. \n ; \n ; ***************************************************************************\n\n ; -------------------------------------------------------------------------------- ; $Id: persr6x.per 17928 2024-05-23 14:27:15Z kwisniewski $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 sif (CORENAME()=="CORTEXR52") AUTOINDENT.PUSH AUTOINDENT.OFF tree "Core Registers (Cortex-R52)" AUTOINDENT.PUSH AUTOINDENT.ON center tree tree "ID Registers" rgroup.long c15:0x0010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. "STATE3,Thumb execution environment (thumb-EE) support" "Not supported,?..." bitfld.long 0x00 8.--11. "STATE2,Support for jazelle extension" "Reserved,No cleaning,?..." bitfld.long 0x00 4.--7. "STATE1,Thumb encoding supported by the processor type" "Reserved,Reserved,Reserved,After thumb-2,?..." newline bitfld.long 0x00 0.--3. "STATE0,ARM instruction set support" "Reserved,Supported,?..." rgroup.long c15:0x0110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU support" "Reserved,Enabled,?..." bitfld.long 0x00 24.--27. "VF,Virtualization fractional support" "Not supported,?..." bitfld.long 0x00 20.--23. "SF,Security fractional support" "Reserved,VBAR,?..." newline bitfld.long 0x00 16.--19. "GT,Generic timer support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "VE,Virtualization extensions support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "MPM,Microcontroller programmer's model support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "SE,Security extensions architecture v1 support" "Not supported,?..." bitfld.long 0x00 0.--3. "PM,Standard ARMv4 programmer's model support" "Reserved,Supported,?..." rgroup.long c15:0x0310++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long c15:0x0410++0x00 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Non-cacheable,?..." bitfld.long 0x00 24.--27. "FCSE,Fast context switch memory mappings support" "Not supported,?..." bitfld.long 0x00 20.--23. "AR,Auxiliary register support" "Reserved,Reserved,Control/fault status,?..." newline bitfld.long 0x00 16.--19. "TCM,TCM and associated DMA support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. "OSS,Outer shareable support" "Non-cacheable,?..." newline bitfld.long 0x00 4.--7. "PMSA,Physical memory system architecture (PMSA) support" "Reserved,Reserved,Reserved,Reserved,ARMv8-R base+limit PMSA,?..." bitfld.long 0x00 0.--3. "VMSA,Virtual memory system architecture (VMSA) support" "Not supported,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. "BTB,Branch predictor" "Reserved,Reserved,Reserved,Reserved,No flushing,?..." bitfld.long 0x00 24.--27. "L1TCO,Test and clean operations on data cache/harvard/unified architecture support" "Not supported,?..." bitfld.long 0x00 20.--23. "L1UCMO,L1 cache/all maintenance operations/unified architecture support" "Not supported,?..." newline bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/all maintenance operations/harvard architecture support" "Not supported,?..." bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 cache line maintenance operations by set and way/unified architecture support" "Not supported,?..." bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 cache line maintenance operations by set and way/harvard architecture support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 cache line maintenance operations by MVA/unified architecture support" "Not supported,?..." bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 cache line maintenance operations by MVA/harvard architecture" "Not supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. "HAF,Hardware access flag support" "Not supported,?..." bitfld.long 0x00 24.--27. "WFI,Wait for interrupt stalling support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MBF,Memory barrier operations support" "Reserved,Reserved,DSB/ISB/DMB,?..." newline bitfld.long 0x00 16.--19. "UTLBMO,TLB maintenance operations/unified architecture support" "Not supported,?..." bitfld.long 0x00 12.--15. "HTLBMO,TLB maintenance operations/harvard architecture support" "Not supported,?..." bitfld.long 0x00 8.--11. "HL1CMRO,Cache maintenance range operations/harvard architecture support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "HL1BPCRO,Background prefetch cache range operations/harvard architecture support" "Not supported,?..." bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground prefetch cache range operations/harvard architecture support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. "SS,Supersection support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not supported" bitfld.long 0x00 24.--27. "CMEMSZ,Cached memory size" "4GByte,?..." bitfld.long 0x00 20.--23. "CW,Coherent walk. Indicates whether translation table updates require a clean to the point of unification" "Reserved,Not required,?..." newline bitfld.long 0x00 12.--15. "MB,Maintenance broadcast support" "Reserved,Reserved,Shareability/defined behavior,?..." bitfld.long 0x00 8.--11. "BPM,Invalidate branch predictor support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. "HCMOSW,Invalidate cache by set and way/clean by set and way/invalidate and clean by set and way support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate cache MVA support" "Reserved,Supported,?..." rgroup.long c15:0x0620++0x00 line.long 0x00 "ID_MMFR4,Memory Model Feature Register 4" bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Reserved,Supported,?..." rgroup.long c15:0x0020++0x00 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. "DIVI,Divide instructions support" "Reserved,Reserved,T32/A32,?..." bitfld.long 0x00 20.--23. "DEBI,Debug instructions support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. "CI,Coprocessor instructions support" "Not supported,?..." newline bitfld.long 0x00 12.--15. "CBI,Combined compare and branch instructions support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BI,Bitfield instructions support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "BCI,Bit counting instructions support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "SI,Swap instructions support" "Not supported,?..." rgroup.long c15:0x0120++0x00 line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x00 28.--31. "JI,Jazelle instructions support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. "INTI,Interwork instructions support" "Reserved,Reserved,Reserved,A32-BX like,?..." bitfld.long 0x00 20.--23. "IMMI,Immediate instructions support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "ITEI,If then instructions support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "EXTI,Extend instructions support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "EARI,Exception A and R instructions support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "EXIN,Exception in ARM instructions support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "ENDI,Endian instructions support" "Reserved,Supported,?..." rgroup.long c15:0x0220++0x00 line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x00 28.--31. "RI,Reversal instructions support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. "PSRI,PSR instructions support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "UMI,Advanced unsigned multiply instructions support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "SMI,Advanced signed multiply instructions support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "MI,Multiply instructions support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "II,Multi-access interruptible instructions support" "Reserved,Restartable,?..." newline bitfld.long 0x00 4.--7. "MHI,Memory hint instructions support" "Reserved,Reserved,Reserved,Reserved,PLD/PLI/PLDW,?..." bitfld.long 0x00 0.--3. "LSI,Load and store instructions support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0320++0x00 line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE extensions support" "Not supported,?..." bitfld.long 0x00 24.--27. "NOPI,True NOP instructions support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "TCI,Thumb copy instructions support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TBI,Table branch instructions support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SPI,Synchronization primitive instructions support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "SVCI,SVC instructions support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "SIMDI,Single instruction multiple data (SIMD) instructions support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SI,Saturate instructions support" "Reserved,Supported,?..." rgroup.long c15:0x0420++0x00 line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x00 28.--31. "SWP_FRAC,Memory system locking support" "Not supported,?..." bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M instructions support" "Not supported,?..." bitfld.long 0x00 20.--23. "SPRI,Synchronization primitive instructions" "Supported,?..." newline bitfld.long 0x00 16.--19. "BI,Barrier instructions support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SMCI,SMC instructions support" "Not supported,?..." bitfld.long 0x00 8.--11. "WBI,Write-back instructions support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "WSI,With-shift instructions support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "UI,Unprivileged instructions support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0520++0x00 line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5" bitfld.long 0x00 16.--19. "CRC32,CRC32 instructions support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SHA2,SHA2 instructions support" "Not supported,?..." bitfld.long 0x00 8.--11. "SHA1,SHA1 instructions support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "AES,AES instructions support" "Not supported,?..." bitfld.long 0x00 0.--3. "SEVL,SEVL instructions support" "Reserved,Supported,?..." rgroup.long c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance monitor model support" "Reserved,Reserved,Reserved,PMUv3,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped debug model for M profile processors support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace model (memory-mapped) support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-based trace debug model support" "Not supported,?..." bitfld.long 0x00 0.--3. "CDM_CB,Secure debug model (Coprocessor) support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.long c15:0x0000++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x00 24.--31. 1. "IMPL,Implementer code" bitfld.long 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "ARCH,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme" hexmask.long.word 0x00 4.--15. 1. "PART,Primary part number" newline bitfld.long 0x00 0.--3. "REV,Revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x0700++0x00 line.long 0x00 "MIDR,Main ID Register (Alias)" hexmask.long.byte 0x00 24.--31. 1. "IMPL,Implementer code" bitfld.long 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "ARCH,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme" hexmask.long.word 0x00 4.--15. 1. "PART,Primary part number" newline bitfld.long 0x00 0.--3. "REV,Revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x0200++0x00 line.long 0x00 "TCMTR,TCM Type Register" bitfld.long 0x00 29.--31. "TCMS,TCM implemented" "No TCMs,Reserved,Reserved,Reserved,1 TCMs,?..." bitfld.long 0x00 2. "CTCM,CTCM implemented with non zero size" "Not implemented,Implemented" bitfld.long 0x00 1. "BTCM,BTCM implemented with non zero size" "Not implemented,Implemented" newline bitfld.long 0x00 0. "ATCM,ATCM implemented with non zero size" "Not implemented,Implemented" rgroup.long c15:0x0300++0x00 line.long 0x00 "TLBTR,TLB Type Register" rgroup.long c15:0x0500++0x00 line.long 0x00 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. "U,Single core system as distinct from core 0 in a cluster" "Part of a cluster,?..." bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..." newline hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. The least significant affinity field for this PE in the system" hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. The intermediate affinity level field for this PE in the system" hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. The most significant affinity level field for this PE in the system" rgroup.long c15:0x0600++0x00 line.long 0x00 "REVIDR,Revision ID Register" hexmask.long.word 0x00 0.--11. 1. "IDNUMBER,Implementation-specific revision information" rgroup.long c15:0x1700++0x00 line.long 0x00 "AIDR,Auxiliary ID Register" tree.end tree "System Control and Configuration" group.long c15:0x0001++0x00 line.long 0x00 "SCTLR,System Control Register" bitfld.long 0x00 30. "TE,Thumb exception enable" "A32,T32" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" rbitfld.long 0x00 21. "FI,Fast interrupts configuration enable" "Disabled,Enabled" newline bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies EL1 Execute Never (XN)" "Not forced,Forced" bitfld.long 0x00 19. "WXN,Write permission implies Execute Never (XN)" "Not forced,Forced" newline bitfld.long 0x00 18. "NTWE,Do not trap WFE (Wait for Event) instruction" "Trapped,Not trapped" bitfld.long 0x00 17. "BR,Background region enable" "Disabled,Enabled" newline bitfld.long 0x00 16. "NTWI,Do not trap WFI (Wait For Interrupt) instruction" "Trapped,Not trapped" bitfld.long 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND instruction disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT instruction disable" "No,Yes" bitfld.long 0x00 5. "CP15BEN,CP15* barrier operations enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "C,Data/Unified cache enable" "Disabled,Enabled" bitfld.long 0x00 1. "A,Alignment fault checking enable" "Disabled,Enabled" bitfld.long 0x00 0. "M,EL1-controlled MPU enable" "Disabled,Enabled" group.long c15:0x0201++0x00 line.long 0x00 "CPACR,Architectural Feature Access Control Register" bitfld.long 0x00 31. "ASEDIS,Disable advanced SIMD extension functionality" "No,Yes" bitfld.long 0x00 22.--23. "CP11,Coprocessor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x00 20.--21. "CP10,Coprocessor access control" "Denied,Privileged,Reserved,Full" rgroup.long c15:0x0101++0x00 line.long 0x00 "ACTLR,Auxiliary Control Register" rgroup.long c15:0x0301++0x00 line.long 0x00 "ACTLR2,Auxiliary Control Register 2" rgroup.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" group.long c15:0x000B++0x00 line.long 0x00 "IMP_SLAVEPCTLR,Slave Port Control Register" bitfld.long 0x00 0.--1. "TCMACCLVL,Indicates the privilege level required for the AXIS to access the TCM" "Denied,Privileged,Reserved,Full" group.long c15:0x000C++0x00 line.long 0x00 "VBAR,Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector base address" rgroup.long c15:0x010C++0x00 line.long 0x00 "RVBAR,Reset Vector Base Address Register" hexmask.long 0x00 1.--31. 0x02 "ADDR,Reset address" rgroup.long c15:0x001C++0x00 line.long 0x00 "ISR,Interrupt Status Register" bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending" bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending" bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending" group.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" bitfld.long 0x00 2.--4. "PORT,Memory or port that caused the fault" "AXIM,Flash interface,LLPP,Internal interface,ATCM,BTCM,CTCM,Overlap" bitfld.long 0x00 0.--1. "TYPE,Fault type" "Other error,External bus control,TCM/cache/bus data,Bus timeout" group.long c15:0x0115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" bitfld.long 0x00 2.--4. "PORT,Memory or port that caused the fault" "AXIM,Flash interface,LLPP,Reserved,ATCM,BTCM,CTCM,Overlap" bitfld.long 0x00 0.--1. "TYPE,Fault type" "Other error,External bus control,TCM/cache/bus data,Bus timeout" group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. "CM,Cache maintenance fault" "No fault,Fault" bitfld.long 0x00 12. "EXT,External abort qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access caused an abort type" "Read,Write" bitfld.long 0x00 0.--5. "STATUS,Fault status bits" "Reserved,Reserved,Reserved,Reserved,Translation fault/0th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault/0th level,Reserved,Reserved,Reserved,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access,Asynchronous parity error on memory access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,LDREX or STREX,?..." group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 16. "FNV,FAR not Valid for a Synchronous External abort" "Valid,?..." bitfld.long 0x00 12. "EXT,External abort qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 9. "LPAE,Translation table formats on Data Abort exception" "Reserved,Long-descriptor" bitfld.long 0x00 0.--5. "STATUS,Fault status bits" "Reserved,Reserved,Reserved,Reserved,Translation fault/0th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault/0th level,Reserved,Reserved,Reserved,Synchronous external abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..." group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" rgroup.long c15:0x000D++0x00 line.long 0x00 "FCSEIDR,FCSE PID Register" rgroup.long c15:0x103F++0x00 line.long 0x00 "IMP_CBAR,Configuration Base Address Register" hexmask.long.word 0x00 21.--31. 0x20 "PERIPHBASE,Upper bits of base physical address of memory-mapped peripherals" group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,Thread Pointer ID Register Unprivileged Read-Write" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,Thread Pointer ID Register Unprivileged Read-Only" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,Thread Pointer ID Register Privileged Read-Write" tree "System Instructions" wgroup.long c15:0x0017++0x00 line.long 0x00 "ICIALLUIS,ICIALLUIS" wgroup.long c15:0x0617++0x00 line.long 0x00 "BPIALLIS,BPIALLIS" wgroup.long c15:0x0057++0x00 line.long 0x00 "ICIALLU,ICIALLU" wgroup.long c15:0x0157++0x00 line.long 0x00 "ICIMVAU,ICIMVAU" wgroup.long c15:0x0457++0x00 line.long 0x00 "CP15ISB,CP15ISB" wgroup.long c15:0x0657++0x00 line.long 0x00 "BPIALL,BPIALL" wgroup.long c15:0x0757++0x00 line.long 0x00 "BPIMVA,BPIMVA" wgroup.long c15:0x0167++0x00 line.long 0x00 "DCIMVAC,DCIMVAC" wgroup.long c15:0x0267++0x00 line.long 0x00 "DCISW,DCISW" wgroup.long c15:0x0087++0x00 line.long 0x00 "ATS1CPR,ATS1CPR" wgroup.long c15:0x0187++0x00 line.long 0x00 "ATS1CPW,ATS1CPW" wgroup.long c15:0x0287++0x00 line.long 0x00 "ATS1CUR,ATS1CUR" wgroup.long c15:0x0387++0x00 line.long 0x00 "ATS1CUW,ATS1CUW" wgroup.long c15:0x0487++0x00 line.long 0x00 "ATS12NSOPR,ATS12NSOPR" wgroup.long c15:0x0587++0x00 line.long 0x00 "ATS12NSOPW,ATS12NSOPW" wgroup.long c15:0x0687++0x00 line.long 0x00 "ATS12NSOUR,ATS12NSOUR" wgroup.long c15:0x0787++0x00 line.long 0x00 "ATS12NSOUW,ATS12NSOUW" wgroup.long c15:0x01A7++0x00 line.long 0x00 "DCCMVAC,DCCMVAC" wgroup.long c15:0x02A7++0x00 line.long 0x00 "DCCSW,DCCSW" wgroup.long c15:0x04A7++0x00 line.long 0x00 "CP15DSB,CP15DSB" wgroup.long c15:0x05A7++0x00 line.long 0x00 "CP15DMB,CP15DMB" wgroup.long c15:0x01B7++0x00 line.long 0x00 "DCCMVAU,DCCMVAU" wgroup.long c15:0x01E7++0x00 line.long 0x00 "DCCIMVAC,DCCIMVAC" wgroup.long c15:0x02E7++0x00 line.long 0x00 "DCCISW,DCCISW" wgroup.long c15:0x4087++0x00 line.long 0x00 "ATS1HR,ATS1HR" wgroup.long c15:0x4187++0x00 line.long 0x00 "ATS1HW,ATS1HW" tree.end tree.end tree "MPU Control and Configuration" group.long c15:0x0001++0x00 line.long 0x00 "SCTLR,System Control Register" bitfld.long 0x00 30. "TE,Thumb exception enable" "A32,T32" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" rbitfld.long 0x00 21. "FI,Fast interrupts configuration enable" "Disabled,Enabled" newline bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies EL1 Execute Never (XN)" "Not forced,Forced" bitfld.long 0x00 19. "WXN,Write permission implies Execute Never (XN)" "Not forced,Forced" newline bitfld.long 0x00 18. "NTWE,Do not trap WFE (Wait for Event) instruction" "Trapped,Not trapped" bitfld.long 0x00 17. "BR,Background region enable" "Disabled,Enabled" newline bitfld.long 0x00 16. "NTWI,Do not trap WFI (Wait For Interrupt) instruction" "Trapped,Not trapped" bitfld.long 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND instruction disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT instruction disable" "No,Yes" bitfld.long 0x00 5. "CP15BEN,CP15* barrier operations enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "C,Data/Unified cache enable" "Disabled,Enabled" bitfld.long 0x00 1. "A,Alignment fault checking enable" "Disabled,Enabled" bitfld.long 0x00 0. "M,EL1-controlled MPU enable" "Disabled,Enabled" if (((per.l(c15:0x10070))&0x1)==0x0) group.quad c15:0x10070++0x01 line.quad 0x00 "PAR,Physical Address Register" hexmask.quad.byte 0x00 56.--63. 1. "ATTR,Memory attributes for the returned PA" hexmask.quad.long 0x00 12.--31. 0x1000 "PA,Physical address" newline bitfld.quad 0x00 9. "NS,Non-secure" "Reserved,Yes" bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" else group.quad c15:0x10070++0x01 line.quad 0x00 "PAR,Physical Address Register" bitfld.quad 0x00 9. "FSTAGE,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. "S2WLK,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,?..." newline bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "Reserved,Reserved,Reserved,Reserved,Translation fault/0th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault/0th level,Reserved,Reserved,Reserved,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access,Asynchronous parity error on memory access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Unsupported Exclusive access,?..." newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" endif tree.open "Memory Attribute Indirection Registers" group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" rgroup.long c15:0x003A++0x00 line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0" rgroup.long c15:0x013A++0x00 line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1" rgroup.long c15:0x403A++0x00 line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0" rgroup.long c15:0x413A++0x00 line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1" group.long c15:0x010D++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" tree.end newline group.long c15:(0x0019+0x0)++0x00 line.long 0x00 "IMP_ATCMREGIONR,TCM Region Register A" hexmask.long.long 0x00 13.--31. 0x2000 "BASEADDRESS,TCM base address" bitfld.long 0x00 8. "WAITSTATES,Wait states for TCM accesses" "0,1" newline bitfld.long 0x00 2.--6. "SIZE,TCM size" "No TCM,Reserved,Reserved,Reserved,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,?..." bitfld.long 0x00 1. "ENABLEEL2,Enable TCM at EL2" "Disabled,Enabled" newline bitfld.long 0x00 0. "ENABLEEL10,Enable TCM at EL1 and EL0" "Disabled,Enabled" group.long c15:(0x0019+0x100)++0x00 line.long 0x00 "IMP_BTCMREGIONR,TCM Region Register B" hexmask.long.long 0x00 13.--31. 0x2000 "BASEADDRESS,TCM base address" bitfld.long 0x00 8. "WAITSTATES,Wait states for TCM accesses" "0,1" newline bitfld.long 0x00 2.--6. "SIZE,TCM size" "No TCM,Reserved,Reserved,Reserved,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,?..." bitfld.long 0x00 1. "ENABLEEL2,Enable TCM at EL2" "Disabled,Enabled" newline bitfld.long 0x00 0. "ENABLEEL10,Enable TCM at EL1 and EL0" "Disabled,Enabled" group.long c15:(0x0019+0x200)++0x00 line.long 0x00 "IMP_CTCMREGIONR,TCM Region Register C" hexmask.long.long 0x00 13.--31. 0x2000 "BASEADDRESS,TCM base address" bitfld.long 0x00 8. "WAITSTATES,Wait states for TCM accesses" "0,1" newline bitfld.long 0x00 2.--6. "SIZE,TCM size" "No TCM,Reserved,Reserved,Reserved,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,?..." bitfld.long 0x00 1. "ENABLEEL2,Enable TCM at EL2" "Disabled,Enabled" newline bitfld.long 0x00 0. "ENABLEEL10,Enable TCM at EL1 and EL0" "Disabled,Enabled" group.long c15:0x1219++0x00 line.long 0x00 "IMP_MEMPROTCTLR,Memory Protection Control Register" rbitfld.long 0x00 5. "FLASHPROTIMP,Flash protection implemented" "Not implemented,Implemented" rbitfld.long 0x00 4. "RAMPROTIMP,RAM protection implemented" "Not implemented,Implemented" newline bitfld.long 0x00 1. "FLASHPROTEN,Flash interface protection enable" "Disabled,Enabled" bitfld.long 0x00 0. "RAMPROTEN,TCM and L1 cache RAM protection enable" "Disabled,Enabled" group.long c15:0x000F++0x00 line.long 0x00 "IMP_PERIPHPREGIONR,Peripheral Port Region Register" hexmask.long.tbyte 0x00 12.--31. 0x10 "BASEADDRESS,Peripheral port region base address" bitfld.long 0x00 2.--6. "SIZE,Peripheral port region size" "No peripheral port,Reserved,Reserved,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,?..." newline bitfld.long 0x00 1. "ENABLEEL2,Enable peripheral port at EL2" "Disabled,Enabled" bitfld.long 0x00 0. "ENABLEEL10,Enable peripheral port at EL1 and EL0" "Disabled,Enabled" group.long c15:0x010F++0x00 line.long 0x00 "IMP_FLASHIFREGIONR,Flash Interface Region Register" hexmask.long.byte 0x00 27.--31. 0x08 "BASEADDRESS,Peripheral port region base address" bitfld.long 0x00 2.--6. "SIZE,Flash interface region size" "No flash,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,?..." newline bitfld.long 0x00 0. "ENABLE,Enable the flash interface" "Disabled,Enabled" rgroup.long c15:0x002F++0x00 line.long 0x00 "IMP_BUILDOPTR,Build Options Register" bitfld.long 0x00 30.--31. "LOCK_STEP,DCLS functionality implemented" "Not implemented,DCLS configuration,Split/lock configuration,?..." bitfld.long 0x00 28.--29. "BUS_PROTECTION,Bus protection scheme implemented (signal integrity/interconnect protection)" "Not implemented,Implemented/Not implemented,Implemented,?..." newline bitfld.long 0x00 26.--27. "FLASH_DATA_ECC_SCHEME,Flash memory interface data ECC chunk size" "Reserved,64 bit,128 bit,?..." bitfld.long 0x00 20.--23. "AXIS_ID_WIDTH,Width of AXIS interface ID signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8. "NUM_GIC_EXT_DEV,Number of external device interfaces to the GIC" "0,1" bitfld.long 0x00 0.--3. "NUM_CORES,Number of cores in the Cortex-R52 processor" "0,1,2,3,?..." rgroup.long c15:0x072F++0x00 line.long 0x00 "IMP_PINOPTR,Pin Options Register" hexmask.long.byte 0x00 24.--31. 1. "CFGAXISTCMBASEADDR,Value of the CFGAXISTCMBASEADDR signal" bitfld.long 0x00 23. "CFGSLSPLIT,Value of the CFGSLSPLIT signal" "0,1" newline bitfld.long 0x00 21.--22. "CFGCLUSTERUTID,Value of the CFGCLUSTERUTID signal" "0,1,2,3" bitfld.long 0x00 18. "CFGFLASHPROTEN,Value of the CFGFLASHPROTEN signal" "0,1" newline bitfld.long 0x00 17. "CFGRAMPROTEN,Value of the CFGRAMPROTEN signal" "0,1" bitfld.long 0x00 16. "CFGINITREG,Value of the CFGINITREG signal" "0,1" newline bitfld.long 0x00 15. "CFGMRPEN,Value of the CFGMRPEN signal" "0,1" bitfld.long 0x00 6. "CFGL1CACHEINVDISX,Value of the CFGL1CACHEINVDISx signal" "0,1" newline bitfld.long 0x00 5. "CFGENDIANNESSX,Value of the CFGENDIANNESSX signal" "0,1" bitfld.long 0x00 4. "CFGTHUMBEXCEPTIONSX,Value of the CFGTHUMBEXCEPTIONSx signal" "0,1" newline bitfld.long 0x00 2. "CFGFLASHENX,Value of the CFGFLASHENx signal" "0,1" bitfld.long 0x00 0. "CFGTCMBOOTX,Value of the CFGTCMBOOTx signal" "0,1" group.long c15:0x113F++0x00 line.long 0x00 "IMP_QOSR,Quality Of Service Register" bitfld.long 0x00 8.--11. "AWQOS[3:0],QoS identifier sent on the write address channel for each write transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "ARQOS[3:0],QoS identifier sent on the read address channel for each read transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long c15:0x123F++0x00 line.long 0x00 "IMP_BUSTIMEOUTR,Bus Timeout Register" hexmask.long.byte 0x00 24.--31. 1. "MAXCYCLESBY16FLASH,Flash interface timeout value in cycles divided by 16" hexmask.long.byte 0x00 16.--23. 1. "MAXCYCLESBY16LLPP,LLPP timeout value in cycles divided by 16" newline hexmask.long.byte 0x00 8.--15. 1. "MAXCYCLESBY16AXIM,AXIM interface timeout value in cycles divided by 16" bitfld.long 0x00 6. "ABORTFLASH,Abort flash access" "Not aborted,Aborted" newline bitfld.long 0x00 5. "ABORTLLPP,Abort LLPP access" "Not aborted,Aborted" bitfld.long 0x00 4. "ABORTAXIM,Abort AXIM access" "Not aborted,Aborted" newline bitfld.long 0x00 2. "ENABLEFLASH,Timeout counter enable for flash interface" "Disabled,Enabled" bitfld.long 0x00 1. "ENABLELLPP,Timeout counter enable for LLPP" "Disabled,Enabled" newline bitfld.long 0x00 0. "ENABLEAXIM,Timeout counter enable for AXIM interface" "Disabled,Enabled" group.long c15:0x143F++0x00 line.long 0x00 "IMP_INTMONR,Interrupt Monitoring Register" hexmask.long.byte 0x00 8.--15. 1. "MAXCYCLESBY16,Maximum count divided by 16" bitfld.long 0x00 4. "MODE,Operation mode of the counter" "Watchdog,Maximum value monitor" newline bitfld.long 0x00 2. "ENABLESER,Enable counting of cycles in which physical system errors are masked" "Disabled,Enabled" bitfld.long 0x00 1. "ENABLEIRQ,Enable counting of physical interrupts that cannot be taken" "Disabled,Enabled" newline bitfld.long 0x00 0. "ENABLEFIQ,Enable counting of fast interrupts that cannot be taken" "Disabled,Enabled" group.long c15:(0x200F+0x0)++0x00 line.long 0x00 "IMP_ICERR0,Instruction Cache Error Record Register 0" hexmask.long.byte 0x00 24.--31. 1. "RAMID,RAM bank" hexmask.long.byte 0x00 4.--10. 1. "INDEX,Instruction cache index" newline bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid" group.long c15:(0x200F+0x100)++0x00 line.long 0x00 "IMP_ICERR1,Instruction Cache Error Record Register 1" hexmask.long.byte 0x00 24.--31. 1. "RAMID,RAM bank" hexmask.long.byte 0x00 4.--10. 1. "INDEX,Instruction cache index" newline bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid" group.long c15:(0x201F+0x0)++0x00 line.long 0x00 "IMP_DCERR0,Data Cache Error Record Register 0" hexmask.long.word 0x00 20.--31. 1. "RAMID,RAM bank" hexmask.long.byte 0x00 4.--10. 1. "INDEX,Data cache index" newline bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid" group.long c15:(0x201F+0x100)++0x00 line.long 0x00 "IMP_DCERR1,Data Cache Error Record Register 1" hexmask.long.word 0x00 20.--31. 1. "RAMID,RAM bank" hexmask.long.byte 0x00 4.--10. 1. "INDEX,Data cache index" newline bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid" group.long c15:(0x202F+0x0)++0x00 line.long 0x00 "IMP_TCMERR0,TCM Error Record Register 0" hexmask.long.byte 0x00 24.--31. 1. "RAMID,RAM bank" hexmask.long.tbyte 0x00 4.--20. 1. "INDEX,Bits [19:3] of the access address" newline bitfld.long 0x00 1. "FATAL,Fatal error" "Correctable,Fatal" bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid" group.long c15:(0x202F+0x100)++0x00 line.long 0x00 "IMP_TCMERR1,TCM Error Record Register 1" hexmask.long.byte 0x00 24.--31. 1. "RAMID,RAM bank" hexmask.long.tbyte 0x00 4.--20. 1. "INDEX,Bits [19:3] of the access address" newline bitfld.long 0x00 1. "FATAL,Fatal error" "Correctable,Fatal" bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid" rgroup.long c15:(0x222F+0x0)++0x00 line.long 0x00 "IMP_TCMSYNDR0,TCM Syndrome Register 0" hexmask.long.byte 0x00 8.--14. 1. "BANK1,Syndrome for a bank 1 error" hexmask.long.byte 0x00 0.--7. 1. "BANK0,Syndrome for a bank 0 error" rgroup.long c15:(0x222F+0x100)++0x00 line.long 0x00 "IMP_TCMSYNDR1,TCM Syndrome Register 1" hexmask.long.byte 0x00 8.--14. 1. "BANK1,Syndrome for a bank 1 error" hexmask.long.byte 0x00 0.--7. 1. "BANK0,Syndrome for a bank 0 error" group.long c15:(0x203F+0x0)++0x00 line.long 0x00 "IMP_FLASHERR0,Flash Error Record Register 0" hexmask.long 0x00 4.--28. 1. "INDEX,Bits [25:1] of the access address" bitfld.long 0x00 2. "LATE,Late error" "Not late,Late" newline bitfld.long 0x00 1. "FATAL,Fatal error" "Correctable,Fatal" bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid" group.long c15:(0x203F+0x100)++0x00 line.long 0x00 "IMP_FLASHERR1,Flash Error Record Register 1" hexmask.long 0x00 4.--28. 1. "INDEX,Bits [25:1] of the access address" bitfld.long 0x00 2. "LATE,Late error" "Not late,Late" newline bitfld.long 0x00 1. "FATAL,Fatal error" "Correctable,Fatal" bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid" rgroup.long c15:0x400F++0x00 line.long 0x00 "IMP_TESTR0,Test Register 0" bitfld.long 0x00 5. "VSEI,Virtual system error interrupt signal value" "0,1" bitfld.long 0x00 4. "SEI,System error interrupt signal value" "0,1" newline bitfld.long 0x00 3. "VIRQ,Virtual IRQ interrupt signal value" "0,1" bitfld.long 0x00 2. "IRQ,IRQ interrupt signal value" "0,1" newline bitfld.long 0x00 1. "VFIQ,Virtual FIQ interrupt signal value" "0,1" bitfld.long 0x00 0. "FIQ,FIQ interrupt signal value" "0,1" wgroup.long c15:0x410F++0x00 line.long 0x00 "IMP_TESTR1,Test Register 1" tree.end tree "Memory Protection Unit PL1" rgroup.long c15:0x400++0x00 line.long 0x00 "MPUIR,MPU Type Register" bitfld.long 0x00 8.--15. 1. "DREGION,Number of programmable memory regions" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16,Reserved,Reserved,Reserved,20,Reserved,Reserved,Reserved,24,?..." bitfld.long 0x00 0. "NU,Not unified MPU" "Unified,?..." if (((per.l(c15:0x400))&0xFF00)>=0x1800) group.long c15:0x0126++0x00 line.long 0x00 "PRSELR,Protection Region Selection Register" bitfld.long 0x00 0.--4. "REGION,Indicates the memory region accessed by PRBAR and PRBAR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." elif (((per.l(c15:0x400))&0xFF00)>=0x1400) group.long c15:0x0126++0x00 line.long 0x00 "PRSELR,Protection Region Selection Register" bitfld.long 0x00 0.--4. "REGION,Indicates the memory region accessed by PRBAR and PRBAR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..." elif (((per.l(c15:0x400))&0xFF00)>=0x1000) group.long c15:0x0126++0x00 line.long 0x00 "PRSELR,Protection Region Selection Register" bitfld.long 0x00 0.--3. "REGION,Indicates the memory region accessed by PRBAR and PRBAR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else hgroup.long c15:0x0126++0x00 hide.long 0x00 "PRSELR,Protection Region Selection Register" endif group.long c15:0x0036++0x00 line.long 0x00 "PRBAR,Protection Region Base Address Register" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:0x0136++0x00 line.long 0x00 "PRLAR,Protection Region Limit Address Register" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" tree "MPU regions" if (((per.l(c15:0x400))&0xFF00)>=0x1000) group.long c15:(0x0086+0x0)++0x00 "Region 0" line.long 0x00 "PRBAR0,Protection Region Base Address Register 0" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0186+0x0)++0x00 line.long 0x00 "PRLAR0,Protection Region Limit Address Register 0" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0486+0x0)++0x00 "Region 1" line.long 0x00 "PRBAR1,Protection Region Base Address Register 1" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0586+0x0)++0x00 line.long 0x00 "PRLAR1,Protection Region Limit Address Register 1" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0086+0x10)++0x00 "Region 2" line.long 0x00 "PRBAR2,Protection Region Base Address Register 2" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0186+0x10)++0x00 line.long 0x00 "PRLAR2,Protection Region Limit Address Register 2" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0486+0x10)++0x00 "Region 3" line.long 0x00 "PRBAR3,Protection Region Base Address Register 3" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0586+0x10)++0x00 line.long 0x00 "PRLAR3,Protection Region Limit Address Register 3" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0086+0x20)++0x00 "Region 4" line.long 0x00 "PRBAR4,Protection Region Base Address Register 4" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0186+0x20)++0x00 line.long 0x00 "PRLAR4,Protection Region Limit Address Register 4" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0486+0x20)++0x00 "Region 5" line.long 0x00 "PRBAR5,Protection Region Base Address Register 5" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0586+0x20)++0x00 line.long 0x00 "PRLAR5,Protection Region Limit Address Register 5" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0086+0x30)++0x00 "Region 6" line.long 0x00 "PRBAR6,Protection Region Base Address Register 6" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0186+0x30)++0x00 line.long 0x00 "PRLAR6,Protection Region Limit Address Register 6" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0486+0x30)++0x00 "Region 7" line.long 0x00 "PRBAR7,Protection Region Base Address Register 7" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0586+0x30)++0x00 line.long 0x00 "PRLAR7,Protection Region Limit Address Register 7" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0086+0x40)++0x00 "Region 8" line.long 0x00 "PRBAR8,Protection Region Base Address Register 8" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0186+0x40)++0x00 line.long 0x00 "PRLAR8,Protection Region Limit Address Register 8" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0486+0x40)++0x00 "Region 9" line.long 0x00 "PRBAR9,Protection Region Base Address Register 9" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0586+0x40)++0x00 line.long 0x00 "PRLAR9,Protection Region Limit Address Register 9" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0086+0x50)++0x00 "Region 10" line.long 0x00 "PRBAR10,Protection Region Base Address Register 10" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0186+0x50)++0x00 line.long 0x00 "PRLAR10,Protection Region Limit Address Register 10" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0486+0x50)++0x00 "Region 11" line.long 0x00 "PRBAR11,Protection Region Base Address Register 11" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0586+0x50)++0x00 line.long 0x00 "PRLAR11,Protection Region Limit Address Register 11" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0086+0x60)++0x00 "Region 12" line.long 0x00 "PRBAR12,Protection Region Base Address Register 12" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0186+0x60)++0x00 line.long 0x00 "PRLAR12,Protection Region Limit Address Register 12" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0486+0x60)++0x00 "Region 13" line.long 0x00 "PRBAR13,Protection Region Base Address Register 13" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0586+0x60)++0x00 line.long 0x00 "PRLAR13,Protection Region Limit Address Register 13" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0086+0x70)++0x00 "Region 14" line.long 0x00 "PRBAR14,Protection Region Base Address Register 14" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0186+0x70)++0x00 line.long 0x00 "PRLAR14,Protection Region Limit Address Register 14" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0486+0x70)++0x00 "Region 15" line.long 0x00 "PRBAR15,Protection Region Base Address Register 15" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0586+0x70)++0x00 line.long 0x00 "PRLAR15,Protection Region Limit Address Register 15" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" else hgroup.long c15:(0x0086+0x0)++0x00 "Region 0 (not implemented)" hide.long 0x00 "PRBAR0,Protection Region Base Address Register 0" newline hgroup.long c15:(0x0186+0x0)++0x00 hide.long 0x00 "PRLAR0,Protection Region Limit Address Register 0" hgroup.long c15:(0x0486+0x0)++0x00 "Region 1 (not implemented)" hide.long 0x00 "PRBAR1,Protection Region Base Address Register 1" newline hgroup.long c15:(0x0586+0x0)++0x00 hide.long 0x00 "PRLAR1,Protection Region Limit Address Register 1" hgroup.long c15:(0x0086+0x10)++0x00 "Region 2 (not implemented)" hide.long 0x00 "PRBAR2,Protection Region Base Address Register 2" newline hgroup.long c15:(0x0186+0x10)++0x00 hide.long 0x00 "PRLAR2,Protection Region Limit Address Register 2" hgroup.long c15:(0x0486+0x10)++0x00 "Region 3 (not implemented)" hide.long 0x00 "PRBAR3,Protection Region Base Address Register 3" newline hgroup.long c15:(0x0586+0x10)++0x00 hide.long 0x00 "PRLAR3,Protection Region Limit Address Register 3" hgroup.long c15:(0x0086+0x20)++0x00 "Region 4 (not implemented)" hide.long 0x00 "PRBAR4,Protection Region Base Address Register 4" newline hgroup.long c15:(0x0186+0x20)++0x00 hide.long 0x00 "PRLAR4,Protection Region Limit Address Register 4" hgroup.long c15:(0x0486+0x20)++0x00 "Region 5 (not implemented)" hide.long 0x00 "PRBAR5,Protection Region Base Address Register 5" newline hgroup.long c15:(0x0586+0x20)++0x00 hide.long 0x00 "PRLAR5,Protection Region Limit Address Register 5" hgroup.long c15:(0x0086+0x30)++0x00 "Region 6 (not implemented)" hide.long 0x00 "PRBAR6,Protection Region Base Address Register 6" newline hgroup.long c15:(0x0186+0x30)++0x00 hide.long 0x00 "PRLAR6,Protection Region Limit Address Register 6" hgroup.long c15:(0x0486+0x30)++0x00 "Region 7 (not implemented)" hide.long 0x00 "PRBAR7,Protection Region Base Address Register 7" newline hgroup.long c15:(0x0586+0x30)++0x00 hide.long 0x00 "PRLAR7,Protection Region Limit Address Register 7" hgroup.long c15:(0x0086+0x40)++0x00 "Region 8 (not implemented)" hide.long 0x00 "PRBAR8,Protection Region Base Address Register 8" newline hgroup.long c15:(0x0186+0x40)++0x00 hide.long 0x00 "PRLAR8,Protection Region Limit Address Register 8" hgroup.long c15:(0x0486+0x40)++0x00 "Region 9 (not implemented)" hide.long 0x00 "PRBAR9,Protection Region Base Address Register 9" newline hgroup.long c15:(0x0586+0x40)++0x00 hide.long 0x00 "PRLAR9,Protection Region Limit Address Register 9" hgroup.long c15:(0x0086+0x50)++0x00 "Region 10 (not implemented)" hide.long 0x00 "PRBAR10,Protection Region Base Address Register 10" newline hgroup.long c15:(0x0186+0x50)++0x00 hide.long 0x00 "PRLAR10,Protection Region Limit Address Register 10" hgroup.long c15:(0x0486+0x50)++0x00 "Region 11 (not implemented)" hide.long 0x00 "PRBAR11,Protection Region Base Address Register 11" newline hgroup.long c15:(0x0586+0x50)++0x00 hide.long 0x00 "PRLAR11,Protection Region Limit Address Register 11" hgroup.long c15:(0x0086+0x60)++0x00 "Region 12 (not implemented)" hide.long 0x00 "PRBAR12,Protection Region Base Address Register 12" newline hgroup.long c15:(0x0186+0x60)++0x00 hide.long 0x00 "PRLAR12,Protection Region Limit Address Register 12" hgroup.long c15:(0x0486+0x60)++0x00 "Region 13 (not implemented)" hide.long 0x00 "PRBAR13,Protection Region Base Address Register 13" newline hgroup.long c15:(0x0586+0x60)++0x00 hide.long 0x00 "PRLAR13,Protection Region Limit Address Register 13" hgroup.long c15:(0x0086+0x70)++0x00 "Region 14 (not implemented)" hide.long 0x00 "PRBAR14,Protection Region Base Address Register 14" newline hgroup.long c15:(0x0186+0x70)++0x00 hide.long 0x00 "PRLAR14,Protection Region Limit Address Register 14" hgroup.long c15:(0x0486+0x70)++0x00 "Region 15 (not implemented)" hide.long 0x00 "PRBAR15,Protection Region Base Address Register 15" newline hgroup.long c15:(0x0586+0x70)++0x00 hide.long 0x00 "PRLAR15,Protection Region Limit Address Register 15" endif if (((per.l(c15:0x400))&0xFF00)>=0x1400) group.long c15:(0x1086+0x0)++0x00 "Region 16" line.long 0x00 "PRBAR16,Protection Region Base Address Register 16" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x1186+0x0)++0x00 line.long 0x00 "PRLAR16,Protection Region Limit Address Register 16" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x1486+0x0)++0x00 "Region 17" line.long 0x00 "PRBAR17,Protection Region Base Address Register 17" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x1586+0x0)++0x00 line.long 0x00 "PRLAR17,Protection Region Limit Address Register 17" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x1086+0x10)++0x00 "Region 18" line.long 0x00 "PRBAR18,Protection Region Base Address Register 18" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x1186+0x10)++0x00 line.long 0x00 "PRLAR18,Protection Region Limit Address Register 18" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x1486+0x10)++0x00 "Region 19" line.long 0x00 "PRBAR19,Protection Region Base Address Register 19" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x1586+0x10)++0x00 line.long 0x00 "PRLAR19,Protection Region Limit Address Register 19" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" else hgroup.long c15:(0x1086+0x0)++0x00 "Region 16 (not implemented)" hide.long 0x00 "PRBAR16,Protection Region Base Address Register 16" newline hgroup.long c15:(0x1186+0x0)++0x00 hide.long 0x00 "PRLAR16,Protection Region Limit Address Register 16" hgroup.long c15:(0x1486+0x0)++0x00 "Region 17 (not implemented)" hide.long 0x00 "PRBAR17,Protection Region Base Address Register 17" newline hgroup.long c15:(0x1586+0x0)++0x00 hide.long 0x00 "PRLAR17,Protection Region Limit Address Register 17" hgroup.long c15:(0x1086+0x10)++0x00 "Region 18 (not implemented)" hide.long 0x00 "PRBAR18,Protection Region Base Address Register 18" newline hgroup.long c15:(0x1186+0x10)++0x00 hide.long 0x00 "PRLAR18,Protection Region Limit Address Register 18" hgroup.long c15:(0x1486+0x10)++0x00 "Region 19 (not implemented)" hide.long 0x00 "PRBAR19,Protection Region Base Address Register 19" newline hgroup.long c15:(0x1586+0x10)++0x00 hide.long 0x00 "PRLAR19,Protection Region Limit Address Register 19" endif if (((per.l(c15:0x400))&0xFF00)>=0x1800) group.long c15:(0x1086+0x20)++0x00 "Region 20" line.long 0x00 "PRBAR20,Protection Region Base Address Register 20" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x1186+0x20)++0x00 line.long 0x00 "PRLAR20,Protection Region Limit Address Register 20" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x1486+0x20)++0x00 "Region 21" line.long 0x00 "PRBAR21,Protection Region Base Address Register 21" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x1586+0x20)++0x00 line.long 0x00 "PRLAR21,Protection Region Limit Address Register 21" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x1086+0x30)++0x00 "Region 22" line.long 0x00 "PRBAR22,Protection Region Base Address Register 22" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x1186+0x30)++0x00 line.long 0x00 "PRLAR22,Protection Region Limit Address Register 22" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x1486+0x30)++0x00 "Region 23" line.long 0x00 "PRBAR23,Protection Region Base Address Register 23" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x1586+0x30)++0x00 line.long 0x00 "PRLAR23,Protection Region Limit Address Register 23" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" else hgroup.long c15:(0x1086+0x20)++0x00 "Region 20 (not implemented)" hide.long 0x00 "PRBAR20,Protection Region Base Address Register 20" newline hgroup.long c15:(0x1186+0x20)++0x00 hide.long 0x00 "PRLAR20,Protection Region Limit Address Register 20" hgroup.long c15:(0x1486+0x20)++0x00 "Region 21 (not implemented)" hide.long 0x00 "PRBAR21,Protection Region Base Address Register 21" newline hgroup.long c15:(0x1586+0x20)++0x00 hide.long 0x00 "PRLAR21,Protection Region Limit Address Register 21" hgroup.long c15:(0x1086+0x30)++0x00 "Region 22 (not implemented)" hide.long 0x00 "PRBAR22,Protection Region Base Address Register 22" newline hgroup.long c15:(0x1186+0x30)++0x00 hide.long 0x00 "PRLAR22,Protection Region Limit Address Register 22" hgroup.long c15:(0x1486+0x30)++0x00 "Region 23 (not implemented)" hide.long 0x00 "PRBAR23,Protection Region Base Address Register 23" newline hgroup.long c15:(0x1586+0x30)++0x00 hide.long 0x00 "PRLAR23,Protection Region Limit Address Register 23" endif tree.end tree.end tree "Memory Protection Unit PL2" rgroup.long c15:0x4400++0x00 line.long 0x00 "HMPUIR,Hypervisor MPU Type Register" bitfld.long 0x00 0.--7. 1. "REGION,Identifies the number of implemented regions" "0,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16,Reserved,Reserved,Reserved,20,Reserved,Reserved,Reserved,24,?..." if (((per.l(c15:0x4400))&0xFF)>=0x18) group.long c15:0x4116++0x00 line.long 0x00 "HPRENR,Hypervisor MPU Region Enable Register" bitfld.long 0x00 23. "EN23,Region enable 23" "Disabled,Enabled" bitfld.long 0x00 22. "EN22,Region enable 22" "Disabled,Enabled" bitfld.long 0x00 21. "EN21,Region enable 21" "Disabled,Enabled" newline bitfld.long 0x00 20. "EN20,Region enable 20" "Disabled,Enabled" bitfld.long 0x00 19. "EN19,Region enable 19" "Disabled,Enabled" bitfld.long 0x00 18. "EN18,Region enable 18" "Disabled,Enabled" newline bitfld.long 0x00 17. "EN17,Region enable 17" "Disabled,Enabled" bitfld.long 0x00 16. "EN16,Region enable 16" "Disabled,Enabled" bitfld.long 0x00 15. "EN15,Region enable 15" "Disabled,Enabled" newline bitfld.long 0x00 14. "EN14,Region enable 14" "Disabled,Enabled" bitfld.long 0x00 13. "EN13,Region enable 13" "Disabled,Enabled" bitfld.long 0x00 12. "EN12,Region enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. "EN11,Region enable 11" "Disabled,Enabled" bitfld.long 0x00 10. "EN10,Region enable 10" "Disabled,Enabled" bitfld.long 0x00 9. "EN9,Region enable 9" "Disabled,Enabled" newline bitfld.long 0x00 8. "EN8,Region enable 8" "Disabled,Enabled" bitfld.long 0x00 7. "EN7,Region enable 7" "Disabled,Enabled" bitfld.long 0x00 6. "EN6,Region enable 6" "Disabled,Enabled" newline bitfld.long 0x00 5. "EN5,Region enable 5" "Disabled,Enabled" bitfld.long 0x00 4. "EN4,Region enable 4" "Disabled,Enabled" bitfld.long 0x00 3. "EN3,Region enable 3" "Disabled,Enabled" newline bitfld.long 0x00 2. "EN2,Region enable 2" "Disabled,Enabled" bitfld.long 0x00 1. "EN1,Region enable 1" "Disabled,Enabled" bitfld.long 0x00 0. "EN0,Region enable 0" "Disabled,Enabled" elif (((per.l(c15:0x4400))&0xFF)>=0x14) group.long c15:0x4116++0x00 line.long 0x00 "HPRENR,Hypervisor MPU Region Enable Register" bitfld.long 0x00 19. "EN19,Region enable 19" "Disabled,Enabled" bitfld.long 0x00 18. "EN18,Region enable 18" "Disabled,Enabled" bitfld.long 0x00 17. "EN17,Region enable 17" "Disabled,Enabled" newline bitfld.long 0x00 16. "EN16,Region enable 16" "Disabled,Enabled" bitfld.long 0x00 15. "EN15,Region enable 15" "Disabled,Enabled" bitfld.long 0x00 14. "EN14,Region enable 14" "Disabled,Enabled" newline bitfld.long 0x00 13. "EN13,Region enable 13" "Disabled,Enabled" bitfld.long 0x00 12. "EN12,Region enable 12" "Disabled,Enabled" bitfld.long 0x00 11. "EN11,Region enable 11" "Disabled,Enabled" newline bitfld.long 0x00 10. "EN10,Region enable 10" "Disabled,Enabled" bitfld.long 0x00 9. "EN9,Region enable 9" "Disabled,Enabled" bitfld.long 0x00 8. "EN8,Region enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. "EN7,Region enable 7" "Disabled,Enabled" bitfld.long 0x00 6. "EN6,Region enable 6" "Disabled,Enabled" bitfld.long 0x00 5. "EN5,Region enable 5" "Disabled,Enabled" newline bitfld.long 0x00 4. "EN4,Region enable 4" "Disabled,Enabled" bitfld.long 0x00 3. "EN3,Region enable 3" "Disabled,Enabled" bitfld.long 0x00 2. "EN2,Region enable 2" "Disabled,Enabled" newline bitfld.long 0x00 1. "EN1,Region enable 1" "Disabled,Enabled" bitfld.long 0x00 0. "EN0,Region enable 0" "Disabled,Enabled" elif (((per.l(c15:0x4400))&0xFF)>=0x10) group.long c15:0x4116++0x00 line.long 0x00 "HPRENR,Hypervisor MPU Region Enable Register" bitfld.long 0x00 15. "EN15,Region enable 15" "Disabled,Enabled" bitfld.long 0x00 14. "EN14,Region enable 14" "Disabled,Enabled" bitfld.long 0x00 13. "EN13,Region enable 13" "Disabled,Enabled" newline bitfld.long 0x00 12. "EN12,Region enable 12" "Disabled,Enabled" bitfld.long 0x00 11. "EN11,Region enable 11" "Disabled,Enabled" bitfld.long 0x00 10. "EN10,Region enable 10" "Disabled,Enabled" newline bitfld.long 0x00 9. "EN9,Region enable 9" "Disabled,Enabled" bitfld.long 0x00 8. "EN8,Region enable 8" "Disabled,Enabled" bitfld.long 0x00 7. "EN7,Region enable 7" "Disabled,Enabled" newline bitfld.long 0x00 6. "EN6,Region enable 6" "Disabled,Enabled" bitfld.long 0x00 5. "EN5,Region enable 5" "Disabled,Enabled" bitfld.long 0x00 4. "EN4,Region enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. "EN3,Region enable 3" "Disabled,Enabled" bitfld.long 0x00 2. "EN2,Region enable 2" "Disabled,Enabled" bitfld.long 0x00 1. "EN1,Region enable 1" "Disabled,Enabled" newline bitfld.long 0x00 0. "EN0,Region enable 0" "Disabled,Enabled" else rgroup.long c15:0x4116++0x00 line.long 0x00 "HPRENR,Hypervisor MPU Region Enable Register" endif if (((per.l(c15:0x4400))&0xFF)>=0x18) group.long c15:0x4126++0x00 line.long 0x00 "HPRSELR,Hypervisor Protection Region Selection Register" bitfld.long 0x00 0.--4. "REGION,The number of the current region visible in HPRBAR and HPRLAR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." elif (((per.l(c15:0x4400))&0xFF)>=0x14) group.long c15:0x4126++0x00 line.long 0x00 "HPRSELR,Hypervisor Protection Region Selection Register" bitfld.long 0x00 0.--4. "REGION,The number of the current region visible in HPRBAR and HPRLAR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..." elif (((per.l(c15:0x4400))&0xFF)>=0x10) group.long c15:0x4126++0x00 line.long 0x00 "HPRSELR,Hypervisor Protection Region Selection Register" bitfld.long 0x00 0.--3. "REGION,The number of the current region visible in HPRBAR and HPRLAR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else hgroup.long c15:0x4126++0x00 hide.long 0x00 "HPRSELR,Hypervisor Protection Region Selection Register" endif group.long c15:0x4036++0x00 line.long 0x00 "HPRBAR,Hypervisor Protection Region Base Address Register" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:0x4136++0x00 line.long 0x00 "HPRLAR,Hypervisor Protection Region Limit Address Register" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" tree "MPU regions" if (((per.l(c15:0x4400))&0xFF)>=0x10) group.long c15:(0x4086+0x0)++0x00 "Region 0" line.long 0x00 "HPRBAR0,Hypervisor Protection Region Base Address Register 0" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4186+0x0)++0x00 line.long 0x00 "HPRLAR0,Hypervisor Protection Region Limit Address Register 0" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4486+0x0)++0x00 "Region 1" line.long 0x00 "HPRBAR1,Hypervisor Protection Region Base Address Register 1" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4586+0x0)++0x00 line.long 0x00 "HPRLAR1,Hypervisor Protection Region Limit Address Register 1" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4086+0x10)++0x00 "Region 2" line.long 0x00 "HPRBAR2,Hypervisor Protection Region Base Address Register 2" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4186+0x10)++0x00 line.long 0x00 "HPRLAR2,Hypervisor Protection Region Limit Address Register 2" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4486+0x10)++0x00 "Region 3" line.long 0x00 "HPRBAR3,Hypervisor Protection Region Base Address Register 3" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4586+0x10)++0x00 line.long 0x00 "HPRLAR3,Hypervisor Protection Region Limit Address Register 3" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4086+0x20)++0x00 "Region 4" line.long 0x00 "HPRBAR4,Hypervisor Protection Region Base Address Register 4" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4186+0x20)++0x00 line.long 0x00 "HPRLAR4,Hypervisor Protection Region Limit Address Register 4" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4486+0x20)++0x00 "Region 5" line.long 0x00 "HPRBAR5,Hypervisor Protection Region Base Address Register 5" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4586+0x20)++0x00 line.long 0x00 "HPRLAR5,Hypervisor Protection Region Limit Address Register 5" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4086+0x30)++0x00 "Region 6" line.long 0x00 "HPRBAR6,Hypervisor Protection Region Base Address Register 6" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4186+0x30)++0x00 line.long 0x00 "HPRLAR6,Hypervisor Protection Region Limit Address Register 6" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4486+0x30)++0x00 "Region 7" line.long 0x00 "HPRBAR7,Hypervisor Protection Region Base Address Register 7" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4586+0x30)++0x00 line.long 0x00 "HPRLAR7,Hypervisor Protection Region Limit Address Register 7" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4086+0x40)++0x00 "Region 8" line.long 0x00 "HPRBAR8,Hypervisor Protection Region Base Address Register 8" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4186+0x40)++0x00 line.long 0x00 "HPRLAR8,Hypervisor Protection Region Limit Address Register 8" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4486+0x40)++0x00 "Region 9" line.long 0x00 "HPRBAR9,Hypervisor Protection Region Base Address Register 9" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4586+0x40)++0x00 line.long 0x00 "HPRLAR9,Hypervisor Protection Region Limit Address Register 9" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4086+0x50)++0x00 "Region 10" line.long 0x00 "HPRBAR10,Hypervisor Protection Region Base Address Register 10" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4186+0x50)++0x00 line.long 0x00 "HPRLAR10,Hypervisor Protection Region Limit Address Register 10" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4486+0x50)++0x00 "Region 11" line.long 0x00 "HPRBAR11,Hypervisor Protection Region Base Address Register 11" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4586+0x50)++0x00 line.long 0x00 "HPRLAR11,Hypervisor Protection Region Limit Address Register 11" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4086+0x60)++0x00 "Region 12" line.long 0x00 "HPRBAR12,Hypervisor Protection Region Base Address Register 12" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4186+0x60)++0x00 line.long 0x00 "HPRLAR12,Hypervisor Protection Region Limit Address Register 12" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4486+0x60)++0x00 "Region 13" line.long 0x00 "HPRBAR13,Hypervisor Protection Region Base Address Register 13" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4586+0x60)++0x00 line.long 0x00 "HPRLAR13,Hypervisor Protection Region Limit Address Register 13" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4086+0x70)++0x00 "Region 14" line.long 0x00 "HPRBAR14,Hypervisor Protection Region Base Address Register 14" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4186+0x70)++0x00 line.long 0x00 "HPRLAR14,Hypervisor Protection Region Limit Address Register 14" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4486+0x70)++0x00 "Region 15" line.long 0x00 "HPRBAR15,Hypervisor Protection Region Base Address Register 15" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4586+0x70)++0x00 line.long 0x00 "HPRLAR15,Hypervisor Protection Region Limit Address Register 15" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" else hgroup.long c15:(0x4086+0x0)++0x00 "Region 0 (not implemented)" hide.long 0x00 "HPRBAR0,Hypervisor Protection Region Base Address Register 0" newline hgroup.long c15:(0x4186+0x0)++0x00 hide.long 0x00 "HPRLAR0,Hypervisor Protection Region Limit Address Register 0" hgroup.long c15:(0x4486+0x0)++0x00 "Region 1 (not implemented)" hide.long 0x00 "HPRBAR1,Hypervisor Protection Region Base Address Register 1" newline hgroup.long c15:(0x4586+0x0)++0x00 hide.long 0x00 "HPRLAR1,Hypervisor Protection Region Limit Address Register 1" hgroup.long c15:(0x4086+0x10)++0x00 "Region 2 (not implemented)" hide.long 0x00 "HPRBAR2,Hypervisor Protection Region Base Address Register 2" newline hgroup.long c15:(0x4186+0x10)++0x00 hide.long 0x00 "HPRLAR2,Hypervisor Protection Region Limit Address Register 2" hgroup.long c15:(0x4486+0x10)++0x00 "Region 3 (not implemented)" hide.long 0x00 "HPRBAR3,Hypervisor Protection Region Base Address Register 3" newline hgroup.long c15:(0x4586+0x10)++0x00 hide.long 0x00 "HPRLAR3,Hypervisor Protection Region Limit Address Register 3" hgroup.long c15:(0x4086+0x20)++0x00 "Region 4 (not implemented)" hide.long 0x00 "HPRBAR4,Hypervisor Protection Region Base Address Register 4" newline hgroup.long c15:(0x4186+0x20)++0x00 hide.long 0x00 "HPRLAR4,Hypervisor Protection Region Limit Address Register 4" hgroup.long c15:(0x4486+0x20)++0x00 "Region 5 (not implemented)" hide.long 0x00 "HPRBAR5,Hypervisor Protection Region Base Address Register 5" newline hgroup.long c15:(0x4586+0x20)++0x00 hide.long 0x00 "HPRLAR5,Hypervisor Protection Region Limit Address Register 5" hgroup.long c15:(0x4086+0x30)++0x00 "Region 6 (not implemented)" hide.long 0x00 "HPRBAR6,Hypervisor Protection Region Base Address Register 6" newline hgroup.long c15:(0x4186+0x30)++0x00 hide.long 0x00 "HPRLAR6,Hypervisor Protection Region Limit Address Register 6" hgroup.long c15:(0x4486+0x30)++0x00 "Region 7 (not implemented)" hide.long 0x00 "HPRBAR7,Hypervisor Protection Region Base Address Register 7" newline hgroup.long c15:(0x4586+0x30)++0x00 hide.long 0x00 "HPRLAR7,Hypervisor Protection Region Limit Address Register 7" hgroup.long c15:(0x4086+0x40)++0x00 "Region 8 (not implemented)" hide.long 0x00 "HPRBAR8,Hypervisor Protection Region Base Address Register 8" newline hgroup.long c15:(0x4186+0x40)++0x00 hide.long 0x00 "HPRLAR8,Hypervisor Protection Region Limit Address Register 8" hgroup.long c15:(0x4486+0x40)++0x00 "Region 9 (not implemented)" hide.long 0x00 "HPRBAR9,Hypervisor Protection Region Base Address Register 9" newline hgroup.long c15:(0x4586+0x40)++0x00 hide.long 0x00 "HPRLAR9,Hypervisor Protection Region Limit Address Register 9" hgroup.long c15:(0x4086+0x50)++0x00 "Region 10 (not implemented)" hide.long 0x00 "HPRBAR10,Hypervisor Protection Region Base Address Register 10" newline hgroup.long c15:(0x4186+0x50)++0x00 hide.long 0x00 "HPRLAR10,Hypervisor Protection Region Limit Address Register 10" hgroup.long c15:(0x4486+0x50)++0x00 "Region 11 (not implemented)" hide.long 0x00 "HPRBAR11,Hypervisor Protection Region Base Address Register 11" newline hgroup.long c15:(0x4586+0x50)++0x00 hide.long 0x00 "HPRLAR11,Hypervisor Protection Region Limit Address Register 11" hgroup.long c15:(0x4086+0x60)++0x00 "Region 12 (not implemented)" hide.long 0x00 "HPRBAR12,Hypervisor Protection Region Base Address Register 12" newline hgroup.long c15:(0x4186+0x60)++0x00 hide.long 0x00 "HPRLAR12,Hypervisor Protection Region Limit Address Register 12" hgroup.long c15:(0x4486+0x60)++0x00 "Region 13 (not implemented)" hide.long 0x00 "HPRBAR13,Hypervisor Protection Region Base Address Register 13" newline hgroup.long c15:(0x4586+0x60)++0x00 hide.long 0x00 "HPRLAR13,Hypervisor Protection Region Limit Address Register 13" hgroup.long c15:(0x4086+0x70)++0x00 "Region 14 (not implemented)" hide.long 0x00 "HPRBAR14,Hypervisor Protection Region Base Address Register 14" newline hgroup.long c15:(0x4186+0x70)++0x00 hide.long 0x00 "HPRLAR14,Hypervisor Protection Region Limit Address Register 14" hgroup.long c15:(0x4486+0x70)++0x00 "Region 15 (not implemented)" hide.long 0x00 "HPRBAR15,Hypervisor Protection Region Base Address Register 15" newline hgroup.long c15:(0x4586+0x70)++0x00 hide.long 0x00 "HPRLAR15,Hypervisor Protection Region Limit Address Register 15" endif if (((per.l(c15:0x4400))&0xFF)>=0x14) group.long c15:(0x5086+0x0)++0x00 "Region 16" line.long 0x00 "HPRBAR16,Hypervisor Protection Region Base Address Register 16" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x5186+0x0)++0x00 line.long 0x00 "HPRLAR16,Hypervisor Protection Region Limit Address Register 16" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x5486+0x0)++0x00 "Region 17" line.long 0x00 "HPRBAR17,Hypervisor Protection Region Base Address Register 17" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x5586+0x0)++0x00 line.long 0x00 "HPRLAR17,Hypervisor Protection Region Limit Address Register 17" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x5086+0x10)++0x00 "Region 18" line.long 0x00 "HPRBAR18,Hypervisor Protection Region Base Address Register 18" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x5186+0x10)++0x00 line.long 0x00 "HPRLAR18,Hypervisor Protection Region Limit Address Register 18" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x5486+0x10)++0x00 "Region 19" line.long 0x00 "HPRBAR19,Hypervisor Protection Region Base Address Register 19" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x5586+0x10)++0x00 line.long 0x00 "HPRLAR19,Hypervisor Protection Region Limit Address Register 19" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" else hgroup.long c15:(0x5086+0x0)++0x00 "Region 16 (not implemented)" hide.long 0x00 "HPRBAR16,Hypervisor Protection Region Base Address Register 16" newline hgroup.long c15:(0x5186+0x0)++0x00 hide.long 0x00 "HPRLAR16,Hypervisor Protection Region Limit Address Register 16" hgroup.long c15:(0x5486+0x0)++0x00 "Region 17 (not implemented)" hide.long 0x00 "HPRBAR17,Hypervisor Protection Region Base Address Register 17" newline hgroup.long c15:(0x5586+0x0)++0x00 hide.long 0x00 "HPRLAR17,Hypervisor Protection Region Limit Address Register 17" hgroup.long c15:(0x5086+0x10)++0x00 "Region 18 (not implemented)" hide.long 0x00 "HPRBAR18,Hypervisor Protection Region Base Address Register 18" newline hgroup.long c15:(0x5186+0x10)++0x00 hide.long 0x00 "HPRLAR18,Hypervisor Protection Region Limit Address Register 18" hgroup.long c15:(0x5486+0x10)++0x00 "Region 19 (not implemented)" hide.long 0x00 "HPRBAR19,Hypervisor Protection Region Base Address Register 19" newline hgroup.long c15:(0x5586+0x10)++0x00 hide.long 0x00 "HPRLAR19,Hypervisor Protection Region Limit Address Register 19" endif if (((per.l(c15:0x4400))&0xFF)>=0x18) group.long c15:(0x5086+0x20)++0x00 "Region 20" line.long 0x00 "HPRBAR20,Hypervisor Protection Region Base Address Register 20" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x5186+0x20)++0x00 line.long 0x00 "HPRLAR20,Hypervisor Protection Region Limit Address Register 20" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x5486+0x20)++0x00 "Region 21" line.long 0x00 "HPRBAR21,Hypervisor Protection Region Base Address Register 21" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x5586+0x20)++0x00 line.long 0x00 "HPRLAR21,Hypervisor Protection Region Limit Address Register 21" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x5086+0x30)++0x00 "Region 22" line.long 0x00 "HPRBAR22,Hypervisor Protection Region Base Address Register 22" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x5186+0x30)++0x00 line.long 0x00 "HPRLAR22,Hypervisor Protection Region Limit Address Register 22" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x5486+0x30)++0x00 "Region 23" line.long 0x00 "HPRBAR23,Hypervisor Protection Region Base Address Register 23" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x5586+0x30)++0x00 line.long 0x00 "HPRLAR23,Hypervisor Protection Region Limit Address Register 23" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" else hgroup.long c15:(0x5086+0x20)++0x00 "Region 20 (not implemented)" hide.long 0x00 "HPRBAR20,Hypervisor Protection Region Base Address Register 20" newline hgroup.long c15:(0x5186+0x20)++0x00 hide.long 0x00 "HPRLAR20,Hypervisor Protection Region Limit Address Register 20" hgroup.long c15:(0x5486+0x20)++0x00 "Region 21 (not implemented)" hide.long 0x00 "HPRBAR21,Hypervisor Protection Region Base Address Register 21" newline hgroup.long c15:(0x5586+0x20)++0x00 hide.long 0x00 "HPRLAR21,Hypervisor Protection Region Limit Address Register 21" hgroup.long c15:(0x5086+0x30)++0x00 "Region 22 (not implemented)" hide.long 0x00 "HPRBAR22,Hypervisor Protection Region Base Address Register 22" newline hgroup.long c15:(0x5186+0x30)++0x00 hide.long 0x00 "HPRLAR22,Hypervisor Protection Region Limit Address Register 22" hgroup.long c15:(0x5486+0x30)++0x00 "Region 23 (not implemented)" hide.long 0x00 "HPRBAR23,Hypervisor Protection Region Base Address Register 23" newline hgroup.long c15:(0x5586+0x30)++0x00 hide.long 0x00 "HPRLAR23,Hypervisor Protection Region Limit Address Register 23" endif tree.end tree.end tree "Virtualization Extensions" group.long c15:0x4000++0x00 line.long 0x00 "VPIDR,Virtualization Processor ID Register" hexmask.long.byte 0x00 24.--31. 1. "IMPL,Implementer code" bitfld.long 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "ARCH,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme" hexmask.long.word 0x00 4.--15. 1. "PART,Primary part number" newline bitfld.long 0x00 0.--3. "REV,Minor revision of the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long c15:0x4500++0x00 line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Register" bitfld.long 0x00 30. "U,Single core system as distinct from core 0 in a cluster" "Part of a cluster,?..." bitfld.long 0x00 24. "MT,Multi-threading type approach for logical cores in lowest level of affinity" "Largely independent,?..." newline hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2" hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1" hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register" group.long c15:0x4001++0x00 line.long 0x00 "HSCTLR,Hypervisor System Control Register" bitfld.long 0x00 30. "TE,Thumb exception enable" "A32,T32" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.long 0x00 21. "FI,Fast interrupts configuration enable" "Disabled,Enabled" newline bitfld.long 0x00 19. "WXN,Write permission implies Execute Never (XN)" "Not forced,Forced" bitfld.long 0x00 17. "BR,Background region enable" "Disabled,Enabled" bitfld.long 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND instruction disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT instruction disable" "No,Yes" bitfld.long 0x00 5. "CP15BEN,CP15* barrier operations enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "C,Data cache enable" "Disabled,Enabled" bitfld.long 0x00 1. "A,Alignment fault checking enable" "Disabled,Enabled" bitfld.long 0x00 0. "M,EL2-controlled MPU enable" "Disabled,Enabled" group.long c15:0x4002++0x00 line.long 0x00 "VSCTLR,Virtualization System Control Register" hexmask.long.byte 0x00 16.--23. 1. "VMID,Virtual machine ID" bitfld.long 0x00 2. "S2NIE,Stage-2 normal interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. "S2DMAD,Stage-2 device multiple access disable" "Disabled,Enabled" group.long c15:0x4101++0x00 line.long 0x00 "HACTLR,Hypervisor Auxiliary Control Register" bitfld.long 0x00 15. "TESTR1,Controls access to TESTR1 at EL0 and EL1" "Trapped,Enabled" bitfld.long 0x00 13. "ERR,Controls access to IMP_DCERR0, IMP_DCERR1, IMP_ICERR0, IMP_ICERR1, IMP_TCMERR0, IMP_TCMERR1, IMP_FLASHERR0 and IMP_FLASHERR1 registers" "Trapped,Enabled" bitfld.long 0x00 12. "INTMONR,Controls access to IMP_INTMONR at EL1" "Trapped,Enabled" newline bitfld.long 0x00 10. "BUSTIMEOUTR,Controls access to IMP_BUSTIMEOUTR at EL1" "Trapped,Enabled" bitfld.long 0x00 9. "QOSR,Controls access to QOSR at EL1" "Trapped,Enabled" bitfld.long 0x00 8. "PERIPHPREGIONR,Controls access to IMP_PERIPHPREGIONR at EL1" "Trapped,Enabled" newline bitfld.long 0x00 7. "FLASHIFREGIONR,Controls access to IMP_FLASHIFREGIONR at EL1" "Trapped,Enabled" bitfld.long 0x00 1. "CDBGDCI,Controls access to CDBGDCI at EL1" "Trapped,Enabled" bitfld.long 0x00 0. "CPUACTLR,IMP_CPUACTLR write access control" "Trapped,Enabled" rgroup.long c15:0x4711++0x00 line.long 0x00 "HACR,Hypervisor Auxiliary Configuration Register" group.long c15:0x4011++0x00 line.long 0x00 "HCR,Hypervisor Configuration Register" bitfld.long 0x00 30. "TRVM,Trap read of virtual memory controls" "Disabled,Enabled" bitfld.long 0x00 29. "HCD,HVC instruction disable" "No,Yes" bitfld.long 0x00 27. "TGE,Trap general exceptions" "Disabled,Enabled" newline bitfld.long 0x00 26. "TVM,Trap virtual memory controls" "Disabled,Enabled" bitfld.long 0x00 24. "TPU,Trap cache maintenance instructions that operate to the point of unification" "Disabled,Enabled" bitfld.long 0x00 23. "TPC,Trap Data Cache maintenance operations that operate to the point of coherency" "Disabled,Enabled" newline bitfld.long 0x00 22. "TSW,Trap data/unified cache maintenance instructions by set/way" "Disabled,Enabled" bitfld.long 0x00 21. "TAC,Trap ACTLR accesses" "Disabled,Enabled" bitfld.long 0x00 20. "TIDCP,Trap lockdown" "Disabled,Enabled" newline bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" newline bitfld.long 0x00 12. "DC,Default cacheable" "Disabled,Enabled" bitfld.long 0x00 10.--11. "BSU,Barrier shareability upgrade" "No effect,Inner shareable,Outer shareable,Full system" bitfld.long 0x00 9. "FB,Force broadcast" "Not forced,Forced" newline bitfld.long 0x00 8. "VA,Virtual asynchronous abort exception" "Not pending,Pending" bitfld.long 0x00 7. "VI,Virtual IRQ exception" "Not pending,Pending" bitfld.long 0x00 6. "VF,Virtual FIQ exception" "Not pending,Pending" newline bitfld.long 0x00 5. "AMO,A-bit mask override" "Disabled,Enabled" bitfld.long 0x00 4. "IMO,I-bit mask override" "Disabled,Enabled" bitfld.long 0x00 3. "FMO,F-bit mask override" "Disabled,Enabled" newline bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override" bitfld.long 0x00 0. "VM,Second stage of translation enable" "Disabled,Enabled" rgroup.long c15:0x4411++0x00 line.long 0x00 "HCR2,Hypervisor Configuration Register 2" group.long c15:0x3054++0x00 line.long 0x00 "DSPSR,Debug Saved Program Status Register" bitfld.long 0x00 31. "N,Negative condition flag" "Not negative,Negative" bitfld.long 0x00 30. "Z,Zero condition flag" "Not zero,Zero" bitfld.long 0x00 29. "C,Carry condition flag" "Not carry,Carry" newline bitfld.long 0x00 28. "V,Overflow condition flag" "No overflow,Overflow" bitfld.long 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred" bitfld.long 0x00 21. "SS,Software step" "0,1" newline bitfld.long 0x00 20. "IL,Illegal execution state" "0,1" bitfld.long 0x00 14.--15. 25.--26. "IT[4:7],IT block state bits for the T32 IT (if-then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--13. "IT[0:3],IT block state bits for the T32 IT (if-then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "GE,Greater than or equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 9. "E,Endianness state bit" "Little,Big" bitfld.long 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked" newline bitfld.long 0x00 7. "I,IRQ mask bit" "Not masked,Masked" bitfld.long 0x00 6. "F,FIQ mask bit" "Not masked,Masked" bitfld.long 0x00 5. "T,T32 Instruction set state" "A32,T32" newline bitfld.long 0x00 4. "M[4],Execution state that the exception was taken from" "Reserved,AArch32" bitfld.long 0x00 0.--3. "M[3:0],Current PE mode" "User,FIQ,IRQ,Supervisor,Reserved,Reserved,Monitor,Abort,Reserved,Reserved,Hyp,Undefined,Reserved,Reserved,Reserved,System" group.long c15:0x4111++0x00 line.long 0x00 "HDCR,Hypervisor Debug Control Register" bitfld.long 0x00 21. "EPMAD,External debugger access to hypervisor performance monitors registers disabled" "No,Yes" bitfld.long 0x00 17. "HPMD,Hypervisor performance monitors disable" "No,Yes" bitfld.long 0x00 11. "TDRA,Trap debug ROM access" "No effect,Valid" newline bitfld.long 0x00 10. "TDOSA,Trap debug OS-related register access" "No effect,Valid" bitfld.long 0x00 9. "TDA,Trap debug access" "No effect,Valid" bitfld.long 0x00 8. "TDE,Trap debug exceptions" "No effect,Valid" newline bitfld.long 0x00 7. "HPME,Hypervisor performance monitors enable" "Disabled,Enabled" bitfld.long 0x00 6. "TPM,Trap performance monitors accesses" "No effect,Valid" bitfld.long 0x00 5. "TPMCR,Trap performance monitor control register accesses" "No effect,Valid" newline bitfld.long 0x00 0.--4. "HPMN,Defines the number of performance monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x4211++0x00 line.long 0x00 "HCPTR,Hypervisor Architectural Feature Trap Register" bitfld.long 0x00 31. "TCPAC,Trap coprocessor access control" "Not trapped,Trapped" bitfld.long 0x00 15. "TASE,Trap advanced SIMD extensions" "Not trapped,Trapped" newline bitfld.long 0x00 11. "TCP11,Trap coprocessor 11" "Not trapped,Trapped" bitfld.long 0x00 10. "TCP10,Trap coprocessor 10" "Not trapped,Trapped" group.long c15:0x4311++0x00 line.long 0x00 "HSTR,Hypervisor System Trap Register" bitfld.long 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "No effect,Trap" bitfld.long 0x00 13. "T13,Trap to Hypervisor mode Non-secure priv 13" "No effect,Trap" bitfld.long 0x00 12. "T12,Trap to Hypervisor mode Non-secure priv 12" "No effect,Trap" newline bitfld.long 0x00 11. "T11,Trap to Hypervisor mode Non-secure priv 11" "No effect,Trap" bitfld.long 0x00 10. "T10,Trap to Hypervisor mode Non-secure priv 10" "No effect,Trap" bitfld.long 0x00 9. "T9,Trap to Hypervisor mode Non-secure priv 9" "No effect,Trap" newline bitfld.long 0x00 8. "T8,Trap to Hypervisor mode Non-secure priv 8" "No effect,Trap" bitfld.long 0x00 7. "T7,Trap to Hypervisor mode Non-secure priv 7" "No effect,Trap" bitfld.long 0x00 6. "T6,Trap to Hypervisor mode Non-secure priv 6" "No effect,Trap" newline bitfld.long 0x00 5. "T5,Trap to Hypervisor mode Non-secure priv 5" "No effect,Trap" bitfld.long 0x00 3. "T3,Trap to Hypervisor mode Non-secure priv 3" "No effect,Trap" bitfld.long 0x00 2. "T2,Trap to Hypervisor mode Non-secure priv 2" "No effect,Trap" newline bitfld.long 0x00 1. "T1,Trap to Hypervisor mode Non-secure priv 1" "No effect,Trap" bitfld.long 0x00 0. "T0,Trap to Hypervisor mode Non-secure priv 0" "No effect,Trap" rgroup.long c15:0x4301++0x00 line.long 0x00 "HACTLR2,Hypervisor Auxiliary Control Register 2" group.long c15:0x3154++0x00 line.long 0x00 "DLR,Debug Link Register" group.long c15:0x4015++0x00 line.long 0x00 "HADFSR,Hypervisor Auxiliary Data Fault Status Syndrome Register" bitfld.long 0x00 2.--4. "PORT,Memory or port that caused the fault" "AXIM,Flash interface,LLPP,Internal interface,ATCM,BTCM,CTCM,?..." bitfld.long 0x00 0.--1. "TYPE,Fault type" "Undefined,Response,ECC on data,Bus timeout" group.long c15:0x4006++0x00 line.long 0x00 "HDFAR,Hypervisor Data Fault Address Register" if (((per.l(c15:0x4025))&0xFC000000)==(0x00000000||0x38000000||0x88000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." elif (((per.l(c15:0x4025))&0xFC000000)==0x04000000) if (((per.l(c15:0x4025))&0x01000000)==0x01000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" endif elif (((per.l(c15:0x4025))&0xFC000000)==(0x0C000000||0x14000000||0x20000000)) if (((per.l(c15:0x4025))&0x01000000)==0x01000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--8. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.long 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--8. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.l(c15:0x4025))&0xFC000000)==(0x10000000||0x30000000)) if (((per.l(c15:0x4025))&0x01000000)==0x01000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--13. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--8. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.long 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--13. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--8. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.l(c15:0x4025))&0xFC000000)==0x18000000) if (((per.l(c15:0x4025))&0x01000000)==0x01000000) if (((per.l(c15:0x4025))&0x08)==0x00) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--8. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..." newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..." newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif else if (((per.l(c15:0x4025))&0x08)==0x00) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--8. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif endif elif (((per.l(c15:0x4025))&0xFC000000)==0x1C000000) if (((per.l(c15:0x4025))&0x01000000)==0x01000000) if (((per.l(c15:0x4025))&0x20)==0x20) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 5. "TA,Indicates trapped use of advanced SIMD functionality" "Not trapped,Trapped" bitfld.long 0x00 0.--3. "COPROC,COPROC" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,0b1010,?..." else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 5. "TA,Indicates trapped use of advanced SIMD functionality" "Not trapped,Trapped" endif else if (((per.l(c15:0x4025))&0x20)==0x20) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.long 0x00 5. "TA,Indicates trapped use of advanced SIMD functionality" "Not trapped,Trapped" bitfld.long 0x00 0.--3. "COPROC,COPROC" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,0b1010,?..." else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.long 0x00 5. "TA,Indicates trapped use of advanced SIMD functionality" "Not trapped,Trapped" endif endif elif (((per.l(c15:0x4025))&0xFC000000)==(0x44000000||0x48000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.l(c15:0x4025))&0xFC000000)==(0x80000000||0x84000000)) if (((per.l(c15:0x4025))&0x3F)==0x10) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not valid" "No,Yes" newline bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 0.--5. "IFSC,Instruction fault status code" "Reserved,Reserved,Reserved,Reserved,Translation fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault,Reserved,Reserved,Reserved,Synch. external abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synch. parity/ECC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug,?..." else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline newline bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 0.--5. "IFSC,Instruction fault status code" "Reserved,Reserved,Reserved,Reserved,Translation fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault,Reserved,Reserved,Reserved,Synch. external abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synch. parity/ECC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug,?..." endif elif (((per.l(c15:0x4025))&0xFD00003F)==(0x95000010||0x91000010)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline bitfld.long 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword" bitfld.long 0x00 21. "SSE,Syndrome sign extend" "Not required,Required" bitfld.long 0x00 16.--19. "SRT,Syndrome register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not valid" "No,Yes" newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not read" "Read,Write" newline bitfld.long 0x00 0.--5. "DFSC,Data fault status code" "Reserved,Reserved,Reserved,Reserved,Translation fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault,Reserved,Reserved,Reserved,Synch. external abort,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synch. parity/ECC,SError/parity/ECC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Cache lockdown fault,Unsupported Exclusive access,?..." elif (((per.l(c15:0x4025))&0xFD000000)==(0x95000000||0x91000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline bitfld.long 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword" bitfld.long 0x00 21. "SSE,Syndrome sign extend" "Not required,Required" bitfld.long 0x00 16.--19. "SRT,Syndrome register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not read" "Read,Write" newline bitfld.long 0x00 0.--5. "DFSC,Data fault status code" "Reserved,Reserved,Reserved,Reserved,Translation fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault,Reserved,Reserved,Reserved,Synch. external abort,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synch. parity/ECC,SError/parity/ECC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Cache lockdown fault,Unsupported Exclusive access,?..." elif (((per.l(c15:0x4025))&0xFD00003F)==(0x90000010||0x94000010)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline newline newline bitfld.long 0x00 10. "FNV,FAR not valid" "No,Yes" newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not read" "Read,Write" newline bitfld.long 0x00 0.--5. "DFSC,Data fault status code" "Reserved,Reserved,Reserved,Reserved,Translation fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault,Reserved,Reserved,Reserved,Synch. external abort,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synch. parity/ECC,SError/parity/ECC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Cache lockdown fault,Unsupported Exclusive access,?..." elif (((per.l(c15:0x4025))&0xFD000000)==(0x90000000||0x94000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline newline newline newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not read" "Read,Write" newline bitfld.long 0x00 0.--5. "DFSC,Data fault status code" "Reserved,Reserved,Reserved,Reserved,Translation fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault,Reserved,Reserved,Reserved,Synch. external abort,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synch. parity/ECC,SError/parity/ECC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Cache lockdown fault,Unsupported Exclusive access,?..." else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" endif group.long c15:0x4115++0x00 line.long 0x00 "HAIFSR,Hypervisor Auxiliary Instruction Fault Status Register" bitfld.long 0x00 2.--4. "PORT,Memory or port that caused the fault" "AXIM,Flash interface,LLPP,Reserved,ATCM,BTCM,CTCM,UNKNOWN" bitfld.long 0x00 0.--1. "TYPE,Fault type" "Undefined,Response,ECC on data,Bus timeout" group.long c15:0x4206++0x00 line.long 0x00 "HIFAR,Hypervisor Instruction Fault Address Register" group.long c15:0x4406++0x00 line.long 0x00 "HPFAR,Hypervisor IPA Fault Address Register" hexmask.long 0x00 4.--31. 1. "FIPA,Faulting IPA bits" tree.open "Hypervisor Memory Attribute Indirection Registers" group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" rgroup.long c15:0x403A++0x00 line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0" rgroup.long c15:0x413A++0x00 line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1" tree.end newline group.long c15:0x400C++0x00 line.long 0x00 "HVBAR,Hypervisor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector base address" group.long c15:0x420C++0x00 line.long 0x00 "HRMR,Hypervisor Reset Management Register" bitfld.long 0x00 1. "RR,Reset request" "Not requested,Requested" group.long c15:0x1119++0x00 line.long 0x00 "IMP_BPCTLR,Branch Predictor Control Register" bitfld.long 0x00 2. "DBPEL2DIS,Disable dynamic branch predictor when running at EL2" "No,Yes" bitfld.long 0x00 1. "DBPEL1DIS,Disable dynamic branch predictor when running at EL1" "No,Yes" bitfld.long 0x00 0. "DBPEL0DIS,Disable dynamic branch predictor when running at EL0" "No,Yes" tree.end tree "Cache Control and Configuration" rgroup.long c15:0x0100++0x00 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 24.--27. "CWG,Cache write-back granule" "Reserved,2 words,?..." bitfld.long 0x00 20.--23. "ERG,Exclusives reservation granule" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x00 16.--19. "DMINLINE,D-cache minimum line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x00 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.long 0x00 0.--3. "IMINLINE,I-cache minimum line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." group.long c15:0x2000++0x00 line.long 0x00 "CSSELR,Cache Size Selection Register" rbitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,?..." bitfld.long 0x00 0. "IND,Instruction/not data" "Data/unified,Instruction" rgroup.long c15:0x1000++0x00 line.long 0x00 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. "WT,Write-through" "Not supported,Supported" bitfld.long 0x00 30. "WB,Write-back" "Not supported,?..." newline bitfld.long 0x00 29. "RA,Read-allocate" "Reserved,Supported" bitfld.long 0x00 28. "WA,Write-allocate" "Not supported,Supported" newline hexmask.long.word 0x00 13.--27. 1. 1. "SETS,Number of sets" hexmask.long.word 0x00 3.--12. 1. 1. "ASSOC,Associativity" newline bitfld.long 0x00 0.--2. "LSIZE,Number of words in each cache line" "Reserved,Reserved,16,?..." rgroup.long c15:0x1100++0x00 line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..." bitfld.long 0x00 27.--29. "LOUU,Level of unification" "Level 0,Level 1,?..." bitfld.long 0x00 24.--26. "LOC,Level of coherency" "Level 0,Level 1,?..." newline bitfld.long 0x00 21.--23. "LOUIS,Level of unification inner shareable" "Level 0,Level 1,?..." bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..." newline bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..." bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..." newline bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." newline bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,?..." bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "No cache,Instruction cache,Data cache,Both separated,?..." group.long c15:0x1019++0x00 line.long 0x00 "IMP_CSCTLR,Cache Segregation Control Register" bitfld.long 0x00 8.--10. "IFLW,Instruction cache flash ways" "Reserved,0,0-1,0-2,0-3,?..." bitfld.long 0x00 0.--2. "DFLW,Data cache flash ways" "Reserved,0,0-1,0-2,0-3,?..." group.quad c15:0x100F0++0x01 line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register" bitfld.quad 0x00 47. "FIXEDDIV,Enable fixed latency for integer divide instructions" "Disabled,Enabled" bitfld.quad 0x00 46. "ETACDIS,Disable PFU exception target address cache" "No,Yes" bitfld.quad 0x00 45. "OOODIVDIS,Disable out-of-order completion of divide instructions" "No,Yes" newline bitfld.quad 0x00 41. "TLACDIS,Disable the store unit (STU) tag lookup avoidance cache" "No,Yes" bitfld.quad 0x00 40. "FLASHNDDIS,Disable flash accesses use of non-flash-dedicated resources" "No,Yes" bitfld.quad 0x00 39. "FLASHARBCTL,Flash interface arbitration control" "D-side,I-side" newline bitfld.quad 0x00 38. "AXIMARBCTL,AXIM interface arbitration control" "D-side,I-side" bitfld.quad 0x00 33. "ISPECDIS,Disable I-side speculative access" "No,Yes" bitfld.quad 0x00 32. "DSPECDIS,Disable D-side speculative access" "No,Yes" newline bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes" bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes" bitfld.quad 0x00 25.--26. "WSTRNOL1ACTL,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled streaming" newline bitfld.quad 0x00 19.--20. "DPFSTRCTL,Number of independent data prefetch streams" "1,2,3,4" bitfld.quad 0x00 17. "STRIDECTL,Enable stride detection" "2,3" bitfld.quad 0x00 13.--15. "L1DPFCTL,L1 Data prefetch control" "Disabled,1 outstanding prefetch,2 outstanding prefetch,3 outstanding prefetch,4 outstanding prefetch,5 outstanding prefetch,6 outstanding prefetch,8 outstanding prefetch" newline bitfld.quad 0x00 11. "L1IPFCTL,L1 Instruction prefetch control" "Disabled,Enabled" bitfld.quad 0x00 10. "DMB2DSBEN,Enable data memory barrier behaving as data synchronization barrier" "Disabled,Enabled" wgroup.long c15:0x10EF++0x00 line.long 0x00 "IMP_CDBGDCI,Invalidate All Register" tree "Level 1 memory system" rgroup.long c15:0x300F++0x00 line.long 0x00 "IMP_CDBGDR0,Cache Debug Data Register 0" bitfld.long 0x00 22. "V,Valid" "0,1" hexmask.long.tbyte 0x00 0.--21. 1. "TB,Tag bits" rgroup.long c15:0x310F++0x00 line.long 0x00 "IMP_CDBGDR1,Cache Debug Data Register 1" wgroup.long c15:0x302F++0x00 line.long 0x00 "IMP_CDBGDCT,Data Cache Tag Read Operation Register" bitfld.long 0x00 30.--31. "CW,Cache way" "0,1,2,3" hexmask.long.word 0x00 6.--12. 1. "SETIND,Set index" wgroup.long c15:0x312F++0x00 line.long 0x00 "IMP_CDBGICT,Instruction Cache Tag Read Operation Register" bitfld.long 0x00 30.--31. "CW,Cache way" "0,1,2,3" hexmask.long.word 0x00 6.--12. 1. "SETIND,Set index" wgroup.long c15:0x304F++0x00 line.long 0x00 "IMP_CDBGDCD,Data Cache Data Read Operation Register" bitfld.long 0x00 30.--31. "CW,Cache way" "0,1,2,3" hexmask.long.word 0x00 6.--12. 1. "SETIND,Set index" bitfld.long 0x00 3.--5. "DO,Data offset" "0,1,2,3,4,5,6,7" wgroup.long c15:0x314F++0x00 line.long 0x00 "IMP_CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. "CW,Cache way" "0,1,2,3" hexmask.long.word 0x00 6.--12. 1. "SETIND,Set index" bitfld.long 0x00 3.--5. "DO,Data offset" "0,1,2,3,4,5,6,7" tree.end tree.end tree "System Performance Monitor" group.long c15:0x00C9++0x00 line.long 0x00 "PMCR,Performance Monitors Control Register" hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code" rbitfld.long 0x00 11.--15. "N,Number of counters implemented" "Reserved,Reserved,Reserved,Reserved,4,?..." bitfld.long 0x00 6. "LC,Long cycle counter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes" bitfld.long 0x00 4. "X,Export enable" "Disabled,Enabled" bitfld.long 0x00 3. "D,Clock divider" "Every cycle,64th cycle" bitfld.long 0x00 2. "C,Clock counter reset" "No reset,Reset" newline bitfld.long 0x00 1. "P,Performance counter reset" "No reset,Reset" bitfld.long 0x00 0. "E,All counters enable" "Disabled,Enabled" group.long c15:0x01C9++0x00 line.long 0x00 "PMCNTENSET,Count Enable Set Register" bitfld.long 0x00 31. "C,CCNT overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. "P3,Event counter PMN 3 enable bit" "Disabled,Enabled" bitfld.long 0x00 2. "P2,Event counter PMN 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. "P1,Event counter PMN 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. "P0,Event counter PMN 0 enable bit" "Disabled,Enabled" group.long c15:0x02C9++0x00 line.long 0x00 "PMCNTENCLR,Count Enable Clear Register" bitfld.long 0x00 31. "C,CCNT overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. "P3,Event counter PMN 3 enable bit" "Disabled,Enabled" bitfld.long 0x00 2. "P2,Event counter PMN 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. "P1,Event counter PMN 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. "P0,Event counter PMN 0 enable bit" "Disabled,Enabled" group.long c15:0x03C9++0x00 line.long 0x00 "PMOVSR,Overflow Status Flags Register" eventfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow" newline eventfld.long 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow" eventfld.long 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow" eventfld.long 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow" eventfld.long 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow" wgroup.long c15:0x04C9++0x00 line.long 0x00 "PMSWINC,Software Increment Register" bitfld.long 0x00 3. "P3,PMN3 software increment" "No effect,Increment" bitfld.long 0x00 2. "P2,PMN2 software increment" "No effect,Increment" bitfld.long 0x00 1. "P1,PMN1 software increment" "No effect,Increment" bitfld.long 0x00 0. "P0,PMN0 software increment" "No effect,Increment" group.long c15:0x05C9++0x00 line.long 0x00 "PMSELR,Event Counter Selection Register" bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.open "Common Event Identification Registers" rgroup.long c15:0x06C9++0x00 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 30. "CHAIN,Chain" "Not implemented,Implemented" bitfld.long 0x00 29. "BUS_CYCLES,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 27. "INST_SPEC,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. "MEMORY_ERROR,Local memory error" "Not implemented,Implemented" newline bitfld.long 0x00 25. "BUS_ACCESS,Bus access" "Not implemented,Implemented" bitfld.long 0x00 20. "L1I_CACHE,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. "MEM_ACCESS,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 18. "BR_PRED,Predictable branch speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 17. "CPU_CYCLES,CPU cycle" "Not implemented,Implemented" bitfld.long 0x00 16. "BR_MIS_PRED,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 15. "UNALIGNED_LDST_RETIRED,Instruction architecturally executed condition code check pass unaligned load or store" "Not implemented,Implemented" bitfld.long 0x00 14. "BR_RETURN_RETIRED,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" newline bitfld.long 0x00 13. "BR_IMMED_RETIRED,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.long 0x00 12. "PC_WRITE_RETIRED,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 11. "CID_WRITE_RETIRED,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. "EXC_RETURN,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" newline bitfld.long 0x00 9. "EXC_TAKEN,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 8. "INST_RETIRED,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. "ST_RETIRED,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.long 0x00 6. "LD_RETIRED,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" newline bitfld.long 0x00 4. "L1D_CACHE,Level 1 data cache access" "Not implemented,Implemented" bitfld.long 0x00 3. "L1D_CACHE_REFILL,Level 1 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 1. "L1I_CACHE_REFILL,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.long 0x00 0. "SW_INCR,Software increment" "Not implemented,Implemented" rgroup.long c15:0x07C9++0x00 line.long 0x00 "PMCEID1,Common Event Identification Register 1" bitfld.long 0x00 19. "STALL_BACKEND,No operation issued due to backend" "Not implemented,Implemented" bitfld.long 0x00 18. "STALL_FRONTEND,No operation issued due to the frontend" "Not implemented,Implemented" bitfld.long 0x00 17. "BR_MIS_PRED_RETIRED,Instruction architecturally executed mispredicted branch" "Not implemented,Implemented" bitfld.long 0x00 16. "BR_RETIRED,Instruction architecturally executed branch" "Not implemented,Implemented" tree.end newline group.long c15:0x00D9++0x00 line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register [31:0]" group.quad c15:0x10090++0x01 line.quad 0x00 "PMCCNTR,Performance Monitor Cycle Count Register [63:0]" if (((per.l(c15:0x05C9))&0x1F)==0x1F) group.long c15:0x01D9++0x00 line.long 0x00 "PMXEVTYPER,Selected Event Type and Filter Register - PMCCFILTR" bitfld.long 0x00 31. "P,Privileged modes filtering" "Disabled,Enabled" bitfld.long 0x00 30. "U,User modes filtering" "Disabled,Enabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering" "Disabled,Enabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering" "Disabled,Enabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering" "Disabled,Enabled" elif (((per.l(c15:0x05C9))&0x1F)<=0x03) group.long c15:0x01D9++0x00 line.long 0x00 "PMXEVTYPER,Selected Event Type and Filter Register - PMEVTYPER" bitfld.long 0x00 31. "P,Privileged modes filtering" "Disabled,Enabled" bitfld.long 0x00 30. "U,User modes filtering" "Disabled,Enabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering" "Disabled,Enabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering" "Disabled,Enabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering" "Disabled,Enabled" bitfld.long 0x00 25. "MT,Multithreading" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event number" else rgroup.long c15:0x01D9++0x00 line.long 0x00 "PMXEVTYPER,Selected Event Type and Filter Register" endif group.long c15:0x02D9++0x00 line.long 0x00 "PMXEVCNTR,Selected Event Counter Register" group.long c15:0x00E9++0x00 line.long 0x00 "PMUSERENR,User Enable Register" bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,User enable" "Disabled,Enabled" group.long c15:0x01E9++0x00 line.long 0x00 "PMINTENSET,Interrupt Enable Set Register" bitfld.long 0x00 31. "C,CCNT overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. "P3,PMCNT3 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. "P2,PMCNT2 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. "P1,PMCNT1 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. "P0,PMCNT0 overflow interrupt enable" "Disabled,Enabled" group.long c15:0x02E9++0x00 line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register" eventfld.long 0x00 31. "C,CCNT overflow interrupt enable" "Disabled,Enabled" newline eventfld.long 0x00 3. "P3,PMCNT3 overflow interrupt enable" "Disabled,Enabled" eventfld.long 0x00 2. "P2,PMCNT2 overflow interrupt enable" "Disabled,Enabled" eventfld.long 0x00 1. "P1,PMCNT1 overflow interrupt enable" "Disabled,Enabled" eventfld.long 0x00 0. "P0,PMCNT0 overflow interrupt enable" "Disabled,Enabled" group.long c15:0x3E9++0x00 line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register" group.long c15:(0x008E+0x0)++0x00 line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0" group.long c15:(0x00CE+0x0)++0x00 line.long 0x00 "PMEVTYPER0,Performance Monitors Event Type Register 0" group.long c15:(0x008E+0x100)++0x00 line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1" group.long c15:(0x00CE+0x100)++0x00 line.long 0x00 "PMEVTYPER1,Performance Monitors Event Type Register 1" group.long c15:(0x008E+0x200)++0x00 line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2" group.long c15:(0x00CE+0x200)++0x00 line.long 0x00 "PMEVTYPER2,Performance Monitors Event Type Register 2" group.long c15:(0x008E+0x300)++0x00 line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3" group.long c15:(0x00CE+0x300)++0x00 line.long 0x00 "PMEVTYPER3,Performance Monitors Event Type Register 3" group.long c15:0x07FE++0x00 line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" tree.end tree "System Timer Registers" rgroup.long c15:0x000E++0x00 line.long 0x00 "CNTFRQ,Counter Frequency Register" rgroup.quad c15:0x100E0++0x01 line.quad 0x00 "CNTPCT,Counter Physical Count Register" rgroup.quad c15:0x110E0++0x01 line.quad 0x00 "CNTVCT,Counter Virtual Count Register" group.quad c15:0x140E0++0x01 line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register" group.long c15:0x001E++0x00 line.long 0x00 "CNTKCTL,Timer PL1 Control Register" bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 mode" "Disabled,Enabled" bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 mode" "Disabled,Enabled" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter, when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" newline bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled" bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled" group.long c15:0x401E++0x00 line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTPCT is the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTPCT trigger bit, defined by EVNTI" "0 to 1,1 to 0" bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the physical counter" "Disabled,Enabled" bitfld.long 0x00 1. "EL1PCEN,Controls whether the Non-secure copies of the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" newline bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" group.long c15:0x002E++0x00 line.long 0x00 "CNTP_TVAL,Counter EL1 Physical Timer Value Register" group.long c15:0x012E++0x00 line.long 0x00 "CNTP_CTL,Counter EL1 Physical Timer Control Register" bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x120E0++0x01 line.quad 0x00 "CNTP_CVAL,Counter EL1 Physical Compare Value Register" group.long c15:0x003E++0x00 line.long 0x00 "CNTV_TVAL,Counter EL1 Virtual Timer Value Register" group.long c15:0x013E++0x00 line.long 0x00 "CNTV_CTL,Counter EL1 Virtual Timer Control Register" bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x130E0++0x01 line.quad 0x00 "CNTV_CVAL,Counter EL1 Virtual Compare Value Register" group.long c15:0x402E++0x00 line.long 0x00 "CNTHP_TVAL,Counter Non-secure EL2 Physical Timer Value Register" group.long c15:0x412E++0x00 line.long 0x00 "CNTHP_CTL,Counter Non-secure EL2 Physical Timer Control Register" bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x160E0++0x01 line.quad 0x00 "CNTHP_CVAL,Counter Non-secure EL2 Physical Compare Value Register" tree.end tree "Generic Interrupt Controller CPU Interface" tree "AArch32 GIC Physical CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.long c15:(0x048C+0x0)++0x00 line.long 0x00 "ICC_AP0R0,Interrupt Controller Active Priorities Group 0x0 Register" bitfld.long 0x00 31. "P[31],Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P[30],Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P[29],Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.long 0x00 28. "P[28],Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. "P[27],Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P[26],Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.long 0x00 25. "P[25],Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P[24],Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. "P[23],Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.long 0x00 22. "P[22],Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P[21],Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P[20],Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P[19],Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P[18],Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P[17],Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" bitfld.long 0x00 16. "P[16],Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. "P[15],Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P[14],Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.long 0x00 13. "P[13],Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P[12],Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. "P[11],Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.long 0x00 10. "P[10],Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P[9],Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P[8],Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P[7],Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P[6],Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P[5],Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.long 0x00 4. "P[4],Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. "P[3],Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P[2],Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "P[1],Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P[0],Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:(0x048C+0xFFFFFFFFFFFFFC10)++0x00 line.long 0x00 "ICC_AP1R0,Interrupt Controller Active Priorities Group 0xFFFFFFFFFFFFFC10 Register" bitfld.long 0x00 31. "P[31],Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P[30],Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P[29],Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.long 0x00 28. "P[28],Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. "P[27],Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P[26],Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.long 0x00 25. "P[25],Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P[24],Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. "P[23],Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.long 0x00 22. "P[22],Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P[21],Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P[20],Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P[19],Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P[18],Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P[17],Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" bitfld.long 0x00 16. "P[16],Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. "P[15],Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P[14],Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.long 0x00 13. "P[13],Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P[12],Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. "P[11],Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.long 0x00 10. "P[10],Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P[9],Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P[8],Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P[7],Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P[6],Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P[5],Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.long 0x00 4. "P[4],Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. "P[3],Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P[2],Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "P[1],Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P[0],Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline group.long c15:(0x038C+0x0)++0x00 line.long 0x00 "ICC_BPR0,Interrupt Controller Binary Point Register 0" bitfld.long 0x00 0.--2. "BINARYPOINT,5-bit interrupt priority field control" "Reserved,Reserved,2,3,4,5,6,7" group.long c15:(0x038C+0x40)++0x00 line.long 0x00 "ICC_BPR1,Interrupt Controller Binary Point Register 1" bitfld.long 0x00 0.--2. "BINARYPOINT,5-bit interrupt priority field control" "Reserved,Reserved,2,3,4,5,6,7" group.long c15:0x04CC++0x00 line.long 0x00 "ICC_CTLR,Interrupt Control Register for EL1" rbitfld.long 0x00 15. "A3V,Affinity 3 valid" "Not supported,?..." rbitfld.long 0x00 14. "SEIS,SEI support" "Not supported,?..." rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,?..." newline rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..." bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1" bitfld.long 0x00 0. "CBPR,Common binary point register" "0,1" wgroup.long c15:0x01BC++0x00 line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register" hexmask.long.word 0x00 0.--9. 1. "INTID,Interrupt ID" wgroup.long c15:(0x018C+0x0)++0x00 line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0" hexmask.long.word 0x00 0.--9. 1. "INTID,INTID from the corresponding ICC_IAR0 access" rgroup.long c15:(0x028C+0x0)++0x00 line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.long.word 0x00 0.--9. 1. "INTID,INTID of the highest priority pending Group 0 interrupt" rgroup.long c15:(0x008C+0x0)++0x00 line.long 0x00 "ICC_IAR0,Interrupt Controller Interrupt Acknowledge Register 0" hexmask.long.word 0x00 0.--9. 1. "INTID,INTID of the signaled interrupt" group.long c15:(0x06CC+0x0)++0x00 line.long 0x00 "ICC_IGRPEN0,Interrupt Controller Group Enable Register 0" bitfld.long 0x00 0. "ENABLE,Enable group 0 interrupts" "Disabled,Enabled" wgroup.long c15:(0x018C+0x40)++0x00 line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1" hexmask.long.word 0x00 0.--9. 1. "INTID,INTID from the corresponding ICC_IAR0 access" rgroup.long c15:(0x028C+0x40)++0x00 line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.long.word 0x00 0.--9. 1. "INTID,INTID of the highest priority pending Group 1 interrupt" rgroup.long c15:(0x008C+0x40)++0x00 line.long 0x00 "ICC_IAR1,Interrupt Controller Interrupt Acknowledge Register 1" hexmask.long.word 0x00 0.--9. 1. "INTID,INTID of the signaled interrupt" group.long c15:(0x06CC+0x100)++0x00 line.long 0x00 "ICC_IGRPEN1,Interrupt Controller Group Enable Register 1" bitfld.long 0x00 0. "ENABLE,Enable group 1 interrupts" "Disabled,Enabled" group.long c15:0x0064++0x00 line.long 0x00 "ICC_PMR,Interrupt Controller Interrupt Priority Mask Register" bitfld.long 0x00 3.--7. "PRIORITY,The priority mask level for the CPU interface" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Lowest" rgroup.long c15:0x03BC++0x00 line.long 0x00 "ICC_RPR,Interrupt Controller Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" wgroup.quad c15:(0x120C0-0x0)++0x01 line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" bitfld.quad 0x00 0.--4. "TARGETLIST,Target list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" wgroup.quad c15:(0x120C0-0x2000)++0x01 line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" bitfld.quad 0x00 0.--4. "TARGETLIST,Target list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" wgroup.quad c15:0x110C0++0x01 line.quad 0x00 "ICC_ASGI1R,Alias SGI Generation Register $2" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" bitfld.quad 0x00 0.--4. "TARGETLIST,Target list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x05CC++0x00 line.long 0x00 "ICC_SRE,System Register Enable Register for EL1" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "Reserved,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "Reserved,Yes" bitfld.long 0x00 0. "SRE,System register enable" "Reserved,Enabled" group.long c15:0x459C++0x00 line.long 0x00 "ICC_HSRE,System Register Enable Register for EL2" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Reserved,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "Reserved,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "Reserved,Yes" newline bitfld.long 0x00 0. "SRE,System register enable" "Reserved,Enabled" tree.end tree "AArch32 GIC Virtual CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.long c15:(0x048C+0x0)++0x00 line.long 0x00 "ICV_AP0R0,Interrupt Controller Virtual Active Priorities Group 0x0 Register 0" bitfld.long 0x00 31. "P[31],Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P[30],Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P[29],Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.long 0x00 28. "P[28],Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. "P[27],Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P[26],Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.long 0x00 25. "P[25],Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P[24],Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. "P[23],Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.long 0x00 22. "P[22],Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P[21],Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P[20],Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P[19],Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P[18],Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P[17],Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" bitfld.long 0x00 16. "P[16],Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. "P[15],Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P[14],Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.long 0x00 13. "P[13],Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P[12],Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. "P[11],Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.long 0x00 10. "P[10],Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P[9],Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P[8],Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P[7],Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P[6],Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P[5],Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.long 0x00 4. "P[4],Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. "P[3],Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P[2],Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "P[1],Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P[0],Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:(0x048C+0xFFFFFFFFFFFFFC10)++0x00 line.long 0x00 "ICV_AP1R0,Interrupt Controller Virtual Active Priorities Group 0xFFFFFFFFFFFFFC10 Register 0" bitfld.long 0x00 31. "P[31],Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P[30],Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P[29],Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.long 0x00 28. "P[28],Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. "P[27],Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P[26],Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.long 0x00 25. "P[25],Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P[24],Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. "P[23],Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.long 0x00 22. "P[22],Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P[21],Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P[20],Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P[19],Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P[18],Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P[17],Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" bitfld.long 0x00 16. "P[16],Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. "P[15],Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P[14],Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.long 0x00 13. "P[13],Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P[12],Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. "P[11],Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.long 0x00 10. "P[10],Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P[9],Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P[8],Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P[7],Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P[6],Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P[5],Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.long 0x00 4. "P[4],Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. "P[3],Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P[2],Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "P[1],Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P[0],Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline group.long c15:0x04CC++0x00 line.long 0x00 "ICV_CTLR,Interrupt Controller Virtual Control Register" rbitfld.long 0x00 15. "A3V,Affinity 3 valid" "Not supported,?..." rbitfld.long 0x00 14. "SEIS,SEI support" "Not supported,?..." rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,?..." newline rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..." bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1" bitfld.long 0x00 0. "CBPR,Common binary point register" "0,1" wgroup.long c15:0x01BC++0x00 line.long 0x00 "ICV_DIR,Interrupt Controller Virtual Deactivate Interrupt Register" hexmask.long.word 0x00 0.--15. 1. "INTID,Interrupt ID" hgroup.long c15:(0x008C+0x0)++0x00 hide.long 0x00 "ICV_IAR0,Interrupt Controller Vitrtual Interrupt Acknowledge Register 0" wgroup.long c15:(0x018C+0x0)++0x00 line.long 0x00 "ICV_EOIR0,Interrupt Controller Vitrtual End Of Interrupt Register 0" hexmask.long.word 0x00 0.--15. 1. "INTID,INTID from the corresponding ICC_IAR0 access" rgroup.long c15:(0x028C+0x0)++0x00 line.long 0x00 "ICV_HPPIR0,Interrupt Controller Vitrtual Highest Priority Pending Interrupt Register 0" hexmask.long.word 0x00 0.--15. 1. "INTID,INTID of the highest priority pending Group 0 interrupt" group.long c15:(0x038C+0x0)++0x00 line.long 0x00 "ICV_BPR0,Interrupt Controller Vitrtual Binary Point Register 0" bitfld.long 0x00 0.--2. "BINARYPOINT,5-bit interrupt priority field control" "Reserved,Reserved,2,3,4,5,6,7" hgroup.long c15:(0x008C+0x40)++0x00 hide.long 0x00 "ICV_IAR1,Interrupt Controller Vitrtual Interrupt Acknowledge Register 1" wgroup.long c15:(0x018C+0x40)++0x00 line.long 0x00 "ICV_EOIR1,Interrupt Controller Vitrtual End Of Interrupt Register 1" hexmask.long.word 0x00 0.--15. 1. "INTID,INTID from the corresponding ICC_IAR1 access" rgroup.long c15:(0x028C+0x40)++0x00 line.long 0x00 "ICV_HPPIR1,Interrupt Controller Vitrtual Highest Priority Pending Interrupt Register 1" hexmask.long.word 0x00 0.--15. 1. "INTID,INTID of the highest priority pending Group 1 interrupt" group.long c15:(0x038C+0x40)++0x00 line.long 0x00 "ICV_BPR1,Interrupt Controller Vitrtual Binary Point Register 1" bitfld.long 0x00 0.--2. "BINARYPOINT,5-bit interrupt priority field control" "Reserved,Reserved,2,3,4,5,6,7" group.long c15:0x07CC++0x00 line.long 0x00 "ICV_IGRPEN1,Interrupt Controller Virtual Group Enable Register 1" bitfld.long 0x00 0. "ENABLE,Enable group 1 interrupts" "Disabled,Enabled" group.long c15:0x06CC++0x00 line.long 0x00 "ICV_IGRPEN0,Interrupt Controller Virtual Interrupt Group 0 Enable Register" bitfld.long 0x00 0. "ENABLE,Enable group 0 interrupts" "Disabled,Enabled" group.long c15:0x0064++0x00 line.long 0x00 "ICV_PMR,Interrupt Controller Virtual Interrupt Priority Mask Register" bitfld.long 0x00 3.--7. "PRIORITY,The priority mask level for the CPU interface" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Lowest" rgroup.long c15:0x03BC++0x00 line.long 0x00 "ICV_RPR,Interrupt Controller Virtual Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" tree.end tree "AArch32 Virtual Interface Control System Registers" tree.open "Interrupt Controller Hypervisor Active Priorities Register" group.long c15:0x408C++0x00 line.long 0x00 "ICH_AP0R0,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0" bitfld.long 0x00 31. "P[31],Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P[30],Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P[29],Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.long 0x00 28. "P[28],Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. "P[27],Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P[26],Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.long 0x00 25. "P[25],Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P[24],Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. "P[23],Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.long 0x00 22. "P[22],Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P[21],Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P[20],Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P[19],Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P[18],Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P[17],Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" bitfld.long 0x00 16. "P[16],Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. "P[15],Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P[14],Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.long 0x00 13. "P[13],Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P[12],Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. "P[11],Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.long 0x00 10. "P[10],Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P[9],Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P[8],Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P[7],Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P[6],Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P[5],Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.long 0x00 4. "P[4],Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. "P[3],Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P[2],Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "P[1],Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P[0],Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:0x409C++0x00 line.long 0x00 "ICH_AP1R0,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0" bitfld.long 0x00 31. "P[31],Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P[30],Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P[29],Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.long 0x00 28. "P[28],Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. "P[27],Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P[26],Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.long 0x00 25. "P[25],Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P[24],Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. "P[23],Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.long 0x00 22. "P[22],Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P[21],Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P[20],Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P[19],Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P[18],Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 18. "P[17],Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" bitfld.long 0x00 16. "P[16],Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. "P[15],Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P[14],Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.long 0x00 13. "P[13],Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P[12],Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. "P[11],Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.long 0x00 10. "P[10],Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P[9],Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P[8],Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P[7],Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P[6],Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P[5],Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.long 0x00 4. "P[4],Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. "P[3],Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P[2],Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "P[1],Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P[0],Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline group.long c15:0x40BC++0x00 line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register" bitfld.long 0x00 27.--31. "EOICOUNT,Number of successful write to a virtual EOIR or DIR resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. "TDIR,Trap virtual EL1 writes to ICC_DIR" "Not trapped,Trapped" bitfld.long 0x00 12. "TALL1,Trap all virtual EL1 accesses to ICC_* system registers for Group 1 interrupts to EL2" "Not trapped,Trapped" newline bitfld.long 0x00 11. "TALL0,Trap all virtual EL1 accesses to ICC_* system registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 10. "TC,Trap all virtual EL1 accesses to system registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" bitfld.long 0x00 7. "VGRP1DIE,VM group 1 disabled interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. "VGRP1EIE,VM group 1 enabled interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "VGRP0DIE,VM group 0 disabled interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. "VGRP0EIE,VM group 0 enabled interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. "NPIE,No pending interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. "LRENPIE,List register entry not present interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "UIE,Underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" rgroup.long c15:0x41BC++0x00 line.long 0x00 "ICH_VTR,Interrupt Controller Hypervisor Control VGIC Type Register" bitfld.long 0x00 29.--31. "PRIBITS,Priority bits" "Reserved,Reserved,Reserved,Reserved,5,?..." bitfld.long 0x00 26.--28. "PREBITS,Preemption bits" "Reserved,Reserved,Reserved,Reserved,5,?..." bitfld.long 0x00 23.--25. "IDBITS,The number of virtual interrupt identifier bits supported" "16 bits,?..." bitfld.long 0x00 22. "SEIS,SEI Support" "Not supported,?..." newline bitfld.long 0x00 21. "A3V,Affinity 3 support" "Not supported,?..." bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Reserved,Not supported" bitfld.long 0x00 19. "TDS,Separate trapping EL1 writes to ICV_DIR supported" "Reserved,Supported" bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers" "Reserved,Reserved,Reserved,4,?..." rgroup.long c15:0x42BC++0x00 line.long 0x00 "ICH_MISR,Interrupt Controller Maintenance Interrupt Status Register" bitfld.long 0x00 7. "VGRP1D,vPE group 1 disabled" "No,Yes" bitfld.long 0x00 6. "VGRP1E,vPE group 1 enabled" "Disabled,Enabled" bitfld.long 0x00 5. "VGRP0D,vPE group 0 disabled" "No,Yes" bitfld.long 0x00 4. "VGRP0E,vPE group 0 enabled" "Disabled,Enabled" newline bitfld.long 0x00 3. "NP,No pending maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 2. "LRENP,List register entry not present" "Not present,Present" bitfld.long 0x00 1. "U,Underflow assertion" "Not asserted,Asserted" bitfld.long 0x00 0. "EOI,End of interrupt assertion" "Not asserted,Asserted" rgroup.long c15:0x43BC++0x00 line.long 0x00 "ICH_EISR,Interrupt Controller End of Interrupt Status Register" bitfld.long 0x00 3. "STATUS[3],EOI maintenance interrupt status bit for List (ICH_LR3) register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "STATUS[2],EOI maintenance interrupt status bit for List (ICH_LR2) register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "STATUS[1],EOI maintenance interrupt status bit for List (ICH_LR1) register 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "STATUS[0],EOI maintenance interrupt status bit for List (ICH_LR0) register 0" "No interrupt,Interrupt" group.long c15:0x47BC++0x00 line.long 0x00 "ICH_VMCR,Interrupt Controller Virtual Machine Control Register" bitfld.long 0x00 27.--31. "VPMR,Virtual priority mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 21.--23. "VBPR0,Virtual binary point register for group 0" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. "VBPR1,Virtual binary point register for group 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9. "VEOIM,Virtual EOI mode" "Drop & interrupt,Drop" newline bitfld.long 0x00 4. "VCBPR,Virtual common binary point register" "Separate,Both" bitfld.long 0x00 1. "VENG1,Virtual group 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. "VENG0,Virtual group 0 interrupt enable" "Disabled,Enabled" rgroup.long c15:0x45BC++0x00 line.long 0x00 "ICH_ELRSR,Interrupt Controller Empty List Register Status Register" bitfld.long 0x00 3. "STATUS[3],Status bit for list (ICH_LR3) register 3" "Interrupt,No interrupt" bitfld.long 0x00 2. "STATUS[2],Status bit for list (ICH_LR2) register 2" "Interrupt,No interrupt" bitfld.long 0x00 1. "STATUS[1],Status bit for list (ICH_LR1) register 1" "Interrupt,No interrupt" bitfld.long 0x00 0. "STATUS[0],Status bit for list (ICH_LR0) register 0" "Interrupt,No interrupt" group.long c15:(0x40CC+0x0)++0x00 line.long 0x00 "ICH_LR0,Interrupt Controller List Register 0" hexmask.long.word 0x00 0.--15. 1. "VINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x100)++0x00 line.long 0x00 "ICH_LR1,Interrupt Controller List Register 1" hexmask.long.word 0x00 0.--15. 1. "VINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x200)++0x00 line.long 0x00 "ICH_LR2,Interrupt Controller List Register 2" hexmask.long.word 0x00 0.--15. 1. "VINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x300)++0x00 line.long 0x00 "ICH_LR3,Interrupt Controller List Register 3" hexmask.long.word 0x00 0.--15. 1. "VINTID,Virtual INTID of the interrupt" if (((per.l(c15:0x40EC+0x0))&0x20000000)==0x00) group.long c15:(0x40EC+0x0)++0x00 line.long 0x00 "ICH_LRC0,Interrupt Controller List Register 0" bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1" newline bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 9. "EOI,End of interrupt" "Not EOI,EOI" else group.long c15:(0x40EC+0x0)++0x00 line.long 0x00 "ICH_LRC0,Interrupt Controller List Register 0" bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1" newline bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" endif if (((per.l(c15:0x40EC+0x100))&0x20000000)==0x00) group.long c15:(0x40EC+0x100)++0x00 line.long 0x00 "ICH_LRC1,Interrupt Controller List Register 1" bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1" newline bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 9. "EOI,End of interrupt" "Not EOI,EOI" else group.long c15:(0x40EC+0x100)++0x00 line.long 0x00 "ICH_LRC1,Interrupt Controller List Register 1" bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1" newline bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" endif if (((per.l(c15:0x40EC+0x200))&0x20000000)==0x00) group.long c15:(0x40EC+0x200)++0x00 line.long 0x00 "ICH_LRC2,Interrupt Controller List Register 2" bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1" newline bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 9. "EOI,End of interrupt" "Not EOI,EOI" else group.long c15:(0x40EC+0x200)++0x00 line.long 0x00 "ICH_LRC2,Interrupt Controller List Register 2" bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1" newline bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" endif if (((per.l(c15:0x40EC+0x300))&0x20000000)==0x00) group.long c15:(0x40EC+0x300)++0x00 line.long 0x00 "ICH_LRC3,Interrupt Controller List Register 3" bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1" newline bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 9. "EOI,End of interrupt" "Not EOI,EOI" else group.long c15:(0x40EC+0x300)++0x00 line.long 0x00 "ICH_LRC3,Interrupt Controller List Register 3" bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1" newline bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" endif tree.end tree.end tree "Debug Registers" tree "Coresight Management Registers" rgroup.long c14:0x0000++0x00 line.long 0x00 "DBGDIDR,Debug ID Register" bitfld.long 0x00 28.--31. "WRP,Number of watchpoint register pairs" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8,?..." bitfld.long 0x00 24.--27. "BRP,Number of breakpoint register pairs" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8,?..." newline bitfld.long 0x00 20.--23. "CTX_CMP,Number of BRPs with context ID comparison capability" "Reserved,2,?..." bitfld.long 0x00 16.--19. "VERSION,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8,?..." newline bitfld.long 0x00 14. "NSUHD_IMP,Secure user halting debug-mode" "Not supported,?..." bitfld.long 0x00 12. "SE_IMP,Security extensions implemented" "Not implemented,?..." rgroup.long c14:0x0060++0x00 line.long 0x00 "DBGWFAR,Debug Watchpoint Fault Address Register" group.long c14:0x0070++0x00 line.long 0x00 "DBGVCR,Debug Vector Catch Register" bitfld.long 0x00 7. "FIQVCE,FIQ vector catch enable" "Disabled,Enabled" bitfld.long 0x00 6. "IRQVCE,IRQ vector catch enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "DAVCE,Data abort vector catch enable" "Disabled,Enabled" bitfld.long 0x00 3. "PAVCE,Prefetch abort vector catch enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "SVCVCE,Supervisor call (SVC) vector catch enable" "Disabled,Enabled" bitfld.long 0x00 1. "UIVCE,Undefined instruction vector catch enable" "Disabled,Enabled" group.long c14:0x0200++0x00 line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)" rgroup.long c14:0x0050++0x00 line.long 0x00 "DBGDTRRXINT,Debug Receive Register (Internal View)" group.long c14:0x0020++0x00 line.long 0x00 "DBGDCCINT,Debug Comms Channel Interrupt Enable Register" bitfld.long 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled" bitfld.long 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled" rgroup.long c14:0x0010++0x00 line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX register full" "Empty,Full" newline bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" newline bitfld.long 0x00 12. "UDCCDIS,User mode access to communications channel disable" "No,Yes" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,Software breakpoint (BKPT),Reserved,Vector catch,Reserved,Reserved,Reserved,Reserved,Watchpoint,?..." if (((per.l(c14:0x0411))&0x02)==0x02) group.long c14:0x0220++0x00 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX register full" "Empty,Full" newline bitfld.long 0x00 27. "RXO,DBGDTRRX overflow" "No overflow,Overflow" bitfld.long 0x00 26. "TXU,DBGDTRTX underflow" "No underflow,Underflow" newline bitfld.long 0x00 22.--23. "INTDIS,Interrupt disable" "Don't disable interrupts,Disable interrupts targeting non-sec EL1,Disable interrupts targeting EL1 & EL2,Disable all interrupts" bitfld.long 0x00 21. "TDA,Trap debug register access" "Not trapped,Trapped" newline rbitfld.long 0x00 18. "NS,Non-secure status bit" "Reserved,Non-secure" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" newline bitfld.long 0x00 14. "HDE,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 12. "UDCCDIS,User mode access to communications channel disable" "No,Yes" newline bitfld.long 0x00 6. "ERR,Cummulative error flag" "Not error,Error" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,Software breakpoint (BKPT),Reserved,Vector catch,Reserved,Reserved,Reserved,Reserved,Watchpoint,?..." else group.long c14:0x0220++0x00 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)" rbitfld.long 0x00 30. "RXFULL,DBGDTRRX register full" "Empty,Full" rbitfld.long 0x00 29. "TXFULL,DBGDTRTX register full" "Empty,Full" newline rbitfld.long 0x00 27. "RXO,DBGDTRRX overflow" "No overflow,Overflow" rbitfld.long 0x00 26. "TXU,DBGDTRTX underflow" "No underflow,Underflow" newline rbitfld.long 0x00 22.--23. "INTDIS,Interrupt disable" "Don't disable interrupts,Disable interrupts targeting non-sec EL1,Disable interrupts targeting EL1 & EL2,Disable all interrupts" rbitfld.long 0x00 21. "TDA,Trap debug register access" "Not trapped,Trapped" newline rbitfld.long 0x00 18. "NS,Non-secure status bit" "Reserved,Non-secure" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" newline rbitfld.long 0x00 14. "HDE,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 12. "UDCCDIS,User mode access to communications channel disable" "No,Yes" newline rbitfld.long 0x00 6. "ERR,Cummulative error flag" "Not error,Error" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,Software breakpoint (BKPT),Reserved,Vector catch,Reserved,Reserved,Reserved,Reserved,Watchpoint,?..." endif group.long c14:0x0230++0x00 line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)" if (((per.l(c14:0x0411))&0x02)==0x02) group.long c14:0x0260++0x00 line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" else rgroup.long c14:0x0260++0x00 line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" endif wgroup.long c14:0x0050++0x00 line.long 0x00 "DBGDTRTXINT,Debug Transmit Register (Internal View)" rgroup.long c14:0x0707++0x00 line.long 0x00 "DBGDEVID2,Debug Device ID Register 2" rgroup.long c14:0x0717++0x00 line.long 0x00 "DBGDEVID1,Debug Device ID Register 1" bitfld.long 0x00 0.--3. "PCSROFFSET,PC samples returned offset" "Reserved,Reserved,No offset,?..." rgroup.long c14:0x0727++0x00 line.long 0x00 "DBGDEVID0,Debug Device ID Register 0" bitfld.long 0x00 28.--31. "CIDMASK,Level of support for the context ID matching breakpoint masking capability." "Not implemented,?..." bitfld.long 0x00 24.--27. "AR,Debug external auxiliary control register support status" "Not supported,?..." newline bitfld.long 0x00 20.--23. "DL,Support for debug OS double lock register" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. "VE,Specifies implementation of virtualization extension" "Reserved,Implemented,?..." newline bitfld.long 0x00 12.--15. "VC,Form of the vector catch event implemented" "Implemented,?..." bitfld.long 0x00 8.--11. "BPAM,Level of support for immediate virtual address matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" newline bitfld.long 0x00 4.--7. "WPAM,Level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..." bitfld.long 0x00 0.--3. "PCS,Level of support for program counter sampling using debug registers 40 and 43" "Reserved,Reserved,Reserved,Implemented,?..." newline tree.end rgroup.long c14:0x0001++0x00 line.long 0x00 "DBGDRAR,Debug ROM Address Register" hexmask.long 0x00 12.--31. 0x1000 "ROMADDR,ROM physical address" newline bitfld.long 0x00 0. "VALID,ROM table address valid" "Not valid,Valid" rgroup.long c14:0x0002++0x00 line.long 0x00 "DBGDSAR,Debug Self Address Register" wgroup.long c14:0x0401++0x00 line.long 0x00 "DBGOSLAR,Operating System Lock Access Register" rgroup.long c14:0x0411++0x00 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 2. "NTT,32-bit access" "Not required,Required" bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked" newline bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..." group.long c14:0x0431++0x00 line.long 0x00 "DBGOSDLR,OS Double-lock Register" bitfld.long 0x00 0. "DLK,OS double-lock control" "Not locked,Locked" group.long c14:0x0441++0x00 line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Powered down,Emulated" group.long c14:0x0687++0x00 line.long 0x00 "DBGCLAIMSET,Debug Claim Tag Set Register" bitfld.long 0x00 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.long 0x00 6. "CT6,Claim Tag 6 Set" "Not set,Set" newline bitfld.long 0x00 5. "CT5,Claim Tag 5 Set" "Not set,Set" bitfld.long 0x00 4. "CT4,Claim Tag 4 Set" "Not set,Set" newline bitfld.long 0x00 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.long 0x00 2. "CT2,Claim Tag 2 Set" "Not set,Set" newline bitfld.long 0x00 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.long 0x00 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.long c14:0x0697++0x00 line.long 0x00 "DBGCLAIMCLR,Debug Claim Tag Clear Register" bitfld.long 0x00 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.long 0x00 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" newline bitfld.long 0x00 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" bitfld.long 0x00 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" newline bitfld.long 0x00 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.long 0x00 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" newline bitfld.long 0x00 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.long 0x00 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Debug Authentication Status Register" bitfld.long 0x00 10.--11. "HNID,Hyp non-invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x00 8.--9. "HID,Hyp invasive debug" "Reserved,Reserved,Disabled,Enabled" newline bitfld.long 0x00 6.--7. "SNID,Secure non-invasive debug" "Not implemented,?..." bitfld.long 0x00 4.--5. "SID,Secure invasive debug" "Not implemented,?..." newline bitfld.long 0x00 2.--3. "NSNID,Non-secure non-invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x00 0.--1. "NSID,Non-secure invasive debug" "Reserved,Reserved,Disabled,Enabled" rgroup.long c14:0x7000++0x00 "Jazelle Registers" line.long 0x00 "JIDR,Jazelle ID Register" rgroup.long c14:0x7001++0x00 line.long 0x00 "JOSCR,Jazelle OS Control Register" rgroup.long c14:0x7002++0x00 line.long 0x00 "JMCR,Jazelle Main Configuration Register" tree.end tree "Breakpoint Registers" tree "Breakpoint 0" if (((per.l(c14:0x0500+0x0))&0xA00000)==0x0) group.long c14:(0x0400+0x0)++0x00 line.long 0x00 "DBGBVR0,Debug Breakpoint Value Register" hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)" elif (((per.l(c14:0x0500+0x0))&0xA00000)==(0xA00000||0x200000)) group.long c14:(0x0400+0x0)++0x00 line.long 0x00 "DBGBVR0,Debug Breakpoint Value Register" else rgroup.long c14:(0x0400+0x0)++0x00 line.long 0x00 "DBGBVR0,Debug Breakpoint Value Register" endif if ((per.l(c14:0x0500+0x0)&0x2000)==0x2000) if ((per.l(c14:0x0500+0x0)&0xC000)==(0x0000||0x4000)) group.long c14:(0x0500+0x0)++0x00 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif ((per.l(c14:0x0500+0x0)&0xC000)==0x8000) group.long c14:(0x0500+0x0)++0x00 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x0)++0x00 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..." newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x0)++0x00 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 1" if (((per.l(c14:0x0500+0x10))&0xA00000)==0x0) group.long c14:(0x0400+0x10)++0x00 line.long 0x00 "DBGBVR1,Debug Breakpoint Value Register" hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)" elif (((per.l(c14:0x0500+0x10))&0xA00000)==(0xA00000||0x200000)) group.long c14:(0x0400+0x10)++0x00 line.long 0x00 "DBGBVR1,Debug Breakpoint Value Register" else rgroup.long c14:(0x0400+0x10)++0x00 line.long 0x00 "DBGBVR1,Debug Breakpoint Value Register" endif if ((per.l(c14:0x0500+0x10)&0x2000)==0x2000) if ((per.l(c14:0x0500+0x10)&0xC000)==(0x0000||0x4000)) group.long c14:(0x0500+0x10)++0x00 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif ((per.l(c14:0x0500+0x10)&0xC000)==0x8000) group.long c14:(0x0500+0x10)++0x00 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x10)++0x00 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..." newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x10)++0x00 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 2" if (((per.l(c14:0x0500+0x20))&0xA00000)==0x0) group.long c14:(0x0400+0x20)++0x00 line.long 0x00 "DBGBVR2,Debug Breakpoint Value Register" hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)" elif (((per.l(c14:0x0500+0x20))&0xA00000)==(0xA00000||0x200000)) group.long c14:(0x0400+0x20)++0x00 line.long 0x00 "DBGBVR2,Debug Breakpoint Value Register" else rgroup.long c14:(0x0400+0x20)++0x00 line.long 0x00 "DBGBVR2,Debug Breakpoint Value Register" endif if ((per.l(c14:0x0500+0x20)&0x2000)==0x2000) if ((per.l(c14:0x0500+0x20)&0xC000)==(0x0000||0x4000)) group.long c14:(0x0500+0x20)++0x00 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif ((per.l(c14:0x0500+0x20)&0xC000)==0x8000) group.long c14:(0x0500+0x20)++0x00 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x20)++0x00 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..." newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x20)++0x00 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 3" if (((per.l(c14:0x0500+0x30))&0xA00000)==0x0) group.long c14:(0x0400+0x30)++0x00 line.long 0x00 "DBGBVR3,Debug Breakpoint Value Register" hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)" elif (((per.l(c14:0x0500+0x30))&0xA00000)==(0xA00000||0x200000)) group.long c14:(0x0400+0x30)++0x00 line.long 0x00 "DBGBVR3,Debug Breakpoint Value Register" else rgroup.long c14:(0x0400+0x30)++0x00 line.long 0x00 "DBGBVR3,Debug Breakpoint Value Register" endif if ((per.l(c14:0x0500+0x30)&0x2000)==0x2000) if ((per.l(c14:0x0500+0x30)&0xC000)==(0x0000||0x4000)) group.long c14:(0x0500+0x30)++0x00 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif ((per.l(c14:0x0500+0x30)&0xC000)==0x8000) group.long c14:(0x0500+0x30)++0x00 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x30)++0x00 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..." newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x30)++0x00 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 4" if (((per.l(c14:0x0500+0x40))&0xA00000)==0x0) group.long c14:(0x0400+0x40)++0x00 line.long 0x00 "DBGBVR4,Debug Breakpoint Value Register" hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)" elif (((per.l(c14:0x0500+0x40))&0xA00000)==(0xA00000||0x200000)) group.long c14:(0x0400+0x40)++0x00 line.long 0x00 "DBGBVR4,Debug Breakpoint Value Register" else rgroup.long c14:(0x0400+0x40)++0x00 line.long 0x00 "DBGBVR4,Debug Breakpoint Value Register" endif if ((per.l(c14:0x0500+0x40)&0x2000)==0x2000) if ((per.l(c14:0x0500+0x40)&0xC000)==(0x0000||0x4000)) group.long c14:(0x0500+0x40)++0x00 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif ((per.l(c14:0x0500+0x40)&0xC000)==0x8000) group.long c14:(0x0500+0x40)++0x00 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x40)++0x00 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..." newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x40)++0x00 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 5" if (((per.l(c14:0x0500+0x50))&0xA00000)==0x0) group.long c14:(0x0400+0x50)++0x00 line.long 0x00 "DBGBVR5,Debug Breakpoint Value Register" hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)" elif (((per.l(c14:0x0500+0x50))&0xA00000)==(0xA00000||0x200000)) group.long c14:(0x0400+0x50)++0x00 line.long 0x00 "DBGBVR5,Debug Breakpoint Value Register" else rgroup.long c14:(0x0400+0x50)++0x00 line.long 0x00 "DBGBVR5,Debug Breakpoint Value Register" endif if ((per.l(c14:0x0500+0x50)&0x2000)==0x2000) if ((per.l(c14:0x0500+0x50)&0xC000)==(0x0000||0x4000)) group.long c14:(0x0500+0x50)++0x00 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif ((per.l(c14:0x0500+0x50)&0xC000)==0x8000) group.long c14:(0x0500+0x50)++0x00 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x50)++0x00 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..." newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x50)++0x00 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 6" if (((per.l(c14:0x0500+0x60))&0xA00000)==0x0) group.long c14:(0x0400+0x60)++0x00 line.long 0x00 "DBGBVR6,Debug Breakpoint Value Register" hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)" elif (((per.l(c14:0x0500+0x60))&0xA00000)==(0xA00000||0x200000)) group.long c14:(0x0400+0x60)++0x00 line.long 0x00 "DBGBVR6,Debug Breakpoint Value Register" else rgroup.long c14:(0x0400+0x60)++0x00 line.long 0x00 "DBGBVR6,Debug Breakpoint Value Register" endif group.long c14:(0x0101+0x60)++0x00 line.long 0x00 "DBGBXVR6,Breakpoint Extended Value Register" hexmask.long.byte 0x00 0.--7. 1. "VMID,VMID value for comparison" if ((per.l(c14:0x0500+0x60)&0x2000)==0x2000) if ((per.l(c14:0x0500+0x60)&0xC000)==(0x0000||0x4000)) group.long c14:(0x0500+0x60)++0x00 line.long 0x00 "DBGBCR6,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif ((per.l(c14:0x0500+0x60)&0xC000)==0x8000) group.long c14:(0x0500+0x60)++0x00 line.long 0x00 "DBGBCR6,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x60)++0x00 line.long 0x00 "DBGBCR6,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..." newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x60)++0x00 line.long 0x00 "DBGBCR6,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 7" if (((per.l(c14:0x0500+0x70))&0xA00000)==0x0) group.long c14:(0x0400+0x70)++0x00 line.long 0x00 "DBGBVR7,Debug Breakpoint Value Register" hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)" elif (((per.l(c14:0x0500+0x70))&0xA00000)==(0xA00000||0x200000)) group.long c14:(0x0400+0x70)++0x00 line.long 0x00 "DBGBVR7,Debug Breakpoint Value Register" else rgroup.long c14:(0x0400+0x70)++0x00 line.long 0x00 "DBGBVR7,Debug Breakpoint Value Register" endif group.long c14:(0x0101+0x70)++0x00 line.long 0x00 "DBGBXVR7,Breakpoint Extended Value Register" hexmask.long.byte 0x00 0.--7. 1. "VMID,VMID value for comparison" if ((per.l(c14:0x0500+0x70)&0x2000)==0x2000) if ((per.l(c14:0x0500+0x70)&0xC000)==(0x0000||0x4000)) group.long c14:(0x0500+0x70)++0x00 line.long 0x00 "DBGBCR7,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif ((per.l(c14:0x0500+0x70)&0xC000)==0x8000) group.long c14:(0x0500+0x70)++0x00 line.long 0x00 "DBGBCR7,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x70)++0x00 line.long 0x00 "DBGBCR7,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..." newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x70)++0x00 line.long 0x00 "DBGBCR7,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif tree.end tree.end tree "Watchpoint Registers" tree "Watchpoint 0" group.long c14:(0x0600+0x0)++0x00 line.long 0x00 "DBGWVR0,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Address value" if ((per.l(c14:0x0700+0x0)&0x2000)==0x2000) if ((per.l(c14:(0x0700+0x0))&0xC000)==(0x0000||0x4000)) group.long c14:(0x0700+0x0)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" elif ((per.l(c14:0x0700+0x0)&0xC000)==0x8000) group.long c14:(0x0700+0x0)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" else group.long c14:(0x0700+0x0)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..." bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif else group.long c14:(0x0700+0x0)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif tree.end tree "Watchpoint 1" group.long c14:(0x0600+0x10)++0x00 line.long 0x00 "DBGWVR1,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Address value" if ((per.l(c14:0x0700+0x10)&0x2000)==0x2000) if ((per.l(c14:(0x0700+0x10))&0xC000)==(0x0000||0x4000)) group.long c14:(0x0700+0x10)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" elif ((per.l(c14:0x0700+0x10)&0xC000)==0x8000) group.long c14:(0x0700+0x10)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" else group.long c14:(0x0700+0x10)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..." bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif else group.long c14:(0x0700+0x10)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif tree.end tree "Watchpoint 2" group.long c14:(0x0600+0x20)++0x00 line.long 0x00 "DBGWVR2,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Address value" if ((per.l(c14:0x0700+0x20)&0x2000)==0x2000) if ((per.l(c14:(0x0700+0x20))&0xC000)==(0x0000||0x4000)) group.long c14:(0x0700+0x20)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" elif ((per.l(c14:0x0700+0x20)&0xC000)==0x8000) group.long c14:(0x0700+0x20)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" else group.long c14:(0x0700+0x20)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..." bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif else group.long c14:(0x0700+0x20)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif tree.end tree "Watchpoint 3" group.long c14:(0x0600+0x30)++0x00 line.long 0x00 "DBGWVR3,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Address value" if ((per.l(c14:0x0700+0x30)&0x2000)==0x2000) if ((per.l(c14:(0x0700+0x30))&0xC000)==(0x0000||0x4000)) group.long c14:(0x0700+0x30)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" elif ((per.l(c14:0x0700+0x30)&0xC000)==0x8000) group.long c14:(0x0700+0x30)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" else group.long c14:(0x0700+0x30)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..." bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif else group.long c14:(0x0700+0x30)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif tree.end tree "Watchpoint 4" group.long c14:(0x0600+0x40)++0x00 line.long 0x00 "DBGWVR4,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Address value" if ((per.l(c14:0x0700+0x40)&0x2000)==0x2000) if ((per.l(c14:(0x0700+0x40))&0xC000)==(0x0000||0x4000)) group.long c14:(0x0700+0x40)++0x00 line.long 0x00 "DBGWCR4,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" elif ((per.l(c14:0x0700+0x40)&0xC000)==0x8000) group.long c14:(0x0700+0x40)++0x00 line.long 0x00 "DBGWCR4,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" else group.long c14:(0x0700+0x40)++0x00 line.long 0x00 "DBGWCR4,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..." bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif else group.long c14:(0x0700+0x40)++0x00 line.long 0x00 "DBGWCR4,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif tree.end tree "Watchpoint 5" group.long c14:(0x0600+0x50)++0x00 line.long 0x00 "DBGWVR5,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Address value" if ((per.l(c14:0x0700+0x50)&0x2000)==0x2000) if ((per.l(c14:(0x0700+0x50))&0xC000)==(0x0000||0x4000)) group.long c14:(0x0700+0x50)++0x00 line.long 0x00 "DBGWCR5,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" elif ((per.l(c14:0x0700+0x50)&0xC000)==0x8000) group.long c14:(0x0700+0x50)++0x00 line.long 0x00 "DBGWCR5,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" else group.long c14:(0x0700+0x50)++0x00 line.long 0x00 "DBGWCR5,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..." bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif else group.long c14:(0x0700+0x50)++0x00 line.long 0x00 "DBGWCR5,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif tree.end tree "Watchpoint 6" group.long c14:(0x0600+0x60)++0x00 line.long 0x00 "DBGWVR6,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Address value" if ((per.l(c14:0x0700+0x60)&0x2000)==0x2000) if ((per.l(c14:(0x0700+0x60))&0xC000)==(0x0000||0x4000)) group.long c14:(0x0700+0x60)++0x00 line.long 0x00 "DBGWCR6,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" elif ((per.l(c14:0x0700+0x60)&0xC000)==0x8000) group.long c14:(0x0700+0x60)++0x00 line.long 0x00 "DBGWCR6,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" else group.long c14:(0x0700+0x60)++0x00 line.long 0x00 "DBGWCR6,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..." bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif else group.long c14:(0x0700+0x60)++0x00 line.long 0x00 "DBGWCR6,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif tree.end tree "Watchpoint 7" group.long c14:(0x0600+0x70)++0x00 line.long 0x00 "DBGWVR7,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Address value" if ((per.l(c14:0x0700+0x70)&0x2000)==0x2000) if ((per.l(c14:(0x0700+0x70))&0xC000)==(0x0000||0x4000)) group.long c14:(0x0700+0x70)++0x00 line.long 0x00 "DBGWCR7,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" elif ((per.l(c14:0x0700+0x70)&0xC000)==0x8000) group.long c14:(0x0700+0x70)++0x00 line.long 0x00 "DBGWCR7,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" else group.long c14:(0x0700+0x70)++0x00 line.long 0x00 "DBGWCR7,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..." bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif else group.long c14:(0x0700+0x70)++0x00 line.long 0x00 "DBGWCR7,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif tree.end tree.end AUTOINDENT.OFF AUTOINDENT.POP AUTOINDENT.PUSH AUTOINDENT.OFF tree.open "Interrupt Controller (GIC-500)" base COMP.BASE("GICD",-1.) tree "Distributor Interface" width 11. group.long 0x0000++0x03 "Interrupt Controller Distributor" line.long 0x00 "GICD_CTLR,Distributor Control Register" rbitfld.long 0x00 31. " RWP ,Register Write Pending" "Not pending,Pending" rbitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" rbitfld.long 0x00 6. " DS ,Disable Security" "Reserved,Yes" textline " " bitfld.long 0x00 4. " ARE ,Affinity Routing Enable" "Disabled,Enabled" bitfld.long 0x00 1. " ENABLEGRP1 ,Group 1 interrupts Enable" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Group 1 interrupts Enable" "Disabled,Enabled" rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 25. " NO1N ,GIC Distributor supports 1 of N SPIs" "Reserved,Not supported" bitfld.long 0x00 24. " A3V ,GIC Distributor supports non zero values of Affinity level 3" "Supported,?..." bitfld.long 0x00 19.--23. " IDBITS ,Number of INTID bits that the GIC Distributor supports" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,10 bits,?..." textline " " bitfld.long 0x00 18. " DVIS ,GIC Distributor supports Direct Virtual LPI injection" "Not supported,?..." bitfld.long 0x00 17. " LPIS ,GIC Distributor supports Locality-specific Peripheral Interrupts" "Not supported,?..." bitfld.long 0x00 16. " MBIS ,GIC Distributor supports Message-Based Interrupts Supported" "Not supported,?..." textline " " bitfld.long 0x00 10. " SECURITYEXTN ,Indicates whether interrupt controller implements the security extensions" "Not implemented,?..." bitfld.long 0x00 5.--7. " CPUNUMBER ,Number of cores that can be used as interrupt targets when GICD_CTLR.ARE is 0" "Not supported,?..." bitfld.long 0x00 0.--4. " ITLINESNUMBER ,Number of SPI INTIDs that the GIC Distributor supports" "Reserved,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Reserved" rgroup.long 0x0008++0x03 line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register" hexmask.long.byte 0x00 24.--31. 1. " PRODUCTID ,Product ID" bitfld.long 0x00 16.--19. " VARIANT ,Major revision number" "Reserved,r1p3,?..." textline " " bitfld.long 0x00 12.--15. " REVISION ,Minor revision number" "Reserved,Reserved,Reserved,r1p3,?..." hexmask.long.word 0x00 0.--11. 1. " IMPLEMENTER ,Implementer" width 17. tree "Group Registers" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x84))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 (Secure Access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 " bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1" else rgroup.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x88))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 (Secure Access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 " bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1" else rgroup.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x8C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 (Secure Access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 " bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1" else rgroup.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x90))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 (Secure Access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 " bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1" else rgroup.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x94))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 (Secure Access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 " bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1" else rgroup.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x98))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 (Secure Access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 " bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1" else rgroup.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x9C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 (Secure Access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 " bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1" else rgroup.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 (Secure Access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 " bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1" else rgroup.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 (Secure Access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 " bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1" else rgroup.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure Access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1" else rgroup.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xAC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure Access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1" else rgroup.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure Access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1" else rgroup.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure Access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1" else rgroup.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure Access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1" else rgroup.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xBC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure Access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1" else rgroup.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure Access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0,Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0,Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0,Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0,Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0,Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0,Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0,Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0,Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0,Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0,Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0,Group 1" else rgroup.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure Access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0,Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0,Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0,Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0,Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0,Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0,Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0,Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0,Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0,Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0,Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0,Group 1" else rgroup.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure Access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0,Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0,Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0,Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0,Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0,Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0,Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0,Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0,Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0,Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0,Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0,Group 1" else rgroup.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xCC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure Access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0,Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0,Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0,Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0,Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0,Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0,Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0,Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0,Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0,Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0,Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0,Group 1" else rgroup.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure Access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0,Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0,Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0,Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0,Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0,Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0,Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0,Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0,Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0,Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0,Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0,Group 1" else rgroup.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure Access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0,Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0,Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0,Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0,Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0,Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0,Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0,Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0,Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0,Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0,Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0,Group 1" else rgroup.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure Access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0,Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0,Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0,Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0,Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0,Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0,Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0,Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0,Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0,Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0,Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0,Group 1" else rgroup.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xDC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure Access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0,Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0,Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0,Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0,Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0,Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0,Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0,Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0,Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0,Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0,Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0,Group 1" else rgroup.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure Access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0,Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0,Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0,Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0,Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0,Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0,Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0,Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0,Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0,Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0,Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0,Group 1" else rgroup.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure Access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0,Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0,Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0,Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0,Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0,Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0,Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0,Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0,Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0,Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0,Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0,Group 1" else rgroup.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure Access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0,Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0,Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0,Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0,Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0,Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0,Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0,Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0,Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0,Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0,Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0,Group 1" else rgroup.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure Access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0,Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0,Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0,Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0,Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0,Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0,Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0,Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0,Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0,Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0,Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0,Group 1" else rgroup.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure Access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0,Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0,Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0,Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0,Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0,Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0,Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0,Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0,Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0,Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0,Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0,Group 1" else rgroup.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure Access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0,Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0,Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0,Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0,Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0,Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0,Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0,Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0,Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0,Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0,Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0,Group 1" else rgroup.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure Access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0,Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0,Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0,Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0,Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0,Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0,Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0,Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0,Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0,Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0,Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0,Group 1" else rgroup.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" endif tree.end width 22. tree "Set/Clear Enable Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63 ,Set/Clear Enable Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB62 ,Set/Clear Enable Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB61 ,Set/Clear Enable Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60 ,Set/Clear Enable Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB59 ,Set/Clear Enable Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB58 ,Set/Clear Enable Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57 ,Set/Clear Enable Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB56 ,Set/Clear Enable Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB55 ,Set/Clear Enable Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54 ,Set/Clear Enable Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB53 ,Set/Clear Enable Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB52 ,Set/Clear Enable Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51 ,Set/Clear Enable Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB50 ,Set/Clear Enable Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB49 ,Set/Clear Enable Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48 ,Set/Clear Enable Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB47 ,Set/Clear Enable Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB46 ,Set/Clear Enable Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45 ,Set/Clear Enable Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB44 ,Set/Clear Enable Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB43 ,Set/Clear Enable Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42 ,Set/Clear Enable Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB41 ,Set/Clear Enable Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB40 ,Set/Clear Enable Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39 ,Set/Clear Enable Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB38 ,Set/Clear Enable Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB37 ,Set/Clear Enable Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36 ,Set/Clear Enable Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB35 ,Set/Clear Enable Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB34 ,Set/Clear Enable Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33 ,Set/Clear Enable Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB32 ,Set/Clear Enable Bit 32" "Disabled,Enabled" else rgroup.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95 ,Set/Clear Enable Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB94 ,Set/Clear Enable Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB93 ,Set/Clear Enable Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92 ,Set/Clear Enable Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB91 ,Set/Clear Enable Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB90 ,Set/Clear Enable Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89 ,Set/Clear Enable Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB88 ,Set/Clear Enable Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB87 ,Set/Clear Enable Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86 ,Set/Clear Enable Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB85 ,Set/Clear Enable Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB84 ,Set/Clear Enable Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83 ,Set/Clear Enable Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB82 ,Set/Clear Enable Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB81 ,Set/Clear Enable Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80 ,Set/Clear Enable Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB79 ,Set/Clear Enable Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB78 ,Set/Clear Enable Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77 ,Set/Clear Enable Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB76 ,Set/Clear Enable Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB75 ,Set/Clear Enable Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74 ,Set/Clear Enable Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB73 ,Set/Clear Enable Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB72 ,Set/Clear Enable Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71 ,Set/Clear Enable Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB70 ,Set/Clear Enable Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB69 ,Set/Clear Enable Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68 ,Set/Clear Enable Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB67 ,Set/Clear Enable Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB66 ,Set/Clear Enable Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65 ,Set/Clear Enable Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB64 ,Set/Clear Enable Bit 64" "Disabled,Enabled" else rgroup.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127 ,Set/Clear Enable Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB126 ,Set/Clear Enable Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB125 ,Set/Clear Enable Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124 ,Set/Clear Enable Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB123 ,Set/Clear Enable Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB122 ,Set/Clear Enable Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121 ,Set/Clear Enable Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB120 ,Set/Clear Enable Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB119 ,Set/Clear Enable Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118 ,Set/Clear Enable Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB117 ,Set/Clear Enable Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB116 ,Set/Clear Enable Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115 ,Set/Clear Enable Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB114 ,Set/Clear Enable Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB113 ,Set/Clear Enable Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112 ,Set/Clear Enable Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB111 ,Set/Clear Enable Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB110 ,Set/Clear Enable Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109 ,Set/Clear Enable Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB108 ,Set/Clear Enable Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB107 ,Set/Clear Enable Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106 ,Set/Clear Enable Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB105 ,Set/Clear Enable Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB104 ,Set/Clear Enable Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103 ,Set/Clear Enable Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB102 ,Set/Clear Enable Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB101 ,Set/Clear Enable Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100 ,Set/Clear Enable Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB99 ,Set/Clear Enable Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB98 ,Set/Clear Enable Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97 ,Set/Clear Enable Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB96 ,Set/Clear Enable Bit 96" "Disabled,Enabled" else rgroup.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159 ,Set/Clear Enable Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB158 ,Set/Clear Enable Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB157 ,Set/Clear Enable Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156 ,Set/Clear Enable Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB155 ,Set/Clear Enable Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB154 ,Set/Clear Enable Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153 ,Set/Clear Enable Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB152 ,Set/Clear Enable Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB151 ,Set/Clear Enable Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150 ,Set/Clear Enable Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB149 ,Set/Clear Enable Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB148 ,Set/Clear Enable Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147 ,Set/Clear Enable Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB146 ,Set/Clear Enable Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB145 ,Set/Clear Enable Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144 ,Set/Clear Enable Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB143 ,Set/Clear Enable Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB142 ,Set/Clear Enable Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141 ,Set/Clear Enable Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB140 ,Set/Clear Enable Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB139 ,Set/Clear Enable Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138 ,Set/Clear Enable Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB137 ,Set/Clear Enable Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB136 ,Set/Clear Enable Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135 ,Set/Clear Enable Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB134 ,Set/Clear Enable Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB133 ,Set/Clear Enable Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132 ,Set/Clear Enable Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB131 ,Set/Clear Enable Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB130 ,Set/Clear Enable Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129 ,Set/Clear Enable Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB128 ,Set/Clear Enable Bit 128" "Disabled,Enabled" else rgroup.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191 ,Set/Clear Enable Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB190 ,Set/Clear Enable Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB189 ,Set/Clear Enable Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188 ,Set/Clear Enable Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB187 ,Set/Clear Enable Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB186 ,Set/Clear Enable Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185 ,Set/Clear Enable Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB184 ,Set/Clear Enable Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB183 ,Set/Clear Enable Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182 ,Set/Clear Enable Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB181 ,Set/Clear Enable Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB180 ,Set/Clear Enable Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179 ,Set/Clear Enable Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB178 ,Set/Clear Enable Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB177 ,Set/Clear Enable Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176 ,Set/Clear Enable Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB175 ,Set/Clear Enable Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB174 ,Set/Clear Enable Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173 ,Set/Clear Enable Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB172 ,Set/Clear Enable Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB171 ,Set/Clear Enable Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170 ,Set/Clear Enable Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB169 ,Set/Clear Enable Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB168 ,Set/Clear Enable Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167 ,Set/Clear Enable Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB166 ,Set/Clear Enable Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB165 ,Set/Clear Enable Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164 ,Set/Clear Enable Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB163 ,Set/Clear Enable Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB162 ,Set/Clear Enable Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161 ,Set/Clear Enable Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB160 ,Set/Clear Enable Bit 160" "Disabled,Enabled" else rgroup.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223 ,Set/Clear Enable Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB222 ,Set/Clear Enable Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB221 ,Set/Clear Enable Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220 ,Set/Clear Enable Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB219 ,Set/Clear Enable Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB218 ,Set/Clear Enable Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217 ,Set/Clear Enable Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB216 ,Set/Clear Enable Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB215 ,Set/Clear Enable Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214 ,Set/Clear Enable Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB213 ,Set/Clear Enable Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB212 ,Set/Clear Enable Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211 ,Set/Clear Enable Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB210 ,Set/Clear Enable Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB209 ,Set/Clear Enable Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208 ,Set/Clear Enable Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB207 ,Set/Clear Enable Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB206 ,Set/Clear Enable Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205 ,Set/Clear Enable Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB204 ,Set/Clear Enable Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB203 ,Set/Clear Enable Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202 ,Set/Clear Enable Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB201 ,Set/Clear Enable Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB200 ,Set/Clear Enable Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199 ,Set/Clear Enable Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB198 ,Set/Clear Enable Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB197 ,Set/Clear Enable Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196 ,Set/Clear Enable Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB195 ,Set/Clear Enable Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB194 ,Set/Clear Enable Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193 ,Set/Clear Enable Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB192 ,Set/Clear Enable Bit 192" "Disabled,Enabled" else rgroup.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255 ,Set/Clear Enable Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB254 ,Set/Clear Enable Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB253 ,Set/Clear Enable Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252 ,Set/Clear Enable Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB251 ,Set/Clear Enable Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB250 ,Set/Clear Enable Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249 ,Set/Clear Enable Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB248 ,Set/Clear Enable Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB247 ,Set/Clear Enable Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246 ,Set/Clear Enable Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB245 ,Set/Clear Enable Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB244 ,Set/Clear Enable Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243 ,Set/Clear Enable Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB242 ,Set/Clear Enable Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB241 ,Set/Clear Enable Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240 ,Set/Clear Enable Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB239 ,Set/Clear Enable Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB238 ,Set/Clear Enable Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237 ,Set/Clear Enable Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB236 ,Set/Clear Enable Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB235 ,Set/Clear Enable Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234 ,Set/Clear Enable Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB233 ,Set/Clear Enable Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB232 ,Set/Clear Enable Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231 ,Set/Clear Enable Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB230 ,Set/Clear Enable Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB229 ,Set/Clear Enable Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228 ,Set/Clear Enable Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB227 ,Set/Clear Enable Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB226 ,Set/Clear Enable Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225 ,Set/Clear Enable Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB224 ,Set/Clear Enable Bit 224" "Disabled,Enabled" else rgroup.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287 ,Set/Clear Enable Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB286 ,Set/Clear Enable Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB285 ,Set/Clear Enable Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284 ,Set/Clear Enable Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB283 ,Set/Clear Enable Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB282 ,Set/Clear Enable Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281 ,Set/Clear Enable Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB280 ,Set/Clear Enable Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB279 ,Set/Clear Enable Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278 ,Set/Clear Enable Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB277 ,Set/Clear Enable Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB276 ,Set/Clear Enable Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275 ,Set/Clear Enable Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB274 ,Set/Clear Enable Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB273 ,Set/Clear Enable Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272 ,Set/Clear Enable Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB271 ,Set/Clear Enable Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB270 ,Set/Clear Enable Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269 ,Set/Clear Enable Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB268 ,Set/Clear Enable Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB267 ,Set/Clear Enable Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266 ,Set/Clear Enable Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB265 ,Set/Clear Enable Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB264 ,Set/Clear Enable Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263 ,Set/Clear Enable Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB262 ,Set/Clear Enable Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB261 ,Set/Clear Enable Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260 ,Set/Clear Enable Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB259 ,Set/Clear Enable Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB258 ,Set/Clear Enable Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257 ,Set/Clear Enable Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB256 ,Set/Clear Enable Bit 256" "Disabled,Enabled" else rgroup.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319 ,Set/Clear Enable Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB318 ,Set/Clear Enable Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB317 ,Set/Clear Enable Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316 ,Set/Clear Enable Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB315 ,Set/Clear Enable Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB314 ,Set/Clear Enable Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313 ,Set/Clear Enable Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB312 ,Set/Clear Enable Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB311 ,Set/Clear Enable Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310 ,Set/Clear Enable Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB309 ,Set/Clear Enable Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB308 ,Set/Clear Enable Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307 ,Set/Clear Enable Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB306 ,Set/Clear Enable Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB305 ,Set/Clear Enable Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304 ,Set/Clear Enable Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB303 ,Set/Clear Enable Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB302 ,Set/Clear Enable Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301 ,Set/Clear Enable Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB300 ,Set/Clear Enable Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB299 ,Set/Clear Enable Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298 ,Set/Clear Enable Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB297 ,Set/Clear Enable Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB296 ,Set/Clear Enable Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295 ,Set/Clear Enable Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB294 ,Set/Clear Enable Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB293 ,Set/Clear Enable Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292 ,Set/Clear Enable Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB291 ,Set/Clear Enable Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB290 ,Set/Clear Enable Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289 ,Set/Clear Enable Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB288 ,Set/Clear Enable Bit 288" "Disabled,Enabled" else rgroup.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351 ,Set/Clear Enable Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB350 ,Set/Clear Enable Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB349 ,Set/Clear Enable Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348 ,Set/Clear Enable Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB347 ,Set/Clear Enable Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB346 ,Set/Clear Enable Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345 ,Set/Clear Enable Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB344 ,Set/Clear Enable Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB343 ,Set/Clear Enable Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342 ,Set/Clear Enable Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB341 ,Set/Clear Enable Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB340 ,Set/Clear Enable Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339 ,Set/Clear Enable Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB338 ,Set/Clear Enable Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB337 ,Set/Clear Enable Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336 ,Set/Clear Enable Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB335 ,Set/Clear Enable Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB334 ,Set/Clear Enable Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333 ,Set/Clear Enable Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB332 ,Set/Clear Enable Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB331 ,Set/Clear Enable Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330 ,Set/Clear Enable Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB329 ,Set/Clear Enable Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB328 ,Set/Clear Enable Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327 ,Set/Clear Enable Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB326 ,Set/Clear Enable Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB325 ,Set/Clear Enable Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324 ,Set/Clear Enable Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB323 ,Set/Clear Enable Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB322 ,Set/Clear Enable Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321 ,Set/Clear Enable Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB320 ,Set/Clear Enable Bit 320" "Disabled,Enabled" else rgroup.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383 ,Set/Clear Enable Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB382 ,Set/Clear Enable Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB381 ,Set/Clear Enable Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380 ,Set/Clear Enable Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB379 ,Set/Clear Enable Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB378 ,Set/Clear Enable Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377 ,Set/Clear Enable Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB376 ,Set/Clear Enable Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB375 ,Set/Clear Enable Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374 ,Set/Clear Enable Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB373 ,Set/Clear Enable Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB372 ,Set/Clear Enable Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371 ,Set/Clear Enable Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB370 ,Set/Clear Enable Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB369 ,Set/Clear Enable Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368 ,Set/Clear Enable Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB367 ,Set/Clear Enable Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB366 ,Set/Clear Enable Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365 ,Set/Clear Enable Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB364 ,Set/Clear Enable Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB363 ,Set/Clear Enable Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362 ,Set/Clear Enable Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB361 ,Set/Clear Enable Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB360 ,Set/Clear Enable Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359 ,Set/Clear Enable Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB358 ,Set/Clear Enable Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB357 ,Set/Clear Enable Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356 ,Set/Clear Enable Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB355 ,Set/Clear Enable Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB354 ,Set/Clear Enable Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353 ,Set/Clear Enable Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB352 ,Set/Clear Enable Bit 352" "Disabled,Enabled" else rgroup.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415 ,Set/Clear Enable Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB414 ,Set/Clear Enable Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB413 ,Set/Clear Enable Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412 ,Set/Clear Enable Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB411 ,Set/Clear Enable Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB410 ,Set/Clear Enable Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409 ,Set/Clear Enable Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB408 ,Set/Clear Enable Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB407 ,Set/Clear Enable Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406 ,Set/Clear Enable Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB405 ,Set/Clear Enable Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB404 ,Set/Clear Enable Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403 ,Set/Clear Enable Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB402 ,Set/Clear Enable Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB401 ,Set/Clear Enable Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400 ,Set/Clear Enable Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB399 ,Set/Clear Enable Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB398 ,Set/Clear Enable Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397 ,Set/Clear Enable Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB396 ,Set/Clear Enable Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB395 ,Set/Clear Enable Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394 ,Set/Clear Enable Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB393 ,Set/Clear Enable Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB392 ,Set/Clear Enable Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391 ,Set/Clear Enable Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB390 ,Set/Clear Enable Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB389 ,Set/Clear Enable Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388 ,Set/Clear Enable Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB387 ,Set/Clear Enable Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB386 ,Set/Clear Enable Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385 ,Set/Clear Enable Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB384 ,Set/Clear Enable Bit 384" "Disabled,Enabled" else rgroup.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447 ,Set/Clear Enable Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB446 ,Set/Clear Enable Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB445 ,Set/Clear Enable Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444 ,Set/Clear Enable Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB443 ,Set/Clear Enable Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB442 ,Set/Clear Enable Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441 ,Set/Clear Enable Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB440 ,Set/Clear Enable Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB439 ,Set/Clear Enable Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438 ,Set/Clear Enable Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB437 ,Set/Clear Enable Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB436 ,Set/Clear Enable Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435 ,Set/Clear Enable Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB434 ,Set/Clear Enable Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB433 ,Set/Clear Enable Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432 ,Set/Clear Enable Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB431 ,Set/Clear Enable Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB430 ,Set/Clear Enable Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429 ,Set/Clear Enable Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB428 ,Set/Clear Enable Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB427 ,Set/Clear Enable Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426 ,Set/Clear Enable Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB425 ,Set/Clear Enable Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB424 ,Set/Clear Enable Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423 ,Set/Clear Enable Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB422 ,Set/Clear Enable Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB421 ,Set/Clear Enable Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420 ,Set/Clear Enable Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB419 ,Set/Clear Enable Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB418 ,Set/Clear Enable Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417 ,Set/Clear Enable Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB416 ,Set/Clear Enable Bit 416" "Disabled,Enabled" else rgroup.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479 ,Set/Clear Enable Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB478 ,Set/Clear Enable Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB477 ,Set/Clear Enable Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476 ,Set/Clear Enable Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB475 ,Set/Clear Enable Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB474 ,Set/Clear Enable Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473 ,Set/Clear Enable Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB472 ,Set/Clear Enable Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB471 ,Set/Clear Enable Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470 ,Set/Clear Enable Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB469 ,Set/Clear Enable Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB468 ,Set/Clear Enable Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467 ,Set/Clear Enable Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB466 ,Set/Clear Enable Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB465 ,Set/Clear Enable Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464 ,Set/Clear Enable Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB463 ,Set/Clear Enable Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB462 ,Set/Clear Enable Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461 ,Set/Clear Enable Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB460 ,Set/Clear Enable Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB459 ,Set/Clear Enable Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458 ,Set/Clear Enable Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB457 ,Set/Clear Enable Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB456 ,Set/Clear Enable Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455 ,Set/Clear Enable Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB454 ,Set/Clear Enable Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB453 ,Set/Clear Enable Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452 ,Set/Clear Enable Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB451 ,Set/Clear Enable Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB450 ,Set/Clear Enable Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449 ,Set/Clear Enable Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB448 ,Set/Clear Enable Bit 448" "Disabled,Enabled" else rgroup.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511 ,Set/Clear Enable Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB510 ,Set/Clear Enable Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB509 ,Set/Clear Enable Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508 ,Set/Clear Enable Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB507 ,Set/Clear Enable Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB506 ,Set/Clear Enable Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505 ,Set/Clear Enable Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB504 ,Set/Clear Enable Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB503 ,Set/Clear Enable Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502 ,Set/Clear Enable Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB501 ,Set/Clear Enable Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB500 ,Set/Clear Enable Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499 ,Set/Clear Enable Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB498 ,Set/Clear Enable Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB497 ,Set/Clear Enable Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496 ,Set/Clear Enable Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB495 ,Set/Clear Enable Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB494 ,Set/Clear Enable Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493 ,Set/Clear Enable Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB492 ,Set/Clear Enable Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB491 ,Set/Clear Enable Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490 ,Set/Clear Enable Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB489 ,Set/Clear Enable Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB488 ,Set/Clear Enable Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487 ,Set/Clear Enable Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB486 ,Set/Clear Enable Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB485 ,Set/Clear Enable Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484 ,Set/Clear Enable Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB483 ,Set/Clear Enable Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB482 ,Set/Clear Enable Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481 ,Set/Clear Enable Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB480 ,Set/Clear Enable Bit 480" "Disabled,Enabled" else rgroup.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543 ,Set/Clear Enable Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB542 ,Set/Clear Enable Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB541 ,Set/Clear Enable Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540 ,Set/Clear Enable Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB539 ,Set/Clear Enable Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB538 ,Set/Clear Enable Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537 ,Set/Clear Enable Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB536 ,Set/Clear Enable Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB535 ,Set/Clear Enable Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534 ,Set/Clear Enable Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB533 ,Set/Clear Enable Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB532 ,Set/Clear Enable Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531 ,Set/Clear Enable Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB530 ,Set/Clear Enable Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB529 ,Set/Clear Enable Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528 ,Set/Clear Enable Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB527 ,Set/Clear Enable Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB526 ,Set/Clear Enable Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525 ,Set/Clear Enable Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB524 ,Set/Clear Enable Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB523 ,Set/Clear Enable Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522 ,Set/Clear Enable Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB521 ,Set/Clear Enable Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB520 ,Set/Clear Enable Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519 ,Set/Clear Enable Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB518 ,Set/Clear Enable Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB517 ,Set/Clear Enable Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516 ,Set/Clear Enable Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB515 ,Set/Clear Enable Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB514 ,Set/Clear Enable Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513 ,Set/Clear Enable Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB512 ,Set/Clear Enable Bit 512" "Disabled,Enabled" else rgroup.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575 ,Set/Clear Enable Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB574 ,Set/Clear Enable Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB573 ,Set/Clear Enable Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572 ,Set/Clear Enable Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB571 ,Set/Clear Enable Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB570 ,Set/Clear Enable Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569 ,Set/Clear Enable Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB568 ,Set/Clear Enable Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB567 ,Set/Clear Enable Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566 ,Set/Clear Enable Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB565 ,Set/Clear Enable Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB564 ,Set/Clear Enable Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563 ,Set/Clear Enable Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB562 ,Set/Clear Enable Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB561 ,Set/Clear Enable Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560 ,Set/Clear Enable Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB559 ,Set/Clear Enable Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB558 ,Set/Clear Enable Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557 ,Set/Clear Enable Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB556 ,Set/Clear Enable Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB555 ,Set/Clear Enable Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554 ,Set/Clear Enable Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB553 ,Set/Clear Enable Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB552 ,Set/Clear Enable Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551 ,Set/Clear Enable Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB550 ,Set/Clear Enable Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB549 ,Set/Clear Enable Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548 ,Set/Clear Enable Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB547 ,Set/Clear Enable Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB546 ,Set/Clear Enable Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545 ,Set/Clear Enable Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB544 ,Set/Clear Enable Bit 544" "Disabled,Enabled" else rgroup.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607 ,Set/Clear Enable Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB606 ,Set/Clear Enable Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB605 ,Set/Clear Enable Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604 ,Set/Clear Enable Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB603 ,Set/Clear Enable Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB602 ,Set/Clear Enable Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601 ,Set/Clear Enable Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB600 ,Set/Clear Enable Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB599 ,Set/Clear Enable Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598 ,Set/Clear Enable Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB597 ,Set/Clear Enable Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB596 ,Set/Clear Enable Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595 ,Set/Clear Enable Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB594 ,Set/Clear Enable Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB593 ,Set/Clear Enable Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592 ,Set/Clear Enable Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB591 ,Set/Clear Enable Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB590 ,Set/Clear Enable Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589 ,Set/Clear Enable Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB588 ,Set/Clear Enable Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB587 ,Set/Clear Enable Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586 ,Set/Clear Enable Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB585 ,Set/Clear Enable Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB584 ,Set/Clear Enable Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583 ,Set/Clear Enable Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB582 ,Set/Clear Enable Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB581 ,Set/Clear Enable Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580 ,Set/Clear Enable Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB579 ,Set/Clear Enable Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB578 ,Set/Clear Enable Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577 ,Set/Clear Enable Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB576 ,Set/Clear Enable Bit 576" "Disabled,Enabled" else rgroup.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639 ,Set/Clear Enable Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB638 ,Set/Clear Enable Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB637 ,Set/Clear Enable Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636 ,Set/Clear Enable Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB635 ,Set/Clear Enable Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB634 ,Set/Clear Enable Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633 ,Set/Clear Enable Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB632 ,Set/Clear Enable Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB631 ,Set/Clear Enable Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630 ,Set/Clear Enable Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB629 ,Set/Clear Enable Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB628 ,Set/Clear Enable Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627 ,Set/Clear Enable Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB626 ,Set/Clear Enable Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB625 ,Set/Clear Enable Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624 ,Set/Clear Enable Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB623 ,Set/Clear Enable Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB622 ,Set/Clear Enable Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621 ,Set/Clear Enable Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB620 ,Set/Clear Enable Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB619 ,Set/Clear Enable Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618 ,Set/Clear Enable Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB617 ,Set/Clear Enable Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB616 ,Set/Clear Enable Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615 ,Set/Clear Enable Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB614 ,Set/Clear Enable Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB613 ,Set/Clear Enable Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612 ,Set/Clear Enable Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB611 ,Set/Clear Enable Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB610 ,Set/Clear Enable Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609 ,Set/Clear Enable Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB608 ,Set/Clear Enable Bit 608" "Disabled,Enabled" else rgroup.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671 ,Set/Clear Enable Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB670 ,Set/Clear Enable Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB669 ,Set/Clear Enable Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668 ,Set/Clear Enable Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB667 ,Set/Clear Enable Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB666 ,Set/Clear Enable Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665 ,Set/Clear Enable Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB664 ,Set/Clear Enable Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB663 ,Set/Clear Enable Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662 ,Set/Clear Enable Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB661 ,Set/Clear Enable Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB660 ,Set/Clear Enable Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659 ,Set/Clear Enable Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB658 ,Set/Clear Enable Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB657 ,Set/Clear Enable Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656 ,Set/Clear Enable Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB655 ,Set/Clear Enable Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB654 ,Set/Clear Enable Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653 ,Set/Clear Enable Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB652 ,Set/Clear Enable Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB651 ,Set/Clear Enable Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650 ,Set/Clear Enable Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB649 ,Set/Clear Enable Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB648 ,Set/Clear Enable Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647 ,Set/Clear Enable Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB646 ,Set/Clear Enable Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB645 ,Set/Clear Enable Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644 ,Set/Clear Enable Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB643 ,Set/Clear Enable Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB642 ,Set/Clear Enable Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641 ,Set/Clear Enable Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB640 ,Set/Clear Enable Bit 640" "Disabled,Enabled" else rgroup.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703 ,Set/Clear Enable Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB702 ,Set/Clear Enable Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB701 ,Set/Clear Enable Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700 ,Set/Clear Enable Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB699 ,Set/Clear Enable Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB698 ,Set/Clear Enable Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697 ,Set/Clear Enable Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB696 ,Set/Clear Enable Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB695 ,Set/Clear Enable Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694 ,Set/Clear Enable Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB693 ,Set/Clear Enable Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB692 ,Set/Clear Enable Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691 ,Set/Clear Enable Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB690 ,Set/Clear Enable Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB689 ,Set/Clear Enable Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688 ,Set/Clear Enable Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB687 ,Set/Clear Enable Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB686 ,Set/Clear Enable Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685 ,Set/Clear Enable Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB684 ,Set/Clear Enable Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB683 ,Set/Clear Enable Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682 ,Set/Clear Enable Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB681 ,Set/Clear Enable Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB680 ,Set/Clear Enable Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679 ,Set/Clear Enable Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB678 ,Set/Clear Enable Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB677 ,Set/Clear Enable Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676 ,Set/Clear Enable Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB675 ,Set/Clear Enable Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB674 ,Set/Clear Enable Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673 ,Set/Clear Enable Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB672 ,Set/Clear Enable Bit 672" "Disabled,Enabled" else rgroup.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735 ,Set/Clear Enable Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB734 ,Set/Clear Enable Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB733 ,Set/Clear Enable Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732 ,Set/Clear Enable Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB731 ,Set/Clear Enable Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB730 ,Set/Clear Enable Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729 ,Set/Clear Enable Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB728 ,Set/Clear Enable Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB727 ,Set/Clear Enable Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726 ,Set/Clear Enable Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB725 ,Set/Clear Enable Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB724 ,Set/Clear Enable Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723 ,Set/Clear Enable Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB722 ,Set/Clear Enable Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB721 ,Set/Clear Enable Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720 ,Set/Clear Enable Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB719 ,Set/Clear Enable Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB718 ,Set/Clear Enable Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717 ,Set/Clear Enable Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB716 ,Set/Clear Enable Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB715 ,Set/Clear Enable Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714 ,Set/Clear Enable Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB713 ,Set/Clear Enable Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB712 ,Set/Clear Enable Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711 ,Set/Clear Enable Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB710 ,Set/Clear Enable Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB709 ,Set/Clear Enable Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708 ,Set/Clear Enable Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB707 ,Set/Clear Enable Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB706 ,Set/Clear Enable Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705 ,Set/Clear Enable Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB704 ,Set/Clear Enable Bit 704" "Disabled,Enabled" else rgroup.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767 ,Set/Clear Enable Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB766 ,Set/Clear Enable Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB765 ,Set/Clear Enable Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764 ,Set/Clear Enable Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB763 ,Set/Clear Enable Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB762 ,Set/Clear Enable Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761 ,Set/Clear Enable Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB760 ,Set/Clear Enable Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB759 ,Set/Clear Enable Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758 ,Set/Clear Enable Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB757 ,Set/Clear Enable Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB756 ,Set/Clear Enable Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755 ,Set/Clear Enable Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB754 ,Set/Clear Enable Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB753 ,Set/Clear Enable Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752 ,Set/Clear Enable Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB751 ,Set/Clear Enable Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB750 ,Set/Clear Enable Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749 ,Set/Clear Enable Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB748 ,Set/Clear Enable Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB747 ,Set/Clear Enable Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746 ,Set/Clear Enable Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB745 ,Set/Clear Enable Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB744 ,Set/Clear Enable Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743 ,Set/Clear Enable Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB742 ,Set/Clear Enable Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB741 ,Set/Clear Enable Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740 ,Set/Clear Enable Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB739 ,Set/Clear Enable Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB738 ,Set/Clear Enable Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737 ,Set/Clear Enable Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB736 ,Set/Clear Enable Bit 736" "Disabled,Enabled" else rgroup.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799 ,Set/Clear Enable Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB798 ,Set/Clear Enable Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB797 ,Set/Clear Enable Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796 ,Set/Clear Enable Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB795 ,Set/Clear Enable Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB794 ,Set/Clear Enable Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793 ,Set/Clear Enable Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB792 ,Set/Clear Enable Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB791 ,Set/Clear Enable Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790 ,Set/Clear Enable Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB789 ,Set/Clear Enable Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB788 ,Set/Clear Enable Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787 ,Set/Clear Enable Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB786 ,Set/Clear Enable Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB785 ,Set/Clear Enable Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784 ,Set/Clear Enable Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB783 ,Set/Clear Enable Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB782 ,Set/Clear Enable Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781 ,Set/Clear Enable Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB780 ,Set/Clear Enable Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB779 ,Set/Clear Enable Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778 ,Set/Clear Enable Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB777 ,Set/Clear Enable Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB776 ,Set/Clear Enable Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775 ,Set/Clear Enable Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB774 ,Set/Clear Enable Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB773 ,Set/Clear Enable Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772 ,Set/Clear Enable Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB771 ,Set/Clear Enable Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB770 ,Set/Clear Enable Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769 ,Set/Clear Enable Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB768 ,Set/Clear Enable Bit 768" "Disabled,Enabled" else rgroup.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831 ,Set/Clear Enable Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB830 ,Set/Clear Enable Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB829 ,Set/Clear Enable Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828 ,Set/Clear Enable Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB827 ,Set/Clear Enable Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB826 ,Set/Clear Enable Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825 ,Set/Clear Enable Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB824 ,Set/Clear Enable Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB823 ,Set/Clear Enable Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822 ,Set/Clear Enable Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB821 ,Set/Clear Enable Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB820 ,Set/Clear Enable Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819 ,Set/Clear Enable Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB818 ,Set/Clear Enable Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB817 ,Set/Clear Enable Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816 ,Set/Clear Enable Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB815 ,Set/Clear Enable Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB814 ,Set/Clear Enable Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813 ,Set/Clear Enable Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB812 ,Set/Clear Enable Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB811 ,Set/Clear Enable Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810 ,Set/Clear Enable Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB809 ,Set/Clear Enable Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB808 ,Set/Clear Enable Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807 ,Set/Clear Enable Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB806 ,Set/Clear Enable Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB805 ,Set/Clear Enable Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804 ,Set/Clear Enable Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB803 ,Set/Clear Enable Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB802 ,Set/Clear Enable Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801 ,Set/Clear Enable Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB800 ,Set/Clear Enable Bit 800" "Disabled,Enabled" else rgroup.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863 ,Set/Clear Enable Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB862 ,Set/Clear Enable Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB861 ,Set/Clear Enable Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860 ,Set/Clear Enable Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB859 ,Set/Clear Enable Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB858 ,Set/Clear Enable Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857 ,Set/Clear Enable Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB856 ,Set/Clear Enable Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB855 ,Set/Clear Enable Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854 ,Set/Clear Enable Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB853 ,Set/Clear Enable Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB852 ,Set/Clear Enable Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851 ,Set/Clear Enable Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB850 ,Set/Clear Enable Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB849 ,Set/Clear Enable Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848 ,Set/Clear Enable Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB847 ,Set/Clear Enable Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB846 ,Set/Clear Enable Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845 ,Set/Clear Enable Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB844 ,Set/Clear Enable Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB843 ,Set/Clear Enable Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842 ,Set/Clear Enable Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB841 ,Set/Clear Enable Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB840 ,Set/Clear Enable Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839 ,Set/Clear Enable Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB838 ,Set/Clear Enable Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB837 ,Set/Clear Enable Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836 ,Set/Clear Enable Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB835 ,Set/Clear Enable Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB834 ,Set/Clear Enable Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833 ,Set/Clear Enable Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB832 ,Set/Clear Enable Bit 832" "Disabled,Enabled" else rgroup.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895 ,Set/Clear Enable Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB894 ,Set/Clear Enable Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB893 ,Set/Clear Enable Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892 ,Set/Clear Enable Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB891 ,Set/Clear Enable Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB890 ,Set/Clear Enable Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889 ,Set/Clear Enable Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB888 ,Set/Clear Enable Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB887 ,Set/Clear Enable Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886 ,Set/Clear Enable Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB885 ,Set/Clear Enable Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB884 ,Set/Clear Enable Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883 ,Set/Clear Enable Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB882 ,Set/Clear Enable Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB881 ,Set/Clear Enable Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880 ,Set/Clear Enable Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB879 ,Set/Clear Enable Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB878 ,Set/Clear Enable Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877 ,Set/Clear Enable Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB876 ,Set/Clear Enable Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB875 ,Set/Clear Enable Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874 ,Set/Clear Enable Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB873 ,Set/Clear Enable Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB872 ,Set/Clear Enable Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871 ,Set/Clear Enable Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB870 ,Set/Clear Enable Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB869 ,Set/Clear Enable Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868 ,Set/Clear Enable Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB867 ,Set/Clear Enable Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB866 ,Set/Clear Enable Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865 ,Set/Clear Enable Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB864 ,Set/Clear Enable Bit 864" "Disabled,Enabled" else rgroup.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927 ,Set/Clear Enable Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB926 ,Set/Clear Enable Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB925 ,Set/Clear Enable Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924 ,Set/Clear Enable Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB923 ,Set/Clear Enable Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB922 ,Set/Clear Enable Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921 ,Set/Clear Enable Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB920 ,Set/Clear Enable Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB919 ,Set/Clear Enable Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918 ,Set/Clear Enable Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB917 ,Set/Clear Enable Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB916 ,Set/Clear Enable Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915 ,Set/Clear Enable Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB914 ,Set/Clear Enable Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB913 ,Set/Clear Enable Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912 ,Set/Clear Enable Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB911 ,Set/Clear Enable Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB910 ,Set/Clear Enable Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909 ,Set/Clear Enable Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB908 ,Set/Clear Enable Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB907 ,Set/Clear Enable Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906 ,Set/Clear Enable Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB905 ,Set/Clear Enable Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB904 ,Set/Clear Enable Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903 ,Set/Clear Enable Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB902 ,Set/Clear Enable Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB901 ,Set/Clear Enable Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900 ,Set/Clear Enable Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB899 ,Set/Clear Enable Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB898 ,Set/Clear Enable Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897 ,Set/Clear Enable Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB896 ,Set/Clear Enable Bit 896" "Disabled,Enabled" else rgroup.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959 ,Set/Clear Enable Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB958 ,Set/Clear Enable Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB957 ,Set/Clear Enable Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956 ,Set/Clear Enable Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB955 ,Set/Clear Enable Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB954 ,Set/Clear Enable Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953 ,Set/Clear Enable Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB952 ,Set/Clear Enable Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB951 ,Set/Clear Enable Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950 ,Set/Clear Enable Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB949 ,Set/Clear Enable Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB948 ,Set/Clear Enable Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947 ,Set/Clear Enable Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB946 ,Set/Clear Enable Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB945 ,Set/Clear Enable Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944 ,Set/Clear Enable Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB943 ,Set/Clear Enable Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB942 ,Set/Clear Enable Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941 ,Set/Clear Enable Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB940 ,Set/Clear Enable Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB939 ,Set/Clear Enable Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938 ,Set/Clear Enable Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB937 ,Set/Clear Enable Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB936 ,Set/Clear Enable Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935 ,Set/Clear Enable Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB934 ,Set/Clear Enable Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB933 ,Set/Clear Enable Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932 ,Set/Clear Enable Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB931 ,Set/Clear Enable Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB930 ,Set/Clear Enable Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929 ,Set/Clear Enable Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB928 ,Set/Clear Enable Bit 928" "Disabled,Enabled" else rgroup.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991 ,Set/Clear Enable Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB990 ,Set/Clear Enable Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB989 ,Set/Clear Enable Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988 ,Set/Clear Enable Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB987 ,Set/Clear Enable Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB986 ,Set/Clear Enable Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985 ,Set/Clear Enable Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB984 ,Set/Clear Enable Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB983 ,Set/Clear Enable Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982 ,Set/Clear Enable Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB981 ,Set/Clear Enable Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB980 ,Set/Clear Enable Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979 ,Set/Clear Enable Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB978 ,Set/Clear Enable Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB977 ,Set/Clear Enable Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976 ,Set/Clear Enable Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB975 ,Set/Clear Enable Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB974 ,Set/Clear Enable Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973 ,Set/Clear Enable Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB972 ,Set/Clear Enable Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB971 ,Set/Clear Enable Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970 ,Set/Clear Enable Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB969 ,Set/Clear Enable Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB968 ,Set/Clear Enable Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967 ,Set/Clear Enable Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB966 ,Set/Clear Enable Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB965 ,Set/Clear Enable Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964 ,Set/Clear Enable Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB963 ,Set/Clear Enable Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB962 ,Set/Clear Enable Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961 ,Set/Clear Enable Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB960 ,Set/Clear Enable Bit 960" "Disabled,Enabled" else rgroup.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" endif tree.end width 22. tree "Set/Clear Pending Registers" rgroup.long 0x0200++0x03 line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63 ,Set/Clear Pending Bit 63" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND62 ,Set/Clear Pending Bit 62" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND61 ,Set/Clear Pending Bit 61" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60 ,Set/Clear Pending Bit 60" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND59 ,Set/Clear Pending Bit 59" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND58 ,Set/Clear Pending Bit 58" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57 ,Set/Clear Pending Bit 57" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND56 ,Set/Clear Pending Bit 56" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND55 ,Set/Clear Pending Bit 55" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54 ,Set/Clear Pending Bit 54" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND53 ,Set/Clear Pending Bit 53" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND52 ,Set/Clear Pending Bit 52" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51 ,Set/Clear Pending Bit 51" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND50 ,Set/Clear Pending Bit 50" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND49 ,Set/Clear Pending Bit 49" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48 ,Set/Clear Pending Bit 48" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND47 ,Set/Clear Pending Bit 47" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND46 ,Set/Clear Pending Bit 46" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45 ,Set/Clear Pending Bit 45" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND44 ,Set/Clear Pending Bit 44" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND43 ,Set/Clear Pending Bit 43" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42 ,Set/Clear Pending Bit 42" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND41 ,Set/Clear Pending Bit 41" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND40 ,Set/Clear Pending Bit 40" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39 ,Set/Clear Pending Bit 39" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND38 ,Set/Clear Pending Bit 38" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND37 ,Set/Clear Pending Bit 37" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36 ,Set/Clear Pending Bit 36" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND35 ,Set/Clear Pending Bit 35" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND34 ,Set/Clear Pending Bit 34" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33 ,Set/Clear Pending Bit 33" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND32 ,Set/Clear Pending Bit 32" "Not pending,Pending" else rgroup.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95 ,Set/Clear Pending Bit 95" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND94 ,Set/Clear Pending Bit 94" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND93 ,Set/Clear Pending Bit 93" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92 ,Set/Clear Pending Bit 92" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND91 ,Set/Clear Pending Bit 91" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND90 ,Set/Clear Pending Bit 90" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89 ,Set/Clear Pending Bit 89" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND88 ,Set/Clear Pending Bit 88" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND87 ,Set/Clear Pending Bit 87" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86 ,Set/Clear Pending Bit 86" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND85 ,Set/Clear Pending Bit 85" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND84 ,Set/Clear Pending Bit 84" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83 ,Set/Clear Pending Bit 83" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND82 ,Set/Clear Pending Bit 82" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND81 ,Set/Clear Pending Bit 81" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80 ,Set/Clear Pending Bit 80" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND79 ,Set/Clear Pending Bit 79" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND78 ,Set/Clear Pending Bit 78" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77 ,Set/Clear Pending Bit 77" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND76 ,Set/Clear Pending Bit 76" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND75 ,Set/Clear Pending Bit 75" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74 ,Set/Clear Pending Bit 74" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND73 ,Set/Clear Pending Bit 73" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND72 ,Set/Clear Pending Bit 72" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71 ,Set/Clear Pending Bit 71" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND70 ,Set/Clear Pending Bit 70" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND69 ,Set/Clear Pending Bit 69" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68 ,Set/Clear Pending Bit 68" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND67 ,Set/Clear Pending Bit 67" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND66 ,Set/Clear Pending Bit 66" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65 ,Set/Clear Pending Bit 65" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND64 ,Set/Clear Pending Bit 64" "Not pending,Pending" else rgroup.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127 ,Set/Clear Pending Bit 127" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND126 ,Set/Clear Pending Bit 126" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND125 ,Set/Clear Pending Bit 125" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124 ,Set/Clear Pending Bit 124" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND123 ,Set/Clear Pending Bit 123" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND122 ,Set/Clear Pending Bit 122" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121 ,Set/Clear Pending Bit 121" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND120 ,Set/Clear Pending Bit 120" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND119 ,Set/Clear Pending Bit 119" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118 ,Set/Clear Pending Bit 118" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND117 ,Set/Clear Pending Bit 117" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND116 ,Set/Clear Pending Bit 116" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115 ,Set/Clear Pending Bit 115" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND114 ,Set/Clear Pending Bit 114" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND113 ,Set/Clear Pending Bit 113" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112 ,Set/Clear Pending Bit 112" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND111 ,Set/Clear Pending Bit 111" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND110 ,Set/Clear Pending Bit 110" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109 ,Set/Clear Pending Bit 109" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND108 ,Set/Clear Pending Bit 108" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND107 ,Set/Clear Pending Bit 107" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106 ,Set/Clear Pending Bit 106" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND105 ,Set/Clear Pending Bit 105" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND104 ,Set/Clear Pending Bit 104" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103 ,Set/Clear Pending Bit 103" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND102 ,Set/Clear Pending Bit 102" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND101 ,Set/Clear Pending Bit 101" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100 ,Set/Clear Pending Bit 100" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND99 ,Set/Clear Pending Bit 99" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND98 ,Set/Clear Pending Bit 98" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97 ,Set/Clear Pending Bit 97" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND96 ,Set/Clear Pending Bit 96" "Not pending,Pending" else rgroup.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159 ,Set/Clear Pending Bit 159" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND158 ,Set/Clear Pending Bit 158" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND157 ,Set/Clear Pending Bit 157" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156 ,Set/Clear Pending Bit 156" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND155 ,Set/Clear Pending Bit 155" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND154 ,Set/Clear Pending Bit 154" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153 ,Set/Clear Pending Bit 153" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND152 ,Set/Clear Pending Bit 152" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND151 ,Set/Clear Pending Bit 151" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150 ,Set/Clear Pending Bit 150" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND149 ,Set/Clear Pending Bit 149" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND148 ,Set/Clear Pending Bit 148" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147 ,Set/Clear Pending Bit 147" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND146 ,Set/Clear Pending Bit 146" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND145 ,Set/Clear Pending Bit 145" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144 ,Set/Clear Pending Bit 144" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND143 ,Set/Clear Pending Bit 143" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND142 ,Set/Clear Pending Bit 142" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141 ,Set/Clear Pending Bit 141" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND140 ,Set/Clear Pending Bit 140" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND139 ,Set/Clear Pending Bit 139" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138 ,Set/Clear Pending Bit 138" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND137 ,Set/Clear Pending Bit 137" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND136 ,Set/Clear Pending Bit 136" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135 ,Set/Clear Pending Bit 135" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND134 ,Set/Clear Pending Bit 134" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND133 ,Set/Clear Pending Bit 133" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132 ,Set/Clear Pending Bit 132" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND131 ,Set/Clear Pending Bit 131" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND130 ,Set/Clear Pending Bit 130" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129 ,Set/Clear Pending Bit 129" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND128 ,Set/Clear Pending Bit 128" "Not pending,Pending" else rgroup.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191 ,Set/Clear Pending Bit 191" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND190 ,Set/Clear Pending Bit 190" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND189 ,Set/Clear Pending Bit 189" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188 ,Set/Clear Pending Bit 188" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND187 ,Set/Clear Pending Bit 187" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND186 ,Set/Clear Pending Bit 186" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185 ,Set/Clear Pending Bit 185" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND184 ,Set/Clear Pending Bit 184" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND183 ,Set/Clear Pending Bit 183" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182 ,Set/Clear Pending Bit 182" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND181 ,Set/Clear Pending Bit 181" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND180 ,Set/Clear Pending Bit 180" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179 ,Set/Clear Pending Bit 179" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND178 ,Set/Clear Pending Bit 178" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND177 ,Set/Clear Pending Bit 177" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176 ,Set/Clear Pending Bit 176" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND175 ,Set/Clear Pending Bit 175" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND174 ,Set/Clear Pending Bit 174" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173 ,Set/Clear Pending Bit 173" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND172 ,Set/Clear Pending Bit 172" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND171 ,Set/Clear Pending Bit 171" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170 ,Set/Clear Pending Bit 170" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND169 ,Set/Clear Pending Bit 169" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND168 ,Set/Clear Pending Bit 168" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167 ,Set/Clear Pending Bit 167" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND166 ,Set/Clear Pending Bit 166" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND165 ,Set/Clear Pending Bit 165" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164 ,Set/Clear Pending Bit 164" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND163 ,Set/Clear Pending Bit 163" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND162 ,Set/Clear Pending Bit 162" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161 ,Set/Clear Pending Bit 161" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND160 ,Set/Clear Pending Bit 160" "Not pending,Pending" else rgroup.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223 ,Set/Clear Pending Bit 223" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND222 ,Set/Clear Pending Bit 222" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND221 ,Set/Clear Pending Bit 221" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220 ,Set/Clear Pending Bit 220" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND219 ,Set/Clear Pending Bit 219" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND218 ,Set/Clear Pending Bit 218" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217 ,Set/Clear Pending Bit 217" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND216 ,Set/Clear Pending Bit 216" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND215 ,Set/Clear Pending Bit 215" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214 ,Set/Clear Pending Bit 214" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND213 ,Set/Clear Pending Bit 213" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND212 ,Set/Clear Pending Bit 212" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211 ,Set/Clear Pending Bit 211" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND210 ,Set/Clear Pending Bit 210" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND209 ,Set/Clear Pending Bit 209" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208 ,Set/Clear Pending Bit 208" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND207 ,Set/Clear Pending Bit 207" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND206 ,Set/Clear Pending Bit 206" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205 ,Set/Clear Pending Bit 205" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND204 ,Set/Clear Pending Bit 204" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND203 ,Set/Clear Pending Bit 203" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202 ,Set/Clear Pending Bit 202" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND201 ,Set/Clear Pending Bit 201" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND200 ,Set/Clear Pending Bit 200" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199 ,Set/Clear Pending Bit 199" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND198 ,Set/Clear Pending Bit 198" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND197 ,Set/Clear Pending Bit 197" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196 ,Set/Clear Pending Bit 196" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND195 ,Set/Clear Pending Bit 195" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND194 ,Set/Clear Pending Bit 194" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193 ,Set/Clear Pending Bit 193" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND192 ,Set/Clear Pending Bit 192" "Not pending,Pending" else rgroup.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255 ,Set/Clear Pending Bit 255" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND254 ,Set/Clear Pending Bit 254" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND253 ,Set/Clear Pending Bit 253" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252 ,Set/Clear Pending Bit 252" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND251 ,Set/Clear Pending Bit 251" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND250 ,Set/Clear Pending Bit 250" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249 ,Set/Clear Pending Bit 249" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND248 ,Set/Clear Pending Bit 248" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND247 ,Set/Clear Pending Bit 247" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246 ,Set/Clear Pending Bit 246" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND245 ,Set/Clear Pending Bit 245" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND244 ,Set/Clear Pending Bit 244" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243 ,Set/Clear Pending Bit 243" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND242 ,Set/Clear Pending Bit 242" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND241 ,Set/Clear Pending Bit 241" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240 ,Set/Clear Pending Bit 240" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND239 ,Set/Clear Pending Bit 239" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND238 ,Set/Clear Pending Bit 238" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237 ,Set/Clear Pending Bit 237" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND236 ,Set/Clear Pending Bit 236" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND235 ,Set/Clear Pending Bit 235" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234 ,Set/Clear Pending Bit 234" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND233 ,Set/Clear Pending Bit 233" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND232 ,Set/Clear Pending Bit 232" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231 ,Set/Clear Pending Bit 231" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND230 ,Set/Clear Pending Bit 230" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND229 ,Set/Clear Pending Bit 229" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228 ,Set/Clear Pending Bit 228" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND227 ,Set/Clear Pending Bit 227" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND226 ,Set/Clear Pending Bit 226" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225 ,Set/Clear Pending Bit 225" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND224 ,Set/Clear Pending Bit 224" "Not pending,Pending" else rgroup.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287 ,Set/Clear Pending Bit 287" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND286 ,Set/Clear Pending Bit 286" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND285 ,Set/Clear Pending Bit 285" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284 ,Set/Clear Pending Bit 284" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND283 ,Set/Clear Pending Bit 283" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND282 ,Set/Clear Pending Bit 282" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281 ,Set/Clear Pending Bit 281" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND280 ,Set/Clear Pending Bit 280" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND279 ,Set/Clear Pending Bit 279" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278 ,Set/Clear Pending Bit 278" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND277 ,Set/Clear Pending Bit 277" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND276 ,Set/Clear Pending Bit 276" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275 ,Set/Clear Pending Bit 275" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND274 ,Set/Clear Pending Bit 274" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND273 ,Set/Clear Pending Bit 273" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272 ,Set/Clear Pending Bit 272" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND271 ,Set/Clear Pending Bit 271" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND270 ,Set/Clear Pending Bit 270" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269 ,Set/Clear Pending Bit 269" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND268 ,Set/Clear Pending Bit 268" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND267 ,Set/Clear Pending Bit 267" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266 ,Set/Clear Pending Bit 266" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND265 ,Set/Clear Pending Bit 265" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND264 ,Set/Clear Pending Bit 264" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263 ,Set/Clear Pending Bit 263" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND262 ,Set/Clear Pending Bit 262" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND261 ,Set/Clear Pending Bit 261" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260 ,Set/Clear Pending Bit 260" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND259 ,Set/Clear Pending Bit 259" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND258 ,Set/Clear Pending Bit 258" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257 ,Set/Clear Pending Bit 257" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND256 ,Set/Clear Pending Bit 256" "Not pending,Pending" else rgroup.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319 ,Set/Clear Pending Bit 319" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND318 ,Set/Clear Pending Bit 318" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND317 ,Set/Clear Pending Bit 317" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316 ,Set/Clear Pending Bit 316" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND315 ,Set/Clear Pending Bit 315" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND314 ,Set/Clear Pending Bit 314" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313 ,Set/Clear Pending Bit 313" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND312 ,Set/Clear Pending Bit 312" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND311 ,Set/Clear Pending Bit 311" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310 ,Set/Clear Pending Bit 310" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND309 ,Set/Clear Pending Bit 309" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND308 ,Set/Clear Pending Bit 308" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307 ,Set/Clear Pending Bit 307" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND306 ,Set/Clear Pending Bit 306" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND305 ,Set/Clear Pending Bit 305" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304 ,Set/Clear Pending Bit 304" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND303 ,Set/Clear Pending Bit 303" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND302 ,Set/Clear Pending Bit 302" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301 ,Set/Clear Pending Bit 301" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND300 ,Set/Clear Pending Bit 300" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND299 ,Set/Clear Pending Bit 299" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298 ,Set/Clear Pending Bit 298" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND297 ,Set/Clear Pending Bit 297" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND296 ,Set/Clear Pending Bit 296" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295 ,Set/Clear Pending Bit 295" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND294 ,Set/Clear Pending Bit 294" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND293 ,Set/Clear Pending Bit 293" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292 ,Set/Clear Pending Bit 292" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND291 ,Set/Clear Pending Bit 291" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND290 ,Set/Clear Pending Bit 290" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289 ,Set/Clear Pending Bit 289" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND288 ,Set/Clear Pending Bit 288" "Not pending,Pending" else rgroup.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351 ,Set/Clear Pending Bit 351" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND350 ,Set/Clear Pending Bit 350" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND349 ,Set/Clear Pending Bit 349" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348 ,Set/Clear Pending Bit 348" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND347 ,Set/Clear Pending Bit 347" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND346 ,Set/Clear Pending Bit 346" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345 ,Set/Clear Pending Bit 345" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND344 ,Set/Clear Pending Bit 344" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND343 ,Set/Clear Pending Bit 343" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342 ,Set/Clear Pending Bit 342" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND341 ,Set/Clear Pending Bit 341" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND340 ,Set/Clear Pending Bit 340" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339 ,Set/Clear Pending Bit 339" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND338 ,Set/Clear Pending Bit 338" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND337 ,Set/Clear Pending Bit 337" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336 ,Set/Clear Pending Bit 336" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND335 ,Set/Clear Pending Bit 335" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND334 ,Set/Clear Pending Bit 334" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333 ,Set/Clear Pending Bit 333" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND332 ,Set/Clear Pending Bit 332" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND331 ,Set/Clear Pending Bit 331" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330 ,Set/Clear Pending Bit 330" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND329 ,Set/Clear Pending Bit 329" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND328 ,Set/Clear Pending Bit 328" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327 ,Set/Clear Pending Bit 327" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND326 ,Set/Clear Pending Bit 326" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND325 ,Set/Clear Pending Bit 325" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324 ,Set/Clear Pending Bit 324" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND323 ,Set/Clear Pending Bit 323" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND322 ,Set/Clear Pending Bit 322" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321 ,Set/Clear Pending Bit 321" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND320 ,Set/Clear Pending Bit 320" "Not pending,Pending" else rgroup.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383 ,Set/Clear Pending Bit 383" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND382 ,Set/Clear Pending Bit 382" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND381 ,Set/Clear Pending Bit 381" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380 ,Set/Clear Pending Bit 380" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND379 ,Set/Clear Pending Bit 379" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND378 ,Set/Clear Pending Bit 378" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377 ,Set/Clear Pending Bit 377" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND376 ,Set/Clear Pending Bit 376" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND375 ,Set/Clear Pending Bit 375" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374 ,Set/Clear Pending Bit 374" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND373 ,Set/Clear Pending Bit 373" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND372 ,Set/Clear Pending Bit 372" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371 ,Set/Clear Pending Bit 371" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND370 ,Set/Clear Pending Bit 370" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND369 ,Set/Clear Pending Bit 369" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368 ,Set/Clear Pending Bit 368" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND367 ,Set/Clear Pending Bit 367" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND366 ,Set/Clear Pending Bit 366" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365 ,Set/Clear Pending Bit 365" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND364 ,Set/Clear Pending Bit 364" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND363 ,Set/Clear Pending Bit 363" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362 ,Set/Clear Pending Bit 362" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND361 ,Set/Clear Pending Bit 361" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND360 ,Set/Clear Pending Bit 360" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359 ,Set/Clear Pending Bit 359" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND358 ,Set/Clear Pending Bit 358" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND357 ,Set/Clear Pending Bit 357" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356 ,Set/Clear Pending Bit 356" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND355 ,Set/Clear Pending Bit 355" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND354 ,Set/Clear Pending Bit 354" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353 ,Set/Clear Pending Bit 353" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND352 ,Set/Clear Pending Bit 352" "Not pending,Pending" else rgroup.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415 ,Set/Clear Pending Bit 415" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND414 ,Set/Clear Pending Bit 414" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND413 ,Set/Clear Pending Bit 413" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412 ,Set/Clear Pending Bit 412" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND411 ,Set/Clear Pending Bit 411" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND410 ,Set/Clear Pending Bit 410" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409 ,Set/Clear Pending Bit 409" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND408 ,Set/Clear Pending Bit 408" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND407 ,Set/Clear Pending Bit 407" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406 ,Set/Clear Pending Bit 406" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND405 ,Set/Clear Pending Bit 405" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND404 ,Set/Clear Pending Bit 404" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403 ,Set/Clear Pending Bit 403" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND402 ,Set/Clear Pending Bit 402" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND401 ,Set/Clear Pending Bit 401" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400 ,Set/Clear Pending Bit 400" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND399 ,Set/Clear Pending Bit 399" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND398 ,Set/Clear Pending Bit 398" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397 ,Set/Clear Pending Bit 397" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND396 ,Set/Clear Pending Bit 396" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND395 ,Set/Clear Pending Bit 395" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394 ,Set/Clear Pending Bit 394" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND393 ,Set/Clear Pending Bit 393" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND392 ,Set/Clear Pending Bit 392" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391 ,Set/Clear Pending Bit 391" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND390 ,Set/Clear Pending Bit 390" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND389 ,Set/Clear Pending Bit 389" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388 ,Set/Clear Pending Bit 388" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND387 ,Set/Clear Pending Bit 387" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND386 ,Set/Clear Pending Bit 386" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385 ,Set/Clear Pending Bit 385" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND384 ,Set/Clear Pending Bit 384" "Not pending,Pending" else rgroup.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447 ,Set/Clear Pending Bit 447" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND446 ,Set/Clear Pending Bit 446" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND445 ,Set/Clear Pending Bit 445" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444 ,Set/Clear Pending Bit 444" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND443 ,Set/Clear Pending Bit 443" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND442 ,Set/Clear Pending Bit 442" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441 ,Set/Clear Pending Bit 441" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND440 ,Set/Clear Pending Bit 440" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND439 ,Set/Clear Pending Bit 439" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438 ,Set/Clear Pending Bit 438" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND437 ,Set/Clear Pending Bit 437" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND436 ,Set/Clear Pending Bit 436" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435 ,Set/Clear Pending Bit 435" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND434 ,Set/Clear Pending Bit 434" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND433 ,Set/Clear Pending Bit 433" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432 ,Set/Clear Pending Bit 432" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND431 ,Set/Clear Pending Bit 431" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND430 ,Set/Clear Pending Bit 430" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429 ,Set/Clear Pending Bit 429" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND428 ,Set/Clear Pending Bit 428" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND427 ,Set/Clear Pending Bit 427" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426 ,Set/Clear Pending Bit 426" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND425 ,Set/Clear Pending Bit 425" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND424 ,Set/Clear Pending Bit 424" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423 ,Set/Clear Pending Bit 423" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND422 ,Set/Clear Pending Bit 422" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND421 ,Set/Clear Pending Bit 421" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420 ,Set/Clear Pending Bit 420" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND419 ,Set/Clear Pending Bit 419" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND418 ,Set/Clear Pending Bit 418" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417 ,Set/Clear Pending Bit 417" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND416 ,Set/Clear Pending Bit 416" "Not pending,Pending" else rgroup.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479 ,Set/Clear Pending Bit 479" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND478 ,Set/Clear Pending Bit 478" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND477 ,Set/Clear Pending Bit 477" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476 ,Set/Clear Pending Bit 476" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND475 ,Set/Clear Pending Bit 475" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND474 ,Set/Clear Pending Bit 474" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473 ,Set/Clear Pending Bit 473" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND472 ,Set/Clear Pending Bit 472" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND471 ,Set/Clear Pending Bit 471" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470 ,Set/Clear Pending Bit 470" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND469 ,Set/Clear Pending Bit 469" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND468 ,Set/Clear Pending Bit 468" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467 ,Set/Clear Pending Bit 467" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND466 ,Set/Clear Pending Bit 466" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND465 ,Set/Clear Pending Bit 465" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464 ,Set/Clear Pending Bit 464" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND463 ,Set/Clear Pending Bit 463" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND462 ,Set/Clear Pending Bit 462" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461 ,Set/Clear Pending Bit 461" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND460 ,Set/Clear Pending Bit 460" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND459 ,Set/Clear Pending Bit 459" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458 ,Set/Clear Pending Bit 458" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND457 ,Set/Clear Pending Bit 457" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND456 ,Set/Clear Pending Bit 456" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455 ,Set/Clear Pending Bit 455" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND454 ,Set/Clear Pending Bit 454" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND453 ,Set/Clear Pending Bit 453" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452 ,Set/Clear Pending Bit 452" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND451 ,Set/Clear Pending Bit 451" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND450 ,Set/Clear Pending Bit 450" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449 ,Set/Clear Pending Bit 449" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND448 ,Set/Clear Pending Bit 448" "Not pending,Pending" else rgroup.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511 ,Set/Clear Pending Bit 511" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND510 ,Set/Clear Pending Bit 510" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND509 ,Set/Clear Pending Bit 509" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508 ,Set/Clear Pending Bit 508" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND507 ,Set/Clear Pending Bit 507" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND506 ,Set/Clear Pending Bit 506" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505 ,Set/Clear Pending Bit 505" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND504 ,Set/Clear Pending Bit 504" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND503 ,Set/Clear Pending Bit 503" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502 ,Set/Clear Pending Bit 502" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND501 ,Set/Clear Pending Bit 501" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND500 ,Set/Clear Pending Bit 500" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499 ,Set/Clear Pending Bit 499" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND498 ,Set/Clear Pending Bit 498" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND497 ,Set/Clear Pending Bit 497" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496 ,Set/Clear Pending Bit 496" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND495 ,Set/Clear Pending Bit 495" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND494 ,Set/Clear Pending Bit 494" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493 ,Set/Clear Pending Bit 493" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND492 ,Set/Clear Pending Bit 492" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND491 ,Set/Clear Pending Bit 491" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490 ,Set/Clear Pending Bit 490" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND489 ,Set/Clear Pending Bit 489" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND488 ,Set/Clear Pending Bit 488" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487 ,Set/Clear Pending Bit 487" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND486 ,Set/Clear Pending Bit 486" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND485 ,Set/Clear Pending Bit 485" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484 ,Set/Clear Pending Bit 484" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND483 ,Set/Clear Pending Bit 483" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND482 ,Set/Clear Pending Bit 482" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481 ,Set/Clear Pending Bit 481" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND480 ,Set/Clear Pending Bit 480" "Not pending,Pending" else rgroup.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543 ,Set/Clear Pending Bit 543" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND542 ,Set/Clear Pending Bit 542" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND541 ,Set/Clear Pending Bit 541" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540 ,Set/Clear Pending Bit 540" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND539 ,Set/Clear Pending Bit 539" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND538 ,Set/Clear Pending Bit 538" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537 ,Set/Clear Pending Bit 537" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND536 ,Set/Clear Pending Bit 536" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND535 ,Set/Clear Pending Bit 535" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534 ,Set/Clear Pending Bit 534" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND533 ,Set/Clear Pending Bit 533" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND532 ,Set/Clear Pending Bit 532" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531 ,Set/Clear Pending Bit 531" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND530 ,Set/Clear Pending Bit 530" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND529 ,Set/Clear Pending Bit 529" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528 ,Set/Clear Pending Bit 528" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND527 ,Set/Clear Pending Bit 527" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND526 ,Set/Clear Pending Bit 526" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525 ,Set/Clear Pending Bit 525" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND524 ,Set/Clear Pending Bit 524" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND523 ,Set/Clear Pending Bit 523" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522 ,Set/Clear Pending Bit 522" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND521 ,Set/Clear Pending Bit 521" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND520 ,Set/Clear Pending Bit 520" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519 ,Set/Clear Pending Bit 519" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND518 ,Set/Clear Pending Bit 518" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND517 ,Set/Clear Pending Bit 517" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516 ,Set/Clear Pending Bit 516" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND515 ,Set/Clear Pending Bit 515" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND514 ,Set/Clear Pending Bit 514" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513 ,Set/Clear Pending Bit 513" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND512 ,Set/Clear Pending Bit 512" "Not pending,Pending" else rgroup.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575 ,Set/Clear Pending Bit 575" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND574 ,Set/Clear Pending Bit 574" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND573 ,Set/Clear Pending Bit 573" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572 ,Set/Clear Pending Bit 572" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND571 ,Set/Clear Pending Bit 571" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND570 ,Set/Clear Pending Bit 570" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569 ,Set/Clear Pending Bit 569" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND568 ,Set/Clear Pending Bit 568" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND567 ,Set/Clear Pending Bit 567" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566 ,Set/Clear Pending Bit 566" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND565 ,Set/Clear Pending Bit 565" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND564 ,Set/Clear Pending Bit 564" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563 ,Set/Clear Pending Bit 563" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND562 ,Set/Clear Pending Bit 562" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND561 ,Set/Clear Pending Bit 561" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560 ,Set/Clear Pending Bit 560" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND559 ,Set/Clear Pending Bit 559" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND558 ,Set/Clear Pending Bit 558" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557 ,Set/Clear Pending Bit 557" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND556 ,Set/Clear Pending Bit 556" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND555 ,Set/Clear Pending Bit 555" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554 ,Set/Clear Pending Bit 554" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND553 ,Set/Clear Pending Bit 553" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND552 ,Set/Clear Pending Bit 552" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551 ,Set/Clear Pending Bit 551" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND550 ,Set/Clear Pending Bit 550" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND549 ,Set/Clear Pending Bit 549" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548 ,Set/Clear Pending Bit 548" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND547 ,Set/Clear Pending Bit 547" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND546 ,Set/Clear Pending Bit 546" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545 ,Set/Clear Pending Bit 545" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND544 ,Set/Clear Pending Bit 544" "Not pending,Pending" else rgroup.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607 ,Set/Clear Pending Bit 607" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND606 ,Set/Clear Pending Bit 606" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND605 ,Set/Clear Pending Bit 605" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604 ,Set/Clear Pending Bit 604" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND603 ,Set/Clear Pending Bit 603" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND602 ,Set/Clear Pending Bit 602" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601 ,Set/Clear Pending Bit 601" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND600 ,Set/Clear Pending Bit 600" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND599 ,Set/Clear Pending Bit 599" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598 ,Set/Clear Pending Bit 598" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND597 ,Set/Clear Pending Bit 597" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND596 ,Set/Clear Pending Bit 596" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595 ,Set/Clear Pending Bit 595" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND594 ,Set/Clear Pending Bit 594" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND593 ,Set/Clear Pending Bit 593" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592 ,Set/Clear Pending Bit 592" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND591 ,Set/Clear Pending Bit 591" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND590 ,Set/Clear Pending Bit 590" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589 ,Set/Clear Pending Bit 589" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND588 ,Set/Clear Pending Bit 588" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND587 ,Set/Clear Pending Bit 587" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586 ,Set/Clear Pending Bit 586" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND585 ,Set/Clear Pending Bit 585" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND584 ,Set/Clear Pending Bit 584" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583 ,Set/Clear Pending Bit 583" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND582 ,Set/Clear Pending Bit 582" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND581 ,Set/Clear Pending Bit 581" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580 ,Set/Clear Pending Bit 580" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND579 ,Set/Clear Pending Bit 579" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND578 ,Set/Clear Pending Bit 578" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577 ,Set/Clear Pending Bit 577" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND576 ,Set/Clear Pending Bit 576" "Not pending,Pending" else rgroup.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639 ,Set/Clear Pending Bit 639" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND638 ,Set/Clear Pending Bit 638" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND637 ,Set/Clear Pending Bit 637" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636 ,Set/Clear Pending Bit 636" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND635 ,Set/Clear Pending Bit 635" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND634 ,Set/Clear Pending Bit 634" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633 ,Set/Clear Pending Bit 633" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND632 ,Set/Clear Pending Bit 632" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND631 ,Set/Clear Pending Bit 631" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630 ,Set/Clear Pending Bit 630" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND629 ,Set/Clear Pending Bit 629" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND628 ,Set/Clear Pending Bit 628" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627 ,Set/Clear Pending Bit 627" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND626 ,Set/Clear Pending Bit 626" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND625 ,Set/Clear Pending Bit 625" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624 ,Set/Clear Pending Bit 624" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND623 ,Set/Clear Pending Bit 623" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND622 ,Set/Clear Pending Bit 622" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621 ,Set/Clear Pending Bit 621" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND620 ,Set/Clear Pending Bit 620" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND619 ,Set/Clear Pending Bit 619" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618 ,Set/Clear Pending Bit 618" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND617 ,Set/Clear Pending Bit 617" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND616 ,Set/Clear Pending Bit 616" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615 ,Set/Clear Pending Bit 615" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND614 ,Set/Clear Pending Bit 614" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND613 ,Set/Clear Pending Bit 613" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612 ,Set/Clear Pending Bit 612" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND611 ,Set/Clear Pending Bit 611" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND610 ,Set/Clear Pending Bit 610" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609 ,Set/Clear Pending Bit 609" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND608 ,Set/Clear Pending Bit 608" "Not pending,Pending" else rgroup.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671 ,Set/Clear Pending Bit 671" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND670 ,Set/Clear Pending Bit 670" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND669 ,Set/Clear Pending Bit 669" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668 ,Set/Clear Pending Bit 668" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND667 ,Set/Clear Pending Bit 667" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND666 ,Set/Clear Pending Bit 666" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665 ,Set/Clear Pending Bit 665" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND664 ,Set/Clear Pending Bit 664" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND663 ,Set/Clear Pending Bit 663" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662 ,Set/Clear Pending Bit 662" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND661 ,Set/Clear Pending Bit 661" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND660 ,Set/Clear Pending Bit 660" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659 ,Set/Clear Pending Bit 659" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND658 ,Set/Clear Pending Bit 658" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND657 ,Set/Clear Pending Bit 657" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656 ,Set/Clear Pending Bit 656" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND655 ,Set/Clear Pending Bit 655" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND654 ,Set/Clear Pending Bit 654" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653 ,Set/Clear Pending Bit 653" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND652 ,Set/Clear Pending Bit 652" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND651 ,Set/Clear Pending Bit 651" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650 ,Set/Clear Pending Bit 650" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND649 ,Set/Clear Pending Bit 649" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND648 ,Set/Clear Pending Bit 648" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647 ,Set/Clear Pending Bit 647" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND646 ,Set/Clear Pending Bit 646" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND645 ,Set/Clear Pending Bit 645" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644 ,Set/Clear Pending Bit 644" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND643 ,Set/Clear Pending Bit 643" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND642 ,Set/Clear Pending Bit 642" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641 ,Set/Clear Pending Bit 641" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND640 ,Set/Clear Pending Bit 640" "Not pending,Pending" else rgroup.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703 ,Set/Clear Pending Bit 703" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND702 ,Set/Clear Pending Bit 702" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND701 ,Set/Clear Pending Bit 701" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700 ,Set/Clear Pending Bit 700" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND699 ,Set/Clear Pending Bit 699" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND698 ,Set/Clear Pending Bit 698" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697 ,Set/Clear Pending Bit 697" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND696 ,Set/Clear Pending Bit 696" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND695 ,Set/Clear Pending Bit 695" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694 ,Set/Clear Pending Bit 694" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND693 ,Set/Clear Pending Bit 693" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND692 ,Set/Clear Pending Bit 692" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691 ,Set/Clear Pending Bit 691" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND690 ,Set/Clear Pending Bit 690" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND689 ,Set/Clear Pending Bit 689" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688 ,Set/Clear Pending Bit 688" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND687 ,Set/Clear Pending Bit 687" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND686 ,Set/Clear Pending Bit 686" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685 ,Set/Clear Pending Bit 685" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND684 ,Set/Clear Pending Bit 684" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND683 ,Set/Clear Pending Bit 683" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682 ,Set/Clear Pending Bit 682" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND681 ,Set/Clear Pending Bit 681" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND680 ,Set/Clear Pending Bit 680" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679 ,Set/Clear Pending Bit 679" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND678 ,Set/Clear Pending Bit 678" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND677 ,Set/Clear Pending Bit 677" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676 ,Set/Clear Pending Bit 676" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND675 ,Set/Clear Pending Bit 675" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND674 ,Set/Clear Pending Bit 674" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673 ,Set/Clear Pending Bit 673" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND672 ,Set/Clear Pending Bit 672" "Not pending,Pending" else rgroup.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735 ,Set/Clear Pending Bit 735" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND734 ,Set/Clear Pending Bit 734" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND733 ,Set/Clear Pending Bit 733" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732 ,Set/Clear Pending Bit 732" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND731 ,Set/Clear Pending Bit 731" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND730 ,Set/Clear Pending Bit 730" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729 ,Set/Clear Pending Bit 729" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND728 ,Set/Clear Pending Bit 728" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND727 ,Set/Clear Pending Bit 727" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726 ,Set/Clear Pending Bit 726" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND725 ,Set/Clear Pending Bit 725" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND724 ,Set/Clear Pending Bit 724" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723 ,Set/Clear Pending Bit 723" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND722 ,Set/Clear Pending Bit 722" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND721 ,Set/Clear Pending Bit 721" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720 ,Set/Clear Pending Bit 720" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND719 ,Set/Clear Pending Bit 719" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND718 ,Set/Clear Pending Bit 718" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717 ,Set/Clear Pending Bit 717" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND716 ,Set/Clear Pending Bit 716" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND715 ,Set/Clear Pending Bit 715" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714 ,Set/Clear Pending Bit 714" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND713 ,Set/Clear Pending Bit 713" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND712 ,Set/Clear Pending Bit 712" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711 ,Set/Clear Pending Bit 711" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND710 ,Set/Clear Pending Bit 710" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND709 ,Set/Clear Pending Bit 709" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708 ,Set/Clear Pending Bit 708" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND707 ,Set/Clear Pending Bit 707" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND706 ,Set/Clear Pending Bit 706" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705 ,Set/Clear Pending Bit 705" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND704 ,Set/Clear Pending Bit 704" "Not pending,Pending" else rgroup.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767 ,Set/Clear Pending Bit 767" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND766 ,Set/Clear Pending Bit 766" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND765 ,Set/Clear Pending Bit 765" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764 ,Set/Clear Pending Bit 764" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND763 ,Set/Clear Pending Bit 763" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND762 ,Set/Clear Pending Bit 762" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761 ,Set/Clear Pending Bit 761" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND760 ,Set/Clear Pending Bit 760" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND759 ,Set/Clear Pending Bit 759" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758 ,Set/Clear Pending Bit 758" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND757 ,Set/Clear Pending Bit 757" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND756 ,Set/Clear Pending Bit 756" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755 ,Set/Clear Pending Bit 755" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND754 ,Set/Clear Pending Bit 754" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND753 ,Set/Clear Pending Bit 753" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752 ,Set/Clear Pending Bit 752" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND751 ,Set/Clear Pending Bit 751" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND750 ,Set/Clear Pending Bit 750" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749 ,Set/Clear Pending Bit 749" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND748 ,Set/Clear Pending Bit 748" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND747 ,Set/Clear Pending Bit 747" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746 ,Set/Clear Pending Bit 746" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND745 ,Set/Clear Pending Bit 745" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND744 ,Set/Clear Pending Bit 744" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743 ,Set/Clear Pending Bit 743" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND742 ,Set/Clear Pending Bit 742" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND741 ,Set/Clear Pending Bit 741" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740 ,Set/Clear Pending Bit 740" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND739 ,Set/Clear Pending Bit 739" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND738 ,Set/Clear Pending Bit 738" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737 ,Set/Clear Pending Bit 737" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND736 ,Set/Clear Pending Bit 736" "Not pending,Pending" else rgroup.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799 ,Set/Clear Pending Bit 799" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND798 ,Set/Clear Pending Bit 798" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND797 ,Set/Clear Pending Bit 797" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796 ,Set/Clear Pending Bit 796" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND795 ,Set/Clear Pending Bit 795" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND794 ,Set/Clear Pending Bit 794" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793 ,Set/Clear Pending Bit 793" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND792 ,Set/Clear Pending Bit 792" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND791 ,Set/Clear Pending Bit 791" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790 ,Set/Clear Pending Bit 790" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND789 ,Set/Clear Pending Bit 789" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND788 ,Set/Clear Pending Bit 788" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787 ,Set/Clear Pending Bit 787" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND786 ,Set/Clear Pending Bit 786" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND785 ,Set/Clear Pending Bit 785" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784 ,Set/Clear Pending Bit 784" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND783 ,Set/Clear Pending Bit 783" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND782 ,Set/Clear Pending Bit 782" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781 ,Set/Clear Pending Bit 781" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND780 ,Set/Clear Pending Bit 780" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND779 ,Set/Clear Pending Bit 779" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778 ,Set/Clear Pending Bit 778" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND777 ,Set/Clear Pending Bit 777" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND776 ,Set/Clear Pending Bit 776" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775 ,Set/Clear Pending Bit 775" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND774 ,Set/Clear Pending Bit 774" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND773 ,Set/Clear Pending Bit 773" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772 ,Set/Clear Pending Bit 772" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND771 ,Set/Clear Pending Bit 771" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND770 ,Set/Clear Pending Bit 770" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769 ,Set/Clear Pending Bit 769" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND768 ,Set/Clear Pending Bit 768" "Not pending,Pending" else rgroup.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831 ,Set/Clear Pending Bit 831" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND830 ,Set/Clear Pending Bit 830" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND829 ,Set/Clear Pending Bit 829" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828 ,Set/Clear Pending Bit 828" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND827 ,Set/Clear Pending Bit 827" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND826 ,Set/Clear Pending Bit 826" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825 ,Set/Clear Pending Bit 825" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND824 ,Set/Clear Pending Bit 824" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND823 ,Set/Clear Pending Bit 823" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822 ,Set/Clear Pending Bit 822" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND821 ,Set/Clear Pending Bit 821" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND820 ,Set/Clear Pending Bit 820" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819 ,Set/Clear Pending Bit 819" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND818 ,Set/Clear Pending Bit 818" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND817 ,Set/Clear Pending Bit 817" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816 ,Set/Clear Pending Bit 816" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND815 ,Set/Clear Pending Bit 815" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND814 ,Set/Clear Pending Bit 814" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813 ,Set/Clear Pending Bit 813" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND812 ,Set/Clear Pending Bit 812" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND811 ,Set/Clear Pending Bit 811" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810 ,Set/Clear Pending Bit 810" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND809 ,Set/Clear Pending Bit 809" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND808 ,Set/Clear Pending Bit 808" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807 ,Set/Clear Pending Bit 807" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND806 ,Set/Clear Pending Bit 806" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND805 ,Set/Clear Pending Bit 805" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804 ,Set/Clear Pending Bit 804" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND803 ,Set/Clear Pending Bit 803" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND802 ,Set/Clear Pending Bit 802" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801 ,Set/Clear Pending Bit 801" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND800 ,Set/Clear Pending Bit 800" "Not pending,Pending" else rgroup.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863 ,Set/Clear Pending Bit 863" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND862 ,Set/Clear Pending Bit 862" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND861 ,Set/Clear Pending Bit 861" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860 ,Set/Clear Pending Bit 860" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND859 ,Set/Clear Pending Bit 859" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND858 ,Set/Clear Pending Bit 858" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857 ,Set/Clear Pending Bit 857" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND856 ,Set/Clear Pending Bit 856" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND855 ,Set/Clear Pending Bit 855" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854 ,Set/Clear Pending Bit 854" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND853 ,Set/Clear Pending Bit 853" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND852 ,Set/Clear Pending Bit 852" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851 ,Set/Clear Pending Bit 851" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND850 ,Set/Clear Pending Bit 850" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND849 ,Set/Clear Pending Bit 849" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848 ,Set/Clear Pending Bit 848" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND847 ,Set/Clear Pending Bit 847" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND846 ,Set/Clear Pending Bit 846" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845 ,Set/Clear Pending Bit 845" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND844 ,Set/Clear Pending Bit 844" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND843 ,Set/Clear Pending Bit 843" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842 ,Set/Clear Pending Bit 842" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND841 ,Set/Clear Pending Bit 841" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND840 ,Set/Clear Pending Bit 840" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839 ,Set/Clear Pending Bit 839" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND838 ,Set/Clear Pending Bit 838" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND837 ,Set/Clear Pending Bit 837" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836 ,Set/Clear Pending Bit 836" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND835 ,Set/Clear Pending Bit 835" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND834 ,Set/Clear Pending Bit 834" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833 ,Set/Clear Pending Bit 833" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND832 ,Set/Clear Pending Bit 832" "Not pending,Pending" else rgroup.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895 ,Set/Clear Pending Bit 895" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND894 ,Set/Clear Pending Bit 894" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND893 ,Set/Clear Pending Bit 893" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892 ,Set/Clear Pending Bit 892" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND891 ,Set/Clear Pending Bit 891" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND890 ,Set/Clear Pending Bit 890" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889 ,Set/Clear Pending Bit 889" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND888 ,Set/Clear Pending Bit 888" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND887 ,Set/Clear Pending Bit 887" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886 ,Set/Clear Pending Bit 886" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND885 ,Set/Clear Pending Bit 885" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND884 ,Set/Clear Pending Bit 884" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883 ,Set/Clear Pending Bit 883" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND882 ,Set/Clear Pending Bit 882" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND881 ,Set/Clear Pending Bit 881" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880 ,Set/Clear Pending Bit 880" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND879 ,Set/Clear Pending Bit 879" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND878 ,Set/Clear Pending Bit 878" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877 ,Set/Clear Pending Bit 877" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND876 ,Set/Clear Pending Bit 876" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND875 ,Set/Clear Pending Bit 875" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874 ,Set/Clear Pending Bit 874" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND873 ,Set/Clear Pending Bit 873" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND872 ,Set/Clear Pending Bit 872" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871 ,Set/Clear Pending Bit 871" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND870 ,Set/Clear Pending Bit 870" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND869 ,Set/Clear Pending Bit 869" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868 ,Set/Clear Pending Bit 868" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND867 ,Set/Clear Pending Bit 867" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND866 ,Set/Clear Pending Bit 866" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865 ,Set/Clear Pending Bit 865" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND864 ,Set/Clear Pending Bit 864" "Not pending,Pending" else rgroup.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927 ,Set/Clear Pending Bit 927" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND926 ,Set/Clear Pending Bit 926" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND925 ,Set/Clear Pending Bit 925" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924 ,Set/Clear Pending Bit 924" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND923 ,Set/Clear Pending Bit 923" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND922 ,Set/Clear Pending Bit 922" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921 ,Set/Clear Pending Bit 921" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND920 ,Set/Clear Pending Bit 920" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND919 ,Set/Clear Pending Bit 919" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918 ,Set/Clear Pending Bit 918" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND917 ,Set/Clear Pending Bit 917" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND916 ,Set/Clear Pending Bit 916" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915 ,Set/Clear Pending Bit 915" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND914 ,Set/Clear Pending Bit 914" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND913 ,Set/Clear Pending Bit 913" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912 ,Set/Clear Pending Bit 912" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND911 ,Set/Clear Pending Bit 911" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND910 ,Set/Clear Pending Bit 910" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909 ,Set/Clear Pending Bit 909" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND908 ,Set/Clear Pending Bit 908" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND907 ,Set/Clear Pending Bit 907" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906 ,Set/Clear Pending Bit 906" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND905 ,Set/Clear Pending Bit 905" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND904 ,Set/Clear Pending Bit 904" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903 ,Set/Clear Pending Bit 903" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND902 ,Set/Clear Pending Bit 902" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND901 ,Set/Clear Pending Bit 901" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900 ,Set/Clear Pending Bit 900" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND899 ,Set/Clear Pending Bit 899" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND898 ,Set/Clear Pending Bit 898" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897 ,Set/Clear Pending Bit 897" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND896 ,Set/Clear Pending Bit 896" "Not pending,Pending" else rgroup.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959 ,Set/Clear Pending Bit 959" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND958 ,Set/Clear Pending Bit 958" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND957 ,Set/Clear Pending Bit 957" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956 ,Set/Clear Pending Bit 956" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND955 ,Set/Clear Pending Bit 955" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND954 ,Set/Clear Pending Bit 954" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953 ,Set/Clear Pending Bit 953" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND952 ,Set/Clear Pending Bit 952" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND951 ,Set/Clear Pending Bit 951" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950 ,Set/Clear Pending Bit 950" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND949 ,Set/Clear Pending Bit 949" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND948 ,Set/Clear Pending Bit 948" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947 ,Set/Clear Pending Bit 947" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND946 ,Set/Clear Pending Bit 946" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND945 ,Set/Clear Pending Bit 945" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944 ,Set/Clear Pending Bit 944" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND943 ,Set/Clear Pending Bit 943" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND942 ,Set/Clear Pending Bit 942" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941 ,Set/Clear Pending Bit 941" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND940 ,Set/Clear Pending Bit 940" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND939 ,Set/Clear Pending Bit 939" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938 ,Set/Clear Pending Bit 938" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND937 ,Set/Clear Pending Bit 937" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND936 ,Set/Clear Pending Bit 936" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935 ,Set/Clear Pending Bit 935" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND934 ,Set/Clear Pending Bit 934" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND933 ,Set/Clear Pending Bit 933" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932 ,Set/Clear Pending Bit 932" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND931 ,Set/Clear Pending Bit 931" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND930 ,Set/Clear Pending Bit 930" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929 ,Set/Clear Pending Bit 929" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND928 ,Set/Clear Pending Bit 928" "Not pending,Pending" else rgroup.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991 ,Set/Clear Pending Bit 991" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND990 ,Set/Clear Pending Bit 990" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND989 ,Set/Clear Pending Bit 989" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988 ,Set/Clear Pending Bit 988" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND987 ,Set/Clear Pending Bit 987" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND986 ,Set/Clear Pending Bit 986" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985 ,Set/Clear Pending Bit 985" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND984 ,Set/Clear Pending Bit 984" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND983 ,Set/Clear Pending Bit 983" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982 ,Set/Clear Pending Bit 982" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND981 ,Set/Clear Pending Bit 981" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND980 ,Set/Clear Pending Bit 980" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979 ,Set/Clear Pending Bit 979" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND978 ,Set/Clear Pending Bit 978" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND977 ,Set/Clear Pending Bit 977" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976 ,Set/Clear Pending Bit 976" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND975 ,Set/Clear Pending Bit 975" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND974 ,Set/Clear Pending Bit 974" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973 ,Set/Clear Pending Bit 973" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND972 ,Set/Clear Pending Bit 972" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND971 ,Set/Clear Pending Bit 971" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970 ,Set/Clear Pending Bit 970" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND969 ,Set/Clear Pending Bit 969" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND968 ,Set/Clear Pending Bit 968" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967 ,Set/Clear Pending Bit 967" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND966 ,Set/Clear Pending Bit 966" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND965 ,Set/Clear Pending Bit 965" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964 ,Set/Clear Pending Bit 964" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND963 ,Set/Clear Pending Bit 963" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND962 ,Set/Clear Pending Bit 962" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961 ,Set/Clear Pending Bit 961" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND960 ,Set/Clear Pending Bit 960" "Not pending,Pending" else rgroup.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" endif tree.end width 24. tree "Set/Clear Active Registers" rgroup.long 0x0300++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63 ,Set/Clear Active Bit 63" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE62 ,Set/Clear Active Bit 62" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE61 ,Set/Clear Active Bit 61" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60 ,Set/Clear Active Bit 60" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE59 ,Set/Clear Active Bit 59" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE58 ,Set/Clear Active Bit 58" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57 ,Set/Clear Active Bit 57" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE56 ,Set/Clear Active Bit 56" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE55 ,Set/Clear Active Bit 55" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54 ,Set/Clear Active Bit 54" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE53 ,Set/Clear Active Bit 53" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE52 ,Set/Clear Active Bit 52" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51 ,Set/Clear Active Bit 51" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE50 ,Set/Clear Active Bit 50" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE49 ,Set/Clear Active Bit 49" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48 ,Set/Clear Active Bit 48" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE47 ,Set/Clear Active Bit 47" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE46 ,Set/Clear Active Bit 46" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45 ,Set/Clear Active Bit 45" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE44 ,Set/Clear Active Bit 44" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE43 ,Set/Clear Active Bit 43" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42 ,Set/Clear Active Bit 42" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE41 ,Set/Clear Active Bit 41" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE40 ,Set/Clear Active Bit 40" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39 ,Set/Clear Active Bit 39" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE38 ,Set/Clear Active Bit 38" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE37 ,Set/Clear Active Bit 37" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36 ,Set/Clear Active Bit 36" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE35 ,Set/Clear Active Bit 35" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE34 ,Set/Clear Active Bit 34" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33 ,Set/Clear Active Bit 33" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE32 ,Set/Clear Active Bit 32" "Not active,Active" else rgroup.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95 ,Set/Clear Active Bit 95" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE94 ,Set/Clear Active Bit 94" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE93 ,Set/Clear Active Bit 93" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92 ,Set/Clear Active Bit 92" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE91 ,Set/Clear Active Bit 91" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE90 ,Set/Clear Active Bit 90" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89 ,Set/Clear Active Bit 89" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE88 ,Set/Clear Active Bit 88" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE87 ,Set/Clear Active Bit 87" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86 ,Set/Clear Active Bit 86" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE85 ,Set/Clear Active Bit 85" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE84 ,Set/Clear Active Bit 84" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83 ,Set/Clear Active Bit 83" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE82 ,Set/Clear Active Bit 82" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE81 ,Set/Clear Active Bit 81" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80 ,Set/Clear Active Bit 80" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE79 ,Set/Clear Active Bit 79" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE78 ,Set/Clear Active Bit 78" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77 ,Set/Clear Active Bit 77" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE76 ,Set/Clear Active Bit 76" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE75 ,Set/Clear Active Bit 75" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74 ,Set/Clear Active Bit 74" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE73 ,Set/Clear Active Bit 73" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE72 ,Set/Clear Active Bit 72" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71 ,Set/Clear Active Bit 71" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE70 ,Set/Clear Active Bit 70" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE69 ,Set/Clear Active Bit 69" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68 ,Set/Clear Active Bit 68" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE67 ,Set/Clear Active Bit 67" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE66 ,Set/Clear Active Bit 66" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65 ,Set/Clear Active Bit 65" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE64 ,Set/Clear Active Bit 64" "Not active,Active" else rgroup.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE99 ,Set/Clear Active Bit 99" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE98 ,Set/Clear Active Bit 98" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97 ,Set/Clear Active Bit 97" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE96 ,Set/Clear Active Bit 96" "Not active,Active" else rgroup.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active" else rgroup.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active" else rgroup.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active" else rgroup.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active" else rgroup.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active" else rgroup.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active" else rgroup.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active" else rgroup.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active" else rgroup.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active" else rgroup.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active" else rgroup.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active" else rgroup.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active" else rgroup.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0340++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE543 ,Set/Clear Active Bit 543" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE542 ,Set/Clear Active Bit 542" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE541 ,Set/Clear Active Bit 541" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE540 ,Set/Clear Active Bit 540" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE539 ,Set/Clear Active Bit 539" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE538 ,Set/Clear Active Bit 538" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE537 ,Set/Clear Active Bit 537" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE536 ,Set/Clear Active Bit 536" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE535 ,Set/Clear Active Bit 535" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE534 ,Set/Clear Active Bit 534" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE533 ,Set/Clear Active Bit 533" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE532 ,Set/Clear Active Bit 532" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE531 ,Set/Clear Active Bit 531" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE530 ,Set/Clear Active Bit 530" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE529 ,Set/Clear Active Bit 529" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE528 ,Set/Clear Active Bit 528" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE527 ,Set/Clear Active Bit 527" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE526 ,Set/Clear Active Bit 526" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE525 ,Set/Clear Active Bit 525" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE524 ,Set/Clear Active Bit 524" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE523 ,Set/Clear Active Bit 523" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE522 ,Set/Clear Active Bit 522" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE521 ,Set/Clear Active Bit 521" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE520 ,Set/Clear Active Bit 520" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE519 ,Set/Clear Active Bit 519" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE518 ,Set/Clear Active Bit 518" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE517 ,Set/Clear Active Bit 517" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE516 ,Set/Clear Active Bit 516" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE515 ,Set/Clear Active Bit 515" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE514 ,Set/Clear Active Bit 514" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE513 ,Set/Clear Active Bit 513" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE512 ,Set/Clear Active Bit 512" "Not active,Active" else rgroup.long 0x0340++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0344++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE575 ,Set/Clear Active Bit 575" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE574 ,Set/Clear Active Bit 574" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE573 ,Set/Clear Active Bit 573" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE572 ,Set/Clear Active Bit 572" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE571 ,Set/Clear Active Bit 571" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE570 ,Set/Clear Active Bit 570" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE569 ,Set/Clear Active Bit 569" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE568 ,Set/Clear Active Bit 568" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE567 ,Set/Clear Active Bit 567" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE566 ,Set/Clear Active Bit 566" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE565 ,Set/Clear Active Bit 565" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE564 ,Set/Clear Active Bit 564" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE563 ,Set/Clear Active Bit 563" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE562 ,Set/Clear Active Bit 562" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE561 ,Set/Clear Active Bit 561" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE560 ,Set/Clear Active Bit 560" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE559 ,Set/Clear Active Bit 559" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE558 ,Set/Clear Active Bit 558" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE557 ,Set/Clear Active Bit 557" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE556 ,Set/Clear Active Bit 556" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE555 ,Set/Clear Active Bit 555" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE554 ,Set/Clear Active Bit 554" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE553 ,Set/Clear Active Bit 553" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE552 ,Set/Clear Active Bit 552" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE551 ,Set/Clear Active Bit 551" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE550 ,Set/Clear Active Bit 550" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE549 ,Set/Clear Active Bit 549" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE548 ,Set/Clear Active Bit 548" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE547 ,Set/Clear Active Bit 547" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE546 ,Set/Clear Active Bit 546" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE545 ,Set/Clear Active Bit 545" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE544 ,Set/Clear Active Bit 544" "Not active,Active" else rgroup.long 0x0344++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0348++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE607 ,Set/Clear Active Bit 607" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE606 ,Set/Clear Active Bit 606" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE605 ,Set/Clear Active Bit 605" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE604 ,Set/Clear Active Bit 604" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE603 ,Set/Clear Active Bit 603" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE602 ,Set/Clear Active Bit 602" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE601 ,Set/Clear Active Bit 601" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE600 ,Set/Clear Active Bit 600" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE599 ,Set/Clear Active Bit 599" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE598 ,Set/Clear Active Bit 598" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE597 ,Set/Clear Active Bit 597" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE596 ,Set/Clear Active Bit 596" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE595 ,Set/Clear Active Bit 595" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE594 ,Set/Clear Active Bit 594" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE593 ,Set/Clear Active Bit 593" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE592 ,Set/Clear Active Bit 592" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE591 ,Set/Clear Active Bit 591" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE590 ,Set/Clear Active Bit 590" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE589 ,Set/Clear Active Bit 589" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE588 ,Set/Clear Active Bit 588" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE587 ,Set/Clear Active Bit 587" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE586 ,Set/Clear Active Bit 586" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE585 ,Set/Clear Active Bit 585" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE584 ,Set/Clear Active Bit 584" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE583 ,Set/Clear Active Bit 583" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE582 ,Set/Clear Active Bit 582" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE581 ,Set/Clear Active Bit 581" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE580 ,Set/Clear Active Bit 580" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE579 ,Set/Clear Active Bit 579" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE578 ,Set/Clear Active Bit 578" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE577 ,Set/Clear Active Bit 577" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE576 ,Set/Clear Active Bit 576" "Not active,Active" else rgroup.long 0x0348++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x034C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE639 ,Set/Clear Active Bit 639" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE638 ,Set/Clear Active Bit 638" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE637 ,Set/Clear Active Bit 637" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE636 ,Set/Clear Active Bit 636" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE635 ,Set/Clear Active Bit 635" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE634 ,Set/Clear Active Bit 634" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE633 ,Set/Clear Active Bit 633" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE632 ,Set/Clear Active Bit 632" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE631 ,Set/Clear Active Bit 631" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE630 ,Set/Clear Active Bit 630" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE629 ,Set/Clear Active Bit 629" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE628 ,Set/Clear Active Bit 628" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE627 ,Set/Clear Active Bit 627" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE626 ,Set/Clear Active Bit 626" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE625 ,Set/Clear Active Bit 625" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE624 ,Set/Clear Active Bit 624" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE623 ,Set/Clear Active Bit 623" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE622 ,Set/Clear Active Bit 622" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE621 ,Set/Clear Active Bit 621" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE620 ,Set/Clear Active Bit 620" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE619 ,Set/Clear Active Bit 619" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE618 ,Set/Clear Active Bit 618" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE617 ,Set/Clear Active Bit 617" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE616 ,Set/Clear Active Bit 616" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE615 ,Set/Clear Active Bit 615" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE614 ,Set/Clear Active Bit 614" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE613 ,Set/Clear Active Bit 613" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE612 ,Set/Clear Active Bit 612" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE611 ,Set/Clear Active Bit 611" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE610 ,Set/Clear Active Bit 610" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE609 ,Set/Clear Active Bit 609" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE608 ,Set/Clear Active Bit 608" "Not active,Active" else rgroup.long 0x034C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0350++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE671 ,Set/Clear Active Bit 671" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE670 ,Set/Clear Active Bit 670" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE669 ,Set/Clear Active Bit 669" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE668 ,Set/Clear Active Bit 668" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE667 ,Set/Clear Active Bit 667" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE666 ,Set/Clear Active Bit 666" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE665 ,Set/Clear Active Bit 665" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE664 ,Set/Clear Active Bit 664" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE663 ,Set/Clear Active Bit 663" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE662 ,Set/Clear Active Bit 662" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE661 ,Set/Clear Active Bit 661" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE660 ,Set/Clear Active Bit 660" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE659 ,Set/Clear Active Bit 659" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE658 ,Set/Clear Active Bit 658" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE657 ,Set/Clear Active Bit 657" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE656 ,Set/Clear Active Bit 656" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE655 ,Set/Clear Active Bit 655" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE654 ,Set/Clear Active Bit 654" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE653 ,Set/Clear Active Bit 653" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE652 ,Set/Clear Active Bit 652" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE651 ,Set/Clear Active Bit 651" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE650 ,Set/Clear Active Bit 650" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE649 ,Set/Clear Active Bit 649" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE648 ,Set/Clear Active Bit 648" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE647 ,Set/Clear Active Bit 647" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE646 ,Set/Clear Active Bit 646" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE645 ,Set/Clear Active Bit 645" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE644 ,Set/Clear Active Bit 644" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE643 ,Set/Clear Active Bit 643" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE642 ,Set/Clear Active Bit 642" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE641 ,Set/Clear Active Bit 641" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE640 ,Set/Clear Active Bit 640" "Not active,Active" else rgroup.long 0x0350++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0354++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE703 ,Set/Clear Active Bit 703" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE702 ,Set/Clear Active Bit 702" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE701 ,Set/Clear Active Bit 701" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE700 ,Set/Clear Active Bit 700" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE699 ,Set/Clear Active Bit 699" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE698 ,Set/Clear Active Bit 698" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE697 ,Set/Clear Active Bit 697" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE696 ,Set/Clear Active Bit 696" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE695 ,Set/Clear Active Bit 695" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE694 ,Set/Clear Active Bit 694" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE693 ,Set/Clear Active Bit 693" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE692 ,Set/Clear Active Bit 692" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE691 ,Set/Clear Active Bit 691" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE690 ,Set/Clear Active Bit 690" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE689 ,Set/Clear Active Bit 689" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE688 ,Set/Clear Active Bit 688" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE687 ,Set/Clear Active Bit 687" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE686 ,Set/Clear Active Bit 686" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE685 ,Set/Clear Active Bit 685" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE684 ,Set/Clear Active Bit 684" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE683 ,Set/Clear Active Bit 683" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE682 ,Set/Clear Active Bit 682" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE681 ,Set/Clear Active Bit 681" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE680 ,Set/Clear Active Bit 680" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE679 ,Set/Clear Active Bit 679" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE678 ,Set/Clear Active Bit 678" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE677 ,Set/Clear Active Bit 677" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE676 ,Set/Clear Active Bit 676" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE675 ,Set/Clear Active Bit 675" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE674 ,Set/Clear Active Bit 674" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE673 ,Set/Clear Active Bit 673" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE672 ,Set/Clear Active Bit 672" "Not active,Active" else rgroup.long 0x0354++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0358++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE735 ,Set/Clear Active Bit 735" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE734 ,Set/Clear Active Bit 734" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE733 ,Set/Clear Active Bit 733" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE732 ,Set/Clear Active Bit 732" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE731 ,Set/Clear Active Bit 731" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE730 ,Set/Clear Active Bit 730" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE729 ,Set/Clear Active Bit 729" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE728 ,Set/Clear Active Bit 728" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE727 ,Set/Clear Active Bit 727" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE726 ,Set/Clear Active Bit 726" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE725 ,Set/Clear Active Bit 725" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE724 ,Set/Clear Active Bit 724" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE723 ,Set/Clear Active Bit 723" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE722 ,Set/Clear Active Bit 722" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE721 ,Set/Clear Active Bit 721" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE720 ,Set/Clear Active Bit 720" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE719 ,Set/Clear Active Bit 719" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE718 ,Set/Clear Active Bit 718" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE717 ,Set/Clear Active Bit 717" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE716 ,Set/Clear Active Bit 716" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE715 ,Set/Clear Active Bit 715" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE714 ,Set/Clear Active Bit 714" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE713 ,Set/Clear Active Bit 713" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE712 ,Set/Clear Active Bit 712" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE711 ,Set/Clear Active Bit 711" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE710 ,Set/Clear Active Bit 710" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE709 ,Set/Clear Active Bit 709" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE708 ,Set/Clear Active Bit 708" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE707 ,Set/Clear Active Bit 707" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE706 ,Set/Clear Active Bit 706" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE705 ,Set/Clear Active Bit 705" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE704 ,Set/Clear Active Bit 704" "Not active,Active" else rgroup.long 0x0358++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x035C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE767 ,Set/Clear Active Bit 767" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE766 ,Set/Clear Active Bit 766" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE765 ,Set/Clear Active Bit 765" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE764 ,Set/Clear Active Bit 764" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE763 ,Set/Clear Active Bit 763" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE762 ,Set/Clear Active Bit 762" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE761 ,Set/Clear Active Bit 761" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE760 ,Set/Clear Active Bit 760" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE759 ,Set/Clear Active Bit 759" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE758 ,Set/Clear Active Bit 758" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE757 ,Set/Clear Active Bit 757" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE756 ,Set/Clear Active Bit 756" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE755 ,Set/Clear Active Bit 755" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE754 ,Set/Clear Active Bit 754" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE753 ,Set/Clear Active Bit 753" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE752 ,Set/Clear Active Bit 752" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE751 ,Set/Clear Active Bit 751" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE750 ,Set/Clear Active Bit 750" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE749 ,Set/Clear Active Bit 749" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE748 ,Set/Clear Active Bit 748" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE747 ,Set/Clear Active Bit 747" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE746 ,Set/Clear Active Bit 746" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE745 ,Set/Clear Active Bit 745" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE744 ,Set/Clear Active Bit 744" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE743 ,Set/Clear Active Bit 743" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE742 ,Set/Clear Active Bit 742" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE741 ,Set/Clear Active Bit 741" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE740 ,Set/Clear Active Bit 740" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE739 ,Set/Clear Active Bit 739" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE738 ,Set/Clear Active Bit 738" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE737 ,Set/Clear Active Bit 737" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE736 ,Set/Clear Active Bit 736" "Not active,Active" else rgroup.long 0x035C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0360++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE799 ,Set/Clear Active Bit 799" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE798 ,Set/Clear Active Bit 798" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE797 ,Set/Clear Active Bit 797" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE796 ,Set/Clear Active Bit 796" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE795 ,Set/Clear Active Bit 795" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE794 ,Set/Clear Active Bit 794" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE793 ,Set/Clear Active Bit 793" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE792 ,Set/Clear Active Bit 792" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE791 ,Set/Clear Active Bit 791" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE790 ,Set/Clear Active Bit 790" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE789 ,Set/Clear Active Bit 789" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE788 ,Set/Clear Active Bit 788" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE787 ,Set/Clear Active Bit 787" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE786 ,Set/Clear Active Bit 786" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE785 ,Set/Clear Active Bit 785" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE784 ,Set/Clear Active Bit 784" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE783 ,Set/Clear Active Bit 783" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE782 ,Set/Clear Active Bit 782" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE781 ,Set/Clear Active Bit 781" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE780 ,Set/Clear Active Bit 780" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE779 ,Set/Clear Active Bit 779" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE778 ,Set/Clear Active Bit 778" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE777 ,Set/Clear Active Bit 777" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE776 ,Set/Clear Active Bit 776" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE775 ,Set/Clear Active Bit 775" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE774 ,Set/Clear Active Bit 774" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE773 ,Set/Clear Active Bit 773" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE772 ,Set/Clear Active Bit 772" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE771 ,Set/Clear Active Bit 771" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE770 ,Set/Clear Active Bit 770" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE769 ,Set/Clear Active Bit 769" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE768 ,Set/Clear Active Bit 768" "Not active,Active" else rgroup.long 0x0360++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0364++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE831 ,Set/Clear Active Bit 831" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE830 ,Set/Clear Active Bit 830" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE829 ,Set/Clear Active Bit 829" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE828 ,Set/Clear Active Bit 828" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE827 ,Set/Clear Active Bit 827" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE826 ,Set/Clear Active Bit 826" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE825 ,Set/Clear Active Bit 825" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE824 ,Set/Clear Active Bit 824" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE823 ,Set/Clear Active Bit 823" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE822 ,Set/Clear Active Bit 822" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE821 ,Set/Clear Active Bit 821" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE820 ,Set/Clear Active Bit 820" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE819 ,Set/Clear Active Bit 819" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE818 ,Set/Clear Active Bit 818" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE817 ,Set/Clear Active Bit 817" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE816 ,Set/Clear Active Bit 816" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE815 ,Set/Clear Active Bit 815" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE814 ,Set/Clear Active Bit 814" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE813 ,Set/Clear Active Bit 813" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE812 ,Set/Clear Active Bit 812" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE811 ,Set/Clear Active Bit 811" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE810 ,Set/Clear Active Bit 810" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE809 ,Set/Clear Active Bit 809" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE808 ,Set/Clear Active Bit 808" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE807 ,Set/Clear Active Bit 807" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE806 ,Set/Clear Active Bit 806" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE805 ,Set/Clear Active Bit 805" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE804 ,Set/Clear Active Bit 804" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE803 ,Set/Clear Active Bit 803" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE802 ,Set/Clear Active Bit 802" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE801 ,Set/Clear Active Bit 801" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE800 ,Set/Clear Active Bit 800" "Not active,Active" else rgroup.long 0x0364++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0368++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE863 ,Set/Clear Active Bit 863" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE862 ,Set/Clear Active Bit 862" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE861 ,Set/Clear Active Bit 861" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE860 ,Set/Clear Active Bit 860" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE859 ,Set/Clear Active Bit 859" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE858 ,Set/Clear Active Bit 858" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE857 ,Set/Clear Active Bit 857" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE856 ,Set/Clear Active Bit 856" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE855 ,Set/Clear Active Bit 855" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE854 ,Set/Clear Active Bit 854" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE853 ,Set/Clear Active Bit 853" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE852 ,Set/Clear Active Bit 852" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE851 ,Set/Clear Active Bit 851" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE850 ,Set/Clear Active Bit 850" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE849 ,Set/Clear Active Bit 849" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE848 ,Set/Clear Active Bit 848" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE847 ,Set/Clear Active Bit 847" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE846 ,Set/Clear Active Bit 846" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE845 ,Set/Clear Active Bit 845" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE844 ,Set/Clear Active Bit 844" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE843 ,Set/Clear Active Bit 843" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE842 ,Set/Clear Active Bit 842" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE841 ,Set/Clear Active Bit 841" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE840 ,Set/Clear Active Bit 840" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE839 ,Set/Clear Active Bit 839" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE838 ,Set/Clear Active Bit 838" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE837 ,Set/Clear Active Bit 837" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE836 ,Set/Clear Active Bit 836" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE835 ,Set/Clear Active Bit 835" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE834 ,Set/Clear Active Bit 834" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE833 ,Set/Clear Active Bit 833" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE832 ,Set/Clear Active Bit 832" "Not active,Active" else rgroup.long 0x0368++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x036C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE895 ,Set/Clear Active Bit 895" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE894 ,Set/Clear Active Bit 894" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE893 ,Set/Clear Active Bit 893" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE892 ,Set/Clear Active Bit 892" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE891 ,Set/Clear Active Bit 891" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE890 ,Set/Clear Active Bit 890" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE889 ,Set/Clear Active Bit 889" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE888 ,Set/Clear Active Bit 888" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE887 ,Set/Clear Active Bit 887" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE886 ,Set/Clear Active Bit 886" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE885 ,Set/Clear Active Bit 885" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE884 ,Set/Clear Active Bit 884" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE883 ,Set/Clear Active Bit 883" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE882 ,Set/Clear Active Bit 882" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE881 ,Set/Clear Active Bit 881" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE880 ,Set/Clear Active Bit 880" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE879 ,Set/Clear Active Bit 879" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE878 ,Set/Clear Active Bit 878" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE877 ,Set/Clear Active Bit 877" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE876 ,Set/Clear Active Bit 876" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE875 ,Set/Clear Active Bit 875" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE874 ,Set/Clear Active Bit 874" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE873 ,Set/Clear Active Bit 873" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE872 ,Set/Clear Active Bit 872" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE871 ,Set/Clear Active Bit 871" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE870 ,Set/Clear Active Bit 870" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE869 ,Set/Clear Active Bit 869" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE868 ,Set/Clear Active Bit 868" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE867 ,Set/Clear Active Bit 867" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE866 ,Set/Clear Active Bit 866" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE865 ,Set/Clear Active Bit 865" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE864 ,Set/Clear Active Bit 864" "Not active,Active" else rgroup.long 0x036C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0370++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE927 ,Set/Clear Active Bit 927" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE926 ,Set/Clear Active Bit 926" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE925 ,Set/Clear Active Bit 925" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE924 ,Set/Clear Active Bit 924" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE923 ,Set/Clear Active Bit 923" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE922 ,Set/Clear Active Bit 922" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE921 ,Set/Clear Active Bit 921" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE920 ,Set/Clear Active Bit 920" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE919 ,Set/Clear Active Bit 919" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE918 ,Set/Clear Active Bit 918" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE917 ,Set/Clear Active Bit 917" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE916 ,Set/Clear Active Bit 916" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE915 ,Set/Clear Active Bit 915" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE914 ,Set/Clear Active Bit 914" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE913 ,Set/Clear Active Bit 913" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE912 ,Set/Clear Active Bit 912" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE911 ,Set/Clear Active Bit 911" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE910 ,Set/Clear Active Bit 910" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE909 ,Set/Clear Active Bit 909" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE908 ,Set/Clear Active Bit 908" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE907 ,Set/Clear Active Bit 907" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE906 ,Set/Clear Active Bit 906" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE905 ,Set/Clear Active Bit 905" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE904 ,Set/Clear Active Bit 904" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE903 ,Set/Clear Active Bit 903" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE902 ,Set/Clear Active Bit 902" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE901 ,Set/Clear Active Bit 901" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE900 ,Set/Clear Active Bit 900" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE899 ,Set/Clear Active Bit 899" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE898 ,Set/Clear Active Bit 898" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE897 ,Set/Clear Active Bit 897" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE896 ,Set/Clear Active Bit 896" "Not active,Active" else rgroup.long 0x0370++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0374++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE959 ,Set/Clear Active Bit 959" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE958 ,Set/Clear Active Bit 958" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE957 ,Set/Clear Active Bit 957" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE956 ,Set/Clear Active Bit 956" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE955 ,Set/Clear Active Bit 955" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE954 ,Set/Clear Active Bit 954" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE953 ,Set/Clear Active Bit 953" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE952 ,Set/Clear Active Bit 952" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE951 ,Set/Clear Active Bit 951" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE950 ,Set/Clear Active Bit 950" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE949 ,Set/Clear Active Bit 949" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE948 ,Set/Clear Active Bit 948" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE947 ,Set/Clear Active Bit 947" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE946 ,Set/Clear Active Bit 946" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE945 ,Set/Clear Active Bit 945" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE944 ,Set/Clear Active Bit 944" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE943 ,Set/Clear Active Bit 943" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE942 ,Set/Clear Active Bit 942" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE941 ,Set/Clear Active Bit 941" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE940 ,Set/Clear Active Bit 940" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE939 ,Set/Clear Active Bit 939" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE938 ,Set/Clear Active Bit 938" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE937 ,Set/Clear Active Bit 937" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE936 ,Set/Clear Active Bit 936" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE935 ,Set/Clear Active Bit 935" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE934 ,Set/Clear Active Bit 934" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE933 ,Set/Clear Active Bit 933" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE932 ,Set/Clear Active Bit 932" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE931 ,Set/Clear Active Bit 931" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE930 ,Set/Clear Active Bit 930" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE929 ,Set/Clear Active Bit 929" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE928 ,Set/Clear Active Bit 928" "Not active,Active" else rgroup.long 0x0374++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0378++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE991 ,Set/Clear Active Bit 991" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE990 ,Set/Clear Active Bit 990" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE989 ,Set/Clear Active Bit 989" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE988 ,Set/Clear Active Bit 988" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE987 ,Set/Clear Active Bit 987" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE986 ,Set/Clear Active Bit 986" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE985 ,Set/Clear Active Bit 985" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE984 ,Set/Clear Active Bit 984" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE983 ,Set/Clear Active Bit 983" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE982 ,Set/Clear Active Bit 982" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE981 ,Set/Clear Active Bit 981" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE980 ,Set/Clear Active Bit 980" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE979 ,Set/Clear Active Bit 979" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE978 ,Set/Clear Active Bit 978" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE977 ,Set/Clear Active Bit 977" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE976 ,Set/Clear Active Bit 976" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE975 ,Set/Clear Active Bit 975" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE974 ,Set/Clear Active Bit 974" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE973 ,Set/Clear Active Bit 973" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE972 ,Set/Clear Active Bit 972" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE971 ,Set/Clear Active Bit 971" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE970 ,Set/Clear Active Bit 970" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE969 ,Set/Clear Active Bit 969" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE968 ,Set/Clear Active Bit 968" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE967 ,Set/Clear Active Bit 967" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE966 ,Set/Clear Active Bit 966" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE965 ,Set/Clear Active Bit 965" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE964 ,Set/Clear Active Bit 964" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE963 ,Set/Clear Active Bit 963" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE962 ,Set/Clear Active Bit 962" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE961 ,Set/Clear Active Bit 961" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE960 ,Set/Clear Active Bit 960" "Not active,Active" else rgroup.long 0x0378++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" endif tree.end width 20. tree "Priority Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hexmask.long.byte 0x00 27.--31. 1. " INTID35 ,Interrupt ID35 Priority/Priority Byte Offset 35 " hexmask.long.byte 0x00 19.--23. 1. " INTID34 ,Interrupt ID34 Priority/Priority Byte Offset 34 " hexmask.long.byte 0x00 11.--15. 1. " INTID33 ,Interrupt ID33 Priority/Priority Byte Offset 33 " hexmask.long.byte 0x00 3.--7. 1. " INTID32 ,Interrupt ID32 Priority/Priority Byte Offset 32 " group.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hexmask.long.byte 0x00 27.--31. 1. " INTID39 ,Interrupt ID39 Priority/Priority Byte Offset 39 " hexmask.long.byte 0x00 19.--23. 1. " INTID38 ,Interrupt ID38 Priority/Priority Byte Offset 38 " hexmask.long.byte 0x00 11.--15. 1. " INTID37 ,Interrupt ID37 Priority/Priority Byte Offset 37 " hexmask.long.byte 0x00 3.--7. 1. " INTID36 ,Interrupt ID36 Priority/Priority Byte Offset 36 " group.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hexmask.long.byte 0x00 27.--31. 1. " INTID43 ,Interrupt ID43 Priority/Priority Byte Offset 43 " hexmask.long.byte 0x00 19.--23. 1. " INTID42 ,Interrupt ID42 Priority/Priority Byte Offset 42 " hexmask.long.byte 0x00 11.--15. 1. " INTID41 ,Interrupt ID41 Priority/Priority Byte Offset 41 " hexmask.long.byte 0x00 3.--7. 1. " INTID40 ,Interrupt ID40 Priority/Priority Byte Offset 40 " group.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hexmask.long.byte 0x00 27.--31. 1. " INTID47 ,Interrupt ID47 Priority/Priority Byte Offset 47 " hexmask.long.byte 0x00 19.--23. 1. " INTID46 ,Interrupt ID46 Priority/Priority Byte Offset 46 " hexmask.long.byte 0x00 11.--15. 1. " INTID45 ,Interrupt ID45 Priority/Priority Byte Offset 45 " hexmask.long.byte 0x00 3.--7. 1. " INTID44 ,Interrupt ID44 Priority/Priority Byte Offset 44 " group.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hexmask.long.byte 0x00 27.--31. 1. " INTID51 ,Interrupt ID51 Priority/Priority Byte Offset 51 " hexmask.long.byte 0x00 19.--23. 1. " INTID50 ,Interrupt ID50 Priority/Priority Byte Offset 50 " hexmask.long.byte 0x00 11.--15. 1. " INTID49 ,Interrupt ID49 Priority/Priority Byte Offset 49 " hexmask.long.byte 0x00 3.--7. 1. " INTID48 ,Interrupt ID48 Priority/Priority Byte Offset 48 " group.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hexmask.long.byte 0x00 27.--31. 1. " INTID55 ,Interrupt ID55 Priority/Priority Byte Offset 55 " hexmask.long.byte 0x00 19.--23. 1. " INTID54 ,Interrupt ID54 Priority/Priority Byte Offset 54 " hexmask.long.byte 0x00 11.--15. 1. " INTID53 ,Interrupt ID53 Priority/Priority Byte Offset 53 " hexmask.long.byte 0x00 3.--7. 1. " INTID52 ,Interrupt ID52 Priority/Priority Byte Offset 52 " group.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hexmask.long.byte 0x00 27.--31. 1. " INTID59 ,Interrupt ID59 Priority/Priority Byte Offset 59 " hexmask.long.byte 0x00 19.--23. 1. " INTID58 ,Interrupt ID58 Priority/Priority Byte Offset 58 " hexmask.long.byte 0x00 11.--15. 1. " INTID57 ,Interrupt ID57 Priority/Priority Byte Offset 57 " hexmask.long.byte 0x00 3.--7. 1. " INTID56 ,Interrupt ID56 Priority/Priority Byte Offset 56 " group.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" hexmask.long.byte 0x00 27.--31. 1. " INTID63 ,Interrupt ID63 Priority/Priority Byte Offset 63 " hexmask.long.byte 0x00 19.--23. 1. " INTID62 ,Interrupt ID62 Priority/Priority Byte Offset 62 " hexmask.long.byte 0x00 11.--15. 1. " INTID61 ,Interrupt ID61 Priority/Priority Byte Offset 61 " hexmask.long.byte 0x00 3.--7. 1. " INTID60 ,Interrupt ID60 Priority/Priority Byte Offset 60 " else rgroup.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" rgroup.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" rgroup.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" rgroup.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" rgroup.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" rgroup.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" rgroup.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" rgroup.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hexmask.long.byte 0x00 27.--31. 1. " INTID67 ,Interrupt ID67 Priority/Priority Byte Offset 67 " hexmask.long.byte 0x00 19.--23. 1. " INTID66 ,Interrupt ID66 Priority/Priority Byte Offset 66 " hexmask.long.byte 0x00 11.--15. 1. " INTID65 ,Interrupt ID65 Priority/Priority Byte Offset 65 " hexmask.long.byte 0x00 3.--7. 1. " INTID64 ,Interrupt ID64 Priority/Priority Byte Offset 64 " group.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hexmask.long.byte 0x00 27.--31. 1. " INTID71 ,Interrupt ID71 Priority/Priority Byte Offset 71 " hexmask.long.byte 0x00 19.--23. 1. " INTID70 ,Interrupt ID70 Priority/Priority Byte Offset 70 " hexmask.long.byte 0x00 11.--15. 1. " INTID69 ,Interrupt ID69 Priority/Priority Byte Offset 69 " hexmask.long.byte 0x00 3.--7. 1. " INTID68 ,Interrupt ID68 Priority/Priority Byte Offset 68 " group.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hexmask.long.byte 0x00 27.--31. 1. " INTID75 ,Interrupt ID75 Priority/Priority Byte Offset 75 " hexmask.long.byte 0x00 19.--23. 1. " INTID74 ,Interrupt ID74 Priority/Priority Byte Offset 74 " hexmask.long.byte 0x00 11.--15. 1. " INTID73 ,Interrupt ID73 Priority/Priority Byte Offset 73 " hexmask.long.byte 0x00 3.--7. 1. " INTID72 ,Interrupt ID72 Priority/Priority Byte Offset 72 " group.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hexmask.long.byte 0x00 27.--31. 1. " INTID79 ,Interrupt ID79 Priority/Priority Byte Offset 79 " hexmask.long.byte 0x00 19.--23. 1. " INTID78 ,Interrupt ID78 Priority/Priority Byte Offset 78 " hexmask.long.byte 0x00 11.--15. 1. " INTID77 ,Interrupt ID77 Priority/Priority Byte Offset 77 " hexmask.long.byte 0x00 3.--7. 1. " INTID76 ,Interrupt ID76 Priority/Priority Byte Offset 76 " group.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hexmask.long.byte 0x00 27.--31. 1. " INTID83 ,Interrupt ID83 Priority/Priority Byte Offset 83 " hexmask.long.byte 0x00 19.--23. 1. " INTID82 ,Interrupt ID82 Priority/Priority Byte Offset 82 " hexmask.long.byte 0x00 11.--15. 1. " INTID81 ,Interrupt ID81 Priority/Priority Byte Offset 81 " hexmask.long.byte 0x00 3.--7. 1. " INTID80 ,Interrupt ID80 Priority/Priority Byte Offset 80 " group.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hexmask.long.byte 0x00 27.--31. 1. " INTID87 ,Interrupt ID87 Priority/Priority Byte Offset 87 " hexmask.long.byte 0x00 19.--23. 1. " INTID86 ,Interrupt ID86 Priority/Priority Byte Offset 86 " hexmask.long.byte 0x00 11.--15. 1. " INTID85 ,Interrupt ID85 Priority/Priority Byte Offset 85 " hexmask.long.byte 0x00 3.--7. 1. " INTID84 ,Interrupt ID84 Priority/Priority Byte Offset 84 " group.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hexmask.long.byte 0x00 27.--31. 1. " INTID91 ,Interrupt ID91 Priority/Priority Byte Offset 91 " hexmask.long.byte 0x00 19.--23. 1. " INTID90 ,Interrupt ID90 Priority/Priority Byte Offset 90 " hexmask.long.byte 0x00 11.--15. 1. " INTID89 ,Interrupt ID89 Priority/Priority Byte Offset 89 " hexmask.long.byte 0x00 3.--7. 1. " INTID88 ,Interrupt ID88 Priority/Priority Byte Offset 88 " group.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" hexmask.long.byte 0x00 27.--31. 1. " INTID95 ,Interrupt ID95 Priority/Priority Byte Offset 95 " hexmask.long.byte 0x00 19.--23. 1. " INTID94 ,Interrupt ID94 Priority/Priority Byte Offset 94 " hexmask.long.byte 0x00 11.--15. 1. " INTID93 ,Interrupt ID93 Priority/Priority Byte Offset 93 " hexmask.long.byte 0x00 3.--7. 1. " INTID92 ,Interrupt ID92 Priority/Priority Byte Offset 92 " else rgroup.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" rgroup.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" rgroup.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" rgroup.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" rgroup.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" rgroup.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" rgroup.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" rgroup.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hexmask.long.byte 0x00 27.--31. 1. " INTID99 ,Interrupt ID99 Priority/Priority Byte Offset 99 " hexmask.long.byte 0x00 19.--23. 1. " INTID98 ,Interrupt ID98 Priority/Priority Byte Offset 98 " hexmask.long.byte 0x00 11.--15. 1. " INTID97 ,Interrupt ID97 Priority/Priority Byte Offset 97 " hexmask.long.byte 0x00 3.--7. 1. " INTID96 ,Interrupt ID96 Priority/Priority Byte Offset 96 " group.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hexmask.long.byte 0x00 27.--31. 1. " INTID103 ,Interrupt ID103 Priority/Priority Byte Offset 103 " hexmask.long.byte 0x00 19.--23. 1. " INTID102 ,Interrupt ID102 Priority/Priority Byte Offset 102 " hexmask.long.byte 0x00 11.--15. 1. " INTID101 ,Interrupt ID101 Priority/Priority Byte Offset 101 " hexmask.long.byte 0x00 3.--7. 1. " INTID100 ,Interrupt ID100 Priority/Priority Byte Offset 100 " group.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hexmask.long.byte 0x00 27.--31. 1. " INTID107 ,Interrupt ID107 Priority/Priority Byte Offset 107 " hexmask.long.byte 0x00 19.--23. 1. " INTID106 ,Interrupt ID106 Priority/Priority Byte Offset 106 " hexmask.long.byte 0x00 11.--15. 1. " INTID105 ,Interrupt ID105 Priority/Priority Byte Offset 105 " hexmask.long.byte 0x00 3.--7. 1. " INTID104 ,Interrupt ID104 Priority/Priority Byte Offset 104 " group.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hexmask.long.byte 0x00 27.--31. 1. " INTID111 ,Interrupt ID111 Priority/Priority Byte Offset 111 " hexmask.long.byte 0x00 19.--23. 1. " INTID110 ,Interrupt ID110 Priority/Priority Byte Offset 110 " hexmask.long.byte 0x00 11.--15. 1. " INTID109 ,Interrupt ID109 Priority/Priority Byte Offset 109 " hexmask.long.byte 0x00 3.--7. 1. " INTID108 ,Interrupt ID108 Priority/Priority Byte Offset 108 " group.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hexmask.long.byte 0x00 27.--31. 1. " INTID115 ,Interrupt ID115 Priority/Priority Byte Offset 115 " hexmask.long.byte 0x00 19.--23. 1. " INTID114 ,Interrupt ID114 Priority/Priority Byte Offset 114 " hexmask.long.byte 0x00 11.--15. 1. " INTID113 ,Interrupt ID113 Priority/Priority Byte Offset 113 " hexmask.long.byte 0x00 3.--7. 1. " INTID112 ,Interrupt ID112 Priority/Priority Byte Offset 112 " group.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hexmask.long.byte 0x00 27.--31. 1. " INTID119 ,Interrupt ID119 Priority/Priority Byte Offset 119 " hexmask.long.byte 0x00 19.--23. 1. " INTID118 ,Interrupt ID118 Priority/Priority Byte Offset 118 " hexmask.long.byte 0x00 11.--15. 1. " INTID117 ,Interrupt ID117 Priority/Priority Byte Offset 117 " hexmask.long.byte 0x00 3.--7. 1. " INTID116 ,Interrupt ID116 Priority/Priority Byte Offset 116 " group.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hexmask.long.byte 0x00 27.--31. 1. " INTID123 ,Interrupt ID123 Priority/Priority Byte Offset 123 " hexmask.long.byte 0x00 19.--23. 1. " INTID122 ,Interrupt ID122 Priority/Priority Byte Offset 122 " hexmask.long.byte 0x00 11.--15. 1. " INTID121 ,Interrupt ID121 Priority/Priority Byte Offset 121 " hexmask.long.byte 0x00 3.--7. 1. " INTID120 ,Interrupt ID120 Priority/Priority Byte Offset 120 " group.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" hexmask.long.byte 0x00 27.--31. 1. " INTID127 ,Interrupt ID127 Priority/Priority Byte Offset 127 " hexmask.long.byte 0x00 19.--23. 1. " INTID126 ,Interrupt ID126 Priority/Priority Byte Offset 126 " hexmask.long.byte 0x00 11.--15. 1. " INTID125 ,Interrupt ID125 Priority/Priority Byte Offset 125 " hexmask.long.byte 0x00 3.--7. 1. " INTID124 ,Interrupt ID124 Priority/Priority Byte Offset 124 " else rgroup.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" rgroup.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" rgroup.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" rgroup.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" rgroup.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" rgroup.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" rgroup.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" rgroup.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hexmask.long.byte 0x00 27.--31. 1. " INTID131 ,Interrupt ID131 Priority/Priority Byte Offset 131 " hexmask.long.byte 0x00 19.--23. 1. " INTID130 ,Interrupt ID130 Priority/Priority Byte Offset 130 " hexmask.long.byte 0x00 11.--15. 1. " INTID129 ,Interrupt ID129 Priority/Priority Byte Offset 129 " hexmask.long.byte 0x00 3.--7. 1. " INTID128 ,Interrupt ID128 Priority/Priority Byte Offset 128 " group.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hexmask.long.byte 0x00 27.--31. 1. " INTID135 ,Interrupt ID135 Priority/Priority Byte Offset 135 " hexmask.long.byte 0x00 19.--23. 1. " INTID134 ,Interrupt ID134 Priority/Priority Byte Offset 134 " hexmask.long.byte 0x00 11.--15. 1. " INTID133 ,Interrupt ID133 Priority/Priority Byte Offset 133 " hexmask.long.byte 0x00 3.--7. 1. " INTID132 ,Interrupt ID132 Priority/Priority Byte Offset 132 " group.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hexmask.long.byte 0x00 27.--31. 1. " INTID139 ,Interrupt ID139 Priority/Priority Byte Offset 139 " hexmask.long.byte 0x00 19.--23. 1. " INTID138 ,Interrupt ID138 Priority/Priority Byte Offset 138 " hexmask.long.byte 0x00 11.--15. 1. " INTID137 ,Interrupt ID137 Priority/Priority Byte Offset 137 " hexmask.long.byte 0x00 3.--7. 1. " INTID136 ,Interrupt ID136 Priority/Priority Byte Offset 136 " group.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hexmask.long.byte 0x00 27.--31. 1. " INTID143 ,Interrupt ID143 Priority/Priority Byte Offset 143 " hexmask.long.byte 0x00 19.--23. 1. " INTID142 ,Interrupt ID142 Priority/Priority Byte Offset 142 " hexmask.long.byte 0x00 11.--15. 1. " INTID141 ,Interrupt ID141 Priority/Priority Byte Offset 141 " hexmask.long.byte 0x00 3.--7. 1. " INTID140 ,Interrupt ID140 Priority/Priority Byte Offset 140 " group.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hexmask.long.byte 0x00 27.--31. 1. " INTID147 ,Interrupt ID147 Priority/Priority Byte Offset 147 " hexmask.long.byte 0x00 19.--23. 1. " INTID146 ,Interrupt ID146 Priority/Priority Byte Offset 146 " hexmask.long.byte 0x00 11.--15. 1. " INTID145 ,Interrupt ID145 Priority/Priority Byte Offset 145 " hexmask.long.byte 0x00 3.--7. 1. " INTID144 ,Interrupt ID144 Priority/Priority Byte Offset 144 " group.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hexmask.long.byte 0x00 27.--31. 1. " INTID151 ,Interrupt ID151 Priority/Priority Byte Offset 151 " hexmask.long.byte 0x00 19.--23. 1. " INTID150 ,Interrupt ID150 Priority/Priority Byte Offset 150 " hexmask.long.byte 0x00 11.--15. 1. " INTID149 ,Interrupt ID149 Priority/Priority Byte Offset 149 " hexmask.long.byte 0x00 3.--7. 1. " INTID148 ,Interrupt ID148 Priority/Priority Byte Offset 148 " group.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hexmask.long.byte 0x00 27.--31. 1. " INTID155 ,Interrupt ID155 Priority/Priority Byte Offset 155 " hexmask.long.byte 0x00 19.--23. 1. " INTID154 ,Interrupt ID154 Priority/Priority Byte Offset 154 " hexmask.long.byte 0x00 11.--15. 1. " INTID153 ,Interrupt ID153 Priority/Priority Byte Offset 153 " hexmask.long.byte 0x00 3.--7. 1. " INTID152 ,Interrupt ID152 Priority/Priority Byte Offset 152 " group.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" hexmask.long.byte 0x00 27.--31. 1. " INTID159 ,Interrupt ID159 Priority/Priority Byte Offset 159 " hexmask.long.byte 0x00 19.--23. 1. " INTID158 ,Interrupt ID158 Priority/Priority Byte Offset 158 " hexmask.long.byte 0x00 11.--15. 1. " INTID157 ,Interrupt ID157 Priority/Priority Byte Offset 157 " hexmask.long.byte 0x00 3.--7. 1. " INTID156 ,Interrupt ID156 Priority/Priority Byte Offset 156 " else rgroup.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" rgroup.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" rgroup.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" rgroup.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" rgroup.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" rgroup.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" rgroup.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" rgroup.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hexmask.long.byte 0x00 27.--31. 1. " INTID163 ,Interrupt ID163 Priority/Priority Byte Offset 163 " hexmask.long.byte 0x00 19.--23. 1. " INTID162 ,Interrupt ID162 Priority/Priority Byte Offset 162 " hexmask.long.byte 0x00 11.--15. 1. " INTID161 ,Interrupt ID161 Priority/Priority Byte Offset 161 " hexmask.long.byte 0x00 3.--7. 1. " INTID160 ,Interrupt ID160 Priority/Priority Byte Offset 160 " group.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hexmask.long.byte 0x00 27.--31. 1. " INTID167 ,Interrupt ID167 Priority/Priority Byte Offset 167 " hexmask.long.byte 0x00 19.--23. 1. " INTID166 ,Interrupt ID166 Priority/Priority Byte Offset 166 " hexmask.long.byte 0x00 11.--15. 1. " INTID165 ,Interrupt ID165 Priority/Priority Byte Offset 165 " hexmask.long.byte 0x00 3.--7. 1. " INTID164 ,Interrupt ID164 Priority/Priority Byte Offset 164 " group.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hexmask.long.byte 0x00 27.--31. 1. " INTID171 ,Interrupt ID171 Priority/Priority Byte Offset 171 " hexmask.long.byte 0x00 19.--23. 1. " INTID170 ,Interrupt ID170 Priority/Priority Byte Offset 170 " hexmask.long.byte 0x00 11.--15. 1. " INTID169 ,Interrupt ID169 Priority/Priority Byte Offset 169 " hexmask.long.byte 0x00 3.--7. 1. " INTID168 ,Interrupt ID168 Priority/Priority Byte Offset 168 " group.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hexmask.long.byte 0x00 27.--31. 1. " INTID175 ,Interrupt ID175 Priority/Priority Byte Offset 175 " hexmask.long.byte 0x00 19.--23. 1. " INTID174 ,Interrupt ID174 Priority/Priority Byte Offset 174 " hexmask.long.byte 0x00 11.--15. 1. " INTID173 ,Interrupt ID173 Priority/Priority Byte Offset 173 " hexmask.long.byte 0x00 3.--7. 1. " INTID172 ,Interrupt ID172 Priority/Priority Byte Offset 172 " group.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hexmask.long.byte 0x00 27.--31. 1. " INTID179 ,Interrupt ID179 Priority/Priority Byte Offset 179 " hexmask.long.byte 0x00 19.--23. 1. " INTID178 ,Interrupt ID178 Priority/Priority Byte Offset 178 " hexmask.long.byte 0x00 11.--15. 1. " INTID177 ,Interrupt ID177 Priority/Priority Byte Offset 177 " hexmask.long.byte 0x00 3.--7. 1. " INTID176 ,Interrupt ID176 Priority/Priority Byte Offset 176 " group.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hexmask.long.byte 0x00 27.--31. 1. " INTID183 ,Interrupt ID183 Priority/Priority Byte Offset 183 " hexmask.long.byte 0x00 19.--23. 1. " INTID182 ,Interrupt ID182 Priority/Priority Byte Offset 182 " hexmask.long.byte 0x00 11.--15. 1. " INTID181 ,Interrupt ID181 Priority/Priority Byte Offset 181 " hexmask.long.byte 0x00 3.--7. 1. " INTID180 ,Interrupt ID180 Priority/Priority Byte Offset 180 " group.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hexmask.long.byte 0x00 27.--31. 1. " INTID187 ,Interrupt ID187 Priority/Priority Byte Offset 187 " hexmask.long.byte 0x00 19.--23. 1. " INTID186 ,Interrupt ID186 Priority/Priority Byte Offset 186 " hexmask.long.byte 0x00 11.--15. 1. " INTID185 ,Interrupt ID185 Priority/Priority Byte Offset 185 " hexmask.long.byte 0x00 3.--7. 1. " INTID184 ,Interrupt ID184 Priority/Priority Byte Offset 184 " group.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" hexmask.long.byte 0x00 27.--31. 1. " INTID191 ,Interrupt ID191 Priority/Priority Byte Offset 191 " hexmask.long.byte 0x00 19.--23. 1. " INTID190 ,Interrupt ID190 Priority/Priority Byte Offset 190 " hexmask.long.byte 0x00 11.--15. 1. " INTID189 ,Interrupt ID189 Priority/Priority Byte Offset 189 " hexmask.long.byte 0x00 3.--7. 1. " INTID188 ,Interrupt ID188 Priority/Priority Byte Offset 188 " else rgroup.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" rgroup.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" rgroup.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" rgroup.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" rgroup.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" rgroup.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" rgroup.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" rgroup.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hexmask.long.byte 0x00 27.--31. 1. " INTID195 ,Interrupt ID195 Priority/Priority Byte Offset 195 " hexmask.long.byte 0x00 19.--23. 1. " INTID194 ,Interrupt ID194 Priority/Priority Byte Offset 194 " hexmask.long.byte 0x00 11.--15. 1. " INTID193 ,Interrupt ID193 Priority/Priority Byte Offset 193 " hexmask.long.byte 0x00 3.--7. 1. " INTID192 ,Interrupt ID192 Priority/Priority Byte Offset 192 " group.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hexmask.long.byte 0x00 27.--31. 1. " INTID199 ,Interrupt ID199 Priority/Priority Byte Offset 199 " hexmask.long.byte 0x00 19.--23. 1. " INTID198 ,Interrupt ID198 Priority/Priority Byte Offset 198 " hexmask.long.byte 0x00 11.--15. 1. " INTID197 ,Interrupt ID197 Priority/Priority Byte Offset 197 " hexmask.long.byte 0x00 3.--7. 1. " INTID196 ,Interrupt ID196 Priority/Priority Byte Offset 196 " group.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hexmask.long.byte 0x00 27.--31. 1. " INTID203 ,Interrupt ID203 Priority/Priority Byte Offset 203 " hexmask.long.byte 0x00 19.--23. 1. " INTID202 ,Interrupt ID202 Priority/Priority Byte Offset 202 " hexmask.long.byte 0x00 11.--15. 1. " INTID201 ,Interrupt ID201 Priority/Priority Byte Offset 201 " hexmask.long.byte 0x00 3.--7. 1. " INTID200 ,Interrupt ID200 Priority/Priority Byte Offset 200 " group.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hexmask.long.byte 0x00 27.--31. 1. " INTID207 ,Interrupt ID207 Priority/Priority Byte Offset 207 " hexmask.long.byte 0x00 19.--23. 1. " INTID206 ,Interrupt ID206 Priority/Priority Byte Offset 206 " hexmask.long.byte 0x00 11.--15. 1. " INTID205 ,Interrupt ID205 Priority/Priority Byte Offset 205 " hexmask.long.byte 0x00 3.--7. 1. " INTID204 ,Interrupt ID204 Priority/Priority Byte Offset 204 " group.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hexmask.long.byte 0x00 27.--31. 1. " INTID211 ,Interrupt ID211 Priority/Priority Byte Offset 211 " hexmask.long.byte 0x00 19.--23. 1. " INTID210 ,Interrupt ID210 Priority/Priority Byte Offset 210 " hexmask.long.byte 0x00 11.--15. 1. " INTID209 ,Interrupt ID209 Priority/Priority Byte Offset 209 " hexmask.long.byte 0x00 3.--7. 1. " INTID208 ,Interrupt ID208 Priority/Priority Byte Offset 208 " group.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hexmask.long.byte 0x00 27.--31. 1. " INTID215 ,Interrupt ID215 Priority/Priority Byte Offset 215 " hexmask.long.byte 0x00 19.--23. 1. " INTID214 ,Interrupt ID214 Priority/Priority Byte Offset 214 " hexmask.long.byte 0x00 11.--15. 1. " INTID213 ,Interrupt ID213 Priority/Priority Byte Offset 213 " hexmask.long.byte 0x00 3.--7. 1. " INTID212 ,Interrupt ID212 Priority/Priority Byte Offset 212 " group.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hexmask.long.byte 0x00 27.--31. 1. " INTID219 ,Interrupt ID219 Priority/Priority Byte Offset 219 " hexmask.long.byte 0x00 19.--23. 1. " INTID218 ,Interrupt ID218 Priority/Priority Byte Offset 218 " hexmask.long.byte 0x00 11.--15. 1. " INTID217 ,Interrupt ID217 Priority/Priority Byte Offset 217 " hexmask.long.byte 0x00 3.--7. 1. " INTID216 ,Interrupt ID216 Priority/Priority Byte Offset 216 " group.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" hexmask.long.byte 0x00 27.--31. 1. " INTID223 ,Interrupt ID223 Priority/Priority Byte Offset 223 " hexmask.long.byte 0x00 19.--23. 1. " INTID222 ,Interrupt ID222 Priority/Priority Byte Offset 222 " hexmask.long.byte 0x00 11.--15. 1. " INTID221 ,Interrupt ID221 Priority/Priority Byte Offset 221 " hexmask.long.byte 0x00 3.--7. 1. " INTID220 ,Interrupt ID220 Priority/Priority Byte Offset 220 " else rgroup.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" rgroup.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" rgroup.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" rgroup.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" rgroup.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" rgroup.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" rgroup.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" rgroup.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hexmask.long.byte 0x00 27.--31. 1. " INTID227 ,Interrupt ID227 Priority/Priority Byte Offset 227 " hexmask.long.byte 0x00 19.--23. 1. " INTID226 ,Interrupt ID226 Priority/Priority Byte Offset 226 " hexmask.long.byte 0x00 11.--15. 1. " INTID225 ,Interrupt ID225 Priority/Priority Byte Offset 225 " hexmask.long.byte 0x00 3.--7. 1. " INTID224 ,Interrupt ID224 Priority/Priority Byte Offset 224 " group.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hexmask.long.byte 0x00 27.--31. 1. " INTID231 ,Interrupt ID231 Priority/Priority Byte Offset 231 " hexmask.long.byte 0x00 19.--23. 1. " INTID230 ,Interrupt ID230 Priority/Priority Byte Offset 230 " hexmask.long.byte 0x00 11.--15. 1. " INTID229 ,Interrupt ID229 Priority/Priority Byte Offset 229 " hexmask.long.byte 0x00 3.--7. 1. " INTID228 ,Interrupt ID228 Priority/Priority Byte Offset 228 " group.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hexmask.long.byte 0x00 27.--31. 1. " INTID235 ,Interrupt ID235 Priority/Priority Byte Offset 235 " hexmask.long.byte 0x00 19.--23. 1. " INTID234 ,Interrupt ID234 Priority/Priority Byte Offset 234 " hexmask.long.byte 0x00 11.--15. 1. " INTID233 ,Interrupt ID233 Priority/Priority Byte Offset 233 " hexmask.long.byte 0x00 3.--7. 1. " INTID232 ,Interrupt ID232 Priority/Priority Byte Offset 232 " group.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hexmask.long.byte 0x00 27.--31. 1. " INTID239 ,Interrupt ID239 Priority/Priority Byte Offset 239 " hexmask.long.byte 0x00 19.--23. 1. " INTID238 ,Interrupt ID238 Priority/Priority Byte Offset 238 " hexmask.long.byte 0x00 11.--15. 1. " INTID237 ,Interrupt ID237 Priority/Priority Byte Offset 237 " hexmask.long.byte 0x00 3.--7. 1. " INTID236 ,Interrupt ID236 Priority/Priority Byte Offset 236 " group.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hexmask.long.byte 0x00 27.--31. 1. " INTID243 ,Interrupt ID243 Priority/Priority Byte Offset 243 " hexmask.long.byte 0x00 19.--23. 1. " INTID242 ,Interrupt ID242 Priority/Priority Byte Offset 242 " hexmask.long.byte 0x00 11.--15. 1. " INTID241 ,Interrupt ID241 Priority/Priority Byte Offset 241 " hexmask.long.byte 0x00 3.--7. 1. " INTID240 ,Interrupt ID240 Priority/Priority Byte Offset 240 " group.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hexmask.long.byte 0x00 27.--31. 1. " INTID247 ,Interrupt ID247 Priority/Priority Byte Offset 247 " hexmask.long.byte 0x00 19.--23. 1. " INTID246 ,Interrupt ID246 Priority/Priority Byte Offset 246 " hexmask.long.byte 0x00 11.--15. 1. " INTID245 ,Interrupt ID245 Priority/Priority Byte Offset 245 " hexmask.long.byte 0x00 3.--7. 1. " INTID244 ,Interrupt ID244 Priority/Priority Byte Offset 244 " group.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hexmask.long.byte 0x00 27.--31. 1. " INTID251 ,Interrupt ID251 Priority/Priority Byte Offset 251 " hexmask.long.byte 0x00 19.--23. 1. " INTID250 ,Interrupt ID250 Priority/Priority Byte Offset 250 " hexmask.long.byte 0x00 11.--15. 1. " INTID249 ,Interrupt ID249 Priority/Priority Byte Offset 249 " hexmask.long.byte 0x00 3.--7. 1. " INTID248 ,Interrupt ID248 Priority/Priority Byte Offset 248 " group.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" hexmask.long.byte 0x00 27.--31. 1. " INTID255 ,Interrupt ID255 Priority/Priority Byte Offset 255 " hexmask.long.byte 0x00 19.--23. 1. " INTID254 ,Interrupt ID254 Priority/Priority Byte Offset 254 " hexmask.long.byte 0x00 11.--15. 1. " INTID253 ,Interrupt ID253 Priority/Priority Byte Offset 253 " hexmask.long.byte 0x00 3.--7. 1. " INTID252 ,Interrupt ID252 Priority/Priority Byte Offset 252 " else rgroup.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" rgroup.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" rgroup.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" rgroup.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" rgroup.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" rgroup.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" rgroup.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" rgroup.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hexmask.long.byte 0x00 27.--31. 1. " INTID259 ,Interrupt ID259 Priority/Priority Byte Offset 259 " hexmask.long.byte 0x00 19.--23. 1. " INTID258 ,Interrupt ID258 Priority/Priority Byte Offset 258 " hexmask.long.byte 0x00 11.--15. 1. " INTID257 ,Interrupt ID257 Priority/Priority Byte Offset 257 " hexmask.long.byte 0x00 3.--7. 1. " INTID256 ,Interrupt ID256 Priority/Priority Byte Offset 256 " group.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hexmask.long.byte 0x00 27.--31. 1. " INTID263 ,Interrupt ID263 Priority/Priority Byte Offset 263 " hexmask.long.byte 0x00 19.--23. 1. " INTID262 ,Interrupt ID262 Priority/Priority Byte Offset 262 " hexmask.long.byte 0x00 11.--15. 1. " INTID261 ,Interrupt ID261 Priority/Priority Byte Offset 261 " hexmask.long.byte 0x00 3.--7. 1. " INTID260 ,Interrupt ID260 Priority/Priority Byte Offset 260 " group.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hexmask.long.byte 0x00 27.--31. 1. " INTID267 ,Interrupt ID267 Priority/Priority Byte Offset 267 " hexmask.long.byte 0x00 19.--23. 1. " INTID266 ,Interrupt ID266 Priority/Priority Byte Offset 266 " hexmask.long.byte 0x00 11.--15. 1. " INTID265 ,Interrupt ID265 Priority/Priority Byte Offset 265 " hexmask.long.byte 0x00 3.--7. 1. " INTID264 ,Interrupt ID264 Priority/Priority Byte Offset 264 " group.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hexmask.long.byte 0x00 27.--31. 1. " INTID271 ,Interrupt ID271 Priority/Priority Byte Offset 271 " hexmask.long.byte 0x00 19.--23. 1. " INTID270 ,Interrupt ID270 Priority/Priority Byte Offset 270 " hexmask.long.byte 0x00 11.--15. 1. " INTID269 ,Interrupt ID269 Priority/Priority Byte Offset 269 " hexmask.long.byte 0x00 3.--7. 1. " INTID268 ,Interrupt ID268 Priority/Priority Byte Offset 268 " group.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hexmask.long.byte 0x00 27.--31. 1. " INTID275 ,Interrupt ID275 Priority/Priority Byte Offset 275 " hexmask.long.byte 0x00 19.--23. 1. " INTID274 ,Interrupt ID274 Priority/Priority Byte Offset 274 " hexmask.long.byte 0x00 11.--15. 1. " INTID273 ,Interrupt ID273 Priority/Priority Byte Offset 273 " hexmask.long.byte 0x00 3.--7. 1. " INTID272 ,Interrupt ID272 Priority/Priority Byte Offset 272 " group.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hexmask.long.byte 0x00 27.--31. 1. " INTID279 ,Interrupt ID279 Priority/Priority Byte Offset 279 " hexmask.long.byte 0x00 19.--23. 1. " INTID278 ,Interrupt ID278 Priority/Priority Byte Offset 278 " hexmask.long.byte 0x00 11.--15. 1. " INTID277 ,Interrupt ID277 Priority/Priority Byte Offset 277 " hexmask.long.byte 0x00 3.--7. 1. " INTID276 ,Interrupt ID276 Priority/Priority Byte Offset 276 " group.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hexmask.long.byte 0x00 27.--31. 1. " INTID283 ,Interrupt ID283 Priority/Priority Byte Offset 283 " hexmask.long.byte 0x00 19.--23. 1. " INTID282 ,Interrupt ID282 Priority/Priority Byte Offset 282 " hexmask.long.byte 0x00 11.--15. 1. " INTID281 ,Interrupt ID281 Priority/Priority Byte Offset 281 " hexmask.long.byte 0x00 3.--7. 1. " INTID280 ,Interrupt ID280 Priority/Priority Byte Offset 280 " group.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" hexmask.long.byte 0x00 27.--31. 1. " INTID287 ,Interrupt ID287 Priority/Priority Byte Offset 287 " hexmask.long.byte 0x00 19.--23. 1. " INTID286 ,Interrupt ID286 Priority/Priority Byte Offset 286 " hexmask.long.byte 0x00 11.--15. 1. " INTID285 ,Interrupt ID285 Priority/Priority Byte Offset 285 " hexmask.long.byte 0x00 3.--7. 1. " INTID284 ,Interrupt ID284 Priority/Priority Byte Offset 284 " else rgroup.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" rgroup.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" rgroup.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" rgroup.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" rgroup.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" rgroup.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" rgroup.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" rgroup.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hexmask.long.byte 0x00 27.--31. 1. " INTID291 ,Interrupt ID291 Priority/Priority Byte Offset 291 " hexmask.long.byte 0x00 19.--23. 1. " INTID290 ,Interrupt ID290 Priority/Priority Byte Offset 290 " hexmask.long.byte 0x00 11.--15. 1. " INTID289 ,Interrupt ID289 Priority/Priority Byte Offset 289 " hexmask.long.byte 0x00 3.--7. 1. " INTID288 ,Interrupt ID288 Priority/Priority Byte Offset 288 " group.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hexmask.long.byte 0x00 27.--31. 1. " INTID295 ,Interrupt ID295 Priority/Priority Byte Offset 295 " hexmask.long.byte 0x00 19.--23. 1. " INTID294 ,Interrupt ID294 Priority/Priority Byte Offset 294 " hexmask.long.byte 0x00 11.--15. 1. " INTID293 ,Interrupt ID293 Priority/Priority Byte Offset 293 " hexmask.long.byte 0x00 3.--7. 1. " INTID292 ,Interrupt ID292 Priority/Priority Byte Offset 292 " group.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hexmask.long.byte 0x00 27.--31. 1. " INTID299 ,Interrupt ID299 Priority/Priority Byte Offset 299 " hexmask.long.byte 0x00 19.--23. 1. " INTID298 ,Interrupt ID298 Priority/Priority Byte Offset 298 " hexmask.long.byte 0x00 11.--15. 1. " INTID297 ,Interrupt ID297 Priority/Priority Byte Offset 297 " hexmask.long.byte 0x00 3.--7. 1. " INTID296 ,Interrupt ID296 Priority/Priority Byte Offset 296 " group.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hexmask.long.byte 0x00 27.--31. 1. " INTID303 ,Interrupt ID303 Priority/Priority Byte Offset 303 " hexmask.long.byte 0x00 19.--23. 1. " INTID302 ,Interrupt ID302 Priority/Priority Byte Offset 302 " hexmask.long.byte 0x00 11.--15. 1. " INTID301 ,Interrupt ID301 Priority/Priority Byte Offset 301 " hexmask.long.byte 0x00 3.--7. 1. " INTID300 ,Interrupt ID300 Priority/Priority Byte Offset 300 " group.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hexmask.long.byte 0x00 27.--31. 1. " INTID307 ,Interrupt ID307 Priority/Priority Byte Offset 307 " hexmask.long.byte 0x00 19.--23. 1. " INTID306 ,Interrupt ID306 Priority/Priority Byte Offset 306 " hexmask.long.byte 0x00 11.--15. 1. " INTID305 ,Interrupt ID305 Priority/Priority Byte Offset 305 " hexmask.long.byte 0x00 3.--7. 1. " INTID304 ,Interrupt ID304 Priority/Priority Byte Offset 304 " group.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hexmask.long.byte 0x00 27.--31. 1. " INTID311 ,Interrupt ID311 Priority/Priority Byte Offset 311 " hexmask.long.byte 0x00 19.--23. 1. " INTID310 ,Interrupt ID310 Priority/Priority Byte Offset 310 " hexmask.long.byte 0x00 11.--15. 1. " INTID309 ,Interrupt ID309 Priority/Priority Byte Offset 309 " hexmask.long.byte 0x00 3.--7. 1. " INTID308 ,Interrupt ID308 Priority/Priority Byte Offset 308 " group.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hexmask.long.byte 0x00 27.--31. 1. " INTID315 ,Interrupt ID315 Priority/Priority Byte Offset 315 " hexmask.long.byte 0x00 19.--23. 1. " INTID314 ,Interrupt ID314 Priority/Priority Byte Offset 314 " hexmask.long.byte 0x00 11.--15. 1. " INTID313 ,Interrupt ID313 Priority/Priority Byte Offset 313 " hexmask.long.byte 0x00 3.--7. 1. " INTID312 ,Interrupt ID312 Priority/Priority Byte Offset 312 " group.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" hexmask.long.byte 0x00 27.--31. 1. " INTID319 ,Interrupt ID319 Priority/Priority Byte Offset 319 " hexmask.long.byte 0x00 19.--23. 1. " INTID318 ,Interrupt ID318 Priority/Priority Byte Offset 318 " hexmask.long.byte 0x00 11.--15. 1. " INTID317 ,Interrupt ID317 Priority/Priority Byte Offset 317 " hexmask.long.byte 0x00 3.--7. 1. " INTID316 ,Interrupt ID316 Priority/Priority Byte Offset 316 " else rgroup.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" rgroup.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" rgroup.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" rgroup.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" rgroup.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" rgroup.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" rgroup.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" rgroup.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hexmask.long.byte 0x00 27.--31. 1. " INTID323 ,Interrupt ID323 Priority/Priority Byte Offset 323 " hexmask.long.byte 0x00 19.--23. 1. " INTID322 ,Interrupt ID322 Priority/Priority Byte Offset 322 " hexmask.long.byte 0x00 11.--15. 1. " INTID321 ,Interrupt ID321 Priority/Priority Byte Offset 321 " hexmask.long.byte 0x00 3.--7. 1. " INTID320 ,Interrupt ID320 Priority/Priority Byte Offset 320 " group.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hexmask.long.byte 0x00 27.--31. 1. " INTID327 ,Interrupt ID327 Priority/Priority Byte Offset 327 " hexmask.long.byte 0x00 19.--23. 1. " INTID326 ,Interrupt ID326 Priority/Priority Byte Offset 326 " hexmask.long.byte 0x00 11.--15. 1. " INTID325 ,Interrupt ID325 Priority/Priority Byte Offset 325 " hexmask.long.byte 0x00 3.--7. 1. " INTID324 ,Interrupt ID324 Priority/Priority Byte Offset 324 " group.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hexmask.long.byte 0x00 27.--31. 1. " INTID331 ,Interrupt ID331 Priority/Priority Byte Offset 331 " hexmask.long.byte 0x00 19.--23. 1. " INTID330 ,Interrupt ID330 Priority/Priority Byte Offset 330 " hexmask.long.byte 0x00 11.--15. 1. " INTID329 ,Interrupt ID329 Priority/Priority Byte Offset 329 " hexmask.long.byte 0x00 3.--7. 1. " INTID328 ,Interrupt ID328 Priority/Priority Byte Offset 328 " group.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hexmask.long.byte 0x00 27.--31. 1. " INTID335 ,Interrupt ID335 Priority/Priority Byte Offset 335 " hexmask.long.byte 0x00 19.--23. 1. " INTID334 ,Interrupt ID334 Priority/Priority Byte Offset 334 " hexmask.long.byte 0x00 11.--15. 1. " INTID333 ,Interrupt ID333 Priority/Priority Byte Offset 333 " hexmask.long.byte 0x00 3.--7. 1. " INTID332 ,Interrupt ID332 Priority/Priority Byte Offset 332 " group.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hexmask.long.byte 0x00 27.--31. 1. " INTID339 ,Interrupt ID339 Priority/Priority Byte Offset 339 " hexmask.long.byte 0x00 19.--23. 1. " INTID338 ,Interrupt ID338 Priority/Priority Byte Offset 338 " hexmask.long.byte 0x00 11.--15. 1. " INTID337 ,Interrupt ID337 Priority/Priority Byte Offset 337 " hexmask.long.byte 0x00 3.--7. 1. " INTID336 ,Interrupt ID336 Priority/Priority Byte Offset 336 " group.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hexmask.long.byte 0x00 27.--31. 1. " INTID343 ,Interrupt ID343 Priority/Priority Byte Offset 343 " hexmask.long.byte 0x00 19.--23. 1. " INTID342 ,Interrupt ID342 Priority/Priority Byte Offset 342 " hexmask.long.byte 0x00 11.--15. 1. " INTID341 ,Interrupt ID341 Priority/Priority Byte Offset 341 " hexmask.long.byte 0x00 3.--7. 1. " INTID340 ,Interrupt ID340 Priority/Priority Byte Offset 340 " group.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hexmask.long.byte 0x00 27.--31. 1. " INTID347 ,Interrupt ID347 Priority/Priority Byte Offset 347 " hexmask.long.byte 0x00 19.--23. 1. " INTID346 ,Interrupt ID346 Priority/Priority Byte Offset 346 " hexmask.long.byte 0x00 11.--15. 1. " INTID345 ,Interrupt ID345 Priority/Priority Byte Offset 345 " hexmask.long.byte 0x00 3.--7. 1. " INTID344 ,Interrupt ID344 Priority/Priority Byte Offset 344 " group.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" hexmask.long.byte 0x00 27.--31. 1. " INTID351 ,Interrupt ID351 Priority/Priority Byte Offset 351 " hexmask.long.byte 0x00 19.--23. 1. " INTID350 ,Interrupt ID350 Priority/Priority Byte Offset 350 " hexmask.long.byte 0x00 11.--15. 1. " INTID349 ,Interrupt ID349 Priority/Priority Byte Offset 349 " hexmask.long.byte 0x00 3.--7. 1. " INTID348 ,Interrupt ID348 Priority/Priority Byte Offset 348 " else rgroup.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" rgroup.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" rgroup.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" rgroup.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" rgroup.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" rgroup.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" rgroup.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" rgroup.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hexmask.long.byte 0x00 27.--31. 1. " INTID355 ,Interrupt ID355 Priority/Priority Byte Offset 355 " hexmask.long.byte 0x00 19.--23. 1. " INTID354 ,Interrupt ID354 Priority/Priority Byte Offset 354 " hexmask.long.byte 0x00 11.--15. 1. " INTID353 ,Interrupt ID353 Priority/Priority Byte Offset 353 " hexmask.long.byte 0x00 3.--7. 1. " INTID352 ,Interrupt ID352 Priority/Priority Byte Offset 352 " group.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hexmask.long.byte 0x00 27.--31. 1. " INTID359 ,Interrupt ID359 Priority/Priority Byte Offset 359 " hexmask.long.byte 0x00 19.--23. 1. " INTID358 ,Interrupt ID358 Priority/Priority Byte Offset 358 " hexmask.long.byte 0x00 11.--15. 1. " INTID357 ,Interrupt ID357 Priority/Priority Byte Offset 357 " hexmask.long.byte 0x00 3.--7. 1. " INTID356 ,Interrupt ID356 Priority/Priority Byte Offset 356 " group.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hexmask.long.byte 0x00 27.--31. 1. " INTID363 ,Interrupt ID363 Priority/Priority Byte Offset 363 " hexmask.long.byte 0x00 19.--23. 1. " INTID362 ,Interrupt ID362 Priority/Priority Byte Offset 362 " hexmask.long.byte 0x00 11.--15. 1. " INTID361 ,Interrupt ID361 Priority/Priority Byte Offset 361 " hexmask.long.byte 0x00 3.--7. 1. " INTID360 ,Interrupt ID360 Priority/Priority Byte Offset 360 " group.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hexmask.long.byte 0x00 27.--31. 1. " INTID367 ,Interrupt ID367 Priority/Priority Byte Offset 367 " hexmask.long.byte 0x00 19.--23. 1. " INTID366 ,Interrupt ID366 Priority/Priority Byte Offset 366 " hexmask.long.byte 0x00 11.--15. 1. " INTID365 ,Interrupt ID365 Priority/Priority Byte Offset 365 " hexmask.long.byte 0x00 3.--7. 1. " INTID364 ,Interrupt ID364 Priority/Priority Byte Offset 364 " group.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hexmask.long.byte 0x00 27.--31. 1. " INTID371 ,Interrupt ID371 Priority/Priority Byte Offset 371 " hexmask.long.byte 0x00 19.--23. 1. " INTID370 ,Interrupt ID370 Priority/Priority Byte Offset 370 " hexmask.long.byte 0x00 11.--15. 1. " INTID369 ,Interrupt ID369 Priority/Priority Byte Offset 369 " hexmask.long.byte 0x00 3.--7. 1. " INTID368 ,Interrupt ID368 Priority/Priority Byte Offset 368 " group.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hexmask.long.byte 0x00 27.--31. 1. " INTID375 ,Interrupt ID375 Priority/Priority Byte Offset 375 " hexmask.long.byte 0x00 19.--23. 1. " INTID374 ,Interrupt ID374 Priority/Priority Byte Offset 374 " hexmask.long.byte 0x00 11.--15. 1. " INTID373 ,Interrupt ID373 Priority/Priority Byte Offset 373 " hexmask.long.byte 0x00 3.--7. 1. " INTID372 ,Interrupt ID372 Priority/Priority Byte Offset 372 " group.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hexmask.long.byte 0x00 27.--31. 1. " INTID379 ,Interrupt ID379 Priority/Priority Byte Offset 379 " hexmask.long.byte 0x00 19.--23. 1. " INTID378 ,Interrupt ID378 Priority/Priority Byte Offset 378 " hexmask.long.byte 0x00 11.--15. 1. " INTID377 ,Interrupt ID377 Priority/Priority Byte Offset 377 " hexmask.long.byte 0x00 3.--7. 1. " INTID376 ,Interrupt ID376 Priority/Priority Byte Offset 376 " group.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" hexmask.long.byte 0x00 27.--31. 1. " INTID383 ,Interrupt ID383 Priority/Priority Byte Offset 383 " hexmask.long.byte 0x00 19.--23. 1. " INTID382 ,Interrupt ID382 Priority/Priority Byte Offset 382 " hexmask.long.byte 0x00 11.--15. 1. " INTID381 ,Interrupt ID381 Priority/Priority Byte Offset 381 " hexmask.long.byte 0x00 3.--7. 1. " INTID380 ,Interrupt ID380 Priority/Priority Byte Offset 380 " else rgroup.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" rgroup.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" rgroup.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" rgroup.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" rgroup.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" rgroup.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" rgroup.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" rgroup.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hexmask.long.byte 0x00 27.--31. 1. " INTID387 ,Interrupt ID387 Priority/Priority Byte Offset 387 " hexmask.long.byte 0x00 19.--23. 1. " INTID386 ,Interrupt ID386 Priority/Priority Byte Offset 386 " hexmask.long.byte 0x00 11.--15. 1. " INTID385 ,Interrupt ID385 Priority/Priority Byte Offset 385 " hexmask.long.byte 0x00 3.--7. 1. " INTID384 ,Interrupt ID384 Priority/Priority Byte Offset 384 " group.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hexmask.long.byte 0x00 27.--31. 1. " INTID391 ,Interrupt ID391 Priority/Priority Byte Offset 391 " hexmask.long.byte 0x00 19.--23. 1. " INTID390 ,Interrupt ID390 Priority/Priority Byte Offset 390 " hexmask.long.byte 0x00 11.--15. 1. " INTID389 ,Interrupt ID389 Priority/Priority Byte Offset 389 " hexmask.long.byte 0x00 3.--7. 1. " INTID388 ,Interrupt ID388 Priority/Priority Byte Offset 388 " group.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hexmask.long.byte 0x00 27.--31. 1. " INTID395 ,Interrupt ID395 Priority/Priority Byte Offset 395 " hexmask.long.byte 0x00 19.--23. 1. " INTID394 ,Interrupt ID394 Priority/Priority Byte Offset 394 " hexmask.long.byte 0x00 11.--15. 1. " INTID393 ,Interrupt ID393 Priority/Priority Byte Offset 393 " hexmask.long.byte 0x00 3.--7. 1. " INTID392 ,Interrupt ID392 Priority/Priority Byte Offset 392 " group.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hexmask.long.byte 0x00 27.--31. 1. " INTID399 ,Interrupt ID399 Priority/Priority Byte Offset 399 " hexmask.long.byte 0x00 19.--23. 1. " INTID398 ,Interrupt ID398 Priority/Priority Byte Offset 398 " hexmask.long.byte 0x00 11.--15. 1. " INTID397 ,Interrupt ID397 Priority/Priority Byte Offset 397 " hexmask.long.byte 0x00 3.--7. 1. " INTID396 ,Interrupt ID396 Priority/Priority Byte Offset 396 " group.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hexmask.long.byte 0x00 27.--31. 1. " INTID403 ,Interrupt ID403 Priority/Priority Byte Offset 403 " hexmask.long.byte 0x00 19.--23. 1. " INTID402 ,Interrupt ID402 Priority/Priority Byte Offset 402 " hexmask.long.byte 0x00 11.--15. 1. " INTID401 ,Interrupt ID401 Priority/Priority Byte Offset 401 " hexmask.long.byte 0x00 3.--7. 1. " INTID400 ,Interrupt ID400 Priority/Priority Byte Offset 400 " group.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hexmask.long.byte 0x00 27.--31. 1. " INTID407 ,Interrupt ID407 Priority/Priority Byte Offset 407 " hexmask.long.byte 0x00 19.--23. 1. " INTID406 ,Interrupt ID406 Priority/Priority Byte Offset 406 " hexmask.long.byte 0x00 11.--15. 1. " INTID405 ,Interrupt ID405 Priority/Priority Byte Offset 405 " hexmask.long.byte 0x00 3.--7. 1. " INTID404 ,Interrupt ID404 Priority/Priority Byte Offset 404 " group.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hexmask.long.byte 0x00 27.--31. 1. " INTID411 ,Interrupt ID411 Priority/Priority Byte Offset 411 " hexmask.long.byte 0x00 19.--23. 1. " INTID410 ,Interrupt ID410 Priority/Priority Byte Offset 410 " hexmask.long.byte 0x00 11.--15. 1. " INTID409 ,Interrupt ID409 Priority/Priority Byte Offset 409 " hexmask.long.byte 0x00 3.--7. 1. " INTID408 ,Interrupt ID408 Priority/Priority Byte Offset 408 " group.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" hexmask.long.byte 0x00 27.--31. 1. " INTID415 ,Interrupt ID415 Priority/Priority Byte Offset 415 " hexmask.long.byte 0x00 19.--23. 1. " INTID414 ,Interrupt ID414 Priority/Priority Byte Offset 414 " hexmask.long.byte 0x00 11.--15. 1. " INTID413 ,Interrupt ID413 Priority/Priority Byte Offset 413 " hexmask.long.byte 0x00 3.--7. 1. " INTID412 ,Interrupt ID412 Priority/Priority Byte Offset 412 " else rgroup.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" rgroup.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" rgroup.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" rgroup.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" rgroup.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" rgroup.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" rgroup.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" rgroup.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hexmask.long.byte 0x00 27.--31. 1. " INTID419 ,Interrupt ID419 Priority/Priority Byte Offset 419 " hexmask.long.byte 0x00 19.--23. 1. " INTID418 ,Interrupt ID418 Priority/Priority Byte Offset 418 " hexmask.long.byte 0x00 11.--15. 1. " INTID417 ,Interrupt ID417 Priority/Priority Byte Offset 417 " hexmask.long.byte 0x00 3.--7. 1. " INTID416 ,Interrupt ID416 Priority/Priority Byte Offset 416 " group.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hexmask.long.byte 0x00 27.--31. 1. " INTID423 ,Interrupt ID423 Priority/Priority Byte Offset 423 " hexmask.long.byte 0x00 19.--23. 1. " INTID422 ,Interrupt ID422 Priority/Priority Byte Offset 422 " hexmask.long.byte 0x00 11.--15. 1. " INTID421 ,Interrupt ID421 Priority/Priority Byte Offset 421 " hexmask.long.byte 0x00 3.--7. 1. " INTID420 ,Interrupt ID420 Priority/Priority Byte Offset 420 " group.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hexmask.long.byte 0x00 27.--31. 1. " INTID427 ,Interrupt ID427 Priority/Priority Byte Offset 427 " hexmask.long.byte 0x00 19.--23. 1. " INTID426 ,Interrupt ID426 Priority/Priority Byte Offset 426 " hexmask.long.byte 0x00 11.--15. 1. " INTID425 ,Interrupt ID425 Priority/Priority Byte Offset 425 " hexmask.long.byte 0x00 3.--7. 1. " INTID424 ,Interrupt ID424 Priority/Priority Byte Offset 424 " group.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hexmask.long.byte 0x00 27.--31. 1. " INTID431 ,Interrupt ID431 Priority/Priority Byte Offset 431 " hexmask.long.byte 0x00 19.--23. 1. " INTID430 ,Interrupt ID430 Priority/Priority Byte Offset 430 " hexmask.long.byte 0x00 11.--15. 1. " INTID429 ,Interrupt ID429 Priority/Priority Byte Offset 429 " hexmask.long.byte 0x00 3.--7. 1. " INTID428 ,Interrupt ID428 Priority/Priority Byte Offset 428 " group.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hexmask.long.byte 0x00 27.--31. 1. " INTID435 ,Interrupt ID435 Priority/Priority Byte Offset 435 " hexmask.long.byte 0x00 19.--23. 1. " INTID434 ,Interrupt ID434 Priority/Priority Byte Offset 434 " hexmask.long.byte 0x00 11.--15. 1. " INTID433 ,Interrupt ID433 Priority/Priority Byte Offset 433 " hexmask.long.byte 0x00 3.--7. 1. " INTID432 ,Interrupt ID432 Priority/Priority Byte Offset 432 " group.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hexmask.long.byte 0x00 27.--31. 1. " INTID439 ,Interrupt ID439 Priority/Priority Byte Offset 439 " hexmask.long.byte 0x00 19.--23. 1. " INTID438 ,Interrupt ID438 Priority/Priority Byte Offset 438 " hexmask.long.byte 0x00 11.--15. 1. " INTID437 ,Interrupt ID437 Priority/Priority Byte Offset 437 " hexmask.long.byte 0x00 3.--7. 1. " INTID436 ,Interrupt ID436 Priority/Priority Byte Offset 436 " group.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hexmask.long.byte 0x00 27.--31. 1. " INTID443 ,Interrupt ID443 Priority/Priority Byte Offset 443 " hexmask.long.byte 0x00 19.--23. 1. " INTID442 ,Interrupt ID442 Priority/Priority Byte Offset 442 " hexmask.long.byte 0x00 11.--15. 1. " INTID441 ,Interrupt ID441 Priority/Priority Byte Offset 441 " hexmask.long.byte 0x00 3.--7. 1. " INTID440 ,Interrupt ID440 Priority/Priority Byte Offset 440 " group.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" hexmask.long.byte 0x00 27.--31. 1. " INTID447 ,Interrupt ID447 Priority/Priority Byte Offset 447 " hexmask.long.byte 0x00 19.--23. 1. " INTID446 ,Interrupt ID446 Priority/Priority Byte Offset 446 " hexmask.long.byte 0x00 11.--15. 1. " INTID445 ,Interrupt ID445 Priority/Priority Byte Offset 445 " hexmask.long.byte 0x00 3.--7. 1. " INTID444 ,Interrupt ID444 Priority/Priority Byte Offset 444 " else rgroup.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" rgroup.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" rgroup.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" rgroup.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" rgroup.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" rgroup.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" rgroup.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" rgroup.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hexmask.long.byte 0x00 27.--31. 1. " INTID451 ,Interrupt ID451 Priority/Priority Byte Offset 451 " hexmask.long.byte 0x00 19.--23. 1. " INTID450 ,Interrupt ID450 Priority/Priority Byte Offset 450 " hexmask.long.byte 0x00 11.--15. 1. " INTID449 ,Interrupt ID449 Priority/Priority Byte Offset 449 " hexmask.long.byte 0x00 3.--7. 1. " INTID448 ,Interrupt ID448 Priority/Priority Byte Offset 448 " group.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hexmask.long.byte 0x00 27.--31. 1. " INTID455 ,Interrupt ID455 Priority/Priority Byte Offset 455 " hexmask.long.byte 0x00 19.--23. 1. " INTID454 ,Interrupt ID454 Priority/Priority Byte Offset 454 " hexmask.long.byte 0x00 11.--15. 1. " INTID453 ,Interrupt ID453 Priority/Priority Byte Offset 453 " hexmask.long.byte 0x00 3.--7. 1. " INTID452 ,Interrupt ID452 Priority/Priority Byte Offset 452 " group.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hexmask.long.byte 0x00 27.--31. 1. " INTID459 ,Interrupt ID459 Priority/Priority Byte Offset 459 " hexmask.long.byte 0x00 19.--23. 1. " INTID458 ,Interrupt ID458 Priority/Priority Byte Offset 458 " hexmask.long.byte 0x00 11.--15. 1. " INTID457 ,Interrupt ID457 Priority/Priority Byte Offset 457 " hexmask.long.byte 0x00 3.--7. 1. " INTID456 ,Interrupt ID456 Priority/Priority Byte Offset 456 " group.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hexmask.long.byte 0x00 27.--31. 1. " INTID463 ,Interrupt ID463 Priority/Priority Byte Offset 463 " hexmask.long.byte 0x00 19.--23. 1. " INTID462 ,Interrupt ID462 Priority/Priority Byte Offset 462 " hexmask.long.byte 0x00 11.--15. 1. " INTID461 ,Interrupt ID461 Priority/Priority Byte Offset 461 " hexmask.long.byte 0x00 3.--7. 1. " INTID460 ,Interrupt ID460 Priority/Priority Byte Offset 460 " group.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hexmask.long.byte 0x00 27.--31. 1. " INTID467 ,Interrupt ID467 Priority/Priority Byte Offset 467 " hexmask.long.byte 0x00 19.--23. 1. " INTID466 ,Interrupt ID466 Priority/Priority Byte Offset 466 " hexmask.long.byte 0x00 11.--15. 1. " INTID465 ,Interrupt ID465 Priority/Priority Byte Offset 465 " hexmask.long.byte 0x00 3.--7. 1. " INTID464 ,Interrupt ID464 Priority/Priority Byte Offset 464 " group.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hexmask.long.byte 0x00 27.--31. 1. " INTID471 ,Interrupt ID471 Priority/Priority Byte Offset 471 " hexmask.long.byte 0x00 19.--23. 1. " INTID470 ,Interrupt ID470 Priority/Priority Byte Offset 470 " hexmask.long.byte 0x00 11.--15. 1. " INTID469 ,Interrupt ID469 Priority/Priority Byte Offset 469 " hexmask.long.byte 0x00 3.--7. 1. " INTID468 ,Interrupt ID468 Priority/Priority Byte Offset 468 " group.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hexmask.long.byte 0x00 27.--31. 1. " INTID475 ,Interrupt ID475 Priority/Priority Byte Offset 475 " hexmask.long.byte 0x00 19.--23. 1. " INTID474 ,Interrupt ID474 Priority/Priority Byte Offset 474 " hexmask.long.byte 0x00 11.--15. 1. " INTID473 ,Interrupt ID473 Priority/Priority Byte Offset 473 " hexmask.long.byte 0x00 3.--7. 1. " INTID472 ,Interrupt ID472 Priority/Priority Byte Offset 472 " group.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" hexmask.long.byte 0x00 27.--31. 1. " INTID479 ,Interrupt ID479 Priority/Priority Byte Offset 479 " hexmask.long.byte 0x00 19.--23. 1. " INTID478 ,Interrupt ID478 Priority/Priority Byte Offset 478 " hexmask.long.byte 0x00 11.--15. 1. " INTID477 ,Interrupt ID477 Priority/Priority Byte Offset 477 " hexmask.long.byte 0x00 3.--7. 1. " INTID476 ,Interrupt ID476 Priority/Priority Byte Offset 476 " else rgroup.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" rgroup.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" rgroup.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" rgroup.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" rgroup.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" rgroup.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" rgroup.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" rgroup.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hexmask.long.byte 0x00 27.--31. 1. " INTID483 ,Interrupt ID483 Priority/Priority Byte Offset 483 " hexmask.long.byte 0x00 19.--23. 1. " INTID482 ,Interrupt ID482 Priority/Priority Byte Offset 482 " hexmask.long.byte 0x00 11.--15. 1. " INTID481 ,Interrupt ID481 Priority/Priority Byte Offset 481 " hexmask.long.byte 0x00 3.--7. 1. " INTID480 ,Interrupt ID480 Priority/Priority Byte Offset 480 " group.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hexmask.long.byte 0x00 27.--31. 1. " INTID487 ,Interrupt ID487 Priority/Priority Byte Offset 487 " hexmask.long.byte 0x00 19.--23. 1. " INTID486 ,Interrupt ID486 Priority/Priority Byte Offset 486 " hexmask.long.byte 0x00 11.--15. 1. " INTID485 ,Interrupt ID485 Priority/Priority Byte Offset 485 " hexmask.long.byte 0x00 3.--7. 1. " INTID484 ,Interrupt ID484 Priority/Priority Byte Offset 484 " group.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hexmask.long.byte 0x00 27.--31. 1. " INTID491 ,Interrupt ID491 Priority/Priority Byte Offset 491 " hexmask.long.byte 0x00 19.--23. 1. " INTID490 ,Interrupt ID490 Priority/Priority Byte Offset 490 " hexmask.long.byte 0x00 11.--15. 1. " INTID489 ,Interrupt ID489 Priority/Priority Byte Offset 489 " hexmask.long.byte 0x00 3.--7. 1. " INTID488 ,Interrupt ID488 Priority/Priority Byte Offset 488 " group.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hexmask.long.byte 0x00 27.--31. 1. " INTID495 ,Interrupt ID495 Priority/Priority Byte Offset 495 " hexmask.long.byte 0x00 19.--23. 1. " INTID494 ,Interrupt ID494 Priority/Priority Byte Offset 494 " hexmask.long.byte 0x00 11.--15. 1. " INTID493 ,Interrupt ID493 Priority/Priority Byte Offset 493 " hexmask.long.byte 0x00 3.--7. 1. " INTID492 ,Interrupt ID492 Priority/Priority Byte Offset 492 " group.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hexmask.long.byte 0x00 27.--31. 1. " INTID499 ,Interrupt ID499 Priority/Priority Byte Offset 499 " hexmask.long.byte 0x00 19.--23. 1. " INTID498 ,Interrupt ID498 Priority/Priority Byte Offset 498 " hexmask.long.byte 0x00 11.--15. 1. " INTID497 ,Interrupt ID497 Priority/Priority Byte Offset 497 " hexmask.long.byte 0x00 3.--7. 1. " INTID496 ,Interrupt ID496 Priority/Priority Byte Offset 496 " group.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hexmask.long.byte 0x00 27.--31. 1. " INTID503 ,Interrupt ID503 Priority/Priority Byte Offset 503 " hexmask.long.byte 0x00 19.--23. 1. " INTID502 ,Interrupt ID502 Priority/Priority Byte Offset 502 " hexmask.long.byte 0x00 11.--15. 1. " INTID501 ,Interrupt ID501 Priority/Priority Byte Offset 501 " hexmask.long.byte 0x00 3.--7. 1. " INTID500 ,Interrupt ID500 Priority/Priority Byte Offset 500 " group.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hexmask.long.byte 0x00 27.--31. 1. " INTID507 ,Interrupt ID507 Priority/Priority Byte Offset 507 " hexmask.long.byte 0x00 19.--23. 1. " INTID506 ,Interrupt ID506 Priority/Priority Byte Offset 506 " hexmask.long.byte 0x00 11.--15. 1. " INTID505 ,Interrupt ID505 Priority/Priority Byte Offset 505 " hexmask.long.byte 0x00 3.--7. 1. " INTID504 ,Interrupt ID504 Priority/Priority Byte Offset 504 " group.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" hexmask.long.byte 0x00 27.--31. 1. " INTID511 ,Interrupt ID511 Priority/Priority Byte Offset 511 " hexmask.long.byte 0x00 19.--23. 1. " INTID510 ,Interrupt ID510 Priority/Priority Byte Offset 510 " hexmask.long.byte 0x00 11.--15. 1. " INTID509 ,Interrupt ID509 Priority/Priority Byte Offset 509 " hexmask.long.byte 0x00 3.--7. 1. " INTID508 ,Interrupt ID508 Priority/Priority Byte Offset 508 " else rgroup.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" rgroup.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" rgroup.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" rgroup.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" rgroup.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" rgroup.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" rgroup.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" rgroup.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hexmask.long.byte 0x00 27.--31. 1. " INTID515 ,Interrupt ID515 Priority/Priority Byte Offset 515 " hexmask.long.byte 0x00 19.--23. 1. " INTID514 ,Interrupt ID514 Priority/Priority Byte Offset 514 " hexmask.long.byte 0x00 11.--15. 1. " INTID513 ,Interrupt ID513 Priority/Priority Byte Offset 513 " hexmask.long.byte 0x00 3.--7. 1. " INTID512 ,Interrupt ID512 Priority/Priority Byte Offset 512 " group.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hexmask.long.byte 0x00 27.--31. 1. " INTID519 ,Interrupt ID519 Priority/Priority Byte Offset 519 " hexmask.long.byte 0x00 19.--23. 1. " INTID518 ,Interrupt ID518 Priority/Priority Byte Offset 518 " hexmask.long.byte 0x00 11.--15. 1. " INTID517 ,Interrupt ID517 Priority/Priority Byte Offset 517 " hexmask.long.byte 0x00 3.--7. 1. " INTID516 ,Interrupt ID516 Priority/Priority Byte Offset 516 " group.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hexmask.long.byte 0x00 27.--31. 1. " INTID523 ,Interrupt ID523 Priority/Priority Byte Offset 523 " hexmask.long.byte 0x00 19.--23. 1. " INTID522 ,Interrupt ID522 Priority/Priority Byte Offset 522 " hexmask.long.byte 0x00 11.--15. 1. " INTID521 ,Interrupt ID521 Priority/Priority Byte Offset 521 " hexmask.long.byte 0x00 3.--7. 1. " INTID520 ,Interrupt ID520 Priority/Priority Byte Offset 520 " group.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hexmask.long.byte 0x00 27.--31. 1. " INTID527 ,Interrupt ID527 Priority/Priority Byte Offset 527 " hexmask.long.byte 0x00 19.--23. 1. " INTID526 ,Interrupt ID526 Priority/Priority Byte Offset 526 " hexmask.long.byte 0x00 11.--15. 1. " INTID525 ,Interrupt ID525 Priority/Priority Byte Offset 525 " hexmask.long.byte 0x00 3.--7. 1. " INTID524 ,Interrupt ID524 Priority/Priority Byte Offset 524 " group.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hexmask.long.byte 0x00 27.--31. 1. " INTID531 ,Interrupt ID531 Priority/Priority Byte Offset 531 " hexmask.long.byte 0x00 19.--23. 1. " INTID530 ,Interrupt ID530 Priority/Priority Byte Offset 530 " hexmask.long.byte 0x00 11.--15. 1. " INTID529 ,Interrupt ID529 Priority/Priority Byte Offset 529 " hexmask.long.byte 0x00 3.--7. 1. " INTID528 ,Interrupt ID528 Priority/Priority Byte Offset 528 " group.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hexmask.long.byte 0x00 27.--31. 1. " INTID535 ,Interrupt ID535 Priority/Priority Byte Offset 535 " hexmask.long.byte 0x00 19.--23. 1. " INTID534 ,Interrupt ID534 Priority/Priority Byte Offset 534 " hexmask.long.byte 0x00 11.--15. 1. " INTID533 ,Interrupt ID533 Priority/Priority Byte Offset 533 " hexmask.long.byte 0x00 3.--7. 1. " INTID532 ,Interrupt ID532 Priority/Priority Byte Offset 532 " group.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hexmask.long.byte 0x00 27.--31. 1. " INTID539 ,Interrupt ID539 Priority/Priority Byte Offset 539 " hexmask.long.byte 0x00 19.--23. 1. " INTID538 ,Interrupt ID538 Priority/Priority Byte Offset 538 " hexmask.long.byte 0x00 11.--15. 1. " INTID537 ,Interrupt ID537 Priority/Priority Byte Offset 537 " hexmask.long.byte 0x00 3.--7. 1. " INTID536 ,Interrupt ID536 Priority/Priority Byte Offset 536 " group.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" hexmask.long.byte 0x00 27.--31. 1. " INTID543 ,Interrupt ID543 Priority/Priority Byte Offset 543 " hexmask.long.byte 0x00 19.--23. 1. " INTID542 ,Interrupt ID542 Priority/Priority Byte Offset 542 " hexmask.long.byte 0x00 11.--15. 1. " INTID541 ,Interrupt ID541 Priority/Priority Byte Offset 541 " hexmask.long.byte 0x00 3.--7. 1. " INTID540 ,Interrupt ID540 Priority/Priority Byte Offset 540 " else rgroup.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" rgroup.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" rgroup.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" rgroup.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" rgroup.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" rgroup.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" rgroup.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" rgroup.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hexmask.long.byte 0x00 27.--31. 1. " INTID547 ,Interrupt ID547 Priority/Priority Byte Offset 547 " hexmask.long.byte 0x00 19.--23. 1. " INTID546 ,Interrupt ID546 Priority/Priority Byte Offset 546 " hexmask.long.byte 0x00 11.--15. 1. " INTID545 ,Interrupt ID545 Priority/Priority Byte Offset 545 " hexmask.long.byte 0x00 3.--7. 1. " INTID544 ,Interrupt ID544 Priority/Priority Byte Offset 544 " group.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hexmask.long.byte 0x00 27.--31. 1. " INTID551 ,Interrupt ID551 Priority/Priority Byte Offset 551 " hexmask.long.byte 0x00 19.--23. 1. " INTID550 ,Interrupt ID550 Priority/Priority Byte Offset 550 " hexmask.long.byte 0x00 11.--15. 1. " INTID549 ,Interrupt ID549 Priority/Priority Byte Offset 549 " hexmask.long.byte 0x00 3.--7. 1. " INTID548 ,Interrupt ID548 Priority/Priority Byte Offset 548 " group.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hexmask.long.byte 0x00 27.--31. 1. " INTID555 ,Interrupt ID555 Priority/Priority Byte Offset 555 " hexmask.long.byte 0x00 19.--23. 1. " INTID554 ,Interrupt ID554 Priority/Priority Byte Offset 554 " hexmask.long.byte 0x00 11.--15. 1. " INTID553 ,Interrupt ID553 Priority/Priority Byte Offset 553 " hexmask.long.byte 0x00 3.--7. 1. " INTID552 ,Interrupt ID552 Priority/Priority Byte Offset 552 " group.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hexmask.long.byte 0x00 27.--31. 1. " INTID559 ,Interrupt ID559 Priority/Priority Byte Offset 559 " hexmask.long.byte 0x00 19.--23. 1. " INTID558 ,Interrupt ID558 Priority/Priority Byte Offset 558 " hexmask.long.byte 0x00 11.--15. 1. " INTID557 ,Interrupt ID557 Priority/Priority Byte Offset 557 " hexmask.long.byte 0x00 3.--7. 1. " INTID556 ,Interrupt ID556 Priority/Priority Byte Offset 556 " group.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hexmask.long.byte 0x00 27.--31. 1. " INTID563 ,Interrupt ID563 Priority/Priority Byte Offset 563 " hexmask.long.byte 0x00 19.--23. 1. " INTID562 ,Interrupt ID562 Priority/Priority Byte Offset 562 " hexmask.long.byte 0x00 11.--15. 1. " INTID561 ,Interrupt ID561 Priority/Priority Byte Offset 561 " hexmask.long.byte 0x00 3.--7. 1. " INTID560 ,Interrupt ID560 Priority/Priority Byte Offset 560 " group.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hexmask.long.byte 0x00 27.--31. 1. " INTID567 ,Interrupt ID567 Priority/Priority Byte Offset 567 " hexmask.long.byte 0x00 19.--23. 1. " INTID566 ,Interrupt ID566 Priority/Priority Byte Offset 566 " hexmask.long.byte 0x00 11.--15. 1. " INTID565 ,Interrupt ID565 Priority/Priority Byte Offset 565 " hexmask.long.byte 0x00 3.--7. 1. " INTID564 ,Interrupt ID564 Priority/Priority Byte Offset 564 " group.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hexmask.long.byte 0x00 27.--31. 1. " INTID571 ,Interrupt ID571 Priority/Priority Byte Offset 571 " hexmask.long.byte 0x00 19.--23. 1. " INTID570 ,Interrupt ID570 Priority/Priority Byte Offset 570 " hexmask.long.byte 0x00 11.--15. 1. " INTID569 ,Interrupt ID569 Priority/Priority Byte Offset 569 " hexmask.long.byte 0x00 3.--7. 1. " INTID568 ,Interrupt ID568 Priority/Priority Byte Offset 568 " group.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" hexmask.long.byte 0x00 27.--31. 1. " INTID575 ,Interrupt ID575 Priority/Priority Byte Offset 575 " hexmask.long.byte 0x00 19.--23. 1. " INTID574 ,Interrupt ID574 Priority/Priority Byte Offset 574 " hexmask.long.byte 0x00 11.--15. 1. " INTID573 ,Interrupt ID573 Priority/Priority Byte Offset 573 " hexmask.long.byte 0x00 3.--7. 1. " INTID572 ,Interrupt ID572 Priority/Priority Byte Offset 572 " else rgroup.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" rgroup.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" rgroup.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" rgroup.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" rgroup.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" rgroup.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" rgroup.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" rgroup.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hexmask.long.byte 0x00 27.--31. 1. " INTID579 ,Interrupt ID579 Priority/Priority Byte Offset 579 " hexmask.long.byte 0x00 19.--23. 1. " INTID578 ,Interrupt ID578 Priority/Priority Byte Offset 578 " hexmask.long.byte 0x00 11.--15. 1. " INTID577 ,Interrupt ID577 Priority/Priority Byte Offset 577 " hexmask.long.byte 0x00 3.--7. 1. " INTID576 ,Interrupt ID576 Priority/Priority Byte Offset 576 " group.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hexmask.long.byte 0x00 27.--31. 1. " INTID583 ,Interrupt ID583 Priority/Priority Byte Offset 583 " hexmask.long.byte 0x00 19.--23. 1. " INTID582 ,Interrupt ID582 Priority/Priority Byte Offset 582 " hexmask.long.byte 0x00 11.--15. 1. " INTID581 ,Interrupt ID581 Priority/Priority Byte Offset 581 " hexmask.long.byte 0x00 3.--7. 1. " INTID580 ,Interrupt ID580 Priority/Priority Byte Offset 580 " group.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hexmask.long.byte 0x00 27.--31. 1. " INTID587 ,Interrupt ID587 Priority/Priority Byte Offset 587 " hexmask.long.byte 0x00 19.--23. 1. " INTID586 ,Interrupt ID586 Priority/Priority Byte Offset 586 " hexmask.long.byte 0x00 11.--15. 1. " INTID585 ,Interrupt ID585 Priority/Priority Byte Offset 585 " hexmask.long.byte 0x00 3.--7. 1. " INTID584 ,Interrupt ID584 Priority/Priority Byte Offset 584 " group.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hexmask.long.byte 0x00 27.--31. 1. " INTID591 ,Interrupt ID591 Priority/Priority Byte Offset 591 " hexmask.long.byte 0x00 19.--23. 1. " INTID590 ,Interrupt ID590 Priority/Priority Byte Offset 590 " hexmask.long.byte 0x00 11.--15. 1. " INTID589 ,Interrupt ID589 Priority/Priority Byte Offset 589 " hexmask.long.byte 0x00 3.--7. 1. " INTID588 ,Interrupt ID588 Priority/Priority Byte Offset 588 " group.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hexmask.long.byte 0x00 27.--31. 1. " INTID595 ,Interrupt ID595 Priority/Priority Byte Offset 595 " hexmask.long.byte 0x00 19.--23. 1. " INTID594 ,Interrupt ID594 Priority/Priority Byte Offset 594 " hexmask.long.byte 0x00 11.--15. 1. " INTID593 ,Interrupt ID593 Priority/Priority Byte Offset 593 " hexmask.long.byte 0x00 3.--7. 1. " INTID592 ,Interrupt ID592 Priority/Priority Byte Offset 592 " group.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hexmask.long.byte 0x00 27.--31. 1. " INTID599 ,Interrupt ID599 Priority/Priority Byte Offset 599 " hexmask.long.byte 0x00 19.--23. 1. " INTID598 ,Interrupt ID598 Priority/Priority Byte Offset 598 " hexmask.long.byte 0x00 11.--15. 1. " INTID597 ,Interrupt ID597 Priority/Priority Byte Offset 597 " hexmask.long.byte 0x00 3.--7. 1. " INTID596 ,Interrupt ID596 Priority/Priority Byte Offset 596 " group.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hexmask.long.byte 0x00 27.--31. 1. " INTID603 ,Interrupt ID603 Priority/Priority Byte Offset 603 " hexmask.long.byte 0x00 19.--23. 1. " INTID602 ,Interrupt ID602 Priority/Priority Byte Offset 602 " hexmask.long.byte 0x00 11.--15. 1. " INTID601 ,Interrupt ID601 Priority/Priority Byte Offset 601 " hexmask.long.byte 0x00 3.--7. 1. " INTID600 ,Interrupt ID600 Priority/Priority Byte Offset 600 " group.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" hexmask.long.byte 0x00 27.--31. 1. " INTID607 ,Interrupt ID607 Priority/Priority Byte Offset 607 " hexmask.long.byte 0x00 19.--23. 1. " INTID606 ,Interrupt ID606 Priority/Priority Byte Offset 606 " hexmask.long.byte 0x00 11.--15. 1. " INTID605 ,Interrupt ID605 Priority/Priority Byte Offset 605 " hexmask.long.byte 0x00 3.--7. 1. " INTID604 ,Interrupt ID604 Priority/Priority Byte Offset 604 " else rgroup.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" rgroup.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" rgroup.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" rgroup.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" rgroup.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" rgroup.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" rgroup.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" rgroup.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hexmask.long.byte 0x00 27.--31. 1. " INTID611 ,Interrupt ID611 Priority/Priority Byte Offset 611 " hexmask.long.byte 0x00 19.--23. 1. " INTID610 ,Interrupt ID610 Priority/Priority Byte Offset 610 " hexmask.long.byte 0x00 11.--15. 1. " INTID609 ,Interrupt ID609 Priority/Priority Byte Offset 609 " hexmask.long.byte 0x00 3.--7. 1. " INTID608 ,Interrupt ID608 Priority/Priority Byte Offset 608 " group.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hexmask.long.byte 0x00 27.--31. 1. " INTID615 ,Interrupt ID615 Priority/Priority Byte Offset 615 " hexmask.long.byte 0x00 19.--23. 1. " INTID614 ,Interrupt ID614 Priority/Priority Byte Offset 614 " hexmask.long.byte 0x00 11.--15. 1. " INTID613 ,Interrupt ID613 Priority/Priority Byte Offset 613 " hexmask.long.byte 0x00 3.--7. 1. " INTID612 ,Interrupt ID612 Priority/Priority Byte Offset 612 " group.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hexmask.long.byte 0x00 27.--31. 1. " INTID619 ,Interrupt ID619 Priority/Priority Byte Offset 619 " hexmask.long.byte 0x00 19.--23. 1. " INTID618 ,Interrupt ID618 Priority/Priority Byte Offset 618 " hexmask.long.byte 0x00 11.--15. 1. " INTID617 ,Interrupt ID617 Priority/Priority Byte Offset 617 " hexmask.long.byte 0x00 3.--7. 1. " INTID616 ,Interrupt ID616 Priority/Priority Byte Offset 616 " group.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hexmask.long.byte 0x00 27.--31. 1. " INTID623 ,Interrupt ID623 Priority/Priority Byte Offset 623 " hexmask.long.byte 0x00 19.--23. 1. " INTID622 ,Interrupt ID622 Priority/Priority Byte Offset 622 " hexmask.long.byte 0x00 11.--15. 1. " INTID621 ,Interrupt ID621 Priority/Priority Byte Offset 621 " hexmask.long.byte 0x00 3.--7. 1. " INTID620 ,Interrupt ID620 Priority/Priority Byte Offset 620 " group.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hexmask.long.byte 0x00 27.--31. 1. " INTID627 ,Interrupt ID627 Priority/Priority Byte Offset 627 " hexmask.long.byte 0x00 19.--23. 1. " INTID626 ,Interrupt ID626 Priority/Priority Byte Offset 626 " hexmask.long.byte 0x00 11.--15. 1. " INTID625 ,Interrupt ID625 Priority/Priority Byte Offset 625 " hexmask.long.byte 0x00 3.--7. 1. " INTID624 ,Interrupt ID624 Priority/Priority Byte Offset 624 " group.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hexmask.long.byte 0x00 27.--31. 1. " INTID631 ,Interrupt ID631 Priority/Priority Byte Offset 631 " hexmask.long.byte 0x00 19.--23. 1. " INTID630 ,Interrupt ID630 Priority/Priority Byte Offset 630 " hexmask.long.byte 0x00 11.--15. 1. " INTID629 ,Interrupt ID629 Priority/Priority Byte Offset 629 " hexmask.long.byte 0x00 3.--7. 1. " INTID628 ,Interrupt ID628 Priority/Priority Byte Offset 628 " group.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hexmask.long.byte 0x00 27.--31. 1. " INTID635 ,Interrupt ID635 Priority/Priority Byte Offset 635 " hexmask.long.byte 0x00 19.--23. 1. " INTID634 ,Interrupt ID634 Priority/Priority Byte Offset 634 " hexmask.long.byte 0x00 11.--15. 1. " INTID633 ,Interrupt ID633 Priority/Priority Byte Offset 633 " hexmask.long.byte 0x00 3.--7. 1. " INTID632 ,Interrupt ID632 Priority/Priority Byte Offset 632 " group.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" hexmask.long.byte 0x00 27.--31. 1. " INTID639 ,Interrupt ID639 Priority/Priority Byte Offset 639 " hexmask.long.byte 0x00 19.--23. 1. " INTID638 ,Interrupt ID638 Priority/Priority Byte Offset 638 " hexmask.long.byte 0x00 11.--15. 1. " INTID637 ,Interrupt ID637 Priority/Priority Byte Offset 637 " hexmask.long.byte 0x00 3.--7. 1. " INTID636 ,Interrupt ID636 Priority/Priority Byte Offset 636 " else rgroup.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" rgroup.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" rgroup.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" rgroup.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" rgroup.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" rgroup.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" rgroup.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" rgroup.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hexmask.long.byte 0x00 27.--31. 1. " INTID643 ,Interrupt ID643 Priority/Priority Byte Offset 643 " hexmask.long.byte 0x00 19.--23. 1. " INTID642 ,Interrupt ID642 Priority/Priority Byte Offset 642 " hexmask.long.byte 0x00 11.--15. 1. " INTID641 ,Interrupt ID641 Priority/Priority Byte Offset 641 " hexmask.long.byte 0x00 3.--7. 1. " INTID640 ,Interrupt ID640 Priority/Priority Byte Offset 640 " group.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hexmask.long.byte 0x00 27.--31. 1. " INTID647 ,Interrupt ID647 Priority/Priority Byte Offset 647 " hexmask.long.byte 0x00 19.--23. 1. " INTID646 ,Interrupt ID646 Priority/Priority Byte Offset 646 " hexmask.long.byte 0x00 11.--15. 1. " INTID645 ,Interrupt ID645 Priority/Priority Byte Offset 645 " hexmask.long.byte 0x00 3.--7. 1. " INTID644 ,Interrupt ID644 Priority/Priority Byte Offset 644 " group.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hexmask.long.byte 0x00 27.--31. 1. " INTID651 ,Interrupt ID651 Priority/Priority Byte Offset 651 " hexmask.long.byte 0x00 19.--23. 1. " INTID650 ,Interrupt ID650 Priority/Priority Byte Offset 650 " hexmask.long.byte 0x00 11.--15. 1. " INTID649 ,Interrupt ID649 Priority/Priority Byte Offset 649 " hexmask.long.byte 0x00 3.--7. 1. " INTID648 ,Interrupt ID648 Priority/Priority Byte Offset 648 " group.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hexmask.long.byte 0x00 27.--31. 1. " INTID655 ,Interrupt ID655 Priority/Priority Byte Offset 655 " hexmask.long.byte 0x00 19.--23. 1. " INTID654 ,Interrupt ID654 Priority/Priority Byte Offset 654 " hexmask.long.byte 0x00 11.--15. 1. " INTID653 ,Interrupt ID653 Priority/Priority Byte Offset 653 " hexmask.long.byte 0x00 3.--7. 1. " INTID652 ,Interrupt ID652 Priority/Priority Byte Offset 652 " group.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hexmask.long.byte 0x00 27.--31. 1. " INTID659 ,Interrupt ID659 Priority/Priority Byte Offset 659 " hexmask.long.byte 0x00 19.--23. 1. " INTID658 ,Interrupt ID658 Priority/Priority Byte Offset 658 " hexmask.long.byte 0x00 11.--15. 1. " INTID657 ,Interrupt ID657 Priority/Priority Byte Offset 657 " hexmask.long.byte 0x00 3.--7. 1. " INTID656 ,Interrupt ID656 Priority/Priority Byte Offset 656 " group.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hexmask.long.byte 0x00 27.--31. 1. " INTID663 ,Interrupt ID663 Priority/Priority Byte Offset 663 " hexmask.long.byte 0x00 19.--23. 1. " INTID662 ,Interrupt ID662 Priority/Priority Byte Offset 662 " hexmask.long.byte 0x00 11.--15. 1. " INTID661 ,Interrupt ID661 Priority/Priority Byte Offset 661 " hexmask.long.byte 0x00 3.--7. 1. " INTID660 ,Interrupt ID660 Priority/Priority Byte Offset 660 " group.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hexmask.long.byte 0x00 27.--31. 1. " INTID667 ,Interrupt ID667 Priority/Priority Byte Offset 667 " hexmask.long.byte 0x00 19.--23. 1. " INTID666 ,Interrupt ID666 Priority/Priority Byte Offset 666 " hexmask.long.byte 0x00 11.--15. 1. " INTID665 ,Interrupt ID665 Priority/Priority Byte Offset 665 " hexmask.long.byte 0x00 3.--7. 1. " INTID664 ,Interrupt ID664 Priority/Priority Byte Offset 664 " group.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" hexmask.long.byte 0x00 27.--31. 1. " INTID671 ,Interrupt ID671 Priority/Priority Byte Offset 671 " hexmask.long.byte 0x00 19.--23. 1. " INTID670 ,Interrupt ID670 Priority/Priority Byte Offset 670 " hexmask.long.byte 0x00 11.--15. 1. " INTID669 ,Interrupt ID669 Priority/Priority Byte Offset 669 " hexmask.long.byte 0x00 3.--7. 1. " INTID668 ,Interrupt ID668 Priority/Priority Byte Offset 668 " else rgroup.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" rgroup.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" rgroup.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" rgroup.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" rgroup.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" rgroup.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" rgroup.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" rgroup.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hexmask.long.byte 0x00 27.--31. 1. " INTID675 ,Interrupt ID675 Priority/Priority Byte Offset 675 " hexmask.long.byte 0x00 19.--23. 1. " INTID674 ,Interrupt ID674 Priority/Priority Byte Offset 674 " hexmask.long.byte 0x00 11.--15. 1. " INTID673 ,Interrupt ID673 Priority/Priority Byte Offset 673 " hexmask.long.byte 0x00 3.--7. 1. " INTID672 ,Interrupt ID672 Priority/Priority Byte Offset 672 " group.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hexmask.long.byte 0x00 27.--31. 1. " INTID679 ,Interrupt ID679 Priority/Priority Byte Offset 679 " hexmask.long.byte 0x00 19.--23. 1. " INTID678 ,Interrupt ID678 Priority/Priority Byte Offset 678 " hexmask.long.byte 0x00 11.--15. 1. " INTID677 ,Interrupt ID677 Priority/Priority Byte Offset 677 " hexmask.long.byte 0x00 3.--7. 1. " INTID676 ,Interrupt ID676 Priority/Priority Byte Offset 676 " group.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hexmask.long.byte 0x00 27.--31. 1. " INTID683 ,Interrupt ID683 Priority/Priority Byte Offset 683 " hexmask.long.byte 0x00 19.--23. 1. " INTID682 ,Interrupt ID682 Priority/Priority Byte Offset 682 " hexmask.long.byte 0x00 11.--15. 1. " INTID681 ,Interrupt ID681 Priority/Priority Byte Offset 681 " hexmask.long.byte 0x00 3.--7. 1. " INTID680 ,Interrupt ID680 Priority/Priority Byte Offset 680 " group.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hexmask.long.byte 0x00 27.--31. 1. " INTID687 ,Interrupt ID687 Priority/Priority Byte Offset 687 " hexmask.long.byte 0x00 19.--23. 1. " INTID686 ,Interrupt ID686 Priority/Priority Byte Offset 686 " hexmask.long.byte 0x00 11.--15. 1. " INTID685 ,Interrupt ID685 Priority/Priority Byte Offset 685 " hexmask.long.byte 0x00 3.--7. 1. " INTID684 ,Interrupt ID684 Priority/Priority Byte Offset 684 " group.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hexmask.long.byte 0x00 27.--31. 1. " INTID691 ,Interrupt ID691 Priority/Priority Byte Offset 691 " hexmask.long.byte 0x00 19.--23. 1. " INTID690 ,Interrupt ID690 Priority/Priority Byte Offset 690 " hexmask.long.byte 0x00 11.--15. 1. " INTID689 ,Interrupt ID689 Priority/Priority Byte Offset 689 " hexmask.long.byte 0x00 3.--7. 1. " INTID688 ,Interrupt ID688 Priority/Priority Byte Offset 688 " group.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hexmask.long.byte 0x00 27.--31. 1. " INTID695 ,Interrupt ID695 Priority/Priority Byte Offset 695 " hexmask.long.byte 0x00 19.--23. 1. " INTID694 ,Interrupt ID694 Priority/Priority Byte Offset 694 " hexmask.long.byte 0x00 11.--15. 1. " INTID693 ,Interrupt ID693 Priority/Priority Byte Offset 693 " hexmask.long.byte 0x00 3.--7. 1. " INTID692 ,Interrupt ID692 Priority/Priority Byte Offset 692 " group.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hexmask.long.byte 0x00 27.--31. 1. " INTID699 ,Interrupt ID699 Priority/Priority Byte Offset 699 " hexmask.long.byte 0x00 19.--23. 1. " INTID698 ,Interrupt ID698 Priority/Priority Byte Offset 698 " hexmask.long.byte 0x00 11.--15. 1. " INTID697 ,Interrupt ID697 Priority/Priority Byte Offset 697 " hexmask.long.byte 0x00 3.--7. 1. " INTID696 ,Interrupt ID696 Priority/Priority Byte Offset 696 " group.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" hexmask.long.byte 0x00 27.--31. 1. " INTID703 ,Interrupt ID703 Priority/Priority Byte Offset 703 " hexmask.long.byte 0x00 19.--23. 1. " INTID702 ,Interrupt ID702 Priority/Priority Byte Offset 702 " hexmask.long.byte 0x00 11.--15. 1. " INTID701 ,Interrupt ID701 Priority/Priority Byte Offset 701 " hexmask.long.byte 0x00 3.--7. 1. " INTID700 ,Interrupt ID700 Priority/Priority Byte Offset 700 " else rgroup.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" rgroup.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" rgroup.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" rgroup.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" rgroup.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" rgroup.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" rgroup.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" rgroup.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hexmask.long.byte 0x00 27.--31. 1. " INTID707 ,Interrupt ID707 Priority/Priority Byte Offset 707 " hexmask.long.byte 0x00 19.--23. 1. " INTID706 ,Interrupt ID706 Priority/Priority Byte Offset 706 " hexmask.long.byte 0x00 11.--15. 1. " INTID705 ,Interrupt ID705 Priority/Priority Byte Offset 705 " hexmask.long.byte 0x00 3.--7. 1. " INTID704 ,Interrupt ID704 Priority/Priority Byte Offset 704 " group.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hexmask.long.byte 0x00 27.--31. 1. " INTID711 ,Interrupt ID711 Priority/Priority Byte Offset 711 " hexmask.long.byte 0x00 19.--23. 1. " INTID710 ,Interrupt ID710 Priority/Priority Byte Offset 710 " hexmask.long.byte 0x00 11.--15. 1. " INTID709 ,Interrupt ID709 Priority/Priority Byte Offset 709 " hexmask.long.byte 0x00 3.--7. 1. " INTID708 ,Interrupt ID708 Priority/Priority Byte Offset 708 " group.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hexmask.long.byte 0x00 27.--31. 1. " INTID715 ,Interrupt ID715 Priority/Priority Byte Offset 715 " hexmask.long.byte 0x00 19.--23. 1. " INTID714 ,Interrupt ID714 Priority/Priority Byte Offset 714 " hexmask.long.byte 0x00 11.--15. 1. " INTID713 ,Interrupt ID713 Priority/Priority Byte Offset 713 " hexmask.long.byte 0x00 3.--7. 1. " INTID712 ,Interrupt ID712 Priority/Priority Byte Offset 712 " group.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hexmask.long.byte 0x00 27.--31. 1. " INTID719 ,Interrupt ID719 Priority/Priority Byte Offset 719 " hexmask.long.byte 0x00 19.--23. 1. " INTID718 ,Interrupt ID718 Priority/Priority Byte Offset 718 " hexmask.long.byte 0x00 11.--15. 1. " INTID717 ,Interrupt ID717 Priority/Priority Byte Offset 717 " hexmask.long.byte 0x00 3.--7. 1. " INTID716 ,Interrupt ID716 Priority/Priority Byte Offset 716 " group.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hexmask.long.byte 0x00 27.--31. 1. " INTID723 ,Interrupt ID723 Priority/Priority Byte Offset 723 " hexmask.long.byte 0x00 19.--23. 1. " INTID722 ,Interrupt ID722 Priority/Priority Byte Offset 722 " hexmask.long.byte 0x00 11.--15. 1. " INTID721 ,Interrupt ID721 Priority/Priority Byte Offset 721 " hexmask.long.byte 0x00 3.--7. 1. " INTID720 ,Interrupt ID720 Priority/Priority Byte Offset 720 " group.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hexmask.long.byte 0x00 27.--31. 1. " INTID727 ,Interrupt ID727 Priority/Priority Byte Offset 727 " hexmask.long.byte 0x00 19.--23. 1. " INTID726 ,Interrupt ID726 Priority/Priority Byte Offset 726 " hexmask.long.byte 0x00 11.--15. 1. " INTID725 ,Interrupt ID725 Priority/Priority Byte Offset 725 " hexmask.long.byte 0x00 3.--7. 1. " INTID724 ,Interrupt ID724 Priority/Priority Byte Offset 724 " group.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hexmask.long.byte 0x00 27.--31. 1. " INTID731 ,Interrupt ID731 Priority/Priority Byte Offset 731 " hexmask.long.byte 0x00 19.--23. 1. " INTID730 ,Interrupt ID730 Priority/Priority Byte Offset 730 " hexmask.long.byte 0x00 11.--15. 1. " INTID729 ,Interrupt ID729 Priority/Priority Byte Offset 729 " hexmask.long.byte 0x00 3.--7. 1. " INTID728 ,Interrupt ID728 Priority/Priority Byte Offset 728 " group.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" hexmask.long.byte 0x00 27.--31. 1. " INTID735 ,Interrupt ID735 Priority/Priority Byte Offset 735 " hexmask.long.byte 0x00 19.--23. 1. " INTID734 ,Interrupt ID734 Priority/Priority Byte Offset 734 " hexmask.long.byte 0x00 11.--15. 1. " INTID733 ,Interrupt ID733 Priority/Priority Byte Offset 733 " hexmask.long.byte 0x00 3.--7. 1. " INTID732 ,Interrupt ID732 Priority/Priority Byte Offset 732 " else rgroup.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" rgroup.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" rgroup.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" rgroup.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" rgroup.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" rgroup.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" rgroup.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" rgroup.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hexmask.long.byte 0x00 27.--31. 1. " INTID739 ,Interrupt ID739 Priority/Priority Byte Offset 739 " hexmask.long.byte 0x00 19.--23. 1. " INTID738 ,Interrupt ID738 Priority/Priority Byte Offset 738 " hexmask.long.byte 0x00 11.--15. 1. " INTID737 ,Interrupt ID737 Priority/Priority Byte Offset 737 " hexmask.long.byte 0x00 3.--7. 1. " INTID736 ,Interrupt ID736 Priority/Priority Byte Offset 736 " group.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hexmask.long.byte 0x00 27.--31. 1. " INTID743 ,Interrupt ID743 Priority/Priority Byte Offset 743 " hexmask.long.byte 0x00 19.--23. 1. " INTID742 ,Interrupt ID742 Priority/Priority Byte Offset 742 " hexmask.long.byte 0x00 11.--15. 1. " INTID741 ,Interrupt ID741 Priority/Priority Byte Offset 741 " hexmask.long.byte 0x00 3.--7. 1. " INTID740 ,Interrupt ID740 Priority/Priority Byte Offset 740 " group.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hexmask.long.byte 0x00 27.--31. 1. " INTID747 ,Interrupt ID747 Priority/Priority Byte Offset 747 " hexmask.long.byte 0x00 19.--23. 1. " INTID746 ,Interrupt ID746 Priority/Priority Byte Offset 746 " hexmask.long.byte 0x00 11.--15. 1. " INTID745 ,Interrupt ID745 Priority/Priority Byte Offset 745 " hexmask.long.byte 0x00 3.--7. 1. " INTID744 ,Interrupt ID744 Priority/Priority Byte Offset 744 " group.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hexmask.long.byte 0x00 27.--31. 1. " INTID751 ,Interrupt ID751 Priority/Priority Byte Offset 751 " hexmask.long.byte 0x00 19.--23. 1. " INTID750 ,Interrupt ID750 Priority/Priority Byte Offset 750 " hexmask.long.byte 0x00 11.--15. 1. " INTID749 ,Interrupt ID749 Priority/Priority Byte Offset 749 " hexmask.long.byte 0x00 3.--7. 1. " INTID748 ,Interrupt ID748 Priority/Priority Byte Offset 748 " group.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hexmask.long.byte 0x00 27.--31. 1. " INTID755 ,Interrupt ID755 Priority/Priority Byte Offset 755 " hexmask.long.byte 0x00 19.--23. 1. " INTID754 ,Interrupt ID754 Priority/Priority Byte Offset 754 " hexmask.long.byte 0x00 11.--15. 1. " INTID753 ,Interrupt ID753 Priority/Priority Byte Offset 753 " hexmask.long.byte 0x00 3.--7. 1. " INTID752 ,Interrupt ID752 Priority/Priority Byte Offset 752 " group.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hexmask.long.byte 0x00 27.--31. 1. " INTID759 ,Interrupt ID759 Priority/Priority Byte Offset 759 " hexmask.long.byte 0x00 19.--23. 1. " INTID758 ,Interrupt ID758 Priority/Priority Byte Offset 758 " hexmask.long.byte 0x00 11.--15. 1. " INTID757 ,Interrupt ID757 Priority/Priority Byte Offset 757 " hexmask.long.byte 0x00 3.--7. 1. " INTID756 ,Interrupt ID756 Priority/Priority Byte Offset 756 " group.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hexmask.long.byte 0x00 27.--31. 1. " INTID763 ,Interrupt ID763 Priority/Priority Byte Offset 763 " hexmask.long.byte 0x00 19.--23. 1. " INTID762 ,Interrupt ID762 Priority/Priority Byte Offset 762 " hexmask.long.byte 0x00 11.--15. 1. " INTID761 ,Interrupt ID761 Priority/Priority Byte Offset 761 " hexmask.long.byte 0x00 3.--7. 1. " INTID760 ,Interrupt ID760 Priority/Priority Byte Offset 760 " group.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" hexmask.long.byte 0x00 27.--31. 1. " INTID767 ,Interrupt ID767 Priority/Priority Byte Offset 767 " hexmask.long.byte 0x00 19.--23. 1. " INTID766 ,Interrupt ID766 Priority/Priority Byte Offset 766 " hexmask.long.byte 0x00 11.--15. 1. " INTID765 ,Interrupt ID765 Priority/Priority Byte Offset 765 " hexmask.long.byte 0x00 3.--7. 1. " INTID764 ,Interrupt ID764 Priority/Priority Byte Offset 764 " else rgroup.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" rgroup.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" rgroup.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" rgroup.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" rgroup.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" rgroup.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" rgroup.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" rgroup.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hexmask.long.byte 0x00 27.--31. 1. " INTID771 ,Interrupt ID771 Priority/Priority Byte Offset 771 " hexmask.long.byte 0x00 19.--23. 1. " INTID770 ,Interrupt ID770 Priority/Priority Byte Offset 770 " hexmask.long.byte 0x00 11.--15. 1. " INTID769 ,Interrupt ID769 Priority/Priority Byte Offset 769 " hexmask.long.byte 0x00 3.--7. 1. " INTID768 ,Interrupt ID768 Priority/Priority Byte Offset 768 " group.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hexmask.long.byte 0x00 27.--31. 1. " INTID775 ,Interrupt ID775 Priority/Priority Byte Offset 775 " hexmask.long.byte 0x00 19.--23. 1. " INTID774 ,Interrupt ID774 Priority/Priority Byte Offset 774 " hexmask.long.byte 0x00 11.--15. 1. " INTID773 ,Interrupt ID773 Priority/Priority Byte Offset 773 " hexmask.long.byte 0x00 3.--7. 1. " INTID772 ,Interrupt ID772 Priority/Priority Byte Offset 772 " group.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hexmask.long.byte 0x00 27.--31. 1. " INTID779 ,Interrupt ID779 Priority/Priority Byte Offset 779 " hexmask.long.byte 0x00 19.--23. 1. " INTID778 ,Interrupt ID778 Priority/Priority Byte Offset 778 " hexmask.long.byte 0x00 11.--15. 1. " INTID777 ,Interrupt ID777 Priority/Priority Byte Offset 777 " hexmask.long.byte 0x00 3.--7. 1. " INTID776 ,Interrupt ID776 Priority/Priority Byte Offset 776 " group.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hexmask.long.byte 0x00 27.--31. 1. " INTID783 ,Interrupt ID783 Priority/Priority Byte Offset 783 " hexmask.long.byte 0x00 19.--23. 1. " INTID782 ,Interrupt ID782 Priority/Priority Byte Offset 782 " hexmask.long.byte 0x00 11.--15. 1. " INTID781 ,Interrupt ID781 Priority/Priority Byte Offset 781 " hexmask.long.byte 0x00 3.--7. 1. " INTID780 ,Interrupt ID780 Priority/Priority Byte Offset 780 " group.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hexmask.long.byte 0x00 27.--31. 1. " INTID787 ,Interrupt ID787 Priority/Priority Byte Offset 787 " hexmask.long.byte 0x00 19.--23. 1. " INTID786 ,Interrupt ID786 Priority/Priority Byte Offset 786 " hexmask.long.byte 0x00 11.--15. 1. " INTID785 ,Interrupt ID785 Priority/Priority Byte Offset 785 " hexmask.long.byte 0x00 3.--7. 1. " INTID784 ,Interrupt ID784 Priority/Priority Byte Offset 784 " group.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hexmask.long.byte 0x00 27.--31. 1. " INTID791 ,Interrupt ID791 Priority/Priority Byte Offset 791 " hexmask.long.byte 0x00 19.--23. 1. " INTID790 ,Interrupt ID790 Priority/Priority Byte Offset 790 " hexmask.long.byte 0x00 11.--15. 1. " INTID789 ,Interrupt ID789 Priority/Priority Byte Offset 789 " hexmask.long.byte 0x00 3.--7. 1. " INTID788 ,Interrupt ID788 Priority/Priority Byte Offset 788 " group.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hexmask.long.byte 0x00 27.--31. 1. " INTID795 ,Interrupt ID795 Priority/Priority Byte Offset 795 " hexmask.long.byte 0x00 19.--23. 1. " INTID794 ,Interrupt ID794 Priority/Priority Byte Offset 794 " hexmask.long.byte 0x00 11.--15. 1. " INTID793 ,Interrupt ID793 Priority/Priority Byte Offset 793 " hexmask.long.byte 0x00 3.--7. 1. " INTID792 ,Interrupt ID792 Priority/Priority Byte Offset 792 " group.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" hexmask.long.byte 0x00 27.--31. 1. " INTID799 ,Interrupt ID799 Priority/Priority Byte Offset 799 " hexmask.long.byte 0x00 19.--23. 1. " INTID798 ,Interrupt ID798 Priority/Priority Byte Offset 798 " hexmask.long.byte 0x00 11.--15. 1. " INTID797 ,Interrupt ID797 Priority/Priority Byte Offset 797 " hexmask.long.byte 0x00 3.--7. 1. " INTID796 ,Interrupt ID796 Priority/Priority Byte Offset 796 " else rgroup.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" rgroup.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" rgroup.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" rgroup.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" rgroup.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" rgroup.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" rgroup.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" rgroup.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hexmask.long.byte 0x00 27.--31. 1. " INTID803 ,Interrupt ID803 Priority/Priority Byte Offset 803 " hexmask.long.byte 0x00 19.--23. 1. " INTID802 ,Interrupt ID802 Priority/Priority Byte Offset 802 " hexmask.long.byte 0x00 11.--15. 1. " INTID801 ,Interrupt ID801 Priority/Priority Byte Offset 801 " hexmask.long.byte 0x00 3.--7. 1. " INTID800 ,Interrupt ID800 Priority/Priority Byte Offset 800 " group.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hexmask.long.byte 0x00 27.--31. 1. " INTID807 ,Interrupt ID807 Priority/Priority Byte Offset 807 " hexmask.long.byte 0x00 19.--23. 1. " INTID806 ,Interrupt ID806 Priority/Priority Byte Offset 806 " hexmask.long.byte 0x00 11.--15. 1. " INTID805 ,Interrupt ID805 Priority/Priority Byte Offset 805 " hexmask.long.byte 0x00 3.--7. 1. " INTID804 ,Interrupt ID804 Priority/Priority Byte Offset 804 " group.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hexmask.long.byte 0x00 27.--31. 1. " INTID811 ,Interrupt ID811 Priority/Priority Byte Offset 811 " hexmask.long.byte 0x00 19.--23. 1. " INTID810 ,Interrupt ID810 Priority/Priority Byte Offset 810 " hexmask.long.byte 0x00 11.--15. 1. " INTID809 ,Interrupt ID809 Priority/Priority Byte Offset 809 " hexmask.long.byte 0x00 3.--7. 1. " INTID808 ,Interrupt ID808 Priority/Priority Byte Offset 808 " group.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hexmask.long.byte 0x00 27.--31. 1. " INTID815 ,Interrupt ID815 Priority/Priority Byte Offset 815 " hexmask.long.byte 0x00 19.--23. 1. " INTID814 ,Interrupt ID814 Priority/Priority Byte Offset 814 " hexmask.long.byte 0x00 11.--15. 1. " INTID813 ,Interrupt ID813 Priority/Priority Byte Offset 813 " hexmask.long.byte 0x00 3.--7. 1. " INTID812 ,Interrupt ID812 Priority/Priority Byte Offset 812 " group.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hexmask.long.byte 0x00 27.--31. 1. " INTID819 ,Interrupt ID819 Priority/Priority Byte Offset 819 " hexmask.long.byte 0x00 19.--23. 1. " INTID818 ,Interrupt ID818 Priority/Priority Byte Offset 818 " hexmask.long.byte 0x00 11.--15. 1. " INTID817 ,Interrupt ID817 Priority/Priority Byte Offset 817 " hexmask.long.byte 0x00 3.--7. 1. " INTID816 ,Interrupt ID816 Priority/Priority Byte Offset 816 " group.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hexmask.long.byte 0x00 27.--31. 1. " INTID823 ,Interrupt ID823 Priority/Priority Byte Offset 823 " hexmask.long.byte 0x00 19.--23. 1. " INTID822 ,Interrupt ID822 Priority/Priority Byte Offset 822 " hexmask.long.byte 0x00 11.--15. 1. " INTID821 ,Interrupt ID821 Priority/Priority Byte Offset 821 " hexmask.long.byte 0x00 3.--7. 1. " INTID820 ,Interrupt ID820 Priority/Priority Byte Offset 820 " group.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hexmask.long.byte 0x00 27.--31. 1. " INTID827 ,Interrupt ID827 Priority/Priority Byte Offset 827 " hexmask.long.byte 0x00 19.--23. 1. " INTID826 ,Interrupt ID826 Priority/Priority Byte Offset 826 " hexmask.long.byte 0x00 11.--15. 1. " INTID825 ,Interrupt ID825 Priority/Priority Byte Offset 825 " hexmask.long.byte 0x00 3.--7. 1. " INTID824 ,Interrupt ID824 Priority/Priority Byte Offset 824 " group.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" hexmask.long.byte 0x00 27.--31. 1. " INTID831 ,Interrupt ID831 Priority/Priority Byte Offset 831 " hexmask.long.byte 0x00 19.--23. 1. " INTID830 ,Interrupt ID830 Priority/Priority Byte Offset 830 " hexmask.long.byte 0x00 11.--15. 1. " INTID829 ,Interrupt ID829 Priority/Priority Byte Offset 829 " hexmask.long.byte 0x00 3.--7. 1. " INTID828 ,Interrupt ID828 Priority/Priority Byte Offset 828 " else rgroup.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" rgroup.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" rgroup.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" rgroup.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" rgroup.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" rgroup.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" rgroup.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" rgroup.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hexmask.long.byte 0x00 27.--31. 1. " INTID835 ,Interrupt ID835 Priority/Priority Byte Offset 835 " hexmask.long.byte 0x00 19.--23. 1. " INTID834 ,Interrupt ID834 Priority/Priority Byte Offset 834 " hexmask.long.byte 0x00 11.--15. 1. " INTID833 ,Interrupt ID833 Priority/Priority Byte Offset 833 " hexmask.long.byte 0x00 3.--7. 1. " INTID832 ,Interrupt ID832 Priority/Priority Byte Offset 832 " group.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hexmask.long.byte 0x00 27.--31. 1. " INTID839 ,Interrupt ID839 Priority/Priority Byte Offset 839 " hexmask.long.byte 0x00 19.--23. 1. " INTID838 ,Interrupt ID838 Priority/Priority Byte Offset 838 " hexmask.long.byte 0x00 11.--15. 1. " INTID837 ,Interrupt ID837 Priority/Priority Byte Offset 837 " hexmask.long.byte 0x00 3.--7. 1. " INTID836 ,Interrupt ID836 Priority/Priority Byte Offset 836 " group.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hexmask.long.byte 0x00 27.--31. 1. " INTID843 ,Interrupt ID843 Priority/Priority Byte Offset 843 " hexmask.long.byte 0x00 19.--23. 1. " INTID842 ,Interrupt ID842 Priority/Priority Byte Offset 842 " hexmask.long.byte 0x00 11.--15. 1. " INTID841 ,Interrupt ID841 Priority/Priority Byte Offset 841 " hexmask.long.byte 0x00 3.--7. 1. " INTID840 ,Interrupt ID840 Priority/Priority Byte Offset 840 " group.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hexmask.long.byte 0x00 27.--31. 1. " INTID847 ,Interrupt ID847 Priority/Priority Byte Offset 847 " hexmask.long.byte 0x00 19.--23. 1. " INTID846 ,Interrupt ID846 Priority/Priority Byte Offset 846 " hexmask.long.byte 0x00 11.--15. 1. " INTID845 ,Interrupt ID845 Priority/Priority Byte Offset 845 " hexmask.long.byte 0x00 3.--7. 1. " INTID844 ,Interrupt ID844 Priority/Priority Byte Offset 844 " group.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hexmask.long.byte 0x00 27.--31. 1. " INTID851 ,Interrupt ID851 Priority/Priority Byte Offset 851 " hexmask.long.byte 0x00 19.--23. 1. " INTID850 ,Interrupt ID850 Priority/Priority Byte Offset 850 " hexmask.long.byte 0x00 11.--15. 1. " INTID849 ,Interrupt ID849 Priority/Priority Byte Offset 849 " hexmask.long.byte 0x00 3.--7. 1. " INTID848 ,Interrupt ID848 Priority/Priority Byte Offset 848 " group.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hexmask.long.byte 0x00 27.--31. 1. " INTID855 ,Interrupt ID855 Priority/Priority Byte Offset 855 " hexmask.long.byte 0x00 19.--23. 1. " INTID854 ,Interrupt ID854 Priority/Priority Byte Offset 854 " hexmask.long.byte 0x00 11.--15. 1. " INTID853 ,Interrupt ID853 Priority/Priority Byte Offset 853 " hexmask.long.byte 0x00 3.--7. 1. " INTID852 ,Interrupt ID852 Priority/Priority Byte Offset 852 " group.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hexmask.long.byte 0x00 27.--31. 1. " INTID859 ,Interrupt ID859 Priority/Priority Byte Offset 859 " hexmask.long.byte 0x00 19.--23. 1. " INTID858 ,Interrupt ID858 Priority/Priority Byte Offset 858 " hexmask.long.byte 0x00 11.--15. 1. " INTID857 ,Interrupt ID857 Priority/Priority Byte Offset 857 " hexmask.long.byte 0x00 3.--7. 1. " INTID856 ,Interrupt ID856 Priority/Priority Byte Offset 856 " group.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" hexmask.long.byte 0x00 27.--31. 1. " INTID863 ,Interrupt ID863 Priority/Priority Byte Offset 863 " hexmask.long.byte 0x00 19.--23. 1. " INTID862 ,Interrupt ID862 Priority/Priority Byte Offset 862 " hexmask.long.byte 0x00 11.--15. 1. " INTID861 ,Interrupt ID861 Priority/Priority Byte Offset 861 " hexmask.long.byte 0x00 3.--7. 1. " INTID860 ,Interrupt ID860 Priority/Priority Byte Offset 860 " else rgroup.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" rgroup.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" rgroup.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" rgroup.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" rgroup.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" rgroup.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" rgroup.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" rgroup.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hexmask.long.byte 0x00 27.--31. 1. " INTID867 ,Interrupt ID867 Priority/Priority Byte Offset 867 " hexmask.long.byte 0x00 19.--23. 1. " INTID866 ,Interrupt ID866 Priority/Priority Byte Offset 866 " hexmask.long.byte 0x00 11.--15. 1. " INTID865 ,Interrupt ID865 Priority/Priority Byte Offset 865 " hexmask.long.byte 0x00 3.--7. 1. " INTID864 ,Interrupt ID864 Priority/Priority Byte Offset 864 " group.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hexmask.long.byte 0x00 27.--31. 1. " INTID871 ,Interrupt ID871 Priority/Priority Byte Offset 871 " hexmask.long.byte 0x00 19.--23. 1. " INTID870 ,Interrupt ID870 Priority/Priority Byte Offset 870 " hexmask.long.byte 0x00 11.--15. 1. " INTID869 ,Interrupt ID869 Priority/Priority Byte Offset 869 " hexmask.long.byte 0x00 3.--7. 1. " INTID868 ,Interrupt ID868 Priority/Priority Byte Offset 868 " group.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hexmask.long.byte 0x00 27.--31. 1. " INTID875 ,Interrupt ID875 Priority/Priority Byte Offset 875 " hexmask.long.byte 0x00 19.--23. 1. " INTID874 ,Interrupt ID874 Priority/Priority Byte Offset 874 " hexmask.long.byte 0x00 11.--15. 1. " INTID873 ,Interrupt ID873 Priority/Priority Byte Offset 873 " hexmask.long.byte 0x00 3.--7. 1. " INTID872 ,Interrupt ID872 Priority/Priority Byte Offset 872 " group.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hexmask.long.byte 0x00 27.--31. 1. " INTID879 ,Interrupt ID879 Priority/Priority Byte Offset 879 " hexmask.long.byte 0x00 19.--23. 1. " INTID878 ,Interrupt ID878 Priority/Priority Byte Offset 878 " hexmask.long.byte 0x00 11.--15. 1. " INTID877 ,Interrupt ID877 Priority/Priority Byte Offset 877 " hexmask.long.byte 0x00 3.--7. 1. " INTID876 ,Interrupt ID876 Priority/Priority Byte Offset 876 " group.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hexmask.long.byte 0x00 27.--31. 1. " INTID883 ,Interrupt ID883 Priority/Priority Byte Offset 883 " hexmask.long.byte 0x00 19.--23. 1. " INTID882 ,Interrupt ID882 Priority/Priority Byte Offset 882 " hexmask.long.byte 0x00 11.--15. 1. " INTID881 ,Interrupt ID881 Priority/Priority Byte Offset 881 " hexmask.long.byte 0x00 3.--7. 1. " INTID880 ,Interrupt ID880 Priority/Priority Byte Offset 880 " group.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hexmask.long.byte 0x00 27.--31. 1. " INTID887 ,Interrupt ID887 Priority/Priority Byte Offset 887 " hexmask.long.byte 0x00 19.--23. 1. " INTID886 ,Interrupt ID886 Priority/Priority Byte Offset 886 " hexmask.long.byte 0x00 11.--15. 1. " INTID885 ,Interrupt ID885 Priority/Priority Byte Offset 885 " hexmask.long.byte 0x00 3.--7. 1. " INTID884 ,Interrupt ID884 Priority/Priority Byte Offset 884 " group.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hexmask.long.byte 0x00 27.--31. 1. " INTID891 ,Interrupt ID891 Priority/Priority Byte Offset 891 " hexmask.long.byte 0x00 19.--23. 1. " INTID890 ,Interrupt ID890 Priority/Priority Byte Offset 890 " hexmask.long.byte 0x00 11.--15. 1. " INTID889 ,Interrupt ID889 Priority/Priority Byte Offset 889 " hexmask.long.byte 0x00 3.--7. 1. " INTID888 ,Interrupt ID888 Priority/Priority Byte Offset 888 " group.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" hexmask.long.byte 0x00 27.--31. 1. " INTID895 ,Interrupt ID895 Priority/Priority Byte Offset 895 " hexmask.long.byte 0x00 19.--23. 1. " INTID894 ,Interrupt ID894 Priority/Priority Byte Offset 894 " hexmask.long.byte 0x00 11.--15. 1. " INTID893 ,Interrupt ID893 Priority/Priority Byte Offset 893 " hexmask.long.byte 0x00 3.--7. 1. " INTID892 ,Interrupt ID892 Priority/Priority Byte Offset 892 " else rgroup.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" rgroup.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" rgroup.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" rgroup.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" rgroup.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" rgroup.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" rgroup.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" rgroup.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hexmask.long.byte 0x00 27.--31. 1. " INTID899 ,Interrupt ID899 Priority/Priority Byte Offset 899 " hexmask.long.byte 0x00 19.--23. 1. " INTID898 ,Interrupt ID898 Priority/Priority Byte Offset 898 " hexmask.long.byte 0x00 11.--15. 1. " INTID897 ,Interrupt ID897 Priority/Priority Byte Offset 897 " hexmask.long.byte 0x00 3.--7. 1. " INTID896 ,Interrupt ID896 Priority/Priority Byte Offset 896 " group.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hexmask.long.byte 0x00 27.--31. 1. " INTID903 ,Interrupt ID903 Priority/Priority Byte Offset 903 " hexmask.long.byte 0x00 19.--23. 1. " INTID902 ,Interrupt ID902 Priority/Priority Byte Offset 902 " hexmask.long.byte 0x00 11.--15. 1. " INTID901 ,Interrupt ID901 Priority/Priority Byte Offset 901 " hexmask.long.byte 0x00 3.--7. 1. " INTID900 ,Interrupt ID900 Priority/Priority Byte Offset 900 " group.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hexmask.long.byte 0x00 27.--31. 1. " INTID907 ,Interrupt ID907 Priority/Priority Byte Offset 907 " hexmask.long.byte 0x00 19.--23. 1. " INTID906 ,Interrupt ID906 Priority/Priority Byte Offset 906 " hexmask.long.byte 0x00 11.--15. 1. " INTID905 ,Interrupt ID905 Priority/Priority Byte Offset 905 " hexmask.long.byte 0x00 3.--7. 1. " INTID904 ,Interrupt ID904 Priority/Priority Byte Offset 904 " group.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hexmask.long.byte 0x00 27.--31. 1. " INTID911 ,Interrupt ID911 Priority/Priority Byte Offset 911 " hexmask.long.byte 0x00 19.--23. 1. " INTID910 ,Interrupt ID910 Priority/Priority Byte Offset 910 " hexmask.long.byte 0x00 11.--15. 1. " INTID909 ,Interrupt ID909 Priority/Priority Byte Offset 909 " hexmask.long.byte 0x00 3.--7. 1. " INTID908 ,Interrupt ID908 Priority/Priority Byte Offset 908 " group.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hexmask.long.byte 0x00 27.--31. 1. " INTID915 ,Interrupt ID915 Priority/Priority Byte Offset 915 " hexmask.long.byte 0x00 19.--23. 1. " INTID914 ,Interrupt ID914 Priority/Priority Byte Offset 914 " hexmask.long.byte 0x00 11.--15. 1. " INTID913 ,Interrupt ID913 Priority/Priority Byte Offset 913 " hexmask.long.byte 0x00 3.--7. 1. " INTID912 ,Interrupt ID912 Priority/Priority Byte Offset 912 " group.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hexmask.long.byte 0x00 27.--31. 1. " INTID919 ,Interrupt ID919 Priority/Priority Byte Offset 919 " hexmask.long.byte 0x00 19.--23. 1. " INTID918 ,Interrupt ID918 Priority/Priority Byte Offset 918 " hexmask.long.byte 0x00 11.--15. 1. " INTID917 ,Interrupt ID917 Priority/Priority Byte Offset 917 " hexmask.long.byte 0x00 3.--7. 1. " INTID916 ,Interrupt ID916 Priority/Priority Byte Offset 916 " group.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hexmask.long.byte 0x00 27.--31. 1. " INTID923 ,Interrupt ID923 Priority/Priority Byte Offset 923 " hexmask.long.byte 0x00 19.--23. 1. " INTID922 ,Interrupt ID922 Priority/Priority Byte Offset 922 " hexmask.long.byte 0x00 11.--15. 1. " INTID921 ,Interrupt ID921 Priority/Priority Byte Offset 921 " hexmask.long.byte 0x00 3.--7. 1. " INTID920 ,Interrupt ID920 Priority/Priority Byte Offset 920 " group.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" hexmask.long.byte 0x00 27.--31. 1. " INTID927 ,Interrupt ID927 Priority/Priority Byte Offset 927 " hexmask.long.byte 0x00 19.--23. 1. " INTID926 ,Interrupt ID926 Priority/Priority Byte Offset 926 " hexmask.long.byte 0x00 11.--15. 1. " INTID925 ,Interrupt ID925 Priority/Priority Byte Offset 925 " hexmask.long.byte 0x00 3.--7. 1. " INTID924 ,Interrupt ID924 Priority/Priority Byte Offset 924 " else rgroup.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" rgroup.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" rgroup.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" rgroup.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" rgroup.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" rgroup.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" rgroup.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" rgroup.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hexmask.long.byte 0x00 27.--31. 1. " INTID931 ,Interrupt ID931 Priority/Priority Byte Offset 931 " hexmask.long.byte 0x00 19.--23. 1. " INTID930 ,Interrupt ID930 Priority/Priority Byte Offset 930 " hexmask.long.byte 0x00 11.--15. 1. " INTID929 ,Interrupt ID929 Priority/Priority Byte Offset 929 " hexmask.long.byte 0x00 3.--7. 1. " INTID928 ,Interrupt ID928 Priority/Priority Byte Offset 928 " group.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hexmask.long.byte 0x00 27.--31. 1. " INTID935 ,Interrupt ID935 Priority/Priority Byte Offset 935 " hexmask.long.byte 0x00 19.--23. 1. " INTID934 ,Interrupt ID934 Priority/Priority Byte Offset 934 " hexmask.long.byte 0x00 11.--15. 1. " INTID933 ,Interrupt ID933 Priority/Priority Byte Offset 933 " hexmask.long.byte 0x00 3.--7. 1. " INTID932 ,Interrupt ID932 Priority/Priority Byte Offset 932 " group.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hexmask.long.byte 0x00 27.--31. 1. " INTID939 ,Interrupt ID939 Priority/Priority Byte Offset 939 " hexmask.long.byte 0x00 19.--23. 1. " INTID938 ,Interrupt ID938 Priority/Priority Byte Offset 938 " hexmask.long.byte 0x00 11.--15. 1. " INTID937 ,Interrupt ID937 Priority/Priority Byte Offset 937 " hexmask.long.byte 0x00 3.--7. 1. " INTID936 ,Interrupt ID936 Priority/Priority Byte Offset 936 " group.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hexmask.long.byte 0x00 27.--31. 1. " INTID943 ,Interrupt ID943 Priority/Priority Byte Offset 943 " hexmask.long.byte 0x00 19.--23. 1. " INTID942 ,Interrupt ID942 Priority/Priority Byte Offset 942 " hexmask.long.byte 0x00 11.--15. 1. " INTID941 ,Interrupt ID941 Priority/Priority Byte Offset 941 " hexmask.long.byte 0x00 3.--7. 1. " INTID940 ,Interrupt ID940 Priority/Priority Byte Offset 940 " group.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hexmask.long.byte 0x00 27.--31. 1. " INTID947 ,Interrupt ID947 Priority/Priority Byte Offset 947 " hexmask.long.byte 0x00 19.--23. 1. " INTID946 ,Interrupt ID946 Priority/Priority Byte Offset 946 " hexmask.long.byte 0x00 11.--15. 1. " INTID945 ,Interrupt ID945 Priority/Priority Byte Offset 945 " hexmask.long.byte 0x00 3.--7. 1. " INTID944 ,Interrupt ID944 Priority/Priority Byte Offset 944 " group.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hexmask.long.byte 0x00 27.--31. 1. " INTID951 ,Interrupt ID951 Priority/Priority Byte Offset 951 " hexmask.long.byte 0x00 19.--23. 1. " INTID950 ,Interrupt ID950 Priority/Priority Byte Offset 950 " hexmask.long.byte 0x00 11.--15. 1. " INTID949 ,Interrupt ID949 Priority/Priority Byte Offset 949 " hexmask.long.byte 0x00 3.--7. 1. " INTID948 ,Interrupt ID948 Priority/Priority Byte Offset 948 " group.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hexmask.long.byte 0x00 27.--31. 1. " INTID955 ,Interrupt ID955 Priority/Priority Byte Offset 955 " hexmask.long.byte 0x00 19.--23. 1. " INTID954 ,Interrupt ID954 Priority/Priority Byte Offset 954 " hexmask.long.byte 0x00 11.--15. 1. " INTID953 ,Interrupt ID953 Priority/Priority Byte Offset 953 " hexmask.long.byte 0x00 3.--7. 1. " INTID952 ,Interrupt ID952 Priority/Priority Byte Offset 952 " group.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" hexmask.long.byte 0x00 27.--31. 1. " INTID959 ,Interrupt ID959 Priority/Priority Byte Offset 959 " hexmask.long.byte 0x00 19.--23. 1. " INTID958 ,Interrupt ID958 Priority/Priority Byte Offset 958 " hexmask.long.byte 0x00 11.--15. 1. " INTID957 ,Interrupt ID957 Priority/Priority Byte Offset 957 " hexmask.long.byte 0x00 3.--7. 1. " INTID956 ,Interrupt ID956 Priority/Priority Byte Offset 956 " else rgroup.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" rgroup.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" rgroup.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" rgroup.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" rgroup.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" rgroup.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" rgroup.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" rgroup.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hexmask.long.byte 0x00 27.--31. 1. " INTID963 ,Interrupt ID963 Priority/Priority Byte Offset 963 " hexmask.long.byte 0x00 19.--23. 1. " INTID962 ,Interrupt ID962 Priority/Priority Byte Offset 962 " hexmask.long.byte 0x00 11.--15. 1. " INTID961 ,Interrupt ID961 Priority/Priority Byte Offset 961 " hexmask.long.byte 0x00 3.--7. 1. " INTID960 ,Interrupt ID960 Priority/Priority Byte Offset 960 " group.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hexmask.long.byte 0x00 27.--31. 1. " INTID967 ,Interrupt ID967 Priority/Priority Byte Offset 967 " hexmask.long.byte 0x00 19.--23. 1. " INTID966 ,Interrupt ID966 Priority/Priority Byte Offset 966 " hexmask.long.byte 0x00 11.--15. 1. " INTID965 ,Interrupt ID965 Priority/Priority Byte Offset 965 " hexmask.long.byte 0x00 3.--7. 1. " INTID964 ,Interrupt ID964 Priority/Priority Byte Offset 964 " group.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hexmask.long.byte 0x00 27.--31. 1. " INTID971 ,Interrupt ID971 Priority/Priority Byte Offset 971 " hexmask.long.byte 0x00 19.--23. 1. " INTID970 ,Interrupt ID970 Priority/Priority Byte Offset 970 " hexmask.long.byte 0x00 11.--15. 1. " INTID969 ,Interrupt ID969 Priority/Priority Byte Offset 969 " hexmask.long.byte 0x00 3.--7. 1. " INTID968 ,Interrupt ID968 Priority/Priority Byte Offset 968 " group.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hexmask.long.byte 0x00 27.--31. 1. " INTID975 ,Interrupt ID975 Priority/Priority Byte Offset 975 " hexmask.long.byte 0x00 19.--23. 1. " INTID974 ,Interrupt ID974 Priority/Priority Byte Offset 974 " hexmask.long.byte 0x00 11.--15. 1. " INTID973 ,Interrupt ID973 Priority/Priority Byte Offset 973 " hexmask.long.byte 0x00 3.--7. 1. " INTID972 ,Interrupt ID972 Priority/Priority Byte Offset 972 " group.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hexmask.long.byte 0x00 27.--31. 1. " INTID979 ,Interrupt ID979 Priority/Priority Byte Offset 979 " hexmask.long.byte 0x00 19.--23. 1. " INTID978 ,Interrupt ID978 Priority/Priority Byte Offset 978 " hexmask.long.byte 0x00 11.--15. 1. " INTID977 ,Interrupt ID977 Priority/Priority Byte Offset 977 " hexmask.long.byte 0x00 3.--7. 1. " INTID976 ,Interrupt ID976 Priority/Priority Byte Offset 976 " group.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hexmask.long.byte 0x00 27.--31. 1. " INTID983 ,Interrupt ID983 Priority/Priority Byte Offset 983 " hexmask.long.byte 0x00 19.--23. 1. " INTID982 ,Interrupt ID982 Priority/Priority Byte Offset 982 " hexmask.long.byte 0x00 11.--15. 1. " INTID981 ,Interrupt ID981 Priority/Priority Byte Offset 981 " hexmask.long.byte 0x00 3.--7. 1. " INTID980 ,Interrupt ID980 Priority/Priority Byte Offset 980 " group.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hexmask.long.byte 0x00 27.--31. 1. " INTID987 ,Interrupt ID987 Priority/Priority Byte Offset 987 " hexmask.long.byte 0x00 19.--23. 1. " INTID986 ,Interrupt ID986 Priority/Priority Byte Offset 986 " hexmask.long.byte 0x00 11.--15. 1. " INTID985 ,Interrupt ID985 Priority/Priority Byte Offset 985 " hexmask.long.byte 0x00 3.--7. 1. " INTID984 ,Interrupt ID984 Priority/Priority Byte Offset 984 " group.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" hexmask.long.byte 0x00 27.--31. 1. " INTID991 ,Interrupt ID991 Priority/Priority Byte Offset 991 " hexmask.long.byte 0x00 19.--23. 1. " INTID990 ,Interrupt ID990 Priority/Priority Byte Offset 990 " hexmask.long.byte 0x00 11.--15. 1. " INTID989 ,Interrupt ID989 Priority/Priority Byte Offset 989 " hexmask.long.byte 0x00 3.--7. 1. " INTID988 ,Interrupt ID988 Priority/Priority Byte Offset 988 " else rgroup.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" rgroup.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" rgroup.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" rgroup.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" rgroup.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" rgroup.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" rgroup.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" rgroup.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" endif tree.end width 14. tree "Configuration Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1) group.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" rgroup.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2) group.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" rgroup.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3) group.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" rgroup.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4) group.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" rgroup.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5) group.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" rgroup.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6) group.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" rgroup.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7) group.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" rgroup.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8) group.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" rgroup.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9) group.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" rgroup.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA) group.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" rgroup.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB) group.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" rgroup.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC) group.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" rgroup.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD) group.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" rgroup.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE) group.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" rgroup.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF) group.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" rgroup.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" rgroup.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" rgroup.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" rgroup.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" rgroup.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" rgroup.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" rgroup.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" rgroup.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" rgroup.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" rgroup.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" rgroup.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" rgroup.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" rgroup.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" rgroup.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" rgroup.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" rgroup.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" endif tree.end width 24. tree "Interrupt Routing Registers" group.quad 0x6100++0x07 line.quad 0x00 "GICD_IROUTER32,Interrupt Routing Register 32" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6108++0x07 line.quad 0x00 "GICD_IROUTER33,Interrupt Routing Register 33" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6110++0x07 line.quad 0x00 "GICD_IROUTER34,Interrupt Routing Register 34" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6118++0x07 line.quad 0x00 "GICD_IROUTER35,Interrupt Routing Register 35" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6120++0x07 line.quad 0x00 "GICD_IROUTER36,Interrupt Routing Register 36" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6128++0x07 line.quad 0x00 "GICD_IROUTER37,Interrupt Routing Register 37" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6130++0x07 line.quad 0x00 "GICD_IROUTER38,Interrupt Routing Register 38" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6138++0x07 line.quad 0x00 "GICD_IROUTER39,Interrupt Routing Register 39" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6140++0x07 line.quad 0x00 "GICD_IROUTER40,Interrupt Routing Register 40" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6148++0x07 line.quad 0x00 "GICD_IROUTER41,Interrupt Routing Register 41" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6150++0x07 line.quad 0x00 "GICD_IROUTER42,Interrupt Routing Register 42" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6158++0x07 line.quad 0x00 "GICD_IROUTER43,Interrupt Routing Register 43" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6160++0x07 line.quad 0x00 "GICD_IROUTER44,Interrupt Routing Register 44" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6168++0x07 line.quad 0x00 "GICD_IROUTER45,Interrupt Routing Register 45" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6170++0x07 line.quad 0x00 "GICD_IROUTER46,Interrupt Routing Register 46" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6178++0x07 line.quad 0x00 "GICD_IROUTER47,Interrupt Routing Register 47" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6180++0x07 line.quad 0x00 "GICD_IROUTER48,Interrupt Routing Register 48" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6188++0x07 line.quad 0x00 "GICD_IROUTER49,Interrupt Routing Register 49" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6190++0x07 line.quad 0x00 "GICD_IROUTER50,Interrupt Routing Register 50" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6198++0x07 line.quad 0x00 "GICD_IROUTER51,Interrupt Routing Register 51" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61A0++0x07 line.quad 0x00 "GICD_IROUTER52,Interrupt Routing Register 52" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61A8++0x07 line.quad 0x00 "GICD_IROUTER53,Interrupt Routing Register 53" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61B0++0x07 line.quad 0x00 "GICD_IROUTER54,Interrupt Routing Register 54" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61B8++0x07 line.quad 0x00 "GICD_IROUTER55,Interrupt Routing Register 55" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61C0++0x07 line.quad 0x00 "GICD_IROUTER56,Interrupt Routing Register 56" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61C8++0x07 line.quad 0x00 "GICD_IROUTER57,Interrupt Routing Register 57" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61D0++0x07 line.quad 0x00 "GICD_IROUTER58,Interrupt Routing Register 58" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61D8++0x07 line.quad 0x00 "GICD_IROUTER59,Interrupt Routing Register 59" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61E0++0x07 line.quad 0x00 "GICD_IROUTER60,Interrupt Routing Register 60" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61E8++0x07 line.quad 0x00 "GICD_IROUTER61,Interrupt Routing Register 61" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61F0++0x07 line.quad 0x00 "GICD_IROUTER62,Interrupt Routing Register 62" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61F8++0x07 line.quad 0x00 "GICD_IROUTER63,Interrupt Routing Register 63" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6200++0x07 line.quad 0x00 "GICD_IROUTER64,Interrupt Routing Register 64" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6208++0x07 line.quad 0x00 "GICD_IROUTER65,Interrupt Routing Register 65" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6210++0x07 line.quad 0x00 "GICD_IROUTER66,Interrupt Routing Register 66" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6218++0x07 line.quad 0x00 "GICD_IROUTER67,Interrupt Routing Register 67" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6220++0x07 line.quad 0x00 "GICD_IROUTER68,Interrupt Routing Register 68" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6228++0x07 line.quad 0x00 "GICD_IROUTER69,Interrupt Routing Register 69" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6230++0x07 line.quad 0x00 "GICD_IROUTER70,Interrupt Routing Register 70" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6238++0x07 line.quad 0x00 "GICD_IROUTER71,Interrupt Routing Register 71" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6240++0x07 line.quad 0x00 "GICD_IROUTER72,Interrupt Routing Register 72" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6248++0x07 line.quad 0x00 "GICD_IROUTER73,Interrupt Routing Register 73" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6250++0x07 line.quad 0x00 "GICD_IROUTER74,Interrupt Routing Register 74" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6258++0x07 line.quad 0x00 "GICD_IROUTER75,Interrupt Routing Register 75" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6260++0x07 line.quad 0x00 "GICD_IROUTER76,Interrupt Routing Register 76" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6268++0x07 line.quad 0x00 "GICD_IROUTER77,Interrupt Routing Register 77" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6270++0x07 line.quad 0x00 "GICD_IROUTER78,Interrupt Routing Register 78" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6278++0x07 line.quad 0x00 "GICD_IROUTER79,Interrupt Routing Register 79" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6280++0x07 line.quad 0x00 "GICD_IROUTER80,Interrupt Routing Register 80" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6288++0x07 line.quad 0x00 "GICD_IROUTER81,Interrupt Routing Register 81" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6290++0x07 line.quad 0x00 "GICD_IROUTER82,Interrupt Routing Register 82" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6298++0x07 line.quad 0x00 "GICD_IROUTER83,Interrupt Routing Register 83" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62A0++0x07 line.quad 0x00 "GICD_IROUTER84,Interrupt Routing Register 84" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62A8++0x07 line.quad 0x00 "GICD_IROUTER85,Interrupt Routing Register 85" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62B0++0x07 line.quad 0x00 "GICD_IROUTER86,Interrupt Routing Register 86" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62B8++0x07 line.quad 0x00 "GICD_IROUTER87,Interrupt Routing Register 87" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62C0++0x07 line.quad 0x00 "GICD_IROUTER88,Interrupt Routing Register 88" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62C8++0x07 line.quad 0x00 "GICD_IROUTER89,Interrupt Routing Register 89" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62D0++0x07 line.quad 0x00 "GICD_IROUTER90,Interrupt Routing Register 90" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62D8++0x07 line.quad 0x00 "GICD_IROUTER91,Interrupt Routing Register 91" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62E0++0x07 line.quad 0x00 "GICD_IROUTER92,Interrupt Routing Register 92" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62E8++0x07 line.quad 0x00 "GICD_IROUTER93,Interrupt Routing Register 93" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62F0++0x07 line.quad 0x00 "GICD_IROUTER94,Interrupt Routing Register 94" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62F8++0x07 line.quad 0x00 "GICD_IROUTER95,Interrupt Routing Register 95" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6300++0x07 line.quad 0x00 "GICD_IROUTER96,Interrupt Routing Register 96" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6308++0x07 line.quad 0x00 "GICD_IROUTER97,Interrupt Routing Register 97" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6310++0x07 line.quad 0x00 "GICD_IROUTER98,Interrupt Routing Register 98" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6318++0x07 line.quad 0x00 "GICD_IROUTER99,Interrupt Routing Register 99" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6320++0x07 line.quad 0x00 "GICD_IROUTER100,Interrupt Routing Register 100" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6328++0x07 line.quad 0x00 "GICD_IROUTER101,Interrupt Routing Register 101" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6330++0x07 line.quad 0x00 "GICD_IROUTER102,Interrupt Routing Register 102" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6338++0x07 line.quad 0x00 "GICD_IROUTER103,Interrupt Routing Register 103" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6340++0x07 line.quad 0x00 "GICD_IROUTER104,Interrupt Routing Register 104" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6348++0x07 line.quad 0x00 "GICD_IROUTER105,Interrupt Routing Register 105" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6350++0x07 line.quad 0x00 "GICD_IROUTER106,Interrupt Routing Register 106" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6358++0x07 line.quad 0x00 "GICD_IROUTER107,Interrupt Routing Register 107" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6360++0x07 line.quad 0x00 "GICD_IROUTER108,Interrupt Routing Register 108" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6368++0x07 line.quad 0x00 "GICD_IROUTER109,Interrupt Routing Register 109" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6370++0x07 line.quad 0x00 "GICD_IROUTER110,Interrupt Routing Register 110" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6378++0x07 line.quad 0x00 "GICD_IROUTER111,Interrupt Routing Register 111" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6380++0x07 line.quad 0x00 "GICD_IROUTER112,Interrupt Routing Register 112" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6388++0x07 line.quad 0x00 "GICD_IROUTER113,Interrupt Routing Register 113" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6390++0x07 line.quad 0x00 "GICD_IROUTER114,Interrupt Routing Register 114" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6398++0x07 line.quad 0x00 "GICD_IROUTER115,Interrupt Routing Register 115" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63A0++0x07 line.quad 0x00 "GICD_IROUTER116,Interrupt Routing Register 116" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63A8++0x07 line.quad 0x00 "GICD_IROUTER117,Interrupt Routing Register 117" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63B0++0x07 line.quad 0x00 "GICD_IROUTER118,Interrupt Routing Register 118" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63B8++0x07 line.quad 0x00 "GICD_IROUTER119,Interrupt Routing Register 119" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63C0++0x07 line.quad 0x00 "GICD_IROUTER120,Interrupt Routing Register 120" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63C8++0x07 line.quad 0x00 "GICD_IROUTER121,Interrupt Routing Register 121" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63D0++0x07 line.quad 0x00 "GICD_IROUTER122,Interrupt Routing Register 122" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63D8++0x07 line.quad 0x00 "GICD_IROUTER123,Interrupt Routing Register 123" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63E0++0x07 line.quad 0x00 "GICD_IROUTER124,Interrupt Routing Register 124" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63E8++0x07 line.quad 0x00 "GICD_IROUTER125,Interrupt Routing Register 125" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63F0++0x07 line.quad 0x00 "GICD_IROUTER126,Interrupt Routing Register 126" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63F8++0x07 line.quad 0x00 "GICD_IROUTER127,Interrupt Routing Register 127" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6400++0x07 line.quad 0x00 "GICD_IROUTER128,Interrupt Routing Register 128" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6408++0x07 line.quad 0x00 "GICD_IROUTER129,Interrupt Routing Register 129" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6410++0x07 line.quad 0x00 "GICD_IROUTER130,Interrupt Routing Register 130" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6418++0x07 line.quad 0x00 "GICD_IROUTER131,Interrupt Routing Register 131" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6420++0x07 line.quad 0x00 "GICD_IROUTER132,Interrupt Routing Register 132" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6428++0x07 line.quad 0x00 "GICD_IROUTER133,Interrupt Routing Register 133" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6430++0x07 line.quad 0x00 "GICD_IROUTER134,Interrupt Routing Register 134" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6438++0x07 line.quad 0x00 "GICD_IROUTER135,Interrupt Routing Register 135" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6440++0x07 line.quad 0x00 "GICD_IROUTER136,Interrupt Routing Register 136" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6448++0x07 line.quad 0x00 "GICD_IROUTER137,Interrupt Routing Register 137" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6450++0x07 line.quad 0x00 "GICD_IROUTER138,Interrupt Routing Register 138" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6458++0x07 line.quad 0x00 "GICD_IROUTER139,Interrupt Routing Register 139" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6460++0x07 line.quad 0x00 "GICD_IROUTER140,Interrupt Routing Register 140" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6468++0x07 line.quad 0x00 "GICD_IROUTER141,Interrupt Routing Register 141" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6470++0x07 line.quad 0x00 "GICD_IROUTER142,Interrupt Routing Register 142" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6478++0x07 line.quad 0x00 "GICD_IROUTER143,Interrupt Routing Register 143" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6480++0x07 line.quad 0x00 "GICD_IROUTER144,Interrupt Routing Register 144" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6488++0x07 line.quad 0x00 "GICD_IROUTER145,Interrupt Routing Register 145" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6490++0x07 line.quad 0x00 "GICD_IROUTER146,Interrupt Routing Register 146" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6498++0x07 line.quad 0x00 "GICD_IROUTER147,Interrupt Routing Register 147" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64A0++0x07 line.quad 0x00 "GICD_IROUTER148,Interrupt Routing Register 148" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64A8++0x07 line.quad 0x00 "GICD_IROUTER149,Interrupt Routing Register 149" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64B0++0x07 line.quad 0x00 "GICD_IROUTER150,Interrupt Routing Register 150" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64B8++0x07 line.quad 0x00 "GICD_IROUTER151,Interrupt Routing Register 151" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64C0++0x07 line.quad 0x00 "GICD_IROUTER152,Interrupt Routing Register 152" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64C8++0x07 line.quad 0x00 "GICD_IROUTER153,Interrupt Routing Register 153" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64D0++0x07 line.quad 0x00 "GICD_IROUTER154,Interrupt Routing Register 154" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64D8++0x07 line.quad 0x00 "GICD_IROUTER155,Interrupt Routing Register 155" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64E0++0x07 line.quad 0x00 "GICD_IROUTER156,Interrupt Routing Register 156" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64E8++0x07 line.quad 0x00 "GICD_IROUTER157,Interrupt Routing Register 157" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64F0++0x07 line.quad 0x00 "GICD_IROUTER158,Interrupt Routing Register 158" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64F8++0x07 line.quad 0x00 "GICD_IROUTER159,Interrupt Routing Register 159" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6500++0x07 line.quad 0x00 "GICD_IROUTER160,Interrupt Routing Register 160" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6508++0x07 line.quad 0x00 "GICD_IROUTER161,Interrupt Routing Register 161" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6510++0x07 line.quad 0x00 "GICD_IROUTER162,Interrupt Routing Register 162" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6518++0x07 line.quad 0x00 "GICD_IROUTER163,Interrupt Routing Register 163" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6520++0x07 line.quad 0x00 "GICD_IROUTER164,Interrupt Routing Register 164" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6528++0x07 line.quad 0x00 "GICD_IROUTER165,Interrupt Routing Register 165" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6530++0x07 line.quad 0x00 "GICD_IROUTER166,Interrupt Routing Register 166" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6538++0x07 line.quad 0x00 "GICD_IROUTER167,Interrupt Routing Register 167" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6540++0x07 line.quad 0x00 "GICD_IROUTER168,Interrupt Routing Register 168" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6548++0x07 line.quad 0x00 "GICD_IROUTER169,Interrupt Routing Register 169" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6550++0x07 line.quad 0x00 "GICD_IROUTER170,Interrupt Routing Register 170" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6558++0x07 line.quad 0x00 "GICD_IROUTER171,Interrupt Routing Register 171" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6560++0x07 line.quad 0x00 "GICD_IROUTER172,Interrupt Routing Register 172" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6568++0x07 line.quad 0x00 "GICD_IROUTER173,Interrupt Routing Register 173" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6570++0x07 line.quad 0x00 "GICD_IROUTER174,Interrupt Routing Register 174" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6578++0x07 line.quad 0x00 "GICD_IROUTER175,Interrupt Routing Register 175" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6580++0x07 line.quad 0x00 "GICD_IROUTER176,Interrupt Routing Register 176" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6588++0x07 line.quad 0x00 "GICD_IROUTER177,Interrupt Routing Register 177" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6590++0x07 line.quad 0x00 "GICD_IROUTER178,Interrupt Routing Register 178" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6598++0x07 line.quad 0x00 "GICD_IROUTER179,Interrupt Routing Register 179" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65A0++0x07 line.quad 0x00 "GICD_IROUTER180,Interrupt Routing Register 180" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65A8++0x07 line.quad 0x00 "GICD_IROUTER181,Interrupt Routing Register 181" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65B0++0x07 line.quad 0x00 "GICD_IROUTER182,Interrupt Routing Register 182" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65B8++0x07 line.quad 0x00 "GICD_IROUTER183,Interrupt Routing Register 183" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65C0++0x07 line.quad 0x00 "GICD_IROUTER184,Interrupt Routing Register 184" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65C8++0x07 line.quad 0x00 "GICD_IROUTER185,Interrupt Routing Register 185" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65D0++0x07 line.quad 0x00 "GICD_IROUTER186,Interrupt Routing Register 186" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65D8++0x07 line.quad 0x00 "GICD_IROUTER187,Interrupt Routing Register 187" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65E0++0x07 line.quad 0x00 "GICD_IROUTER188,Interrupt Routing Register 188" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65E8++0x07 line.quad 0x00 "GICD_IROUTER189,Interrupt Routing Register 189" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65F0++0x07 line.quad 0x00 "GICD_IROUTER190,Interrupt Routing Register 190" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65F8++0x07 line.quad 0x00 "GICD_IROUTER191,Interrupt Routing Register 191" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6600++0x07 line.quad 0x00 "GICD_IROUTER192,Interrupt Routing Register 192" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6608++0x07 line.quad 0x00 "GICD_IROUTER193,Interrupt Routing Register 193" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6610++0x07 line.quad 0x00 "GICD_IROUTER194,Interrupt Routing Register 194" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6618++0x07 line.quad 0x00 "GICD_IROUTER195,Interrupt Routing Register 195" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6620++0x07 line.quad 0x00 "GICD_IROUTER196,Interrupt Routing Register 196" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6628++0x07 line.quad 0x00 "GICD_IROUTER197,Interrupt Routing Register 197" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6630++0x07 line.quad 0x00 "GICD_IROUTER198,Interrupt Routing Register 198" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6638++0x07 line.quad 0x00 "GICD_IROUTER199,Interrupt Routing Register 199" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6640++0x07 line.quad 0x00 "GICD_IROUTER200,Interrupt Routing Register 200" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6648++0x07 line.quad 0x00 "GICD_IROUTER201,Interrupt Routing Register 201" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6650++0x07 line.quad 0x00 "GICD_IROUTER202,Interrupt Routing Register 202" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6658++0x07 line.quad 0x00 "GICD_IROUTER203,Interrupt Routing Register 203" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6660++0x07 line.quad 0x00 "GICD_IROUTER204,Interrupt Routing Register 204" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6668++0x07 line.quad 0x00 "GICD_IROUTER205,Interrupt Routing Register 205" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6670++0x07 line.quad 0x00 "GICD_IROUTER206,Interrupt Routing Register 206" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6678++0x07 line.quad 0x00 "GICD_IROUTER207,Interrupt Routing Register 207" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6680++0x07 line.quad 0x00 "GICD_IROUTER208,Interrupt Routing Register 208" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6688++0x07 line.quad 0x00 "GICD_IROUTER209,Interrupt Routing Register 209" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6690++0x07 line.quad 0x00 "GICD_IROUTER210,Interrupt Routing Register 210" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6698++0x07 line.quad 0x00 "GICD_IROUTER211,Interrupt Routing Register 211" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66A0++0x07 line.quad 0x00 "GICD_IROUTER212,Interrupt Routing Register 212" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66A8++0x07 line.quad 0x00 "GICD_IROUTER213,Interrupt Routing Register 213" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66B0++0x07 line.quad 0x00 "GICD_IROUTER214,Interrupt Routing Register 214" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66B8++0x07 line.quad 0x00 "GICD_IROUTER215,Interrupt Routing Register 215" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66C0++0x07 line.quad 0x00 "GICD_IROUTER216,Interrupt Routing Register 216" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66C8++0x07 line.quad 0x00 "GICD_IROUTER217,Interrupt Routing Register 217" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66D0++0x07 line.quad 0x00 "GICD_IROUTER218,Interrupt Routing Register 218" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66D8++0x07 line.quad 0x00 "GICD_IROUTER219,Interrupt Routing Register 219" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66E0++0x07 line.quad 0x00 "GICD_IROUTER220,Interrupt Routing Register 220" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66E8++0x07 line.quad 0x00 "GICD_IROUTER221,Interrupt Routing Register 221" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66F0++0x07 line.quad 0x00 "GICD_IROUTER222,Interrupt Routing Register 222" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66F8++0x07 line.quad 0x00 "GICD_IROUTER223,Interrupt Routing Register 223" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6700++0x07 line.quad 0x00 "GICD_IROUTER224,Interrupt Routing Register 224" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6708++0x07 line.quad 0x00 "GICD_IROUTER225,Interrupt Routing Register 225" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6710++0x07 line.quad 0x00 "GICD_IROUTER226,Interrupt Routing Register 226" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6718++0x07 line.quad 0x00 "GICD_IROUTER227,Interrupt Routing Register 227" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6720++0x07 line.quad 0x00 "GICD_IROUTER228,Interrupt Routing Register 228" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6728++0x07 line.quad 0x00 "GICD_IROUTER229,Interrupt Routing Register 229" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6730++0x07 line.quad 0x00 "GICD_IROUTER230,Interrupt Routing Register 230" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6738++0x07 line.quad 0x00 "GICD_IROUTER231,Interrupt Routing Register 231" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6740++0x07 line.quad 0x00 "GICD_IROUTER232,Interrupt Routing Register 232" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6748++0x07 line.quad 0x00 "GICD_IROUTER233,Interrupt Routing Register 233" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6750++0x07 line.quad 0x00 "GICD_IROUTER234,Interrupt Routing Register 234" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6758++0x07 line.quad 0x00 "GICD_IROUTER235,Interrupt Routing Register 235" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6760++0x07 line.quad 0x00 "GICD_IROUTER236,Interrupt Routing Register 236" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6768++0x07 line.quad 0x00 "GICD_IROUTER237,Interrupt Routing Register 237" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6770++0x07 line.quad 0x00 "GICD_IROUTER238,Interrupt Routing Register 238" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6778++0x07 line.quad 0x00 "GICD_IROUTER239,Interrupt Routing Register 239" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6780++0x07 line.quad 0x00 "GICD_IROUTER240,Interrupt Routing Register 240" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6788++0x07 line.quad 0x00 "GICD_IROUTER241,Interrupt Routing Register 241" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6790++0x07 line.quad 0x00 "GICD_IROUTER242,Interrupt Routing Register 242" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6798++0x07 line.quad 0x00 "GICD_IROUTER243,Interrupt Routing Register 243" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67A0++0x07 line.quad 0x00 "GICD_IROUTER244,Interrupt Routing Register 244" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67A8++0x07 line.quad 0x00 "GICD_IROUTER245,Interrupt Routing Register 245" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67B0++0x07 line.quad 0x00 "GICD_IROUTER246,Interrupt Routing Register 246" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67B8++0x07 line.quad 0x00 "GICD_IROUTER247,Interrupt Routing Register 247" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67C0++0x07 line.quad 0x00 "GICD_IROUTER248,Interrupt Routing Register 248" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67C8++0x07 line.quad 0x00 "GICD_IROUTER249,Interrupt Routing Register 249" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67D0++0x07 line.quad 0x00 "GICD_IROUTER250,Interrupt Routing Register 250" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67D8++0x07 line.quad 0x00 "GICD_IROUTER251,Interrupt Routing Register 251" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67E0++0x07 line.quad 0x00 "GICD_IROUTER252,Interrupt Routing Register 252" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67E8++0x07 line.quad 0x00 "GICD_IROUTER253,Interrupt Routing Register 253" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67F0++0x07 line.quad 0x00 "GICD_IROUTER254,Interrupt Routing Register 254" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67F8++0x07 line.quad 0x00 "GICD_IROUTER255,Interrupt Routing Register 255" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6800++0x07 line.quad 0x00 "GICD_IROUTER256,Interrupt Routing Register 256" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6808++0x07 line.quad 0x00 "GICD_IROUTER257,Interrupt Routing Register 257" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6810++0x07 line.quad 0x00 "GICD_IROUTER258,Interrupt Routing Register 258" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6818++0x07 line.quad 0x00 "GICD_IROUTER259,Interrupt Routing Register 259" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6820++0x07 line.quad 0x00 "GICD_IROUTER260,Interrupt Routing Register 260" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6828++0x07 line.quad 0x00 "GICD_IROUTER261,Interrupt Routing Register 261" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6830++0x07 line.quad 0x00 "GICD_IROUTER262,Interrupt Routing Register 262" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6838++0x07 line.quad 0x00 "GICD_IROUTER263,Interrupt Routing Register 263" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6840++0x07 line.quad 0x00 "GICD_IROUTER264,Interrupt Routing Register 264" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6848++0x07 line.quad 0x00 "GICD_IROUTER265,Interrupt Routing Register 265" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6850++0x07 line.quad 0x00 "GICD_IROUTER266,Interrupt Routing Register 266" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6858++0x07 line.quad 0x00 "GICD_IROUTER267,Interrupt Routing Register 267" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6860++0x07 line.quad 0x00 "GICD_IROUTER268,Interrupt Routing Register 268" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6868++0x07 line.quad 0x00 "GICD_IROUTER269,Interrupt Routing Register 269" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6870++0x07 line.quad 0x00 "GICD_IROUTER270,Interrupt Routing Register 270" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6878++0x07 line.quad 0x00 "GICD_IROUTER271,Interrupt Routing Register 271" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6880++0x07 line.quad 0x00 "GICD_IROUTER272,Interrupt Routing Register 272" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6888++0x07 line.quad 0x00 "GICD_IROUTER273,Interrupt Routing Register 273" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6890++0x07 line.quad 0x00 "GICD_IROUTER274,Interrupt Routing Register 274" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6898++0x07 line.quad 0x00 "GICD_IROUTER275,Interrupt Routing Register 275" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68A0++0x07 line.quad 0x00 "GICD_IROUTER276,Interrupt Routing Register 276" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68A8++0x07 line.quad 0x00 "GICD_IROUTER277,Interrupt Routing Register 277" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68B0++0x07 line.quad 0x00 "GICD_IROUTER278,Interrupt Routing Register 278" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68B8++0x07 line.quad 0x00 "GICD_IROUTER279,Interrupt Routing Register 279" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68C0++0x07 line.quad 0x00 "GICD_IROUTER280,Interrupt Routing Register 280" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68C8++0x07 line.quad 0x00 "GICD_IROUTER281,Interrupt Routing Register 281" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68D0++0x07 line.quad 0x00 "GICD_IROUTER282,Interrupt Routing Register 282" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68D8++0x07 line.quad 0x00 "GICD_IROUTER283,Interrupt Routing Register 283" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68E0++0x07 line.quad 0x00 "GICD_IROUTER284,Interrupt Routing Register 284" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68E8++0x07 line.quad 0x00 "GICD_IROUTER285,Interrupt Routing Register 285" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68F0++0x07 line.quad 0x00 "GICD_IROUTER286,Interrupt Routing Register 286" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68F8++0x07 line.quad 0x00 "GICD_IROUTER287,Interrupt Routing Register 287" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6900++0x07 line.quad 0x00 "GICD_IROUTER288,Interrupt Routing Register 288" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6908++0x07 line.quad 0x00 "GICD_IROUTER289,Interrupt Routing Register 289" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6910++0x07 line.quad 0x00 "GICD_IROUTER290,Interrupt Routing Register 290" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6918++0x07 line.quad 0x00 "GICD_IROUTER291,Interrupt Routing Register 291" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6920++0x07 line.quad 0x00 "GICD_IROUTER292,Interrupt Routing Register 292" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6928++0x07 line.quad 0x00 "GICD_IROUTER293,Interrupt Routing Register 293" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6930++0x07 line.quad 0x00 "GICD_IROUTER294,Interrupt Routing Register 294" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6938++0x07 line.quad 0x00 "GICD_IROUTER295,Interrupt Routing Register 295" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6940++0x07 line.quad 0x00 "GICD_IROUTER296,Interrupt Routing Register 296" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6948++0x07 line.quad 0x00 "GICD_IROUTER297,Interrupt Routing Register 297" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6950++0x07 line.quad 0x00 "GICD_IROUTER298,Interrupt Routing Register 298" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6958++0x07 line.quad 0x00 "GICD_IROUTER299,Interrupt Routing Register 299" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6960++0x07 line.quad 0x00 "GICD_IROUTER300,Interrupt Routing Register 300" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6968++0x07 line.quad 0x00 "GICD_IROUTER301,Interrupt Routing Register 301" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6970++0x07 line.quad 0x00 "GICD_IROUTER302,Interrupt Routing Register 302" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6978++0x07 line.quad 0x00 "GICD_IROUTER303,Interrupt Routing Register 303" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6980++0x07 line.quad 0x00 "GICD_IROUTER304,Interrupt Routing Register 304" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6988++0x07 line.quad 0x00 "GICD_IROUTER305,Interrupt Routing Register 305" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6990++0x07 line.quad 0x00 "GICD_IROUTER306,Interrupt Routing Register 306" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6998++0x07 line.quad 0x00 "GICD_IROUTER307,Interrupt Routing Register 307" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69A0++0x07 line.quad 0x00 "GICD_IROUTER308,Interrupt Routing Register 308" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69A8++0x07 line.quad 0x00 "GICD_IROUTER309,Interrupt Routing Register 309" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69B0++0x07 line.quad 0x00 "GICD_IROUTER310,Interrupt Routing Register 310" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69B8++0x07 line.quad 0x00 "GICD_IROUTER311,Interrupt Routing Register 311" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69C0++0x07 line.quad 0x00 "GICD_IROUTER312,Interrupt Routing Register 312" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69C8++0x07 line.quad 0x00 "GICD_IROUTER313,Interrupt Routing Register 313" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69D0++0x07 line.quad 0x00 "GICD_IROUTER314,Interrupt Routing Register 314" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69D8++0x07 line.quad 0x00 "GICD_IROUTER315,Interrupt Routing Register 315" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69E0++0x07 line.quad 0x00 "GICD_IROUTER316,Interrupt Routing Register 316" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69E8++0x07 line.quad 0x00 "GICD_IROUTER317,Interrupt Routing Register 317" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69F0++0x07 line.quad 0x00 "GICD_IROUTER318,Interrupt Routing Register 318" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69F8++0x07 line.quad 0x00 "GICD_IROUTER319,Interrupt Routing Register 319" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A00++0x07 line.quad 0x00 "GICD_IROUTER320,Interrupt Routing Register 320" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A08++0x07 line.quad 0x00 "GICD_IROUTER321,Interrupt Routing Register 321" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A10++0x07 line.quad 0x00 "GICD_IROUTER322,Interrupt Routing Register 322" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A18++0x07 line.quad 0x00 "GICD_IROUTER323,Interrupt Routing Register 323" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A20++0x07 line.quad 0x00 "GICD_IROUTER324,Interrupt Routing Register 324" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A28++0x07 line.quad 0x00 "GICD_IROUTER325,Interrupt Routing Register 325" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A30++0x07 line.quad 0x00 "GICD_IROUTER326,Interrupt Routing Register 326" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A38++0x07 line.quad 0x00 "GICD_IROUTER327,Interrupt Routing Register 327" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A40++0x07 line.quad 0x00 "GICD_IROUTER328,Interrupt Routing Register 328" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A48++0x07 line.quad 0x00 "GICD_IROUTER329,Interrupt Routing Register 329" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A50++0x07 line.quad 0x00 "GICD_IROUTER330,Interrupt Routing Register 330" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A58++0x07 line.quad 0x00 "GICD_IROUTER331,Interrupt Routing Register 331" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A60++0x07 line.quad 0x00 "GICD_IROUTER332,Interrupt Routing Register 332" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A68++0x07 line.quad 0x00 "GICD_IROUTER333,Interrupt Routing Register 333" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A70++0x07 line.quad 0x00 "GICD_IROUTER334,Interrupt Routing Register 334" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A78++0x07 line.quad 0x00 "GICD_IROUTER335,Interrupt Routing Register 335" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A80++0x07 line.quad 0x00 "GICD_IROUTER336,Interrupt Routing Register 336" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A88++0x07 line.quad 0x00 "GICD_IROUTER337,Interrupt Routing Register 337" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A90++0x07 line.quad 0x00 "GICD_IROUTER338,Interrupt Routing Register 338" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A98++0x07 line.quad 0x00 "GICD_IROUTER339,Interrupt Routing Register 339" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AA0++0x07 line.quad 0x00 "GICD_IROUTER340,Interrupt Routing Register 340" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AA8++0x07 line.quad 0x00 "GICD_IROUTER341,Interrupt Routing Register 341" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AB0++0x07 line.quad 0x00 "GICD_IROUTER342,Interrupt Routing Register 342" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AB8++0x07 line.quad 0x00 "GICD_IROUTER343,Interrupt Routing Register 343" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AC0++0x07 line.quad 0x00 "GICD_IROUTER344,Interrupt Routing Register 344" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AC8++0x07 line.quad 0x00 "GICD_IROUTER345,Interrupt Routing Register 345" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AD0++0x07 line.quad 0x00 "GICD_IROUTER346,Interrupt Routing Register 346" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AD8++0x07 line.quad 0x00 "GICD_IROUTER347,Interrupt Routing Register 347" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AE0++0x07 line.quad 0x00 "GICD_IROUTER348,Interrupt Routing Register 348" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AE8++0x07 line.quad 0x00 "GICD_IROUTER349,Interrupt Routing Register 349" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AF0++0x07 line.quad 0x00 "GICD_IROUTER350,Interrupt Routing Register 350" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AF8++0x07 line.quad 0x00 "GICD_IROUTER351,Interrupt Routing Register 351" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B00++0x07 line.quad 0x00 "GICD_IROUTER352,Interrupt Routing Register 352" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B08++0x07 line.quad 0x00 "GICD_IROUTER353,Interrupt Routing Register 353" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B10++0x07 line.quad 0x00 "GICD_IROUTER354,Interrupt Routing Register 354" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B18++0x07 line.quad 0x00 "GICD_IROUTER355,Interrupt Routing Register 355" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B20++0x07 line.quad 0x00 "GICD_IROUTER356,Interrupt Routing Register 356" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B28++0x07 line.quad 0x00 "GICD_IROUTER357,Interrupt Routing Register 357" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B30++0x07 line.quad 0x00 "GICD_IROUTER358,Interrupt Routing Register 358" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B38++0x07 line.quad 0x00 "GICD_IROUTER359,Interrupt Routing Register 359" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B40++0x07 line.quad 0x00 "GICD_IROUTER360,Interrupt Routing Register 360" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B48++0x07 line.quad 0x00 "GICD_IROUTER361,Interrupt Routing Register 361" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B50++0x07 line.quad 0x00 "GICD_IROUTER362,Interrupt Routing Register 362" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B58++0x07 line.quad 0x00 "GICD_IROUTER363,Interrupt Routing Register 363" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B60++0x07 line.quad 0x00 "GICD_IROUTER364,Interrupt Routing Register 364" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B68++0x07 line.quad 0x00 "GICD_IROUTER365,Interrupt Routing Register 365" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B70++0x07 line.quad 0x00 "GICD_IROUTER366,Interrupt Routing Register 366" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B78++0x07 line.quad 0x00 "GICD_IROUTER367,Interrupt Routing Register 367" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B80++0x07 line.quad 0x00 "GICD_IROUTER368,Interrupt Routing Register 368" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B88++0x07 line.quad 0x00 "GICD_IROUTER369,Interrupt Routing Register 369" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B90++0x07 line.quad 0x00 "GICD_IROUTER370,Interrupt Routing Register 370" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B98++0x07 line.quad 0x00 "GICD_IROUTER371,Interrupt Routing Register 371" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BA0++0x07 line.quad 0x00 "GICD_IROUTER372,Interrupt Routing Register 372" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BA8++0x07 line.quad 0x00 "GICD_IROUTER373,Interrupt Routing Register 373" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BB0++0x07 line.quad 0x00 "GICD_IROUTER374,Interrupt Routing Register 374" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BB8++0x07 line.quad 0x00 "GICD_IROUTER375,Interrupt Routing Register 375" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BC0++0x07 line.quad 0x00 "GICD_IROUTER376,Interrupt Routing Register 376" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BC8++0x07 line.quad 0x00 "GICD_IROUTER377,Interrupt Routing Register 377" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BD0++0x07 line.quad 0x00 "GICD_IROUTER378,Interrupt Routing Register 378" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BD8++0x07 line.quad 0x00 "GICD_IROUTER379,Interrupt Routing Register 379" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BE0++0x07 line.quad 0x00 "GICD_IROUTER380,Interrupt Routing Register 380" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BE8++0x07 line.quad 0x00 "GICD_IROUTER381,Interrupt Routing Register 381" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BF0++0x07 line.quad 0x00 "GICD_IROUTER382,Interrupt Routing Register 382" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BF8++0x07 line.quad 0x00 "GICD_IROUTER383,Interrupt Routing Register 383" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C00++0x07 line.quad 0x00 "GICD_IROUTER384,Interrupt Routing Register 384" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C08++0x07 line.quad 0x00 "GICD_IROUTER385,Interrupt Routing Register 385" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C10++0x07 line.quad 0x00 "GICD_IROUTER386,Interrupt Routing Register 386" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C18++0x07 line.quad 0x00 "GICD_IROUTER387,Interrupt Routing Register 387" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C20++0x07 line.quad 0x00 "GICD_IROUTER388,Interrupt Routing Register 388" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C28++0x07 line.quad 0x00 "GICD_IROUTER389,Interrupt Routing Register 389" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C30++0x07 line.quad 0x00 "GICD_IROUTER390,Interrupt Routing Register 390" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C38++0x07 line.quad 0x00 "GICD_IROUTER391,Interrupt Routing Register 391" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C40++0x07 line.quad 0x00 "GICD_IROUTER392,Interrupt Routing Register 392" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C48++0x07 line.quad 0x00 "GICD_IROUTER393,Interrupt Routing Register 393" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C50++0x07 line.quad 0x00 "GICD_IROUTER394,Interrupt Routing Register 394" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C58++0x07 line.quad 0x00 "GICD_IROUTER395,Interrupt Routing Register 395" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C60++0x07 line.quad 0x00 "GICD_IROUTER396,Interrupt Routing Register 396" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C68++0x07 line.quad 0x00 "GICD_IROUTER397,Interrupt Routing Register 397" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C70++0x07 line.quad 0x00 "GICD_IROUTER398,Interrupt Routing Register 398" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C78++0x07 line.quad 0x00 "GICD_IROUTER399,Interrupt Routing Register 399" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C80++0x07 line.quad 0x00 "GICD_IROUTER400,Interrupt Routing Register 400" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C88++0x07 line.quad 0x00 "GICD_IROUTER401,Interrupt Routing Register 401" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C90++0x07 line.quad 0x00 "GICD_IROUTER402,Interrupt Routing Register 402" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C98++0x07 line.quad 0x00 "GICD_IROUTER403,Interrupt Routing Register 403" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CA0++0x07 line.quad 0x00 "GICD_IROUTER404,Interrupt Routing Register 404" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CA8++0x07 line.quad 0x00 "GICD_IROUTER405,Interrupt Routing Register 405" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CB0++0x07 line.quad 0x00 "GICD_IROUTER406,Interrupt Routing Register 406" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CB8++0x07 line.quad 0x00 "GICD_IROUTER407,Interrupt Routing Register 407" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CC0++0x07 line.quad 0x00 "GICD_IROUTER408,Interrupt Routing Register 408" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CC8++0x07 line.quad 0x00 "GICD_IROUTER409,Interrupt Routing Register 409" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CD0++0x07 line.quad 0x00 "GICD_IROUTER410,Interrupt Routing Register 410" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CD8++0x07 line.quad 0x00 "GICD_IROUTER411,Interrupt Routing Register 411" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CE0++0x07 line.quad 0x00 "GICD_IROUTER412,Interrupt Routing Register 412" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CE8++0x07 line.quad 0x00 "GICD_IROUTER413,Interrupt Routing Register 413" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CF0++0x07 line.quad 0x00 "GICD_IROUTER414,Interrupt Routing Register 414" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CF8++0x07 line.quad 0x00 "GICD_IROUTER415,Interrupt Routing Register 415" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D00++0x07 line.quad 0x00 "GICD_IROUTER416,Interrupt Routing Register 416" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D08++0x07 line.quad 0x00 "GICD_IROUTER417,Interrupt Routing Register 417" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D10++0x07 line.quad 0x00 "GICD_IROUTER418,Interrupt Routing Register 418" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D18++0x07 line.quad 0x00 "GICD_IROUTER419,Interrupt Routing Register 419" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D20++0x07 line.quad 0x00 "GICD_IROUTER420,Interrupt Routing Register 420" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D28++0x07 line.quad 0x00 "GICD_IROUTER421,Interrupt Routing Register 421" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D30++0x07 line.quad 0x00 "GICD_IROUTER422,Interrupt Routing Register 422" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D38++0x07 line.quad 0x00 "GICD_IROUTER423,Interrupt Routing Register 423" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D40++0x07 line.quad 0x00 "GICD_IROUTER424,Interrupt Routing Register 424" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D48++0x07 line.quad 0x00 "GICD_IROUTER425,Interrupt Routing Register 425" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D50++0x07 line.quad 0x00 "GICD_IROUTER426,Interrupt Routing Register 426" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D58++0x07 line.quad 0x00 "GICD_IROUTER427,Interrupt Routing Register 427" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D60++0x07 line.quad 0x00 "GICD_IROUTER428,Interrupt Routing Register 428" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D68++0x07 line.quad 0x00 "GICD_IROUTER429,Interrupt Routing Register 429" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D70++0x07 line.quad 0x00 "GICD_IROUTER430,Interrupt Routing Register 430" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D78++0x07 line.quad 0x00 "GICD_IROUTER431,Interrupt Routing Register 431" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D80++0x07 line.quad 0x00 "GICD_IROUTER432,Interrupt Routing Register 432" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D88++0x07 line.quad 0x00 "GICD_IROUTER433,Interrupt Routing Register 433" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D90++0x07 line.quad 0x00 "GICD_IROUTER434,Interrupt Routing Register 434" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D98++0x07 line.quad 0x00 "GICD_IROUTER435,Interrupt Routing Register 435" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DA0++0x07 line.quad 0x00 "GICD_IROUTER436,Interrupt Routing Register 436" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DA8++0x07 line.quad 0x00 "GICD_IROUTER437,Interrupt Routing Register 437" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DB0++0x07 line.quad 0x00 "GICD_IROUTER438,Interrupt Routing Register 438" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DB8++0x07 line.quad 0x00 "GICD_IROUTER439,Interrupt Routing Register 439" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DC0++0x07 line.quad 0x00 "GICD_IROUTER440,Interrupt Routing Register 440" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DC8++0x07 line.quad 0x00 "GICD_IROUTER441,Interrupt Routing Register 441" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DD0++0x07 line.quad 0x00 "GICD_IROUTER442,Interrupt Routing Register 442" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DD8++0x07 line.quad 0x00 "GICD_IROUTER443,Interrupt Routing Register 443" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DE0++0x07 line.quad 0x00 "GICD_IROUTER444,Interrupt Routing Register 444" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DE8++0x07 line.quad 0x00 "GICD_IROUTER445,Interrupt Routing Register 445" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DF0++0x07 line.quad 0x00 "GICD_IROUTER446,Interrupt Routing Register 446" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DF8++0x07 line.quad 0x00 "GICD_IROUTER447,Interrupt Routing Register 447" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E00++0x07 line.quad 0x00 "GICD_IROUTER448,Interrupt Routing Register 448" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E08++0x07 line.quad 0x00 "GICD_IROUTER449,Interrupt Routing Register 449" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E10++0x07 line.quad 0x00 "GICD_IROUTER450,Interrupt Routing Register 450" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E18++0x07 line.quad 0x00 "GICD_IROUTER451,Interrupt Routing Register 451" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E20++0x07 line.quad 0x00 "GICD_IROUTER452,Interrupt Routing Register 452" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E28++0x07 line.quad 0x00 "GICD_IROUTER453,Interrupt Routing Register 453" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E30++0x07 line.quad 0x00 "GICD_IROUTER454,Interrupt Routing Register 454" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E38++0x07 line.quad 0x00 "GICD_IROUTER455,Interrupt Routing Register 455" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E40++0x07 line.quad 0x00 "GICD_IROUTER456,Interrupt Routing Register 456" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E48++0x07 line.quad 0x00 "GICD_IROUTER457,Interrupt Routing Register 457" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E50++0x07 line.quad 0x00 "GICD_IROUTER458,Interrupt Routing Register 458" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E58++0x07 line.quad 0x00 "GICD_IROUTER459,Interrupt Routing Register 459" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E60++0x07 line.quad 0x00 "GICD_IROUTER460,Interrupt Routing Register 460" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E68++0x07 line.quad 0x00 "GICD_IROUTER461,Interrupt Routing Register 461" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E70++0x07 line.quad 0x00 "GICD_IROUTER462,Interrupt Routing Register 462" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E78++0x07 line.quad 0x00 "GICD_IROUTER463,Interrupt Routing Register 463" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E80++0x07 line.quad 0x00 "GICD_IROUTER464,Interrupt Routing Register 464" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E88++0x07 line.quad 0x00 "GICD_IROUTER465,Interrupt Routing Register 465" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E90++0x07 line.quad 0x00 "GICD_IROUTER466,Interrupt Routing Register 466" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E98++0x07 line.quad 0x00 "GICD_IROUTER467,Interrupt Routing Register 467" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EA0++0x07 line.quad 0x00 "GICD_IROUTER468,Interrupt Routing Register 468" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EA8++0x07 line.quad 0x00 "GICD_IROUTER469,Interrupt Routing Register 469" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EB0++0x07 line.quad 0x00 "GICD_IROUTER470,Interrupt Routing Register 470" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EB8++0x07 line.quad 0x00 "GICD_IROUTER471,Interrupt Routing Register 471" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EC0++0x07 line.quad 0x00 "GICD_IROUTER472,Interrupt Routing Register 472" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EC8++0x07 line.quad 0x00 "GICD_IROUTER473,Interrupt Routing Register 473" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6ED0++0x07 line.quad 0x00 "GICD_IROUTER474,Interrupt Routing Register 474" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6ED8++0x07 line.quad 0x00 "GICD_IROUTER475,Interrupt Routing Register 475" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EE0++0x07 line.quad 0x00 "GICD_IROUTER476,Interrupt Routing Register 476" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EE8++0x07 line.quad 0x00 "GICD_IROUTER477,Interrupt Routing Register 477" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EF0++0x07 line.quad 0x00 "GICD_IROUTER478,Interrupt Routing Register 478" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EF8++0x07 line.quad 0x00 "GICD_IROUTER479,Interrupt Routing Register 479" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F00++0x07 line.quad 0x00 "GICD_IROUTER480,Interrupt Routing Register 480" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F08++0x07 line.quad 0x00 "GICD_IROUTER481,Interrupt Routing Register 481" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F10++0x07 line.quad 0x00 "GICD_IROUTER482,Interrupt Routing Register 482" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F18++0x07 line.quad 0x00 "GICD_IROUTER483,Interrupt Routing Register 483" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F20++0x07 line.quad 0x00 "GICD_IROUTER484,Interrupt Routing Register 484" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F28++0x07 line.quad 0x00 "GICD_IROUTER485,Interrupt Routing Register 485" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F30++0x07 line.quad 0x00 "GICD_IROUTER486,Interrupt Routing Register 486" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F38++0x07 line.quad 0x00 "GICD_IROUTER487,Interrupt Routing Register 487" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F40++0x07 line.quad 0x00 "GICD_IROUTER488,Interrupt Routing Register 488" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F48++0x07 line.quad 0x00 "GICD_IROUTER489,Interrupt Routing Register 489" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F50++0x07 line.quad 0x00 "GICD_IROUTER490,Interrupt Routing Register 490" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F58++0x07 line.quad 0x00 "GICD_IROUTER491,Interrupt Routing Register 491" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F60++0x07 line.quad 0x00 "GICD_IROUTER492,Interrupt Routing Register 492" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F68++0x07 line.quad 0x00 "GICD_IROUTER493,Interrupt Routing Register 493" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F70++0x07 line.quad 0x00 "GICD_IROUTER494,Interrupt Routing Register 494" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F78++0x07 line.quad 0x00 "GICD_IROUTER495,Interrupt Routing Register 495" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F80++0x07 line.quad 0x00 "GICD_IROUTER496,Interrupt Routing Register 496" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F88++0x07 line.quad 0x00 "GICD_IROUTER497,Interrupt Routing Register 497" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F90++0x07 line.quad 0x00 "GICD_IROUTER498,Interrupt Routing Register 498" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F98++0x07 line.quad 0x00 "GICD_IROUTER499,Interrupt Routing Register 499" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FA0++0x07 line.quad 0x00 "GICD_IROUTER500,Interrupt Routing Register 500" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FA8++0x07 line.quad 0x00 "GICD_IROUTER501,Interrupt Routing Register 501" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FB0++0x07 line.quad 0x00 "GICD_IROUTER502,Interrupt Routing Register 502" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FB8++0x07 line.quad 0x00 "GICD_IROUTER503,Interrupt Routing Register 503" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FC0++0x07 line.quad 0x00 "GICD_IROUTER504,Interrupt Routing Register 504" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FC8++0x07 line.quad 0x00 "GICD_IROUTER505,Interrupt Routing Register 505" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FD0++0x07 line.quad 0x00 "GICD_IROUTER506,Interrupt Routing Register 506" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FD8++0x07 line.quad 0x00 "GICD_IROUTER507,Interrupt Routing Register 507" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FE0++0x07 line.quad 0x00 "GICD_IROUTER508,Interrupt Routing Register 508" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FE8++0x07 line.quad 0x00 "GICD_IROUTER509,Interrupt Routing Register 509" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FF0++0x07 line.quad 0x00 "GICD_IROUTER510,Interrupt Routing Register 510" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FF8++0x07 line.quad 0x00 "GICD_IROUTER511,Interrupt Routing Register 511" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7000++0x07 line.quad 0x00 "GICD_IROUTER512,Interrupt Routing Register 512" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7008++0x07 line.quad 0x00 "GICD_IROUTER513,Interrupt Routing Register 513" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7010++0x07 line.quad 0x00 "GICD_IROUTER514,Interrupt Routing Register 514" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7018++0x07 line.quad 0x00 "GICD_IROUTER515,Interrupt Routing Register 515" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7020++0x07 line.quad 0x00 "GICD_IROUTER516,Interrupt Routing Register 516" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7028++0x07 line.quad 0x00 "GICD_IROUTER517,Interrupt Routing Register 517" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7030++0x07 line.quad 0x00 "GICD_IROUTER518,Interrupt Routing Register 518" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7038++0x07 line.quad 0x00 "GICD_IROUTER519,Interrupt Routing Register 519" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7040++0x07 line.quad 0x00 "GICD_IROUTER520,Interrupt Routing Register 520" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7048++0x07 line.quad 0x00 "GICD_IROUTER521,Interrupt Routing Register 521" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7050++0x07 line.quad 0x00 "GICD_IROUTER522,Interrupt Routing Register 522" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7058++0x07 line.quad 0x00 "GICD_IROUTER523,Interrupt Routing Register 523" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7060++0x07 line.quad 0x00 "GICD_IROUTER524,Interrupt Routing Register 524" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7068++0x07 line.quad 0x00 "GICD_IROUTER525,Interrupt Routing Register 525" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7070++0x07 line.quad 0x00 "GICD_IROUTER526,Interrupt Routing Register 526" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7078++0x07 line.quad 0x00 "GICD_IROUTER527,Interrupt Routing Register 527" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7080++0x07 line.quad 0x00 "GICD_IROUTER528,Interrupt Routing Register 528" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7088++0x07 line.quad 0x00 "GICD_IROUTER529,Interrupt Routing Register 529" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7090++0x07 line.quad 0x00 "GICD_IROUTER530,Interrupt Routing Register 530" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7098++0x07 line.quad 0x00 "GICD_IROUTER531,Interrupt Routing Register 531" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70A0++0x07 line.quad 0x00 "GICD_IROUTER532,Interrupt Routing Register 532" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70A8++0x07 line.quad 0x00 "GICD_IROUTER533,Interrupt Routing Register 533" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70B0++0x07 line.quad 0x00 "GICD_IROUTER534,Interrupt Routing Register 534" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70B8++0x07 line.quad 0x00 "GICD_IROUTER535,Interrupt Routing Register 535" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70C0++0x07 line.quad 0x00 "GICD_IROUTER536,Interrupt Routing Register 536" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70C8++0x07 line.quad 0x00 "GICD_IROUTER537,Interrupt Routing Register 537" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70D0++0x07 line.quad 0x00 "GICD_IROUTER538,Interrupt Routing Register 538" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70D8++0x07 line.quad 0x00 "GICD_IROUTER539,Interrupt Routing Register 539" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70E0++0x07 line.quad 0x00 "GICD_IROUTER540,Interrupt Routing Register 540" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70E8++0x07 line.quad 0x00 "GICD_IROUTER541,Interrupt Routing Register 541" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70F0++0x07 line.quad 0x00 "GICD_IROUTER542,Interrupt Routing Register 542" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70F8++0x07 line.quad 0x00 "GICD_IROUTER543,Interrupt Routing Register 543" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7100++0x07 line.quad 0x00 "GICD_IROUTER544,Interrupt Routing Register 544" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7108++0x07 line.quad 0x00 "GICD_IROUTER545,Interrupt Routing Register 545" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7110++0x07 line.quad 0x00 "GICD_IROUTER546,Interrupt Routing Register 546" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7118++0x07 line.quad 0x00 "GICD_IROUTER547,Interrupt Routing Register 547" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7120++0x07 line.quad 0x00 "GICD_IROUTER548,Interrupt Routing Register 548" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7128++0x07 line.quad 0x00 "GICD_IROUTER549,Interrupt Routing Register 549" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7130++0x07 line.quad 0x00 "GICD_IROUTER550,Interrupt Routing Register 550" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7138++0x07 line.quad 0x00 "GICD_IROUTER551,Interrupt Routing Register 551" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7140++0x07 line.quad 0x00 "GICD_IROUTER552,Interrupt Routing Register 552" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7148++0x07 line.quad 0x00 "GICD_IROUTER553,Interrupt Routing Register 553" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7150++0x07 line.quad 0x00 "GICD_IROUTER554,Interrupt Routing Register 554" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7158++0x07 line.quad 0x00 "GICD_IROUTER555,Interrupt Routing Register 555" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7160++0x07 line.quad 0x00 "GICD_IROUTER556,Interrupt Routing Register 556" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7168++0x07 line.quad 0x00 "GICD_IROUTER557,Interrupt Routing Register 557" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7170++0x07 line.quad 0x00 "GICD_IROUTER558,Interrupt Routing Register 558" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7178++0x07 line.quad 0x00 "GICD_IROUTER559,Interrupt Routing Register 559" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7180++0x07 line.quad 0x00 "GICD_IROUTER560,Interrupt Routing Register 560" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7188++0x07 line.quad 0x00 "GICD_IROUTER561,Interrupt Routing Register 561" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7190++0x07 line.quad 0x00 "GICD_IROUTER562,Interrupt Routing Register 562" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7198++0x07 line.quad 0x00 "GICD_IROUTER563,Interrupt Routing Register 563" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71A0++0x07 line.quad 0x00 "GICD_IROUTER564,Interrupt Routing Register 564" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71A8++0x07 line.quad 0x00 "GICD_IROUTER565,Interrupt Routing Register 565" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71B0++0x07 line.quad 0x00 "GICD_IROUTER566,Interrupt Routing Register 566" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71B8++0x07 line.quad 0x00 "GICD_IROUTER567,Interrupt Routing Register 567" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71C0++0x07 line.quad 0x00 "GICD_IROUTER568,Interrupt Routing Register 568" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71C8++0x07 line.quad 0x00 "GICD_IROUTER569,Interrupt Routing Register 569" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71D0++0x07 line.quad 0x00 "GICD_IROUTER570,Interrupt Routing Register 570" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71D8++0x07 line.quad 0x00 "GICD_IROUTER571,Interrupt Routing Register 571" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71E0++0x07 line.quad 0x00 "GICD_IROUTER572,Interrupt Routing Register 572" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71E8++0x07 line.quad 0x00 "GICD_IROUTER573,Interrupt Routing Register 573" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71F0++0x07 line.quad 0x00 "GICD_IROUTER574,Interrupt Routing Register 574" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71F8++0x07 line.quad 0x00 "GICD_IROUTER575,Interrupt Routing Register 575" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7200++0x07 line.quad 0x00 "GICD_IROUTER576,Interrupt Routing Register 576" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7208++0x07 line.quad 0x00 "GICD_IROUTER577,Interrupt Routing Register 577" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7210++0x07 line.quad 0x00 "GICD_IROUTER578,Interrupt Routing Register 578" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7218++0x07 line.quad 0x00 "GICD_IROUTER579,Interrupt Routing Register 579" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7220++0x07 line.quad 0x00 "GICD_IROUTER580,Interrupt Routing Register 580" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7228++0x07 line.quad 0x00 "GICD_IROUTER581,Interrupt Routing Register 581" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7230++0x07 line.quad 0x00 "GICD_IROUTER582,Interrupt Routing Register 582" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7238++0x07 line.quad 0x00 "GICD_IROUTER583,Interrupt Routing Register 583" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7240++0x07 line.quad 0x00 "GICD_IROUTER584,Interrupt Routing Register 584" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7248++0x07 line.quad 0x00 "GICD_IROUTER585,Interrupt Routing Register 585" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7250++0x07 line.quad 0x00 "GICD_IROUTER586,Interrupt Routing Register 586" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7258++0x07 line.quad 0x00 "GICD_IROUTER587,Interrupt Routing Register 587" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7260++0x07 line.quad 0x00 "GICD_IROUTER588,Interrupt Routing Register 588" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7268++0x07 line.quad 0x00 "GICD_IROUTER589,Interrupt Routing Register 589" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7270++0x07 line.quad 0x00 "GICD_IROUTER590,Interrupt Routing Register 590" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7278++0x07 line.quad 0x00 "GICD_IROUTER591,Interrupt Routing Register 591" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7280++0x07 line.quad 0x00 "GICD_IROUTER592,Interrupt Routing Register 592" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7288++0x07 line.quad 0x00 "GICD_IROUTER593,Interrupt Routing Register 593" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7290++0x07 line.quad 0x00 "GICD_IROUTER594,Interrupt Routing Register 594" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7298++0x07 line.quad 0x00 "GICD_IROUTER595,Interrupt Routing Register 595" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72A0++0x07 line.quad 0x00 "GICD_IROUTER596,Interrupt Routing Register 596" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72A8++0x07 line.quad 0x00 "GICD_IROUTER597,Interrupt Routing Register 597" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72B0++0x07 line.quad 0x00 "GICD_IROUTER598,Interrupt Routing Register 598" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72B8++0x07 line.quad 0x00 "GICD_IROUTER599,Interrupt Routing Register 599" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72C0++0x07 line.quad 0x00 "GICD_IROUTER600,Interrupt Routing Register 600" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72C8++0x07 line.quad 0x00 "GICD_IROUTER601,Interrupt Routing Register 601" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72D0++0x07 line.quad 0x00 "GICD_IROUTER602,Interrupt Routing Register 602" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72D8++0x07 line.quad 0x00 "GICD_IROUTER603,Interrupt Routing Register 603" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72E0++0x07 line.quad 0x00 "GICD_IROUTER604,Interrupt Routing Register 604" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72E8++0x07 line.quad 0x00 "GICD_IROUTER605,Interrupt Routing Register 605" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72F0++0x07 line.quad 0x00 "GICD_IROUTER606,Interrupt Routing Register 606" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72F8++0x07 line.quad 0x00 "GICD_IROUTER607,Interrupt Routing Register 607" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7300++0x07 line.quad 0x00 "GICD_IROUTER608,Interrupt Routing Register 608" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7308++0x07 line.quad 0x00 "GICD_IROUTER609,Interrupt Routing Register 609" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7310++0x07 line.quad 0x00 "GICD_IROUTER610,Interrupt Routing Register 610" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7318++0x07 line.quad 0x00 "GICD_IROUTER611,Interrupt Routing Register 611" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7320++0x07 line.quad 0x00 "GICD_IROUTER612,Interrupt Routing Register 612" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7328++0x07 line.quad 0x00 "GICD_IROUTER613,Interrupt Routing Register 613" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7330++0x07 line.quad 0x00 "GICD_IROUTER614,Interrupt Routing Register 614" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7338++0x07 line.quad 0x00 "GICD_IROUTER615,Interrupt Routing Register 615" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7340++0x07 line.quad 0x00 "GICD_IROUTER616,Interrupt Routing Register 616" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7348++0x07 line.quad 0x00 "GICD_IROUTER617,Interrupt Routing Register 617" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7350++0x07 line.quad 0x00 "GICD_IROUTER618,Interrupt Routing Register 618" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7358++0x07 line.quad 0x00 "GICD_IROUTER619,Interrupt Routing Register 619" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7360++0x07 line.quad 0x00 "GICD_IROUTER620,Interrupt Routing Register 620" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7368++0x07 line.quad 0x00 "GICD_IROUTER621,Interrupt Routing Register 621" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7370++0x07 line.quad 0x00 "GICD_IROUTER622,Interrupt Routing Register 622" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7378++0x07 line.quad 0x00 "GICD_IROUTER623,Interrupt Routing Register 623" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7380++0x07 line.quad 0x00 "GICD_IROUTER624,Interrupt Routing Register 624" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7388++0x07 line.quad 0x00 "GICD_IROUTER625,Interrupt Routing Register 625" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7390++0x07 line.quad 0x00 "GICD_IROUTER626,Interrupt Routing Register 626" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7398++0x07 line.quad 0x00 "GICD_IROUTER627,Interrupt Routing Register 627" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73A0++0x07 line.quad 0x00 "GICD_IROUTER628,Interrupt Routing Register 628" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73A8++0x07 line.quad 0x00 "GICD_IROUTER629,Interrupt Routing Register 629" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73B0++0x07 line.quad 0x00 "GICD_IROUTER630,Interrupt Routing Register 630" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73B8++0x07 line.quad 0x00 "GICD_IROUTER631,Interrupt Routing Register 631" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73C0++0x07 line.quad 0x00 "GICD_IROUTER632,Interrupt Routing Register 632" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73C8++0x07 line.quad 0x00 "GICD_IROUTER633,Interrupt Routing Register 633" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73D0++0x07 line.quad 0x00 "GICD_IROUTER634,Interrupt Routing Register 634" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73D8++0x07 line.quad 0x00 "GICD_IROUTER635,Interrupt Routing Register 635" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73E0++0x07 line.quad 0x00 "GICD_IROUTER636,Interrupt Routing Register 636" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73E8++0x07 line.quad 0x00 "GICD_IROUTER637,Interrupt Routing Register 637" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73F0++0x07 line.quad 0x00 "GICD_IROUTER638,Interrupt Routing Register 638" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73F8++0x07 line.quad 0x00 "GICD_IROUTER639,Interrupt Routing Register 639" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7400++0x07 line.quad 0x00 "GICD_IROUTER640,Interrupt Routing Register 640" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7408++0x07 line.quad 0x00 "GICD_IROUTER641,Interrupt Routing Register 641" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7410++0x07 line.quad 0x00 "GICD_IROUTER642,Interrupt Routing Register 642" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7418++0x07 line.quad 0x00 "GICD_IROUTER643,Interrupt Routing Register 643" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7420++0x07 line.quad 0x00 "GICD_IROUTER644,Interrupt Routing Register 644" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7428++0x07 line.quad 0x00 "GICD_IROUTER645,Interrupt Routing Register 645" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7430++0x07 line.quad 0x00 "GICD_IROUTER646,Interrupt Routing Register 646" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7438++0x07 line.quad 0x00 "GICD_IROUTER647,Interrupt Routing Register 647" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7440++0x07 line.quad 0x00 "GICD_IROUTER648,Interrupt Routing Register 648" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7448++0x07 line.quad 0x00 "GICD_IROUTER649,Interrupt Routing Register 649" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7450++0x07 line.quad 0x00 "GICD_IROUTER650,Interrupt Routing Register 650" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7458++0x07 line.quad 0x00 "GICD_IROUTER651,Interrupt Routing Register 651" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7460++0x07 line.quad 0x00 "GICD_IROUTER652,Interrupt Routing Register 652" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7468++0x07 line.quad 0x00 "GICD_IROUTER653,Interrupt Routing Register 653" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7470++0x07 line.quad 0x00 "GICD_IROUTER654,Interrupt Routing Register 654" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7478++0x07 line.quad 0x00 "GICD_IROUTER655,Interrupt Routing Register 655" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7480++0x07 line.quad 0x00 "GICD_IROUTER656,Interrupt Routing Register 656" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7488++0x07 line.quad 0x00 "GICD_IROUTER657,Interrupt Routing Register 657" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7490++0x07 line.quad 0x00 "GICD_IROUTER658,Interrupt Routing Register 658" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7498++0x07 line.quad 0x00 "GICD_IROUTER659,Interrupt Routing Register 659" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74A0++0x07 line.quad 0x00 "GICD_IROUTER660,Interrupt Routing Register 660" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74A8++0x07 line.quad 0x00 "GICD_IROUTER661,Interrupt Routing Register 661" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74B0++0x07 line.quad 0x00 "GICD_IROUTER662,Interrupt Routing Register 662" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74B8++0x07 line.quad 0x00 "GICD_IROUTER663,Interrupt Routing Register 663" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74C0++0x07 line.quad 0x00 "GICD_IROUTER664,Interrupt Routing Register 664" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74C8++0x07 line.quad 0x00 "GICD_IROUTER665,Interrupt Routing Register 665" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74D0++0x07 line.quad 0x00 "GICD_IROUTER666,Interrupt Routing Register 666" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74D8++0x07 line.quad 0x00 "GICD_IROUTER667,Interrupt Routing Register 667" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74E0++0x07 line.quad 0x00 "GICD_IROUTER668,Interrupt Routing Register 668" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74E8++0x07 line.quad 0x00 "GICD_IROUTER669,Interrupt Routing Register 669" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74F0++0x07 line.quad 0x00 "GICD_IROUTER670,Interrupt Routing Register 670" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74F8++0x07 line.quad 0x00 "GICD_IROUTER671,Interrupt Routing Register 671" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7500++0x07 line.quad 0x00 "GICD_IROUTER672,Interrupt Routing Register 672" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7508++0x07 line.quad 0x00 "GICD_IROUTER673,Interrupt Routing Register 673" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7510++0x07 line.quad 0x00 "GICD_IROUTER674,Interrupt Routing Register 674" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7518++0x07 line.quad 0x00 "GICD_IROUTER675,Interrupt Routing Register 675" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7520++0x07 line.quad 0x00 "GICD_IROUTER676,Interrupt Routing Register 676" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7528++0x07 line.quad 0x00 "GICD_IROUTER677,Interrupt Routing Register 677" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7530++0x07 line.quad 0x00 "GICD_IROUTER678,Interrupt Routing Register 678" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7538++0x07 line.quad 0x00 "GICD_IROUTER679,Interrupt Routing Register 679" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7540++0x07 line.quad 0x00 "GICD_IROUTER680,Interrupt Routing Register 680" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7548++0x07 line.quad 0x00 "GICD_IROUTER681,Interrupt Routing Register 681" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7550++0x07 line.quad 0x00 "GICD_IROUTER682,Interrupt Routing Register 682" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7558++0x07 line.quad 0x00 "GICD_IROUTER683,Interrupt Routing Register 683" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7560++0x07 line.quad 0x00 "GICD_IROUTER684,Interrupt Routing Register 684" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7568++0x07 line.quad 0x00 "GICD_IROUTER685,Interrupt Routing Register 685" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7570++0x07 line.quad 0x00 "GICD_IROUTER686,Interrupt Routing Register 686" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7578++0x07 line.quad 0x00 "GICD_IROUTER687,Interrupt Routing Register 687" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7580++0x07 line.quad 0x00 "GICD_IROUTER688,Interrupt Routing Register 688" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7588++0x07 line.quad 0x00 "GICD_IROUTER689,Interrupt Routing Register 689" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7590++0x07 line.quad 0x00 "GICD_IROUTER690,Interrupt Routing Register 690" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7598++0x07 line.quad 0x00 "GICD_IROUTER691,Interrupt Routing Register 691" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75A0++0x07 line.quad 0x00 "GICD_IROUTER692,Interrupt Routing Register 692" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75A8++0x07 line.quad 0x00 "GICD_IROUTER693,Interrupt Routing Register 693" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75B0++0x07 line.quad 0x00 "GICD_IROUTER694,Interrupt Routing Register 694" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75B8++0x07 line.quad 0x00 "GICD_IROUTER695,Interrupt Routing Register 695" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75C0++0x07 line.quad 0x00 "GICD_IROUTER696,Interrupt Routing Register 696" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75C8++0x07 line.quad 0x00 "GICD_IROUTER697,Interrupt Routing Register 697" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75D0++0x07 line.quad 0x00 "GICD_IROUTER698,Interrupt Routing Register 698" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75D8++0x07 line.quad 0x00 "GICD_IROUTER699,Interrupt Routing Register 699" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75E0++0x07 line.quad 0x00 "GICD_IROUTER700,Interrupt Routing Register 700" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75E8++0x07 line.quad 0x00 "GICD_IROUTER701,Interrupt Routing Register 701" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75F0++0x07 line.quad 0x00 "GICD_IROUTER702,Interrupt Routing Register 702" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75F8++0x07 line.quad 0x00 "GICD_IROUTER703,Interrupt Routing Register 703" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7600++0x07 line.quad 0x00 "GICD_IROUTER704,Interrupt Routing Register 704" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7608++0x07 line.quad 0x00 "GICD_IROUTER705,Interrupt Routing Register 705" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7610++0x07 line.quad 0x00 "GICD_IROUTER706,Interrupt Routing Register 706" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7618++0x07 line.quad 0x00 "GICD_IROUTER707,Interrupt Routing Register 707" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7620++0x07 line.quad 0x00 "GICD_IROUTER708,Interrupt Routing Register 708" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7628++0x07 line.quad 0x00 "GICD_IROUTER709,Interrupt Routing Register 709" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7630++0x07 line.quad 0x00 "GICD_IROUTER710,Interrupt Routing Register 710" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7638++0x07 line.quad 0x00 "GICD_IROUTER711,Interrupt Routing Register 711" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7640++0x07 line.quad 0x00 "GICD_IROUTER712,Interrupt Routing Register 712" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7648++0x07 line.quad 0x00 "GICD_IROUTER713,Interrupt Routing Register 713" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7650++0x07 line.quad 0x00 "GICD_IROUTER714,Interrupt Routing Register 714" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7658++0x07 line.quad 0x00 "GICD_IROUTER715,Interrupt Routing Register 715" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7660++0x07 line.quad 0x00 "GICD_IROUTER716,Interrupt Routing Register 716" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7668++0x07 line.quad 0x00 "GICD_IROUTER717,Interrupt Routing Register 717" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7670++0x07 line.quad 0x00 "GICD_IROUTER718,Interrupt Routing Register 718" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7678++0x07 line.quad 0x00 "GICD_IROUTER719,Interrupt Routing Register 719" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7680++0x07 line.quad 0x00 "GICD_IROUTER720,Interrupt Routing Register 720" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7688++0x07 line.quad 0x00 "GICD_IROUTER721,Interrupt Routing Register 721" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7690++0x07 line.quad 0x00 "GICD_IROUTER722,Interrupt Routing Register 722" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7698++0x07 line.quad 0x00 "GICD_IROUTER723,Interrupt Routing Register 723" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76A0++0x07 line.quad 0x00 "GICD_IROUTER724,Interrupt Routing Register 724" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76A8++0x07 line.quad 0x00 "GICD_IROUTER725,Interrupt Routing Register 725" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76B0++0x07 line.quad 0x00 "GICD_IROUTER726,Interrupt Routing Register 726" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76B8++0x07 line.quad 0x00 "GICD_IROUTER727,Interrupt Routing Register 727" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76C0++0x07 line.quad 0x00 "GICD_IROUTER728,Interrupt Routing Register 728" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76C8++0x07 line.quad 0x00 "GICD_IROUTER729,Interrupt Routing Register 729" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76D0++0x07 line.quad 0x00 "GICD_IROUTER730,Interrupt Routing Register 730" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76D8++0x07 line.quad 0x00 "GICD_IROUTER731,Interrupt Routing Register 731" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76E0++0x07 line.quad 0x00 "GICD_IROUTER732,Interrupt Routing Register 732" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76E8++0x07 line.quad 0x00 "GICD_IROUTER733,Interrupt Routing Register 733" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76F0++0x07 line.quad 0x00 "GICD_IROUTER734,Interrupt Routing Register 734" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76F8++0x07 line.quad 0x00 "GICD_IROUTER735,Interrupt Routing Register 735" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7700++0x07 line.quad 0x00 "GICD_IROUTER736,Interrupt Routing Register 736" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7708++0x07 line.quad 0x00 "GICD_IROUTER737,Interrupt Routing Register 737" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7710++0x07 line.quad 0x00 "GICD_IROUTER738,Interrupt Routing Register 738" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7718++0x07 line.quad 0x00 "GICD_IROUTER739,Interrupt Routing Register 739" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7720++0x07 line.quad 0x00 "GICD_IROUTER740,Interrupt Routing Register 740" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7728++0x07 line.quad 0x00 "GICD_IROUTER741,Interrupt Routing Register 741" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7730++0x07 line.quad 0x00 "GICD_IROUTER742,Interrupt Routing Register 742" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7738++0x07 line.quad 0x00 "GICD_IROUTER743,Interrupt Routing Register 743" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7740++0x07 line.quad 0x00 "GICD_IROUTER744,Interrupt Routing Register 744" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7748++0x07 line.quad 0x00 "GICD_IROUTER745,Interrupt Routing Register 745" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7750++0x07 line.quad 0x00 "GICD_IROUTER746,Interrupt Routing Register 746" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7758++0x07 line.quad 0x00 "GICD_IROUTER747,Interrupt Routing Register 747" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7760++0x07 line.quad 0x00 "GICD_IROUTER748,Interrupt Routing Register 748" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7768++0x07 line.quad 0x00 "GICD_IROUTER749,Interrupt Routing Register 749" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7770++0x07 line.quad 0x00 "GICD_IROUTER750,Interrupt Routing Register 750" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7778++0x07 line.quad 0x00 "GICD_IROUTER751,Interrupt Routing Register 751" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7780++0x07 line.quad 0x00 "GICD_IROUTER752,Interrupt Routing Register 752" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7788++0x07 line.quad 0x00 "GICD_IROUTER753,Interrupt Routing Register 753" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7790++0x07 line.quad 0x00 "GICD_IROUTER754,Interrupt Routing Register 754" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7798++0x07 line.quad 0x00 "GICD_IROUTER755,Interrupt Routing Register 755" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77A0++0x07 line.quad 0x00 "GICD_IROUTER756,Interrupt Routing Register 756" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77A8++0x07 line.quad 0x00 "GICD_IROUTER757,Interrupt Routing Register 757" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77B0++0x07 line.quad 0x00 "GICD_IROUTER758,Interrupt Routing Register 758" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77B8++0x07 line.quad 0x00 "GICD_IROUTER759,Interrupt Routing Register 759" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77C0++0x07 line.quad 0x00 "GICD_IROUTER760,Interrupt Routing Register 760" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77C8++0x07 line.quad 0x00 "GICD_IROUTER761,Interrupt Routing Register 761" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77D0++0x07 line.quad 0x00 "GICD_IROUTER762,Interrupt Routing Register 762" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77D8++0x07 line.quad 0x00 "GICD_IROUTER763,Interrupt Routing Register 763" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77E0++0x07 line.quad 0x00 "GICD_IROUTER764,Interrupt Routing Register 764" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77E8++0x07 line.quad 0x00 "GICD_IROUTER765,Interrupt Routing Register 765" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77F0++0x07 line.quad 0x00 "GICD_IROUTER766,Interrupt Routing Register 766" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77F8++0x07 line.quad 0x00 "GICD_IROUTER767,Interrupt Routing Register 767" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7800++0x07 line.quad 0x00 "GICD_IROUTER768,Interrupt Routing Register 768" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7808++0x07 line.quad 0x00 "GICD_IROUTER769,Interrupt Routing Register 769" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7810++0x07 line.quad 0x00 "GICD_IROUTER770,Interrupt Routing Register 770" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7818++0x07 line.quad 0x00 "GICD_IROUTER771,Interrupt Routing Register 771" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7820++0x07 line.quad 0x00 "GICD_IROUTER772,Interrupt Routing Register 772" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7828++0x07 line.quad 0x00 "GICD_IROUTER773,Interrupt Routing Register 773" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7830++0x07 line.quad 0x00 "GICD_IROUTER774,Interrupt Routing Register 774" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7838++0x07 line.quad 0x00 "GICD_IROUTER775,Interrupt Routing Register 775" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7840++0x07 line.quad 0x00 "GICD_IROUTER776,Interrupt Routing Register 776" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7848++0x07 line.quad 0x00 "GICD_IROUTER777,Interrupt Routing Register 777" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7850++0x07 line.quad 0x00 "GICD_IROUTER778,Interrupt Routing Register 778" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7858++0x07 line.quad 0x00 "GICD_IROUTER779,Interrupt Routing Register 779" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7860++0x07 line.quad 0x00 "GICD_IROUTER780,Interrupt Routing Register 780" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7868++0x07 line.quad 0x00 "GICD_IROUTER781,Interrupt Routing Register 781" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7870++0x07 line.quad 0x00 "GICD_IROUTER782,Interrupt Routing Register 782" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7878++0x07 line.quad 0x00 "GICD_IROUTER783,Interrupt Routing Register 783" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7880++0x07 line.quad 0x00 "GICD_IROUTER784,Interrupt Routing Register 784" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7888++0x07 line.quad 0x00 "GICD_IROUTER785,Interrupt Routing Register 785" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7890++0x07 line.quad 0x00 "GICD_IROUTER786,Interrupt Routing Register 786" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7898++0x07 line.quad 0x00 "GICD_IROUTER787,Interrupt Routing Register 787" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78A0++0x07 line.quad 0x00 "GICD_IROUTER788,Interrupt Routing Register 788" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78A8++0x07 line.quad 0x00 "GICD_IROUTER789,Interrupt Routing Register 789" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78B0++0x07 line.quad 0x00 "GICD_IROUTER790,Interrupt Routing Register 790" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78B8++0x07 line.quad 0x00 "GICD_IROUTER791,Interrupt Routing Register 791" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78C0++0x07 line.quad 0x00 "GICD_IROUTER792,Interrupt Routing Register 792" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78C8++0x07 line.quad 0x00 "GICD_IROUTER793,Interrupt Routing Register 793" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78D0++0x07 line.quad 0x00 "GICD_IROUTER794,Interrupt Routing Register 794" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78D8++0x07 line.quad 0x00 "GICD_IROUTER795,Interrupt Routing Register 795" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78E0++0x07 line.quad 0x00 "GICD_IROUTER796,Interrupt Routing Register 796" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78E8++0x07 line.quad 0x00 "GICD_IROUTER797,Interrupt Routing Register 797" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78F0++0x07 line.quad 0x00 "GICD_IROUTER798,Interrupt Routing Register 798" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78F8++0x07 line.quad 0x00 "GICD_IROUTER799,Interrupt Routing Register 799" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7900++0x07 line.quad 0x00 "GICD_IROUTER800,Interrupt Routing Register 800" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7908++0x07 line.quad 0x00 "GICD_IROUTER801,Interrupt Routing Register 801" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7910++0x07 line.quad 0x00 "GICD_IROUTER802,Interrupt Routing Register 802" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7918++0x07 line.quad 0x00 "GICD_IROUTER803,Interrupt Routing Register 803" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7920++0x07 line.quad 0x00 "GICD_IROUTER804,Interrupt Routing Register 804" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7928++0x07 line.quad 0x00 "GICD_IROUTER805,Interrupt Routing Register 805" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7930++0x07 line.quad 0x00 "GICD_IROUTER806,Interrupt Routing Register 806" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7938++0x07 line.quad 0x00 "GICD_IROUTER807,Interrupt Routing Register 807" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7940++0x07 line.quad 0x00 "GICD_IROUTER808,Interrupt Routing Register 808" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7948++0x07 line.quad 0x00 "GICD_IROUTER809,Interrupt Routing Register 809" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7950++0x07 line.quad 0x00 "GICD_IROUTER810,Interrupt Routing Register 810" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7958++0x07 line.quad 0x00 "GICD_IROUTER811,Interrupt Routing Register 811" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7960++0x07 line.quad 0x00 "GICD_IROUTER812,Interrupt Routing Register 812" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7968++0x07 line.quad 0x00 "GICD_IROUTER813,Interrupt Routing Register 813" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7970++0x07 line.quad 0x00 "GICD_IROUTER814,Interrupt Routing Register 814" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7978++0x07 line.quad 0x00 "GICD_IROUTER815,Interrupt Routing Register 815" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7980++0x07 line.quad 0x00 "GICD_IROUTER816,Interrupt Routing Register 816" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7988++0x07 line.quad 0x00 "GICD_IROUTER817,Interrupt Routing Register 817" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7990++0x07 line.quad 0x00 "GICD_IROUTER818,Interrupt Routing Register 818" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7998++0x07 line.quad 0x00 "GICD_IROUTER819,Interrupt Routing Register 819" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79A0++0x07 line.quad 0x00 "GICD_IROUTER820,Interrupt Routing Register 820" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79A8++0x07 line.quad 0x00 "GICD_IROUTER821,Interrupt Routing Register 821" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79B0++0x07 line.quad 0x00 "GICD_IROUTER822,Interrupt Routing Register 822" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79B8++0x07 line.quad 0x00 "GICD_IROUTER823,Interrupt Routing Register 823" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79C0++0x07 line.quad 0x00 "GICD_IROUTER824,Interrupt Routing Register 824" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79C8++0x07 line.quad 0x00 "GICD_IROUTER825,Interrupt Routing Register 825" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79D0++0x07 line.quad 0x00 "GICD_IROUTER826,Interrupt Routing Register 826" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79D8++0x07 line.quad 0x00 "GICD_IROUTER827,Interrupt Routing Register 827" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79E0++0x07 line.quad 0x00 "GICD_IROUTER828,Interrupt Routing Register 828" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79E8++0x07 line.quad 0x00 "GICD_IROUTER829,Interrupt Routing Register 829" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79F0++0x07 line.quad 0x00 "GICD_IROUTER830,Interrupt Routing Register 830" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79F8++0x07 line.quad 0x00 "GICD_IROUTER831,Interrupt Routing Register 831" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A00++0x07 line.quad 0x00 "GICD_IROUTER832,Interrupt Routing Register 832" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A08++0x07 line.quad 0x00 "GICD_IROUTER833,Interrupt Routing Register 833" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A10++0x07 line.quad 0x00 "GICD_IROUTER834,Interrupt Routing Register 834" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A18++0x07 line.quad 0x00 "GICD_IROUTER835,Interrupt Routing Register 835" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A20++0x07 line.quad 0x00 "GICD_IROUTER836,Interrupt Routing Register 836" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A28++0x07 line.quad 0x00 "GICD_IROUTER837,Interrupt Routing Register 837" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A30++0x07 line.quad 0x00 "GICD_IROUTER838,Interrupt Routing Register 838" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A38++0x07 line.quad 0x00 "GICD_IROUTER839,Interrupt Routing Register 839" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A40++0x07 line.quad 0x00 "GICD_IROUTER840,Interrupt Routing Register 840" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A48++0x07 line.quad 0x00 "GICD_IROUTER841,Interrupt Routing Register 841" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A50++0x07 line.quad 0x00 "GICD_IROUTER842,Interrupt Routing Register 842" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A58++0x07 line.quad 0x00 "GICD_IROUTER843,Interrupt Routing Register 843" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A60++0x07 line.quad 0x00 "GICD_IROUTER844,Interrupt Routing Register 844" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A68++0x07 line.quad 0x00 "GICD_IROUTER845,Interrupt Routing Register 845" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A70++0x07 line.quad 0x00 "GICD_IROUTER846,Interrupt Routing Register 846" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A78++0x07 line.quad 0x00 "GICD_IROUTER847,Interrupt Routing Register 847" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A80++0x07 line.quad 0x00 "GICD_IROUTER848,Interrupt Routing Register 848" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A88++0x07 line.quad 0x00 "GICD_IROUTER849,Interrupt Routing Register 849" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A90++0x07 line.quad 0x00 "GICD_IROUTER850,Interrupt Routing Register 850" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A98++0x07 line.quad 0x00 "GICD_IROUTER851,Interrupt Routing Register 851" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AA0++0x07 line.quad 0x00 "GICD_IROUTER852,Interrupt Routing Register 852" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AA8++0x07 line.quad 0x00 "GICD_IROUTER853,Interrupt Routing Register 853" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AB0++0x07 line.quad 0x00 "GICD_IROUTER854,Interrupt Routing Register 854" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AB8++0x07 line.quad 0x00 "GICD_IROUTER855,Interrupt Routing Register 855" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AC0++0x07 line.quad 0x00 "GICD_IROUTER856,Interrupt Routing Register 856" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AC8++0x07 line.quad 0x00 "GICD_IROUTER857,Interrupt Routing Register 857" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AD0++0x07 line.quad 0x00 "GICD_IROUTER858,Interrupt Routing Register 858" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AD8++0x07 line.quad 0x00 "GICD_IROUTER859,Interrupt Routing Register 859" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AE0++0x07 line.quad 0x00 "GICD_IROUTER860,Interrupt Routing Register 860" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AE8++0x07 line.quad 0x00 "GICD_IROUTER861,Interrupt Routing Register 861" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AF0++0x07 line.quad 0x00 "GICD_IROUTER862,Interrupt Routing Register 862" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AF8++0x07 line.quad 0x00 "GICD_IROUTER863,Interrupt Routing Register 863" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B00++0x07 line.quad 0x00 "GICD_IROUTER864,Interrupt Routing Register 864" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B08++0x07 line.quad 0x00 "GICD_IROUTER865,Interrupt Routing Register 865" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B10++0x07 line.quad 0x00 "GICD_IROUTER866,Interrupt Routing Register 866" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B18++0x07 line.quad 0x00 "GICD_IROUTER867,Interrupt Routing Register 867" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B20++0x07 line.quad 0x00 "GICD_IROUTER868,Interrupt Routing Register 868" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B28++0x07 line.quad 0x00 "GICD_IROUTER869,Interrupt Routing Register 869" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B30++0x07 line.quad 0x00 "GICD_IROUTER870,Interrupt Routing Register 870" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B38++0x07 line.quad 0x00 "GICD_IROUTER871,Interrupt Routing Register 871" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B40++0x07 line.quad 0x00 "GICD_IROUTER872,Interrupt Routing Register 872" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B48++0x07 line.quad 0x00 "GICD_IROUTER873,Interrupt Routing Register 873" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B50++0x07 line.quad 0x00 "GICD_IROUTER874,Interrupt Routing Register 874" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B58++0x07 line.quad 0x00 "GICD_IROUTER875,Interrupt Routing Register 875" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B60++0x07 line.quad 0x00 "GICD_IROUTER876,Interrupt Routing Register 876" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B68++0x07 line.quad 0x00 "GICD_IROUTER877,Interrupt Routing Register 877" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B70++0x07 line.quad 0x00 "GICD_IROUTER878,Interrupt Routing Register 878" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B78++0x07 line.quad 0x00 "GICD_IROUTER879,Interrupt Routing Register 879" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B80++0x07 line.quad 0x00 "GICD_IROUTER880,Interrupt Routing Register 880" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B88++0x07 line.quad 0x00 "GICD_IROUTER881,Interrupt Routing Register 881" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B90++0x07 line.quad 0x00 "GICD_IROUTER882,Interrupt Routing Register 882" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B98++0x07 line.quad 0x00 "GICD_IROUTER883,Interrupt Routing Register 883" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BA0++0x07 line.quad 0x00 "GICD_IROUTER884,Interrupt Routing Register 884" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BA8++0x07 line.quad 0x00 "GICD_IROUTER885,Interrupt Routing Register 885" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BB0++0x07 line.quad 0x00 "GICD_IROUTER886,Interrupt Routing Register 886" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BB8++0x07 line.quad 0x00 "GICD_IROUTER887,Interrupt Routing Register 887" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BC0++0x07 line.quad 0x00 "GICD_IROUTER888,Interrupt Routing Register 888" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BC8++0x07 line.quad 0x00 "GICD_IROUTER889,Interrupt Routing Register 889" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BD0++0x07 line.quad 0x00 "GICD_IROUTER890,Interrupt Routing Register 890" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BD8++0x07 line.quad 0x00 "GICD_IROUTER891,Interrupt Routing Register 891" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BE0++0x07 line.quad 0x00 "GICD_IROUTER892,Interrupt Routing Register 892" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BE8++0x07 line.quad 0x00 "GICD_IROUTER893,Interrupt Routing Register 893" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BF0++0x07 line.quad 0x00 "GICD_IROUTER894,Interrupt Routing Register 894" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BF8++0x07 line.quad 0x00 "GICD_IROUTER895,Interrupt Routing Register 895" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C00++0x07 line.quad 0x00 "GICD_IROUTER896,Interrupt Routing Register 896" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C08++0x07 line.quad 0x00 "GICD_IROUTER897,Interrupt Routing Register 897" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C10++0x07 line.quad 0x00 "GICD_IROUTER898,Interrupt Routing Register 898" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C18++0x07 line.quad 0x00 "GICD_IROUTER899,Interrupt Routing Register 899" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C20++0x07 line.quad 0x00 "GICD_IROUTER900,Interrupt Routing Register 900" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C28++0x07 line.quad 0x00 "GICD_IROUTER901,Interrupt Routing Register 901" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C30++0x07 line.quad 0x00 "GICD_IROUTER902,Interrupt Routing Register 902" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C38++0x07 line.quad 0x00 "GICD_IROUTER903,Interrupt Routing Register 903" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C40++0x07 line.quad 0x00 "GICD_IROUTER904,Interrupt Routing Register 904" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C48++0x07 line.quad 0x00 "GICD_IROUTER905,Interrupt Routing Register 905" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C50++0x07 line.quad 0x00 "GICD_IROUTER906,Interrupt Routing Register 906" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C58++0x07 line.quad 0x00 "GICD_IROUTER907,Interrupt Routing Register 907" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C60++0x07 line.quad 0x00 "GICD_IROUTER908,Interrupt Routing Register 908" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C68++0x07 line.quad 0x00 "GICD_IROUTER909,Interrupt Routing Register 909" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C70++0x07 line.quad 0x00 "GICD_IROUTER910,Interrupt Routing Register 910" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C78++0x07 line.quad 0x00 "GICD_IROUTER911,Interrupt Routing Register 911" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C80++0x07 line.quad 0x00 "GICD_IROUTER912,Interrupt Routing Register 912" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C88++0x07 line.quad 0x00 "GICD_IROUTER913,Interrupt Routing Register 913" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C90++0x07 line.quad 0x00 "GICD_IROUTER914,Interrupt Routing Register 914" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C98++0x07 line.quad 0x00 "GICD_IROUTER915,Interrupt Routing Register 915" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CA0++0x07 line.quad 0x00 "GICD_IROUTER916,Interrupt Routing Register 916" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CA8++0x07 line.quad 0x00 "GICD_IROUTER917,Interrupt Routing Register 917" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CB0++0x07 line.quad 0x00 "GICD_IROUTER918,Interrupt Routing Register 918" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CB8++0x07 line.quad 0x00 "GICD_IROUTER919,Interrupt Routing Register 919" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CC0++0x07 line.quad 0x00 "GICD_IROUTER920,Interrupt Routing Register 920" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CC8++0x07 line.quad 0x00 "GICD_IROUTER921,Interrupt Routing Register 921" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CD0++0x07 line.quad 0x00 "GICD_IROUTER922,Interrupt Routing Register 922" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CD8++0x07 line.quad 0x00 "GICD_IROUTER923,Interrupt Routing Register 923" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CE0++0x07 line.quad 0x00 "GICD_IROUTER924,Interrupt Routing Register 924" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CE8++0x07 line.quad 0x00 "GICD_IROUTER925,Interrupt Routing Register 925" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CF0++0x07 line.quad 0x00 "GICD_IROUTER926,Interrupt Routing Register 926" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CF8++0x07 line.quad 0x00 "GICD_IROUTER927,Interrupt Routing Register 927" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D00++0x07 line.quad 0x00 "GICD_IROUTER928,Interrupt Routing Register 928" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D08++0x07 line.quad 0x00 "GICD_IROUTER929,Interrupt Routing Register 929" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D10++0x07 line.quad 0x00 "GICD_IROUTER930,Interrupt Routing Register 930" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D18++0x07 line.quad 0x00 "GICD_IROUTER931,Interrupt Routing Register 931" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D20++0x07 line.quad 0x00 "GICD_IROUTER932,Interrupt Routing Register 932" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D28++0x07 line.quad 0x00 "GICD_IROUTER933,Interrupt Routing Register 933" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D30++0x07 line.quad 0x00 "GICD_IROUTER934,Interrupt Routing Register 934" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D38++0x07 line.quad 0x00 "GICD_IROUTER935,Interrupt Routing Register 935" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D40++0x07 line.quad 0x00 "GICD_IROUTER936,Interrupt Routing Register 936" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D48++0x07 line.quad 0x00 "GICD_IROUTER937,Interrupt Routing Register 937" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D50++0x07 line.quad 0x00 "GICD_IROUTER938,Interrupt Routing Register 938" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D58++0x07 line.quad 0x00 "GICD_IROUTER939,Interrupt Routing Register 939" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D60++0x07 line.quad 0x00 "GICD_IROUTER940,Interrupt Routing Register 940" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D68++0x07 line.quad 0x00 "GICD_IROUTER941,Interrupt Routing Register 941" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D70++0x07 line.quad 0x00 "GICD_IROUTER942,Interrupt Routing Register 942" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D78++0x07 line.quad 0x00 "GICD_IROUTER943,Interrupt Routing Register 943" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D80++0x07 line.quad 0x00 "GICD_IROUTER944,Interrupt Routing Register 944" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D88++0x07 line.quad 0x00 "GICD_IROUTER945,Interrupt Routing Register 945" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D90++0x07 line.quad 0x00 "GICD_IROUTER946,Interrupt Routing Register 946" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D98++0x07 line.quad 0x00 "GICD_IROUTER947,Interrupt Routing Register 947" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DA0++0x07 line.quad 0x00 "GICD_IROUTER948,Interrupt Routing Register 948" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DA8++0x07 line.quad 0x00 "GICD_IROUTER949,Interrupt Routing Register 949" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DB0++0x07 line.quad 0x00 "GICD_IROUTER950,Interrupt Routing Register 950" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DB8++0x07 line.quad 0x00 "GICD_IROUTER951,Interrupt Routing Register 951" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DC0++0x07 line.quad 0x00 "GICD_IROUTER952,Interrupt Routing Register 952" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DC8++0x07 line.quad 0x00 "GICD_IROUTER953,Interrupt Routing Register 953" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DD0++0x07 line.quad 0x00 "GICD_IROUTER954,Interrupt Routing Register 954" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DD8++0x07 line.quad 0x00 "GICD_IROUTER955,Interrupt Routing Register 955" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DE0++0x07 line.quad 0x00 "GICD_IROUTER956,Interrupt Routing Register 956" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DE8++0x07 line.quad 0x00 "GICD_IROUTER957,Interrupt Routing Register 957" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DF0++0x07 line.quad 0x00 "GICD_IROUTER958,Interrupt Routing Register 958" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DF8++0x07 line.quad 0x00 "GICD_IROUTER959,Interrupt Routing Register 959" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E00++0x07 line.quad 0x00 "GICD_IROUTER960,Interrupt Routing Register 960" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E08++0x07 line.quad 0x00 "GICD_IROUTER961,Interrupt Routing Register 961" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E10++0x07 line.quad 0x00 "GICD_IROUTER962,Interrupt Routing Register 962" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E18++0x07 line.quad 0x00 "GICD_IROUTER963,Interrupt Routing Register 963" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E20++0x07 line.quad 0x00 "GICD_IROUTER964,Interrupt Routing Register 964" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E28++0x07 line.quad 0x00 "GICD_IROUTER965,Interrupt Routing Register 965" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E30++0x07 line.quad 0x00 "GICD_IROUTER966,Interrupt Routing Register 966" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E38++0x07 line.quad 0x00 "GICD_IROUTER967,Interrupt Routing Register 967" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E40++0x07 line.quad 0x00 "GICD_IROUTER968,Interrupt Routing Register 968" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E48++0x07 line.quad 0x00 "GICD_IROUTER969,Interrupt Routing Register 969" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E50++0x07 line.quad 0x00 "GICD_IROUTER970,Interrupt Routing Register 970" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E58++0x07 line.quad 0x00 "GICD_IROUTER971,Interrupt Routing Register 971" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E60++0x07 line.quad 0x00 "GICD_IROUTER972,Interrupt Routing Register 972" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E68++0x07 line.quad 0x00 "GICD_IROUTER973,Interrupt Routing Register 973" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E70++0x07 line.quad 0x00 "GICD_IROUTER974,Interrupt Routing Register 974" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E78++0x07 line.quad 0x00 "GICD_IROUTER975,Interrupt Routing Register 975" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E80++0x07 line.quad 0x00 "GICD_IROUTER976,Interrupt Routing Register 976" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E88++0x07 line.quad 0x00 "GICD_IROUTER977,Interrupt Routing Register 977" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E90++0x07 line.quad 0x00 "GICD_IROUTER978,Interrupt Routing Register 978" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E98++0x07 line.quad 0x00 "GICD_IROUTER979,Interrupt Routing Register 979" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EA0++0x07 line.quad 0x00 "GICD_IROUTER980,Interrupt Routing Register 980" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EA8++0x07 line.quad 0x00 "GICD_IROUTER981,Interrupt Routing Register 981" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EB0++0x07 line.quad 0x00 "GICD_IROUTER982,Interrupt Routing Register 982" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EB8++0x07 line.quad 0x00 "GICD_IROUTER983,Interrupt Routing Register 983" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EC0++0x07 line.quad 0x00 "GICD_IROUTER984,Interrupt Routing Register 984" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EC8++0x07 line.quad 0x00 "GICD_IROUTER985,Interrupt Routing Register 985" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7ED0++0x07 line.quad 0x00 "GICD_IROUTER986,Interrupt Routing Register 986" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7ED8++0x07 line.quad 0x00 "GICD_IROUTER987,Interrupt Routing Register 987" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EE0++0x07 line.quad 0x00 "GICD_IROUTER988,Interrupt Routing Register 988" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EE8++0x07 line.quad 0x00 "GICD_IROUTER989,Interrupt Routing Register 989" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EF0++0x07 line.quad 0x00 "GICD_IROUTER990,Interrupt Routing Register 990" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EF8++0x07 line.quad 0x00 "GICD_IROUTER991,Interrupt Routing Register 991" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.long 0xFFE0++0x03 line.long 0x00 "GICD_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFE4++0x03 line.long 0x00 "GICD_PIDR1,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFE8++0x03 line.long 0x00 "GICD_PIDR2,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFEC++0x03 line.long 0x00 "GICD_PIDR3,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFD0++0x03 line.long 0x00 "GICD_PIDR4,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFD4++0x03 line.long 0x00 "GICD_PIDR5,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFD8++0x03 line.long 0x00 "GICD_PIDR6,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFDC++0x03 line.long 0x00 "GICD_PIDR7,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" textline " " rgroup.long 0xFFF0++0x03 line.long 0x00 "GICD_CIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFF4++0x03 line.long 0x00 "GICD_CIDR1,Component ID1 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFF8++0x03 line.long 0x00 "GICD_CIDR2,Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFFC++0x03 line.long 0x00 "GICD_CIDR3,Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" textline " " tree.end tree.end width 0x0B base COMP.BASE("GICR",-1.) width 15. tree "Redistributor Interface" tree "Control Registers" rgroup.long 0x00++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" bitfld.long 0x00 31. " UWP ,Upstream writes pending" "Not pending,?..." bitfld.long 0x00 3. " RWP ,Register Write Pending" "Not pending,Pending" rgroup.long 0x0004++0x03 line.long 0x00 "GICR_IIDR,Distributor Implementer Identification Register" hexmask.long.byte 0x00 24.--31. 1. " PRODUCTID ,Product ID" bitfld.long 0x00 16.--19. " VARIANT ,Major revision number" "Reserved,r1p3,?..." textline " " bitfld.long 0x00 12.--15. " REVISION ,Minor revision number" "Reserved,Reserved,Reserved,r1p3,?..." hexmask.long.word 0x00 0.--11. 1. " IMPLEMENTER ,Implementer" rgroup.quad 0x0008++0x07 line.quad 0x00 "GICR_TYPER,Redistributor Type Register" hexmask.quad.byte 0x00 32.--39. 1. " AFF0 ,Affinity level 0" hexmask.quad.word 0x00 8.--23. 1. " PROCESSOR_NUMBER ,Processor Number" textline " " bitfld.quad 0x00 5. " DPGS ,GICR_CTLR.DPG* bits support" "Not supported,?..." bitfld.quad 0x00 4. " LAST ,Last numbered Redistributor" "Not last,Last" bitfld.quad 0x00 3. " DIRECTLPI ,Direct injection of LPIs support" "Not supported,?..." textline " " bitfld.quad 0x00 1. " VLPIS ,Virtual LPIs support" "Not supported,?..." bitfld.quad 0x00 0. " PLPIS ,Physical LPI support" "Not supported,?..." group.long 0x0014++0x03 line.long 0x00 "GICR_WAKER,Redistributor Wake Register" bitfld.long 0x00 2. " CHILDRENASLEEP ,Connected target quiescent" "Not quiescent,Quiescent" bitfld.long 0x00 1. " PROCESSORSLEEP ,Target is entering the processor sleep state" "No,Yes" tree.end tree "SGI and PPI Registers" group.long 0x10080++0x03 line.long 0x00 "GICR_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " PPIS[15] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 30. " PPIS[14] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 29. " PPIS[13] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " PPIS[12] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 27. " PPIS[11] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 26. " PPIS[10] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " PPIS[9] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 24. " PPIS[8] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 23. " PPIS[7] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " PPIS[6] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 21. " PPIS[5] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 20. " PPIS[4] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " PPIS[3] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 18. " PPIS[2] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 17. " PPIS[1] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " PPIS[0] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 15. " SGI[15] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" bitfld.long 0x00 14. " SGI[14] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " SGI[13] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" bitfld.long 0x00 12. " SGI[12] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" bitfld.long 0x00 11. " SGI[11] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " SGI[10] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" bitfld.long 0x00 9. " SGI[9] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" bitfld.long 0x00 8. " SGI[8] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " SGI[7] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" bitfld.long 0x00 6. " SGI[6] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" bitfld.long 0x00 5. " SGI[5] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " SGI[4] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" bitfld.long 0x00 3. " SGI[3] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" bitfld.long 0x00 2. " SGI[2] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " SGI[1] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" bitfld.long 0x00 0. " SGI[0] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" textline " " width 24. group.long 0x10100++0x03 line.long 0x00 "GICR_ISET/CLR_ENABLER0,Interrupt Group Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PPI[15] ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PPI[14] ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PPI[13] ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PPI[12] ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PPI[11] ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PPI[10] ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PPI[9] ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PPI[8] ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PPI[7] ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PPI[6] ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PPI[5] ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PPI[4] ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PPI[3] ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PPI[2] ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PPI[1] ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PPI[0] ,Set/Clear Enable Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SGI[15] ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SGI[14] ,Set/Clear Enable Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SGI[13] ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SGI[12] ,Set/Clear Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SGI[11] ,Set/Clear Enable Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SGI[10] ,Set/Clear Enable Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SGI[9] ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SGI[8] ,Set/Clear Enable Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SGI[7] ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SGI[6] ,Set/Clear Enable Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SGI[5] ,Set/Clear Enable Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SGI[4] ,Set/Clear Enable Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SGI[3] ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SGI[2] ,Set/Clear Enable Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SGI[1] ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SGI[0] ,Set/Clear Enable Bit 0" "Disabled,Enabled" group.long 0x10200++0x03 line.long 0x00 "GICR_ISET/CLR_PENDR0,Interrupt Set/Clear-Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PPI[15] ,Set/Clear Pending Bit 31" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PPI[14] ,Set/Clear Pending Bit 30" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PPI[13] ,Set/Clear Pending Bit 29" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PPI[12] ,Set/Clear Pending Bit 28" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PPI[11] ,Set/Clear Pending Bit 27" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PPI[10] ,Set/Clear Pending Bit 26" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PPI[9] ,Set/Clear Pending Bit 25" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PPI[8] ,Set/Clear Pending Bit 24" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PPI[7] ,Set/Clear Pending Bit 23" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PPI[6] ,Set/Clear Pending Bit 22" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PPI[5] ,Set/Clear Pending Bit 21" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PPI[4] ,Set/Clear Pending Bit 20" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PPI[3] ,Set/Clear Pending Bit 19" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PPI[2] ,Set/Clear Pending Bit 18" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PPI[1] ,Set/Clear Pending Bit 17" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PPI[0] ,Set/Clear Pending Bit 16" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SGI[15] ,Set/Clear Pending Bit 15" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SGI[14] ,Set/Clear Pending Bit 14" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SGI[13] ,Set/Clear Pending Bit 13" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SGI[12] ,Set/Clear Pending Bit 12" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SGI[11] ,Set/Clear Pending Bit 11" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SGI[10] ,Set/Clear Pending Bit 10" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SGI[9] ,Set/Clear Pending Bit 9" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SGI[8] ,Set/Clear Pending Bit 8" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SGI[7] ,Set/Clear Pending Bit 7" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SGI[6] ,Set/Clear Pending Bit 6" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SGI[5] ,Set/Clear Pending Bit 5" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SGI[4] ,Set/Clear Pending Bit 4" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SGI[3] ,Set/Clear Pending Bit 3" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SGI[2] ,Set/Clear Pending Bit 2" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SGI[1] ,Set/Clear Pending Bit 1" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SGI[0] ,Set/Clear Pending Bit 0" "Not pending,Pending" group.long 0x10300++0x03 line.long 0x00 "GICR_ISET/CLR_ACTIVER0,Interrupt Set/Clear-Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PPI[15] ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PPI[14] ,Set/Clear Active Bit 30" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PPI[13] ,Set/Clear Active Bit 29" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PPI[12] ,Set/Clear Active Bit 28" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PPI[11] ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PPI[10] ,Set/Clear Active Bit 26" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PPI[9] ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PPI[8] ,Set/Clear Active Bit 24" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PPI[7] ,Set/Clear Active Bit 23" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PPI[6] ,Set/Clear Active Bit 22" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PPI[5] ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PPI[4] ,Set/Clear Active Bit 20" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PPI[3] ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PPI[2] ,Set/Clear Active Bit 18" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PPI[1] ,Set/Clear Active Bit 17" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PPI[0] ,Set/Clear Active Bit 16" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SGI[15] ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SGI[14] ,Set/Clear Active Bit 14" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SGI[13] ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SGI[12] ,Set/Clear Active Bit 12" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SGI[11] ,Set/Clear Active Bit 11" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SGI[10] ,Set/Clear Active Bit 10" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SGI[9] ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SGI[8] ,Set/Clear Active Bit 8" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SGI[7] ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SGI[6] ,Set/Clear Active Bit 6" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SGI[5] ,Set/Clear Active Bit 5" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SGI[4] ,Set/Clear Active Bit 4" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SGI[3] ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SGI[2] ,Set/Clear Active Bit 2" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SGI[1] ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SGI[0] ,Set/Clear Active Bit 0" "Not active,Active" textline " " width 18. group.long 0x10400++0x03 line.long 0x00 "GICR_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 27.--31. 1. " PRI3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 19.--23. 1. " PRI2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 11.--15. 1. " PRI1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 3.--7. 1. " PRI0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x10404++0x03 line.long 0x00 "GICR_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 27.--31. 1. " PRI7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 19.--23. 1. " PRI6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 11.--15. 1. " PRI5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 3.--7. 1. " PRI4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x10408++0x03 line.long 0x00 "GICR_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 27.--31. 1. " PRI11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 19.--23. 1. " PRI10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 11.--15. 1. " PRI9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 3.--7. 1. " PRI8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x1040C++0x03 line.long 0x00 "GICR_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 27.--31. 1. " PRI15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 19.--23. 1. " PRI14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 11.--15. 1. " PRI13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 3.--7. 1. " PRI12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x10410++0x03 line.long 0x00 "GICR_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 27.--31. 1. " PRI19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 19.--23. 1. " PRI18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 11.--15. 1. " PRI17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 3.--7. 1. " PRI16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x10414++0x03 line.long 0x00 "GICR_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 27.--31. 1. " PRI23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 19.--23. 1. " PRI22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 11.--15. 1. " PRI21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 3.--7. 1. " PRI20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x10418++0x03 line.long 0x00 "GICR_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 27.--31. 1. " PRI27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 19.--23. 1. " PRI26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 11.--15. 1. " PRI25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 3.--7. 1. " PRI24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x1041C++0x03 line.long 0x00 "GICR_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 27.--31. 1. " PRI31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 19.--23. 1. " PRI30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 11.--15. 1. " PRI29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 3.--7. 1. " PRI28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " textline " " rgroup.long 0x10C00++0x03 line.long 0x00 "GICR_ICFGR0,Interrupt Configuration Register 0" bitfld.long 0x00 31. " ICF[15] ,Interrupt configuration 15 (SGI)" "Level,Edge" bitfld.long 0x00 29. " ICF[14] ,Interrupt configuration 14 (SGI)" "Level,Edge" bitfld.long 0x00 27. " ICF[13] ,Interrupt configuration 13 (SGI)" "Level,Edge" bitfld.long 0x00 25. " ICF[12] ,Interrupt configuration 12 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 23. " ICF[11] ,Interrupt configuration 11 (SGI)" "Level,Edge" bitfld.long 0x00 21. " ICF[10] ,Interrupt configuration 10 (SGI)" "Level,Edge" bitfld.long 0x00 19. " ICF[9] ,Interrupt configuration 9 (SGI)" "Level,Edge" bitfld.long 0x00 17. " ICF[8] ,Interrupt configuration 8 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 15. " ICF[7] ,Interrupt configuration 7 (SGI)" "Level,Edge" bitfld.long 0x00 13. " ICF[6] ,Interrupt configuration 6 (SGI)" "Level,Edge" bitfld.long 0x00 11. " ICF[5] ,Interrupt configuration 5 (SGI)" "Level,Edge" bitfld.long 0x00 9. " ICF[4] ,Interrupt configuration 4 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF[3] ,Interrupt configuration 3 (SGI)" "Level,Edge" bitfld.long 0x00 5. " ICF[2] ,Interrupt configuration 2 (SGI)" "Level,Edge" bitfld.long 0x00 3. " ICF[1] ,Interrupt configuration 1 (SGI)" "Level,Edge" bitfld.long 0x00 1. " ICF[0] ,Interrupt configuration 0 (SGI)" "Level,Edge" group.long 0x10C04++0x03 line.long 0x00 "GICR_ICFGR1,Interrupt Configuration Register 1" bitfld.long 0x00 31. " ICF[15] ,Interrupt configuration 15 (PPI)" "Level,Edge" bitfld.long 0x00 29. " ICF[14] ,Interrupt configuration 14 (PPI)" "Level,Edge" bitfld.long 0x00 27. " ICF[13] ,Interrupt configuration 13 (PPI)" "Level,Edge" bitfld.long 0x00 25. " ICF[12] ,Interrupt configuration 12 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 23. " ICF[11] ,Interrupt configuration 11 (PPI)" "Level,Edge" bitfld.long 0x00 21. " ICF[10] ,Interrupt configuration 10 (PPI)" "Level,Edge" bitfld.long 0x00 19. " ICF[9] ,Interrupt configuration 9 (PPI)" "Level,Edge" bitfld.long 0x00 17. " ICF[8] ,Interrupt configuration 8 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 15. " ICF[7] ,Interrupt configuration 7 (PPI)" "Level,Edge" bitfld.long 0x00 13. " ICF[6] ,Interrupt configuration 6 (PPI)" "Level,Edge" bitfld.long 0x00 11. " ICF[5] ,Interrupt configuration 5 (PPI)" "Level,Edge" bitfld.long 0x00 9. " ICF[4] ,Interrupt configuration 4 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF[3] ,Interrupt configuration 3 (PPI)" "Level,Edge" bitfld.long 0x00 5. " ICF[2] ,Interrupt configuration 2 (PPI)" "Level,Edge" bitfld.long 0x00 3. " ICF[1] ,Interrupt configuration 1 (PPI)" "Level,Edge" bitfld.long 0x00 1. " ICF[0] ,Interrupt configuration 0 (PPI)" "Level,Edge" textline " " tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.long 0xFFE0++0x03 line.long 0x00 "GICR_PIDR0,Redistributor Identification Register 0" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFE4++0x03 line.long 0x00 "GICR_PIDR1,Redistributor Identification Register 1" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFE8++0x03 line.long 0x00 "GICR_PIDR2,Redistributor Identification Register 2" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFEC++0x03 line.long 0x00 "GICR_PIDR3,Redistributor Identification Register 3" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFF0++0x03 line.long 0x00 "GICR_PIDR4,Redistributor Identification Register 4" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFF4++0x03 line.long 0x00 "GICR_PIDR5,Redistributor Identification Register 5" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFF8++0x03 line.long 0x00 "GICR_PIDR6,Redistributor Identification Register 6" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFFC++0x03 line.long 0x00 "GICR_PIDR7,Redistributor Identification Register 7" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFD0++0x03 line.long 0x00 "GICR_PIDR4,Redistributor Identification Register 4" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFD4++0x03 line.long 0x00 "GICR_PIDR5,Redistributor Identification Register 5" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFD8++0x03 line.long 0x00 "GICR_PIDR6,Redistributor Identification Register 6" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFDC++0x03 line.long 0x00 "GICR_PIDR7,Redistributor Identification Register 7" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFF0++0x03 line.long 0x00 "GICR_CIDR0,Redistributor Component Identification Register 0" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFF4++0x03 line.long 0x00 "GICR_CIDR1,Redistributor Component Identification Register 1" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFF8++0x03 line.long 0x00 "GICR_CIDR2,Redistributor Component Identification Register 2" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFFC++0x03 line.long 0x00 "GICR_CIDR3,Redistributor Component Identification Register 3" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" tree.end tree.end width 0x0B tree.end AUTOINDENT.POP tree.end AUTOINDENT.POP endif sif (CORENAME()=="CORTEXM4F") tree.close "Core Registers (Cortex-M4F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end endif tree "AES_LIGHT (Advanced Encryption Standard Light)" base ad:0x0 tree "AES_LIGHT_0" base ad:0x75700000 group.quad 0x0++0x17 line.quad 0x0 "HOST_DATAIN0,Host Data Input 0 Register" hexmask.quad 0x0 0.--63. 1. "DATAIN0,AES Light Data Input 8-bytes" line.quad 0x8 "HOST_DATAIN1,Host Data Input 1 Register" hexmask.quad 0x8 0.--63. 1. "DATAIN1,AES Light Data Input 8-bytes" line.quad 0x10 "HOST_CTRL,Host Control Register" bitfld.quad 0x10 63. "RST,This field is used to reset the AES Light HOST interface." "0: No reset,1: soft reset" bitfld.quad 0x10 62. "INT,This field controls interrupt generation." "0: Interrupt generation is disabled,1: Interrupt generation is enabled" newline bitfld.quad 0x10 61. "DMARD,This field indicates whether a DMA read request shall be activated at the" "0: DMA is disabled for the data reading,1: DMA is enabled for the data reading" bitfld.quad 0x10 60. "DMAWR,This field indicates whether a DMA write request shall be activated when" "0: DMA is disabled for data writing,1: DMA is enabled for data writing" newline bitfld.quad 0x10 48. "SHL,This field indicates whether a signature verification (which compares the number of bits defined by the CVS field) shall be done using the most significant or the less significant part of the data. The chosen bit alignment is valid for both the.." "0: Most significant bits (the number being defined..,1: Least significant bits (the number being defined.." hexmask.quad.byte 0x10 40.--47. 1. "HLBS,This field indicates the size in bits of the last block of HEADER during GCM mode. This field is latched during CMD = Header Last Append." newline hexmask.quad.byte 0x10 32.--39. 1. "UID_CTRL,This field shall be mirrored in the UID field of HOST_STATUS register. SW can set crypto operation ID with each crypto operation. This will allow HOST SW to trace the ongoing cryptographic operation. This field is latched during CMD = INIT." hexmask.quad.byte 0x10 24.--31. 1. "DLBS,This field indicates the size in bits of the last block of DATA during CMAC and GCM mode. This field is latched during CMD = Data Last Append." newline hexmask.quad.byte 0x10 16.--23. 1. "KEY,This field indicates which key is to be used for the cryptographic operation. It is used only when CMD = Init." hexmask.quad.byte 0x10 8.--15. 1. "CVS,This field specifies the number of bits to be used when a CMAC/GCM Verify operation is done. This field is latched during CMD = INIT." newline hexmask.quad.byte 0x10 3.--7. 1. "MODE,This field specifies the type of encryption operation (AES mode)." bitfld.quad 0x10 0.--2. "CMD,This field specifies the type of command." "0: No operation,1: Initialization,2: Data Append,3: Data Last Append,4: Signature,5: Header Append,6: Header Last Append,?" rgroup.quad 0x58++0x17 line.quad 0x0 "HOST_STATUS,Host Status Register" bitfld.quad 0x0 31. "CV,This bit specify whether the CMAC/GCM verify comparison was successful:" "0: CMAC/GCM Sgnature Verify has failed,1: CMAC/GCM Signature Verify is successful" hexmask.quad.byte 0x0 16.--23. 1. "UID_STATUS,This field reports value inserted in UID field of HOST_CTRL register" newline bitfld.quad 0x0 1. "READY,This field indicates when whole cryptographic operation is completed." "0: AESLIGHT is executing a cryptographic operation..,1: AESLIGHT is not executing a cryptographic.." bitfld.quad 0x0 0. "BSY,This bit specify whether the HOST interface is busy:" "0: No process is running,1: The AES Light is serving a cryptographic operation" line.quad 0x8 "HOST_DATAOUT0,Host Data Output 0 Register" hexmask.quad 0x8 0.--63. 1. "DATAOUT0,AESLight processed output data 8 bytes" line.quad 0x10 "HOST_DATAOUT1,Host Data Output 1 Register" hexmask.quad 0x10 0.--63. 1. "DATAOUT1,AESLight processed output data 8 bytes" group.quad 0x80++0xF line.quad 0x0 "HOST_INT_STATUS,Host Interrupt Status Register" bitfld.quad 0x0 2. "INVKEY,This bit indicates an error occurring when the AES-Light is requested to run a cryptographic operation using a certain key and failed to serve the cryptographic operation" "0: No error,1: Invalid Key error" bitfld.quad 0x0 1. "OVF,This bit indicates an error occurring when the AES-Light is servicing one request i.e. BSY = 1 and the Host application requests a new one" "0: No error,1: Overflow error" newline bitfld.quad 0x0 0. "DONE,This bit indicates when a micro-operation is completed. The field is set when BSY bit is de-asserted to ‘0’." "0: Operation is running,1: Operation is completed" line.quad 0x8 "HOST_INTMASK,Host Interrupt Mask Register" bitfld.quad 0x8 2. "INVKEY,This bit is used to mask the INV_KEY interrupt:" "0: Interrupt is not masked,1: Interrupt is masked" bitfld.quad 0x8 1. "OVF,This bit is used to mask the OVF interrupt:" "0: Interrupt is not masked,1: Interrupt is masked" newline bitfld.quad 0x8 0. "DONE,This bit is used to mask the DONE interrupt:" "0: Interrupt is not masked,1: Interrupt is masked" tree.end tree "AES_LIGHT_1" base ad:0x75704000 group.quad 0x0++0x17 line.quad 0x0 "HOST_DATAIN0,Host Data Input 0 Register" hexmask.quad 0x0 0.--63. 1. "DATAIN0,AES Light Data Input 8-bytes" line.quad 0x8 "HOST_DATAIN1,Host Data Input 1 Register" hexmask.quad 0x8 0.--63. 1. "DATAIN1,AES Light Data Input 8-bytes" line.quad 0x10 "HOST_CTRL,Host Control Register" bitfld.quad 0x10 63. "RST,This field is used to reset the AES Light HOST interface." "0: No reset,1: soft reset" bitfld.quad 0x10 62. "INT,This field controls interrupt generation." "0: Interrupt generation is disabled,1: Interrupt generation is enabled" newline bitfld.quad 0x10 61. "DMARD,This field indicates whether a DMA read request shall be activated at the" "0: DMA is disabled for the data reading,1: DMA is enabled for the data reading" bitfld.quad 0x10 60. "DMAWR,This field indicates whether a DMA write request shall be activated when" "0: DMA is disabled for data writing,1: DMA is enabled for data writing" newline bitfld.quad 0x10 48. "SHL,This field indicates whether a signature verification (which compares the number of bits defined by the CVS field) shall be done using the most significant or the less significant part of the data. The chosen bit alignment is valid for both the.." "0: Most significant bits (the number being defined..,1: Least significant bits (the number being defined.." hexmask.quad.byte 0x10 40.--47. 1. "HLBS,This field indicates the size in bits of the last block of HEADER during GCM mode. This field is latched during CMD = Header Last Append." newline hexmask.quad.byte 0x10 32.--39. 1. "UID_CTRL,This field shall be mirrored in the UID field of HOST_STATUS register. SW can set crypto operation ID with each crypto operation. This will allow HOST SW to trace the ongoing cryptographic operation. This field is latched during CMD = INIT." hexmask.quad.byte 0x10 24.--31. 1. "DLBS,This field indicates the size in bits of the last block of DATA during CMAC and GCM mode. This field is latched during CMD = Data Last Append." newline hexmask.quad.byte 0x10 16.--23. 1. "KEY,This field indicates which key is to be used for the cryptographic operation. It is used only when CMD = Init." hexmask.quad.byte 0x10 8.--15. 1. "CVS,This field specifies the number of bits to be used when a CMAC/GCM Verify operation is done. This field is latched during CMD = INIT." newline hexmask.quad.byte 0x10 3.--7. 1. "MODE,This field specifies the type of encryption operation (AES mode)." bitfld.quad 0x10 0.--2. "CMD,This field specifies the type of command." "0: No operation,1: Initialization,2: Data Append,3: Data Last Append,4: Signature,5: Header Append,6: Header Last Append,?" rgroup.quad 0x58++0x17 line.quad 0x0 "HOST_STATUS,Host Status Register" bitfld.quad 0x0 31. "CV,This bit specify whether the CMAC/GCM verify comparison was successful:" "0: CMAC/GCM Sgnature Verify has failed,1: CMAC/GCM Signature Verify is successful" hexmask.quad.byte 0x0 16.--23. 1. "UID_STATUS,This field reports value inserted in UID field of HOST_CTRL register" newline bitfld.quad 0x0 1. "READY,This field indicates when whole cryptographic operation is completed." "0: AESLIGHT is executing a cryptographic operation..,1: AESLIGHT is not executing a cryptographic.." bitfld.quad 0x0 0. "BSY,This bit specify whether the HOST interface is busy:" "0: No process is running,1: The AES Light is serving a cryptographic operation" line.quad 0x8 "HOST_DATAOUT0,Host Data Output 0 Register" hexmask.quad 0x8 0.--63. 1. "DATAOUT0,AESLight processed output data 8 bytes" line.quad 0x10 "HOST_DATAOUT1,Host Data Output 1 Register" hexmask.quad 0x10 0.--63. 1. "DATAOUT1,AESLight processed output data 8 bytes" group.quad 0x80++0xF line.quad 0x0 "HOST_INT_STATUS,Host Interrupt Status Register" bitfld.quad 0x0 2. "INVKEY,This bit indicates an error occurring when the AES-Light is requested to run a cryptographic operation using a certain key and failed to serve the cryptographic operation" "0: No error,1: Invalid Key error" bitfld.quad 0x0 1. "OVF,This bit indicates an error occurring when the AES-Light is servicing one request i.e. BSY = 1 and the Host application requests a new one" "0: No error,1: Overflow error" newline bitfld.quad 0x0 0. "DONE,This bit indicates when a micro-operation is completed. The field is set when BSY bit is de-asserted to ‘0’." "0: Operation is running,1: Operation is completed" line.quad 0x8 "HOST_INTMASK,Host Interrupt Mask Register" bitfld.quad 0x8 2. "INVKEY,This bit is used to mask the INV_KEY interrupt:" "0: Interrupt is not masked,1: Interrupt is masked" bitfld.quad 0x8 1. "OVF,This bit is used to mask the OVF interrupt:" "0: Interrupt is not masked,1: Interrupt is masked" newline bitfld.quad 0x8 0. "DONE,This bit is used to mask the DONE interrupt:" "0: Interrupt is not masked,1: Interrupt is masked" tree.end tree "AES_LIGHT_2" base ad:0x75708000 group.quad 0x0++0x17 line.quad 0x0 "HOST_DATAIN0,Host Data Input 0 Register" hexmask.quad 0x0 0.--63. 1. "DATAIN0,AES Light Data Input 8-bytes" line.quad 0x8 "HOST_DATAIN1,Host Data Input 1 Register" hexmask.quad 0x8 0.--63. 1. "DATAIN1,AES Light Data Input 8-bytes" line.quad 0x10 "HOST_CTRL,Host Control Register" bitfld.quad 0x10 63. "RST,This field is used to reset the AES Light HOST interface." "0: No reset,1: soft reset" bitfld.quad 0x10 62. "INT,This field controls interrupt generation." "0: Interrupt generation is disabled,1: Interrupt generation is enabled" newline bitfld.quad 0x10 61. "DMARD,This field indicates whether a DMA read request shall be activated at the" "0: DMA is disabled for the data reading,1: DMA is enabled for the data reading" bitfld.quad 0x10 60. "DMAWR,This field indicates whether a DMA write request shall be activated when" "0: DMA is disabled for data writing,1: DMA is enabled for data writing" newline bitfld.quad 0x10 48. "SHL,This field indicates whether a signature verification (which compares the number of bits defined by the CVS field) shall be done using the most significant or the less significant part of the data. The chosen bit alignment is valid for both the.." "0: Most significant bits (the number being defined..,1: Least significant bits (the number being defined.." hexmask.quad.byte 0x10 40.--47. 1. "HLBS,This field indicates the size in bits of the last block of HEADER during GCM mode. This field is latched during CMD = Header Last Append." newline hexmask.quad.byte 0x10 32.--39. 1. "UID_CTRL,This field shall be mirrored in the UID field of HOST_STATUS register. SW can set crypto operation ID with each crypto operation. This will allow HOST SW to trace the ongoing cryptographic operation. This field is latched during CMD = INIT." hexmask.quad.byte 0x10 24.--31. 1. "DLBS,This field indicates the size in bits of the last block of DATA during CMAC and GCM mode. This field is latched during CMD = Data Last Append." newline hexmask.quad.byte 0x10 16.--23. 1. "KEY,This field indicates which key is to be used for the cryptographic operation. It is used only when CMD = Init." hexmask.quad.byte 0x10 8.--15. 1. "CVS,This field specifies the number of bits to be used when a CMAC/GCM Verify operation is done. This field is latched during CMD = INIT." newline hexmask.quad.byte 0x10 3.--7. 1. "MODE,This field specifies the type of encryption operation (AES mode)." bitfld.quad 0x10 0.--2. "CMD,This field specifies the type of command." "0: No operation,1: Initialization,2: Data Append,3: Data Last Append,4: Signature,5: Header Append,6: Header Last Append,?" rgroup.quad 0x58++0x17 line.quad 0x0 "HOST_STATUS,Host Status Register" bitfld.quad 0x0 31. "CV,This bit specify whether the CMAC/GCM verify comparison was successful:" "0: CMAC/GCM Sgnature Verify has failed,1: CMAC/GCM Signature Verify is successful" hexmask.quad.byte 0x0 16.--23. 1. "UID_STATUS,This field reports value inserted in UID field of HOST_CTRL register" newline bitfld.quad 0x0 1. "READY,This field indicates when whole cryptographic operation is completed." "0: AESLIGHT is executing a cryptographic operation..,1: AESLIGHT is not executing a cryptographic.." bitfld.quad 0x0 0. "BSY,This bit specify whether the HOST interface is busy:" "0: No process is running,1: The AES Light is serving a cryptographic operation" line.quad 0x8 "HOST_DATAOUT0,Host Data Output 0 Register" hexmask.quad 0x8 0.--63. 1. "DATAOUT0,AESLight processed output data 8 bytes" line.quad 0x10 "HOST_DATAOUT1,Host Data Output 1 Register" hexmask.quad 0x10 0.--63. 1. "DATAOUT1,AESLight processed output data 8 bytes" group.quad 0x80++0xF line.quad 0x0 "HOST_INT_STATUS,Host Interrupt Status Register" bitfld.quad 0x0 2. "INVKEY,This bit indicates an error occurring when the AES-Light is requested to run a cryptographic operation using a certain key and failed to serve the cryptographic operation" "0: No error,1: Invalid Key error" bitfld.quad 0x0 1. "OVF,This bit indicates an error occurring when the AES-Light is servicing one request i.e. BSY = 1 and the Host application requests a new one" "0: No error,1: Overflow error" newline bitfld.quad 0x0 0. "DONE,This bit indicates when a micro-operation is completed. The field is set when BSY bit is de-asserted to ‘0’." "0: Operation is running,1: Operation is completed" line.quad 0x8 "HOST_INTMASK,Host Interrupt Mask Register" bitfld.quad 0x8 2. "INVKEY,This bit is used to mask the INV_KEY interrupt:" "0: Interrupt is not masked,1: Interrupt is masked" bitfld.quad 0x8 1. "OVF,This bit is used to mask the OVF interrupt:" "0: Interrupt is not masked,1: Interrupt is masked" newline bitfld.quad 0x8 0. "DONE,This bit is used to mask the DONE interrupt:" "0: Interrupt is not masked,1: Interrupt is masked" tree.end tree "AES_LIGHT_3" base ad:0x7570C000 group.quad 0x0++0x17 line.quad 0x0 "HOST_DATAIN0,Host Data Input 0 Register" hexmask.quad 0x0 0.--63. 1. "DATAIN0,AES Light Data Input 8-bytes" line.quad 0x8 "HOST_DATAIN1,Host Data Input 1 Register" hexmask.quad 0x8 0.--63. 1. "DATAIN1,AES Light Data Input 8-bytes" line.quad 0x10 "HOST_CTRL,Host Control Register" bitfld.quad 0x10 63. "RST,This field is used to reset the AES Light HOST interface." "0: No reset,1: soft reset" bitfld.quad 0x10 62. "INT,This field controls interrupt generation." "0: Interrupt generation is disabled,1: Interrupt generation is enabled" newline bitfld.quad 0x10 61. "DMARD,This field indicates whether a DMA read request shall be activated at the" "0: DMA is disabled for the data reading,1: DMA is enabled for the data reading" bitfld.quad 0x10 60. "DMAWR,This field indicates whether a DMA write request shall be activated when" "0: DMA is disabled for data writing,1: DMA is enabled for data writing" newline bitfld.quad 0x10 48. "SHL,This field indicates whether a signature verification (which compares the number of bits defined by the CVS field) shall be done using the most significant or the less significant part of the data. The chosen bit alignment is valid for both the.." "0: Most significant bits (the number being defined..,1: Least significant bits (the number being defined.." hexmask.quad.byte 0x10 40.--47. 1. "HLBS,This field indicates the size in bits of the last block of HEADER during GCM mode. This field is latched during CMD = Header Last Append." newline hexmask.quad.byte 0x10 32.--39. 1. "UID_CTRL,This field shall be mirrored in the UID field of HOST_STATUS register. SW can set crypto operation ID with each crypto operation. This will allow HOST SW to trace the ongoing cryptographic operation. This field is latched during CMD = INIT." hexmask.quad.byte 0x10 24.--31. 1. "DLBS,This field indicates the size in bits of the last block of DATA during CMAC and GCM mode. This field is latched during CMD = Data Last Append." newline hexmask.quad.byte 0x10 16.--23. 1. "KEY,This field indicates which key is to be used for the cryptographic operation. It is used only when CMD = Init." hexmask.quad.byte 0x10 8.--15. 1. "CVS,This field specifies the number of bits to be used when a CMAC/GCM Verify operation is done. This field is latched during CMD = INIT." newline hexmask.quad.byte 0x10 3.--7. 1. "MODE,This field specifies the type of encryption operation (AES mode)." bitfld.quad 0x10 0.--2. "CMD,This field specifies the type of command." "0: No operation,1: Initialization,2: Data Append,3: Data Last Append,4: Signature,5: Header Append,6: Header Last Append,?" rgroup.quad 0x58++0x17 line.quad 0x0 "HOST_STATUS,Host Status Register" bitfld.quad 0x0 31. "CV,This bit specify whether the CMAC/GCM verify comparison was successful:" "0: CMAC/GCM Sgnature Verify has failed,1: CMAC/GCM Signature Verify is successful" hexmask.quad.byte 0x0 16.--23. 1. "UID_STATUS,This field reports value inserted in UID field of HOST_CTRL register" newline bitfld.quad 0x0 1. "READY,This field indicates when whole cryptographic operation is completed." "0: AESLIGHT is executing a cryptographic operation..,1: AESLIGHT is not executing a cryptographic.." bitfld.quad 0x0 0. "BSY,This bit specify whether the HOST interface is busy:" "0: No process is running,1: The AES Light is serving a cryptographic operation" line.quad 0x8 "HOST_DATAOUT0,Host Data Output 0 Register" hexmask.quad 0x8 0.--63. 1. "DATAOUT0,AESLight processed output data 8 bytes" line.quad 0x10 "HOST_DATAOUT1,Host Data Output 1 Register" hexmask.quad 0x10 0.--63. 1. "DATAOUT1,AESLight processed output data 8 bytes" group.quad 0x80++0xF line.quad 0x0 "HOST_INT_STATUS,Host Interrupt Status Register" bitfld.quad 0x0 2. "INVKEY,This bit indicates an error occurring when the AES-Light is requested to run a cryptographic operation using a certain key and failed to serve the cryptographic operation" "0: No error,1: Invalid Key error" bitfld.quad 0x0 1. "OVF,This bit indicates an error occurring when the AES-Light is servicing one request i.e. BSY = 1 and the Host application requests a new one" "0: No error,1: Overflow error" newline bitfld.quad 0x0 0. "DONE,This bit indicates when a micro-operation is completed. The field is set when BSY bit is de-asserted to ‘0’." "0: Operation is running,1: Operation is completed" line.quad 0x8 "HOST_INTMASK,Host Interrupt Mask Register" bitfld.quad 0x8 2. "INVKEY,This bit is used to mask the INV_KEY interrupt:" "0: Interrupt is not masked,1: Interrupt is masked" bitfld.quad 0x8 1. "OVF,This bit is used to mask the OVF interrupt:" "0: Interrupt is not masked,1: Interrupt is masked" newline bitfld.quad 0x8 0. "DONE,This bit is used to mask the DONE interrupt:" "0: Interrupt is not masked,1: Interrupt is masked" tree.end tree.end tree "AXBS (Crossbar Switch)" base ad:0x0 tree "AXBS_0" base ad:0x723DC000 rgroup.long 0x0++0x3 line.long 0x0 "PRS0,Priority Registers Slave" bitfld.long 0x0 12.--14. "M3,Master 3 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." bitfld.long 0x0 8.--10. "M2,Master 2 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." newline bitfld.long 0x0 4.--6. "M1,Master 1 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." group.long 0x10++0x3 line.long 0x0 "CRS0,Control Register" bitfld.long 0x0 31. "RO,Read only" "0: The slave port's registers are writable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HRP,Halt Request Priority" "0: The halt request has the highest priority for..,1: The halt request has the lowest initial priority.." newline bitfld.long 0x0 19. "HPE3,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." bitfld.long 0x0 18. "HPE2,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." newline bitfld.long 0x0 17. "HPE1,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." bitfld.long 0x0 16. "HPE0,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration mode" "0: Fixed priority,1: Round-robin (rotating) priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7" rgroup.long 0x100++0x3 line.long 0x0 "PRS1,Priority Registers Slave" bitfld.long 0x0 12.--14. "M3,Master 3 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." bitfld.long 0x0 8.--10. "M2,Master 2 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." newline bitfld.long 0x0 4.--6. "M1,Master 1 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." group.long 0x110++0x3 line.long 0x0 "CRS1,Control Register" bitfld.long 0x0 31. "RO,Read only" "0: The slave port's registers are writable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HRP,Halt Request Priority" "0: The halt request has the highest priority for..,1: The halt request has the lowest initial priority.." newline bitfld.long 0x0 19. "HPE3,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." bitfld.long 0x0 18. "HPE2,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." newline bitfld.long 0x0 17. "HPE1,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." bitfld.long 0x0 16. "HPE0,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration mode" "0: Fixed priority,1: Round-robin (rotating) priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7" rgroup.long 0x200++0x3 line.long 0x0 "PRS2,Priority Registers Slave" bitfld.long 0x0 12.--14. "M3,Master 3 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." bitfld.long 0x0 8.--10. "M2,Master 2 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." newline bitfld.long 0x0 4.--6. "M1,Master 1 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." group.long 0x210++0x3 line.long 0x0 "CRS2,Control Register" bitfld.long 0x0 31. "RO,Read only" "0: The slave port's registers are writable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HRP,Halt Request Priority" "0: The halt request has the highest priority for..,1: The halt request has the lowest initial priority.." newline bitfld.long 0x0 19. "HPE3,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." bitfld.long 0x0 18. "HPE2,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." newline bitfld.long 0x0 17. "HPE1,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." bitfld.long 0x0 16. "HPE0,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration mode" "0: Fixed priority,1: Round-robin (rotating) priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7" rgroup.long 0x300++0x3 line.long 0x0 "PRS3,Priority Registers Slave" bitfld.long 0x0 12.--14. "M3,Master 3 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." bitfld.long 0x0 8.--10. "M2,Master 2 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." newline bitfld.long 0x0 4.--6. "M1,Master 1 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." group.long 0x310++0x3 line.long 0x0 "CRS3,Control Register" bitfld.long 0x0 31. "RO,Read only" "0: The slave port's registers are writable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HRP,Halt Request Priority" "0: The halt request has the highest priority for..,1: The halt request has the lowest initial priority.." newline bitfld.long 0x0 19. "HPE3,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." bitfld.long 0x0 18. "HPE2,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." newline bitfld.long 0x0 17. "HPE1,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." bitfld.long 0x0 16. "HPE0,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration mode" "0: Fixed priority,1: Round-robin (rotating) priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7" group.long 0x800++0x3 line.long 0x0 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x0 0.--2. "AULB,Arbitrate on Undefined Length Bursts" "0: No arbitration will be allowed during undefined..,1: Arbitration will be allowed at any time during..,2: Arbitration will be allowed after 4 beats of an..,3: Arbitration will be allowed after 8 beats of an..,4: Arbitration will be allowed after 16 beats of an..,?,?,?" group.long 0x900++0x3 line.long 0x0 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x0 0.--2. "AULB,Arbitrate on Undefined Length Bursts" "0: No arbitration will be allowed during undefined..,1: Arbitration will be allowed at any time during..,2: Arbitration will be allowed after 4 beats of an..,3: Arbitration will be allowed after 8 beats of an..,4: Arbitration will be allowed after 16 beats of an..,?,?,?" group.long 0xA00++0x3 line.long 0x0 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x0 0.--2. "AULB,Arbitrate on Undefined Length Bursts" "0: No arbitration will be allowed during undefined..,1: Arbitration will be allowed at any time during..,2: Arbitration will be allowed after 4 beats of an..,3: Arbitration will be allowed after 8 beats of an..,4: Arbitration will be allowed after 16 beats of an..,?,?,?" group.long 0xB00++0x3 line.long 0x0 "MGPCR3,Master General Purpose Control Register" bitfld.long 0x0 0.--2. "AULB,Arbitrate on Undefined Length Bursts" "0: No arbitration will be allowed during undefined..,1: Arbitration will be allowed at any time during..,2: Arbitration will be allowed after 4 beats of an..,3: Arbitration will be allowed after 8 beats of an..,4: Arbitration will be allowed after 16 beats of an..,?,?,?" tree.end tree "AXBS_1" base ad:0x717DC000 rgroup.long 0x0++0x3 line.long 0x0 "PRS0,Priority Registers Slave" bitfld.long 0x0 12.--14. "M3,Master 3 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." bitfld.long 0x0 8.--10. "M2,Master 2 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." newline bitfld.long 0x0 4.--6. "M1,Master 1 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." group.long 0x10++0x3 line.long 0x0 "CRS0,Control Register" bitfld.long 0x0 31. "RO,Read only" "0: The slave port's registers are writable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HRP,Halt Request Priority" "0: The halt request has the highest priority for..,1: The halt request has the lowest initial priority.." newline bitfld.long 0x0 19. "HPE3,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." bitfld.long 0x0 18. "HPE2,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." newline bitfld.long 0x0 17. "HPE1,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." bitfld.long 0x0 16. "HPE0,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration mode" "0: Fixed priority,1: Round-robin (rotating) priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7" rgroup.long 0x100++0x3 line.long 0x0 "PRS1,Priority Registers Slave" bitfld.long 0x0 12.--14. "M3,Master 3 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." bitfld.long 0x0 8.--10. "M2,Master 2 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." newline bitfld.long 0x0 4.--6. "M1,Master 1 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." group.long 0x110++0x3 line.long 0x0 "CRS1,Control Register" bitfld.long 0x0 31. "RO,Read only" "0: The slave port's registers are writable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HRP,Halt Request Priority" "0: The halt request has the highest priority for..,1: The halt request has the lowest initial priority.." newline bitfld.long 0x0 19. "HPE3,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." bitfld.long 0x0 18. "HPE2,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." newline bitfld.long 0x0 17. "HPE1,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." bitfld.long 0x0 16. "HPE0,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration mode" "0: Fixed priority,1: Round-robin (rotating) priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7" rgroup.long 0x200++0x3 line.long 0x0 "PRS2,Priority Registers Slave" bitfld.long 0x0 12.--14. "M3,Master 3 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." bitfld.long 0x0 8.--10. "M2,Master 2 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." newline bitfld.long 0x0 4.--6. "M1,Master 1 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." group.long 0x210++0x3 line.long 0x0 "CRS2,Control Register" bitfld.long 0x0 31. "RO,Read only" "0: The slave port's registers are writable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HRP,Halt Request Priority" "0: The halt request has the highest priority for..,1: The halt request has the lowest initial priority.." newline bitfld.long 0x0 19. "HPE3,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." bitfld.long 0x0 18. "HPE2,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." newline bitfld.long 0x0 17. "HPE1,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." bitfld.long 0x0 16. "HPE0,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration mode" "0: Fixed priority,1: Round-robin (rotating) priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7" rgroup.long 0x300++0x3 line.long 0x0 "PRS3,Priority Registers Slave" bitfld.long 0x0 12.--14. "M3,Master 3 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." bitfld.long 0x0 8.--10. "M2,Master 2 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." newline bitfld.long 0x0 4.--6. "M1,Master 1 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 priority" "0: This master has level 1 (highest) priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 (lowest) priority when.." group.long 0x310++0x3 line.long 0x0 "CRS3,Control Register" bitfld.long 0x0 31. "RO,Read only" "0: The slave port's registers are writable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HRP,Halt Request Priority" "0: The halt request has the highest priority for..,1: The halt request has the lowest initial priority.." newline bitfld.long 0x0 19. "HPE3,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." bitfld.long 0x0 18. "HPE2,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." newline bitfld.long 0x0 17. "HPE1,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." bitfld.long 0x0 16. "HPE0,High Priority Enable (HPEx)" "0: High Priority requests from Master x are ignored..,1: High Priority requests from Master x can.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration mode" "0: Fixed priority,1: Round-robin (rotating) priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7" group.long 0x800++0x3 line.long 0x0 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x0 0.--2. "AULB,Arbitrate on Undefined Length Bursts" "0: No arbitration will be allowed during undefined..,1: Arbitration will be allowed at any time during..,2: Arbitration will be allowed after 4 beats of an..,3: Arbitration will be allowed after 8 beats of an..,4: Arbitration will be allowed after 16 beats of an..,?,?,?" group.long 0x900++0x3 line.long 0x0 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x0 0.--2. "AULB,Arbitrate on Undefined Length Bursts" "0: No arbitration will be allowed during undefined..,1: Arbitration will be allowed at any time during..,2: Arbitration will be allowed after 4 beats of an..,3: Arbitration will be allowed after 8 beats of an..,4: Arbitration will be allowed after 16 beats of an..,?,?,?" group.long 0xA00++0x3 line.long 0x0 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x0 0.--2. "AULB,Arbitrate on Undefined Length Bursts" "0: No arbitration will be allowed during undefined..,1: Arbitration will be allowed at any time during..,2: Arbitration will be allowed after 4 beats of an..,3: Arbitration will be allowed after 8 beats of an..,4: Arbitration will be allowed after 16 beats of an..,?,?,?" group.long 0xB00++0x3 line.long 0x0 "MGPCR3,Master General Purpose Control Register" bitfld.long 0x0 0.--2. "AULB,Arbitrate on Undefined Length Bursts" "0: No arbitration will be allowed during undefined..,1: Arbitration will be allowed at any time during..,2: Arbitration will be allowed after 4 beats of an..,3: Arbitration will be allowed after 8 beats of an..,4: Arbitration will be allowed after 16 beats of an..,?,?,?" tree.end tree.end tree "CAN (Controller Area Network)" base ad:0x0 tree "CAN_SUB_0" tree "CAN_SUB_0_DMU_0" base ad:0x72000000 rgroup.long 0x3C0++0x3 line.long 0x0 "DMUCR,DMU Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" group.long 0x3C4++0x13 line.long 0x0 "DMUI,DMU Internals register" bitfld.long 0x0 31. "TXE,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 30. "RX1,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 29. "RX0,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 28. "TX,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 24.--26. "EHS,Element Handler State" "0: wait for bit M_CAN:CCCR.CCE getting zero,1: wait for Start Address,2: wait for Trigger Address,3: wait for transfer of Element word,4: acknowledge to M_CAN,5: exception recovery,?,?" bitfld.long 0x0 23. "DTXE,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 22. "DTX1,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 21. "DTX0,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 20. "DTX,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 16.--18. "DEHS,Detect Element Handler State" "?,?,?,?,?,?,?,7: unused state" newline bitfld.long 0x0 15. "ENA,DMU is enabled" "0: DMU is disabled,1: DMU is enabled and can process DMA data" hexmask.long.byte 0x0 8.--12. 1. "TFQPIP,TX FIFO/Queue Put Index Previous" newline bitfld.long 0x0 3. "TXER,TX Event Service Request line of DMU" "0: No TX Event DMA service requested,1: TX Event DMA Service requested" bitfld.long 0x0 2. "RX1R,RX1 Service Request line of DMU" "0: No RX1 DMA service requested,1: RX1 DMA Service requested" newline bitfld.long 0x0 1. "RX0R,RX0 Service Request line of DMU" "0: No RX0 DMA service requested,1: RX0 DMA Service requested" bitfld.long 0x0 0. "TXR,TX Service Request line of DMU" "0: No TX DMA service requested,1: TX DMA Service requested" line.long 0x4 "DMUQC,DMU Queuing Counter register" hexmask.long.byte 0x4 24.--31. 1. "TXEEDC,TX Event Element Dequeuing Counter" hexmask.long.byte 0x4 16.--23. 1. "RX1EDC,RX1 Element Dequeuing Counter" newline hexmask.long.byte 0x4 8.--15. 1. "RX0EDC,RX0 Element Dequeuing Counter" hexmask.long.byte 0x4 0.--7. 1. "TXEEC,TX Element Enqueuing Counter" line.long 0x8 "DMUIR,DMU Interrupt Register" bitfld.long 0x8 30. "IAC,Illegal Access while in Configuration mode" "0: No Illegal Access while CCE mode,1: Illegal Access while CCE mode" bitfld.long 0x8 29. "DT,Debug Trigger" "0: Debug point not reached,1: Debug point reached" newline bitfld.long 0x8 28. "TXEED,TX Event Element Dequeued" "0: No TX Event Element dequeued,1: TX Event Element successfully dequeued" bitfld.long 0x8 27. "TXEEIW,TX Event Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU TX Event Element.." newline bitfld.long 0x8 26. "TXEEIAS,TX Event Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 25. "TXEEID,TX Event Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 24. "TXEENSA,TX Event Element Not Start Address" "0: No illegal read access,1: Read from TX Event Element begins without using.." bitfld.long 0x8 21. "RX1EIO,RX1 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 20. "RX1ED,RX1 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 19. "RX1EIW,RX1 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 18. "RX1EIAS,RX1 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 17. "RX1EID,RX1 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 16. "RX1ENSA,RX1 Element Not Start Address" "0: No illegal read access,1: Read from RX1 Element begins without using start.." bitfld.long 0x8 15. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Uncorrected bit error detected" newline bitfld.long 0x8 14. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected" bitfld.long 0x8 13. "RX0EIO,RX0 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 12. "RX0ED,RX0 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 11. "RX0EIW,RX0 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 10. "RX0EIAS,RX0 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 9. "RX0EID,RX0 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 8. "RX0ENSA,RX0 Element Not Start Address" "0: No illegal read access,1: Read from RX0 Element begins without using start.." bitfld.long 0x8 6. "TXEE,TX Element Enqueued" "0: No Tx message enqueued,1: Tx message successfully enqueued" newline bitfld.long 0x8 5. "TXEIR,TX Element Illegal Read" "0: No read access,1: Illegal read access to DMU TX Element section.." bitfld.long 0x8 4. "TXEWATA,TX Element Write After Trigger Address" "0: No write after Trigger Address,1: Enqueue a message" newline bitfld.long 0x8 3. "TXEIDLC,TX Element Illegal DLC" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." bitfld.long 0x8 2. "TXEIAS,TX Element Illegal Access Sequence" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." newline bitfld.long 0x8 1. "TXEIE,TX Element Illegal Enqueuing" "0: No illegal enqueuing,1: Start of enqueuing without request detected.." bitfld.long 0x8 0. "TXENSA,TX Element Not Start Address" "0: No illegal write access,1: Write to TX Element begins without using start.." line.long 0xC "DMUIE,DMU Interrupt Enable register" bitfld.long 0xC 30. "IACE,Illegal Access while in Configuration mode Enable" "0: Flag DMUIR.IAC does not activate the interrupt..,1: If DMUIR.IAC = 1 the interrupt line dmu_int will.." bitfld.long 0xC 29. "DTE,Debug Trigger Enable" "0: Flag DMUIR.DT does not activate the interrupt..,1: If DMUIR.DT = 1 the interrupt line dmu_int will.." newline bitfld.long 0xC 28. "TXEEDE,TX Event Element Dequeued" "0: Flag DMUIR.TXEED does not activate the interrupt..,1: If DMUIR.TXEED = 1 the interrupt line dmu_int.." bitfld.long 0xC 27. "TXEEIWE,TX Event Element Illegal Write" "0: Flag DMUIR.TXEEIW does not activate the..,1: If DMUIR.TXEEIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 26. "TXEEIASE,TX Event Element Illegal Access Sequence" "0: Flag DMUIR.TXEEIAS does not activate the..,1: If DMUIR.TXEEIAS = 1 the interrupt line dmu_int.." bitfld.long 0xC 25. "TXEEIDE,TX Event Element Illegal Dequeuing" "0: Flag DMUIR.TXEEID does not activate the..,1: If DMUIR.TXEEID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 24. "TXEENSAE,TX Event Element Not Start Address" "0: Flag TXEENSA.TXEENSA does not activate the..,1: If TXEENSA.TXEENSA = 1 the interrupt line.." bitfld.long 0xC 21. "RX1EIOE,RX1 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX1EIO does not activate the..,1: If TXEENSA.RX1EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 20. "RX1EDE,RX1 Element Dequeued Enable" "0: Flag TXEENSA.RX1ED does not activate the..,1: If TXEENSA.RX1ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 19. "RX1EIWE,RX1 Element Illegal Write Enable" "0: Flag TXEENSA.RX1EIW does not activate the..,1: If TXEENSA.RX1EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 18. "RX1EIASE,RX1 Element Illegal Access Sequence Enable" "0: Flag TXEENSA.RX1EIAS does not activate the..,1: If TXEENSA.RX1EIAS = 1 the interrupt line.." bitfld.long 0xC 17. "RX1EIDE,RX1 Element Illegal Dequeuing Enable" "0: Flag TXEENSA.RX1EID does not activate the..,1: If TXEENSA.RX1EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 16. "RX1ENSAE,RX1 Element Not Start Address Enable" "0: Flag TXEENSA.RX1ENSA does not activate the..,1: If TXEENSA.RX1ENSA = 1 the interrupt line.." bitfld.long 0xC 15. "BEUE,Bit Error Uncorrected Enable" "0: Flag TXEENSA.BEU does not activate the interrupt..,1: If TXEENSA.BEU = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 14. "BECE,Bit Error Corrected Enable" "0: Flag TXEENSA.BEC does not activate the interrupt..,1: If TXEENSA.BEC = 1 the interrupt line dmu_int.." bitfld.long 0xC 13. "RX0EIOE,RX0 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX0EIO does not activate the..,1: If TXEENSA.RX0EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 12. "RX0EDE,RX0 Element Dequeued Enabled" "0: Flag TXEENSA.RX0ED does not activate the..,1: If TXEENSA.RX0ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 11. "RX0EIWE,RX0 Element Illegal Write Enabled" "0: Flag TXEENSA.RX0EIW does not activate the..,1: If TXEENSA.RX0EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 10. "RX0EIASE,RX0 Element Illegal Access Sequence Enabled" "0: Flag TXEENSA.RX0EIAS does not activate the..,1: If TXEENSA.RX0EIAS = 1 the interrupt line.." bitfld.long 0xC 9. "RX0EIDE,RX0 Element Illegal Dequeuing Enabled" "0: Flag TXEENSA.RX0EID does not activate the..,1: If TXEENSA.RX0EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 8. "RX0ENSAE,RX0 Element Not Start Address Enabled" "0: Flag TXEENSA.RX0ENSA does not activate the..,1: If TXEENSA.RX0ENSA = 1 the interrupt line.." bitfld.long 0xC 6. "TXEEE,TX Element Enqueued Enable" "0: Flag TXEENSA.TXEE does not activate the..,1: If TXEENSA.TXEE = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 5. "TXEIRE,TX Element Illegal Read Enable" "0: Flag TXEENSA.TXEIR does not activate the..,1: If TXEENSA.TXEIR = 1 the interrupt line dmu_int.." bitfld.long 0xC 4. "TXEWATAE,TX Element Write After Trigger Address Enable" "0: Flag TXEENSA.TXEWATA does not activate the..,1: If TXEENSA.TXEWATA = 1 the interrupt line.." newline bitfld.long 0xC 3. "TXEIDLCE,TX Element Illegal DLC Enable" "0: Flag TXEENSA.TXEIDLC does not activate the..,1: If TXEENSA.TXEIDLC = 1 the interrupt line.." bitfld.long 0xC 2. "TXEIASE,TX Element Illegal Access Sequence Enable" "0: Flag TXEENSA.TXEIAS does not activate the..,1: If TXEENSA.TXEIAS = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 1. "TXEIEE,TX Element Illegal Enqueuing Enable" "0: Flag TXEENSA.TXEIE does not activate the..,1: If TXEENSA.TXEIE = 1 the interrupt line dmu_int.." bitfld.long 0xC 0. "TXENSAE,TX Element Not Start Address Enable" "0: Flag DMUIR.TXENSA does not activate the..,1: If DMUIR.TXENSA = 1 the interrupt line dmu_int.." line.long 0x10 "DMUC,DMU Configuration register" bitfld.long 0x10 0. "TTS,Transfer Timestamp" "0: No timestamp will be transferred via DMU Virtual..,1: Timestamp of message will be transferred from.." tree.end tree "CAN_SUB_0_DMU_1" base ad:0x72004000 rgroup.long 0x3C0++0x3 line.long 0x0 "DMUCR,DMU Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" group.long 0x3C4++0x13 line.long 0x0 "DMUI,DMU Internals register" bitfld.long 0x0 31. "TXE,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 30. "RX1,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 29. "RX0,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 28. "TX,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 24.--26. "EHS,Element Handler State" "0: wait for bit M_CAN:CCCR.CCE getting zero,1: wait for Start Address,2: wait for Trigger Address,3: wait for transfer of Element word,4: acknowledge to M_CAN,5: exception recovery,?,?" bitfld.long 0x0 23. "DTXE,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 22. "DTX1,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 21. "DTX0,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 20. "DTX,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 16.--18. "DEHS,Detect Element Handler State" "?,?,?,?,?,?,?,7: unused state" newline bitfld.long 0x0 15. "ENA,DMU is enabled" "0: DMU is disabled,1: DMU is enabled and can process DMA data" hexmask.long.byte 0x0 8.--12. 1. "TFQPIP,TX FIFO/Queue Put Index Previous" newline bitfld.long 0x0 3. "TXER,TX Event Service Request line of DMU" "0: No TX Event DMA service requested,1: TX Event DMA Service requested" bitfld.long 0x0 2. "RX1R,RX1 Service Request line of DMU" "0: No RX1 DMA service requested,1: RX1 DMA Service requested" newline bitfld.long 0x0 1. "RX0R,RX0 Service Request line of DMU" "0: No RX0 DMA service requested,1: RX0 DMA Service requested" bitfld.long 0x0 0. "TXR,TX Service Request line of DMU" "0: No TX DMA service requested,1: TX DMA Service requested" line.long 0x4 "DMUQC,DMU Queuing Counter register" hexmask.long.byte 0x4 24.--31. 1. "TXEEDC,TX Event Element Dequeuing Counter" hexmask.long.byte 0x4 16.--23. 1. "RX1EDC,RX1 Element Dequeuing Counter" newline hexmask.long.byte 0x4 8.--15. 1. "RX0EDC,RX0 Element Dequeuing Counter" hexmask.long.byte 0x4 0.--7. 1. "TXEEC,TX Element Enqueuing Counter" line.long 0x8 "DMUIR,DMU Interrupt Register" bitfld.long 0x8 30. "IAC,Illegal Access while in Configuration mode" "0: No Illegal Access while CCE mode,1: Illegal Access while CCE mode" bitfld.long 0x8 29. "DT,Debug Trigger" "0: Debug point not reached,1: Debug point reached" newline bitfld.long 0x8 28. "TXEED,TX Event Element Dequeued" "0: No TX Event Element dequeued,1: TX Event Element successfully dequeued" bitfld.long 0x8 27. "TXEEIW,TX Event Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU TX Event Element.." newline bitfld.long 0x8 26. "TXEEIAS,TX Event Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 25. "TXEEID,TX Event Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 24. "TXEENSA,TX Event Element Not Start Address" "0: No illegal read access,1: Read from TX Event Element begins without using.." bitfld.long 0x8 21. "RX1EIO,RX1 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 20. "RX1ED,RX1 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 19. "RX1EIW,RX1 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 18. "RX1EIAS,RX1 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 17. "RX1EID,RX1 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 16. "RX1ENSA,RX1 Element Not Start Address" "0: No illegal read access,1: Read from RX1 Element begins without using start.." bitfld.long 0x8 15. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Uncorrected bit error detected" newline bitfld.long 0x8 14. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected" bitfld.long 0x8 13. "RX0EIO,RX0 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 12. "RX0ED,RX0 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 11. "RX0EIW,RX0 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 10. "RX0EIAS,RX0 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 9. "RX0EID,RX0 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 8. "RX0ENSA,RX0 Element Not Start Address" "0: No illegal read access,1: Read from RX0 Element begins without using start.." bitfld.long 0x8 6. "TXEE,TX Element Enqueued" "0: No Tx message enqueued,1: Tx message successfully enqueued" newline bitfld.long 0x8 5. "TXEIR,TX Element Illegal Read" "0: No read access,1: Illegal read access to DMU TX Element section.." bitfld.long 0x8 4. "TXEWATA,TX Element Write After Trigger Address" "0: No write after Trigger Address,1: Enqueue a message" newline bitfld.long 0x8 3. "TXEIDLC,TX Element Illegal DLC" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." bitfld.long 0x8 2. "TXEIAS,TX Element Illegal Access Sequence" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." newline bitfld.long 0x8 1. "TXEIE,TX Element Illegal Enqueuing" "0: No illegal enqueuing,1: Start of enqueuing without request detected.." bitfld.long 0x8 0. "TXENSA,TX Element Not Start Address" "0: No illegal write access,1: Write to TX Element begins without using start.." line.long 0xC "DMUIE,DMU Interrupt Enable register" bitfld.long 0xC 30. "IACE,Illegal Access while in Configuration mode Enable" "0: Flag DMUIR.IAC does not activate the interrupt..,1: If DMUIR.IAC = 1 the interrupt line dmu_int will.." bitfld.long 0xC 29. "DTE,Debug Trigger Enable" "0: Flag DMUIR.DT does not activate the interrupt..,1: If DMUIR.DT = 1 the interrupt line dmu_int will.." newline bitfld.long 0xC 28. "TXEEDE,TX Event Element Dequeued" "0: Flag DMUIR.TXEED does not activate the interrupt..,1: If DMUIR.TXEED = 1 the interrupt line dmu_int.." bitfld.long 0xC 27. "TXEEIWE,TX Event Element Illegal Write" "0: Flag DMUIR.TXEEIW does not activate the..,1: If DMUIR.TXEEIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 26. "TXEEIASE,TX Event Element Illegal Access Sequence" "0: Flag DMUIR.TXEEIAS does not activate the..,1: If DMUIR.TXEEIAS = 1 the interrupt line dmu_int.." bitfld.long 0xC 25. "TXEEIDE,TX Event Element Illegal Dequeuing" "0: Flag DMUIR.TXEEID does not activate the..,1: If DMUIR.TXEEID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 24. "TXEENSAE,TX Event Element Not Start Address" "0: Flag TXEENSA.TXEENSA does not activate the..,1: If TXEENSA.TXEENSA = 1 the interrupt line.." bitfld.long 0xC 21. "RX1EIOE,RX1 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX1EIO does not activate the..,1: If TXEENSA.RX1EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 20. "RX1EDE,RX1 Element Dequeued Enable" "0: Flag TXEENSA.RX1ED does not activate the..,1: If TXEENSA.RX1ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 19. "RX1EIWE,RX1 Element Illegal Write Enable" "0: Flag TXEENSA.RX1EIW does not activate the..,1: If TXEENSA.RX1EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 18. "RX1EIASE,RX1 Element Illegal Access Sequence Enable" "0: Flag TXEENSA.RX1EIAS does not activate the..,1: If TXEENSA.RX1EIAS = 1 the interrupt line.." bitfld.long 0xC 17. "RX1EIDE,RX1 Element Illegal Dequeuing Enable" "0: Flag TXEENSA.RX1EID does not activate the..,1: If TXEENSA.RX1EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 16. "RX1ENSAE,RX1 Element Not Start Address Enable" "0: Flag TXEENSA.RX1ENSA does not activate the..,1: If TXEENSA.RX1ENSA = 1 the interrupt line.." bitfld.long 0xC 15. "BEUE,Bit Error Uncorrected Enable" "0: Flag TXEENSA.BEU does not activate the interrupt..,1: If TXEENSA.BEU = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 14. "BECE,Bit Error Corrected Enable" "0: Flag TXEENSA.BEC does not activate the interrupt..,1: If TXEENSA.BEC = 1 the interrupt line dmu_int.." bitfld.long 0xC 13. "RX0EIOE,RX0 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX0EIO does not activate the..,1: If TXEENSA.RX0EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 12. "RX0EDE,RX0 Element Dequeued Enabled" "0: Flag TXEENSA.RX0ED does not activate the..,1: If TXEENSA.RX0ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 11. "RX0EIWE,RX0 Element Illegal Write Enabled" "0: Flag TXEENSA.RX0EIW does not activate the..,1: If TXEENSA.RX0EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 10. "RX0EIASE,RX0 Element Illegal Access Sequence Enabled" "0: Flag TXEENSA.RX0EIAS does not activate the..,1: If TXEENSA.RX0EIAS = 1 the interrupt line.." bitfld.long 0xC 9. "RX0EIDE,RX0 Element Illegal Dequeuing Enabled" "0: Flag TXEENSA.RX0EID does not activate the..,1: If TXEENSA.RX0EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 8. "RX0ENSAE,RX0 Element Not Start Address Enabled" "0: Flag TXEENSA.RX0ENSA does not activate the..,1: If TXEENSA.RX0ENSA = 1 the interrupt line.." bitfld.long 0xC 6. "TXEEE,TX Element Enqueued Enable" "0: Flag TXEENSA.TXEE does not activate the..,1: If TXEENSA.TXEE = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 5. "TXEIRE,TX Element Illegal Read Enable" "0: Flag TXEENSA.TXEIR does not activate the..,1: If TXEENSA.TXEIR = 1 the interrupt line dmu_int.." bitfld.long 0xC 4. "TXEWATAE,TX Element Write After Trigger Address Enable" "0: Flag TXEENSA.TXEWATA does not activate the..,1: If TXEENSA.TXEWATA = 1 the interrupt line.." newline bitfld.long 0xC 3. "TXEIDLCE,TX Element Illegal DLC Enable" "0: Flag TXEENSA.TXEIDLC does not activate the..,1: If TXEENSA.TXEIDLC = 1 the interrupt line.." bitfld.long 0xC 2. "TXEIASE,TX Element Illegal Access Sequence Enable" "0: Flag TXEENSA.TXEIAS does not activate the..,1: If TXEENSA.TXEIAS = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 1. "TXEIEE,TX Element Illegal Enqueuing Enable" "0: Flag TXEENSA.TXEIE does not activate the..,1: If TXEENSA.TXEIE = 1 the interrupt line dmu_int.." bitfld.long 0xC 0. "TXENSAE,TX Element Not Start Address Enable" "0: Flag DMUIR.TXENSA does not activate the..,1: If DMUIR.TXENSA = 1 the interrupt line dmu_int.." line.long 0x10 "DMUC,DMU Configuration register" bitfld.long 0x10 0. "TTS,Transfer Timestamp" "0: No timestamp will be transferred via DMU Virtual..,1: Timestamp of message will be transferred from.." tree.end tree "CAN_SUB_0_DMU_2" base ad:0x72008000 rgroup.long 0x3C0++0x3 line.long 0x0 "DMUCR,DMU Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" group.long 0x3C4++0x13 line.long 0x0 "DMUI,DMU Internals register" bitfld.long 0x0 31. "TXE,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 30. "RX1,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 29. "RX0,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 28. "TX,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 24.--26. "EHS,Element Handler State" "0: wait for bit M_CAN:CCCR.CCE getting zero,1: wait for Start Address,2: wait for Trigger Address,3: wait for transfer of Element word,4: acknowledge to M_CAN,5: exception recovery,?,?" bitfld.long 0x0 23. "DTXE,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 22. "DTX1,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 21. "DTX0,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 20. "DTX,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 16.--18. "DEHS,Detect Element Handler State" "?,?,?,?,?,?,?,7: unused state" newline bitfld.long 0x0 15. "ENA,DMU is enabled" "0: DMU is disabled,1: DMU is enabled and can process DMA data" hexmask.long.byte 0x0 8.--12. 1. "TFQPIP,TX FIFO/Queue Put Index Previous" newline bitfld.long 0x0 3. "TXER,TX Event Service Request line of DMU" "0: No TX Event DMA service requested,1: TX Event DMA Service requested" bitfld.long 0x0 2. "RX1R,RX1 Service Request line of DMU" "0: No RX1 DMA service requested,1: RX1 DMA Service requested" newline bitfld.long 0x0 1. "RX0R,RX0 Service Request line of DMU" "0: No RX0 DMA service requested,1: RX0 DMA Service requested" bitfld.long 0x0 0. "TXR,TX Service Request line of DMU" "0: No TX DMA service requested,1: TX DMA Service requested" line.long 0x4 "DMUQC,DMU Queuing Counter register" hexmask.long.byte 0x4 24.--31. 1. "TXEEDC,TX Event Element Dequeuing Counter" hexmask.long.byte 0x4 16.--23. 1. "RX1EDC,RX1 Element Dequeuing Counter" newline hexmask.long.byte 0x4 8.--15. 1. "RX0EDC,RX0 Element Dequeuing Counter" hexmask.long.byte 0x4 0.--7. 1. "TXEEC,TX Element Enqueuing Counter" line.long 0x8 "DMUIR,DMU Interrupt Register" bitfld.long 0x8 30. "IAC,Illegal Access while in Configuration mode" "0: No Illegal Access while CCE mode,1: Illegal Access while CCE mode" bitfld.long 0x8 29. "DT,Debug Trigger" "0: Debug point not reached,1: Debug point reached" newline bitfld.long 0x8 28. "TXEED,TX Event Element Dequeued" "0: No TX Event Element dequeued,1: TX Event Element successfully dequeued" bitfld.long 0x8 27. "TXEEIW,TX Event Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU TX Event Element.." newline bitfld.long 0x8 26. "TXEEIAS,TX Event Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 25. "TXEEID,TX Event Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 24. "TXEENSA,TX Event Element Not Start Address" "0: No illegal read access,1: Read from TX Event Element begins without using.." bitfld.long 0x8 21. "RX1EIO,RX1 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 20. "RX1ED,RX1 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 19. "RX1EIW,RX1 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 18. "RX1EIAS,RX1 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 17. "RX1EID,RX1 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 16. "RX1ENSA,RX1 Element Not Start Address" "0: No illegal read access,1: Read from RX1 Element begins without using start.." bitfld.long 0x8 15. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Uncorrected bit error detected" newline bitfld.long 0x8 14. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected" bitfld.long 0x8 13. "RX0EIO,RX0 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 12. "RX0ED,RX0 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 11. "RX0EIW,RX0 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 10. "RX0EIAS,RX0 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 9. "RX0EID,RX0 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 8. "RX0ENSA,RX0 Element Not Start Address" "0: No illegal read access,1: Read from RX0 Element begins without using start.." bitfld.long 0x8 6. "TXEE,TX Element Enqueued" "0: No Tx message enqueued,1: Tx message successfully enqueued" newline bitfld.long 0x8 5. "TXEIR,TX Element Illegal Read" "0: No read access,1: Illegal read access to DMU TX Element section.." bitfld.long 0x8 4. "TXEWATA,TX Element Write After Trigger Address" "0: No write after Trigger Address,1: Enqueue a message" newline bitfld.long 0x8 3. "TXEIDLC,TX Element Illegal DLC" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." bitfld.long 0x8 2. "TXEIAS,TX Element Illegal Access Sequence" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." newline bitfld.long 0x8 1. "TXEIE,TX Element Illegal Enqueuing" "0: No illegal enqueuing,1: Start of enqueuing without request detected.." bitfld.long 0x8 0. "TXENSA,TX Element Not Start Address" "0: No illegal write access,1: Write to TX Element begins without using start.." line.long 0xC "DMUIE,DMU Interrupt Enable register" bitfld.long 0xC 30. "IACE,Illegal Access while in Configuration mode Enable" "0: Flag DMUIR.IAC does not activate the interrupt..,1: If DMUIR.IAC = 1 the interrupt line dmu_int will.." bitfld.long 0xC 29. "DTE,Debug Trigger Enable" "0: Flag DMUIR.DT does not activate the interrupt..,1: If DMUIR.DT = 1 the interrupt line dmu_int will.." newline bitfld.long 0xC 28. "TXEEDE,TX Event Element Dequeued" "0: Flag DMUIR.TXEED does not activate the interrupt..,1: If DMUIR.TXEED = 1 the interrupt line dmu_int.." bitfld.long 0xC 27. "TXEEIWE,TX Event Element Illegal Write" "0: Flag DMUIR.TXEEIW does not activate the..,1: If DMUIR.TXEEIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 26. "TXEEIASE,TX Event Element Illegal Access Sequence" "0: Flag DMUIR.TXEEIAS does not activate the..,1: If DMUIR.TXEEIAS = 1 the interrupt line dmu_int.." bitfld.long 0xC 25. "TXEEIDE,TX Event Element Illegal Dequeuing" "0: Flag DMUIR.TXEEID does not activate the..,1: If DMUIR.TXEEID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 24. "TXEENSAE,TX Event Element Not Start Address" "0: Flag TXEENSA.TXEENSA does not activate the..,1: If TXEENSA.TXEENSA = 1 the interrupt line.." bitfld.long 0xC 21. "RX1EIOE,RX1 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX1EIO does not activate the..,1: If TXEENSA.RX1EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 20. "RX1EDE,RX1 Element Dequeued Enable" "0: Flag TXEENSA.RX1ED does not activate the..,1: If TXEENSA.RX1ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 19. "RX1EIWE,RX1 Element Illegal Write Enable" "0: Flag TXEENSA.RX1EIW does not activate the..,1: If TXEENSA.RX1EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 18. "RX1EIASE,RX1 Element Illegal Access Sequence Enable" "0: Flag TXEENSA.RX1EIAS does not activate the..,1: If TXEENSA.RX1EIAS = 1 the interrupt line.." bitfld.long 0xC 17. "RX1EIDE,RX1 Element Illegal Dequeuing Enable" "0: Flag TXEENSA.RX1EID does not activate the..,1: If TXEENSA.RX1EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 16. "RX1ENSAE,RX1 Element Not Start Address Enable" "0: Flag TXEENSA.RX1ENSA does not activate the..,1: If TXEENSA.RX1ENSA = 1 the interrupt line.." bitfld.long 0xC 15. "BEUE,Bit Error Uncorrected Enable" "0: Flag TXEENSA.BEU does not activate the interrupt..,1: If TXEENSA.BEU = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 14. "BECE,Bit Error Corrected Enable" "0: Flag TXEENSA.BEC does not activate the interrupt..,1: If TXEENSA.BEC = 1 the interrupt line dmu_int.." bitfld.long 0xC 13. "RX0EIOE,RX0 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX0EIO does not activate the..,1: If TXEENSA.RX0EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 12. "RX0EDE,RX0 Element Dequeued Enabled" "0: Flag TXEENSA.RX0ED does not activate the..,1: If TXEENSA.RX0ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 11. "RX0EIWE,RX0 Element Illegal Write Enabled" "0: Flag TXEENSA.RX0EIW does not activate the..,1: If TXEENSA.RX0EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 10. "RX0EIASE,RX0 Element Illegal Access Sequence Enabled" "0: Flag TXEENSA.RX0EIAS does not activate the..,1: If TXEENSA.RX0EIAS = 1 the interrupt line.." bitfld.long 0xC 9. "RX0EIDE,RX0 Element Illegal Dequeuing Enabled" "0: Flag TXEENSA.RX0EID does not activate the..,1: If TXEENSA.RX0EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 8. "RX0ENSAE,RX0 Element Not Start Address Enabled" "0: Flag TXEENSA.RX0ENSA does not activate the..,1: If TXEENSA.RX0ENSA = 1 the interrupt line.." bitfld.long 0xC 6. "TXEEE,TX Element Enqueued Enable" "0: Flag TXEENSA.TXEE does not activate the..,1: If TXEENSA.TXEE = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 5. "TXEIRE,TX Element Illegal Read Enable" "0: Flag TXEENSA.TXEIR does not activate the..,1: If TXEENSA.TXEIR = 1 the interrupt line dmu_int.." bitfld.long 0xC 4. "TXEWATAE,TX Element Write After Trigger Address Enable" "0: Flag TXEENSA.TXEWATA does not activate the..,1: If TXEENSA.TXEWATA = 1 the interrupt line.." newline bitfld.long 0xC 3. "TXEIDLCE,TX Element Illegal DLC Enable" "0: Flag TXEENSA.TXEIDLC does not activate the..,1: If TXEENSA.TXEIDLC = 1 the interrupt line.." bitfld.long 0xC 2. "TXEIASE,TX Element Illegal Access Sequence Enable" "0: Flag TXEENSA.TXEIAS does not activate the..,1: If TXEENSA.TXEIAS = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 1. "TXEIEE,TX Element Illegal Enqueuing Enable" "0: Flag TXEENSA.TXEIE does not activate the..,1: If TXEENSA.TXEIE = 1 the interrupt line dmu_int.." bitfld.long 0xC 0. "TXENSAE,TX Element Not Start Address Enable" "0: Flag DMUIR.TXENSA does not activate the..,1: If DMUIR.TXENSA = 1 the interrupt line dmu_int.." line.long 0x10 "DMUC,DMU Configuration register" bitfld.long 0x10 0. "TTS,Transfer Timestamp" "0: No timestamp will be transferred via DMU Virtual..,1: Timestamp of message will be transferred from.." tree.end tree "CAN_SUB_0_DMU_3" base ad:0x7200C000 rgroup.long 0x3C0++0x3 line.long 0x0 "DMUCR,DMU Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" group.long 0x3C4++0x13 line.long 0x0 "DMUI,DMU Internals register" bitfld.long 0x0 31. "TXE,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 30. "RX1,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 29. "RX0,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 28. "TX,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 24.--26. "EHS,Element Handler State" "0: wait for bit M_CAN:CCCR.CCE getting zero,1: wait for Start Address,2: wait for Trigger Address,3: wait for transfer of Element word,4: acknowledge to M_CAN,5: exception recovery,?,?" bitfld.long 0x0 23. "DTXE,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 22. "DTX1,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 21. "DTX0,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 20. "DTX,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 16.--18. "DEHS,Detect Element Handler State" "?,?,?,?,?,?,?,7: unused state" newline bitfld.long 0x0 15. "ENA,DMU is enabled" "0: DMU is disabled,1: DMU is enabled and can process DMA data" hexmask.long.byte 0x0 8.--12. 1. "TFQPIP,TX FIFO/Queue Put Index Previous" newline bitfld.long 0x0 3. "TXER,TX Event Service Request line of DMU" "0: No TX Event DMA service requested,1: TX Event DMA Service requested" bitfld.long 0x0 2. "RX1R,RX1 Service Request line of DMU" "0: No RX1 DMA service requested,1: RX1 DMA Service requested" newline bitfld.long 0x0 1. "RX0R,RX0 Service Request line of DMU" "0: No RX0 DMA service requested,1: RX0 DMA Service requested" bitfld.long 0x0 0. "TXR,TX Service Request line of DMU" "0: No TX DMA service requested,1: TX DMA Service requested" line.long 0x4 "DMUQC,DMU Queuing Counter register" hexmask.long.byte 0x4 24.--31. 1. "TXEEDC,TX Event Element Dequeuing Counter" hexmask.long.byte 0x4 16.--23. 1. "RX1EDC,RX1 Element Dequeuing Counter" newline hexmask.long.byte 0x4 8.--15. 1. "RX0EDC,RX0 Element Dequeuing Counter" hexmask.long.byte 0x4 0.--7. 1. "TXEEC,TX Element Enqueuing Counter" line.long 0x8 "DMUIR,DMU Interrupt Register" bitfld.long 0x8 30. "IAC,Illegal Access while in Configuration mode" "0: No Illegal Access while CCE mode,1: Illegal Access while CCE mode" bitfld.long 0x8 29. "DT,Debug Trigger" "0: Debug point not reached,1: Debug point reached" newline bitfld.long 0x8 28. "TXEED,TX Event Element Dequeued" "0: No TX Event Element dequeued,1: TX Event Element successfully dequeued" bitfld.long 0x8 27. "TXEEIW,TX Event Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU TX Event Element.." newline bitfld.long 0x8 26. "TXEEIAS,TX Event Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 25. "TXEEID,TX Event Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 24. "TXEENSA,TX Event Element Not Start Address" "0: No illegal read access,1: Read from TX Event Element begins without using.." bitfld.long 0x8 21. "RX1EIO,RX1 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 20. "RX1ED,RX1 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 19. "RX1EIW,RX1 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 18. "RX1EIAS,RX1 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 17. "RX1EID,RX1 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 16. "RX1ENSA,RX1 Element Not Start Address" "0: No illegal read access,1: Read from RX1 Element begins without using start.." bitfld.long 0x8 15. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Uncorrected bit error detected" newline bitfld.long 0x8 14. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected" bitfld.long 0x8 13. "RX0EIO,RX0 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 12. "RX0ED,RX0 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 11. "RX0EIW,RX0 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 10. "RX0EIAS,RX0 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 9. "RX0EID,RX0 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 8. "RX0ENSA,RX0 Element Not Start Address" "0: No illegal read access,1: Read from RX0 Element begins without using start.." bitfld.long 0x8 6. "TXEE,TX Element Enqueued" "0: No Tx message enqueued,1: Tx message successfully enqueued" newline bitfld.long 0x8 5. "TXEIR,TX Element Illegal Read" "0: No read access,1: Illegal read access to DMU TX Element section.." bitfld.long 0x8 4. "TXEWATA,TX Element Write After Trigger Address" "0: No write after Trigger Address,1: Enqueue a message" newline bitfld.long 0x8 3. "TXEIDLC,TX Element Illegal DLC" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." bitfld.long 0x8 2. "TXEIAS,TX Element Illegal Access Sequence" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." newline bitfld.long 0x8 1. "TXEIE,TX Element Illegal Enqueuing" "0: No illegal enqueuing,1: Start of enqueuing without request detected.." bitfld.long 0x8 0. "TXENSA,TX Element Not Start Address" "0: No illegal write access,1: Write to TX Element begins without using start.." line.long 0xC "DMUIE,DMU Interrupt Enable register" bitfld.long 0xC 30. "IACE,Illegal Access while in Configuration mode Enable" "0: Flag DMUIR.IAC does not activate the interrupt..,1: If DMUIR.IAC = 1 the interrupt line dmu_int will.." bitfld.long 0xC 29. "DTE,Debug Trigger Enable" "0: Flag DMUIR.DT does not activate the interrupt..,1: If DMUIR.DT = 1 the interrupt line dmu_int will.." newline bitfld.long 0xC 28. "TXEEDE,TX Event Element Dequeued" "0: Flag DMUIR.TXEED does not activate the interrupt..,1: If DMUIR.TXEED = 1 the interrupt line dmu_int.." bitfld.long 0xC 27. "TXEEIWE,TX Event Element Illegal Write" "0: Flag DMUIR.TXEEIW does not activate the..,1: If DMUIR.TXEEIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 26. "TXEEIASE,TX Event Element Illegal Access Sequence" "0: Flag DMUIR.TXEEIAS does not activate the..,1: If DMUIR.TXEEIAS = 1 the interrupt line dmu_int.." bitfld.long 0xC 25. "TXEEIDE,TX Event Element Illegal Dequeuing" "0: Flag DMUIR.TXEEID does not activate the..,1: If DMUIR.TXEEID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 24. "TXEENSAE,TX Event Element Not Start Address" "0: Flag TXEENSA.TXEENSA does not activate the..,1: If TXEENSA.TXEENSA = 1 the interrupt line.." bitfld.long 0xC 21. "RX1EIOE,RX1 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX1EIO does not activate the..,1: If TXEENSA.RX1EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 20. "RX1EDE,RX1 Element Dequeued Enable" "0: Flag TXEENSA.RX1ED does not activate the..,1: If TXEENSA.RX1ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 19. "RX1EIWE,RX1 Element Illegal Write Enable" "0: Flag TXEENSA.RX1EIW does not activate the..,1: If TXEENSA.RX1EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 18. "RX1EIASE,RX1 Element Illegal Access Sequence Enable" "0: Flag TXEENSA.RX1EIAS does not activate the..,1: If TXEENSA.RX1EIAS = 1 the interrupt line.." bitfld.long 0xC 17. "RX1EIDE,RX1 Element Illegal Dequeuing Enable" "0: Flag TXEENSA.RX1EID does not activate the..,1: If TXEENSA.RX1EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 16. "RX1ENSAE,RX1 Element Not Start Address Enable" "0: Flag TXEENSA.RX1ENSA does not activate the..,1: If TXEENSA.RX1ENSA = 1 the interrupt line.." bitfld.long 0xC 15. "BEUE,Bit Error Uncorrected Enable" "0: Flag TXEENSA.BEU does not activate the interrupt..,1: If TXEENSA.BEU = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 14. "BECE,Bit Error Corrected Enable" "0: Flag TXEENSA.BEC does not activate the interrupt..,1: If TXEENSA.BEC = 1 the interrupt line dmu_int.." bitfld.long 0xC 13. "RX0EIOE,RX0 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX0EIO does not activate the..,1: If TXEENSA.RX0EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 12. "RX0EDE,RX0 Element Dequeued Enabled" "0: Flag TXEENSA.RX0ED does not activate the..,1: If TXEENSA.RX0ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 11. "RX0EIWE,RX0 Element Illegal Write Enabled" "0: Flag TXEENSA.RX0EIW does not activate the..,1: If TXEENSA.RX0EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 10. "RX0EIASE,RX0 Element Illegal Access Sequence Enabled" "0: Flag TXEENSA.RX0EIAS does not activate the..,1: If TXEENSA.RX0EIAS = 1 the interrupt line.." bitfld.long 0xC 9. "RX0EIDE,RX0 Element Illegal Dequeuing Enabled" "0: Flag TXEENSA.RX0EID does not activate the..,1: If TXEENSA.RX0EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 8. "RX0ENSAE,RX0 Element Not Start Address Enabled" "0: Flag TXEENSA.RX0ENSA does not activate the..,1: If TXEENSA.RX0ENSA = 1 the interrupt line.." bitfld.long 0xC 6. "TXEEE,TX Element Enqueued Enable" "0: Flag TXEENSA.TXEE does not activate the..,1: If TXEENSA.TXEE = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 5. "TXEIRE,TX Element Illegal Read Enable" "0: Flag TXEENSA.TXEIR does not activate the..,1: If TXEENSA.TXEIR = 1 the interrupt line dmu_int.." bitfld.long 0xC 4. "TXEWATAE,TX Element Write After Trigger Address Enable" "0: Flag TXEENSA.TXEWATA does not activate the..,1: If TXEENSA.TXEWATA = 1 the interrupt line.." newline bitfld.long 0xC 3. "TXEIDLCE,TX Element Illegal DLC Enable" "0: Flag TXEENSA.TXEIDLC does not activate the..,1: If TXEENSA.TXEIDLC = 1 the interrupt line.." bitfld.long 0xC 2. "TXEIASE,TX Element Illegal Access Sequence Enable" "0: Flag TXEENSA.TXEIAS does not activate the..,1: If TXEENSA.TXEIAS = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 1. "TXEIEE,TX Element Illegal Enqueuing Enable" "0: Flag TXEENSA.TXEIE does not activate the..,1: If TXEENSA.TXEIE = 1 the interrupt line dmu_int.." bitfld.long 0xC 0. "TXENSAE,TX Element Not Start Address Enable" "0: Flag DMUIR.TXENSA does not activate the..,1: If DMUIR.TXENSA = 1 the interrupt line dmu_int.." line.long 0x10 "DMUC,DMU Configuration register" bitfld.long 0x10 0. "TTS,Transfer Timestamp" "0: No timestamp will be transferred via DMU Virtual..,1: Timestamp of message will be transferred from.." tree.end tree "CAN_SUB_0_M_CAN_1" base ad:0x72004000 rgroup.long 0x0++0x7 line.long 0x0 "CREL,Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Substep of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "TS_MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "ENDN,Endian Register" hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value" group.long 0xC++0x23 line.long 0x0 "DBTP,Data Bit Timing and Prescaler Register" bitfld.long 0x0 23. "TDC,Transceiver Delay Compensation" "0: Transceiver Delay Compensation disabled,1: Transceiver Delay Compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re) Synchronization Jump Width" line.long 0x4 "TEST,Test register" bitfld.long 0x4 21. "SVAL,Started Valid" "0: Value of TXBNS not valid,1: Value of TXBNS valid" hexmask.long.byte 0x4 16.--20. 1. "TXBNS,Tx Buffer Number Started" newline bitfld.long 0x4 13. "PVAL,Prepared Valid" "0: Value of TXBNP not valid,1: Value of TXBNP valid" hexmask.long.byte 0x4 8.--12. 1. "TXBNP,Tx Buffer Number Prepared" newline bitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant (CAN Rx input = '0'),1: The CAN bus is recessive (CAN Rx input = '1')" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CAN Tx output is controlled by the..,1: Sample Point can be monitored at pin CAN Tx output,2: Dominant ('0') level at pin CAN Tx output,3: Recessive ('1') at pin CAN Tx output" newline bitfld.long 0x4 4. "LBCK,Loop Back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (refer to.." line.long 0x8 "RWD,RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration" line.long 0xC "CCCR,CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0xC 11. "WMM,Wide Message Marker" "0: 8-bit Message Marker used,1: 16-bit Message Marker used replacing 16-bit.." bitfld.long 0xC 10. "UTSU,Use Timestamping Unit" "0: Internal time stamping,1: External time stamping by TSU" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST_EN,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_CAN may be set in power down by stopping Host.." bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started" line.long 0x10 "NBTP,Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,(Re) Synchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Time segment before sample point" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,The time segment after the sample point" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Same as 00" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. "TOC,The Timeout Counter is decremented in multiples of CAN bit times (1 to 16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are.." rgroup.long 0x40++0x7 line.long 0x0 "ECR,Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "PSR,Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Received CAN FD Message" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set." newline bitfld.long 0x4 11. "RESI,ESI CAN FD Message with ESI flag" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state" bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state. It..,1: The M_CAN is in the Error_Passive state" bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing node is synchronizing on CAN..,1: Idle-node is neither receiver nor transmitter,2: Receiver-node is operating as receiver,3: Transmitter-node is operating as transmitter" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: consecutive recessive bits,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.." group.long 0x48++0x3 line.long 0x0 "TDCR,Transmitter Delay compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0xF line.long 0x0 "IR,Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected uncorrected (for example.." bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected (for example ECC)" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Event Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx Event FIDO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "IE,Interrupt Enable Register" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "ILS,Interrupt Line Select Register" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 16. "TSWL,TSWL: Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" line.long 0xC "ILE,Interrupt Line Enable Register" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line disabled,1: Interrupt line enabled" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line disabled,1: Interrupt line enabled" group.long 0x80++0xB line.long 0x0 "GFC,Global Filter Configuration Register" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,ANFE[1:0]: Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x8 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x3 line.long 0x0 "XIDAM,Extended ID and Mask Register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "HPMS,High Priority Message Status Register" bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "NDAT1,New Data 1 Register" bitfld.long 0x0 31. "ND31,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 30. "ND30,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 28. "ND28,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 26. "ND26,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 24. "ND24,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 22. "ND22,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 20. "ND20,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 18. "ND18,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 16. "ND16,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 14. "ND14,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 12. "ND12,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 10. "ND10,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 8. "ND8,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 6. "ND6,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 4. "ND4,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 2. "ND2,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 0. "ND0,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x4 "NDAT2,New Data 2 Register" bitfld.long 0x4 31. "ND63,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 30. "ND62,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 28. "ND60,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 26. "ND58,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 24. "ND56,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 22. "ND54,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 20. "ND52,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 18. "ND50,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 16. "ND48,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 14. "ND46,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 12. "ND44,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 10. "ND42,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 8. "ND40,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 6. "ND38,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 4. "ND36,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 2. "ND34,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 0. "ND32,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x8 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x0 25. "RF0L,RF0L" "0,1" bitfld.long 0x0 24. "F0F,F0F" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,F0PI" hexmask.long.byte 0x0 8.--13. 1. "F0GI,F0GI" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,F0FL" group.long 0xA8++0xB line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "RXF1C,Rx FIFO 1 Configuration Register" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,F1S[6:0]:" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is set" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" line.long 0x8 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Tx FIFO/Queue Size" newline hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x3 line.long 0x0 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x0 31. "AR31,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 30. "AR30,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 29. "AR29,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 28. "AR28,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 27. "AR27,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 26. "AR26,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 25. "AR25,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 24. "AR24,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 23. "AR23,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 22. "AR22,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 21. "AR21,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 20. "AR20,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 19. "AR19,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 18. "AR18,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 17. "AR17,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 16. "AR16,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 15. "AR15,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 14. "AR14,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 13. "AR13,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 12. "AR12,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 11. "AR11,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 10. "AR10,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 9. "AR9,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 8. "AR8,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 7. "AR7,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 6. "AR6,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 5. "AR5,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 4. "AR4,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 3. "AR3,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 2. "AR2,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 1. "AR1,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 0. "AR0,Add Request" "0: No transmission request added,1: Transmission requested added" line.long 0x4 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x4 31. "CR31,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 30. "CR30,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 29. "CR29,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 28. "CR28,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 27. "CR27,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 26. "CR26,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 24. "CR24,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 23. "CR23,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 22. "CR22,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 21. "CR21,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 20. "CR20,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 18. "CR18,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 17. "CR17,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 16. "CR16,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 15. "CR15,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 14. "CR14,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 12. "CR12,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 11. "CR11,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 10. "CR10,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 9. "CR9,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 8. "CR8,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 6. "CR6,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 5. "CR5,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 4. "CR4,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 3. "CR3,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 2. "CR2,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 0. "CR0,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" rgroup.long 0xD8++0x7 line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 29. "TO29,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 28. "TO28,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 27. "TO27,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 23. "TO23,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 22. "TO22,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 21. "TO21,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 17. "TO17,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 16. "TO16,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 15. "TO15,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 11. "TO11,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 10. "TO10,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 9. "TO9,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 5. "TO5,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 4. "TO4,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 3. "TO3,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 29. "CF29,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 28. "CF28,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 27. "CF27,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 23. "CF23,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 22. "CF22,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 21. "CF21,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 17. "CF17,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 16. "CF16,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 15. "CF15,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 11. "CF11,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 10. "CF10,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 9. "CF9,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 5. "CF5,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 4. "CF4,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 3. "CF3,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" group.long 0xE0++0x7 line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" group.long 0xF0++0x3 line.long 0x0 "TXEFC,Tx Event FIFO Configuration Register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address." rgroup.long 0xF4++0x3 line.long 0x0 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0x3 line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge Register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" tree.end tree "CAN_SUB_0_M_CAN_2" base ad:0x72008000 rgroup.long 0x0++0x7 line.long 0x0 "CREL,Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Substep of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "TS_MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "ENDN,Endian Register" hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value" group.long 0xC++0x23 line.long 0x0 "DBTP,Data Bit Timing and Prescaler Register" bitfld.long 0x0 23. "TDC,Transceiver Delay Compensation" "0: Transceiver Delay Compensation disabled,1: Transceiver Delay Compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re) Synchronization Jump Width" line.long 0x4 "TEST,Test register" bitfld.long 0x4 21. "SVAL,Started Valid" "0: Value of TXBNS not valid,1: Value of TXBNS valid" hexmask.long.byte 0x4 16.--20. 1. "TXBNS,Tx Buffer Number Started" newline bitfld.long 0x4 13. "PVAL,Prepared Valid" "0: Value of TXBNP not valid,1: Value of TXBNP valid" hexmask.long.byte 0x4 8.--12. 1. "TXBNP,Tx Buffer Number Prepared" newline bitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant (CAN Rx input = '0'),1: The CAN bus is recessive (CAN Rx input = '1')" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CAN Tx output is controlled by the..,1: Sample Point can be monitored at pin CAN Tx output,2: Dominant ('0') level at pin CAN Tx output,3: Recessive ('1') at pin CAN Tx output" newline bitfld.long 0x4 4. "LBCK,Loop Back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (refer to.." line.long 0x8 "RWD,RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration" line.long 0xC "CCCR,CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0xC 11. "WMM,Wide Message Marker" "0: 8-bit Message Marker used,1: 16-bit Message Marker used replacing 16-bit.." bitfld.long 0xC 10. "UTSU,Use Timestamping Unit" "0: Internal time stamping,1: External time stamping by TSU" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST_EN,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_CAN may be set in power down by stopping Host.." bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started" line.long 0x10 "NBTP,Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,(Re) Synchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Time segment before sample point" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,The time segment after the sample point" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Same as 00" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. "TOC,The Timeout Counter is decremented in multiples of CAN bit times (1 to 16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are.." rgroup.long 0x40++0x7 line.long 0x0 "ECR,Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "PSR,Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Received CAN FD Message" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set." newline bitfld.long 0x4 11. "RESI,ESI CAN FD Message with ESI flag" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state" bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state. It..,1: The M_CAN is in the Error_Passive state" bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing node is synchronizing on CAN..,1: Idle-node is neither receiver nor transmitter,2: Receiver-node is operating as receiver,3: Transmitter-node is operating as transmitter" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: consecutive recessive bits,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.." group.long 0x48++0x3 line.long 0x0 "TDCR,Transmitter Delay compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0xF line.long 0x0 "IR,Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected uncorrected (for example.." bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected (for example ECC)" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Event Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx Event FIDO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "IE,Interrupt Enable Register" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "ILS,Interrupt Line Select Register" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 16. "TSWL,TSWL: Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" line.long 0xC "ILE,Interrupt Line Enable Register" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line disabled,1: Interrupt line enabled" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line disabled,1: Interrupt line enabled" group.long 0x80++0xB line.long 0x0 "GFC,Global Filter Configuration Register" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,ANFE[1:0]: Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x8 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x3 line.long 0x0 "XIDAM,Extended ID and Mask Register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "HPMS,High Priority Message Status Register" bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "NDAT1,New Data 1 Register" bitfld.long 0x0 31. "ND31,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 30. "ND30,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 28. "ND28,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 26. "ND26,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 24. "ND24,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 22. "ND22,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 20. "ND20,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 18. "ND18,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 16. "ND16,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 14. "ND14,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 12. "ND12,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 10. "ND10,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 8. "ND8,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 6. "ND6,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 4. "ND4,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 2. "ND2,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 0. "ND0,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x4 "NDAT2,New Data 2 Register" bitfld.long 0x4 31. "ND63,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 30. "ND62,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 28. "ND60,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 26. "ND58,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 24. "ND56,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 22. "ND54,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 20. "ND52,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 18. "ND50,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 16. "ND48,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 14. "ND46,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 12. "ND44,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 10. "ND42,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 8. "ND40,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 6. "ND38,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 4. "ND36,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 2. "ND34,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 0. "ND32,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x8 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x0 25. "RF0L,RF0L" "0,1" bitfld.long 0x0 24. "F0F,F0F" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,F0PI" hexmask.long.byte 0x0 8.--13. 1. "F0GI,F0GI" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,F0FL" group.long 0xA8++0xB line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "RXF1C,Rx FIFO 1 Configuration Register" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,F1S[6:0]:" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is set" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" line.long 0x8 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Tx FIFO/Queue Size" newline hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x3 line.long 0x0 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x0 31. "AR31,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 30. "AR30,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 29. "AR29,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 28. "AR28,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 27. "AR27,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 26. "AR26,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 25. "AR25,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 24. "AR24,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 23. "AR23,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 22. "AR22,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 21. "AR21,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 20. "AR20,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 19. "AR19,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 18. "AR18,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 17. "AR17,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 16. "AR16,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 15. "AR15,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 14. "AR14,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 13. "AR13,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 12. "AR12,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 11. "AR11,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 10. "AR10,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 9. "AR9,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 8. "AR8,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 7. "AR7,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 6. "AR6,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 5. "AR5,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 4. "AR4,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 3. "AR3,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 2. "AR2,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 1. "AR1,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 0. "AR0,Add Request" "0: No transmission request added,1: Transmission requested added" line.long 0x4 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x4 31. "CR31,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 30. "CR30,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 29. "CR29,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 28. "CR28,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 27. "CR27,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 26. "CR26,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 24. "CR24,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 23. "CR23,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 22. "CR22,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 21. "CR21,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 20. "CR20,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 18. "CR18,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 17. "CR17,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 16. "CR16,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 15. "CR15,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 14. "CR14,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 12. "CR12,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 11. "CR11,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 10. "CR10,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 9. "CR9,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 8. "CR8,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 6. "CR6,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 5. "CR5,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 4. "CR4,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 3. "CR3,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 2. "CR2,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 0. "CR0,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" rgroup.long 0xD8++0x7 line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 29. "TO29,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 28. "TO28,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 27. "TO27,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 23. "TO23,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 22. "TO22,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 21. "TO21,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 17. "TO17,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 16. "TO16,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 15. "TO15,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 11. "TO11,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 10. "TO10,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 9. "TO9,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 5. "TO5,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 4. "TO4,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 3. "TO3,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 29. "CF29,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 28. "CF28,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 27. "CF27,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 23. "CF23,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 22. "CF22,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 21. "CF21,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 17. "CF17,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 16. "CF16,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 15. "CF15,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 11. "CF11,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 10. "CF10,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 9. "CF9,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 5. "CF5,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 4. "CF4,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 3. "CF3,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" group.long 0xE0++0x7 line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" group.long 0xF0++0x3 line.long 0x0 "TXEFC,Tx Event FIFO Configuration Register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address." rgroup.long 0xF4++0x3 line.long 0x0 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0x3 line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge Register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" tree.end tree "CAN_SUB_0_M_CAN_3" base ad:0x7200C000 rgroup.long 0x0++0x7 line.long 0x0 "CREL,Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Substep of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "TS_MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "ENDN,Endian Register" hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value" group.long 0xC++0x23 line.long 0x0 "DBTP,Data Bit Timing and Prescaler Register" bitfld.long 0x0 23. "TDC,Transceiver Delay Compensation" "0: Transceiver Delay Compensation disabled,1: Transceiver Delay Compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re) Synchronization Jump Width" line.long 0x4 "TEST,Test register" bitfld.long 0x4 21. "SVAL,Started Valid" "0: Value of TXBNS not valid,1: Value of TXBNS valid" hexmask.long.byte 0x4 16.--20. 1. "TXBNS,Tx Buffer Number Started" newline bitfld.long 0x4 13. "PVAL,Prepared Valid" "0: Value of TXBNP not valid,1: Value of TXBNP valid" hexmask.long.byte 0x4 8.--12. 1. "TXBNP,Tx Buffer Number Prepared" newline bitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant (CAN Rx input = '0'),1: The CAN bus is recessive (CAN Rx input = '1')" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CAN Tx output is controlled by the..,1: Sample Point can be monitored at pin CAN Tx output,2: Dominant ('0') level at pin CAN Tx output,3: Recessive ('1') at pin CAN Tx output" newline bitfld.long 0x4 4. "LBCK,Loop Back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (refer to.." line.long 0x8 "RWD,RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration" line.long 0xC "CCCR,CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0xC 11. "WMM,Wide Message Marker" "0: 8-bit Message Marker used,1: 16-bit Message Marker used replacing 16-bit.." bitfld.long 0xC 10. "UTSU,Use Timestamping Unit" "0: Internal time stamping,1: External time stamping by TSU" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST_EN,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_CAN may be set in power down by stopping Host.." bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started" line.long 0x10 "NBTP,Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,(Re) Synchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Time segment before sample point" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,The time segment after the sample point" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Same as 00" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. "TOC,The Timeout Counter is decremented in multiples of CAN bit times (1 to 16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are.." rgroup.long 0x40++0x7 line.long 0x0 "ECR,Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "PSR,Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Received CAN FD Message" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set." newline bitfld.long 0x4 11. "RESI,ESI CAN FD Message with ESI flag" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state" bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state. It..,1: The M_CAN is in the Error_Passive state" bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing node is synchronizing on CAN..,1: Idle-node is neither receiver nor transmitter,2: Receiver-node is operating as receiver,3: Transmitter-node is operating as transmitter" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: consecutive recessive bits,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.." group.long 0x48++0x3 line.long 0x0 "TDCR,Transmitter Delay compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0xF line.long 0x0 "IR,Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected uncorrected (for example.." bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected (for example ECC)" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Event Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx Event FIDO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "IE,Interrupt Enable Register" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "ILS,Interrupt Line Select Register" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 16. "TSWL,TSWL: Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" line.long 0xC "ILE,Interrupt Line Enable Register" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line disabled,1: Interrupt line enabled" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line disabled,1: Interrupt line enabled" group.long 0x80++0xB line.long 0x0 "GFC,Global Filter Configuration Register" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,ANFE[1:0]: Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x8 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x3 line.long 0x0 "XIDAM,Extended ID and Mask Register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "HPMS,High Priority Message Status Register" bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "NDAT1,New Data 1 Register" bitfld.long 0x0 31. "ND31,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 30. "ND30,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 28. "ND28,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 26. "ND26,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 24. "ND24,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 22. "ND22,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 20. "ND20,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 18. "ND18,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 16. "ND16,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 14. "ND14,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 12. "ND12,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 10. "ND10,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 8. "ND8,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 6. "ND6,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 4. "ND4,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 2. "ND2,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 0. "ND0,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x4 "NDAT2,New Data 2 Register" bitfld.long 0x4 31. "ND63,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 30. "ND62,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 28. "ND60,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 26. "ND58,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 24. "ND56,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 22. "ND54,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 20. "ND52,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 18. "ND50,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 16. "ND48,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 14. "ND46,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 12. "ND44,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 10. "ND42,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 8. "ND40,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 6. "ND38,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 4. "ND36,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 2. "ND34,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 0. "ND32,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x8 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x0 25. "RF0L,RF0L" "0,1" bitfld.long 0x0 24. "F0F,F0F" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,F0PI" hexmask.long.byte 0x0 8.--13. 1. "F0GI,F0GI" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,F0FL" group.long 0xA8++0xB line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "RXF1C,Rx FIFO 1 Configuration Register" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,F1S[6:0]:" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is set" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" line.long 0x8 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Tx FIFO/Queue Size" newline hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x3 line.long 0x0 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x0 31. "AR31,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 30. "AR30,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 29. "AR29,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 28. "AR28,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 27. "AR27,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 26. "AR26,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 25. "AR25,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 24. "AR24,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 23. "AR23,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 22. "AR22,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 21. "AR21,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 20. "AR20,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 19. "AR19,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 18. "AR18,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 17. "AR17,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 16. "AR16,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 15. "AR15,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 14. "AR14,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 13. "AR13,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 12. "AR12,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 11. "AR11,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 10. "AR10,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 9. "AR9,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 8. "AR8,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 7. "AR7,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 6. "AR6,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 5. "AR5,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 4. "AR4,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 3. "AR3,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 2. "AR2,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 1. "AR1,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 0. "AR0,Add Request" "0: No transmission request added,1: Transmission requested added" line.long 0x4 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x4 31. "CR31,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 30. "CR30,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 29. "CR29,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 28. "CR28,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 27. "CR27,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 26. "CR26,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 24. "CR24,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 23. "CR23,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 22. "CR22,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 21. "CR21,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 20. "CR20,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 18. "CR18,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 17. "CR17,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 16. "CR16,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 15. "CR15,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 14. "CR14,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 12. "CR12,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 11. "CR11,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 10. "CR10,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 9. "CR9,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 8. "CR8,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 6. "CR6,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 5. "CR5,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 4. "CR4,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 3. "CR3,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 2. "CR2,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 0. "CR0,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" rgroup.long 0xD8++0x7 line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 29. "TO29,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 28. "TO28,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 27. "TO27,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 23. "TO23,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 22. "TO22,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 21. "TO21,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 17. "TO17,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 16. "TO16,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 15. "TO15,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 11. "TO11,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 10. "TO10,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 9. "TO9,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 5. "TO5,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 4. "TO4,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 3. "TO3,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 29. "CF29,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 28. "CF28,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 27. "CF27,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 23. "CF23,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 22. "CF22,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 21. "CF21,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 17. "CF17,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 16. "CF16,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 15. "CF15,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 11. "CF11,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 10. "CF10,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 9. "CF9,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 5. "CF5,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 4. "CF4,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 3. "CF3,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" group.long 0xE0++0x7 line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" group.long 0xF0++0x3 line.long 0x0 "TXEFC,Tx Event FIFO Configuration Register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address." rgroup.long 0xF4++0x3 line.long 0x0 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0x3 line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge Register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" tree.end tree "CAN_SUB_0_M_TTCAN_0" base ad:0x72000000 rgroup.long 0x0++0x7 line.long 0x0 "CREL,Core Release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "TS_MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "ENDN,Endian Register" hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value" group.long 0xC++0x23 line.long 0x0 "DBTP,Data Bit Timing and Prescaler register" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Bit Rate Prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width" line.long 0x4 "TEST,Test Register" bitfld.long 0x4 21. "SVAL,Started Valid" "0: Value of TXBNS not valid,1: Value of TXBNS valid" hexmask.long.byte 0x4 16.--20. 1. "TXBNS,Tx Buffer Number Started" newline bitfld.long 0x4 13. "PVAL,Prepared Valid" "0: Value of TXBNP not valid,1: Value of TXBNP valid" hexmask.long.byte 0x4 8.--12. 1. "TXBNP,Tx Buffer Number Prepared" newline bitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant,1: The CAN bus is recessive" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value TTCAN Tx output pinis controlled by..,1: Sample Point can be monitored at TTCAN Tx output..,2: Dominant (0) level at TTCAN Tx output pin,3: Recessive (1) at TTCAN Tx output pin" newline bitfld.long 0x4 4. "LBCK,Loop Back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (refer to.." bitfld.long 0x4 3. "CAT,Check ASC Transmit Control" "0: Output M_TTCAN ASC transmit control pin = 0,1: Output M_TTCAN ASC transmit control pin = 1" newline bitfld.long 0x4 2. "CAM,Check ASC Multiplexer Control" "0: Output M_TTCAN ASC multiplexer control pin = 0,1: Output M_TTCAN ASC multiplexer control pin = 1" bitfld.long 0x4 1. "TAT,Test ASC Transmit Control" "0: Level at M_TTCAN ASC transmit control pin..,1: Level at M_TTCAN ASC transmit control pin = 1" newline bitfld.long 0x4 0. "TAM,Test ASC Multiplexer Control" "0: Level at M_TTCAN ASC multiplexer control pin..,1: Level at M_TTCAN ASC multiplexer control pin = 1" line.long 0x8 "RWD,RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration" line.long 0xC "CCCR,CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0xC 14. "TXP,TXP Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,CAN FD Bit Rate Switching" "0: This node transmits no frames with bit rate..,1: This node transmits all frames (excluding remote.." bitfld.long 0xC 12. "PXHD,CAN FD Operation" "0: This node transmits all frames in CAN format..,1: This node transmits all frames (excluding remote.." newline bitfld.long 0xC 11. "WMM,Wide Message Marker" "0: 8-bit Message Marker used,1: 16-bit Message Marker used replacing 16-bit.." bitfld.long 0xC 10. "UTSU,Use Timestamping Unit" "0: Internal time stamping,1: External time stamping by TSU" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST_EN,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_TTCAN may be set in power down by stopping.." bitfld.long 0xC 2. "ASM,ASM Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started" line.long 0x10 "NBTP,Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re) Synchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Same as 00" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter" rgroup.long 0x40++0x7 line.long 0x0 "ECR,Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "PSR,Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Received CAN FD Message" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with EDL flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set." newline bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" bitfld.long 0x4 8.--10. "DLEC,Data phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_TTCAN is not Bus_Off,1: The M_TTCAN is in Bus_Off state" bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive" "0: The M_TTCAN is in the Error_Active state. It..,1: The M_TTCAN is in the Error_Passive state" bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter,2: Receiver: node is operating as receiver,3: Transmitter: node is operating as transmitter" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the M_TTCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.." group.long 0x48++0x3 line.long 0x0 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0xF line.long 0x0 "IR,Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol Error in Data phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.." bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected uncorrected (for example.." bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected (for example ECC)" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "IE,Interrupt Enable Register" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 28. "PEDE,Protocol Error in Data phase Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "ILS,Interrupt Line Select Register" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data phase Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" bitfld.long 0x8 16. "TSWL,TSWL: Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_TTCAN INT0,1: Interrupt assigned to interrupt line M_TTCAN INT1" line.long 0xC "ILE,Interrupt Line Enable Register" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line disabled,1: Interrupt line enabled" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line disabled,1: Interrupt line enabled" group.long 0x80++0xB line.long 0x0 "GFC,Global Filter Configuration Register" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x8 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x3 line.long 0x0 "XIDAM,Extended ID and Mask Register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "HPMS,High Priority Message Status Register" bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "NDAT1,New Data 1 Register" bitfld.long 0x0 31. "ND31,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 30. "ND30,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 28. "ND28,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 26. "ND26,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 24. "ND24,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 22. "ND22,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 20. "ND20,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 18. "ND18,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 16. "ND16,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 14. "ND14,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 12. "ND12,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 10. "ND10,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 8. "ND8,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 6. "ND6,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 4. "ND4,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 2. "ND2,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 0. "ND0,New Data [31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x4 "NDAT2,New Data 2 Register" bitfld.long 0x4 31. "ND63,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 30. "ND62,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 28. "ND60,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 26. "ND58,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 24. "ND56,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 22. "ND54,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 20. "ND52,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 18. "ND50,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 16. "ND48,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 14. "ND46,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 12. "ND44,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 10. "ND42,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 8. "ND40,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 6. "ND38,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 4. "ND36,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 2. "ND34,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 0. "ND32,New Data [63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x8 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0xA8++0xB line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "RXF1C,Rx FIFO 1 Configuration Register" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is set" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "RXESC,Rx Buffer / FIFO element size configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" line.long 0x8 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" newline hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "TXESC,Tx buffer element size configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x3 line.long 0x0 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x0 31. "AR31,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 30. "AR30,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 29. "AR29,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 28. "AR28,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 27. "AR27,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 26. "AR26,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 25. "AR25,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 24. "AR24,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 23. "AR23,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 22. "AR22,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 21. "AR21,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 20. "AR20,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 19. "AR19,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 18. "AR18,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 17. "AR17,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 16. "AR16,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 15. "AR15,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 14. "AR14,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 13. "AR13,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 12. "AR12,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 11. "AR11,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 10. "AR10,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 9. "AR9,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 8. "AR8,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 7. "AR7,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 6. "AR6,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 5. "AR5,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 4. "AR4,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 3. "AR3,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 2. "AR2,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 1. "AR1,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 0. "AR0,Add Request" "0: No transmission request added,1: Transmission requested added" line.long 0x4 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x4 31. "CR31,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 30. "CR30,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 29. "CR29,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 28. "CR28,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 27. "CR27,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 26. "CR26,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 24. "CR24,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 23. "CR23,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 22. "CR22,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 21. "CR21,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 20. "CR20,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 18. "CR18,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 17. "CR17,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 16. "CR16,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 15. "CR15,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 14. "CR14,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 12. "CR12,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 11. "CR11,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 10. "CR10,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 9. "CR9,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 8. "CR8,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 6. "CR6,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 5. "CR5,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 4. "CR4,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 3. "CR3,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 2. "CR2,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 0. "CR0,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" rgroup.long 0xD8++0x7 line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 29. "TO29,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 28. "TO28,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 27. "TO27,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 23. "TO23,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 22. "TO22,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 21. "TO21,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 17. "TO17,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 16. "TO16,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 15. "TO15,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 11. "TO11,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 10. "TO10,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 9. "TO9,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 5. "TO5,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 4. "TO4,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 3. "TO3,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 29. "CF29,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 28. "CF28,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 27. "CF27,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 23. "CF23,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 22. "CF22,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 21. "CF21,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 17. "CF17,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 16. "CF16,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 15. "CF15,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 11. "CF11,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 10. "CF10,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 9. "CF9,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 5. "CF5,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 4. "CF4,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 3. "CF3,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" group.long 0xE0++0x7 line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" group.long 0xF0++0x3 line.long 0x0 "TXEFC,Tx Event FIFO Configuration Register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size." newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost." "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 24. "EFF,Event FIFO Full." "0: Tx Event FIFO not full,1: Tx Event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index." hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index." newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level." group.long 0xF8++0x3 line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge Register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index." group.long 0x100++0x2B line.long 0x0 "TTTMC,TT Trigger Memory Configuration Register" hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger Memory Elements." hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger Memory Start Address." line.long 0x4 "TTRMC,TT Reference Message Configuration Register" bitfld.long 0x4 31. "RMPS,Reference Message Payload Select." "0: Reference message has no additional payload,1: bytes 2-8" bitfld.long 0x4 30. "XTD,Extended Identifier" "0: 11-bit standard identifier,1: 29-bit extended identifier" newline hexmask.long 0x4 0.--28. 1. "RID,Reference Identifier." line.long 0x8 "TTOCF,TT Operation Configuration Register" bitfld.long 0x8 26. "EVTP,Event Trigger Polarity" "0: Rising edge trigger,1: Falling edge trigger" bitfld.long 0x8 25. "ECC,Enable Clock Calibration" "0: Automatic clock calibration in M_TTCAN Level 0 2..,1: Automatic clock calibration in M_TTCAN Level 0 2.." newline bitfld.long 0x8 24. "EGTF,Enable Global Time Filtering" "0: Global time filtering in M_TTCAN Level 0 2 is..,1: Global time filtering in M_TTCAN Level 0 2 is.." hexmask.long.byte 0x8 16.--23. 1. "AWL,Application Watchdog Limit" newline bitfld.long 0x8 15. "EECS,Enable External Clock Synchronization" "0: External clock synchronization in M_TTCAN Level..,1: External clock synchronization in M_TTCAN Level.." hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial Reference Trigger Offset" newline bitfld.long 0x8 5.--7. "LDSDL,LD of Synchronization Deviation Limit" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "TM,Time Master" "0: Time Master function disabled,1: Potential Time Master" newline bitfld.long 0x8 3. "GEN,Gap Enable" "0: Strictly time-triggered operation,1: External event-synchronized time-triggered.." bitfld.long 0x8 0.--1. "OM,Operation Mode" "0: Event-driven CAN communication default,1: M_TTCAN level 1,2: M_TTCAN level 2,3: M_TTCAN level 0" line.long 0xC "TTMLM,TT Matrix Limits Register" hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected Number of Tx Triggers" hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx Enable Window" newline bitfld.long 0xC 6.--7. "CSS,Cycle Start Synchronization" "0: No sync pulse,1: Sync pulse at start of basic cycle,2: Sync pulse at start of matrix cycle,?" hexmask.long.byte 0xC 0.--5. 1. "CCM,Cycle Count Max" line.long 0x10 "TURCF,TUR Configuration Register" bitfld.long 0x10 31. "ELT,Enable Local Time" "0: Local time is stopped default,1: Local time is enabled" hexmask.long.word 0x10 16.--29. 1. "DC,Denominator Configuration" newline hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator Configuration Low" line.long 0x14 "TTOCN,TT Operation Control Register" bitfld.long 0x14 15. "LCKC,TT Operation Control Register Locked" "0: Write access to TTOCN enabled,1: Write access to TTOCN locked" bitfld.long 0x14 13. "ESCN,External Synchronization Control" "0: External synchronization disabled,1: External synchronization enabled" newline bitfld.long 0x14 12. "NIG,Next is Gap" "0: No action reset by reception of any Reference..,1: Transmit next Reference Message with Next_is_Gap.." bitfld.long 0x14 11. "TMG,Time Mark Gap" "0: Reset by each Reference message,1: Next Reference message started when Register.." newline bitfld.long 0x14 10. "FGP,Finish Gap" "0: No reference message requested,1: Application requested start of reference message" bitfld.long 0x14 9. "GCS,Gap Control Select" "0: Gap control independent from Event trigger,1: Gap control by input Event trigger pin" newline bitfld.long 0x14 8. "TTIE,Trigger Time Mark Interrupt Pulse Enable" "0: Trigger Time Mark Interrupt output disabled,1: Trigger Time Mark Interrupt output enabled" bitfld.long 0x14 6.--7. "TMC,Register Time Mark Compare" "0: No Register Time Mark Interrupt generated,1: Register Time Mark Interrupt if Time Mark =..,2: Register Time Mark Interrupt if Time Mark =..,3: Register Time Mark Interrupt if Time Mark =.." newline bitfld.long 0x14 5. "RTIE,Register Time Mark Interrupt Pulse Enable" "0: Register Time Mark Interrupt output disabled,1: Register Time Mark Interrupt output enabled" bitfld.long 0x14 3.--4. "SWS,Stop Watch Source" "0: Stop Watch disabled,1: Actual value of cycle time is copied to TTCPT[SWV],2: Actual value of local time is copied to TTCPT[SWV],3: Actual value of global time is copied to.." newline bitfld.long 0x14 2. "SWP,Stop Watch Polarity" "0: Rising edge trigger,1: Falling edge trigger" bitfld.long 0x14 1. "ECS,External Clock Synchronization" "0,1" newline bitfld.long 0x14 0. "SGT,Set Global time" "0,1" line.long 0x18 "TTGTP,TT Global Time Preset Register" hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle Time Target Phase" hexmask.long.word 0x18 0.--15. 1. "TP,Time Preset" line.long 0x1C "TTTMK,TT Time Mark Register" bitfld.long 0x1C 31. "LCKM,TT Time Mark Register Locked" "0: Write access to TTTMK enabled,1: Write access to TTTMK locked" hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time Mark Cycle Code" newline hexmask.long.word 0x1C 0.--15. 1. "TM,Time Mark" line.long 0x20 "TTIR,TT Interrupt Register" bitfld.long 0x20 18. "CER,Configuration Error" "0: No error found in trigger list,1: Error found in trigger list" bitfld.long 0x20 17. "AW,Application Watchdog" "0: Application watchdog served in time,1: Application watchdog not served in time" newline bitfld.long 0x20 16. "WT,Watch Trigger" "0: No missing Reference message,1: Missing Reference message (Level 0: cycle time.." bitfld.long 0x20 15. "IWT,Initialization Watch Trigger" "0: No missing Reference message during system startup,1: No system startup due to missing Reference message" newline bitfld.long 0x20 14. "ELC,Error Level Changed" "0: No change in error level,1: Error level changed" bitfld.long 0x20 13. "SE2,Scheduling Error 2" "0: No scheduling error 2,1: Scheduling error 2 occurred" newline bitfld.long 0x20 12. "SE1,Scheduling Error 1" "0: No scheduling error 1,1: Scheduling error 1 occurred" bitfld.long 0x20 11. "TXO,Tx Count Overflow" "0: Number of Tx Trigger as expected,1: More Tx trigger than expected in one cycle" newline bitfld.long 0x20 10. "TXU,Tx Count Underflow" "0: Number of Tx Trigger as expected,1: Less Tx trigger than expected in one cycle" bitfld.long 0x20 9. "GTE,Global Time Error" "0: Synchronization deviation within limit,1: Synchronization deviation exceeded limit" newline bitfld.long 0x20 8. "GTD,Global Time Discontinuity" "0: No discontinuity of global time,1: Discontinuity of global time" bitfld.long 0x20 7. "GTW,Global Time Wrap" "0: No global time wrap occurred,1: Global time wrap from 0xFFFF to 0x0000 occurred" newline bitfld.long 0x20 6. "SWE,Stop Watch Event" "0: No rising/falling edge at stop watch trigger pin..,1: Rising/falling edge at stop watch trigger pin.." bitfld.long 0x20 5. "TTMI,Trigger Time Mark Event Internal" "0: Time mark not reached,1: Time mark reached (Level 0: cycle time.." newline bitfld.long 0x20 4. "RTMI,Register Time Mark Interrupt" "0: Time mark not reached,1: Time mark reached" bitfld.long 0x20 3. "SOG,Start of Gap" "0: No reference message seen with Next_is_Gap bit set,1: Reference message with Next_is_Gap bit set.." newline bitfld.long 0x20 2. "CSM,Change of Synchronization Mode" "0: No change in master to slave relation or..,1: Master to slave relation or schedule.." bitfld.long 0x20 1. "SMC,Start of Matrix Cycle" "0: No Matrix Cycle started since bit has been reset,1: Matrix Cycle started" newline bitfld.long 0x20 0. "SBC,Start of Basic Cycle" "0: No Basic Cycle started since bit has been reset,1: Basic Cycle started" line.long 0x24 "TTIE,TT Interrupt Enable Register" bitfld.long 0x24 18. "CERE,Configuration Error Interrupt Enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 17. "AWE,Application Watchdog Interrupt Enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 16. "WTE,Watch Trigger Interrupt Enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 15. "IWTE,Initialization Watch Trigger Interrupt Enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 14. "ELCE,Change Error Level Interrupt Enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 13. "SE2E,Scheduling Error 2 Interrupt Enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 12. "SE1E,Scheduling Error 1 Interrupt Enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 11. "TXOE,Tx Count Overflow Interrupt Enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 10. "TXUE,Tx Count Underflow Interrupt Enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 9. "GTEE,Global Time Error Interrupt Enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 8. "GTDE,Global Time Discontinuity Interrupt Enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 7. "GTWE,Global Time Wrap Interrupt Enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 6. "SWEE,Stop Watch Event Interrupt Enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 5. "TTMIE,Trigger Time Mark Event Internal Enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 4. "RTMIE,Register Time Mark Interrupt Enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 3. "SOGE,Start of Gap Interrupt Enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 2. "CSME,Change of Synchronization Mode Interrupt Enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 1. "SMCE,Start of Matrix Cycle Interrupt Enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 0. "SBCE,Start of Basic Cycle Interrupt Enable" "0: TT interrupt disabled,1: TT interrupt enabled" line.long 0x28 "TTILS,TT Interrupt Line Select Register" bitfld.long 0x28 18. "CERL,Configuration Error Interrupt Line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 17. "AWL,Application Watchdog Interrupt Line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 16. "WTL,Watch Trigger Interrupt Line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 15. "IWTL,Initialization Watch Trigger Interrupt Line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 14. "ELCL,Change Error Level Interrupt Line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 13. "SE2L,Scheduling Error 2 Interrupt Line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 12. "SE1L,Scheduling Error 1 Interrupt Line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 11. "TXOL,Tx Count Overflow Interrupt Line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 10. "TXUL,Tx Count Underflow Interrupt Line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 9. "GTEL,Global Time Error Interrupt Line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 8. "GTDL,Global Time Discontinuity Interrupt Line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 7. "GTWL,Global Time Wrap Interrupt Line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 6. "SWEL,Stop Watch Event Interrupt Line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 5. "TTMIL,Trigger Time Mark Event Internal Line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 4. "RTMIL,Register Time Mark Interrupt Line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 3. "SOGL,Start of Gap Interrupt Line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 2. "CSML,Change of Synchronization Mode Interrupt Line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 1. "SMCL,Start of Matrix Cycle Interrupt Line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 0. "SBCL,Start of Basic Cycle Interrupt Line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" rgroup.long 0x12C++0x17 line.long 0x0 "TTOST,TT Operation Status Register" bitfld.long 0x0 31. "SPL,Schedule Phase Lock" "0: Phase outside range,1: Phase inside range" bitfld.long 0x0 30. "WECS,Wait for External Clock Synchronization" "0: No external clock synchronization pending,1: Node waits for external clock synchronization to.." newline bitfld.long 0x0 29. "AWE,Application Watchdog Event" "0: Application Watchdog served in time,1: Failed to serve Application Watchdog in time" bitfld.long 0x0 28. "WFE,Wait for Event" "0: No Gap announced reset by a Reference Message..,1: Reference Message with Next_is_Gap = 1 received" newline bitfld.long 0x0 27. "GSI,Gap Started Indicator" "0: No Gap in schedule reset by each reference..,1: Gap time after Basic Cycle has started" bitfld.long 0x0 24.--26. "TMP,Time Master Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GFI,Gap Finished Indicator" "0: Reset at the end of each reference message,1: Gap finished by M_TTCAN" bitfld.long 0x0 22. "WGTD,Wait for Global Time Discontinuity" "0: No global time preset pending,1: Node waits for the global time preset to take.." newline hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference Trigger Offset" bitfld.long 0x0 7. "QCS,Quality of Clock Speed" "0: Local clock speed not synchronized to Time..,1: Synchronization Deviation SDL" newline bitfld.long 0x0 6. "QGTP,Quality of Global Time Phase" "0: Global time not valid,1: Global time in phase with Time Master" bitfld.long 0x0 4.--5. "SYS,Synchronization State" "0: Out of Synchronization,1: Synchronizing to M_TTCAN communication,2: Schedule suspended by Gap (In_Gap),3: Synchronized to schedule (In_Schedule)" newline bitfld.long 0x0 2.--3. "MS,Master State" "0: Master_Off no master properties relevant,1: Operating as Time Slave,2: Operating as Backup Time Master,3: Operating as current Time Master" bitfld.long 0x0 0.--1. "EL,Error Level" "0: Severity 0: No Error,1: Severity 1: Warning,2: Severity 2: Error,3: Severity 3: Severe Error" line.long 0x4 "TURNA,TUR Numerator Actual Register" hexmask.long.tbyte 0x4 0.--17. 1. "NAV,Numerator Actual Value" line.long 0x8 "TTLGT,TT Local and Global Time Register" hexmask.long.word 0x8 16.--31. 1. "GT,Global Time" hexmask.long.word 0x8 0.--15. 1. "LT,Local Time" line.long 0xC "TTCTC,TT Cycle Time and Count Register" hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle Count" hexmask.long.word 0xC 0.--15. 1. "CT,Cycle Time" line.long 0x10 "TTCPT,TT Capture Time Register" hexmask.long.word 0x10 16.--31. 1. "SWV,Stop Watch Value" hexmask.long.byte 0x10 0.--5. 1. "CCV,Cycle Count Value" line.long 0x14 "TTCSM,TT Cycle Sync Mark Register" hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle Sync Mark" tree.end tree "CAN_SUB_0_TSU_0" base ad:0x72000000 rgroup.long 0x160++0x7 line.long 0x0 "CREL,Core Release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "TSCFG,Timestamp Configuration register" hexmask.long.byte 0x4 8.--15. 1. "TBPRE,TBPRE" bitfld.long 0x4 2. "SCP,Select Capturing Position" "0: Capture Timestamp at EOF,1: Capture Timestamp at SOF" newline bitfld.long 0x4 1. "TBCS,Timebase Counter Select" "0: Timestamp value captured from internal timebase..,1: : Timestamp value captured from input.." bitfld.long 0x4 0. "TSUE,Timestamp Unit Enable 0" "0: TSU disabled,1: TSU enabled" group.long 0x168++0x3 line.long 0x0 "TSS1,Timestamp Status 1 register" bitfld.long 0x0 31. "TSL15,Timestamp Lost" "0,1" bitfld.long 0x0 30. "TSL14,Timestamp Lost" "0,1" newline bitfld.long 0x0 29. "TSL13,Timestamp Lost" "0,1" bitfld.long 0x0 28. "TSL12,Timestamp Lost" "0,1" newline bitfld.long 0x0 27. "TSL11,Timestamp Lost" "0,1" bitfld.long 0x0 26. "TSL10,Timestamp Lost" "0,1" newline bitfld.long 0x0 25. "TSL9,Timestamp Lost" "0,1" bitfld.long 0x0 24. "TSL8,Timestamp Lost" "0,1" newline bitfld.long 0x0 23. "TSL7,Timestamp Lost" "0,1" bitfld.long 0x0 22. "TSL6,Timestamp Lost" "0,1" newline bitfld.long 0x0 21. "TSL5,Timestamp Lost" "0,1" bitfld.long 0x0 20. "TSL4,Timestamp Lost" "0,1" newline bitfld.long 0x0 19. "TSL3,Timestamp Lost" "0,1" bitfld.long 0x0 18. "TSL2,Timestamp Lost" "0,1" newline bitfld.long 0x0 17. "TSL1,Timestamp Lost" "0,1" bitfld.long 0x0 16. "TSL0,Timestamp Lost" "0,1" newline bitfld.long 0x0 15. "TSN15,Timestamp New" "0,1" bitfld.long 0x0 14. "TSN14,Timestamp New" "0,1" newline bitfld.long 0x0 13. "TSN13,Timestamp New" "0,1" bitfld.long 0x0 12. "TSN12,Timestamp New" "0,1" newline bitfld.long 0x0 11. "TSN11,Timestamp New" "0,1" bitfld.long 0x0 10. "TSN10,Timestamp New" "0,1" newline bitfld.long 0x0 9. "TSN9,Timestamp New" "0,1" bitfld.long 0x0 8. "TSN8,Timestamp New" "0,1" newline bitfld.long 0x0 7. "TSN7,Timestamp New" "0,1" bitfld.long 0x0 6. "TSN6,Timestamp New" "0,1" newline bitfld.long 0x0 5. "TSN5,Timestamp New" "0,1" bitfld.long 0x0 4. "TSN4,Timestamp New" "0,1" newline bitfld.long 0x0 3. "TSN3,Timestamp New" "0,1" bitfld.long 0x0 2. "TSN2,Timestamp New" "0,1" newline bitfld.long 0x0 1. "TSN1,Timestamp New" "0,1" bitfld.long 0x0 0. "TSN0,Timestamp New" "0,1" rgroup.long 0x16C++0x43 line.long 0x0 "TSS2,Timestamp Status 2 register" bitfld.long 0x0 14.--15. "ITBG,Internal Timebase and SOF select Generic" "0: no SOF option no internal timebase,1: no SOF option internal timebase (default),2: SOF option no internal timebase,3: SOF option internal timebase" bitfld.long 0x0 12.--13. "NTSG,Number of Timestamps Generic" "0: 4 timestamp registers TS0-TS3,1: 8 timestamp registers TS0-TS7 (default),2: 16 timestamp registers TS0-TS15,3: not a valid value" newline hexmask.long.byte 0x0 0.--3. 1. "TSP,Timestamp Pointer" line.long 0x4 "TS0,Timestamp 0 register" hexmask.long 0x4 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x8 "TS1,Timestamp 1 register" hexmask.long 0x8 0.--31. 1. "TS,Timestamp Word TSn" line.long 0xC "TS2,Timestamp 2 register" hexmask.long 0xC 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x10 "TS3,Timestamp 3 register" hexmask.long 0x10 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x14 "TS4,Timestamp 4 register" hexmask.long 0x14 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x18 "TS5,Timestamp 5 register" hexmask.long 0x18 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x1C "TS6,Timestamp 6 register" hexmask.long 0x1C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x20 "TS7,Timestamp 7 register" hexmask.long 0x20 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x24 "TS8,Timestamp 8 register" hexmask.long 0x24 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x28 "TS9,Timestamp 9 register" hexmask.long 0x28 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x2C "TS10,Timestamp 10 register" hexmask.long 0x2C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x30 "TS11,Timestamp 11 register" hexmask.long 0x30 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x34 "TS12,Timestamp 12 register" hexmask.long 0x34 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x38 "TS13,Timestamp 13 register" hexmask.long 0x38 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x3C "TS14,Timestamp 14 register" hexmask.long 0x3C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x40 "TS15,Timestamp 15 register" hexmask.long 0x40 0.--31. 1. "TS,Timestamp Word TSn" group.long 0x1B0++0x3 line.long 0x0 "ATB,Actual Timebase" hexmask.long 0x0 0.--31. 1. "TB,Timebase for timestamp generation" tree.end tree "CAN_SUB_0_TSU_1" base ad:0x72004000 rgroup.long 0x160++0x7 line.long 0x0 "CREL,Core Release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "TSCFG,Timestamp Configuration register" hexmask.long.byte 0x4 8.--15. 1. "TBPRE,TBPRE" bitfld.long 0x4 2. "SCP,Select Capturing Position" "0: Capture Timestamp at EOF,1: Capture Timestamp at SOF" newline bitfld.long 0x4 1. "TBCS,Timebase Counter Select" "0: Timestamp value captured from internal timebase..,1: : Timestamp value captured from input.." bitfld.long 0x4 0. "TSUE,Timestamp Unit Enable 0" "0: TSU disabled,1: TSU enabled" group.long 0x168++0x3 line.long 0x0 "TSS1,Timestamp Status 1 register" bitfld.long 0x0 31. "TSL15,Timestamp Lost" "0,1" bitfld.long 0x0 30. "TSL14,Timestamp Lost" "0,1" newline bitfld.long 0x0 29. "TSL13,Timestamp Lost" "0,1" bitfld.long 0x0 28. "TSL12,Timestamp Lost" "0,1" newline bitfld.long 0x0 27. "TSL11,Timestamp Lost" "0,1" bitfld.long 0x0 26. "TSL10,Timestamp Lost" "0,1" newline bitfld.long 0x0 25. "TSL9,Timestamp Lost" "0,1" bitfld.long 0x0 24. "TSL8,Timestamp Lost" "0,1" newline bitfld.long 0x0 23. "TSL7,Timestamp Lost" "0,1" bitfld.long 0x0 22. "TSL6,Timestamp Lost" "0,1" newline bitfld.long 0x0 21. "TSL5,Timestamp Lost" "0,1" bitfld.long 0x0 20. "TSL4,Timestamp Lost" "0,1" newline bitfld.long 0x0 19. "TSL3,Timestamp Lost" "0,1" bitfld.long 0x0 18. "TSL2,Timestamp Lost" "0,1" newline bitfld.long 0x0 17. "TSL1,Timestamp Lost" "0,1" bitfld.long 0x0 16. "TSL0,Timestamp Lost" "0,1" newline bitfld.long 0x0 15. "TSN15,Timestamp New" "0,1" bitfld.long 0x0 14. "TSN14,Timestamp New" "0,1" newline bitfld.long 0x0 13. "TSN13,Timestamp New" "0,1" bitfld.long 0x0 12. "TSN12,Timestamp New" "0,1" newline bitfld.long 0x0 11. "TSN11,Timestamp New" "0,1" bitfld.long 0x0 10. "TSN10,Timestamp New" "0,1" newline bitfld.long 0x0 9. "TSN9,Timestamp New" "0,1" bitfld.long 0x0 8. "TSN8,Timestamp New" "0,1" newline bitfld.long 0x0 7. "TSN7,Timestamp New" "0,1" bitfld.long 0x0 6. "TSN6,Timestamp New" "0,1" newline bitfld.long 0x0 5. "TSN5,Timestamp New" "0,1" bitfld.long 0x0 4. "TSN4,Timestamp New" "0,1" newline bitfld.long 0x0 3. "TSN3,Timestamp New" "0,1" bitfld.long 0x0 2. "TSN2,Timestamp New" "0,1" newline bitfld.long 0x0 1. "TSN1,Timestamp New" "0,1" bitfld.long 0x0 0. "TSN0,Timestamp New" "0,1" rgroup.long 0x16C++0x43 line.long 0x0 "TSS2,Timestamp Status 2 register" bitfld.long 0x0 14.--15. "ITBG,Internal Timebase and SOF select Generic" "0: no SOF option no internal timebase,1: no SOF option internal timebase (default),2: SOF option no internal timebase,3: SOF option internal timebase" bitfld.long 0x0 12.--13. "NTSG,Number of Timestamps Generic" "0: 4 timestamp registers TS0-TS3,1: 8 timestamp registers TS0-TS7 (default),2: 16 timestamp registers TS0-TS15,3: not a valid value" newline hexmask.long.byte 0x0 0.--3. 1. "TSP,Timestamp Pointer" line.long 0x4 "TS0,Timestamp 0 register" hexmask.long 0x4 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x8 "TS1,Timestamp 1 register" hexmask.long 0x8 0.--31. 1. "TS,Timestamp Word TSn" line.long 0xC "TS2,Timestamp 2 register" hexmask.long 0xC 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x10 "TS3,Timestamp 3 register" hexmask.long 0x10 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x14 "TS4,Timestamp 4 register" hexmask.long 0x14 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x18 "TS5,Timestamp 5 register" hexmask.long 0x18 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x1C "TS6,Timestamp 6 register" hexmask.long 0x1C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x20 "TS7,Timestamp 7 register" hexmask.long 0x20 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x24 "TS8,Timestamp 8 register" hexmask.long 0x24 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x28 "TS9,Timestamp 9 register" hexmask.long 0x28 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x2C "TS10,Timestamp 10 register" hexmask.long 0x2C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x30 "TS11,Timestamp 11 register" hexmask.long 0x30 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x34 "TS12,Timestamp 12 register" hexmask.long 0x34 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x38 "TS13,Timestamp 13 register" hexmask.long 0x38 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x3C "TS14,Timestamp 14 register" hexmask.long 0x3C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x40 "TS15,Timestamp 15 register" hexmask.long 0x40 0.--31. 1. "TS,Timestamp Word TSn" group.long 0x1B0++0x3 line.long 0x0 "ATB,Actual Timebase" hexmask.long 0x0 0.--31. 1. "TB,Timebase for timestamp generation" tree.end tree "CAN_SUB_0_TSU_2" base ad:0x72008000 rgroup.long 0x160++0x7 line.long 0x0 "CREL,Core Release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "TSCFG,Timestamp Configuration register" hexmask.long.byte 0x4 8.--15. 1. "TBPRE,TBPRE" bitfld.long 0x4 2. "SCP,Select Capturing Position" "0: Capture Timestamp at EOF,1: Capture Timestamp at SOF" newline bitfld.long 0x4 1. "TBCS,Timebase Counter Select" "0: Timestamp value captured from internal timebase..,1: : Timestamp value captured from input.." bitfld.long 0x4 0. "TSUE,Timestamp Unit Enable 0" "0: TSU disabled,1: TSU enabled" group.long 0x168++0x3 line.long 0x0 "TSS1,Timestamp Status 1 register" bitfld.long 0x0 31. "TSL15,Timestamp Lost" "0,1" bitfld.long 0x0 30. "TSL14,Timestamp Lost" "0,1" newline bitfld.long 0x0 29. "TSL13,Timestamp Lost" "0,1" bitfld.long 0x0 28. "TSL12,Timestamp Lost" "0,1" newline bitfld.long 0x0 27. "TSL11,Timestamp Lost" "0,1" bitfld.long 0x0 26. "TSL10,Timestamp Lost" "0,1" newline bitfld.long 0x0 25. "TSL9,Timestamp Lost" "0,1" bitfld.long 0x0 24. "TSL8,Timestamp Lost" "0,1" newline bitfld.long 0x0 23. "TSL7,Timestamp Lost" "0,1" bitfld.long 0x0 22. "TSL6,Timestamp Lost" "0,1" newline bitfld.long 0x0 21. "TSL5,Timestamp Lost" "0,1" bitfld.long 0x0 20. "TSL4,Timestamp Lost" "0,1" newline bitfld.long 0x0 19. "TSL3,Timestamp Lost" "0,1" bitfld.long 0x0 18. "TSL2,Timestamp Lost" "0,1" newline bitfld.long 0x0 17. "TSL1,Timestamp Lost" "0,1" bitfld.long 0x0 16. "TSL0,Timestamp Lost" "0,1" newline bitfld.long 0x0 15. "TSN15,Timestamp New" "0,1" bitfld.long 0x0 14. "TSN14,Timestamp New" "0,1" newline bitfld.long 0x0 13. "TSN13,Timestamp New" "0,1" bitfld.long 0x0 12. "TSN12,Timestamp New" "0,1" newline bitfld.long 0x0 11. "TSN11,Timestamp New" "0,1" bitfld.long 0x0 10. "TSN10,Timestamp New" "0,1" newline bitfld.long 0x0 9. "TSN9,Timestamp New" "0,1" bitfld.long 0x0 8. "TSN8,Timestamp New" "0,1" newline bitfld.long 0x0 7. "TSN7,Timestamp New" "0,1" bitfld.long 0x0 6. "TSN6,Timestamp New" "0,1" newline bitfld.long 0x0 5. "TSN5,Timestamp New" "0,1" bitfld.long 0x0 4. "TSN4,Timestamp New" "0,1" newline bitfld.long 0x0 3. "TSN3,Timestamp New" "0,1" bitfld.long 0x0 2. "TSN2,Timestamp New" "0,1" newline bitfld.long 0x0 1. "TSN1,Timestamp New" "0,1" bitfld.long 0x0 0. "TSN0,Timestamp New" "0,1" rgroup.long 0x16C++0x43 line.long 0x0 "TSS2,Timestamp Status 2 register" bitfld.long 0x0 14.--15. "ITBG,Internal Timebase and SOF select Generic" "0: no SOF option no internal timebase,1: no SOF option internal timebase (default),2: SOF option no internal timebase,3: SOF option internal timebase" bitfld.long 0x0 12.--13. "NTSG,Number of Timestamps Generic" "0: 4 timestamp registers TS0-TS3,1: 8 timestamp registers TS0-TS7 (default),2: 16 timestamp registers TS0-TS15,3: not a valid value" newline hexmask.long.byte 0x0 0.--3. 1. "TSP,Timestamp Pointer" line.long 0x4 "TS0,Timestamp 0 register" hexmask.long 0x4 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x8 "TS1,Timestamp 1 register" hexmask.long 0x8 0.--31. 1. "TS,Timestamp Word TSn" line.long 0xC "TS2,Timestamp 2 register" hexmask.long 0xC 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x10 "TS3,Timestamp 3 register" hexmask.long 0x10 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x14 "TS4,Timestamp 4 register" hexmask.long 0x14 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x18 "TS5,Timestamp 5 register" hexmask.long 0x18 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x1C "TS6,Timestamp 6 register" hexmask.long 0x1C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x20 "TS7,Timestamp 7 register" hexmask.long 0x20 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x24 "TS8,Timestamp 8 register" hexmask.long 0x24 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x28 "TS9,Timestamp 9 register" hexmask.long 0x28 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x2C "TS10,Timestamp 10 register" hexmask.long 0x2C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x30 "TS11,Timestamp 11 register" hexmask.long 0x30 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x34 "TS12,Timestamp 12 register" hexmask.long 0x34 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x38 "TS13,Timestamp 13 register" hexmask.long 0x38 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x3C "TS14,Timestamp 14 register" hexmask.long 0x3C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x40 "TS15,Timestamp 15 register" hexmask.long 0x40 0.--31. 1. "TS,Timestamp Word TSn" group.long 0x1B0++0x3 line.long 0x0 "ATB,Actual Timebase" hexmask.long 0x0 0.--31. 1. "TB,Timebase for timestamp generation" tree.end tree "CAN_SUB_0_TSU_3" base ad:0x7200C000 rgroup.long 0x160++0x7 line.long 0x0 "CREL,Core Release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "TSCFG,Timestamp Configuration register" hexmask.long.byte 0x4 8.--15. 1. "TBPRE,TBPRE" bitfld.long 0x4 2. "SCP,Select Capturing Position" "0: Capture Timestamp at EOF,1: Capture Timestamp at SOF" newline bitfld.long 0x4 1. "TBCS,Timebase Counter Select" "0: Timestamp value captured from internal timebase..,1: : Timestamp value captured from input.." bitfld.long 0x4 0. "TSUE,Timestamp Unit Enable 0" "0: TSU disabled,1: TSU enabled" group.long 0x168++0x3 line.long 0x0 "TSS1,Timestamp Status 1 register" bitfld.long 0x0 31. "TSL15,Timestamp Lost" "0,1" bitfld.long 0x0 30. "TSL14,Timestamp Lost" "0,1" newline bitfld.long 0x0 29. "TSL13,Timestamp Lost" "0,1" bitfld.long 0x0 28. "TSL12,Timestamp Lost" "0,1" newline bitfld.long 0x0 27. "TSL11,Timestamp Lost" "0,1" bitfld.long 0x0 26. "TSL10,Timestamp Lost" "0,1" newline bitfld.long 0x0 25. "TSL9,Timestamp Lost" "0,1" bitfld.long 0x0 24. "TSL8,Timestamp Lost" "0,1" newline bitfld.long 0x0 23. "TSL7,Timestamp Lost" "0,1" bitfld.long 0x0 22. "TSL6,Timestamp Lost" "0,1" newline bitfld.long 0x0 21. "TSL5,Timestamp Lost" "0,1" bitfld.long 0x0 20. "TSL4,Timestamp Lost" "0,1" newline bitfld.long 0x0 19. "TSL3,Timestamp Lost" "0,1" bitfld.long 0x0 18. "TSL2,Timestamp Lost" "0,1" newline bitfld.long 0x0 17. "TSL1,Timestamp Lost" "0,1" bitfld.long 0x0 16. "TSL0,Timestamp Lost" "0,1" newline bitfld.long 0x0 15. "TSN15,Timestamp New" "0,1" bitfld.long 0x0 14. "TSN14,Timestamp New" "0,1" newline bitfld.long 0x0 13. "TSN13,Timestamp New" "0,1" bitfld.long 0x0 12. "TSN12,Timestamp New" "0,1" newline bitfld.long 0x0 11. "TSN11,Timestamp New" "0,1" bitfld.long 0x0 10. "TSN10,Timestamp New" "0,1" newline bitfld.long 0x0 9. "TSN9,Timestamp New" "0,1" bitfld.long 0x0 8. "TSN8,Timestamp New" "0,1" newline bitfld.long 0x0 7. "TSN7,Timestamp New" "0,1" bitfld.long 0x0 6. "TSN6,Timestamp New" "0,1" newline bitfld.long 0x0 5. "TSN5,Timestamp New" "0,1" bitfld.long 0x0 4. "TSN4,Timestamp New" "0,1" newline bitfld.long 0x0 3. "TSN3,Timestamp New" "0,1" bitfld.long 0x0 2. "TSN2,Timestamp New" "0,1" newline bitfld.long 0x0 1. "TSN1,Timestamp New" "0,1" bitfld.long 0x0 0. "TSN0,Timestamp New" "0,1" rgroup.long 0x16C++0x43 line.long 0x0 "TSS2,Timestamp Status 2 register" bitfld.long 0x0 14.--15. "ITBG,Internal Timebase and SOF select Generic" "0: no SOF option no internal timebase,1: no SOF option internal timebase (default),2: SOF option no internal timebase,3: SOF option internal timebase" bitfld.long 0x0 12.--13. "NTSG,Number of Timestamps Generic" "0: 4 timestamp registers TS0-TS3,1: 8 timestamp registers TS0-TS7 (default),2: 16 timestamp registers TS0-TS15,3: not a valid value" newline hexmask.long.byte 0x0 0.--3. 1. "TSP,Timestamp Pointer" line.long 0x4 "TS0,Timestamp 0 register" hexmask.long 0x4 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x8 "TS1,Timestamp 1 register" hexmask.long 0x8 0.--31. 1. "TS,Timestamp Word TSn" line.long 0xC "TS2,Timestamp 2 register" hexmask.long 0xC 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x10 "TS3,Timestamp 3 register" hexmask.long 0x10 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x14 "TS4,Timestamp 4 register" hexmask.long 0x14 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x18 "TS5,Timestamp 5 register" hexmask.long 0x18 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x1C "TS6,Timestamp 6 register" hexmask.long 0x1C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x20 "TS7,Timestamp 7 register" hexmask.long 0x20 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x24 "TS8,Timestamp 8 register" hexmask.long 0x24 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x28 "TS9,Timestamp 9 register" hexmask.long 0x28 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x2C "TS10,Timestamp 10 register" hexmask.long 0x2C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x30 "TS11,Timestamp 11 register" hexmask.long 0x30 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x34 "TS12,Timestamp 12 register" hexmask.long 0x34 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x38 "TS13,Timestamp 13 register" hexmask.long 0x38 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x3C "TS14,Timestamp 14 register" hexmask.long 0x3C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x40 "TS15,Timestamp 15 register" hexmask.long 0x40 0.--31. 1. "TS,Timestamp Word TSn" group.long 0x1B0++0x3 line.long 0x0 "ATB,Actual Timebase" hexmask.long 0x0 0.--31. 1. "TB,Timebase for timestamp generation" tree.end tree.end tree "CAN_SUB_1" tree "CAN_SUB_1_DMU_1" base ad:0x70804000 rgroup.long 0x3C0++0x3 line.long 0x0 "DMUCR,DMU Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" group.long 0x3C4++0x13 line.long 0x0 "DMUI,DMU Internals register" bitfld.long 0x0 31. "TXE,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 30. "RX1,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 29. "RX0,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 28. "TX,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 24.--26. "EHS,Element Handler State" "0: wait for bit M_CAN:CCCR.CCE getting zero,1: wait for Start Address,2: wait for Trigger Address,3: wait for transfer of Element word,4: acknowledge to M_CAN,5: exception recovery,?,?" bitfld.long 0x0 23. "DTXE,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 22. "DTX1,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 21. "DTX0,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 20. "DTX,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 16.--18. "DEHS,Detect Element Handler State" "?,?,?,?,?,?,?,7: unused state" newline bitfld.long 0x0 15. "ENA,DMU is enabled" "0: DMU is disabled,1: DMU is enabled and can process DMA data" hexmask.long.byte 0x0 8.--12. 1. "TFQPIP,TX FIFO/Queue Put Index Previous" newline bitfld.long 0x0 3. "TXER,TX Event Service Request line of DMU" "0: No TX Event DMA service requested,1: TX Event DMA Service requested" bitfld.long 0x0 2. "RX1R,RX1 Service Request line of DMU" "0: No RX1 DMA service requested,1: RX1 DMA Service requested" newline bitfld.long 0x0 1. "RX0R,RX0 Service Request line of DMU" "0: No RX0 DMA service requested,1: RX0 DMA Service requested" bitfld.long 0x0 0. "TXR,TX Service Request line of DMU" "0: No TX DMA service requested,1: TX DMA Service requested" line.long 0x4 "DMUQC,DMU Queuing Counter register" hexmask.long.byte 0x4 24.--31. 1. "TXEEDC,TX Event Element Dequeuing Counter" hexmask.long.byte 0x4 16.--23. 1. "RX1EDC,RX1 Element Dequeuing Counter" newline hexmask.long.byte 0x4 8.--15. 1. "RX0EDC,RX0 Element Dequeuing Counter" hexmask.long.byte 0x4 0.--7. 1. "TXEEC,TX Element Enqueuing Counter" line.long 0x8 "DMUIR,DMU Interrupt Register" bitfld.long 0x8 30. "IAC,Illegal Access while in Configuration mode" "0: No Illegal Access while CCE mode,1: Illegal Access while CCE mode" bitfld.long 0x8 29. "DT,Debug Trigger" "0: Debug point not reached,1: Debug point reached" newline bitfld.long 0x8 28. "TXEED,TX Event Element Dequeued" "0: No TX Event Element dequeued,1: TX Event Element successfully dequeued" bitfld.long 0x8 27. "TXEEIW,TX Event Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU TX Event Element.." newline bitfld.long 0x8 26. "TXEEIAS,TX Event Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 25. "TXEEID,TX Event Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 24. "TXEENSA,TX Event Element Not Start Address" "0: No illegal read access,1: Read from TX Event Element begins without using.." bitfld.long 0x8 21. "RX1EIO,RX1 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 20. "RX1ED,RX1 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 19. "RX1EIW,RX1 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 18. "RX1EIAS,RX1 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 17. "RX1EID,RX1 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 16. "RX1ENSA,RX1 Element Not Start Address" "0: No illegal read access,1: Read from RX1 Element begins without using start.." bitfld.long 0x8 15. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Uncorrected bit error detected" newline bitfld.long 0x8 14. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected" bitfld.long 0x8 13. "RX0EIO,RX0 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 12. "RX0ED,RX0 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 11. "RX0EIW,RX0 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 10. "RX0EIAS,RX0 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 9. "RX0EID,RX0 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 8. "RX0ENSA,RX0 Element Not Start Address" "0: No illegal read access,1: Read from RX0 Element begins without using start.." bitfld.long 0x8 6. "TXEE,TX Element Enqueued" "0: No Tx message enqueued,1: Tx message successfully enqueued" newline bitfld.long 0x8 5. "TXEIR,TX Element Illegal Read" "0: No read access,1: Illegal read access to DMU TX Element section.." bitfld.long 0x8 4. "TXEWATA,TX Element Write After Trigger Address" "0: No write after Trigger Address,1: Enqueue a message" newline bitfld.long 0x8 3. "TXEIDLC,TX Element Illegal DLC" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." bitfld.long 0x8 2. "TXEIAS,TX Element Illegal Access Sequence" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." newline bitfld.long 0x8 1. "TXEIE,TX Element Illegal Enqueuing" "0: No illegal enqueuing,1: Start of enqueuing without request detected.." bitfld.long 0x8 0. "TXENSA,TX Element Not Start Address" "0: No illegal write access,1: Write to TX Element begins without using start.." line.long 0xC "DMUIE,DMU Interrupt Enable register" bitfld.long 0xC 30. "IACE,Illegal Access while in Configuration mode Enable" "0: Flag DMUIR.IAC does not activate the interrupt..,1: If DMUIR.IAC = 1 the interrupt line dmu_int will.." bitfld.long 0xC 29. "DTE,Debug Trigger Enable" "0: Flag DMUIR.DT does not activate the interrupt..,1: If DMUIR.DT = 1 the interrupt line dmu_int will.." newline bitfld.long 0xC 28. "TXEEDE,TX Event Element Dequeued" "0: Flag DMUIR.TXEED does not activate the interrupt..,1: If DMUIR.TXEED = 1 the interrupt line dmu_int.." bitfld.long 0xC 27. "TXEEIWE,TX Event Element Illegal Write" "0: Flag DMUIR.TXEEIW does not activate the..,1: If DMUIR.TXEEIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 26. "TXEEIASE,TX Event Element Illegal Access Sequence" "0: Flag DMUIR.TXEEIAS does not activate the..,1: If DMUIR.TXEEIAS = 1 the interrupt line dmu_int.." bitfld.long 0xC 25. "TXEEIDE,TX Event Element Illegal Dequeuing" "0: Flag DMUIR.TXEEID does not activate the..,1: If DMUIR.TXEEID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 24. "TXEENSAE,TX Event Element Not Start Address" "0: Flag TXEENSA.TXEENSA does not activate the..,1: If TXEENSA.TXEENSA = 1 the interrupt line.." bitfld.long 0xC 21. "RX1EIOE,RX1 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX1EIO does not activate the..,1: If TXEENSA.RX1EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 20. "RX1EDE,RX1 Element Dequeued Enable" "0: Flag TXEENSA.RX1ED does not activate the..,1: If TXEENSA.RX1ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 19. "RX1EIWE,RX1 Element Illegal Write Enable" "0: Flag TXEENSA.RX1EIW does not activate the..,1: If TXEENSA.RX1EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 18. "RX1EIASE,RX1 Element Illegal Access Sequence Enable" "0: Flag TXEENSA.RX1EIAS does not activate the..,1: If TXEENSA.RX1EIAS = 1 the interrupt line.." bitfld.long 0xC 17. "RX1EIDE,RX1 Element Illegal Dequeuing Enable" "0: Flag TXEENSA.RX1EID does not activate the..,1: If TXEENSA.RX1EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 16. "RX1ENSAE,RX1 Element Not Start Address Enable" "0: Flag TXEENSA.RX1ENSA does not activate the..,1: If TXEENSA.RX1ENSA = 1 the interrupt line.." bitfld.long 0xC 15. "BEUE,Bit Error Uncorrected Enable" "0: Flag TXEENSA.BEU does not activate the interrupt..,1: If TXEENSA.BEU = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 14. "BECE,Bit Error Corrected Enable" "0: Flag TXEENSA.BEC does not activate the interrupt..,1: If TXEENSA.BEC = 1 the interrupt line dmu_int.." bitfld.long 0xC 13. "RX0EIOE,RX0 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX0EIO does not activate the..,1: If TXEENSA.RX0EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 12. "RX0EDE,RX0 Element Dequeued Enabled" "0: Flag TXEENSA.RX0ED does not activate the..,1: If TXEENSA.RX0ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 11. "RX0EIWE,RX0 Element Illegal Write Enabled" "0: Flag TXEENSA.RX0EIW does not activate the..,1: If TXEENSA.RX0EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 10. "RX0EIASE,RX0 Element Illegal Access Sequence Enabled" "0: Flag TXEENSA.RX0EIAS does not activate the..,1: If TXEENSA.RX0EIAS = 1 the interrupt line.." bitfld.long 0xC 9. "RX0EIDE,RX0 Element Illegal Dequeuing Enabled" "0: Flag TXEENSA.RX0EID does not activate the..,1: If TXEENSA.RX0EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 8. "RX0ENSAE,RX0 Element Not Start Address Enabled" "0: Flag TXEENSA.RX0ENSA does not activate the..,1: If TXEENSA.RX0ENSA = 1 the interrupt line.." bitfld.long 0xC 6. "TXEEE,TX Element Enqueued Enable" "0: Flag TXEENSA.TXEE does not activate the..,1: If TXEENSA.TXEE = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 5. "TXEIRE,TX Element Illegal Read Enable" "0: Flag TXEENSA.TXEIR does not activate the..,1: If TXEENSA.TXEIR = 1 the interrupt line dmu_int.." bitfld.long 0xC 4. "TXEWATAE,TX Element Write After Trigger Address Enable" "0: Flag TXEENSA.TXEWATA does not activate the..,1: If TXEENSA.TXEWATA = 1 the interrupt line.." newline bitfld.long 0xC 3. "TXEIDLCE,TX Element Illegal DLC Enable" "0: Flag TXEENSA.TXEIDLC does not activate the..,1: If TXEENSA.TXEIDLC = 1 the interrupt line.." bitfld.long 0xC 2. "TXEIASE,TX Element Illegal Access Sequence Enable" "0: Flag TXEENSA.TXEIAS does not activate the..,1: If TXEENSA.TXEIAS = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 1. "TXEIEE,TX Element Illegal Enqueuing Enable" "0: Flag TXEENSA.TXEIE does not activate the..,1: If TXEENSA.TXEIE = 1 the interrupt line dmu_int.." bitfld.long 0xC 0. "TXENSAE,TX Element Not Start Address Enable" "0: Flag DMUIR.TXENSA does not activate the..,1: If DMUIR.TXENSA = 1 the interrupt line dmu_int.." line.long 0x10 "DMUC,DMU Configuration register" bitfld.long 0x10 0. "TTS,Transfer Timestamp" "0: No timestamp will be transferred via DMU Virtual..,1: Timestamp of message will be transferred from.." tree.end tree "CAN_SUB_1_DMU_2" base ad:0x70808000 rgroup.long 0x3C0++0x3 line.long 0x0 "DMUCR,DMU Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" group.long 0x3C4++0x13 line.long 0x0 "DMUI,DMU Internals register" bitfld.long 0x0 31. "TXE,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 30. "RX1,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 29. "RX0,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 28. "TX,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 24.--26. "EHS,Element Handler State" "0: wait for bit M_CAN:CCCR.CCE getting zero,1: wait for Start Address,2: wait for Trigger Address,3: wait for transfer of Element word,4: acknowledge to M_CAN,5: exception recovery,?,?" bitfld.long 0x0 23. "DTXE,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 22. "DTX1,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 21. "DTX0,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 20. "DTX,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 16.--18. "DEHS,Detect Element Handler State" "?,?,?,?,?,?,?,7: unused state" newline bitfld.long 0x0 15. "ENA,DMU is enabled" "0: DMU is disabled,1: DMU is enabled and can process DMA data" hexmask.long.byte 0x0 8.--12. 1. "TFQPIP,TX FIFO/Queue Put Index Previous" newline bitfld.long 0x0 3. "TXER,TX Event Service Request line of DMU" "0: No TX Event DMA service requested,1: TX Event DMA Service requested" bitfld.long 0x0 2. "RX1R,RX1 Service Request line of DMU" "0: No RX1 DMA service requested,1: RX1 DMA Service requested" newline bitfld.long 0x0 1. "RX0R,RX0 Service Request line of DMU" "0: No RX0 DMA service requested,1: RX0 DMA Service requested" bitfld.long 0x0 0. "TXR,TX Service Request line of DMU" "0: No TX DMA service requested,1: TX DMA Service requested" line.long 0x4 "DMUQC,DMU Queuing Counter register" hexmask.long.byte 0x4 24.--31. 1. "TXEEDC,TX Event Element Dequeuing Counter" hexmask.long.byte 0x4 16.--23. 1. "RX1EDC,RX1 Element Dequeuing Counter" newline hexmask.long.byte 0x4 8.--15. 1. "RX0EDC,RX0 Element Dequeuing Counter" hexmask.long.byte 0x4 0.--7. 1. "TXEEC,TX Element Enqueuing Counter" line.long 0x8 "DMUIR,DMU Interrupt Register" bitfld.long 0x8 30. "IAC,Illegal Access while in Configuration mode" "0: No Illegal Access while CCE mode,1: Illegal Access while CCE mode" bitfld.long 0x8 29. "DT,Debug Trigger" "0: Debug point not reached,1: Debug point reached" newline bitfld.long 0x8 28. "TXEED,TX Event Element Dequeued" "0: No TX Event Element dequeued,1: TX Event Element successfully dequeued" bitfld.long 0x8 27. "TXEEIW,TX Event Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU TX Event Element.." newline bitfld.long 0x8 26. "TXEEIAS,TX Event Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 25. "TXEEID,TX Event Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 24. "TXEENSA,TX Event Element Not Start Address" "0: No illegal read access,1: Read from TX Event Element begins without using.." bitfld.long 0x8 21. "RX1EIO,RX1 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 20. "RX1ED,RX1 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 19. "RX1EIW,RX1 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 18. "RX1EIAS,RX1 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 17. "RX1EID,RX1 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 16. "RX1ENSA,RX1 Element Not Start Address" "0: No illegal read access,1: Read from RX1 Element begins without using start.." bitfld.long 0x8 15. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Uncorrected bit error detected" newline bitfld.long 0x8 14. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected" bitfld.long 0x8 13. "RX0EIO,RX0 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 12. "RX0ED,RX0 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 11. "RX0EIW,RX0 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 10. "RX0EIAS,RX0 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 9. "RX0EID,RX0 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 8. "RX0ENSA,RX0 Element Not Start Address" "0: No illegal read access,1: Read from RX0 Element begins without using start.." bitfld.long 0x8 6. "TXEE,TX Element Enqueued" "0: No Tx message enqueued,1: Tx message successfully enqueued" newline bitfld.long 0x8 5. "TXEIR,TX Element Illegal Read" "0: No read access,1: Illegal read access to DMU TX Element section.." bitfld.long 0x8 4. "TXEWATA,TX Element Write After Trigger Address" "0: No write after Trigger Address,1: Enqueue a message" newline bitfld.long 0x8 3. "TXEIDLC,TX Element Illegal DLC" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." bitfld.long 0x8 2. "TXEIAS,TX Element Illegal Access Sequence" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." newline bitfld.long 0x8 1. "TXEIE,TX Element Illegal Enqueuing" "0: No illegal enqueuing,1: Start of enqueuing without request detected.." bitfld.long 0x8 0. "TXENSA,TX Element Not Start Address" "0: No illegal write access,1: Write to TX Element begins without using start.." line.long 0xC "DMUIE,DMU Interrupt Enable register" bitfld.long 0xC 30. "IACE,Illegal Access while in Configuration mode Enable" "0: Flag DMUIR.IAC does not activate the interrupt..,1: If DMUIR.IAC = 1 the interrupt line dmu_int will.." bitfld.long 0xC 29. "DTE,Debug Trigger Enable" "0: Flag DMUIR.DT does not activate the interrupt..,1: If DMUIR.DT = 1 the interrupt line dmu_int will.." newline bitfld.long 0xC 28. "TXEEDE,TX Event Element Dequeued" "0: Flag DMUIR.TXEED does not activate the interrupt..,1: If DMUIR.TXEED = 1 the interrupt line dmu_int.." bitfld.long 0xC 27. "TXEEIWE,TX Event Element Illegal Write" "0: Flag DMUIR.TXEEIW does not activate the..,1: If DMUIR.TXEEIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 26. "TXEEIASE,TX Event Element Illegal Access Sequence" "0: Flag DMUIR.TXEEIAS does not activate the..,1: If DMUIR.TXEEIAS = 1 the interrupt line dmu_int.." bitfld.long 0xC 25. "TXEEIDE,TX Event Element Illegal Dequeuing" "0: Flag DMUIR.TXEEID does not activate the..,1: If DMUIR.TXEEID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 24. "TXEENSAE,TX Event Element Not Start Address" "0: Flag TXEENSA.TXEENSA does not activate the..,1: If TXEENSA.TXEENSA = 1 the interrupt line.." bitfld.long 0xC 21. "RX1EIOE,RX1 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX1EIO does not activate the..,1: If TXEENSA.RX1EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 20. "RX1EDE,RX1 Element Dequeued Enable" "0: Flag TXEENSA.RX1ED does not activate the..,1: If TXEENSA.RX1ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 19. "RX1EIWE,RX1 Element Illegal Write Enable" "0: Flag TXEENSA.RX1EIW does not activate the..,1: If TXEENSA.RX1EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 18. "RX1EIASE,RX1 Element Illegal Access Sequence Enable" "0: Flag TXEENSA.RX1EIAS does not activate the..,1: If TXEENSA.RX1EIAS = 1 the interrupt line.." bitfld.long 0xC 17. "RX1EIDE,RX1 Element Illegal Dequeuing Enable" "0: Flag TXEENSA.RX1EID does not activate the..,1: If TXEENSA.RX1EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 16. "RX1ENSAE,RX1 Element Not Start Address Enable" "0: Flag TXEENSA.RX1ENSA does not activate the..,1: If TXEENSA.RX1ENSA = 1 the interrupt line.." bitfld.long 0xC 15. "BEUE,Bit Error Uncorrected Enable" "0: Flag TXEENSA.BEU does not activate the interrupt..,1: If TXEENSA.BEU = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 14. "BECE,Bit Error Corrected Enable" "0: Flag TXEENSA.BEC does not activate the interrupt..,1: If TXEENSA.BEC = 1 the interrupt line dmu_int.." bitfld.long 0xC 13. "RX0EIOE,RX0 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX0EIO does not activate the..,1: If TXEENSA.RX0EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 12. "RX0EDE,RX0 Element Dequeued Enabled" "0: Flag TXEENSA.RX0ED does not activate the..,1: If TXEENSA.RX0ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 11. "RX0EIWE,RX0 Element Illegal Write Enabled" "0: Flag TXEENSA.RX0EIW does not activate the..,1: If TXEENSA.RX0EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 10. "RX0EIASE,RX0 Element Illegal Access Sequence Enabled" "0: Flag TXEENSA.RX0EIAS does not activate the..,1: If TXEENSA.RX0EIAS = 1 the interrupt line.." bitfld.long 0xC 9. "RX0EIDE,RX0 Element Illegal Dequeuing Enabled" "0: Flag TXEENSA.RX0EID does not activate the..,1: If TXEENSA.RX0EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 8. "RX0ENSAE,RX0 Element Not Start Address Enabled" "0: Flag TXEENSA.RX0ENSA does not activate the..,1: If TXEENSA.RX0ENSA = 1 the interrupt line.." bitfld.long 0xC 6. "TXEEE,TX Element Enqueued Enable" "0: Flag TXEENSA.TXEE does not activate the..,1: If TXEENSA.TXEE = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 5. "TXEIRE,TX Element Illegal Read Enable" "0: Flag TXEENSA.TXEIR does not activate the..,1: If TXEENSA.TXEIR = 1 the interrupt line dmu_int.." bitfld.long 0xC 4. "TXEWATAE,TX Element Write After Trigger Address Enable" "0: Flag TXEENSA.TXEWATA does not activate the..,1: If TXEENSA.TXEWATA = 1 the interrupt line.." newline bitfld.long 0xC 3. "TXEIDLCE,TX Element Illegal DLC Enable" "0: Flag TXEENSA.TXEIDLC does not activate the..,1: If TXEENSA.TXEIDLC = 1 the interrupt line.." bitfld.long 0xC 2. "TXEIASE,TX Element Illegal Access Sequence Enable" "0: Flag TXEENSA.TXEIAS does not activate the..,1: If TXEENSA.TXEIAS = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 1. "TXEIEE,TX Element Illegal Enqueuing Enable" "0: Flag TXEENSA.TXEIE does not activate the..,1: If TXEENSA.TXEIE = 1 the interrupt line dmu_int.." bitfld.long 0xC 0. "TXENSAE,TX Element Not Start Address Enable" "0: Flag DMUIR.TXENSA does not activate the..,1: If DMUIR.TXENSA = 1 the interrupt line dmu_int.." line.long 0x10 "DMUC,DMU Configuration register" bitfld.long 0x10 0. "TTS,Transfer Timestamp" "0: No timestamp will be transferred via DMU Virtual..,1: Timestamp of message will be transferred from.." tree.end tree "CAN_SUB_1_DMU_3" base ad:0x7080C000 rgroup.long 0x3C0++0x3 line.long 0x0 "DMUCR,DMU Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" group.long 0x3C4++0x13 line.long 0x0 "DMUI,DMU Internals register" bitfld.long 0x0 31. "TXE,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 30. "RX1,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 29. "RX0,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 28. "TX,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 24.--26. "EHS,Element Handler State" "0: wait for bit M_CAN:CCCR.CCE getting zero,1: wait for Start Address,2: wait for Trigger Address,3: wait for transfer of Element word,4: acknowledge to M_CAN,5: exception recovery,?,?" bitfld.long 0x0 23. "DTXE,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 22. "DTX1,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 21. "DTX0,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 20. "DTX,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 16.--18. "DEHS,Detect Element Handler State" "?,?,?,?,?,?,?,7: unused state" newline bitfld.long 0x0 15. "ENA,DMU is enabled" "0: DMU is disabled,1: DMU is enabled and can process DMA data" hexmask.long.byte 0x0 8.--12. 1. "TFQPIP,TX FIFO/Queue Put Index Previous" newline bitfld.long 0x0 3. "TXER,TX Event Service Request line of DMU" "0: No TX Event DMA service requested,1: TX Event DMA Service requested" bitfld.long 0x0 2. "RX1R,RX1 Service Request line of DMU" "0: No RX1 DMA service requested,1: RX1 DMA Service requested" newline bitfld.long 0x0 1. "RX0R,RX0 Service Request line of DMU" "0: No RX0 DMA service requested,1: RX0 DMA Service requested" bitfld.long 0x0 0. "TXR,TX Service Request line of DMU" "0: No TX DMA service requested,1: TX DMA Service requested" line.long 0x4 "DMUQC,DMU Queuing Counter register" hexmask.long.byte 0x4 24.--31. 1. "TXEEDC,TX Event Element Dequeuing Counter" hexmask.long.byte 0x4 16.--23. 1. "RX1EDC,RX1 Element Dequeuing Counter" newline hexmask.long.byte 0x4 8.--15. 1. "RX0EDC,RX0 Element Dequeuing Counter" hexmask.long.byte 0x4 0.--7. 1. "TXEEC,TX Element Enqueuing Counter" line.long 0x8 "DMUIR,DMU Interrupt Register" bitfld.long 0x8 30. "IAC,Illegal Access while in Configuration mode" "0: No Illegal Access while CCE mode,1: Illegal Access while CCE mode" bitfld.long 0x8 29. "DT,Debug Trigger" "0: Debug point not reached,1: Debug point reached" newline bitfld.long 0x8 28. "TXEED,TX Event Element Dequeued" "0: No TX Event Element dequeued,1: TX Event Element successfully dequeued" bitfld.long 0x8 27. "TXEEIW,TX Event Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU TX Event Element.." newline bitfld.long 0x8 26. "TXEEIAS,TX Event Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 25. "TXEEID,TX Event Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 24. "TXEENSA,TX Event Element Not Start Address" "0: No illegal read access,1: Read from TX Event Element begins without using.." bitfld.long 0x8 21. "RX1EIO,RX1 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 20. "RX1ED,RX1 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 19. "RX1EIW,RX1 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 18. "RX1EIAS,RX1 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 17. "RX1EID,RX1 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 16. "RX1ENSA,RX1 Element Not Start Address" "0: No illegal read access,1: Read from RX1 Element begins without using start.." bitfld.long 0x8 15. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Uncorrected bit error detected" newline bitfld.long 0x8 14. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected" bitfld.long 0x8 13. "RX0EIO,RX0 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 12. "RX0ED,RX0 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 11. "RX0EIW,RX0 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 10. "RX0EIAS,RX0 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 9. "RX0EID,RX0 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 8. "RX0ENSA,RX0 Element Not Start Address" "0: No illegal read access,1: Read from RX0 Element begins without using start.." bitfld.long 0x8 6. "TXEE,TX Element Enqueued" "0: No Tx message enqueued,1: Tx message successfully enqueued" newline bitfld.long 0x8 5. "TXEIR,TX Element Illegal Read" "0: No read access,1: Illegal read access to DMU TX Element section.." bitfld.long 0x8 4. "TXEWATA,TX Element Write After Trigger Address" "0: No write after Trigger Address,1: Enqueue a message" newline bitfld.long 0x8 3. "TXEIDLC,TX Element Illegal DLC" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." bitfld.long 0x8 2. "TXEIAS,TX Element Illegal Access Sequence" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." newline bitfld.long 0x8 1. "TXEIE,TX Element Illegal Enqueuing" "0: No illegal enqueuing,1: Start of enqueuing without request detected.." bitfld.long 0x8 0. "TXENSA,TX Element Not Start Address" "0: No illegal write access,1: Write to TX Element begins without using start.." line.long 0xC "DMUIE,DMU Interrupt Enable register" bitfld.long 0xC 30. "IACE,Illegal Access while in Configuration mode Enable" "0: Flag DMUIR.IAC does not activate the interrupt..,1: If DMUIR.IAC = 1 the interrupt line dmu_int will.." bitfld.long 0xC 29. "DTE,Debug Trigger Enable" "0: Flag DMUIR.DT does not activate the interrupt..,1: If DMUIR.DT = 1 the interrupt line dmu_int will.." newline bitfld.long 0xC 28. "TXEEDE,TX Event Element Dequeued" "0: Flag DMUIR.TXEED does not activate the interrupt..,1: If DMUIR.TXEED = 1 the interrupt line dmu_int.." bitfld.long 0xC 27. "TXEEIWE,TX Event Element Illegal Write" "0: Flag DMUIR.TXEEIW does not activate the..,1: If DMUIR.TXEEIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 26. "TXEEIASE,TX Event Element Illegal Access Sequence" "0: Flag DMUIR.TXEEIAS does not activate the..,1: If DMUIR.TXEEIAS = 1 the interrupt line dmu_int.." bitfld.long 0xC 25. "TXEEIDE,TX Event Element Illegal Dequeuing" "0: Flag DMUIR.TXEEID does not activate the..,1: If DMUIR.TXEEID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 24. "TXEENSAE,TX Event Element Not Start Address" "0: Flag TXEENSA.TXEENSA does not activate the..,1: If TXEENSA.TXEENSA = 1 the interrupt line.." bitfld.long 0xC 21. "RX1EIOE,RX1 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX1EIO does not activate the..,1: If TXEENSA.RX1EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 20. "RX1EDE,RX1 Element Dequeued Enable" "0: Flag TXEENSA.RX1ED does not activate the..,1: If TXEENSA.RX1ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 19. "RX1EIWE,RX1 Element Illegal Write Enable" "0: Flag TXEENSA.RX1EIW does not activate the..,1: If TXEENSA.RX1EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 18. "RX1EIASE,RX1 Element Illegal Access Sequence Enable" "0: Flag TXEENSA.RX1EIAS does not activate the..,1: If TXEENSA.RX1EIAS = 1 the interrupt line.." bitfld.long 0xC 17. "RX1EIDE,RX1 Element Illegal Dequeuing Enable" "0: Flag TXEENSA.RX1EID does not activate the..,1: If TXEENSA.RX1EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 16. "RX1ENSAE,RX1 Element Not Start Address Enable" "0: Flag TXEENSA.RX1ENSA does not activate the..,1: If TXEENSA.RX1ENSA = 1 the interrupt line.." bitfld.long 0xC 15. "BEUE,Bit Error Uncorrected Enable" "0: Flag TXEENSA.BEU does not activate the interrupt..,1: If TXEENSA.BEU = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 14. "BECE,Bit Error Corrected Enable" "0: Flag TXEENSA.BEC does not activate the interrupt..,1: If TXEENSA.BEC = 1 the interrupt line dmu_int.." bitfld.long 0xC 13. "RX0EIOE,RX0 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX0EIO does not activate the..,1: If TXEENSA.RX0EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 12. "RX0EDE,RX0 Element Dequeued Enabled" "0: Flag TXEENSA.RX0ED does not activate the..,1: If TXEENSA.RX0ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 11. "RX0EIWE,RX0 Element Illegal Write Enabled" "0: Flag TXEENSA.RX0EIW does not activate the..,1: If TXEENSA.RX0EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 10. "RX0EIASE,RX0 Element Illegal Access Sequence Enabled" "0: Flag TXEENSA.RX0EIAS does not activate the..,1: If TXEENSA.RX0EIAS = 1 the interrupt line.." bitfld.long 0xC 9. "RX0EIDE,RX0 Element Illegal Dequeuing Enabled" "0: Flag TXEENSA.RX0EID does not activate the..,1: If TXEENSA.RX0EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 8. "RX0ENSAE,RX0 Element Not Start Address Enabled" "0: Flag TXEENSA.RX0ENSA does not activate the..,1: If TXEENSA.RX0ENSA = 1 the interrupt line.." bitfld.long 0xC 6. "TXEEE,TX Element Enqueued Enable" "0: Flag TXEENSA.TXEE does not activate the..,1: If TXEENSA.TXEE = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 5. "TXEIRE,TX Element Illegal Read Enable" "0: Flag TXEENSA.TXEIR does not activate the..,1: If TXEENSA.TXEIR = 1 the interrupt line dmu_int.." bitfld.long 0xC 4. "TXEWATAE,TX Element Write After Trigger Address Enable" "0: Flag TXEENSA.TXEWATA does not activate the..,1: If TXEENSA.TXEWATA = 1 the interrupt line.." newline bitfld.long 0xC 3. "TXEIDLCE,TX Element Illegal DLC Enable" "0: Flag TXEENSA.TXEIDLC does not activate the..,1: If TXEENSA.TXEIDLC = 1 the interrupt line.." bitfld.long 0xC 2. "TXEIASE,TX Element Illegal Access Sequence Enable" "0: Flag TXEENSA.TXEIAS does not activate the..,1: If TXEENSA.TXEIAS = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 1. "TXEIEE,TX Element Illegal Enqueuing Enable" "0: Flag TXEENSA.TXEIE does not activate the..,1: If TXEENSA.TXEIE = 1 the interrupt line dmu_int.." bitfld.long 0xC 0. "TXENSAE,TX Element Not Start Address Enable" "0: Flag DMUIR.TXENSA does not activate the..,1: If DMUIR.TXENSA = 1 the interrupt line dmu_int.." line.long 0x10 "DMUC,DMU Configuration register" bitfld.long 0x10 0. "TTS,Transfer Timestamp" "0: No timestamp will be transferred via DMU Virtual..,1: Timestamp of message will be transferred from.." tree.end tree "CAN_SUB_1_DMU_4" base ad:0x70810000 rgroup.long 0x3C0++0x3 line.long 0x0 "DMUCR,DMU Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" group.long 0x3C4++0x13 line.long 0x0 "DMUI,DMU Internals register" bitfld.long 0x0 31. "TXE,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 30. "RX1,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 29. "RX0,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 28. "TX,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 24.--26. "EHS,Element Handler State" "0: wait for bit M_CAN:CCCR.CCE getting zero,1: wait for Start Address,2: wait for Trigger Address,3: wait for transfer of Element word,4: acknowledge to M_CAN,5: exception recovery,?,?" bitfld.long 0x0 23. "DTXE,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 22. "DTX1,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 21. "DTX0,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 20. "DTX,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 16.--18. "DEHS,Detect Element Handler State" "?,?,?,?,?,?,?,7: unused state" newline bitfld.long 0x0 15. "ENA,DMU is enabled" "0: DMU is disabled,1: DMU is enabled and can process DMA data" hexmask.long.byte 0x0 8.--12. 1. "TFQPIP,TX FIFO/Queue Put Index Previous" newline bitfld.long 0x0 3. "TXER,TX Event Service Request line of DMU" "0: No TX Event DMA service requested,1: TX Event DMA Service requested" bitfld.long 0x0 2. "RX1R,RX1 Service Request line of DMU" "0: No RX1 DMA service requested,1: RX1 DMA Service requested" newline bitfld.long 0x0 1. "RX0R,RX0 Service Request line of DMU" "0: No RX0 DMA service requested,1: RX0 DMA Service requested" bitfld.long 0x0 0. "TXR,TX Service Request line of DMU" "0: No TX DMA service requested,1: TX DMA Service requested" line.long 0x4 "DMUQC,DMU Queuing Counter register" hexmask.long.byte 0x4 24.--31. 1. "TXEEDC,TX Event Element Dequeuing Counter" hexmask.long.byte 0x4 16.--23. 1. "RX1EDC,RX1 Element Dequeuing Counter" newline hexmask.long.byte 0x4 8.--15. 1. "RX0EDC,RX0 Element Dequeuing Counter" hexmask.long.byte 0x4 0.--7. 1. "TXEEC,TX Element Enqueuing Counter" line.long 0x8 "DMUIR,DMU Interrupt Register" bitfld.long 0x8 30. "IAC,Illegal Access while in Configuration mode" "0: No Illegal Access while CCE mode,1: Illegal Access while CCE mode" bitfld.long 0x8 29. "DT,Debug Trigger" "0: Debug point not reached,1: Debug point reached" newline bitfld.long 0x8 28. "TXEED,TX Event Element Dequeued" "0: No TX Event Element dequeued,1: TX Event Element successfully dequeued" bitfld.long 0x8 27. "TXEEIW,TX Event Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU TX Event Element.." newline bitfld.long 0x8 26. "TXEEIAS,TX Event Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 25. "TXEEID,TX Event Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 24. "TXEENSA,TX Event Element Not Start Address" "0: No illegal read access,1: Read from TX Event Element begins without using.." bitfld.long 0x8 21. "RX1EIO,RX1 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 20. "RX1ED,RX1 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 19. "RX1EIW,RX1 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 18. "RX1EIAS,RX1 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 17. "RX1EID,RX1 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 16. "RX1ENSA,RX1 Element Not Start Address" "0: No illegal read access,1: Read from RX1 Element begins without using start.." bitfld.long 0x8 15. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Uncorrected bit error detected" newline bitfld.long 0x8 14. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected" bitfld.long 0x8 13. "RX0EIO,RX0 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 12. "RX0ED,RX0 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 11. "RX0EIW,RX0 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 10. "RX0EIAS,RX0 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 9. "RX0EID,RX0 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 8. "RX0ENSA,RX0 Element Not Start Address" "0: No illegal read access,1: Read from RX0 Element begins without using start.." bitfld.long 0x8 6. "TXEE,TX Element Enqueued" "0: No Tx message enqueued,1: Tx message successfully enqueued" newline bitfld.long 0x8 5. "TXEIR,TX Element Illegal Read" "0: No read access,1: Illegal read access to DMU TX Element section.." bitfld.long 0x8 4. "TXEWATA,TX Element Write After Trigger Address" "0: No write after Trigger Address,1: Enqueue a message" newline bitfld.long 0x8 3. "TXEIDLC,TX Element Illegal DLC" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." bitfld.long 0x8 2. "TXEIAS,TX Element Illegal Access Sequence" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." newline bitfld.long 0x8 1. "TXEIE,TX Element Illegal Enqueuing" "0: No illegal enqueuing,1: Start of enqueuing without request detected.." bitfld.long 0x8 0. "TXENSA,TX Element Not Start Address" "0: No illegal write access,1: Write to TX Element begins without using start.." line.long 0xC "DMUIE,DMU Interrupt Enable register" bitfld.long 0xC 30. "IACE,Illegal Access while in Configuration mode Enable" "0: Flag DMUIR.IAC does not activate the interrupt..,1: If DMUIR.IAC = 1 the interrupt line dmu_int will.." bitfld.long 0xC 29. "DTE,Debug Trigger Enable" "0: Flag DMUIR.DT does not activate the interrupt..,1: If DMUIR.DT = 1 the interrupt line dmu_int will.." newline bitfld.long 0xC 28. "TXEEDE,TX Event Element Dequeued" "0: Flag DMUIR.TXEED does not activate the interrupt..,1: If DMUIR.TXEED = 1 the interrupt line dmu_int.." bitfld.long 0xC 27. "TXEEIWE,TX Event Element Illegal Write" "0: Flag DMUIR.TXEEIW does not activate the..,1: If DMUIR.TXEEIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 26. "TXEEIASE,TX Event Element Illegal Access Sequence" "0: Flag DMUIR.TXEEIAS does not activate the..,1: If DMUIR.TXEEIAS = 1 the interrupt line dmu_int.." bitfld.long 0xC 25. "TXEEIDE,TX Event Element Illegal Dequeuing" "0: Flag DMUIR.TXEEID does not activate the..,1: If DMUIR.TXEEID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 24. "TXEENSAE,TX Event Element Not Start Address" "0: Flag TXEENSA.TXEENSA does not activate the..,1: If TXEENSA.TXEENSA = 1 the interrupt line.." bitfld.long 0xC 21. "RX1EIOE,RX1 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX1EIO does not activate the..,1: If TXEENSA.RX1EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 20. "RX1EDE,RX1 Element Dequeued Enable" "0: Flag TXEENSA.RX1ED does not activate the..,1: If TXEENSA.RX1ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 19. "RX1EIWE,RX1 Element Illegal Write Enable" "0: Flag TXEENSA.RX1EIW does not activate the..,1: If TXEENSA.RX1EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 18. "RX1EIASE,RX1 Element Illegal Access Sequence Enable" "0: Flag TXEENSA.RX1EIAS does not activate the..,1: If TXEENSA.RX1EIAS = 1 the interrupt line.." bitfld.long 0xC 17. "RX1EIDE,RX1 Element Illegal Dequeuing Enable" "0: Flag TXEENSA.RX1EID does not activate the..,1: If TXEENSA.RX1EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 16. "RX1ENSAE,RX1 Element Not Start Address Enable" "0: Flag TXEENSA.RX1ENSA does not activate the..,1: If TXEENSA.RX1ENSA = 1 the interrupt line.." bitfld.long 0xC 15. "BEUE,Bit Error Uncorrected Enable" "0: Flag TXEENSA.BEU does not activate the interrupt..,1: If TXEENSA.BEU = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 14. "BECE,Bit Error Corrected Enable" "0: Flag TXEENSA.BEC does not activate the interrupt..,1: If TXEENSA.BEC = 1 the interrupt line dmu_int.." bitfld.long 0xC 13. "RX0EIOE,RX0 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX0EIO does not activate the..,1: If TXEENSA.RX0EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 12. "RX0EDE,RX0 Element Dequeued Enabled" "0: Flag TXEENSA.RX0ED does not activate the..,1: If TXEENSA.RX0ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 11. "RX0EIWE,RX0 Element Illegal Write Enabled" "0: Flag TXEENSA.RX0EIW does not activate the..,1: If TXEENSA.RX0EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 10. "RX0EIASE,RX0 Element Illegal Access Sequence Enabled" "0: Flag TXEENSA.RX0EIAS does not activate the..,1: If TXEENSA.RX0EIAS = 1 the interrupt line.." bitfld.long 0xC 9. "RX0EIDE,RX0 Element Illegal Dequeuing Enabled" "0: Flag TXEENSA.RX0EID does not activate the..,1: If TXEENSA.RX0EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 8. "RX0ENSAE,RX0 Element Not Start Address Enabled" "0: Flag TXEENSA.RX0ENSA does not activate the..,1: If TXEENSA.RX0ENSA = 1 the interrupt line.." bitfld.long 0xC 6. "TXEEE,TX Element Enqueued Enable" "0: Flag TXEENSA.TXEE does not activate the..,1: If TXEENSA.TXEE = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 5. "TXEIRE,TX Element Illegal Read Enable" "0: Flag TXEENSA.TXEIR does not activate the..,1: If TXEENSA.TXEIR = 1 the interrupt line dmu_int.." bitfld.long 0xC 4. "TXEWATAE,TX Element Write After Trigger Address Enable" "0: Flag TXEENSA.TXEWATA does not activate the..,1: If TXEENSA.TXEWATA = 1 the interrupt line.." newline bitfld.long 0xC 3. "TXEIDLCE,TX Element Illegal DLC Enable" "0: Flag TXEENSA.TXEIDLC does not activate the..,1: If TXEENSA.TXEIDLC = 1 the interrupt line.." bitfld.long 0xC 2. "TXEIASE,TX Element Illegal Access Sequence Enable" "0: Flag TXEENSA.TXEIAS does not activate the..,1: If TXEENSA.TXEIAS = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 1. "TXEIEE,TX Element Illegal Enqueuing Enable" "0: Flag TXEENSA.TXEIE does not activate the..,1: If TXEENSA.TXEIE = 1 the interrupt line dmu_int.." bitfld.long 0xC 0. "TXENSAE,TX Element Not Start Address Enable" "0: Flag DMUIR.TXENSA does not activate the..,1: If DMUIR.TXENSA = 1 the interrupt line dmu_int.." line.long 0x10 "DMUC,DMU Configuration register" bitfld.long 0x10 0. "TTS,Transfer Timestamp" "0: No timestamp will be transferred via DMU Virtual..,1: Timestamp of message will be transferred from.." tree.end tree "CAN_SUB_1_M_CAN_1" base ad:0x70804000 rgroup.long 0x0++0x7 line.long 0x0 "CREL,Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Substep of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "TS_MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "ENDN,Endian Register" hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value" group.long 0xC++0x23 line.long 0x0 "DBTP,Data Bit Timing and Prescaler Register" bitfld.long 0x0 23. "TDC,Transceiver Delay Compensation" "0: Transceiver Delay Compensation disabled,1: Transceiver Delay Compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re) Synchronization Jump Width" line.long 0x4 "TEST,Test register" bitfld.long 0x4 21. "SVAL,Started Valid" "0: Value of TXBNS not valid,1: Value of TXBNS valid" hexmask.long.byte 0x4 16.--20. 1. "TXBNS,Tx Buffer Number Started" newline bitfld.long 0x4 13. "PVAL,Prepared Valid" "0: Value of TXBNP not valid,1: Value of TXBNP valid" hexmask.long.byte 0x4 8.--12. 1. "TXBNP,Tx Buffer Number Prepared" newline bitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant (CAN Rx input = '0'),1: The CAN bus is recessive (CAN Rx input = '1')" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CAN Tx output is controlled by the..,1: Sample Point can be monitored at pin CAN Tx output,2: Dominant ('0') level at pin CAN Tx output,3: Recessive ('1') at pin CAN Tx output" newline bitfld.long 0x4 4. "LBCK,Loop Back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (refer to.." line.long 0x8 "RWD,RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration" line.long 0xC "CCCR,CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0xC 11. "WMM,Wide Message Marker" "0: 8-bit Message Marker used,1: 16-bit Message Marker used replacing 16-bit.." bitfld.long 0xC 10. "UTSU,Use Timestamping Unit" "0: Internal time stamping,1: External time stamping by TSU" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST_EN,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_CAN may be set in power down by stopping Host.." bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started" line.long 0x10 "NBTP,Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,(Re) Synchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Time segment before sample point" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,The time segment after the sample point" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Same as 00" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. "TOC,The Timeout Counter is decremented in multiples of CAN bit times (1 to 16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are.." rgroup.long 0x40++0x7 line.long 0x0 "ECR,Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "PSR,Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Received CAN FD Message" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set." newline bitfld.long 0x4 11. "RESI,ESI CAN FD Message with ESI flag" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state" bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state. It..,1: The M_CAN is in the Error_Passive state" bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing node is synchronizing on CAN..,1: Idle-node is neither receiver nor transmitter,2: Receiver-node is operating as receiver,3: Transmitter-node is operating as transmitter" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: consecutive recessive bits,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.." group.long 0x48++0x3 line.long 0x0 "TDCR,Transmitter Delay compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0xF line.long 0x0 "IR,Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected uncorrected (for example.." bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected (for example ECC)" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Event Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx Event FIDO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "IE,Interrupt Enable Register" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "ILS,Interrupt Line Select Register" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 16. "TSWL,TSWL: Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" line.long 0xC "ILE,Interrupt Line Enable Register" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line disabled,1: Interrupt line enabled" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line disabled,1: Interrupt line enabled" group.long 0x80++0xB line.long 0x0 "GFC,Global Filter Configuration Register" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,ANFE[1:0]: Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x8 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x3 line.long 0x0 "XIDAM,Extended ID and Mask Register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "HPMS,High Priority Message Status Register" bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "NDAT1,New Data 1 Register" bitfld.long 0x0 31. "ND31,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 30. "ND30,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 28. "ND28,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 26. "ND26,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 24. "ND24,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 22. "ND22,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 20. "ND20,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 18. "ND18,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 16. "ND16,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 14. "ND14,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 12. "ND12,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 10. "ND10,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 8. "ND8,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 6. "ND6,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 4. "ND4,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 2. "ND2,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 0. "ND0,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x4 "NDAT2,New Data 2 Register" bitfld.long 0x4 31. "ND63,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 30. "ND62,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 28. "ND60,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 26. "ND58,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 24. "ND56,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 22. "ND54,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 20. "ND52,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 18. "ND50,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 16. "ND48,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 14. "ND46,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 12. "ND44,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 10. "ND42,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 8. "ND40,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 6. "ND38,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 4. "ND36,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 2. "ND34,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 0. "ND32,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x8 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x0 25. "RF0L,RF0L" "0,1" bitfld.long 0x0 24. "F0F,F0F" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,F0PI" hexmask.long.byte 0x0 8.--13. 1. "F0GI,F0GI" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,F0FL" group.long 0xA8++0xB line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "RXF1C,Rx FIFO 1 Configuration Register" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,F1S[6:0]:" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is set" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" line.long 0x8 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Tx FIFO/Queue Size" newline hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x3 line.long 0x0 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x0 31. "AR31,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 30. "AR30,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 29. "AR29,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 28. "AR28,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 27. "AR27,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 26. "AR26,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 25. "AR25,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 24. "AR24,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 23. "AR23,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 22. "AR22,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 21. "AR21,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 20. "AR20,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 19. "AR19,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 18. "AR18,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 17. "AR17,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 16. "AR16,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 15. "AR15,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 14. "AR14,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 13. "AR13,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 12. "AR12,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 11. "AR11,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 10. "AR10,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 9. "AR9,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 8. "AR8,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 7. "AR7,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 6. "AR6,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 5. "AR5,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 4. "AR4,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 3. "AR3,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 2. "AR2,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 1. "AR1,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 0. "AR0,Add Request" "0: No transmission request added,1: Transmission requested added" line.long 0x4 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x4 31. "CR31,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 30. "CR30,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 29. "CR29,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 28. "CR28,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 27. "CR27,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 26. "CR26,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 24. "CR24,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 23. "CR23,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 22. "CR22,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 21. "CR21,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 20. "CR20,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 18. "CR18,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 17. "CR17,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 16. "CR16,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 15. "CR15,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 14. "CR14,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 12. "CR12,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 11. "CR11,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 10. "CR10,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 9. "CR9,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 8. "CR8,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 6. "CR6,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 5. "CR5,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 4. "CR4,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 3. "CR3,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 2. "CR2,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 0. "CR0,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" rgroup.long 0xD8++0x7 line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 29. "TO29,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 28. "TO28,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 27. "TO27,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 23. "TO23,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 22. "TO22,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 21. "TO21,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 17. "TO17,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 16. "TO16,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 15. "TO15,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 11. "TO11,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 10. "TO10,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 9. "TO9,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 5. "TO5,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 4. "TO4,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 3. "TO3,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 29. "CF29,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 28. "CF28,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 27. "CF27,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 23. "CF23,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 22. "CF22,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 21. "CF21,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 17. "CF17,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 16. "CF16,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 15. "CF15,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 11. "CF11,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 10. "CF10,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 9. "CF9,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 5. "CF5,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 4. "CF4,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 3. "CF3,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" group.long 0xE0++0x7 line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" group.long 0xF0++0x3 line.long 0x0 "TXEFC,Tx Event FIFO Configuration Register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address." rgroup.long 0xF4++0x3 line.long 0x0 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0x3 line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge Register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" tree.end tree "CAN_SUB_1_M_CAN_2" base ad:0x70808000 rgroup.long 0x0++0x7 line.long 0x0 "CREL,Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Substep of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "TS_MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "ENDN,Endian Register" hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value" group.long 0xC++0x23 line.long 0x0 "DBTP,Data Bit Timing and Prescaler Register" bitfld.long 0x0 23. "TDC,Transceiver Delay Compensation" "0: Transceiver Delay Compensation disabled,1: Transceiver Delay Compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re) Synchronization Jump Width" line.long 0x4 "TEST,Test register" bitfld.long 0x4 21. "SVAL,Started Valid" "0: Value of TXBNS not valid,1: Value of TXBNS valid" hexmask.long.byte 0x4 16.--20. 1. "TXBNS,Tx Buffer Number Started" newline bitfld.long 0x4 13. "PVAL,Prepared Valid" "0: Value of TXBNP not valid,1: Value of TXBNP valid" hexmask.long.byte 0x4 8.--12. 1. "TXBNP,Tx Buffer Number Prepared" newline bitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant (CAN Rx input = '0'),1: The CAN bus is recessive (CAN Rx input = '1')" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CAN Tx output is controlled by the..,1: Sample Point can be monitored at pin CAN Tx output,2: Dominant ('0') level at pin CAN Tx output,3: Recessive ('1') at pin CAN Tx output" newline bitfld.long 0x4 4. "LBCK,Loop Back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (refer to.." line.long 0x8 "RWD,RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration" line.long 0xC "CCCR,CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0xC 11. "WMM,Wide Message Marker" "0: 8-bit Message Marker used,1: 16-bit Message Marker used replacing 16-bit.." bitfld.long 0xC 10. "UTSU,Use Timestamping Unit" "0: Internal time stamping,1: External time stamping by TSU" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST_EN,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_CAN may be set in power down by stopping Host.." bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started" line.long 0x10 "NBTP,Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,(Re) Synchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Time segment before sample point" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,The time segment after the sample point" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Same as 00" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. "TOC,The Timeout Counter is decremented in multiples of CAN bit times (1 to 16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are.." rgroup.long 0x40++0x7 line.long 0x0 "ECR,Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "PSR,Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Received CAN FD Message" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set." newline bitfld.long 0x4 11. "RESI,ESI CAN FD Message with ESI flag" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state" bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state. It..,1: The M_CAN is in the Error_Passive state" bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing node is synchronizing on CAN..,1: Idle-node is neither receiver nor transmitter,2: Receiver-node is operating as receiver,3: Transmitter-node is operating as transmitter" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: consecutive recessive bits,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.." group.long 0x48++0x3 line.long 0x0 "TDCR,Transmitter Delay compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0xF line.long 0x0 "IR,Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected uncorrected (for example.." bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected (for example ECC)" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Event Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx Event FIDO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "IE,Interrupt Enable Register" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "ILS,Interrupt Line Select Register" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 16. "TSWL,TSWL: Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" line.long 0xC "ILE,Interrupt Line Enable Register" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line disabled,1: Interrupt line enabled" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line disabled,1: Interrupt line enabled" group.long 0x80++0xB line.long 0x0 "GFC,Global Filter Configuration Register" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,ANFE[1:0]: Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x8 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x3 line.long 0x0 "XIDAM,Extended ID and Mask Register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "HPMS,High Priority Message Status Register" bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "NDAT1,New Data 1 Register" bitfld.long 0x0 31. "ND31,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 30. "ND30,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 28. "ND28,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 26. "ND26,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 24. "ND24,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 22. "ND22,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 20. "ND20,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 18. "ND18,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 16. "ND16,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 14. "ND14,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 12. "ND12,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 10. "ND10,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 8. "ND8,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 6. "ND6,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 4. "ND4,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 2. "ND2,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 0. "ND0,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x4 "NDAT2,New Data 2 Register" bitfld.long 0x4 31. "ND63,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 30. "ND62,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 28. "ND60,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 26. "ND58,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 24. "ND56,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 22. "ND54,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 20. "ND52,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 18. "ND50,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 16. "ND48,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 14. "ND46,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 12. "ND44,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 10. "ND42,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 8. "ND40,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 6. "ND38,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 4. "ND36,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 2. "ND34,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 0. "ND32,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x8 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x0 25. "RF0L,RF0L" "0,1" bitfld.long 0x0 24. "F0F,F0F" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,F0PI" hexmask.long.byte 0x0 8.--13. 1. "F0GI,F0GI" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,F0FL" group.long 0xA8++0xB line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "RXF1C,Rx FIFO 1 Configuration Register" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,F1S[6:0]:" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is set" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" line.long 0x8 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Tx FIFO/Queue Size" newline hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x3 line.long 0x0 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x0 31. "AR31,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 30. "AR30,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 29. "AR29,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 28. "AR28,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 27. "AR27,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 26. "AR26,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 25. "AR25,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 24. "AR24,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 23. "AR23,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 22. "AR22,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 21. "AR21,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 20. "AR20,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 19. "AR19,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 18. "AR18,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 17. "AR17,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 16. "AR16,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 15. "AR15,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 14. "AR14,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 13. "AR13,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 12. "AR12,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 11. "AR11,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 10. "AR10,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 9. "AR9,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 8. "AR8,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 7. "AR7,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 6. "AR6,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 5. "AR5,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 4. "AR4,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 3. "AR3,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 2. "AR2,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 1. "AR1,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 0. "AR0,Add Request" "0: No transmission request added,1: Transmission requested added" line.long 0x4 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x4 31. "CR31,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 30. "CR30,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 29. "CR29,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 28. "CR28,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 27. "CR27,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 26. "CR26,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 24. "CR24,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 23. "CR23,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 22. "CR22,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 21. "CR21,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 20. "CR20,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 18. "CR18,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 17. "CR17,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 16. "CR16,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 15. "CR15,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 14. "CR14,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 12. "CR12,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 11. "CR11,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 10. "CR10,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 9. "CR9,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 8. "CR8,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 6. "CR6,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 5. "CR5,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 4. "CR4,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 3. "CR3,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 2. "CR2,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 0. "CR0,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" rgroup.long 0xD8++0x7 line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 29. "TO29,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 28. "TO28,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 27. "TO27,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 23. "TO23,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 22. "TO22,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 21. "TO21,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 17. "TO17,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 16. "TO16,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 15. "TO15,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 11. "TO11,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 10. "TO10,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 9. "TO9,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 5. "TO5,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 4. "TO4,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 3. "TO3,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 29. "CF29,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 28. "CF28,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 27. "CF27,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 23. "CF23,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 22. "CF22,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 21. "CF21,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 17. "CF17,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 16. "CF16,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 15. "CF15,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 11. "CF11,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 10. "CF10,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 9. "CF9,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 5. "CF5,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 4. "CF4,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 3. "CF3,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" group.long 0xE0++0x7 line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" group.long 0xF0++0x3 line.long 0x0 "TXEFC,Tx Event FIFO Configuration Register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address." rgroup.long 0xF4++0x3 line.long 0x0 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0x3 line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge Register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" tree.end tree "CAN_SUB_1_M_CAN_3" base ad:0x7080C000 rgroup.long 0x0++0x7 line.long 0x0 "CREL,Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Substep of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "TS_MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "ENDN,Endian Register" hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value" group.long 0xC++0x23 line.long 0x0 "DBTP,Data Bit Timing and Prescaler Register" bitfld.long 0x0 23. "TDC,Transceiver Delay Compensation" "0: Transceiver Delay Compensation disabled,1: Transceiver Delay Compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re) Synchronization Jump Width" line.long 0x4 "TEST,Test register" bitfld.long 0x4 21. "SVAL,Started Valid" "0: Value of TXBNS not valid,1: Value of TXBNS valid" hexmask.long.byte 0x4 16.--20. 1. "TXBNS,Tx Buffer Number Started" newline bitfld.long 0x4 13. "PVAL,Prepared Valid" "0: Value of TXBNP not valid,1: Value of TXBNP valid" hexmask.long.byte 0x4 8.--12. 1. "TXBNP,Tx Buffer Number Prepared" newline bitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant (CAN Rx input = '0'),1: The CAN bus is recessive (CAN Rx input = '1')" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CAN Tx output is controlled by the..,1: Sample Point can be monitored at pin CAN Tx output,2: Dominant ('0') level at pin CAN Tx output,3: Recessive ('1') at pin CAN Tx output" newline bitfld.long 0x4 4. "LBCK,Loop Back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (refer to.." line.long 0x8 "RWD,RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration" line.long 0xC "CCCR,CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0xC 11. "WMM,Wide Message Marker" "0: 8-bit Message Marker used,1: 16-bit Message Marker used replacing 16-bit.." bitfld.long 0xC 10. "UTSU,Use Timestamping Unit" "0: Internal time stamping,1: External time stamping by TSU" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST_EN,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_CAN may be set in power down by stopping Host.." bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started" line.long 0x10 "NBTP,Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,(Re) Synchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Time segment before sample point" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,The time segment after the sample point" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Same as 00" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. "TOC,The Timeout Counter is decremented in multiples of CAN bit times (1 to 16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are.." rgroup.long 0x40++0x7 line.long 0x0 "ECR,Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "PSR,Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Received CAN FD Message" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set." newline bitfld.long 0x4 11. "RESI,ESI CAN FD Message with ESI flag" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state" bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state. It..,1: The M_CAN is in the Error_Passive state" bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing node is synchronizing on CAN..,1: Idle-node is neither receiver nor transmitter,2: Receiver-node is operating as receiver,3: Transmitter-node is operating as transmitter" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: consecutive recessive bits,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.." group.long 0x48++0x3 line.long 0x0 "TDCR,Transmitter Delay compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0xF line.long 0x0 "IR,Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected uncorrected (for example.." bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected (for example ECC)" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Event Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx Event FIDO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "IE,Interrupt Enable Register" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "ILS,Interrupt Line Select Register" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 16. "TSWL,TSWL: Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" line.long 0xC "ILE,Interrupt Line Enable Register" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line disabled,1: Interrupt line enabled" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line disabled,1: Interrupt line enabled" group.long 0x80++0xB line.long 0x0 "GFC,Global Filter Configuration Register" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,ANFE[1:0]: Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x8 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x3 line.long 0x0 "XIDAM,Extended ID and Mask Register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "HPMS,High Priority Message Status Register" bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "NDAT1,New Data 1 Register" bitfld.long 0x0 31. "ND31,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 30. "ND30,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 28. "ND28,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 26. "ND26,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 24. "ND24,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 22. "ND22,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 20. "ND20,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 18. "ND18,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 16. "ND16,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 14. "ND14,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 12. "ND12,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 10. "ND10,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 8. "ND8,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 6. "ND6,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 4. "ND4,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 2. "ND2,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 0. "ND0,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x4 "NDAT2,New Data 2 Register" bitfld.long 0x4 31. "ND63,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 30. "ND62,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 28. "ND60,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 26. "ND58,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 24. "ND56,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 22. "ND54,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 20. "ND52,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 18. "ND50,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 16. "ND48,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 14. "ND46,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 12. "ND44,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 10. "ND42,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 8. "ND40,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 6. "ND38,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 4. "ND36,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 2. "ND34,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 0. "ND32,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x8 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x0 25. "RF0L,RF0L" "0,1" bitfld.long 0x0 24. "F0F,F0F" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,F0PI" hexmask.long.byte 0x0 8.--13. 1. "F0GI,F0GI" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,F0FL" group.long 0xA8++0xB line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "RXF1C,Rx FIFO 1 Configuration Register" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,F1S[6:0]:" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is set" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" line.long 0x8 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Tx FIFO/Queue Size" newline hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x3 line.long 0x0 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x0 31. "AR31,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 30. "AR30,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 29. "AR29,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 28. "AR28,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 27. "AR27,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 26. "AR26,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 25. "AR25,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 24. "AR24,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 23. "AR23,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 22. "AR22,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 21. "AR21,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 20. "AR20,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 19. "AR19,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 18. "AR18,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 17. "AR17,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 16. "AR16,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 15. "AR15,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 14. "AR14,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 13. "AR13,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 12. "AR12,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 11. "AR11,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 10. "AR10,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 9. "AR9,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 8. "AR8,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 7. "AR7,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 6. "AR6,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 5. "AR5,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 4. "AR4,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 3. "AR3,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 2. "AR2,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 1. "AR1,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 0. "AR0,Add Request" "0: No transmission request added,1: Transmission requested added" line.long 0x4 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x4 31. "CR31,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 30. "CR30,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 29. "CR29,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 28. "CR28,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 27. "CR27,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 26. "CR26,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 24. "CR24,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 23. "CR23,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 22. "CR22,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 21. "CR21,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 20. "CR20,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 18. "CR18,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 17. "CR17,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 16. "CR16,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 15. "CR15,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 14. "CR14,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 12. "CR12,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 11. "CR11,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 10. "CR10,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 9. "CR9,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 8. "CR8,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 6. "CR6,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 5. "CR5,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 4. "CR4,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 3. "CR3,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 2. "CR2,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 0. "CR0,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" rgroup.long 0xD8++0x7 line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 29. "TO29,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 28. "TO28,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 27. "TO27,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 23. "TO23,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 22. "TO22,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 21. "TO21,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 17. "TO17,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 16. "TO16,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 15. "TO15,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 11. "TO11,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 10. "TO10,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 9. "TO9,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 5. "TO5,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 4. "TO4,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 3. "TO3,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 29. "CF29,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 28. "CF28,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 27. "CF27,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 23. "CF23,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 22. "CF22,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 21. "CF21,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 17. "CF17,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 16. "CF16,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 15. "CF15,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 11. "CF11,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 10. "CF10,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 9. "CF9,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 5. "CF5,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 4. "CF4,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 3. "CF3,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" group.long 0xE0++0x7 line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" group.long 0xF0++0x3 line.long 0x0 "TXEFC,Tx Event FIFO Configuration Register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address." rgroup.long 0xF4++0x3 line.long 0x0 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0x3 line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge Register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" tree.end tree "CAN_SUB_1_M_CAN_4" base ad:0x70810000 rgroup.long 0x0++0x7 line.long 0x0 "CREL,Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Substep of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "TS_MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "ENDN,Endian Register" hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value" group.long 0xC++0x23 line.long 0x0 "DBTP,Data Bit Timing and Prescaler Register" bitfld.long 0x0 23. "TDC,Transceiver Delay Compensation" "0: Transceiver Delay Compensation disabled,1: Transceiver Delay Compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re) Synchronization Jump Width" line.long 0x4 "TEST,Test register" bitfld.long 0x4 21. "SVAL,Started Valid" "0: Value of TXBNS not valid,1: Value of TXBNS valid" hexmask.long.byte 0x4 16.--20. 1. "TXBNS,Tx Buffer Number Started" newline bitfld.long 0x4 13. "PVAL,Prepared Valid" "0: Value of TXBNP not valid,1: Value of TXBNP valid" hexmask.long.byte 0x4 8.--12. 1. "TXBNP,Tx Buffer Number Prepared" newline bitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant (CAN Rx input = '0'),1: The CAN bus is recessive (CAN Rx input = '1')" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CAN Tx output is controlled by the..,1: Sample Point can be monitored at pin CAN Tx output,2: Dominant ('0') level at pin CAN Tx output,3: Recessive ('1') at pin CAN Tx output" newline bitfld.long 0x4 4. "LBCK,Loop Back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (refer to.." line.long 0x8 "RWD,RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration" line.long 0xC "CCCR,CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0xC 11. "WMM,Wide Message Marker" "0: 8-bit Message Marker used,1: 16-bit Message Marker used replacing 16-bit.." bitfld.long 0xC 10. "UTSU,Use Timestamping Unit" "0: Internal time stamping,1: External time stamping by TSU" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST_EN,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_CAN may be set in power down by stopping Host.." bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started" line.long 0x10 "NBTP,Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,(Re) Synchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Time segment before sample point" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,The time segment after the sample point" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Same as 00" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. "TOC,The Timeout Counter is decremented in multiples of CAN bit times (1 to 16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are.." rgroup.long 0x40++0x7 line.long 0x0 "ECR,Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "PSR,Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Received CAN FD Message" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set." newline bitfld.long 0x4 11. "RESI,ESI CAN FD Message with ESI flag" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state" bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state. It..,1: The M_CAN is in the Error_Passive state" bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing node is synchronizing on CAN..,1: Idle-node is neither receiver nor transmitter,2: Receiver-node is operating as receiver,3: Transmitter-node is operating as transmitter" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: consecutive recessive bits,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.." group.long 0x48++0x3 line.long 0x0 "TDCR,Transmitter Delay compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0xF line.long 0x0 "IR,Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected uncorrected (for example.." bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected (for example ECC)" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Event Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx Event FIDO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "IE,Interrupt Enable Register" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "ILS,Interrupt Line Select Register" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 16. "TSWL,TSWL: Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" line.long 0xC "ILE,Interrupt Line Enable Register" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line disabled,1: Interrupt line enabled" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line disabled,1: Interrupt line enabled" group.long 0x80++0xB line.long 0x0 "GFC,Global Filter Configuration Register" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,ANFE[1:0]: Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x8 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x3 line.long 0x0 "XIDAM,Extended ID and Mask Register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "HPMS,High Priority Message Status Register" bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "NDAT1,New Data 1 Register" bitfld.long 0x0 31. "ND31,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 30. "ND30,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 28. "ND28,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 26. "ND26,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 24. "ND24,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 22. "ND22,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 20. "ND20,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 18. "ND18,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 16. "ND16,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 14. "ND14,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 12. "ND12,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 10. "ND10,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 8. "ND8,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 6. "ND6,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 4. "ND4,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 2. "ND2,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 0. "ND0,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x4 "NDAT2,New Data 2 Register" bitfld.long 0x4 31. "ND63,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 30. "ND62,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 28. "ND60,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 26. "ND58,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 24. "ND56,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 22. "ND54,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 20. "ND52,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 18. "ND50,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 16. "ND48,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 14. "ND46,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 12. "ND44,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 10. "ND42,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 8. "ND40,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 6. "ND38,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 4. "ND36,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 2. "ND34,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 0. "ND32,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x8 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x0 25. "RF0L,RF0L" "0,1" bitfld.long 0x0 24. "F0F,F0F" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,F0PI" hexmask.long.byte 0x0 8.--13. 1. "F0GI,F0GI" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,F0FL" group.long 0xA8++0xB line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "RXF1C,Rx FIFO 1 Configuration Register" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,F1S[6:0]:" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is set" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" line.long 0x8 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Tx FIFO/Queue Size" newline hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x3 line.long 0x0 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x0 31. "AR31,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 30. "AR30,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 29. "AR29,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 28. "AR28,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 27. "AR27,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 26. "AR26,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 25. "AR25,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 24. "AR24,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 23. "AR23,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 22. "AR22,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 21. "AR21,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 20. "AR20,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 19. "AR19,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 18. "AR18,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 17. "AR17,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 16. "AR16,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 15. "AR15,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 14. "AR14,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 13. "AR13,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 12. "AR12,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 11. "AR11,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 10. "AR10,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 9. "AR9,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 8. "AR8,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 7. "AR7,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 6. "AR6,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 5. "AR5,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 4. "AR4,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 3. "AR3,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 2. "AR2,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 1. "AR1,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 0. "AR0,Add Request" "0: No transmission request added,1: Transmission requested added" line.long 0x4 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x4 31. "CR31,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 30. "CR30,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 29. "CR29,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 28. "CR28,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 27. "CR27,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 26. "CR26,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 24. "CR24,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 23. "CR23,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 22. "CR22,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 21. "CR21,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 20. "CR20,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 18. "CR18,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 17. "CR17,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 16. "CR16,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 15. "CR15,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 14. "CR14,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 12. "CR12,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 11. "CR11,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 10. "CR10,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 9. "CR9,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 8. "CR8,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 6. "CR6,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 5. "CR5,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 4. "CR4,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 3. "CR3,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 2. "CR2,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 0. "CR0,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" rgroup.long 0xD8++0x7 line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 29. "TO29,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 28. "TO28,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 27. "TO27,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 23. "TO23,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 22. "TO22,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 21. "TO21,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 17. "TO17,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 16. "TO16,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 15. "TO15,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 11. "TO11,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 10. "TO10,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 9. "TO9,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 5. "TO5,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 4. "TO4,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 3. "TO3,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 29. "CF29,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 28. "CF28,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 27. "CF27,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 23. "CF23,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 22. "CF22,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 21. "CF21,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 17. "CF17,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 16. "CF16,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 15. "CF15,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 11. "CF11,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 10. "CF10,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 9. "CF9,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 5. "CF5,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 4. "CF4,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 3. "CF3,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" group.long 0xE0++0x7 line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" group.long 0xF0++0x3 line.long 0x0 "TXEFC,Tx Event FIFO Configuration Register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address." rgroup.long 0xF4++0x3 line.long 0x0 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0x3 line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge Register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" tree.end tree "CAN_SUB_1_TSU_1" base ad:0x70804000 rgroup.long 0x160++0x7 line.long 0x0 "CREL,Core Release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "TSCFG,Timestamp Configuration register" hexmask.long.byte 0x4 8.--15. 1. "TBPRE,TBPRE" bitfld.long 0x4 2. "SCP,Select Capturing Position" "0: Capture Timestamp at EOF,1: Capture Timestamp at SOF" newline bitfld.long 0x4 1. "TBCS,Timebase Counter Select" "0: Timestamp value captured from internal timebase..,1: : Timestamp value captured from input.." bitfld.long 0x4 0. "TSUE,Timestamp Unit Enable 0" "0: TSU disabled,1: TSU enabled" group.long 0x168++0x3 line.long 0x0 "TSS1,Timestamp Status 1 register" bitfld.long 0x0 31. "TSL15,Timestamp Lost" "0,1" bitfld.long 0x0 30. "TSL14,Timestamp Lost" "0,1" newline bitfld.long 0x0 29. "TSL13,Timestamp Lost" "0,1" bitfld.long 0x0 28. "TSL12,Timestamp Lost" "0,1" newline bitfld.long 0x0 27. "TSL11,Timestamp Lost" "0,1" bitfld.long 0x0 26. "TSL10,Timestamp Lost" "0,1" newline bitfld.long 0x0 25. "TSL9,Timestamp Lost" "0,1" bitfld.long 0x0 24. "TSL8,Timestamp Lost" "0,1" newline bitfld.long 0x0 23. "TSL7,Timestamp Lost" "0,1" bitfld.long 0x0 22. "TSL6,Timestamp Lost" "0,1" newline bitfld.long 0x0 21. "TSL5,Timestamp Lost" "0,1" bitfld.long 0x0 20. "TSL4,Timestamp Lost" "0,1" newline bitfld.long 0x0 19. "TSL3,Timestamp Lost" "0,1" bitfld.long 0x0 18. "TSL2,Timestamp Lost" "0,1" newline bitfld.long 0x0 17. "TSL1,Timestamp Lost" "0,1" bitfld.long 0x0 16. "TSL0,Timestamp Lost" "0,1" newline bitfld.long 0x0 15. "TSN15,Timestamp New" "0,1" bitfld.long 0x0 14. "TSN14,Timestamp New" "0,1" newline bitfld.long 0x0 13. "TSN13,Timestamp New" "0,1" bitfld.long 0x0 12. "TSN12,Timestamp New" "0,1" newline bitfld.long 0x0 11. "TSN11,Timestamp New" "0,1" bitfld.long 0x0 10. "TSN10,Timestamp New" "0,1" newline bitfld.long 0x0 9. "TSN9,Timestamp New" "0,1" bitfld.long 0x0 8. "TSN8,Timestamp New" "0,1" newline bitfld.long 0x0 7. "TSN7,Timestamp New" "0,1" bitfld.long 0x0 6. "TSN6,Timestamp New" "0,1" newline bitfld.long 0x0 5. "TSN5,Timestamp New" "0,1" bitfld.long 0x0 4. "TSN4,Timestamp New" "0,1" newline bitfld.long 0x0 3. "TSN3,Timestamp New" "0,1" bitfld.long 0x0 2. "TSN2,Timestamp New" "0,1" newline bitfld.long 0x0 1. "TSN1,Timestamp New" "0,1" bitfld.long 0x0 0. "TSN0,Timestamp New" "0,1" rgroup.long 0x16C++0x43 line.long 0x0 "TSS2,Timestamp Status 2 register" bitfld.long 0x0 14.--15. "ITBG,Internal Timebase and SOF select Generic" "0: no SOF option no internal timebase,1: no SOF option internal timebase (default),2: SOF option no internal timebase,3: SOF option internal timebase" bitfld.long 0x0 12.--13. "NTSG,Number of Timestamps Generic" "0: 4 timestamp registers TS0-TS3,1: 8 timestamp registers TS0-TS7 (default),2: 16 timestamp registers TS0-TS15,3: not a valid value" newline hexmask.long.byte 0x0 0.--3. 1. "TSP,Timestamp Pointer" line.long 0x4 "TS0,Timestamp 0 register" hexmask.long 0x4 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x8 "TS1,Timestamp 1 register" hexmask.long 0x8 0.--31. 1. "TS,Timestamp Word TSn" line.long 0xC "TS2,Timestamp 2 register" hexmask.long 0xC 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x10 "TS3,Timestamp 3 register" hexmask.long 0x10 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x14 "TS4,Timestamp 4 register" hexmask.long 0x14 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x18 "TS5,Timestamp 5 register" hexmask.long 0x18 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x1C "TS6,Timestamp 6 register" hexmask.long 0x1C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x20 "TS7,Timestamp 7 register" hexmask.long 0x20 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x24 "TS8,Timestamp 8 register" hexmask.long 0x24 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x28 "TS9,Timestamp 9 register" hexmask.long 0x28 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x2C "TS10,Timestamp 10 register" hexmask.long 0x2C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x30 "TS11,Timestamp 11 register" hexmask.long 0x30 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x34 "TS12,Timestamp 12 register" hexmask.long 0x34 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x38 "TS13,Timestamp 13 register" hexmask.long 0x38 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x3C "TS14,Timestamp 14 register" hexmask.long 0x3C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x40 "TS15,Timestamp 15 register" hexmask.long 0x40 0.--31. 1. "TS,Timestamp Word TSn" group.long 0x1B0++0x3 line.long 0x0 "ATB,Actual Timebase" hexmask.long 0x0 0.--31. 1. "TB,Timebase for timestamp generation" tree.end tree "CAN_SUB_1_TSU_2" base ad:0x70808000 rgroup.long 0x160++0x7 line.long 0x0 "CREL,Core Release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "TSCFG,Timestamp Configuration register" hexmask.long.byte 0x4 8.--15. 1. "TBPRE,TBPRE" bitfld.long 0x4 2. "SCP,Select Capturing Position" "0: Capture Timestamp at EOF,1: Capture Timestamp at SOF" newline bitfld.long 0x4 1. "TBCS,Timebase Counter Select" "0: Timestamp value captured from internal timebase..,1: : Timestamp value captured from input.." bitfld.long 0x4 0. "TSUE,Timestamp Unit Enable 0" "0: TSU disabled,1: TSU enabled" group.long 0x168++0x3 line.long 0x0 "TSS1,Timestamp Status 1 register" bitfld.long 0x0 31. "TSL15,Timestamp Lost" "0,1" bitfld.long 0x0 30. "TSL14,Timestamp Lost" "0,1" newline bitfld.long 0x0 29. "TSL13,Timestamp Lost" "0,1" bitfld.long 0x0 28. "TSL12,Timestamp Lost" "0,1" newline bitfld.long 0x0 27. "TSL11,Timestamp Lost" "0,1" bitfld.long 0x0 26. "TSL10,Timestamp Lost" "0,1" newline bitfld.long 0x0 25. "TSL9,Timestamp Lost" "0,1" bitfld.long 0x0 24. "TSL8,Timestamp Lost" "0,1" newline bitfld.long 0x0 23. "TSL7,Timestamp Lost" "0,1" bitfld.long 0x0 22. "TSL6,Timestamp Lost" "0,1" newline bitfld.long 0x0 21. "TSL5,Timestamp Lost" "0,1" bitfld.long 0x0 20. "TSL4,Timestamp Lost" "0,1" newline bitfld.long 0x0 19. "TSL3,Timestamp Lost" "0,1" bitfld.long 0x0 18. "TSL2,Timestamp Lost" "0,1" newline bitfld.long 0x0 17. "TSL1,Timestamp Lost" "0,1" bitfld.long 0x0 16. "TSL0,Timestamp Lost" "0,1" newline bitfld.long 0x0 15. "TSN15,Timestamp New" "0,1" bitfld.long 0x0 14. "TSN14,Timestamp New" "0,1" newline bitfld.long 0x0 13. "TSN13,Timestamp New" "0,1" bitfld.long 0x0 12. "TSN12,Timestamp New" "0,1" newline bitfld.long 0x0 11. "TSN11,Timestamp New" "0,1" bitfld.long 0x0 10. "TSN10,Timestamp New" "0,1" newline bitfld.long 0x0 9. "TSN9,Timestamp New" "0,1" bitfld.long 0x0 8. "TSN8,Timestamp New" "0,1" newline bitfld.long 0x0 7. "TSN7,Timestamp New" "0,1" bitfld.long 0x0 6. "TSN6,Timestamp New" "0,1" newline bitfld.long 0x0 5. "TSN5,Timestamp New" "0,1" bitfld.long 0x0 4. "TSN4,Timestamp New" "0,1" newline bitfld.long 0x0 3. "TSN3,Timestamp New" "0,1" bitfld.long 0x0 2. "TSN2,Timestamp New" "0,1" newline bitfld.long 0x0 1. "TSN1,Timestamp New" "0,1" bitfld.long 0x0 0. "TSN0,Timestamp New" "0,1" rgroup.long 0x16C++0x43 line.long 0x0 "TSS2,Timestamp Status 2 register" bitfld.long 0x0 14.--15. "ITBG,Internal Timebase and SOF select Generic" "0: no SOF option no internal timebase,1: no SOF option internal timebase (default),2: SOF option no internal timebase,3: SOF option internal timebase" bitfld.long 0x0 12.--13. "NTSG,Number of Timestamps Generic" "0: 4 timestamp registers TS0-TS3,1: 8 timestamp registers TS0-TS7 (default),2: 16 timestamp registers TS0-TS15,3: not a valid value" newline hexmask.long.byte 0x0 0.--3. 1. "TSP,Timestamp Pointer" line.long 0x4 "TS0,Timestamp 0 register" hexmask.long 0x4 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x8 "TS1,Timestamp 1 register" hexmask.long 0x8 0.--31. 1. "TS,Timestamp Word TSn" line.long 0xC "TS2,Timestamp 2 register" hexmask.long 0xC 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x10 "TS3,Timestamp 3 register" hexmask.long 0x10 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x14 "TS4,Timestamp 4 register" hexmask.long 0x14 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x18 "TS5,Timestamp 5 register" hexmask.long 0x18 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x1C "TS6,Timestamp 6 register" hexmask.long 0x1C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x20 "TS7,Timestamp 7 register" hexmask.long 0x20 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x24 "TS8,Timestamp 8 register" hexmask.long 0x24 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x28 "TS9,Timestamp 9 register" hexmask.long 0x28 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x2C "TS10,Timestamp 10 register" hexmask.long 0x2C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x30 "TS11,Timestamp 11 register" hexmask.long 0x30 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x34 "TS12,Timestamp 12 register" hexmask.long 0x34 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x38 "TS13,Timestamp 13 register" hexmask.long 0x38 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x3C "TS14,Timestamp 14 register" hexmask.long 0x3C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x40 "TS15,Timestamp 15 register" hexmask.long 0x40 0.--31. 1. "TS,Timestamp Word TSn" group.long 0x1B0++0x3 line.long 0x0 "ATB,Actual Timebase" hexmask.long 0x0 0.--31. 1. "TB,Timebase for timestamp generation" tree.end tree "CAN_SUB_1_TSU_3" base ad:0x7080C000 rgroup.long 0x160++0x7 line.long 0x0 "CREL,Core Release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "TSCFG,Timestamp Configuration register" hexmask.long.byte 0x4 8.--15. 1. "TBPRE,TBPRE" bitfld.long 0x4 2. "SCP,Select Capturing Position" "0: Capture Timestamp at EOF,1: Capture Timestamp at SOF" newline bitfld.long 0x4 1. "TBCS,Timebase Counter Select" "0: Timestamp value captured from internal timebase..,1: : Timestamp value captured from input.." bitfld.long 0x4 0. "TSUE,Timestamp Unit Enable 0" "0: TSU disabled,1: TSU enabled" group.long 0x168++0x3 line.long 0x0 "TSS1,Timestamp Status 1 register" bitfld.long 0x0 31. "TSL15,Timestamp Lost" "0,1" bitfld.long 0x0 30. "TSL14,Timestamp Lost" "0,1" newline bitfld.long 0x0 29. "TSL13,Timestamp Lost" "0,1" bitfld.long 0x0 28. "TSL12,Timestamp Lost" "0,1" newline bitfld.long 0x0 27. "TSL11,Timestamp Lost" "0,1" bitfld.long 0x0 26. "TSL10,Timestamp Lost" "0,1" newline bitfld.long 0x0 25. "TSL9,Timestamp Lost" "0,1" bitfld.long 0x0 24. "TSL8,Timestamp Lost" "0,1" newline bitfld.long 0x0 23. "TSL7,Timestamp Lost" "0,1" bitfld.long 0x0 22. "TSL6,Timestamp Lost" "0,1" newline bitfld.long 0x0 21. "TSL5,Timestamp Lost" "0,1" bitfld.long 0x0 20. "TSL4,Timestamp Lost" "0,1" newline bitfld.long 0x0 19. "TSL3,Timestamp Lost" "0,1" bitfld.long 0x0 18. "TSL2,Timestamp Lost" "0,1" newline bitfld.long 0x0 17. "TSL1,Timestamp Lost" "0,1" bitfld.long 0x0 16. "TSL0,Timestamp Lost" "0,1" newline bitfld.long 0x0 15. "TSN15,Timestamp New" "0,1" bitfld.long 0x0 14. "TSN14,Timestamp New" "0,1" newline bitfld.long 0x0 13. "TSN13,Timestamp New" "0,1" bitfld.long 0x0 12. "TSN12,Timestamp New" "0,1" newline bitfld.long 0x0 11. "TSN11,Timestamp New" "0,1" bitfld.long 0x0 10. "TSN10,Timestamp New" "0,1" newline bitfld.long 0x0 9. "TSN9,Timestamp New" "0,1" bitfld.long 0x0 8. "TSN8,Timestamp New" "0,1" newline bitfld.long 0x0 7. "TSN7,Timestamp New" "0,1" bitfld.long 0x0 6. "TSN6,Timestamp New" "0,1" newline bitfld.long 0x0 5. "TSN5,Timestamp New" "0,1" bitfld.long 0x0 4. "TSN4,Timestamp New" "0,1" newline bitfld.long 0x0 3. "TSN3,Timestamp New" "0,1" bitfld.long 0x0 2. "TSN2,Timestamp New" "0,1" newline bitfld.long 0x0 1. "TSN1,Timestamp New" "0,1" bitfld.long 0x0 0. "TSN0,Timestamp New" "0,1" rgroup.long 0x16C++0x43 line.long 0x0 "TSS2,Timestamp Status 2 register" bitfld.long 0x0 14.--15. "ITBG,Internal Timebase and SOF select Generic" "0: no SOF option no internal timebase,1: no SOF option internal timebase (default),2: SOF option no internal timebase,3: SOF option internal timebase" bitfld.long 0x0 12.--13. "NTSG,Number of Timestamps Generic" "0: 4 timestamp registers TS0-TS3,1: 8 timestamp registers TS0-TS7 (default),2: 16 timestamp registers TS0-TS15,3: not a valid value" newline hexmask.long.byte 0x0 0.--3. 1. "TSP,Timestamp Pointer" line.long 0x4 "TS0,Timestamp 0 register" hexmask.long 0x4 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x8 "TS1,Timestamp 1 register" hexmask.long 0x8 0.--31. 1. "TS,Timestamp Word TSn" line.long 0xC "TS2,Timestamp 2 register" hexmask.long 0xC 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x10 "TS3,Timestamp 3 register" hexmask.long 0x10 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x14 "TS4,Timestamp 4 register" hexmask.long 0x14 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x18 "TS5,Timestamp 5 register" hexmask.long 0x18 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x1C "TS6,Timestamp 6 register" hexmask.long 0x1C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x20 "TS7,Timestamp 7 register" hexmask.long 0x20 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x24 "TS8,Timestamp 8 register" hexmask.long 0x24 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x28 "TS9,Timestamp 9 register" hexmask.long 0x28 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x2C "TS10,Timestamp 10 register" hexmask.long 0x2C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x30 "TS11,Timestamp 11 register" hexmask.long 0x30 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x34 "TS12,Timestamp 12 register" hexmask.long 0x34 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x38 "TS13,Timestamp 13 register" hexmask.long 0x38 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x3C "TS14,Timestamp 14 register" hexmask.long 0x3C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x40 "TS15,Timestamp 15 register" hexmask.long 0x40 0.--31. 1. "TS,Timestamp Word TSn" group.long 0x1B0++0x3 line.long 0x0 "ATB,Actual Timebase" hexmask.long 0x0 0.--31. 1. "TB,Timebase for timestamp generation" tree.end tree "CAN_SUB_1_TSU_4" base ad:0x70810000 rgroup.long 0x160++0x7 line.long 0x0 "CREL,Core Release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "TSCFG,Timestamp Configuration register" hexmask.long.byte 0x4 8.--15. 1. "TBPRE,TBPRE" bitfld.long 0x4 2. "SCP,Select Capturing Position" "0: Capture Timestamp at EOF,1: Capture Timestamp at SOF" newline bitfld.long 0x4 1. "TBCS,Timebase Counter Select" "0: Timestamp value captured from internal timebase..,1: : Timestamp value captured from input.." bitfld.long 0x4 0. "TSUE,Timestamp Unit Enable 0" "0: TSU disabled,1: TSU enabled" group.long 0x168++0x3 line.long 0x0 "TSS1,Timestamp Status 1 register" bitfld.long 0x0 31. "TSL15,Timestamp Lost" "0,1" bitfld.long 0x0 30. "TSL14,Timestamp Lost" "0,1" newline bitfld.long 0x0 29. "TSL13,Timestamp Lost" "0,1" bitfld.long 0x0 28. "TSL12,Timestamp Lost" "0,1" newline bitfld.long 0x0 27. "TSL11,Timestamp Lost" "0,1" bitfld.long 0x0 26. "TSL10,Timestamp Lost" "0,1" newline bitfld.long 0x0 25. "TSL9,Timestamp Lost" "0,1" bitfld.long 0x0 24. "TSL8,Timestamp Lost" "0,1" newline bitfld.long 0x0 23. "TSL7,Timestamp Lost" "0,1" bitfld.long 0x0 22. "TSL6,Timestamp Lost" "0,1" newline bitfld.long 0x0 21. "TSL5,Timestamp Lost" "0,1" bitfld.long 0x0 20. "TSL4,Timestamp Lost" "0,1" newline bitfld.long 0x0 19. "TSL3,Timestamp Lost" "0,1" bitfld.long 0x0 18. "TSL2,Timestamp Lost" "0,1" newline bitfld.long 0x0 17. "TSL1,Timestamp Lost" "0,1" bitfld.long 0x0 16. "TSL0,Timestamp Lost" "0,1" newline bitfld.long 0x0 15. "TSN15,Timestamp New" "0,1" bitfld.long 0x0 14. "TSN14,Timestamp New" "0,1" newline bitfld.long 0x0 13. "TSN13,Timestamp New" "0,1" bitfld.long 0x0 12. "TSN12,Timestamp New" "0,1" newline bitfld.long 0x0 11. "TSN11,Timestamp New" "0,1" bitfld.long 0x0 10. "TSN10,Timestamp New" "0,1" newline bitfld.long 0x0 9. "TSN9,Timestamp New" "0,1" bitfld.long 0x0 8. "TSN8,Timestamp New" "0,1" newline bitfld.long 0x0 7. "TSN7,Timestamp New" "0,1" bitfld.long 0x0 6. "TSN6,Timestamp New" "0,1" newline bitfld.long 0x0 5. "TSN5,Timestamp New" "0,1" bitfld.long 0x0 4. "TSN4,Timestamp New" "0,1" newline bitfld.long 0x0 3. "TSN3,Timestamp New" "0,1" bitfld.long 0x0 2. "TSN2,Timestamp New" "0,1" newline bitfld.long 0x0 1. "TSN1,Timestamp New" "0,1" bitfld.long 0x0 0. "TSN0,Timestamp New" "0,1" rgroup.long 0x16C++0x43 line.long 0x0 "TSS2,Timestamp Status 2 register" bitfld.long 0x0 14.--15. "ITBG,Internal Timebase and SOF select Generic" "0: no SOF option no internal timebase,1: no SOF option internal timebase (default),2: SOF option no internal timebase,3: SOF option internal timebase" bitfld.long 0x0 12.--13. "NTSG,Number of Timestamps Generic" "0: 4 timestamp registers TS0-TS3,1: 8 timestamp registers TS0-TS7 (default),2: 16 timestamp registers TS0-TS15,3: not a valid value" newline hexmask.long.byte 0x0 0.--3. 1. "TSP,Timestamp Pointer" line.long 0x4 "TS0,Timestamp 0 register" hexmask.long 0x4 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x8 "TS1,Timestamp 1 register" hexmask.long 0x8 0.--31. 1. "TS,Timestamp Word TSn" line.long 0xC "TS2,Timestamp 2 register" hexmask.long 0xC 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x10 "TS3,Timestamp 3 register" hexmask.long 0x10 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x14 "TS4,Timestamp 4 register" hexmask.long 0x14 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x18 "TS5,Timestamp 5 register" hexmask.long 0x18 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x1C "TS6,Timestamp 6 register" hexmask.long 0x1C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x20 "TS7,Timestamp 7 register" hexmask.long 0x20 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x24 "TS8,Timestamp 8 register" hexmask.long 0x24 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x28 "TS9,Timestamp 9 register" hexmask.long 0x28 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x2C "TS10,Timestamp 10 register" hexmask.long 0x2C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x30 "TS11,Timestamp 11 register" hexmask.long 0x30 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x34 "TS12,Timestamp 12 register" hexmask.long 0x34 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x38 "TS13,Timestamp 13 register" hexmask.long 0x38 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x3C "TS14,Timestamp 14 register" hexmask.long 0x3C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x40 "TS15,Timestamp 15 register" hexmask.long 0x40 0.--31. 1. "TS,Timestamp Word TSn" group.long 0x1B0++0x3 line.long 0x0 "ATB,Actual Timebase" hexmask.long 0x0 0.--31. 1. "TB,Timebase for timestamp generation" tree.end tree.end tree "CAN_SUB_2" tree "CAN_SUB_2_DMU_1" base ad:0x70230000 rgroup.long 0x3C0++0x3 line.long 0x0 "DMUCR,DMU Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" group.long 0x3C4++0x13 line.long 0x0 "DMUI,DMU Internals register" bitfld.long 0x0 31. "TXE,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 30. "RX1,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 29. "RX0,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 28. "TX,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 24.--26. "EHS,Element Handler State" "0: wait for bit M_CAN:CCCR.CCE getting zero,1: wait for Start Address,2: wait for Trigger Address,3: wait for transfer of Element word,4: acknowledge to M_CAN,5: exception recovery,?,?" bitfld.long 0x0 23. "DTXE,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 22. "DTX1,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 21. "DTX0,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 20. "DTX,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 16.--18. "DEHS,Detect Element Handler State" "?,?,?,?,?,?,?,7: unused state" newline bitfld.long 0x0 15. "ENA,DMU is enabled" "0: DMU is disabled,1: DMU is enabled and can process DMA data" hexmask.long.byte 0x0 8.--12. 1. "TFQPIP,TX FIFO/Queue Put Index Previous" newline bitfld.long 0x0 3. "TXER,TX Event Service Request line of DMU" "0: No TX Event DMA service requested,1: TX Event DMA Service requested" bitfld.long 0x0 2. "RX1R,RX1 Service Request line of DMU" "0: No RX1 DMA service requested,1: RX1 DMA Service requested" newline bitfld.long 0x0 1. "RX0R,RX0 Service Request line of DMU" "0: No RX0 DMA service requested,1: RX0 DMA Service requested" bitfld.long 0x0 0. "TXR,TX Service Request line of DMU" "0: No TX DMA service requested,1: TX DMA Service requested" line.long 0x4 "DMUQC,DMU Queuing Counter register" hexmask.long.byte 0x4 24.--31. 1. "TXEEDC,TX Event Element Dequeuing Counter" hexmask.long.byte 0x4 16.--23. 1. "RX1EDC,RX1 Element Dequeuing Counter" newline hexmask.long.byte 0x4 8.--15. 1. "RX0EDC,RX0 Element Dequeuing Counter" hexmask.long.byte 0x4 0.--7. 1. "TXEEC,TX Element Enqueuing Counter" line.long 0x8 "DMUIR,DMU Interrupt Register" bitfld.long 0x8 30. "IAC,Illegal Access while in Configuration mode" "0: No Illegal Access while CCE mode,1: Illegal Access while CCE mode" bitfld.long 0x8 29. "DT,Debug Trigger" "0: Debug point not reached,1: Debug point reached" newline bitfld.long 0x8 28. "TXEED,TX Event Element Dequeued" "0: No TX Event Element dequeued,1: TX Event Element successfully dequeued" bitfld.long 0x8 27. "TXEEIW,TX Event Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU TX Event Element.." newline bitfld.long 0x8 26. "TXEEIAS,TX Event Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 25. "TXEEID,TX Event Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 24. "TXEENSA,TX Event Element Not Start Address" "0: No illegal read access,1: Read from TX Event Element begins without using.." bitfld.long 0x8 21. "RX1EIO,RX1 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 20. "RX1ED,RX1 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 19. "RX1EIW,RX1 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 18. "RX1EIAS,RX1 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 17. "RX1EID,RX1 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 16. "RX1ENSA,RX1 Element Not Start Address" "0: No illegal read access,1: Read from RX1 Element begins without using start.." bitfld.long 0x8 15. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Uncorrected bit error detected" newline bitfld.long 0x8 14. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected" bitfld.long 0x8 13. "RX0EIO,RX0 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 12. "RX0ED,RX0 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 11. "RX0EIW,RX0 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 10. "RX0EIAS,RX0 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 9. "RX0EID,RX0 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 8. "RX0ENSA,RX0 Element Not Start Address" "0: No illegal read access,1: Read from RX0 Element begins without using start.." bitfld.long 0x8 6. "TXEE,TX Element Enqueued" "0: No Tx message enqueued,1: Tx message successfully enqueued" newline bitfld.long 0x8 5. "TXEIR,TX Element Illegal Read" "0: No read access,1: Illegal read access to DMU TX Element section.." bitfld.long 0x8 4. "TXEWATA,TX Element Write After Trigger Address" "0: No write after Trigger Address,1: Enqueue a message" newline bitfld.long 0x8 3. "TXEIDLC,TX Element Illegal DLC" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." bitfld.long 0x8 2. "TXEIAS,TX Element Illegal Access Sequence" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." newline bitfld.long 0x8 1. "TXEIE,TX Element Illegal Enqueuing" "0: No illegal enqueuing,1: Start of enqueuing without request detected.." bitfld.long 0x8 0. "TXENSA,TX Element Not Start Address" "0: No illegal write access,1: Write to TX Element begins without using start.." line.long 0xC "DMUIE,DMU Interrupt Enable register" bitfld.long 0xC 30. "IACE,Illegal Access while in Configuration mode Enable" "0: Flag DMUIR.IAC does not activate the interrupt..,1: If DMUIR.IAC = 1 the interrupt line dmu_int will.." bitfld.long 0xC 29. "DTE,Debug Trigger Enable" "0: Flag DMUIR.DT does not activate the interrupt..,1: If DMUIR.DT = 1 the interrupt line dmu_int will.." newline bitfld.long 0xC 28. "TXEEDE,TX Event Element Dequeued" "0: Flag DMUIR.TXEED does not activate the interrupt..,1: If DMUIR.TXEED = 1 the interrupt line dmu_int.." bitfld.long 0xC 27. "TXEEIWE,TX Event Element Illegal Write" "0: Flag DMUIR.TXEEIW does not activate the..,1: If DMUIR.TXEEIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 26. "TXEEIASE,TX Event Element Illegal Access Sequence" "0: Flag DMUIR.TXEEIAS does not activate the..,1: If DMUIR.TXEEIAS = 1 the interrupt line dmu_int.." bitfld.long 0xC 25. "TXEEIDE,TX Event Element Illegal Dequeuing" "0: Flag DMUIR.TXEEID does not activate the..,1: If DMUIR.TXEEID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 24. "TXEENSAE,TX Event Element Not Start Address" "0: Flag TXEENSA.TXEENSA does not activate the..,1: If TXEENSA.TXEENSA = 1 the interrupt line.." bitfld.long 0xC 21. "RX1EIOE,RX1 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX1EIO does not activate the..,1: If TXEENSA.RX1EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 20. "RX1EDE,RX1 Element Dequeued Enable" "0: Flag TXEENSA.RX1ED does not activate the..,1: If TXEENSA.RX1ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 19. "RX1EIWE,RX1 Element Illegal Write Enable" "0: Flag TXEENSA.RX1EIW does not activate the..,1: If TXEENSA.RX1EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 18. "RX1EIASE,RX1 Element Illegal Access Sequence Enable" "0: Flag TXEENSA.RX1EIAS does not activate the..,1: If TXEENSA.RX1EIAS = 1 the interrupt line.." bitfld.long 0xC 17. "RX1EIDE,RX1 Element Illegal Dequeuing Enable" "0: Flag TXEENSA.RX1EID does not activate the..,1: If TXEENSA.RX1EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 16. "RX1ENSAE,RX1 Element Not Start Address Enable" "0: Flag TXEENSA.RX1ENSA does not activate the..,1: If TXEENSA.RX1ENSA = 1 the interrupt line.." bitfld.long 0xC 15. "BEUE,Bit Error Uncorrected Enable" "0: Flag TXEENSA.BEU does not activate the interrupt..,1: If TXEENSA.BEU = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 14. "BECE,Bit Error Corrected Enable" "0: Flag TXEENSA.BEC does not activate the interrupt..,1: If TXEENSA.BEC = 1 the interrupt line dmu_int.." bitfld.long 0xC 13. "RX0EIOE,RX0 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX0EIO does not activate the..,1: If TXEENSA.RX0EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 12. "RX0EDE,RX0 Element Dequeued Enabled" "0: Flag TXEENSA.RX0ED does not activate the..,1: If TXEENSA.RX0ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 11. "RX0EIWE,RX0 Element Illegal Write Enabled" "0: Flag TXEENSA.RX0EIW does not activate the..,1: If TXEENSA.RX0EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 10. "RX0EIASE,RX0 Element Illegal Access Sequence Enabled" "0: Flag TXEENSA.RX0EIAS does not activate the..,1: If TXEENSA.RX0EIAS = 1 the interrupt line.." bitfld.long 0xC 9. "RX0EIDE,RX0 Element Illegal Dequeuing Enabled" "0: Flag TXEENSA.RX0EID does not activate the..,1: If TXEENSA.RX0EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 8. "RX0ENSAE,RX0 Element Not Start Address Enabled" "0: Flag TXEENSA.RX0ENSA does not activate the..,1: If TXEENSA.RX0ENSA = 1 the interrupt line.." bitfld.long 0xC 6. "TXEEE,TX Element Enqueued Enable" "0: Flag TXEENSA.TXEE does not activate the..,1: If TXEENSA.TXEE = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 5. "TXEIRE,TX Element Illegal Read Enable" "0: Flag TXEENSA.TXEIR does not activate the..,1: If TXEENSA.TXEIR = 1 the interrupt line dmu_int.." bitfld.long 0xC 4. "TXEWATAE,TX Element Write After Trigger Address Enable" "0: Flag TXEENSA.TXEWATA does not activate the..,1: If TXEENSA.TXEWATA = 1 the interrupt line.." newline bitfld.long 0xC 3. "TXEIDLCE,TX Element Illegal DLC Enable" "0: Flag TXEENSA.TXEIDLC does not activate the..,1: If TXEENSA.TXEIDLC = 1 the interrupt line.." bitfld.long 0xC 2. "TXEIASE,TX Element Illegal Access Sequence Enable" "0: Flag TXEENSA.TXEIAS does not activate the..,1: If TXEENSA.TXEIAS = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 1. "TXEIEE,TX Element Illegal Enqueuing Enable" "0: Flag TXEENSA.TXEIE does not activate the..,1: If TXEENSA.TXEIE = 1 the interrupt line dmu_int.." bitfld.long 0xC 0. "TXENSAE,TX Element Not Start Address Enable" "0: Flag DMUIR.TXENSA does not activate the..,1: If DMUIR.TXENSA = 1 the interrupt line dmu_int.." line.long 0x10 "DMUC,DMU Configuration register" bitfld.long 0x10 0. "TTS,Transfer Timestamp" "0: No timestamp will be transferred via DMU Virtual..,1: Timestamp of message will be transferred from.." tree.end tree "CAN_SUB_2_DMU_2" base ad:0x70234000 rgroup.long 0x3C0++0x3 line.long 0x0 "DMUCR,DMU Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" group.long 0x3C4++0x13 line.long 0x0 "DMUI,DMU Internals register" bitfld.long 0x0 31. "TXE,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 30. "RX1,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 29. "RX0,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 28. "TX,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 24.--26. "EHS,Element Handler State" "0: wait for bit M_CAN:CCCR.CCE getting zero,1: wait for Start Address,2: wait for Trigger Address,3: wait for transfer of Element word,4: acknowledge to M_CAN,5: exception recovery,?,?" bitfld.long 0x0 23. "DTXE,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 22. "DTX1,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 21. "DTX0,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 20. "DTX,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 16.--18. "DEHS,Detect Element Handler State" "?,?,?,?,?,?,?,7: unused state" newline bitfld.long 0x0 15. "ENA,DMU is enabled" "0: DMU is disabled,1: DMU is enabled and can process DMA data" hexmask.long.byte 0x0 8.--12. 1. "TFQPIP,TX FIFO/Queue Put Index Previous" newline bitfld.long 0x0 3. "TXER,TX Event Service Request line of DMU" "0: No TX Event DMA service requested,1: TX Event DMA Service requested" bitfld.long 0x0 2. "RX1R,RX1 Service Request line of DMU" "0: No RX1 DMA service requested,1: RX1 DMA Service requested" newline bitfld.long 0x0 1. "RX0R,RX0 Service Request line of DMU" "0: No RX0 DMA service requested,1: RX0 DMA Service requested" bitfld.long 0x0 0. "TXR,TX Service Request line of DMU" "0: No TX DMA service requested,1: TX DMA Service requested" line.long 0x4 "DMUQC,DMU Queuing Counter register" hexmask.long.byte 0x4 24.--31. 1. "TXEEDC,TX Event Element Dequeuing Counter" hexmask.long.byte 0x4 16.--23. 1. "RX1EDC,RX1 Element Dequeuing Counter" newline hexmask.long.byte 0x4 8.--15. 1. "RX0EDC,RX0 Element Dequeuing Counter" hexmask.long.byte 0x4 0.--7. 1. "TXEEC,TX Element Enqueuing Counter" line.long 0x8 "DMUIR,DMU Interrupt Register" bitfld.long 0x8 30. "IAC,Illegal Access while in Configuration mode" "0: No Illegal Access while CCE mode,1: Illegal Access while CCE mode" bitfld.long 0x8 29. "DT,Debug Trigger" "0: Debug point not reached,1: Debug point reached" newline bitfld.long 0x8 28. "TXEED,TX Event Element Dequeued" "0: No TX Event Element dequeued,1: TX Event Element successfully dequeued" bitfld.long 0x8 27. "TXEEIW,TX Event Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU TX Event Element.." newline bitfld.long 0x8 26. "TXEEIAS,TX Event Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 25. "TXEEID,TX Event Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 24. "TXEENSA,TX Event Element Not Start Address" "0: No illegal read access,1: Read from TX Event Element begins without using.." bitfld.long 0x8 21. "RX1EIO,RX1 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 20. "RX1ED,RX1 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 19. "RX1EIW,RX1 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 18. "RX1EIAS,RX1 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 17. "RX1EID,RX1 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 16. "RX1ENSA,RX1 Element Not Start Address" "0: No illegal read access,1: Read from RX1 Element begins without using start.." bitfld.long 0x8 15. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Uncorrected bit error detected" newline bitfld.long 0x8 14. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected" bitfld.long 0x8 13. "RX0EIO,RX0 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 12. "RX0ED,RX0 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 11. "RX0EIW,RX0 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 10. "RX0EIAS,RX0 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 9. "RX0EID,RX0 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 8. "RX0ENSA,RX0 Element Not Start Address" "0: No illegal read access,1: Read from RX0 Element begins without using start.." bitfld.long 0x8 6. "TXEE,TX Element Enqueued" "0: No Tx message enqueued,1: Tx message successfully enqueued" newline bitfld.long 0x8 5. "TXEIR,TX Element Illegal Read" "0: No read access,1: Illegal read access to DMU TX Element section.." bitfld.long 0x8 4. "TXEWATA,TX Element Write After Trigger Address" "0: No write after Trigger Address,1: Enqueue a message" newline bitfld.long 0x8 3. "TXEIDLC,TX Element Illegal DLC" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." bitfld.long 0x8 2. "TXEIAS,TX Element Illegal Access Sequence" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." newline bitfld.long 0x8 1. "TXEIE,TX Element Illegal Enqueuing" "0: No illegal enqueuing,1: Start of enqueuing without request detected.." bitfld.long 0x8 0. "TXENSA,TX Element Not Start Address" "0: No illegal write access,1: Write to TX Element begins without using start.." line.long 0xC "DMUIE,DMU Interrupt Enable register" bitfld.long 0xC 30. "IACE,Illegal Access while in Configuration mode Enable" "0: Flag DMUIR.IAC does not activate the interrupt..,1: If DMUIR.IAC = 1 the interrupt line dmu_int will.." bitfld.long 0xC 29. "DTE,Debug Trigger Enable" "0: Flag DMUIR.DT does not activate the interrupt..,1: If DMUIR.DT = 1 the interrupt line dmu_int will.." newline bitfld.long 0xC 28. "TXEEDE,TX Event Element Dequeued" "0: Flag DMUIR.TXEED does not activate the interrupt..,1: If DMUIR.TXEED = 1 the interrupt line dmu_int.." bitfld.long 0xC 27. "TXEEIWE,TX Event Element Illegal Write" "0: Flag DMUIR.TXEEIW does not activate the..,1: If DMUIR.TXEEIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 26. "TXEEIASE,TX Event Element Illegal Access Sequence" "0: Flag DMUIR.TXEEIAS does not activate the..,1: If DMUIR.TXEEIAS = 1 the interrupt line dmu_int.." bitfld.long 0xC 25. "TXEEIDE,TX Event Element Illegal Dequeuing" "0: Flag DMUIR.TXEEID does not activate the..,1: If DMUIR.TXEEID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 24. "TXEENSAE,TX Event Element Not Start Address" "0: Flag TXEENSA.TXEENSA does not activate the..,1: If TXEENSA.TXEENSA = 1 the interrupt line.." bitfld.long 0xC 21. "RX1EIOE,RX1 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX1EIO does not activate the..,1: If TXEENSA.RX1EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 20. "RX1EDE,RX1 Element Dequeued Enable" "0: Flag TXEENSA.RX1ED does not activate the..,1: If TXEENSA.RX1ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 19. "RX1EIWE,RX1 Element Illegal Write Enable" "0: Flag TXEENSA.RX1EIW does not activate the..,1: If TXEENSA.RX1EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 18. "RX1EIASE,RX1 Element Illegal Access Sequence Enable" "0: Flag TXEENSA.RX1EIAS does not activate the..,1: If TXEENSA.RX1EIAS = 1 the interrupt line.." bitfld.long 0xC 17. "RX1EIDE,RX1 Element Illegal Dequeuing Enable" "0: Flag TXEENSA.RX1EID does not activate the..,1: If TXEENSA.RX1EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 16. "RX1ENSAE,RX1 Element Not Start Address Enable" "0: Flag TXEENSA.RX1ENSA does not activate the..,1: If TXEENSA.RX1ENSA = 1 the interrupt line.." bitfld.long 0xC 15. "BEUE,Bit Error Uncorrected Enable" "0: Flag TXEENSA.BEU does not activate the interrupt..,1: If TXEENSA.BEU = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 14. "BECE,Bit Error Corrected Enable" "0: Flag TXEENSA.BEC does not activate the interrupt..,1: If TXEENSA.BEC = 1 the interrupt line dmu_int.." bitfld.long 0xC 13. "RX0EIOE,RX0 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX0EIO does not activate the..,1: If TXEENSA.RX0EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 12. "RX0EDE,RX0 Element Dequeued Enabled" "0: Flag TXEENSA.RX0ED does not activate the..,1: If TXEENSA.RX0ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 11. "RX0EIWE,RX0 Element Illegal Write Enabled" "0: Flag TXEENSA.RX0EIW does not activate the..,1: If TXEENSA.RX0EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 10. "RX0EIASE,RX0 Element Illegal Access Sequence Enabled" "0: Flag TXEENSA.RX0EIAS does not activate the..,1: If TXEENSA.RX0EIAS = 1 the interrupt line.." bitfld.long 0xC 9. "RX0EIDE,RX0 Element Illegal Dequeuing Enabled" "0: Flag TXEENSA.RX0EID does not activate the..,1: If TXEENSA.RX0EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 8. "RX0ENSAE,RX0 Element Not Start Address Enabled" "0: Flag TXEENSA.RX0ENSA does not activate the..,1: If TXEENSA.RX0ENSA = 1 the interrupt line.." bitfld.long 0xC 6. "TXEEE,TX Element Enqueued Enable" "0: Flag TXEENSA.TXEE does not activate the..,1: If TXEENSA.TXEE = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 5. "TXEIRE,TX Element Illegal Read Enable" "0: Flag TXEENSA.TXEIR does not activate the..,1: If TXEENSA.TXEIR = 1 the interrupt line dmu_int.." bitfld.long 0xC 4. "TXEWATAE,TX Element Write After Trigger Address Enable" "0: Flag TXEENSA.TXEWATA does not activate the..,1: If TXEENSA.TXEWATA = 1 the interrupt line.." newline bitfld.long 0xC 3. "TXEIDLCE,TX Element Illegal DLC Enable" "0: Flag TXEENSA.TXEIDLC does not activate the..,1: If TXEENSA.TXEIDLC = 1 the interrupt line.." bitfld.long 0xC 2. "TXEIASE,TX Element Illegal Access Sequence Enable" "0: Flag TXEENSA.TXEIAS does not activate the..,1: If TXEENSA.TXEIAS = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 1. "TXEIEE,TX Element Illegal Enqueuing Enable" "0: Flag TXEENSA.TXEIE does not activate the..,1: If TXEENSA.TXEIE = 1 the interrupt line dmu_int.." bitfld.long 0xC 0. "TXENSAE,TX Element Not Start Address Enable" "0: Flag DMUIR.TXENSA does not activate the..,1: If DMUIR.TXENSA = 1 the interrupt line dmu_int.." line.long 0x10 "DMUC,DMU Configuration register" bitfld.long 0x10 0. "TTS,Transfer Timestamp" "0: No timestamp will be transferred via DMU Virtual..,1: Timestamp of message will be transferred from.." tree.end tree "CAN_SUB_2_DMU_3" base ad:0x70238000 rgroup.long 0x3C0++0x3 line.long 0x0 "DMUCR,DMU Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" group.long 0x3C4++0x13 line.long 0x0 "DMUI,DMU Internals register" bitfld.long 0x0 31. "TXE,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 30. "RX1,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 29. "RX0,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 28. "TX,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 24.--26. "EHS,Element Handler State" "0: wait for bit M_CAN:CCCR.CCE getting zero,1: wait for Start Address,2: wait for Trigger Address,3: wait for transfer of Element word,4: acknowledge to M_CAN,5: exception recovery,?,?" bitfld.long 0x0 23. "DTXE,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 22. "DTX1,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 21. "DTX0,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 20. "DTX,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 16.--18. "DEHS,Detect Element Handler State" "?,?,?,?,?,?,?,7: unused state" newline bitfld.long 0x0 15. "ENA,DMU is enabled" "0: DMU is disabled,1: DMU is enabled and can process DMA data" hexmask.long.byte 0x0 8.--12. 1. "TFQPIP,TX FIFO/Queue Put Index Previous" newline bitfld.long 0x0 3. "TXER,TX Event Service Request line of DMU" "0: No TX Event DMA service requested,1: TX Event DMA Service requested" bitfld.long 0x0 2. "RX1R,RX1 Service Request line of DMU" "0: No RX1 DMA service requested,1: RX1 DMA Service requested" newline bitfld.long 0x0 1. "RX0R,RX0 Service Request line of DMU" "0: No RX0 DMA service requested,1: RX0 DMA Service requested" bitfld.long 0x0 0. "TXR,TX Service Request line of DMU" "0: No TX DMA service requested,1: TX DMA Service requested" line.long 0x4 "DMUQC,DMU Queuing Counter register" hexmask.long.byte 0x4 24.--31. 1. "TXEEDC,TX Event Element Dequeuing Counter" hexmask.long.byte 0x4 16.--23. 1. "RX1EDC,RX1 Element Dequeuing Counter" newline hexmask.long.byte 0x4 8.--15. 1. "RX0EDC,RX0 Element Dequeuing Counter" hexmask.long.byte 0x4 0.--7. 1. "TXEEC,TX Element Enqueuing Counter" line.long 0x8 "DMUIR,DMU Interrupt Register" bitfld.long 0x8 30. "IAC,Illegal Access while in Configuration mode" "0: No Illegal Access while CCE mode,1: Illegal Access while CCE mode" bitfld.long 0x8 29. "DT,Debug Trigger" "0: Debug point not reached,1: Debug point reached" newline bitfld.long 0x8 28. "TXEED,TX Event Element Dequeued" "0: No TX Event Element dequeued,1: TX Event Element successfully dequeued" bitfld.long 0x8 27. "TXEEIW,TX Event Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU TX Event Element.." newline bitfld.long 0x8 26. "TXEEIAS,TX Event Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 25. "TXEEID,TX Event Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 24. "TXEENSA,TX Event Element Not Start Address" "0: No illegal read access,1: Read from TX Event Element begins without using.." bitfld.long 0x8 21. "RX1EIO,RX1 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 20. "RX1ED,RX1 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 19. "RX1EIW,RX1 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 18. "RX1EIAS,RX1 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 17. "RX1EID,RX1 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 16. "RX1ENSA,RX1 Element Not Start Address" "0: No illegal read access,1: Read from RX1 Element begins without using start.." bitfld.long 0x8 15. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Uncorrected bit error detected" newline bitfld.long 0x8 14. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected" bitfld.long 0x8 13. "RX0EIO,RX0 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 12. "RX0ED,RX0 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 11. "RX0EIW,RX0 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 10. "RX0EIAS,RX0 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 9. "RX0EID,RX0 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 8. "RX0ENSA,RX0 Element Not Start Address" "0: No illegal read access,1: Read from RX0 Element begins without using start.." bitfld.long 0x8 6. "TXEE,TX Element Enqueued" "0: No Tx message enqueued,1: Tx message successfully enqueued" newline bitfld.long 0x8 5. "TXEIR,TX Element Illegal Read" "0: No read access,1: Illegal read access to DMU TX Element section.." bitfld.long 0x8 4. "TXEWATA,TX Element Write After Trigger Address" "0: No write after Trigger Address,1: Enqueue a message" newline bitfld.long 0x8 3. "TXEIDLC,TX Element Illegal DLC" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." bitfld.long 0x8 2. "TXEIAS,TX Element Illegal Access Sequence" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." newline bitfld.long 0x8 1. "TXEIE,TX Element Illegal Enqueuing" "0: No illegal enqueuing,1: Start of enqueuing without request detected.." bitfld.long 0x8 0. "TXENSA,TX Element Not Start Address" "0: No illegal write access,1: Write to TX Element begins without using start.." line.long 0xC "DMUIE,DMU Interrupt Enable register" bitfld.long 0xC 30. "IACE,Illegal Access while in Configuration mode Enable" "0: Flag DMUIR.IAC does not activate the interrupt..,1: If DMUIR.IAC = 1 the interrupt line dmu_int will.." bitfld.long 0xC 29. "DTE,Debug Trigger Enable" "0: Flag DMUIR.DT does not activate the interrupt..,1: If DMUIR.DT = 1 the interrupt line dmu_int will.." newline bitfld.long 0xC 28. "TXEEDE,TX Event Element Dequeued" "0: Flag DMUIR.TXEED does not activate the interrupt..,1: If DMUIR.TXEED = 1 the interrupt line dmu_int.." bitfld.long 0xC 27. "TXEEIWE,TX Event Element Illegal Write" "0: Flag DMUIR.TXEEIW does not activate the..,1: If DMUIR.TXEEIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 26. "TXEEIASE,TX Event Element Illegal Access Sequence" "0: Flag DMUIR.TXEEIAS does not activate the..,1: If DMUIR.TXEEIAS = 1 the interrupt line dmu_int.." bitfld.long 0xC 25. "TXEEIDE,TX Event Element Illegal Dequeuing" "0: Flag DMUIR.TXEEID does not activate the..,1: If DMUIR.TXEEID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 24. "TXEENSAE,TX Event Element Not Start Address" "0: Flag TXEENSA.TXEENSA does not activate the..,1: If TXEENSA.TXEENSA = 1 the interrupt line.." bitfld.long 0xC 21. "RX1EIOE,RX1 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX1EIO does not activate the..,1: If TXEENSA.RX1EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 20. "RX1EDE,RX1 Element Dequeued Enable" "0: Flag TXEENSA.RX1ED does not activate the..,1: If TXEENSA.RX1ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 19. "RX1EIWE,RX1 Element Illegal Write Enable" "0: Flag TXEENSA.RX1EIW does not activate the..,1: If TXEENSA.RX1EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 18. "RX1EIASE,RX1 Element Illegal Access Sequence Enable" "0: Flag TXEENSA.RX1EIAS does not activate the..,1: If TXEENSA.RX1EIAS = 1 the interrupt line.." bitfld.long 0xC 17. "RX1EIDE,RX1 Element Illegal Dequeuing Enable" "0: Flag TXEENSA.RX1EID does not activate the..,1: If TXEENSA.RX1EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 16. "RX1ENSAE,RX1 Element Not Start Address Enable" "0: Flag TXEENSA.RX1ENSA does not activate the..,1: If TXEENSA.RX1ENSA = 1 the interrupt line.." bitfld.long 0xC 15. "BEUE,Bit Error Uncorrected Enable" "0: Flag TXEENSA.BEU does not activate the interrupt..,1: If TXEENSA.BEU = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 14. "BECE,Bit Error Corrected Enable" "0: Flag TXEENSA.BEC does not activate the interrupt..,1: If TXEENSA.BEC = 1 the interrupt line dmu_int.." bitfld.long 0xC 13. "RX0EIOE,RX0 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX0EIO does not activate the..,1: If TXEENSA.RX0EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 12. "RX0EDE,RX0 Element Dequeued Enabled" "0: Flag TXEENSA.RX0ED does not activate the..,1: If TXEENSA.RX0ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 11. "RX0EIWE,RX0 Element Illegal Write Enabled" "0: Flag TXEENSA.RX0EIW does not activate the..,1: If TXEENSA.RX0EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 10. "RX0EIASE,RX0 Element Illegal Access Sequence Enabled" "0: Flag TXEENSA.RX0EIAS does not activate the..,1: If TXEENSA.RX0EIAS = 1 the interrupt line.." bitfld.long 0xC 9. "RX0EIDE,RX0 Element Illegal Dequeuing Enabled" "0: Flag TXEENSA.RX0EID does not activate the..,1: If TXEENSA.RX0EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 8. "RX0ENSAE,RX0 Element Not Start Address Enabled" "0: Flag TXEENSA.RX0ENSA does not activate the..,1: If TXEENSA.RX0ENSA = 1 the interrupt line.." bitfld.long 0xC 6. "TXEEE,TX Element Enqueued Enable" "0: Flag TXEENSA.TXEE does not activate the..,1: If TXEENSA.TXEE = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 5. "TXEIRE,TX Element Illegal Read Enable" "0: Flag TXEENSA.TXEIR does not activate the..,1: If TXEENSA.TXEIR = 1 the interrupt line dmu_int.." bitfld.long 0xC 4. "TXEWATAE,TX Element Write After Trigger Address Enable" "0: Flag TXEENSA.TXEWATA does not activate the..,1: If TXEENSA.TXEWATA = 1 the interrupt line.." newline bitfld.long 0xC 3. "TXEIDLCE,TX Element Illegal DLC Enable" "0: Flag TXEENSA.TXEIDLC does not activate the..,1: If TXEENSA.TXEIDLC = 1 the interrupt line.." bitfld.long 0xC 2. "TXEIASE,TX Element Illegal Access Sequence Enable" "0: Flag TXEENSA.TXEIAS does not activate the..,1: If TXEENSA.TXEIAS = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 1. "TXEIEE,TX Element Illegal Enqueuing Enable" "0: Flag TXEENSA.TXEIE does not activate the..,1: If TXEENSA.TXEIE = 1 the interrupt line dmu_int.." bitfld.long 0xC 0. "TXENSAE,TX Element Not Start Address Enable" "0: Flag DMUIR.TXENSA does not activate the..,1: If DMUIR.TXENSA = 1 the interrupt line dmu_int.." line.long 0x10 "DMUC,DMU Configuration register" bitfld.long 0x10 0. "TTS,Transfer Timestamp" "0: No timestamp will be transferred via DMU Virtual..,1: Timestamp of message will be transferred from.." tree.end tree "CAN_SUB_2_DMU_4" base ad:0x7023C000 rgroup.long 0x3C0++0x3 line.long 0x0 "DMUCR,DMU Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" group.long 0x3C4++0x13 line.long 0x0 "DMUI,DMU Internals register" bitfld.long 0x0 31. "TXE,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 30. "RX1,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 29. "RX0,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 28. "TX,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 24.--26. "EHS,Element Handler State" "0: wait for bit M_CAN:CCCR.CCE getting zero,1: wait for Start Address,2: wait for Trigger Address,3: wait for transfer of Element word,4: acknowledge to M_CAN,5: exception recovery,?,?" bitfld.long 0x0 23. "DTXE,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 22. "DTX1,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 21. "DTX0,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 20. "DTX,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 16.--18. "DEHS,Detect Element Handler State" "?,?,?,?,?,?,?,7: unused state" newline bitfld.long 0x0 15. "ENA,DMU is enabled" "0: DMU is disabled,1: DMU is enabled and can process DMA data" hexmask.long.byte 0x0 8.--12. 1. "TFQPIP,TX FIFO/Queue Put Index Previous" newline bitfld.long 0x0 3. "TXER,TX Event Service Request line of DMU" "0: No TX Event DMA service requested,1: TX Event DMA Service requested" bitfld.long 0x0 2. "RX1R,RX1 Service Request line of DMU" "0: No RX1 DMA service requested,1: RX1 DMA Service requested" newline bitfld.long 0x0 1. "RX0R,RX0 Service Request line of DMU" "0: No RX0 DMA service requested,1: RX0 DMA Service requested" bitfld.long 0x0 0. "TXR,TX Service Request line of DMU" "0: No TX DMA service requested,1: TX DMA Service requested" line.long 0x4 "DMUQC,DMU Queuing Counter register" hexmask.long.byte 0x4 24.--31. 1. "TXEEDC,TX Event Element Dequeuing Counter" hexmask.long.byte 0x4 16.--23. 1. "RX1EDC,RX1 Element Dequeuing Counter" newline hexmask.long.byte 0x4 8.--15. 1. "RX0EDC,RX0 Element Dequeuing Counter" hexmask.long.byte 0x4 0.--7. 1. "TXEEC,TX Element Enqueuing Counter" line.long 0x8 "DMUIR,DMU Interrupt Register" bitfld.long 0x8 30. "IAC,Illegal Access while in Configuration mode" "0: No Illegal Access while CCE mode,1: Illegal Access while CCE mode" bitfld.long 0x8 29. "DT,Debug Trigger" "0: Debug point not reached,1: Debug point reached" newline bitfld.long 0x8 28. "TXEED,TX Event Element Dequeued" "0: No TX Event Element dequeued,1: TX Event Element successfully dequeued" bitfld.long 0x8 27. "TXEEIW,TX Event Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU TX Event Element.." newline bitfld.long 0x8 26. "TXEEIAS,TX Event Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 25. "TXEEID,TX Event Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 24. "TXEENSA,TX Event Element Not Start Address" "0: No illegal read access,1: Read from TX Event Element begins without using.." bitfld.long 0x8 21. "RX1EIO,RX1 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 20. "RX1ED,RX1 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 19. "RX1EIW,RX1 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 18. "RX1EIAS,RX1 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 17. "RX1EID,RX1 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 16. "RX1ENSA,RX1 Element Not Start Address" "0: No illegal read access,1: Read from RX1 Element begins without using start.." bitfld.long 0x8 15. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Uncorrected bit error detected" newline bitfld.long 0x8 14. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected" bitfld.long 0x8 13. "RX0EIO,RX0 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 12. "RX0ED,RX0 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 11. "RX0EIW,RX0 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 10. "RX0EIAS,RX0 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 9. "RX0EID,RX0 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 8. "RX0ENSA,RX0 Element Not Start Address" "0: No illegal read access,1: Read from RX0 Element begins without using start.." bitfld.long 0x8 6. "TXEE,TX Element Enqueued" "0: No Tx message enqueued,1: Tx message successfully enqueued" newline bitfld.long 0x8 5. "TXEIR,TX Element Illegal Read" "0: No read access,1: Illegal read access to DMU TX Element section.." bitfld.long 0x8 4. "TXEWATA,TX Element Write After Trigger Address" "0: No write after Trigger Address,1: Enqueue a message" newline bitfld.long 0x8 3. "TXEIDLC,TX Element Illegal DLC" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." bitfld.long 0x8 2. "TXEIAS,TX Element Illegal Access Sequence" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." newline bitfld.long 0x8 1. "TXEIE,TX Element Illegal Enqueuing" "0: No illegal enqueuing,1: Start of enqueuing without request detected.." bitfld.long 0x8 0. "TXENSA,TX Element Not Start Address" "0: No illegal write access,1: Write to TX Element begins without using start.." line.long 0xC "DMUIE,DMU Interrupt Enable register" bitfld.long 0xC 30. "IACE,Illegal Access while in Configuration mode Enable" "0: Flag DMUIR.IAC does not activate the interrupt..,1: If DMUIR.IAC = 1 the interrupt line dmu_int will.." bitfld.long 0xC 29. "DTE,Debug Trigger Enable" "0: Flag DMUIR.DT does not activate the interrupt..,1: If DMUIR.DT = 1 the interrupt line dmu_int will.." newline bitfld.long 0xC 28. "TXEEDE,TX Event Element Dequeued" "0: Flag DMUIR.TXEED does not activate the interrupt..,1: If DMUIR.TXEED = 1 the interrupt line dmu_int.." bitfld.long 0xC 27. "TXEEIWE,TX Event Element Illegal Write" "0: Flag DMUIR.TXEEIW does not activate the..,1: If DMUIR.TXEEIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 26. "TXEEIASE,TX Event Element Illegal Access Sequence" "0: Flag DMUIR.TXEEIAS does not activate the..,1: If DMUIR.TXEEIAS = 1 the interrupt line dmu_int.." bitfld.long 0xC 25. "TXEEIDE,TX Event Element Illegal Dequeuing" "0: Flag DMUIR.TXEEID does not activate the..,1: If DMUIR.TXEEID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 24. "TXEENSAE,TX Event Element Not Start Address" "0: Flag TXEENSA.TXEENSA does not activate the..,1: If TXEENSA.TXEENSA = 1 the interrupt line.." bitfld.long 0xC 21. "RX1EIOE,RX1 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX1EIO does not activate the..,1: If TXEENSA.RX1EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 20. "RX1EDE,RX1 Element Dequeued Enable" "0: Flag TXEENSA.RX1ED does not activate the..,1: If TXEENSA.RX1ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 19. "RX1EIWE,RX1 Element Illegal Write Enable" "0: Flag TXEENSA.RX1EIW does not activate the..,1: If TXEENSA.RX1EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 18. "RX1EIASE,RX1 Element Illegal Access Sequence Enable" "0: Flag TXEENSA.RX1EIAS does not activate the..,1: If TXEENSA.RX1EIAS = 1 the interrupt line.." bitfld.long 0xC 17. "RX1EIDE,RX1 Element Illegal Dequeuing Enable" "0: Flag TXEENSA.RX1EID does not activate the..,1: If TXEENSA.RX1EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 16. "RX1ENSAE,RX1 Element Not Start Address Enable" "0: Flag TXEENSA.RX1ENSA does not activate the..,1: If TXEENSA.RX1ENSA = 1 the interrupt line.." bitfld.long 0xC 15. "BEUE,Bit Error Uncorrected Enable" "0: Flag TXEENSA.BEU does not activate the interrupt..,1: If TXEENSA.BEU = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 14. "BECE,Bit Error Corrected Enable" "0: Flag TXEENSA.BEC does not activate the interrupt..,1: If TXEENSA.BEC = 1 the interrupt line dmu_int.." bitfld.long 0xC 13. "RX0EIOE,RX0 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX0EIO does not activate the..,1: If TXEENSA.RX0EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 12. "RX0EDE,RX0 Element Dequeued Enabled" "0: Flag TXEENSA.RX0ED does not activate the..,1: If TXEENSA.RX0ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 11. "RX0EIWE,RX0 Element Illegal Write Enabled" "0: Flag TXEENSA.RX0EIW does not activate the..,1: If TXEENSA.RX0EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 10. "RX0EIASE,RX0 Element Illegal Access Sequence Enabled" "0: Flag TXEENSA.RX0EIAS does not activate the..,1: If TXEENSA.RX0EIAS = 1 the interrupt line.." bitfld.long 0xC 9. "RX0EIDE,RX0 Element Illegal Dequeuing Enabled" "0: Flag TXEENSA.RX0EID does not activate the..,1: If TXEENSA.RX0EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 8. "RX0ENSAE,RX0 Element Not Start Address Enabled" "0: Flag TXEENSA.RX0ENSA does not activate the..,1: If TXEENSA.RX0ENSA = 1 the interrupt line.." bitfld.long 0xC 6. "TXEEE,TX Element Enqueued Enable" "0: Flag TXEENSA.TXEE does not activate the..,1: If TXEENSA.TXEE = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 5. "TXEIRE,TX Element Illegal Read Enable" "0: Flag TXEENSA.TXEIR does not activate the..,1: If TXEENSA.TXEIR = 1 the interrupt line dmu_int.." bitfld.long 0xC 4. "TXEWATAE,TX Element Write After Trigger Address Enable" "0: Flag TXEENSA.TXEWATA does not activate the..,1: If TXEENSA.TXEWATA = 1 the interrupt line.." newline bitfld.long 0xC 3. "TXEIDLCE,TX Element Illegal DLC Enable" "0: Flag TXEENSA.TXEIDLC does not activate the..,1: If TXEENSA.TXEIDLC = 1 the interrupt line.." bitfld.long 0xC 2. "TXEIASE,TX Element Illegal Access Sequence Enable" "0: Flag TXEENSA.TXEIAS does not activate the..,1: If TXEENSA.TXEIAS = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 1. "TXEIEE,TX Element Illegal Enqueuing Enable" "0: Flag TXEENSA.TXEIE does not activate the..,1: If TXEENSA.TXEIE = 1 the interrupt line dmu_int.." bitfld.long 0xC 0. "TXENSAE,TX Element Not Start Address Enable" "0: Flag DMUIR.TXENSA does not activate the..,1: If DMUIR.TXENSA = 1 the interrupt line dmu_int.." line.long 0x10 "DMUC,DMU Configuration register" bitfld.long 0x10 0. "TTS,Transfer Timestamp" "0: No timestamp will be transferred via DMU Virtual..,1: Timestamp of message will be transferred from.." tree.end tree "CAN_SUB_2_M_CAN_1" base ad:0x70230000 rgroup.long 0x0++0x7 line.long 0x0 "CREL,Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Substep of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "TS_MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "ENDN,Endian Register" hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value" group.long 0xC++0x23 line.long 0x0 "DBTP,Data Bit Timing and Prescaler Register" bitfld.long 0x0 23. "TDC,Transceiver Delay Compensation" "0: Transceiver Delay Compensation disabled,1: Transceiver Delay Compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re) Synchronization Jump Width" line.long 0x4 "TEST,Test register" bitfld.long 0x4 21. "SVAL,Started Valid" "0: Value of TXBNS not valid,1: Value of TXBNS valid" hexmask.long.byte 0x4 16.--20. 1. "TXBNS,Tx Buffer Number Started" newline bitfld.long 0x4 13. "PVAL,Prepared Valid" "0: Value of TXBNP not valid,1: Value of TXBNP valid" hexmask.long.byte 0x4 8.--12. 1. "TXBNP,Tx Buffer Number Prepared" newline bitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant (CAN Rx input = '0'),1: The CAN bus is recessive (CAN Rx input = '1')" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CAN Tx output is controlled by the..,1: Sample Point can be monitored at pin CAN Tx output,2: Dominant ('0') level at pin CAN Tx output,3: Recessive ('1') at pin CAN Tx output" newline bitfld.long 0x4 4. "LBCK,Loop Back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (refer to.." line.long 0x8 "RWD,RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration" line.long 0xC "CCCR,CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0xC 11. "WMM,Wide Message Marker" "0: 8-bit Message Marker used,1: 16-bit Message Marker used replacing 16-bit.." bitfld.long 0xC 10. "UTSU,Use Timestamping Unit" "0: Internal time stamping,1: External time stamping by TSU" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST_EN,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_CAN may be set in power down by stopping Host.." bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started" line.long 0x10 "NBTP,Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,(Re) Synchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Time segment before sample point" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,The time segment after the sample point" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Same as 00" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. "TOC,The Timeout Counter is decremented in multiples of CAN bit times (1 to 16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are.." rgroup.long 0x40++0x7 line.long 0x0 "ECR,Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "PSR,Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Received CAN FD Message" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set." newline bitfld.long 0x4 11. "RESI,ESI CAN FD Message with ESI flag" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state" bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state. It..,1: The M_CAN is in the Error_Passive state" bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing node is synchronizing on CAN..,1: Idle-node is neither receiver nor transmitter,2: Receiver-node is operating as receiver,3: Transmitter-node is operating as transmitter" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: consecutive recessive bits,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.." group.long 0x48++0x3 line.long 0x0 "TDCR,Transmitter Delay compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0xF line.long 0x0 "IR,Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected uncorrected (for example.." bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected (for example ECC)" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Event Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx Event FIDO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "IE,Interrupt Enable Register" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "ILS,Interrupt Line Select Register" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 16. "TSWL,TSWL: Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" line.long 0xC "ILE,Interrupt Line Enable Register" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line disabled,1: Interrupt line enabled" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line disabled,1: Interrupt line enabled" group.long 0x80++0xB line.long 0x0 "GFC,Global Filter Configuration Register" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,ANFE[1:0]: Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x8 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x3 line.long 0x0 "XIDAM,Extended ID and Mask Register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "HPMS,High Priority Message Status Register" bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "NDAT1,New Data 1 Register" bitfld.long 0x0 31. "ND31,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 30. "ND30,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 28. "ND28,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 26. "ND26,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 24. "ND24,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 22. "ND22,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 20. "ND20,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 18. "ND18,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 16. "ND16,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 14. "ND14,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 12. "ND12,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 10. "ND10,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 8. "ND8,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 6. "ND6,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 4. "ND4,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 2. "ND2,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 0. "ND0,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x4 "NDAT2,New Data 2 Register" bitfld.long 0x4 31. "ND63,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 30. "ND62,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 28. "ND60,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 26. "ND58,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 24. "ND56,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 22. "ND54,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 20. "ND52,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 18. "ND50,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 16. "ND48,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 14. "ND46,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 12. "ND44,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 10. "ND42,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 8. "ND40,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 6. "ND38,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 4. "ND36,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 2. "ND34,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 0. "ND32,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x8 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x0 25. "RF0L,RF0L" "0,1" bitfld.long 0x0 24. "F0F,F0F" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,F0PI" hexmask.long.byte 0x0 8.--13. 1. "F0GI,F0GI" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,F0FL" group.long 0xA8++0xB line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "RXF1C,Rx FIFO 1 Configuration Register" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,F1S[6:0]:" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is set" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" line.long 0x8 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Tx FIFO/Queue Size" newline hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x3 line.long 0x0 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x0 31. "AR31,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 30. "AR30,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 29. "AR29,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 28. "AR28,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 27. "AR27,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 26. "AR26,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 25. "AR25,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 24. "AR24,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 23. "AR23,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 22. "AR22,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 21. "AR21,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 20. "AR20,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 19. "AR19,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 18. "AR18,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 17. "AR17,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 16. "AR16,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 15. "AR15,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 14. "AR14,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 13. "AR13,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 12. "AR12,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 11. "AR11,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 10. "AR10,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 9. "AR9,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 8. "AR8,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 7. "AR7,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 6. "AR6,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 5. "AR5,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 4. "AR4,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 3. "AR3,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 2. "AR2,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 1. "AR1,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 0. "AR0,Add Request" "0: No transmission request added,1: Transmission requested added" line.long 0x4 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x4 31. "CR31,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 30. "CR30,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 29. "CR29,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 28. "CR28,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 27. "CR27,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 26. "CR26,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 24. "CR24,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 23. "CR23,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 22. "CR22,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 21. "CR21,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 20. "CR20,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 18. "CR18,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 17. "CR17,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 16. "CR16,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 15. "CR15,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 14. "CR14,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 12. "CR12,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 11. "CR11,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 10. "CR10,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 9. "CR9,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 8. "CR8,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 6. "CR6,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 5. "CR5,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 4. "CR4,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 3. "CR3,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 2. "CR2,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 0. "CR0,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" rgroup.long 0xD8++0x7 line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 29. "TO29,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 28. "TO28,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 27. "TO27,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 23. "TO23,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 22. "TO22,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 21. "TO21,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 17. "TO17,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 16. "TO16,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 15. "TO15,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 11. "TO11,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 10. "TO10,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 9. "TO9,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 5. "TO5,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 4. "TO4,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 3. "TO3,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 29. "CF29,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 28. "CF28,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 27. "CF27,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 23. "CF23,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 22. "CF22,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 21. "CF21,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 17. "CF17,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 16. "CF16,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 15. "CF15,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 11. "CF11,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 10. "CF10,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 9. "CF9,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 5. "CF5,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 4. "CF4,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 3. "CF3,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" group.long 0xE0++0x7 line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" group.long 0xF0++0x3 line.long 0x0 "TXEFC,Tx Event FIFO Configuration Register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address." rgroup.long 0xF4++0x3 line.long 0x0 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0x3 line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge Register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" tree.end tree "CAN_SUB_2_M_CAN_2" base ad:0x70234000 rgroup.long 0x0++0x7 line.long 0x0 "CREL,Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Substep of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "TS_MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "ENDN,Endian Register" hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value" group.long 0xC++0x23 line.long 0x0 "DBTP,Data Bit Timing and Prescaler Register" bitfld.long 0x0 23. "TDC,Transceiver Delay Compensation" "0: Transceiver Delay Compensation disabled,1: Transceiver Delay Compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re) Synchronization Jump Width" line.long 0x4 "TEST,Test register" bitfld.long 0x4 21. "SVAL,Started Valid" "0: Value of TXBNS not valid,1: Value of TXBNS valid" hexmask.long.byte 0x4 16.--20. 1. "TXBNS,Tx Buffer Number Started" newline bitfld.long 0x4 13. "PVAL,Prepared Valid" "0: Value of TXBNP not valid,1: Value of TXBNP valid" hexmask.long.byte 0x4 8.--12. 1. "TXBNP,Tx Buffer Number Prepared" newline bitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant (CAN Rx input = '0'),1: The CAN bus is recessive (CAN Rx input = '1')" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CAN Tx output is controlled by the..,1: Sample Point can be monitored at pin CAN Tx output,2: Dominant ('0') level at pin CAN Tx output,3: Recessive ('1') at pin CAN Tx output" newline bitfld.long 0x4 4. "LBCK,Loop Back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (refer to.." line.long 0x8 "RWD,RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration" line.long 0xC "CCCR,CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0xC 11. "WMM,Wide Message Marker" "0: 8-bit Message Marker used,1: 16-bit Message Marker used replacing 16-bit.." bitfld.long 0xC 10. "UTSU,Use Timestamping Unit" "0: Internal time stamping,1: External time stamping by TSU" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST_EN,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_CAN may be set in power down by stopping Host.." bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started" line.long 0x10 "NBTP,Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,(Re) Synchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Time segment before sample point" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,The time segment after the sample point" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Same as 00" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. "TOC,The Timeout Counter is decremented in multiples of CAN bit times (1 to 16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are.." rgroup.long 0x40++0x7 line.long 0x0 "ECR,Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "PSR,Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Received CAN FD Message" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set." newline bitfld.long 0x4 11. "RESI,ESI CAN FD Message with ESI flag" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state" bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state. It..,1: The M_CAN is in the Error_Passive state" bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing node is synchronizing on CAN..,1: Idle-node is neither receiver nor transmitter,2: Receiver-node is operating as receiver,3: Transmitter-node is operating as transmitter" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: consecutive recessive bits,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.." group.long 0x48++0x3 line.long 0x0 "TDCR,Transmitter Delay compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0xF line.long 0x0 "IR,Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected uncorrected (for example.." bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected (for example ECC)" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Event Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx Event FIDO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "IE,Interrupt Enable Register" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "ILS,Interrupt Line Select Register" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 16. "TSWL,TSWL: Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" line.long 0xC "ILE,Interrupt Line Enable Register" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line disabled,1: Interrupt line enabled" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line disabled,1: Interrupt line enabled" group.long 0x80++0xB line.long 0x0 "GFC,Global Filter Configuration Register" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,ANFE[1:0]: Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x8 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x3 line.long 0x0 "XIDAM,Extended ID and Mask Register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "HPMS,High Priority Message Status Register" bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "NDAT1,New Data 1 Register" bitfld.long 0x0 31. "ND31,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 30. "ND30,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 28. "ND28,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 26. "ND26,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 24. "ND24,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 22. "ND22,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 20. "ND20,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 18. "ND18,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 16. "ND16,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 14. "ND14,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 12. "ND12,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 10. "ND10,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 8. "ND8,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 6. "ND6,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 4. "ND4,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 2. "ND2,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 0. "ND0,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x4 "NDAT2,New Data 2 Register" bitfld.long 0x4 31. "ND63,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 30. "ND62,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 28. "ND60,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 26. "ND58,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 24. "ND56,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 22. "ND54,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 20. "ND52,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 18. "ND50,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 16. "ND48,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 14. "ND46,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 12. "ND44,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 10. "ND42,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 8. "ND40,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 6. "ND38,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 4. "ND36,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 2. "ND34,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 0. "ND32,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x8 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x0 25. "RF0L,RF0L" "0,1" bitfld.long 0x0 24. "F0F,F0F" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,F0PI" hexmask.long.byte 0x0 8.--13. 1. "F0GI,F0GI" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,F0FL" group.long 0xA8++0xB line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "RXF1C,Rx FIFO 1 Configuration Register" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,F1S[6:0]:" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is set" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" line.long 0x8 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Tx FIFO/Queue Size" newline hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x3 line.long 0x0 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x0 31. "AR31,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 30. "AR30,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 29. "AR29,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 28. "AR28,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 27. "AR27,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 26. "AR26,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 25. "AR25,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 24. "AR24,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 23. "AR23,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 22. "AR22,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 21. "AR21,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 20. "AR20,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 19. "AR19,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 18. "AR18,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 17. "AR17,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 16. "AR16,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 15. "AR15,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 14. "AR14,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 13. "AR13,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 12. "AR12,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 11. "AR11,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 10. "AR10,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 9. "AR9,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 8. "AR8,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 7. "AR7,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 6. "AR6,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 5. "AR5,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 4. "AR4,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 3. "AR3,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 2. "AR2,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 1. "AR1,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 0. "AR0,Add Request" "0: No transmission request added,1: Transmission requested added" line.long 0x4 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x4 31. "CR31,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 30. "CR30,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 29. "CR29,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 28. "CR28,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 27. "CR27,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 26. "CR26,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 24. "CR24,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 23. "CR23,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 22. "CR22,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 21. "CR21,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 20. "CR20,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 18. "CR18,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 17. "CR17,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 16. "CR16,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 15. "CR15,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 14. "CR14,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 12. "CR12,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 11. "CR11,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 10. "CR10,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 9. "CR9,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 8. "CR8,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 6. "CR6,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 5. "CR5,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 4. "CR4,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 3. "CR3,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 2. "CR2,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 0. "CR0,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" rgroup.long 0xD8++0x7 line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 29. "TO29,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 28. "TO28,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 27. "TO27,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 23. "TO23,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 22. "TO22,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 21. "TO21,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 17. "TO17,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 16. "TO16,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 15. "TO15,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 11. "TO11,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 10. "TO10,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 9. "TO9,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 5. "TO5,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 4. "TO4,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 3. "TO3,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 29. "CF29,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 28. "CF28,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 27. "CF27,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 23. "CF23,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 22. "CF22,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 21. "CF21,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 17. "CF17,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 16. "CF16,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 15. "CF15,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 11. "CF11,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 10. "CF10,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 9. "CF9,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 5. "CF5,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 4. "CF4,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 3. "CF3,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" group.long 0xE0++0x7 line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" group.long 0xF0++0x3 line.long 0x0 "TXEFC,Tx Event FIFO Configuration Register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address." rgroup.long 0xF4++0x3 line.long 0x0 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0x3 line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge Register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" tree.end tree "CAN_SUB_2_M_CAN_3" base ad:0x70238000 rgroup.long 0x0++0x7 line.long 0x0 "CREL,Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Substep of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "TS_MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "ENDN,Endian Register" hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value" group.long 0xC++0x23 line.long 0x0 "DBTP,Data Bit Timing and Prescaler Register" bitfld.long 0x0 23. "TDC,Transceiver Delay Compensation" "0: Transceiver Delay Compensation disabled,1: Transceiver Delay Compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re) Synchronization Jump Width" line.long 0x4 "TEST,Test register" bitfld.long 0x4 21. "SVAL,Started Valid" "0: Value of TXBNS not valid,1: Value of TXBNS valid" hexmask.long.byte 0x4 16.--20. 1. "TXBNS,Tx Buffer Number Started" newline bitfld.long 0x4 13. "PVAL,Prepared Valid" "0: Value of TXBNP not valid,1: Value of TXBNP valid" hexmask.long.byte 0x4 8.--12. 1. "TXBNP,Tx Buffer Number Prepared" newline bitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant (CAN Rx input = '0'),1: The CAN bus is recessive (CAN Rx input = '1')" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CAN Tx output is controlled by the..,1: Sample Point can be monitored at pin CAN Tx output,2: Dominant ('0') level at pin CAN Tx output,3: Recessive ('1') at pin CAN Tx output" newline bitfld.long 0x4 4. "LBCK,Loop Back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (refer to.." line.long 0x8 "RWD,RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration" line.long 0xC "CCCR,CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0xC 11. "WMM,Wide Message Marker" "0: 8-bit Message Marker used,1: 16-bit Message Marker used replacing 16-bit.." bitfld.long 0xC 10. "UTSU,Use Timestamping Unit" "0: Internal time stamping,1: External time stamping by TSU" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST_EN,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_CAN may be set in power down by stopping Host.." bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started" line.long 0x10 "NBTP,Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,(Re) Synchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Time segment before sample point" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,The time segment after the sample point" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Same as 00" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. "TOC,The Timeout Counter is decremented in multiples of CAN bit times (1 to 16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are.." rgroup.long 0x40++0x7 line.long 0x0 "ECR,Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "PSR,Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Received CAN FD Message" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set." newline bitfld.long 0x4 11. "RESI,ESI CAN FD Message with ESI flag" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state" bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state. It..,1: The M_CAN is in the Error_Passive state" bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing node is synchronizing on CAN..,1: Idle-node is neither receiver nor transmitter,2: Receiver-node is operating as receiver,3: Transmitter-node is operating as transmitter" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: consecutive recessive bits,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.." group.long 0x48++0x3 line.long 0x0 "TDCR,Transmitter Delay compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0xF line.long 0x0 "IR,Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected uncorrected (for example.." bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected (for example ECC)" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Event Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx Event FIDO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "IE,Interrupt Enable Register" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "ILS,Interrupt Line Select Register" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 16. "TSWL,TSWL: Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" line.long 0xC "ILE,Interrupt Line Enable Register" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line disabled,1: Interrupt line enabled" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line disabled,1: Interrupt line enabled" group.long 0x80++0xB line.long 0x0 "GFC,Global Filter Configuration Register" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,ANFE[1:0]: Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x8 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x3 line.long 0x0 "XIDAM,Extended ID and Mask Register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "HPMS,High Priority Message Status Register" bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "NDAT1,New Data 1 Register" bitfld.long 0x0 31. "ND31,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 30. "ND30,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 28. "ND28,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 26. "ND26,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 24. "ND24,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 22. "ND22,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 20. "ND20,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 18. "ND18,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 16. "ND16,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 14. "ND14,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 12. "ND12,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 10. "ND10,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 8. "ND8,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 6. "ND6,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 4. "ND4,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 2. "ND2,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 0. "ND0,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x4 "NDAT2,New Data 2 Register" bitfld.long 0x4 31. "ND63,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 30. "ND62,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 28. "ND60,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 26. "ND58,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 24. "ND56,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 22. "ND54,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 20. "ND52,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 18. "ND50,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 16. "ND48,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 14. "ND46,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 12. "ND44,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 10. "ND42,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 8. "ND40,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 6. "ND38,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 4. "ND36,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 2. "ND34,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 0. "ND32,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x8 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x0 25. "RF0L,RF0L" "0,1" bitfld.long 0x0 24. "F0F,F0F" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,F0PI" hexmask.long.byte 0x0 8.--13. 1. "F0GI,F0GI" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,F0FL" group.long 0xA8++0xB line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "RXF1C,Rx FIFO 1 Configuration Register" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,F1S[6:0]:" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is set" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" line.long 0x8 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Tx FIFO/Queue Size" newline hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x3 line.long 0x0 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x0 31. "AR31,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 30. "AR30,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 29. "AR29,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 28. "AR28,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 27. "AR27,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 26. "AR26,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 25. "AR25,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 24. "AR24,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 23. "AR23,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 22. "AR22,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 21. "AR21,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 20. "AR20,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 19. "AR19,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 18. "AR18,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 17. "AR17,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 16. "AR16,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 15. "AR15,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 14. "AR14,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 13. "AR13,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 12. "AR12,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 11. "AR11,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 10. "AR10,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 9. "AR9,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 8. "AR8,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 7. "AR7,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 6. "AR6,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 5. "AR5,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 4. "AR4,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 3. "AR3,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 2. "AR2,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 1. "AR1,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 0. "AR0,Add Request" "0: No transmission request added,1: Transmission requested added" line.long 0x4 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x4 31. "CR31,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 30. "CR30,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 29. "CR29,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 28. "CR28,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 27. "CR27,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 26. "CR26,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 24. "CR24,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 23. "CR23,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 22. "CR22,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 21. "CR21,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 20. "CR20,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 18. "CR18,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 17. "CR17,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 16. "CR16,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 15. "CR15,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 14. "CR14,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 12. "CR12,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 11. "CR11,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 10. "CR10,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 9. "CR9,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 8. "CR8,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 6. "CR6,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 5. "CR5,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 4. "CR4,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 3. "CR3,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 2. "CR2,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 0. "CR0,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" rgroup.long 0xD8++0x7 line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 29. "TO29,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 28. "TO28,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 27. "TO27,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 23. "TO23,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 22. "TO22,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 21. "TO21,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 17. "TO17,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 16. "TO16,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 15. "TO15,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 11. "TO11,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 10. "TO10,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 9. "TO9,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 5. "TO5,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 4. "TO4,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 3. "TO3,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 29. "CF29,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 28. "CF28,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 27. "CF27,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 23. "CF23,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 22. "CF22,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 21. "CF21,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 17. "CF17,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 16. "CF16,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 15. "CF15,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 11. "CF11,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 10. "CF10,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 9. "CF9,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 5. "CF5,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 4. "CF4,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 3. "CF3,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" group.long 0xE0++0x7 line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" group.long 0xF0++0x3 line.long 0x0 "TXEFC,Tx Event FIFO Configuration Register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address." rgroup.long 0xF4++0x3 line.long 0x0 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0x3 line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge Register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" tree.end tree "CAN_SUB_2_M_CAN_4" base ad:0x7023C000 rgroup.long 0x0++0x7 line.long 0x0 "CREL,Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Substep of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "TS_MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "ENDN,Endian Register" hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value" group.long 0xC++0x23 line.long 0x0 "DBTP,Data Bit Timing and Prescaler Register" bitfld.long 0x0 23. "TDC,Transceiver Delay Compensation" "0: Transceiver Delay Compensation disabled,1: Transceiver Delay Compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re) Synchronization Jump Width" line.long 0x4 "TEST,Test register" bitfld.long 0x4 21. "SVAL,Started Valid" "0: Value of TXBNS not valid,1: Value of TXBNS valid" hexmask.long.byte 0x4 16.--20. 1. "TXBNS,Tx Buffer Number Started" newline bitfld.long 0x4 13. "PVAL,Prepared Valid" "0: Value of TXBNP not valid,1: Value of TXBNP valid" hexmask.long.byte 0x4 8.--12. 1. "TXBNP,Tx Buffer Number Prepared" newline bitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant (CAN Rx input = '0'),1: The CAN bus is recessive (CAN Rx input = '1')" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CAN Tx output is controlled by the..,1: Sample Point can be monitored at pin CAN Tx output,2: Dominant ('0') level at pin CAN Tx output,3: Recessive ('1') at pin CAN Tx output" newline bitfld.long 0x4 4. "LBCK,Loop Back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (refer to.." line.long 0x8 "RWD,RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration" line.long 0xC "CCCR,CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0xC 11. "WMM,Wide Message Marker" "0: 8-bit Message Marker used,1: 16-bit Message Marker used replacing 16-bit.." bitfld.long 0xC 10. "UTSU,Use Timestamping Unit" "0: Internal time stamping,1: External time stamping by TSU" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST_EN,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_CAN may be set in power down by stopping Host.." bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started" line.long 0x10 "NBTP,Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,(Re) Synchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Time segment before sample point" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,The time segment after the sample point" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Same as 00" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. "TOC,The Timeout Counter is decremented in multiples of CAN bit times (1 to 16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are.." rgroup.long 0x40++0x7 line.long 0x0 "ECR,Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "PSR,Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Received CAN FD Message" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set." newline bitfld.long 0x4 11. "RESI,ESI CAN FD Message with ESI flag" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state" bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state. It..,1: The M_CAN is in the Error_Passive state" bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing node is synchronizing on CAN..,1: Idle-node is neither receiver nor transmitter,2: Receiver-node is operating as receiver,3: Transmitter-node is operating as transmitter" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: consecutive recessive bits,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.." group.long 0x48++0x3 line.long 0x0 "TDCR,Transmitter Delay compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0xF line.long 0x0 "IR,Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected uncorrected (for example.." bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected (for example ECC)" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Event Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx Event FIDO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "IE,Interrupt Enable Register" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "ILS,Interrupt Line Select Register" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 16. "TSWL,TSWL: Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" line.long 0xC "ILE,Interrupt Line Enable Register" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line disabled,1: Interrupt line enabled" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line disabled,1: Interrupt line enabled" group.long 0x80++0xB line.long 0x0 "GFC,Global Filter Configuration Register" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,ANFE[1:0]: Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x8 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x3 line.long 0x0 "XIDAM,Extended ID and Mask Register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "HPMS,High Priority Message Status Register" bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "NDAT1,New Data 1 Register" bitfld.long 0x0 31. "ND31,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 30. "ND30,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 28. "ND28,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 26. "ND26,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 24. "ND24,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 22. "ND22,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 20. "ND20,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 18. "ND18,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 16. "ND16,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 14. "ND14,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 12. "ND12,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 10. "ND10,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 8. "ND8,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 6. "ND6,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 4. "ND4,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 2. "ND2,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 0. "ND0,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x4 "NDAT2,New Data 2 Register" bitfld.long 0x4 31. "ND63,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 30. "ND62,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 28. "ND60,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 26. "ND58,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 24. "ND56,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 22. "ND54,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 20. "ND52,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 18. "ND50,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 16. "ND48,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 14. "ND46,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 12. "ND44,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 10. "ND42,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 8. "ND40,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 6. "ND38,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 4. "ND36,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 2. "ND34,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 0. "ND32,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x8 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x0 25. "RF0L,RF0L" "0,1" bitfld.long 0x0 24. "F0F,F0F" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,F0PI" hexmask.long.byte 0x0 8.--13. 1. "F0GI,F0GI" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,F0FL" group.long 0xA8++0xB line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "RXF1C,Rx FIFO 1 Configuration Register" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,F1S[6:0]:" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is set" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" line.long 0x8 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Tx FIFO/Queue Size" newline hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x3 line.long 0x0 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x0 31. "AR31,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 30. "AR30,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 29. "AR29,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 28. "AR28,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 27. "AR27,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 26. "AR26,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 25. "AR25,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 24. "AR24,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 23. "AR23,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 22. "AR22,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 21. "AR21,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 20. "AR20,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 19. "AR19,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 18. "AR18,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 17. "AR17,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 16. "AR16,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 15. "AR15,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 14. "AR14,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 13. "AR13,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 12. "AR12,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 11. "AR11,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 10. "AR10,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 9. "AR9,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 8. "AR8,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 7. "AR7,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 6. "AR6,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 5. "AR5,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 4. "AR4,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 3. "AR3,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 2. "AR2,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 1. "AR1,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 0. "AR0,Add Request" "0: No transmission request added,1: Transmission requested added" line.long 0x4 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x4 31. "CR31,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 30. "CR30,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 29. "CR29,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 28. "CR28,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 27. "CR27,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 26. "CR26,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 24. "CR24,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 23. "CR23,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 22. "CR22,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 21. "CR21,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 20. "CR20,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 18. "CR18,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 17. "CR17,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 16. "CR16,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 15. "CR15,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 14. "CR14,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 12. "CR12,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 11. "CR11,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 10. "CR10,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 9. "CR9,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 8. "CR8,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 6. "CR6,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 5. "CR5,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 4. "CR4,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 3. "CR3,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 2. "CR2,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 0. "CR0,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" rgroup.long 0xD8++0x7 line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 29. "TO29,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 28. "TO28,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 27. "TO27,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 23. "TO23,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 22. "TO22,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 21. "TO21,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 17. "TO17,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 16. "TO16,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 15. "TO15,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 11. "TO11,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 10. "TO10,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 9. "TO9,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 5. "TO5,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 4. "TO4,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 3. "TO3,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 29. "CF29,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 28. "CF28,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 27. "CF27,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 23. "CF23,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 22. "CF22,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 21. "CF21,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 17. "CF17,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 16. "CF16,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 15. "CF15,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 11. "CF11,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 10. "CF10,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 9. "CF9,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 5. "CF5,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 4. "CF4,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 3. "CF3,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" group.long 0xE0++0x7 line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" group.long 0xF0++0x3 line.long 0x0 "TXEFC,Tx Event FIFO Configuration Register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address." rgroup.long 0xF4++0x3 line.long 0x0 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0x3 line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge Register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" tree.end tree "CAN_SUB_2_TSU_1" base ad:0x70230000 rgroup.long 0x160++0x7 line.long 0x0 "CREL,Core Release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "TSCFG,Timestamp Configuration register" hexmask.long.byte 0x4 8.--15. 1. "TBPRE,TBPRE" bitfld.long 0x4 2. "SCP,Select Capturing Position" "0: Capture Timestamp at EOF,1: Capture Timestamp at SOF" newline bitfld.long 0x4 1. "TBCS,Timebase Counter Select" "0: Timestamp value captured from internal timebase..,1: : Timestamp value captured from input.." bitfld.long 0x4 0. "TSUE,Timestamp Unit Enable 0" "0: TSU disabled,1: TSU enabled" group.long 0x168++0x3 line.long 0x0 "TSS1,Timestamp Status 1 register" bitfld.long 0x0 31. "TSL15,Timestamp Lost" "0,1" bitfld.long 0x0 30. "TSL14,Timestamp Lost" "0,1" newline bitfld.long 0x0 29. "TSL13,Timestamp Lost" "0,1" bitfld.long 0x0 28. "TSL12,Timestamp Lost" "0,1" newline bitfld.long 0x0 27. "TSL11,Timestamp Lost" "0,1" bitfld.long 0x0 26. "TSL10,Timestamp Lost" "0,1" newline bitfld.long 0x0 25. "TSL9,Timestamp Lost" "0,1" bitfld.long 0x0 24. "TSL8,Timestamp Lost" "0,1" newline bitfld.long 0x0 23. "TSL7,Timestamp Lost" "0,1" bitfld.long 0x0 22. "TSL6,Timestamp Lost" "0,1" newline bitfld.long 0x0 21. "TSL5,Timestamp Lost" "0,1" bitfld.long 0x0 20. "TSL4,Timestamp Lost" "0,1" newline bitfld.long 0x0 19. "TSL3,Timestamp Lost" "0,1" bitfld.long 0x0 18. "TSL2,Timestamp Lost" "0,1" newline bitfld.long 0x0 17. "TSL1,Timestamp Lost" "0,1" bitfld.long 0x0 16. "TSL0,Timestamp Lost" "0,1" newline bitfld.long 0x0 15. "TSN15,Timestamp New" "0,1" bitfld.long 0x0 14. "TSN14,Timestamp New" "0,1" newline bitfld.long 0x0 13. "TSN13,Timestamp New" "0,1" bitfld.long 0x0 12. "TSN12,Timestamp New" "0,1" newline bitfld.long 0x0 11. "TSN11,Timestamp New" "0,1" bitfld.long 0x0 10. "TSN10,Timestamp New" "0,1" newline bitfld.long 0x0 9. "TSN9,Timestamp New" "0,1" bitfld.long 0x0 8. "TSN8,Timestamp New" "0,1" newline bitfld.long 0x0 7. "TSN7,Timestamp New" "0,1" bitfld.long 0x0 6. "TSN6,Timestamp New" "0,1" newline bitfld.long 0x0 5. "TSN5,Timestamp New" "0,1" bitfld.long 0x0 4. "TSN4,Timestamp New" "0,1" newline bitfld.long 0x0 3. "TSN3,Timestamp New" "0,1" bitfld.long 0x0 2. "TSN2,Timestamp New" "0,1" newline bitfld.long 0x0 1. "TSN1,Timestamp New" "0,1" bitfld.long 0x0 0. "TSN0,Timestamp New" "0,1" rgroup.long 0x16C++0x43 line.long 0x0 "TSS2,Timestamp Status 2 register" bitfld.long 0x0 14.--15. "ITBG,Internal Timebase and SOF select Generic" "0: no SOF option no internal timebase,1: no SOF option internal timebase (default),2: SOF option no internal timebase,3: SOF option internal timebase" bitfld.long 0x0 12.--13. "NTSG,Number of Timestamps Generic" "0: 4 timestamp registers TS0-TS3,1: 8 timestamp registers TS0-TS7 (default),2: 16 timestamp registers TS0-TS15,3: not a valid value" newline hexmask.long.byte 0x0 0.--3. 1. "TSP,Timestamp Pointer" line.long 0x4 "TS0,Timestamp 0 register" hexmask.long 0x4 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x8 "TS1,Timestamp 1 register" hexmask.long 0x8 0.--31. 1. "TS,Timestamp Word TSn" line.long 0xC "TS2,Timestamp 2 register" hexmask.long 0xC 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x10 "TS3,Timestamp 3 register" hexmask.long 0x10 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x14 "TS4,Timestamp 4 register" hexmask.long 0x14 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x18 "TS5,Timestamp 5 register" hexmask.long 0x18 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x1C "TS6,Timestamp 6 register" hexmask.long 0x1C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x20 "TS7,Timestamp 7 register" hexmask.long 0x20 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x24 "TS8,Timestamp 8 register" hexmask.long 0x24 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x28 "TS9,Timestamp 9 register" hexmask.long 0x28 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x2C "TS10,Timestamp 10 register" hexmask.long 0x2C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x30 "TS11,Timestamp 11 register" hexmask.long 0x30 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x34 "TS12,Timestamp 12 register" hexmask.long 0x34 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x38 "TS13,Timestamp 13 register" hexmask.long 0x38 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x3C "TS14,Timestamp 14 register" hexmask.long 0x3C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x40 "TS15,Timestamp 15 register" hexmask.long 0x40 0.--31. 1. "TS,Timestamp Word TSn" group.long 0x1B0++0x3 line.long 0x0 "ATB,Actual Timebase" hexmask.long 0x0 0.--31. 1. "TB,Timebase for timestamp generation" tree.end tree "CAN_SUB_2_TSU_2" base ad:0x70234000 rgroup.long 0x160++0x7 line.long 0x0 "CREL,Core Release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "TSCFG,Timestamp Configuration register" hexmask.long.byte 0x4 8.--15. 1. "TBPRE,TBPRE" bitfld.long 0x4 2. "SCP,Select Capturing Position" "0: Capture Timestamp at EOF,1: Capture Timestamp at SOF" newline bitfld.long 0x4 1. "TBCS,Timebase Counter Select" "0: Timestamp value captured from internal timebase..,1: : Timestamp value captured from input.." bitfld.long 0x4 0. "TSUE,Timestamp Unit Enable 0" "0: TSU disabled,1: TSU enabled" group.long 0x168++0x3 line.long 0x0 "TSS1,Timestamp Status 1 register" bitfld.long 0x0 31. "TSL15,Timestamp Lost" "0,1" bitfld.long 0x0 30. "TSL14,Timestamp Lost" "0,1" newline bitfld.long 0x0 29. "TSL13,Timestamp Lost" "0,1" bitfld.long 0x0 28. "TSL12,Timestamp Lost" "0,1" newline bitfld.long 0x0 27. "TSL11,Timestamp Lost" "0,1" bitfld.long 0x0 26. "TSL10,Timestamp Lost" "0,1" newline bitfld.long 0x0 25. "TSL9,Timestamp Lost" "0,1" bitfld.long 0x0 24. "TSL8,Timestamp Lost" "0,1" newline bitfld.long 0x0 23. "TSL7,Timestamp Lost" "0,1" bitfld.long 0x0 22. "TSL6,Timestamp Lost" "0,1" newline bitfld.long 0x0 21. "TSL5,Timestamp Lost" "0,1" bitfld.long 0x0 20. "TSL4,Timestamp Lost" "0,1" newline bitfld.long 0x0 19. "TSL3,Timestamp Lost" "0,1" bitfld.long 0x0 18. "TSL2,Timestamp Lost" "0,1" newline bitfld.long 0x0 17. "TSL1,Timestamp Lost" "0,1" bitfld.long 0x0 16. "TSL0,Timestamp Lost" "0,1" newline bitfld.long 0x0 15. "TSN15,Timestamp New" "0,1" bitfld.long 0x0 14. "TSN14,Timestamp New" "0,1" newline bitfld.long 0x0 13. "TSN13,Timestamp New" "0,1" bitfld.long 0x0 12. "TSN12,Timestamp New" "0,1" newline bitfld.long 0x0 11. "TSN11,Timestamp New" "0,1" bitfld.long 0x0 10. "TSN10,Timestamp New" "0,1" newline bitfld.long 0x0 9. "TSN9,Timestamp New" "0,1" bitfld.long 0x0 8. "TSN8,Timestamp New" "0,1" newline bitfld.long 0x0 7. "TSN7,Timestamp New" "0,1" bitfld.long 0x0 6. "TSN6,Timestamp New" "0,1" newline bitfld.long 0x0 5. "TSN5,Timestamp New" "0,1" bitfld.long 0x0 4. "TSN4,Timestamp New" "0,1" newline bitfld.long 0x0 3. "TSN3,Timestamp New" "0,1" bitfld.long 0x0 2. "TSN2,Timestamp New" "0,1" newline bitfld.long 0x0 1. "TSN1,Timestamp New" "0,1" bitfld.long 0x0 0. "TSN0,Timestamp New" "0,1" rgroup.long 0x16C++0x43 line.long 0x0 "TSS2,Timestamp Status 2 register" bitfld.long 0x0 14.--15. "ITBG,Internal Timebase and SOF select Generic" "0: no SOF option no internal timebase,1: no SOF option internal timebase (default),2: SOF option no internal timebase,3: SOF option internal timebase" bitfld.long 0x0 12.--13. "NTSG,Number of Timestamps Generic" "0: 4 timestamp registers TS0-TS3,1: 8 timestamp registers TS0-TS7 (default),2: 16 timestamp registers TS0-TS15,3: not a valid value" newline hexmask.long.byte 0x0 0.--3. 1. "TSP,Timestamp Pointer" line.long 0x4 "TS0,Timestamp 0 register" hexmask.long 0x4 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x8 "TS1,Timestamp 1 register" hexmask.long 0x8 0.--31. 1. "TS,Timestamp Word TSn" line.long 0xC "TS2,Timestamp 2 register" hexmask.long 0xC 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x10 "TS3,Timestamp 3 register" hexmask.long 0x10 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x14 "TS4,Timestamp 4 register" hexmask.long 0x14 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x18 "TS5,Timestamp 5 register" hexmask.long 0x18 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x1C "TS6,Timestamp 6 register" hexmask.long 0x1C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x20 "TS7,Timestamp 7 register" hexmask.long 0x20 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x24 "TS8,Timestamp 8 register" hexmask.long 0x24 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x28 "TS9,Timestamp 9 register" hexmask.long 0x28 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x2C "TS10,Timestamp 10 register" hexmask.long 0x2C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x30 "TS11,Timestamp 11 register" hexmask.long 0x30 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x34 "TS12,Timestamp 12 register" hexmask.long 0x34 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x38 "TS13,Timestamp 13 register" hexmask.long 0x38 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x3C "TS14,Timestamp 14 register" hexmask.long 0x3C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x40 "TS15,Timestamp 15 register" hexmask.long 0x40 0.--31. 1. "TS,Timestamp Word TSn" group.long 0x1B0++0x3 line.long 0x0 "ATB,Actual Timebase" hexmask.long 0x0 0.--31. 1. "TB,Timebase for timestamp generation" tree.end tree "CAN_SUB_2_TSU_3" base ad:0x70238000 rgroup.long 0x160++0x7 line.long 0x0 "CREL,Core Release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "TSCFG,Timestamp Configuration register" hexmask.long.byte 0x4 8.--15. 1. "TBPRE,TBPRE" bitfld.long 0x4 2. "SCP,Select Capturing Position" "0: Capture Timestamp at EOF,1: Capture Timestamp at SOF" newline bitfld.long 0x4 1. "TBCS,Timebase Counter Select" "0: Timestamp value captured from internal timebase..,1: : Timestamp value captured from input.." bitfld.long 0x4 0. "TSUE,Timestamp Unit Enable 0" "0: TSU disabled,1: TSU enabled" group.long 0x168++0x3 line.long 0x0 "TSS1,Timestamp Status 1 register" bitfld.long 0x0 31. "TSL15,Timestamp Lost" "0,1" bitfld.long 0x0 30. "TSL14,Timestamp Lost" "0,1" newline bitfld.long 0x0 29. "TSL13,Timestamp Lost" "0,1" bitfld.long 0x0 28. "TSL12,Timestamp Lost" "0,1" newline bitfld.long 0x0 27. "TSL11,Timestamp Lost" "0,1" bitfld.long 0x0 26. "TSL10,Timestamp Lost" "0,1" newline bitfld.long 0x0 25. "TSL9,Timestamp Lost" "0,1" bitfld.long 0x0 24. "TSL8,Timestamp Lost" "0,1" newline bitfld.long 0x0 23. "TSL7,Timestamp Lost" "0,1" bitfld.long 0x0 22. "TSL6,Timestamp Lost" "0,1" newline bitfld.long 0x0 21. "TSL5,Timestamp Lost" "0,1" bitfld.long 0x0 20. "TSL4,Timestamp Lost" "0,1" newline bitfld.long 0x0 19. "TSL3,Timestamp Lost" "0,1" bitfld.long 0x0 18. "TSL2,Timestamp Lost" "0,1" newline bitfld.long 0x0 17. "TSL1,Timestamp Lost" "0,1" bitfld.long 0x0 16. "TSL0,Timestamp Lost" "0,1" newline bitfld.long 0x0 15. "TSN15,Timestamp New" "0,1" bitfld.long 0x0 14. "TSN14,Timestamp New" "0,1" newline bitfld.long 0x0 13. "TSN13,Timestamp New" "0,1" bitfld.long 0x0 12. "TSN12,Timestamp New" "0,1" newline bitfld.long 0x0 11. "TSN11,Timestamp New" "0,1" bitfld.long 0x0 10. "TSN10,Timestamp New" "0,1" newline bitfld.long 0x0 9. "TSN9,Timestamp New" "0,1" bitfld.long 0x0 8. "TSN8,Timestamp New" "0,1" newline bitfld.long 0x0 7. "TSN7,Timestamp New" "0,1" bitfld.long 0x0 6. "TSN6,Timestamp New" "0,1" newline bitfld.long 0x0 5. "TSN5,Timestamp New" "0,1" bitfld.long 0x0 4. "TSN4,Timestamp New" "0,1" newline bitfld.long 0x0 3. "TSN3,Timestamp New" "0,1" bitfld.long 0x0 2. "TSN2,Timestamp New" "0,1" newline bitfld.long 0x0 1. "TSN1,Timestamp New" "0,1" bitfld.long 0x0 0. "TSN0,Timestamp New" "0,1" rgroup.long 0x16C++0x43 line.long 0x0 "TSS2,Timestamp Status 2 register" bitfld.long 0x0 14.--15. "ITBG,Internal Timebase and SOF select Generic" "0: no SOF option no internal timebase,1: no SOF option internal timebase (default),2: SOF option no internal timebase,3: SOF option internal timebase" bitfld.long 0x0 12.--13. "NTSG,Number of Timestamps Generic" "0: 4 timestamp registers TS0-TS3,1: 8 timestamp registers TS0-TS7 (default),2: 16 timestamp registers TS0-TS15,3: not a valid value" newline hexmask.long.byte 0x0 0.--3. 1. "TSP,Timestamp Pointer" line.long 0x4 "TS0,Timestamp 0 register" hexmask.long 0x4 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x8 "TS1,Timestamp 1 register" hexmask.long 0x8 0.--31. 1. "TS,Timestamp Word TSn" line.long 0xC "TS2,Timestamp 2 register" hexmask.long 0xC 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x10 "TS3,Timestamp 3 register" hexmask.long 0x10 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x14 "TS4,Timestamp 4 register" hexmask.long 0x14 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x18 "TS5,Timestamp 5 register" hexmask.long 0x18 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x1C "TS6,Timestamp 6 register" hexmask.long 0x1C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x20 "TS7,Timestamp 7 register" hexmask.long 0x20 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x24 "TS8,Timestamp 8 register" hexmask.long 0x24 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x28 "TS9,Timestamp 9 register" hexmask.long 0x28 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x2C "TS10,Timestamp 10 register" hexmask.long 0x2C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x30 "TS11,Timestamp 11 register" hexmask.long 0x30 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x34 "TS12,Timestamp 12 register" hexmask.long 0x34 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x38 "TS13,Timestamp 13 register" hexmask.long 0x38 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x3C "TS14,Timestamp 14 register" hexmask.long 0x3C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x40 "TS15,Timestamp 15 register" hexmask.long 0x40 0.--31. 1. "TS,Timestamp Word TSn" group.long 0x1B0++0x3 line.long 0x0 "ATB,Actual Timebase" hexmask.long 0x0 0.--31. 1. "TB,Timebase for timestamp generation" tree.end tree "CAN_SUB_2_TSU_4" base ad:0x7023C000 rgroup.long 0x160++0x7 line.long 0x0 "CREL,Core Release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "TSCFG,Timestamp Configuration register" hexmask.long.byte 0x4 8.--15. 1. "TBPRE,TBPRE" bitfld.long 0x4 2. "SCP,Select Capturing Position" "0: Capture Timestamp at EOF,1: Capture Timestamp at SOF" newline bitfld.long 0x4 1. "TBCS,Timebase Counter Select" "0: Timestamp value captured from internal timebase..,1: : Timestamp value captured from input.." bitfld.long 0x4 0. "TSUE,Timestamp Unit Enable 0" "0: TSU disabled,1: TSU enabled" group.long 0x168++0x3 line.long 0x0 "TSS1,Timestamp Status 1 register" bitfld.long 0x0 31. "TSL15,Timestamp Lost" "0,1" bitfld.long 0x0 30. "TSL14,Timestamp Lost" "0,1" newline bitfld.long 0x0 29. "TSL13,Timestamp Lost" "0,1" bitfld.long 0x0 28. "TSL12,Timestamp Lost" "0,1" newline bitfld.long 0x0 27. "TSL11,Timestamp Lost" "0,1" bitfld.long 0x0 26. "TSL10,Timestamp Lost" "0,1" newline bitfld.long 0x0 25. "TSL9,Timestamp Lost" "0,1" bitfld.long 0x0 24. "TSL8,Timestamp Lost" "0,1" newline bitfld.long 0x0 23. "TSL7,Timestamp Lost" "0,1" bitfld.long 0x0 22. "TSL6,Timestamp Lost" "0,1" newline bitfld.long 0x0 21. "TSL5,Timestamp Lost" "0,1" bitfld.long 0x0 20. "TSL4,Timestamp Lost" "0,1" newline bitfld.long 0x0 19. "TSL3,Timestamp Lost" "0,1" bitfld.long 0x0 18. "TSL2,Timestamp Lost" "0,1" newline bitfld.long 0x0 17. "TSL1,Timestamp Lost" "0,1" bitfld.long 0x0 16. "TSL0,Timestamp Lost" "0,1" newline bitfld.long 0x0 15. "TSN15,Timestamp New" "0,1" bitfld.long 0x0 14. "TSN14,Timestamp New" "0,1" newline bitfld.long 0x0 13. "TSN13,Timestamp New" "0,1" bitfld.long 0x0 12. "TSN12,Timestamp New" "0,1" newline bitfld.long 0x0 11. "TSN11,Timestamp New" "0,1" bitfld.long 0x0 10. "TSN10,Timestamp New" "0,1" newline bitfld.long 0x0 9. "TSN9,Timestamp New" "0,1" bitfld.long 0x0 8. "TSN8,Timestamp New" "0,1" newline bitfld.long 0x0 7. "TSN7,Timestamp New" "0,1" bitfld.long 0x0 6. "TSN6,Timestamp New" "0,1" newline bitfld.long 0x0 5. "TSN5,Timestamp New" "0,1" bitfld.long 0x0 4. "TSN4,Timestamp New" "0,1" newline bitfld.long 0x0 3. "TSN3,Timestamp New" "0,1" bitfld.long 0x0 2. "TSN2,Timestamp New" "0,1" newline bitfld.long 0x0 1. "TSN1,Timestamp New" "0,1" bitfld.long 0x0 0. "TSN0,Timestamp New" "0,1" rgroup.long 0x16C++0x43 line.long 0x0 "TSS2,Timestamp Status 2 register" bitfld.long 0x0 14.--15. "ITBG,Internal Timebase and SOF select Generic" "0: no SOF option no internal timebase,1: no SOF option internal timebase (default),2: SOF option no internal timebase,3: SOF option internal timebase" bitfld.long 0x0 12.--13. "NTSG,Number of Timestamps Generic" "0: 4 timestamp registers TS0-TS3,1: 8 timestamp registers TS0-TS7 (default),2: 16 timestamp registers TS0-TS15,3: not a valid value" newline hexmask.long.byte 0x0 0.--3. 1. "TSP,Timestamp Pointer" line.long 0x4 "TS0,Timestamp 0 register" hexmask.long 0x4 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x8 "TS1,Timestamp 1 register" hexmask.long 0x8 0.--31. 1. "TS,Timestamp Word TSn" line.long 0xC "TS2,Timestamp 2 register" hexmask.long 0xC 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x10 "TS3,Timestamp 3 register" hexmask.long 0x10 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x14 "TS4,Timestamp 4 register" hexmask.long 0x14 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x18 "TS5,Timestamp 5 register" hexmask.long 0x18 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x1C "TS6,Timestamp 6 register" hexmask.long 0x1C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x20 "TS7,Timestamp 7 register" hexmask.long 0x20 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x24 "TS8,Timestamp 8 register" hexmask.long 0x24 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x28 "TS9,Timestamp 9 register" hexmask.long 0x28 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x2C "TS10,Timestamp 10 register" hexmask.long 0x2C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x30 "TS11,Timestamp 11 register" hexmask.long 0x30 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x34 "TS12,Timestamp 12 register" hexmask.long 0x34 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x38 "TS13,Timestamp 13 register" hexmask.long 0x38 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x3C "TS14,Timestamp 14 register" hexmask.long 0x3C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x40 "TS15,Timestamp 15 register" hexmask.long 0x40 0.--31. 1. "TS,Timestamp Word TSn" group.long 0x1B0++0x3 line.long 0x0 "ATB,Actual Timebase" hexmask.long 0x0 0.--31. 1. "TB,Timebase for timestamp generation" tree.end tree.end tree "CAN_SUB_3" tree "CAN_SUB_3_DMU_1" base ad:0x70830000 rgroup.long 0x3C0++0x3 line.long 0x0 "DMUCR,DMU Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" group.long 0x3C4++0x13 line.long 0x0 "DMUI,DMU Internals register" bitfld.long 0x0 31. "TXE,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 30. "RX1,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 29. "RX0,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 28. "TX,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 24.--26. "EHS,Element Handler State" "0: wait for bit M_CAN:CCCR.CCE getting zero,1: wait for Start Address,2: wait for Trigger Address,3: wait for transfer of Element word,4: acknowledge to M_CAN,5: exception recovery,?,?" bitfld.long 0x0 23. "DTXE,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 22. "DTX1,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 21. "DTX0,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 20. "DTX,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 16.--18. "DEHS,Detect Element Handler State" "?,?,?,?,?,?,?,7: unused state" newline bitfld.long 0x0 15. "ENA,DMU is enabled" "0: DMU is disabled,1: DMU is enabled and can process DMA data" hexmask.long.byte 0x0 8.--12. 1. "TFQPIP,TX FIFO/Queue Put Index Previous" newline bitfld.long 0x0 3. "TXER,TX Event Service Request line of DMU" "0: No TX Event DMA service requested,1: TX Event DMA Service requested" bitfld.long 0x0 2. "RX1R,RX1 Service Request line of DMU" "0: No RX1 DMA service requested,1: RX1 DMA Service requested" newline bitfld.long 0x0 1. "RX0R,RX0 Service Request line of DMU" "0: No RX0 DMA service requested,1: RX0 DMA Service requested" bitfld.long 0x0 0. "TXR,TX Service Request line of DMU" "0: No TX DMA service requested,1: TX DMA Service requested" line.long 0x4 "DMUQC,DMU Queuing Counter register" hexmask.long.byte 0x4 24.--31. 1. "TXEEDC,TX Event Element Dequeuing Counter" hexmask.long.byte 0x4 16.--23. 1. "RX1EDC,RX1 Element Dequeuing Counter" newline hexmask.long.byte 0x4 8.--15. 1. "RX0EDC,RX0 Element Dequeuing Counter" hexmask.long.byte 0x4 0.--7. 1. "TXEEC,TX Element Enqueuing Counter" line.long 0x8 "DMUIR,DMU Interrupt Register" bitfld.long 0x8 30. "IAC,Illegal Access while in Configuration mode" "0: No Illegal Access while CCE mode,1: Illegal Access while CCE mode" bitfld.long 0x8 29. "DT,Debug Trigger" "0: Debug point not reached,1: Debug point reached" newline bitfld.long 0x8 28. "TXEED,TX Event Element Dequeued" "0: No TX Event Element dequeued,1: TX Event Element successfully dequeued" bitfld.long 0x8 27. "TXEEIW,TX Event Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU TX Event Element.." newline bitfld.long 0x8 26. "TXEEIAS,TX Event Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 25. "TXEEID,TX Event Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 24. "TXEENSA,TX Event Element Not Start Address" "0: No illegal read access,1: Read from TX Event Element begins without using.." bitfld.long 0x8 21. "RX1EIO,RX1 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 20. "RX1ED,RX1 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 19. "RX1EIW,RX1 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 18. "RX1EIAS,RX1 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 17. "RX1EID,RX1 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 16. "RX1ENSA,RX1 Element Not Start Address" "0: No illegal read access,1: Read from RX1 Element begins without using start.." bitfld.long 0x8 15. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Uncorrected bit error detected" newline bitfld.long 0x8 14. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected" bitfld.long 0x8 13. "RX0EIO,RX0 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 12. "RX0ED,RX0 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 11. "RX0EIW,RX0 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 10. "RX0EIAS,RX0 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 9. "RX0EID,RX0 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 8. "RX0ENSA,RX0 Element Not Start Address" "0: No illegal read access,1: Read from RX0 Element begins without using start.." bitfld.long 0x8 6. "TXEE,TX Element Enqueued" "0: No Tx message enqueued,1: Tx message successfully enqueued" newline bitfld.long 0x8 5. "TXEIR,TX Element Illegal Read" "0: No read access,1: Illegal read access to DMU TX Element section.." bitfld.long 0x8 4. "TXEWATA,TX Element Write After Trigger Address" "0: No write after Trigger Address,1: Enqueue a message" newline bitfld.long 0x8 3. "TXEIDLC,TX Element Illegal DLC" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." bitfld.long 0x8 2. "TXEIAS,TX Element Illegal Access Sequence" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." newline bitfld.long 0x8 1. "TXEIE,TX Element Illegal Enqueuing" "0: No illegal enqueuing,1: Start of enqueuing without request detected.." bitfld.long 0x8 0. "TXENSA,TX Element Not Start Address" "0: No illegal write access,1: Write to TX Element begins without using start.." line.long 0xC "DMUIE,DMU Interrupt Enable register" bitfld.long 0xC 30. "IACE,Illegal Access while in Configuration mode Enable" "0: Flag DMUIR.IAC does not activate the interrupt..,1: If DMUIR.IAC = 1 the interrupt line dmu_int will.." bitfld.long 0xC 29. "DTE,Debug Trigger Enable" "0: Flag DMUIR.DT does not activate the interrupt..,1: If DMUIR.DT = 1 the interrupt line dmu_int will.." newline bitfld.long 0xC 28. "TXEEDE,TX Event Element Dequeued" "0: Flag DMUIR.TXEED does not activate the interrupt..,1: If DMUIR.TXEED = 1 the interrupt line dmu_int.." bitfld.long 0xC 27. "TXEEIWE,TX Event Element Illegal Write" "0: Flag DMUIR.TXEEIW does not activate the..,1: If DMUIR.TXEEIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 26. "TXEEIASE,TX Event Element Illegal Access Sequence" "0: Flag DMUIR.TXEEIAS does not activate the..,1: If DMUIR.TXEEIAS = 1 the interrupt line dmu_int.." bitfld.long 0xC 25. "TXEEIDE,TX Event Element Illegal Dequeuing" "0: Flag DMUIR.TXEEID does not activate the..,1: If DMUIR.TXEEID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 24. "TXEENSAE,TX Event Element Not Start Address" "0: Flag TXEENSA.TXEENSA does not activate the..,1: If TXEENSA.TXEENSA = 1 the interrupt line.." bitfld.long 0xC 21. "RX1EIOE,RX1 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX1EIO does not activate the..,1: If TXEENSA.RX1EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 20. "RX1EDE,RX1 Element Dequeued Enable" "0: Flag TXEENSA.RX1ED does not activate the..,1: If TXEENSA.RX1ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 19. "RX1EIWE,RX1 Element Illegal Write Enable" "0: Flag TXEENSA.RX1EIW does not activate the..,1: If TXEENSA.RX1EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 18. "RX1EIASE,RX1 Element Illegal Access Sequence Enable" "0: Flag TXEENSA.RX1EIAS does not activate the..,1: If TXEENSA.RX1EIAS = 1 the interrupt line.." bitfld.long 0xC 17. "RX1EIDE,RX1 Element Illegal Dequeuing Enable" "0: Flag TXEENSA.RX1EID does not activate the..,1: If TXEENSA.RX1EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 16. "RX1ENSAE,RX1 Element Not Start Address Enable" "0: Flag TXEENSA.RX1ENSA does not activate the..,1: If TXEENSA.RX1ENSA = 1 the interrupt line.." bitfld.long 0xC 15. "BEUE,Bit Error Uncorrected Enable" "0: Flag TXEENSA.BEU does not activate the interrupt..,1: If TXEENSA.BEU = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 14. "BECE,Bit Error Corrected Enable" "0: Flag TXEENSA.BEC does not activate the interrupt..,1: If TXEENSA.BEC = 1 the interrupt line dmu_int.." bitfld.long 0xC 13. "RX0EIOE,RX0 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX0EIO does not activate the..,1: If TXEENSA.RX0EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 12. "RX0EDE,RX0 Element Dequeued Enabled" "0: Flag TXEENSA.RX0ED does not activate the..,1: If TXEENSA.RX0ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 11. "RX0EIWE,RX0 Element Illegal Write Enabled" "0: Flag TXEENSA.RX0EIW does not activate the..,1: If TXEENSA.RX0EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 10. "RX0EIASE,RX0 Element Illegal Access Sequence Enabled" "0: Flag TXEENSA.RX0EIAS does not activate the..,1: If TXEENSA.RX0EIAS = 1 the interrupt line.." bitfld.long 0xC 9. "RX0EIDE,RX0 Element Illegal Dequeuing Enabled" "0: Flag TXEENSA.RX0EID does not activate the..,1: If TXEENSA.RX0EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 8. "RX0ENSAE,RX0 Element Not Start Address Enabled" "0: Flag TXEENSA.RX0ENSA does not activate the..,1: If TXEENSA.RX0ENSA = 1 the interrupt line.." bitfld.long 0xC 6. "TXEEE,TX Element Enqueued Enable" "0: Flag TXEENSA.TXEE does not activate the..,1: If TXEENSA.TXEE = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 5. "TXEIRE,TX Element Illegal Read Enable" "0: Flag TXEENSA.TXEIR does not activate the..,1: If TXEENSA.TXEIR = 1 the interrupt line dmu_int.." bitfld.long 0xC 4. "TXEWATAE,TX Element Write After Trigger Address Enable" "0: Flag TXEENSA.TXEWATA does not activate the..,1: If TXEENSA.TXEWATA = 1 the interrupt line.." newline bitfld.long 0xC 3. "TXEIDLCE,TX Element Illegal DLC Enable" "0: Flag TXEENSA.TXEIDLC does not activate the..,1: If TXEENSA.TXEIDLC = 1 the interrupt line.." bitfld.long 0xC 2. "TXEIASE,TX Element Illegal Access Sequence Enable" "0: Flag TXEENSA.TXEIAS does not activate the..,1: If TXEENSA.TXEIAS = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 1. "TXEIEE,TX Element Illegal Enqueuing Enable" "0: Flag TXEENSA.TXEIE does not activate the..,1: If TXEENSA.TXEIE = 1 the interrupt line dmu_int.." bitfld.long 0xC 0. "TXENSAE,TX Element Not Start Address Enable" "0: Flag DMUIR.TXENSA does not activate the..,1: If DMUIR.TXENSA = 1 the interrupt line dmu_int.." line.long 0x10 "DMUC,DMU Configuration register" bitfld.long 0x10 0. "TTS,Transfer Timestamp" "0: No timestamp will be transferred via DMU Virtual..,1: Timestamp of message will be transferred from.." tree.end tree "CAN_SUB_3_DMU_2" base ad:0x70834000 rgroup.long 0x3C0++0x3 line.long 0x0 "DMUCR,DMU Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" group.long 0x3C4++0x13 line.long 0x0 "DMUI,DMU Internals register" bitfld.long 0x0 31. "TXE,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 30. "RX1,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 29. "RX0,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 28. "TX,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 24.--26. "EHS,Element Handler State" "0: wait for bit M_CAN:CCCR.CCE getting zero,1: wait for Start Address,2: wait for Trigger Address,3: wait for transfer of Element word,4: acknowledge to M_CAN,5: exception recovery,?,?" bitfld.long 0x0 23. "DTXE,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 22. "DTX1,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 21. "DTX0,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 20. "DTX,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 16.--18. "DEHS,Detect Element Handler State" "?,?,?,?,?,?,?,7: unused state" newline bitfld.long 0x0 15. "ENA,DMU is enabled" "0: DMU is disabled,1: DMU is enabled and can process DMA data" hexmask.long.byte 0x0 8.--12. 1. "TFQPIP,TX FIFO/Queue Put Index Previous" newline bitfld.long 0x0 3. "TXER,TX Event Service Request line of DMU" "0: No TX Event DMA service requested,1: TX Event DMA Service requested" bitfld.long 0x0 2. "RX1R,RX1 Service Request line of DMU" "0: No RX1 DMA service requested,1: RX1 DMA Service requested" newline bitfld.long 0x0 1. "RX0R,RX0 Service Request line of DMU" "0: No RX0 DMA service requested,1: RX0 DMA Service requested" bitfld.long 0x0 0. "TXR,TX Service Request line of DMU" "0: No TX DMA service requested,1: TX DMA Service requested" line.long 0x4 "DMUQC,DMU Queuing Counter register" hexmask.long.byte 0x4 24.--31. 1. "TXEEDC,TX Event Element Dequeuing Counter" hexmask.long.byte 0x4 16.--23. 1. "RX1EDC,RX1 Element Dequeuing Counter" newline hexmask.long.byte 0x4 8.--15. 1. "RX0EDC,RX0 Element Dequeuing Counter" hexmask.long.byte 0x4 0.--7. 1. "TXEEC,TX Element Enqueuing Counter" line.long 0x8 "DMUIR,DMU Interrupt Register" bitfld.long 0x8 30. "IAC,Illegal Access while in Configuration mode" "0: No Illegal Access while CCE mode,1: Illegal Access while CCE mode" bitfld.long 0x8 29. "DT,Debug Trigger" "0: Debug point not reached,1: Debug point reached" newline bitfld.long 0x8 28. "TXEED,TX Event Element Dequeued" "0: No TX Event Element dequeued,1: TX Event Element successfully dequeued" bitfld.long 0x8 27. "TXEEIW,TX Event Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU TX Event Element.." newline bitfld.long 0x8 26. "TXEEIAS,TX Event Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 25. "TXEEID,TX Event Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 24. "TXEENSA,TX Event Element Not Start Address" "0: No illegal read access,1: Read from TX Event Element begins without using.." bitfld.long 0x8 21. "RX1EIO,RX1 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 20. "RX1ED,RX1 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 19. "RX1EIW,RX1 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 18. "RX1EIAS,RX1 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 17. "RX1EID,RX1 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 16. "RX1ENSA,RX1 Element Not Start Address" "0: No illegal read access,1: Read from RX1 Element begins without using start.." bitfld.long 0x8 15. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Uncorrected bit error detected" newline bitfld.long 0x8 14. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected" bitfld.long 0x8 13. "RX0EIO,RX0 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 12. "RX0ED,RX0 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 11. "RX0EIW,RX0 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 10. "RX0EIAS,RX0 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 9. "RX0EID,RX0 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 8. "RX0ENSA,RX0 Element Not Start Address" "0: No illegal read access,1: Read from RX0 Element begins without using start.." bitfld.long 0x8 6. "TXEE,TX Element Enqueued" "0: No Tx message enqueued,1: Tx message successfully enqueued" newline bitfld.long 0x8 5. "TXEIR,TX Element Illegal Read" "0: No read access,1: Illegal read access to DMU TX Element section.." bitfld.long 0x8 4. "TXEWATA,TX Element Write After Trigger Address" "0: No write after Trigger Address,1: Enqueue a message" newline bitfld.long 0x8 3. "TXEIDLC,TX Element Illegal DLC" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." bitfld.long 0x8 2. "TXEIAS,TX Element Illegal Access Sequence" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." newline bitfld.long 0x8 1. "TXEIE,TX Element Illegal Enqueuing" "0: No illegal enqueuing,1: Start of enqueuing without request detected.." bitfld.long 0x8 0. "TXENSA,TX Element Not Start Address" "0: No illegal write access,1: Write to TX Element begins without using start.." line.long 0xC "DMUIE,DMU Interrupt Enable register" bitfld.long 0xC 30. "IACE,Illegal Access while in Configuration mode Enable" "0: Flag DMUIR.IAC does not activate the interrupt..,1: If DMUIR.IAC = 1 the interrupt line dmu_int will.." bitfld.long 0xC 29. "DTE,Debug Trigger Enable" "0: Flag DMUIR.DT does not activate the interrupt..,1: If DMUIR.DT = 1 the interrupt line dmu_int will.." newline bitfld.long 0xC 28. "TXEEDE,TX Event Element Dequeued" "0: Flag DMUIR.TXEED does not activate the interrupt..,1: If DMUIR.TXEED = 1 the interrupt line dmu_int.." bitfld.long 0xC 27. "TXEEIWE,TX Event Element Illegal Write" "0: Flag DMUIR.TXEEIW does not activate the..,1: If DMUIR.TXEEIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 26. "TXEEIASE,TX Event Element Illegal Access Sequence" "0: Flag DMUIR.TXEEIAS does not activate the..,1: If DMUIR.TXEEIAS = 1 the interrupt line dmu_int.." bitfld.long 0xC 25. "TXEEIDE,TX Event Element Illegal Dequeuing" "0: Flag DMUIR.TXEEID does not activate the..,1: If DMUIR.TXEEID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 24. "TXEENSAE,TX Event Element Not Start Address" "0: Flag TXEENSA.TXEENSA does not activate the..,1: If TXEENSA.TXEENSA = 1 the interrupt line.." bitfld.long 0xC 21. "RX1EIOE,RX1 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX1EIO does not activate the..,1: If TXEENSA.RX1EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 20. "RX1EDE,RX1 Element Dequeued Enable" "0: Flag TXEENSA.RX1ED does not activate the..,1: If TXEENSA.RX1ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 19. "RX1EIWE,RX1 Element Illegal Write Enable" "0: Flag TXEENSA.RX1EIW does not activate the..,1: If TXEENSA.RX1EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 18. "RX1EIASE,RX1 Element Illegal Access Sequence Enable" "0: Flag TXEENSA.RX1EIAS does not activate the..,1: If TXEENSA.RX1EIAS = 1 the interrupt line.." bitfld.long 0xC 17. "RX1EIDE,RX1 Element Illegal Dequeuing Enable" "0: Flag TXEENSA.RX1EID does not activate the..,1: If TXEENSA.RX1EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 16. "RX1ENSAE,RX1 Element Not Start Address Enable" "0: Flag TXEENSA.RX1ENSA does not activate the..,1: If TXEENSA.RX1ENSA = 1 the interrupt line.." bitfld.long 0xC 15. "BEUE,Bit Error Uncorrected Enable" "0: Flag TXEENSA.BEU does not activate the interrupt..,1: If TXEENSA.BEU = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 14. "BECE,Bit Error Corrected Enable" "0: Flag TXEENSA.BEC does not activate the interrupt..,1: If TXEENSA.BEC = 1 the interrupt line dmu_int.." bitfld.long 0xC 13. "RX0EIOE,RX0 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX0EIO does not activate the..,1: If TXEENSA.RX0EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 12. "RX0EDE,RX0 Element Dequeued Enabled" "0: Flag TXEENSA.RX0ED does not activate the..,1: If TXEENSA.RX0ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 11. "RX0EIWE,RX0 Element Illegal Write Enabled" "0: Flag TXEENSA.RX0EIW does not activate the..,1: If TXEENSA.RX0EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 10. "RX0EIASE,RX0 Element Illegal Access Sequence Enabled" "0: Flag TXEENSA.RX0EIAS does not activate the..,1: If TXEENSA.RX0EIAS = 1 the interrupt line.." bitfld.long 0xC 9. "RX0EIDE,RX0 Element Illegal Dequeuing Enabled" "0: Flag TXEENSA.RX0EID does not activate the..,1: If TXEENSA.RX0EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 8. "RX0ENSAE,RX0 Element Not Start Address Enabled" "0: Flag TXEENSA.RX0ENSA does not activate the..,1: If TXEENSA.RX0ENSA = 1 the interrupt line.." bitfld.long 0xC 6. "TXEEE,TX Element Enqueued Enable" "0: Flag TXEENSA.TXEE does not activate the..,1: If TXEENSA.TXEE = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 5. "TXEIRE,TX Element Illegal Read Enable" "0: Flag TXEENSA.TXEIR does not activate the..,1: If TXEENSA.TXEIR = 1 the interrupt line dmu_int.." bitfld.long 0xC 4. "TXEWATAE,TX Element Write After Trigger Address Enable" "0: Flag TXEENSA.TXEWATA does not activate the..,1: If TXEENSA.TXEWATA = 1 the interrupt line.." newline bitfld.long 0xC 3. "TXEIDLCE,TX Element Illegal DLC Enable" "0: Flag TXEENSA.TXEIDLC does not activate the..,1: If TXEENSA.TXEIDLC = 1 the interrupt line.." bitfld.long 0xC 2. "TXEIASE,TX Element Illegal Access Sequence Enable" "0: Flag TXEENSA.TXEIAS does not activate the..,1: If TXEENSA.TXEIAS = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 1. "TXEIEE,TX Element Illegal Enqueuing Enable" "0: Flag TXEENSA.TXEIE does not activate the..,1: If TXEENSA.TXEIE = 1 the interrupt line dmu_int.." bitfld.long 0xC 0. "TXENSAE,TX Element Not Start Address Enable" "0: Flag DMUIR.TXENSA does not activate the..,1: If DMUIR.TXENSA = 1 the interrupt line dmu_int.." line.long 0x10 "DMUC,DMU Configuration register" bitfld.long 0x10 0. "TTS,Transfer Timestamp" "0: No timestamp will be transferred via DMU Virtual..,1: Timestamp of message will be transferred from.." tree.end tree "CAN_SUB_3_DMU_3" base ad:0x70838000 rgroup.long 0x3C0++0x3 line.long 0x0 "DMUCR,DMU Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" group.long 0x3C4++0x13 line.long 0x0 "DMUI,DMU Internals register" bitfld.long 0x0 31. "TXE,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 30. "RX1,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 29. "RX0,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 28. "TX,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 24.--26. "EHS,Element Handler State" "0: wait for bit M_CAN:CCCR.CCE getting zero,1: wait for Start Address,2: wait for Trigger Address,3: wait for transfer of Element word,4: acknowledge to M_CAN,5: exception recovery,?,?" bitfld.long 0x0 23. "DTXE,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 22. "DTX1,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 21. "DTX0,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 20. "DTX,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 16.--18. "DEHS,Detect Element Handler State" "?,?,?,?,?,?,?,7: unused state" newline bitfld.long 0x0 15. "ENA,DMU is enabled" "0: DMU is disabled,1: DMU is enabled and can process DMA data" hexmask.long.byte 0x0 8.--12. 1. "TFQPIP,TX FIFO/Queue Put Index Previous" newline bitfld.long 0x0 3. "TXER,TX Event Service Request line of DMU" "0: No TX Event DMA service requested,1: TX Event DMA Service requested" bitfld.long 0x0 2. "RX1R,RX1 Service Request line of DMU" "0: No RX1 DMA service requested,1: RX1 DMA Service requested" newline bitfld.long 0x0 1. "RX0R,RX0 Service Request line of DMU" "0: No RX0 DMA service requested,1: RX0 DMA Service requested" bitfld.long 0x0 0. "TXR,TX Service Request line of DMU" "0: No TX DMA service requested,1: TX DMA Service requested" line.long 0x4 "DMUQC,DMU Queuing Counter register" hexmask.long.byte 0x4 24.--31. 1. "TXEEDC,TX Event Element Dequeuing Counter" hexmask.long.byte 0x4 16.--23. 1. "RX1EDC,RX1 Element Dequeuing Counter" newline hexmask.long.byte 0x4 8.--15. 1. "RX0EDC,RX0 Element Dequeuing Counter" hexmask.long.byte 0x4 0.--7. 1. "TXEEC,TX Element Enqueuing Counter" line.long 0x8 "DMUIR,DMU Interrupt Register" bitfld.long 0x8 30. "IAC,Illegal Access while in Configuration mode" "0: No Illegal Access while CCE mode,1: Illegal Access while CCE mode" bitfld.long 0x8 29. "DT,Debug Trigger" "0: Debug point not reached,1: Debug point reached" newline bitfld.long 0x8 28. "TXEED,TX Event Element Dequeued" "0: No TX Event Element dequeued,1: TX Event Element successfully dequeued" bitfld.long 0x8 27. "TXEEIW,TX Event Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU TX Event Element.." newline bitfld.long 0x8 26. "TXEEIAS,TX Event Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 25. "TXEEID,TX Event Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 24. "TXEENSA,TX Event Element Not Start Address" "0: No illegal read access,1: Read from TX Event Element begins without using.." bitfld.long 0x8 21. "RX1EIO,RX1 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 20. "RX1ED,RX1 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 19. "RX1EIW,RX1 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 18. "RX1EIAS,RX1 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 17. "RX1EID,RX1 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 16. "RX1ENSA,RX1 Element Not Start Address" "0: No illegal read access,1: Read from RX1 Element begins without using start.." bitfld.long 0x8 15. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Uncorrected bit error detected" newline bitfld.long 0x8 14. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected" bitfld.long 0x8 13. "RX0EIO,RX0 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 12. "RX0ED,RX0 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 11. "RX0EIW,RX0 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 10. "RX0EIAS,RX0 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 9. "RX0EID,RX0 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 8. "RX0ENSA,RX0 Element Not Start Address" "0: No illegal read access,1: Read from RX0 Element begins without using start.." bitfld.long 0x8 6. "TXEE,TX Element Enqueued" "0: No Tx message enqueued,1: Tx message successfully enqueued" newline bitfld.long 0x8 5. "TXEIR,TX Element Illegal Read" "0: No read access,1: Illegal read access to DMU TX Element section.." bitfld.long 0x8 4. "TXEWATA,TX Element Write After Trigger Address" "0: No write after Trigger Address,1: Enqueue a message" newline bitfld.long 0x8 3. "TXEIDLC,TX Element Illegal DLC" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." bitfld.long 0x8 2. "TXEIAS,TX Element Illegal Access Sequence" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." newline bitfld.long 0x8 1. "TXEIE,TX Element Illegal Enqueuing" "0: No illegal enqueuing,1: Start of enqueuing without request detected.." bitfld.long 0x8 0. "TXENSA,TX Element Not Start Address" "0: No illegal write access,1: Write to TX Element begins without using start.." line.long 0xC "DMUIE,DMU Interrupt Enable register" bitfld.long 0xC 30. "IACE,Illegal Access while in Configuration mode Enable" "0: Flag DMUIR.IAC does not activate the interrupt..,1: If DMUIR.IAC = 1 the interrupt line dmu_int will.." bitfld.long 0xC 29. "DTE,Debug Trigger Enable" "0: Flag DMUIR.DT does not activate the interrupt..,1: If DMUIR.DT = 1 the interrupt line dmu_int will.." newline bitfld.long 0xC 28. "TXEEDE,TX Event Element Dequeued" "0: Flag DMUIR.TXEED does not activate the interrupt..,1: If DMUIR.TXEED = 1 the interrupt line dmu_int.." bitfld.long 0xC 27. "TXEEIWE,TX Event Element Illegal Write" "0: Flag DMUIR.TXEEIW does not activate the..,1: If DMUIR.TXEEIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 26. "TXEEIASE,TX Event Element Illegal Access Sequence" "0: Flag DMUIR.TXEEIAS does not activate the..,1: If DMUIR.TXEEIAS = 1 the interrupt line dmu_int.." bitfld.long 0xC 25. "TXEEIDE,TX Event Element Illegal Dequeuing" "0: Flag DMUIR.TXEEID does not activate the..,1: If DMUIR.TXEEID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 24. "TXEENSAE,TX Event Element Not Start Address" "0: Flag TXEENSA.TXEENSA does not activate the..,1: If TXEENSA.TXEENSA = 1 the interrupt line.." bitfld.long 0xC 21. "RX1EIOE,RX1 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX1EIO does not activate the..,1: If TXEENSA.RX1EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 20. "RX1EDE,RX1 Element Dequeued Enable" "0: Flag TXEENSA.RX1ED does not activate the..,1: If TXEENSA.RX1ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 19. "RX1EIWE,RX1 Element Illegal Write Enable" "0: Flag TXEENSA.RX1EIW does not activate the..,1: If TXEENSA.RX1EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 18. "RX1EIASE,RX1 Element Illegal Access Sequence Enable" "0: Flag TXEENSA.RX1EIAS does not activate the..,1: If TXEENSA.RX1EIAS = 1 the interrupt line.." bitfld.long 0xC 17. "RX1EIDE,RX1 Element Illegal Dequeuing Enable" "0: Flag TXEENSA.RX1EID does not activate the..,1: If TXEENSA.RX1EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 16. "RX1ENSAE,RX1 Element Not Start Address Enable" "0: Flag TXEENSA.RX1ENSA does not activate the..,1: If TXEENSA.RX1ENSA = 1 the interrupt line.." bitfld.long 0xC 15. "BEUE,Bit Error Uncorrected Enable" "0: Flag TXEENSA.BEU does not activate the interrupt..,1: If TXEENSA.BEU = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 14. "BECE,Bit Error Corrected Enable" "0: Flag TXEENSA.BEC does not activate the interrupt..,1: If TXEENSA.BEC = 1 the interrupt line dmu_int.." bitfld.long 0xC 13. "RX0EIOE,RX0 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX0EIO does not activate the..,1: If TXEENSA.RX0EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 12. "RX0EDE,RX0 Element Dequeued Enabled" "0: Flag TXEENSA.RX0ED does not activate the..,1: If TXEENSA.RX0ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 11. "RX0EIWE,RX0 Element Illegal Write Enabled" "0: Flag TXEENSA.RX0EIW does not activate the..,1: If TXEENSA.RX0EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 10. "RX0EIASE,RX0 Element Illegal Access Sequence Enabled" "0: Flag TXEENSA.RX0EIAS does not activate the..,1: If TXEENSA.RX0EIAS = 1 the interrupt line.." bitfld.long 0xC 9. "RX0EIDE,RX0 Element Illegal Dequeuing Enabled" "0: Flag TXEENSA.RX0EID does not activate the..,1: If TXEENSA.RX0EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 8. "RX0ENSAE,RX0 Element Not Start Address Enabled" "0: Flag TXEENSA.RX0ENSA does not activate the..,1: If TXEENSA.RX0ENSA = 1 the interrupt line.." bitfld.long 0xC 6. "TXEEE,TX Element Enqueued Enable" "0: Flag TXEENSA.TXEE does not activate the..,1: If TXEENSA.TXEE = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 5. "TXEIRE,TX Element Illegal Read Enable" "0: Flag TXEENSA.TXEIR does not activate the..,1: If TXEENSA.TXEIR = 1 the interrupt line dmu_int.." bitfld.long 0xC 4. "TXEWATAE,TX Element Write After Trigger Address Enable" "0: Flag TXEENSA.TXEWATA does not activate the..,1: If TXEENSA.TXEWATA = 1 the interrupt line.." newline bitfld.long 0xC 3. "TXEIDLCE,TX Element Illegal DLC Enable" "0: Flag TXEENSA.TXEIDLC does not activate the..,1: If TXEENSA.TXEIDLC = 1 the interrupt line.." bitfld.long 0xC 2. "TXEIASE,TX Element Illegal Access Sequence Enable" "0: Flag TXEENSA.TXEIAS does not activate the..,1: If TXEENSA.TXEIAS = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 1. "TXEIEE,TX Element Illegal Enqueuing Enable" "0: Flag TXEENSA.TXEIE does not activate the..,1: If TXEENSA.TXEIE = 1 the interrupt line dmu_int.." bitfld.long 0xC 0. "TXENSAE,TX Element Not Start Address Enable" "0: Flag DMUIR.TXENSA does not activate the..,1: If DMUIR.TXENSA = 1 the interrupt line dmu_int.." line.long 0x10 "DMUC,DMU Configuration register" bitfld.long 0x10 0. "TTS,Transfer Timestamp" "0: No timestamp will be transferred via DMU Virtual..,1: Timestamp of message will be transferred from.." tree.end tree "CAN_SUB_3_DMU_4" base ad:0x7083C000 rgroup.long 0x3C0++0x3 line.long 0x0 "DMUCR,DMU Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" group.long 0x3C4++0x13 line.long 0x0 "DMUI,DMU Internals register" bitfld.long 0x0 31. "TXE,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 30. "RX1,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 29. "RX0,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 28. "TX,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 24.--26. "EHS,Element Handler State" "0: wait for bit M_CAN:CCCR.CCE getting zero,1: wait for Start Address,2: wait for Trigger Address,3: wait for transfer of Element word,4: acknowledge to M_CAN,5: exception recovery,?,?" bitfld.long 0x0 23. "DTXE,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 22. "DTX1,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 21. "DTX0,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 20. "DTX,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 16.--18. "DEHS,Detect Element Handler State" "?,?,?,?,?,?,?,7: unused state" newline bitfld.long 0x0 15. "ENA,DMU is enabled" "0: DMU is disabled,1: DMU is enabled and can process DMA data" hexmask.long.byte 0x0 8.--12. 1. "TFQPIP,TX FIFO/Queue Put Index Previous" newline bitfld.long 0x0 3. "TXER,TX Event Service Request line of DMU" "0: No TX Event DMA service requested,1: TX Event DMA Service requested" bitfld.long 0x0 2. "RX1R,RX1 Service Request line of DMU" "0: No RX1 DMA service requested,1: RX1 DMA Service requested" newline bitfld.long 0x0 1. "RX0R,RX0 Service Request line of DMU" "0: No RX0 DMA service requested,1: RX0 DMA Service requested" bitfld.long 0x0 0. "TXR,TX Service Request line of DMU" "0: No TX DMA service requested,1: TX DMA Service requested" line.long 0x4 "DMUQC,DMU Queuing Counter register" hexmask.long.byte 0x4 24.--31. 1. "TXEEDC,TX Event Element Dequeuing Counter" hexmask.long.byte 0x4 16.--23. 1. "RX1EDC,RX1 Element Dequeuing Counter" newline hexmask.long.byte 0x4 8.--15. 1. "RX0EDC,RX0 Element Dequeuing Counter" hexmask.long.byte 0x4 0.--7. 1. "TXEEC,TX Element Enqueuing Counter" line.long 0x8 "DMUIR,DMU Interrupt Register" bitfld.long 0x8 30. "IAC,Illegal Access while in Configuration mode" "0: No Illegal Access while CCE mode,1: Illegal Access while CCE mode" bitfld.long 0x8 29. "DT,Debug Trigger" "0: Debug point not reached,1: Debug point reached" newline bitfld.long 0x8 28. "TXEED,TX Event Element Dequeued" "0: No TX Event Element dequeued,1: TX Event Element successfully dequeued" bitfld.long 0x8 27. "TXEEIW,TX Event Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU TX Event Element.." newline bitfld.long 0x8 26. "TXEEIAS,TX Event Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 25. "TXEEID,TX Event Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 24. "TXEENSA,TX Event Element Not Start Address" "0: No illegal read access,1: Read from TX Event Element begins without using.." bitfld.long 0x8 21. "RX1EIO,RX1 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 20. "RX1ED,RX1 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 19. "RX1EIW,RX1 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 18. "RX1EIAS,RX1 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 17. "RX1EID,RX1 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 16. "RX1ENSA,RX1 Element Not Start Address" "0: No illegal read access,1: Read from RX1 Element begins without using start.." bitfld.long 0x8 15. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Uncorrected bit error detected" newline bitfld.long 0x8 14. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected" bitfld.long 0x8 13. "RX0EIO,RX0 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 12. "RX0ED,RX0 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 11. "RX0EIW,RX0 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 10. "RX0EIAS,RX0 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 9. "RX0EID,RX0 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 8. "RX0ENSA,RX0 Element Not Start Address" "0: No illegal read access,1: Read from RX0 Element begins without using start.." bitfld.long 0x8 6. "TXEE,TX Element Enqueued" "0: No Tx message enqueued,1: Tx message successfully enqueued" newline bitfld.long 0x8 5. "TXEIR,TX Element Illegal Read" "0: No read access,1: Illegal read access to DMU TX Element section.." bitfld.long 0x8 4. "TXEWATA,TX Element Write After Trigger Address" "0: No write after Trigger Address,1: Enqueue a message" newline bitfld.long 0x8 3. "TXEIDLC,TX Element Illegal DLC" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." bitfld.long 0x8 2. "TXEIAS,TX Element Illegal Access Sequence" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." newline bitfld.long 0x8 1. "TXEIE,TX Element Illegal Enqueuing" "0: No illegal enqueuing,1: Start of enqueuing without request detected.." bitfld.long 0x8 0. "TXENSA,TX Element Not Start Address" "0: No illegal write access,1: Write to TX Element begins without using start.." line.long 0xC "DMUIE,DMU Interrupt Enable register" bitfld.long 0xC 30. "IACE,Illegal Access while in Configuration mode Enable" "0: Flag DMUIR.IAC does not activate the interrupt..,1: If DMUIR.IAC = 1 the interrupt line dmu_int will.." bitfld.long 0xC 29. "DTE,Debug Trigger Enable" "0: Flag DMUIR.DT does not activate the interrupt..,1: If DMUIR.DT = 1 the interrupt line dmu_int will.." newline bitfld.long 0xC 28. "TXEEDE,TX Event Element Dequeued" "0: Flag DMUIR.TXEED does not activate the interrupt..,1: If DMUIR.TXEED = 1 the interrupt line dmu_int.." bitfld.long 0xC 27. "TXEEIWE,TX Event Element Illegal Write" "0: Flag DMUIR.TXEEIW does not activate the..,1: If DMUIR.TXEEIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 26. "TXEEIASE,TX Event Element Illegal Access Sequence" "0: Flag DMUIR.TXEEIAS does not activate the..,1: If DMUIR.TXEEIAS = 1 the interrupt line dmu_int.." bitfld.long 0xC 25. "TXEEIDE,TX Event Element Illegal Dequeuing" "0: Flag DMUIR.TXEEID does not activate the..,1: If DMUIR.TXEEID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 24. "TXEENSAE,TX Event Element Not Start Address" "0: Flag TXEENSA.TXEENSA does not activate the..,1: If TXEENSA.TXEENSA = 1 the interrupt line.." bitfld.long 0xC 21. "RX1EIOE,RX1 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX1EIO does not activate the..,1: If TXEENSA.RX1EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 20. "RX1EDE,RX1 Element Dequeued Enable" "0: Flag TXEENSA.RX1ED does not activate the..,1: If TXEENSA.RX1ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 19. "RX1EIWE,RX1 Element Illegal Write Enable" "0: Flag TXEENSA.RX1EIW does not activate the..,1: If TXEENSA.RX1EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 18. "RX1EIASE,RX1 Element Illegal Access Sequence Enable" "0: Flag TXEENSA.RX1EIAS does not activate the..,1: If TXEENSA.RX1EIAS = 1 the interrupt line.." bitfld.long 0xC 17. "RX1EIDE,RX1 Element Illegal Dequeuing Enable" "0: Flag TXEENSA.RX1EID does not activate the..,1: If TXEENSA.RX1EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 16. "RX1ENSAE,RX1 Element Not Start Address Enable" "0: Flag TXEENSA.RX1ENSA does not activate the..,1: If TXEENSA.RX1ENSA = 1 the interrupt line.." bitfld.long 0xC 15. "BEUE,Bit Error Uncorrected Enable" "0: Flag TXEENSA.BEU does not activate the interrupt..,1: If TXEENSA.BEU = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 14. "BECE,Bit Error Corrected Enable" "0: Flag TXEENSA.BEC does not activate the interrupt..,1: If TXEENSA.BEC = 1 the interrupt line dmu_int.." bitfld.long 0xC 13. "RX0EIOE,RX0 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX0EIO does not activate the..,1: If TXEENSA.RX0EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 12. "RX0EDE,RX0 Element Dequeued Enabled" "0: Flag TXEENSA.RX0ED does not activate the..,1: If TXEENSA.RX0ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 11. "RX0EIWE,RX0 Element Illegal Write Enabled" "0: Flag TXEENSA.RX0EIW does not activate the..,1: If TXEENSA.RX0EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 10. "RX0EIASE,RX0 Element Illegal Access Sequence Enabled" "0: Flag TXEENSA.RX0EIAS does not activate the..,1: If TXEENSA.RX0EIAS = 1 the interrupt line.." bitfld.long 0xC 9. "RX0EIDE,RX0 Element Illegal Dequeuing Enabled" "0: Flag TXEENSA.RX0EID does not activate the..,1: If TXEENSA.RX0EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 8. "RX0ENSAE,RX0 Element Not Start Address Enabled" "0: Flag TXEENSA.RX0ENSA does not activate the..,1: If TXEENSA.RX0ENSA = 1 the interrupt line.." bitfld.long 0xC 6. "TXEEE,TX Element Enqueued Enable" "0: Flag TXEENSA.TXEE does not activate the..,1: If TXEENSA.TXEE = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 5. "TXEIRE,TX Element Illegal Read Enable" "0: Flag TXEENSA.TXEIR does not activate the..,1: If TXEENSA.TXEIR = 1 the interrupt line dmu_int.." bitfld.long 0xC 4. "TXEWATAE,TX Element Write After Trigger Address Enable" "0: Flag TXEENSA.TXEWATA does not activate the..,1: If TXEENSA.TXEWATA = 1 the interrupt line.." newline bitfld.long 0xC 3. "TXEIDLCE,TX Element Illegal DLC Enable" "0: Flag TXEENSA.TXEIDLC does not activate the..,1: If TXEENSA.TXEIDLC = 1 the interrupt line.." bitfld.long 0xC 2. "TXEIASE,TX Element Illegal Access Sequence Enable" "0: Flag TXEENSA.TXEIAS does not activate the..,1: If TXEENSA.TXEIAS = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 1. "TXEIEE,TX Element Illegal Enqueuing Enable" "0: Flag TXEENSA.TXEIE does not activate the..,1: If TXEENSA.TXEIE = 1 the interrupt line dmu_int.." bitfld.long 0xC 0. "TXENSAE,TX Element Not Start Address Enable" "0: Flag DMUIR.TXENSA does not activate the..,1: If DMUIR.TXENSA = 1 the interrupt line dmu_int.." line.long 0x10 "DMUC,DMU Configuration register" bitfld.long 0x10 0. "TTS,Transfer Timestamp" "0: No timestamp will be transferred via DMU Virtual..,1: Timestamp of message will be transferred from.." tree.end tree "CAN_SUB_3_M_CAN_1" base ad:0x70830000 rgroup.long 0x0++0x7 line.long 0x0 "CREL,Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Substep of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "TS_MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "ENDN,Endian Register" hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value" group.long 0xC++0x23 line.long 0x0 "DBTP,Data Bit Timing and Prescaler Register" bitfld.long 0x0 23. "TDC,Transceiver Delay Compensation" "0: Transceiver Delay Compensation disabled,1: Transceiver Delay Compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re) Synchronization Jump Width" line.long 0x4 "TEST,Test register" bitfld.long 0x4 21. "SVAL,Started Valid" "0: Value of TXBNS not valid,1: Value of TXBNS valid" hexmask.long.byte 0x4 16.--20. 1. "TXBNS,Tx Buffer Number Started" newline bitfld.long 0x4 13. "PVAL,Prepared Valid" "0: Value of TXBNP not valid,1: Value of TXBNP valid" hexmask.long.byte 0x4 8.--12. 1. "TXBNP,Tx Buffer Number Prepared" newline bitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant (CAN Rx input = '0'),1: The CAN bus is recessive (CAN Rx input = '1')" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CAN Tx output is controlled by the..,1: Sample Point can be monitored at pin CAN Tx output,2: Dominant ('0') level at pin CAN Tx output,3: Recessive ('1') at pin CAN Tx output" newline bitfld.long 0x4 4. "LBCK,Loop Back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (refer to.." line.long 0x8 "RWD,RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration" line.long 0xC "CCCR,CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0xC 11. "WMM,Wide Message Marker" "0: 8-bit Message Marker used,1: 16-bit Message Marker used replacing 16-bit.." bitfld.long 0xC 10. "UTSU,Use Timestamping Unit" "0: Internal time stamping,1: External time stamping by TSU" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST_EN,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_CAN may be set in power down by stopping Host.." bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started" line.long 0x10 "NBTP,Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,(Re) Synchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Time segment before sample point" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,The time segment after the sample point" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Same as 00" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. "TOC,The Timeout Counter is decremented in multiples of CAN bit times (1 to 16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are.." rgroup.long 0x40++0x7 line.long 0x0 "ECR,Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "PSR,Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Received CAN FD Message" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set." newline bitfld.long 0x4 11. "RESI,ESI CAN FD Message with ESI flag" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state" bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state. It..,1: The M_CAN is in the Error_Passive state" bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing node is synchronizing on CAN..,1: Idle-node is neither receiver nor transmitter,2: Receiver-node is operating as receiver,3: Transmitter-node is operating as transmitter" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: consecutive recessive bits,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.." group.long 0x48++0x3 line.long 0x0 "TDCR,Transmitter Delay compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0xF line.long 0x0 "IR,Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected uncorrected (for example.." bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected (for example ECC)" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Event Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx Event FIDO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "IE,Interrupt Enable Register" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "ILS,Interrupt Line Select Register" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 16. "TSWL,TSWL: Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" line.long 0xC "ILE,Interrupt Line Enable Register" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line disabled,1: Interrupt line enabled" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line disabled,1: Interrupt line enabled" group.long 0x80++0xB line.long 0x0 "GFC,Global Filter Configuration Register" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,ANFE[1:0]: Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x8 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x3 line.long 0x0 "XIDAM,Extended ID and Mask Register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "HPMS,High Priority Message Status Register" bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "NDAT1,New Data 1 Register" bitfld.long 0x0 31. "ND31,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 30. "ND30,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 28. "ND28,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 26. "ND26,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 24. "ND24,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 22. "ND22,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 20. "ND20,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 18. "ND18,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 16. "ND16,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 14. "ND14,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 12. "ND12,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 10. "ND10,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 8. "ND8,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 6. "ND6,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 4. "ND4,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 2. "ND2,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 0. "ND0,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x4 "NDAT2,New Data 2 Register" bitfld.long 0x4 31. "ND63,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 30. "ND62,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 28. "ND60,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 26. "ND58,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 24. "ND56,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 22. "ND54,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 20. "ND52,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 18. "ND50,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 16. "ND48,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 14. "ND46,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 12. "ND44,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 10. "ND42,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 8. "ND40,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 6. "ND38,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 4. "ND36,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 2. "ND34,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 0. "ND32,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x8 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x0 25. "RF0L,RF0L" "0,1" bitfld.long 0x0 24. "F0F,F0F" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,F0PI" hexmask.long.byte 0x0 8.--13. 1. "F0GI,F0GI" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,F0FL" group.long 0xA8++0xB line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "RXF1C,Rx FIFO 1 Configuration Register" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,F1S[6:0]:" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is set" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" line.long 0x8 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Tx FIFO/Queue Size" newline hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x3 line.long 0x0 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x0 31. "AR31,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 30. "AR30,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 29. "AR29,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 28. "AR28,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 27. "AR27,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 26. "AR26,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 25. "AR25,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 24. "AR24,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 23. "AR23,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 22. "AR22,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 21. "AR21,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 20. "AR20,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 19. "AR19,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 18. "AR18,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 17. "AR17,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 16. "AR16,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 15. "AR15,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 14. "AR14,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 13. "AR13,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 12. "AR12,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 11. "AR11,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 10. "AR10,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 9. "AR9,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 8. "AR8,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 7. "AR7,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 6. "AR6,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 5. "AR5,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 4. "AR4,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 3. "AR3,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 2. "AR2,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 1. "AR1,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 0. "AR0,Add Request" "0: No transmission request added,1: Transmission requested added" line.long 0x4 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x4 31. "CR31,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 30. "CR30,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 29. "CR29,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 28. "CR28,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 27. "CR27,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 26. "CR26,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 24. "CR24,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 23. "CR23,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 22. "CR22,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 21. "CR21,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 20. "CR20,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 18. "CR18,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 17. "CR17,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 16. "CR16,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 15. "CR15,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 14. "CR14,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 12. "CR12,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 11. "CR11,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 10. "CR10,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 9. "CR9,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 8. "CR8,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 6. "CR6,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 5. "CR5,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 4. "CR4,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 3. "CR3,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 2. "CR2,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 0. "CR0,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" rgroup.long 0xD8++0x7 line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 29. "TO29,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 28. "TO28,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 27. "TO27,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 23. "TO23,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 22. "TO22,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 21. "TO21,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 17. "TO17,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 16. "TO16,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 15. "TO15,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 11. "TO11,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 10. "TO10,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 9. "TO9,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 5. "TO5,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 4. "TO4,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 3. "TO3,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 29. "CF29,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 28. "CF28,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 27. "CF27,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 23. "CF23,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 22. "CF22,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 21. "CF21,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 17. "CF17,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 16. "CF16,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 15. "CF15,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 11. "CF11,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 10. "CF10,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 9. "CF9,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 5. "CF5,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 4. "CF4,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 3. "CF3,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" group.long 0xE0++0x7 line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" group.long 0xF0++0x3 line.long 0x0 "TXEFC,Tx Event FIFO Configuration Register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address." rgroup.long 0xF4++0x3 line.long 0x0 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0x3 line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge Register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" tree.end tree "CAN_SUB_3_M_CAN_2" base ad:0x70834000 rgroup.long 0x0++0x7 line.long 0x0 "CREL,Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Substep of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "TS_MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "ENDN,Endian Register" hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value" group.long 0xC++0x23 line.long 0x0 "DBTP,Data Bit Timing and Prescaler Register" bitfld.long 0x0 23. "TDC,Transceiver Delay Compensation" "0: Transceiver Delay Compensation disabled,1: Transceiver Delay Compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re) Synchronization Jump Width" line.long 0x4 "TEST,Test register" bitfld.long 0x4 21. "SVAL,Started Valid" "0: Value of TXBNS not valid,1: Value of TXBNS valid" hexmask.long.byte 0x4 16.--20. 1. "TXBNS,Tx Buffer Number Started" newline bitfld.long 0x4 13. "PVAL,Prepared Valid" "0: Value of TXBNP not valid,1: Value of TXBNP valid" hexmask.long.byte 0x4 8.--12. 1. "TXBNP,Tx Buffer Number Prepared" newline bitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant (CAN Rx input = '0'),1: The CAN bus is recessive (CAN Rx input = '1')" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CAN Tx output is controlled by the..,1: Sample Point can be monitored at pin CAN Tx output,2: Dominant ('0') level at pin CAN Tx output,3: Recessive ('1') at pin CAN Tx output" newline bitfld.long 0x4 4. "LBCK,Loop Back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (refer to.." line.long 0x8 "RWD,RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration" line.long 0xC "CCCR,CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0xC 11. "WMM,Wide Message Marker" "0: 8-bit Message Marker used,1: 16-bit Message Marker used replacing 16-bit.." bitfld.long 0xC 10. "UTSU,Use Timestamping Unit" "0: Internal time stamping,1: External time stamping by TSU" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST_EN,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_CAN may be set in power down by stopping Host.." bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started" line.long 0x10 "NBTP,Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,(Re) Synchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Time segment before sample point" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,The time segment after the sample point" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Same as 00" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. "TOC,The Timeout Counter is decremented in multiples of CAN bit times (1 to 16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are.." rgroup.long 0x40++0x7 line.long 0x0 "ECR,Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "PSR,Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Received CAN FD Message" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set." newline bitfld.long 0x4 11. "RESI,ESI CAN FD Message with ESI flag" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state" bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state. It..,1: The M_CAN is in the Error_Passive state" bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing node is synchronizing on CAN..,1: Idle-node is neither receiver nor transmitter,2: Receiver-node is operating as receiver,3: Transmitter-node is operating as transmitter" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: consecutive recessive bits,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.." group.long 0x48++0x3 line.long 0x0 "TDCR,Transmitter Delay compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0xF line.long 0x0 "IR,Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected uncorrected (for example.." bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected (for example ECC)" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Event Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx Event FIDO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "IE,Interrupt Enable Register" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "ILS,Interrupt Line Select Register" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 16. "TSWL,TSWL: Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" line.long 0xC "ILE,Interrupt Line Enable Register" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line disabled,1: Interrupt line enabled" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line disabled,1: Interrupt line enabled" group.long 0x80++0xB line.long 0x0 "GFC,Global Filter Configuration Register" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,ANFE[1:0]: Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x8 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x3 line.long 0x0 "XIDAM,Extended ID and Mask Register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "HPMS,High Priority Message Status Register" bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "NDAT1,New Data 1 Register" bitfld.long 0x0 31. "ND31,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 30. "ND30,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 28. "ND28,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 26. "ND26,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 24. "ND24,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 22. "ND22,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 20. "ND20,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 18. "ND18,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 16. "ND16,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 14. "ND14,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 12. "ND12,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 10. "ND10,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 8. "ND8,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 6. "ND6,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 4. "ND4,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 2. "ND2,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 0. "ND0,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x4 "NDAT2,New Data 2 Register" bitfld.long 0x4 31. "ND63,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 30. "ND62,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 28. "ND60,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 26. "ND58,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 24. "ND56,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 22. "ND54,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 20. "ND52,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 18. "ND50,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 16. "ND48,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 14. "ND46,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 12. "ND44,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 10. "ND42,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 8. "ND40,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 6. "ND38,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 4. "ND36,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 2. "ND34,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 0. "ND32,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x8 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x0 25. "RF0L,RF0L" "0,1" bitfld.long 0x0 24. "F0F,F0F" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,F0PI" hexmask.long.byte 0x0 8.--13. 1. "F0GI,F0GI" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,F0FL" group.long 0xA8++0xB line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "RXF1C,Rx FIFO 1 Configuration Register" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,F1S[6:0]:" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is set" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" line.long 0x8 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Tx FIFO/Queue Size" newline hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x3 line.long 0x0 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x0 31. "AR31,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 30. "AR30,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 29. "AR29,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 28. "AR28,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 27. "AR27,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 26. "AR26,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 25. "AR25,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 24. "AR24,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 23. "AR23,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 22. "AR22,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 21. "AR21,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 20. "AR20,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 19. "AR19,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 18. "AR18,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 17. "AR17,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 16. "AR16,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 15. "AR15,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 14. "AR14,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 13. "AR13,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 12. "AR12,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 11. "AR11,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 10. "AR10,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 9. "AR9,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 8. "AR8,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 7. "AR7,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 6. "AR6,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 5. "AR5,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 4. "AR4,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 3. "AR3,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 2. "AR2,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 1. "AR1,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 0. "AR0,Add Request" "0: No transmission request added,1: Transmission requested added" line.long 0x4 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x4 31. "CR31,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 30. "CR30,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 29. "CR29,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 28. "CR28,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 27. "CR27,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 26. "CR26,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 24. "CR24,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 23. "CR23,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 22. "CR22,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 21. "CR21,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 20. "CR20,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 18. "CR18,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 17. "CR17,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 16. "CR16,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 15. "CR15,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 14. "CR14,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 12. "CR12,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 11. "CR11,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 10. "CR10,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 9. "CR9,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 8. "CR8,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 6. "CR6,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 5. "CR5,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 4. "CR4,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 3. "CR3,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 2. "CR2,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 0. "CR0,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" rgroup.long 0xD8++0x7 line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 29. "TO29,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 28. "TO28,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 27. "TO27,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 23. "TO23,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 22. "TO22,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 21. "TO21,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 17. "TO17,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 16. "TO16,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 15. "TO15,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 11. "TO11,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 10. "TO10,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 9. "TO9,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 5. "TO5,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 4. "TO4,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 3. "TO3,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 29. "CF29,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 28. "CF28,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 27. "CF27,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 23. "CF23,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 22. "CF22,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 21. "CF21,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 17. "CF17,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 16. "CF16,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 15. "CF15,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 11. "CF11,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 10. "CF10,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 9. "CF9,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 5. "CF5,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 4. "CF4,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 3. "CF3,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" group.long 0xE0++0x7 line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" group.long 0xF0++0x3 line.long 0x0 "TXEFC,Tx Event FIFO Configuration Register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address." rgroup.long 0xF4++0x3 line.long 0x0 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0x3 line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge Register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" tree.end tree "CAN_SUB_3_M_CAN_3" base ad:0x70838000 rgroup.long 0x0++0x7 line.long 0x0 "CREL,Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Substep of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "TS_MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "ENDN,Endian Register" hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value" group.long 0xC++0x23 line.long 0x0 "DBTP,Data Bit Timing and Prescaler Register" bitfld.long 0x0 23. "TDC,Transceiver Delay Compensation" "0: Transceiver Delay Compensation disabled,1: Transceiver Delay Compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re) Synchronization Jump Width" line.long 0x4 "TEST,Test register" bitfld.long 0x4 21. "SVAL,Started Valid" "0: Value of TXBNS not valid,1: Value of TXBNS valid" hexmask.long.byte 0x4 16.--20. 1. "TXBNS,Tx Buffer Number Started" newline bitfld.long 0x4 13. "PVAL,Prepared Valid" "0: Value of TXBNP not valid,1: Value of TXBNP valid" hexmask.long.byte 0x4 8.--12. 1. "TXBNP,Tx Buffer Number Prepared" newline bitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant (CAN Rx input = '0'),1: The CAN bus is recessive (CAN Rx input = '1')" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CAN Tx output is controlled by the..,1: Sample Point can be monitored at pin CAN Tx output,2: Dominant ('0') level at pin CAN Tx output,3: Recessive ('1') at pin CAN Tx output" newline bitfld.long 0x4 4. "LBCK,Loop Back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (refer to.." line.long 0x8 "RWD,RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration" line.long 0xC "CCCR,CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0xC 11. "WMM,Wide Message Marker" "0: 8-bit Message Marker used,1: 16-bit Message Marker used replacing 16-bit.." bitfld.long 0xC 10. "UTSU,Use Timestamping Unit" "0: Internal time stamping,1: External time stamping by TSU" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST_EN,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_CAN may be set in power down by stopping Host.." bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started" line.long 0x10 "NBTP,Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,(Re) Synchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Time segment before sample point" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,The time segment after the sample point" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Same as 00" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. "TOC,The Timeout Counter is decremented in multiples of CAN bit times (1 to 16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are.." rgroup.long 0x40++0x7 line.long 0x0 "ECR,Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "PSR,Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Received CAN FD Message" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set." newline bitfld.long 0x4 11. "RESI,ESI CAN FD Message with ESI flag" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state" bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state. It..,1: The M_CAN is in the Error_Passive state" bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing node is synchronizing on CAN..,1: Idle-node is neither receiver nor transmitter,2: Receiver-node is operating as receiver,3: Transmitter-node is operating as transmitter" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: consecutive recessive bits,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.." group.long 0x48++0x3 line.long 0x0 "TDCR,Transmitter Delay compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0xF line.long 0x0 "IR,Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected uncorrected (for example.." bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected (for example ECC)" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Event Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx Event FIDO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "IE,Interrupt Enable Register" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "ILS,Interrupt Line Select Register" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 16. "TSWL,TSWL: Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" line.long 0xC "ILE,Interrupt Line Enable Register" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line disabled,1: Interrupt line enabled" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line disabled,1: Interrupt line enabled" group.long 0x80++0xB line.long 0x0 "GFC,Global Filter Configuration Register" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,ANFE[1:0]: Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x8 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x3 line.long 0x0 "XIDAM,Extended ID and Mask Register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "HPMS,High Priority Message Status Register" bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "NDAT1,New Data 1 Register" bitfld.long 0x0 31. "ND31,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 30. "ND30,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 28. "ND28,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 26. "ND26,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 24. "ND24,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 22. "ND22,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 20. "ND20,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 18. "ND18,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 16. "ND16,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 14. "ND14,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 12. "ND12,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 10. "ND10,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 8. "ND8,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 6. "ND6,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 4. "ND4,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 2. "ND2,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 0. "ND0,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x4 "NDAT2,New Data 2 Register" bitfld.long 0x4 31. "ND63,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 30. "ND62,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 28. "ND60,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 26. "ND58,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 24. "ND56,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 22. "ND54,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 20. "ND52,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 18. "ND50,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 16. "ND48,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 14. "ND46,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 12. "ND44,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 10. "ND42,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 8. "ND40,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 6. "ND38,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 4. "ND36,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 2. "ND34,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 0. "ND32,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x8 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x0 25. "RF0L,RF0L" "0,1" bitfld.long 0x0 24. "F0F,F0F" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,F0PI" hexmask.long.byte 0x0 8.--13. 1. "F0GI,F0GI" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,F0FL" group.long 0xA8++0xB line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "RXF1C,Rx FIFO 1 Configuration Register" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,F1S[6:0]:" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is set" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" line.long 0x8 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Tx FIFO/Queue Size" newline hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x3 line.long 0x0 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x0 31. "AR31,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 30. "AR30,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 29. "AR29,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 28. "AR28,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 27. "AR27,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 26. "AR26,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 25. "AR25,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 24. "AR24,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 23. "AR23,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 22. "AR22,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 21. "AR21,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 20. "AR20,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 19. "AR19,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 18. "AR18,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 17. "AR17,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 16. "AR16,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 15. "AR15,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 14. "AR14,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 13. "AR13,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 12. "AR12,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 11. "AR11,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 10. "AR10,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 9. "AR9,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 8. "AR8,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 7. "AR7,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 6. "AR6,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 5. "AR5,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 4. "AR4,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 3. "AR3,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 2. "AR2,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 1. "AR1,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 0. "AR0,Add Request" "0: No transmission request added,1: Transmission requested added" line.long 0x4 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x4 31. "CR31,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 30. "CR30,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 29. "CR29,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 28. "CR28,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 27. "CR27,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 26. "CR26,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 24. "CR24,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 23. "CR23,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 22. "CR22,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 21. "CR21,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 20. "CR20,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 18. "CR18,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 17. "CR17,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 16. "CR16,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 15. "CR15,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 14. "CR14,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 12. "CR12,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 11. "CR11,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 10. "CR10,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 9. "CR9,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 8. "CR8,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 6. "CR6,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 5. "CR5,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 4. "CR4,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 3. "CR3,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 2. "CR2,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 0. "CR0,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" rgroup.long 0xD8++0x7 line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 29. "TO29,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 28. "TO28,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 27. "TO27,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 23. "TO23,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 22. "TO22,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 21. "TO21,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 17. "TO17,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 16. "TO16,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 15. "TO15,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 11. "TO11,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 10. "TO10,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 9. "TO9,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 5. "TO5,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 4. "TO4,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 3. "TO3,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 29. "CF29,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 28. "CF28,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 27. "CF27,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 23. "CF23,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 22. "CF22,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 21. "CF21,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 17. "CF17,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 16. "CF16,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 15. "CF15,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 11. "CF11,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 10. "CF10,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 9. "CF9,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 5. "CF5,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 4. "CF4,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 3. "CF3,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" group.long 0xE0++0x7 line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" group.long 0xF0++0x3 line.long 0x0 "TXEFC,Tx Event FIFO Configuration Register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address." rgroup.long 0xF4++0x3 line.long 0x0 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0x3 line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge Register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" tree.end tree "CAN_SUB_3_M_CAN_4" base ad:0x7083C000 rgroup.long 0x0++0x7 line.long 0x0 "CREL,Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Substep of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "TS_MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "ENDN,Endian Register" hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value" group.long 0xC++0x23 line.long 0x0 "DBTP,Data Bit Timing and Prescaler Register" bitfld.long 0x0 23. "TDC,Transceiver Delay Compensation" "0: Transceiver Delay Compensation disabled,1: Transceiver Delay Compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re) Synchronization Jump Width" line.long 0x4 "TEST,Test register" bitfld.long 0x4 21. "SVAL,Started Valid" "0: Value of TXBNS not valid,1: Value of TXBNS valid" hexmask.long.byte 0x4 16.--20. 1. "TXBNS,Tx Buffer Number Started" newline bitfld.long 0x4 13. "PVAL,Prepared Valid" "0: Value of TXBNP not valid,1: Value of TXBNP valid" hexmask.long.byte 0x4 8.--12. 1. "TXBNP,Tx Buffer Number Prepared" newline bitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant (CAN Rx input = '0'),1: The CAN bus is recessive (CAN Rx input = '1')" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CAN Tx output is controlled by the..,1: Sample Point can be monitored at pin CAN Tx output,2: Dominant ('0') level at pin CAN Tx output,3: Recessive ('1') at pin CAN Tx output" newline bitfld.long 0x4 4. "LBCK,Loop Back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (refer to.." line.long 0x8 "RWD,RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration" line.long 0xC "CCCR,CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0xC 11. "WMM,Wide Message Marker" "0: 8-bit Message Marker used,1: 16-bit Message Marker used replacing 16-bit.." bitfld.long 0xC 10. "UTSU,Use Timestamping Unit" "0: Internal time stamping,1: External time stamping by TSU" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST_EN,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_CAN may be set in power down by stopping Host.." bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started" line.long 0x10 "NBTP,Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,(Re) Synchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Time segment before sample point" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,The time segment after the sample point" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Same as 00" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. "TOC,The Timeout Counter is decremented in multiples of CAN bit times (1 to 16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are.." rgroup.long 0x40++0x7 line.long 0x0 "ECR,Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "PSR,Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Received CAN FD Message" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set." newline bitfld.long 0x4 11. "RESI,ESI CAN FD Message with ESI flag" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state" bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state. It..,1: The M_CAN is in the Error_Passive state" bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing node is synchronizing on CAN..,1: Idle-node is neither receiver nor transmitter,2: Receiver-node is operating as receiver,3: Transmitter-node is operating as transmitter" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: consecutive recessive bits,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.." group.long 0x48++0x3 line.long 0x0 "TDCR,Transmitter Delay compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0xF line.long 0x0 "IR,Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected uncorrected (for example.." bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected (for example ECC)" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Event Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx Event FIDO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "IE,Interrupt Enable Register" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "ILS,Interrupt Line Select Register" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 16. "TSWL,TSWL: Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" line.long 0xC "ILE,Interrupt Line Enable Register" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line disabled,1: Interrupt line enabled" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line disabled,1: Interrupt line enabled" group.long 0x80++0xB line.long 0x0 "GFC,Global Filter Configuration Register" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,ANFE[1:0]: Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x8 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x3 line.long 0x0 "XIDAM,Extended ID and Mask Register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "HPMS,High Priority Message Status Register" bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "NDAT1,New Data 1 Register" bitfld.long 0x0 31. "ND31,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 30. "ND30,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 28. "ND28,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 26. "ND26,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 24. "ND24,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 22. "ND22,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 20. "ND20,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 18. "ND18,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 16. "ND16,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 14. "ND14,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 12. "ND12,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 10. "ND10,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 8. "ND8,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 6. "ND6,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 4. "ND4,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 2. "ND2,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 0. "ND0,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x4 "NDAT2,New Data 2 Register" bitfld.long 0x4 31. "ND63,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 30. "ND62,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 28. "ND60,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 26. "ND58,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 24. "ND56,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 22. "ND54,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 20. "ND52,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 18. "ND50,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 16. "ND48,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 14. "ND46,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 12. "ND44,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 10. "ND42,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 8. "ND40,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 6. "ND38,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 4. "ND36,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 2. "ND34,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 0. "ND32,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x8 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x0 25. "RF0L,RF0L" "0,1" bitfld.long 0x0 24. "F0F,F0F" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,F0PI" hexmask.long.byte 0x0 8.--13. 1. "F0GI,F0GI" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,F0FL" group.long 0xA8++0xB line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "RXF1C,Rx FIFO 1 Configuration Register" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,F1S[6:0]:" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is set" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" line.long 0x8 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Tx FIFO/Queue Size" newline hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x3 line.long 0x0 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x0 31. "AR31,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 30. "AR30,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 29. "AR29,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 28. "AR28,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 27. "AR27,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 26. "AR26,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 25. "AR25,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 24. "AR24,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 23. "AR23,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 22. "AR22,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 21. "AR21,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 20. "AR20,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 19. "AR19,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 18. "AR18,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 17. "AR17,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 16. "AR16,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 15. "AR15,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 14. "AR14,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 13. "AR13,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 12. "AR12,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 11. "AR11,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 10. "AR10,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 9. "AR9,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 8. "AR8,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 7. "AR7,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 6. "AR6,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 5. "AR5,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 4. "AR4,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 3. "AR3,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 2. "AR2,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 1. "AR1,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 0. "AR0,Add Request" "0: No transmission request added,1: Transmission requested added" line.long 0x4 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x4 31. "CR31,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 30. "CR30,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 29. "CR29,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 28. "CR28,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 27. "CR27,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 26. "CR26,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 24. "CR24,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 23. "CR23,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 22. "CR22,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 21. "CR21,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 20. "CR20,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 18. "CR18,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 17. "CR17,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 16. "CR16,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 15. "CR15,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 14. "CR14,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 12. "CR12,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 11. "CR11,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 10. "CR10,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 9. "CR9,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 8. "CR8,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 6. "CR6,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 5. "CR5,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 4. "CR4,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 3. "CR3,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 2. "CR2,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 0. "CR0,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" rgroup.long 0xD8++0x7 line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 29. "TO29,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 28. "TO28,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 27. "TO27,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 23. "TO23,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 22. "TO22,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 21. "TO21,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 17. "TO17,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 16. "TO16,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 15. "TO15,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 11. "TO11,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 10. "TO10,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 9. "TO9,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 5. "TO5,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 4. "TO4,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 3. "TO3,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 29. "CF29,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 28. "CF28,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 27. "CF27,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 23. "CF23,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 22. "CF22,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 21. "CF21,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 17. "CF17,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 16. "CF16,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 15. "CF15,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 11. "CF11,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 10. "CF10,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 9. "CF9,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 5. "CF5,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 4. "CF4,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 3. "CF3,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" group.long 0xE0++0x7 line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" group.long 0xF0++0x3 line.long 0x0 "TXEFC,Tx Event FIFO Configuration Register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address." rgroup.long 0xF4++0x3 line.long 0x0 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0x3 line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge Register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" tree.end tree "CAN_SUB_3_TSU_1" base ad:0x70830000 rgroup.long 0x160++0x7 line.long 0x0 "CREL,Core Release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "TSCFG,Timestamp Configuration register" hexmask.long.byte 0x4 8.--15. 1. "TBPRE,TBPRE" bitfld.long 0x4 2. "SCP,Select Capturing Position" "0: Capture Timestamp at EOF,1: Capture Timestamp at SOF" newline bitfld.long 0x4 1. "TBCS,Timebase Counter Select" "0: Timestamp value captured from internal timebase..,1: : Timestamp value captured from input.." bitfld.long 0x4 0. "TSUE,Timestamp Unit Enable 0" "0: TSU disabled,1: TSU enabled" group.long 0x168++0x3 line.long 0x0 "TSS1,Timestamp Status 1 register" bitfld.long 0x0 31. "TSL15,Timestamp Lost" "0,1" bitfld.long 0x0 30. "TSL14,Timestamp Lost" "0,1" newline bitfld.long 0x0 29. "TSL13,Timestamp Lost" "0,1" bitfld.long 0x0 28. "TSL12,Timestamp Lost" "0,1" newline bitfld.long 0x0 27. "TSL11,Timestamp Lost" "0,1" bitfld.long 0x0 26. "TSL10,Timestamp Lost" "0,1" newline bitfld.long 0x0 25. "TSL9,Timestamp Lost" "0,1" bitfld.long 0x0 24. "TSL8,Timestamp Lost" "0,1" newline bitfld.long 0x0 23. "TSL7,Timestamp Lost" "0,1" bitfld.long 0x0 22. "TSL6,Timestamp Lost" "0,1" newline bitfld.long 0x0 21. "TSL5,Timestamp Lost" "0,1" bitfld.long 0x0 20. "TSL4,Timestamp Lost" "0,1" newline bitfld.long 0x0 19. "TSL3,Timestamp Lost" "0,1" bitfld.long 0x0 18. "TSL2,Timestamp Lost" "0,1" newline bitfld.long 0x0 17. "TSL1,Timestamp Lost" "0,1" bitfld.long 0x0 16. "TSL0,Timestamp Lost" "0,1" newline bitfld.long 0x0 15. "TSN15,Timestamp New" "0,1" bitfld.long 0x0 14. "TSN14,Timestamp New" "0,1" newline bitfld.long 0x0 13. "TSN13,Timestamp New" "0,1" bitfld.long 0x0 12. "TSN12,Timestamp New" "0,1" newline bitfld.long 0x0 11. "TSN11,Timestamp New" "0,1" bitfld.long 0x0 10. "TSN10,Timestamp New" "0,1" newline bitfld.long 0x0 9. "TSN9,Timestamp New" "0,1" bitfld.long 0x0 8. "TSN8,Timestamp New" "0,1" newline bitfld.long 0x0 7. "TSN7,Timestamp New" "0,1" bitfld.long 0x0 6. "TSN6,Timestamp New" "0,1" newline bitfld.long 0x0 5. "TSN5,Timestamp New" "0,1" bitfld.long 0x0 4. "TSN4,Timestamp New" "0,1" newline bitfld.long 0x0 3. "TSN3,Timestamp New" "0,1" bitfld.long 0x0 2. "TSN2,Timestamp New" "0,1" newline bitfld.long 0x0 1. "TSN1,Timestamp New" "0,1" bitfld.long 0x0 0. "TSN0,Timestamp New" "0,1" rgroup.long 0x16C++0x43 line.long 0x0 "TSS2,Timestamp Status 2 register" bitfld.long 0x0 14.--15. "ITBG,Internal Timebase and SOF select Generic" "0: no SOF option no internal timebase,1: no SOF option internal timebase (default),2: SOF option no internal timebase,3: SOF option internal timebase" bitfld.long 0x0 12.--13. "NTSG,Number of Timestamps Generic" "0: 4 timestamp registers TS0-TS3,1: 8 timestamp registers TS0-TS7 (default),2: 16 timestamp registers TS0-TS15,3: not a valid value" newline hexmask.long.byte 0x0 0.--3. 1. "TSP,Timestamp Pointer" line.long 0x4 "TS0,Timestamp 0 register" hexmask.long 0x4 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x8 "TS1,Timestamp 1 register" hexmask.long 0x8 0.--31. 1. "TS,Timestamp Word TSn" line.long 0xC "TS2,Timestamp 2 register" hexmask.long 0xC 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x10 "TS3,Timestamp 3 register" hexmask.long 0x10 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x14 "TS4,Timestamp 4 register" hexmask.long 0x14 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x18 "TS5,Timestamp 5 register" hexmask.long 0x18 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x1C "TS6,Timestamp 6 register" hexmask.long 0x1C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x20 "TS7,Timestamp 7 register" hexmask.long 0x20 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x24 "TS8,Timestamp 8 register" hexmask.long 0x24 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x28 "TS9,Timestamp 9 register" hexmask.long 0x28 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x2C "TS10,Timestamp 10 register" hexmask.long 0x2C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x30 "TS11,Timestamp 11 register" hexmask.long 0x30 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x34 "TS12,Timestamp 12 register" hexmask.long 0x34 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x38 "TS13,Timestamp 13 register" hexmask.long 0x38 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x3C "TS14,Timestamp 14 register" hexmask.long 0x3C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x40 "TS15,Timestamp 15 register" hexmask.long 0x40 0.--31. 1. "TS,Timestamp Word TSn" group.long 0x1B0++0x3 line.long 0x0 "ATB,Actual Timebase" hexmask.long 0x0 0.--31. 1. "TB,Timebase for timestamp generation" tree.end tree "CAN_SUB_3_TSU_2" base ad:0x70834000 rgroup.long 0x160++0x7 line.long 0x0 "CREL,Core Release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "TSCFG,Timestamp Configuration register" hexmask.long.byte 0x4 8.--15. 1. "TBPRE,TBPRE" bitfld.long 0x4 2. "SCP,Select Capturing Position" "0: Capture Timestamp at EOF,1: Capture Timestamp at SOF" newline bitfld.long 0x4 1. "TBCS,Timebase Counter Select" "0: Timestamp value captured from internal timebase..,1: : Timestamp value captured from input.." bitfld.long 0x4 0. "TSUE,Timestamp Unit Enable 0" "0: TSU disabled,1: TSU enabled" group.long 0x168++0x3 line.long 0x0 "TSS1,Timestamp Status 1 register" bitfld.long 0x0 31. "TSL15,Timestamp Lost" "0,1" bitfld.long 0x0 30. "TSL14,Timestamp Lost" "0,1" newline bitfld.long 0x0 29. "TSL13,Timestamp Lost" "0,1" bitfld.long 0x0 28. "TSL12,Timestamp Lost" "0,1" newline bitfld.long 0x0 27. "TSL11,Timestamp Lost" "0,1" bitfld.long 0x0 26. "TSL10,Timestamp Lost" "0,1" newline bitfld.long 0x0 25. "TSL9,Timestamp Lost" "0,1" bitfld.long 0x0 24. "TSL8,Timestamp Lost" "0,1" newline bitfld.long 0x0 23. "TSL7,Timestamp Lost" "0,1" bitfld.long 0x0 22. "TSL6,Timestamp Lost" "0,1" newline bitfld.long 0x0 21. "TSL5,Timestamp Lost" "0,1" bitfld.long 0x0 20. "TSL4,Timestamp Lost" "0,1" newline bitfld.long 0x0 19. "TSL3,Timestamp Lost" "0,1" bitfld.long 0x0 18. "TSL2,Timestamp Lost" "0,1" newline bitfld.long 0x0 17. "TSL1,Timestamp Lost" "0,1" bitfld.long 0x0 16. "TSL0,Timestamp Lost" "0,1" newline bitfld.long 0x0 15. "TSN15,Timestamp New" "0,1" bitfld.long 0x0 14. "TSN14,Timestamp New" "0,1" newline bitfld.long 0x0 13. "TSN13,Timestamp New" "0,1" bitfld.long 0x0 12. "TSN12,Timestamp New" "0,1" newline bitfld.long 0x0 11. "TSN11,Timestamp New" "0,1" bitfld.long 0x0 10. "TSN10,Timestamp New" "0,1" newline bitfld.long 0x0 9. "TSN9,Timestamp New" "0,1" bitfld.long 0x0 8. "TSN8,Timestamp New" "0,1" newline bitfld.long 0x0 7. "TSN7,Timestamp New" "0,1" bitfld.long 0x0 6. "TSN6,Timestamp New" "0,1" newline bitfld.long 0x0 5. "TSN5,Timestamp New" "0,1" bitfld.long 0x0 4. "TSN4,Timestamp New" "0,1" newline bitfld.long 0x0 3. "TSN3,Timestamp New" "0,1" bitfld.long 0x0 2. "TSN2,Timestamp New" "0,1" newline bitfld.long 0x0 1. "TSN1,Timestamp New" "0,1" bitfld.long 0x0 0. "TSN0,Timestamp New" "0,1" rgroup.long 0x16C++0x43 line.long 0x0 "TSS2,Timestamp Status 2 register" bitfld.long 0x0 14.--15. "ITBG,Internal Timebase and SOF select Generic" "0: no SOF option no internal timebase,1: no SOF option internal timebase (default),2: SOF option no internal timebase,3: SOF option internal timebase" bitfld.long 0x0 12.--13. "NTSG,Number of Timestamps Generic" "0: 4 timestamp registers TS0-TS3,1: 8 timestamp registers TS0-TS7 (default),2: 16 timestamp registers TS0-TS15,3: not a valid value" newline hexmask.long.byte 0x0 0.--3. 1. "TSP,Timestamp Pointer" line.long 0x4 "TS0,Timestamp 0 register" hexmask.long 0x4 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x8 "TS1,Timestamp 1 register" hexmask.long 0x8 0.--31. 1. "TS,Timestamp Word TSn" line.long 0xC "TS2,Timestamp 2 register" hexmask.long 0xC 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x10 "TS3,Timestamp 3 register" hexmask.long 0x10 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x14 "TS4,Timestamp 4 register" hexmask.long 0x14 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x18 "TS5,Timestamp 5 register" hexmask.long 0x18 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x1C "TS6,Timestamp 6 register" hexmask.long 0x1C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x20 "TS7,Timestamp 7 register" hexmask.long 0x20 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x24 "TS8,Timestamp 8 register" hexmask.long 0x24 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x28 "TS9,Timestamp 9 register" hexmask.long 0x28 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x2C "TS10,Timestamp 10 register" hexmask.long 0x2C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x30 "TS11,Timestamp 11 register" hexmask.long 0x30 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x34 "TS12,Timestamp 12 register" hexmask.long 0x34 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x38 "TS13,Timestamp 13 register" hexmask.long 0x38 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x3C "TS14,Timestamp 14 register" hexmask.long 0x3C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x40 "TS15,Timestamp 15 register" hexmask.long 0x40 0.--31. 1. "TS,Timestamp Word TSn" group.long 0x1B0++0x3 line.long 0x0 "ATB,Actual Timebase" hexmask.long 0x0 0.--31. 1. "TB,Timebase for timestamp generation" tree.end tree "CAN_SUB_3_TSU_3" base ad:0x70838000 rgroup.long 0x160++0x7 line.long 0x0 "CREL,Core Release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "TSCFG,Timestamp Configuration register" hexmask.long.byte 0x4 8.--15. 1. "TBPRE,TBPRE" bitfld.long 0x4 2. "SCP,Select Capturing Position" "0: Capture Timestamp at EOF,1: Capture Timestamp at SOF" newline bitfld.long 0x4 1. "TBCS,Timebase Counter Select" "0: Timestamp value captured from internal timebase..,1: : Timestamp value captured from input.." bitfld.long 0x4 0. "TSUE,Timestamp Unit Enable 0" "0: TSU disabled,1: TSU enabled" group.long 0x168++0x3 line.long 0x0 "TSS1,Timestamp Status 1 register" bitfld.long 0x0 31. "TSL15,Timestamp Lost" "0,1" bitfld.long 0x0 30. "TSL14,Timestamp Lost" "0,1" newline bitfld.long 0x0 29. "TSL13,Timestamp Lost" "0,1" bitfld.long 0x0 28. "TSL12,Timestamp Lost" "0,1" newline bitfld.long 0x0 27. "TSL11,Timestamp Lost" "0,1" bitfld.long 0x0 26. "TSL10,Timestamp Lost" "0,1" newline bitfld.long 0x0 25. "TSL9,Timestamp Lost" "0,1" bitfld.long 0x0 24. "TSL8,Timestamp Lost" "0,1" newline bitfld.long 0x0 23. "TSL7,Timestamp Lost" "0,1" bitfld.long 0x0 22. "TSL6,Timestamp Lost" "0,1" newline bitfld.long 0x0 21. "TSL5,Timestamp Lost" "0,1" bitfld.long 0x0 20. "TSL4,Timestamp Lost" "0,1" newline bitfld.long 0x0 19. "TSL3,Timestamp Lost" "0,1" bitfld.long 0x0 18. "TSL2,Timestamp Lost" "0,1" newline bitfld.long 0x0 17. "TSL1,Timestamp Lost" "0,1" bitfld.long 0x0 16. "TSL0,Timestamp Lost" "0,1" newline bitfld.long 0x0 15. "TSN15,Timestamp New" "0,1" bitfld.long 0x0 14. "TSN14,Timestamp New" "0,1" newline bitfld.long 0x0 13. "TSN13,Timestamp New" "0,1" bitfld.long 0x0 12. "TSN12,Timestamp New" "0,1" newline bitfld.long 0x0 11. "TSN11,Timestamp New" "0,1" bitfld.long 0x0 10. "TSN10,Timestamp New" "0,1" newline bitfld.long 0x0 9. "TSN9,Timestamp New" "0,1" bitfld.long 0x0 8. "TSN8,Timestamp New" "0,1" newline bitfld.long 0x0 7. "TSN7,Timestamp New" "0,1" bitfld.long 0x0 6. "TSN6,Timestamp New" "0,1" newline bitfld.long 0x0 5. "TSN5,Timestamp New" "0,1" bitfld.long 0x0 4. "TSN4,Timestamp New" "0,1" newline bitfld.long 0x0 3. "TSN3,Timestamp New" "0,1" bitfld.long 0x0 2. "TSN2,Timestamp New" "0,1" newline bitfld.long 0x0 1. "TSN1,Timestamp New" "0,1" bitfld.long 0x0 0. "TSN0,Timestamp New" "0,1" rgroup.long 0x16C++0x43 line.long 0x0 "TSS2,Timestamp Status 2 register" bitfld.long 0x0 14.--15. "ITBG,Internal Timebase and SOF select Generic" "0: no SOF option no internal timebase,1: no SOF option internal timebase (default),2: SOF option no internal timebase,3: SOF option internal timebase" bitfld.long 0x0 12.--13. "NTSG,Number of Timestamps Generic" "0: 4 timestamp registers TS0-TS3,1: 8 timestamp registers TS0-TS7 (default),2: 16 timestamp registers TS0-TS15,3: not a valid value" newline hexmask.long.byte 0x0 0.--3. 1. "TSP,Timestamp Pointer" line.long 0x4 "TS0,Timestamp 0 register" hexmask.long 0x4 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x8 "TS1,Timestamp 1 register" hexmask.long 0x8 0.--31. 1. "TS,Timestamp Word TSn" line.long 0xC "TS2,Timestamp 2 register" hexmask.long 0xC 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x10 "TS3,Timestamp 3 register" hexmask.long 0x10 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x14 "TS4,Timestamp 4 register" hexmask.long 0x14 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x18 "TS5,Timestamp 5 register" hexmask.long 0x18 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x1C "TS6,Timestamp 6 register" hexmask.long 0x1C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x20 "TS7,Timestamp 7 register" hexmask.long 0x20 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x24 "TS8,Timestamp 8 register" hexmask.long 0x24 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x28 "TS9,Timestamp 9 register" hexmask.long 0x28 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x2C "TS10,Timestamp 10 register" hexmask.long 0x2C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x30 "TS11,Timestamp 11 register" hexmask.long 0x30 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x34 "TS12,Timestamp 12 register" hexmask.long 0x34 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x38 "TS13,Timestamp 13 register" hexmask.long 0x38 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x3C "TS14,Timestamp 14 register" hexmask.long 0x3C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x40 "TS15,Timestamp 15 register" hexmask.long 0x40 0.--31. 1. "TS,Timestamp Word TSn" group.long 0x1B0++0x3 line.long 0x0 "ATB,Actual Timebase" hexmask.long 0x0 0.--31. 1. "TB,Timebase for timestamp generation" tree.end tree "CAN_SUB_3_TSU_4" base ad:0x7083C000 rgroup.long 0x160++0x7 line.long 0x0 "CREL,Core Release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "TSCFG,Timestamp Configuration register" hexmask.long.byte 0x4 8.--15. 1. "TBPRE,TBPRE" bitfld.long 0x4 2. "SCP,Select Capturing Position" "0: Capture Timestamp at EOF,1: Capture Timestamp at SOF" newline bitfld.long 0x4 1. "TBCS,Timebase Counter Select" "0: Timestamp value captured from internal timebase..,1: : Timestamp value captured from input.." bitfld.long 0x4 0. "TSUE,Timestamp Unit Enable 0" "0: TSU disabled,1: TSU enabled" group.long 0x168++0x3 line.long 0x0 "TSS1,Timestamp Status 1 register" bitfld.long 0x0 31. "TSL15,Timestamp Lost" "0,1" bitfld.long 0x0 30. "TSL14,Timestamp Lost" "0,1" newline bitfld.long 0x0 29. "TSL13,Timestamp Lost" "0,1" bitfld.long 0x0 28. "TSL12,Timestamp Lost" "0,1" newline bitfld.long 0x0 27. "TSL11,Timestamp Lost" "0,1" bitfld.long 0x0 26. "TSL10,Timestamp Lost" "0,1" newline bitfld.long 0x0 25. "TSL9,Timestamp Lost" "0,1" bitfld.long 0x0 24. "TSL8,Timestamp Lost" "0,1" newline bitfld.long 0x0 23. "TSL7,Timestamp Lost" "0,1" bitfld.long 0x0 22. "TSL6,Timestamp Lost" "0,1" newline bitfld.long 0x0 21. "TSL5,Timestamp Lost" "0,1" bitfld.long 0x0 20. "TSL4,Timestamp Lost" "0,1" newline bitfld.long 0x0 19. "TSL3,Timestamp Lost" "0,1" bitfld.long 0x0 18. "TSL2,Timestamp Lost" "0,1" newline bitfld.long 0x0 17. "TSL1,Timestamp Lost" "0,1" bitfld.long 0x0 16. "TSL0,Timestamp Lost" "0,1" newline bitfld.long 0x0 15. "TSN15,Timestamp New" "0,1" bitfld.long 0x0 14. "TSN14,Timestamp New" "0,1" newline bitfld.long 0x0 13. "TSN13,Timestamp New" "0,1" bitfld.long 0x0 12. "TSN12,Timestamp New" "0,1" newline bitfld.long 0x0 11. "TSN11,Timestamp New" "0,1" bitfld.long 0x0 10. "TSN10,Timestamp New" "0,1" newline bitfld.long 0x0 9. "TSN9,Timestamp New" "0,1" bitfld.long 0x0 8. "TSN8,Timestamp New" "0,1" newline bitfld.long 0x0 7. "TSN7,Timestamp New" "0,1" bitfld.long 0x0 6. "TSN6,Timestamp New" "0,1" newline bitfld.long 0x0 5. "TSN5,Timestamp New" "0,1" bitfld.long 0x0 4. "TSN4,Timestamp New" "0,1" newline bitfld.long 0x0 3. "TSN3,Timestamp New" "0,1" bitfld.long 0x0 2. "TSN2,Timestamp New" "0,1" newline bitfld.long 0x0 1. "TSN1,Timestamp New" "0,1" bitfld.long 0x0 0. "TSN0,Timestamp New" "0,1" rgroup.long 0x16C++0x43 line.long 0x0 "TSS2,Timestamp Status 2 register" bitfld.long 0x0 14.--15. "ITBG,Internal Timebase and SOF select Generic" "0: no SOF option no internal timebase,1: no SOF option internal timebase (default),2: SOF option no internal timebase,3: SOF option internal timebase" bitfld.long 0x0 12.--13. "NTSG,Number of Timestamps Generic" "0: 4 timestamp registers TS0-TS3,1: 8 timestamp registers TS0-TS7 (default),2: 16 timestamp registers TS0-TS15,3: not a valid value" newline hexmask.long.byte 0x0 0.--3. 1. "TSP,Timestamp Pointer" line.long 0x4 "TS0,Timestamp 0 register" hexmask.long 0x4 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x8 "TS1,Timestamp 1 register" hexmask.long 0x8 0.--31. 1. "TS,Timestamp Word TSn" line.long 0xC "TS2,Timestamp 2 register" hexmask.long 0xC 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x10 "TS3,Timestamp 3 register" hexmask.long 0x10 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x14 "TS4,Timestamp 4 register" hexmask.long 0x14 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x18 "TS5,Timestamp 5 register" hexmask.long 0x18 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x1C "TS6,Timestamp 6 register" hexmask.long 0x1C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x20 "TS7,Timestamp 7 register" hexmask.long 0x20 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x24 "TS8,Timestamp 8 register" hexmask.long 0x24 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x28 "TS9,Timestamp 9 register" hexmask.long 0x28 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x2C "TS10,Timestamp 10 register" hexmask.long 0x2C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x30 "TS11,Timestamp 11 register" hexmask.long 0x30 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x34 "TS12,Timestamp 12 register" hexmask.long 0x34 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x38 "TS13,Timestamp 13 register" hexmask.long 0x38 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x3C "TS14,Timestamp 14 register" hexmask.long 0x3C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x40 "TS15,Timestamp 15 register" hexmask.long 0x40 0.--31. 1. "TS,Timestamp Word TSn" group.long 0x1B0++0x3 line.long 0x0 "ATB,Actual Timebase" hexmask.long 0x0 0.--31. 1. "TB,Timebase for timestamp generation" tree.end tree.end tree "CAN_SUB_4" tree "CAN_SUB_4_DMU_1" base ad:0x7025C000 rgroup.long 0x3C0++0x3 line.long 0x0 "DMUCR,DMU Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" group.long 0x3C4++0x13 line.long 0x0 "DMUI,DMU Internals register" bitfld.long 0x0 31. "TXE,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 30. "RX1,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 29. "RX0,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 28. "TX,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 24.--26. "EHS,Element Handler State" "0: wait for bit M_CAN:CCCR.CCE getting zero,1: wait for Start Address,2: wait for Trigger Address,3: wait for transfer of Element word,4: acknowledge to M_CAN,5: exception recovery,?,?" bitfld.long 0x0 23. "DTXE,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 22. "DTX1,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 21. "DTX0,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 20. "DTX,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 16.--18. "DEHS,Detect Element Handler State" "?,?,?,?,?,?,?,7: unused state" newline bitfld.long 0x0 15. "ENA,DMU is enabled" "0: DMU is disabled,1: DMU is enabled and can process DMA data" hexmask.long.byte 0x0 8.--12. 1. "TFQPIP,TX FIFO/Queue Put Index Previous" newline bitfld.long 0x0 3. "TXER,TX Event Service Request line of DMU" "0: No TX Event DMA service requested,1: TX Event DMA Service requested" bitfld.long 0x0 2. "RX1R,RX1 Service Request line of DMU" "0: No RX1 DMA service requested,1: RX1 DMA Service requested" newline bitfld.long 0x0 1. "RX0R,RX0 Service Request line of DMU" "0: No RX0 DMA service requested,1: RX0 DMA Service requested" bitfld.long 0x0 0. "TXR,TX Service Request line of DMU" "0: No TX DMA service requested,1: TX DMA Service requested" line.long 0x4 "DMUQC,DMU Queuing Counter register" hexmask.long.byte 0x4 24.--31. 1. "TXEEDC,TX Event Element Dequeuing Counter" hexmask.long.byte 0x4 16.--23. 1. "RX1EDC,RX1 Element Dequeuing Counter" newline hexmask.long.byte 0x4 8.--15. 1. "RX0EDC,RX0 Element Dequeuing Counter" hexmask.long.byte 0x4 0.--7. 1. "TXEEC,TX Element Enqueuing Counter" line.long 0x8 "DMUIR,DMU Interrupt Register" bitfld.long 0x8 30. "IAC,Illegal Access while in Configuration mode" "0: No Illegal Access while CCE mode,1: Illegal Access while CCE mode" bitfld.long 0x8 29. "DT,Debug Trigger" "0: Debug point not reached,1: Debug point reached" newline bitfld.long 0x8 28. "TXEED,TX Event Element Dequeued" "0: No TX Event Element dequeued,1: TX Event Element successfully dequeued" bitfld.long 0x8 27. "TXEEIW,TX Event Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU TX Event Element.." newline bitfld.long 0x8 26. "TXEEIAS,TX Event Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 25. "TXEEID,TX Event Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 24. "TXEENSA,TX Event Element Not Start Address" "0: No illegal read access,1: Read from TX Event Element begins without using.." bitfld.long 0x8 21. "RX1EIO,RX1 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 20. "RX1ED,RX1 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 19. "RX1EIW,RX1 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 18. "RX1EIAS,RX1 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 17. "RX1EID,RX1 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 16. "RX1ENSA,RX1 Element Not Start Address" "0: No illegal read access,1: Read from RX1 Element begins without using start.." bitfld.long 0x8 15. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Uncorrected bit error detected" newline bitfld.long 0x8 14. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected" bitfld.long 0x8 13. "RX0EIO,RX0 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 12. "RX0ED,RX0 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 11. "RX0EIW,RX0 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 10. "RX0EIAS,RX0 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 9. "RX0EID,RX0 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 8. "RX0ENSA,RX0 Element Not Start Address" "0: No illegal read access,1: Read from RX0 Element begins without using start.." bitfld.long 0x8 6. "TXEE,TX Element Enqueued" "0: No Tx message enqueued,1: Tx message successfully enqueued" newline bitfld.long 0x8 5. "TXEIR,TX Element Illegal Read" "0: No read access,1: Illegal read access to DMU TX Element section.." bitfld.long 0x8 4. "TXEWATA,TX Element Write After Trigger Address" "0: No write after Trigger Address,1: Enqueue a message" newline bitfld.long 0x8 3. "TXEIDLC,TX Element Illegal DLC" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." bitfld.long 0x8 2. "TXEIAS,TX Element Illegal Access Sequence" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." newline bitfld.long 0x8 1. "TXEIE,TX Element Illegal Enqueuing" "0: No illegal enqueuing,1: Start of enqueuing without request detected.." bitfld.long 0x8 0. "TXENSA,TX Element Not Start Address" "0: No illegal write access,1: Write to TX Element begins without using start.." line.long 0xC "DMUIE,DMU Interrupt Enable register" bitfld.long 0xC 30. "IACE,Illegal Access while in Configuration mode Enable" "0: Flag DMUIR.IAC does not activate the interrupt..,1: If DMUIR.IAC = 1 the interrupt line dmu_int will.." bitfld.long 0xC 29. "DTE,Debug Trigger Enable" "0: Flag DMUIR.DT does not activate the interrupt..,1: If DMUIR.DT = 1 the interrupt line dmu_int will.." newline bitfld.long 0xC 28. "TXEEDE,TX Event Element Dequeued" "0: Flag DMUIR.TXEED does not activate the interrupt..,1: If DMUIR.TXEED = 1 the interrupt line dmu_int.." bitfld.long 0xC 27. "TXEEIWE,TX Event Element Illegal Write" "0: Flag DMUIR.TXEEIW does not activate the..,1: If DMUIR.TXEEIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 26. "TXEEIASE,TX Event Element Illegal Access Sequence" "0: Flag DMUIR.TXEEIAS does not activate the..,1: If DMUIR.TXEEIAS = 1 the interrupt line dmu_int.." bitfld.long 0xC 25. "TXEEIDE,TX Event Element Illegal Dequeuing" "0: Flag DMUIR.TXEEID does not activate the..,1: If DMUIR.TXEEID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 24. "TXEENSAE,TX Event Element Not Start Address" "0: Flag TXEENSA.TXEENSA does not activate the..,1: If TXEENSA.TXEENSA = 1 the interrupt line.." bitfld.long 0xC 21. "RX1EIOE,RX1 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX1EIO does not activate the..,1: If TXEENSA.RX1EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 20. "RX1EDE,RX1 Element Dequeued Enable" "0: Flag TXEENSA.RX1ED does not activate the..,1: If TXEENSA.RX1ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 19. "RX1EIWE,RX1 Element Illegal Write Enable" "0: Flag TXEENSA.RX1EIW does not activate the..,1: If TXEENSA.RX1EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 18. "RX1EIASE,RX1 Element Illegal Access Sequence Enable" "0: Flag TXEENSA.RX1EIAS does not activate the..,1: If TXEENSA.RX1EIAS = 1 the interrupt line.." bitfld.long 0xC 17. "RX1EIDE,RX1 Element Illegal Dequeuing Enable" "0: Flag TXEENSA.RX1EID does not activate the..,1: If TXEENSA.RX1EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 16. "RX1ENSAE,RX1 Element Not Start Address Enable" "0: Flag TXEENSA.RX1ENSA does not activate the..,1: If TXEENSA.RX1ENSA = 1 the interrupt line.." bitfld.long 0xC 15. "BEUE,Bit Error Uncorrected Enable" "0: Flag TXEENSA.BEU does not activate the interrupt..,1: If TXEENSA.BEU = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 14. "BECE,Bit Error Corrected Enable" "0: Flag TXEENSA.BEC does not activate the interrupt..,1: If TXEENSA.BEC = 1 the interrupt line dmu_int.." bitfld.long 0xC 13. "RX0EIOE,RX0 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX0EIO does not activate the..,1: If TXEENSA.RX0EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 12. "RX0EDE,RX0 Element Dequeued Enabled" "0: Flag TXEENSA.RX0ED does not activate the..,1: If TXEENSA.RX0ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 11. "RX0EIWE,RX0 Element Illegal Write Enabled" "0: Flag TXEENSA.RX0EIW does not activate the..,1: If TXEENSA.RX0EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 10. "RX0EIASE,RX0 Element Illegal Access Sequence Enabled" "0: Flag TXEENSA.RX0EIAS does not activate the..,1: If TXEENSA.RX0EIAS = 1 the interrupt line.." bitfld.long 0xC 9. "RX0EIDE,RX0 Element Illegal Dequeuing Enabled" "0: Flag TXEENSA.RX0EID does not activate the..,1: If TXEENSA.RX0EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 8. "RX0ENSAE,RX0 Element Not Start Address Enabled" "0: Flag TXEENSA.RX0ENSA does not activate the..,1: If TXEENSA.RX0ENSA = 1 the interrupt line.." bitfld.long 0xC 6. "TXEEE,TX Element Enqueued Enable" "0: Flag TXEENSA.TXEE does not activate the..,1: If TXEENSA.TXEE = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 5. "TXEIRE,TX Element Illegal Read Enable" "0: Flag TXEENSA.TXEIR does not activate the..,1: If TXEENSA.TXEIR = 1 the interrupt line dmu_int.." bitfld.long 0xC 4. "TXEWATAE,TX Element Write After Trigger Address Enable" "0: Flag TXEENSA.TXEWATA does not activate the..,1: If TXEENSA.TXEWATA = 1 the interrupt line.." newline bitfld.long 0xC 3. "TXEIDLCE,TX Element Illegal DLC Enable" "0: Flag TXEENSA.TXEIDLC does not activate the..,1: If TXEENSA.TXEIDLC = 1 the interrupt line.." bitfld.long 0xC 2. "TXEIASE,TX Element Illegal Access Sequence Enable" "0: Flag TXEENSA.TXEIAS does not activate the..,1: If TXEENSA.TXEIAS = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 1. "TXEIEE,TX Element Illegal Enqueuing Enable" "0: Flag TXEENSA.TXEIE does not activate the..,1: If TXEENSA.TXEIE = 1 the interrupt line dmu_int.." bitfld.long 0xC 0. "TXENSAE,TX Element Not Start Address Enable" "0: Flag DMUIR.TXENSA does not activate the..,1: If DMUIR.TXENSA = 1 the interrupt line dmu_int.." line.long 0x10 "DMUC,DMU Configuration register" bitfld.long 0x10 0. "TTS,Transfer Timestamp" "0: No timestamp will be transferred via DMU Virtual..,1: Timestamp of message will be transferred from.." tree.end tree "CAN_SUB_4_DMU_2" base ad:0x70260000 rgroup.long 0x3C0++0x3 line.long 0x0 "DMUCR,DMU Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" group.long 0x3C4++0x13 line.long 0x0 "DMUI,DMU Internals register" bitfld.long 0x0 31. "TXE,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 30. "RX1,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 29. "RX0,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 28. "TX,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 24.--26. "EHS,Element Handler State" "0: wait for bit M_CAN:CCCR.CCE getting zero,1: wait for Start Address,2: wait for Trigger Address,3: wait for transfer of Element word,4: acknowledge to M_CAN,5: exception recovery,?,?" bitfld.long 0x0 23. "DTXE,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 22. "DTX1,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 21. "DTX0,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 20. "DTX,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 16.--18. "DEHS,Detect Element Handler State" "?,?,?,?,?,?,?,7: unused state" newline bitfld.long 0x0 15. "ENA,DMU is enabled" "0: DMU is disabled,1: DMU is enabled and can process DMA data" hexmask.long.byte 0x0 8.--12. 1. "TFQPIP,TX FIFO/Queue Put Index Previous" newline bitfld.long 0x0 3. "TXER,TX Event Service Request line of DMU" "0: No TX Event DMA service requested,1: TX Event DMA Service requested" bitfld.long 0x0 2. "RX1R,RX1 Service Request line of DMU" "0: No RX1 DMA service requested,1: RX1 DMA Service requested" newline bitfld.long 0x0 1. "RX0R,RX0 Service Request line of DMU" "0: No RX0 DMA service requested,1: RX0 DMA Service requested" bitfld.long 0x0 0. "TXR,TX Service Request line of DMU" "0: No TX DMA service requested,1: TX DMA Service requested" line.long 0x4 "DMUQC,DMU Queuing Counter register" hexmask.long.byte 0x4 24.--31. 1. "TXEEDC,TX Event Element Dequeuing Counter" hexmask.long.byte 0x4 16.--23. 1. "RX1EDC,RX1 Element Dequeuing Counter" newline hexmask.long.byte 0x4 8.--15. 1. "RX0EDC,RX0 Element Dequeuing Counter" hexmask.long.byte 0x4 0.--7. 1. "TXEEC,TX Element Enqueuing Counter" line.long 0x8 "DMUIR,DMU Interrupt Register" bitfld.long 0x8 30. "IAC,Illegal Access while in Configuration mode" "0: No Illegal Access while CCE mode,1: Illegal Access while CCE mode" bitfld.long 0x8 29. "DT,Debug Trigger" "0: Debug point not reached,1: Debug point reached" newline bitfld.long 0x8 28. "TXEED,TX Event Element Dequeued" "0: No TX Event Element dequeued,1: TX Event Element successfully dequeued" bitfld.long 0x8 27. "TXEEIW,TX Event Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU TX Event Element.." newline bitfld.long 0x8 26. "TXEEIAS,TX Event Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 25. "TXEEID,TX Event Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 24. "TXEENSA,TX Event Element Not Start Address" "0: No illegal read access,1: Read from TX Event Element begins without using.." bitfld.long 0x8 21. "RX1EIO,RX1 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 20. "RX1ED,RX1 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 19. "RX1EIW,RX1 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 18. "RX1EIAS,RX1 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 17. "RX1EID,RX1 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 16. "RX1ENSA,RX1 Element Not Start Address" "0: No illegal read access,1: Read from RX1 Element begins without using start.." bitfld.long 0x8 15. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Uncorrected bit error detected" newline bitfld.long 0x8 14. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected" bitfld.long 0x8 13. "RX0EIO,RX0 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 12. "RX0ED,RX0 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 11. "RX0EIW,RX0 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 10. "RX0EIAS,RX0 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 9. "RX0EID,RX0 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 8. "RX0ENSA,RX0 Element Not Start Address" "0: No illegal read access,1: Read from RX0 Element begins without using start.." bitfld.long 0x8 6. "TXEE,TX Element Enqueued" "0: No Tx message enqueued,1: Tx message successfully enqueued" newline bitfld.long 0x8 5. "TXEIR,TX Element Illegal Read" "0: No read access,1: Illegal read access to DMU TX Element section.." bitfld.long 0x8 4. "TXEWATA,TX Element Write After Trigger Address" "0: No write after Trigger Address,1: Enqueue a message" newline bitfld.long 0x8 3. "TXEIDLC,TX Element Illegal DLC" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." bitfld.long 0x8 2. "TXEIAS,TX Element Illegal Access Sequence" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." newline bitfld.long 0x8 1. "TXEIE,TX Element Illegal Enqueuing" "0: No illegal enqueuing,1: Start of enqueuing without request detected.." bitfld.long 0x8 0. "TXENSA,TX Element Not Start Address" "0: No illegal write access,1: Write to TX Element begins without using start.." line.long 0xC "DMUIE,DMU Interrupt Enable register" bitfld.long 0xC 30. "IACE,Illegal Access while in Configuration mode Enable" "0: Flag DMUIR.IAC does not activate the interrupt..,1: If DMUIR.IAC = 1 the interrupt line dmu_int will.." bitfld.long 0xC 29. "DTE,Debug Trigger Enable" "0: Flag DMUIR.DT does not activate the interrupt..,1: If DMUIR.DT = 1 the interrupt line dmu_int will.." newline bitfld.long 0xC 28. "TXEEDE,TX Event Element Dequeued" "0: Flag DMUIR.TXEED does not activate the interrupt..,1: If DMUIR.TXEED = 1 the interrupt line dmu_int.." bitfld.long 0xC 27. "TXEEIWE,TX Event Element Illegal Write" "0: Flag DMUIR.TXEEIW does not activate the..,1: If DMUIR.TXEEIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 26. "TXEEIASE,TX Event Element Illegal Access Sequence" "0: Flag DMUIR.TXEEIAS does not activate the..,1: If DMUIR.TXEEIAS = 1 the interrupt line dmu_int.." bitfld.long 0xC 25. "TXEEIDE,TX Event Element Illegal Dequeuing" "0: Flag DMUIR.TXEEID does not activate the..,1: If DMUIR.TXEEID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 24. "TXEENSAE,TX Event Element Not Start Address" "0: Flag TXEENSA.TXEENSA does not activate the..,1: If TXEENSA.TXEENSA = 1 the interrupt line.." bitfld.long 0xC 21. "RX1EIOE,RX1 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX1EIO does not activate the..,1: If TXEENSA.RX1EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 20. "RX1EDE,RX1 Element Dequeued Enable" "0: Flag TXEENSA.RX1ED does not activate the..,1: If TXEENSA.RX1ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 19. "RX1EIWE,RX1 Element Illegal Write Enable" "0: Flag TXEENSA.RX1EIW does not activate the..,1: If TXEENSA.RX1EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 18. "RX1EIASE,RX1 Element Illegal Access Sequence Enable" "0: Flag TXEENSA.RX1EIAS does not activate the..,1: If TXEENSA.RX1EIAS = 1 the interrupt line.." bitfld.long 0xC 17. "RX1EIDE,RX1 Element Illegal Dequeuing Enable" "0: Flag TXEENSA.RX1EID does not activate the..,1: If TXEENSA.RX1EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 16. "RX1ENSAE,RX1 Element Not Start Address Enable" "0: Flag TXEENSA.RX1ENSA does not activate the..,1: If TXEENSA.RX1ENSA = 1 the interrupt line.." bitfld.long 0xC 15. "BEUE,Bit Error Uncorrected Enable" "0: Flag TXEENSA.BEU does not activate the interrupt..,1: If TXEENSA.BEU = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 14. "BECE,Bit Error Corrected Enable" "0: Flag TXEENSA.BEC does not activate the interrupt..,1: If TXEENSA.BEC = 1 the interrupt line dmu_int.." bitfld.long 0xC 13. "RX0EIOE,RX0 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX0EIO does not activate the..,1: If TXEENSA.RX0EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 12. "RX0EDE,RX0 Element Dequeued Enabled" "0: Flag TXEENSA.RX0ED does not activate the..,1: If TXEENSA.RX0ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 11. "RX0EIWE,RX0 Element Illegal Write Enabled" "0: Flag TXEENSA.RX0EIW does not activate the..,1: If TXEENSA.RX0EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 10. "RX0EIASE,RX0 Element Illegal Access Sequence Enabled" "0: Flag TXEENSA.RX0EIAS does not activate the..,1: If TXEENSA.RX0EIAS = 1 the interrupt line.." bitfld.long 0xC 9. "RX0EIDE,RX0 Element Illegal Dequeuing Enabled" "0: Flag TXEENSA.RX0EID does not activate the..,1: If TXEENSA.RX0EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 8. "RX0ENSAE,RX0 Element Not Start Address Enabled" "0: Flag TXEENSA.RX0ENSA does not activate the..,1: If TXEENSA.RX0ENSA = 1 the interrupt line.." bitfld.long 0xC 6. "TXEEE,TX Element Enqueued Enable" "0: Flag TXEENSA.TXEE does not activate the..,1: If TXEENSA.TXEE = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 5. "TXEIRE,TX Element Illegal Read Enable" "0: Flag TXEENSA.TXEIR does not activate the..,1: If TXEENSA.TXEIR = 1 the interrupt line dmu_int.." bitfld.long 0xC 4. "TXEWATAE,TX Element Write After Trigger Address Enable" "0: Flag TXEENSA.TXEWATA does not activate the..,1: If TXEENSA.TXEWATA = 1 the interrupt line.." newline bitfld.long 0xC 3. "TXEIDLCE,TX Element Illegal DLC Enable" "0: Flag TXEENSA.TXEIDLC does not activate the..,1: If TXEENSA.TXEIDLC = 1 the interrupt line.." bitfld.long 0xC 2. "TXEIASE,TX Element Illegal Access Sequence Enable" "0: Flag TXEENSA.TXEIAS does not activate the..,1: If TXEENSA.TXEIAS = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 1. "TXEIEE,TX Element Illegal Enqueuing Enable" "0: Flag TXEENSA.TXEIE does not activate the..,1: If TXEENSA.TXEIE = 1 the interrupt line dmu_int.." bitfld.long 0xC 0. "TXENSAE,TX Element Not Start Address Enable" "0: Flag DMUIR.TXENSA does not activate the..,1: If DMUIR.TXENSA = 1 the interrupt line dmu_int.." line.long 0x10 "DMUC,DMU Configuration register" bitfld.long 0x10 0. "TTS,Transfer Timestamp" "0: No timestamp will be transferred via DMU Virtual..,1: Timestamp of message will be transferred from.." tree.end tree "CAN_SUB_4_DMU_3" base ad:0x70264000 rgroup.long 0x3C0++0x3 line.long 0x0 "DMUCR,DMU Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" group.long 0x3C4++0x13 line.long 0x0 "DMUI,DMU Internals register" bitfld.long 0x0 31. "TXE,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 30. "RX1,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 29. "RX0,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 28. "TX,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 24.--26. "EHS,Element Handler State" "0: wait for bit M_CAN:CCCR.CCE getting zero,1: wait for Start Address,2: wait for Trigger Address,3: wait for transfer of Element word,4: acknowledge to M_CAN,5: exception recovery,?,?" bitfld.long 0x0 23. "DTXE,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 22. "DTX1,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 21. "DTX0,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 20. "DTX,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 16.--18. "DEHS,Detect Element Handler State" "?,?,?,?,?,?,?,7: unused state" newline bitfld.long 0x0 15. "ENA,DMU is enabled" "0: DMU is disabled,1: DMU is enabled and can process DMA data" hexmask.long.byte 0x0 8.--12. 1. "TFQPIP,TX FIFO/Queue Put Index Previous" newline bitfld.long 0x0 3. "TXER,TX Event Service Request line of DMU" "0: No TX Event DMA service requested,1: TX Event DMA Service requested" bitfld.long 0x0 2. "RX1R,RX1 Service Request line of DMU" "0: No RX1 DMA service requested,1: RX1 DMA Service requested" newline bitfld.long 0x0 1. "RX0R,RX0 Service Request line of DMU" "0: No RX0 DMA service requested,1: RX0 DMA Service requested" bitfld.long 0x0 0. "TXR,TX Service Request line of DMU" "0: No TX DMA service requested,1: TX DMA Service requested" line.long 0x4 "DMUQC,DMU Queuing Counter register" hexmask.long.byte 0x4 24.--31. 1. "TXEEDC,TX Event Element Dequeuing Counter" hexmask.long.byte 0x4 16.--23. 1. "RX1EDC,RX1 Element Dequeuing Counter" newline hexmask.long.byte 0x4 8.--15. 1. "RX0EDC,RX0 Element Dequeuing Counter" hexmask.long.byte 0x4 0.--7. 1. "TXEEC,TX Element Enqueuing Counter" line.long 0x8 "DMUIR,DMU Interrupt Register" bitfld.long 0x8 30. "IAC,Illegal Access while in Configuration mode" "0: No Illegal Access while CCE mode,1: Illegal Access while CCE mode" bitfld.long 0x8 29. "DT,Debug Trigger" "0: Debug point not reached,1: Debug point reached" newline bitfld.long 0x8 28. "TXEED,TX Event Element Dequeued" "0: No TX Event Element dequeued,1: TX Event Element successfully dequeued" bitfld.long 0x8 27. "TXEEIW,TX Event Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU TX Event Element.." newline bitfld.long 0x8 26. "TXEEIAS,TX Event Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 25. "TXEEID,TX Event Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 24. "TXEENSA,TX Event Element Not Start Address" "0: No illegal read access,1: Read from TX Event Element begins without using.." bitfld.long 0x8 21. "RX1EIO,RX1 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 20. "RX1ED,RX1 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 19. "RX1EIW,RX1 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 18. "RX1EIAS,RX1 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 17. "RX1EID,RX1 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 16. "RX1ENSA,RX1 Element Not Start Address" "0: No illegal read access,1: Read from RX1 Element begins without using start.." bitfld.long 0x8 15. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Uncorrected bit error detected" newline bitfld.long 0x8 14. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected" bitfld.long 0x8 13. "RX0EIO,RX0 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 12. "RX0ED,RX0 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 11. "RX0EIW,RX0 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 10. "RX0EIAS,RX0 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 9. "RX0EID,RX0 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 8. "RX0ENSA,RX0 Element Not Start Address" "0: No illegal read access,1: Read from RX0 Element begins without using start.." bitfld.long 0x8 6. "TXEE,TX Element Enqueued" "0: No Tx message enqueued,1: Tx message successfully enqueued" newline bitfld.long 0x8 5. "TXEIR,TX Element Illegal Read" "0: No read access,1: Illegal read access to DMU TX Element section.." bitfld.long 0x8 4. "TXEWATA,TX Element Write After Trigger Address" "0: No write after Trigger Address,1: Enqueue a message" newline bitfld.long 0x8 3. "TXEIDLC,TX Element Illegal DLC" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." bitfld.long 0x8 2. "TXEIAS,TX Element Illegal Access Sequence" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." newline bitfld.long 0x8 1. "TXEIE,TX Element Illegal Enqueuing" "0: No illegal enqueuing,1: Start of enqueuing without request detected.." bitfld.long 0x8 0. "TXENSA,TX Element Not Start Address" "0: No illegal write access,1: Write to TX Element begins without using start.." line.long 0xC "DMUIE,DMU Interrupt Enable register" bitfld.long 0xC 30. "IACE,Illegal Access while in Configuration mode Enable" "0: Flag DMUIR.IAC does not activate the interrupt..,1: If DMUIR.IAC = 1 the interrupt line dmu_int will.." bitfld.long 0xC 29. "DTE,Debug Trigger Enable" "0: Flag DMUIR.DT does not activate the interrupt..,1: If DMUIR.DT = 1 the interrupt line dmu_int will.." newline bitfld.long 0xC 28. "TXEEDE,TX Event Element Dequeued" "0: Flag DMUIR.TXEED does not activate the interrupt..,1: If DMUIR.TXEED = 1 the interrupt line dmu_int.." bitfld.long 0xC 27. "TXEEIWE,TX Event Element Illegal Write" "0: Flag DMUIR.TXEEIW does not activate the..,1: If DMUIR.TXEEIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 26. "TXEEIASE,TX Event Element Illegal Access Sequence" "0: Flag DMUIR.TXEEIAS does not activate the..,1: If DMUIR.TXEEIAS = 1 the interrupt line dmu_int.." bitfld.long 0xC 25. "TXEEIDE,TX Event Element Illegal Dequeuing" "0: Flag DMUIR.TXEEID does not activate the..,1: If DMUIR.TXEEID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 24. "TXEENSAE,TX Event Element Not Start Address" "0: Flag TXEENSA.TXEENSA does not activate the..,1: If TXEENSA.TXEENSA = 1 the interrupt line.." bitfld.long 0xC 21. "RX1EIOE,RX1 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX1EIO does not activate the..,1: If TXEENSA.RX1EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 20. "RX1EDE,RX1 Element Dequeued Enable" "0: Flag TXEENSA.RX1ED does not activate the..,1: If TXEENSA.RX1ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 19. "RX1EIWE,RX1 Element Illegal Write Enable" "0: Flag TXEENSA.RX1EIW does not activate the..,1: If TXEENSA.RX1EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 18. "RX1EIASE,RX1 Element Illegal Access Sequence Enable" "0: Flag TXEENSA.RX1EIAS does not activate the..,1: If TXEENSA.RX1EIAS = 1 the interrupt line.." bitfld.long 0xC 17. "RX1EIDE,RX1 Element Illegal Dequeuing Enable" "0: Flag TXEENSA.RX1EID does not activate the..,1: If TXEENSA.RX1EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 16. "RX1ENSAE,RX1 Element Not Start Address Enable" "0: Flag TXEENSA.RX1ENSA does not activate the..,1: If TXEENSA.RX1ENSA = 1 the interrupt line.." bitfld.long 0xC 15. "BEUE,Bit Error Uncorrected Enable" "0: Flag TXEENSA.BEU does not activate the interrupt..,1: If TXEENSA.BEU = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 14. "BECE,Bit Error Corrected Enable" "0: Flag TXEENSA.BEC does not activate the interrupt..,1: If TXEENSA.BEC = 1 the interrupt line dmu_int.." bitfld.long 0xC 13. "RX0EIOE,RX0 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX0EIO does not activate the..,1: If TXEENSA.RX0EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 12. "RX0EDE,RX0 Element Dequeued Enabled" "0: Flag TXEENSA.RX0ED does not activate the..,1: If TXEENSA.RX0ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 11. "RX0EIWE,RX0 Element Illegal Write Enabled" "0: Flag TXEENSA.RX0EIW does not activate the..,1: If TXEENSA.RX0EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 10. "RX0EIASE,RX0 Element Illegal Access Sequence Enabled" "0: Flag TXEENSA.RX0EIAS does not activate the..,1: If TXEENSA.RX0EIAS = 1 the interrupt line.." bitfld.long 0xC 9. "RX0EIDE,RX0 Element Illegal Dequeuing Enabled" "0: Flag TXEENSA.RX0EID does not activate the..,1: If TXEENSA.RX0EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 8. "RX0ENSAE,RX0 Element Not Start Address Enabled" "0: Flag TXEENSA.RX0ENSA does not activate the..,1: If TXEENSA.RX0ENSA = 1 the interrupt line.." bitfld.long 0xC 6. "TXEEE,TX Element Enqueued Enable" "0: Flag TXEENSA.TXEE does not activate the..,1: If TXEENSA.TXEE = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 5. "TXEIRE,TX Element Illegal Read Enable" "0: Flag TXEENSA.TXEIR does not activate the..,1: If TXEENSA.TXEIR = 1 the interrupt line dmu_int.." bitfld.long 0xC 4. "TXEWATAE,TX Element Write After Trigger Address Enable" "0: Flag TXEENSA.TXEWATA does not activate the..,1: If TXEENSA.TXEWATA = 1 the interrupt line.." newline bitfld.long 0xC 3. "TXEIDLCE,TX Element Illegal DLC Enable" "0: Flag TXEENSA.TXEIDLC does not activate the..,1: If TXEENSA.TXEIDLC = 1 the interrupt line.." bitfld.long 0xC 2. "TXEIASE,TX Element Illegal Access Sequence Enable" "0: Flag TXEENSA.TXEIAS does not activate the..,1: If TXEENSA.TXEIAS = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 1. "TXEIEE,TX Element Illegal Enqueuing Enable" "0: Flag TXEENSA.TXEIE does not activate the..,1: If TXEENSA.TXEIE = 1 the interrupt line dmu_int.." bitfld.long 0xC 0. "TXENSAE,TX Element Not Start Address Enable" "0: Flag DMUIR.TXENSA does not activate the..,1: If DMUIR.TXENSA = 1 the interrupt line dmu_int.." line.long 0x10 "DMUC,DMU Configuration register" bitfld.long 0x10 0. "TTS,Transfer Timestamp" "0: No timestamp will be transferred via DMU Virtual..,1: Timestamp of message will be transferred from.." tree.end tree "CAN_SUB_4_DMU_4" base ad:0x70268000 rgroup.long 0x3C0++0x3 line.long 0x0 "DMUCR,DMU Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" group.long 0x3C4++0x13 line.long 0x0 "DMUI,DMU Internals register" bitfld.long 0x0 31. "TXE,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 30. "RX1,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 29. "RX0,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" bitfld.long 0x0 28. "TX,Actual DMU Element Service" "0: DMU Virtual Buffer is currently not served,1: DMU Virtual Buffer is currently served" newline bitfld.long 0x0 24.--26. "EHS,Element Handler State" "0: wait for bit M_CAN:CCCR.CCE getting zero,1: wait for Start Address,2: wait for Trigger Address,3: wait for transfer of Element word,4: acknowledge to M_CAN,5: exception recovery,?,?" bitfld.long 0x0 23. "DTXE,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 22. "DTX1,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 21. "DTX0,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." newline bitfld.long 0x0 20. "DTX,Detect DMU Element Service" "0: Queuing of DMU Element does not activate..,1: Queuing of DMU Element will activate interrupt.." bitfld.long 0x0 16.--18. "DEHS,Detect Element Handler State" "?,?,?,?,?,?,?,7: unused state" newline bitfld.long 0x0 15. "ENA,DMU is enabled" "0: DMU is disabled,1: DMU is enabled and can process DMA data" hexmask.long.byte 0x0 8.--12. 1. "TFQPIP,TX FIFO/Queue Put Index Previous" newline bitfld.long 0x0 3. "TXER,TX Event Service Request line of DMU" "0: No TX Event DMA service requested,1: TX Event DMA Service requested" bitfld.long 0x0 2. "RX1R,RX1 Service Request line of DMU" "0: No RX1 DMA service requested,1: RX1 DMA Service requested" newline bitfld.long 0x0 1. "RX0R,RX0 Service Request line of DMU" "0: No RX0 DMA service requested,1: RX0 DMA Service requested" bitfld.long 0x0 0. "TXR,TX Service Request line of DMU" "0: No TX DMA service requested,1: TX DMA Service requested" line.long 0x4 "DMUQC,DMU Queuing Counter register" hexmask.long.byte 0x4 24.--31. 1. "TXEEDC,TX Event Element Dequeuing Counter" hexmask.long.byte 0x4 16.--23. 1. "RX1EDC,RX1 Element Dequeuing Counter" newline hexmask.long.byte 0x4 8.--15. 1. "RX0EDC,RX0 Element Dequeuing Counter" hexmask.long.byte 0x4 0.--7. 1. "TXEEC,TX Element Enqueuing Counter" line.long 0x8 "DMUIR,DMU Interrupt Register" bitfld.long 0x8 30. "IAC,Illegal Access while in Configuration mode" "0: No Illegal Access while CCE mode,1: Illegal Access while CCE mode" bitfld.long 0x8 29. "DT,Debug Trigger" "0: Debug point not reached,1: Debug point reached" newline bitfld.long 0x8 28. "TXEED,TX Event Element Dequeued" "0: No TX Event Element dequeued,1: TX Event Element successfully dequeued" bitfld.long 0x8 27. "TXEEIW,TX Event Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU TX Event Element.." newline bitfld.long 0x8 26. "TXEEIAS,TX Event Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 25. "TXEEID,TX Event Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 24. "TXEENSA,TX Event Element Not Start Address" "0: No illegal read access,1: Read from TX Event Element begins without using.." bitfld.long 0x8 21. "RX1EIO,RX1 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 20. "RX1ED,RX1 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 19. "RX1EIW,RX1 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 18. "RX1EIAS,RX1 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 17. "RX1EID,RX1 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 16. "RX1ENSA,RX1 Element Not Start Address" "0: No illegal read access,1: Read from RX1 Element begins without using start.." bitfld.long 0x8 15. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Uncorrected bit error detected" newline bitfld.long 0x8 14. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected" bitfld.long 0x8 13. "RX0EIO,RX0 Element Illegal Overwrite by timestamp" "0: No illegal overwrite detected,1: Timestamp at DMU RX element" newline bitfld.long 0x8 12. "RX0ED,RX0 Element Dequeued" "0: No Rx message dequeued,1: Rx message successfully dequeued" bitfld.long 0x8 11. "RX0EIW,RX0 Element Illegal Write" "0: No write access detected,1: Illegal write access to DMU RX1 Element detected.." newline bitfld.long 0x8 10. "RX0EIAS,RX0 Element Illegal Access Sequence" "0: No illegal addressing sequence detected,1: Accesses are not strictly linear to ascending.." bitfld.long 0x8 9. "RX0EID,RX0 Element Illegal Dequeuing" "0: No illegal dequeuing,1: Start of dequeuing without request detected.." newline bitfld.long 0x8 8. "RX0ENSA,RX0 Element Not Start Address" "0: No illegal read access,1: Read from RX0 Element begins without using start.." bitfld.long 0x8 6. "TXEE,TX Element Enqueued" "0: No Tx message enqueued,1: Tx message successfully enqueued" newline bitfld.long 0x8 5. "TXEIR,TX Element Illegal Read" "0: No read access,1: Illegal read access to DMU TX Element section.." bitfld.long 0x8 4. "TXEWATA,TX Element Write After Trigger Address" "0: No write after Trigger Address,1: Enqueue a message" newline bitfld.long 0x8 3. "TXEIDLC,TX Element Illegal DLC" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." bitfld.long 0x8 2. "TXEIAS,TX Element Illegal Access Sequence" "0: No illegal DLC detected,1: DLC exceeds Tx Buffer element size of M_CAN.." newline bitfld.long 0x8 1. "TXEIE,TX Element Illegal Enqueuing" "0: No illegal enqueuing,1: Start of enqueuing without request detected.." bitfld.long 0x8 0. "TXENSA,TX Element Not Start Address" "0: No illegal write access,1: Write to TX Element begins without using start.." line.long 0xC "DMUIE,DMU Interrupt Enable register" bitfld.long 0xC 30. "IACE,Illegal Access while in Configuration mode Enable" "0: Flag DMUIR.IAC does not activate the interrupt..,1: If DMUIR.IAC = 1 the interrupt line dmu_int will.." bitfld.long 0xC 29. "DTE,Debug Trigger Enable" "0: Flag DMUIR.DT does not activate the interrupt..,1: If DMUIR.DT = 1 the interrupt line dmu_int will.." newline bitfld.long 0xC 28. "TXEEDE,TX Event Element Dequeued" "0: Flag DMUIR.TXEED does not activate the interrupt..,1: If DMUIR.TXEED = 1 the interrupt line dmu_int.." bitfld.long 0xC 27. "TXEEIWE,TX Event Element Illegal Write" "0: Flag DMUIR.TXEEIW does not activate the..,1: If DMUIR.TXEEIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 26. "TXEEIASE,TX Event Element Illegal Access Sequence" "0: Flag DMUIR.TXEEIAS does not activate the..,1: If DMUIR.TXEEIAS = 1 the interrupt line dmu_int.." bitfld.long 0xC 25. "TXEEIDE,TX Event Element Illegal Dequeuing" "0: Flag DMUIR.TXEEID does not activate the..,1: If DMUIR.TXEEID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 24. "TXEENSAE,TX Event Element Not Start Address" "0: Flag TXEENSA.TXEENSA does not activate the..,1: If TXEENSA.TXEENSA = 1 the interrupt line.." bitfld.long 0xC 21. "RX1EIOE,RX1 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX1EIO does not activate the..,1: If TXEENSA.RX1EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 20. "RX1EDE,RX1 Element Dequeued Enable" "0: Flag TXEENSA.RX1ED does not activate the..,1: If TXEENSA.RX1ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 19. "RX1EIWE,RX1 Element Illegal Write Enable" "0: Flag TXEENSA.RX1EIW does not activate the..,1: If TXEENSA.RX1EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 18. "RX1EIASE,RX1 Element Illegal Access Sequence Enable" "0: Flag TXEENSA.RX1EIAS does not activate the..,1: If TXEENSA.RX1EIAS = 1 the interrupt line.." bitfld.long 0xC 17. "RX1EIDE,RX1 Element Illegal Dequeuing Enable" "0: Flag TXEENSA.RX1EID does not activate the..,1: If TXEENSA.RX1EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 16. "RX1ENSAE,RX1 Element Not Start Address Enable" "0: Flag TXEENSA.RX1ENSA does not activate the..,1: If TXEENSA.RX1ENSA = 1 the interrupt line.." bitfld.long 0xC 15. "BEUE,Bit Error Uncorrected Enable" "0: Flag TXEENSA.BEU does not activate the interrupt..,1: If TXEENSA.BEU = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 14. "BECE,Bit Error Corrected Enable" "0: Flag TXEENSA.BEC does not activate the interrupt..,1: If TXEENSA.BEC = 1 the interrupt line dmu_int.." bitfld.long 0xC 13. "RX0EIOE,RX0 Element Illegal Overwrite by timestamp Enable" "0: Flag TXEENSA.RX0EIO does not activate the..,1: If TXEENSA.RX0EIO = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 12. "RX0EDE,RX0 Element Dequeued Enabled" "0: Flag TXEENSA.RX0ED does not activate the..,1: If TXEENSA.RX0ED = 1 the interrupt line dmu_int.." bitfld.long 0xC 11. "RX0EIWE,RX0 Element Illegal Write Enabled" "0: Flag TXEENSA.RX0EIW does not activate the..,1: If TXEENSA.RX0EIW = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 10. "RX0EIASE,RX0 Element Illegal Access Sequence Enabled" "0: Flag TXEENSA.RX0EIAS does not activate the..,1: If TXEENSA.RX0EIAS = 1 the interrupt line.." bitfld.long 0xC 9. "RX0EIDE,RX0 Element Illegal Dequeuing Enabled" "0: Flag TXEENSA.RX0EID does not activate the..,1: If TXEENSA.RX0EID = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 8. "RX0ENSAE,RX0 Element Not Start Address Enabled" "0: Flag TXEENSA.RX0ENSA does not activate the..,1: If TXEENSA.RX0ENSA = 1 the interrupt line.." bitfld.long 0xC 6. "TXEEE,TX Element Enqueued Enable" "0: Flag TXEENSA.TXEE does not activate the..,1: If TXEENSA.TXEE = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 5. "TXEIRE,TX Element Illegal Read Enable" "0: Flag TXEENSA.TXEIR does not activate the..,1: If TXEENSA.TXEIR = 1 the interrupt line dmu_int.." bitfld.long 0xC 4. "TXEWATAE,TX Element Write After Trigger Address Enable" "0: Flag TXEENSA.TXEWATA does not activate the..,1: If TXEENSA.TXEWATA = 1 the interrupt line.." newline bitfld.long 0xC 3. "TXEIDLCE,TX Element Illegal DLC Enable" "0: Flag TXEENSA.TXEIDLC does not activate the..,1: If TXEENSA.TXEIDLC = 1 the interrupt line.." bitfld.long 0xC 2. "TXEIASE,TX Element Illegal Access Sequence Enable" "0: Flag TXEENSA.TXEIAS does not activate the..,1: If TXEENSA.TXEIAS = 1 the interrupt line dmu_int.." newline bitfld.long 0xC 1. "TXEIEE,TX Element Illegal Enqueuing Enable" "0: Flag TXEENSA.TXEIE does not activate the..,1: If TXEENSA.TXEIE = 1 the interrupt line dmu_int.." bitfld.long 0xC 0. "TXENSAE,TX Element Not Start Address Enable" "0: Flag DMUIR.TXENSA does not activate the..,1: If DMUIR.TXENSA = 1 the interrupt line dmu_int.." line.long 0x10 "DMUC,DMU Configuration register" bitfld.long 0x10 0. "TTS,Transfer Timestamp" "0: No timestamp will be transferred via DMU Virtual..,1: Timestamp of message will be transferred from.." tree.end tree "CAN_SUB_4_M_CAN_1" base ad:0x7025C000 rgroup.long 0x0++0x7 line.long 0x0 "CREL,Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Substep of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "TS_MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "ENDN,Endian Register" hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value" group.long 0xC++0x23 line.long 0x0 "DBTP,Data Bit Timing and Prescaler Register" bitfld.long 0x0 23. "TDC,Transceiver Delay Compensation" "0: Transceiver Delay Compensation disabled,1: Transceiver Delay Compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re) Synchronization Jump Width" line.long 0x4 "TEST,Test register" bitfld.long 0x4 21. "SVAL,Started Valid" "0: Value of TXBNS not valid,1: Value of TXBNS valid" hexmask.long.byte 0x4 16.--20. 1. "TXBNS,Tx Buffer Number Started" newline bitfld.long 0x4 13. "PVAL,Prepared Valid" "0: Value of TXBNP not valid,1: Value of TXBNP valid" hexmask.long.byte 0x4 8.--12. 1. "TXBNP,Tx Buffer Number Prepared" newline bitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant (CAN Rx input = '0'),1: The CAN bus is recessive (CAN Rx input = '1')" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CAN Tx output is controlled by the..,1: Sample Point can be monitored at pin CAN Tx output,2: Dominant ('0') level at pin CAN Tx output,3: Recessive ('1') at pin CAN Tx output" newline bitfld.long 0x4 4. "LBCK,Loop Back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (refer to.." line.long 0x8 "RWD,RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration" line.long 0xC "CCCR,CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0xC 11. "WMM,Wide Message Marker" "0: 8-bit Message Marker used,1: 16-bit Message Marker used replacing 16-bit.." bitfld.long 0xC 10. "UTSU,Use Timestamping Unit" "0: Internal time stamping,1: External time stamping by TSU" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST_EN,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_CAN may be set in power down by stopping Host.." bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started" line.long 0x10 "NBTP,Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,(Re) Synchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Time segment before sample point" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,The time segment after the sample point" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Same as 00" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. "TOC,The Timeout Counter is decremented in multiples of CAN bit times (1 to 16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are.." rgroup.long 0x40++0x7 line.long 0x0 "ECR,Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "PSR,Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Received CAN FD Message" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set." newline bitfld.long 0x4 11. "RESI,ESI CAN FD Message with ESI flag" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state" bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state. It..,1: The M_CAN is in the Error_Passive state" bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing node is synchronizing on CAN..,1: Idle-node is neither receiver nor transmitter,2: Receiver-node is operating as receiver,3: Transmitter-node is operating as transmitter" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: consecutive recessive bits,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.." group.long 0x48++0x3 line.long 0x0 "TDCR,Transmitter Delay compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0xF line.long 0x0 "IR,Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected uncorrected (for example.." bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected (for example ECC)" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Event Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx Event FIDO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "IE,Interrupt Enable Register" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "ILS,Interrupt Line Select Register" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 16. "TSWL,TSWL: Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" line.long 0xC "ILE,Interrupt Line Enable Register" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line disabled,1: Interrupt line enabled" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line disabled,1: Interrupt line enabled" group.long 0x80++0xB line.long 0x0 "GFC,Global Filter Configuration Register" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,ANFE[1:0]: Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x8 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x3 line.long 0x0 "XIDAM,Extended ID and Mask Register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "HPMS,High Priority Message Status Register" bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "NDAT1,New Data 1 Register" bitfld.long 0x0 31. "ND31,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 30. "ND30,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 28. "ND28,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 26. "ND26,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 24. "ND24,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 22. "ND22,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 20. "ND20,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 18. "ND18,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 16. "ND16,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 14. "ND14,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 12. "ND12,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 10. "ND10,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 8. "ND8,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 6. "ND6,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 4. "ND4,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 2. "ND2,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 0. "ND0,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x4 "NDAT2,New Data 2 Register" bitfld.long 0x4 31. "ND63,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 30. "ND62,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 28. "ND60,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 26. "ND58,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 24. "ND56,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 22. "ND54,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 20. "ND52,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 18. "ND50,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 16. "ND48,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 14. "ND46,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 12. "ND44,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 10. "ND42,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 8. "ND40,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 6. "ND38,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 4. "ND36,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 2. "ND34,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 0. "ND32,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x8 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x0 25. "RF0L,RF0L" "0,1" bitfld.long 0x0 24. "F0F,F0F" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,F0PI" hexmask.long.byte 0x0 8.--13. 1. "F0GI,F0GI" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,F0FL" group.long 0xA8++0xB line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "RXF1C,Rx FIFO 1 Configuration Register" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,F1S[6:0]:" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is set" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" line.long 0x8 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Tx FIFO/Queue Size" newline hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x3 line.long 0x0 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x0 31. "AR31,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 30. "AR30,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 29. "AR29,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 28. "AR28,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 27. "AR27,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 26. "AR26,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 25. "AR25,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 24. "AR24,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 23. "AR23,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 22. "AR22,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 21. "AR21,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 20. "AR20,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 19. "AR19,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 18. "AR18,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 17. "AR17,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 16. "AR16,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 15. "AR15,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 14. "AR14,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 13. "AR13,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 12. "AR12,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 11. "AR11,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 10. "AR10,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 9. "AR9,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 8. "AR8,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 7. "AR7,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 6. "AR6,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 5. "AR5,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 4. "AR4,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 3. "AR3,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 2. "AR2,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 1. "AR1,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 0. "AR0,Add Request" "0: No transmission request added,1: Transmission requested added" line.long 0x4 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x4 31. "CR31,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 30. "CR30,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 29. "CR29,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 28. "CR28,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 27. "CR27,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 26. "CR26,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 24. "CR24,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 23. "CR23,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 22. "CR22,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 21. "CR21,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 20. "CR20,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 18. "CR18,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 17. "CR17,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 16. "CR16,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 15. "CR15,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 14. "CR14,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 12. "CR12,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 11. "CR11,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 10. "CR10,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 9. "CR9,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 8. "CR8,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 6. "CR6,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 5. "CR5,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 4. "CR4,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 3. "CR3,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 2. "CR2,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 0. "CR0,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" rgroup.long 0xD8++0x7 line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 29. "TO29,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 28. "TO28,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 27. "TO27,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 23. "TO23,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 22. "TO22,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 21. "TO21,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 17. "TO17,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 16. "TO16,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 15. "TO15,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 11. "TO11,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 10. "TO10,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 9. "TO9,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 5. "TO5,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 4. "TO4,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 3. "TO3,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 29. "CF29,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 28. "CF28,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 27. "CF27,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 23. "CF23,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 22. "CF22,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 21. "CF21,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 17. "CF17,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 16. "CF16,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 15. "CF15,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 11. "CF11,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 10. "CF10,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 9. "CF9,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 5. "CF5,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 4. "CF4,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 3. "CF3,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" group.long 0xE0++0x7 line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" group.long 0xF0++0x3 line.long 0x0 "TXEFC,Tx Event FIFO Configuration Register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address." rgroup.long 0xF4++0x3 line.long 0x0 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0x3 line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge Register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" tree.end tree "CAN_SUB_4_M_CAN_2" base ad:0x70260000 rgroup.long 0x0++0x7 line.long 0x0 "CREL,Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Substep of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "TS_MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "ENDN,Endian Register" hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value" group.long 0xC++0x23 line.long 0x0 "DBTP,Data Bit Timing and Prescaler Register" bitfld.long 0x0 23. "TDC,Transceiver Delay Compensation" "0: Transceiver Delay Compensation disabled,1: Transceiver Delay Compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re) Synchronization Jump Width" line.long 0x4 "TEST,Test register" bitfld.long 0x4 21. "SVAL,Started Valid" "0: Value of TXBNS not valid,1: Value of TXBNS valid" hexmask.long.byte 0x4 16.--20. 1. "TXBNS,Tx Buffer Number Started" newline bitfld.long 0x4 13. "PVAL,Prepared Valid" "0: Value of TXBNP not valid,1: Value of TXBNP valid" hexmask.long.byte 0x4 8.--12. 1. "TXBNP,Tx Buffer Number Prepared" newline bitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant (CAN Rx input = '0'),1: The CAN bus is recessive (CAN Rx input = '1')" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CAN Tx output is controlled by the..,1: Sample Point can be monitored at pin CAN Tx output,2: Dominant ('0') level at pin CAN Tx output,3: Recessive ('1') at pin CAN Tx output" newline bitfld.long 0x4 4. "LBCK,Loop Back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (refer to.." line.long 0x8 "RWD,RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration" line.long 0xC "CCCR,CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0xC 11. "WMM,Wide Message Marker" "0: 8-bit Message Marker used,1: 16-bit Message Marker used replacing 16-bit.." bitfld.long 0xC 10. "UTSU,Use Timestamping Unit" "0: Internal time stamping,1: External time stamping by TSU" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST_EN,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_CAN may be set in power down by stopping Host.." bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started" line.long 0x10 "NBTP,Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,(Re) Synchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Time segment before sample point" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,The time segment after the sample point" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Same as 00" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. "TOC,The Timeout Counter is decremented in multiples of CAN bit times (1 to 16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are.." rgroup.long 0x40++0x7 line.long 0x0 "ECR,Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "PSR,Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Received CAN FD Message" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set." newline bitfld.long 0x4 11. "RESI,ESI CAN FD Message with ESI flag" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state" bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state. It..,1: The M_CAN is in the Error_Passive state" bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing node is synchronizing on CAN..,1: Idle-node is neither receiver nor transmitter,2: Receiver-node is operating as receiver,3: Transmitter-node is operating as transmitter" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: consecutive recessive bits,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.." group.long 0x48++0x3 line.long 0x0 "TDCR,Transmitter Delay compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0xF line.long 0x0 "IR,Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected uncorrected (for example.." bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected (for example ECC)" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Event Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx Event FIDO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "IE,Interrupt Enable Register" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "ILS,Interrupt Line Select Register" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 16. "TSWL,TSWL: Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" line.long 0xC "ILE,Interrupt Line Enable Register" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line disabled,1: Interrupt line enabled" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line disabled,1: Interrupt line enabled" group.long 0x80++0xB line.long 0x0 "GFC,Global Filter Configuration Register" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,ANFE[1:0]: Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x8 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x3 line.long 0x0 "XIDAM,Extended ID and Mask Register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "HPMS,High Priority Message Status Register" bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "NDAT1,New Data 1 Register" bitfld.long 0x0 31. "ND31,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 30. "ND30,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 28. "ND28,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 26. "ND26,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 24. "ND24,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 22. "ND22,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 20. "ND20,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 18. "ND18,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 16. "ND16,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 14. "ND14,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 12. "ND12,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 10. "ND10,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 8. "ND8,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 6. "ND6,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 4. "ND4,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 2. "ND2,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 0. "ND0,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x4 "NDAT2,New Data 2 Register" bitfld.long 0x4 31. "ND63,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 30. "ND62,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 28. "ND60,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 26. "ND58,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 24. "ND56,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 22. "ND54,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 20. "ND52,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 18. "ND50,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 16. "ND48,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 14. "ND46,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 12. "ND44,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 10. "ND42,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 8. "ND40,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 6. "ND38,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 4. "ND36,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 2. "ND34,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 0. "ND32,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x8 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x0 25. "RF0L,RF0L" "0,1" bitfld.long 0x0 24. "F0F,F0F" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,F0PI" hexmask.long.byte 0x0 8.--13. 1. "F0GI,F0GI" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,F0FL" group.long 0xA8++0xB line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "RXF1C,Rx FIFO 1 Configuration Register" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,F1S[6:0]:" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is set" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" line.long 0x8 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Tx FIFO/Queue Size" newline hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x3 line.long 0x0 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x0 31. "AR31,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 30. "AR30,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 29. "AR29,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 28. "AR28,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 27. "AR27,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 26. "AR26,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 25. "AR25,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 24. "AR24,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 23. "AR23,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 22. "AR22,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 21. "AR21,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 20. "AR20,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 19. "AR19,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 18. "AR18,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 17. "AR17,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 16. "AR16,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 15. "AR15,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 14. "AR14,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 13. "AR13,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 12. "AR12,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 11. "AR11,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 10. "AR10,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 9. "AR9,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 8. "AR8,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 7. "AR7,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 6. "AR6,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 5. "AR5,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 4. "AR4,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 3. "AR3,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 2. "AR2,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 1. "AR1,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 0. "AR0,Add Request" "0: No transmission request added,1: Transmission requested added" line.long 0x4 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x4 31. "CR31,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 30. "CR30,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 29. "CR29,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 28. "CR28,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 27. "CR27,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 26. "CR26,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 24. "CR24,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 23. "CR23,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 22. "CR22,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 21. "CR21,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 20. "CR20,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 18. "CR18,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 17. "CR17,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 16. "CR16,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 15. "CR15,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 14. "CR14,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 12. "CR12,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 11. "CR11,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 10. "CR10,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 9. "CR9,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 8. "CR8,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 6. "CR6,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 5. "CR5,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 4. "CR4,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 3. "CR3,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 2. "CR2,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 0. "CR0,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" rgroup.long 0xD8++0x7 line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 29. "TO29,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 28. "TO28,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 27. "TO27,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 23. "TO23,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 22. "TO22,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 21. "TO21,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 17. "TO17,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 16. "TO16,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 15. "TO15,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 11. "TO11,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 10. "TO10,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 9. "TO9,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 5. "TO5,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 4. "TO4,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 3. "TO3,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 29. "CF29,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 28. "CF28,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 27. "CF27,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 23. "CF23,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 22. "CF22,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 21. "CF21,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 17. "CF17,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 16. "CF16,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 15. "CF15,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 11. "CF11,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 10. "CF10,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 9. "CF9,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 5. "CF5,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 4. "CF4,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 3. "CF3,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" group.long 0xE0++0x7 line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" group.long 0xF0++0x3 line.long 0x0 "TXEFC,Tx Event FIFO Configuration Register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address." rgroup.long 0xF4++0x3 line.long 0x0 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0x3 line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge Register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" tree.end tree "CAN_SUB_4_M_CAN_3" base ad:0x70264000 rgroup.long 0x0++0x7 line.long 0x0 "CREL,Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Substep of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "TS_MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "ENDN,Endian Register" hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value" group.long 0xC++0x23 line.long 0x0 "DBTP,Data Bit Timing and Prescaler Register" bitfld.long 0x0 23. "TDC,Transceiver Delay Compensation" "0: Transceiver Delay Compensation disabled,1: Transceiver Delay Compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re) Synchronization Jump Width" line.long 0x4 "TEST,Test register" bitfld.long 0x4 21. "SVAL,Started Valid" "0: Value of TXBNS not valid,1: Value of TXBNS valid" hexmask.long.byte 0x4 16.--20. 1. "TXBNS,Tx Buffer Number Started" newline bitfld.long 0x4 13. "PVAL,Prepared Valid" "0: Value of TXBNP not valid,1: Value of TXBNP valid" hexmask.long.byte 0x4 8.--12. 1. "TXBNP,Tx Buffer Number Prepared" newline bitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant (CAN Rx input = '0'),1: The CAN bus is recessive (CAN Rx input = '1')" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CAN Tx output is controlled by the..,1: Sample Point can be monitored at pin CAN Tx output,2: Dominant ('0') level at pin CAN Tx output,3: Recessive ('1') at pin CAN Tx output" newline bitfld.long 0x4 4. "LBCK,Loop Back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (refer to.." line.long 0x8 "RWD,RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration" line.long 0xC "CCCR,CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0xC 11. "WMM,Wide Message Marker" "0: 8-bit Message Marker used,1: 16-bit Message Marker used replacing 16-bit.." bitfld.long 0xC 10. "UTSU,Use Timestamping Unit" "0: Internal time stamping,1: External time stamping by TSU" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST_EN,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_CAN may be set in power down by stopping Host.." bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started" line.long 0x10 "NBTP,Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,(Re) Synchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Time segment before sample point" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,The time segment after the sample point" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Same as 00" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. "TOC,The Timeout Counter is decremented in multiples of CAN bit times (1 to 16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are.." rgroup.long 0x40++0x7 line.long 0x0 "ECR,Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "PSR,Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Received CAN FD Message" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set." newline bitfld.long 0x4 11. "RESI,ESI CAN FD Message with ESI flag" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state" bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state. It..,1: The M_CAN is in the Error_Passive state" bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing node is synchronizing on CAN..,1: Idle-node is neither receiver nor transmitter,2: Receiver-node is operating as receiver,3: Transmitter-node is operating as transmitter" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: consecutive recessive bits,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.." group.long 0x48++0x3 line.long 0x0 "TDCR,Transmitter Delay compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0xF line.long 0x0 "IR,Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected uncorrected (for example.." bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected (for example ECC)" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Event Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx Event FIDO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "IE,Interrupt Enable Register" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "ILS,Interrupt Line Select Register" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 16. "TSWL,TSWL: Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" line.long 0xC "ILE,Interrupt Line Enable Register" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line disabled,1: Interrupt line enabled" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line disabled,1: Interrupt line enabled" group.long 0x80++0xB line.long 0x0 "GFC,Global Filter Configuration Register" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,ANFE[1:0]: Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x8 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x3 line.long 0x0 "XIDAM,Extended ID and Mask Register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "HPMS,High Priority Message Status Register" bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "NDAT1,New Data 1 Register" bitfld.long 0x0 31. "ND31,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 30. "ND30,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 28. "ND28,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 26. "ND26,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 24. "ND24,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 22. "ND22,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 20. "ND20,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 18. "ND18,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 16. "ND16,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 14. "ND14,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 12. "ND12,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 10. "ND10,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 8. "ND8,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 6. "ND6,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 4. "ND4,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 2. "ND2,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 0. "ND0,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x4 "NDAT2,New Data 2 Register" bitfld.long 0x4 31. "ND63,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 30. "ND62,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 28. "ND60,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 26. "ND58,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 24. "ND56,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 22. "ND54,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 20. "ND52,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 18. "ND50,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 16. "ND48,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 14. "ND46,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 12. "ND44,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 10. "ND42,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 8. "ND40,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 6. "ND38,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 4. "ND36,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 2. "ND34,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 0. "ND32,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x8 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x0 25. "RF0L,RF0L" "0,1" bitfld.long 0x0 24. "F0F,F0F" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,F0PI" hexmask.long.byte 0x0 8.--13. 1. "F0GI,F0GI" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,F0FL" group.long 0xA8++0xB line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "RXF1C,Rx FIFO 1 Configuration Register" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,F1S[6:0]:" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is set" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" line.long 0x8 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Tx FIFO/Queue Size" newline hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x3 line.long 0x0 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x0 31. "AR31,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 30. "AR30,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 29. "AR29,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 28. "AR28,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 27. "AR27,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 26. "AR26,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 25. "AR25,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 24. "AR24,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 23. "AR23,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 22. "AR22,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 21. "AR21,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 20. "AR20,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 19. "AR19,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 18. "AR18,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 17. "AR17,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 16. "AR16,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 15. "AR15,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 14. "AR14,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 13. "AR13,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 12. "AR12,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 11. "AR11,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 10. "AR10,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 9. "AR9,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 8. "AR8,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 7. "AR7,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 6. "AR6,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 5. "AR5,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 4. "AR4,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 3. "AR3,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 2. "AR2,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 1. "AR1,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 0. "AR0,Add Request" "0: No transmission request added,1: Transmission requested added" line.long 0x4 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x4 31. "CR31,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 30. "CR30,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 29. "CR29,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 28. "CR28,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 27. "CR27,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 26. "CR26,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 24. "CR24,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 23. "CR23,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 22. "CR22,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 21. "CR21,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 20. "CR20,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 18. "CR18,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 17. "CR17,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 16. "CR16,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 15. "CR15,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 14. "CR14,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 12. "CR12,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 11. "CR11,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 10. "CR10,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 9. "CR9,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 8. "CR8,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 6. "CR6,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 5. "CR5,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 4. "CR4,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 3. "CR3,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 2. "CR2,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 0. "CR0,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" rgroup.long 0xD8++0x7 line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 29. "TO29,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 28. "TO28,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 27. "TO27,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 23. "TO23,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 22. "TO22,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 21. "TO21,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 17. "TO17,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 16. "TO16,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 15. "TO15,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 11. "TO11,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 10. "TO10,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 9. "TO9,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 5. "TO5,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 4. "TO4,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 3. "TO3,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 29. "CF29,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 28. "CF28,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 27. "CF27,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 23. "CF23,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 22. "CF22,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 21. "CF21,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 17. "CF17,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 16. "CF16,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 15. "CF15,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 11. "CF11,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 10. "CF10,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 9. "CF9,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 5. "CF5,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 4. "CF4,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 3. "CF3,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" group.long 0xE0++0x7 line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" group.long 0xF0++0x3 line.long 0x0 "TXEFC,Tx Event FIFO Configuration Register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address." rgroup.long 0xF4++0x3 line.long 0x0 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0x3 line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge Register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" tree.end tree "CAN_SUB_4_M_CAN_4" base ad:0x70268000 rgroup.long 0x0++0x7 line.long 0x0 "CREL,Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Substep of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "TS_MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "ENDN,Endian Register" hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value" group.long 0xC++0x23 line.long 0x0 "DBTP,Data Bit Timing and Prescaler Register" bitfld.long 0x0 23. "TDC,Transceiver Delay Compensation" "0: Transceiver Delay Compensation disabled,1: Transceiver Delay Compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re) Synchronization Jump Width" line.long 0x4 "TEST,Test register" bitfld.long 0x4 21. "SVAL,Started Valid" "0: Value of TXBNS not valid,1: Value of TXBNS valid" hexmask.long.byte 0x4 16.--20. 1. "TXBNS,Tx Buffer Number Started" newline bitfld.long 0x4 13. "PVAL,Prepared Valid" "0: Value of TXBNP not valid,1: Value of TXBNP valid" hexmask.long.byte 0x4 8.--12. 1. "TXBNP,Tx Buffer Number Prepared" newline bitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant (CAN Rx input = '0'),1: The CAN bus is recessive (CAN Rx input = '1')" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CAN Tx output is controlled by the..,1: Sample Point can be monitored at pin CAN Tx output,2: Dominant ('0') level at pin CAN Tx output,3: Recessive ('1') at pin CAN Tx output" newline bitfld.long 0x4 4. "LBCK,Loop Back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (refer to.." line.long 0x8 "RWD,RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration" line.long 0xC "CCCR,CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0xC 11. "WMM,Wide Message Marker" "0: 8-bit Message Marker used,1: 16-bit Message Marker used replacing 16-bit.." bitfld.long 0xC 10. "UTSU,Use Timestamping Unit" "0: Internal time stamping,1: External time stamping by TSU" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST_EN,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_CAN may be set in power down by stopping Host.." bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started" line.long 0x10 "NBTP,Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,(Re) Synchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Time segment before sample point" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,The time segment after the sample point" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Same as 00" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. "TOC,The Timeout Counter is decremented in multiples of CAN bit times (1 to 16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are.." rgroup.long 0x40++0x7 line.long 0x0 "ECR,Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "PSR,Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Received CAN FD Message" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set." newline bitfld.long 0x4 11. "RESI,ESI CAN FD Message with ESI flag" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state" bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state. It..,1: The M_CAN is in the Error_Passive state" bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing node is synchronizing on CAN..,1: Idle-node is neither receiver nor transmitter,2: Receiver-node is operating as receiver,3: Transmitter-node is operating as transmitter" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: consecutive recessive bits,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.." group.long 0x48++0x3 line.long 0x0 "TDCR,Transmitter Delay compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0xF line.long 0x0 "IR,Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected uncorrected (for example.." bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from Message..,1: Bit error detected and corrected (for example ECC)" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Event Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx Event FIDO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "IE,Interrupt Enable Register" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "ILS,Interrupt Line Select Register" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 16. "TSWL,TSWL: Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line M_CAN INT0,1: Interrupt assigned to interrupt line M_CAN INT1" line.long 0xC "ILE,Interrupt Line Enable Register" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line disabled,1: Interrupt line enabled" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line disabled,1: Interrupt line enabled" group.long 0x80++0xB line.long 0x0 "GFC,Global Filter Configuration Register" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,ANFE[1:0]: Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x8 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x3 line.long 0x0 "XIDAM,Extended ID and Mask Register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "HPMS,High Priority Message Status Register" bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "NDAT1,New Data 1 Register" bitfld.long 0x0 31. "ND31,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 30. "ND30,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 28. "ND28,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 26. "ND26,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 24. "ND24,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 22. "ND22,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 20. "ND20,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 18. "ND18,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 16. "ND16,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 14. "ND14,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 12. "ND12,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 10. "ND10,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 8. "ND8,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 6. "ND6,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 4. "ND4,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 2. "ND2,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x0 0. "ND0,New Data[31:0]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x4 "NDAT2,New Data 2 Register" bitfld.long 0x4 31. "ND63,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 30. "ND62,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 28. "ND60,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 26. "ND58,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 24. "ND56,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 22. "ND54,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 20. "ND52,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 18. "ND50,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 16. "ND48,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 14. "ND46,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 12. "ND44,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 10. "ND42,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 8. "ND40,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 6. "ND38,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 4. "ND36,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 2. "ND34,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" bitfld.long 0x4 0. "ND32,New Data[63:32]" "0: Rx Buffer not updated,1: Rx Buffer updated from new message" line.long 0x8 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x0 25. "RF0L,RF0L" "0,1" bitfld.long 0x0 24. "F0F,F0F" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,F0PI" hexmask.long.byte 0x0 8.--13. 1. "F0GI,F0GI" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,F0FL" group.long 0xA8++0xB line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "RXF1C,Rx FIFO 1 Configuration Register" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,F1S[6:0]:" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is set" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge Register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" line.long 0x8 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Tx FIFO/Queue Size" newline hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x3 line.long 0x0 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0: No transmission request pending,1: Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x0 31. "AR31,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 30. "AR30,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 29. "AR29,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 28. "AR28,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 27. "AR27,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 26. "AR26,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 25. "AR25,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 24. "AR24,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 23. "AR23,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 22. "AR22,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 21. "AR21,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 20. "AR20,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 19. "AR19,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 18. "AR18,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 17. "AR17,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 16. "AR16,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 15. "AR15,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 14. "AR14,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 13. "AR13,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 12. "AR12,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 11. "AR11,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 10. "AR10,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 9. "AR9,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 8. "AR8,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 7. "AR7,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 6. "AR6,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 5. "AR5,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 4. "AR4,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 3. "AR3,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 2. "AR2,Add Request" "0: No transmission request added,1: Transmission requested added" newline bitfld.long 0x0 1. "AR1,Add Request" "0: No transmission request added,1: Transmission requested added" bitfld.long 0x0 0. "AR0,Add Request" "0: No transmission request added,1: Transmission requested added" line.long 0x4 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x4 31. "CR31,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 30. "CR30,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 29. "CR29,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 28. "CR28,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 27. "CR27,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 26. "CR26,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 24. "CR24,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 23. "CR23,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 22. "CR22,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 21. "CR21,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 20. "CR20,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 18. "CR18,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 17. "CR17,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 16. "CR16,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 15. "CR15,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 14. "CR14,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 12. "CR12,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 11. "CR11,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 10. "CR10,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 9. "CR9,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 8. "CR8,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 6. "CR6,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 5. "CR5,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 4. "CR4,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 3. "CR3,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 2. "CR2,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" bitfld.long 0x4 0. "CR0,Cancellation Request" "0: No cancellation pending,1: Cancellation pending" rgroup.long 0xD8++0x7 line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 29. "TO29,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 28. "TO28,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 27. "TO27,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 23. "TO23,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 22. "TO22,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 21. "TO21,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 17. "TO17,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 16. "TO16,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 15. "TO15,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 11. "TO11,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 10. "TO10,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 9. "TO9,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 5. "TO5,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 4. "TO4,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 3. "TO3,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0: No transmission occurred,1: Transmission occurred" line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 29. "CF29,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 28. "CF28,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 27. "CF27,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 23. "CF23,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 22. "CF22,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 21. "CF21,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 17. "CF17,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 16. "CF16,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 15. "CF15,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 11. "CF11,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 10. "CF10,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 9. "CF9,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 5. "CF5,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 4. "CF4,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 3. "CF3,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished" group.long 0xE0++0x7 line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable" line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled" group.long 0xF0++0x3 line.long 0x0 "TXEFC,Tx Event FIFO Configuration Register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address." rgroup.long 0xF4++0x3 line.long 0x0 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.." bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0x3 line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge Register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" tree.end tree "CAN_SUB_4_TSU_1" base ad:0x7025C000 rgroup.long 0x160++0x7 line.long 0x0 "CREL,Core Release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "TSCFG,Timestamp Configuration register" hexmask.long.byte 0x4 8.--15. 1. "TBPRE,TBPRE" bitfld.long 0x4 2. "SCP,Select Capturing Position" "0: Capture Timestamp at EOF,1: Capture Timestamp at SOF" newline bitfld.long 0x4 1. "TBCS,Timebase Counter Select" "0: Timestamp value captured from internal timebase..,1: : Timestamp value captured from input.." bitfld.long 0x4 0. "TSUE,Timestamp Unit Enable 0" "0: TSU disabled,1: TSU enabled" group.long 0x168++0x3 line.long 0x0 "TSS1,Timestamp Status 1 register" bitfld.long 0x0 31. "TSL15,Timestamp Lost" "0,1" bitfld.long 0x0 30. "TSL14,Timestamp Lost" "0,1" newline bitfld.long 0x0 29. "TSL13,Timestamp Lost" "0,1" bitfld.long 0x0 28. "TSL12,Timestamp Lost" "0,1" newline bitfld.long 0x0 27. "TSL11,Timestamp Lost" "0,1" bitfld.long 0x0 26. "TSL10,Timestamp Lost" "0,1" newline bitfld.long 0x0 25. "TSL9,Timestamp Lost" "0,1" bitfld.long 0x0 24. "TSL8,Timestamp Lost" "0,1" newline bitfld.long 0x0 23. "TSL7,Timestamp Lost" "0,1" bitfld.long 0x0 22. "TSL6,Timestamp Lost" "0,1" newline bitfld.long 0x0 21. "TSL5,Timestamp Lost" "0,1" bitfld.long 0x0 20. "TSL4,Timestamp Lost" "0,1" newline bitfld.long 0x0 19. "TSL3,Timestamp Lost" "0,1" bitfld.long 0x0 18. "TSL2,Timestamp Lost" "0,1" newline bitfld.long 0x0 17. "TSL1,Timestamp Lost" "0,1" bitfld.long 0x0 16. "TSL0,Timestamp Lost" "0,1" newline bitfld.long 0x0 15. "TSN15,Timestamp New" "0,1" bitfld.long 0x0 14. "TSN14,Timestamp New" "0,1" newline bitfld.long 0x0 13. "TSN13,Timestamp New" "0,1" bitfld.long 0x0 12. "TSN12,Timestamp New" "0,1" newline bitfld.long 0x0 11. "TSN11,Timestamp New" "0,1" bitfld.long 0x0 10. "TSN10,Timestamp New" "0,1" newline bitfld.long 0x0 9. "TSN9,Timestamp New" "0,1" bitfld.long 0x0 8. "TSN8,Timestamp New" "0,1" newline bitfld.long 0x0 7. "TSN7,Timestamp New" "0,1" bitfld.long 0x0 6. "TSN6,Timestamp New" "0,1" newline bitfld.long 0x0 5. "TSN5,Timestamp New" "0,1" bitfld.long 0x0 4. "TSN4,Timestamp New" "0,1" newline bitfld.long 0x0 3. "TSN3,Timestamp New" "0,1" bitfld.long 0x0 2. "TSN2,Timestamp New" "0,1" newline bitfld.long 0x0 1. "TSN1,Timestamp New" "0,1" bitfld.long 0x0 0. "TSN0,Timestamp New" "0,1" rgroup.long 0x16C++0x43 line.long 0x0 "TSS2,Timestamp Status 2 register" bitfld.long 0x0 14.--15. "ITBG,Internal Timebase and SOF select Generic" "0: no SOF option no internal timebase,1: no SOF option internal timebase (default),2: SOF option no internal timebase,3: SOF option internal timebase" bitfld.long 0x0 12.--13. "NTSG,Number of Timestamps Generic" "0: 4 timestamp registers TS0-TS3,1: 8 timestamp registers TS0-TS7 (default),2: 16 timestamp registers TS0-TS15,3: not a valid value" newline hexmask.long.byte 0x0 0.--3. 1. "TSP,Timestamp Pointer" line.long 0x4 "TS0,Timestamp 0 register" hexmask.long 0x4 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x8 "TS1,Timestamp 1 register" hexmask.long 0x8 0.--31. 1. "TS,Timestamp Word TSn" line.long 0xC "TS2,Timestamp 2 register" hexmask.long 0xC 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x10 "TS3,Timestamp 3 register" hexmask.long 0x10 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x14 "TS4,Timestamp 4 register" hexmask.long 0x14 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x18 "TS5,Timestamp 5 register" hexmask.long 0x18 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x1C "TS6,Timestamp 6 register" hexmask.long 0x1C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x20 "TS7,Timestamp 7 register" hexmask.long 0x20 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x24 "TS8,Timestamp 8 register" hexmask.long 0x24 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x28 "TS9,Timestamp 9 register" hexmask.long 0x28 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x2C "TS10,Timestamp 10 register" hexmask.long 0x2C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x30 "TS11,Timestamp 11 register" hexmask.long 0x30 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x34 "TS12,Timestamp 12 register" hexmask.long 0x34 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x38 "TS13,Timestamp 13 register" hexmask.long 0x38 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x3C "TS14,Timestamp 14 register" hexmask.long 0x3C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x40 "TS15,Timestamp 15 register" hexmask.long 0x40 0.--31. 1. "TS,Timestamp Word TSn" group.long 0x1B0++0x3 line.long 0x0 "ATB,Actual Timebase" hexmask.long 0x0 0.--31. 1. "TB,Timebase for timestamp generation" tree.end tree "CAN_SUB_4_TSU_2" base ad:0x70260000 rgroup.long 0x160++0x7 line.long 0x0 "CREL,Core Release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "TSCFG,Timestamp Configuration register" hexmask.long.byte 0x4 8.--15. 1. "TBPRE,TBPRE" bitfld.long 0x4 2. "SCP,Select Capturing Position" "0: Capture Timestamp at EOF,1: Capture Timestamp at SOF" newline bitfld.long 0x4 1. "TBCS,Timebase Counter Select" "0: Timestamp value captured from internal timebase..,1: : Timestamp value captured from input.." bitfld.long 0x4 0. "TSUE,Timestamp Unit Enable 0" "0: TSU disabled,1: TSU enabled" group.long 0x168++0x3 line.long 0x0 "TSS1,Timestamp Status 1 register" bitfld.long 0x0 31. "TSL15,Timestamp Lost" "0,1" bitfld.long 0x0 30. "TSL14,Timestamp Lost" "0,1" newline bitfld.long 0x0 29. "TSL13,Timestamp Lost" "0,1" bitfld.long 0x0 28. "TSL12,Timestamp Lost" "0,1" newline bitfld.long 0x0 27. "TSL11,Timestamp Lost" "0,1" bitfld.long 0x0 26. "TSL10,Timestamp Lost" "0,1" newline bitfld.long 0x0 25. "TSL9,Timestamp Lost" "0,1" bitfld.long 0x0 24. "TSL8,Timestamp Lost" "0,1" newline bitfld.long 0x0 23. "TSL7,Timestamp Lost" "0,1" bitfld.long 0x0 22. "TSL6,Timestamp Lost" "0,1" newline bitfld.long 0x0 21. "TSL5,Timestamp Lost" "0,1" bitfld.long 0x0 20. "TSL4,Timestamp Lost" "0,1" newline bitfld.long 0x0 19. "TSL3,Timestamp Lost" "0,1" bitfld.long 0x0 18. "TSL2,Timestamp Lost" "0,1" newline bitfld.long 0x0 17. "TSL1,Timestamp Lost" "0,1" bitfld.long 0x0 16. "TSL0,Timestamp Lost" "0,1" newline bitfld.long 0x0 15. "TSN15,Timestamp New" "0,1" bitfld.long 0x0 14. "TSN14,Timestamp New" "0,1" newline bitfld.long 0x0 13. "TSN13,Timestamp New" "0,1" bitfld.long 0x0 12. "TSN12,Timestamp New" "0,1" newline bitfld.long 0x0 11. "TSN11,Timestamp New" "0,1" bitfld.long 0x0 10. "TSN10,Timestamp New" "0,1" newline bitfld.long 0x0 9. "TSN9,Timestamp New" "0,1" bitfld.long 0x0 8. "TSN8,Timestamp New" "0,1" newline bitfld.long 0x0 7. "TSN7,Timestamp New" "0,1" bitfld.long 0x0 6. "TSN6,Timestamp New" "0,1" newline bitfld.long 0x0 5. "TSN5,Timestamp New" "0,1" bitfld.long 0x0 4. "TSN4,Timestamp New" "0,1" newline bitfld.long 0x0 3. "TSN3,Timestamp New" "0,1" bitfld.long 0x0 2. "TSN2,Timestamp New" "0,1" newline bitfld.long 0x0 1. "TSN1,Timestamp New" "0,1" bitfld.long 0x0 0. "TSN0,Timestamp New" "0,1" rgroup.long 0x16C++0x43 line.long 0x0 "TSS2,Timestamp Status 2 register" bitfld.long 0x0 14.--15. "ITBG,Internal Timebase and SOF select Generic" "0: no SOF option no internal timebase,1: no SOF option internal timebase (default),2: SOF option no internal timebase,3: SOF option internal timebase" bitfld.long 0x0 12.--13. "NTSG,Number of Timestamps Generic" "0: 4 timestamp registers TS0-TS3,1: 8 timestamp registers TS0-TS7 (default),2: 16 timestamp registers TS0-TS15,3: not a valid value" newline hexmask.long.byte 0x0 0.--3. 1. "TSP,Timestamp Pointer" line.long 0x4 "TS0,Timestamp 0 register" hexmask.long 0x4 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x8 "TS1,Timestamp 1 register" hexmask.long 0x8 0.--31. 1. "TS,Timestamp Word TSn" line.long 0xC "TS2,Timestamp 2 register" hexmask.long 0xC 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x10 "TS3,Timestamp 3 register" hexmask.long 0x10 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x14 "TS4,Timestamp 4 register" hexmask.long 0x14 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x18 "TS5,Timestamp 5 register" hexmask.long 0x18 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x1C "TS6,Timestamp 6 register" hexmask.long 0x1C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x20 "TS7,Timestamp 7 register" hexmask.long 0x20 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x24 "TS8,Timestamp 8 register" hexmask.long 0x24 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x28 "TS9,Timestamp 9 register" hexmask.long 0x28 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x2C "TS10,Timestamp 10 register" hexmask.long 0x2C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x30 "TS11,Timestamp 11 register" hexmask.long 0x30 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x34 "TS12,Timestamp 12 register" hexmask.long 0x34 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x38 "TS13,Timestamp 13 register" hexmask.long 0x38 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x3C "TS14,Timestamp 14 register" hexmask.long 0x3C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x40 "TS15,Timestamp 15 register" hexmask.long 0x40 0.--31. 1. "TS,Timestamp Word TSn" group.long 0x1B0++0x3 line.long 0x0 "ATB,Actual Timebase" hexmask.long 0x0 0.--31. 1. "TB,Timebase for timestamp generation" tree.end tree "CAN_SUB_4_TSU_3" base ad:0x70264000 rgroup.long 0x160++0x7 line.long 0x0 "CREL,Core Release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "TSCFG,Timestamp Configuration register" hexmask.long.byte 0x4 8.--15. 1. "TBPRE,TBPRE" bitfld.long 0x4 2. "SCP,Select Capturing Position" "0: Capture Timestamp at EOF,1: Capture Timestamp at SOF" newline bitfld.long 0x4 1. "TBCS,Timebase Counter Select" "0: Timestamp value captured from internal timebase..,1: : Timestamp value captured from input.." bitfld.long 0x4 0. "TSUE,Timestamp Unit Enable 0" "0: TSU disabled,1: TSU enabled" group.long 0x168++0x3 line.long 0x0 "TSS1,Timestamp Status 1 register" bitfld.long 0x0 31. "TSL15,Timestamp Lost" "0,1" bitfld.long 0x0 30. "TSL14,Timestamp Lost" "0,1" newline bitfld.long 0x0 29. "TSL13,Timestamp Lost" "0,1" bitfld.long 0x0 28. "TSL12,Timestamp Lost" "0,1" newline bitfld.long 0x0 27. "TSL11,Timestamp Lost" "0,1" bitfld.long 0x0 26. "TSL10,Timestamp Lost" "0,1" newline bitfld.long 0x0 25. "TSL9,Timestamp Lost" "0,1" bitfld.long 0x0 24. "TSL8,Timestamp Lost" "0,1" newline bitfld.long 0x0 23. "TSL7,Timestamp Lost" "0,1" bitfld.long 0x0 22. "TSL6,Timestamp Lost" "0,1" newline bitfld.long 0x0 21. "TSL5,Timestamp Lost" "0,1" bitfld.long 0x0 20. "TSL4,Timestamp Lost" "0,1" newline bitfld.long 0x0 19. "TSL3,Timestamp Lost" "0,1" bitfld.long 0x0 18. "TSL2,Timestamp Lost" "0,1" newline bitfld.long 0x0 17. "TSL1,Timestamp Lost" "0,1" bitfld.long 0x0 16. "TSL0,Timestamp Lost" "0,1" newline bitfld.long 0x0 15. "TSN15,Timestamp New" "0,1" bitfld.long 0x0 14. "TSN14,Timestamp New" "0,1" newline bitfld.long 0x0 13. "TSN13,Timestamp New" "0,1" bitfld.long 0x0 12. "TSN12,Timestamp New" "0,1" newline bitfld.long 0x0 11. "TSN11,Timestamp New" "0,1" bitfld.long 0x0 10. "TSN10,Timestamp New" "0,1" newline bitfld.long 0x0 9. "TSN9,Timestamp New" "0,1" bitfld.long 0x0 8. "TSN8,Timestamp New" "0,1" newline bitfld.long 0x0 7. "TSN7,Timestamp New" "0,1" bitfld.long 0x0 6. "TSN6,Timestamp New" "0,1" newline bitfld.long 0x0 5. "TSN5,Timestamp New" "0,1" bitfld.long 0x0 4. "TSN4,Timestamp New" "0,1" newline bitfld.long 0x0 3. "TSN3,Timestamp New" "0,1" bitfld.long 0x0 2. "TSN2,Timestamp New" "0,1" newline bitfld.long 0x0 1. "TSN1,Timestamp New" "0,1" bitfld.long 0x0 0. "TSN0,Timestamp New" "0,1" rgroup.long 0x16C++0x43 line.long 0x0 "TSS2,Timestamp Status 2 register" bitfld.long 0x0 14.--15. "ITBG,Internal Timebase and SOF select Generic" "0: no SOF option no internal timebase,1: no SOF option internal timebase (default),2: SOF option no internal timebase,3: SOF option internal timebase" bitfld.long 0x0 12.--13. "NTSG,Number of Timestamps Generic" "0: 4 timestamp registers TS0-TS3,1: 8 timestamp registers TS0-TS7 (default),2: 16 timestamp registers TS0-TS15,3: not a valid value" newline hexmask.long.byte 0x0 0.--3. 1. "TSP,Timestamp Pointer" line.long 0x4 "TS0,Timestamp 0 register" hexmask.long 0x4 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x8 "TS1,Timestamp 1 register" hexmask.long 0x8 0.--31. 1. "TS,Timestamp Word TSn" line.long 0xC "TS2,Timestamp 2 register" hexmask.long 0xC 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x10 "TS3,Timestamp 3 register" hexmask.long 0x10 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x14 "TS4,Timestamp 4 register" hexmask.long 0x14 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x18 "TS5,Timestamp 5 register" hexmask.long 0x18 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x1C "TS6,Timestamp 6 register" hexmask.long 0x1C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x20 "TS7,Timestamp 7 register" hexmask.long 0x20 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x24 "TS8,Timestamp 8 register" hexmask.long 0x24 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x28 "TS9,Timestamp 9 register" hexmask.long 0x28 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x2C "TS10,Timestamp 10 register" hexmask.long 0x2C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x30 "TS11,Timestamp 11 register" hexmask.long 0x30 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x34 "TS12,Timestamp 12 register" hexmask.long 0x34 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x38 "TS13,Timestamp 13 register" hexmask.long 0x38 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x3C "TS14,Timestamp 14 register" hexmask.long 0x3C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x40 "TS15,Timestamp 15 register" hexmask.long 0x40 0.--31. 1. "TS,Timestamp Word TSn" group.long 0x1B0++0x3 line.long 0x0 "ATB,Actual Timebase" hexmask.long 0x0 0.--31. 1. "TB,Timebase for timestamp generation" tree.end tree "CAN_SUB_4_TSU_4" base ad:0x70268000 rgroup.long 0x160++0x7 line.long 0x0 "CREL,Core Release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "TSCFG,Timestamp Configuration register" hexmask.long.byte 0x4 8.--15. 1. "TBPRE,TBPRE" bitfld.long 0x4 2. "SCP,Select Capturing Position" "0: Capture Timestamp at EOF,1: Capture Timestamp at SOF" newline bitfld.long 0x4 1. "TBCS,Timebase Counter Select" "0: Timestamp value captured from internal timebase..,1: : Timestamp value captured from input.." bitfld.long 0x4 0. "TSUE,Timestamp Unit Enable 0" "0: TSU disabled,1: TSU enabled" group.long 0x168++0x3 line.long 0x0 "TSS1,Timestamp Status 1 register" bitfld.long 0x0 31. "TSL15,Timestamp Lost" "0,1" bitfld.long 0x0 30. "TSL14,Timestamp Lost" "0,1" newline bitfld.long 0x0 29. "TSL13,Timestamp Lost" "0,1" bitfld.long 0x0 28. "TSL12,Timestamp Lost" "0,1" newline bitfld.long 0x0 27. "TSL11,Timestamp Lost" "0,1" bitfld.long 0x0 26. "TSL10,Timestamp Lost" "0,1" newline bitfld.long 0x0 25. "TSL9,Timestamp Lost" "0,1" bitfld.long 0x0 24. "TSL8,Timestamp Lost" "0,1" newline bitfld.long 0x0 23. "TSL7,Timestamp Lost" "0,1" bitfld.long 0x0 22. "TSL6,Timestamp Lost" "0,1" newline bitfld.long 0x0 21. "TSL5,Timestamp Lost" "0,1" bitfld.long 0x0 20. "TSL4,Timestamp Lost" "0,1" newline bitfld.long 0x0 19. "TSL3,Timestamp Lost" "0,1" bitfld.long 0x0 18. "TSL2,Timestamp Lost" "0,1" newline bitfld.long 0x0 17. "TSL1,Timestamp Lost" "0,1" bitfld.long 0x0 16. "TSL0,Timestamp Lost" "0,1" newline bitfld.long 0x0 15. "TSN15,Timestamp New" "0,1" bitfld.long 0x0 14. "TSN14,Timestamp New" "0,1" newline bitfld.long 0x0 13. "TSN13,Timestamp New" "0,1" bitfld.long 0x0 12. "TSN12,Timestamp New" "0,1" newline bitfld.long 0x0 11. "TSN11,Timestamp New" "0,1" bitfld.long 0x0 10. "TSN10,Timestamp New" "0,1" newline bitfld.long 0x0 9. "TSN9,Timestamp New" "0,1" bitfld.long 0x0 8. "TSN8,Timestamp New" "0,1" newline bitfld.long 0x0 7. "TSN7,Timestamp New" "0,1" bitfld.long 0x0 6. "TSN6,Timestamp New" "0,1" newline bitfld.long 0x0 5. "TSN5,Timestamp New" "0,1" bitfld.long 0x0 4. "TSN4,Timestamp New" "0,1" newline bitfld.long 0x0 3. "TSN3,Timestamp New" "0,1" bitfld.long 0x0 2. "TSN2,Timestamp New" "0,1" newline bitfld.long 0x0 1. "TSN1,Timestamp New" "0,1" bitfld.long 0x0 0. "TSN0,Timestamp New" "0,1" rgroup.long 0x16C++0x43 line.long 0x0 "TSS2,Timestamp Status 2 register" bitfld.long 0x0 14.--15. "ITBG,Internal Timebase and SOF select Generic" "0: no SOF option no internal timebase,1: no SOF option internal timebase (default),2: SOF option no internal timebase,3: SOF option internal timebase" bitfld.long 0x0 12.--13. "NTSG,Number of Timestamps Generic" "0: 4 timestamp registers TS0-TS3,1: 8 timestamp registers TS0-TS7 (default),2: 16 timestamp registers TS0-TS15,3: not a valid value" newline hexmask.long.byte 0x0 0.--3. 1. "TSP,Timestamp Pointer" line.long 0x4 "TS0,Timestamp 0 register" hexmask.long 0x4 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x8 "TS1,Timestamp 1 register" hexmask.long 0x8 0.--31. 1. "TS,Timestamp Word TSn" line.long 0xC "TS2,Timestamp 2 register" hexmask.long 0xC 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x10 "TS3,Timestamp 3 register" hexmask.long 0x10 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x14 "TS4,Timestamp 4 register" hexmask.long 0x14 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x18 "TS5,Timestamp 5 register" hexmask.long 0x18 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x1C "TS6,Timestamp 6 register" hexmask.long 0x1C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x20 "TS7,Timestamp 7 register" hexmask.long 0x20 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x24 "TS8,Timestamp 8 register" hexmask.long 0x24 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x28 "TS9,Timestamp 9 register" hexmask.long 0x28 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x2C "TS10,Timestamp 10 register" hexmask.long 0x2C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x30 "TS11,Timestamp 11 register" hexmask.long 0x30 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x34 "TS12,Timestamp 12 register" hexmask.long 0x34 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x38 "TS13,Timestamp 13 register" hexmask.long 0x38 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x3C "TS14,Timestamp 14 register" hexmask.long 0x3C 0.--31. 1. "TS,Timestamp Word TSn" line.long 0x40 "TS15,Timestamp 15 register" hexmask.long 0x40 0.--31. 1. "TS,Timestamp Word TSn" group.long 0x1B0++0x3 line.long 0x0 "ATB,Actual Timebase" hexmask.long 0x0 0.--31. 1. "TB,Timebase for timestamp generation" tree.end tree.end tree.end tree "CASCADEDMUX (Cascaded MUX Module)" base ad:0x0 tree "CASCADEDMUX_0_SYS_0" base ad:0x703DC800 group.byte 0x0++0x7 line.byte 0x0 "CHCONFIG0,Channel 0 Configuration registers" bitfld.byte 0x0 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x0 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x1 "CHCONFIG1,Channel 1 Configuration registers" bitfld.byte 0x1 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x1 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x2 "CHCONFIG2,Channel 2 Configuration registers" bitfld.byte 0x2 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x2 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x3 "CHCONFIG3,Channel 3 Configuration registers" bitfld.byte 0x3 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x3 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x4 "CHCONFIG4,Channel 4 Configuration registers" bitfld.byte 0x4 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x4 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x5 "CHCONFIG5,Channel 5 Configuration registers" bitfld.byte 0x5 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x5 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x6 "CHCONFIG6,Channel 6 Configuration registers" bitfld.byte 0x6 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x6 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x7 "CHCONFIG7,Channel 7 Configuration registers" bitfld.byte 0x7 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x7 0.--5. 1. "SOURCE,DMA Channel Source" tree.end tree "CASCADEDMUX_0_SYS_1" base ad:0x709DC800 group.byte 0x0++0x7 line.byte 0x0 "CHCONFIG0,Channel 0 Configuration registers" bitfld.byte 0x0 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x0 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x1 "CHCONFIG1,Channel 1 Configuration registers" bitfld.byte 0x1 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x1 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x2 "CHCONFIG2,Channel 2 Configuration registers" bitfld.byte 0x2 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x2 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x3 "CHCONFIG3,Channel 3 Configuration registers" bitfld.byte 0x3 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x3 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x4 "CHCONFIG4,Channel 4 Configuration registers" bitfld.byte 0x4 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x4 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x5 "CHCONFIG5,Channel 5 Configuration registers" bitfld.byte 0x5 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x5 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x6 "CHCONFIG6,Channel 6 Configuration registers" bitfld.byte 0x6 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x6 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x7 "CHCONFIG7,Channel 7 Configuration registers" bitfld.byte 0x7 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x7 0.--5. 1. "SOURCE,DMA Channel Source" tree.end tree "CASCADEDMUX_0_SYS_2" base ad:0x703E0800 group.byte 0x0++0x7 line.byte 0x0 "CHCONFIG0,Channel 0 Configuration registers" bitfld.byte 0x0 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x0 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x1 "CHCONFIG1,Channel 1 Configuration registers" bitfld.byte 0x1 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x1 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x2 "CHCONFIG2,Channel 2 Configuration registers" bitfld.byte 0x2 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x2 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x3 "CHCONFIG3,Channel 3 Configuration registers" bitfld.byte 0x3 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x3 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x4 "CHCONFIG4,Channel 4 Configuration registers" bitfld.byte 0x4 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x4 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x5 "CHCONFIG5,Channel 5 Configuration registers" bitfld.byte 0x5 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x5 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x6 "CHCONFIG6,Channel 6 Configuration registers" bitfld.byte 0x6 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x6 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x7 "CHCONFIG7,Channel 7 Configuration registers" bitfld.byte 0x7 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x7 0.--5. 1. "SOURCE,DMA Channel Source" tree.end tree "CASCADEDMUX_0_SYS_3" base ad:0x709E0800 group.byte 0x0++0x7 line.byte 0x0 "CHCONFIG0,Channel 0 Configuration registers" bitfld.byte 0x0 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x0 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x1 "CHCONFIG1,Channel 1 Configuration registers" bitfld.byte 0x1 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x1 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x2 "CHCONFIG2,Channel 2 Configuration registers" bitfld.byte 0x2 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x2 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x3 "CHCONFIG3,Channel 3 Configuration registers" bitfld.byte 0x3 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x3 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x4 "CHCONFIG4,Channel 4 Configuration registers" bitfld.byte 0x4 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x4 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x5 "CHCONFIG5,Channel 5 Configuration registers" bitfld.byte 0x5 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x5 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x6 "CHCONFIG6,Channel 6 Configuration registers" bitfld.byte 0x6 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x6 0.--5. 1. "SOURCE,DMA Channel Source" line.byte 0x7 "CHCONFIG7,Channel 7 Configuration registers" bitfld.byte 0x7 6. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" hexmask.byte 0x7 0.--5. 1. "SOURCE,DMA Channel Source" tree.end tree.end tree "CEM (Collective Error Manager)" base ad:0x0 tree "CEM_0_CEM_ADDRBLK" base ad:0x7107C000 group.long 0x0++0x3 line.long 0x0 "CMD,Command register" hexmask.long.word 0x0 16.--31. 1. "KEY,Key for writing to CEM programmable registers validated against the “super” key" hexmask.long.byte 0x0 11.--15. 1. "COMMAND,Command for accessing the CEM internal register (set/clear enable set/disable fake fault injection read status and so on)" newline hexmask.long.word 0x0 0.--10. 1. "FAULT_OR_GRP_NUM,Fault number/group number of corresponding internal CEM registers for accessing individual error control/status info as well as error group control/status info." rgroup.long 0x4++0x3 line.long 0x0 "RDATA,Read data register" hexmask.long 0x0 0.--31. 1. "READ_DATA,Data read after command is executed. If only single bit is accessed (fault_inj status or enable) read_data[0] is the output." group.long 0x8++0x3 line.long 0x0 "WDATA,Write data register" hexmask.long 0x0 0.--31. 1. "WRITE_DATA,Write data for setting/clearing internal RW register groups (fault_inj and enable). The mask bits may be applied to write to selected bits." group.long 0x10++0x3 line.long 0x0 "WMASK,Write mask register" hexmask.long 0x0 0.--31. 1. "WRITE_MASK,Mask bits for accessing individual fault group bits during write operations." rgroup.long 0x14++0x3 line.long 0x0 "CMD_STATUS,Command status register" bitfld.long 0x0 2. "INV_CMD,Invalid command is written in the CMD.COMMAND field" "0: Valid command is issued by the user,1: Invalid command is issued by the user" bitfld.long 0x0 1. "INV_KEY,Invalid key is written in CMD.KEY field" "0: Valid key is used for access,1: Invalid key is used for access" newline bitfld.long 0x0 0. "INV_REG,Invalid address is being accessed" "0: Valid address is provided for internal register..,1: Invalid address is provided for internal.." group.long 0x24++0x3 line.long 0x0 "SUPERKEY_REG,Super key register" hexmask.long.word 0x0 0.--15. 1. "SUPERKEY,Golden key used for validation during write access. Write access only during supervisor mode" rgroup.long 0x30++0x7 line.long 0x0 "HW_CFG,Hardware configuration register" hexmask.long 0x0 0.--31. 1. "HW_CFG_PARAM,Hardware configuration parameter for each IP release. This information is provided for debug purposes. The value of this register is dependent on number of faults." line.long 0x4 "VERSION_REG,Verison register" hexmask.long 0x4 0.--31. 1. "VERSION,Release version of IP. This information is provided for debug purposes. The value is fixed per CEM instance depending on the release number." tree.end tree "CEM_1_CEM_ADDRBLK" base ad:0x7167C000 group.long 0x0++0x3 line.long 0x0 "CMD,Command register" hexmask.long.word 0x0 16.--31. 1. "KEY,Key for writing to CEM programmable registers validated against the “super” key" hexmask.long.byte 0x0 11.--15. 1. "COMMAND,Command for accessing the CEM internal register (set/clear enable set/disable fake fault injection read status and so on)" newline hexmask.long.word 0x0 0.--10. 1. "FAULT_OR_GRP_NUM,Fault number/group number of corresponding internal CEM registers for accessing individual error control/status info as well as error group control/status info." rgroup.long 0x4++0x3 line.long 0x0 "RDATA,Read data register" hexmask.long 0x0 0.--31. 1. "READ_DATA,Data read after command is executed. If only single bit is accessed (fault_inj status or enable) read_data[0] is the output." group.long 0x8++0x3 line.long 0x0 "WDATA,Write data register" hexmask.long 0x0 0.--31. 1. "WRITE_DATA,Write data for setting/clearing internal RW register groups (fault_inj and enable). The mask bits may be applied to write to selected bits." group.long 0x10++0x3 line.long 0x0 "WMASK,Write mask register" hexmask.long 0x0 0.--31. 1. "WRITE_MASK,Mask bits for accessing individual fault group bits during write operations." rgroup.long 0x14++0x3 line.long 0x0 "CMD_STATUS,Command status register" bitfld.long 0x0 2. "INV_CMD,Invalid command is written in the CMD.COMMAND field" "0: Valid command is issued by the user,1: Invalid command is issued by the user" bitfld.long 0x0 1. "INV_KEY,Invalid key is written in CMD.KEY field" "0: Valid key is used for access,1: Invalid key is used for access" newline bitfld.long 0x0 0. "INV_REG,Invalid address is being accessed" "0: Valid address is provided for internal register..,1: Invalid address is provided for internal.." group.long 0x24++0x3 line.long 0x0 "SUPERKEY_REG,Super key register" hexmask.long.word 0x0 0.--15. 1. "SUPERKEY,Golden key used for validation during write access. Write access only during supervisor mode" rgroup.long 0x30++0x7 line.long 0x0 "HW_CFG,Hardware configuration register" hexmask.long 0x0 0.--31. 1. "HW_CFG_PARAM,Hardware configuration parameter for each IP release. This information is provided for debug purposes. The value of this register is dependent on number of faults." line.long 0x4 "VERSION_REG,Verison register" hexmask.long 0x4 0.--31. 1. "VERSION,Release version of IP. This information is provided for debug purposes. The value is fixed per CEM instance depending on the release number." tree.end tree "CEM_2_CEM_ADDRBLK" base ad:0x71080000 group.long 0x0++0x3 line.long 0x0 "CMD,Command register" hexmask.long.word 0x0 16.--31. 1. "KEY,Key for writing to CEM programmable registers validated against the “super” key" hexmask.long.byte 0x0 11.--15. 1. "COMMAND,Command for accessing the CEM internal register (set/clear enable set/disable fake fault injection read status and so on)" newline hexmask.long.word 0x0 0.--10. 1. "FAULT_OR_GRP_NUM,Fault number/group number of corresponding internal CEM registers for accessing individual error control/status info as well as error group control/status info." rgroup.long 0x4++0x3 line.long 0x0 "RDATA,Read data register" hexmask.long 0x0 0.--31. 1. "READ_DATA,Data read after command is executed. If only single bit is accessed (fault_inj status or enable) read_data[0] is the output." group.long 0x8++0x3 line.long 0x0 "WDATA,Write data register" hexmask.long 0x0 0.--31. 1. "WRITE_DATA,Write data for setting/clearing internal RW register groups (fault_inj and enable). The mask bits may be applied to write to selected bits." group.long 0x10++0x3 line.long 0x0 "WMASK,Write mask register" hexmask.long 0x0 0.--31. 1. "WRITE_MASK,Mask bits for accessing individual fault group bits during write operations." rgroup.long 0x14++0x3 line.long 0x0 "CMD_STATUS,Command status register" bitfld.long 0x0 2. "INV_CMD,Invalid command is written in the CMD.COMMAND field" "0: Valid command is issued by the user,1: Invalid command is issued by the user" bitfld.long 0x0 1. "INV_KEY,Invalid key is written in CMD.KEY field" "0: Valid key is used for access,1: Invalid key is used for access" newline bitfld.long 0x0 0. "INV_REG,Invalid address is being accessed" "0: Valid address is provided for internal register..,1: Invalid address is provided for internal.." group.long 0x24++0x3 line.long 0x0 "SUPERKEY_REG,Super key register" hexmask.long.word 0x0 0.--15. 1. "SUPERKEY,Golden key used for validation during write access. Write access only during supervisor mode" rgroup.long 0x30++0x7 line.long 0x0 "HW_CFG,Hardware configuration register" hexmask.long 0x0 0.--31. 1. "HW_CFG_PARAM,Hardware configuration parameter for each IP release. This information is provided for debug purposes. The value of this register is dependent on number of faults." line.long 0x4 "VERSION_REG,Verison register" hexmask.long 0x4 0.--31. 1. "VERSION,Release version of IP. This information is provided for debug purposes. The value is fixed per CEM instance depending on the release number." tree.end tree "CEM_3_CEM_ADDRBLK" base ad:0x71680000 group.long 0x0++0x3 line.long 0x0 "CMD,Command register" hexmask.long.word 0x0 16.--31. 1. "KEY,Key for writing to CEM programmable registers validated against the “super” key" hexmask.long.byte 0x0 11.--15. 1. "COMMAND,Command for accessing the CEM internal register (set/clear enable set/disable fake fault injection read status and so on)" newline hexmask.long.word 0x0 0.--10. 1. "FAULT_OR_GRP_NUM,Fault number/group number of corresponding internal CEM registers for accessing individual error control/status info as well as error group control/status info." rgroup.long 0x4++0x3 line.long 0x0 "RDATA,Read data register" hexmask.long 0x0 0.--31. 1. "READ_DATA,Data read after command is executed. If only single bit is accessed (fault_inj status or enable) read_data[0] is the output." group.long 0x8++0x3 line.long 0x0 "WDATA,Write data register" hexmask.long 0x0 0.--31. 1. "WRITE_DATA,Write data for setting/clearing internal RW register groups (fault_inj and enable). The mask bits may be applied to write to selected bits." group.long 0x10++0x3 line.long 0x0 "WMASK,Write mask register" hexmask.long 0x0 0.--31. 1. "WRITE_MASK,Mask bits for accessing individual fault group bits during write operations." rgroup.long 0x14++0x3 line.long 0x0 "CMD_STATUS,Command status register" bitfld.long 0x0 2. "INV_CMD,Invalid command is written in the CMD.COMMAND field" "0: Valid command is issued by the user,1: Invalid command is issued by the user" bitfld.long 0x0 1. "INV_KEY,Invalid key is written in CMD.KEY field" "0: Valid key is used for access,1: Invalid key is used for access" newline bitfld.long 0x0 0. "INV_REG,Invalid address is being accessed" "0: Valid address is provided for internal register..,1: Invalid address is provided for internal.." group.long 0x24++0x3 line.long 0x0 "SUPERKEY_REG,Super key register" hexmask.long.word 0x0 0.--15. 1. "SUPERKEY,Golden key used for validation during write access. Write access only during supervisor mode" rgroup.long 0x30++0x7 line.long 0x0 "HW_CFG,Hardware configuration register" hexmask.long 0x0 0.--31. 1. "HW_CFG_PARAM,Hardware configuration parameter for each IP release. This information is provided for debug purposes. The value of this register is dependent on number of faults." line.long 0x4 "VERSION_REG,Verison register" hexmask.long 0x4 0.--31. 1. "VERSION,Release version of IP. This information is provided for debug purposes. The value is fixed per CEM instance depending on the release number." tree.end tree "CEM_4_CEM_ADDRBLK" base ad:0x71084000 group.long 0x0++0x3 line.long 0x0 "CMD,Command register" hexmask.long.word 0x0 16.--31. 1. "KEY,Key for writing to CEM programmable registers validated against the “super” key" hexmask.long.byte 0x0 11.--15. 1. "COMMAND,Command for accessing the CEM internal register (set/clear enable set/disable fake fault injection read status and so on)" newline hexmask.long.word 0x0 0.--10. 1. "FAULT_OR_GRP_NUM,Fault number/group number of corresponding internal CEM registers for accessing individual error control/status info as well as error group control/status info." rgroup.long 0x4++0x3 line.long 0x0 "RDATA,Read data register" hexmask.long 0x0 0.--31. 1. "READ_DATA,Data read after command is executed. If only single bit is accessed (fault_inj status or enable) read_data[0] is the output." group.long 0x8++0x3 line.long 0x0 "WDATA,Write data register" hexmask.long 0x0 0.--31. 1. "WRITE_DATA,Write data for setting/clearing internal RW register groups (fault_inj and enable). The mask bits may be applied to write to selected bits." group.long 0x10++0x3 line.long 0x0 "WMASK,Write mask register" hexmask.long 0x0 0.--31. 1. "WRITE_MASK,Mask bits for accessing individual fault group bits during write operations." rgroup.long 0x14++0x3 line.long 0x0 "CMD_STATUS,Command status register" bitfld.long 0x0 2. "INV_CMD,Invalid command is written in the CMD.COMMAND field" "0: Valid command is issued by the user,1: Invalid command is issued by the user" bitfld.long 0x0 1. "INV_KEY,Invalid key is written in CMD.KEY field" "0: Valid key is used for access,1: Invalid key is used for access" newline bitfld.long 0x0 0. "INV_REG,Invalid address is being accessed" "0: Valid address is provided for internal register..,1: Invalid address is provided for internal.." group.long 0x24++0x3 line.long 0x0 "SUPERKEY_REG,Super key register" hexmask.long.word 0x0 0.--15. 1. "SUPERKEY,Golden key used for validation during write access. Write access only during supervisor mode" rgroup.long 0x30++0x7 line.long 0x0 "HW_CFG,Hardware configuration register" hexmask.long 0x0 0.--31. 1. "HW_CFG_PARAM,Hardware configuration parameter for each IP release. This information is provided for debug purposes. The value of this register is dependent on number of faults." line.long 0x4 "VERSION_REG,Verison register" hexmask.long 0x4 0.--31. 1. "VERSION,Release version of IP. This information is provided for debug purposes. The value is fixed per CEM instance depending on the release number." tree.end tree "CEM_5_CEM_ADDRBLK" base ad:0x71684000 group.long 0x0++0x3 line.long 0x0 "CMD,Command register" hexmask.long.word 0x0 16.--31. 1. "KEY,Key for writing to CEM programmable registers validated against the “super” key" hexmask.long.byte 0x0 11.--15. 1. "COMMAND,Command for accessing the CEM internal register (set/clear enable set/disable fake fault injection read status and so on)" newline hexmask.long.word 0x0 0.--10. 1. "FAULT_OR_GRP_NUM,Fault number/group number of corresponding internal CEM registers for accessing individual error control/status info as well as error group control/status info." rgroup.long 0x4++0x3 line.long 0x0 "RDATA,Read data register" hexmask.long 0x0 0.--31. 1. "READ_DATA,Data read after command is executed. If only single bit is accessed (fault_inj status or enable) read_data[0] is the output." group.long 0x8++0x3 line.long 0x0 "WDATA,Write data register" hexmask.long 0x0 0.--31. 1. "WRITE_DATA,Write data for setting/clearing internal RW register groups (fault_inj and enable). The mask bits may be applied to write to selected bits." group.long 0x10++0x3 line.long 0x0 "WMASK,Write mask register" hexmask.long 0x0 0.--31. 1. "WRITE_MASK,Mask bits for accessing individual fault group bits during write operations." rgroup.long 0x14++0x3 line.long 0x0 "CMD_STATUS,Command status register" bitfld.long 0x0 2. "INV_CMD,Invalid command is written in the CMD.COMMAND field" "0: Valid command is issued by the user,1: Invalid command is issued by the user" bitfld.long 0x0 1. "INV_KEY,Invalid key is written in CMD.KEY field" "0: Valid key is used for access,1: Invalid key is used for access" newline bitfld.long 0x0 0. "INV_REG,Invalid address is being accessed" "0: Valid address is provided for internal register..,1: Invalid address is provided for internal.." group.long 0x24++0x3 line.long 0x0 "SUPERKEY_REG,Super key register" hexmask.long.word 0x0 0.--15. 1. "SUPERKEY,Golden key used for validation during write access. Write access only during supervisor mode" rgroup.long 0x30++0x7 line.long 0x0 "HW_CFG,Hardware configuration register" hexmask.long 0x0 0.--31. 1. "HW_CFG_PARAM,Hardware configuration parameter for each IP release. This information is provided for debug purposes. The value of this register is dependent on number of faults." line.long 0x4 "VERSION_REG,Verison register" hexmask.long 0x4 0.--31. 1. "VERSION,Release version of IP. This information is provided for debug purposes. The value is fixed per CEM instance depending on the release number." tree.end tree "CEM_6_CEM_ADDRBLK" base ad:0x71088000 group.long 0x0++0x3 line.long 0x0 "CMD,Command register" hexmask.long.word 0x0 16.--31. 1. "KEY,Key for writing to CEM programmable registers validated against the “super” key" hexmask.long.byte 0x0 11.--15. 1. "COMMAND,Command for accessing the CEM internal register (set/clear enable set/disable fake fault injection read status and so on)" newline hexmask.long.word 0x0 0.--10. 1. "FAULT_OR_GRP_NUM,Fault number/group number of corresponding internal CEM registers for accessing individual error control/status info as well as error group control/status info." rgroup.long 0x4++0x3 line.long 0x0 "RDATA,Read data register" hexmask.long 0x0 0.--31. 1. "READ_DATA,Data read after command is executed. If only single bit is accessed (fault_inj status or enable) read_data[0] is the output." group.long 0x8++0x3 line.long 0x0 "WDATA,Write data register" hexmask.long 0x0 0.--31. 1. "WRITE_DATA,Write data for setting/clearing internal RW register groups (fault_inj and enable). The mask bits may be applied to write to selected bits." group.long 0x10++0x3 line.long 0x0 "WMASK,Write mask register" hexmask.long 0x0 0.--31. 1. "WRITE_MASK,Mask bits for accessing individual fault group bits during write operations." rgroup.long 0x14++0x3 line.long 0x0 "CMD_STATUS,Command status register" bitfld.long 0x0 2. "INV_CMD,Invalid command is written in the CMD.COMMAND field" "0: Valid command is issued by the user,1: Invalid command is issued by the user" bitfld.long 0x0 1. "INV_KEY,Invalid key is written in CMD.KEY field" "0: Valid key is used for access,1: Invalid key is used for access" newline bitfld.long 0x0 0. "INV_REG,Invalid address is being accessed" "0: Valid address is provided for internal register..,1: Invalid address is provided for internal.." group.long 0x24++0x3 line.long 0x0 "SUPERKEY_REG,Super key register" hexmask.long.word 0x0 0.--15. 1. "SUPERKEY,Golden key used for validation during write access. Write access only during supervisor mode" rgroup.long 0x30++0x7 line.long 0x0 "HW_CFG,Hardware configuration register" hexmask.long 0x0 0.--31. 1. "HW_CFG_PARAM,Hardware configuration parameter for each IP release. This information is provided for debug purposes. The value of this register is dependent on number of faults." line.long 0x4 "VERSION_REG,Verison register" hexmask.long 0x4 0.--31. 1. "VERSION,Release version of IP. This information is provided for debug purposes. The value is fixed per CEM instance depending on the release number." tree.end tree "CEM_7_CEM_ADDRBLK" base ad:0x71688000 group.long 0x0++0x3 line.long 0x0 "CMD,Command register" hexmask.long.word 0x0 16.--31. 1. "KEY,Key for writing to CEM programmable registers validated against the “super” key" hexmask.long.byte 0x0 11.--15. 1. "COMMAND,Command for accessing the CEM internal register (set/clear enable set/disable fake fault injection read status and so on)" newline hexmask.long.word 0x0 0.--10. 1. "FAULT_OR_GRP_NUM,Fault number/group number of corresponding internal CEM registers for accessing individual error control/status info as well as error group control/status info." rgroup.long 0x4++0x3 line.long 0x0 "RDATA,Read data register" hexmask.long 0x0 0.--31. 1. "READ_DATA,Data read after command is executed. If only single bit is accessed (fault_inj status or enable) read_data[0] is the output." group.long 0x8++0x3 line.long 0x0 "WDATA,Write data register" hexmask.long 0x0 0.--31. 1. "WRITE_DATA,Write data for setting/clearing internal RW register groups (fault_inj and enable). The mask bits may be applied to write to selected bits." group.long 0x10++0x3 line.long 0x0 "WMASK,Write mask register" hexmask.long 0x0 0.--31. 1. "WRITE_MASK,Mask bits for accessing individual fault group bits during write operations." rgroup.long 0x14++0x3 line.long 0x0 "CMD_STATUS,Command status register" bitfld.long 0x0 2. "INV_CMD,Invalid command is written in the CMD.COMMAND field" "0: Valid command is issued by the user,1: Invalid command is issued by the user" bitfld.long 0x0 1. "INV_KEY,Invalid key is written in CMD.KEY field" "0: Valid key is used for access,1: Invalid key is used for access" newline bitfld.long 0x0 0. "INV_REG,Invalid address is being accessed" "0: Valid address is provided for internal register..,1: Invalid address is provided for internal.." group.long 0x24++0x3 line.long 0x0 "SUPERKEY_REG,Super key register" hexmask.long.word 0x0 0.--15. 1. "SUPERKEY,Golden key used for validation during write access. Write access only during supervisor mode" rgroup.long 0x30++0x7 line.long 0x0 "HW_CFG,Hardware configuration register" hexmask.long 0x0 0.--31. 1. "HW_CFG_PARAM,Hardware configuration parameter for each IP release. This information is provided for debug purposes. The value of this register is dependent on number of faults." line.long 0x4 "VERSION_REG,Verison register" hexmask.long 0x4 0.--31. 1. "VERSION,Release version of IP. This information is provided for debug purposes. The value is fixed per CEM instance depending on the release number." tree.end tree "CEM_8_CEM_ADDRBLK" base ad:0x7108C000 group.long 0x0++0x3 line.long 0x0 "CMD,Command register" hexmask.long.word 0x0 16.--31. 1. "KEY,Key for writing to CEM programmable registers validated against the “super” key" hexmask.long.byte 0x0 11.--15. 1. "COMMAND,Command for accessing the CEM internal register (set/clear enable set/disable fake fault injection read status and so on)" newline hexmask.long.word 0x0 0.--10. 1. "FAULT_OR_GRP_NUM,Fault number/group number of corresponding internal CEM registers for accessing individual error control/status info as well as error group control/status info." rgroup.long 0x4++0x3 line.long 0x0 "RDATA,Read data register" hexmask.long 0x0 0.--31. 1. "READ_DATA,Data read after command is executed. If only single bit is accessed (fault_inj status or enable) read_data[0] is the output." group.long 0x8++0x3 line.long 0x0 "WDATA,Write data register" hexmask.long 0x0 0.--31. 1. "WRITE_DATA,Write data for setting/clearing internal RW register groups (fault_inj and enable). The mask bits may be applied to write to selected bits." group.long 0x10++0x3 line.long 0x0 "WMASK,Write mask register" hexmask.long 0x0 0.--31. 1. "WRITE_MASK,Mask bits for accessing individual fault group bits during write operations." rgroup.long 0x14++0x3 line.long 0x0 "CMD_STATUS,Command status register" bitfld.long 0x0 2. "INV_CMD,Invalid command is written in the CMD.COMMAND field" "0: Valid command is issued by the user,1: Invalid command is issued by the user" bitfld.long 0x0 1. "INV_KEY,Invalid key is written in CMD.KEY field" "0: Valid key is used for access,1: Invalid key is used for access" newline bitfld.long 0x0 0. "INV_REG,Invalid address is being accessed" "0: Valid address is provided for internal register..,1: Invalid address is provided for internal.." group.long 0x24++0x3 line.long 0x0 "SUPERKEY_REG,Super key register" hexmask.long.word 0x0 0.--15. 1. "SUPERKEY,Golden key used for validation during write access. Write access only during supervisor mode" rgroup.long 0x30++0x7 line.long 0x0 "HW_CFG,Hardware configuration register" hexmask.long 0x0 0.--31. 1. "HW_CFG_PARAM,Hardware configuration parameter for each IP release. This information is provided for debug purposes. The value of this register is dependent on number of faults." line.long 0x4 "VERSION_REG,Verison register" hexmask.long 0x4 0.--31. 1. "VERSION,Release version of IP. This information is provided for debug purposes. The value is fixed per CEM instance depending on the release number." tree.end tree "CEM_9_CEM_ADDRBLK" base ad:0x7168C000 group.long 0x0++0x3 line.long 0x0 "CMD,Command register" hexmask.long.word 0x0 16.--31. 1. "KEY,Key for writing to CEM programmable registers validated against the “super” key" hexmask.long.byte 0x0 11.--15. 1. "COMMAND,Command for accessing the CEM internal register (set/clear enable set/disable fake fault injection read status and so on)" newline hexmask.long.word 0x0 0.--10. 1. "FAULT_OR_GRP_NUM,Fault number/group number of corresponding internal CEM registers for accessing individual error control/status info as well as error group control/status info." rgroup.long 0x4++0x3 line.long 0x0 "RDATA,Read data register" hexmask.long 0x0 0.--31. 1. "READ_DATA,Data read after command is executed. If only single bit is accessed (fault_inj status or enable) read_data[0] is the output." group.long 0x8++0x3 line.long 0x0 "WDATA,Write data register" hexmask.long 0x0 0.--31. 1. "WRITE_DATA,Write data for setting/clearing internal RW register groups (fault_inj and enable). The mask bits may be applied to write to selected bits." group.long 0x10++0x3 line.long 0x0 "WMASK,Write mask register" hexmask.long 0x0 0.--31. 1. "WRITE_MASK,Mask bits for accessing individual fault group bits during write operations." rgroup.long 0x14++0x3 line.long 0x0 "CMD_STATUS,Command status register" bitfld.long 0x0 2. "INV_CMD,Invalid command is written in the CMD.COMMAND field" "0: Valid command is issued by the user,1: Invalid command is issued by the user" bitfld.long 0x0 1. "INV_KEY,Invalid key is written in CMD.KEY field" "0: Valid key is used for access,1: Invalid key is used for access" newline bitfld.long 0x0 0. "INV_REG,Invalid address is being accessed" "0: Valid address is provided for internal register..,1: Invalid address is provided for internal.." group.long 0x24++0x3 line.long 0x0 "SUPERKEY_REG,Super key register" hexmask.long.word 0x0 0.--15. 1. "SUPERKEY,Golden key used for validation during write access. Write access only during supervisor mode" rgroup.long 0x30++0x7 line.long 0x0 "HW_CFG,Hardware configuration register" hexmask.long 0x0 0.--31. 1. "HW_CFG_PARAM,Hardware configuration parameter for each IP release. This information is provided for debug purposes. The value of this register is dependent on number of faults." line.long 0x4 "VERSION_REG,Verison register" hexmask.long 0x4 0.--31. 1. "VERSION,Release version of IP. This information is provided for debug purposes. The value is fixed per CEM instance depending on the release number." tree.end tree "CEM_10_CEM_ADDRBLK" base ad:0x71090000 group.long 0x0++0x3 line.long 0x0 "CMD,Command register" hexmask.long.word 0x0 16.--31. 1. "KEY,Key for writing to CEM programmable registers validated against the “super” key" hexmask.long.byte 0x0 11.--15. 1. "COMMAND,Command for accessing the CEM internal register (set/clear enable set/disable fake fault injection read status and so on)" newline hexmask.long.word 0x0 0.--10. 1. "FAULT_OR_GRP_NUM,Fault number/group number of corresponding internal CEM registers for accessing individual error control/status info as well as error group control/status info." rgroup.long 0x4++0x3 line.long 0x0 "RDATA,Read data register" hexmask.long 0x0 0.--31. 1. "READ_DATA,Data read after command is executed. If only single bit is accessed (fault_inj status or enable) read_data[0] is the output." group.long 0x8++0x3 line.long 0x0 "WDATA,Write data register" hexmask.long 0x0 0.--31. 1. "WRITE_DATA,Write data for setting/clearing internal RW register groups (fault_inj and enable). The mask bits may be applied to write to selected bits." group.long 0x10++0x3 line.long 0x0 "WMASK,Write mask register" hexmask.long 0x0 0.--31. 1. "WRITE_MASK,Mask bits for accessing individual fault group bits during write operations." rgroup.long 0x14++0x3 line.long 0x0 "CMD_STATUS,Command status register" bitfld.long 0x0 2. "INV_CMD,Invalid command is written in the CMD.COMMAND field" "0: Valid command is issued by the user,1: Invalid command is issued by the user" bitfld.long 0x0 1. "INV_KEY,Invalid key is written in CMD.KEY field" "0: Valid key is used for access,1: Invalid key is used for access" newline bitfld.long 0x0 0. "INV_REG,Invalid address is being accessed" "0: Valid address is provided for internal register..,1: Invalid address is provided for internal.." group.long 0x24++0x3 line.long 0x0 "SUPERKEY_REG,Super key register" hexmask.long.word 0x0 0.--15. 1. "SUPERKEY,Golden key used for validation during write access. Write access only during supervisor mode" rgroup.long 0x30++0x7 line.long 0x0 "HW_CFG,Hardware configuration register" hexmask.long 0x0 0.--31. 1. "HW_CFG_PARAM,Hardware configuration parameter for each IP release. This information is provided for debug purposes. The value of this register is dependent on number of faults." line.long 0x4 "VERSION_REG,Verison register" hexmask.long 0x4 0.--31. 1. "VERSION,Release version of IP. This information is provided for debug purposes. The value is fixed per CEM instance depending on the release number." tree.end tree "CEM_11_CEM_ADDRBLK" base ad:0x72280000 group.long 0x0++0x3 line.long 0x0 "CMD,Command register" hexmask.long.word 0x0 16.--31. 1. "KEY,Key for writing to CEM programmable registers validated against the “super” key" hexmask.long.byte 0x0 11.--15. 1. "COMMAND,Command for accessing the CEM internal register (set/clear enable set/disable fake fault injection read status and so on)" newline hexmask.long.word 0x0 0.--10. 1. "FAULT_OR_GRP_NUM,Fault number/group number of corresponding internal CEM registers for accessing individual error control/status info as well as error group control/status info." rgroup.long 0x4++0x3 line.long 0x0 "RDATA,Read data register" hexmask.long 0x0 0.--31. 1. "READ_DATA,Data read after command is executed. If only single bit is accessed (fault_inj status or enable) read_data[0] is the output." group.long 0x8++0x3 line.long 0x0 "WDATA,Write data register" hexmask.long 0x0 0.--31. 1. "WRITE_DATA,Write data for setting/clearing internal RW register groups (fault_inj and enable). The mask bits may be applied to write to selected bits." group.long 0x10++0x3 line.long 0x0 "WMASK,Write mask register" hexmask.long 0x0 0.--31. 1. "WRITE_MASK,Mask bits for accessing individual fault group bits during write operations." rgroup.long 0x14++0x3 line.long 0x0 "CMD_STATUS,Command status register" bitfld.long 0x0 2. "INV_CMD,Invalid command is written in the CMD.COMMAND field" "0: Valid command is issued by the user,1: Invalid command is issued by the user" bitfld.long 0x0 1. "INV_KEY,Invalid key is written in CMD.KEY field" "0: Valid key is used for access,1: Invalid key is used for access" newline bitfld.long 0x0 0. "INV_REG,Invalid address is being accessed" "0: Valid address is provided for internal register..,1: Invalid address is provided for internal.." group.long 0x24++0x3 line.long 0x0 "SUPERKEY_REG,Super key register" hexmask.long.word 0x0 0.--15. 1. "SUPERKEY,Golden key used for validation during write access. Write access only during supervisor mode" rgroup.long 0x30++0x7 line.long 0x0 "HW_CFG,Hardware configuration register" hexmask.long 0x0 0.--31. 1. "HW_CFG_PARAM,Hardware configuration parameter for each IP release. This information is provided for debug purposes. The value of this register is dependent on number of faults." line.long 0x4 "VERSION_REG,Verison register" hexmask.long 0x4 0.--31. 1. "VERSION,Release version of IP. This information is provided for debug purposes. The value is fixed per CEM instance depending on the release number." tree.end tree.end tree "CLUSTER_SWT (Cortex-R52 Local Peripherals - SWT)" base ad:0x0 tree "CLUSTER_0" tree "CLUSTER_0_CORE_0_SWT_0" base ad:0x6C218000 group.long 0x0++0xF line.long 0x0 "CR,SWT Control Register" bitfld.long 0x0 31. "MAP0,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 30. "MAP1,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 29. "MAP2,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 28. "MAP3,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 27. "MAP4,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 26. "MAP5,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 25. "MAP6,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 24. "MAP7,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 9.--10. "SMD,SMD" "0: Fixed Service Sequence the watchdog is serviced..,1: Keyed Service Sequence the watchdog is serviced..,2: Reserved-do not use. Writing this value can..,3: Incremental Address Execution the watchdog is.." bitfld.long 0x0 8. "RIA,RIA" "0: Invalid access to the SWT generates a bus error,1: Invalid access to the SWT causes a system reset.." newline bitfld.long 0x0 7. "WND,WND" "0: Regular mode service sequence can be done at any..,1: Windowed mode the service sequence is only valid.." bitfld.long 0x0 6. "ITR,ITR" "0: Generate a reset on a time-out,1: Generate an interrupt on an initial time-out.." newline bitfld.long 0x0 5. "HLK,This bit is only cleared at reset." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." bitfld.long 0x0 4. "SLK,This bit is cleared by writing the unlock sequence to the service register." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." newline bitfld.long 0x0 3. "CSL,Selects the clock that drives the internal timer." "0: System clock,1: Oscillator clock" bitfld.long 0x0 2. "STP,Allows the watchdog timer to be stopped when the device enters stop mode." "0: SWT counter continues to run in stop mode,1: SWT counter is stopped in stop mode" newline bitfld.long 0x0 1. "FRZ,Allows the watchdog timer to be stopped when the device enters debug mode." "0: SWT counter continues to run in debug mode,1: SWT counter is stopped in debug mode" bitfld.long 0x0 0. "WEN,WEN" "0: SWT is disabled,1: SWT is enabled" line.long 0x4 "IR,SWT Interrupt Register" bitfld.long 0x4 0. "TIF,The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect." "0: No interrupt request.,1: Interrupt request due to an initial time-out." line.long 0x8 "TO,SWT Time-Out Register" hexmask.long 0x8 0.--31. 1. "WTO,An internal 32-bit down counter is loaded with this value when the service sequence is written or when the SWT is enabled." line.long 0xC "WN,SWT Window Register" hexmask.long 0xC 0.--31. 1. "WST,When window mode is enabled the service sequence can only be written when the internal down counter is less than this value." wgroup.long 0x10++0x3 line.long 0x0 "SR,SWT Service Register" hexmask.long.word 0x0 0.--15. 1. "WSC,This field is used to service the watchdog and to clear the soft lock bit (SWT_CR[SLK]). If the SWT_CR[SMD]=01 two pseudorandom key values are written to service the watchdog refer to Section 1.4.1.1: SWT Control Register (SWT_CR) for details." rgroup.long 0x14++0x3 line.long 0x0 "CO,SWT Counter Output Register" hexmask.long 0x0 0.--31. 1. "CNT,When the watchdog is disabled (SWT_CR[WEN]=0) this field shows the value of the internal down counter. When the watchdog is enabled (SWT_CR[WEN]=1) this field is cleared (the value is 0x0000_0000). Values in this field can lag behind the internal.." group.long 0x18++0x3 line.long 0x0 "SK,SWT Service Key Register" hexmask.long.word 0x0 0.--15. 1. "SK,This field is the previous (or initial) service key value used in keyed service mode. If SWT_CR[SMD]=01 the next key value to be written to the SWT_SR is (17*SK+3) mod 2^16." tree.end tree "CLUSTER_0_CORE_0_SWT_1" base ad:0x6C21C000 group.long 0x0++0xF line.long 0x0 "CR,SWT Control Register" bitfld.long 0x0 31. "MAP0,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 30. "MAP1,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 29. "MAP2,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 28. "MAP3,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 27. "MAP4,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 26. "MAP5,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 25. "MAP6,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 24. "MAP7,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 9.--10. "SMD,SMD" "0: Fixed Service Sequence the watchdog is serviced..,1: Keyed Service Sequence the watchdog is serviced..,2: Reserved-do not use. Writing this value can..,3: Reserved-do not use. Writing this value can.." bitfld.long 0x0 8. "RIA,RIA" "0: Invalid access to the SWT generates a bus error,1: Invalid access to the SWT causes a system reset.." newline bitfld.long 0x0 7. "WND,WND" "0: Regular mode service sequence can be done at any..,1: Windowed mode the service sequence is only valid.." bitfld.long 0x0 6. "ITR,ITR" "0: Generate a reset on a time-out,1: Generate an interrupt on an initial time-out.." newline bitfld.long 0x0 5. "HLK,This bit is only cleared at reset." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." bitfld.long 0x0 4. "SLK,This bit is cleared by writing the unlock sequence to the service register." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." newline bitfld.long 0x0 3. "CSL,Selects the clock that drives the internal timer." "0: System clock,1: Oscillator clock" bitfld.long 0x0 2. "STP,Allows the watchdog timer to be stopped when the device enters stop mode." "0: SWT counter continues to run in stop mode,1: SWT counter is stopped in stop mode" newline bitfld.long 0x0 1. "FRZ,Allows the watchdog timer to be stopped when the device enters debug mode." "0: SWT counter continues to run in debug mode,1: SWT counter is stopped in debug mode" bitfld.long 0x0 0. "WEN,WEN" "0: SWT is disabled,1: SWT is enabled" line.long 0x4 "IR,SWT Interrupt Register" bitfld.long 0x4 0. "TIF,The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect." "0: No interrupt request.,1: Interrupt request due to an initial time-out." line.long 0x8 "TO,SWT Time-Out Register" hexmask.long 0x8 0.--31. 1. "WTO,An internal 32-bit down counter is loaded with this value when the service sequence is written or when the SWT is enabled." line.long 0xC "WN,SWT Window Register" hexmask.long 0xC 0.--31. 1. "WST,When window mode is enabled the service sequence can only be written when the internal down counter is less than this value." wgroup.long 0x10++0x3 line.long 0x0 "SR,SWT Service Register" hexmask.long.word 0x0 0.--15. 1. "WSC,This field is used to service the watchdog and to clear the soft lock bit (SWT_CR[SLK]). If the SWT_CR[SMD]=01 two pseudorandom key values are written to service the watchdog refer to Section 1.4.1.1: SWT Control Register (SWT_CR) for details." rgroup.long 0x14++0x3 line.long 0x0 "CO,SWT Counter Output Register" hexmask.long 0x0 0.--31. 1. "CNT,When the watchdog is disabled (SWT_CR[WEN]=0) this field shows the value of the internal down counter. When the watchdog is enabled (SWT_CR[WEN]=1) this field is cleared (the value is 0x0000_0000). Values in this field can lag behind the internal.." group.long 0x18++0x3 line.long 0x0 "SK,SWT Service Key Register" hexmask.long.word 0x0 0.--15. 1. "SK,This field is the previous (or initial) service key value used in keyed service mode. If SWT_CR[SMD]=01 the next key value to be written to the SWT_SR is (17*SK+3) mod 2^16." tree.end tree "CLUSTER_0_CORE_1_SWT_0" base ad:0x6C218000 group.long 0x0++0xF line.long 0x0 "CR,SWT Control Register" bitfld.long 0x0 31. "MAP0,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 30. "MAP1,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 29. "MAP2,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 28. "MAP3,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 27. "MAP4,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 26. "MAP5,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 25. "MAP6,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 24. "MAP7,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 9.--10. "SMD,SMD" "0: Fixed Service Sequence the watchdog is serviced..,1: Keyed Service Sequence the watchdog is serviced..,2: Reserved-do not use. Writing this value can..,3: Incremental Address Execution the watchdog is.." bitfld.long 0x0 8. "RIA,RIA" "0: Invalid access to the SWT generates a bus error,1: Invalid access to the SWT causes a system reset.." newline bitfld.long 0x0 7. "WND,WND" "0: Regular mode service sequence can be done at any..,1: Windowed mode the service sequence is only valid.." bitfld.long 0x0 6. "ITR,ITR" "0: Generate a reset on a time-out,1: Generate an interrupt on an initial time-out.." newline bitfld.long 0x0 5. "HLK,This bit is only cleared at reset." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." bitfld.long 0x0 4. "SLK,This bit is cleared by writing the unlock sequence to the service register." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." newline bitfld.long 0x0 3. "CSL,Selects the clock that drives the internal timer." "0: System clock,1: Oscillator clock" bitfld.long 0x0 2. "STP,Allows the watchdog timer to be stopped when the device enters stop mode." "0: SWT counter continues to run in stop mode,1: SWT counter is stopped in stop mode" newline bitfld.long 0x0 1. "FRZ,Allows the watchdog timer to be stopped when the device enters debug mode." "0: SWT counter continues to run in debug mode,1: SWT counter is stopped in debug mode" bitfld.long 0x0 0. "WEN,WEN" "0: SWT is disabled,1: SWT is enabled" line.long 0x4 "IR,SWT Interrupt Register" bitfld.long 0x4 0. "TIF,The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect." "0: No interrupt request.,1: Interrupt request due to an initial time-out." line.long 0x8 "TO,SWT Time-Out Register" hexmask.long 0x8 0.--31. 1. "WTO,An internal 32-bit down counter is loaded with this value when the service sequence is written or when the SWT is enabled." line.long 0xC "WN,SWT Window Register" hexmask.long 0xC 0.--31. 1. "WST,When window mode is enabled the service sequence can only be written when the internal down counter is less than this value." wgroup.long 0x10++0x3 line.long 0x0 "SR,SWT Service Register" hexmask.long.word 0x0 0.--15. 1. "WSC,This field is used to service the watchdog and to clear the soft lock bit (SWT_CR[SLK]). If the SWT_CR[SMD]=01 two pseudorandom key values are written to service the watchdog refer to Section 1.4.1.1: SWT Control Register (SWT_CR) for details." rgroup.long 0x14++0x3 line.long 0x0 "CO,SWT Counter Output Register" hexmask.long 0x0 0.--31. 1. "CNT,When the watchdog is disabled (SWT_CR[WEN]=0) this field shows the value of the internal down counter. When the watchdog is enabled (SWT_CR[WEN]=1) this field is cleared (the value is 0x0000_0000). Values in this field can lag behind the internal.." group.long 0x18++0x3 line.long 0x0 "SK,SWT Service Key Register" hexmask.long.word 0x0 0.--15. 1. "SK,This field is the previous (or initial) service key value used in keyed service mode. If SWT_CR[SMD]=01 the next key value to be written to the SWT_SR is (17*SK+3) mod 2^16." tree.end tree "CLUSTER_0_CORE_1_SWT_1" base ad:0x6C21C000 group.long 0x0++0xF line.long 0x0 "CR,SWT Control Register" bitfld.long 0x0 31. "MAP0,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 30. "MAP1,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 29. "MAP2,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 28. "MAP3,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 27. "MAP4,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 26. "MAP5,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 25. "MAP6,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 24. "MAP7,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 9.--10. "SMD,SMD" "0: Fixed Service Sequence the watchdog is serviced..,1: Keyed Service Sequence the watchdog is serviced..,2: Reserved-do not use. Writing this value can..,3: Reserved-do not use. Writing this value can.." bitfld.long 0x0 8. "RIA,RIA" "0: Invalid access to the SWT generates a bus error,1: Invalid access to the SWT causes a system reset.." newline bitfld.long 0x0 7. "WND,WND" "0: Regular mode service sequence can be done at any..,1: Windowed mode the service sequence is only valid.." bitfld.long 0x0 6. "ITR,ITR" "0: Generate a reset on a time-out,1: Generate an interrupt on an initial time-out.." newline bitfld.long 0x0 5. "HLK,This bit is only cleared at reset." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." bitfld.long 0x0 4. "SLK,This bit is cleared by writing the unlock sequence to the service register." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." newline bitfld.long 0x0 3. "CSL,Selects the clock that drives the internal timer." "0: System clock,1: Oscillator clock" bitfld.long 0x0 2. "STP,Allows the watchdog timer to be stopped when the device enters stop mode." "0: SWT counter continues to run in stop mode,1: SWT counter is stopped in stop mode" newline bitfld.long 0x0 1. "FRZ,Allows the watchdog timer to be stopped when the device enters debug mode." "0: SWT counter continues to run in debug mode,1: SWT counter is stopped in debug mode" bitfld.long 0x0 0. "WEN,WEN" "0: SWT is disabled,1: SWT is enabled" line.long 0x4 "IR,SWT Interrupt Register" bitfld.long 0x4 0. "TIF,The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect." "0: No interrupt request.,1: Interrupt request due to an initial time-out." line.long 0x8 "TO,SWT Time-Out Register" hexmask.long 0x8 0.--31. 1. "WTO,An internal 32-bit down counter is loaded with this value when the service sequence is written or when the SWT is enabled." line.long 0xC "WN,SWT Window Register" hexmask.long 0xC 0.--31. 1. "WST,When window mode is enabled the service sequence can only be written when the internal down counter is less than this value." wgroup.long 0x10++0x3 line.long 0x0 "SR,SWT Service Register" hexmask.long.word 0x0 0.--15. 1. "WSC,This field is used to service the watchdog and to clear the soft lock bit (SWT_CR[SLK]). If the SWT_CR[SMD]=01 two pseudorandom key values are written to service the watchdog refer to Section 1.4.1.1: SWT Control Register (SWT_CR) for details." rgroup.long 0x14++0x3 line.long 0x0 "CO,SWT Counter Output Register" hexmask.long 0x0 0.--31. 1. "CNT,When the watchdog is disabled (SWT_CR[WEN]=0) this field shows the value of the internal down counter. When the watchdog is enabled (SWT_CR[WEN]=1) this field is cleared (the value is 0x0000_0000). Values in this field can lag behind the internal.." group.long 0x18++0x3 line.long 0x0 "SK,SWT Service Key Register" hexmask.long.word 0x0 0.--15. 1. "SK,This field is the previous (or initial) service key value used in keyed service mode. If SWT_CR[SMD]=01 the next key value to be written to the SWT_SR is (17*SK+3) mod 2^16." tree.end tree.end tree "CLUSTER_1" tree "CLUSTER_1_CORE_0_SWT_0" base ad:0x6C218000 group.long 0x0++0xF line.long 0x0 "CR,SWT Control Register" bitfld.long 0x0 31. "MAP0,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 30. "MAP1,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 29. "MAP2,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 28. "MAP3,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 27. "MAP4,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 26. "MAP5,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 25. "MAP6,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 24. "MAP7,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 9.--10. "SMD,SMD" "0: Fixed Service Sequence the watchdog is serviced..,1: Keyed Service Sequence the watchdog is serviced..,2: Reserved-do not use. Writing this value can..,3: Incremental Address Execution the watchdog is.." bitfld.long 0x0 8. "RIA,RIA" "0: Invalid access to the SWT generates a bus error,1: Invalid access to the SWT causes a system reset.." newline bitfld.long 0x0 7. "WND,WND" "0: Regular mode service sequence can be done at any..,1: Windowed mode the service sequence is only valid.." bitfld.long 0x0 6. "ITR,ITR" "0: Generate a reset on a time-out,1: Generate an interrupt on an initial time-out.." newline bitfld.long 0x0 5. "HLK,This bit is only cleared at reset." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." bitfld.long 0x0 4. "SLK,This bit is cleared by writing the unlock sequence to the service register." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." newline bitfld.long 0x0 3. "CSL,Selects the clock that drives the internal timer." "0: System clock,1: Oscillator clock" bitfld.long 0x0 2. "STP,Allows the watchdog timer to be stopped when the device enters stop mode." "0: SWT counter continues to run in stop mode,1: SWT counter is stopped in stop mode" newline bitfld.long 0x0 1. "FRZ,Allows the watchdog timer to be stopped when the device enters debug mode." "0: SWT counter continues to run in debug mode,1: SWT counter is stopped in debug mode" bitfld.long 0x0 0. "WEN,WEN" "0: SWT is disabled,1: SWT is enabled" line.long 0x4 "IR,SWT Interrupt Register" bitfld.long 0x4 0. "TIF,The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect." "0: No interrupt request.,1: Interrupt request due to an initial time-out." line.long 0x8 "TO,SWT Time-Out Register" hexmask.long 0x8 0.--31. 1. "WTO,An internal 32-bit down counter is loaded with this value when the service sequence is written or when the SWT is enabled." line.long 0xC "WN,SWT Window Register" hexmask.long 0xC 0.--31. 1. "WST,When window mode is enabled the service sequence can only be written when the internal down counter is less than this value." wgroup.long 0x10++0x3 line.long 0x0 "SR,SWT Service Register" hexmask.long.word 0x0 0.--15. 1. "WSC,This field is used to service the watchdog and to clear the soft lock bit (SWT_CR[SLK]). If the SWT_CR[SMD]=01 two pseudorandom key values are written to service the watchdog refer to Section 1.4.1.1: SWT Control Register (SWT_CR) for details." rgroup.long 0x14++0x3 line.long 0x0 "CO,SWT Counter Output Register" hexmask.long 0x0 0.--31. 1. "CNT,When the watchdog is disabled (SWT_CR[WEN]=0) this field shows the value of the internal down counter. When the watchdog is enabled (SWT_CR[WEN]=1) this field is cleared (the value is 0x0000_0000). Values in this field can lag behind the internal.." group.long 0x18++0x3 line.long 0x0 "SK,SWT Service Key Register" hexmask.long.word 0x0 0.--15. 1. "SK,This field is the previous (or initial) service key value used in keyed service mode. If SWT_CR[SMD]=01 the next key value to be written to the SWT_SR is (17*SK+3) mod 2^16." tree.end tree "CLUSTER_1_CORE_0_SWT_1" base ad:0x6C21C000 group.long 0x0++0xF line.long 0x0 "CR,SWT Control Register" bitfld.long 0x0 31. "MAP0,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 30. "MAP1,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 29. "MAP2,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 28. "MAP3,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 27. "MAP4,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 26. "MAP5,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 25. "MAP6,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 24. "MAP7,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 9.--10. "SMD,SMD" "0: Fixed Service Sequence the watchdog is serviced..,1: Keyed Service Sequence the watchdog is serviced..,2: Reserved-do not use. Writing this value can..,3: Reserved-do not use. Writing this value can.." bitfld.long 0x0 8. "RIA,RIA" "0: Invalid access to the SWT generates a bus error,1: Invalid access to the SWT causes a system reset.." newline bitfld.long 0x0 7. "WND,WND" "0: Regular mode service sequence can be done at any..,1: Windowed mode the service sequence is only valid.." bitfld.long 0x0 6. "ITR,ITR" "0: Generate a reset on a time-out,1: Generate an interrupt on an initial time-out.." newline bitfld.long 0x0 5. "HLK,This bit is only cleared at reset." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." bitfld.long 0x0 4. "SLK,This bit is cleared by writing the unlock sequence to the service register." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." newline bitfld.long 0x0 3. "CSL,Selects the clock that drives the internal timer." "0: System clock,1: Oscillator clock" bitfld.long 0x0 2. "STP,Allows the watchdog timer to be stopped when the device enters stop mode." "0: SWT counter continues to run in stop mode,1: SWT counter is stopped in stop mode" newline bitfld.long 0x0 1. "FRZ,Allows the watchdog timer to be stopped when the device enters debug mode." "0: SWT counter continues to run in debug mode,1: SWT counter is stopped in debug mode" bitfld.long 0x0 0. "WEN,WEN" "0: SWT is disabled,1: SWT is enabled" line.long 0x4 "IR,SWT Interrupt Register" bitfld.long 0x4 0. "TIF,The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect." "0: No interrupt request.,1: Interrupt request due to an initial time-out." line.long 0x8 "TO,SWT Time-Out Register" hexmask.long 0x8 0.--31. 1. "WTO,An internal 32-bit down counter is loaded with this value when the service sequence is written or when the SWT is enabled." line.long 0xC "WN,SWT Window Register" hexmask.long 0xC 0.--31. 1. "WST,When window mode is enabled the service sequence can only be written when the internal down counter is less than this value." wgroup.long 0x10++0x3 line.long 0x0 "SR,SWT Service Register" hexmask.long.word 0x0 0.--15. 1. "WSC,This field is used to service the watchdog and to clear the soft lock bit (SWT_CR[SLK]). If the SWT_CR[SMD]=01 two pseudorandom key values are written to service the watchdog refer to Section 1.4.1.1: SWT Control Register (SWT_CR) for details." rgroup.long 0x14++0x3 line.long 0x0 "CO,SWT Counter Output Register" hexmask.long 0x0 0.--31. 1. "CNT,When the watchdog is disabled (SWT_CR[WEN]=0) this field shows the value of the internal down counter. When the watchdog is enabled (SWT_CR[WEN]=1) this field is cleared (the value is 0x0000_0000). Values in this field can lag behind the internal.." group.long 0x18++0x3 line.long 0x0 "SK,SWT Service Key Register" hexmask.long.word 0x0 0.--15. 1. "SK,This field is the previous (or initial) service key value used in keyed service mode. If SWT_CR[SMD]=01 the next key value to be written to the SWT_SR is (17*SK+3) mod 2^16." tree.end tree "CLUSTER_1_CORE_1_SWT_0" base ad:0x6C218000 group.long 0x0++0xF line.long 0x0 "CR,SWT Control Register" bitfld.long 0x0 31. "MAP0,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 30. "MAP1,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 29. "MAP2,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 28. "MAP3,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 27. "MAP4,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 26. "MAP5,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 25. "MAP6,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 24. "MAP7,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 9.--10. "SMD,SMD" "0: Fixed Service Sequence the watchdog is serviced..,1: Keyed Service Sequence the watchdog is serviced..,2: Reserved-do not use. Writing this value can..,3: Incremental Address Execution the watchdog is.." bitfld.long 0x0 8. "RIA,RIA" "0: Invalid access to the SWT generates a bus error,1: Invalid access to the SWT causes a system reset.." newline bitfld.long 0x0 7. "WND,WND" "0: Regular mode service sequence can be done at any..,1: Windowed mode the service sequence is only valid.." bitfld.long 0x0 6. "ITR,ITR" "0: Generate a reset on a time-out,1: Generate an interrupt on an initial time-out.." newline bitfld.long 0x0 5. "HLK,This bit is only cleared at reset." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." bitfld.long 0x0 4. "SLK,This bit is cleared by writing the unlock sequence to the service register." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." newline bitfld.long 0x0 3. "CSL,Selects the clock that drives the internal timer." "0: System clock,1: Oscillator clock" bitfld.long 0x0 2. "STP,Allows the watchdog timer to be stopped when the device enters stop mode." "0: SWT counter continues to run in stop mode,1: SWT counter is stopped in stop mode" newline bitfld.long 0x0 1. "FRZ,Allows the watchdog timer to be stopped when the device enters debug mode." "0: SWT counter continues to run in debug mode,1: SWT counter is stopped in debug mode" bitfld.long 0x0 0. "WEN,WEN" "0: SWT is disabled,1: SWT is enabled" line.long 0x4 "IR,SWT Interrupt Register" bitfld.long 0x4 0. "TIF,The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect." "0: No interrupt request.,1: Interrupt request due to an initial time-out." line.long 0x8 "TO,SWT Time-Out Register" hexmask.long 0x8 0.--31. 1. "WTO,An internal 32-bit down counter is loaded with this value when the service sequence is written or when the SWT is enabled." line.long 0xC "WN,SWT Window Register" hexmask.long 0xC 0.--31. 1. "WST,When window mode is enabled the service sequence can only be written when the internal down counter is less than this value." wgroup.long 0x10++0x3 line.long 0x0 "SR,SWT Service Register" hexmask.long.word 0x0 0.--15. 1. "WSC,This field is used to service the watchdog and to clear the soft lock bit (SWT_CR[SLK]). If the SWT_CR[SMD]=01 two pseudorandom key values are written to service the watchdog refer to Section 1.4.1.1: SWT Control Register (SWT_CR) for details." rgroup.long 0x14++0x3 line.long 0x0 "CO,SWT Counter Output Register" hexmask.long 0x0 0.--31. 1. "CNT,When the watchdog is disabled (SWT_CR[WEN]=0) this field shows the value of the internal down counter. When the watchdog is enabled (SWT_CR[WEN]=1) this field is cleared (the value is 0x0000_0000). Values in this field can lag behind the internal.." group.long 0x18++0x3 line.long 0x0 "SK,SWT Service Key Register" hexmask.long.word 0x0 0.--15. 1. "SK,This field is the previous (or initial) service key value used in keyed service mode. If SWT_CR[SMD]=01 the next key value to be written to the SWT_SR is (17*SK+3) mod 2^16." tree.end tree "CLUSTER_1_CORE_1_SWT_1" base ad:0x6C21C000 group.long 0x0++0xF line.long 0x0 "CR,SWT Control Register" bitfld.long 0x0 31. "MAP0,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 30. "MAP1,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 29. "MAP2,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 28. "MAP3,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 27. "MAP4,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 26. "MAP5,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 25. "MAP6,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 24. "MAP7,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 9.--10. "SMD,SMD" "0: Fixed Service Sequence the watchdog is serviced..,1: Keyed Service Sequence the watchdog is serviced..,2: Reserved-do not use. Writing this value can..,3: Reserved-do not use. Writing this value can.." bitfld.long 0x0 8. "RIA,RIA" "0: Invalid access to the SWT generates a bus error,1: Invalid access to the SWT causes a system reset.." newline bitfld.long 0x0 7. "WND,WND" "0: Regular mode service sequence can be done at any..,1: Windowed mode the service sequence is only valid.." bitfld.long 0x0 6. "ITR,ITR" "0: Generate a reset on a time-out,1: Generate an interrupt on an initial time-out.." newline bitfld.long 0x0 5. "HLK,This bit is only cleared at reset." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." bitfld.long 0x0 4. "SLK,This bit is cleared by writing the unlock sequence to the service register." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." newline bitfld.long 0x0 3. "CSL,Selects the clock that drives the internal timer." "0: System clock,1: Oscillator clock" bitfld.long 0x0 2. "STP,Allows the watchdog timer to be stopped when the device enters stop mode." "0: SWT counter continues to run in stop mode,1: SWT counter is stopped in stop mode" newline bitfld.long 0x0 1. "FRZ,Allows the watchdog timer to be stopped when the device enters debug mode." "0: SWT counter continues to run in debug mode,1: SWT counter is stopped in debug mode" bitfld.long 0x0 0. "WEN,WEN" "0: SWT is disabled,1: SWT is enabled" line.long 0x4 "IR,SWT Interrupt Register" bitfld.long 0x4 0. "TIF,The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect." "0: No interrupt request.,1: Interrupt request due to an initial time-out." line.long 0x8 "TO,SWT Time-Out Register" hexmask.long 0x8 0.--31. 1. "WTO,An internal 32-bit down counter is loaded with this value when the service sequence is written or when the SWT is enabled." line.long 0xC "WN,SWT Window Register" hexmask.long 0xC 0.--31. 1. "WST,When window mode is enabled the service sequence can only be written when the internal down counter is less than this value." wgroup.long 0x10++0x3 line.long 0x0 "SR,SWT Service Register" hexmask.long.word 0x0 0.--15. 1. "WSC,This field is used to service the watchdog and to clear the soft lock bit (SWT_CR[SLK]). If the SWT_CR[SMD]=01 two pseudorandom key values are written to service the watchdog refer to Section 1.4.1.1: SWT Control Register (SWT_CR) for details." rgroup.long 0x14++0x3 line.long 0x0 "CO,SWT Counter Output Register" hexmask.long 0x0 0.--31. 1. "CNT,When the watchdog is disabled (SWT_CR[WEN]=0) this field shows the value of the internal down counter. When the watchdog is enabled (SWT_CR[WEN]=1) this field is cleared (the value is 0x0000_0000). Values in this field can lag behind the internal.." group.long 0x18++0x3 line.long 0x0 "SK,SWT Service Key Register" hexmask.long.word 0x0 0.--15. 1. "SK,This field is the previous (or initial) service key value used in keyed service mode. If SWT_CR[SMD]=01 the next key value to be written to the SWT_SR is (17*SK+3) mod 2^16." tree.end tree.end tree "CLUSTER_2" tree "CLUSTER_2_CORE_0_SWT_0" base ad:0x6C218000 group.long 0x0++0xF line.long 0x0 "CR,SWT Control Register" bitfld.long 0x0 31. "MAP0,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 30. "MAP1,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 29. "MAP2,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 28. "MAP3,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 27. "MAP4,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 26. "MAP5,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 25. "MAP6,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 24. "MAP7,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 9.--10. "SMD,SMD" "0: Fixed Service Sequence the watchdog is serviced..,1: Keyed Service Sequence the watchdog is serviced..,2: Reserved-do not use. Writing this value can..,3: Incremental Address Execution the watchdog is.." bitfld.long 0x0 8. "RIA,RIA" "0: Invalid access to the SWT generates a bus error,1: Invalid access to the SWT causes a system reset.." newline bitfld.long 0x0 7. "WND,WND" "0: Regular mode service sequence can be done at any..,1: Windowed mode the service sequence is only valid.." bitfld.long 0x0 6. "ITR,ITR" "0: Generate a reset on a time-out,1: Generate an interrupt on an initial time-out.." newline bitfld.long 0x0 5. "HLK,This bit is only cleared at reset." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." bitfld.long 0x0 4. "SLK,This bit is cleared by writing the unlock sequence to the service register." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." newline bitfld.long 0x0 3. "CSL,Selects the clock that drives the internal timer." "0: System clock,1: Oscillator clock" bitfld.long 0x0 2. "STP,Allows the watchdog timer to be stopped when the device enters stop mode." "0: SWT counter continues to run in stop mode,1: SWT counter is stopped in stop mode" newline bitfld.long 0x0 1. "FRZ,Allows the watchdog timer to be stopped when the device enters debug mode." "0: SWT counter continues to run in debug mode,1: SWT counter is stopped in debug mode" bitfld.long 0x0 0. "WEN,WEN" "0: SWT is disabled,1: SWT is enabled" line.long 0x4 "IR,SWT Interrupt Register" bitfld.long 0x4 0. "TIF,The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect." "0: No interrupt request.,1: Interrupt request due to an initial time-out." line.long 0x8 "TO,SWT Time-Out Register" hexmask.long 0x8 0.--31. 1. "WTO,An internal 32-bit down counter is loaded with this value when the service sequence is written or when the SWT is enabled." line.long 0xC "WN,SWT Window Register" hexmask.long 0xC 0.--31. 1. "WST,When window mode is enabled the service sequence can only be written when the internal down counter is less than this value." wgroup.long 0x10++0x3 line.long 0x0 "SR,SWT Service Register" hexmask.long.word 0x0 0.--15. 1. "WSC,This field is used to service the watchdog and to clear the soft lock bit (SWT_CR[SLK]). If the SWT_CR[SMD]=01 two pseudorandom key values are written to service the watchdog refer to Section 1.4.1.1: SWT Control Register (SWT_CR) for details." rgroup.long 0x14++0x3 line.long 0x0 "CO,SWT Counter Output Register" hexmask.long 0x0 0.--31. 1. "CNT,When the watchdog is disabled (SWT_CR[WEN]=0) this field shows the value of the internal down counter. When the watchdog is enabled (SWT_CR[WEN]=1) this field is cleared (the value is 0x0000_0000). Values in this field can lag behind the internal.." group.long 0x18++0x3 line.long 0x0 "SK,SWT Service Key Register" hexmask.long.word 0x0 0.--15. 1. "SK,This field is the previous (or initial) service key value used in keyed service mode. If SWT_CR[SMD]=01 the next key value to be written to the SWT_SR is (17*SK+3) mod 2^16." tree.end tree "CLUSTER_2_CORE_0_SWT_1" base ad:0x6C21C000 group.long 0x0++0xF line.long 0x0 "CR,SWT Control Register" bitfld.long 0x0 31. "MAP0,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 30. "MAP1,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 29. "MAP2,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 28. "MAP3,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 27. "MAP4,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 26. "MAP5,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 25. "MAP6,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 24. "MAP7,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 9.--10. "SMD,SMD" "0: Fixed Service Sequence the watchdog is serviced..,1: Keyed Service Sequence the watchdog is serviced..,2: Reserved-do not use. Writing this value can..,3: Reserved-do not use. Writing this value can.." bitfld.long 0x0 8. "RIA,RIA" "0: Invalid access to the SWT generates a bus error,1: Invalid access to the SWT causes a system reset.." newline bitfld.long 0x0 7. "WND,WND" "0: Regular mode service sequence can be done at any..,1: Windowed mode the service sequence is only valid.." bitfld.long 0x0 6. "ITR,ITR" "0: Generate a reset on a time-out,1: Generate an interrupt on an initial time-out.." newline bitfld.long 0x0 5. "HLK,This bit is only cleared at reset." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." bitfld.long 0x0 4. "SLK,This bit is cleared by writing the unlock sequence to the service register." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." newline bitfld.long 0x0 3. "CSL,Selects the clock that drives the internal timer." "0: System clock,1: Oscillator clock" bitfld.long 0x0 2. "STP,Allows the watchdog timer to be stopped when the device enters stop mode." "0: SWT counter continues to run in stop mode,1: SWT counter is stopped in stop mode" newline bitfld.long 0x0 1. "FRZ,Allows the watchdog timer to be stopped when the device enters debug mode." "0: SWT counter continues to run in debug mode,1: SWT counter is stopped in debug mode" bitfld.long 0x0 0. "WEN,WEN" "0: SWT is disabled,1: SWT is enabled" line.long 0x4 "IR,SWT Interrupt Register" bitfld.long 0x4 0. "TIF,The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect." "0: No interrupt request.,1: Interrupt request due to an initial time-out." line.long 0x8 "TO,SWT Time-Out Register" hexmask.long 0x8 0.--31. 1. "WTO,An internal 32-bit down counter is loaded with this value when the service sequence is written or when the SWT is enabled." line.long 0xC "WN,SWT Window Register" hexmask.long 0xC 0.--31. 1. "WST,When window mode is enabled the service sequence can only be written when the internal down counter is less than this value." wgroup.long 0x10++0x3 line.long 0x0 "SR,SWT Service Register" hexmask.long.word 0x0 0.--15. 1. "WSC,This field is used to service the watchdog and to clear the soft lock bit (SWT_CR[SLK]). If the SWT_CR[SMD]=01 two pseudorandom key values are written to service the watchdog refer to Section 1.4.1.1: SWT Control Register (SWT_CR) for details." rgroup.long 0x14++0x3 line.long 0x0 "CO,SWT Counter Output Register" hexmask.long 0x0 0.--31. 1. "CNT,When the watchdog is disabled (SWT_CR[WEN]=0) this field shows the value of the internal down counter. When the watchdog is enabled (SWT_CR[WEN]=1) this field is cleared (the value is 0x0000_0000). Values in this field can lag behind the internal.." group.long 0x18++0x3 line.long 0x0 "SK,SWT Service Key Register" hexmask.long.word 0x0 0.--15. 1. "SK,This field is the previous (or initial) service key value used in keyed service mode. If SWT_CR[SMD]=01 the next key value to be written to the SWT_SR is (17*SK+3) mod 2^16." tree.end tree "CLUSTER_2_CORE_1_SWT_0" base ad:0x6C218000 group.long 0x0++0xF line.long 0x0 "CR,SWT Control Register" bitfld.long 0x0 31. "MAP0,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 30. "MAP1,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 29. "MAP2,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 28. "MAP3,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 27. "MAP4,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 26. "MAP5,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 25. "MAP6,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 24. "MAP7,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 9.--10. "SMD,SMD" "0: Fixed Service Sequence the watchdog is serviced..,1: Keyed Service Sequence the watchdog is serviced..,2: Reserved-do not use. Writing this value can..,3: Incremental Address Execution the watchdog is.." bitfld.long 0x0 8. "RIA,RIA" "0: Invalid access to the SWT generates a bus error,1: Invalid access to the SWT causes a system reset.." newline bitfld.long 0x0 7. "WND,WND" "0: Regular mode service sequence can be done at any..,1: Windowed mode the service sequence is only valid.." bitfld.long 0x0 6. "ITR,ITR" "0: Generate a reset on a time-out,1: Generate an interrupt on an initial time-out.." newline bitfld.long 0x0 5. "HLK,This bit is only cleared at reset." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." bitfld.long 0x0 4. "SLK,This bit is cleared by writing the unlock sequence to the service register." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." newline bitfld.long 0x0 3. "CSL,Selects the clock that drives the internal timer." "0: System clock,1: Oscillator clock" bitfld.long 0x0 2. "STP,Allows the watchdog timer to be stopped when the device enters stop mode." "0: SWT counter continues to run in stop mode,1: SWT counter is stopped in stop mode" newline bitfld.long 0x0 1. "FRZ,Allows the watchdog timer to be stopped when the device enters debug mode." "0: SWT counter continues to run in debug mode,1: SWT counter is stopped in debug mode" bitfld.long 0x0 0. "WEN,WEN" "0: SWT is disabled,1: SWT is enabled" line.long 0x4 "IR,SWT Interrupt Register" bitfld.long 0x4 0. "TIF,The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect." "0: No interrupt request.,1: Interrupt request due to an initial time-out." line.long 0x8 "TO,SWT Time-Out Register" hexmask.long 0x8 0.--31. 1. "WTO,An internal 32-bit down counter is loaded with this value when the service sequence is written or when the SWT is enabled." line.long 0xC "WN,SWT Window Register" hexmask.long 0xC 0.--31. 1. "WST,When window mode is enabled the service sequence can only be written when the internal down counter is less than this value." wgroup.long 0x10++0x3 line.long 0x0 "SR,SWT Service Register" hexmask.long.word 0x0 0.--15. 1. "WSC,This field is used to service the watchdog and to clear the soft lock bit (SWT_CR[SLK]). If the SWT_CR[SMD]=01 two pseudorandom key values are written to service the watchdog refer to Section 1.4.1.1: SWT Control Register (SWT_CR) for details." rgroup.long 0x14++0x3 line.long 0x0 "CO,SWT Counter Output Register" hexmask.long 0x0 0.--31. 1. "CNT,When the watchdog is disabled (SWT_CR[WEN]=0) this field shows the value of the internal down counter. When the watchdog is enabled (SWT_CR[WEN]=1) this field is cleared (the value is 0x0000_0000). Values in this field can lag behind the internal.." group.long 0x18++0x3 line.long 0x0 "SK,SWT Service Key Register" hexmask.long.word 0x0 0.--15. 1. "SK,This field is the previous (or initial) service key value used in keyed service mode. If SWT_CR[SMD]=01 the next key value to be written to the SWT_SR is (17*SK+3) mod 2^16." tree.end tree "CLUSTER_2_CORE_1_SWT_1" base ad:0x6C21C000 group.long 0x0++0xF line.long 0x0 "CR,SWT Control Register" bitfld.long 0x0 31. "MAP0,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 30. "MAP1,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 29. "MAP2,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 28. "MAP3,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 27. "MAP4,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 26. "MAP5,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 25. "MAP6,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 24. "MAP7,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 9.--10. "SMD,SMD" "0: Fixed Service Sequence the watchdog is serviced..,1: Keyed Service Sequence the watchdog is serviced..,2: Reserved-do not use. Writing this value can..,3: Reserved-do not use. Writing this value can.." bitfld.long 0x0 8. "RIA,RIA" "0: Invalid access to the SWT generates a bus error,1: Invalid access to the SWT causes a system reset.." newline bitfld.long 0x0 7. "WND,WND" "0: Regular mode service sequence can be done at any..,1: Windowed mode the service sequence is only valid.." bitfld.long 0x0 6. "ITR,ITR" "0: Generate a reset on a time-out,1: Generate an interrupt on an initial time-out.." newline bitfld.long 0x0 5. "HLK,This bit is only cleared at reset." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." bitfld.long 0x0 4. "SLK,This bit is cleared by writing the unlock sequence to the service register." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." newline bitfld.long 0x0 3. "CSL,Selects the clock that drives the internal timer." "0: System clock,1: Oscillator clock" bitfld.long 0x0 2. "STP,Allows the watchdog timer to be stopped when the device enters stop mode." "0: SWT counter continues to run in stop mode,1: SWT counter is stopped in stop mode" newline bitfld.long 0x0 1. "FRZ,Allows the watchdog timer to be stopped when the device enters debug mode." "0: SWT counter continues to run in debug mode,1: SWT counter is stopped in debug mode" bitfld.long 0x0 0. "WEN,WEN" "0: SWT is disabled,1: SWT is enabled" line.long 0x4 "IR,SWT Interrupt Register" bitfld.long 0x4 0. "TIF,The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect." "0: No interrupt request.,1: Interrupt request due to an initial time-out." line.long 0x8 "TO,SWT Time-Out Register" hexmask.long 0x8 0.--31. 1. "WTO,An internal 32-bit down counter is loaded with this value when the service sequence is written or when the SWT is enabled." line.long 0xC "WN,SWT Window Register" hexmask.long 0xC 0.--31. 1. "WST,When window mode is enabled the service sequence can only be written when the internal down counter is less than this value." wgroup.long 0x10++0x3 line.long 0x0 "SR,SWT Service Register" hexmask.long.word 0x0 0.--15. 1. "WSC,This field is used to service the watchdog and to clear the soft lock bit (SWT_CR[SLK]). If the SWT_CR[SMD]=01 two pseudorandom key values are written to service the watchdog refer to Section 1.4.1.1: SWT Control Register (SWT_CR) for details." rgroup.long 0x14++0x3 line.long 0x0 "CO,SWT Counter Output Register" hexmask.long 0x0 0.--31. 1. "CNT,When the watchdog is disabled (SWT_CR[WEN]=0) this field shows the value of the internal down counter. When the watchdog is enabled (SWT_CR[WEN]=1) this field is cleared (the value is 0x0000_0000). Values in this field can lag behind the internal.." group.long 0x18++0x3 line.long 0x0 "SK,SWT Service Key Register" hexmask.long.word 0x0 0.--15. 1. "SK,This field is the previous (or initial) service key value used in keyed service mode. If SWT_CR[SMD]=01 the next key value to be written to the SWT_SR is (17*SK+3) mod 2^16." tree.end tree.end tree.end tree "CMU (Clock Monitor Unit)" base ad:0x0 tree "CMU_0" base ad:0x716C0200 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_1" base ad:0x710C0240 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_2" base ad:0x710C0280 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_3" base ad:0x710C02C0 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_4" base ad:0x710C0300 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_5" base ad:0x710C0340 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_6" base ad:0x710C0380 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" bitfld.long 0x0 31. "TREN,frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x0 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x0 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x0 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x0 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x0 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x0 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value 0" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" bitfld.long 0x4 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x4 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 26. "STOP,Frequency limit monitor during STOP mode" "?,1: Enabled" bitfld.long 0x4 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x4 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x4 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value 0" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 5. "FHHI_1,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 4. "FLLI_1,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0xB line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" line.long 0x4 "HFREFR_1,CMU High Frequency Reference Register CLKMN1" bitfld.long 0x4 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x4 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x4 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x4 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x4 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "HFREF_1,High Frequency reference value 1" line.long 0x8 "LFREFR_1,CMU Low Frequency Reference Register CLKMN1" bitfld.long 0x8 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x8 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x8 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x8 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x8 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x8 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x8 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x8 0.--11. 1. "LFREF_1,Low Frequency reference value 1" tree.end tree "CMU_7" base ad:0x710C03C0 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" bitfld.long 0x0 31. "TREN,frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x0 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x0 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x0 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x0 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x0 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x0 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value 0" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" bitfld.long 0x4 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x4 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 26. "STOP,Frequency limit monitor during STOP mode" "?,1: Enabled" bitfld.long 0x4 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x4 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x4 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value 0" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 5. "FHHI_1,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 4. "FLLI_1,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0xB line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" line.long 0x4 "HFREFR_1,CMU High Frequency Reference Register CLKMN1" bitfld.long 0x4 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x4 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x4 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x4 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x4 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "HFREF_1,High Frequency reference value 1" line.long 0x8 "LFREFR_1,CMU Low Frequency Reference Register CLKMN1" bitfld.long 0x8 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x8 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x8 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x8 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x8 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x8 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x8 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x8 0.--11. 1. "LFREF_1,Low Frequency reference value 1" tree.end tree "CMU_8" base ad:0x710C0400 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" bitfld.long 0x0 31. "TREN,frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x0 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x0 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x0 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x0 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x0 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x0 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value 0" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" bitfld.long 0x4 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x4 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 26. "STOP,Frequency limit monitor during STOP mode" "?,1: Enabled" bitfld.long 0x4 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x4 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x4 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value 0" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 5. "FHHI_1,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 4. "FLLI_1,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0xB line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" line.long 0x4 "HFREFR_1,CMU High Frequency Reference Register CLKMN1" bitfld.long 0x4 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x4 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x4 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x4 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x4 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "HFREF_1,High Frequency reference value 1" line.long 0x8 "LFREFR_1,CMU Low Frequency Reference Register CLKMN1" bitfld.long 0x8 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x8 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x8 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x8 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x8 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x8 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x8 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x8 0.--11. 1. "LFREF_1,Low Frequency reference value 1" tree.end tree "CMU_9" base ad:0x710C0440 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" bitfld.long 0x0 31. "TREN,frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x0 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x0 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x0 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x0 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x0 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x0 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value 0" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" bitfld.long 0x4 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x4 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 26. "STOP,Frequency limit monitor during STOP mode" "?,1: Enabled" bitfld.long 0x4 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x4 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x4 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value 0" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 5. "FHHI_1,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 4. "FLLI_1,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0xB line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" line.long 0x4 "HFREFR_1,CMU High Frequency Reference Register CLKMN1" bitfld.long 0x4 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x4 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x4 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x4 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x4 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "HFREF_1,High Frequency reference value 1" line.long 0x8 "LFREFR_1,CMU Low Frequency Reference Register CLKMN1" bitfld.long 0x8 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x8 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x8 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x8 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x8 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x8 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x8 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x8 0.--11. 1. "LFREF_1,Low Frequency reference value 1" tree.end tree "CMU_10" base ad:0x710C0480 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" bitfld.long 0x0 31. "TREN,frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x0 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x0 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x0 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x0 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x0 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x0 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value 0" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" bitfld.long 0x4 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x4 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 26. "STOP,Frequency limit monitor during STOP mode" "?,1: Enabled" bitfld.long 0x4 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x4 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x4 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value 0" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 5. "FHHI_1,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 4. "FLLI_1,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0xB line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" line.long 0x4 "HFREFR_1,CMU High Frequency Reference Register CLKMN1" bitfld.long 0x4 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x4 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x4 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x4 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x4 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "HFREF_1,High Frequency reference value 1" line.long 0x8 "LFREFR_1,CMU Low Frequency Reference Register CLKMN1" bitfld.long 0x8 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x8 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x8 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x8 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x8 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x8 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x8 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x8 0.--11. 1. "LFREF_1,Low Frequency reference value 1" tree.end tree "CMU_11" base ad:0x710C04C0 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" bitfld.long 0x0 31. "TREN,frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x0 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x0 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x0 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x0 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x0 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x0 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value 0" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" bitfld.long 0x4 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x4 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 26. "STOP,Frequency limit monitor during STOP mode" "?,1: Enabled" bitfld.long 0x4 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x4 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x4 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value 0" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 5. "FHHI_1,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 4. "FLLI_1,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0xB line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" line.long 0x4 "HFREFR_1,CMU High Frequency Reference Register CLKMN1" bitfld.long 0x4 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x4 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x4 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x4 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x4 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "HFREF_1,High Frequency reference value 1" line.long 0x8 "LFREFR_1,CMU Low Frequency Reference Register CLKMN1" bitfld.long 0x8 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x8 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x8 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x8 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x8 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x8 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x8 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x8 0.--11. 1. "LFREF_1,Low Frequency reference value 1" tree.end tree "CMU_12" base ad:0x710C0500 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" bitfld.long 0x0 31. "TREN,frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x0 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x0 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x0 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x0 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x0 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x0 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value 0" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" bitfld.long 0x4 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x4 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 26. "STOP,Frequency limit monitor during STOP mode" "?,1: Enabled" bitfld.long 0x4 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x4 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x4 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value 0" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 5. "FHHI_1,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 4. "FLLI_1,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0xB line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" line.long 0x4 "HFREFR_1,CMU High Frequency Reference Register CLKMN1" bitfld.long 0x4 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x4 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x4 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x4 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x4 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "HFREF_1,High Frequency reference value 1" line.long 0x8 "LFREFR_1,CMU Low Frequency Reference Register CLKMN1" bitfld.long 0x8 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x8 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x8 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x8 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x8 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x8 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x8 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x8 0.--11. 1. "LFREF_1,Low Frequency reference value 1" tree.end tree "CMU_13" base ad:0x710C0540 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" bitfld.long 0x0 31. "TREN,frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x0 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x0 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x0 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x0 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x0 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x0 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value 0" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" bitfld.long 0x4 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x4 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 26. "STOP,Frequency limit monitor during STOP mode" "?,1: Enabled" bitfld.long 0x4 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x4 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x4 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value 0" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 5. "FHHI_1,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 4. "FLLI_1,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0xB line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" line.long 0x4 "HFREFR_1,CMU High Frequency Reference Register CLKMN1" bitfld.long 0x4 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x4 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x4 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x4 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x4 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "HFREF_1,High Frequency reference value 1" line.long 0x8 "LFREFR_1,CMU Low Frequency Reference Register CLKMN1" bitfld.long 0x8 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x8 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x8 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x8 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x8 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x8 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x8 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x8 0.--11. 1. "LFREF_1,Low Frequency reference value 1" tree.end tree "CMU_14" base ad:0x710C0580 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" bitfld.long 0x0 31. "TREN,frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x0 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x0 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x0 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x0 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x0 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x0 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value 0" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" bitfld.long 0x4 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x4 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 26. "STOP,Frequency limit monitor during STOP mode" "?,1: Enabled" bitfld.long 0x4 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x4 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x4 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value 0" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 5. "FHHI_1,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 4. "FLLI_1,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0xB line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" line.long 0x4 "HFREFR_1,CMU High Frequency Reference Register CLKMN1" bitfld.long 0x4 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x4 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x4 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x4 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x4 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x4 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "HFREF_1,High Frequency reference value 1" line.long 0x8 "LFREFR_1,CMU Low Frequency Reference Register CLKMN1" bitfld.long 0x8 31. "TREN,Frequency limit monitor during run mode transition" "0: Frequency limit monitor disabled,1: Frequency limit monitor enabled only if it is.." bitfld.long 0x8 29. "STANDBY,Frequency limit monitor during STANDBY mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 26. "STOP,Frequency limit monitor during STOP mode" "0: Disabled,1: Enabled" bitfld.long 0x8 24. "HALT,Frequency limit monitor during HALT mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 23. "RUN3,Frequency limit monitor during RUN3 mode" "0: Disabled,1: Enabled" bitfld.long 0x8 22. "RUN2,Frequency limit monitor during RUN2 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 21. "RUN1,Frequency limit monitor during RUN1 mode" "0: Disabled,1: Enabled" bitfld.long 0x8 20. "RUN0,Frequency limit monitor during RUN0 mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 19. "DRUN,Frequency limit monitor during DRUN mode" "0: Disabled,1: Enabled" bitfld.long 0x8 18. "SAFE,Frequency limit monitor during SAFE mode" "0: Disabled,1: Enabled" newline bitfld.long 0x8 17. "TEST,Frequency limit monitor during TEST mode" "0: Disabled,1: Enabled" bitfld.long 0x8 16. "RESET,Frequency limit monitor during RESET mode" "0: Disabled,1: Enabled" newline hexmask.long.word 0x8 0.--11. 1. "LFREF_1,Low Frequency reference value 1" tree.end tree "CMU_15" base ad:0x710C05C0 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_20" base ad:0x722C8200 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_21" base ad:0x722C8240 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_22" base ad:0x722C8280 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_23" base ad:0x722C82C0 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_24" base ad:0x722C8300 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_25" base ad:0x722C8340 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_26" base ad:0x722C8380 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_27" base ad:0x722C83C0 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_28" base ad:0x722C8400 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_29" base ad:0x722C8440 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_30" base ad:0x722C8480 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_31" base ad:0x722C84C0 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_40" base ad:0x716C0240 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_41" base ad:0x716C0280 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_43" base ad:0x716C0300 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_44" base ad:0x716C0340 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_45" base ad:0x716C0380 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree "CMU_46" base ad:0x716C03C0 group.long 0x0++0x3 line.long 0x0 "CSR,CMU Control Status Register" bitfld.long 0x0 23. "SFM,Start Frequency Measure" "0: Frequency measurement is completed or not yet..,1: Frequency measurement is not completed." bitfld.long 0x0 16.--18. "CMU_MEASUR_WINDOW,This field defines the measurement duration in the number of clock ticks of the reference clock. The measurement window duration should be set by software before the CMU is enabled." "0: Measurement duration of 64 clock ticks of..,1: Measurement duration of 128 clock ticks of..,2: Measurement duration of 256 clock ticks of..,3: Measurement duration of 512 clock ticks of..,4: Measurement duration of 1024 clock ticks of..,5: Measurement duration of 2048 clock ticks of..,6: Measurement duration of 4096 clock ticks of..,7: Measurement duration of 8192 clock ticks of.." newline bitfld.long 0x0 8.--9. "CKSEL1,Frequency measure clock selection bit" "0: CLKMT0_RMN is selected.,?,?,3: CLKMT0_RMN is selected." bitfld.long 0x0 1.--2. "RCDIV,CLKMT0_RMN division factor" "0: CLKMT0_RMN divided by 1 (No division).,1: CLKMT0_RMN divided by 2.,2: CLKMT0_RMN divided by 4.,3: CLKMT0_RMN divided by 8." newline bitfld.long 0x0 0. "CME,CLKMN1 monitor enable" "0: CLKMN1 monitor is disabled.,1: CLKMN1 monitor is enabled." rgroup.long 0x4++0x3 line.long 0x0 "FDR,CMU Frequency Display Register" hexmask.long.tbyte 0x0 0.--19. 1. "FD,Measured frequency bits" group.long 0x8++0xB line.long 0x0 "HFREFR,CMU High Frequency Reference Register CLKMN1" hexmask.long.word 0x0 0.--11. 1. "HFREF,High Frequency reference value" line.long 0x4 "LFREFR,CMU Low Frequency Reference Register CLKMN1" hexmask.long.word 0x4 0.--11. 1. "LFREF,Low Frequency reference value" line.long 0x8 "ISR,CMU Interrupt Status Register" bitfld.long 0x8 2. "FHHI,CLKMN1 frequency higher than high reference event status" "0: No FHH event,1: FHH event occurred" bitfld.long 0x8 1. "FLLI,CLKMN1 frequency less than low reference event status" "0: No FLL event,1: FLL event occurred" newline bitfld.long 0x8 0. "OLRI,Oscillator frequency less than fCLKMT0_RMN/2RCDIV event status" "0: No OLR event,1: OLR event occurred" group.long 0x18++0x3 line.long 0x0 "MDR,CMU Measurement Duration Register" hexmask.long.tbyte 0x0 0.--19. 1. "MD,Measurement duration bits" tree.end tree.end tree "CRC (Cyclic Redundancy Check)" base ad:0x0 tree "CRC_0" base ad:0x703EC000 group.long 0x0++0xB line.long 0x0 "CFG0,CRC Configuration Register 0" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP0,CRC Input Register 0" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT0,CRC Current Status Register 0" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0xC++0x3 line.long 0x0 "OUTP0,CRC Output Register 0" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" group.long 0x10++0xB line.long 0x0 "CFG1,CRC Configuration Register 1" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP1,CRC Input Register 1" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT1,CRC Current Status Register 1" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0x1C++0x3 line.long 0x0 "OUTP1,CRC Output Register 1" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" group.long 0x20++0xB line.long 0x0 "CFG2,CRC Configuration Register 2" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP2,CRC Input Register 2" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT2,CRC Current Status Register 2" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0x2C++0x3 line.long 0x0 "OUTP2,CRC Output Register 2" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" group.long 0x30++0xB line.long 0x0 "CFG3,CRC Configuration Register 3" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP3,CRC Input Register 3" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT3,CRC Current Status Register 3" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0x3C++0x3 line.long 0x0 "OUTP3,CRC Output Register 3" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" tree.end tree "CRC_1" base ad:0x709EC000 group.long 0x0++0xB line.long 0x0 "CFG0,CRC Configuration Register 0" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP0,CRC Input Register 0" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT0,CRC Current Status Register 0" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0xC++0x3 line.long 0x0 "OUTP0,CRC Output Register 0" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" group.long 0x10++0xB line.long 0x0 "CFG1,CRC Configuration Register 1" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP1,CRC Input Register 1" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT1,CRC Current Status Register 1" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0x1C++0x3 line.long 0x0 "OUTP1,CRC Output Register 1" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" group.long 0x20++0xB line.long 0x0 "CFG2,CRC Configuration Register 2" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP2,CRC Input Register 2" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT2,CRC Current Status Register 2" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0x2C++0x3 line.long 0x0 "OUTP2,CRC Output Register 2" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" group.long 0x30++0xB line.long 0x0 "CFG3,CRC Configuration Register 3" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP3,CRC Input Register 3" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT3,CRC Current Status Register 3" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0x3C++0x3 line.long 0x0 "OUTP3,CRC Output Register 3" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" tree.end tree "CRC_2" base ad:0x703F0000 group.long 0x0++0xB line.long 0x0 "CFG0,CRC Configuration Register 0" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP0,CRC Input Register 0" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT0,CRC Current Status Register 0" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0xC++0x3 line.long 0x0 "OUTP0,CRC Output Register 0" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" group.long 0x10++0xB line.long 0x0 "CFG1,CRC Configuration Register 1" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP1,CRC Input Register 1" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT1,CRC Current Status Register 1" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0x1C++0x3 line.long 0x0 "OUTP1,CRC Output Register 1" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" group.long 0x20++0xB line.long 0x0 "CFG2,CRC Configuration Register 2" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP2,CRC Input Register 2" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT2,CRC Current Status Register 2" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0x2C++0x3 line.long 0x0 "OUTP2,CRC Output Register 2" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" group.long 0x30++0xB line.long 0x0 "CFG3,CRC Configuration Register 3" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP3,CRC Input Register 3" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT3,CRC Current Status Register 3" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0x3C++0x3 line.long 0x0 "OUTP3,CRC Output Register 3" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" tree.end tree "CRC_3" base ad:0x709F0000 group.long 0x0++0xB line.long 0x0 "CFG0,CRC Configuration Register 0" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP0,CRC Input Register 0" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT0,CRC Current Status Register 0" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0xC++0x3 line.long 0x0 "OUTP0,CRC Output Register 0" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" group.long 0x10++0xB line.long 0x0 "CFG1,CRC Configuration Register 1" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP1,CRC Input Register 1" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT1,CRC Current Status Register 1" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0x1C++0x3 line.long 0x0 "OUTP1,CRC Output Register 1" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" group.long 0x20++0xB line.long 0x0 "CFG2,CRC Configuration Register 2" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP2,CRC Input Register 2" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT2,CRC Current Status Register 2" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0x2C++0x3 line.long 0x0 "OUTP2,CRC Output Register 2" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" group.long 0x30++0xB line.long 0x0 "CFG3,CRC Configuration Register 3" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP3,CRC Input Register 3" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT3,CRC Current Status Register 3" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0x3C++0x3 line.long 0x0 "OUTP3,CRC Output Register 3" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" tree.end tree "CRC_4" base ad:0x703F4000 group.long 0x0++0xB line.long 0x0 "CFG0,CRC Configuration Register 0" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP0,CRC Input Register 0" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT0,CRC Current Status Register 0" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0xC++0x3 line.long 0x0 "OUTP0,CRC Output Register 0" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" group.long 0x10++0xB line.long 0x0 "CFG1,CRC Configuration Register 1" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP1,CRC Input Register 1" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT1,CRC Current Status Register 1" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0x1C++0x3 line.long 0x0 "OUTP1,CRC Output Register 1" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" group.long 0x20++0xB line.long 0x0 "CFG2,CRC Configuration Register 2" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP2,CRC Input Register 2" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT2,CRC Current Status Register 2" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0x2C++0x3 line.long 0x0 "OUTP2,CRC Output Register 2" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" group.long 0x30++0xB line.long 0x0 "CFG3,CRC Configuration Register 3" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP3,CRC Input Register 3" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT3,CRC Current Status Register 3" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0x3C++0x3 line.long 0x0 "OUTP3,CRC Output Register 3" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" tree.end tree "CRC_5" base ad:0x709F4000 group.long 0x0++0xB line.long 0x0 "CFG0,CRC Configuration Register 0" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP0,CRC Input Register 0" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT0,CRC Current Status Register 0" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0xC++0x3 line.long 0x0 "OUTP0,CRC Output Register 0" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" group.long 0x10++0xB line.long 0x0 "CFG1,CRC Configuration Register 1" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP1,CRC Input Register 1" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT1,CRC Current Status Register 1" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0x1C++0x3 line.long 0x0 "OUTP1,CRC Output Register 1" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" group.long 0x20++0xB line.long 0x0 "CFG2,CRC Configuration Register 2" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP2,CRC Input Register 2" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT2,CRC Current Status Register 2" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0x2C++0x3 line.long 0x0 "OUTP2,CRC Output Register 2" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" group.long 0x30++0xB line.long 0x0 "CFG3,CRC Configuration Register 3" bitfld.long 0x0 5. "SWAP_BYTEWISE,SWAP_BYTEWISE" "0: No swap,1: Byte wise (MSB to LSB LSB to MSB) bytes swap.." bitfld.long 0x0 4. "SWAP_BITWISE,SWAP_BITWISE" "0: No swap,1: Bit wise (MSB to LSB LSB to MSB) bits swap.." newline bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8H2F autosar polynomial" bitfld.long 0x0 1. "SWAP,SWAP selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." newline bitfld.long 0x0 0. "INV,INV selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP3,CRC Input Register 3" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT3,CRC Current Status Register 3" hexmask.long 0x8 0.--31. 1. "CSTAT,Status of the CRC signature" rgroup.long 0x3C++0x3 line.long 0x0 "OUTP3,CRC Output Register 3" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" tree.end tree.end tree "DLYB (Delay block)" base ad:0x0 tree "ABLK" base ad:0x4FFFE800 group.long 0x0++0x7 line.long 0x0 "CR,Control Register" bitfld.long 0x0 1. "SEN,Decides if sampler length should be enabled or not." "0: Sampler length and register access to UNIT and..,1: Sampler length and register access to UNIT and.." bitfld.long 0x0 0. "DEN,Decides if delay block is enabled or not" "0: Delay block disabled.,1: Delay block enabled." line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 31. "LNGF,Indicate when the delay line length value in LNG is valid after a change in UNIT." "0: Length value in LNG is not valid.,1: Length value in LNG is valid." hexmask.long.word 0x4 16.--27. 1. "LNG,Reflect the 12 Unit delay values sampled at the rising edge of the Input clock" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Defines the delay of a Unit delay cell." hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output clock." tree.end tree "OCTOSPI_DELAY_BLK_1_ABLK" base ad:0x4FFFF400 group.long 0x0++0x7 line.long 0x0 "CR,Control Register" bitfld.long 0x0 1. "SEN,Decides if sampler length should be enabled or not." "0: Sampler length and register access to UNIT and..,1: Sampler length and register access to UNIT and.." bitfld.long 0x0 0. "DEN,Decides if delay block is enabled or not" "0: Delay block disabled.,1: Delay block enabled." line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 31. "LNGF,Indicate when the delay line length value in LNG is valid after a change in UNIT." "0: Length value in LNG is not valid.,1: Length value in LNG is valid." hexmask.long.word 0x4 16.--27. 1. "LNG,Reflect the 12 Unit delay values sampled at the rising edge of the Input clock" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Defines the delay of a Unit delay cell." hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output clock." tree.end tree.end tree "DMAMUX (DMA Channel Multiplexer)" base ad:0x0 tree "DMAMUX_0" tree "DMAMUX_0_SYS_0" base ad:0x703DC000 group.byte 0x0++0xF line.byte 0x0 "CHCFG0,Channel 0 Configuration registers" bitfld.byte 0x0 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x0 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x0 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x1 "CHCFG1,Channel 1 Configuration registers" bitfld.byte 0x1 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x1 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x1 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x2 "CHCFG2,Channel 2 Configuration registers" bitfld.byte 0x2 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x2 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x2 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x3 "CHCFG3,Channel 3 Configuration registers" bitfld.byte 0x3 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x3 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x3 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x4 "CHCFG4,Channel 4 Configuration registers" bitfld.byte 0x4 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x4 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x4 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x5 "CHCFG5,Channel 5 Configuration registers" bitfld.byte 0x5 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x5 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x5 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x6 "CHCFG6,Channel 6 Configuration registers" bitfld.byte 0x6 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x6 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x6 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x7 "CHCFG7,Channel 7 Configuration registers" bitfld.byte 0x7 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x7 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x7 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x8 "CHCFG8,Channel 8 Configuration registers" bitfld.byte 0x8 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x8 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x8 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x9 "CHCFG9,Channel 9 Configuration registers" bitfld.byte 0x9 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x9 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x9 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xA "CHCFG10,Channel 10 Configuration registers" bitfld.byte 0xA 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xA 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xA 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xB "CHCFG11,Channel 11 Configuration registers" bitfld.byte 0xB 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xB 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xB 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xC "CHCFG12,Channel 12 Configuration registers" bitfld.byte 0xC 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xC 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xC 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xD "CHCFG13,Channel 13 Configuration registers" bitfld.byte 0xD 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xD 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xD 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xE "CHCFG14,Channel 14 Configuration registers" bitfld.byte 0xE 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xE 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xE 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xF "CHCFG15,Channel 15 Configuration registers" bitfld.byte 0xF 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xF 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xF 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" tree.end tree "DMAMUX_0_SYS_1" base ad:0x709DC000 group.byte 0x0++0xF line.byte 0x0 "CHCFG0,Channel 0 Configuration registers" bitfld.byte 0x0 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x0 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x0 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x1 "CHCFG1,Channel 1 Configuration registers" bitfld.byte 0x1 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x1 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x1 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x2 "CHCFG2,Channel 2 Configuration registers" bitfld.byte 0x2 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x2 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x2 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x3 "CHCFG3,Channel 3 Configuration registers" bitfld.byte 0x3 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x3 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x3 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x4 "CHCFG4,Channel 4 Configuration registers" bitfld.byte 0x4 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x4 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x4 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x5 "CHCFG5,Channel 5 Configuration registers" bitfld.byte 0x5 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x5 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x5 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x6 "CHCFG6,Channel 6 Configuration registers" bitfld.byte 0x6 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x6 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x6 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x7 "CHCFG7,Channel 7 Configuration registers" bitfld.byte 0x7 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x7 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x7 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x8 "CHCFG8,Channel 8 Configuration registers" bitfld.byte 0x8 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x8 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x8 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x9 "CHCFG9,Channel 9 Configuration registers" bitfld.byte 0x9 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x9 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x9 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xA "CHCFG10,Channel 10 Configuration registers" bitfld.byte 0xA 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xA 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xA 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xB "CHCFG11,Channel 11 Configuration registers" bitfld.byte 0xB 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xB 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xB 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xC "CHCFG12,Channel 12 Configuration registers" bitfld.byte 0xC 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xC 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xC 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xD "CHCFG13,Channel 13 Configuration registers" bitfld.byte 0xD 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xD 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xD 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xE "CHCFG14,Channel 14 Configuration registers" bitfld.byte 0xE 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xE 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xE 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xF "CHCFG15,Channel 15 Configuration registers" bitfld.byte 0xF 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xF 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xF 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" tree.end tree "DMAMUX_0_SYS_2" base ad:0x703E0000 group.byte 0x0++0xF line.byte 0x0 "CHCFG0,Channel 0 Configuration registers" bitfld.byte 0x0 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x0 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x0 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x1 "CHCFG1,Channel 1 Configuration registers" bitfld.byte 0x1 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x1 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x1 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x2 "CHCFG2,Channel 2 Configuration registers" bitfld.byte 0x2 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x2 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x2 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x3 "CHCFG3,Channel 3 Configuration registers" bitfld.byte 0x3 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x3 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x3 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x4 "CHCFG4,Channel 4 Configuration registers" bitfld.byte 0x4 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x4 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x4 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x5 "CHCFG5,Channel 5 Configuration registers" bitfld.byte 0x5 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x5 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x5 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x6 "CHCFG6,Channel 6 Configuration registers" bitfld.byte 0x6 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x6 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x6 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x7 "CHCFG7,Channel 7 Configuration registers" bitfld.byte 0x7 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x7 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x7 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x8 "CHCFG8,Channel 8 Configuration registers" bitfld.byte 0x8 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x8 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x8 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x9 "CHCFG9,Channel 9 Configuration registers" bitfld.byte 0x9 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x9 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x9 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xA "CHCFG10,Channel 10 Configuration registers" bitfld.byte 0xA 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xA 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xA 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xB "CHCFG11,Channel 11 Configuration registers" bitfld.byte 0xB 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xB 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xB 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xC "CHCFG12,Channel 12 Configuration registers" bitfld.byte 0xC 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xC 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xC 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xD "CHCFG13,Channel 13 Configuration registers" bitfld.byte 0xD 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xD 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xD 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xE "CHCFG14,Channel 14 Configuration registers" bitfld.byte 0xE 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xE 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xE 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xF "CHCFG15,Channel 15 Configuration registers" bitfld.byte 0xF 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xF 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xF 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" tree.end tree "DMAMUX_0_SYS_3" base ad:0x709E0000 group.byte 0x0++0xF line.byte 0x0 "CHCFG0,Channel 0 Configuration registers" bitfld.byte 0x0 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x0 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x0 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x1 "CHCFG1,Channel 1 Configuration registers" bitfld.byte 0x1 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x1 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x1 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x2 "CHCFG2,Channel 2 Configuration registers" bitfld.byte 0x2 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x2 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x2 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x3 "CHCFG3,Channel 3 Configuration registers" bitfld.byte 0x3 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x3 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x3 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x4 "CHCFG4,Channel 4 Configuration registers" bitfld.byte 0x4 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x4 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x4 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x5 "CHCFG5,Channel 5 Configuration registers" bitfld.byte 0x5 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x5 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x5 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x6 "CHCFG6,Channel 6 Configuration registers" bitfld.byte 0x6 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x6 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x6 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x7 "CHCFG7,Channel 7 Configuration registers" bitfld.byte 0x7 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x7 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x7 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x8 "CHCFG8,Channel 8 Configuration registers" bitfld.byte 0x8 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x8 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x8 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x9 "CHCFG9,Channel 9 Configuration registers" bitfld.byte 0x9 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x9 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x9 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xA "CHCFG10,Channel 10 Configuration registers" bitfld.byte 0xA 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xA 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xA 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xB "CHCFG11,Channel 11 Configuration registers" bitfld.byte 0xB 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xB 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xB 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xC "CHCFG12,Channel 12 Configuration registers" bitfld.byte 0xC 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xC 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xC 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xD "CHCFG13,Channel 13 Configuration registers" bitfld.byte 0xD 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xD 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xD 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xE "CHCFG14,Channel 14 Configuration registers" bitfld.byte 0xE 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xE 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xE 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xF "CHCFG15,Channel 15 Configuration registers" bitfld.byte 0xF 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xF 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xF 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" tree.end tree.end tree "DMAMUX_1" tree "DMAMUX_1_SYS_0" base ad:0x703DC200 group.byte 0x0++0xF line.byte 0x0 "CHCFG0,Channel 0 Configuration registers" bitfld.byte 0x0 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x0 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x0 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x1 "CHCFG1,Channel 1 Configuration registers" bitfld.byte 0x1 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x1 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x1 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x2 "CHCFG2,Channel 2 Configuration registers" bitfld.byte 0x2 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x2 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x2 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x3 "CHCFG3,Channel 3 Configuration registers" bitfld.byte 0x3 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x3 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x3 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x4 "CHCFG4,Channel 4 Configuration registers" bitfld.byte 0x4 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x4 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x4 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x5 "CHCFG5,Channel 5 Configuration registers" bitfld.byte 0x5 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x5 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x5 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x6 "CHCFG6,Channel 6 Configuration registers" bitfld.byte 0x6 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x6 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x6 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x7 "CHCFG7,Channel 7 Configuration registers" bitfld.byte 0x7 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x7 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x7 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x8 "CHCFG8,Channel 8 Configuration registers" bitfld.byte 0x8 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x8 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x8 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x9 "CHCFG9,Channel 9 Configuration registers" bitfld.byte 0x9 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x9 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x9 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xA "CHCFG10,Channel 10 Configuration registers" bitfld.byte 0xA 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xA 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xA 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xB "CHCFG11,Channel 11 Configuration registers" bitfld.byte 0xB 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xB 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xB 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xC "CHCFG12,Channel 12 Configuration registers" bitfld.byte 0xC 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xC 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xC 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xD "CHCFG13,Channel 13 Configuration registers" bitfld.byte 0xD 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xD 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xD 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xE "CHCFG14,Channel 14 Configuration registers" bitfld.byte 0xE 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xE 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xE 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xF "CHCFG15,Channel 15 Configuration registers" bitfld.byte 0xF 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xF 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xF 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" tree.end tree "DMAMUX_1_SYS_1" base ad:0x709DC200 group.byte 0x0++0xF line.byte 0x0 "CHCFG0,Channel 0 Configuration registers" bitfld.byte 0x0 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x0 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x0 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x1 "CHCFG1,Channel 1 Configuration registers" bitfld.byte 0x1 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x1 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x1 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x2 "CHCFG2,Channel 2 Configuration registers" bitfld.byte 0x2 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x2 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x2 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x3 "CHCFG3,Channel 3 Configuration registers" bitfld.byte 0x3 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x3 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x3 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x4 "CHCFG4,Channel 4 Configuration registers" bitfld.byte 0x4 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x4 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x4 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x5 "CHCFG5,Channel 5 Configuration registers" bitfld.byte 0x5 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x5 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x5 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x6 "CHCFG6,Channel 6 Configuration registers" bitfld.byte 0x6 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x6 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x6 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x7 "CHCFG7,Channel 7 Configuration registers" bitfld.byte 0x7 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x7 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x7 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x8 "CHCFG8,Channel 8 Configuration registers" bitfld.byte 0x8 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x8 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x8 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x9 "CHCFG9,Channel 9 Configuration registers" bitfld.byte 0x9 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x9 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x9 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xA "CHCFG10,Channel 10 Configuration registers" bitfld.byte 0xA 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xA 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xA 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xB "CHCFG11,Channel 11 Configuration registers" bitfld.byte 0xB 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xB 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xB 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xC "CHCFG12,Channel 12 Configuration registers" bitfld.byte 0xC 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xC 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xC 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xD "CHCFG13,Channel 13 Configuration registers" bitfld.byte 0xD 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xD 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xD 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xE "CHCFG14,Channel 14 Configuration registers" bitfld.byte 0xE 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xE 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xE 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xF "CHCFG15,Channel 15 Configuration registers" bitfld.byte 0xF 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xF 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xF 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" tree.end tree "DMAMUX_1_SYS_2" base ad:0x703E0200 group.byte 0x0++0xF line.byte 0x0 "CHCFG0,Channel 0 Configuration registers" bitfld.byte 0x0 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x0 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x0 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x1 "CHCFG1,Channel 1 Configuration registers" bitfld.byte 0x1 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x1 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x1 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x2 "CHCFG2,Channel 2 Configuration registers" bitfld.byte 0x2 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x2 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x2 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x3 "CHCFG3,Channel 3 Configuration registers" bitfld.byte 0x3 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x3 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x3 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x4 "CHCFG4,Channel 4 Configuration registers" bitfld.byte 0x4 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x4 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x4 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x5 "CHCFG5,Channel 5 Configuration registers" bitfld.byte 0x5 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x5 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x5 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x6 "CHCFG6,Channel 6 Configuration registers" bitfld.byte 0x6 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x6 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x6 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x7 "CHCFG7,Channel 7 Configuration registers" bitfld.byte 0x7 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x7 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x7 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x8 "CHCFG8,Channel 8 Configuration registers" bitfld.byte 0x8 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x8 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x8 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x9 "CHCFG9,Channel 9 Configuration registers" bitfld.byte 0x9 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x9 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x9 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xA "CHCFG10,Channel 10 Configuration registers" bitfld.byte 0xA 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xA 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xA 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xB "CHCFG11,Channel 11 Configuration registers" bitfld.byte 0xB 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xB 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xB 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xC "CHCFG12,Channel 12 Configuration registers" bitfld.byte 0xC 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xC 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xC 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xD "CHCFG13,Channel 13 Configuration registers" bitfld.byte 0xD 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xD 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xD 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xE "CHCFG14,Channel 14 Configuration registers" bitfld.byte 0xE 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xE 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xE 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xF "CHCFG15,Channel 15 Configuration registers" bitfld.byte 0xF 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xF 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xF 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" tree.end tree "DMAMUX_1_SYS_3" base ad:0x709E0200 group.byte 0x0++0xF line.byte 0x0 "CHCFG0,Channel 0 Configuration registers" bitfld.byte 0x0 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x0 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x0 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x1 "CHCFG1,Channel 1 Configuration registers" bitfld.byte 0x1 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x1 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x1 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x2 "CHCFG2,Channel 2 Configuration registers" bitfld.byte 0x2 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x2 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x2 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x3 "CHCFG3,Channel 3 Configuration registers" bitfld.byte 0x3 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x3 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x3 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x4 "CHCFG4,Channel 4 Configuration registers" bitfld.byte 0x4 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x4 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x4 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x5 "CHCFG5,Channel 5 Configuration registers" bitfld.byte 0x5 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x5 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x5 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x6 "CHCFG6,Channel 6 Configuration registers" bitfld.byte 0x6 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x6 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x6 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x7 "CHCFG7,Channel 7 Configuration registers" bitfld.byte 0x7 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x7 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x7 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x8 "CHCFG8,Channel 8 Configuration registers" bitfld.byte 0x8 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x8 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x8 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x9 "CHCFG9,Channel 9 Configuration registers" bitfld.byte 0x9 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x9 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x9 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xA "CHCFG10,Channel 10 Configuration registers" bitfld.byte 0xA 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xA 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xA 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xB "CHCFG11,Channel 11 Configuration registers" bitfld.byte 0xB 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xB 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xB 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xC "CHCFG12,Channel 12 Configuration registers" bitfld.byte 0xC 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xC 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xC 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xD "CHCFG13,Channel 13 Configuration registers" bitfld.byte 0xD 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xD 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xD 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xE "CHCFG14,Channel 14 Configuration registers" bitfld.byte 0xE 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xE 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xE 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xF "CHCFG15,Channel 15 Configuration registers" bitfld.byte 0xF 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xF 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xF 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" tree.end tree.end tree "DMAMUX_2" tree "DMAMUX_2_SYS_3" base ad:0x709E0400 group.byte 0x0++0xF line.byte 0x0 "CHCFG0,Channel 0 Configuration registers" bitfld.byte 0x0 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x0 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x0 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x1 "CHCFG1,Channel 1 Configuration registers" bitfld.byte 0x1 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x1 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x1 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x2 "CHCFG2,Channel 2 Configuration registers" bitfld.byte 0x2 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x2 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x2 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x3 "CHCFG3,Channel 3 Configuration registers" bitfld.byte 0x3 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x3 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x3 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x4 "CHCFG4,Channel 4 Configuration registers" bitfld.byte 0x4 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x4 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x4 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x5 "CHCFG5,Channel 5 Configuration registers" bitfld.byte 0x5 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x5 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x5 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x6 "CHCFG6,Channel 6 Configuration registers" bitfld.byte 0x6 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x6 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x6 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x7 "CHCFG7,Channel 7 Configuration registers" bitfld.byte 0x7 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x7 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x7 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x8 "CHCFG8,Channel 8 Configuration registers" bitfld.byte 0x8 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x8 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x8 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x9 "CHCFG9,Channel 9 Configuration registers" bitfld.byte 0x9 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x9 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x9 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xA "CHCFG10,Channel 10 Configuration registers" bitfld.byte 0xA 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xA 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xA 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xB "CHCFG11,Channel 11 Configuration registers" bitfld.byte 0xB 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xB 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xB 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xC "CHCFG12,Channel 12 Configuration registers" bitfld.byte 0xC 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xC 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xC 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xD "CHCFG13,Channel 13 Configuration registers" bitfld.byte 0xD 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xD 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xD 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xE "CHCFG14,Channel 14 Configuration registers" bitfld.byte 0xE 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xE 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xE 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xF "CHCFG15,Channel 15 Configuration registers" bitfld.byte 0xF 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xF 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xF 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" tree.end tree.end tree "DMAMUX_3" tree "DMAMUX_3_SYS_3" base ad:0x709E0600 group.byte 0x0++0xF line.byte 0x0 "CHCFG0,Channel 0 Configuration registers" bitfld.byte 0x0 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x0 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x0 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x1 "CHCFG1,Channel 1 Configuration registers" bitfld.byte 0x1 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x1 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x1 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x2 "CHCFG2,Channel 2 Configuration registers" bitfld.byte 0x2 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x2 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x2 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x3 "CHCFG3,Channel 3 Configuration registers" bitfld.byte 0x3 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x3 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x3 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x4 "CHCFG4,Channel 4 Configuration registers" bitfld.byte 0x4 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x4 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x4 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x5 "CHCFG5,Channel 5 Configuration registers" bitfld.byte 0x5 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x5 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x5 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x6 "CHCFG6,Channel 6 Configuration registers" bitfld.byte 0x6 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x6 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x6 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x7 "CHCFG7,Channel 7 Configuration registers" bitfld.byte 0x7 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x7 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x7 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x8 "CHCFG8,Channel 8 Configuration registers" bitfld.byte 0x8 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x8 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x8 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0x9 "CHCFG9,Channel 9 Configuration registers" bitfld.byte 0x9 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x9 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0x9 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xA "CHCFG10,Channel 10 Configuration registers" bitfld.byte 0xA 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xA 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xA 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xB "CHCFG11,Channel 11 Configuration registers" bitfld.byte 0xB 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xB 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xB 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xC "CHCFG12,Channel 12 Configuration registers" bitfld.byte 0xC 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xC 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xC 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xD "CHCFG13,Channel 13 Configuration registers" bitfld.byte 0xD 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xD 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xD 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xE "CHCFG14,Channel 14 Configuration registers" bitfld.byte 0xE 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xE 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xE 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" line.byte 0xF "CHCFG15,Channel 15 Configuration registers" bitfld.byte 0xF 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0xF 6. "TRIG,DMA Channel Trigger Enable (for triggered channels only)" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled" hexmask.byte 0xF 0.--5. 1. "SOURCE,DMA Channel Source (DMACHMUX slot)" tree.end tree.end tree.end tree "DSPI (Deserial Serial Peripheral Interface)" base ad:0x0 tree "DSPI_0" base ad:0x70E50000 group.long 0x0++0x3 line.long 0x0 "MCR,DSPI Module Configuration Register" bitfld.long 0x0 31. "MSTR,Master/Slave Mode Select" "0: DSPI is in slave mode.,1: DSPI is in master mode." bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK Enable" "0: Continuous SCK disabled.,1: Continuous SCK enabled." newline bitfld.long 0x0 28.--29. "DCONF,DSPI Configuration" "0: SPI,1: DSI,2: CSI,?" bitfld.long 0x0 27. "FRZ,Freeze" "0: Do not halt serial transfers in debug mode.,1: Halt serial transfers in debug mode." newline bitfld.long 0x0 26. "MTFE,Modified Timing Format Enable" "0: Modified SPI transfer format disabled.,1: Modified SPI transfer format enabled." bitfld.long 0x0 25. "PCSSE,Peripheral Chip Select Strobe Enable" "0: PCS[5]/PCSS is used as the Peripheral Chip..,1: PCS[5]/PCSS is used as an active-low PCS Strobe.." newline bitfld.long 0x0 24. "ROOE,Receive FIFO Overflow Overwrite Enable" "0: Incoming data is ignored.,1: Incoming data is shifted into the shift register." bitfld.long 0x0 23. "PCSIS7,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 22. "PCSIS6,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 21. "PCSIS5,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 20. "PCSIS4,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 19. "PCSIS3,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 18. "PCSIS2,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 17. "PCSIS1,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 16. "PCSIS0,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 14. "MDIS,Module Disable" "0: Enable DSPI clocks.,1: Allow external logic to disable DSPI clocks." newline bitfld.long 0x0 13. "DIS_TXF,Disable Transmit FIFO" "0: Tx FIFO is enabled.,1: Tx FIFO is disabled." bitfld.long 0x0 12. "DIS_RXF,Disable Receive FIFO" "0: Rx FIFO is enabled.,1: Rx FIFO is disabled." newline bitfld.long 0x0 11. "CLR_TXF,Clear TX FIFO" "0: Do not clear the Tx FIFO and CMD FIFO counters.,1: Clears the Tx FIFO and CMD FIFO counters." bitfld.long 0x0 10. "CLR_RXF,Clear RX FIFO" "0: Do not clear the Rx FIFO counter.,1: Clear the Rx FIFO counter." newline bitfld.long 0x0 8.--9. "SMPL_PT,Sample Point" "0: 0 protocol clocks between SCK edge and SIN sample,1: 1 protocol clock between SCK edge and SIN sample,2: 2 protocol clocks between SCK edge and SIN sample,?" bitfld.long 0x0 3. "XSPI,Extended SPI Mode" "0: Normal SPI Mode. Up to 16-bit Frames. Command..,1: Extended SPI Mode. Up to 32-bit SPI Frames." newline bitfld.long 0x0 2. "FCPCS,Fast Continuous PCS Mode." "0: Normal or Slow Continuous PCS mode. Masking of..,1: Fast Continuous PCS mode. Delays masked via.." bitfld.long 0x0 1. "PES,Parity Error Stop" "0: SPI frame transmission continues.,1: SPI frame transmission stops." newline bitfld.long 0x0 0. "HALT,Halt" "0: Start transfers.,1: Stop transfers." rgroup.long 0x4++0x3 line.long 0x0 "HCR,Hardware Configuration Register" bitfld.long 0x0 31. "DSI,DSI features are implemented for the module." "0: DSI features are not implemented DSI registers..,1: DSI features are implemented" bitfld.long 0x0 30. "PISR,PISR0-3 and parallel inputs frame positions selection logic (DSI Muxing Logic) are implemented for the module." "0: PISR0-3 registers are not implemented.,1: PISR0-3 registers are implemented." newline bitfld.long 0x0 29. "DSI64,DSI features in 64 bit mode are implemented for the module." "0: DSI features for 64 bit mode are not..,1: DSI features for 64 bit mode are implemented" bitfld.long 0x0 28. "PISR_EX,PISR4-7 and parallel inputs frame positions selection logic (DSI 64 bit Muxing Logic) are implemented for the module." "0: PISR4-7 registers are not implemented.,1: PISR4-7 registers are implemented." newline bitfld.long 0x0 27. "XSPI,Extended SPI Mode feature is implemented for the module." "0: Extended SPI Mode is not implemented.,1: Extended SPI Mode is implemented." bitfld.long 0x0 24.--26. "CTAR,Maximum implemented CTAR register number." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 20.--23. 1. "TXFR,Maximum implemented TXFR register number." hexmask.long.byte 0x0 16.--19. 1. "RXFR,Maximum implemented RXFR register number." newline hexmask.long.byte 0x0 12.--15. 1. "CMDFR,Maximum implemented command FIFO number." bitfld.long 0x0 11. "MSTR_MODE,Master Mode implementation is enabled" "0,1" newline bitfld.long 0x0 10. "SLV_MODE,Slave Mode implementation is enabled" "0,1" bitfld.long 0x0 9. "TSB_EN,TSB Mode implementation is enabled" "0,1" newline bitfld.long 0x0 8. "ITSB_EN,Interleaved TSB Mode implementation is enabled" "0,1" group.long 0x8++0x7 line.long 0x0 "TCR,DSPI Transfer Count Register" hexmask.long.word 0x0 16.--31. 1. "SPI_TCNT,SPI Transfer Counter" line.long 0x4 "CTAR0,DSPI Clock and Transfer Attributes Register 0 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" group.long 0xC++0x7 line.long 0x0 "CTAR0_SLAVE,When the DSPI is configured as:SPI master - the CTAS field in the command portion of the TX FIFO entry selects which CTAR is used.SPI bus slave - the CTAR0 register is used.DSI master - the DSICTAS field in the DSPI DSI Configuration Register.." hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." bitfld.long 0x0 22. "FMSZ5,MSB of Frame Size when DSI is used in 64-bit Mode" "0,1" line.long 0x4 "CTAR1,DSPI Clock and Transfer Attributes Register 1 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" group.long 0x10++0x27 line.long 0x0 "CTAR1_SLAVE,When the DSPI is configured as:SPI master - the CTAS field in the command portion of the TX FIFO entry selects which CTAR is used.SPI bus slave - the CTAR0 register is used.DSI master - the DSICTAS field in the DSPI DSI Configuration Register.." hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." bitfld.long 0x0 22. "FMSZ5,MSB of Frame Size when DSI is used in 64-bit Mode" "0,1" line.long 0x4 "CTAR2,DSPI Clock and Transfer Attributes Register 2 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x8 "CTAR3,DSPI Clock and Transfer Attributes Register 3 (In Master Mode)" bitfld.long 0x8 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x8 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x8 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x8 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x8 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x8 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x8 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x8 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x8 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x8 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x8 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x8 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x8 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0xC "CTAR4,DSPI Clock and Transfer Attributes Register 4 (In Master Mode)" bitfld.long 0xC 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0xC 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0xC 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0xC 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0xC 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0xC 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0xC 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0xC 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0xC 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0xC 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0xC 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0xC 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x10 "CTAR5,DSPI Clock and Transfer Attributes Register 5 (In Master Mode)" bitfld.long 0x10 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x10 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x10 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x10 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x10 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x10 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x10 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x10 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x10 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x10 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x10 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x10 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x10 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x14 "CTAR6,DSPI Clock and Transfer Attributes Register 6 (In Master Mode)" bitfld.long 0x14 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x14 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x14 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x14 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x14 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x14 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x14 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x14 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x14 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x14 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x14 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x14 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x18 "CTAR7,DSPI Clock and Transfer Attributes Register 7 (In Master Mode)" bitfld.long 0x18 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x18 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x18 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x18 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x18 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x18 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x18 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x18 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x18 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x18 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x18 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x18 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x18 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x1C "SR,DSPI Status Register" bitfld.long 0x1C 31. "TCF,Transfer Complete Flag." "0: Transfer not complete.,1: Transfer complete." bitfld.long 0x1C 30. "TXRXS,TX and RX Status." "0: Transmit and receive operations are disabled..,1: Transmit and receive operations are enabled.." newline bitfld.long 0x1C 29. "SPITCF,SPI Frame Transfer Complete Flag." "0: SPI frame transfer is not complete.,1: SPI frame transfer is complete." bitfld.long 0x1C 28. "EOQF,End of Queue Flag." "0: EOQ is not set in the executing command.,1: EOQ is set in the executing SPI command." newline bitfld.long 0x1C 27. "TFUF,Transmit FIFO Underflow Flag." "0: No Tx FIFO underflow.,1: Tx FIFO underflow has occurred." bitfld.long 0x1C 26. "DSITCF,DSI Frame Transfer Complete Flag." "0: DSI frame transfer is not complete.,1: DSI frame transfer is complete." newline bitfld.long 0x1C 25. "TFFF,Transmit FIFO Fill Flag." "0: Tx FIFO is full.,1: Tx FIFO is not full." bitfld.long 0x1C 24. "BSYF,Busy Flag." "0: No Cyclic Command Transfer in Progress.,1: Cyclic Command Transfer is in progress. Current.." newline bitfld.long 0x1C 23. "CMDTCF,Command Transfer Complete Flag." "0: Data Transfer by current Command not complete.,1: Data Transfer by current Command complete." bitfld.long 0x1C 22. "DPEF,DSI Parity Error Flag." "0: No parity error.,1: Parity error has occurred." newline bitfld.long 0x1C 21. "SPEF,SPI Parity Error Flag." "0: No parity error.,1: Parity error has occurred." bitfld.long 0x1C 20. "DDIF,DSI Data Received with Active Bits." "0: No DSI data with active bits was received.,1: DSI data with active bits was received." newline bitfld.long 0x1C 19. "RFOF,Receive FIFO Overflow Flag." "0: No Rx FIFO overflow.,1: Rx FIFO overflow has occurred." bitfld.long 0x1C 18. "TFIWF,Transmit FIFO Invalid Write Flag." "0: No Invalid Data present in TX FIFO,1: Invalid Data present in TX FIFO since CMD FIFO.." newline bitfld.long 0x1C 17. "RFDF,Receive FIFO Drain Flag." "0: Rx FIFO is empty.,1: Rx FIFO is not empty." bitfld.long 0x1C 16. "CMDFFF,Command FIFO Fill Flag." "0: CMD FIFO is full.,1: CMD FIFO is not full." newline hexmask.long.byte 0x1C 12.--15. 1. "TXCTR,TX FIFO Counter." hexmask.long.byte 0x1C 8.--11. 1. "TXNXTPTR,Transmit Next Pointer." newline hexmask.long.byte 0x1C 4.--7. 1. "RXCTR,RX FIFO Counter." hexmask.long.byte 0x1C 0.--3. 1. "POPNXTPTR,Pop Next Pointer." line.long 0x20 "RSER,DSPI DMA/Interrupt Request Select and Enable Register" bitfld.long 0x20 31. "TCF_RE,Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 30. "CMDFFF_RE,Command FIFO Fill Flag Request Enable." "0: Disabled.,1: Enabled." newline bitfld.long 0x20 29. "SPITCF_RE,SPI Frame Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 28. "EOQF_RE,DSPI Finished Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 27. "TFUF_RE,Transmit FIFO Underflow Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 26. "DSITCF_RE,DSI Frame Transmission Complete Request Enable." "0: Disabled.,1: Enabled." newline bitfld.long 0x20 25. "TFFF_RE,Transmit FIFO Fill Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 24. "TFFF_DIRS,Transmit FIFO Fill DMA or Interrupt Request Select" "0: Interrupt requests.,1: DMA requests." newline bitfld.long 0x20 23. "CMDTCF_RE,Command Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 22. "DPEF_RE,DSI Parity Error Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 21. "SPEF_RE,SPI Parity Error Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 20. "DDIF_RE,DSI data received with active bits Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 19. "RFOF_RE,Receive FIFO Overflow Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 18. "TFIWF_RE,Transmit FIFO Invalid Write Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 17. "RFDF_RE,Receive FIFO Drain Request Enable" "0: Disabled,1: Enabled" bitfld.long 0x20 16. "RFDF_DIRS,Receive FIFO Drain DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." newline bitfld.long 0x20 15. "CMDFFF_DIRS,Command FIFO FIll DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." bitfld.long 0x20 14. "DDIF_DIRS,DSI data received with active bits - DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." line.long 0x24 "PUSHR,DSPI PUSH FIFO Register In Master mode" bitfld.long 0x24 31. "CONT,Continuous Peripheral Chip Select Enable. (SPI master mode)" "0: Return PCSn signals to their inactive state..,1: Keep PCSn signals asserted between transfers." bitfld.long 0x24 28.--30. "CTAS,Clock and Transfer Attributes Select." "0: CTAR0/CTARE0,1: CTAR1/CTARE1,2: CTAR2/CTARE2,3: CTAR3/CTARE3,4: CTAR4/CTARE4,5: CTAR5/CTARE5,6: CTAR6/CTARE6,7: CTAR7/CTARE7" newline bitfld.long 0x24 27. "EOQ,End Of Queue" "0: The SPI data is not the last data to transfer.,1: The SPI data is the last data to transfer." bitfld.long 0x24 26. "CTCNT,Clear Transfer Counter." "0: Do not clear the TCR[SPI_TCNT] field.,1: Clear the TCR[SPI_TCNT] field." newline bitfld.long 0x24 25. "PE_MASC,Parity Enable or Mask tASC delay in the current frame" "0: PE: No parity bit included/checked. MASC: tASC..,1: PE: Parity bit is transmitted instead of the.." bitfld.long 0x24 24. "PP_MCSC,Parity Polarity or Mask tCSC delay in the next frame" "0: PP: Even Parity: the number of 1 bits in the..,1: PP: Odd Parity: the number of 1 bits in the.." newline hexmask.long.byte 0x24 16.--23. 1. "PCS,Select which PCS signals are to be asserted for the transfer." hexmask.long.word 0x24 0.--15. 1. "TXDATA,Transmit Data" group.long 0x34++0x3 line.long 0x0 "PUSHR_SLAVE,PUSHR provides the means to write to the TX FIFO.Data written to this register is transferred to:The TX FIFO for 8- or 16-bit writes to the Data field of PUSHR.In master mode. the register provides 16-bit command to the CMD FIFO and 16-bit.." hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x38++0x13 line.long 0x0 "POPR,DSPI POP FIFO Register" hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data" line.long 0x4 "TXFR0,DSPI Transmit FIFO Registers" hexmask.long.word 0x4 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x4 0.--15. 1. "TXDATA,Transmit Data" line.long 0x8 "TXFR1,DSPI Transmit FIFO Registers" hexmask.long.word 0x8 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x8 0.--15. 1. "TXDATA,Transmit Data" line.long 0xC "TXFR2,DSPI Transmit FIFO Registers" hexmask.long.word 0xC 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0xC 0.--15. 1. "TXDATA,Transmit Data" line.long 0x10 "TXFR3,DSPI Transmit FIFO Registers" hexmask.long.word 0x10 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x10 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x7C++0xF line.long 0x0 "RXFR0,DSPI Receive FIFO Registers" hexmask.long 0x0 0.--31. 1. "RXDATA,Receive Data" line.long 0x4 "RXFR1,DSPI Receive FIFO Registers" hexmask.long 0x4 0.--31. 1. "RXDATA,Receive Data" line.long 0x8 "RXFR2,DSPI Receive FIFO Registers" hexmask.long 0x8 0.--31. 1. "RXDATA,Receive Data" line.long 0xC "RXFR3,DSPI Receive FIFO Registers" hexmask.long 0xC 0.--31. 1. "RXDATA,Receive Data" group.long 0xBC++0x3 line.long 0x0 "DSICR0,DSPI DSI Configuration Register 0" bitfld.long 0x0 30. "FMSZ4,MSB of the frame size in master mode when DSI is used in 32-bit mode." "0,1" bitfld.long 0x0 23. "FMSZ5,MSB of the frame size in master mode when DSI is used in 64-bit mode." "0,1" newline bitfld.long 0x0 21. "ITSB,Interleaved TSB mode." "0: Disabled.,1: Enabled." bitfld.long 0x0 20. "TSBC,Timed Serial Bus Configuration." "0: Disabled.,1: Enabled." newline bitfld.long 0x0 19. "TXSS,Transmit Data Source Select." "0: SDR source.,1: ASDR source." bitfld.long 0x0 18. "TPOL,Trigger Polarity" "0: Falling edge initiates a transfer.,1: Rising edge initiates a transfer." newline bitfld.long 0x0 16. "CID,Change In Data Transfer Enable" "0: Disabled.,1: Enabled." bitfld.long 0x0 15. "DCONT,DSI Continuous Peripheral Chip Select Enable (DSI Master mode only)" "0: PCS signals return to inactive.,1: PCS signals remain asserted." newline bitfld.long 0x0 12.--14. "DSICTAS,DSI Clock and Transfer Attributes Select (DSI Master mode only)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "DMS,Data Match Stop" "0: Disabled.,1: Enabled." newline bitfld.long 0x0 10. "PES,Parity Error Stop" "0: Disabled.,1: Enabled." bitfld.long 0x0 9. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of the last.." newline bitfld.long 0x0 8. "PP,Parity Polarity" "0: Even Parity: the number of '1' bits in the..,1: Odd Parity: the number of 1 bits in the.." hexmask.long.byte 0x0 0.--7. 1. "DPCSX,DSI Peripheral Chip Select 07" rgroup.long 0xC0++0x3 line.long 0x0 "SDR0,DSPI DSI Serialization Data Register 0" hexmask.long 0x0 0.--31. 1. "SER_DATA,Serialized Data" group.long 0xC4++0x3 line.long 0x0 "ASDR0,DSPI DSI Alternate Serialization Data Register 0" hexmask.long 0x0 0.--31. 1. "ASER_DATA,Alternate Serialized Data" rgroup.long 0xC8++0x7 line.long 0x0 "COMPR0,DSPI DSI Transmit Comparison Register 0" hexmask.long 0x0 0.--31. 1. "COMP_DATA,Compare Data" line.long 0x4 "DDR0,DSPI DSI Deserialization Data Register 0" hexmask.long 0x4 0.--31. 1. "DESER_DATA,Deserialized Data" group.long 0xD0++0x1F line.long 0x0 "DSICR1,DSPI DSI Configuration Register 1" hexmask.long.byte 0x0 24.--29. 1. "TSBCNT,Timed Serial Bus Operation Count" bitfld.long 0x0 18. "DSI64E,DSI 64-bit Mode Enable" "0: Disabled. DSI Mode operates in the default..,1: Enabled. DSI Mode operates in 64-bit configuration" newline bitfld.long 0x0 17. "DSE1,Data Select Enable 1" "0: No Zero bit is inserted in the middle of the..,1: Zero bit is inserted at the middle of the data.." bitfld.long 0x0 16. "DSE0,Data Select Enable 0" "0: No Zero bit is inserted in the beginning of the..,1: Zero bit is inserted at the beginning of the.." newline hexmask.long.byte 0x0 8.--15. 1. "TRGPRD,Internal Trigger Period for the ITSB mode." hexmask.long.byte 0x0 0.--7. 1. "DPCS1_X,DSI Peripheral Chip Select 07" line.long 0x4 "SSR0,DSPI DSI Serialization Source Select Register 0" hexmask.long 0x4 0.--31. 1. "SS,Source Select" line.long 0x8 "PISR0,DSPI DSI Parallel Input Select Register 0" hexmask.long.byte 0x8 28.--31. 1. "IPS7,Input Pin Select 7" hexmask.long.byte 0x8 24.--27. 1. "IPS6,Input Pin Select 6" newline hexmask.long.byte 0x8 20.--23. 1. "IPS5,Input Pin Select 5" hexmask.long.byte 0x8 16.--19. 1. "IPS4,Input Pin Select 5" newline hexmask.long.byte 0x8 12.--15. 1. "IPS3,Input Pin Select 3" hexmask.long.byte 0x8 8.--11. 1. "IPS2,Input Pin Select 2" newline hexmask.long.byte 0x8 4.--7. 1. "IPS1,Input Pin Select 1" hexmask.long.byte 0x8 0.--3. 1. "IPS0,Input Pin Select 0" line.long 0xC "PISR1,DSPI DSI Parallel Input Select Register 1" hexmask.long.byte 0xC 28.--31. 1. "IPS15,Input Pin Select 15" hexmask.long.byte 0xC 24.--27. 1. "IPS14,Input Pin Select 14" newline hexmask.long.byte 0xC 20.--23. 1. "IPS13,Input Pin Select 13" hexmask.long.byte 0xC 16.--19. 1. "IPS12,Input Pin Select 12" newline hexmask.long.byte 0xC 12.--15. 1. "IPS11,Input Pin Select 11" hexmask.long.byte 0xC 8.--11. 1. "IPS10,Input Pin Select 10" newline hexmask.long.byte 0xC 4.--7. 1. "IPS9,Input Pin Select 9" hexmask.long.byte 0xC 0.--3. 1. "IPS8,Input Pin Select 8" line.long 0x10 "PISR2,DSPI DSI Parallel Input Select Register 2" hexmask.long.byte 0x10 28.--31. 1. "IPS23,Input Pin Select 23" hexmask.long.byte 0x10 24.--27. 1. "IPS22,Input Pin Select 22" newline hexmask.long.byte 0x10 20.--23. 1. "IPS21,Input Pin Select 21" hexmask.long.byte 0x10 16.--19. 1. "IPS20,Input Pin Select 20" newline hexmask.long.byte 0x10 12.--15. 1. "IPS19,Input Pin Select 19" hexmask.long.byte 0x10 8.--11. 1. "IPS18,Input Pin Select 18" newline hexmask.long.byte 0x10 4.--7. 1. "IPS17,Input Pin Select 17" hexmask.long.byte 0x10 0.--3. 1. "IPS16,Input Pin Select 16" line.long 0x14 "PISR3,DSPI DSI Parallel Input Select Register 3" hexmask.long.byte 0x14 28.--31. 1. "IPS31,Input Pin Select 31" hexmask.long.byte 0x14 24.--27. 1. "IPS30,Input Pin Select 30" newline hexmask.long.byte 0x14 20.--23. 1. "IPS29,Input Pin Select 29" hexmask.long.byte 0x14 16.--19. 1. "IPS28,Input Pin Select 28" newline hexmask.long.byte 0x14 12.--15. 1. "IPS27,Input Pin Select 27" hexmask.long.byte 0x14 8.--11. 1. "IPS26,Input Pin Select 26" newline hexmask.long.byte 0x14 4.--7. 1. "IPS25,Input Pin Select 25" hexmask.long.byte 0x14 0.--3. 1. "IPS24,Input Pin Select 24" line.long 0x18 "DIMR0,DSPI DSI Deserialized Data Interrupt Mask Register 0" hexmask.long 0x18 0.--31. 1. "MASK,Mask" line.long 0x1C "DPIR0,DSPI DSI Deserialized Data Polarity Interrupt Register 0" hexmask.long 0x1C 0.--31. 1. "DP,Data Polarity" rgroup.long 0xF0++0x3 line.long 0x0 "SDR1,DSPI DSI Serialization Data Register 1" hexmask.long 0x0 0.--31. 1. "SER_DATA,Serialized Data" group.long 0xF4++0x3 line.long 0x0 "ASDR1,DSPI DSI Alternate Serialization Data Register 1" hexmask.long 0x0 0.--31. 1. "ASER_DATA,Alternate Serialized Data" rgroup.long 0xF8++0x7 line.long 0x0 "COMPR1,DSPI DSI Transmit Comparison Register 1" hexmask.long 0x0 0.--31. 1. "COMP_DATA,Compare Data" line.long 0x4 "DDR1,DSPI DSI Deserialization Data Register 1" hexmask.long 0x4 0.--31. 1. "DESER_DATA,Deserialized Data" group.long 0x100++0x3B line.long 0x0 "SSR1,DSPI DSI Serialization Source Select Register 1" hexmask.long 0x0 0.--31. 1. "SS,Source Select" line.long 0x4 "PISR4,DSPI DSI Parallel Input Select Register 4" hexmask.long.byte 0x4 28.--31. 1. "IPS39,Input Pin Select 39" hexmask.long.byte 0x4 24.--27. 1. "IPS38,Input Pin Select 38" newline hexmask.long.byte 0x4 20.--23. 1. "IPS37,Input Pin Select 37" hexmask.long.byte 0x4 16.--19. 1. "IPS36,Input Pin Select 36" newline hexmask.long.byte 0x4 12.--15. 1. "IPS35,Input Pin Select 35" hexmask.long.byte 0x4 8.--11. 1. "IPS34,Input Pin Select 34" newline hexmask.long.byte 0x4 4.--7. 1. "IPS33,Input Pin Select 33" hexmask.long.byte 0x4 0.--3. 1. "IPS32,Input Pin Select 32" line.long 0x8 "PISR5,DSPI DSI Parallel Input Select Register 5" hexmask.long.byte 0x8 28.--31. 1. "IPS47,Input Pin Select 47" hexmask.long.byte 0x8 24.--27. 1. "IPS46,Input Pin Select 46" newline hexmask.long.byte 0x8 20.--23. 1. "IPS45,Input Pin Select 45" hexmask.long.byte 0x8 16.--19. 1. "IPS44,Input Pin Select 44" newline hexmask.long.byte 0x8 12.--15. 1. "IPS43,Input Pin Select 43" hexmask.long.byte 0x8 8.--11. 1. "IPS42,Input Pin Select 42" newline hexmask.long.byte 0x8 4.--7. 1. "IPS41,Input Pin Select 41" hexmask.long.byte 0x8 0.--3. 1. "IPS40,Input Pin Select 40" line.long 0xC "PISR6,DSPI DSI Parallel Input Select Register 6" hexmask.long.byte 0xC 28.--31. 1. "IPS55,Input Pin Select 55" hexmask.long.byte 0xC 24.--27. 1. "IPS54,Input Pin Select 54" newline hexmask.long.byte 0xC 20.--23. 1. "IPS53,Input Pin Select 53" hexmask.long.byte 0xC 16.--19. 1. "IPS52,Input Pin Select 52" newline hexmask.long.byte 0xC 12.--15. 1. "IPS51,Input Pin Select 51" hexmask.long.byte 0xC 8.--11. 1. "IPS50,Input Pin Select 50" newline hexmask.long.byte 0xC 4.--7. 1. "IPS49,Input Pin Select 49" hexmask.long.byte 0xC 0.--3. 1. "IPS48,Input Pin Select 48" line.long 0x10 "PISR7,DSPI DSI Parallel Input Select Register 7" hexmask.long.byte 0x10 28.--31. 1. "IPS63,Input Pin Select 63" hexmask.long.byte 0x10 24.--27. 1. "IPS62,Input Pin Select 62" newline hexmask.long.byte 0x10 20.--23. 1. "IPS61,Input Pin Select 61" hexmask.long.byte 0x10 16.--19. 1. "IPS60,Input Pin Select 60" newline hexmask.long.byte 0x10 12.--15. 1. "IPS59,Input Pin Select 59" hexmask.long.byte 0x10 8.--11. 1. "IPS58,Input Pin Select 58" newline hexmask.long.byte 0x10 4.--7. 1. "IPS57,Input Pin Select 57" hexmask.long.byte 0x10 0.--3. 1. "IPS56,Input Pin Select 56" line.long 0x14 "DIMR1,DSPI DSI Deserialized Data Interrupt Mask Register 1" hexmask.long 0x14 0.--31. 1. "MASK,Mask" line.long 0x18 "DPIR1,DSPI DSI Deserialized Data Polarity Interrupt Register 1" hexmask.long 0x18 0.--31. 1. "DP,Data Polarity" line.long 0x1C "CTARE0,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x1C 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x1C 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x20 "CTARE1,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x20 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x20 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x24 "CTARE2,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x24 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x24 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x28 "CTARE3,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x28 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x28 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x2C "CTARE4,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x2C 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x2C 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x30 "CTARE5,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x30 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x30 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x34 "CTARE6,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x34 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x34 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x38 "CTARE7,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x38 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x38 0.--10. 1. "DTCP,Data Transfer Count Preload" rgroup.long 0x13C++0x3 line.long 0x0 "SREX,DSPI Status Register Extended" hexmask.long.byte 0x0 4.--7. 1. "CMDCTR,CMD FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "CMDNXTPTR,Command Next Pointer" tree.end tree "DSPI_1" base ad:0x71A8C000 group.long 0x0++0x3 line.long 0x0 "MCR,DSPI Module Configuration Register" bitfld.long 0x0 31. "MSTR,Master/Slave Mode Select" "0: DSPI is in slave mode.,1: DSPI is in master mode." bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK Enable" "0: Continuous SCK disabled.,1: Continuous SCK enabled." newline bitfld.long 0x0 28.--29. "DCONF,DSPI Configuration" "0: SPI,1: DSI,2: CSI,?" bitfld.long 0x0 27. "FRZ,Freeze" "0: Do not halt serial transfers in debug mode.,1: Halt serial transfers in debug mode." newline bitfld.long 0x0 26. "MTFE,Modified Timing Format Enable" "0: Modified SPI transfer format disabled.,1: Modified SPI transfer format enabled." bitfld.long 0x0 25. "PCSSE,Peripheral Chip Select Strobe Enable" "0: PCS[5]/PCSS is used as the Peripheral Chip..,1: PCS[5]/PCSS is used as an active-low PCS Strobe.." newline bitfld.long 0x0 24. "ROOE,Receive FIFO Overflow Overwrite Enable" "0: Incoming data is ignored.,1: Incoming data is shifted into the shift register." bitfld.long 0x0 23. "PCSIS7,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 22. "PCSIS6,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 21. "PCSIS5,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 20. "PCSIS4,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 19. "PCSIS3,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 18. "PCSIS2,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 17. "PCSIS1,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 16. "PCSIS0,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 14. "MDIS,Module Disable" "0: Enable DSPI clocks.,1: Allow external logic to disable DSPI clocks." newline bitfld.long 0x0 13. "DIS_TXF,Disable Transmit FIFO" "0: Tx FIFO is enabled.,1: Tx FIFO is disabled." bitfld.long 0x0 12. "DIS_RXF,Disable Receive FIFO" "0: Rx FIFO is enabled.,1: Rx FIFO is disabled." newline bitfld.long 0x0 11. "CLR_TXF,Clear TX FIFO" "0: Do not clear the Tx FIFO and CMD FIFO counters.,1: Clears the Tx FIFO and CMD FIFO counters." bitfld.long 0x0 10. "CLR_RXF,Clear RX FIFO" "0: Do not clear the Rx FIFO counter.,1: Clear the Rx FIFO counter." newline bitfld.long 0x0 8.--9. "SMPL_PT,Sample Point" "0: 0 protocol clocks between SCK edge and SIN sample,1: 1 protocol clock between SCK edge and SIN sample,2: 2 protocol clocks between SCK edge and SIN sample,?" bitfld.long 0x0 3. "XSPI,Extended SPI Mode" "0: Normal SPI Mode. Up to 16-bit Frames. Command..,1: Extended SPI Mode. Up to 32-bit SPI Frames." newline bitfld.long 0x0 2. "FCPCS,Fast Continuous PCS Mode." "0: Normal or Slow Continuous PCS mode. Masking of..,1: Fast Continuous PCS mode. Delays masked via.." bitfld.long 0x0 1. "PES,Parity Error Stop" "0: SPI frame transmission continues.,1: SPI frame transmission stops." newline bitfld.long 0x0 0. "HALT,Halt" "0: Start transfers.,1: Stop transfers." rgroup.long 0x4++0x3 line.long 0x0 "HCR,Hardware Configuration Register" bitfld.long 0x0 31. "DSI,DSI features are implemented for the module." "0: DSI features are not implemented DSI registers..,1: DSI features are implemented" bitfld.long 0x0 30. "PISR,PISR0-3 and parallel inputs frame positions selection logic (DSI Muxing Logic) are implemented for the module." "0: PISR0-3 registers are not implemented.,1: PISR0-3 registers are implemented." newline bitfld.long 0x0 29. "DSI64,DSI features in 64 bit mode are implemented for the module." "0: DSI features for 64 bit mode are not..,1: DSI features for 64 bit mode are implemented" bitfld.long 0x0 28. "PISR_EX,PISR4-7 and parallel inputs frame positions selection logic (DSI 64 bit Muxing Logic) are implemented for the module." "0: PISR4-7 registers are not implemented.,1: PISR4-7 registers are implemented." newline bitfld.long 0x0 27. "XSPI,Extended SPI Mode feature is implemented for the module." "0: Extended SPI Mode is not implemented.,1: Extended SPI Mode is implemented." bitfld.long 0x0 24.--26. "CTAR,Maximum implemented CTAR register number." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 20.--23. 1. "TXFR,Maximum implemented TXFR register number." hexmask.long.byte 0x0 16.--19. 1. "RXFR,Maximum implemented RXFR register number." newline hexmask.long.byte 0x0 12.--15. 1. "CMDFR,Maximum implemented command FIFO number." bitfld.long 0x0 11. "MSTR_MODE,Master Mode implementation is enabled" "0,1" newline bitfld.long 0x0 10. "SLV_MODE,Slave Mode implementation is enabled" "0,1" bitfld.long 0x0 9. "TSB_EN,TSB Mode implementation is enabled" "0,1" newline bitfld.long 0x0 8. "ITSB_EN,Interleaved TSB Mode implementation is enabled" "0,1" group.long 0x8++0x7 line.long 0x0 "TCR,DSPI Transfer Count Register" hexmask.long.word 0x0 16.--31. 1. "SPI_TCNT,SPI Transfer Counter" line.long 0x4 "CTAR0,DSPI Clock and Transfer Attributes Register 0 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" group.long 0xC++0x7 line.long 0x0 "CTAR0_SLAVE,When the DSPI is configured as:SPI master - the CTAS field in the command portion of the TX FIFO entry selects which CTAR is used.SPI bus slave - the CTAR0 register is used.DSI master - the DSICTAS field in the DSPI DSI Configuration Register.." hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." bitfld.long 0x0 22. "FMSZ5,MSB of Frame Size when DSI is used in 64-bit Mode" "0,1" line.long 0x4 "CTAR1,DSPI Clock and Transfer Attributes Register 1 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" group.long 0x10++0x27 line.long 0x0 "CTAR1_SLAVE,When the DSPI is configured as:SPI master - the CTAS field in the command portion of the TX FIFO entry selects which CTAR is used.SPI bus slave - the CTAR0 register is used.DSI master - the DSICTAS field in the DSPI DSI Configuration Register.." hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." bitfld.long 0x0 22. "FMSZ5,MSB of Frame Size when DSI is used in 64-bit Mode" "0,1" line.long 0x4 "CTAR2,DSPI Clock and Transfer Attributes Register 2 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x8 "CTAR3,DSPI Clock and Transfer Attributes Register 3 (In Master Mode)" bitfld.long 0x8 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x8 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x8 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x8 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x8 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x8 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x8 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x8 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x8 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x8 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x8 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x8 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x8 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0xC "CTAR4,DSPI Clock and Transfer Attributes Register 4 (In Master Mode)" bitfld.long 0xC 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0xC 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0xC 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0xC 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0xC 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0xC 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0xC 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0xC 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0xC 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0xC 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0xC 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0xC 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x10 "CTAR5,DSPI Clock and Transfer Attributes Register 5 (In Master Mode)" bitfld.long 0x10 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x10 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x10 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x10 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x10 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x10 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x10 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x10 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x10 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x10 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x10 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x10 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x10 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x14 "CTAR6,DSPI Clock and Transfer Attributes Register 6 (In Master Mode)" bitfld.long 0x14 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x14 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x14 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x14 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x14 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x14 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x14 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x14 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x14 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x14 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x14 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x14 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x18 "CTAR7,DSPI Clock and Transfer Attributes Register 7 (In Master Mode)" bitfld.long 0x18 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x18 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x18 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x18 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x18 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x18 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x18 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x18 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x18 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x18 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x18 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x18 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x18 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x1C "SR,DSPI Status Register" bitfld.long 0x1C 31. "TCF,Transfer Complete Flag." "0: Transfer not complete.,1: Transfer complete." bitfld.long 0x1C 30. "TXRXS,TX and RX Status." "0: Transmit and receive operations are disabled..,1: Transmit and receive operations are enabled.." newline bitfld.long 0x1C 29. "SPITCF,SPI Frame Transfer Complete Flag." "0: SPI frame transfer is not complete.,1: SPI frame transfer is complete." bitfld.long 0x1C 28. "EOQF,End of Queue Flag." "0: EOQ is not set in the executing command.,1: EOQ is set in the executing SPI command." newline bitfld.long 0x1C 27. "TFUF,Transmit FIFO Underflow Flag." "0: No Tx FIFO underflow.,1: Tx FIFO underflow has occurred." bitfld.long 0x1C 26. "DSITCF,DSI Frame Transfer Complete Flag." "0: DSI frame transfer is not complete.,1: DSI frame transfer is complete." newline bitfld.long 0x1C 25. "TFFF,Transmit FIFO Fill Flag." "0: Tx FIFO is full.,1: Tx FIFO is not full." bitfld.long 0x1C 24. "BSYF,Busy Flag." "0: No Cyclic Command Transfer in Progress.,1: Cyclic Command Transfer is in progress. Current.." newline bitfld.long 0x1C 23. "CMDTCF,Command Transfer Complete Flag." "0: Data Transfer by current Command not complete.,1: Data Transfer by current Command complete." bitfld.long 0x1C 22. "DPEF,DSI Parity Error Flag." "0: No parity error.,1: Parity error has occurred." newline bitfld.long 0x1C 21. "SPEF,SPI Parity Error Flag." "0: No parity error.,1: Parity error has occurred." bitfld.long 0x1C 20. "DDIF,DSI Data Received with Active Bits." "0: No DSI data with active bits was received.,1: DSI data with active bits was received." newline bitfld.long 0x1C 19. "RFOF,Receive FIFO Overflow Flag." "0: No Rx FIFO overflow.,1: Rx FIFO overflow has occurred." bitfld.long 0x1C 18. "TFIWF,Transmit FIFO Invalid Write Flag." "0: No Invalid Data present in TX FIFO,1: Invalid Data present in TX FIFO since CMD FIFO.." newline bitfld.long 0x1C 17. "RFDF,Receive FIFO Drain Flag." "0: Rx FIFO is empty.,1: Rx FIFO is not empty." bitfld.long 0x1C 16. "CMDFFF,Command FIFO Fill Flag." "0: CMD FIFO is full.,1: CMD FIFO is not full." newline hexmask.long.byte 0x1C 12.--15. 1. "TXCTR,TX FIFO Counter." hexmask.long.byte 0x1C 8.--11. 1. "TXNXTPTR,Transmit Next Pointer." newline hexmask.long.byte 0x1C 4.--7. 1. "RXCTR,RX FIFO Counter." hexmask.long.byte 0x1C 0.--3. 1. "POPNXTPTR,Pop Next Pointer." line.long 0x20 "RSER,DSPI DMA/Interrupt Request Select and Enable Register" bitfld.long 0x20 31. "TCF_RE,Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 30. "CMDFFF_RE,Command FIFO Fill Flag Request Enable." "0: Disabled.,1: Enabled." newline bitfld.long 0x20 29. "SPITCF_RE,SPI Frame Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 28. "EOQF_RE,DSPI Finished Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 27. "TFUF_RE,Transmit FIFO Underflow Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 26. "DSITCF_RE,DSI Frame Transmission Complete Request Enable." "0: Disabled.,1: Enabled." newline bitfld.long 0x20 25. "TFFF_RE,Transmit FIFO Fill Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 24. "TFFF_DIRS,Transmit FIFO Fill DMA or Interrupt Request Select" "0: Interrupt requests.,1: DMA requests." newline bitfld.long 0x20 23. "CMDTCF_RE,Command Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 22. "DPEF_RE,DSI Parity Error Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 21. "SPEF_RE,SPI Parity Error Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 20. "DDIF_RE,DSI data received with active bits Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 19. "RFOF_RE,Receive FIFO Overflow Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 18. "TFIWF_RE,Transmit FIFO Invalid Write Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 17. "RFDF_RE,Receive FIFO Drain Request Enable" "0: Disabled,1: Enabled" bitfld.long 0x20 16. "RFDF_DIRS,Receive FIFO Drain DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." newline bitfld.long 0x20 15. "CMDFFF_DIRS,Command FIFO FIll DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." bitfld.long 0x20 14. "DDIF_DIRS,DSI data received with active bits - DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." line.long 0x24 "PUSHR,DSPI PUSH FIFO Register In Master mode" bitfld.long 0x24 31. "CONT,Continuous Peripheral Chip Select Enable. (SPI master mode)" "0: Return PCSn signals to their inactive state..,1: Keep PCSn signals asserted between transfers." bitfld.long 0x24 28.--30. "CTAS,Clock and Transfer Attributes Select." "0: CTAR0/CTARE0,1: CTAR1/CTARE1,2: CTAR2/CTARE2,3: CTAR3/CTARE3,4: CTAR4/CTARE4,5: CTAR5/CTARE5,6: CTAR6/CTARE6,7: CTAR7/CTARE7" newline bitfld.long 0x24 27. "EOQ,End Of Queue" "0: The SPI data is not the last data to transfer.,1: The SPI data is the last data to transfer." bitfld.long 0x24 26. "CTCNT,Clear Transfer Counter." "0: Do not clear the TCR[SPI_TCNT] field.,1: Clear the TCR[SPI_TCNT] field." newline bitfld.long 0x24 25. "PE_MASC,Parity Enable or Mask tASC delay in the current frame" "0: PE: No parity bit included/checked. MASC: tASC..,1: PE: Parity bit is transmitted instead of the.." bitfld.long 0x24 24. "PP_MCSC,Parity Polarity or Mask tCSC delay in the next frame" "0: PP: Even Parity: the number of 1 bits in the..,1: PP: Odd Parity: the number of 1 bits in the.." newline hexmask.long.byte 0x24 16.--23. 1. "PCS,Select which PCS signals are to be asserted for the transfer." hexmask.long.word 0x24 0.--15. 1. "TXDATA,Transmit Data" group.long 0x34++0x3 line.long 0x0 "PUSHR_SLAVE,PUSHR provides the means to write to the TX FIFO.Data written to this register is transferred to:The TX FIFO for 8- or 16-bit writes to the Data field of PUSHR.In master mode. the register provides 16-bit command to the CMD FIFO and 16-bit.." hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x38++0x13 line.long 0x0 "POPR,DSPI POP FIFO Register" hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data" line.long 0x4 "TXFR0,DSPI Transmit FIFO Registers" hexmask.long.word 0x4 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x4 0.--15. 1. "TXDATA,Transmit Data" line.long 0x8 "TXFR1,DSPI Transmit FIFO Registers" hexmask.long.word 0x8 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x8 0.--15. 1. "TXDATA,Transmit Data" line.long 0xC "TXFR2,DSPI Transmit FIFO Registers" hexmask.long.word 0xC 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0xC 0.--15. 1. "TXDATA,Transmit Data" line.long 0x10 "TXFR3,DSPI Transmit FIFO Registers" hexmask.long.word 0x10 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x10 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x7C++0xF line.long 0x0 "RXFR0,DSPI Receive FIFO Registers" hexmask.long 0x0 0.--31. 1. "RXDATA,Receive Data" line.long 0x4 "RXFR1,DSPI Receive FIFO Registers" hexmask.long 0x4 0.--31. 1. "RXDATA,Receive Data" line.long 0x8 "RXFR2,DSPI Receive FIFO Registers" hexmask.long 0x8 0.--31. 1. "RXDATA,Receive Data" line.long 0xC "RXFR3,DSPI Receive FIFO Registers" hexmask.long 0xC 0.--31. 1. "RXDATA,Receive Data" group.long 0xBC++0x3 line.long 0x0 "DSICR0,DSPI DSI Configuration Register 0" bitfld.long 0x0 30. "FMSZ4,MSB of the frame size in master mode when DSI is used in 32-bit mode." "0,1" bitfld.long 0x0 23. "FMSZ5,MSB of the frame size in master mode when DSI is used in 64-bit mode." "0,1" newline bitfld.long 0x0 21. "ITSB,Interleaved TSB mode." "0: Disabled.,1: Enabled." bitfld.long 0x0 20. "TSBC,Timed Serial Bus Configuration." "0: Disabled.,1: Enabled." newline bitfld.long 0x0 19. "TXSS,Transmit Data Source Select." "0: SDR source.,1: ASDR source." bitfld.long 0x0 18. "TPOL,Trigger Polarity" "0: Falling edge initiates a transfer.,1: Rising edge initiates a transfer." newline bitfld.long 0x0 16. "CID,Change In Data Transfer Enable" "0: Disabled.,1: Enabled." bitfld.long 0x0 15. "DCONT,DSI Continuous Peripheral Chip Select Enable (DSI Master mode only)" "0: PCS signals return to inactive.,1: PCS signals remain asserted." newline bitfld.long 0x0 12.--14. "DSICTAS,DSI Clock and Transfer Attributes Select (DSI Master mode only)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "DMS,Data Match Stop" "0: Disabled.,1: Enabled." newline bitfld.long 0x0 10. "PES,Parity Error Stop" "0: Disabled.,1: Enabled." bitfld.long 0x0 9. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of the last.." newline bitfld.long 0x0 8. "PP,Parity Polarity" "0: Even Parity: the number of '1' bits in the..,1: Odd Parity: the number of 1 bits in the.." hexmask.long.byte 0x0 0.--7. 1. "DPCSX,DSI Peripheral Chip Select 07" rgroup.long 0xC0++0x3 line.long 0x0 "SDR0,DSPI DSI Serialization Data Register 0" hexmask.long 0x0 0.--31. 1. "SER_DATA,Serialized Data" group.long 0xC4++0x3 line.long 0x0 "ASDR0,DSPI DSI Alternate Serialization Data Register 0" hexmask.long 0x0 0.--31. 1. "ASER_DATA,Alternate Serialized Data" rgroup.long 0xC8++0x7 line.long 0x0 "COMPR0,DSPI DSI Transmit Comparison Register 0" hexmask.long 0x0 0.--31. 1. "COMP_DATA,Compare Data" line.long 0x4 "DDR0,DSPI DSI Deserialization Data Register 0" hexmask.long 0x4 0.--31. 1. "DESER_DATA,Deserialized Data" group.long 0xD0++0x1F line.long 0x0 "DSICR1,DSPI DSI Configuration Register 1" hexmask.long.byte 0x0 24.--29. 1. "TSBCNT,Timed Serial Bus Operation Count" bitfld.long 0x0 18. "DSI64E,DSI 64-bit Mode Enable" "0: Disabled. DSI Mode operates in the default..,1: Enabled. DSI Mode operates in 64-bit configuration" newline bitfld.long 0x0 17. "DSE1,Data Select Enable 1" "0: No Zero bit is inserted in the middle of the..,1: Zero bit is inserted at the middle of the data.." bitfld.long 0x0 16. "DSE0,Data Select Enable 0" "0: No Zero bit is inserted in the beginning of the..,1: Zero bit is inserted at the beginning of the.." newline hexmask.long.byte 0x0 8.--15. 1. "TRGPRD,Internal Trigger Period for the ITSB mode." hexmask.long.byte 0x0 0.--7. 1. "DPCS1_X,DSI Peripheral Chip Select 07" line.long 0x4 "SSR0,DSPI DSI Serialization Source Select Register 0" hexmask.long 0x4 0.--31. 1. "SS,Source Select" line.long 0x8 "PISR0,DSPI DSI Parallel Input Select Register 0" hexmask.long.byte 0x8 28.--31. 1. "IPS7,Input Pin Select 7" hexmask.long.byte 0x8 24.--27. 1. "IPS6,Input Pin Select 6" newline hexmask.long.byte 0x8 20.--23. 1. "IPS5,Input Pin Select 5" hexmask.long.byte 0x8 16.--19. 1. "IPS4,Input Pin Select 5" newline hexmask.long.byte 0x8 12.--15. 1. "IPS3,Input Pin Select 3" hexmask.long.byte 0x8 8.--11. 1. "IPS2,Input Pin Select 2" newline hexmask.long.byte 0x8 4.--7. 1. "IPS1,Input Pin Select 1" hexmask.long.byte 0x8 0.--3. 1. "IPS0,Input Pin Select 0" line.long 0xC "PISR1,DSPI DSI Parallel Input Select Register 1" hexmask.long.byte 0xC 28.--31. 1. "IPS15,Input Pin Select 15" hexmask.long.byte 0xC 24.--27. 1. "IPS14,Input Pin Select 14" newline hexmask.long.byte 0xC 20.--23. 1. "IPS13,Input Pin Select 13" hexmask.long.byte 0xC 16.--19. 1. "IPS12,Input Pin Select 12" newline hexmask.long.byte 0xC 12.--15. 1. "IPS11,Input Pin Select 11" hexmask.long.byte 0xC 8.--11. 1. "IPS10,Input Pin Select 10" newline hexmask.long.byte 0xC 4.--7. 1. "IPS9,Input Pin Select 9" hexmask.long.byte 0xC 0.--3. 1. "IPS8,Input Pin Select 8" line.long 0x10 "PISR2,DSPI DSI Parallel Input Select Register 2" hexmask.long.byte 0x10 28.--31. 1. "IPS23,Input Pin Select 23" hexmask.long.byte 0x10 24.--27. 1. "IPS22,Input Pin Select 22" newline hexmask.long.byte 0x10 20.--23. 1. "IPS21,Input Pin Select 21" hexmask.long.byte 0x10 16.--19. 1. "IPS20,Input Pin Select 20" newline hexmask.long.byte 0x10 12.--15. 1. "IPS19,Input Pin Select 19" hexmask.long.byte 0x10 8.--11. 1. "IPS18,Input Pin Select 18" newline hexmask.long.byte 0x10 4.--7. 1. "IPS17,Input Pin Select 17" hexmask.long.byte 0x10 0.--3. 1. "IPS16,Input Pin Select 16" line.long 0x14 "PISR3,DSPI DSI Parallel Input Select Register 3" hexmask.long.byte 0x14 28.--31. 1. "IPS31,Input Pin Select 31" hexmask.long.byte 0x14 24.--27. 1. "IPS30,Input Pin Select 30" newline hexmask.long.byte 0x14 20.--23. 1. "IPS29,Input Pin Select 29" hexmask.long.byte 0x14 16.--19. 1. "IPS28,Input Pin Select 28" newline hexmask.long.byte 0x14 12.--15. 1. "IPS27,Input Pin Select 27" hexmask.long.byte 0x14 8.--11. 1. "IPS26,Input Pin Select 26" newline hexmask.long.byte 0x14 4.--7. 1. "IPS25,Input Pin Select 25" hexmask.long.byte 0x14 0.--3. 1. "IPS24,Input Pin Select 24" line.long 0x18 "DIMR0,DSPI DSI Deserialized Data Interrupt Mask Register 0" hexmask.long 0x18 0.--31. 1. "MASK,Mask" line.long 0x1C "DPIR0,DSPI DSI Deserialized Data Polarity Interrupt Register 0" hexmask.long 0x1C 0.--31. 1. "DP,Data Polarity" rgroup.long 0xF0++0x3 line.long 0x0 "SDR1,DSPI DSI Serialization Data Register 1" hexmask.long 0x0 0.--31. 1. "SER_DATA,Serialized Data" group.long 0xF4++0x3 line.long 0x0 "ASDR1,DSPI DSI Alternate Serialization Data Register 1" hexmask.long 0x0 0.--31. 1. "ASER_DATA,Alternate Serialized Data" rgroup.long 0xF8++0x7 line.long 0x0 "COMPR1,DSPI DSI Transmit Comparison Register 1" hexmask.long 0x0 0.--31. 1. "COMP_DATA,Compare Data" line.long 0x4 "DDR1,DSPI DSI Deserialization Data Register 1" hexmask.long 0x4 0.--31. 1. "DESER_DATA,Deserialized Data" group.long 0x100++0x3B line.long 0x0 "SSR1,DSPI DSI Serialization Source Select Register 1" hexmask.long 0x0 0.--31. 1. "SS,Source Select" line.long 0x4 "PISR4,DSPI DSI Parallel Input Select Register 4" hexmask.long.byte 0x4 28.--31. 1. "IPS39,Input Pin Select 39" hexmask.long.byte 0x4 24.--27. 1. "IPS38,Input Pin Select 38" newline hexmask.long.byte 0x4 20.--23. 1. "IPS37,Input Pin Select 37" hexmask.long.byte 0x4 16.--19. 1. "IPS36,Input Pin Select 36" newline hexmask.long.byte 0x4 12.--15. 1. "IPS35,Input Pin Select 35" hexmask.long.byte 0x4 8.--11. 1. "IPS34,Input Pin Select 34" newline hexmask.long.byte 0x4 4.--7. 1. "IPS33,Input Pin Select 33" hexmask.long.byte 0x4 0.--3. 1. "IPS32,Input Pin Select 32" line.long 0x8 "PISR5,DSPI DSI Parallel Input Select Register 5" hexmask.long.byte 0x8 28.--31. 1. "IPS47,Input Pin Select 47" hexmask.long.byte 0x8 24.--27. 1. "IPS46,Input Pin Select 46" newline hexmask.long.byte 0x8 20.--23. 1. "IPS45,Input Pin Select 45" hexmask.long.byte 0x8 16.--19. 1. "IPS44,Input Pin Select 44" newline hexmask.long.byte 0x8 12.--15. 1. "IPS43,Input Pin Select 43" hexmask.long.byte 0x8 8.--11. 1. "IPS42,Input Pin Select 42" newline hexmask.long.byte 0x8 4.--7. 1. "IPS41,Input Pin Select 41" hexmask.long.byte 0x8 0.--3. 1. "IPS40,Input Pin Select 40" line.long 0xC "PISR6,DSPI DSI Parallel Input Select Register 6" hexmask.long.byte 0xC 28.--31. 1. "IPS55,Input Pin Select 55" hexmask.long.byte 0xC 24.--27. 1. "IPS54,Input Pin Select 54" newline hexmask.long.byte 0xC 20.--23. 1. "IPS53,Input Pin Select 53" hexmask.long.byte 0xC 16.--19. 1. "IPS52,Input Pin Select 52" newline hexmask.long.byte 0xC 12.--15. 1. "IPS51,Input Pin Select 51" hexmask.long.byte 0xC 8.--11. 1. "IPS50,Input Pin Select 50" newline hexmask.long.byte 0xC 4.--7. 1. "IPS49,Input Pin Select 49" hexmask.long.byte 0xC 0.--3. 1. "IPS48,Input Pin Select 48" line.long 0x10 "PISR7,DSPI DSI Parallel Input Select Register 7" hexmask.long.byte 0x10 28.--31. 1. "IPS63,Input Pin Select 63" hexmask.long.byte 0x10 24.--27. 1. "IPS62,Input Pin Select 62" newline hexmask.long.byte 0x10 20.--23. 1. "IPS61,Input Pin Select 61" hexmask.long.byte 0x10 16.--19. 1. "IPS60,Input Pin Select 60" newline hexmask.long.byte 0x10 12.--15. 1. "IPS59,Input Pin Select 59" hexmask.long.byte 0x10 8.--11. 1. "IPS58,Input Pin Select 58" newline hexmask.long.byte 0x10 4.--7. 1. "IPS57,Input Pin Select 57" hexmask.long.byte 0x10 0.--3. 1. "IPS56,Input Pin Select 56" line.long 0x14 "DIMR1,DSPI DSI Deserialized Data Interrupt Mask Register 1" hexmask.long 0x14 0.--31. 1. "MASK,Mask" line.long 0x18 "DPIR1,DSPI DSI Deserialized Data Polarity Interrupt Register 1" hexmask.long 0x18 0.--31. 1. "DP,Data Polarity" line.long 0x1C "CTARE0,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x1C 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x1C 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x20 "CTARE1,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x20 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x20 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x24 "CTARE2,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x24 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x24 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x28 "CTARE3,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x28 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x28 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x2C "CTARE4,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x2C 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x2C 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x30 "CTARE5,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x30 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x30 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x34 "CTARE6,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x34 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x34 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x38 "CTARE7,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x38 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x38 0.--10. 1. "DTCP,Data Transfer Count Preload" rgroup.long 0x13C++0x3 line.long 0x0 "SREX,DSPI Status Register Extended" hexmask.long.byte 0x0 4.--7. 1. "CMDCTR,CMD FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "CMDNXTPTR,Command Next Pointer" tree.end tree "DSPI_2" base ad:0x71A90000 group.long 0x0++0x3 line.long 0x0 "MCR,DSPI Module Configuration Register" bitfld.long 0x0 31. "MSTR,Master/Slave Mode Select" "0: DSPI is in slave mode.,1: DSPI is in master mode." bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK Enable" "0: Continuous SCK disabled.,1: Continuous SCK enabled." newline bitfld.long 0x0 28.--29. "DCONF,DSPI Configuration" "0: SPI,1: DSI,2: CSI,?" bitfld.long 0x0 27. "FRZ,Freeze" "0: Do not halt serial transfers in debug mode.,1: Halt serial transfers in debug mode." newline bitfld.long 0x0 26. "MTFE,Modified Timing Format Enable" "0: Modified SPI transfer format disabled.,1: Modified SPI transfer format enabled." bitfld.long 0x0 25. "PCSSE,Peripheral Chip Select Strobe Enable" "0: PCS[5]/PCSS is used as the Peripheral Chip..,1: PCS[5]/PCSS is used as an active-low PCS Strobe.." newline bitfld.long 0x0 24. "ROOE,Receive FIFO Overflow Overwrite Enable" "0: Incoming data is ignored.,1: Incoming data is shifted into the shift register." bitfld.long 0x0 23. "PCSIS7,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 22. "PCSIS6,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 21. "PCSIS5,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 20. "PCSIS4,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 19. "PCSIS3,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 18. "PCSIS2,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 17. "PCSIS1,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 16. "PCSIS0,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 14. "MDIS,Module Disable" "0: Enable DSPI clocks.,1: Allow external logic to disable DSPI clocks." newline bitfld.long 0x0 13. "DIS_TXF,Disable Transmit FIFO" "0: Tx FIFO is enabled.,1: Tx FIFO is disabled." bitfld.long 0x0 12. "DIS_RXF,Disable Receive FIFO" "0: Rx FIFO is enabled.,1: Rx FIFO is disabled." newline bitfld.long 0x0 11. "CLR_TXF,Clear TX FIFO" "0: Do not clear the Tx FIFO and CMD FIFO counters.,1: Clears the Tx FIFO and CMD FIFO counters." bitfld.long 0x0 10. "CLR_RXF,Clear RX FIFO" "0: Do not clear the Rx FIFO counter.,1: Clear the Rx FIFO counter." newline bitfld.long 0x0 8.--9. "SMPL_PT,Sample Point" "0: 0 protocol clocks between SCK edge and SIN sample,1: 1 protocol clock between SCK edge and SIN sample,2: 2 protocol clocks between SCK edge and SIN sample,?" bitfld.long 0x0 3. "XSPI,Extended SPI Mode" "0: Normal SPI Mode. Up to 16-bit Frames. Command..,1: Extended SPI Mode. Up to 32-bit SPI Frames." newline bitfld.long 0x0 2. "FCPCS,Fast Continuous PCS Mode." "0: Normal or Slow Continuous PCS mode. Masking of..,1: Fast Continuous PCS mode. Delays masked via.." bitfld.long 0x0 1. "PES,Parity Error Stop" "0: SPI frame transmission continues.,1: SPI frame transmission stops." newline bitfld.long 0x0 0. "HALT,Halt" "0: Start transfers.,1: Stop transfers." rgroup.long 0x4++0x3 line.long 0x0 "HCR,Hardware Configuration Register" bitfld.long 0x0 31. "DSI,DSI features are implemented for the module." "0: DSI features are not implemented DSI registers..,1: DSI features are implemented" bitfld.long 0x0 30. "PISR,PISR0-3 and parallel inputs frame positions selection logic (DSI Muxing Logic) are implemented for the module." "0: PISR0-3 registers are not implemented.,1: PISR0-3 registers are implemented." newline bitfld.long 0x0 29. "DSI64,DSI features in 64 bit mode are implemented for the module." "0: DSI features for 64 bit mode are not..,1: DSI features for 64 bit mode are implemented" bitfld.long 0x0 28. "PISR_EX,PISR4-7 and parallel inputs frame positions selection logic (DSI 64 bit Muxing Logic) are implemented for the module." "0: PISR4-7 registers are not implemented.,1: PISR4-7 registers are implemented." newline bitfld.long 0x0 27. "XSPI,Extended SPI Mode feature is implemented for the module." "0: Extended SPI Mode is not implemented.,1: Extended SPI Mode is implemented." bitfld.long 0x0 24.--26. "CTAR,Maximum implemented CTAR register number." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 20.--23. 1. "TXFR,Maximum implemented TXFR register number." hexmask.long.byte 0x0 16.--19. 1. "RXFR,Maximum implemented RXFR register number." newline hexmask.long.byte 0x0 12.--15. 1. "CMDFR,Maximum implemented command FIFO number." bitfld.long 0x0 11. "MSTR_MODE,Master Mode implementation is enabled" "0,1" newline bitfld.long 0x0 10. "SLV_MODE,Slave Mode implementation is enabled" "0,1" bitfld.long 0x0 9. "TSB_EN,TSB Mode implementation is enabled" "0,1" newline bitfld.long 0x0 8. "ITSB_EN,Interleaved TSB Mode implementation is enabled" "0,1" group.long 0x8++0x7 line.long 0x0 "TCR,DSPI Transfer Count Register" hexmask.long.word 0x0 16.--31. 1. "SPI_TCNT,SPI Transfer Counter" line.long 0x4 "CTAR0,DSPI Clock and Transfer Attributes Register 0 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" group.long 0xC++0x7 line.long 0x0 "CTAR0_SLAVE,When the DSPI is configured as:SPI master - the CTAS field in the command portion of the TX FIFO entry selects which CTAR is used.SPI bus slave - the CTAR0 register is used.DSI master - the DSICTAS field in the DSPI DSI Configuration Register.." hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." bitfld.long 0x0 22. "FMSZ5,MSB of Frame Size when DSI is used in 64-bit Mode" "0,1" line.long 0x4 "CTAR1,DSPI Clock and Transfer Attributes Register 1 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" group.long 0x10++0x27 line.long 0x0 "CTAR1_SLAVE,When the DSPI is configured as:SPI master - the CTAS field in the command portion of the TX FIFO entry selects which CTAR is used.SPI bus slave - the CTAR0 register is used.DSI master - the DSICTAS field in the DSPI DSI Configuration Register.." hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." bitfld.long 0x0 22. "FMSZ5,MSB of Frame Size when DSI is used in 64-bit Mode" "0,1" line.long 0x4 "CTAR2,DSPI Clock and Transfer Attributes Register 2 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x8 "CTAR3,DSPI Clock and Transfer Attributes Register 3 (In Master Mode)" bitfld.long 0x8 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x8 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x8 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x8 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x8 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x8 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x8 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x8 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x8 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x8 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x8 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x8 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x8 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0xC "CTAR4,DSPI Clock and Transfer Attributes Register 4 (In Master Mode)" bitfld.long 0xC 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0xC 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0xC 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0xC 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0xC 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0xC 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0xC 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0xC 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0xC 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0xC 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0xC 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0xC 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x10 "CTAR5,DSPI Clock and Transfer Attributes Register 5 (In Master Mode)" bitfld.long 0x10 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x10 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x10 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x10 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x10 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x10 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x10 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x10 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x10 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x10 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x10 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x10 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x10 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x14 "CTAR6,DSPI Clock and Transfer Attributes Register 6 (In Master Mode)" bitfld.long 0x14 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x14 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x14 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x14 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x14 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x14 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x14 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x14 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x14 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x14 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x14 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x14 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x18 "CTAR7,DSPI Clock and Transfer Attributes Register 7 (In Master Mode)" bitfld.long 0x18 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x18 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x18 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x18 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x18 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x18 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x18 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x18 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x18 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x18 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x18 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x18 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x18 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x1C "SR,DSPI Status Register" bitfld.long 0x1C 31. "TCF,Transfer Complete Flag." "0: Transfer not complete.,1: Transfer complete." bitfld.long 0x1C 30. "TXRXS,TX and RX Status." "0: Transmit and receive operations are disabled..,1: Transmit and receive operations are enabled.." newline bitfld.long 0x1C 29. "SPITCF,SPI Frame Transfer Complete Flag." "0: SPI frame transfer is not complete.,1: SPI frame transfer is complete." bitfld.long 0x1C 28. "EOQF,End of Queue Flag." "0: EOQ is not set in the executing command.,1: EOQ is set in the executing SPI command." newline bitfld.long 0x1C 27. "TFUF,Transmit FIFO Underflow Flag." "0: No Tx FIFO underflow.,1: Tx FIFO underflow has occurred." bitfld.long 0x1C 26. "DSITCF,DSI Frame Transfer Complete Flag." "0: DSI frame transfer is not complete.,1: DSI frame transfer is complete." newline bitfld.long 0x1C 25. "TFFF,Transmit FIFO Fill Flag." "0: Tx FIFO is full.,1: Tx FIFO is not full." bitfld.long 0x1C 24. "BSYF,Busy Flag." "0: No Cyclic Command Transfer in Progress.,1: Cyclic Command Transfer is in progress. Current.." newline bitfld.long 0x1C 23. "CMDTCF,Command Transfer Complete Flag." "0: Data Transfer by current Command not complete.,1: Data Transfer by current Command complete." bitfld.long 0x1C 22. "DPEF,DSI Parity Error Flag." "0: No parity error.,1: Parity error has occurred." newline bitfld.long 0x1C 21. "SPEF,SPI Parity Error Flag." "0: No parity error.,1: Parity error has occurred." bitfld.long 0x1C 20. "DDIF,DSI Data Received with Active Bits." "0: No DSI data with active bits was received.,1: DSI data with active bits was received." newline bitfld.long 0x1C 19. "RFOF,Receive FIFO Overflow Flag." "0: No Rx FIFO overflow.,1: Rx FIFO overflow has occurred." bitfld.long 0x1C 18. "TFIWF,Transmit FIFO Invalid Write Flag." "0: No Invalid Data present in TX FIFO,1: Invalid Data present in TX FIFO since CMD FIFO.." newline bitfld.long 0x1C 17. "RFDF,Receive FIFO Drain Flag." "0: Rx FIFO is empty.,1: Rx FIFO is not empty." bitfld.long 0x1C 16. "CMDFFF,Command FIFO Fill Flag." "0: CMD FIFO is full.,1: CMD FIFO is not full." newline hexmask.long.byte 0x1C 12.--15. 1. "TXCTR,TX FIFO Counter." hexmask.long.byte 0x1C 8.--11. 1. "TXNXTPTR,Transmit Next Pointer." newline hexmask.long.byte 0x1C 4.--7. 1. "RXCTR,RX FIFO Counter." hexmask.long.byte 0x1C 0.--3. 1. "POPNXTPTR,Pop Next Pointer." line.long 0x20 "RSER,DSPI DMA/Interrupt Request Select and Enable Register" bitfld.long 0x20 31. "TCF_RE,Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 30. "CMDFFF_RE,Command FIFO Fill Flag Request Enable." "0: Disabled.,1: Enabled." newline bitfld.long 0x20 29. "SPITCF_RE,SPI Frame Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 28. "EOQF_RE,DSPI Finished Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 27. "TFUF_RE,Transmit FIFO Underflow Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 26. "DSITCF_RE,DSI Frame Transmission Complete Request Enable." "0: Disabled.,1: Enabled." newline bitfld.long 0x20 25. "TFFF_RE,Transmit FIFO Fill Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 24. "TFFF_DIRS,Transmit FIFO Fill DMA or Interrupt Request Select" "0: Interrupt requests.,1: DMA requests." newline bitfld.long 0x20 23. "CMDTCF_RE,Command Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 22. "DPEF_RE,DSI Parity Error Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 21. "SPEF_RE,SPI Parity Error Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 20. "DDIF_RE,DSI data received with active bits Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 19. "RFOF_RE,Receive FIFO Overflow Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 18. "TFIWF_RE,Transmit FIFO Invalid Write Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 17. "RFDF_RE,Receive FIFO Drain Request Enable" "0: Disabled,1: Enabled" bitfld.long 0x20 16. "RFDF_DIRS,Receive FIFO Drain DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." newline bitfld.long 0x20 15. "CMDFFF_DIRS,Command FIFO FIll DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." bitfld.long 0x20 14. "DDIF_DIRS,DSI data received with active bits - DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." line.long 0x24 "PUSHR,DSPI PUSH FIFO Register In Master mode" bitfld.long 0x24 31. "CONT,Continuous Peripheral Chip Select Enable. (SPI master mode)" "0: Return PCSn signals to their inactive state..,1: Keep PCSn signals asserted between transfers." bitfld.long 0x24 28.--30. "CTAS,Clock and Transfer Attributes Select." "0: CTAR0/CTARE0,1: CTAR1/CTARE1,2: CTAR2/CTARE2,3: CTAR3/CTARE3,4: CTAR4/CTARE4,5: CTAR5/CTARE5,6: CTAR6/CTARE6,7: CTAR7/CTARE7" newline bitfld.long 0x24 27. "EOQ,End Of Queue" "0: The SPI data is not the last data to transfer.,1: The SPI data is the last data to transfer." bitfld.long 0x24 26. "CTCNT,Clear Transfer Counter." "0: Do not clear the TCR[SPI_TCNT] field.,1: Clear the TCR[SPI_TCNT] field." newline bitfld.long 0x24 25. "PE_MASC,Parity Enable or Mask tASC delay in the current frame" "0: PE: No parity bit included/checked. MASC: tASC..,1: PE: Parity bit is transmitted instead of the.." bitfld.long 0x24 24. "PP_MCSC,Parity Polarity or Mask tCSC delay in the next frame" "0: PP: Even Parity: the number of 1 bits in the..,1: PP: Odd Parity: the number of 1 bits in the.." newline hexmask.long.byte 0x24 16.--23. 1. "PCS,Select which PCS signals are to be asserted for the transfer." hexmask.long.word 0x24 0.--15. 1. "TXDATA,Transmit Data" group.long 0x34++0x3 line.long 0x0 "PUSHR_SLAVE,PUSHR provides the means to write to the TX FIFO.Data written to this register is transferred to:The TX FIFO for 8- or 16-bit writes to the Data field of PUSHR.In master mode. the register provides 16-bit command to the CMD FIFO and 16-bit.." hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x38++0x13 line.long 0x0 "POPR,DSPI POP FIFO Register" hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data" line.long 0x4 "TXFR0,DSPI Transmit FIFO Registers" hexmask.long.word 0x4 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x4 0.--15. 1. "TXDATA,Transmit Data" line.long 0x8 "TXFR1,DSPI Transmit FIFO Registers" hexmask.long.word 0x8 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x8 0.--15. 1. "TXDATA,Transmit Data" line.long 0xC "TXFR2,DSPI Transmit FIFO Registers" hexmask.long.word 0xC 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0xC 0.--15. 1. "TXDATA,Transmit Data" line.long 0x10 "TXFR3,DSPI Transmit FIFO Registers" hexmask.long.word 0x10 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x10 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x7C++0xF line.long 0x0 "RXFR0,DSPI Receive FIFO Registers" hexmask.long 0x0 0.--31. 1. "RXDATA,Receive Data" line.long 0x4 "RXFR1,DSPI Receive FIFO Registers" hexmask.long 0x4 0.--31. 1. "RXDATA,Receive Data" line.long 0x8 "RXFR2,DSPI Receive FIFO Registers" hexmask.long 0x8 0.--31. 1. "RXDATA,Receive Data" line.long 0xC "RXFR3,DSPI Receive FIFO Registers" hexmask.long 0xC 0.--31. 1. "RXDATA,Receive Data" group.long 0xBC++0x3 line.long 0x0 "DSICR0,DSPI DSI Configuration Register 0" bitfld.long 0x0 30. "FMSZ4,MSB of the frame size in master mode when DSI is used in 32-bit mode." "0,1" bitfld.long 0x0 23. "FMSZ5,MSB of the frame size in master mode when DSI is used in 64-bit mode." "0,1" newline bitfld.long 0x0 21. "ITSB,Interleaved TSB mode." "0: Disabled.,1: Enabled." bitfld.long 0x0 20. "TSBC,Timed Serial Bus Configuration." "0: Disabled.,1: Enabled." newline bitfld.long 0x0 19. "TXSS,Transmit Data Source Select." "0: SDR source.,1: ASDR source." bitfld.long 0x0 18. "TPOL,Trigger Polarity" "0: Falling edge initiates a transfer.,1: Rising edge initiates a transfer." newline bitfld.long 0x0 16. "CID,Change In Data Transfer Enable" "0: Disabled.,1: Enabled." bitfld.long 0x0 15. "DCONT,DSI Continuous Peripheral Chip Select Enable (DSI Master mode only)" "0: PCS signals return to inactive.,1: PCS signals remain asserted." newline bitfld.long 0x0 12.--14. "DSICTAS,DSI Clock and Transfer Attributes Select (DSI Master mode only)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "DMS,Data Match Stop" "0: Disabled.,1: Enabled." newline bitfld.long 0x0 10. "PES,Parity Error Stop" "0: Disabled.,1: Enabled." bitfld.long 0x0 9. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of the last.." newline bitfld.long 0x0 8. "PP,Parity Polarity" "0: Even Parity: the number of '1' bits in the..,1: Odd Parity: the number of 1 bits in the.." hexmask.long.byte 0x0 0.--7. 1. "DPCSX,DSI Peripheral Chip Select 07" rgroup.long 0xC0++0x3 line.long 0x0 "SDR0,DSPI DSI Serialization Data Register 0" hexmask.long 0x0 0.--31. 1. "SER_DATA,Serialized Data" group.long 0xC4++0x3 line.long 0x0 "ASDR0,DSPI DSI Alternate Serialization Data Register 0" hexmask.long 0x0 0.--31. 1. "ASER_DATA,Alternate Serialized Data" rgroup.long 0xC8++0x7 line.long 0x0 "COMPR0,DSPI DSI Transmit Comparison Register 0" hexmask.long 0x0 0.--31. 1. "COMP_DATA,Compare Data" line.long 0x4 "DDR0,DSPI DSI Deserialization Data Register 0" hexmask.long 0x4 0.--31. 1. "DESER_DATA,Deserialized Data" group.long 0xD0++0x1F line.long 0x0 "DSICR1,DSPI DSI Configuration Register 1" hexmask.long.byte 0x0 24.--29. 1. "TSBCNT,Timed Serial Bus Operation Count" bitfld.long 0x0 18. "DSI64E,DSI 64-bit Mode Enable" "0: Disabled. DSI Mode operates in the default..,1: Enabled. DSI Mode operates in 64-bit configuration" newline bitfld.long 0x0 17. "DSE1,Data Select Enable 1" "0: No Zero bit is inserted in the middle of the..,1: Zero bit is inserted at the middle of the data.." bitfld.long 0x0 16. "DSE0,Data Select Enable 0" "0: No Zero bit is inserted in the beginning of the..,1: Zero bit is inserted at the beginning of the.." newline hexmask.long.byte 0x0 8.--15. 1. "TRGPRD,Internal Trigger Period for the ITSB mode." hexmask.long.byte 0x0 0.--7. 1. "DPCS1_X,DSI Peripheral Chip Select 07" line.long 0x4 "SSR0,DSPI DSI Serialization Source Select Register 0" hexmask.long 0x4 0.--31. 1. "SS,Source Select" line.long 0x8 "PISR0,DSPI DSI Parallel Input Select Register 0" hexmask.long.byte 0x8 28.--31. 1. "IPS7,Input Pin Select 7" hexmask.long.byte 0x8 24.--27. 1. "IPS6,Input Pin Select 6" newline hexmask.long.byte 0x8 20.--23. 1. "IPS5,Input Pin Select 5" hexmask.long.byte 0x8 16.--19. 1. "IPS4,Input Pin Select 5" newline hexmask.long.byte 0x8 12.--15. 1. "IPS3,Input Pin Select 3" hexmask.long.byte 0x8 8.--11. 1. "IPS2,Input Pin Select 2" newline hexmask.long.byte 0x8 4.--7. 1. "IPS1,Input Pin Select 1" hexmask.long.byte 0x8 0.--3. 1. "IPS0,Input Pin Select 0" line.long 0xC "PISR1,DSPI DSI Parallel Input Select Register 1" hexmask.long.byte 0xC 28.--31. 1. "IPS15,Input Pin Select 15" hexmask.long.byte 0xC 24.--27. 1. "IPS14,Input Pin Select 14" newline hexmask.long.byte 0xC 20.--23. 1. "IPS13,Input Pin Select 13" hexmask.long.byte 0xC 16.--19. 1. "IPS12,Input Pin Select 12" newline hexmask.long.byte 0xC 12.--15. 1. "IPS11,Input Pin Select 11" hexmask.long.byte 0xC 8.--11. 1. "IPS10,Input Pin Select 10" newline hexmask.long.byte 0xC 4.--7. 1. "IPS9,Input Pin Select 9" hexmask.long.byte 0xC 0.--3. 1. "IPS8,Input Pin Select 8" line.long 0x10 "PISR2,DSPI DSI Parallel Input Select Register 2" hexmask.long.byte 0x10 28.--31. 1. "IPS23,Input Pin Select 23" hexmask.long.byte 0x10 24.--27. 1. "IPS22,Input Pin Select 22" newline hexmask.long.byte 0x10 20.--23. 1. "IPS21,Input Pin Select 21" hexmask.long.byte 0x10 16.--19. 1. "IPS20,Input Pin Select 20" newline hexmask.long.byte 0x10 12.--15. 1. "IPS19,Input Pin Select 19" hexmask.long.byte 0x10 8.--11. 1. "IPS18,Input Pin Select 18" newline hexmask.long.byte 0x10 4.--7. 1. "IPS17,Input Pin Select 17" hexmask.long.byte 0x10 0.--3. 1. "IPS16,Input Pin Select 16" line.long 0x14 "PISR3,DSPI DSI Parallel Input Select Register 3" hexmask.long.byte 0x14 28.--31. 1. "IPS31,Input Pin Select 31" hexmask.long.byte 0x14 24.--27. 1. "IPS30,Input Pin Select 30" newline hexmask.long.byte 0x14 20.--23. 1. "IPS29,Input Pin Select 29" hexmask.long.byte 0x14 16.--19. 1. "IPS28,Input Pin Select 28" newline hexmask.long.byte 0x14 12.--15. 1. "IPS27,Input Pin Select 27" hexmask.long.byte 0x14 8.--11. 1. "IPS26,Input Pin Select 26" newline hexmask.long.byte 0x14 4.--7. 1. "IPS25,Input Pin Select 25" hexmask.long.byte 0x14 0.--3. 1. "IPS24,Input Pin Select 24" line.long 0x18 "DIMR0,DSPI DSI Deserialized Data Interrupt Mask Register 0" hexmask.long 0x18 0.--31. 1. "MASK,Mask" line.long 0x1C "DPIR0,DSPI DSI Deserialized Data Polarity Interrupt Register 0" hexmask.long 0x1C 0.--31. 1. "DP,Data Polarity" rgroup.long 0xF0++0x3 line.long 0x0 "SDR1,DSPI DSI Serialization Data Register 1" hexmask.long 0x0 0.--31. 1. "SER_DATA,Serialized Data" group.long 0xF4++0x3 line.long 0x0 "ASDR1,DSPI DSI Alternate Serialization Data Register 1" hexmask.long 0x0 0.--31. 1. "ASER_DATA,Alternate Serialized Data" rgroup.long 0xF8++0x7 line.long 0x0 "COMPR1,DSPI DSI Transmit Comparison Register 1" hexmask.long 0x0 0.--31. 1. "COMP_DATA,Compare Data" line.long 0x4 "DDR1,DSPI DSI Deserialization Data Register 1" hexmask.long 0x4 0.--31. 1. "DESER_DATA,Deserialized Data" group.long 0x100++0x3B line.long 0x0 "SSR1,DSPI DSI Serialization Source Select Register 1" hexmask.long 0x0 0.--31. 1. "SS,Source Select" line.long 0x4 "PISR4,DSPI DSI Parallel Input Select Register 4" hexmask.long.byte 0x4 28.--31. 1. "IPS39,Input Pin Select 39" hexmask.long.byte 0x4 24.--27. 1. "IPS38,Input Pin Select 38" newline hexmask.long.byte 0x4 20.--23. 1. "IPS37,Input Pin Select 37" hexmask.long.byte 0x4 16.--19. 1. "IPS36,Input Pin Select 36" newline hexmask.long.byte 0x4 12.--15. 1. "IPS35,Input Pin Select 35" hexmask.long.byte 0x4 8.--11. 1. "IPS34,Input Pin Select 34" newline hexmask.long.byte 0x4 4.--7. 1. "IPS33,Input Pin Select 33" hexmask.long.byte 0x4 0.--3. 1. "IPS32,Input Pin Select 32" line.long 0x8 "PISR5,DSPI DSI Parallel Input Select Register 5" hexmask.long.byte 0x8 28.--31. 1. "IPS47,Input Pin Select 47" hexmask.long.byte 0x8 24.--27. 1. "IPS46,Input Pin Select 46" newline hexmask.long.byte 0x8 20.--23. 1. "IPS45,Input Pin Select 45" hexmask.long.byte 0x8 16.--19. 1. "IPS44,Input Pin Select 44" newline hexmask.long.byte 0x8 12.--15. 1. "IPS43,Input Pin Select 43" hexmask.long.byte 0x8 8.--11. 1. "IPS42,Input Pin Select 42" newline hexmask.long.byte 0x8 4.--7. 1. "IPS41,Input Pin Select 41" hexmask.long.byte 0x8 0.--3. 1. "IPS40,Input Pin Select 40" line.long 0xC "PISR6,DSPI DSI Parallel Input Select Register 6" hexmask.long.byte 0xC 28.--31. 1. "IPS55,Input Pin Select 55" hexmask.long.byte 0xC 24.--27. 1. "IPS54,Input Pin Select 54" newline hexmask.long.byte 0xC 20.--23. 1. "IPS53,Input Pin Select 53" hexmask.long.byte 0xC 16.--19. 1. "IPS52,Input Pin Select 52" newline hexmask.long.byte 0xC 12.--15. 1. "IPS51,Input Pin Select 51" hexmask.long.byte 0xC 8.--11. 1. "IPS50,Input Pin Select 50" newline hexmask.long.byte 0xC 4.--7. 1. "IPS49,Input Pin Select 49" hexmask.long.byte 0xC 0.--3. 1. "IPS48,Input Pin Select 48" line.long 0x10 "PISR7,DSPI DSI Parallel Input Select Register 7" hexmask.long.byte 0x10 28.--31. 1. "IPS63,Input Pin Select 63" hexmask.long.byte 0x10 24.--27. 1. "IPS62,Input Pin Select 62" newline hexmask.long.byte 0x10 20.--23. 1. "IPS61,Input Pin Select 61" hexmask.long.byte 0x10 16.--19. 1. "IPS60,Input Pin Select 60" newline hexmask.long.byte 0x10 12.--15. 1. "IPS59,Input Pin Select 59" hexmask.long.byte 0x10 8.--11. 1. "IPS58,Input Pin Select 58" newline hexmask.long.byte 0x10 4.--7. 1. "IPS57,Input Pin Select 57" hexmask.long.byte 0x10 0.--3. 1. "IPS56,Input Pin Select 56" line.long 0x14 "DIMR1,DSPI DSI Deserialized Data Interrupt Mask Register 1" hexmask.long 0x14 0.--31. 1. "MASK,Mask" line.long 0x18 "DPIR1,DSPI DSI Deserialized Data Polarity Interrupt Register 1" hexmask.long 0x18 0.--31. 1. "DP,Data Polarity" line.long 0x1C "CTARE0,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x1C 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x1C 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x20 "CTARE1,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x20 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x20 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x24 "CTARE2,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x24 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x24 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x28 "CTARE3,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x28 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x28 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x2C "CTARE4,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x2C 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x2C 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x30 "CTARE5,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x30 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x30 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x34 "CTARE6,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x34 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x34 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x38 "CTARE7,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x38 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x38 0.--10. 1. "DTCP,Data Transfer Count Preload" rgroup.long 0x13C++0x3 line.long 0x0 "SREX,DSPI Status Register Extended" hexmask.long.byte 0x0 4.--7. 1. "CMDCTR,CMD FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "CMDNXTPTR,Command Next Pointer" tree.end tree "DSPI_3" base ad:0x71A94000 group.long 0x0++0x3 line.long 0x0 "MCR,DSPI Module Configuration Register" bitfld.long 0x0 31. "MSTR,Master/Slave Mode Select" "0: DSPI is in slave mode.,1: DSPI is in master mode." bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK Enable" "0: Continuous SCK disabled.,1: Continuous SCK enabled." newline bitfld.long 0x0 28.--29. "DCONF,DSPI Configuration" "0: SPI,1: DSI,2: CSI,?" bitfld.long 0x0 27. "FRZ,Freeze" "0: Do not halt serial transfers in debug mode.,1: Halt serial transfers in debug mode." newline bitfld.long 0x0 26. "MTFE,Modified Timing Format Enable" "0: Modified SPI transfer format disabled.,1: Modified SPI transfer format enabled." bitfld.long 0x0 25. "PCSSE,Peripheral Chip Select Strobe Enable" "0: PCS[5]/PCSS is used as the Peripheral Chip..,1: PCS[5]/PCSS is used as an active-low PCS Strobe.." newline bitfld.long 0x0 24. "ROOE,Receive FIFO Overflow Overwrite Enable" "0: Incoming data is ignored.,1: Incoming data is shifted into the shift register." bitfld.long 0x0 23. "PCSIS7,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 22. "PCSIS6,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 21. "PCSIS5,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 20. "PCSIS4,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 19. "PCSIS3,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 18. "PCSIS2,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 17. "PCSIS1,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 16. "PCSIS0,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 14. "MDIS,Module Disable" "0: Enable DSPI clocks.,1: Allow external logic to disable DSPI clocks." newline bitfld.long 0x0 13. "DIS_TXF,Disable Transmit FIFO" "0: Tx FIFO is enabled.,1: Tx FIFO is disabled." bitfld.long 0x0 12. "DIS_RXF,Disable Receive FIFO" "0: Rx FIFO is enabled.,1: Rx FIFO is disabled." newline bitfld.long 0x0 11. "CLR_TXF,Clear TX FIFO" "0: Do not clear the Tx FIFO and CMD FIFO counters.,1: Clears the Tx FIFO and CMD FIFO counters." bitfld.long 0x0 10. "CLR_RXF,Clear RX FIFO" "0: Do not clear the Rx FIFO counter.,1: Clear the Rx FIFO counter." newline bitfld.long 0x0 8.--9. "SMPL_PT,Sample Point" "0: 0 protocol clocks between SCK edge and SIN sample,1: 1 protocol clock between SCK edge and SIN sample,2: 2 protocol clocks between SCK edge and SIN sample,?" bitfld.long 0x0 3. "XSPI,Extended SPI Mode" "0: Normal SPI Mode. Up to 16-bit Frames. Command..,1: Extended SPI Mode. Up to 32-bit SPI Frames." newline bitfld.long 0x0 2. "FCPCS,Fast Continuous PCS Mode." "0: Normal or Slow Continuous PCS mode. Masking of..,1: Fast Continuous PCS mode. Delays masked via.." bitfld.long 0x0 1. "PES,Parity Error Stop" "0: SPI frame transmission continues.,1: SPI frame transmission stops." newline bitfld.long 0x0 0. "HALT,Halt" "0: Start transfers.,1: Stop transfers." rgroup.long 0x4++0x3 line.long 0x0 "HCR,Hardware Configuration Register" bitfld.long 0x0 31. "DSI,DSI features are implemented for the module." "0: DSI features are not implemented DSI registers..,1: DSI features are implemented" bitfld.long 0x0 30. "PISR,PISR0-3 and parallel inputs frame positions selection logic (DSI Muxing Logic) are implemented for the module." "0: PISR0-3 registers are not implemented.,1: PISR0-3 registers are implemented." newline bitfld.long 0x0 29. "DSI64,DSI features in 64 bit mode are implemented for the module." "0: DSI features for 64 bit mode are not..,1: DSI features for 64 bit mode are implemented" bitfld.long 0x0 28. "PISR_EX,PISR4-7 and parallel inputs frame positions selection logic (DSI 64 bit Muxing Logic) are implemented for the module." "0: PISR4-7 registers are not implemented.,1: PISR4-7 registers are implemented." newline bitfld.long 0x0 27. "XSPI,Extended SPI Mode feature is implemented for the module." "0: Extended SPI Mode is not implemented.,1: Extended SPI Mode is implemented." bitfld.long 0x0 24.--26. "CTAR,Maximum implemented CTAR register number." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 20.--23. 1. "TXFR,Maximum implemented TXFR register number." hexmask.long.byte 0x0 16.--19. 1. "RXFR,Maximum implemented RXFR register number." newline hexmask.long.byte 0x0 12.--15. 1. "CMDFR,Maximum implemented command FIFO number." bitfld.long 0x0 11. "MSTR_MODE,Master Mode implementation is enabled" "0,1" newline bitfld.long 0x0 10. "SLV_MODE,Slave Mode implementation is enabled" "0,1" bitfld.long 0x0 9. "TSB_EN,TSB Mode implementation is enabled" "0,1" newline bitfld.long 0x0 8. "ITSB_EN,Interleaved TSB Mode implementation is enabled" "0,1" group.long 0x8++0x7 line.long 0x0 "TCR,DSPI Transfer Count Register" hexmask.long.word 0x0 16.--31. 1. "SPI_TCNT,SPI Transfer Counter" line.long 0x4 "CTAR0,DSPI Clock and Transfer Attributes Register 0 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" group.long 0xC++0x7 line.long 0x0 "CTAR0_SLAVE,When the DSPI is configured as:SPI master - the CTAS field in the command portion of the TX FIFO entry selects which CTAR is used.SPI bus slave - the CTAR0 register is used.DSI master - the DSICTAS field in the DSPI DSI Configuration Register.." hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." bitfld.long 0x0 22. "FMSZ5,MSB of Frame Size when DSI is used in 64-bit Mode" "0,1" line.long 0x4 "CTAR1,DSPI Clock and Transfer Attributes Register 1 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" group.long 0x10++0x27 line.long 0x0 "CTAR1_SLAVE,When the DSPI is configured as:SPI master - the CTAS field in the command portion of the TX FIFO entry selects which CTAR is used.SPI bus slave - the CTAR0 register is used.DSI master - the DSICTAS field in the DSPI DSI Configuration Register.." hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." bitfld.long 0x0 22. "FMSZ5,MSB of Frame Size when DSI is used in 64-bit Mode" "0,1" line.long 0x4 "CTAR2,DSPI Clock and Transfer Attributes Register 2 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x8 "CTAR3,DSPI Clock and Transfer Attributes Register 3 (In Master Mode)" bitfld.long 0x8 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x8 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x8 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x8 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x8 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x8 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x8 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x8 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x8 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x8 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x8 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x8 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x8 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0xC "CTAR4,DSPI Clock and Transfer Attributes Register 4 (In Master Mode)" bitfld.long 0xC 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0xC 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0xC 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0xC 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0xC 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0xC 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0xC 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0xC 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0xC 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0xC 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0xC 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0xC 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x10 "CTAR5,DSPI Clock and Transfer Attributes Register 5 (In Master Mode)" bitfld.long 0x10 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x10 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x10 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x10 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x10 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x10 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x10 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x10 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x10 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x10 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x10 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x10 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x10 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x14 "CTAR6,DSPI Clock and Transfer Attributes Register 6 (In Master Mode)" bitfld.long 0x14 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x14 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x14 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x14 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x14 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x14 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x14 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x14 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x14 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x14 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x14 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x14 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x18 "CTAR7,DSPI Clock and Transfer Attributes Register 7 (In Master Mode)" bitfld.long 0x18 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x18 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x18 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x18 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x18 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x18 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x18 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x18 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x18 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x18 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x18 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x18 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x18 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x1C "SR,DSPI Status Register" bitfld.long 0x1C 31. "TCF,Transfer Complete Flag." "0: Transfer not complete.,1: Transfer complete." bitfld.long 0x1C 30. "TXRXS,TX and RX Status." "0: Transmit and receive operations are disabled..,1: Transmit and receive operations are enabled.." newline bitfld.long 0x1C 29. "SPITCF,SPI Frame Transfer Complete Flag." "0: SPI frame transfer is not complete.,1: SPI frame transfer is complete." bitfld.long 0x1C 28. "EOQF,End of Queue Flag." "0: EOQ is not set in the executing command.,1: EOQ is set in the executing SPI command." newline bitfld.long 0x1C 27. "TFUF,Transmit FIFO Underflow Flag." "0: No Tx FIFO underflow.,1: Tx FIFO underflow has occurred." bitfld.long 0x1C 26. "DSITCF,DSI Frame Transfer Complete Flag." "0: DSI frame transfer is not complete.,1: DSI frame transfer is complete." newline bitfld.long 0x1C 25. "TFFF,Transmit FIFO Fill Flag." "0: Tx FIFO is full.,1: Tx FIFO is not full." bitfld.long 0x1C 24. "BSYF,Busy Flag." "0: No Cyclic Command Transfer in Progress.,1: Cyclic Command Transfer is in progress. Current.." newline bitfld.long 0x1C 23. "CMDTCF,Command Transfer Complete Flag." "0: Data Transfer by current Command not complete.,1: Data Transfer by current Command complete." bitfld.long 0x1C 22. "DPEF,DSI Parity Error Flag." "0: No parity error.,1: Parity error has occurred." newline bitfld.long 0x1C 21. "SPEF,SPI Parity Error Flag." "0: No parity error.,1: Parity error has occurred." bitfld.long 0x1C 20. "DDIF,DSI Data Received with Active Bits." "0: No DSI data with active bits was received.,1: DSI data with active bits was received." newline bitfld.long 0x1C 19. "RFOF,Receive FIFO Overflow Flag." "0: No Rx FIFO overflow.,1: Rx FIFO overflow has occurred." bitfld.long 0x1C 18. "TFIWF,Transmit FIFO Invalid Write Flag." "0: No Invalid Data present in TX FIFO,1: Invalid Data present in TX FIFO since CMD FIFO.." newline bitfld.long 0x1C 17. "RFDF,Receive FIFO Drain Flag." "0: Rx FIFO is empty.,1: Rx FIFO is not empty." bitfld.long 0x1C 16. "CMDFFF,Command FIFO Fill Flag." "0: CMD FIFO is full.,1: CMD FIFO is not full." newline hexmask.long.byte 0x1C 12.--15. 1. "TXCTR,TX FIFO Counter." hexmask.long.byte 0x1C 8.--11. 1. "TXNXTPTR,Transmit Next Pointer." newline hexmask.long.byte 0x1C 4.--7. 1. "RXCTR,RX FIFO Counter." hexmask.long.byte 0x1C 0.--3. 1. "POPNXTPTR,Pop Next Pointer." line.long 0x20 "RSER,DSPI DMA/Interrupt Request Select and Enable Register" bitfld.long 0x20 31. "TCF_RE,Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 30. "CMDFFF_RE,Command FIFO Fill Flag Request Enable." "0: Disabled.,1: Enabled." newline bitfld.long 0x20 29. "SPITCF_RE,SPI Frame Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 28. "EOQF_RE,DSPI Finished Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 27. "TFUF_RE,Transmit FIFO Underflow Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 26. "DSITCF_RE,DSI Frame Transmission Complete Request Enable." "0: Disabled.,1: Enabled." newline bitfld.long 0x20 25. "TFFF_RE,Transmit FIFO Fill Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 24. "TFFF_DIRS,Transmit FIFO Fill DMA or Interrupt Request Select" "0: Interrupt requests.,1: DMA requests." newline bitfld.long 0x20 23. "CMDTCF_RE,Command Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 22. "DPEF_RE,DSI Parity Error Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 21. "SPEF_RE,SPI Parity Error Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 20. "DDIF_RE,DSI data received with active bits Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 19. "RFOF_RE,Receive FIFO Overflow Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 18. "TFIWF_RE,Transmit FIFO Invalid Write Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 17. "RFDF_RE,Receive FIFO Drain Request Enable" "0: Disabled,1: Enabled" bitfld.long 0x20 16. "RFDF_DIRS,Receive FIFO Drain DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." newline bitfld.long 0x20 15. "CMDFFF_DIRS,Command FIFO FIll DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." bitfld.long 0x20 14. "DDIF_DIRS,DSI data received with active bits - DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." line.long 0x24 "PUSHR,DSPI PUSH FIFO Register In Master mode" bitfld.long 0x24 31. "CONT,Continuous Peripheral Chip Select Enable. (SPI master mode)" "0: Return PCSn signals to their inactive state..,1: Keep PCSn signals asserted between transfers." bitfld.long 0x24 28.--30. "CTAS,Clock and Transfer Attributes Select." "0: CTAR0/CTARE0,1: CTAR1/CTARE1,2: CTAR2/CTARE2,3: CTAR3/CTARE3,4: CTAR4/CTARE4,5: CTAR5/CTARE5,6: CTAR6/CTARE6,7: CTAR7/CTARE7" newline bitfld.long 0x24 27. "EOQ,End Of Queue" "0: The SPI data is not the last data to transfer.,1: The SPI data is the last data to transfer." bitfld.long 0x24 26. "CTCNT,Clear Transfer Counter." "0: Do not clear the TCR[SPI_TCNT] field.,1: Clear the TCR[SPI_TCNT] field." newline bitfld.long 0x24 25. "PE_MASC,Parity Enable or Mask tASC delay in the current frame" "0: PE: No parity bit included/checked. MASC: tASC..,1: PE: Parity bit is transmitted instead of the.." bitfld.long 0x24 24. "PP_MCSC,Parity Polarity or Mask tCSC delay in the next frame" "0: PP: Even Parity: the number of 1 bits in the..,1: PP: Odd Parity: the number of 1 bits in the.." newline hexmask.long.byte 0x24 16.--23. 1. "PCS,Select which PCS signals are to be asserted for the transfer." hexmask.long.word 0x24 0.--15. 1. "TXDATA,Transmit Data" group.long 0x34++0x3 line.long 0x0 "PUSHR_SLAVE,PUSHR provides the means to write to the TX FIFO.Data written to this register is transferred to:The TX FIFO for 8- or 16-bit writes to the Data field of PUSHR.In master mode. the register provides 16-bit command to the CMD FIFO and 16-bit.." hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x38++0x13 line.long 0x0 "POPR,DSPI POP FIFO Register" hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data" line.long 0x4 "TXFR0,DSPI Transmit FIFO Registers" hexmask.long.word 0x4 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x4 0.--15. 1. "TXDATA,Transmit Data" line.long 0x8 "TXFR1,DSPI Transmit FIFO Registers" hexmask.long.word 0x8 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x8 0.--15. 1. "TXDATA,Transmit Data" line.long 0xC "TXFR2,DSPI Transmit FIFO Registers" hexmask.long.word 0xC 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0xC 0.--15. 1. "TXDATA,Transmit Data" line.long 0x10 "TXFR3,DSPI Transmit FIFO Registers" hexmask.long.word 0x10 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x10 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x7C++0xF line.long 0x0 "RXFR0,DSPI Receive FIFO Registers" hexmask.long 0x0 0.--31. 1. "RXDATA,Receive Data" line.long 0x4 "RXFR1,DSPI Receive FIFO Registers" hexmask.long 0x4 0.--31. 1. "RXDATA,Receive Data" line.long 0x8 "RXFR2,DSPI Receive FIFO Registers" hexmask.long 0x8 0.--31. 1. "RXDATA,Receive Data" line.long 0xC "RXFR3,DSPI Receive FIFO Registers" hexmask.long 0xC 0.--31. 1. "RXDATA,Receive Data" group.long 0xBC++0x3 line.long 0x0 "DSICR0,DSPI DSI Configuration Register 0" bitfld.long 0x0 30. "FMSZ4,MSB of the frame size in master mode when DSI is used in 32-bit mode." "0,1" bitfld.long 0x0 23. "FMSZ5,MSB of the frame size in master mode when DSI is used in 64-bit mode." "0,1" newline bitfld.long 0x0 21. "ITSB,Interleaved TSB mode." "0: Disabled.,1: Enabled." bitfld.long 0x0 20. "TSBC,Timed Serial Bus Configuration." "0: Disabled.,1: Enabled." newline bitfld.long 0x0 19. "TXSS,Transmit Data Source Select." "0: SDR source.,1: ASDR source." bitfld.long 0x0 18. "TPOL,Trigger Polarity" "0: Falling edge initiates a transfer.,1: Rising edge initiates a transfer." newline bitfld.long 0x0 16. "CID,Change In Data Transfer Enable" "0: Disabled.,1: Enabled." bitfld.long 0x0 15. "DCONT,DSI Continuous Peripheral Chip Select Enable (DSI Master mode only)" "0: PCS signals return to inactive.,1: PCS signals remain asserted." newline bitfld.long 0x0 12.--14. "DSICTAS,DSI Clock and Transfer Attributes Select (DSI Master mode only)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "DMS,Data Match Stop" "0: Disabled.,1: Enabled." newline bitfld.long 0x0 10. "PES,Parity Error Stop" "0: Disabled.,1: Enabled." bitfld.long 0x0 9. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of the last.." newline bitfld.long 0x0 8. "PP,Parity Polarity" "0: Even Parity: the number of '1' bits in the..,1: Odd Parity: the number of 1 bits in the.." hexmask.long.byte 0x0 0.--7. 1. "DPCSX,DSI Peripheral Chip Select 07" rgroup.long 0xC0++0x3 line.long 0x0 "SDR0,DSPI DSI Serialization Data Register 0" hexmask.long 0x0 0.--31. 1. "SER_DATA,Serialized Data" group.long 0xC4++0x3 line.long 0x0 "ASDR0,DSPI DSI Alternate Serialization Data Register 0" hexmask.long 0x0 0.--31. 1. "ASER_DATA,Alternate Serialized Data" rgroup.long 0xC8++0x7 line.long 0x0 "COMPR0,DSPI DSI Transmit Comparison Register 0" hexmask.long 0x0 0.--31. 1. "COMP_DATA,Compare Data" line.long 0x4 "DDR0,DSPI DSI Deserialization Data Register 0" hexmask.long 0x4 0.--31. 1. "DESER_DATA,Deserialized Data" group.long 0xD0++0x1F line.long 0x0 "DSICR1,DSPI DSI Configuration Register 1" hexmask.long.byte 0x0 24.--29. 1. "TSBCNT,Timed Serial Bus Operation Count" bitfld.long 0x0 18. "DSI64E,DSI 64-bit Mode Enable" "0: Disabled. DSI Mode operates in the default..,1: Enabled. DSI Mode operates in 64-bit configuration" newline bitfld.long 0x0 17. "DSE1,Data Select Enable 1" "0: No Zero bit is inserted in the middle of the..,1: Zero bit is inserted at the middle of the data.." bitfld.long 0x0 16. "DSE0,Data Select Enable 0" "0: No Zero bit is inserted in the beginning of the..,1: Zero bit is inserted at the beginning of the.." newline hexmask.long.byte 0x0 8.--15. 1. "TRGPRD,Internal Trigger Period for the ITSB mode." hexmask.long.byte 0x0 0.--7. 1. "DPCS1_X,DSI Peripheral Chip Select 07" line.long 0x4 "SSR0,DSPI DSI Serialization Source Select Register 0" hexmask.long 0x4 0.--31. 1. "SS,Source Select" line.long 0x8 "PISR0,DSPI DSI Parallel Input Select Register 0" hexmask.long.byte 0x8 28.--31. 1. "IPS7,Input Pin Select 7" hexmask.long.byte 0x8 24.--27. 1. "IPS6,Input Pin Select 6" newline hexmask.long.byte 0x8 20.--23. 1. "IPS5,Input Pin Select 5" hexmask.long.byte 0x8 16.--19. 1. "IPS4,Input Pin Select 5" newline hexmask.long.byte 0x8 12.--15. 1. "IPS3,Input Pin Select 3" hexmask.long.byte 0x8 8.--11. 1. "IPS2,Input Pin Select 2" newline hexmask.long.byte 0x8 4.--7. 1. "IPS1,Input Pin Select 1" hexmask.long.byte 0x8 0.--3. 1. "IPS0,Input Pin Select 0" line.long 0xC "PISR1,DSPI DSI Parallel Input Select Register 1" hexmask.long.byte 0xC 28.--31. 1. "IPS15,Input Pin Select 15" hexmask.long.byte 0xC 24.--27. 1. "IPS14,Input Pin Select 14" newline hexmask.long.byte 0xC 20.--23. 1. "IPS13,Input Pin Select 13" hexmask.long.byte 0xC 16.--19. 1. "IPS12,Input Pin Select 12" newline hexmask.long.byte 0xC 12.--15. 1. "IPS11,Input Pin Select 11" hexmask.long.byte 0xC 8.--11. 1. "IPS10,Input Pin Select 10" newline hexmask.long.byte 0xC 4.--7. 1. "IPS9,Input Pin Select 9" hexmask.long.byte 0xC 0.--3. 1. "IPS8,Input Pin Select 8" line.long 0x10 "PISR2,DSPI DSI Parallel Input Select Register 2" hexmask.long.byte 0x10 28.--31. 1. "IPS23,Input Pin Select 23" hexmask.long.byte 0x10 24.--27. 1. "IPS22,Input Pin Select 22" newline hexmask.long.byte 0x10 20.--23. 1. "IPS21,Input Pin Select 21" hexmask.long.byte 0x10 16.--19. 1. "IPS20,Input Pin Select 20" newline hexmask.long.byte 0x10 12.--15. 1. "IPS19,Input Pin Select 19" hexmask.long.byte 0x10 8.--11. 1. "IPS18,Input Pin Select 18" newline hexmask.long.byte 0x10 4.--7. 1. "IPS17,Input Pin Select 17" hexmask.long.byte 0x10 0.--3. 1. "IPS16,Input Pin Select 16" line.long 0x14 "PISR3,DSPI DSI Parallel Input Select Register 3" hexmask.long.byte 0x14 28.--31. 1. "IPS31,Input Pin Select 31" hexmask.long.byte 0x14 24.--27. 1. "IPS30,Input Pin Select 30" newline hexmask.long.byte 0x14 20.--23. 1. "IPS29,Input Pin Select 29" hexmask.long.byte 0x14 16.--19. 1. "IPS28,Input Pin Select 28" newline hexmask.long.byte 0x14 12.--15. 1. "IPS27,Input Pin Select 27" hexmask.long.byte 0x14 8.--11. 1. "IPS26,Input Pin Select 26" newline hexmask.long.byte 0x14 4.--7. 1. "IPS25,Input Pin Select 25" hexmask.long.byte 0x14 0.--3. 1. "IPS24,Input Pin Select 24" line.long 0x18 "DIMR0,DSPI DSI Deserialized Data Interrupt Mask Register 0" hexmask.long 0x18 0.--31. 1. "MASK,Mask" line.long 0x1C "DPIR0,DSPI DSI Deserialized Data Polarity Interrupt Register 0" hexmask.long 0x1C 0.--31. 1. "DP,Data Polarity" rgroup.long 0xF0++0x3 line.long 0x0 "SDR1,DSPI DSI Serialization Data Register 1" hexmask.long 0x0 0.--31. 1. "SER_DATA,Serialized Data" group.long 0xF4++0x3 line.long 0x0 "ASDR1,DSPI DSI Alternate Serialization Data Register 1" hexmask.long 0x0 0.--31. 1. "ASER_DATA,Alternate Serialized Data" rgroup.long 0xF8++0x7 line.long 0x0 "COMPR1,DSPI DSI Transmit Comparison Register 1" hexmask.long 0x0 0.--31. 1. "COMP_DATA,Compare Data" line.long 0x4 "DDR1,DSPI DSI Deserialization Data Register 1" hexmask.long 0x4 0.--31. 1. "DESER_DATA,Deserialized Data" group.long 0x100++0x3B line.long 0x0 "SSR1,DSPI DSI Serialization Source Select Register 1" hexmask.long 0x0 0.--31. 1. "SS,Source Select" line.long 0x4 "PISR4,DSPI DSI Parallel Input Select Register 4" hexmask.long.byte 0x4 28.--31. 1. "IPS39,Input Pin Select 39" hexmask.long.byte 0x4 24.--27. 1. "IPS38,Input Pin Select 38" newline hexmask.long.byte 0x4 20.--23. 1. "IPS37,Input Pin Select 37" hexmask.long.byte 0x4 16.--19. 1. "IPS36,Input Pin Select 36" newline hexmask.long.byte 0x4 12.--15. 1. "IPS35,Input Pin Select 35" hexmask.long.byte 0x4 8.--11. 1. "IPS34,Input Pin Select 34" newline hexmask.long.byte 0x4 4.--7. 1. "IPS33,Input Pin Select 33" hexmask.long.byte 0x4 0.--3. 1. "IPS32,Input Pin Select 32" line.long 0x8 "PISR5,DSPI DSI Parallel Input Select Register 5" hexmask.long.byte 0x8 28.--31. 1. "IPS47,Input Pin Select 47" hexmask.long.byte 0x8 24.--27. 1. "IPS46,Input Pin Select 46" newline hexmask.long.byte 0x8 20.--23. 1. "IPS45,Input Pin Select 45" hexmask.long.byte 0x8 16.--19. 1. "IPS44,Input Pin Select 44" newline hexmask.long.byte 0x8 12.--15. 1. "IPS43,Input Pin Select 43" hexmask.long.byte 0x8 8.--11. 1. "IPS42,Input Pin Select 42" newline hexmask.long.byte 0x8 4.--7. 1. "IPS41,Input Pin Select 41" hexmask.long.byte 0x8 0.--3. 1. "IPS40,Input Pin Select 40" line.long 0xC "PISR6,DSPI DSI Parallel Input Select Register 6" hexmask.long.byte 0xC 28.--31. 1. "IPS55,Input Pin Select 55" hexmask.long.byte 0xC 24.--27. 1. "IPS54,Input Pin Select 54" newline hexmask.long.byte 0xC 20.--23. 1. "IPS53,Input Pin Select 53" hexmask.long.byte 0xC 16.--19. 1. "IPS52,Input Pin Select 52" newline hexmask.long.byte 0xC 12.--15. 1. "IPS51,Input Pin Select 51" hexmask.long.byte 0xC 8.--11. 1. "IPS50,Input Pin Select 50" newline hexmask.long.byte 0xC 4.--7. 1. "IPS49,Input Pin Select 49" hexmask.long.byte 0xC 0.--3. 1. "IPS48,Input Pin Select 48" line.long 0x10 "PISR7,DSPI DSI Parallel Input Select Register 7" hexmask.long.byte 0x10 28.--31. 1. "IPS63,Input Pin Select 63" hexmask.long.byte 0x10 24.--27. 1. "IPS62,Input Pin Select 62" newline hexmask.long.byte 0x10 20.--23. 1. "IPS61,Input Pin Select 61" hexmask.long.byte 0x10 16.--19. 1. "IPS60,Input Pin Select 60" newline hexmask.long.byte 0x10 12.--15. 1. "IPS59,Input Pin Select 59" hexmask.long.byte 0x10 8.--11. 1. "IPS58,Input Pin Select 58" newline hexmask.long.byte 0x10 4.--7. 1. "IPS57,Input Pin Select 57" hexmask.long.byte 0x10 0.--3. 1. "IPS56,Input Pin Select 56" line.long 0x14 "DIMR1,DSPI DSI Deserialized Data Interrupt Mask Register 1" hexmask.long 0x14 0.--31. 1. "MASK,Mask" line.long 0x18 "DPIR1,DSPI DSI Deserialized Data Polarity Interrupt Register 1" hexmask.long 0x18 0.--31. 1. "DP,Data Polarity" line.long 0x1C "CTARE0,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x1C 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x1C 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x20 "CTARE1,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x20 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x20 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x24 "CTARE2,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x24 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x24 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x28 "CTARE3,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x28 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x28 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x2C "CTARE4,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x2C 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x2C 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x30 "CTARE5,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x30 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x30 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x34 "CTARE6,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x34 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x34 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x38 "CTARE7,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x38 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x38 0.--10. 1. "DTCP,Data Transfer Count Preload" rgroup.long 0x13C++0x3 line.long 0x0 "SREX,DSPI Status Register Extended" hexmask.long.byte 0x0 4.--7. 1. "CMDCTR,CMD FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "CMDNXTPTR,Command Next Pointer" tree.end tree "DSPI_4" base ad:0x70E58000 group.long 0x0++0x3 line.long 0x0 "MCR,DSPI Module Configuration Register" bitfld.long 0x0 31. "MSTR,Master/Slave Mode Select" "0: DSPI is in slave mode.,1: DSPI is in master mode." bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK Enable" "0: Continuous SCK disabled.,1: Continuous SCK enabled." newline bitfld.long 0x0 28.--29. "DCONF,DSPI Configuration" "0: SPI,1: DSI,2: CSI,?" bitfld.long 0x0 27. "FRZ,Freeze" "0: Do not halt serial transfers in debug mode.,1: Halt serial transfers in debug mode." newline bitfld.long 0x0 26. "MTFE,Modified Timing Format Enable" "0: Modified SPI transfer format disabled.,1: Modified SPI transfer format enabled." bitfld.long 0x0 25. "PCSSE,Peripheral Chip Select Strobe Enable" "0: PCS[5]/PCSS is used as the Peripheral Chip..,1: PCS[5]/PCSS is used as an active-low PCS Strobe.." newline bitfld.long 0x0 24. "ROOE,Receive FIFO Overflow Overwrite Enable" "0: Incoming data is ignored.,1: Incoming data is shifted into the shift register." bitfld.long 0x0 23. "PCSIS7,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 22. "PCSIS6,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 21. "PCSIS5,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 20. "PCSIS4,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 19. "PCSIS3,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 18. "PCSIS2,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 17. "PCSIS1,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 16. "PCSIS0,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 14. "MDIS,Module Disable" "0: Enable DSPI clocks.,1: Allow external logic to disable DSPI clocks." newline bitfld.long 0x0 13. "DIS_TXF,Disable Transmit FIFO" "0: Tx FIFO is enabled.,1: Tx FIFO is disabled." bitfld.long 0x0 12. "DIS_RXF,Disable Receive FIFO" "0: Rx FIFO is enabled.,1: Rx FIFO is disabled." newline bitfld.long 0x0 11. "CLR_TXF,Clear TX FIFO" "0: Do not clear the Tx FIFO and CMD FIFO counters.,1: Clears the Tx FIFO and CMD FIFO counters." bitfld.long 0x0 10. "CLR_RXF,Clear RX FIFO" "0: Do not clear the Rx FIFO counter.,1: Clear the Rx FIFO counter." newline bitfld.long 0x0 8.--9. "SMPL_PT,Sample Point" "0: 0 protocol clocks between SCK edge and SIN sample,1: 1 protocol clock between SCK edge and SIN sample,2: 2 protocol clocks between SCK edge and SIN sample,?" bitfld.long 0x0 3. "XSPI,Extended SPI Mode" "0: Normal SPI Mode. Up to 16-bit Frames. Command..,1: Extended SPI Mode. Up to 32-bit SPI Frames." newline bitfld.long 0x0 2. "FCPCS,Fast Continuous PCS Mode." "0: Normal or Slow Continuous PCS mode. Masking of..,1: Fast Continuous PCS mode. Delays masked via.." bitfld.long 0x0 1. "PES,Parity Error Stop" "0: SPI frame transmission continues.,1: SPI frame transmission stops." newline bitfld.long 0x0 0. "HALT,Halt" "0: Start transfers.,1: Stop transfers." rgroup.long 0x4++0x3 line.long 0x0 "HCR,Hardware Configuration Register" bitfld.long 0x0 31. "DSI,DSI features are implemented for the module." "0: DSI features are not implemented DSI registers..,1: DSI features are implemented" bitfld.long 0x0 30. "PISR,PISR0-3 and parallel inputs frame positions selection logic (DSI Muxing Logic) are implemented for the module." "0: PISR0-3 registers are not implemented.,1: PISR0-3 registers are implemented." newline bitfld.long 0x0 29. "DSI64,DSI features in 64 bit mode are implemented for the module." "0: DSI features for 64 bit mode are not..,1: DSI features for 64 bit mode are implemented" bitfld.long 0x0 28. "PISR_EX,PISR4-7 and parallel inputs frame positions selection logic (DSI 64 bit Muxing Logic) are implemented for the module." "0: PISR4-7 registers are not implemented.,1: PISR4-7 registers are implemented." newline bitfld.long 0x0 27. "XSPI,Extended SPI Mode feature is implemented for the module." "0: Extended SPI Mode is not implemented.,1: Extended SPI Mode is implemented." bitfld.long 0x0 24.--26. "CTAR,Maximum implemented CTAR register number." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 20.--23. 1. "TXFR,Maximum implemented TXFR register number." hexmask.long.byte 0x0 16.--19. 1. "RXFR,Maximum implemented RXFR register number." newline hexmask.long.byte 0x0 12.--15. 1. "CMDFR,Maximum implemented command FIFO number." bitfld.long 0x0 11. "MSTR_MODE,Master Mode implementation is enabled" "0,1" newline bitfld.long 0x0 10. "SLV_MODE,Slave Mode implementation is enabled" "0,1" bitfld.long 0x0 9. "TSB_EN,TSB Mode implementation is enabled" "0,1" newline bitfld.long 0x0 8. "ITSB_EN,Interleaved TSB Mode implementation is enabled" "0,1" group.long 0x8++0x7 line.long 0x0 "TCR,DSPI Transfer Count Register" hexmask.long.word 0x0 16.--31. 1. "SPI_TCNT,SPI Transfer Counter" line.long 0x4 "CTAR0,DSPI Clock and Transfer Attributes Register 0 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" group.long 0xC++0x7 line.long 0x0 "CTAR0_SLAVE,When the DSPI is configured as:SPI master - the CTAS field in the command portion of the TX FIFO entry selects which CTAR is used.SPI bus slave - the CTAR0 register is used.DSI master - the DSICTAS field in the DSPI DSI Configuration Register.." hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." bitfld.long 0x0 22. "FMSZ5,MSB of Frame Size when DSI is used in 64-bit Mode" "0,1" line.long 0x4 "CTAR1,DSPI Clock and Transfer Attributes Register 1 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" group.long 0x10++0x27 line.long 0x0 "CTAR1_SLAVE,When the DSPI is configured as:SPI master - the CTAS field in the command portion of the TX FIFO entry selects which CTAR is used.SPI bus slave - the CTAR0 register is used.DSI master - the DSICTAS field in the DSPI DSI Configuration Register.." hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." bitfld.long 0x0 22. "FMSZ5,MSB of Frame Size when DSI is used in 64-bit Mode" "0,1" line.long 0x4 "CTAR2,DSPI Clock and Transfer Attributes Register 2 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x8 "CTAR3,DSPI Clock and Transfer Attributes Register 3 (In Master Mode)" bitfld.long 0x8 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x8 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x8 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x8 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x8 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x8 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x8 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x8 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x8 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x8 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x8 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x8 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x8 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0xC "CTAR4,DSPI Clock and Transfer Attributes Register 4 (In Master Mode)" bitfld.long 0xC 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0xC 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0xC 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0xC 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0xC 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0xC 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0xC 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0xC 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0xC 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0xC 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0xC 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0xC 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x10 "CTAR5,DSPI Clock and Transfer Attributes Register 5 (In Master Mode)" bitfld.long 0x10 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x10 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x10 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x10 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x10 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x10 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x10 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x10 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x10 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x10 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x10 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x10 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x10 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x14 "CTAR6,DSPI Clock and Transfer Attributes Register 6 (In Master Mode)" bitfld.long 0x14 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x14 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x14 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x14 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x14 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x14 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x14 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x14 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x14 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x14 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x14 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x14 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x18 "CTAR7,DSPI Clock and Transfer Attributes Register 7 (In Master Mode)" bitfld.long 0x18 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x18 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x18 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x18 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x18 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x18 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x18 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x18 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x18 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x18 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x18 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x18 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x18 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x1C "SR,DSPI Status Register" bitfld.long 0x1C 31. "TCF,Transfer Complete Flag." "0: Transfer not complete.,1: Transfer complete." bitfld.long 0x1C 30. "TXRXS,TX and RX Status." "0: Transmit and receive operations are disabled..,1: Transmit and receive operations are enabled.." newline bitfld.long 0x1C 29. "SPITCF,SPI Frame Transfer Complete Flag." "0: SPI frame transfer is not complete.,1: SPI frame transfer is complete." bitfld.long 0x1C 28. "EOQF,End of Queue Flag." "0: EOQ is not set in the executing command.,1: EOQ is set in the executing SPI command." newline bitfld.long 0x1C 27. "TFUF,Transmit FIFO Underflow Flag." "0: No Tx FIFO underflow.,1: Tx FIFO underflow has occurred." bitfld.long 0x1C 26. "DSITCF,DSI Frame Transfer Complete Flag." "0: DSI frame transfer is not complete.,1: DSI frame transfer is complete." newline bitfld.long 0x1C 25. "TFFF,Transmit FIFO Fill Flag." "0: Tx FIFO is full.,1: Tx FIFO is not full." bitfld.long 0x1C 24. "BSYF,Busy Flag." "0: No Cyclic Command Transfer in Progress.,1: Cyclic Command Transfer is in progress. Current.." newline bitfld.long 0x1C 23. "CMDTCF,Command Transfer Complete Flag." "0: Data Transfer by current Command not complete.,1: Data Transfer by current Command complete." bitfld.long 0x1C 22. "DPEF,DSI Parity Error Flag." "0: No parity error.,1: Parity error has occurred." newline bitfld.long 0x1C 21. "SPEF,SPI Parity Error Flag." "0: No parity error.,1: Parity error has occurred." bitfld.long 0x1C 20. "DDIF,DSI Data Received with Active Bits." "0: No DSI data with active bits was received.,1: DSI data with active bits was received." newline bitfld.long 0x1C 19. "RFOF,Receive FIFO Overflow Flag." "0: No Rx FIFO overflow.,1: Rx FIFO overflow has occurred." bitfld.long 0x1C 18. "TFIWF,Transmit FIFO Invalid Write Flag." "0: No Invalid Data present in TX FIFO,1: Invalid Data present in TX FIFO since CMD FIFO.." newline bitfld.long 0x1C 17. "RFDF,Receive FIFO Drain Flag." "0: Rx FIFO is empty.,1: Rx FIFO is not empty." bitfld.long 0x1C 16. "CMDFFF,Command FIFO Fill Flag." "0: CMD FIFO is full.,1: CMD FIFO is not full." newline hexmask.long.byte 0x1C 12.--15. 1. "TXCTR,TX FIFO Counter." hexmask.long.byte 0x1C 8.--11. 1. "TXNXTPTR,Transmit Next Pointer." newline hexmask.long.byte 0x1C 4.--7. 1. "RXCTR,RX FIFO Counter." hexmask.long.byte 0x1C 0.--3. 1. "POPNXTPTR,Pop Next Pointer." line.long 0x20 "RSER,DSPI DMA/Interrupt Request Select and Enable Register" bitfld.long 0x20 31. "TCF_RE,Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 30. "CMDFFF_RE,Command FIFO Fill Flag Request Enable." "0: Disabled.,1: Enabled." newline bitfld.long 0x20 29. "SPITCF_RE,SPI Frame Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 28. "EOQF_RE,DSPI Finished Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 27. "TFUF_RE,Transmit FIFO Underflow Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 26. "DSITCF_RE,DSI Frame Transmission Complete Request Enable." "0: Disabled.,1: Enabled." newline bitfld.long 0x20 25. "TFFF_RE,Transmit FIFO Fill Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 24. "TFFF_DIRS,Transmit FIFO Fill DMA or Interrupt Request Select" "0: Interrupt requests.,1: DMA requests." newline bitfld.long 0x20 23. "CMDTCF_RE,Command Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 22. "DPEF_RE,DSI Parity Error Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 21. "SPEF_RE,SPI Parity Error Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 20. "DDIF_RE,DSI data received with active bits Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 19. "RFOF_RE,Receive FIFO Overflow Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 18. "TFIWF_RE,Transmit FIFO Invalid Write Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 17. "RFDF_RE,Receive FIFO Drain Request Enable" "0: Disabled,1: Enabled" bitfld.long 0x20 16. "RFDF_DIRS,Receive FIFO Drain DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." newline bitfld.long 0x20 15. "CMDFFF_DIRS,Command FIFO FIll DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." bitfld.long 0x20 14. "DDIF_DIRS,DSI data received with active bits - DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." line.long 0x24 "PUSHR,DSPI PUSH FIFO Register In Master mode" bitfld.long 0x24 31. "CONT,Continuous Peripheral Chip Select Enable. (SPI master mode)" "0: Return PCSn signals to their inactive state..,1: Keep PCSn signals asserted between transfers." bitfld.long 0x24 28.--30. "CTAS,Clock and Transfer Attributes Select." "0: CTAR0/CTARE0,1: CTAR1/CTARE1,2: CTAR2/CTARE2,3: CTAR3/CTARE3,4: CTAR4/CTARE4,5: CTAR5/CTARE5,6: CTAR6/CTARE6,7: CTAR7/CTARE7" newline bitfld.long 0x24 27. "EOQ,End Of Queue" "0: The SPI data is not the last data to transfer.,1: The SPI data is the last data to transfer." bitfld.long 0x24 26. "CTCNT,Clear Transfer Counter." "0: Do not clear the TCR[SPI_TCNT] field.,1: Clear the TCR[SPI_TCNT] field." newline bitfld.long 0x24 25. "PE_MASC,Parity Enable or Mask tASC delay in the current frame" "0: PE: No parity bit included/checked. MASC: tASC..,1: PE: Parity bit is transmitted instead of the.." bitfld.long 0x24 24. "PP_MCSC,Parity Polarity or Mask tCSC delay in the next frame" "0: PP: Even Parity: the number of 1 bits in the..,1: PP: Odd Parity: the number of 1 bits in the.." newline hexmask.long.byte 0x24 16.--23. 1. "PCS,Select which PCS signals are to be asserted for the transfer." hexmask.long.word 0x24 0.--15. 1. "TXDATA,Transmit Data" group.long 0x34++0x3 line.long 0x0 "PUSHR_SLAVE,PUSHR provides the means to write to the TX FIFO.Data written to this register is transferred to:The TX FIFO for 8- or 16-bit writes to the Data field of PUSHR.In master mode. the register provides 16-bit command to the CMD FIFO and 16-bit.." hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x38++0x13 line.long 0x0 "POPR,DSPI POP FIFO Register" hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data" line.long 0x4 "TXFR0,DSPI Transmit FIFO Registers" hexmask.long.word 0x4 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x4 0.--15. 1. "TXDATA,Transmit Data" line.long 0x8 "TXFR1,DSPI Transmit FIFO Registers" hexmask.long.word 0x8 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x8 0.--15. 1. "TXDATA,Transmit Data" line.long 0xC "TXFR2,DSPI Transmit FIFO Registers" hexmask.long.word 0xC 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0xC 0.--15. 1. "TXDATA,Transmit Data" line.long 0x10 "TXFR3,DSPI Transmit FIFO Registers" hexmask.long.word 0x10 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x10 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x7C++0xF line.long 0x0 "RXFR0,DSPI Receive FIFO Registers" hexmask.long 0x0 0.--31. 1. "RXDATA,Receive Data" line.long 0x4 "RXFR1,DSPI Receive FIFO Registers" hexmask.long 0x4 0.--31. 1. "RXDATA,Receive Data" line.long 0x8 "RXFR2,DSPI Receive FIFO Registers" hexmask.long 0x8 0.--31. 1. "RXDATA,Receive Data" line.long 0xC "RXFR3,DSPI Receive FIFO Registers" hexmask.long 0xC 0.--31. 1. "RXDATA,Receive Data" group.long 0xBC++0x3 line.long 0x0 "DSICR0,DSPI DSI Configuration Register 0" bitfld.long 0x0 30. "FMSZ4,MSB of the frame size in master mode when DSI is used in 32-bit mode." "0,1" bitfld.long 0x0 23. "FMSZ5,MSB of the frame size in master mode when DSI is used in 64-bit mode." "0,1" newline bitfld.long 0x0 21. "ITSB,Interleaved TSB mode." "0: Disabled.,1: Enabled." bitfld.long 0x0 20. "TSBC,Timed Serial Bus Configuration." "0: Disabled.,1: Enabled." newline bitfld.long 0x0 19. "TXSS,Transmit Data Source Select." "0: SDR source.,1: ASDR source." bitfld.long 0x0 18. "TPOL,Trigger Polarity" "0: Falling edge initiates a transfer.,1: Rising edge initiates a transfer." newline bitfld.long 0x0 16. "CID,Change In Data Transfer Enable" "0: Disabled.,1: Enabled." bitfld.long 0x0 15. "DCONT,DSI Continuous Peripheral Chip Select Enable (DSI Master mode only)" "0: PCS signals return to inactive.,1: PCS signals remain asserted." newline bitfld.long 0x0 12.--14. "DSICTAS,DSI Clock and Transfer Attributes Select (DSI Master mode only)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "DMS,Data Match Stop" "0: Disabled.,1: Enabled." newline bitfld.long 0x0 10. "PES,Parity Error Stop" "0: Disabled.,1: Enabled." bitfld.long 0x0 9. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of the last.." newline bitfld.long 0x0 8. "PP,Parity Polarity" "0: Even Parity: the number of '1' bits in the..,1: Odd Parity: the number of 1 bits in the.." hexmask.long.byte 0x0 0.--7. 1. "DPCSX,DSI Peripheral Chip Select 07" rgroup.long 0xC0++0x3 line.long 0x0 "SDR0,DSPI DSI Serialization Data Register 0" hexmask.long 0x0 0.--31. 1. "SER_DATA,Serialized Data" group.long 0xC4++0x3 line.long 0x0 "ASDR0,DSPI DSI Alternate Serialization Data Register 0" hexmask.long 0x0 0.--31. 1. "ASER_DATA,Alternate Serialized Data" rgroup.long 0xC8++0x7 line.long 0x0 "COMPR0,DSPI DSI Transmit Comparison Register 0" hexmask.long 0x0 0.--31. 1. "COMP_DATA,Compare Data" line.long 0x4 "DDR0,DSPI DSI Deserialization Data Register 0" hexmask.long 0x4 0.--31. 1. "DESER_DATA,Deserialized Data" group.long 0xD0++0x1F line.long 0x0 "DSICR1,DSPI DSI Configuration Register 1" hexmask.long.byte 0x0 24.--29. 1. "TSBCNT,Timed Serial Bus Operation Count" bitfld.long 0x0 18. "DSI64E,DSI 64-bit Mode Enable" "0: Disabled. DSI Mode operates in the default..,1: Enabled. DSI Mode operates in 64-bit configuration" newline bitfld.long 0x0 17. "DSE1,Data Select Enable 1" "0: No Zero bit is inserted in the middle of the..,1: Zero bit is inserted at the middle of the data.." bitfld.long 0x0 16. "DSE0,Data Select Enable 0" "0: No Zero bit is inserted in the beginning of the..,1: Zero bit is inserted at the beginning of the.." newline hexmask.long.byte 0x0 8.--15. 1. "TRGPRD,Internal Trigger Period for the ITSB mode." hexmask.long.byte 0x0 0.--7. 1. "DPCS1_X,DSI Peripheral Chip Select 07" line.long 0x4 "SSR0,DSPI DSI Serialization Source Select Register 0" hexmask.long 0x4 0.--31. 1. "SS,Source Select" line.long 0x8 "PISR0,DSPI DSI Parallel Input Select Register 0" hexmask.long.byte 0x8 28.--31. 1. "IPS7,Input Pin Select 7" hexmask.long.byte 0x8 24.--27. 1. "IPS6,Input Pin Select 6" newline hexmask.long.byte 0x8 20.--23. 1. "IPS5,Input Pin Select 5" hexmask.long.byte 0x8 16.--19. 1. "IPS4,Input Pin Select 5" newline hexmask.long.byte 0x8 12.--15. 1. "IPS3,Input Pin Select 3" hexmask.long.byte 0x8 8.--11. 1. "IPS2,Input Pin Select 2" newline hexmask.long.byte 0x8 4.--7. 1. "IPS1,Input Pin Select 1" hexmask.long.byte 0x8 0.--3. 1. "IPS0,Input Pin Select 0" line.long 0xC "PISR1,DSPI DSI Parallel Input Select Register 1" hexmask.long.byte 0xC 28.--31. 1. "IPS15,Input Pin Select 15" hexmask.long.byte 0xC 24.--27. 1. "IPS14,Input Pin Select 14" newline hexmask.long.byte 0xC 20.--23. 1. "IPS13,Input Pin Select 13" hexmask.long.byte 0xC 16.--19. 1. "IPS12,Input Pin Select 12" newline hexmask.long.byte 0xC 12.--15. 1. "IPS11,Input Pin Select 11" hexmask.long.byte 0xC 8.--11. 1. "IPS10,Input Pin Select 10" newline hexmask.long.byte 0xC 4.--7. 1. "IPS9,Input Pin Select 9" hexmask.long.byte 0xC 0.--3. 1. "IPS8,Input Pin Select 8" line.long 0x10 "PISR2,DSPI DSI Parallel Input Select Register 2" hexmask.long.byte 0x10 28.--31. 1. "IPS23,Input Pin Select 23" hexmask.long.byte 0x10 24.--27. 1. "IPS22,Input Pin Select 22" newline hexmask.long.byte 0x10 20.--23. 1. "IPS21,Input Pin Select 21" hexmask.long.byte 0x10 16.--19. 1. "IPS20,Input Pin Select 20" newline hexmask.long.byte 0x10 12.--15. 1. "IPS19,Input Pin Select 19" hexmask.long.byte 0x10 8.--11. 1. "IPS18,Input Pin Select 18" newline hexmask.long.byte 0x10 4.--7. 1. "IPS17,Input Pin Select 17" hexmask.long.byte 0x10 0.--3. 1. "IPS16,Input Pin Select 16" line.long 0x14 "PISR3,DSPI DSI Parallel Input Select Register 3" hexmask.long.byte 0x14 28.--31. 1. "IPS31,Input Pin Select 31" hexmask.long.byte 0x14 24.--27. 1. "IPS30,Input Pin Select 30" newline hexmask.long.byte 0x14 20.--23. 1. "IPS29,Input Pin Select 29" hexmask.long.byte 0x14 16.--19. 1. "IPS28,Input Pin Select 28" newline hexmask.long.byte 0x14 12.--15. 1. "IPS27,Input Pin Select 27" hexmask.long.byte 0x14 8.--11. 1. "IPS26,Input Pin Select 26" newline hexmask.long.byte 0x14 4.--7. 1. "IPS25,Input Pin Select 25" hexmask.long.byte 0x14 0.--3. 1. "IPS24,Input Pin Select 24" line.long 0x18 "DIMR0,DSPI DSI Deserialized Data Interrupt Mask Register 0" hexmask.long 0x18 0.--31. 1. "MASK,Mask" line.long 0x1C "DPIR0,DSPI DSI Deserialized Data Polarity Interrupt Register 0" hexmask.long 0x1C 0.--31. 1. "DP,Data Polarity" rgroup.long 0xF0++0x3 line.long 0x0 "SDR1,DSPI DSI Serialization Data Register 1" hexmask.long 0x0 0.--31. 1. "SER_DATA,Serialized Data" group.long 0xF4++0x3 line.long 0x0 "ASDR1,DSPI DSI Alternate Serialization Data Register 1" hexmask.long 0x0 0.--31. 1. "ASER_DATA,Alternate Serialized Data" rgroup.long 0xF8++0x7 line.long 0x0 "COMPR1,DSPI DSI Transmit Comparison Register 1" hexmask.long 0x0 0.--31. 1. "COMP_DATA,Compare Data" line.long 0x4 "DDR1,DSPI DSI Deserialization Data Register 1" hexmask.long 0x4 0.--31. 1. "DESER_DATA,Deserialized Data" group.long 0x100++0x3B line.long 0x0 "SSR1,DSPI DSI Serialization Source Select Register 1" hexmask.long 0x0 0.--31. 1. "SS,Source Select" line.long 0x4 "PISR4,DSPI DSI Parallel Input Select Register 4" hexmask.long.byte 0x4 28.--31. 1. "IPS39,Input Pin Select 39" hexmask.long.byte 0x4 24.--27. 1. "IPS38,Input Pin Select 38" newline hexmask.long.byte 0x4 20.--23. 1. "IPS37,Input Pin Select 37" hexmask.long.byte 0x4 16.--19. 1. "IPS36,Input Pin Select 36" newline hexmask.long.byte 0x4 12.--15. 1. "IPS35,Input Pin Select 35" hexmask.long.byte 0x4 8.--11. 1. "IPS34,Input Pin Select 34" newline hexmask.long.byte 0x4 4.--7. 1. "IPS33,Input Pin Select 33" hexmask.long.byte 0x4 0.--3. 1. "IPS32,Input Pin Select 32" line.long 0x8 "PISR5,DSPI DSI Parallel Input Select Register 5" hexmask.long.byte 0x8 28.--31. 1. "IPS47,Input Pin Select 47" hexmask.long.byte 0x8 24.--27. 1. "IPS46,Input Pin Select 46" newline hexmask.long.byte 0x8 20.--23. 1. "IPS45,Input Pin Select 45" hexmask.long.byte 0x8 16.--19. 1. "IPS44,Input Pin Select 44" newline hexmask.long.byte 0x8 12.--15. 1. "IPS43,Input Pin Select 43" hexmask.long.byte 0x8 8.--11. 1. "IPS42,Input Pin Select 42" newline hexmask.long.byte 0x8 4.--7. 1. "IPS41,Input Pin Select 41" hexmask.long.byte 0x8 0.--3. 1. "IPS40,Input Pin Select 40" line.long 0xC "PISR6,DSPI DSI Parallel Input Select Register 6" hexmask.long.byte 0xC 28.--31. 1. "IPS55,Input Pin Select 55" hexmask.long.byte 0xC 24.--27. 1. "IPS54,Input Pin Select 54" newline hexmask.long.byte 0xC 20.--23. 1. "IPS53,Input Pin Select 53" hexmask.long.byte 0xC 16.--19. 1. "IPS52,Input Pin Select 52" newline hexmask.long.byte 0xC 12.--15. 1. "IPS51,Input Pin Select 51" hexmask.long.byte 0xC 8.--11. 1. "IPS50,Input Pin Select 50" newline hexmask.long.byte 0xC 4.--7. 1. "IPS49,Input Pin Select 49" hexmask.long.byte 0xC 0.--3. 1. "IPS48,Input Pin Select 48" line.long 0x10 "PISR7,DSPI DSI Parallel Input Select Register 7" hexmask.long.byte 0x10 28.--31. 1. "IPS63,Input Pin Select 63" hexmask.long.byte 0x10 24.--27. 1. "IPS62,Input Pin Select 62" newline hexmask.long.byte 0x10 20.--23. 1. "IPS61,Input Pin Select 61" hexmask.long.byte 0x10 16.--19. 1. "IPS60,Input Pin Select 60" newline hexmask.long.byte 0x10 12.--15. 1. "IPS59,Input Pin Select 59" hexmask.long.byte 0x10 8.--11. 1. "IPS58,Input Pin Select 58" newline hexmask.long.byte 0x10 4.--7. 1. "IPS57,Input Pin Select 57" hexmask.long.byte 0x10 0.--3. 1. "IPS56,Input Pin Select 56" line.long 0x14 "DIMR1,DSPI DSI Deserialized Data Interrupt Mask Register 1" hexmask.long 0x14 0.--31. 1. "MASK,Mask" line.long 0x18 "DPIR1,DSPI DSI Deserialized Data Polarity Interrupt Register 1" hexmask.long 0x18 0.--31. 1. "DP,Data Polarity" line.long 0x1C "CTARE0,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x1C 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x1C 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x20 "CTARE1,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x20 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x20 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x24 "CTARE2,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x24 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x24 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x28 "CTARE3,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x28 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x28 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x2C "CTARE4,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x2C 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x2C 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x30 "CTARE5,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x30 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x30 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x34 "CTARE6,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x34 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x34 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x38 "CTARE7,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x38 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x38 0.--10. 1. "DTCP,Data Transfer Count Preload" rgroup.long 0x13C++0x3 line.long 0x0 "SREX,DSPI Status Register Extended" hexmask.long.byte 0x0 4.--7. 1. "CMDCTR,CMD FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "CMDNXTPTR,Command Next Pointer" tree.end tree "DSPI_5" base ad:0x71A9C000 group.long 0x0++0x3 line.long 0x0 "MCR,DSPI Module Configuration Register" bitfld.long 0x0 31. "MSTR,Master/Slave Mode Select" "0: DSPI is in slave mode.,1: DSPI is in master mode." bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK Enable" "0: Continuous SCK disabled.,1: Continuous SCK enabled." newline bitfld.long 0x0 28.--29. "DCONF,DSPI Configuration" "0: SPI,1: DSI,2: CSI,?" bitfld.long 0x0 27. "FRZ,Freeze" "0: Do not halt serial transfers in debug mode.,1: Halt serial transfers in debug mode." newline bitfld.long 0x0 26. "MTFE,Modified Timing Format Enable" "0: Modified SPI transfer format disabled.,1: Modified SPI transfer format enabled." bitfld.long 0x0 25. "PCSSE,Peripheral Chip Select Strobe Enable" "0: PCS[5]/PCSS is used as the Peripheral Chip..,1: PCS[5]/PCSS is used as an active-low PCS Strobe.." newline bitfld.long 0x0 24. "ROOE,Receive FIFO Overflow Overwrite Enable" "0: Incoming data is ignored.,1: Incoming data is shifted into the shift register." bitfld.long 0x0 23. "PCSIS7,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 22. "PCSIS6,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 21. "PCSIS5,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 20. "PCSIS4,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 19. "PCSIS3,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 18. "PCSIS2,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 17. "PCSIS1,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 16. "PCSIS0,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 14. "MDIS,Module Disable" "0: Enable DSPI clocks.,1: Allow external logic to disable DSPI clocks." newline bitfld.long 0x0 13. "DIS_TXF,Disable Transmit FIFO" "0: Tx FIFO is enabled.,1: Tx FIFO is disabled." bitfld.long 0x0 12. "DIS_RXF,Disable Receive FIFO" "0: Rx FIFO is enabled.,1: Rx FIFO is disabled." newline bitfld.long 0x0 11. "CLR_TXF,Clear TX FIFO" "0: Do not clear the Tx FIFO and CMD FIFO counters.,1: Clears the Tx FIFO and CMD FIFO counters." bitfld.long 0x0 10. "CLR_RXF,Clear RX FIFO" "0: Do not clear the Rx FIFO counter.,1: Clear the Rx FIFO counter." newline bitfld.long 0x0 8.--9. "SMPL_PT,Sample Point" "0: 0 protocol clocks between SCK edge and SIN sample,1: 1 protocol clock between SCK edge and SIN sample,2: 2 protocol clocks between SCK edge and SIN sample,?" bitfld.long 0x0 3. "XSPI,Extended SPI Mode" "0: Normal SPI Mode. Up to 16-bit Frames. Command..,1: Extended SPI Mode. Up to 32-bit SPI Frames." newline bitfld.long 0x0 2. "FCPCS,Fast Continuous PCS Mode." "0: Normal or Slow Continuous PCS mode. Masking of..,1: Fast Continuous PCS mode. Delays masked via.." bitfld.long 0x0 1. "PES,Parity Error Stop" "0: SPI frame transmission continues.,1: SPI frame transmission stops." newline bitfld.long 0x0 0. "HALT,Halt" "0: Start transfers.,1: Stop transfers." rgroup.long 0x4++0x3 line.long 0x0 "HCR,Hardware Configuration Register" bitfld.long 0x0 31. "DSI,DSI features are implemented for the module." "0: DSI features are not implemented DSI registers..,1: DSI features are implemented" bitfld.long 0x0 30. "PISR,PISR0-3 and parallel inputs frame positions selection logic (DSI Muxing Logic) are implemented for the module." "0: PISR0-3 registers are not implemented.,1: PISR0-3 registers are implemented." newline bitfld.long 0x0 29. "DSI64,DSI features in 64 bit mode are implemented for the module." "0: DSI features for 64 bit mode are not..,1: DSI features for 64 bit mode are implemented" bitfld.long 0x0 28. "PISR_EX,PISR4-7 and parallel inputs frame positions selection logic (DSI 64 bit Muxing Logic) are implemented for the module." "0: PISR4-7 registers are not implemented.,1: PISR4-7 registers are implemented." newline bitfld.long 0x0 27. "XSPI,Extended SPI Mode feature is implemented for the module." "0: Extended SPI Mode is not implemented.,1: Extended SPI Mode is implemented." bitfld.long 0x0 24.--26. "CTAR,Maximum implemented CTAR register number." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 20.--23. 1. "TXFR,Maximum implemented TXFR register number." hexmask.long.byte 0x0 16.--19. 1. "RXFR,Maximum implemented RXFR register number." newline hexmask.long.byte 0x0 12.--15. 1. "CMDFR,Maximum implemented command FIFO number." bitfld.long 0x0 11. "MSTR_MODE,Master Mode implementation is enabled" "0,1" newline bitfld.long 0x0 10. "SLV_MODE,Slave Mode implementation is enabled" "0,1" bitfld.long 0x0 9. "TSB_EN,TSB Mode implementation is enabled" "0,1" newline bitfld.long 0x0 8. "ITSB_EN,Interleaved TSB Mode implementation is enabled" "0,1" group.long 0x8++0x7 line.long 0x0 "TCR,DSPI Transfer Count Register" hexmask.long.word 0x0 16.--31. 1. "SPI_TCNT,SPI Transfer Counter" line.long 0x4 "CTAR0,DSPI Clock and Transfer Attributes Register 0 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" group.long 0xC++0x7 line.long 0x0 "CTAR0_SLAVE,When the DSPI is configured as:SPI master - the CTAS field in the command portion of the TX FIFO entry selects which CTAR is used.SPI bus slave - the CTAR0 register is used.DSI master - the DSICTAS field in the DSPI DSI Configuration Register.." hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." bitfld.long 0x0 22. "FMSZ5,MSB of Frame Size when DSI is used in 64-bit Mode" "0,1" line.long 0x4 "CTAR1,DSPI Clock and Transfer Attributes Register 1 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" group.long 0x10++0x27 line.long 0x0 "CTAR1_SLAVE,When the DSPI is configured as:SPI master - the CTAS field in the command portion of the TX FIFO entry selects which CTAR is used.SPI bus slave - the CTAR0 register is used.DSI master - the DSICTAS field in the DSPI DSI Configuration Register.." hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." bitfld.long 0x0 22. "FMSZ5,MSB of Frame Size when DSI is used in 64-bit Mode" "0,1" line.long 0x4 "CTAR2,DSPI Clock and Transfer Attributes Register 2 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x8 "CTAR3,DSPI Clock and Transfer Attributes Register 3 (In Master Mode)" bitfld.long 0x8 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x8 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x8 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x8 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x8 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x8 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x8 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x8 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x8 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x8 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x8 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x8 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x8 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0xC "CTAR4,DSPI Clock and Transfer Attributes Register 4 (In Master Mode)" bitfld.long 0xC 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0xC 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0xC 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0xC 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0xC 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0xC 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0xC 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0xC 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0xC 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0xC 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0xC 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0xC 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x10 "CTAR5,DSPI Clock and Transfer Attributes Register 5 (In Master Mode)" bitfld.long 0x10 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x10 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x10 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x10 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x10 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x10 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x10 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x10 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x10 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x10 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x10 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x10 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x10 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x14 "CTAR6,DSPI Clock and Transfer Attributes Register 6 (In Master Mode)" bitfld.long 0x14 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x14 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x14 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x14 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x14 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x14 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x14 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x14 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x14 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x14 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x14 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x14 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x18 "CTAR7,DSPI Clock and Transfer Attributes Register 7 (In Master Mode)" bitfld.long 0x18 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x18 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x18 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x18 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x18 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x18 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x18 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x18 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x18 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x18 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x18 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x18 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x18 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x1C "SR,DSPI Status Register" bitfld.long 0x1C 31. "TCF,Transfer Complete Flag." "0: Transfer not complete.,1: Transfer complete." bitfld.long 0x1C 30. "TXRXS,TX and RX Status." "0: Transmit and receive operations are disabled..,1: Transmit and receive operations are enabled.." newline bitfld.long 0x1C 29. "SPITCF,SPI Frame Transfer Complete Flag." "0: SPI frame transfer is not complete.,1: SPI frame transfer is complete." bitfld.long 0x1C 28. "EOQF,End of Queue Flag." "0: EOQ is not set in the executing command.,1: EOQ is set in the executing SPI command." newline bitfld.long 0x1C 27. "TFUF,Transmit FIFO Underflow Flag." "0: No Tx FIFO underflow.,1: Tx FIFO underflow has occurred." bitfld.long 0x1C 26. "DSITCF,DSI Frame Transfer Complete Flag." "0: DSI frame transfer is not complete.,1: DSI frame transfer is complete." newline bitfld.long 0x1C 25. "TFFF,Transmit FIFO Fill Flag." "0: Tx FIFO is full.,1: Tx FIFO is not full." bitfld.long 0x1C 24. "BSYF,Busy Flag." "0: No Cyclic Command Transfer in Progress.,1: Cyclic Command Transfer is in progress. Current.." newline bitfld.long 0x1C 23. "CMDTCF,Command Transfer Complete Flag." "0: Data Transfer by current Command not complete.,1: Data Transfer by current Command complete." bitfld.long 0x1C 22. "DPEF,DSI Parity Error Flag." "0: No parity error.,1: Parity error has occurred." newline bitfld.long 0x1C 21. "SPEF,SPI Parity Error Flag." "0: No parity error.,1: Parity error has occurred." bitfld.long 0x1C 20. "DDIF,DSI Data Received with Active Bits." "0: No DSI data with active bits was received.,1: DSI data with active bits was received." newline bitfld.long 0x1C 19. "RFOF,Receive FIFO Overflow Flag." "0: No Rx FIFO overflow.,1: Rx FIFO overflow has occurred." bitfld.long 0x1C 18. "TFIWF,Transmit FIFO Invalid Write Flag." "0: No Invalid Data present in TX FIFO,1: Invalid Data present in TX FIFO since CMD FIFO.." newline bitfld.long 0x1C 17. "RFDF,Receive FIFO Drain Flag." "0: Rx FIFO is empty.,1: Rx FIFO is not empty." bitfld.long 0x1C 16. "CMDFFF,Command FIFO Fill Flag." "0: CMD FIFO is full.,1: CMD FIFO is not full." newline hexmask.long.byte 0x1C 12.--15. 1. "TXCTR,TX FIFO Counter." hexmask.long.byte 0x1C 8.--11. 1. "TXNXTPTR,Transmit Next Pointer." newline hexmask.long.byte 0x1C 4.--7. 1. "RXCTR,RX FIFO Counter." hexmask.long.byte 0x1C 0.--3. 1. "POPNXTPTR,Pop Next Pointer." line.long 0x20 "RSER,DSPI DMA/Interrupt Request Select and Enable Register" bitfld.long 0x20 31. "TCF_RE,Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 30. "CMDFFF_RE,Command FIFO Fill Flag Request Enable." "0: Disabled.,1: Enabled." newline bitfld.long 0x20 29. "SPITCF_RE,SPI Frame Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 28. "EOQF_RE,DSPI Finished Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 27. "TFUF_RE,Transmit FIFO Underflow Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 26. "DSITCF_RE,DSI Frame Transmission Complete Request Enable." "0: Disabled.,1: Enabled." newline bitfld.long 0x20 25. "TFFF_RE,Transmit FIFO Fill Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 24. "TFFF_DIRS,Transmit FIFO Fill DMA or Interrupt Request Select" "0: Interrupt requests.,1: DMA requests." newline bitfld.long 0x20 23. "CMDTCF_RE,Command Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 22. "DPEF_RE,DSI Parity Error Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 21. "SPEF_RE,SPI Parity Error Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 20. "DDIF_RE,DSI data received with active bits Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 19. "RFOF_RE,Receive FIFO Overflow Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 18. "TFIWF_RE,Transmit FIFO Invalid Write Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 17. "RFDF_RE,Receive FIFO Drain Request Enable" "0: Disabled,1: Enabled" bitfld.long 0x20 16. "RFDF_DIRS,Receive FIFO Drain DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." newline bitfld.long 0x20 15. "CMDFFF_DIRS,Command FIFO FIll DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." bitfld.long 0x20 14. "DDIF_DIRS,DSI data received with active bits - DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." line.long 0x24 "PUSHR,DSPI PUSH FIFO Register In Master mode" bitfld.long 0x24 31. "CONT,Continuous Peripheral Chip Select Enable. (SPI master mode)" "0: Return PCSn signals to their inactive state..,1: Keep PCSn signals asserted between transfers." bitfld.long 0x24 28.--30. "CTAS,Clock and Transfer Attributes Select." "0: CTAR0/CTARE0,1: CTAR1/CTARE1,2: CTAR2/CTARE2,3: CTAR3/CTARE3,4: CTAR4/CTARE4,5: CTAR5/CTARE5,6: CTAR6/CTARE6,7: CTAR7/CTARE7" newline bitfld.long 0x24 27. "EOQ,End Of Queue" "0: The SPI data is not the last data to transfer.,1: The SPI data is the last data to transfer." bitfld.long 0x24 26. "CTCNT,Clear Transfer Counter." "0: Do not clear the TCR[SPI_TCNT] field.,1: Clear the TCR[SPI_TCNT] field." newline bitfld.long 0x24 25. "PE_MASC,Parity Enable or Mask tASC delay in the current frame" "0: PE: No parity bit included/checked. MASC: tASC..,1: PE: Parity bit is transmitted instead of the.." bitfld.long 0x24 24. "PP_MCSC,Parity Polarity or Mask tCSC delay in the next frame" "0: PP: Even Parity: the number of 1 bits in the..,1: PP: Odd Parity: the number of 1 bits in the.." newline hexmask.long.byte 0x24 16.--23. 1. "PCS,Select which PCS signals are to be asserted for the transfer." hexmask.long.word 0x24 0.--15. 1. "TXDATA,Transmit Data" group.long 0x34++0x3 line.long 0x0 "PUSHR_SLAVE,PUSHR provides the means to write to the TX FIFO.Data written to this register is transferred to:The TX FIFO for 8- or 16-bit writes to the Data field of PUSHR.In master mode. the register provides 16-bit command to the CMD FIFO and 16-bit.." hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x38++0x13 line.long 0x0 "POPR,DSPI POP FIFO Register" hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data" line.long 0x4 "TXFR0,DSPI Transmit FIFO Registers" hexmask.long.word 0x4 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x4 0.--15. 1. "TXDATA,Transmit Data" line.long 0x8 "TXFR1,DSPI Transmit FIFO Registers" hexmask.long.word 0x8 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x8 0.--15. 1. "TXDATA,Transmit Data" line.long 0xC "TXFR2,DSPI Transmit FIFO Registers" hexmask.long.word 0xC 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0xC 0.--15. 1. "TXDATA,Transmit Data" line.long 0x10 "TXFR3,DSPI Transmit FIFO Registers" hexmask.long.word 0x10 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x10 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x7C++0xF line.long 0x0 "RXFR0,DSPI Receive FIFO Registers" hexmask.long 0x0 0.--31. 1. "RXDATA,Receive Data" line.long 0x4 "RXFR1,DSPI Receive FIFO Registers" hexmask.long 0x4 0.--31. 1. "RXDATA,Receive Data" line.long 0x8 "RXFR2,DSPI Receive FIFO Registers" hexmask.long 0x8 0.--31. 1. "RXDATA,Receive Data" line.long 0xC "RXFR3,DSPI Receive FIFO Registers" hexmask.long 0xC 0.--31. 1. "RXDATA,Receive Data" group.long 0xBC++0x3 line.long 0x0 "DSICR0,DSPI DSI Configuration Register 0" bitfld.long 0x0 30. "FMSZ4,MSB of the frame size in master mode when DSI is used in 32-bit mode." "0,1" bitfld.long 0x0 23. "FMSZ5,MSB of the frame size in master mode when DSI is used in 64-bit mode." "0,1" newline bitfld.long 0x0 21. "ITSB,Interleaved TSB mode." "0: Disabled.,1: Enabled." bitfld.long 0x0 20. "TSBC,Timed Serial Bus Configuration." "0: Disabled.,1: Enabled." newline bitfld.long 0x0 19. "TXSS,Transmit Data Source Select." "0: SDR source.,1: ASDR source." bitfld.long 0x0 18. "TPOL,Trigger Polarity" "0: Falling edge initiates a transfer.,1: Rising edge initiates a transfer." newline bitfld.long 0x0 16. "CID,Change In Data Transfer Enable" "0: Disabled.,1: Enabled." bitfld.long 0x0 15. "DCONT,DSI Continuous Peripheral Chip Select Enable (DSI Master mode only)" "0: PCS signals return to inactive.,1: PCS signals remain asserted." newline bitfld.long 0x0 12.--14. "DSICTAS,DSI Clock and Transfer Attributes Select (DSI Master mode only)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "DMS,Data Match Stop" "0: Disabled.,1: Enabled." newline bitfld.long 0x0 10. "PES,Parity Error Stop" "0: Disabled.,1: Enabled." bitfld.long 0x0 9. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of the last.." newline bitfld.long 0x0 8. "PP,Parity Polarity" "0: Even Parity: the number of '1' bits in the..,1: Odd Parity: the number of 1 bits in the.." hexmask.long.byte 0x0 0.--7. 1. "DPCSX,DSI Peripheral Chip Select 07" rgroup.long 0xC0++0x3 line.long 0x0 "SDR0,DSPI DSI Serialization Data Register 0" hexmask.long 0x0 0.--31. 1. "SER_DATA,Serialized Data" group.long 0xC4++0x3 line.long 0x0 "ASDR0,DSPI DSI Alternate Serialization Data Register 0" hexmask.long 0x0 0.--31. 1. "ASER_DATA,Alternate Serialized Data" rgroup.long 0xC8++0x7 line.long 0x0 "COMPR0,DSPI DSI Transmit Comparison Register 0" hexmask.long 0x0 0.--31. 1. "COMP_DATA,Compare Data" line.long 0x4 "DDR0,DSPI DSI Deserialization Data Register 0" hexmask.long 0x4 0.--31. 1. "DESER_DATA,Deserialized Data" group.long 0xD0++0x1F line.long 0x0 "DSICR1,DSPI DSI Configuration Register 1" hexmask.long.byte 0x0 24.--29. 1. "TSBCNT,Timed Serial Bus Operation Count" bitfld.long 0x0 18. "DSI64E,DSI 64-bit Mode Enable" "0: Disabled. DSI Mode operates in the default..,1: Enabled. DSI Mode operates in 64-bit configuration" newline bitfld.long 0x0 17. "DSE1,Data Select Enable 1" "0: No Zero bit is inserted in the middle of the..,1: Zero bit is inserted at the middle of the data.." bitfld.long 0x0 16. "DSE0,Data Select Enable 0" "0: No Zero bit is inserted in the beginning of the..,1: Zero bit is inserted at the beginning of the.." newline hexmask.long.byte 0x0 8.--15. 1. "TRGPRD,Internal Trigger Period for the ITSB mode." hexmask.long.byte 0x0 0.--7. 1. "DPCS1_X,DSI Peripheral Chip Select 07" line.long 0x4 "SSR0,DSPI DSI Serialization Source Select Register 0" hexmask.long 0x4 0.--31. 1. "SS,Source Select" line.long 0x8 "PISR0,DSPI DSI Parallel Input Select Register 0" hexmask.long.byte 0x8 28.--31. 1. "IPS7,Input Pin Select 7" hexmask.long.byte 0x8 24.--27. 1. "IPS6,Input Pin Select 6" newline hexmask.long.byte 0x8 20.--23. 1. "IPS5,Input Pin Select 5" hexmask.long.byte 0x8 16.--19. 1. "IPS4,Input Pin Select 5" newline hexmask.long.byte 0x8 12.--15. 1. "IPS3,Input Pin Select 3" hexmask.long.byte 0x8 8.--11. 1. "IPS2,Input Pin Select 2" newline hexmask.long.byte 0x8 4.--7. 1. "IPS1,Input Pin Select 1" hexmask.long.byte 0x8 0.--3. 1. "IPS0,Input Pin Select 0" line.long 0xC "PISR1,DSPI DSI Parallel Input Select Register 1" hexmask.long.byte 0xC 28.--31. 1. "IPS15,Input Pin Select 15" hexmask.long.byte 0xC 24.--27. 1. "IPS14,Input Pin Select 14" newline hexmask.long.byte 0xC 20.--23. 1. "IPS13,Input Pin Select 13" hexmask.long.byte 0xC 16.--19. 1. "IPS12,Input Pin Select 12" newline hexmask.long.byte 0xC 12.--15. 1. "IPS11,Input Pin Select 11" hexmask.long.byte 0xC 8.--11. 1. "IPS10,Input Pin Select 10" newline hexmask.long.byte 0xC 4.--7. 1. "IPS9,Input Pin Select 9" hexmask.long.byte 0xC 0.--3. 1. "IPS8,Input Pin Select 8" line.long 0x10 "PISR2,DSPI DSI Parallel Input Select Register 2" hexmask.long.byte 0x10 28.--31. 1. "IPS23,Input Pin Select 23" hexmask.long.byte 0x10 24.--27. 1. "IPS22,Input Pin Select 22" newline hexmask.long.byte 0x10 20.--23. 1. "IPS21,Input Pin Select 21" hexmask.long.byte 0x10 16.--19. 1. "IPS20,Input Pin Select 20" newline hexmask.long.byte 0x10 12.--15. 1. "IPS19,Input Pin Select 19" hexmask.long.byte 0x10 8.--11. 1. "IPS18,Input Pin Select 18" newline hexmask.long.byte 0x10 4.--7. 1. "IPS17,Input Pin Select 17" hexmask.long.byte 0x10 0.--3. 1. "IPS16,Input Pin Select 16" line.long 0x14 "PISR3,DSPI DSI Parallel Input Select Register 3" hexmask.long.byte 0x14 28.--31. 1. "IPS31,Input Pin Select 31" hexmask.long.byte 0x14 24.--27. 1. "IPS30,Input Pin Select 30" newline hexmask.long.byte 0x14 20.--23. 1. "IPS29,Input Pin Select 29" hexmask.long.byte 0x14 16.--19. 1. "IPS28,Input Pin Select 28" newline hexmask.long.byte 0x14 12.--15. 1. "IPS27,Input Pin Select 27" hexmask.long.byte 0x14 8.--11. 1. "IPS26,Input Pin Select 26" newline hexmask.long.byte 0x14 4.--7. 1. "IPS25,Input Pin Select 25" hexmask.long.byte 0x14 0.--3. 1. "IPS24,Input Pin Select 24" line.long 0x18 "DIMR0,DSPI DSI Deserialized Data Interrupt Mask Register 0" hexmask.long 0x18 0.--31. 1. "MASK,Mask" line.long 0x1C "DPIR0,DSPI DSI Deserialized Data Polarity Interrupt Register 0" hexmask.long 0x1C 0.--31. 1. "DP,Data Polarity" rgroup.long 0xF0++0x3 line.long 0x0 "SDR1,DSPI DSI Serialization Data Register 1" hexmask.long 0x0 0.--31. 1. "SER_DATA,Serialized Data" group.long 0xF4++0x3 line.long 0x0 "ASDR1,DSPI DSI Alternate Serialization Data Register 1" hexmask.long 0x0 0.--31. 1. "ASER_DATA,Alternate Serialized Data" rgroup.long 0xF8++0x7 line.long 0x0 "COMPR1,DSPI DSI Transmit Comparison Register 1" hexmask.long 0x0 0.--31. 1. "COMP_DATA,Compare Data" line.long 0x4 "DDR1,DSPI DSI Deserialization Data Register 1" hexmask.long 0x4 0.--31. 1. "DESER_DATA,Deserialized Data" group.long 0x100++0x3B line.long 0x0 "SSR1,DSPI DSI Serialization Source Select Register 1" hexmask.long 0x0 0.--31. 1. "SS,Source Select" line.long 0x4 "PISR4,DSPI DSI Parallel Input Select Register 4" hexmask.long.byte 0x4 28.--31. 1. "IPS39,Input Pin Select 39" hexmask.long.byte 0x4 24.--27. 1. "IPS38,Input Pin Select 38" newline hexmask.long.byte 0x4 20.--23. 1. "IPS37,Input Pin Select 37" hexmask.long.byte 0x4 16.--19. 1. "IPS36,Input Pin Select 36" newline hexmask.long.byte 0x4 12.--15. 1. "IPS35,Input Pin Select 35" hexmask.long.byte 0x4 8.--11. 1. "IPS34,Input Pin Select 34" newline hexmask.long.byte 0x4 4.--7. 1. "IPS33,Input Pin Select 33" hexmask.long.byte 0x4 0.--3. 1. "IPS32,Input Pin Select 32" line.long 0x8 "PISR5,DSPI DSI Parallel Input Select Register 5" hexmask.long.byte 0x8 28.--31. 1. "IPS47,Input Pin Select 47" hexmask.long.byte 0x8 24.--27. 1. "IPS46,Input Pin Select 46" newline hexmask.long.byte 0x8 20.--23. 1. "IPS45,Input Pin Select 45" hexmask.long.byte 0x8 16.--19. 1. "IPS44,Input Pin Select 44" newline hexmask.long.byte 0x8 12.--15. 1. "IPS43,Input Pin Select 43" hexmask.long.byte 0x8 8.--11. 1. "IPS42,Input Pin Select 42" newline hexmask.long.byte 0x8 4.--7. 1. "IPS41,Input Pin Select 41" hexmask.long.byte 0x8 0.--3. 1. "IPS40,Input Pin Select 40" line.long 0xC "PISR6,DSPI DSI Parallel Input Select Register 6" hexmask.long.byte 0xC 28.--31. 1. "IPS55,Input Pin Select 55" hexmask.long.byte 0xC 24.--27. 1. "IPS54,Input Pin Select 54" newline hexmask.long.byte 0xC 20.--23. 1. "IPS53,Input Pin Select 53" hexmask.long.byte 0xC 16.--19. 1. "IPS52,Input Pin Select 52" newline hexmask.long.byte 0xC 12.--15. 1. "IPS51,Input Pin Select 51" hexmask.long.byte 0xC 8.--11. 1. "IPS50,Input Pin Select 50" newline hexmask.long.byte 0xC 4.--7. 1. "IPS49,Input Pin Select 49" hexmask.long.byte 0xC 0.--3. 1. "IPS48,Input Pin Select 48" line.long 0x10 "PISR7,DSPI DSI Parallel Input Select Register 7" hexmask.long.byte 0x10 28.--31. 1. "IPS63,Input Pin Select 63" hexmask.long.byte 0x10 24.--27. 1. "IPS62,Input Pin Select 62" newline hexmask.long.byte 0x10 20.--23. 1. "IPS61,Input Pin Select 61" hexmask.long.byte 0x10 16.--19. 1. "IPS60,Input Pin Select 60" newline hexmask.long.byte 0x10 12.--15. 1. "IPS59,Input Pin Select 59" hexmask.long.byte 0x10 8.--11. 1. "IPS58,Input Pin Select 58" newline hexmask.long.byte 0x10 4.--7. 1. "IPS57,Input Pin Select 57" hexmask.long.byte 0x10 0.--3. 1. "IPS56,Input Pin Select 56" line.long 0x14 "DIMR1,DSPI DSI Deserialized Data Interrupt Mask Register 1" hexmask.long 0x14 0.--31. 1. "MASK,Mask" line.long 0x18 "DPIR1,DSPI DSI Deserialized Data Polarity Interrupt Register 1" hexmask.long 0x18 0.--31. 1. "DP,Data Polarity" line.long 0x1C "CTARE0,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x1C 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x1C 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x20 "CTARE1,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x20 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x20 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x24 "CTARE2,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x24 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x24 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x28 "CTARE3,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x28 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x28 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x2C "CTARE4,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x2C 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x2C 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x30 "CTARE5,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x30 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x30 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x34 "CTARE6,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x34 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x34 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x38 "CTARE7,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x38 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x38 0.--10. 1. "DTCP,Data Transfer Count Preload" rgroup.long 0x13C++0x3 line.long 0x0 "SREX,DSPI Status Register Extended" hexmask.long.byte 0x0 4.--7. 1. "CMDCTR,CMD FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "CMDNXTPTR,Command Next Pointer" tree.end tree "DSPI_6" base ad:0x71AA0000 group.long 0x0++0x3 line.long 0x0 "MCR,DSPI Module Configuration Register" bitfld.long 0x0 31. "MSTR,Master/Slave Mode Select" "0: DSPI is in slave mode.,1: DSPI is in master mode." bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK Enable" "0: Continuous SCK disabled.,1: Continuous SCK enabled." newline bitfld.long 0x0 28.--29. "DCONF,DSPI Configuration" "0: SPI,1: DSI,2: CSI,?" bitfld.long 0x0 27. "FRZ,Freeze" "0: Do not halt serial transfers in debug mode.,1: Halt serial transfers in debug mode." newline bitfld.long 0x0 26. "MTFE,Modified Timing Format Enable" "0: Modified SPI transfer format disabled.,1: Modified SPI transfer format enabled." bitfld.long 0x0 25. "PCSSE,Peripheral Chip Select Strobe Enable" "0: PCS[5]/PCSS is used as the Peripheral Chip..,1: PCS[5]/PCSS is used as an active-low PCS Strobe.." newline bitfld.long 0x0 24. "ROOE,Receive FIFO Overflow Overwrite Enable" "0: Incoming data is ignored.,1: Incoming data is shifted into the shift register." bitfld.long 0x0 23. "PCSIS7,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 22. "PCSIS6,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 21. "PCSIS5,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 20. "PCSIS4,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 19. "PCSIS3,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 18. "PCSIS2,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 17. "PCSIS1,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 16. "PCSIS0,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 14. "MDIS,Module Disable" "0: Enable DSPI clocks.,1: Allow external logic to disable DSPI clocks." newline bitfld.long 0x0 13. "DIS_TXF,Disable Transmit FIFO" "0: Tx FIFO is enabled.,1: Tx FIFO is disabled." bitfld.long 0x0 12. "DIS_RXF,Disable Receive FIFO" "0: Rx FIFO is enabled.,1: Rx FIFO is disabled." newline bitfld.long 0x0 11. "CLR_TXF,Clear TX FIFO" "0: Do not clear the Tx FIFO and CMD FIFO counters.,1: Clears the Tx FIFO and CMD FIFO counters." bitfld.long 0x0 10. "CLR_RXF,Clear RX FIFO" "0: Do not clear the Rx FIFO counter.,1: Clear the Rx FIFO counter." newline bitfld.long 0x0 8.--9. "SMPL_PT,Sample Point" "0: 0 protocol clocks between SCK edge and SIN sample,1: 1 protocol clock between SCK edge and SIN sample,2: 2 protocol clocks between SCK edge and SIN sample,?" bitfld.long 0x0 3. "XSPI,Extended SPI Mode" "0: Normal SPI Mode. Up to 16-bit Frames. Command..,1: Extended SPI Mode. Up to 32-bit SPI Frames." newline bitfld.long 0x0 2. "FCPCS,Fast Continuous PCS Mode." "0: Normal or Slow Continuous PCS mode. Masking of..,1: Fast Continuous PCS mode. Delays masked via.." bitfld.long 0x0 1. "PES,Parity Error Stop" "0: SPI frame transmission continues.,1: SPI frame transmission stops." newline bitfld.long 0x0 0. "HALT,Halt" "0: Start transfers.,1: Stop transfers." rgroup.long 0x4++0x3 line.long 0x0 "HCR,Hardware Configuration Register" bitfld.long 0x0 31. "DSI,DSI features are implemented for the module." "0: DSI features are not implemented DSI registers..,1: DSI features are implemented" bitfld.long 0x0 30. "PISR,PISR0-3 and parallel inputs frame positions selection logic (DSI Muxing Logic) are implemented for the module." "0: PISR0-3 registers are not implemented.,1: PISR0-3 registers are implemented." newline bitfld.long 0x0 29. "DSI64,DSI features in 64 bit mode are implemented for the module." "0: DSI features for 64 bit mode are not..,1: DSI features for 64 bit mode are implemented" bitfld.long 0x0 28. "PISR_EX,PISR4-7 and parallel inputs frame positions selection logic (DSI 64 bit Muxing Logic) are implemented for the module." "0: PISR4-7 registers are not implemented.,1: PISR4-7 registers are implemented." newline bitfld.long 0x0 27. "XSPI,Extended SPI Mode feature is implemented for the module." "0: Extended SPI Mode is not implemented.,1: Extended SPI Mode is implemented." bitfld.long 0x0 24.--26. "CTAR,Maximum implemented CTAR register number." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 20.--23. 1. "TXFR,Maximum implemented TXFR register number." hexmask.long.byte 0x0 16.--19. 1. "RXFR,Maximum implemented RXFR register number." newline hexmask.long.byte 0x0 12.--15. 1. "CMDFR,Maximum implemented command FIFO number." bitfld.long 0x0 11. "MSTR_MODE,Master Mode implementation is enabled" "0,1" newline bitfld.long 0x0 10. "SLV_MODE,Slave Mode implementation is enabled" "0,1" bitfld.long 0x0 9. "TSB_EN,TSB Mode implementation is enabled" "0,1" newline bitfld.long 0x0 8. "ITSB_EN,Interleaved TSB Mode implementation is enabled" "0,1" group.long 0x8++0x7 line.long 0x0 "TCR,DSPI Transfer Count Register" hexmask.long.word 0x0 16.--31. 1. "SPI_TCNT,SPI Transfer Counter" line.long 0x4 "CTAR0,DSPI Clock and Transfer Attributes Register 0 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" group.long 0xC++0x7 line.long 0x0 "CTAR0_SLAVE,When the DSPI is configured as:SPI master - the CTAS field in the command portion of the TX FIFO entry selects which CTAR is used.SPI bus slave - the CTAR0 register is used.DSI master - the DSICTAS field in the DSPI DSI Configuration Register.." hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." bitfld.long 0x0 22. "FMSZ5,MSB of Frame Size when DSI is used in 64-bit Mode" "0,1" line.long 0x4 "CTAR1,DSPI Clock and Transfer Attributes Register 1 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" group.long 0x10++0x27 line.long 0x0 "CTAR1_SLAVE,When the DSPI is configured as:SPI master - the CTAS field in the command portion of the TX FIFO entry selects which CTAR is used.SPI bus slave - the CTAR0 register is used.DSI master - the DSICTAS field in the DSPI DSI Configuration Register.." hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." bitfld.long 0x0 22. "FMSZ5,MSB of Frame Size when DSI is used in 64-bit Mode" "0,1" line.long 0x4 "CTAR2,DSPI Clock and Transfer Attributes Register 2 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x8 "CTAR3,DSPI Clock and Transfer Attributes Register 3 (In Master Mode)" bitfld.long 0x8 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x8 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x8 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x8 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x8 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x8 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x8 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x8 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x8 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x8 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x8 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x8 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x8 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0xC "CTAR4,DSPI Clock and Transfer Attributes Register 4 (In Master Mode)" bitfld.long 0xC 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0xC 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0xC 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0xC 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0xC 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0xC 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0xC 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0xC 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0xC 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0xC 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0xC 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0xC 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x10 "CTAR5,DSPI Clock and Transfer Attributes Register 5 (In Master Mode)" bitfld.long 0x10 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x10 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x10 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x10 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x10 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x10 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x10 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x10 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x10 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x10 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x10 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x10 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x10 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x14 "CTAR6,DSPI Clock and Transfer Attributes Register 6 (In Master Mode)" bitfld.long 0x14 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x14 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x14 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x14 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x14 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x14 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x14 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x14 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x14 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x14 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x14 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x14 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x18 "CTAR7,DSPI Clock and Transfer Attributes Register 7 (In Master Mode)" bitfld.long 0x18 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x18 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x18 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x18 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x18 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x18 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x18 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x18 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x18 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x18 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x18 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x18 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x18 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x1C "SR,DSPI Status Register" bitfld.long 0x1C 31. "TCF,Transfer Complete Flag." "0: Transfer not complete.,1: Transfer complete." bitfld.long 0x1C 30. "TXRXS,TX and RX Status." "0: Transmit and receive operations are disabled..,1: Transmit and receive operations are enabled.." newline bitfld.long 0x1C 29. "SPITCF,SPI Frame Transfer Complete Flag." "0: SPI frame transfer is not complete.,1: SPI frame transfer is complete." bitfld.long 0x1C 28. "EOQF,End of Queue Flag." "0: EOQ is not set in the executing command.,1: EOQ is set in the executing SPI command." newline bitfld.long 0x1C 27. "TFUF,Transmit FIFO Underflow Flag." "0: No Tx FIFO underflow.,1: Tx FIFO underflow has occurred." bitfld.long 0x1C 26. "DSITCF,DSI Frame Transfer Complete Flag." "0: DSI frame transfer is not complete.,1: DSI frame transfer is complete." newline bitfld.long 0x1C 25. "TFFF,Transmit FIFO Fill Flag." "0: Tx FIFO is full.,1: Tx FIFO is not full." bitfld.long 0x1C 24. "BSYF,Busy Flag." "0: No Cyclic Command Transfer in Progress.,1: Cyclic Command Transfer is in progress. Current.." newline bitfld.long 0x1C 23. "CMDTCF,Command Transfer Complete Flag." "0: Data Transfer by current Command not complete.,1: Data Transfer by current Command complete." bitfld.long 0x1C 22. "DPEF,DSI Parity Error Flag." "0: No parity error.,1: Parity error has occurred." newline bitfld.long 0x1C 21. "SPEF,SPI Parity Error Flag." "0: No parity error.,1: Parity error has occurred." bitfld.long 0x1C 20. "DDIF,DSI Data Received with Active Bits." "0: No DSI data with active bits was received.,1: DSI data with active bits was received." newline bitfld.long 0x1C 19. "RFOF,Receive FIFO Overflow Flag." "0: No Rx FIFO overflow.,1: Rx FIFO overflow has occurred." bitfld.long 0x1C 18. "TFIWF,Transmit FIFO Invalid Write Flag." "0: No Invalid Data present in TX FIFO,1: Invalid Data present in TX FIFO since CMD FIFO.." newline bitfld.long 0x1C 17. "RFDF,Receive FIFO Drain Flag." "0: Rx FIFO is empty.,1: Rx FIFO is not empty." bitfld.long 0x1C 16. "CMDFFF,Command FIFO Fill Flag." "0: CMD FIFO is full.,1: CMD FIFO is not full." newline hexmask.long.byte 0x1C 12.--15. 1. "TXCTR,TX FIFO Counter." hexmask.long.byte 0x1C 8.--11. 1. "TXNXTPTR,Transmit Next Pointer." newline hexmask.long.byte 0x1C 4.--7. 1. "RXCTR,RX FIFO Counter." hexmask.long.byte 0x1C 0.--3. 1. "POPNXTPTR,Pop Next Pointer." line.long 0x20 "RSER,DSPI DMA/Interrupt Request Select and Enable Register" bitfld.long 0x20 31. "TCF_RE,Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 30. "CMDFFF_RE,Command FIFO Fill Flag Request Enable." "0: Disabled.,1: Enabled." newline bitfld.long 0x20 29. "SPITCF_RE,SPI Frame Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 28. "EOQF_RE,DSPI Finished Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 27. "TFUF_RE,Transmit FIFO Underflow Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 26. "DSITCF_RE,DSI Frame Transmission Complete Request Enable." "0: Disabled.,1: Enabled." newline bitfld.long 0x20 25. "TFFF_RE,Transmit FIFO Fill Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 24. "TFFF_DIRS,Transmit FIFO Fill DMA or Interrupt Request Select" "0: Interrupt requests.,1: DMA requests." newline bitfld.long 0x20 23. "CMDTCF_RE,Command Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 22. "DPEF_RE,DSI Parity Error Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 21. "SPEF_RE,SPI Parity Error Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 20. "DDIF_RE,DSI data received with active bits Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 19. "RFOF_RE,Receive FIFO Overflow Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 18. "TFIWF_RE,Transmit FIFO Invalid Write Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 17. "RFDF_RE,Receive FIFO Drain Request Enable" "0: Disabled,1: Enabled" bitfld.long 0x20 16. "RFDF_DIRS,Receive FIFO Drain DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." newline bitfld.long 0x20 15. "CMDFFF_DIRS,Command FIFO FIll DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." bitfld.long 0x20 14. "DDIF_DIRS,DSI data received with active bits - DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." line.long 0x24 "PUSHR,DSPI PUSH FIFO Register In Master mode" bitfld.long 0x24 31. "CONT,Continuous Peripheral Chip Select Enable. (SPI master mode)" "0: Return PCSn signals to their inactive state..,1: Keep PCSn signals asserted between transfers." bitfld.long 0x24 28.--30. "CTAS,Clock and Transfer Attributes Select." "0: CTAR0/CTARE0,1: CTAR1/CTARE1,2: CTAR2/CTARE2,3: CTAR3/CTARE3,4: CTAR4/CTARE4,5: CTAR5/CTARE5,6: CTAR6/CTARE6,7: CTAR7/CTARE7" newline bitfld.long 0x24 27. "EOQ,End Of Queue" "0: The SPI data is not the last data to transfer.,1: The SPI data is the last data to transfer." bitfld.long 0x24 26. "CTCNT,Clear Transfer Counter." "0: Do not clear the TCR[SPI_TCNT] field.,1: Clear the TCR[SPI_TCNT] field." newline bitfld.long 0x24 25. "PE_MASC,Parity Enable or Mask tASC delay in the current frame" "0: PE: No parity bit included/checked. MASC: tASC..,1: PE: Parity bit is transmitted instead of the.." bitfld.long 0x24 24. "PP_MCSC,Parity Polarity or Mask tCSC delay in the next frame" "0: PP: Even Parity: the number of 1 bits in the..,1: PP: Odd Parity: the number of 1 bits in the.." newline hexmask.long.byte 0x24 16.--23. 1. "PCS,Select which PCS signals are to be asserted for the transfer." hexmask.long.word 0x24 0.--15. 1. "TXDATA,Transmit Data" group.long 0x34++0x3 line.long 0x0 "PUSHR_SLAVE,PUSHR provides the means to write to the TX FIFO.Data written to this register is transferred to:The TX FIFO for 8- or 16-bit writes to the Data field of PUSHR.In master mode. the register provides 16-bit command to the CMD FIFO and 16-bit.." hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x38++0x13 line.long 0x0 "POPR,DSPI POP FIFO Register" hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data" line.long 0x4 "TXFR0,DSPI Transmit FIFO Registers" hexmask.long.word 0x4 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x4 0.--15. 1. "TXDATA,Transmit Data" line.long 0x8 "TXFR1,DSPI Transmit FIFO Registers" hexmask.long.word 0x8 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x8 0.--15. 1. "TXDATA,Transmit Data" line.long 0xC "TXFR2,DSPI Transmit FIFO Registers" hexmask.long.word 0xC 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0xC 0.--15. 1. "TXDATA,Transmit Data" line.long 0x10 "TXFR3,DSPI Transmit FIFO Registers" hexmask.long.word 0x10 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x10 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x7C++0xF line.long 0x0 "RXFR0,DSPI Receive FIFO Registers" hexmask.long 0x0 0.--31. 1. "RXDATA,Receive Data" line.long 0x4 "RXFR1,DSPI Receive FIFO Registers" hexmask.long 0x4 0.--31. 1. "RXDATA,Receive Data" line.long 0x8 "RXFR2,DSPI Receive FIFO Registers" hexmask.long 0x8 0.--31. 1. "RXDATA,Receive Data" line.long 0xC "RXFR3,DSPI Receive FIFO Registers" hexmask.long 0xC 0.--31. 1. "RXDATA,Receive Data" group.long 0xBC++0x3 line.long 0x0 "DSICR0,DSPI DSI Configuration Register 0" bitfld.long 0x0 30. "FMSZ4,MSB of the frame size in master mode when DSI is used in 32-bit mode." "0,1" bitfld.long 0x0 23. "FMSZ5,MSB of the frame size in master mode when DSI is used in 64-bit mode." "0,1" newline bitfld.long 0x0 21. "ITSB,Interleaved TSB mode." "0: Disabled.,1: Enabled." bitfld.long 0x0 20. "TSBC,Timed Serial Bus Configuration." "0: Disabled.,1: Enabled." newline bitfld.long 0x0 19. "TXSS,Transmit Data Source Select." "0: SDR source.,1: ASDR source." bitfld.long 0x0 18. "TPOL,Trigger Polarity" "0: Falling edge initiates a transfer.,1: Rising edge initiates a transfer." newline bitfld.long 0x0 16. "CID,Change In Data Transfer Enable" "0: Disabled.,1: Enabled." bitfld.long 0x0 15. "DCONT,DSI Continuous Peripheral Chip Select Enable (DSI Master mode only)" "0: PCS signals return to inactive.,1: PCS signals remain asserted." newline bitfld.long 0x0 12.--14. "DSICTAS,DSI Clock and Transfer Attributes Select (DSI Master mode only)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "DMS,Data Match Stop" "0: Disabled.,1: Enabled." newline bitfld.long 0x0 10. "PES,Parity Error Stop" "0: Disabled.,1: Enabled." bitfld.long 0x0 9. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of the last.." newline bitfld.long 0x0 8. "PP,Parity Polarity" "0: Even Parity: the number of '1' bits in the..,1: Odd Parity: the number of 1 bits in the.." hexmask.long.byte 0x0 0.--7. 1. "DPCSX,DSI Peripheral Chip Select 07" rgroup.long 0xC0++0x3 line.long 0x0 "SDR0,DSPI DSI Serialization Data Register 0" hexmask.long 0x0 0.--31. 1. "SER_DATA,Serialized Data" group.long 0xC4++0x3 line.long 0x0 "ASDR0,DSPI DSI Alternate Serialization Data Register 0" hexmask.long 0x0 0.--31. 1. "ASER_DATA,Alternate Serialized Data" rgroup.long 0xC8++0x7 line.long 0x0 "COMPR0,DSPI DSI Transmit Comparison Register 0" hexmask.long 0x0 0.--31. 1. "COMP_DATA,Compare Data" line.long 0x4 "DDR0,DSPI DSI Deserialization Data Register 0" hexmask.long 0x4 0.--31. 1. "DESER_DATA,Deserialized Data" group.long 0xD0++0x1F line.long 0x0 "DSICR1,DSPI DSI Configuration Register 1" hexmask.long.byte 0x0 24.--29. 1. "TSBCNT,Timed Serial Bus Operation Count" bitfld.long 0x0 18. "DSI64E,DSI 64-bit Mode Enable" "0: Disabled. DSI Mode operates in the default..,1: Enabled. DSI Mode operates in 64-bit configuration" newline bitfld.long 0x0 17. "DSE1,Data Select Enable 1" "0: No Zero bit is inserted in the middle of the..,1: Zero bit is inserted at the middle of the data.." bitfld.long 0x0 16. "DSE0,Data Select Enable 0" "0: No Zero bit is inserted in the beginning of the..,1: Zero bit is inserted at the beginning of the.." newline hexmask.long.byte 0x0 8.--15. 1. "TRGPRD,Internal Trigger Period for the ITSB mode." hexmask.long.byte 0x0 0.--7. 1. "DPCS1_X,DSI Peripheral Chip Select 07" line.long 0x4 "SSR0,DSPI DSI Serialization Source Select Register 0" hexmask.long 0x4 0.--31. 1. "SS,Source Select" line.long 0x8 "PISR0,DSPI DSI Parallel Input Select Register 0" hexmask.long.byte 0x8 28.--31. 1. "IPS7,Input Pin Select 7" hexmask.long.byte 0x8 24.--27. 1. "IPS6,Input Pin Select 6" newline hexmask.long.byte 0x8 20.--23. 1. "IPS5,Input Pin Select 5" hexmask.long.byte 0x8 16.--19. 1. "IPS4,Input Pin Select 5" newline hexmask.long.byte 0x8 12.--15. 1. "IPS3,Input Pin Select 3" hexmask.long.byte 0x8 8.--11. 1. "IPS2,Input Pin Select 2" newline hexmask.long.byte 0x8 4.--7. 1. "IPS1,Input Pin Select 1" hexmask.long.byte 0x8 0.--3. 1. "IPS0,Input Pin Select 0" line.long 0xC "PISR1,DSPI DSI Parallel Input Select Register 1" hexmask.long.byte 0xC 28.--31. 1. "IPS15,Input Pin Select 15" hexmask.long.byte 0xC 24.--27. 1. "IPS14,Input Pin Select 14" newline hexmask.long.byte 0xC 20.--23. 1. "IPS13,Input Pin Select 13" hexmask.long.byte 0xC 16.--19. 1. "IPS12,Input Pin Select 12" newline hexmask.long.byte 0xC 12.--15. 1. "IPS11,Input Pin Select 11" hexmask.long.byte 0xC 8.--11. 1. "IPS10,Input Pin Select 10" newline hexmask.long.byte 0xC 4.--7. 1. "IPS9,Input Pin Select 9" hexmask.long.byte 0xC 0.--3. 1. "IPS8,Input Pin Select 8" line.long 0x10 "PISR2,DSPI DSI Parallel Input Select Register 2" hexmask.long.byte 0x10 28.--31. 1. "IPS23,Input Pin Select 23" hexmask.long.byte 0x10 24.--27. 1. "IPS22,Input Pin Select 22" newline hexmask.long.byte 0x10 20.--23. 1. "IPS21,Input Pin Select 21" hexmask.long.byte 0x10 16.--19. 1. "IPS20,Input Pin Select 20" newline hexmask.long.byte 0x10 12.--15. 1. "IPS19,Input Pin Select 19" hexmask.long.byte 0x10 8.--11. 1. "IPS18,Input Pin Select 18" newline hexmask.long.byte 0x10 4.--7. 1. "IPS17,Input Pin Select 17" hexmask.long.byte 0x10 0.--3. 1. "IPS16,Input Pin Select 16" line.long 0x14 "PISR3,DSPI DSI Parallel Input Select Register 3" hexmask.long.byte 0x14 28.--31. 1. "IPS31,Input Pin Select 31" hexmask.long.byte 0x14 24.--27. 1. "IPS30,Input Pin Select 30" newline hexmask.long.byte 0x14 20.--23. 1. "IPS29,Input Pin Select 29" hexmask.long.byte 0x14 16.--19. 1. "IPS28,Input Pin Select 28" newline hexmask.long.byte 0x14 12.--15. 1. "IPS27,Input Pin Select 27" hexmask.long.byte 0x14 8.--11. 1. "IPS26,Input Pin Select 26" newline hexmask.long.byte 0x14 4.--7. 1. "IPS25,Input Pin Select 25" hexmask.long.byte 0x14 0.--3. 1. "IPS24,Input Pin Select 24" line.long 0x18 "DIMR0,DSPI DSI Deserialized Data Interrupt Mask Register 0" hexmask.long 0x18 0.--31. 1. "MASK,Mask" line.long 0x1C "DPIR0,DSPI DSI Deserialized Data Polarity Interrupt Register 0" hexmask.long 0x1C 0.--31. 1. "DP,Data Polarity" rgroup.long 0xF0++0x3 line.long 0x0 "SDR1,DSPI DSI Serialization Data Register 1" hexmask.long 0x0 0.--31. 1. "SER_DATA,Serialized Data" group.long 0xF4++0x3 line.long 0x0 "ASDR1,DSPI DSI Alternate Serialization Data Register 1" hexmask.long 0x0 0.--31. 1. "ASER_DATA,Alternate Serialized Data" rgroup.long 0xF8++0x7 line.long 0x0 "COMPR1,DSPI DSI Transmit Comparison Register 1" hexmask.long 0x0 0.--31. 1. "COMP_DATA,Compare Data" line.long 0x4 "DDR1,DSPI DSI Deserialization Data Register 1" hexmask.long 0x4 0.--31. 1. "DESER_DATA,Deserialized Data" group.long 0x100++0x3B line.long 0x0 "SSR1,DSPI DSI Serialization Source Select Register 1" hexmask.long 0x0 0.--31. 1. "SS,Source Select" line.long 0x4 "PISR4,DSPI DSI Parallel Input Select Register 4" hexmask.long.byte 0x4 28.--31. 1. "IPS39,Input Pin Select 39" hexmask.long.byte 0x4 24.--27. 1. "IPS38,Input Pin Select 38" newline hexmask.long.byte 0x4 20.--23. 1. "IPS37,Input Pin Select 37" hexmask.long.byte 0x4 16.--19. 1. "IPS36,Input Pin Select 36" newline hexmask.long.byte 0x4 12.--15. 1. "IPS35,Input Pin Select 35" hexmask.long.byte 0x4 8.--11. 1. "IPS34,Input Pin Select 34" newline hexmask.long.byte 0x4 4.--7. 1. "IPS33,Input Pin Select 33" hexmask.long.byte 0x4 0.--3. 1. "IPS32,Input Pin Select 32" line.long 0x8 "PISR5,DSPI DSI Parallel Input Select Register 5" hexmask.long.byte 0x8 28.--31. 1. "IPS47,Input Pin Select 47" hexmask.long.byte 0x8 24.--27. 1. "IPS46,Input Pin Select 46" newline hexmask.long.byte 0x8 20.--23. 1. "IPS45,Input Pin Select 45" hexmask.long.byte 0x8 16.--19. 1. "IPS44,Input Pin Select 44" newline hexmask.long.byte 0x8 12.--15. 1. "IPS43,Input Pin Select 43" hexmask.long.byte 0x8 8.--11. 1. "IPS42,Input Pin Select 42" newline hexmask.long.byte 0x8 4.--7. 1. "IPS41,Input Pin Select 41" hexmask.long.byte 0x8 0.--3. 1. "IPS40,Input Pin Select 40" line.long 0xC "PISR6,DSPI DSI Parallel Input Select Register 6" hexmask.long.byte 0xC 28.--31. 1. "IPS55,Input Pin Select 55" hexmask.long.byte 0xC 24.--27. 1. "IPS54,Input Pin Select 54" newline hexmask.long.byte 0xC 20.--23. 1. "IPS53,Input Pin Select 53" hexmask.long.byte 0xC 16.--19. 1. "IPS52,Input Pin Select 52" newline hexmask.long.byte 0xC 12.--15. 1. "IPS51,Input Pin Select 51" hexmask.long.byte 0xC 8.--11. 1. "IPS50,Input Pin Select 50" newline hexmask.long.byte 0xC 4.--7. 1. "IPS49,Input Pin Select 49" hexmask.long.byte 0xC 0.--3. 1. "IPS48,Input Pin Select 48" line.long 0x10 "PISR7,DSPI DSI Parallel Input Select Register 7" hexmask.long.byte 0x10 28.--31. 1. "IPS63,Input Pin Select 63" hexmask.long.byte 0x10 24.--27. 1. "IPS62,Input Pin Select 62" newline hexmask.long.byte 0x10 20.--23. 1. "IPS61,Input Pin Select 61" hexmask.long.byte 0x10 16.--19. 1. "IPS60,Input Pin Select 60" newline hexmask.long.byte 0x10 12.--15. 1. "IPS59,Input Pin Select 59" hexmask.long.byte 0x10 8.--11. 1. "IPS58,Input Pin Select 58" newline hexmask.long.byte 0x10 4.--7. 1. "IPS57,Input Pin Select 57" hexmask.long.byte 0x10 0.--3. 1. "IPS56,Input Pin Select 56" line.long 0x14 "DIMR1,DSPI DSI Deserialized Data Interrupt Mask Register 1" hexmask.long 0x14 0.--31. 1. "MASK,Mask" line.long 0x18 "DPIR1,DSPI DSI Deserialized Data Polarity Interrupt Register 1" hexmask.long 0x18 0.--31. 1. "DP,Data Polarity" line.long 0x1C "CTARE0,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x1C 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x1C 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x20 "CTARE1,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x20 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x20 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x24 "CTARE2,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x24 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x24 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x28 "CTARE3,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x28 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x28 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x2C "CTARE4,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x2C 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x2C 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x30 "CTARE5,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x30 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x30 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x34 "CTARE6,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x34 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x34 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x38 "CTARE7,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x38 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x38 0.--10. 1. "DTCP,Data Transfer Count Preload" rgroup.long 0x13C++0x3 line.long 0x0 "SREX,DSPI Status Register Extended" hexmask.long.byte 0x0 4.--7. 1. "CMDCTR,CMD FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "CMDNXTPTR,Command Next Pointer" tree.end tree "DSPI_7" base ad:0x7145C000 group.long 0x0++0x3 line.long 0x0 "MCR,DSPI Module Configuration Register" bitfld.long 0x0 31. "MSTR,Master/Slave Mode Select" "0: DSPI is in slave mode.,1: DSPI is in master mode." bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK Enable" "0: Continuous SCK disabled.,1: Continuous SCK enabled." newline bitfld.long 0x0 28.--29. "DCONF,DSPI Configuration" "0: SPI,1: DSI,2: CSI,?" bitfld.long 0x0 27. "FRZ,Freeze" "0: Do not halt serial transfers in debug mode.,1: Halt serial transfers in debug mode." newline bitfld.long 0x0 26. "MTFE,Modified Timing Format Enable" "0: Modified SPI transfer format disabled.,1: Modified SPI transfer format enabled." bitfld.long 0x0 25. "PCSSE,Peripheral Chip Select Strobe Enable" "0: PCS[5]/PCSS is used as the Peripheral Chip..,1: PCS[5]/PCSS is used as an active-low PCS Strobe.." newline bitfld.long 0x0 24. "ROOE,Receive FIFO Overflow Overwrite Enable" "0: Incoming data is ignored.,1: Incoming data is shifted into the shift register." bitfld.long 0x0 23. "PCSIS7,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 22. "PCSIS6,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 21. "PCSIS5,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 20. "PCSIS4,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 19. "PCSIS3,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 18. "PCSIS2,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 17. "PCSIS1,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 16. "PCSIS0,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 14. "MDIS,Module Disable" "0: Enable DSPI clocks.,1: Allow external logic to disable DSPI clocks." newline bitfld.long 0x0 13. "DIS_TXF,Disable Transmit FIFO" "0: Tx FIFO is enabled.,1: Tx FIFO is disabled." bitfld.long 0x0 12. "DIS_RXF,Disable Receive FIFO" "0: Rx FIFO is enabled.,1: Rx FIFO is disabled." newline bitfld.long 0x0 11. "CLR_TXF,Clear TX FIFO" "0: Do not clear the Tx FIFO and CMD FIFO counters.,1: Clears the Tx FIFO and CMD FIFO counters." bitfld.long 0x0 10. "CLR_RXF,Clear RX FIFO" "0: Do not clear the Rx FIFO counter.,1: Clear the Rx FIFO counter." newline bitfld.long 0x0 8.--9. "SMPL_PT,Sample Point" "0: 0 protocol clocks between SCK edge and SIN sample,1: 1 protocol clock between SCK edge and SIN sample,2: 2 protocol clocks between SCK edge and SIN sample,?" bitfld.long 0x0 3. "XSPI,Extended SPI Mode" "0: Normal SPI Mode. Up to 16-bit Frames. Command..,1: Extended SPI Mode. Up to 32-bit SPI Frames." newline bitfld.long 0x0 2. "FCPCS,Fast Continuous PCS Mode." "0: Normal or Slow Continuous PCS mode. Masking of..,1: Fast Continuous PCS mode. Delays masked via.." bitfld.long 0x0 1. "PES,Parity Error Stop" "0: SPI frame transmission continues.,1: SPI frame transmission stops." newline bitfld.long 0x0 0. "HALT,Halt" "0: Start transfers.,1: Stop transfers." rgroup.long 0x4++0x3 line.long 0x0 "HCR,Hardware Configuration Register" bitfld.long 0x0 31. "DSI,DSI features are implemented for the module." "0: DSI features are not implemented DSI registers..,1: DSI features are implemented" bitfld.long 0x0 30. "PISR,PISR0-3 and parallel inputs frame positions selection logic (DSI Muxing Logic) are implemented for the module." "0: PISR0-3 registers are not implemented.,1: PISR0-3 registers are implemented." newline bitfld.long 0x0 29. "DSI64,DSI features in 64 bit mode are implemented for the module." "0: DSI features for 64 bit mode are not..,1: DSI features for 64 bit mode are implemented" bitfld.long 0x0 28. "PISR_EX,PISR4-7 and parallel inputs frame positions selection logic (DSI 64 bit Muxing Logic) are implemented for the module." "0: PISR4-7 registers are not implemented.,1: PISR4-7 registers are implemented." newline bitfld.long 0x0 27. "XSPI,Extended SPI Mode feature is implemented for the module." "0: Extended SPI Mode is not implemented.,1: Extended SPI Mode is implemented." bitfld.long 0x0 24.--26. "CTAR,Maximum implemented CTAR register number." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 20.--23. 1. "TXFR,Maximum implemented TXFR register number." hexmask.long.byte 0x0 16.--19. 1. "RXFR,Maximum implemented RXFR register number." newline hexmask.long.byte 0x0 12.--15. 1. "CMDFR,Maximum implemented command FIFO number." bitfld.long 0x0 11. "MSTR_MODE,Master Mode implementation is enabled" "0,1" newline bitfld.long 0x0 10. "SLV_MODE,Slave Mode implementation is enabled" "0,1" bitfld.long 0x0 9. "TSB_EN,TSB Mode implementation is enabled" "0,1" newline bitfld.long 0x0 8. "ITSB_EN,Interleaved TSB Mode implementation is enabled" "0,1" group.long 0x8++0x7 line.long 0x0 "TCR,DSPI Transfer Count Register" hexmask.long.word 0x0 16.--31. 1. "SPI_TCNT,SPI Transfer Counter" line.long 0x4 "CTAR0,DSPI Clock and Transfer Attributes Register 0 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" group.long 0xC++0x7 line.long 0x0 "CTAR0_SLAVE,When the DSPI is configured as:SPI master - the CTAS field in the command portion of the TX FIFO entry selects which CTAR is used.SPI bus slave - the CTAR0 register is used.DSI master - the DSICTAS field in the DSPI DSI Configuration Register.." hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." bitfld.long 0x0 22. "FMSZ5,MSB of Frame Size when DSI is used in 64-bit Mode" "0,1" line.long 0x4 "CTAR1,DSPI Clock and Transfer Attributes Register 1 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" group.long 0x10++0x27 line.long 0x0 "CTAR1_SLAVE,When the DSPI is configured as:SPI master - the CTAS field in the command portion of the TX FIFO entry selects which CTAR is used.SPI bus slave - the CTAR0 register is used.DSI master - the DSICTAS field in the DSPI DSI Configuration Register.." hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." bitfld.long 0x0 22. "FMSZ5,MSB of Frame Size when DSI is used in 64-bit Mode" "0,1" line.long 0x4 "CTAR2,DSPI Clock and Transfer Attributes Register 2 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x8 "CTAR3,DSPI Clock and Transfer Attributes Register 3 (In Master Mode)" bitfld.long 0x8 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x8 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x8 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x8 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x8 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x8 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x8 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x8 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x8 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x8 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x8 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x8 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x8 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0xC "CTAR4,DSPI Clock and Transfer Attributes Register 4 (In Master Mode)" bitfld.long 0xC 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0xC 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0xC 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0xC 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0xC 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0xC 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0xC 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0xC 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0xC 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0xC 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0xC 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0xC 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x10 "CTAR5,DSPI Clock and Transfer Attributes Register 5 (In Master Mode)" bitfld.long 0x10 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x10 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x10 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x10 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x10 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x10 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x10 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x10 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x10 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x10 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x10 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x10 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x10 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x14 "CTAR6,DSPI Clock and Transfer Attributes Register 6 (In Master Mode)" bitfld.long 0x14 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x14 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x14 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x14 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x14 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x14 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x14 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x14 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x14 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x14 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x14 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x14 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x18 "CTAR7,DSPI Clock and Transfer Attributes Register 7 (In Master Mode)" bitfld.long 0x18 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x18 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x18 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x18 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x18 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x18 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x18 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x18 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x18 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x18 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x18 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x18 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x18 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x1C "SR,DSPI Status Register" bitfld.long 0x1C 31. "TCF,Transfer Complete Flag." "0: Transfer not complete.,1: Transfer complete." bitfld.long 0x1C 30. "TXRXS,TX and RX Status." "0: Transmit and receive operations are disabled..,1: Transmit and receive operations are enabled.." newline bitfld.long 0x1C 29. "SPITCF,SPI Frame Transfer Complete Flag." "0: SPI frame transfer is not complete.,1: SPI frame transfer is complete." bitfld.long 0x1C 28. "EOQF,End of Queue Flag." "0: EOQ is not set in the executing command.,1: EOQ is set in the executing SPI command." newline bitfld.long 0x1C 27. "TFUF,Transmit FIFO Underflow Flag." "0: No Tx FIFO underflow.,1: Tx FIFO underflow has occurred." bitfld.long 0x1C 26. "DSITCF,DSI Frame Transfer Complete Flag." "0: DSI frame transfer is not complete.,1: DSI frame transfer is complete." newline bitfld.long 0x1C 25. "TFFF,Transmit FIFO Fill Flag." "0: Tx FIFO is full.,1: Tx FIFO is not full." bitfld.long 0x1C 24. "BSYF,Busy Flag." "0: No Cyclic Command Transfer in Progress.,1: Cyclic Command Transfer is in progress. Current.." newline bitfld.long 0x1C 23. "CMDTCF,Command Transfer Complete Flag." "0: Data Transfer by current Command not complete.,1: Data Transfer by current Command complete." bitfld.long 0x1C 22. "DPEF,DSI Parity Error Flag." "0: No parity error.,1: Parity error has occurred." newline bitfld.long 0x1C 21. "SPEF,SPI Parity Error Flag." "0: No parity error.,1: Parity error has occurred." bitfld.long 0x1C 20. "DDIF,DSI Data Received with Active Bits." "0: No DSI data with active bits was received.,1: DSI data with active bits was received." newline bitfld.long 0x1C 19. "RFOF,Receive FIFO Overflow Flag." "0: No Rx FIFO overflow.,1: Rx FIFO overflow has occurred." bitfld.long 0x1C 18. "TFIWF,Transmit FIFO Invalid Write Flag." "0: No Invalid Data present in TX FIFO,1: Invalid Data present in TX FIFO since CMD FIFO.." newline bitfld.long 0x1C 17. "RFDF,Receive FIFO Drain Flag." "0: Rx FIFO is empty.,1: Rx FIFO is not empty." bitfld.long 0x1C 16. "CMDFFF,Command FIFO Fill Flag." "0: CMD FIFO is full.,1: CMD FIFO is not full." newline hexmask.long.byte 0x1C 12.--15. 1. "TXCTR,TX FIFO Counter." hexmask.long.byte 0x1C 8.--11. 1. "TXNXTPTR,Transmit Next Pointer." newline hexmask.long.byte 0x1C 4.--7. 1. "RXCTR,RX FIFO Counter." hexmask.long.byte 0x1C 0.--3. 1. "POPNXTPTR,Pop Next Pointer." line.long 0x20 "RSER,DSPI DMA/Interrupt Request Select and Enable Register" bitfld.long 0x20 31. "TCF_RE,Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 30. "CMDFFF_RE,Command FIFO Fill Flag Request Enable." "0: Disabled.,1: Enabled." newline bitfld.long 0x20 29. "SPITCF_RE,SPI Frame Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 28. "EOQF_RE,DSPI Finished Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 27. "TFUF_RE,Transmit FIFO Underflow Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 26. "DSITCF_RE,DSI Frame Transmission Complete Request Enable." "0: Disabled.,1: Enabled." newline bitfld.long 0x20 25. "TFFF_RE,Transmit FIFO Fill Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 24. "TFFF_DIRS,Transmit FIFO Fill DMA or Interrupt Request Select" "0: Interrupt requests.,1: DMA requests." newline bitfld.long 0x20 23. "CMDTCF_RE,Command Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 22. "DPEF_RE,DSI Parity Error Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 21. "SPEF_RE,SPI Parity Error Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 20. "DDIF_RE,DSI data received with active bits Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 19. "RFOF_RE,Receive FIFO Overflow Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 18. "TFIWF_RE,Transmit FIFO Invalid Write Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 17. "RFDF_RE,Receive FIFO Drain Request Enable" "0: Disabled,1: Enabled" bitfld.long 0x20 16. "RFDF_DIRS,Receive FIFO Drain DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." newline bitfld.long 0x20 15. "CMDFFF_DIRS,Command FIFO FIll DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." bitfld.long 0x20 14. "DDIF_DIRS,DSI data received with active bits - DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." line.long 0x24 "PUSHR,DSPI PUSH FIFO Register In Master mode" bitfld.long 0x24 31. "CONT,Continuous Peripheral Chip Select Enable. (SPI master mode)" "0: Return PCSn signals to their inactive state..,1: Keep PCSn signals asserted between transfers." bitfld.long 0x24 28.--30. "CTAS,Clock and Transfer Attributes Select." "0: CTAR0/CTARE0,1: CTAR1/CTARE1,2: CTAR2/CTARE2,3: CTAR3/CTARE3,4: CTAR4/CTARE4,5: CTAR5/CTARE5,6: CTAR6/CTARE6,7: CTAR7/CTARE7" newline bitfld.long 0x24 27. "EOQ,End Of Queue" "0: The SPI data is not the last data to transfer.,1: The SPI data is the last data to transfer." bitfld.long 0x24 26. "CTCNT,Clear Transfer Counter." "0: Do not clear the TCR[SPI_TCNT] field.,1: Clear the TCR[SPI_TCNT] field." newline bitfld.long 0x24 25. "PE_MASC,Parity Enable or Mask tASC delay in the current frame" "0: PE: No parity bit included/checked. MASC: tASC..,1: PE: Parity bit is transmitted instead of the.." bitfld.long 0x24 24. "PP_MCSC,Parity Polarity or Mask tCSC delay in the next frame" "0: PP: Even Parity: the number of 1 bits in the..,1: PP: Odd Parity: the number of 1 bits in the.." newline hexmask.long.byte 0x24 16.--23. 1. "PCS,Select which PCS signals are to be asserted for the transfer." hexmask.long.word 0x24 0.--15. 1. "TXDATA,Transmit Data" group.long 0x34++0x3 line.long 0x0 "PUSHR_SLAVE,PUSHR provides the means to write to the TX FIFO.Data written to this register is transferred to:The TX FIFO for 8- or 16-bit writes to the Data field of PUSHR.In master mode. the register provides 16-bit command to the CMD FIFO and 16-bit.." hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x38++0x13 line.long 0x0 "POPR,DSPI POP FIFO Register" hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data" line.long 0x4 "TXFR0,DSPI Transmit FIFO Registers" hexmask.long.word 0x4 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x4 0.--15. 1. "TXDATA,Transmit Data" line.long 0x8 "TXFR1,DSPI Transmit FIFO Registers" hexmask.long.word 0x8 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x8 0.--15. 1. "TXDATA,Transmit Data" line.long 0xC "TXFR2,DSPI Transmit FIFO Registers" hexmask.long.word 0xC 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0xC 0.--15. 1. "TXDATA,Transmit Data" line.long 0x10 "TXFR3,DSPI Transmit FIFO Registers" hexmask.long.word 0x10 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x10 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x7C++0xF line.long 0x0 "RXFR0,DSPI Receive FIFO Registers" hexmask.long 0x0 0.--31. 1. "RXDATA,Receive Data" line.long 0x4 "RXFR1,DSPI Receive FIFO Registers" hexmask.long 0x4 0.--31. 1. "RXDATA,Receive Data" line.long 0x8 "RXFR2,DSPI Receive FIFO Registers" hexmask.long 0x8 0.--31. 1. "RXDATA,Receive Data" line.long 0xC "RXFR3,DSPI Receive FIFO Registers" hexmask.long 0xC 0.--31. 1. "RXDATA,Receive Data" group.long 0xBC++0x3 line.long 0x0 "DSICR0,DSPI DSI Configuration Register 0" bitfld.long 0x0 30. "FMSZ4,MSB of the frame size in master mode when DSI is used in 32-bit mode." "0,1" bitfld.long 0x0 23. "FMSZ5,MSB of the frame size in master mode when DSI is used in 64-bit mode." "0,1" newline bitfld.long 0x0 21. "ITSB,Interleaved TSB mode." "0: Disabled.,1: Enabled." bitfld.long 0x0 20. "TSBC,Timed Serial Bus Configuration." "0: Disabled.,1: Enabled." newline bitfld.long 0x0 19. "TXSS,Transmit Data Source Select." "0: SDR source.,1: ASDR source." bitfld.long 0x0 18. "TPOL,Trigger Polarity" "0: Falling edge initiates a transfer.,1: Rising edge initiates a transfer." newline bitfld.long 0x0 16. "CID,Change In Data Transfer Enable" "0: Disabled.,1: Enabled." bitfld.long 0x0 15. "DCONT,DSI Continuous Peripheral Chip Select Enable (DSI Master mode only)" "0: PCS signals return to inactive.,1: PCS signals remain asserted." newline bitfld.long 0x0 12.--14. "DSICTAS,DSI Clock and Transfer Attributes Select (DSI Master mode only)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "DMS,Data Match Stop" "0: Disabled.,1: Enabled." newline bitfld.long 0x0 10. "PES,Parity Error Stop" "0: Disabled.,1: Enabled." bitfld.long 0x0 9. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of the last.." newline bitfld.long 0x0 8. "PP,Parity Polarity" "0: Even Parity: the number of '1' bits in the..,1: Odd Parity: the number of 1 bits in the.." hexmask.long.byte 0x0 0.--7. 1. "DPCSX,DSI Peripheral Chip Select 07" rgroup.long 0xC0++0x3 line.long 0x0 "SDR0,DSPI DSI Serialization Data Register 0" hexmask.long 0x0 0.--31. 1. "SER_DATA,Serialized Data" group.long 0xC4++0x3 line.long 0x0 "ASDR0,DSPI DSI Alternate Serialization Data Register 0" hexmask.long 0x0 0.--31. 1. "ASER_DATA,Alternate Serialized Data" rgroup.long 0xC8++0x7 line.long 0x0 "COMPR0,DSPI DSI Transmit Comparison Register 0" hexmask.long 0x0 0.--31. 1. "COMP_DATA,Compare Data" line.long 0x4 "DDR0,DSPI DSI Deserialization Data Register 0" hexmask.long 0x4 0.--31. 1. "DESER_DATA,Deserialized Data" group.long 0xD0++0x1F line.long 0x0 "DSICR1,DSPI DSI Configuration Register 1" hexmask.long.byte 0x0 24.--29. 1. "TSBCNT,Timed Serial Bus Operation Count" bitfld.long 0x0 18. "DSI64E,DSI 64-bit Mode Enable" "0: Disabled. DSI Mode operates in the default..,1: Enabled. DSI Mode operates in 64-bit configuration" newline bitfld.long 0x0 17. "DSE1,Data Select Enable 1" "0: No Zero bit is inserted in the middle of the..,1: Zero bit is inserted at the middle of the data.." bitfld.long 0x0 16. "DSE0,Data Select Enable 0" "0: No Zero bit is inserted in the beginning of the..,1: Zero bit is inserted at the beginning of the.." newline hexmask.long.byte 0x0 8.--15. 1. "TRGPRD,Internal Trigger Period for the ITSB mode." hexmask.long.byte 0x0 0.--7. 1. "DPCS1_X,DSI Peripheral Chip Select 07" line.long 0x4 "SSR0,DSPI DSI Serialization Source Select Register 0" hexmask.long 0x4 0.--31. 1. "SS,Source Select" line.long 0x8 "PISR0,DSPI DSI Parallel Input Select Register 0" hexmask.long.byte 0x8 28.--31. 1. "IPS7,Input Pin Select 7" hexmask.long.byte 0x8 24.--27. 1. "IPS6,Input Pin Select 6" newline hexmask.long.byte 0x8 20.--23. 1. "IPS5,Input Pin Select 5" hexmask.long.byte 0x8 16.--19. 1. "IPS4,Input Pin Select 5" newline hexmask.long.byte 0x8 12.--15. 1. "IPS3,Input Pin Select 3" hexmask.long.byte 0x8 8.--11. 1. "IPS2,Input Pin Select 2" newline hexmask.long.byte 0x8 4.--7. 1. "IPS1,Input Pin Select 1" hexmask.long.byte 0x8 0.--3. 1. "IPS0,Input Pin Select 0" line.long 0xC "PISR1,DSPI DSI Parallel Input Select Register 1" hexmask.long.byte 0xC 28.--31. 1. "IPS15,Input Pin Select 15" hexmask.long.byte 0xC 24.--27. 1. "IPS14,Input Pin Select 14" newline hexmask.long.byte 0xC 20.--23. 1. "IPS13,Input Pin Select 13" hexmask.long.byte 0xC 16.--19. 1. "IPS12,Input Pin Select 12" newline hexmask.long.byte 0xC 12.--15. 1. "IPS11,Input Pin Select 11" hexmask.long.byte 0xC 8.--11. 1. "IPS10,Input Pin Select 10" newline hexmask.long.byte 0xC 4.--7. 1. "IPS9,Input Pin Select 9" hexmask.long.byte 0xC 0.--3. 1. "IPS8,Input Pin Select 8" line.long 0x10 "PISR2,DSPI DSI Parallel Input Select Register 2" hexmask.long.byte 0x10 28.--31. 1. "IPS23,Input Pin Select 23" hexmask.long.byte 0x10 24.--27. 1. "IPS22,Input Pin Select 22" newline hexmask.long.byte 0x10 20.--23. 1. "IPS21,Input Pin Select 21" hexmask.long.byte 0x10 16.--19. 1. "IPS20,Input Pin Select 20" newline hexmask.long.byte 0x10 12.--15. 1. "IPS19,Input Pin Select 19" hexmask.long.byte 0x10 8.--11. 1. "IPS18,Input Pin Select 18" newline hexmask.long.byte 0x10 4.--7. 1. "IPS17,Input Pin Select 17" hexmask.long.byte 0x10 0.--3. 1. "IPS16,Input Pin Select 16" line.long 0x14 "PISR3,DSPI DSI Parallel Input Select Register 3" hexmask.long.byte 0x14 28.--31. 1. "IPS31,Input Pin Select 31" hexmask.long.byte 0x14 24.--27. 1. "IPS30,Input Pin Select 30" newline hexmask.long.byte 0x14 20.--23. 1. "IPS29,Input Pin Select 29" hexmask.long.byte 0x14 16.--19. 1. "IPS28,Input Pin Select 28" newline hexmask.long.byte 0x14 12.--15. 1. "IPS27,Input Pin Select 27" hexmask.long.byte 0x14 8.--11. 1. "IPS26,Input Pin Select 26" newline hexmask.long.byte 0x14 4.--7. 1. "IPS25,Input Pin Select 25" hexmask.long.byte 0x14 0.--3. 1. "IPS24,Input Pin Select 24" line.long 0x18 "DIMR0,DSPI DSI Deserialized Data Interrupt Mask Register 0" hexmask.long 0x18 0.--31. 1. "MASK,Mask" line.long 0x1C "DPIR0,DSPI DSI Deserialized Data Polarity Interrupt Register 0" hexmask.long 0x1C 0.--31. 1. "DP,Data Polarity" rgroup.long 0xF0++0x3 line.long 0x0 "SDR1,DSPI DSI Serialization Data Register 1" hexmask.long 0x0 0.--31. 1. "SER_DATA,Serialized Data" group.long 0xF4++0x3 line.long 0x0 "ASDR1,DSPI DSI Alternate Serialization Data Register 1" hexmask.long 0x0 0.--31. 1. "ASER_DATA,Alternate Serialized Data" rgroup.long 0xF8++0x7 line.long 0x0 "COMPR1,DSPI DSI Transmit Comparison Register 1" hexmask.long 0x0 0.--31. 1. "COMP_DATA,Compare Data" line.long 0x4 "DDR1,DSPI DSI Deserialization Data Register 1" hexmask.long 0x4 0.--31. 1. "DESER_DATA,Deserialized Data" group.long 0x100++0x3B line.long 0x0 "SSR1,DSPI DSI Serialization Source Select Register 1" hexmask.long 0x0 0.--31. 1. "SS,Source Select" line.long 0x4 "PISR4,DSPI DSI Parallel Input Select Register 4" hexmask.long.byte 0x4 28.--31. 1. "IPS39,Input Pin Select 39" hexmask.long.byte 0x4 24.--27. 1. "IPS38,Input Pin Select 38" newline hexmask.long.byte 0x4 20.--23. 1. "IPS37,Input Pin Select 37" hexmask.long.byte 0x4 16.--19. 1. "IPS36,Input Pin Select 36" newline hexmask.long.byte 0x4 12.--15. 1. "IPS35,Input Pin Select 35" hexmask.long.byte 0x4 8.--11. 1. "IPS34,Input Pin Select 34" newline hexmask.long.byte 0x4 4.--7. 1. "IPS33,Input Pin Select 33" hexmask.long.byte 0x4 0.--3. 1. "IPS32,Input Pin Select 32" line.long 0x8 "PISR5,DSPI DSI Parallel Input Select Register 5" hexmask.long.byte 0x8 28.--31. 1. "IPS47,Input Pin Select 47" hexmask.long.byte 0x8 24.--27. 1. "IPS46,Input Pin Select 46" newline hexmask.long.byte 0x8 20.--23. 1. "IPS45,Input Pin Select 45" hexmask.long.byte 0x8 16.--19. 1. "IPS44,Input Pin Select 44" newline hexmask.long.byte 0x8 12.--15. 1. "IPS43,Input Pin Select 43" hexmask.long.byte 0x8 8.--11. 1. "IPS42,Input Pin Select 42" newline hexmask.long.byte 0x8 4.--7. 1. "IPS41,Input Pin Select 41" hexmask.long.byte 0x8 0.--3. 1. "IPS40,Input Pin Select 40" line.long 0xC "PISR6,DSPI DSI Parallel Input Select Register 6" hexmask.long.byte 0xC 28.--31. 1. "IPS55,Input Pin Select 55" hexmask.long.byte 0xC 24.--27. 1. "IPS54,Input Pin Select 54" newline hexmask.long.byte 0xC 20.--23. 1. "IPS53,Input Pin Select 53" hexmask.long.byte 0xC 16.--19. 1. "IPS52,Input Pin Select 52" newline hexmask.long.byte 0xC 12.--15. 1. "IPS51,Input Pin Select 51" hexmask.long.byte 0xC 8.--11. 1. "IPS50,Input Pin Select 50" newline hexmask.long.byte 0xC 4.--7. 1. "IPS49,Input Pin Select 49" hexmask.long.byte 0xC 0.--3. 1. "IPS48,Input Pin Select 48" line.long 0x10 "PISR7,DSPI DSI Parallel Input Select Register 7" hexmask.long.byte 0x10 28.--31. 1. "IPS63,Input Pin Select 63" hexmask.long.byte 0x10 24.--27. 1. "IPS62,Input Pin Select 62" newline hexmask.long.byte 0x10 20.--23. 1. "IPS61,Input Pin Select 61" hexmask.long.byte 0x10 16.--19. 1. "IPS60,Input Pin Select 60" newline hexmask.long.byte 0x10 12.--15. 1. "IPS59,Input Pin Select 59" hexmask.long.byte 0x10 8.--11. 1. "IPS58,Input Pin Select 58" newline hexmask.long.byte 0x10 4.--7. 1. "IPS57,Input Pin Select 57" hexmask.long.byte 0x10 0.--3. 1. "IPS56,Input Pin Select 56" line.long 0x14 "DIMR1,DSPI DSI Deserialized Data Interrupt Mask Register 1" hexmask.long 0x14 0.--31. 1. "MASK,Mask" line.long 0x18 "DPIR1,DSPI DSI Deserialized Data Polarity Interrupt Register 1" hexmask.long 0x18 0.--31. 1. "DP,Data Polarity" line.long 0x1C "CTARE0,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x1C 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x1C 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x20 "CTARE1,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x20 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x20 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x24 "CTARE2,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x24 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x24 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x28 "CTARE3,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x28 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x28 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x2C "CTARE4,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x2C 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x2C 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x30 "CTARE5,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x30 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x30 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x34 "CTARE6,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x34 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x34 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x38 "CTARE7,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x38 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x38 0.--10. 1. "DTCP,Data Transfer Count Preload" rgroup.long 0x13C++0x3 line.long 0x0 "SREX,DSPI Status Register Extended" hexmask.long.byte 0x0 4.--7. 1. "CMDCTR,CMD FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "CMDNXTPTR,Command Next Pointer" tree.end tree "DSPI_8" base ad:0x71AA8000 group.long 0x0++0x3 line.long 0x0 "MCR,DSPI Module Configuration Register" bitfld.long 0x0 31. "MSTR,Master/Slave Mode Select" "0: DSPI is in slave mode.,1: DSPI is in master mode." bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK Enable" "0: Continuous SCK disabled.,1: Continuous SCK enabled." newline bitfld.long 0x0 28.--29. "DCONF,DSPI Configuration" "0: SPI,1: DSI,2: CSI,?" bitfld.long 0x0 27. "FRZ,Freeze" "0: Do not halt serial transfers in debug mode.,1: Halt serial transfers in debug mode." newline bitfld.long 0x0 26. "MTFE,Modified Timing Format Enable" "0: Modified SPI transfer format disabled.,1: Modified SPI transfer format enabled." bitfld.long 0x0 25. "PCSSE,Peripheral Chip Select Strobe Enable" "0: PCS[5]/PCSS is used as the Peripheral Chip..,1: PCS[5]/PCSS is used as an active-low PCS Strobe.." newline bitfld.long 0x0 24. "ROOE,Receive FIFO Overflow Overwrite Enable" "0: Incoming data is ignored.,1: Incoming data is shifted into the shift register." bitfld.long 0x0 23. "PCSIS7,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 22. "PCSIS6,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 21. "PCSIS5,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 20. "PCSIS4,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 19. "PCSIS3,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 18. "PCSIS2,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 17. "PCSIS1,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 16. "PCSIS0,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 14. "MDIS,Module Disable" "0: Enable DSPI clocks.,1: Allow external logic to disable DSPI clocks." newline bitfld.long 0x0 13. "DIS_TXF,Disable Transmit FIFO" "0: Tx FIFO is enabled.,1: Tx FIFO is disabled." bitfld.long 0x0 12. "DIS_RXF,Disable Receive FIFO" "0: Rx FIFO is enabled.,1: Rx FIFO is disabled." newline bitfld.long 0x0 11. "CLR_TXF,Clear TX FIFO" "0: Do not clear the Tx FIFO and CMD FIFO counters.,1: Clears the Tx FIFO and CMD FIFO counters." bitfld.long 0x0 10. "CLR_RXF,Clear RX FIFO" "0: Do not clear the Rx FIFO counter.,1: Clear the Rx FIFO counter." newline bitfld.long 0x0 8.--9. "SMPL_PT,Sample Point" "0: 0 protocol clocks between SCK edge and SIN sample,1: 1 protocol clock between SCK edge and SIN sample,2: 2 protocol clocks between SCK edge and SIN sample,?" bitfld.long 0x0 3. "XSPI,Extended SPI Mode" "0: Normal SPI Mode. Up to 16-bit Frames. Command..,1: Extended SPI Mode. Up to 32-bit SPI Frames." newline bitfld.long 0x0 2. "FCPCS,Fast Continuous PCS Mode." "0: Normal or Slow Continuous PCS mode. Masking of..,1: Fast Continuous PCS mode. Delays masked via.." bitfld.long 0x0 1. "PES,Parity Error Stop" "0: SPI frame transmission continues.,1: SPI frame transmission stops." newline bitfld.long 0x0 0. "HALT,Halt" "0: Start transfers.,1: Stop transfers." rgroup.long 0x4++0x3 line.long 0x0 "HCR,Hardware Configuration Register" bitfld.long 0x0 31. "DSI,DSI features are implemented for the module." "0: DSI features are not implemented DSI registers..,1: DSI features are implemented" bitfld.long 0x0 30. "PISR,PISR0-3 and parallel inputs frame positions selection logic (DSI Muxing Logic) are implemented for the module." "0: PISR0-3 registers are not implemented.,1: PISR0-3 registers are implemented." newline bitfld.long 0x0 29. "DSI64,DSI features in 64 bit mode are implemented for the module." "0: DSI features for 64 bit mode are not..,1: DSI features for 64 bit mode are implemented" bitfld.long 0x0 28. "PISR_EX,PISR4-7 and parallel inputs frame positions selection logic (DSI 64 bit Muxing Logic) are implemented for the module." "0: PISR4-7 registers are not implemented.,1: PISR4-7 registers are implemented." newline bitfld.long 0x0 27. "XSPI,Extended SPI Mode feature is implemented for the module." "0: Extended SPI Mode is not implemented.,1: Extended SPI Mode is implemented." bitfld.long 0x0 24.--26. "CTAR,Maximum implemented CTAR register number." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 20.--23. 1. "TXFR,Maximum implemented TXFR register number." hexmask.long.byte 0x0 16.--19. 1. "RXFR,Maximum implemented RXFR register number." newline hexmask.long.byte 0x0 12.--15. 1. "CMDFR,Maximum implemented command FIFO number." bitfld.long 0x0 11. "MSTR_MODE,Master Mode implementation is enabled" "0,1" newline bitfld.long 0x0 10. "SLV_MODE,Slave Mode implementation is enabled" "0,1" bitfld.long 0x0 9. "TSB_EN,TSB Mode implementation is enabled" "0,1" newline bitfld.long 0x0 8. "ITSB_EN,Interleaved TSB Mode implementation is enabled" "0,1" group.long 0x8++0x7 line.long 0x0 "TCR,DSPI Transfer Count Register" hexmask.long.word 0x0 16.--31. 1. "SPI_TCNT,SPI Transfer Counter" line.long 0x4 "CTAR0,DSPI Clock and Transfer Attributes Register 0 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" group.long 0xC++0x7 line.long 0x0 "CTAR0_SLAVE,When the DSPI is configured as:SPI master - the CTAS field in the command portion of the TX FIFO entry selects which CTAR is used.SPI bus slave - the CTAR0 register is used.DSI master - the DSICTAS field in the DSPI DSI Configuration Register.." hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." bitfld.long 0x0 22. "FMSZ5,MSB of Frame Size when DSI is used in 64-bit Mode" "0,1" line.long 0x4 "CTAR1,DSPI Clock and Transfer Attributes Register 1 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" group.long 0x10++0x27 line.long 0x0 "CTAR1_SLAVE,When the DSPI is configured as:SPI master - the CTAS field in the command portion of the TX FIFO entry selects which CTAR is used.SPI bus slave - the CTAR0 register is used.DSI master - the DSICTAS field in the DSPI DSI Configuration Register.." hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." bitfld.long 0x0 22. "FMSZ5,MSB of Frame Size when DSI is used in 64-bit Mode" "0,1" line.long 0x4 "CTAR2,DSPI Clock and Transfer Attributes Register 2 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x8 "CTAR3,DSPI Clock and Transfer Attributes Register 3 (In Master Mode)" bitfld.long 0x8 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x8 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x8 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x8 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x8 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x8 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x8 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x8 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x8 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x8 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x8 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x8 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x8 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0xC "CTAR4,DSPI Clock and Transfer Attributes Register 4 (In Master Mode)" bitfld.long 0xC 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0xC 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0xC 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0xC 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0xC 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0xC 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0xC 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0xC 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0xC 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0xC 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0xC 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0xC 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x10 "CTAR5,DSPI Clock and Transfer Attributes Register 5 (In Master Mode)" bitfld.long 0x10 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x10 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x10 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x10 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x10 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x10 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x10 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x10 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x10 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x10 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x10 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x10 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x10 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x14 "CTAR6,DSPI Clock and Transfer Attributes Register 6 (In Master Mode)" bitfld.long 0x14 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x14 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x14 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x14 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x14 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x14 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x14 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x14 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x14 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x14 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x14 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x14 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x18 "CTAR7,DSPI Clock and Transfer Attributes Register 7 (In Master Mode)" bitfld.long 0x18 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x18 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x18 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x18 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x18 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x18 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x18 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x18 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x18 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x18 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x18 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x18 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x18 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x1C "SR,DSPI Status Register" bitfld.long 0x1C 31. "TCF,Transfer Complete Flag." "0: Transfer not complete.,1: Transfer complete." bitfld.long 0x1C 30. "TXRXS,TX and RX Status." "0: Transmit and receive operations are disabled..,1: Transmit and receive operations are enabled.." newline bitfld.long 0x1C 29. "SPITCF,SPI Frame Transfer Complete Flag." "0: SPI frame transfer is not complete.,1: SPI frame transfer is complete." bitfld.long 0x1C 28. "EOQF,End of Queue Flag." "0: EOQ is not set in the executing command.,1: EOQ is set in the executing SPI command." newline bitfld.long 0x1C 27. "TFUF,Transmit FIFO Underflow Flag." "0: No Tx FIFO underflow.,1: Tx FIFO underflow has occurred." bitfld.long 0x1C 26. "DSITCF,DSI Frame Transfer Complete Flag." "0: DSI frame transfer is not complete.,1: DSI frame transfer is complete." newline bitfld.long 0x1C 25. "TFFF,Transmit FIFO Fill Flag." "0: Tx FIFO is full.,1: Tx FIFO is not full." bitfld.long 0x1C 24. "BSYF,Busy Flag." "0: No Cyclic Command Transfer in Progress.,1: Cyclic Command Transfer is in progress. Current.." newline bitfld.long 0x1C 23. "CMDTCF,Command Transfer Complete Flag." "0: Data Transfer by current Command not complete.,1: Data Transfer by current Command complete." bitfld.long 0x1C 22. "DPEF,DSI Parity Error Flag." "0: No parity error.,1: Parity error has occurred." newline bitfld.long 0x1C 21. "SPEF,SPI Parity Error Flag." "0: No parity error.,1: Parity error has occurred." bitfld.long 0x1C 20. "DDIF,DSI Data Received with Active Bits." "0: No DSI data with active bits was received.,1: DSI data with active bits was received." newline bitfld.long 0x1C 19. "RFOF,Receive FIFO Overflow Flag." "0: No Rx FIFO overflow.,1: Rx FIFO overflow has occurred." bitfld.long 0x1C 18. "TFIWF,Transmit FIFO Invalid Write Flag." "0: No Invalid Data present in TX FIFO,1: Invalid Data present in TX FIFO since CMD FIFO.." newline bitfld.long 0x1C 17. "RFDF,Receive FIFO Drain Flag." "0: Rx FIFO is empty.,1: Rx FIFO is not empty." bitfld.long 0x1C 16. "CMDFFF,Command FIFO Fill Flag." "0: CMD FIFO is full.,1: CMD FIFO is not full." newline hexmask.long.byte 0x1C 12.--15. 1. "TXCTR,TX FIFO Counter." hexmask.long.byte 0x1C 8.--11. 1. "TXNXTPTR,Transmit Next Pointer." newline hexmask.long.byte 0x1C 4.--7. 1. "RXCTR,RX FIFO Counter." hexmask.long.byte 0x1C 0.--3. 1. "POPNXTPTR,Pop Next Pointer." line.long 0x20 "RSER,DSPI DMA/Interrupt Request Select and Enable Register" bitfld.long 0x20 31. "TCF_RE,Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 30. "CMDFFF_RE,Command FIFO Fill Flag Request Enable." "0: Disabled.,1: Enabled." newline bitfld.long 0x20 29. "SPITCF_RE,SPI Frame Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 28. "EOQF_RE,DSPI Finished Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 27. "TFUF_RE,Transmit FIFO Underflow Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 26. "DSITCF_RE,DSI Frame Transmission Complete Request Enable." "0: Disabled.,1: Enabled." newline bitfld.long 0x20 25. "TFFF_RE,Transmit FIFO Fill Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 24. "TFFF_DIRS,Transmit FIFO Fill DMA or Interrupt Request Select" "0: Interrupt requests.,1: DMA requests." newline bitfld.long 0x20 23. "CMDTCF_RE,Command Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 22. "DPEF_RE,DSI Parity Error Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 21. "SPEF_RE,SPI Parity Error Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 20. "DDIF_RE,DSI data received with active bits Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 19. "RFOF_RE,Receive FIFO Overflow Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 18. "TFIWF_RE,Transmit FIFO Invalid Write Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 17. "RFDF_RE,Receive FIFO Drain Request Enable" "0: Disabled,1: Enabled" bitfld.long 0x20 16. "RFDF_DIRS,Receive FIFO Drain DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." newline bitfld.long 0x20 15. "CMDFFF_DIRS,Command FIFO FIll DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." bitfld.long 0x20 14. "DDIF_DIRS,DSI data received with active bits - DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." line.long 0x24 "PUSHR,DSPI PUSH FIFO Register In Master mode" bitfld.long 0x24 31. "CONT,Continuous Peripheral Chip Select Enable. (SPI master mode)" "0: Return PCSn signals to their inactive state..,1: Keep PCSn signals asserted between transfers." bitfld.long 0x24 28.--30. "CTAS,Clock and Transfer Attributes Select." "0: CTAR0/CTARE0,1: CTAR1/CTARE1,2: CTAR2/CTARE2,3: CTAR3/CTARE3,4: CTAR4/CTARE4,5: CTAR5/CTARE5,6: CTAR6/CTARE6,7: CTAR7/CTARE7" newline bitfld.long 0x24 27. "EOQ,End Of Queue" "0: The SPI data is not the last data to transfer.,1: The SPI data is the last data to transfer." bitfld.long 0x24 26. "CTCNT,Clear Transfer Counter." "0: Do not clear the TCR[SPI_TCNT] field.,1: Clear the TCR[SPI_TCNT] field." newline bitfld.long 0x24 25. "PE_MASC,Parity Enable or Mask tASC delay in the current frame" "0: PE: No parity bit included/checked. MASC: tASC..,1: PE: Parity bit is transmitted instead of the.." bitfld.long 0x24 24. "PP_MCSC,Parity Polarity or Mask tCSC delay in the next frame" "0: PP: Even Parity: the number of 1 bits in the..,1: PP: Odd Parity: the number of 1 bits in the.." newline hexmask.long.byte 0x24 16.--23. 1. "PCS,Select which PCS signals are to be asserted for the transfer." hexmask.long.word 0x24 0.--15. 1. "TXDATA,Transmit Data" group.long 0x34++0x3 line.long 0x0 "PUSHR_SLAVE,PUSHR provides the means to write to the TX FIFO.Data written to this register is transferred to:The TX FIFO for 8- or 16-bit writes to the Data field of PUSHR.In master mode. the register provides 16-bit command to the CMD FIFO and 16-bit.." hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x38++0x13 line.long 0x0 "POPR,DSPI POP FIFO Register" hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data" line.long 0x4 "TXFR0,DSPI Transmit FIFO Registers" hexmask.long.word 0x4 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x4 0.--15. 1. "TXDATA,Transmit Data" line.long 0x8 "TXFR1,DSPI Transmit FIFO Registers" hexmask.long.word 0x8 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x8 0.--15. 1. "TXDATA,Transmit Data" line.long 0xC "TXFR2,DSPI Transmit FIFO Registers" hexmask.long.word 0xC 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0xC 0.--15. 1. "TXDATA,Transmit Data" line.long 0x10 "TXFR3,DSPI Transmit FIFO Registers" hexmask.long.word 0x10 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x10 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x7C++0xF line.long 0x0 "RXFR0,DSPI Receive FIFO Registers" hexmask.long 0x0 0.--31. 1. "RXDATA,Receive Data" line.long 0x4 "RXFR1,DSPI Receive FIFO Registers" hexmask.long 0x4 0.--31. 1. "RXDATA,Receive Data" line.long 0x8 "RXFR2,DSPI Receive FIFO Registers" hexmask.long 0x8 0.--31. 1. "RXDATA,Receive Data" line.long 0xC "RXFR3,DSPI Receive FIFO Registers" hexmask.long 0xC 0.--31. 1. "RXDATA,Receive Data" group.long 0xBC++0x3 line.long 0x0 "DSICR0,DSPI DSI Configuration Register 0" bitfld.long 0x0 30. "FMSZ4,MSB of the frame size in master mode when DSI is used in 32-bit mode." "0,1" bitfld.long 0x0 23. "FMSZ5,MSB of the frame size in master mode when DSI is used in 64-bit mode." "0,1" newline bitfld.long 0x0 21. "ITSB,Interleaved TSB mode." "0: Disabled.,1: Enabled." bitfld.long 0x0 20. "TSBC,Timed Serial Bus Configuration." "0: Disabled.,1: Enabled." newline bitfld.long 0x0 19. "TXSS,Transmit Data Source Select." "0: SDR source.,1: ASDR source." bitfld.long 0x0 18. "TPOL,Trigger Polarity" "0: Falling edge initiates a transfer.,1: Rising edge initiates a transfer." newline bitfld.long 0x0 16. "CID,Change In Data Transfer Enable" "0: Disabled.,1: Enabled." bitfld.long 0x0 15. "DCONT,DSI Continuous Peripheral Chip Select Enable (DSI Master mode only)" "0: PCS signals return to inactive.,1: PCS signals remain asserted." newline bitfld.long 0x0 12.--14. "DSICTAS,DSI Clock and Transfer Attributes Select (DSI Master mode only)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "DMS,Data Match Stop" "0: Disabled.,1: Enabled." newline bitfld.long 0x0 10. "PES,Parity Error Stop" "0: Disabled.,1: Enabled." bitfld.long 0x0 9. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of the last.." newline bitfld.long 0x0 8. "PP,Parity Polarity" "0: Even Parity: the number of '1' bits in the..,1: Odd Parity: the number of 1 bits in the.." hexmask.long.byte 0x0 0.--7. 1. "DPCSX,DSI Peripheral Chip Select 07" rgroup.long 0xC0++0x3 line.long 0x0 "SDR0,DSPI DSI Serialization Data Register 0" hexmask.long 0x0 0.--31. 1. "SER_DATA,Serialized Data" group.long 0xC4++0x3 line.long 0x0 "ASDR0,DSPI DSI Alternate Serialization Data Register 0" hexmask.long 0x0 0.--31. 1. "ASER_DATA,Alternate Serialized Data" rgroup.long 0xC8++0x7 line.long 0x0 "COMPR0,DSPI DSI Transmit Comparison Register 0" hexmask.long 0x0 0.--31. 1. "COMP_DATA,Compare Data" line.long 0x4 "DDR0,DSPI DSI Deserialization Data Register 0" hexmask.long 0x4 0.--31. 1. "DESER_DATA,Deserialized Data" group.long 0xD0++0x1F line.long 0x0 "DSICR1,DSPI DSI Configuration Register 1" hexmask.long.byte 0x0 24.--29. 1. "TSBCNT,Timed Serial Bus Operation Count" bitfld.long 0x0 18. "DSI64E,DSI 64-bit Mode Enable" "0: Disabled. DSI Mode operates in the default..,1: Enabled. DSI Mode operates in 64-bit configuration" newline bitfld.long 0x0 17. "DSE1,Data Select Enable 1" "0: No Zero bit is inserted in the middle of the..,1: Zero bit is inserted at the middle of the data.." bitfld.long 0x0 16. "DSE0,Data Select Enable 0" "0: No Zero bit is inserted in the beginning of the..,1: Zero bit is inserted at the beginning of the.." newline hexmask.long.byte 0x0 8.--15. 1. "TRGPRD,Internal Trigger Period for the ITSB mode." hexmask.long.byte 0x0 0.--7. 1. "DPCS1_X,DSI Peripheral Chip Select 07" line.long 0x4 "SSR0,DSPI DSI Serialization Source Select Register 0" hexmask.long 0x4 0.--31. 1. "SS,Source Select" line.long 0x8 "PISR0,DSPI DSI Parallel Input Select Register 0" hexmask.long.byte 0x8 28.--31. 1. "IPS7,Input Pin Select 7" hexmask.long.byte 0x8 24.--27. 1. "IPS6,Input Pin Select 6" newline hexmask.long.byte 0x8 20.--23. 1. "IPS5,Input Pin Select 5" hexmask.long.byte 0x8 16.--19. 1. "IPS4,Input Pin Select 5" newline hexmask.long.byte 0x8 12.--15. 1. "IPS3,Input Pin Select 3" hexmask.long.byte 0x8 8.--11. 1. "IPS2,Input Pin Select 2" newline hexmask.long.byte 0x8 4.--7. 1. "IPS1,Input Pin Select 1" hexmask.long.byte 0x8 0.--3. 1. "IPS0,Input Pin Select 0" line.long 0xC "PISR1,DSPI DSI Parallel Input Select Register 1" hexmask.long.byte 0xC 28.--31. 1. "IPS15,Input Pin Select 15" hexmask.long.byte 0xC 24.--27. 1. "IPS14,Input Pin Select 14" newline hexmask.long.byte 0xC 20.--23. 1. "IPS13,Input Pin Select 13" hexmask.long.byte 0xC 16.--19. 1. "IPS12,Input Pin Select 12" newline hexmask.long.byte 0xC 12.--15. 1. "IPS11,Input Pin Select 11" hexmask.long.byte 0xC 8.--11. 1. "IPS10,Input Pin Select 10" newline hexmask.long.byte 0xC 4.--7. 1. "IPS9,Input Pin Select 9" hexmask.long.byte 0xC 0.--3. 1. "IPS8,Input Pin Select 8" line.long 0x10 "PISR2,DSPI DSI Parallel Input Select Register 2" hexmask.long.byte 0x10 28.--31. 1. "IPS23,Input Pin Select 23" hexmask.long.byte 0x10 24.--27. 1. "IPS22,Input Pin Select 22" newline hexmask.long.byte 0x10 20.--23. 1. "IPS21,Input Pin Select 21" hexmask.long.byte 0x10 16.--19. 1. "IPS20,Input Pin Select 20" newline hexmask.long.byte 0x10 12.--15. 1. "IPS19,Input Pin Select 19" hexmask.long.byte 0x10 8.--11. 1. "IPS18,Input Pin Select 18" newline hexmask.long.byte 0x10 4.--7. 1. "IPS17,Input Pin Select 17" hexmask.long.byte 0x10 0.--3. 1. "IPS16,Input Pin Select 16" line.long 0x14 "PISR3,DSPI DSI Parallel Input Select Register 3" hexmask.long.byte 0x14 28.--31. 1. "IPS31,Input Pin Select 31" hexmask.long.byte 0x14 24.--27. 1. "IPS30,Input Pin Select 30" newline hexmask.long.byte 0x14 20.--23. 1. "IPS29,Input Pin Select 29" hexmask.long.byte 0x14 16.--19. 1. "IPS28,Input Pin Select 28" newline hexmask.long.byte 0x14 12.--15. 1. "IPS27,Input Pin Select 27" hexmask.long.byte 0x14 8.--11. 1. "IPS26,Input Pin Select 26" newline hexmask.long.byte 0x14 4.--7. 1. "IPS25,Input Pin Select 25" hexmask.long.byte 0x14 0.--3. 1. "IPS24,Input Pin Select 24" line.long 0x18 "DIMR0,DSPI DSI Deserialized Data Interrupt Mask Register 0" hexmask.long 0x18 0.--31. 1. "MASK,Mask" line.long 0x1C "DPIR0,DSPI DSI Deserialized Data Polarity Interrupt Register 0" hexmask.long 0x1C 0.--31. 1. "DP,Data Polarity" rgroup.long 0xF0++0x3 line.long 0x0 "SDR1,DSPI DSI Serialization Data Register 1" hexmask.long 0x0 0.--31. 1. "SER_DATA,Serialized Data" group.long 0xF4++0x3 line.long 0x0 "ASDR1,DSPI DSI Alternate Serialization Data Register 1" hexmask.long 0x0 0.--31. 1. "ASER_DATA,Alternate Serialized Data" rgroup.long 0xF8++0x7 line.long 0x0 "COMPR1,DSPI DSI Transmit Comparison Register 1" hexmask.long 0x0 0.--31. 1. "COMP_DATA,Compare Data" line.long 0x4 "DDR1,DSPI DSI Deserialization Data Register 1" hexmask.long 0x4 0.--31. 1. "DESER_DATA,Deserialized Data" group.long 0x100++0x3B line.long 0x0 "SSR1,DSPI DSI Serialization Source Select Register 1" hexmask.long 0x0 0.--31. 1. "SS,Source Select" line.long 0x4 "PISR4,DSPI DSI Parallel Input Select Register 4" hexmask.long.byte 0x4 28.--31. 1. "IPS39,Input Pin Select 39" hexmask.long.byte 0x4 24.--27. 1. "IPS38,Input Pin Select 38" newline hexmask.long.byte 0x4 20.--23. 1. "IPS37,Input Pin Select 37" hexmask.long.byte 0x4 16.--19. 1. "IPS36,Input Pin Select 36" newline hexmask.long.byte 0x4 12.--15. 1. "IPS35,Input Pin Select 35" hexmask.long.byte 0x4 8.--11. 1. "IPS34,Input Pin Select 34" newline hexmask.long.byte 0x4 4.--7. 1. "IPS33,Input Pin Select 33" hexmask.long.byte 0x4 0.--3. 1. "IPS32,Input Pin Select 32" line.long 0x8 "PISR5,DSPI DSI Parallel Input Select Register 5" hexmask.long.byte 0x8 28.--31. 1. "IPS47,Input Pin Select 47" hexmask.long.byte 0x8 24.--27. 1. "IPS46,Input Pin Select 46" newline hexmask.long.byte 0x8 20.--23. 1. "IPS45,Input Pin Select 45" hexmask.long.byte 0x8 16.--19. 1. "IPS44,Input Pin Select 44" newline hexmask.long.byte 0x8 12.--15. 1. "IPS43,Input Pin Select 43" hexmask.long.byte 0x8 8.--11. 1. "IPS42,Input Pin Select 42" newline hexmask.long.byte 0x8 4.--7. 1. "IPS41,Input Pin Select 41" hexmask.long.byte 0x8 0.--3. 1. "IPS40,Input Pin Select 40" line.long 0xC "PISR6,DSPI DSI Parallel Input Select Register 6" hexmask.long.byte 0xC 28.--31. 1. "IPS55,Input Pin Select 55" hexmask.long.byte 0xC 24.--27. 1. "IPS54,Input Pin Select 54" newline hexmask.long.byte 0xC 20.--23. 1. "IPS53,Input Pin Select 53" hexmask.long.byte 0xC 16.--19. 1. "IPS52,Input Pin Select 52" newline hexmask.long.byte 0xC 12.--15. 1. "IPS51,Input Pin Select 51" hexmask.long.byte 0xC 8.--11. 1. "IPS50,Input Pin Select 50" newline hexmask.long.byte 0xC 4.--7. 1. "IPS49,Input Pin Select 49" hexmask.long.byte 0xC 0.--3. 1. "IPS48,Input Pin Select 48" line.long 0x10 "PISR7,DSPI DSI Parallel Input Select Register 7" hexmask.long.byte 0x10 28.--31. 1. "IPS63,Input Pin Select 63" hexmask.long.byte 0x10 24.--27. 1. "IPS62,Input Pin Select 62" newline hexmask.long.byte 0x10 20.--23. 1. "IPS61,Input Pin Select 61" hexmask.long.byte 0x10 16.--19. 1. "IPS60,Input Pin Select 60" newline hexmask.long.byte 0x10 12.--15. 1. "IPS59,Input Pin Select 59" hexmask.long.byte 0x10 8.--11. 1. "IPS58,Input Pin Select 58" newline hexmask.long.byte 0x10 4.--7. 1. "IPS57,Input Pin Select 57" hexmask.long.byte 0x10 0.--3. 1. "IPS56,Input Pin Select 56" line.long 0x14 "DIMR1,DSPI DSI Deserialized Data Interrupt Mask Register 1" hexmask.long 0x14 0.--31. 1. "MASK,Mask" line.long 0x18 "DPIR1,DSPI DSI Deserialized Data Polarity Interrupt Register 1" hexmask.long 0x18 0.--31. 1. "DP,Data Polarity" line.long 0x1C "CTARE0,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x1C 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x1C 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x20 "CTARE1,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x20 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x20 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x24 "CTARE2,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x24 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x24 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x28 "CTARE3,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x28 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x28 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x2C "CTARE4,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x2C 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x2C 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x30 "CTARE5,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x30 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x30 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x34 "CTARE6,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x34 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x34 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x38 "CTARE7,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x38 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x38 0.--10. 1. "DTCP,Data Transfer Count Preload" rgroup.long 0x13C++0x3 line.long 0x0 "SREX,DSPI Status Register Extended" hexmask.long.byte 0x0 4.--7. 1. "CMDCTR,CMD FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "CMDNXTPTR,Command Next Pointer" tree.end tree "DSPI_9" base ad:0x71AAC000 group.long 0x0++0x3 line.long 0x0 "MCR,DSPI Module Configuration Register" bitfld.long 0x0 31. "MSTR,Master/Slave Mode Select" "0: DSPI is in slave mode.,1: DSPI is in master mode." bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK Enable" "0: Continuous SCK disabled.,1: Continuous SCK enabled." newline bitfld.long 0x0 28.--29. "DCONF,DSPI Configuration" "0: SPI,1: DSI,2: CSI,?" bitfld.long 0x0 27. "FRZ,Freeze" "0: Do not halt serial transfers in debug mode.,1: Halt serial transfers in debug mode." newline bitfld.long 0x0 26. "MTFE,Modified Timing Format Enable" "0: Modified SPI transfer format disabled.,1: Modified SPI transfer format enabled." bitfld.long 0x0 25. "PCSSE,Peripheral Chip Select Strobe Enable" "0: PCS[5]/PCSS is used as the Peripheral Chip..,1: PCS[5]/PCSS is used as an active-low PCS Strobe.." newline bitfld.long 0x0 24. "ROOE,Receive FIFO Overflow Overwrite Enable" "0: Incoming data is ignored.,1: Incoming data is shifted into the shift register." bitfld.long 0x0 23. "PCSIS7,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 22. "PCSIS6,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 21. "PCSIS5,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 20. "PCSIS4,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 19. "PCSIS3,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 18. "PCSIS2,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 17. "PCSIS1,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." newline bitfld.long 0x0 16. "PCSIS0,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low.,1: The inactive state of PCSx is high." bitfld.long 0x0 14. "MDIS,Module Disable" "0: Enable DSPI clocks.,1: Allow external logic to disable DSPI clocks." newline bitfld.long 0x0 13. "DIS_TXF,Disable Transmit FIFO" "0: Tx FIFO is enabled.,1: Tx FIFO is disabled." bitfld.long 0x0 12. "DIS_RXF,Disable Receive FIFO" "0: Rx FIFO is enabled.,1: Rx FIFO is disabled." newline bitfld.long 0x0 11. "CLR_TXF,Clear TX FIFO" "0: Do not clear the Tx FIFO and CMD FIFO counters.,1: Clears the Tx FIFO and CMD FIFO counters." bitfld.long 0x0 10. "CLR_RXF,Clear RX FIFO" "0: Do not clear the Rx FIFO counter.,1: Clear the Rx FIFO counter." newline bitfld.long 0x0 8.--9. "SMPL_PT,Sample Point" "0: 0 protocol clocks between SCK edge and SIN sample,1: 1 protocol clock between SCK edge and SIN sample,2: 2 protocol clocks between SCK edge and SIN sample,?" bitfld.long 0x0 3. "XSPI,Extended SPI Mode" "0: Normal SPI Mode. Up to 16-bit Frames. Command..,1: Extended SPI Mode. Up to 32-bit SPI Frames." newline bitfld.long 0x0 2. "FCPCS,Fast Continuous PCS Mode." "0: Normal or Slow Continuous PCS mode. Masking of..,1: Fast Continuous PCS mode. Delays masked via.." bitfld.long 0x0 1. "PES,Parity Error Stop" "0: SPI frame transmission continues.,1: SPI frame transmission stops." newline bitfld.long 0x0 0. "HALT,Halt" "0: Start transfers.,1: Stop transfers." rgroup.long 0x4++0x3 line.long 0x0 "HCR,Hardware Configuration Register" bitfld.long 0x0 31. "DSI,DSI features are implemented for the module." "0: DSI features are not implemented DSI registers..,1: DSI features are implemented" bitfld.long 0x0 30. "PISR,PISR0-3 and parallel inputs frame positions selection logic (DSI Muxing Logic) are implemented for the module." "0: PISR0-3 registers are not implemented.,1: PISR0-3 registers are implemented." newline bitfld.long 0x0 29. "DSI64,DSI features in 64 bit mode are implemented for the module." "0: DSI features for 64 bit mode are not..,1: DSI features for 64 bit mode are implemented" bitfld.long 0x0 28. "PISR_EX,PISR4-7 and parallel inputs frame positions selection logic (DSI 64 bit Muxing Logic) are implemented for the module." "0: PISR4-7 registers are not implemented.,1: PISR4-7 registers are implemented." newline bitfld.long 0x0 27. "XSPI,Extended SPI Mode feature is implemented for the module." "0: Extended SPI Mode is not implemented.,1: Extended SPI Mode is implemented." bitfld.long 0x0 24.--26. "CTAR,Maximum implemented CTAR register number." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 20.--23. 1. "TXFR,Maximum implemented TXFR register number." hexmask.long.byte 0x0 16.--19. 1. "RXFR,Maximum implemented RXFR register number." newline hexmask.long.byte 0x0 12.--15. 1. "CMDFR,Maximum implemented command FIFO number." bitfld.long 0x0 11. "MSTR_MODE,Master Mode implementation is enabled" "0,1" newline bitfld.long 0x0 10. "SLV_MODE,Slave Mode implementation is enabled" "0,1" bitfld.long 0x0 9. "TSB_EN,TSB Mode implementation is enabled" "0,1" newline bitfld.long 0x0 8. "ITSB_EN,Interleaved TSB Mode implementation is enabled" "0,1" group.long 0x8++0x7 line.long 0x0 "TCR,DSPI Transfer Count Register" hexmask.long.word 0x0 16.--31. 1. "SPI_TCNT,SPI Transfer Counter" line.long 0x4 "CTAR0,DSPI Clock and Transfer Attributes Register 0 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" group.long 0xC++0x7 line.long 0x0 "CTAR0_SLAVE,When the DSPI is configured as:SPI master - the CTAS field in the command portion of the TX FIFO entry selects which CTAR is used.SPI bus slave - the CTAR0 register is used.DSI master - the DSICTAS field in the DSPI DSI Configuration Register.." hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." bitfld.long 0x0 22. "FMSZ5,MSB of Frame Size when DSI is used in 64-bit Mode" "0,1" line.long 0x4 "CTAR1,DSPI Clock and Transfer Attributes Register 1 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" group.long 0x10++0x27 line.long 0x0 "CTAR1_SLAVE,When the DSPI is configured as:SPI master - the CTAS field in the command portion of the TX FIFO entry selects which CTAR is used.SPI bus slave - the CTAR0 register is used.DSI master - the DSICTAS field in the DSPI DSI Configuration Register.." hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." bitfld.long 0x0 22. "FMSZ5,MSB of Frame Size when DSI is used in 64-bit Mode" "0,1" line.long 0x4 "CTAR2,DSPI Clock and Transfer Attributes Register 2 (In Master Mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x8 "CTAR3,DSPI Clock and Transfer Attributes Register 3 (In Master Mode)" bitfld.long 0x8 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x8 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x8 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x8 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x8 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x8 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x8 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x8 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x8 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x8 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x8 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x8 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x8 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0xC "CTAR4,DSPI Clock and Transfer Attributes Register 4 (In Master Mode)" bitfld.long 0xC 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0xC 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0xC 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0xC 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0xC 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0xC 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0xC 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0xC 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0xC 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0xC 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0xC 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0xC 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x10 "CTAR5,DSPI Clock and Transfer Attributes Register 5 (In Master Mode)" bitfld.long 0x10 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x10 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x10 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x10 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x10 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x10 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x10 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x10 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x10 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x10 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x10 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x10 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x10 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x14 "CTAR6,DSPI Clock and Transfer Attributes Register 6 (In Master Mode)" bitfld.long 0x14 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x14 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x14 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x14 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x14 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x14 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x14 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x14 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x14 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x14 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x14 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x14 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x18 "CTAR7,DSPI Clock and Transfer Attributes Register 7 (In Master Mode)" bitfld.long 0x18 31. "DBR,Double Baud Rate. (Master mode only)" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x18 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x18 26. "CPOL,Clock Polarity. (Master and Slave mode)" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x18 25. "CPHA,Clock Phase or TSB mode. (Master and Slave mode)" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x18 24. "LSBFE,LSB First." "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x18 22.--23. "PCSSCK,PCS to SCK Delay Prescaler." "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK delay,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x18 20.--21. "PASC,After SCK Delay Prescaler." "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: After SCK delay" bitfld.long 0x18 18.--19. "PDT,Delay after Transfer Prescaler. (Master mode only)" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x18 16.--17. "PBR,Baud Rate Prescaler. (Master mode only)" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x18 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler. (Master mode only)" newline hexmask.long.byte 0x18 8.--11. 1. "ASC,After SCK Delay Scaler. (Master mode only)" hexmask.long.byte 0x18 4.--7. 1. "DT,Delay After Transfer Scaler (Master mode only)" newline hexmask.long.byte 0x18 0.--3. 1. "BR,Baud Rate Scaler. (Master mode only)" line.long 0x1C "SR,DSPI Status Register" bitfld.long 0x1C 31. "TCF,Transfer Complete Flag." "0: Transfer not complete.,1: Transfer complete." bitfld.long 0x1C 30. "TXRXS,TX and RX Status." "0: Transmit and receive operations are disabled..,1: Transmit and receive operations are enabled.." newline bitfld.long 0x1C 29. "SPITCF,SPI Frame Transfer Complete Flag." "0: SPI frame transfer is not complete.,1: SPI frame transfer is complete." bitfld.long 0x1C 28. "EOQF,End of Queue Flag." "0: EOQ is not set in the executing command.,1: EOQ is set in the executing SPI command." newline bitfld.long 0x1C 27. "TFUF,Transmit FIFO Underflow Flag." "0: No Tx FIFO underflow.,1: Tx FIFO underflow has occurred." bitfld.long 0x1C 26. "DSITCF,DSI Frame Transfer Complete Flag." "0: DSI frame transfer is not complete.,1: DSI frame transfer is complete." newline bitfld.long 0x1C 25. "TFFF,Transmit FIFO Fill Flag." "0: Tx FIFO is full.,1: Tx FIFO is not full." bitfld.long 0x1C 24. "BSYF,Busy Flag." "0: No Cyclic Command Transfer in Progress.,1: Cyclic Command Transfer is in progress. Current.." newline bitfld.long 0x1C 23. "CMDTCF,Command Transfer Complete Flag." "0: Data Transfer by current Command not complete.,1: Data Transfer by current Command complete." bitfld.long 0x1C 22. "DPEF,DSI Parity Error Flag." "0: No parity error.,1: Parity error has occurred." newline bitfld.long 0x1C 21. "SPEF,SPI Parity Error Flag." "0: No parity error.,1: Parity error has occurred." bitfld.long 0x1C 20. "DDIF,DSI Data Received with Active Bits." "0: No DSI data with active bits was received.,1: DSI data with active bits was received." newline bitfld.long 0x1C 19. "RFOF,Receive FIFO Overflow Flag." "0: No Rx FIFO overflow.,1: Rx FIFO overflow has occurred." bitfld.long 0x1C 18. "TFIWF,Transmit FIFO Invalid Write Flag." "0: No Invalid Data present in TX FIFO,1: Invalid Data present in TX FIFO since CMD FIFO.." newline bitfld.long 0x1C 17. "RFDF,Receive FIFO Drain Flag." "0: Rx FIFO is empty.,1: Rx FIFO is not empty." bitfld.long 0x1C 16. "CMDFFF,Command FIFO Fill Flag." "0: CMD FIFO is full.,1: CMD FIFO is not full." newline hexmask.long.byte 0x1C 12.--15. 1. "TXCTR,TX FIFO Counter." hexmask.long.byte 0x1C 8.--11. 1. "TXNXTPTR,Transmit Next Pointer." newline hexmask.long.byte 0x1C 4.--7. 1. "RXCTR,RX FIFO Counter." hexmask.long.byte 0x1C 0.--3. 1. "POPNXTPTR,Pop Next Pointer." line.long 0x20 "RSER,DSPI DMA/Interrupt Request Select and Enable Register" bitfld.long 0x20 31. "TCF_RE,Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 30. "CMDFFF_RE,Command FIFO Fill Flag Request Enable." "0: Disabled.,1: Enabled." newline bitfld.long 0x20 29. "SPITCF_RE,SPI Frame Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 28. "EOQF_RE,DSPI Finished Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 27. "TFUF_RE,Transmit FIFO Underflow Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 26. "DSITCF_RE,DSI Frame Transmission Complete Request Enable." "0: Disabled.,1: Enabled." newline bitfld.long 0x20 25. "TFFF_RE,Transmit FIFO Fill Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 24. "TFFF_DIRS,Transmit FIFO Fill DMA or Interrupt Request Select" "0: Interrupt requests.,1: DMA requests." newline bitfld.long 0x20 23. "CMDTCF_RE,Command Transmission Complete Request Enable." "0: Disabled.,1: Enabled." bitfld.long 0x20 22. "DPEF_RE,DSI Parity Error Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 21. "SPEF_RE,SPI Parity Error Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 20. "DDIF_RE,DSI data received with active bits Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 19. "RFOF_RE,Receive FIFO Overflow Request Enable" "0: Disabled.,1: Enabled." bitfld.long 0x20 18. "TFIWF_RE,Transmit FIFO Invalid Write Request Enable" "0: Disabled.,1: Enabled." newline bitfld.long 0x20 17. "RFDF_RE,Receive FIFO Drain Request Enable" "0: Disabled,1: Enabled" bitfld.long 0x20 16. "RFDF_DIRS,Receive FIFO Drain DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." newline bitfld.long 0x20 15. "CMDFFF_DIRS,Command FIFO FIll DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." bitfld.long 0x20 14. "DDIF_DIRS,DSI data received with active bits - DMA or Interrupt Request Select." "0: Interrupt request.,1: DMA request." line.long 0x24 "PUSHR,DSPI PUSH FIFO Register In Master mode" bitfld.long 0x24 31. "CONT,Continuous Peripheral Chip Select Enable. (SPI master mode)" "0: Return PCSn signals to their inactive state..,1: Keep PCSn signals asserted between transfers." bitfld.long 0x24 28.--30. "CTAS,Clock and Transfer Attributes Select." "0: CTAR0/CTARE0,1: CTAR1/CTARE1,2: CTAR2/CTARE2,3: CTAR3/CTARE3,4: CTAR4/CTARE4,5: CTAR5/CTARE5,6: CTAR6/CTARE6,7: CTAR7/CTARE7" newline bitfld.long 0x24 27. "EOQ,End Of Queue" "0: The SPI data is not the last data to transfer.,1: The SPI data is the last data to transfer." bitfld.long 0x24 26. "CTCNT,Clear Transfer Counter." "0: Do not clear the TCR[SPI_TCNT] field.,1: Clear the TCR[SPI_TCNT] field." newline bitfld.long 0x24 25. "PE_MASC,Parity Enable or Mask tASC delay in the current frame" "0: PE: No parity bit included/checked. MASC: tASC..,1: PE: Parity bit is transmitted instead of the.." bitfld.long 0x24 24. "PP_MCSC,Parity Polarity or Mask tCSC delay in the next frame" "0: PP: Even Parity: the number of 1 bits in the..,1: PP: Odd Parity: the number of 1 bits in the.." newline hexmask.long.byte 0x24 16.--23. 1. "PCS,Select which PCS signals are to be asserted for the transfer." hexmask.long.word 0x24 0.--15. 1. "TXDATA,Transmit Data" group.long 0x34++0x3 line.long 0x0 "PUSHR_SLAVE,PUSHR provides the means to write to the TX FIFO.Data written to this register is transferred to:The TX FIFO for 8- or 16-bit writes to the Data field of PUSHR.In master mode. the register provides 16-bit command to the CMD FIFO and 16-bit.." hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x38++0x13 line.long 0x0 "POPR,DSPI POP FIFO Register" hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data" line.long 0x4 "TXFR0,DSPI Transmit FIFO Registers" hexmask.long.word 0x4 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x4 0.--15. 1. "TXDATA,Transmit Data" line.long 0x8 "TXFR1,DSPI Transmit FIFO Registers" hexmask.long.word 0x8 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x8 0.--15. 1. "TXDATA,Transmit Data" line.long 0xC "TXFR2,DSPI Transmit FIFO Registers" hexmask.long.word 0xC 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0xC 0.--15. 1. "TXDATA,Transmit Data" line.long 0x10 "TXFR3,DSPI Transmit FIFO Registers" hexmask.long.word 0x10 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x10 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x7C++0xF line.long 0x0 "RXFR0,DSPI Receive FIFO Registers" hexmask.long 0x0 0.--31. 1. "RXDATA,Receive Data" line.long 0x4 "RXFR1,DSPI Receive FIFO Registers" hexmask.long 0x4 0.--31. 1. "RXDATA,Receive Data" line.long 0x8 "RXFR2,DSPI Receive FIFO Registers" hexmask.long 0x8 0.--31. 1. "RXDATA,Receive Data" line.long 0xC "RXFR3,DSPI Receive FIFO Registers" hexmask.long 0xC 0.--31. 1. "RXDATA,Receive Data" group.long 0xBC++0x3 line.long 0x0 "DSICR0,DSPI DSI Configuration Register 0" bitfld.long 0x0 30. "FMSZ4,MSB of the frame size in master mode when DSI is used in 32-bit mode." "0,1" bitfld.long 0x0 23. "FMSZ5,MSB of the frame size in master mode when DSI is used in 64-bit mode." "0,1" newline bitfld.long 0x0 21. "ITSB,Interleaved TSB mode." "0: Disabled.,1: Enabled." bitfld.long 0x0 20. "TSBC,Timed Serial Bus Configuration." "0: Disabled.,1: Enabled." newline bitfld.long 0x0 19. "TXSS,Transmit Data Source Select." "0: SDR source.,1: ASDR source." bitfld.long 0x0 18. "TPOL,Trigger Polarity" "0: Falling edge initiates a transfer.,1: Rising edge initiates a transfer." newline bitfld.long 0x0 16. "CID,Change In Data Transfer Enable" "0: Disabled.,1: Enabled." bitfld.long 0x0 15. "DCONT,DSI Continuous Peripheral Chip Select Enable (DSI Master mode only)" "0: PCS signals return to inactive.,1: PCS signals remain asserted." newline bitfld.long 0x0 12.--14. "DSICTAS,DSI Clock and Transfer Attributes Select (DSI Master mode only)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "DMS,Data Match Stop" "0: Disabled.,1: Enabled." newline bitfld.long 0x0 10. "PES,Parity Error Stop" "0: Disabled.,1: Enabled." bitfld.long 0x0 9. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of the last.." newline bitfld.long 0x0 8. "PP,Parity Polarity" "0: Even Parity: the number of '1' bits in the..,1: Odd Parity: the number of 1 bits in the.." hexmask.long.byte 0x0 0.--7. 1. "DPCSX,DSI Peripheral Chip Select 07" rgroup.long 0xC0++0x3 line.long 0x0 "SDR0,DSPI DSI Serialization Data Register 0" hexmask.long 0x0 0.--31. 1. "SER_DATA,Serialized Data" group.long 0xC4++0x3 line.long 0x0 "ASDR0,DSPI DSI Alternate Serialization Data Register 0" hexmask.long 0x0 0.--31. 1. "ASER_DATA,Alternate Serialized Data" rgroup.long 0xC8++0x7 line.long 0x0 "COMPR0,DSPI DSI Transmit Comparison Register 0" hexmask.long 0x0 0.--31. 1. "COMP_DATA,Compare Data" line.long 0x4 "DDR0,DSPI DSI Deserialization Data Register 0" hexmask.long 0x4 0.--31. 1. "DESER_DATA,Deserialized Data" group.long 0xD0++0x1F line.long 0x0 "DSICR1,DSPI DSI Configuration Register 1" hexmask.long.byte 0x0 24.--29. 1. "TSBCNT,Timed Serial Bus Operation Count" bitfld.long 0x0 18. "DSI64E,DSI 64-bit Mode Enable" "0: Disabled. DSI Mode operates in the default..,1: Enabled. DSI Mode operates in 64-bit configuration" newline bitfld.long 0x0 17. "DSE1,Data Select Enable 1" "0: No Zero bit is inserted in the middle of the..,1: Zero bit is inserted at the middle of the data.." bitfld.long 0x0 16. "DSE0,Data Select Enable 0" "0: No Zero bit is inserted in the beginning of the..,1: Zero bit is inserted at the beginning of the.." newline hexmask.long.byte 0x0 8.--15. 1. "TRGPRD,Internal Trigger Period for the ITSB mode." hexmask.long.byte 0x0 0.--7. 1. "DPCS1_X,DSI Peripheral Chip Select 07" line.long 0x4 "SSR0,DSPI DSI Serialization Source Select Register 0" hexmask.long 0x4 0.--31. 1. "SS,Source Select" line.long 0x8 "PISR0,DSPI DSI Parallel Input Select Register 0" hexmask.long.byte 0x8 28.--31. 1. "IPS7,Input Pin Select 7" hexmask.long.byte 0x8 24.--27. 1. "IPS6,Input Pin Select 6" newline hexmask.long.byte 0x8 20.--23. 1. "IPS5,Input Pin Select 5" hexmask.long.byte 0x8 16.--19. 1. "IPS4,Input Pin Select 5" newline hexmask.long.byte 0x8 12.--15. 1. "IPS3,Input Pin Select 3" hexmask.long.byte 0x8 8.--11. 1. "IPS2,Input Pin Select 2" newline hexmask.long.byte 0x8 4.--7. 1. "IPS1,Input Pin Select 1" hexmask.long.byte 0x8 0.--3. 1. "IPS0,Input Pin Select 0" line.long 0xC "PISR1,DSPI DSI Parallel Input Select Register 1" hexmask.long.byte 0xC 28.--31. 1. "IPS15,Input Pin Select 15" hexmask.long.byte 0xC 24.--27. 1. "IPS14,Input Pin Select 14" newline hexmask.long.byte 0xC 20.--23. 1. "IPS13,Input Pin Select 13" hexmask.long.byte 0xC 16.--19. 1. "IPS12,Input Pin Select 12" newline hexmask.long.byte 0xC 12.--15. 1. "IPS11,Input Pin Select 11" hexmask.long.byte 0xC 8.--11. 1. "IPS10,Input Pin Select 10" newline hexmask.long.byte 0xC 4.--7. 1. "IPS9,Input Pin Select 9" hexmask.long.byte 0xC 0.--3. 1. "IPS8,Input Pin Select 8" line.long 0x10 "PISR2,DSPI DSI Parallel Input Select Register 2" hexmask.long.byte 0x10 28.--31. 1. "IPS23,Input Pin Select 23" hexmask.long.byte 0x10 24.--27. 1. "IPS22,Input Pin Select 22" newline hexmask.long.byte 0x10 20.--23. 1. "IPS21,Input Pin Select 21" hexmask.long.byte 0x10 16.--19. 1. "IPS20,Input Pin Select 20" newline hexmask.long.byte 0x10 12.--15. 1. "IPS19,Input Pin Select 19" hexmask.long.byte 0x10 8.--11. 1. "IPS18,Input Pin Select 18" newline hexmask.long.byte 0x10 4.--7. 1. "IPS17,Input Pin Select 17" hexmask.long.byte 0x10 0.--3. 1. "IPS16,Input Pin Select 16" line.long 0x14 "PISR3,DSPI DSI Parallel Input Select Register 3" hexmask.long.byte 0x14 28.--31. 1. "IPS31,Input Pin Select 31" hexmask.long.byte 0x14 24.--27. 1. "IPS30,Input Pin Select 30" newline hexmask.long.byte 0x14 20.--23. 1. "IPS29,Input Pin Select 29" hexmask.long.byte 0x14 16.--19. 1. "IPS28,Input Pin Select 28" newline hexmask.long.byte 0x14 12.--15. 1. "IPS27,Input Pin Select 27" hexmask.long.byte 0x14 8.--11. 1. "IPS26,Input Pin Select 26" newline hexmask.long.byte 0x14 4.--7. 1. "IPS25,Input Pin Select 25" hexmask.long.byte 0x14 0.--3. 1. "IPS24,Input Pin Select 24" line.long 0x18 "DIMR0,DSPI DSI Deserialized Data Interrupt Mask Register 0" hexmask.long 0x18 0.--31. 1. "MASK,Mask" line.long 0x1C "DPIR0,DSPI DSI Deserialized Data Polarity Interrupt Register 0" hexmask.long 0x1C 0.--31. 1. "DP,Data Polarity" rgroup.long 0xF0++0x3 line.long 0x0 "SDR1,DSPI DSI Serialization Data Register 1" hexmask.long 0x0 0.--31. 1. "SER_DATA,Serialized Data" group.long 0xF4++0x3 line.long 0x0 "ASDR1,DSPI DSI Alternate Serialization Data Register 1" hexmask.long 0x0 0.--31. 1. "ASER_DATA,Alternate Serialized Data" rgroup.long 0xF8++0x7 line.long 0x0 "COMPR1,DSPI DSI Transmit Comparison Register 1" hexmask.long 0x0 0.--31. 1. "COMP_DATA,Compare Data" line.long 0x4 "DDR1,DSPI DSI Deserialization Data Register 1" hexmask.long 0x4 0.--31. 1. "DESER_DATA,Deserialized Data" group.long 0x100++0x3B line.long 0x0 "SSR1,DSPI DSI Serialization Source Select Register 1" hexmask.long 0x0 0.--31. 1. "SS,Source Select" line.long 0x4 "PISR4,DSPI DSI Parallel Input Select Register 4" hexmask.long.byte 0x4 28.--31. 1. "IPS39,Input Pin Select 39" hexmask.long.byte 0x4 24.--27. 1. "IPS38,Input Pin Select 38" newline hexmask.long.byte 0x4 20.--23. 1. "IPS37,Input Pin Select 37" hexmask.long.byte 0x4 16.--19. 1. "IPS36,Input Pin Select 36" newline hexmask.long.byte 0x4 12.--15. 1. "IPS35,Input Pin Select 35" hexmask.long.byte 0x4 8.--11. 1. "IPS34,Input Pin Select 34" newline hexmask.long.byte 0x4 4.--7. 1. "IPS33,Input Pin Select 33" hexmask.long.byte 0x4 0.--3. 1. "IPS32,Input Pin Select 32" line.long 0x8 "PISR5,DSPI DSI Parallel Input Select Register 5" hexmask.long.byte 0x8 28.--31. 1. "IPS47,Input Pin Select 47" hexmask.long.byte 0x8 24.--27. 1. "IPS46,Input Pin Select 46" newline hexmask.long.byte 0x8 20.--23. 1. "IPS45,Input Pin Select 45" hexmask.long.byte 0x8 16.--19. 1. "IPS44,Input Pin Select 44" newline hexmask.long.byte 0x8 12.--15. 1. "IPS43,Input Pin Select 43" hexmask.long.byte 0x8 8.--11. 1. "IPS42,Input Pin Select 42" newline hexmask.long.byte 0x8 4.--7. 1. "IPS41,Input Pin Select 41" hexmask.long.byte 0x8 0.--3. 1. "IPS40,Input Pin Select 40" line.long 0xC "PISR6,DSPI DSI Parallel Input Select Register 6" hexmask.long.byte 0xC 28.--31. 1. "IPS55,Input Pin Select 55" hexmask.long.byte 0xC 24.--27. 1. "IPS54,Input Pin Select 54" newline hexmask.long.byte 0xC 20.--23. 1. "IPS53,Input Pin Select 53" hexmask.long.byte 0xC 16.--19. 1. "IPS52,Input Pin Select 52" newline hexmask.long.byte 0xC 12.--15. 1. "IPS51,Input Pin Select 51" hexmask.long.byte 0xC 8.--11. 1. "IPS50,Input Pin Select 50" newline hexmask.long.byte 0xC 4.--7. 1. "IPS49,Input Pin Select 49" hexmask.long.byte 0xC 0.--3. 1. "IPS48,Input Pin Select 48" line.long 0x10 "PISR7,DSPI DSI Parallel Input Select Register 7" hexmask.long.byte 0x10 28.--31. 1. "IPS63,Input Pin Select 63" hexmask.long.byte 0x10 24.--27. 1. "IPS62,Input Pin Select 62" newline hexmask.long.byte 0x10 20.--23. 1. "IPS61,Input Pin Select 61" hexmask.long.byte 0x10 16.--19. 1. "IPS60,Input Pin Select 60" newline hexmask.long.byte 0x10 12.--15. 1. "IPS59,Input Pin Select 59" hexmask.long.byte 0x10 8.--11. 1. "IPS58,Input Pin Select 58" newline hexmask.long.byte 0x10 4.--7. 1. "IPS57,Input Pin Select 57" hexmask.long.byte 0x10 0.--3. 1. "IPS56,Input Pin Select 56" line.long 0x14 "DIMR1,DSPI DSI Deserialized Data Interrupt Mask Register 1" hexmask.long 0x14 0.--31. 1. "MASK,Mask" line.long 0x18 "DPIR1,DSPI DSI Deserialized Data Polarity Interrupt Register 1" hexmask.long 0x18 0.--31. 1. "DP,Data Polarity" line.long 0x1C "CTARE0,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x1C 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x1C 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x20 "CTARE1,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x20 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x20 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x24 "CTARE2,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x24 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x24 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x28 "CTARE3,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x28 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x28 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x2C "CTARE4,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x2C 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x2C 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x30 "CTARE5,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x30 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x30 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x34 "CTARE6,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x34 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x34 0.--10. 1. "DTCP,Data Transfer Count Preload" line.long 0x38 "CTARE7,DSPI Clock and Transfer Attributes Register Extended" bitfld.long 0x38 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16-bit SPI frames can be..,1: Up to 32-bit SPI frames can be transferred. Each.." hexmask.long.word 0x38 0.--10. 1. "DTCP,Data Transfer Count Preload" rgroup.long 0x13C++0x3 line.long 0x0 "SREX,DSPI Status Register Extended" hexmask.long.byte 0x0 4.--7. 1. "CMDCTR,CMD FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "CMDNXTPTR,Command Next Pointer" tree.end tree.end tree "DSPL (DSP Low Subsystem)" base ad:0x0 tree "DSPL_0" base ad:0x70404000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 6. "DIIEN,Data Input Interface Enable" "0: Data Input Interface,1: Data Input Interface" bitfld.long 0x0 4. "DMAGATE,DMA Gating Bit" "0: DMA gating feature disabled,1: DMA gating feature enabled" newline bitfld.long 0x0 3. "DMAEN,DMA Enable:" "0: no DMA request,1: new value in DATAOUT register generates a DMA.." bitfld.long 0x0 1. "INIT_PM,Initialize TCPM" "0: TCPM init enabled: write access to TCPM is enabled,1: TCPM init complete" rgroup.long 0x4++0x3 line.long 0x0 "SMBREAD,Status and Mailbox Read Register" bitfld.long 0x0 15. "USR5,User flag 5" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 14. "USR4,User flag 4" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 13. "USR3,User flag 3" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 12. "USR2,User flag 2" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 11. "USR1,User flag 1" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 10. "USR0,User flag 0" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 7. "NCERRF,Non Correctable Error Flag" "0: No error is detected,1: A non correctable error has been detected" bitfld.long 0x0 6. "RUNST,RUN Status of DSP Core" "0: DSP core is in HALT mode,1: DSP core is in RUN mode" newline bitfld.long 0x0 5. "TOS1,Timer Output Status 1" "0: Timer output status 1 is low,1: Timer output status 1 is high" bitfld.long 0x0 4. "TOS0,Timer Output Status 0" "0: Timer output status 0 is low,1: Timer output status 0 is high" newline bitfld.long 0x0 3. "NDOOVF,New Data Out OVerFlow flag" "0: No overflow has occurred,1: Indicates an overwrite of DATAOUT register" bitfld.long 0x0 2. "NDO,New Data Output flag" "0: No new data in the output buffer,1: New data in the output buffer available" newline bitfld.long 0x0 1. "NDIOVF,New Data In Overflow" "0: No overflow has occurred,1: Indicates an overwrite of DATAIN register" bitfld.long 0x0 0. "NDI,New Data Input" "0: No new data in the data input buffer,1: New data in the data input buffer available" group.long 0x8++0xB line.long 0x0 "SMBSET,Status and Mailbox Set Register" bitfld.long 0x0 15. "USR5SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 14. "USR4SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 13. "USR3SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 12. "USR2SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 11. "USR1SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 10. "USR0SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 7. "NCERRFSET,Set request for SMBREAD register bit:" "0: any read access to this bit will return 0,?" bitfld.long 0x0 6. "WKUPSET,Set request for status reflection on SMBREAD register RUNST bit" "0: any read access tit his bit will return 0,?" line.long 0x4 "SMBCLR,Status and Mailbox Clear Register" bitfld.long 0x4 15. "USR5CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 14. "USR4CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 13. "USR3CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 12. "USR2CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 11. "USR1CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 10. "USR0CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 3. "NDOOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 1. "NDIOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" line.long 0x8 "ADCCAL,ADC Calibration Data for Gain and Offset Compensation" hexmask.long.word 0x8 16.--31. 1. "ADC_GAIN,These bits contain the ADC GAIN calibration values." hexmask.long.word 0x8 0.--15. 1. "ADC_OFFSET,These bits contain the ADC OFFSET calibration values 1." group.long 0x18++0x3 line.long 0x0 "DATAIN,Data Input buffer" hexmask.long.word 0x0 0.--15. 1. "DATAIN_1,ADC Data input" group.long 0x20++0x3 line.long 0x0 "DATAOUT,Data Output buffer" hexmask.long.word 0x0 16.--31. 1. "DATAOUTH,ADC Data output high word" hexmask.long.word 0x0 0.--15. 1. "DATAOUTL,ADC Data output low word" tree.end tree "DSPL_1" base ad:0x70A04000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 6. "DIIEN,Data Input Interface Enable" "0: Data Input Interface,1: Data Input Interface" bitfld.long 0x0 4. "DMAGATE,DMA Gating Bit" "0: DMA gating feature disabled,1: DMA gating feature enabled" newline bitfld.long 0x0 3. "DMAEN,DMA Enable:" "0: no DMA request,1: new value in DATAOUT register generates a DMA.." bitfld.long 0x0 1. "INIT_PM,Initialize TCPM" "0: TCPM init enabled: write access to TCPM is enabled,1: TCPM init complete" rgroup.long 0x4++0x3 line.long 0x0 "SMBREAD,Status and Mailbox Read Register" bitfld.long 0x0 15. "USR5,User flag 5" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 14. "USR4,User flag 4" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 13. "USR3,User flag 3" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 12. "USR2,User flag 2" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 11. "USR1,User flag 1" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 10. "USR0,User flag 0" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 7. "NCERRF,Non Correctable Error Flag" "0: No error is detected,1: A non correctable error has been detected" bitfld.long 0x0 6. "RUNST,RUN Status of DSP Core" "0: DSP core is in HALT mode,1: DSP core is in RUN mode" newline bitfld.long 0x0 5. "TOS1,Timer Output Status 1" "0: Timer output status 1 is low,1: Timer output status 1 is high" bitfld.long 0x0 4. "TOS0,Timer Output Status 0" "0: Timer output status 0 is low,1: Timer output status 0 is high" newline bitfld.long 0x0 3. "NDOOVF,New Data Out OVerFlow flag" "0: No overflow has occurred,1: Indicates an overwrite of DATAOUT register" bitfld.long 0x0 2. "NDO,New Data Output flag" "0: No new data in the output buffer,1: New data in the output buffer available" newline bitfld.long 0x0 1. "NDIOVF,New Data In Overflow" "0: No overflow has occurred,1: Indicates an overwrite of DATAIN register" bitfld.long 0x0 0. "NDI,New Data Input" "0: No new data in the data input buffer,1: New data in the data input buffer available" group.long 0x8++0xB line.long 0x0 "SMBSET,Status and Mailbox Set Register" bitfld.long 0x0 15. "USR5SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 14. "USR4SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 13. "USR3SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 12. "USR2SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 11. "USR1SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 10. "USR0SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 7. "NCERRFSET,Set request for SMBREAD register bit:" "0: any read access to this bit will return 0,?" bitfld.long 0x0 6. "WKUPSET,Set request for status reflection on SMBREAD register RUNST bit" "0: any read access tit his bit will return 0,?" line.long 0x4 "SMBCLR,Status and Mailbox Clear Register" bitfld.long 0x4 15. "USR5CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 14. "USR4CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 13. "USR3CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 12. "USR2CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 11. "USR1CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 10. "USR0CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 3. "NDOOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 1. "NDIOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" line.long 0x8 "ADCCAL,ADC Calibration Data for Gain and Offset Compensation" hexmask.long.word 0x8 16.--31. 1. "ADC_GAIN,These bits contain the ADC GAIN calibration values." hexmask.long.word 0x8 0.--15. 1. "ADC_OFFSET,These bits contain the ADC OFFSET calibration values 1." group.long 0x18++0x3 line.long 0x0 "DATAIN,Data Input buffer" hexmask.long.word 0x0 0.--15. 1. "DATAIN_1,ADC Data input" group.long 0x20++0x3 line.long 0x0 "DATAOUT,Data Output buffer" hexmask.long.word 0x0 16.--31. 1. "DATAOUTH,ADC Data output high word" hexmask.long.word 0x0 0.--15. 1. "DATAOUTL,ADC Data output low word" tree.end tree "DSPL_2" base ad:0x70408000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 6. "DIIEN,Data Input Interface Enable" "0: Data Input Interface,1: Data Input Interface" bitfld.long 0x0 4. "DMAGATE,DMA Gating Bit" "0: DMA gating feature disabled,1: DMA gating feature enabled" newline bitfld.long 0x0 3. "DMAEN,DMA Enable:" "0: no DMA request,1: new value in DATAOUT register generates a DMA.." bitfld.long 0x0 1. "INIT_PM,Initialize TCPM" "0: TCPM init enabled: write access to TCPM is enabled,1: TCPM init complete" rgroup.long 0x4++0x3 line.long 0x0 "SMBREAD,Status and Mailbox Read Register" bitfld.long 0x0 15. "USR5,User flag 5" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 14. "USR4,User flag 4" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 13. "USR3,User flag 3" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 12. "USR2,User flag 2" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 11. "USR1,User flag 1" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 10. "USR0,User flag 0" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 7. "NCERRF,Non Correctable Error Flag" "0: No error is detected,1: A non correctable error has been detected" bitfld.long 0x0 6. "RUNST,RUN Status of DSP Core" "0: DSP core is in HALT mode,1: DSP core is in RUN mode" newline bitfld.long 0x0 5. "TOS1,Timer Output Status 1" "0: Timer output status 1 is low,1: Timer output status 1 is high" bitfld.long 0x0 4. "TOS0,Timer Output Status 0" "0: Timer output status 0 is low,1: Timer output status 0 is high" newline bitfld.long 0x0 3. "NDOOVF,New Data Out OVerFlow flag" "0: No overflow has occurred,1: Indicates an overwrite of DATAOUT register" bitfld.long 0x0 2. "NDO,New Data Output flag" "0: No new data in the output buffer,1: New data in the output buffer available" newline bitfld.long 0x0 1. "NDIOVF,New Data In Overflow" "0: No overflow has occurred,1: Indicates an overwrite of DATAIN register" bitfld.long 0x0 0. "NDI,New Data Input" "0: No new data in the data input buffer,1: New data in the data input buffer available" group.long 0x8++0xB line.long 0x0 "SMBSET,Status and Mailbox Set Register" bitfld.long 0x0 15. "USR5SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 14. "USR4SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 13. "USR3SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 12. "USR2SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 11. "USR1SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 10. "USR0SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 7. "NCERRFSET,Set request for SMBREAD register bit:" "0: any read access to this bit will return 0,?" bitfld.long 0x0 6. "WKUPSET,Set request for status reflection on SMBREAD register RUNST bit" "0: any read access tit his bit will return 0,?" line.long 0x4 "SMBCLR,Status and Mailbox Clear Register" bitfld.long 0x4 15. "USR5CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 14. "USR4CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 13. "USR3CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 12. "USR2CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 11. "USR1CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 10. "USR0CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 3. "NDOOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 1. "NDIOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" line.long 0x8 "ADCCAL,ADC Calibration Data for Gain and Offset Compensation" hexmask.long.word 0x8 16.--31. 1. "ADC_GAIN,These bits contain the ADC GAIN calibration values." hexmask.long.word 0x8 0.--15. 1. "ADC_OFFSET,These bits contain the ADC OFFSET calibration values 1." group.long 0x18++0x3 line.long 0x0 "DATAIN,Data Input buffer" hexmask.long.word 0x0 0.--15. 1. "DATAIN_1,ADC Data input" group.long 0x20++0x3 line.long 0x0 "DATAOUT,Data Output buffer" hexmask.long.word 0x0 16.--31. 1. "DATAOUTH,ADC Data output high word" hexmask.long.word 0x0 0.--15. 1. "DATAOUTL,ADC Data output low word" tree.end tree "DSPL_3" base ad:0x70A08000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 6. "DIIEN,Data Input Interface Enable" "0: Data Input Interface,1: Data Input Interface" bitfld.long 0x0 4. "DMAGATE,DMA Gating Bit" "0: DMA gating feature disabled,1: DMA gating feature enabled" newline bitfld.long 0x0 3. "DMAEN,DMA Enable:" "0: no DMA request,1: new value in DATAOUT register generates a DMA.." bitfld.long 0x0 1. "INIT_PM,Initialize TCPM" "0: TCPM init enabled: write access to TCPM is enabled,1: TCPM init complete" rgroup.long 0x4++0x3 line.long 0x0 "SMBREAD,Status and Mailbox Read Register" bitfld.long 0x0 15. "USR5,User flag 5" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 14. "USR4,User flag 4" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 13. "USR3,User flag 3" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 12. "USR2,User flag 2" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 11. "USR1,User flag 1" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 10. "USR0,User flag 0" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 7. "NCERRF,Non Correctable Error Flag" "0: No error is detected,1: A non correctable error has been detected" bitfld.long 0x0 6. "RUNST,RUN Status of DSP Core" "0: DSP core is in HALT mode,1: DSP core is in RUN mode" newline bitfld.long 0x0 5. "TOS1,Timer Output Status 1" "0: Timer output status 1 is low,1: Timer output status 1 is high" bitfld.long 0x0 4. "TOS0,Timer Output Status 0" "0: Timer output status 0 is low,1: Timer output status 0 is high" newline bitfld.long 0x0 3. "NDOOVF,New Data Out OVerFlow flag" "0: No overflow has occurred,1: Indicates an overwrite of DATAOUT register" bitfld.long 0x0 2. "NDO,New Data Output flag" "0: No new data in the output buffer,1: New data in the output buffer available" newline bitfld.long 0x0 1. "NDIOVF,New Data In Overflow" "0: No overflow has occurred,1: Indicates an overwrite of DATAIN register" bitfld.long 0x0 0. "NDI,New Data Input" "0: No new data in the data input buffer,1: New data in the data input buffer available" group.long 0x8++0xB line.long 0x0 "SMBSET,Status and Mailbox Set Register" bitfld.long 0x0 15. "USR5SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 14. "USR4SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 13. "USR3SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 12. "USR2SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 11. "USR1SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 10. "USR0SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 7. "NCERRFSET,Set request for SMBREAD register bit:" "0: any read access to this bit will return 0,?" bitfld.long 0x0 6. "WKUPSET,Set request for status reflection on SMBREAD register RUNST bit" "0: any read access tit his bit will return 0,?" line.long 0x4 "SMBCLR,Status and Mailbox Clear Register" bitfld.long 0x4 15. "USR5CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 14. "USR4CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 13. "USR3CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 12. "USR2CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 11. "USR1CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 10. "USR0CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 3. "NDOOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 1. "NDIOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" line.long 0x8 "ADCCAL,ADC Calibration Data for Gain and Offset Compensation" hexmask.long.word 0x8 16.--31. 1. "ADC_GAIN,These bits contain the ADC GAIN calibration values." hexmask.long.word 0x8 0.--15. 1. "ADC_OFFSET,These bits contain the ADC OFFSET calibration values 1." group.long 0x18++0x3 line.long 0x0 "DATAIN,Data Input buffer" hexmask.long.word 0x0 0.--15. 1. "DATAIN_1,ADC Data input" group.long 0x20++0x3 line.long 0x0 "DATAOUT,Data Output buffer" hexmask.long.word 0x0 16.--31. 1. "DATAOUTH,ADC Data output high word" hexmask.long.word 0x0 0.--15. 1. "DATAOUTL,ADC Data output low word" tree.end tree "DSPL_4" base ad:0x7040C000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 6. "DIIEN,Data Input Interface Enable" "0: Data Input Interface,1: Data Input Interface" bitfld.long 0x0 4. "DMAGATE,DMA Gating Bit" "0: DMA gating feature disabled,1: DMA gating feature enabled" newline bitfld.long 0x0 3. "DMAEN,DMA Enable:" "0: no DMA request,1: new value in DATAOUT register generates a DMA.." bitfld.long 0x0 1. "INIT_PM,Initialize TCPM" "0: TCPM init enabled: write access to TCPM is enabled,1: TCPM init complete" rgroup.long 0x4++0x3 line.long 0x0 "SMBREAD,Status and Mailbox Read Register" bitfld.long 0x0 15. "USR5,User flag 5" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 14. "USR4,User flag 4" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 13. "USR3,User flag 3" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 12. "USR2,User flag 2" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 11. "USR1,User flag 1" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 10. "USR0,User flag 0" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 7. "NCERRF,Non Correctable Error Flag" "0: No error is detected,1: A non correctable error has been detected" bitfld.long 0x0 6. "RUNST,RUN Status of DSP Core" "0: DSP core is in HALT mode,1: DSP core is in RUN mode" newline bitfld.long 0x0 5. "TOS1,Timer Output Status 1" "0: Timer output status 1 is low,1: Timer output status 1 is high" bitfld.long 0x0 4. "TOS0,Timer Output Status 0" "0: Timer output status 0 is low,1: Timer output status 0 is high" newline bitfld.long 0x0 3. "NDOOVF,New Data Out OVerFlow flag" "0: No overflow has occurred,1: Indicates an overwrite of DATAOUT register" bitfld.long 0x0 2. "NDO,New Data Output flag" "0: No new data in the output buffer,1: New data in the output buffer available" newline bitfld.long 0x0 1. "NDIOVF,New Data In Overflow" "0: No overflow has occurred,1: Indicates an overwrite of DATAIN register" bitfld.long 0x0 0. "NDI,New Data Input" "0: No new data in the data input buffer,1: New data in the data input buffer available" group.long 0x8++0xB line.long 0x0 "SMBSET,Status and Mailbox Set Register" bitfld.long 0x0 15. "USR5SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 14. "USR4SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 13. "USR3SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 12. "USR2SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 11. "USR1SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 10. "USR0SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 7. "NCERRFSET,Set request for SMBREAD register bit:" "0: any read access to this bit will return 0,?" bitfld.long 0x0 6. "WKUPSET,Set request for status reflection on SMBREAD register RUNST bit" "0: any read access tit his bit will return 0,?" line.long 0x4 "SMBCLR,Status and Mailbox Clear Register" bitfld.long 0x4 15. "USR5CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 14. "USR4CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 13. "USR3CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 12. "USR2CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 11. "USR1CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 10. "USR0CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 3. "NDOOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 1. "NDIOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" line.long 0x8 "ADCCAL,ADC Calibration Data for Gain and Offset Compensation" hexmask.long.word 0x8 16.--31. 1. "ADC_GAIN,These bits contain the ADC GAIN calibration values." hexmask.long.word 0x8 0.--15. 1. "ADC_OFFSET,These bits contain the ADC OFFSET calibration values 1." group.long 0x18++0x3 line.long 0x0 "DATAIN,Data Input buffer" hexmask.long.word 0x0 0.--15. 1. "DATAIN_1,ADC Data input" group.long 0x20++0x3 line.long 0x0 "DATAOUT,Data Output buffer" hexmask.long.word 0x0 16.--31. 1. "DATAOUTH,ADC Data output high word" hexmask.long.word 0x0 0.--15. 1. "DATAOUTL,ADC Data output low word" tree.end tree "DSPL_5" base ad:0x70A0C000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 6. "DIIEN,Data Input Interface Enable" "0: Data Input Interface,1: Data Input Interface" bitfld.long 0x0 4. "DMAGATE,DMA Gating Bit" "0: DMA gating feature disabled,1: DMA gating feature enabled" newline bitfld.long 0x0 3. "DMAEN,DMA Enable:" "0: no DMA request,1: new value in DATAOUT register generates a DMA.." bitfld.long 0x0 1. "INIT_PM,Initialize TCPM" "0: TCPM init enabled: write access to TCPM is enabled,1: TCPM init complete" rgroup.long 0x4++0x3 line.long 0x0 "SMBREAD,Status and Mailbox Read Register" bitfld.long 0x0 15. "USR5,User flag 5" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 14. "USR4,User flag 4" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 13. "USR3,User flag 3" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 12. "USR2,User flag 2" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 11. "USR1,User flag 1" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 10. "USR0,User flag 0" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 7. "NCERRF,Non Correctable Error Flag" "0: No error is detected,1: A non correctable error has been detected" bitfld.long 0x0 6. "RUNST,RUN Status of DSP Core" "0: DSP core is in HALT mode,1: DSP core is in RUN mode" newline bitfld.long 0x0 5. "TOS1,Timer Output Status 1" "0: Timer output status 1 is low,1: Timer output status 1 is high" bitfld.long 0x0 4. "TOS0,Timer Output Status 0" "0: Timer output status 0 is low,1: Timer output status 0 is high" newline bitfld.long 0x0 3. "NDOOVF,New Data Out OVerFlow flag" "0: No overflow has occurred,1: Indicates an overwrite of DATAOUT register" bitfld.long 0x0 2. "NDO,New Data Output flag" "0: No new data in the output buffer,1: New data in the output buffer available" newline bitfld.long 0x0 1. "NDIOVF,New Data In Overflow" "0: No overflow has occurred,1: Indicates an overwrite of DATAIN register" bitfld.long 0x0 0. "NDI,New Data Input" "0: No new data in the data input buffer,1: New data in the data input buffer available" group.long 0x8++0xB line.long 0x0 "SMBSET,Status and Mailbox Set Register" bitfld.long 0x0 15. "USR5SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 14. "USR4SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 13. "USR3SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 12. "USR2SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 11. "USR1SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 10. "USR0SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 7. "NCERRFSET,Set request for SMBREAD register bit:" "0: any read access to this bit will return 0,?" bitfld.long 0x0 6. "WKUPSET,Set request for status reflection on SMBREAD register RUNST bit" "0: any read access tit his bit will return 0,?" line.long 0x4 "SMBCLR,Status and Mailbox Clear Register" bitfld.long 0x4 15. "USR5CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 14. "USR4CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 13. "USR3CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 12. "USR2CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 11. "USR1CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 10. "USR0CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 3. "NDOOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 1. "NDIOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" line.long 0x8 "ADCCAL,ADC Calibration Data for Gain and Offset Compensation" hexmask.long.word 0x8 16.--31. 1. "ADC_GAIN,These bits contain the ADC GAIN calibration values." hexmask.long.word 0x8 0.--15. 1. "ADC_OFFSET,These bits contain the ADC OFFSET calibration values 1." group.long 0x18++0x3 line.long 0x0 "DATAIN,Data Input buffer" hexmask.long.word 0x0 0.--15. 1. "DATAIN_1,ADC Data input" group.long 0x20++0x3 line.long 0x0 "DATAOUT,Data Output buffer" hexmask.long.word 0x0 16.--31. 1. "DATAOUTH,ADC Data output high word" hexmask.long.word 0x0 0.--15. 1. "DATAOUTL,ADC Data output low word" tree.end tree "DSPL_6" base ad:0x70410000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 6. "DIIEN,Data Input Interface Enable" "0: Data Input Interface,1: Data Input Interface" bitfld.long 0x0 4. "DMAGATE,DMA Gating Bit" "0: DMA gating feature disabled,1: DMA gating feature enabled" newline bitfld.long 0x0 3. "DMAEN,DMA Enable:" "0: no DMA request,1: new value in DATAOUT register generates a DMA.." bitfld.long 0x0 1. "INIT_PM,Initialize TCPM" "0: TCPM init enabled: write access to TCPM is enabled,1: TCPM init complete" rgroup.long 0x4++0x3 line.long 0x0 "SMBREAD,Status and Mailbox Read Register" bitfld.long 0x0 15. "USR5,User flag 5" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 14. "USR4,User flag 4" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 13. "USR3,User flag 3" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 12. "USR2,User flag 2" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 11. "USR1,User flag 1" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 10. "USR0,User flag 0" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 7. "NCERRF,Non Correctable Error Flag" "0: No error is detected,1: A non correctable error has been detected" bitfld.long 0x0 6. "RUNST,RUN Status of DSP Core" "0: DSP core is in HALT mode,1: DSP core is in RUN mode" newline bitfld.long 0x0 5. "TOS1,Timer Output Status 1" "0: Timer output status 1 is low,1: Timer output status 1 is high" bitfld.long 0x0 4. "TOS0,Timer Output Status 0" "0: Timer output status 0 is low,1: Timer output status 0 is high" newline bitfld.long 0x0 3. "NDOOVF,New Data Out OVerFlow flag" "0: No overflow has occurred,1: Indicates an overwrite of DATAOUT register" bitfld.long 0x0 2. "NDO,New Data Output flag" "0: No new data in the output buffer,1: New data in the output buffer available" newline bitfld.long 0x0 1. "NDIOVF,New Data In Overflow" "0: No overflow has occurred,1: Indicates an overwrite of DATAIN register" bitfld.long 0x0 0. "NDI,New Data Input" "0: No new data in the data input buffer,1: New data in the data input buffer available" group.long 0x8++0xB line.long 0x0 "SMBSET,Status and Mailbox Set Register" bitfld.long 0x0 15. "USR5SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 14. "USR4SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 13. "USR3SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 12. "USR2SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 11. "USR1SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 10. "USR0SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 7. "NCERRFSET,Set request for SMBREAD register bit:" "0: any read access to this bit will return 0,?" bitfld.long 0x0 6. "WKUPSET,Set request for status reflection on SMBREAD register RUNST bit" "0: any read access tit his bit will return 0,?" line.long 0x4 "SMBCLR,Status and Mailbox Clear Register" bitfld.long 0x4 15. "USR5CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 14. "USR4CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 13. "USR3CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 12. "USR2CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 11. "USR1CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 10. "USR0CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 3. "NDOOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 1. "NDIOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" line.long 0x8 "ADCCAL,ADC Calibration Data for Gain and Offset Compensation" hexmask.long.word 0x8 16.--31. 1. "ADC_GAIN,These bits contain the ADC GAIN calibration values." hexmask.long.word 0x8 0.--15. 1. "ADC_OFFSET,These bits contain the ADC OFFSET calibration values 1." group.long 0x18++0x3 line.long 0x0 "DATAIN,Data Input buffer" hexmask.long.word 0x0 0.--15. 1. "DATAIN_1,ADC Data input" group.long 0x20++0x3 line.long 0x0 "DATAOUT,Data Output buffer" hexmask.long.word 0x0 16.--31. 1. "DATAOUTH,ADC Data output high word" hexmask.long.word 0x0 0.--15. 1. "DATAOUTL,ADC Data output low word" tree.end tree "DSPL_7" base ad:0x70A10000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 6. "DIIEN,Data Input Interface Enable" "0: Data Input Interface,1: Data Input Interface" bitfld.long 0x0 4. "DMAGATE,DMA Gating Bit" "0: DMA gating feature disabled,1: DMA gating feature enabled" newline bitfld.long 0x0 3. "DMAEN,DMA Enable:" "0: no DMA request,1: new value in DATAOUT register generates a DMA.." bitfld.long 0x0 1. "INIT_PM,Initialize TCPM" "0: TCPM init enabled: write access to TCPM is enabled,1: TCPM init complete" rgroup.long 0x4++0x3 line.long 0x0 "SMBREAD,Status and Mailbox Read Register" bitfld.long 0x0 15. "USR5,User flag 5" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 14. "USR4,User flag 4" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 13. "USR3,User flag 3" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 12. "USR2,User flag 2" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 11. "USR1,User flag 1" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 10. "USR0,User flag 0" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 7. "NCERRF,Non Correctable Error Flag" "0: No error is detected,1: A non correctable error has been detected" bitfld.long 0x0 6. "RUNST,RUN Status of DSP Core" "0: DSP core is in HALT mode,1: DSP core is in RUN mode" newline bitfld.long 0x0 5. "TOS1,Timer Output Status 1" "0: Timer output status 1 is low,1: Timer output status 1 is high" bitfld.long 0x0 4. "TOS0,Timer Output Status 0" "0: Timer output status 0 is low,1: Timer output status 0 is high" newline bitfld.long 0x0 3. "NDOOVF,New Data Out OVerFlow flag" "0: No overflow has occurred,1: Indicates an overwrite of DATAOUT register" bitfld.long 0x0 2. "NDO,New Data Output flag" "0: No new data in the output buffer,1: New data in the output buffer available" newline bitfld.long 0x0 1. "NDIOVF,New Data In Overflow" "0: No overflow has occurred,1: Indicates an overwrite of DATAIN register" bitfld.long 0x0 0. "NDI,New Data Input" "0: No new data in the data input buffer,1: New data in the data input buffer available" group.long 0x8++0xB line.long 0x0 "SMBSET,Status and Mailbox Set Register" bitfld.long 0x0 15. "USR5SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 14. "USR4SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 13. "USR3SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 12. "USR2SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 11. "USR1SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 10. "USR0SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 7. "NCERRFSET,Set request for SMBREAD register bit:" "0: any read access to this bit will return 0,?" bitfld.long 0x0 6. "WKUPSET,Set request for status reflection on SMBREAD register RUNST bit" "0: any read access tit his bit will return 0,?" line.long 0x4 "SMBCLR,Status and Mailbox Clear Register" bitfld.long 0x4 15. "USR5CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 14. "USR4CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 13. "USR3CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 12. "USR2CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 11. "USR1CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 10. "USR0CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 3. "NDOOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 1. "NDIOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" line.long 0x8 "ADCCAL,ADC Calibration Data for Gain and Offset Compensation" hexmask.long.word 0x8 16.--31. 1. "ADC_GAIN,These bits contain the ADC GAIN calibration values." hexmask.long.word 0x8 0.--15. 1. "ADC_OFFSET,These bits contain the ADC OFFSET calibration values 1." group.long 0x18++0x3 line.long 0x0 "DATAIN,Data Input buffer" hexmask.long.word 0x0 0.--15. 1. "DATAIN_1,ADC Data input" group.long 0x20++0x3 line.long 0x0 "DATAOUT,Data Output buffer" hexmask.long.word 0x0 16.--31. 1. "DATAOUTH,ADC Data output high word" hexmask.long.word 0x0 0.--15. 1. "DATAOUTL,ADC Data output low word" tree.end tree "DSPL_8" base ad:0x70414000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 6. "DIIEN,Data Input Interface Enable" "0: Data Input Interface,1: Data Input Interface" bitfld.long 0x0 4. "DMAGATE,DMA Gating Bit" "0: DMA gating feature disabled,1: DMA gating feature enabled" newline bitfld.long 0x0 3. "DMAEN,DMA Enable:" "0: no DMA request,1: new value in DATAOUT register generates a DMA.." bitfld.long 0x0 1. "INIT_PM,Initialize TCPM" "0: TCPM init enabled: write access to TCPM is enabled,1: TCPM init complete" rgroup.long 0x4++0x3 line.long 0x0 "SMBREAD,Status and Mailbox Read Register" bitfld.long 0x0 15. "USR5,User flag 5" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 14. "USR4,User flag 4" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 13. "USR3,User flag 3" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 12. "USR2,User flag 2" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 11. "USR1,User flag 1" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 10. "USR0,User flag 0" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 7. "NCERRF,Non Correctable Error Flag" "0: No error is detected,1: A non correctable error has been detected" bitfld.long 0x0 6. "RUNST,RUN Status of DSP Core" "0: DSP core is in HALT mode,1: DSP core is in RUN mode" newline bitfld.long 0x0 5. "TOS1,Timer Output Status 1" "0: Timer output status 1 is low,1: Timer output status 1 is high" bitfld.long 0x0 4. "TOS0,Timer Output Status 0" "0: Timer output status 0 is low,1: Timer output status 0 is high" newline bitfld.long 0x0 3. "NDOOVF,New Data Out OVerFlow flag" "0: No overflow has occurred,1: Indicates an overwrite of DATAOUT register" bitfld.long 0x0 2. "NDO,New Data Output flag" "0: No new data in the output buffer,1: New data in the output buffer available" newline bitfld.long 0x0 1. "NDIOVF,New Data In Overflow" "0: No overflow has occurred,1: Indicates an overwrite of DATAIN register" bitfld.long 0x0 0. "NDI,New Data Input" "0: No new data in the data input buffer,1: New data in the data input buffer available" group.long 0x8++0xB line.long 0x0 "SMBSET,Status and Mailbox Set Register" bitfld.long 0x0 15. "USR5SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 14. "USR4SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 13. "USR3SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 12. "USR2SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 11. "USR1SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 10. "USR0SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 7. "NCERRFSET,Set request for SMBREAD register bit:" "0: any read access to this bit will return 0,?" bitfld.long 0x0 6. "WKUPSET,Set request for status reflection on SMBREAD register RUNST bit" "0: any read access tit his bit will return 0,?" line.long 0x4 "SMBCLR,Status and Mailbox Clear Register" bitfld.long 0x4 15. "USR5CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 14. "USR4CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 13. "USR3CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 12. "USR2CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 11. "USR1CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 10. "USR0CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 3. "NDOOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 1. "NDIOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" line.long 0x8 "ADCCAL,ADC Calibration Data for Gain and Offset Compensation" hexmask.long.word 0x8 16.--31. 1. "ADC_GAIN,These bits contain the ADC GAIN calibration values." hexmask.long.word 0x8 0.--15. 1. "ADC_OFFSET,These bits contain the ADC OFFSET calibration values 1." group.long 0x18++0x3 line.long 0x0 "DATAIN,Data Input buffer" hexmask.long.word 0x0 0.--15. 1. "DATAIN_1,ADC Data input" group.long 0x20++0x3 line.long 0x0 "DATAOUT,Data Output buffer" hexmask.long.word 0x0 16.--31. 1. "DATAOUTH,ADC Data output high word" hexmask.long.word 0x0 0.--15. 1. "DATAOUTL,ADC Data output low word" tree.end tree "DSPL_9" base ad:0x70A14000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 6. "DIIEN,Data Input Interface Enable" "0: Data Input Interface,1: Data Input Interface" bitfld.long 0x0 4. "DMAGATE,DMA Gating Bit" "0: DMA gating feature disabled,1: DMA gating feature enabled" newline bitfld.long 0x0 3. "DMAEN,DMA Enable:" "0: no DMA request,1: new value in DATAOUT register generates a DMA.." bitfld.long 0x0 1. "INIT_PM,Initialize TCPM" "0: TCPM init enabled: write access to TCPM is enabled,1: TCPM init complete" rgroup.long 0x4++0x3 line.long 0x0 "SMBREAD,Status and Mailbox Read Register" bitfld.long 0x0 15. "USR5,User flag 5" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 14. "USR4,User flag 4" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 13. "USR3,User flag 3" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 12. "USR2,User flag 2" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 11. "USR1,User flag 1" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 10. "USR0,User flag 0" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 7. "NCERRF,Non Correctable Error Flag" "0: No error is detected,1: A non correctable error has been detected" bitfld.long 0x0 6. "RUNST,RUN Status of DSP Core" "0: DSP core is in HALT mode,1: DSP core is in RUN mode" newline bitfld.long 0x0 5. "TOS1,Timer Output Status 1" "0: Timer output status 1 is low,1: Timer output status 1 is high" bitfld.long 0x0 4. "TOS0,Timer Output Status 0" "0: Timer output status 0 is low,1: Timer output status 0 is high" newline bitfld.long 0x0 3. "NDOOVF,New Data Out OVerFlow flag" "0: No overflow has occurred,1: Indicates an overwrite of DATAOUT register" bitfld.long 0x0 2. "NDO,New Data Output flag" "0: No new data in the output buffer,1: New data in the output buffer available" newline bitfld.long 0x0 1. "NDIOVF,New Data In Overflow" "0: No overflow has occurred,1: Indicates an overwrite of DATAIN register" bitfld.long 0x0 0. "NDI,New Data Input" "0: No new data in the data input buffer,1: New data in the data input buffer available" group.long 0x8++0xB line.long 0x0 "SMBSET,Status and Mailbox Set Register" bitfld.long 0x0 15. "USR5SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 14. "USR4SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 13. "USR3SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 12. "USR2SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 11. "USR1SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 10. "USR0SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 7. "NCERRFSET,Set request for SMBREAD register bit:" "0: any read access to this bit will return 0,?" bitfld.long 0x0 6. "WKUPSET,Set request for status reflection on SMBREAD register RUNST bit" "0: any read access tit his bit will return 0,?" line.long 0x4 "SMBCLR,Status and Mailbox Clear Register" bitfld.long 0x4 15. "USR5CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 14. "USR4CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 13. "USR3CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 12. "USR2CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 11. "USR1CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 10. "USR0CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 3. "NDOOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 1. "NDIOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" line.long 0x8 "ADCCAL,ADC Calibration Data for Gain and Offset Compensation" hexmask.long.word 0x8 16.--31. 1. "ADC_GAIN,These bits contain the ADC GAIN calibration values." hexmask.long.word 0x8 0.--15. 1. "ADC_OFFSET,These bits contain the ADC OFFSET calibration values 1." group.long 0x18++0x3 line.long 0x0 "DATAIN,Data Input buffer" hexmask.long.word 0x0 0.--15. 1. "DATAIN_1,ADC Data input" group.long 0x20++0x3 line.long 0x0 "DATAOUT,Data Output buffer" hexmask.long.word 0x0 16.--31. 1. "DATAOUTH,ADC Data output high word" hexmask.long.word 0x0 0.--15. 1. "DATAOUTL,ADC Data output low word" tree.end tree "DSPL_10" base ad:0x70418000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 6. "DIIEN,Data Input Interface Enable" "0: Data Input Interface,1: Data Input Interface" bitfld.long 0x0 4. "DMAGATE,DMA Gating Bit" "0: DMA gating feature disabled,1: DMA gating feature enabled" newline bitfld.long 0x0 3. "DMAEN,DMA Enable:" "0: no DMA request,1: new value in DATAOUT register generates a DMA.." bitfld.long 0x0 1. "INIT_PM,Initialize TCPM" "0: TCPM init enabled: write access to TCPM is enabled,1: TCPM init complete" rgroup.long 0x4++0x3 line.long 0x0 "SMBREAD,Status and Mailbox Read Register" bitfld.long 0x0 15. "USR5,User flag 5" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 14. "USR4,User flag 4" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 13. "USR3,User flag 3" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 12. "USR2,User flag 2" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 11. "USR1,User flag 1" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 10. "USR0,User flag 0" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 7. "NCERRF,Non Correctable Error Flag" "0: No error is detected,1: A non correctable error has been detected" bitfld.long 0x0 6. "RUNST,RUN Status of DSP Core" "0: DSP core is in HALT mode,1: DSP core is in RUN mode" newline bitfld.long 0x0 5. "TOS1,Timer Output Status 1" "0: Timer output status 1 is low,1: Timer output status 1 is high" bitfld.long 0x0 4. "TOS0,Timer Output Status 0" "0: Timer output status 0 is low,1: Timer output status 0 is high" newline bitfld.long 0x0 3. "NDOOVF,New Data Out OVerFlow flag" "0: No overflow has occurred,1: Indicates an overwrite of DATAOUT register" bitfld.long 0x0 2. "NDO,New Data Output flag" "0: No new data in the output buffer,1: New data in the output buffer available" newline bitfld.long 0x0 1. "NDIOVF,New Data In Overflow" "0: No overflow has occurred,1: Indicates an overwrite of DATAIN register" bitfld.long 0x0 0. "NDI,New Data Input" "0: No new data in the data input buffer,1: New data in the data input buffer available" group.long 0x8++0xB line.long 0x0 "SMBSET,Status and Mailbox Set Register" bitfld.long 0x0 15. "USR5SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 14. "USR4SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 13. "USR3SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 12. "USR2SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 11. "USR1SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 10. "USR0SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 7. "NCERRFSET,Set request for SMBREAD register bit:" "0: any read access to this bit will return 0,?" bitfld.long 0x0 6. "WKUPSET,Set request for status reflection on SMBREAD register RUNST bit" "0: any read access tit his bit will return 0,?" line.long 0x4 "SMBCLR,Status and Mailbox Clear Register" bitfld.long 0x4 15. "USR5CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 14. "USR4CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 13. "USR3CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 12. "USR2CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 11. "USR1CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 10. "USR0CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 3. "NDOOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 1. "NDIOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" line.long 0x8 "ADCCAL,ADC Calibration Data for Gain and Offset Compensation" hexmask.long.word 0x8 16.--31. 1. "ADC_GAIN,These bits contain the ADC GAIN calibration values." hexmask.long.word 0x8 0.--15. 1. "ADC_OFFSET,These bits contain the ADC OFFSET calibration values 1." group.long 0x18++0x3 line.long 0x0 "DATAIN,Data Input buffer" hexmask.long.word 0x0 0.--15. 1. "DATAIN_1,ADC Data input" group.long 0x20++0x3 line.long 0x0 "DATAOUT,Data Output buffer" hexmask.long.word 0x0 16.--31. 1. "DATAOUTH,ADC Data output high word" hexmask.long.word 0x0 0.--15. 1. "DATAOUTL,ADC Data output low word" tree.end tree "DSPL_11" base ad:0x70A18000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 6. "DIIEN,Data Input Interface Enable" "0: Data Input Interface,1: Data Input Interface" bitfld.long 0x0 4. "DMAGATE,DMA Gating Bit" "0: DMA gating feature disabled,1: DMA gating feature enabled" newline bitfld.long 0x0 3. "DMAEN,DMA Enable:" "0: no DMA request,1: new value in DATAOUT register generates a DMA.." bitfld.long 0x0 1. "INIT_PM,Initialize TCPM" "0: TCPM init enabled: write access to TCPM is enabled,1: TCPM init complete" rgroup.long 0x4++0x3 line.long 0x0 "SMBREAD,Status and Mailbox Read Register" bitfld.long 0x0 15. "USR5,User flag 5" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 14. "USR4,User flag 4" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 13. "USR3,User flag 3" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 12. "USR2,User flag 2" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 11. "USR1,User flag 1" "0: User flag is reset,1: User flag is set" bitfld.long 0x0 10. "USR0,User flag 0" "0: User flag is reset,1: User flag is set" newline bitfld.long 0x0 7. "NCERRF,Non Correctable Error Flag" "0: No error is detected,1: A non correctable error has been detected" bitfld.long 0x0 6. "RUNST,RUN Status of DSP Core" "0: DSP core is in HALT mode,1: DSP core is in RUN mode" newline bitfld.long 0x0 5. "TOS1,Timer Output Status 1" "0: Timer output status 1 is low,1: Timer output status 1 is high" bitfld.long 0x0 4. "TOS0,Timer Output Status 0" "0: Timer output status 0 is low,1: Timer output status 0 is high" newline bitfld.long 0x0 3. "NDOOVF,New Data Out OVerFlow flag" "0: No overflow has occurred,1: Indicates an overwrite of DATAOUT register" bitfld.long 0x0 2. "NDO,New Data Output flag" "0: No new data in the output buffer,1: New data in the output buffer available" newline bitfld.long 0x0 1. "NDIOVF,New Data In Overflow" "0: No overflow has occurred,1: Indicates an overwrite of DATAIN register" bitfld.long 0x0 0. "NDI,New Data Input" "0: No new data in the data input buffer,1: New data in the data input buffer available" group.long 0x8++0xB line.long 0x0 "SMBSET,Status and Mailbox Set Register" bitfld.long 0x0 15. "USR5SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 14. "USR4SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 13. "USR3SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 12. "USR2SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 11. "USR1SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" bitfld.long 0x0 10. "USR0SET,Set request for corresponding SMBREAD register bit:" "0: a read access to this bit will return 0,?" newline bitfld.long 0x0 7. "NCERRFSET,Set request for SMBREAD register bit:" "0: any read access to this bit will return 0,?" bitfld.long 0x0 6. "WKUPSET,Set request for status reflection on SMBREAD register RUNST bit" "0: any read access tit his bit will return 0,?" line.long 0x4 "SMBCLR,Status and Mailbox Clear Register" bitfld.long 0x4 15. "USR5CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 14. "USR4CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 13. "USR3CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 12. "USR2CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 11. "USR1CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 10. "USR0CLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" newline bitfld.long 0x4 3. "NDOOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" bitfld.long 0x4 1. "NDIOVFCLR,Clear request for corresponding SMBREAD register bit." "0: a read access to this bit will return 0,?" line.long 0x8 "ADCCAL,ADC Calibration Data for Gain and Offset Compensation" hexmask.long.word 0x8 16.--31. 1. "ADC_GAIN,These bits contain the ADC GAIN calibration values." hexmask.long.word 0x8 0.--15. 1. "ADC_OFFSET,These bits contain the ADC OFFSET calibration values 1." group.long 0x18++0x3 line.long 0x0 "DATAIN,Data Input buffer" hexmask.long.word 0x0 0.--15. 1. "DATAIN_1,ADC Data input" group.long 0x20++0x3 line.long 0x0 "DATAOUT,Data Output buffer" hexmask.long.word 0x0 16.--31. 1. "DATAOUTH,ADC Data output high word" hexmask.long.word 0x0 0.--15. 1. "DATAOUTL,ADC Data output low word" tree.end tree.end tree "DTS (Development Trigger Semaphore)" base ad:0x70FCC000 group.long 0x0++0x17 line.long 0x0 "ENABLE,DTS output enable register" bitfld.long 0x0 1. "DTS_EN_B,DTS Enable B" "0: DTS output disabled. Any bit set in the..,1: DTS output enabled. Any bit set in the.." bitfld.long 0x0 0. "DTS_EN,DTS Enable" "0: DTS output disabled. Any bit set in the..,1: DTS output enabled. Any bit set in the.." line.long 0x4 "STARTUP,DTS startup register" hexmask.long 0x4 0.--31. 1. "AD,Application Dependent register bits. The bits have no defined meaning to the microcontroller. They are used to by an external tool to pass information (for example application options and status) to application software running on target.." line.long 0x8 "SEMAPHORE0,DTS semaphore register 0" hexmask.long 0x8 0.--31. 1. "ST,Semaphore Trigger. When a core or eDMA writes a logical '1' to a bit the bit is set. A write of '0' by the core or DMA does not change the state of the bit." line.long 0xC "SEMAPHORE1,DTS semaphore register 1" hexmask.long 0xC 0.--31. 1. "ST,Semaphore Trigger. When a core or eDMA writes a logical '1' to a bit the bit is set. A write of '0' by the core or DMA does not change the state of the bit." line.long 0x10 "SEMAPHORE2,DTS semaphore register 2" hexmask.long 0x10 0.--31. 1. "ST,Semaphore Trigger. When a core or eDMA writes a logical '1' to a bit the bit is set. A write of '0' by the core or DMA does not change the state of the bit." line.long 0x14 "SEMAPHORE3,DTS semaphore register 3" hexmask.long 0x14 0.--31. 1. "ST,Semaphore Trigger. When a core or eDMA writes a logical '1' to a bit the bit is set. A write of '0' by the core or DMA does not change the state of the bit." tree.end tree "EDMA (Enhanced Direct Memory Access)" base ad:0x0 tree "EDMA_0" base ad:0x703CC000 group.long 0x0++0x3 line.long 0x0 "CR,Control Register" bitfld.long 0x0 17. "CX,Cancel transfer" "0: Normal operation,1: Cancel the remaining data transfer. Stop the.." bitfld.long 0x0 16. "ECX,Error cancel transfer" "0: Normal operation,1: Cancel the remaining data transfer in the same.." newline bitfld.long 0x0 10. "GRP1PRI,Channel group 1 priority" "0,1" bitfld.long 0x0 8. "GRP0PRI,Channel group 0 priority" "0,1" newline bitfld.long 0x0 7. "EMLM,Enable minor loop mapping" "0: Disabled. TCDn.word2 is defined as a 32-bit..,1: Enabled. TCDn.word2 is redefined to include.." bitfld.long 0x0 6. "CLM,Continuous Link mode" "0: A minor loop channel link made to itself goes..,1: A minor loop channel link made to itself does.." newline bitfld.long 0x0 5. "HALT,Halt DMA operations" "0: Normal operation,1: Stall the start of any new channels. Executing.." bitfld.long 0x0 4. "HOE,Halt on error" "0: Normal operation,1: Any error causes the HALT bit to set." newline bitfld.long 0x0 3. "ERGA,Enable round-robin group arbitration" "0: Fixed-priority arbitration is used for selection..,1: Round-robin arbitration is used for selection.." bitfld.long 0x0 2. "ERCA,Enable round-robin channel arbitration" "0: Fixed-priority arbitration is used for channel..,1: Round-robin arbitration is used for channel.." newline bitfld.long 0x0 1. "EDBG,Enable debug" "0: When in Debug mode the DMA continues to operate.,1: When in Debug mode the DMA stalls the start of a.." bitfld.long 0x0 0. "EBW,Enable Buffered Writes" "0: The bufferable write signal (hprot[2]) is not..,1: The bufferable write signal (hprot[2]) is.." rgroup.long 0x4++0x3 line.long 0x0 "ES,Error Status Register" bitfld.long 0x0 31. "VLD,ERRH and ERRL status bits" "0: No ERR bits are set.,1: At least one ERR bit is set indicating a valid.." bitfld.long 0x0 17. "UCE,Uncorrectable ECC error" "0: No uncorrectable ECC error,1: The last recorded error was an uncorrectable TCD.." newline bitfld.long 0x0 16. "ECX,Transfer cancelled" "0: No cancelled transfers.,1: The last recorded entry was a cancelled transfer.." bitfld.long 0x0 15. "GPE,Group priority error" "0: No group priority error,1: The last recorded error was a configuration.." newline bitfld.long 0x0 14. "CPE,Channel priority error" "0: No channel priority error,1: The last recorded error was a configuration.." hexmask.long.byte 0x0 8.--13. 1. "ERRCHN,Error channel number or cancelled channel number GPE or last recorded error cancelled transfer." newline bitfld.long 0x0 7. "SAE,Source address error" "0: No source address configuration error.,1: The last recorded error was a configuration.." bitfld.long 0x0 6. "SOE,Source offset error" "0: No source offset configuration error,1: The last recorded error was a configuration.." newline bitfld.long 0x0 5. "DAE,Destination address error" "0: No destination address configuration error,1: The last recorded error was a configuration.." bitfld.long 0x0 4. "DOE,Destination offset error" "0: No destination offset configuration error,1: The last recorded error was a configuration.." newline bitfld.long 0x0 3. "NCE,NBYTES/CITER configuration error" "0: No NBYTES/CITER configuration error,1: The last recorded error was a configuration.." bitfld.long 0x0 2. "SGE,Scatter/gather configuration error" "0: No scatter/gather configuration error,1: The last recorded error was a configuration.." newline bitfld.long 0x0 1. "SBE,Source bus error" "0: No source bus error,1: The last recorded error was a bus error on a.." bitfld.long 0x0 0. "DBE,Destination bus error" "0: No destination bus error,1: The last recorded error was a bus error on a.." group.long 0xC++0x3 line.long 0x0 "ERQL,Enable Request Register Low" bitfld.long 0x0 31. "ERQ31,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 30. "ERQ30,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 29. "ERQ29,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 28. "ERQ28,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 27. "ERQ27,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 26. "ERQ26,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 25. "ERQ25,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 24. "ERQ24,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 23. "ERQ23,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 22. "ERQ22,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 21. "ERQ21,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 20. "ERQ20,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 19. "ERQ19,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 18. "ERQ18,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 17. "ERQ17,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 16. "ERQ16,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 15. "ERQ15,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 14. "ERQ14,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 13. "ERQ13,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 12. "ERQ12,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 11. "ERQ11,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 10. "ERQ10,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 9. "ERQ9,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 8. "ERQ8,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 7. "ERQ7,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 6. "ERQ6,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 5. "ERQ5,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 4. "ERQ4,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 3. "ERQ3,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 2. "ERQ2,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 1. "ERQ1,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 0. "ERQ0,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." group.long 0x14++0x3 line.long 0x0 "EEIL,Enable Error Interrupt Register Low" bitfld.long 0x0 31. "EEI31,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 30. "EEI30,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 29. "EEI29,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 28. "EEI28,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 27. "EEI27,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 26. "EEI26,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 25. "EEI25,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 24. "EEI24,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 23. "EEI23,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 22. "EEI22,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 21. "EEI21,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 20. "EEI20,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 19. "EEI19,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 18. "EEI18,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 17. "EEI17,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 16. "EEI16,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 15. "EEI15,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 14. "EEI14,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 13. "EEI13,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 12. "EEI12,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 11. "EEI11,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 10. "EEI10,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 9. "EEI9,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 8. "EEI8,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 7. "EEI7,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 6. "EEI6,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 5. "EEI5,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 4. "EEI4,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 3. "EEI3,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 2. "EEI2,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 1. "EEI1,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 0. "EEI0,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." wgroup.byte 0x18++0x7 line.byte 0x0 "CEEI,Clear Enable Error Interrupt Register" bitfld.byte 0x0 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x0 6. "CAEE,Clear all enable error interrupts" "0: Clear only those EEI bits specified in the CEEI..,1: Clear all bits in EEI" newline hexmask.byte 0x0 0.--5. 1. "CEEI,Clear enable error interrupt" line.byte 0x1 "SEEI,Set Enable Error Interrupt Register" bitfld.byte 0x1 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x1 6. "SAEE,Sets all enable error interrupts" "0: Set only those EEI bits specified in the SEEI..,1: Sets all bits in EEI." newline hexmask.byte 0x1 0.--5. 1. "SEEI,Set enable error interrupt" line.byte 0x2 "CERQ,Clear Enable Request Register" bitfld.byte 0x2 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x2 6. "CAER,Clear all enable requests" "0: Clear only those ERQ bits specified in the CERQ..,1: Clear all bits in ERQ" newline hexmask.byte 0x2 0.--5. 1. "CERQ,Clear enable request" line.byte 0x3 "SERQ,Set Enable Request Register" bitfld.byte 0x3 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x3 6. "SAER,Set all enable requests" "0: Set only those ERQ bits specified in the SERQ..,1: Set all bits in ERQ{H L}" newline hexmask.byte 0x3 0.--5. 1. "SERQ,Set enable request" line.byte 0x4 "CDNE,Clear DONE Status Bit Register" bitfld.byte 0x4 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x4 6. "CADN,Clears all DONE bits" "0: Clears only those TCDn_CSR[DONE] bits specified..,1: Clears all bits in TCDn_CSR[DONE]" newline hexmask.byte 0x4 0.--5. 1. "CDNE,Clear DONE bit" line.byte 0x5 "SSRT,Set START Bit Register" bitfld.byte 0x5 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x5 6. "SAST,Set all START bits (activates all channels)" "0: Set only those TCDn_CSR[START] bits specified in..,1: Set all bits in TCDn_CSR[START]" newline hexmask.byte 0x5 0.--5. 1. "SSRT,Set START bit" line.byte 0x6 "CERR,Clear Error Register" bitfld.byte 0x6 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x6 6. "CAEI,Clear all error indicators" "0: Clear only those ERR bits specified in the CERR..,1: Clear all bits in ERR" newline hexmask.byte 0x6 0.--5. 1. "CERR,Clear error indicator" line.byte 0x7 "CINT,Clear Interrupt Request Register" bitfld.byte 0x7 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x7 6. "CAIR,Clear all interrupt requests" "0: Clear only those INT bits specified in the CINT..,1: Clear all bits in INT{H L}" newline hexmask.byte 0x7 0.--5. 1. "CINT,Clear interrupt request" group.long 0x24++0x3 line.long 0x0 "INTL,Interrupt Request Register Low" bitfld.long 0x0 31. "INT31,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 30. "INT30,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 29. "INT29,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 28. "INT28,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 27. "INT27,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 26. "INT26,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 25. "INT25,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 24. "INT24,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 23. "INT23,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 22. "INT22,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 21. "INT21,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 20. "INT20,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 19. "INT19,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 18. "INT18,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 17. "INT17,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 16. "INT16,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 15. "INT15,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 14. "INT14,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 13. "INT13,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 12. "INT12,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 11. "INT11,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 10. "INT10,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 9. "INT9,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 8. "INT8,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 7. "INT7,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 6. "INT6,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 5. "INT5,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 4. "INT4,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 3. "INT3,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 2. "INT2,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 1. "INT1,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 0. "INT0,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." group.long 0x2C++0x3 line.long 0x0 "ERRL,Error Register Low" bitfld.long 0x0 31. "ERR31,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 30. "ERR30,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 29. "ERR29,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 28. "ERR28,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 27. "ERR27,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 26. "ERR26,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 25. "ERR25,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 24. "ERR24,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 23. "ERR23,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 22. "ERR22,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 21. "ERR21,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 20. "ERR20,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 19. "ERR19,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 18. "ERR18,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 17. "ERR17,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 16. "ERR16,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 15. "ERR15,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 14. "ERR14,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 13. "ERR13,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 12. "ERR12,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 11. "ERR11,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 10. "ERR10,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 9. "ERR9,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 8. "ERR8,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 7. "ERR7,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 6. "ERR6,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 5. "ERR5,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 4. "ERR4,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 3. "ERR3,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 2. "ERR2,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 1. "ERR1,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 0. "ERR0,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." group.long 0x34++0x3 line.long 0x0 "HRSL,Hardware Request Status Register Low" bitfld.long 0x0 31. "HRS31,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 30. "HRS30,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 29. "HRS29,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 28. "HRS28,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 27. "HRS27,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 26. "HRS26,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 25. "HRS25,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 24. "HRS24,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 23. "HRS23,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 22. "HRS22,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 21. "HRS21,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 20. "HRS20,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 19. "HRS19,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 18. "HRS18,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 17. "HRS17,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 16. "HRS16,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 15. "HRS15,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 14. "HRS14,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 13. "HRS13,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 12. "HRS12,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 11. "HRS11,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 10. "HRS10,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 9. "HRS9,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 8. "HRS8,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 7. "HRS7,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 6. "HRS6,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 5. "HRS5,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 4. "HRS4,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 3. "HRS3,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 2. "HRS2,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 1. "HRS1,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 0. "HRS0,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." group.byte 0x100++0x1F line.byte 0x0 "DCHPRI3,Channel n Priority register" bitfld.byte 0x0 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x0 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x0 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x0 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1 "DCHPRI2,Channel n Priority register" bitfld.byte 0x1 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x2 "DCHPRI1,Channel n Priority register" bitfld.byte 0x2 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x2 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x2 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x2 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x3 "DCHPRI0,Channel n Priority register" bitfld.byte 0x3 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x3 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x3 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x3 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x4 "DCHPRI7,Channel n Priority register" bitfld.byte 0x4 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x4 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x4 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x4 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x5 "DCHPRI6,Channel n Priority register" bitfld.byte 0x5 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x5 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x5 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x5 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x6 "DCHPRI5,Channel n Priority register" bitfld.byte 0x6 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x6 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x6 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x6 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x7 "DCHPRI4,Channel n Priority register" bitfld.byte 0x7 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x7 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x7 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x7 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x8 "DCHPRI11,Channel n Priority register" bitfld.byte 0x8 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x8 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x8 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x8 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x9 "DCHPRI10,Channel n Priority register" bitfld.byte 0x9 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x9 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x9 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x9 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xA "DCHPRI9,Channel n Priority register" bitfld.byte 0xA 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xA 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xA 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xA 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xB "DCHPRI8,Channel n Priority register" bitfld.byte 0xB 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xB 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xB 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xB 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xC "DCHPRI15,Channel n Priority register" bitfld.byte 0xC 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xC 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xC 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xC 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xD "DCHPRI14,Channel n Priority register" bitfld.byte 0xD 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xD 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xD 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xD 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xE "DCHPRI13,Channel n Priority register" bitfld.byte 0xE 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xE 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xE 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xE 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xF "DCHPRI12,Channel n Priority register" bitfld.byte 0xF 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xF 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xF 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xF 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x10 "DCHPRI19,Channel n Priority register" bitfld.byte 0x10 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x10 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x10 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x10 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x11 "DCHPRI18,Channel n Priority register" bitfld.byte 0x11 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x11 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x11 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x11 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x12 "DCHPRI17,Channel n Priority register" bitfld.byte 0x12 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x12 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x12 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x12 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x13 "DCHPRI16,Channel n Priority register" bitfld.byte 0x13 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x13 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x13 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x13 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x14 "DCHPRI23,Channel n Priority register" bitfld.byte 0x14 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x14 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x14 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x14 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x15 "DCHPRI22,Channel n Priority register" bitfld.byte 0x15 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x15 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x15 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x15 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x16 "DCHPRI21,Channel n Priority register" bitfld.byte 0x16 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x16 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x16 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x16 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x17 "DCHPRI20,Channel n Priority register" bitfld.byte 0x17 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x17 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x17 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x17 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x18 "DCHPRI27,Channel n Priority register" bitfld.byte 0x18 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x18 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x18 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x18 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x19 "DCHPRI26,Channel n Priority register" bitfld.byte 0x19 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x19 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x19 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x19 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1A "DCHPRI25,Channel n Priority register" bitfld.byte 0x1A 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1A 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1A 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1A 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1B "DCHPRI24,Channel n Priority register" bitfld.byte 0x1B 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1B 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1B 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1B 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1C "DCHPRI31,Channel n Priority register" bitfld.byte 0x1C 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1C 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1C 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1C 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1D "DCHPRI30,Channel n Priority register" bitfld.byte 0x1D 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1D 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1D 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1D 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1E "DCHPRI29,Channel n Priority register" bitfld.byte 0x1E 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1E 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1E 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1E 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1F "DCHPRI28,Channel n Priority register" bitfld.byte 0x1F 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1F 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1F 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1F 0.--3. 1. "CHPRI,Channel n arbitration priority" group.byte 0x140++0x1F line.byte 0x0 "REQSTR_ID0,Channel 0 Requester ID register" bitfld.byte 0x0 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x0 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x0 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x1 "REQSTR_ID1,Channel 1 Requester ID register" bitfld.byte 0x1 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x1 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x1 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x2 "REQSTR_ID2,Channel 2 Requester ID register" bitfld.byte 0x2 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x2 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x2 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x3 "REQSTR_ID3,Channel 3 Requester ID register" bitfld.byte 0x3 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x3 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x3 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x4 "REQSTR_ID4,Channel 4 Requester ID register" bitfld.byte 0x4 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x4 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x4 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x5 "REQSTR_ID5,Channel 5 Requester ID register" bitfld.byte 0x5 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x5 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x5 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x6 "REQSTR_ID6,Channel 6 Requester ID register" bitfld.byte 0x6 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x6 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x6 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x7 "REQSTR_ID7,Channel 7 Requester ID register" bitfld.byte 0x7 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x7 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x7 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x8 "REQSTR_ID8,Channel 8 Requester ID register" bitfld.byte 0x8 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x8 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x8 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x9 "REQSTR_ID9,Channel 9 Requester ID register" bitfld.byte 0x9 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x9 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x9 0.--5. 1. "REQ_ID,Requester ID" line.byte 0xA "REQSTR_ID10,Channel 10 Requester ID register" bitfld.byte 0xA 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0xA 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0xA 0.--5. 1. "REQ_ID,Requester ID" line.byte 0xB "REQSTR_ID11,Channel 11 Requester ID register" bitfld.byte 0xB 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0xB 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0xB 0.--5. 1. "REQ_ID,Requester ID" line.byte 0xC "REQSTR_ID12,Channel 12 Requester ID register" bitfld.byte 0xC 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0xC 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0xC 0.--5. 1. "REQ_ID,Requester ID" line.byte 0xD "REQSTR_ID13,Channel 13 Requester ID register" bitfld.byte 0xD 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0xD 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0xD 0.--5. 1. "REQ_ID,Requester ID" line.byte 0xE "REQSTR_ID14,Channel 14 Requester ID register" bitfld.byte 0xE 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0xE 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0xE 0.--5. 1. "REQ_ID,Requester ID" line.byte 0xF "REQSTR_ID15,Channel 15 Requester ID register" bitfld.byte 0xF 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0xF 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0xF 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x10 "REQSTR_ID16,Channel 16 Requester ID register" bitfld.byte 0x10 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x10 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x10 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x11 "REQSTR_ID17,Channel 17 Requester ID register" bitfld.byte 0x11 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x11 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x11 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x12 "REQSTR_ID18,Channel 18 Requester ID register" bitfld.byte 0x12 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x12 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x12 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x13 "REQSTR_ID19,Channel 19 Requester ID register" bitfld.byte 0x13 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x13 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x13 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x14 "REQSTR_ID20,Channel 20 Requester ID register" bitfld.byte 0x14 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x14 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x14 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x15 "REQSTR_ID21,Channel 21 Requester ID register" bitfld.byte 0x15 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x15 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x15 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x16 "REQSTR_ID22,Channel 22 Requester ID register" bitfld.byte 0x16 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x16 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x16 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x17 "REQSTR_ID23,Channel 23 Requester ID register" bitfld.byte 0x17 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x17 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x17 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x18 "REQSTR_ID24,Channel 24 Requester ID register" bitfld.byte 0x18 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x18 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x18 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x19 "REQSTR_ID25,Channel 25 Requester ID register" bitfld.byte 0x19 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x19 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x19 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x1A "REQSTR_ID26,Channel 26 Requester ID register" bitfld.byte 0x1A 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x1A 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x1A 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x1B "REQSTR_ID27,Channel 27 Requester ID register" bitfld.byte 0x1B 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x1B 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x1B 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x1C "REQSTR_ID28,Channel 28 Requester ID register" bitfld.byte 0x1C 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x1C 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x1C 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x1D "REQSTR_ID29,Channel 29 Requester ID register" bitfld.byte 0x1D 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x1D 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x1D 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x1E "REQSTR_ID30,Channel 30 Requester ID register" bitfld.byte 0x1E 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x1E 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x1E 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x1F "REQSTR_ID31,Channel 31 Requester ID register" bitfld.byte 0x1F 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x1F 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x1F 0.--5. 1. "REQ_ID,Requester ID" group.long 0x180++0x7 line.long 0x0 "VMID0,Channel 0 to 15 VMID Register" bitfld.long 0x0 8. "VMID_EN,VMID_0 Enable" "0: 8-bit VMID value out disabled.,1: 8-bit VMID value out enabled." hexmask.long.byte 0x0 0.--7. 1. "VMID,VMID_0 value" line.long 0x4 "VMID1,Channel 16 to 31 VMID Register" bitfld.long 0x4 8. "VMID_EN,VMID_1 Enable" "0: 8-bit VMID value out disabled.,1: 8-bit VMID value out enabled." hexmask.long.byte 0x4 0.--7. 1. "VMID,VMID_1 value" group.long 0x190++0x3 line.long 0x0 "VMID_ERR_STATUS,Channel VMID Error Status register" bitfld.long 0x0 0. "VMID_ERR,VMID error" "0: No Non-Hypervisor Access to eDMA_VMID_n register,1: Transfer Error for Non-Hypervisor Access to.." group.long 0x1000++0x3 line.long 0x0 "TCD0_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1004++0x3 line.word 0x0 "TCD0_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD0_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1008++0x3 line.long 0x0 "TCD0_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1008++0x3 line.long 0x0 "TCD0_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1008++0xB line.long 0x0 "TCD0_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD0_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD0_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1014++0x3 line.word 0x0 "TCD0_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1016++0x1 line.word 0x0 "TCD0_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1018++0x3 line.long 0x0 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x101C++0x3 line.word 0x0 "TCD0_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD0_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x101E++0x1 line.word 0x0 "TCD0_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1020++0x3 line.long 0x0 "TCD1_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1024++0x3 line.word 0x0 "TCD1_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD1_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1028++0x3 line.long 0x0 "TCD1_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1028++0x3 line.long 0x0 "TCD1_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1028++0xB line.long 0x0 "TCD1_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD1_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD1_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1034++0x3 line.word 0x0 "TCD1_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1036++0x1 line.word 0x0 "TCD1_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1038++0x3 line.long 0x0 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x103C++0x3 line.word 0x0 "TCD1_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD1_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x103E++0x1 line.word 0x0 "TCD1_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1040++0x3 line.long 0x0 "TCD2_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1044++0x3 line.word 0x0 "TCD2_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD2_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1048++0x3 line.long 0x0 "TCD2_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1048++0x3 line.long 0x0 "TCD2_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1048++0xB line.long 0x0 "TCD2_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD2_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD2_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1054++0x3 line.word 0x0 "TCD2_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1056++0x1 line.word 0x0 "TCD2_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1058++0x3 line.long 0x0 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x105C++0x3 line.word 0x0 "TCD2_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD2_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x105E++0x1 line.word 0x0 "TCD2_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1060++0x3 line.long 0x0 "TCD3_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1064++0x3 line.word 0x0 "TCD3_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD3_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1068++0x3 line.long 0x0 "TCD3_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1068++0x3 line.long 0x0 "TCD3_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1068++0xB line.long 0x0 "TCD3_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD3_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD3_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1074++0x3 line.word 0x0 "TCD3_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1076++0x1 line.word 0x0 "TCD3_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1078++0x3 line.long 0x0 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x107C++0x3 line.word 0x0 "TCD3_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD3_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x107E++0x1 line.word 0x0 "TCD3_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1080++0x3 line.long 0x0 "TCD4_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1084++0x3 line.word 0x0 "TCD4_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD4_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1088++0x3 line.long 0x0 "TCD4_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1088++0x3 line.long 0x0 "TCD4_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1088++0xB line.long 0x0 "TCD4_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD4_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD4_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1094++0x3 line.word 0x0 "TCD4_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD4_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1096++0x1 line.word 0x0 "TCD4_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1098++0x3 line.long 0x0 "TCD4_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x109C++0x3 line.word 0x0 "TCD4_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD4_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x109E++0x1 line.word 0x0 "TCD4_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x10A0++0x3 line.long 0x0 "TCD5_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x10A4++0x3 line.word 0x0 "TCD5_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD5_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x10A8++0x3 line.long 0x0 "TCD5_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x10A8++0x3 line.long 0x0 "TCD5_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x10A8++0xB line.long 0x0 "TCD5_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD5_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD5_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x10B4++0x3 line.word 0x0 "TCD5_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD5_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x10B6++0x1 line.word 0x0 "TCD5_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x10B8++0x3 line.long 0x0 "TCD5_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x10BC++0x3 line.word 0x0 "TCD5_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD5_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x10BE++0x1 line.word 0x0 "TCD5_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x10C0++0x3 line.long 0x0 "TCD6_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x10C4++0x3 line.word 0x0 "TCD6_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD6_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x10C8++0x3 line.long 0x0 "TCD6_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x10C8++0x3 line.long 0x0 "TCD6_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x10C8++0xB line.long 0x0 "TCD6_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD6_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD6_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x10D4++0x3 line.word 0x0 "TCD6_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD6_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x10D6++0x1 line.word 0x0 "TCD6_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x10D8++0x3 line.long 0x0 "TCD6_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x10DC++0x3 line.word 0x0 "TCD6_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD6_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x10DE++0x1 line.word 0x0 "TCD6_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x10E0++0x3 line.long 0x0 "TCD7_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x10E4++0x3 line.word 0x0 "TCD7_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD7_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x10E8++0x3 line.long 0x0 "TCD7_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x10E8++0x3 line.long 0x0 "TCD7_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x10E8++0xB line.long 0x0 "TCD7_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD7_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD7_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x10F4++0x3 line.word 0x0 "TCD7_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD7_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x10F6++0x1 line.word 0x0 "TCD7_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x10F8++0x3 line.long 0x0 "TCD7_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x10FC++0x3 line.word 0x0 "TCD7_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD7_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x10FE++0x1 line.word 0x0 "TCD7_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1100++0x3 line.long 0x0 "TCD8_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1104++0x3 line.word 0x0 "TCD8_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD8_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1108++0x3 line.long 0x0 "TCD8_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1108++0x3 line.long 0x0 "TCD8_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1108++0xB line.long 0x0 "TCD8_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD8_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD8_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1114++0x3 line.word 0x0 "TCD8_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD8_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1116++0x1 line.word 0x0 "TCD8_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1118++0x3 line.long 0x0 "TCD8_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x111C++0x3 line.word 0x0 "TCD8_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD8_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x111E++0x1 line.word 0x0 "TCD8_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1120++0x3 line.long 0x0 "TCD9_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1124++0x3 line.word 0x0 "TCD9_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD9_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1128++0x3 line.long 0x0 "TCD9_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1128++0x3 line.long 0x0 "TCD9_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1128++0xB line.long 0x0 "TCD9_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD9_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD9_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1134++0x3 line.word 0x0 "TCD9_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD9_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1136++0x1 line.word 0x0 "TCD9_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1138++0x3 line.long 0x0 "TCD9_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x113C++0x3 line.word 0x0 "TCD9_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD9_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x113E++0x1 line.word 0x0 "TCD9_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1140++0x3 line.long 0x0 "TCD10_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1144++0x3 line.word 0x0 "TCD10_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD10_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1148++0x3 line.long 0x0 "TCD10_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1148++0x3 line.long 0x0 "TCD10_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1148++0xB line.long 0x0 "TCD10_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD10_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD10_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1154++0x3 line.word 0x0 "TCD10_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD10_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1156++0x1 line.word 0x0 "TCD10_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1158++0x3 line.long 0x0 "TCD10_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x115C++0x3 line.word 0x0 "TCD10_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD10_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x115E++0x1 line.word 0x0 "TCD10_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1160++0x3 line.long 0x0 "TCD11_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1164++0x3 line.word 0x0 "TCD11_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD11_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1168++0x3 line.long 0x0 "TCD11_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1168++0x3 line.long 0x0 "TCD11_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1168++0xB line.long 0x0 "TCD11_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD11_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD11_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1174++0x3 line.word 0x0 "TCD11_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD11_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1176++0x1 line.word 0x0 "TCD11_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1178++0x3 line.long 0x0 "TCD11_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x117C++0x3 line.word 0x0 "TCD11_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD11_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x117E++0x1 line.word 0x0 "TCD11_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1180++0x3 line.long 0x0 "TCD12_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1184++0x3 line.word 0x0 "TCD12_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD12_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1188++0x3 line.long 0x0 "TCD12_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1188++0x3 line.long 0x0 "TCD12_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1188++0xB line.long 0x0 "TCD12_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD12_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD12_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1194++0x3 line.word 0x0 "TCD12_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD12_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1196++0x1 line.word 0x0 "TCD12_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1198++0x3 line.long 0x0 "TCD12_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x119C++0x3 line.word 0x0 "TCD12_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD12_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x119E++0x1 line.word 0x0 "TCD12_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x11A0++0x3 line.long 0x0 "TCD13_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x11A4++0x3 line.word 0x0 "TCD13_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD13_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x11A8++0x3 line.long 0x0 "TCD13_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x11A8++0x3 line.long 0x0 "TCD13_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x11A8++0xB line.long 0x0 "TCD13_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD13_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD13_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x11B4++0x3 line.word 0x0 "TCD13_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD13_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x11B6++0x1 line.word 0x0 "TCD13_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x11B8++0x3 line.long 0x0 "TCD13_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x11BC++0x3 line.word 0x0 "TCD13_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD13_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x11BE++0x1 line.word 0x0 "TCD13_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x11C0++0x3 line.long 0x0 "TCD14_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x11C4++0x3 line.word 0x0 "TCD14_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD14_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x11C8++0x3 line.long 0x0 "TCD14_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x11C8++0x3 line.long 0x0 "TCD14_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x11C8++0xB line.long 0x0 "TCD14_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD14_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD14_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x11D4++0x3 line.word 0x0 "TCD14_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD14_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x11D6++0x1 line.word 0x0 "TCD14_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x11D8++0x3 line.long 0x0 "TCD14_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x11DC++0x3 line.word 0x0 "TCD14_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD14_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x11DE++0x1 line.word 0x0 "TCD14_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x11E0++0x3 line.long 0x0 "TCD15_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x11E4++0x3 line.word 0x0 "TCD15_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD15_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x11E8++0x3 line.long 0x0 "TCD15_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x11E8++0x3 line.long 0x0 "TCD15_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x11E8++0xB line.long 0x0 "TCD15_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD15_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD15_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x11F4++0x3 line.word 0x0 "TCD15_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD15_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x11F6++0x1 line.word 0x0 "TCD15_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x11F8++0x3 line.long 0x0 "TCD15_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x11FC++0x3 line.word 0x0 "TCD15_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD15_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x11FE++0x1 line.word 0x0 "TCD15_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1200++0x3 line.long 0x0 "TCD16_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1204++0x3 line.word 0x0 "TCD16_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD16_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1208++0x3 line.long 0x0 "TCD16_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1208++0x3 line.long 0x0 "TCD16_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1208++0xB line.long 0x0 "TCD16_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD16_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD16_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1214++0x3 line.word 0x0 "TCD16_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD16_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1216++0x1 line.word 0x0 "TCD16_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1218++0x3 line.long 0x0 "TCD16_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x121C++0x3 line.word 0x0 "TCD16_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD16_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x121E++0x1 line.word 0x0 "TCD16_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1220++0x3 line.long 0x0 "TCD17_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1224++0x3 line.word 0x0 "TCD17_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD17_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1228++0x3 line.long 0x0 "TCD17_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1228++0x3 line.long 0x0 "TCD17_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1228++0xB line.long 0x0 "TCD17_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD17_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD17_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1234++0x3 line.word 0x0 "TCD17_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD17_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1236++0x1 line.word 0x0 "TCD17_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1238++0x3 line.long 0x0 "TCD17_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x123C++0x3 line.word 0x0 "TCD17_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD17_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x123E++0x1 line.word 0x0 "TCD17_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1240++0x3 line.long 0x0 "TCD18_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1244++0x3 line.word 0x0 "TCD18_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD18_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1248++0x3 line.long 0x0 "TCD18_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1248++0x3 line.long 0x0 "TCD18_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1248++0xB line.long 0x0 "TCD18_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD18_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD18_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1254++0x3 line.word 0x0 "TCD18_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD18_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1256++0x1 line.word 0x0 "TCD18_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1258++0x3 line.long 0x0 "TCD18_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x125C++0x3 line.word 0x0 "TCD18_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD18_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x125E++0x1 line.word 0x0 "TCD18_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1260++0x3 line.long 0x0 "TCD19_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1264++0x3 line.word 0x0 "TCD19_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD19_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1268++0x3 line.long 0x0 "TCD19_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1268++0x3 line.long 0x0 "TCD19_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1268++0xB line.long 0x0 "TCD19_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD19_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD19_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1274++0x3 line.word 0x0 "TCD19_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD19_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1276++0x1 line.word 0x0 "TCD19_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1278++0x3 line.long 0x0 "TCD19_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x127C++0x3 line.word 0x0 "TCD19_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD19_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x127E++0x1 line.word 0x0 "TCD19_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1280++0x3 line.long 0x0 "TCD20_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1284++0x3 line.word 0x0 "TCD20_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD20_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1288++0x3 line.long 0x0 "TCD20_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1288++0x3 line.long 0x0 "TCD20_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1288++0xB line.long 0x0 "TCD20_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD20_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD20_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1294++0x3 line.word 0x0 "TCD20_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD20_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1296++0x1 line.word 0x0 "TCD20_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1298++0x3 line.long 0x0 "TCD20_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x129C++0x3 line.word 0x0 "TCD20_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD20_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x129E++0x1 line.word 0x0 "TCD20_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x12A0++0x3 line.long 0x0 "TCD21_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x12A4++0x3 line.word 0x0 "TCD21_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD21_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x12A8++0x3 line.long 0x0 "TCD21_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x12A8++0x3 line.long 0x0 "TCD21_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x12A8++0xB line.long 0x0 "TCD21_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD21_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD21_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x12B4++0x3 line.word 0x0 "TCD21_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD21_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x12B6++0x1 line.word 0x0 "TCD21_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x12B8++0x3 line.long 0x0 "TCD21_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x12BC++0x3 line.word 0x0 "TCD21_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD21_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x12BE++0x1 line.word 0x0 "TCD21_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x12C0++0x3 line.long 0x0 "TCD22_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x12C4++0x3 line.word 0x0 "TCD22_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD22_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x12C8++0x3 line.long 0x0 "TCD22_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x12C8++0x3 line.long 0x0 "TCD22_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x12C8++0xB line.long 0x0 "TCD22_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD22_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD22_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x12D4++0x3 line.word 0x0 "TCD22_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD22_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x12D6++0x1 line.word 0x0 "TCD22_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x12D8++0x3 line.long 0x0 "TCD22_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x12DC++0x3 line.word 0x0 "TCD22_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD22_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x12DE++0x1 line.word 0x0 "TCD22_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x12E0++0x3 line.long 0x0 "TCD23_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x12E4++0x3 line.word 0x0 "TCD23_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD23_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x12E8++0x3 line.long 0x0 "TCD23_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x12E8++0x3 line.long 0x0 "TCD23_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x12E8++0xB line.long 0x0 "TCD23_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD23_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD23_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x12F4++0x3 line.word 0x0 "TCD23_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD23_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x12F6++0x1 line.word 0x0 "TCD23_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x12F8++0x3 line.long 0x0 "TCD23_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x12FC++0x3 line.word 0x0 "TCD23_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD23_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x12FE++0x1 line.word 0x0 "TCD23_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1300++0x3 line.long 0x0 "TCD24_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1304++0x3 line.word 0x0 "TCD24_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD24_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1308++0x3 line.long 0x0 "TCD24_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1308++0x3 line.long 0x0 "TCD24_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1308++0xB line.long 0x0 "TCD24_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD24_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD24_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1314++0x3 line.word 0x0 "TCD24_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD24_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1316++0x1 line.word 0x0 "TCD24_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1318++0x3 line.long 0x0 "TCD24_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x131C++0x3 line.word 0x0 "TCD24_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD24_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x131E++0x1 line.word 0x0 "TCD24_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1320++0x3 line.long 0x0 "TCD25_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1324++0x3 line.word 0x0 "TCD25_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD25_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1328++0x3 line.long 0x0 "TCD25_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1328++0x3 line.long 0x0 "TCD25_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1328++0xB line.long 0x0 "TCD25_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD25_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD25_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1334++0x3 line.word 0x0 "TCD25_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD25_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1336++0x1 line.word 0x0 "TCD25_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1338++0x3 line.long 0x0 "TCD25_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x133C++0x3 line.word 0x0 "TCD25_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD25_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x133E++0x1 line.word 0x0 "TCD25_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1340++0x3 line.long 0x0 "TCD26_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1344++0x3 line.word 0x0 "TCD26_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD26_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1348++0x3 line.long 0x0 "TCD26_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1348++0x3 line.long 0x0 "TCD26_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1348++0xB line.long 0x0 "TCD26_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD26_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD26_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1354++0x3 line.word 0x0 "TCD26_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD26_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1356++0x1 line.word 0x0 "TCD26_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1358++0x3 line.long 0x0 "TCD26_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x135C++0x3 line.word 0x0 "TCD26_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD26_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x135E++0x1 line.word 0x0 "TCD26_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1360++0x3 line.long 0x0 "TCD27_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1364++0x3 line.word 0x0 "TCD27_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD27_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1368++0x3 line.long 0x0 "TCD27_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1368++0x3 line.long 0x0 "TCD27_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1368++0xB line.long 0x0 "TCD27_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD27_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD27_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1374++0x3 line.word 0x0 "TCD27_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD27_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1376++0x1 line.word 0x0 "TCD27_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1378++0x3 line.long 0x0 "TCD27_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x137C++0x3 line.word 0x0 "TCD27_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD27_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x137E++0x1 line.word 0x0 "TCD27_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1380++0x3 line.long 0x0 "TCD28_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1384++0x3 line.word 0x0 "TCD28_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD28_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1388++0x3 line.long 0x0 "TCD28_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1388++0x3 line.long 0x0 "TCD28_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1388++0xB line.long 0x0 "TCD28_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD28_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD28_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1394++0x3 line.word 0x0 "TCD28_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD28_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1396++0x1 line.word 0x0 "TCD28_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1398++0x3 line.long 0x0 "TCD28_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x139C++0x3 line.word 0x0 "TCD28_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD28_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x139E++0x1 line.word 0x0 "TCD28_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x13A0++0x3 line.long 0x0 "TCD29_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x13A4++0x3 line.word 0x0 "TCD29_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD29_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x13A8++0x3 line.long 0x0 "TCD29_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x13A8++0x3 line.long 0x0 "TCD29_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x13A8++0xB line.long 0x0 "TCD29_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD29_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD29_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x13B4++0x3 line.word 0x0 "TCD29_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD29_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x13B6++0x1 line.word 0x0 "TCD29_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x13B8++0x3 line.long 0x0 "TCD29_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x13BC++0x3 line.word 0x0 "TCD29_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD29_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x13BE++0x1 line.word 0x0 "TCD29_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x13C0++0x3 line.long 0x0 "TCD30_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x13C4++0x3 line.word 0x0 "TCD30_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD30_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x13C8++0x3 line.long 0x0 "TCD30_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x13C8++0x3 line.long 0x0 "TCD30_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x13C8++0xB line.long 0x0 "TCD30_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD30_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD30_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x13D4++0x3 line.word 0x0 "TCD30_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD30_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x13D6++0x1 line.word 0x0 "TCD30_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x13D8++0x3 line.long 0x0 "TCD30_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x13DC++0x3 line.word 0x0 "TCD30_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD30_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x13DE++0x1 line.word 0x0 "TCD30_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x13E0++0x3 line.long 0x0 "TCD31_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x13E4++0x3 line.word 0x0 "TCD31_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD31_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x13E8++0x3 line.long 0x0 "TCD31_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x13E8++0x3 line.long 0x0 "TCD31_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x13E8++0xB line.long 0x0 "TCD31_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD31_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD31_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x13F4++0x3 line.word 0x0 "TCD31_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD31_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x13F6++0x1 line.word 0x0 "TCD31_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x13F8++0x3 line.long 0x0 "TCD31_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x13FC++0x3 line.word 0x0 "TCD31_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD31_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x13FE++0x1 line.word 0x0 "TCD31_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" tree.end tree "EDMA_1" base ad:0x709CC000 group.long 0x0++0x3 line.long 0x0 "CR,Control Register" bitfld.long 0x0 17. "CX,Cancel transfer" "0: Normal operation,1: Cancel the remaining data transfer. Stop the.." bitfld.long 0x0 16. "ECX,Error cancel transfer" "0: Normal operation,1: Cancel the remaining data transfer in the same.." newline bitfld.long 0x0 10. "GRP1PRI,Channel group 1 priority" "0,1" bitfld.long 0x0 8. "GRP0PRI,Channel group 0 priority" "0,1" newline bitfld.long 0x0 7. "EMLM,Enable minor loop mapping" "0: Disabled. TCDn.word2 is defined as a 32-bit..,1: Enabled. TCDn.word2 is redefined to include.." bitfld.long 0x0 6. "CLM,Continuous Link mode" "0: A minor loop channel link made to itself goes..,1: A minor loop channel link made to itself does.." newline bitfld.long 0x0 5. "HALT,Halt DMA operations" "0: Normal operation,1: Stall the start of any new channels. Executing.." bitfld.long 0x0 4. "HOE,Halt on error" "0: Normal operation,1: Any error causes the HALT bit to set." newline bitfld.long 0x0 3. "ERGA,Enable round-robin group arbitration" "0: Fixed-priority arbitration is used for selection..,1: Round-robin arbitration is used for selection.." bitfld.long 0x0 2. "ERCA,Enable round-robin channel arbitration" "0: Fixed-priority arbitration is used for channel..,1: Round-robin arbitration is used for channel.." newline bitfld.long 0x0 1. "EDBG,Enable debug" "0: When in Debug mode the DMA continues to operate.,1: When in Debug mode the DMA stalls the start of a.." bitfld.long 0x0 0. "EBW,Enable Buffered Writes" "0: The bufferable write signal (hprot[2]) is not..,1: The bufferable write signal (hprot[2]) is.." rgroup.long 0x4++0x3 line.long 0x0 "ES,Error Status Register" bitfld.long 0x0 31. "VLD,ERRH and ERRL status bits" "0: No ERR bits are set.,1: At least one ERR bit is set indicating a valid.." bitfld.long 0x0 17. "UCE,Uncorrectable ECC error" "0: No uncorrectable ECC error,1: The last recorded error was an uncorrectable TCD.." newline bitfld.long 0x0 16. "ECX,Transfer cancelled" "0: No cancelled transfers.,1: The last recorded entry was a cancelled transfer.." bitfld.long 0x0 15. "GPE,Group priority error" "0: No group priority error,1: The last recorded error was a configuration.." newline bitfld.long 0x0 14. "CPE,Channel priority error" "0: No channel priority error,1: The last recorded error was a configuration.." hexmask.long.byte 0x0 8.--13. 1. "ERRCHN,Error channel number or cancelled channel number GPE or last recorded error cancelled transfer." newline bitfld.long 0x0 7. "SAE,Source address error" "0: No source address configuration error.,1: The last recorded error was a configuration.." bitfld.long 0x0 6. "SOE,Source offset error" "0: No source offset configuration error,1: The last recorded error was a configuration.." newline bitfld.long 0x0 5. "DAE,Destination address error" "0: No destination address configuration error,1: The last recorded error was a configuration.." bitfld.long 0x0 4. "DOE,Destination offset error" "0: No destination offset configuration error,1: The last recorded error was a configuration.." newline bitfld.long 0x0 3. "NCE,NBYTES/CITER configuration error" "0: No NBYTES/CITER configuration error,1: The last recorded error was a configuration.." bitfld.long 0x0 2. "SGE,Scatter/gather configuration error" "0: No scatter/gather configuration error,1: The last recorded error was a configuration.." newline bitfld.long 0x0 1. "SBE,Source bus error" "0: No source bus error,1: The last recorded error was a bus error on a.." bitfld.long 0x0 0. "DBE,Destination bus error" "0: No destination bus error,1: The last recorded error was a bus error on a.." group.long 0xC++0x3 line.long 0x0 "ERQL,Enable Request Register Low" bitfld.long 0x0 31. "ERQ31,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 30. "ERQ30,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 29. "ERQ29,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 28. "ERQ28,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 27. "ERQ27,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 26. "ERQ26,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 25. "ERQ25,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 24. "ERQ24,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 23. "ERQ23,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 22. "ERQ22,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 21. "ERQ21,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 20. "ERQ20,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 19. "ERQ19,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 18. "ERQ18,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 17. "ERQ17,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 16. "ERQ16,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 15. "ERQ15,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 14. "ERQ14,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 13. "ERQ13,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 12. "ERQ12,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 11. "ERQ11,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 10. "ERQ10,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 9. "ERQ9,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 8. "ERQ8,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 7. "ERQ7,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 6. "ERQ6,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 5. "ERQ5,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 4. "ERQ4,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 3. "ERQ3,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 2. "ERQ2,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 1. "ERQ1,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 0. "ERQ0,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." group.long 0x14++0x3 line.long 0x0 "EEIL,Enable Error Interrupt Register Low" bitfld.long 0x0 31. "EEI31,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 30. "EEI30,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 29. "EEI29,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 28. "EEI28,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 27. "EEI27,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 26. "EEI26,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 25. "EEI25,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 24. "EEI24,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 23. "EEI23,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 22. "EEI22,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 21. "EEI21,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 20. "EEI20,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 19. "EEI19,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 18. "EEI18,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 17. "EEI17,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 16. "EEI16,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 15. "EEI15,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 14. "EEI14,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 13. "EEI13,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 12. "EEI12,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 11. "EEI11,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 10. "EEI10,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 9. "EEI9,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 8. "EEI8,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 7. "EEI7,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 6. "EEI6,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 5. "EEI5,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 4. "EEI4,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 3. "EEI3,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 2. "EEI2,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 1. "EEI1,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 0. "EEI0,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." wgroup.byte 0x18++0x7 line.byte 0x0 "CEEI,Clear Enable Error Interrupt Register" bitfld.byte 0x0 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x0 6. "CAEE,Clear all enable error interrupts" "0: Clear only those EEI bits specified in the CEEI..,1: Clear all bits in EEI" newline hexmask.byte 0x0 0.--5. 1. "CEEI,Clear enable error interrupt" line.byte 0x1 "SEEI,Set Enable Error Interrupt Register" bitfld.byte 0x1 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x1 6. "SAEE,Sets all enable error interrupts" "0: Set only those EEI bits specified in the SEEI..,1: Sets all bits in EEI." newline hexmask.byte 0x1 0.--5. 1. "SEEI,Set enable error interrupt" line.byte 0x2 "CERQ,Clear Enable Request Register" bitfld.byte 0x2 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x2 6. "CAER,Clear all enable requests" "0: Clear only those ERQ bits specified in the CERQ..,1: Clear all bits in ERQ" newline hexmask.byte 0x2 0.--5. 1. "CERQ,Clear enable request" line.byte 0x3 "SERQ,Set Enable Request Register" bitfld.byte 0x3 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x3 6. "SAER,Set all enable requests" "0: Set only those ERQ bits specified in the SERQ..,1: Set all bits in ERQ{H L}" newline hexmask.byte 0x3 0.--5. 1. "SERQ,Set enable request" line.byte 0x4 "CDNE,Clear DONE Status Bit Register" bitfld.byte 0x4 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x4 6. "CADN,Clears all DONE bits" "0: Clears only those TCDn_CSR[DONE] bits specified..,1: Clears all bits in TCDn_CSR[DONE]" newline hexmask.byte 0x4 0.--5. 1. "CDNE,Clear DONE bit" line.byte 0x5 "SSRT,Set START Bit Register" bitfld.byte 0x5 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x5 6. "SAST,Set all START bits (activates all channels)" "0: Set only those TCDn_CSR[START] bits specified in..,1: Set all bits in TCDn_CSR[START]" newline hexmask.byte 0x5 0.--5. 1. "SSRT,Set START bit" line.byte 0x6 "CERR,Clear Error Register" bitfld.byte 0x6 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x6 6. "CAEI,Clear all error indicators" "0: Clear only those ERR bits specified in the CERR..,1: Clear all bits in ERR" newline hexmask.byte 0x6 0.--5. 1. "CERR,Clear error indicator" line.byte 0x7 "CINT,Clear Interrupt Request Register" bitfld.byte 0x7 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x7 6. "CAIR,Clear all interrupt requests" "0: Clear only those INT bits specified in the CINT..,1: Clear all bits in INT{H L}" newline hexmask.byte 0x7 0.--5. 1. "CINT,Clear interrupt request" group.long 0x24++0x3 line.long 0x0 "INTL,Interrupt Request Register Low" bitfld.long 0x0 31. "INT31,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 30. "INT30,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 29. "INT29,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 28. "INT28,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 27. "INT27,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 26. "INT26,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 25. "INT25,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 24. "INT24,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 23. "INT23,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 22. "INT22,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 21. "INT21,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 20. "INT20,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 19. "INT19,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 18. "INT18,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 17. "INT17,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 16. "INT16,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 15. "INT15,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 14. "INT14,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 13. "INT13,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 12. "INT12,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 11. "INT11,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 10. "INT10,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 9. "INT9,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 8. "INT8,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 7. "INT7,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 6. "INT6,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 5. "INT5,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 4. "INT4,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 3. "INT3,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 2. "INT2,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 1. "INT1,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 0. "INT0,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." group.long 0x2C++0x3 line.long 0x0 "ERRL,Error Register Low" bitfld.long 0x0 31. "ERR31,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 30. "ERR30,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 29. "ERR29,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 28. "ERR28,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 27. "ERR27,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 26. "ERR26,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 25. "ERR25,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 24. "ERR24,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 23. "ERR23,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 22. "ERR22,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 21. "ERR21,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 20. "ERR20,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 19. "ERR19,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 18. "ERR18,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 17. "ERR17,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 16. "ERR16,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 15. "ERR15,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 14. "ERR14,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 13. "ERR13,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 12. "ERR12,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 11. "ERR11,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 10. "ERR10,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 9. "ERR9,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 8. "ERR8,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 7. "ERR7,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 6. "ERR6,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 5. "ERR5,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 4. "ERR4,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 3. "ERR3,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 2. "ERR2,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 1. "ERR1,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 0. "ERR0,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." group.long 0x34++0x3 line.long 0x0 "HRSL,Hardware Request Status Register Low" bitfld.long 0x0 31. "HRS31,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 30. "HRS30,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 29. "HRS29,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 28. "HRS28,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 27. "HRS27,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 26. "HRS26,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 25. "HRS25,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 24. "HRS24,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 23. "HRS23,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 22. "HRS22,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 21. "HRS21,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 20. "HRS20,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 19. "HRS19,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 18. "HRS18,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 17. "HRS17,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 16. "HRS16,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 15. "HRS15,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 14. "HRS14,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 13. "HRS13,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 12. "HRS12,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 11. "HRS11,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 10. "HRS10,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 9. "HRS9,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 8. "HRS8,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 7. "HRS7,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 6. "HRS6,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 5. "HRS5,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 4. "HRS4,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 3. "HRS3,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 2. "HRS2,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 1. "HRS1,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 0. "HRS0,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." group.byte 0x100++0x1F line.byte 0x0 "DCHPRI3,Channel n Priority register" bitfld.byte 0x0 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x0 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x0 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x0 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1 "DCHPRI2,Channel n Priority register" bitfld.byte 0x1 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x2 "DCHPRI1,Channel n Priority register" bitfld.byte 0x2 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x2 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x2 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x2 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x3 "DCHPRI0,Channel n Priority register" bitfld.byte 0x3 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x3 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x3 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x3 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x4 "DCHPRI7,Channel n Priority register" bitfld.byte 0x4 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x4 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x4 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x4 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x5 "DCHPRI6,Channel n Priority register" bitfld.byte 0x5 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x5 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x5 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x5 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x6 "DCHPRI5,Channel n Priority register" bitfld.byte 0x6 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x6 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x6 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x6 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x7 "DCHPRI4,Channel n Priority register" bitfld.byte 0x7 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x7 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x7 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x7 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x8 "DCHPRI11,Channel n Priority register" bitfld.byte 0x8 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x8 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x8 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x8 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x9 "DCHPRI10,Channel n Priority register" bitfld.byte 0x9 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x9 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x9 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x9 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xA "DCHPRI9,Channel n Priority register" bitfld.byte 0xA 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xA 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xA 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xA 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xB "DCHPRI8,Channel n Priority register" bitfld.byte 0xB 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xB 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xB 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xB 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xC "DCHPRI15,Channel n Priority register" bitfld.byte 0xC 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xC 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xC 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xC 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xD "DCHPRI14,Channel n Priority register" bitfld.byte 0xD 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xD 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xD 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xD 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xE "DCHPRI13,Channel n Priority register" bitfld.byte 0xE 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xE 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xE 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xE 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xF "DCHPRI12,Channel n Priority register" bitfld.byte 0xF 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xF 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xF 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xF 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x10 "DCHPRI19,Channel n Priority register" bitfld.byte 0x10 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x10 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x10 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x10 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x11 "DCHPRI18,Channel n Priority register" bitfld.byte 0x11 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x11 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x11 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x11 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x12 "DCHPRI17,Channel n Priority register" bitfld.byte 0x12 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x12 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x12 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x12 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x13 "DCHPRI16,Channel n Priority register" bitfld.byte 0x13 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x13 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x13 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x13 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x14 "DCHPRI23,Channel n Priority register" bitfld.byte 0x14 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x14 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x14 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x14 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x15 "DCHPRI22,Channel n Priority register" bitfld.byte 0x15 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x15 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x15 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x15 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x16 "DCHPRI21,Channel n Priority register" bitfld.byte 0x16 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x16 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x16 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x16 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x17 "DCHPRI20,Channel n Priority register" bitfld.byte 0x17 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x17 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x17 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x17 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x18 "DCHPRI27,Channel n Priority register" bitfld.byte 0x18 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x18 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x18 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x18 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x19 "DCHPRI26,Channel n Priority register" bitfld.byte 0x19 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x19 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x19 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x19 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1A "DCHPRI25,Channel n Priority register" bitfld.byte 0x1A 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1A 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1A 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1A 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1B "DCHPRI24,Channel n Priority register" bitfld.byte 0x1B 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1B 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1B 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1B 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1C "DCHPRI31,Channel n Priority register" bitfld.byte 0x1C 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1C 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1C 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1C 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1D "DCHPRI30,Channel n Priority register" bitfld.byte 0x1D 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1D 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1D 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1D 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1E "DCHPRI29,Channel n Priority register" bitfld.byte 0x1E 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1E 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1E 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1E 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1F "DCHPRI28,Channel n Priority register" bitfld.byte 0x1F 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1F 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1F 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1F 0.--3. 1. "CHPRI,Channel n arbitration priority" group.byte 0x140++0x1F line.byte 0x0 "REQSTR_ID0,Channel 0 Requester ID register" bitfld.byte 0x0 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x0 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x0 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x1 "REQSTR_ID1,Channel 1 Requester ID register" bitfld.byte 0x1 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x1 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x1 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x2 "REQSTR_ID2,Channel 2 Requester ID register" bitfld.byte 0x2 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x2 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x2 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x3 "REQSTR_ID3,Channel 3 Requester ID register" bitfld.byte 0x3 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x3 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x3 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x4 "REQSTR_ID4,Channel 4 Requester ID register" bitfld.byte 0x4 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x4 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x4 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x5 "REQSTR_ID5,Channel 5 Requester ID register" bitfld.byte 0x5 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x5 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x5 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x6 "REQSTR_ID6,Channel 6 Requester ID register" bitfld.byte 0x6 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x6 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x6 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x7 "REQSTR_ID7,Channel 7 Requester ID register" bitfld.byte 0x7 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x7 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x7 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x8 "REQSTR_ID8,Channel 8 Requester ID register" bitfld.byte 0x8 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x8 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x8 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x9 "REQSTR_ID9,Channel 9 Requester ID register" bitfld.byte 0x9 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x9 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x9 0.--5. 1. "REQ_ID,Requester ID" line.byte 0xA "REQSTR_ID10,Channel 10 Requester ID register" bitfld.byte 0xA 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0xA 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0xA 0.--5. 1. "REQ_ID,Requester ID" line.byte 0xB "REQSTR_ID11,Channel 11 Requester ID register" bitfld.byte 0xB 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0xB 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0xB 0.--5. 1. "REQ_ID,Requester ID" line.byte 0xC "REQSTR_ID12,Channel 12 Requester ID register" bitfld.byte 0xC 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0xC 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0xC 0.--5. 1. "REQ_ID,Requester ID" line.byte 0xD "REQSTR_ID13,Channel 13 Requester ID register" bitfld.byte 0xD 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0xD 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0xD 0.--5. 1. "REQ_ID,Requester ID" line.byte 0xE "REQSTR_ID14,Channel 14 Requester ID register" bitfld.byte 0xE 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0xE 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0xE 0.--5. 1. "REQ_ID,Requester ID" line.byte 0xF "REQSTR_ID15,Channel 15 Requester ID register" bitfld.byte 0xF 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0xF 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0xF 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x10 "REQSTR_ID16,Channel 16 Requester ID register" bitfld.byte 0x10 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x10 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x10 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x11 "REQSTR_ID17,Channel 17 Requester ID register" bitfld.byte 0x11 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x11 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x11 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x12 "REQSTR_ID18,Channel 18 Requester ID register" bitfld.byte 0x12 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x12 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x12 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x13 "REQSTR_ID19,Channel 19 Requester ID register" bitfld.byte 0x13 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x13 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x13 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x14 "REQSTR_ID20,Channel 20 Requester ID register" bitfld.byte 0x14 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x14 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x14 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x15 "REQSTR_ID21,Channel 21 Requester ID register" bitfld.byte 0x15 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x15 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x15 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x16 "REQSTR_ID22,Channel 22 Requester ID register" bitfld.byte 0x16 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x16 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x16 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x17 "REQSTR_ID23,Channel 23 Requester ID register" bitfld.byte 0x17 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x17 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x17 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x18 "REQSTR_ID24,Channel 24 Requester ID register" bitfld.byte 0x18 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x18 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x18 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x19 "REQSTR_ID25,Channel 25 Requester ID register" bitfld.byte 0x19 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x19 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x19 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x1A "REQSTR_ID26,Channel 26 Requester ID register" bitfld.byte 0x1A 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x1A 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x1A 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x1B "REQSTR_ID27,Channel 27 Requester ID register" bitfld.byte 0x1B 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x1B 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x1B 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x1C "REQSTR_ID28,Channel 28 Requester ID register" bitfld.byte 0x1C 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x1C 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x1C 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x1D "REQSTR_ID29,Channel 29 Requester ID register" bitfld.byte 0x1D 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x1D 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x1D 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x1E "REQSTR_ID30,Channel 30 Requester ID register" bitfld.byte 0x1E 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x1E 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x1E 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x1F "REQSTR_ID31,Channel 31 Requester ID register" bitfld.byte 0x1F 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x1F 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x1F 0.--5. 1. "REQ_ID,Requester ID" group.long 0x180++0x7 line.long 0x0 "VMID0,Channel 0 to 15 VMID Register" bitfld.long 0x0 8. "VMID_EN,VMID_0 Enable" "0: 8-bit VMID value out disabled.,1: 8-bit VMID value out enabled." hexmask.long.byte 0x0 0.--7. 1. "VMID,VMID_0 value" line.long 0x4 "VMID1,Channel 16 to 31 VMID Register" bitfld.long 0x4 8. "VMID_EN,VMID_1 Enable" "0: 8-bit VMID value out disabled.,1: 8-bit VMID value out enabled." hexmask.long.byte 0x4 0.--7. 1. "VMID,VMID_1 value" group.long 0x190++0x3 line.long 0x0 "VMID_ERR_STATUS,Channel VMID Error Status register" bitfld.long 0x0 0. "VMID_ERR,VMID error" "0: No Non-Hypervisor Access to eDMA_VMID_n register,1: Transfer Error for Non-Hypervisor Access to.." group.long 0x1000++0x3 line.long 0x0 "TCD0_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1004++0x3 line.word 0x0 "TCD0_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD0_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1008++0x3 line.long 0x0 "TCD0_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1008++0x3 line.long 0x0 "TCD0_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1008++0xB line.long 0x0 "TCD0_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD0_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD0_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1014++0x3 line.word 0x0 "TCD0_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1016++0x1 line.word 0x0 "TCD0_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1018++0x3 line.long 0x0 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x101C++0x3 line.word 0x0 "TCD0_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD0_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x101E++0x1 line.word 0x0 "TCD0_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1020++0x3 line.long 0x0 "TCD1_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1024++0x3 line.word 0x0 "TCD1_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD1_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1028++0x3 line.long 0x0 "TCD1_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1028++0x3 line.long 0x0 "TCD1_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1028++0xB line.long 0x0 "TCD1_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD1_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD1_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1034++0x3 line.word 0x0 "TCD1_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1036++0x1 line.word 0x0 "TCD1_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1038++0x3 line.long 0x0 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x103C++0x3 line.word 0x0 "TCD1_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD1_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x103E++0x1 line.word 0x0 "TCD1_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1040++0x3 line.long 0x0 "TCD2_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1044++0x3 line.word 0x0 "TCD2_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD2_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1048++0x3 line.long 0x0 "TCD2_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1048++0x3 line.long 0x0 "TCD2_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1048++0xB line.long 0x0 "TCD2_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD2_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD2_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1054++0x3 line.word 0x0 "TCD2_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1056++0x1 line.word 0x0 "TCD2_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1058++0x3 line.long 0x0 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x105C++0x3 line.word 0x0 "TCD2_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD2_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x105E++0x1 line.word 0x0 "TCD2_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1060++0x3 line.long 0x0 "TCD3_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1064++0x3 line.word 0x0 "TCD3_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD3_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1068++0x3 line.long 0x0 "TCD3_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1068++0x3 line.long 0x0 "TCD3_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1068++0xB line.long 0x0 "TCD3_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD3_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD3_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1074++0x3 line.word 0x0 "TCD3_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1076++0x1 line.word 0x0 "TCD3_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1078++0x3 line.long 0x0 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x107C++0x3 line.word 0x0 "TCD3_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD3_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x107E++0x1 line.word 0x0 "TCD3_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1080++0x3 line.long 0x0 "TCD4_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1084++0x3 line.word 0x0 "TCD4_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD4_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1088++0x3 line.long 0x0 "TCD4_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1088++0x3 line.long 0x0 "TCD4_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1088++0xB line.long 0x0 "TCD4_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD4_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD4_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1094++0x3 line.word 0x0 "TCD4_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD4_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1096++0x1 line.word 0x0 "TCD4_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1098++0x3 line.long 0x0 "TCD4_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x109C++0x3 line.word 0x0 "TCD4_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD4_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x109E++0x1 line.word 0x0 "TCD4_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x10A0++0x3 line.long 0x0 "TCD5_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x10A4++0x3 line.word 0x0 "TCD5_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD5_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x10A8++0x3 line.long 0x0 "TCD5_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x10A8++0x3 line.long 0x0 "TCD5_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x10A8++0xB line.long 0x0 "TCD5_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD5_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD5_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x10B4++0x3 line.word 0x0 "TCD5_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD5_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x10B6++0x1 line.word 0x0 "TCD5_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x10B8++0x3 line.long 0x0 "TCD5_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x10BC++0x3 line.word 0x0 "TCD5_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD5_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x10BE++0x1 line.word 0x0 "TCD5_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x10C0++0x3 line.long 0x0 "TCD6_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x10C4++0x3 line.word 0x0 "TCD6_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD6_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x10C8++0x3 line.long 0x0 "TCD6_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x10C8++0x3 line.long 0x0 "TCD6_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x10C8++0xB line.long 0x0 "TCD6_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD6_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD6_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x10D4++0x3 line.word 0x0 "TCD6_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD6_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x10D6++0x1 line.word 0x0 "TCD6_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x10D8++0x3 line.long 0x0 "TCD6_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x10DC++0x3 line.word 0x0 "TCD6_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD6_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x10DE++0x1 line.word 0x0 "TCD6_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x10E0++0x3 line.long 0x0 "TCD7_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x10E4++0x3 line.word 0x0 "TCD7_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD7_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x10E8++0x3 line.long 0x0 "TCD7_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x10E8++0x3 line.long 0x0 "TCD7_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x10E8++0xB line.long 0x0 "TCD7_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD7_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD7_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x10F4++0x3 line.word 0x0 "TCD7_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD7_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x10F6++0x1 line.word 0x0 "TCD7_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x10F8++0x3 line.long 0x0 "TCD7_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x10FC++0x3 line.word 0x0 "TCD7_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD7_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x10FE++0x1 line.word 0x0 "TCD7_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1100++0x3 line.long 0x0 "TCD8_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1104++0x3 line.word 0x0 "TCD8_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD8_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1108++0x3 line.long 0x0 "TCD8_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1108++0x3 line.long 0x0 "TCD8_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1108++0xB line.long 0x0 "TCD8_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD8_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD8_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1114++0x3 line.word 0x0 "TCD8_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD8_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1116++0x1 line.word 0x0 "TCD8_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1118++0x3 line.long 0x0 "TCD8_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x111C++0x3 line.word 0x0 "TCD8_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD8_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x111E++0x1 line.word 0x0 "TCD8_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1120++0x3 line.long 0x0 "TCD9_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1124++0x3 line.word 0x0 "TCD9_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD9_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1128++0x3 line.long 0x0 "TCD9_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1128++0x3 line.long 0x0 "TCD9_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1128++0xB line.long 0x0 "TCD9_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD9_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD9_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1134++0x3 line.word 0x0 "TCD9_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD9_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1136++0x1 line.word 0x0 "TCD9_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1138++0x3 line.long 0x0 "TCD9_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x113C++0x3 line.word 0x0 "TCD9_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD9_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x113E++0x1 line.word 0x0 "TCD9_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1140++0x3 line.long 0x0 "TCD10_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1144++0x3 line.word 0x0 "TCD10_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD10_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1148++0x3 line.long 0x0 "TCD10_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1148++0x3 line.long 0x0 "TCD10_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1148++0xB line.long 0x0 "TCD10_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD10_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD10_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1154++0x3 line.word 0x0 "TCD10_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD10_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1156++0x1 line.word 0x0 "TCD10_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1158++0x3 line.long 0x0 "TCD10_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x115C++0x3 line.word 0x0 "TCD10_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD10_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x115E++0x1 line.word 0x0 "TCD10_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1160++0x3 line.long 0x0 "TCD11_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1164++0x3 line.word 0x0 "TCD11_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD11_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1168++0x3 line.long 0x0 "TCD11_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1168++0x3 line.long 0x0 "TCD11_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1168++0xB line.long 0x0 "TCD11_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD11_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD11_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1174++0x3 line.word 0x0 "TCD11_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD11_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1176++0x1 line.word 0x0 "TCD11_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1178++0x3 line.long 0x0 "TCD11_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x117C++0x3 line.word 0x0 "TCD11_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD11_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x117E++0x1 line.word 0x0 "TCD11_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1180++0x3 line.long 0x0 "TCD12_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1184++0x3 line.word 0x0 "TCD12_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD12_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1188++0x3 line.long 0x0 "TCD12_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1188++0x3 line.long 0x0 "TCD12_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1188++0xB line.long 0x0 "TCD12_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD12_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD12_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1194++0x3 line.word 0x0 "TCD12_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD12_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1196++0x1 line.word 0x0 "TCD12_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1198++0x3 line.long 0x0 "TCD12_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x119C++0x3 line.word 0x0 "TCD12_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD12_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x119E++0x1 line.word 0x0 "TCD12_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x11A0++0x3 line.long 0x0 "TCD13_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x11A4++0x3 line.word 0x0 "TCD13_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD13_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x11A8++0x3 line.long 0x0 "TCD13_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x11A8++0x3 line.long 0x0 "TCD13_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x11A8++0xB line.long 0x0 "TCD13_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD13_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD13_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x11B4++0x3 line.word 0x0 "TCD13_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD13_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x11B6++0x1 line.word 0x0 "TCD13_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x11B8++0x3 line.long 0x0 "TCD13_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x11BC++0x3 line.word 0x0 "TCD13_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD13_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x11BE++0x1 line.word 0x0 "TCD13_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x11C0++0x3 line.long 0x0 "TCD14_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x11C4++0x3 line.word 0x0 "TCD14_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD14_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x11C8++0x3 line.long 0x0 "TCD14_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x11C8++0x3 line.long 0x0 "TCD14_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x11C8++0xB line.long 0x0 "TCD14_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD14_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD14_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x11D4++0x3 line.word 0x0 "TCD14_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD14_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x11D6++0x1 line.word 0x0 "TCD14_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x11D8++0x3 line.long 0x0 "TCD14_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x11DC++0x3 line.word 0x0 "TCD14_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD14_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x11DE++0x1 line.word 0x0 "TCD14_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x11E0++0x3 line.long 0x0 "TCD15_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x11E4++0x3 line.word 0x0 "TCD15_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD15_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x11E8++0x3 line.long 0x0 "TCD15_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x11E8++0x3 line.long 0x0 "TCD15_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x11E8++0xB line.long 0x0 "TCD15_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD15_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD15_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x11F4++0x3 line.word 0x0 "TCD15_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD15_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x11F6++0x1 line.word 0x0 "TCD15_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x11F8++0x3 line.long 0x0 "TCD15_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x11FC++0x3 line.word 0x0 "TCD15_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD15_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x11FE++0x1 line.word 0x0 "TCD15_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1200++0x3 line.long 0x0 "TCD16_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1204++0x3 line.word 0x0 "TCD16_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD16_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1208++0x3 line.long 0x0 "TCD16_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1208++0x3 line.long 0x0 "TCD16_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1208++0xB line.long 0x0 "TCD16_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD16_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD16_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1214++0x3 line.word 0x0 "TCD16_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD16_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1216++0x1 line.word 0x0 "TCD16_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1218++0x3 line.long 0x0 "TCD16_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x121C++0x3 line.word 0x0 "TCD16_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD16_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x121E++0x1 line.word 0x0 "TCD16_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1220++0x3 line.long 0x0 "TCD17_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1224++0x3 line.word 0x0 "TCD17_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD17_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1228++0x3 line.long 0x0 "TCD17_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1228++0x3 line.long 0x0 "TCD17_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1228++0xB line.long 0x0 "TCD17_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD17_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD17_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1234++0x3 line.word 0x0 "TCD17_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD17_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1236++0x1 line.word 0x0 "TCD17_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1238++0x3 line.long 0x0 "TCD17_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x123C++0x3 line.word 0x0 "TCD17_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD17_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x123E++0x1 line.word 0x0 "TCD17_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1240++0x3 line.long 0x0 "TCD18_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1244++0x3 line.word 0x0 "TCD18_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD18_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1248++0x3 line.long 0x0 "TCD18_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1248++0x3 line.long 0x0 "TCD18_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1248++0xB line.long 0x0 "TCD18_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD18_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD18_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1254++0x3 line.word 0x0 "TCD18_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD18_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1256++0x1 line.word 0x0 "TCD18_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1258++0x3 line.long 0x0 "TCD18_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x125C++0x3 line.word 0x0 "TCD18_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD18_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x125E++0x1 line.word 0x0 "TCD18_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1260++0x3 line.long 0x0 "TCD19_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1264++0x3 line.word 0x0 "TCD19_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD19_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1268++0x3 line.long 0x0 "TCD19_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1268++0x3 line.long 0x0 "TCD19_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1268++0xB line.long 0x0 "TCD19_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD19_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD19_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1274++0x3 line.word 0x0 "TCD19_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD19_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1276++0x1 line.word 0x0 "TCD19_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1278++0x3 line.long 0x0 "TCD19_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x127C++0x3 line.word 0x0 "TCD19_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD19_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x127E++0x1 line.word 0x0 "TCD19_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1280++0x3 line.long 0x0 "TCD20_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1284++0x3 line.word 0x0 "TCD20_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD20_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1288++0x3 line.long 0x0 "TCD20_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1288++0x3 line.long 0x0 "TCD20_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1288++0xB line.long 0x0 "TCD20_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD20_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD20_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1294++0x3 line.word 0x0 "TCD20_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD20_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1296++0x1 line.word 0x0 "TCD20_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1298++0x3 line.long 0x0 "TCD20_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x129C++0x3 line.word 0x0 "TCD20_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD20_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x129E++0x1 line.word 0x0 "TCD20_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x12A0++0x3 line.long 0x0 "TCD21_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x12A4++0x3 line.word 0x0 "TCD21_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD21_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x12A8++0x3 line.long 0x0 "TCD21_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x12A8++0x3 line.long 0x0 "TCD21_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x12A8++0xB line.long 0x0 "TCD21_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD21_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD21_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x12B4++0x3 line.word 0x0 "TCD21_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD21_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x12B6++0x1 line.word 0x0 "TCD21_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x12B8++0x3 line.long 0x0 "TCD21_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x12BC++0x3 line.word 0x0 "TCD21_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD21_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x12BE++0x1 line.word 0x0 "TCD21_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x12C0++0x3 line.long 0x0 "TCD22_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x12C4++0x3 line.word 0x0 "TCD22_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD22_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x12C8++0x3 line.long 0x0 "TCD22_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x12C8++0x3 line.long 0x0 "TCD22_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x12C8++0xB line.long 0x0 "TCD22_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD22_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD22_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x12D4++0x3 line.word 0x0 "TCD22_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD22_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x12D6++0x1 line.word 0x0 "TCD22_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x12D8++0x3 line.long 0x0 "TCD22_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x12DC++0x3 line.word 0x0 "TCD22_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD22_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x12DE++0x1 line.word 0x0 "TCD22_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x12E0++0x3 line.long 0x0 "TCD23_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x12E4++0x3 line.word 0x0 "TCD23_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD23_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x12E8++0x3 line.long 0x0 "TCD23_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x12E8++0x3 line.long 0x0 "TCD23_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x12E8++0xB line.long 0x0 "TCD23_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD23_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD23_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x12F4++0x3 line.word 0x0 "TCD23_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD23_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x12F6++0x1 line.word 0x0 "TCD23_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x12F8++0x3 line.long 0x0 "TCD23_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x12FC++0x3 line.word 0x0 "TCD23_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD23_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x12FE++0x1 line.word 0x0 "TCD23_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1300++0x3 line.long 0x0 "TCD24_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1304++0x3 line.word 0x0 "TCD24_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD24_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1308++0x3 line.long 0x0 "TCD24_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1308++0x3 line.long 0x0 "TCD24_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1308++0xB line.long 0x0 "TCD24_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD24_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD24_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1314++0x3 line.word 0x0 "TCD24_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD24_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1316++0x1 line.word 0x0 "TCD24_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1318++0x3 line.long 0x0 "TCD24_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x131C++0x3 line.word 0x0 "TCD24_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD24_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x131E++0x1 line.word 0x0 "TCD24_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1320++0x3 line.long 0x0 "TCD25_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1324++0x3 line.word 0x0 "TCD25_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD25_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1328++0x3 line.long 0x0 "TCD25_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1328++0x3 line.long 0x0 "TCD25_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1328++0xB line.long 0x0 "TCD25_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD25_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD25_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1334++0x3 line.word 0x0 "TCD25_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD25_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1336++0x1 line.word 0x0 "TCD25_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1338++0x3 line.long 0x0 "TCD25_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x133C++0x3 line.word 0x0 "TCD25_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD25_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x133E++0x1 line.word 0x0 "TCD25_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1340++0x3 line.long 0x0 "TCD26_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1344++0x3 line.word 0x0 "TCD26_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD26_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1348++0x3 line.long 0x0 "TCD26_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1348++0x3 line.long 0x0 "TCD26_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1348++0xB line.long 0x0 "TCD26_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD26_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD26_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1354++0x3 line.word 0x0 "TCD26_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD26_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1356++0x1 line.word 0x0 "TCD26_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1358++0x3 line.long 0x0 "TCD26_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x135C++0x3 line.word 0x0 "TCD26_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD26_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x135E++0x1 line.word 0x0 "TCD26_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1360++0x3 line.long 0x0 "TCD27_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1364++0x3 line.word 0x0 "TCD27_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD27_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1368++0x3 line.long 0x0 "TCD27_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1368++0x3 line.long 0x0 "TCD27_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1368++0xB line.long 0x0 "TCD27_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD27_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD27_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1374++0x3 line.word 0x0 "TCD27_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD27_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1376++0x1 line.word 0x0 "TCD27_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1378++0x3 line.long 0x0 "TCD27_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x137C++0x3 line.word 0x0 "TCD27_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD27_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x137E++0x1 line.word 0x0 "TCD27_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1380++0x3 line.long 0x0 "TCD28_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1384++0x3 line.word 0x0 "TCD28_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD28_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1388++0x3 line.long 0x0 "TCD28_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1388++0x3 line.long 0x0 "TCD28_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1388++0xB line.long 0x0 "TCD28_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD28_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD28_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1394++0x3 line.word 0x0 "TCD28_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD28_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1396++0x1 line.word 0x0 "TCD28_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1398++0x3 line.long 0x0 "TCD28_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x139C++0x3 line.word 0x0 "TCD28_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD28_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x139E++0x1 line.word 0x0 "TCD28_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x13A0++0x3 line.long 0x0 "TCD29_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x13A4++0x3 line.word 0x0 "TCD29_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD29_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x13A8++0x3 line.long 0x0 "TCD29_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x13A8++0x3 line.long 0x0 "TCD29_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x13A8++0xB line.long 0x0 "TCD29_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD29_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD29_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x13B4++0x3 line.word 0x0 "TCD29_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD29_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x13B6++0x1 line.word 0x0 "TCD29_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x13B8++0x3 line.long 0x0 "TCD29_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x13BC++0x3 line.word 0x0 "TCD29_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD29_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x13BE++0x1 line.word 0x0 "TCD29_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x13C0++0x3 line.long 0x0 "TCD30_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x13C4++0x3 line.word 0x0 "TCD30_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD30_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x13C8++0x3 line.long 0x0 "TCD30_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x13C8++0x3 line.long 0x0 "TCD30_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x13C8++0xB line.long 0x0 "TCD30_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD30_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD30_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x13D4++0x3 line.word 0x0 "TCD30_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD30_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x13D6++0x1 line.word 0x0 "TCD30_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x13D8++0x3 line.long 0x0 "TCD30_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x13DC++0x3 line.word 0x0 "TCD30_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD30_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x13DE++0x1 line.word 0x0 "TCD30_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x13E0++0x3 line.long 0x0 "TCD31_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x13E4++0x3 line.word 0x0 "TCD31_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD31_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x13E8++0x3 line.long 0x0 "TCD31_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x13E8++0x3 line.long 0x0 "TCD31_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x13E8++0xB line.long 0x0 "TCD31_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD31_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD31_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x13F4++0x3 line.word 0x0 "TCD31_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD31_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x13F6++0x1 line.word 0x0 "TCD31_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x13F8++0x3 line.long 0x0 "TCD31_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x13FC++0x3 line.word 0x0 "TCD31_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD31_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x13FE++0x1 line.word 0x0 "TCD31_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" tree.end tree "EDMA_2" base ad:0x703D0000 group.long 0x0++0x3 line.long 0x0 "CR,Control Register" bitfld.long 0x0 17. "CX,Cancel transfer" "0: Normal operation,1: Cancel the remaining data transfer. Stop the.." bitfld.long 0x0 16. "ECX,Error cancel transfer" "0: Normal operation,1: Cancel the remaining data transfer in the same.." newline bitfld.long 0x0 10. "GRP1PRI,Channel group 1 priority" "0,1" bitfld.long 0x0 8. "GRP0PRI,Channel group 0 priority" "0,1" newline bitfld.long 0x0 7. "EMLM,Enable minor loop mapping" "0: Disabled. TCDn.word2 is defined as a 32-bit..,1: Enabled. TCDn.word2 is redefined to include.." bitfld.long 0x0 6. "CLM,Continuous Link mode" "0: A minor loop channel link made to itself goes..,1: A minor loop channel link made to itself does.." newline bitfld.long 0x0 5. "HALT,Halt DMA operations" "0: Normal operation,1: Stall the start of any new channels. Executing.." bitfld.long 0x0 4. "HOE,Halt on error" "0: Normal operation,1: Any error causes the HALT bit to set." newline bitfld.long 0x0 3. "ERGA,Enable round-robin group arbitration" "0: Fixed-priority arbitration is used for selection..,1: Round-robin arbitration is used for selection.." bitfld.long 0x0 2. "ERCA,Enable round-robin channel arbitration" "0: Fixed-priority arbitration is used for channel..,1: Round-robin arbitration is used for channel.." newline bitfld.long 0x0 1. "EDBG,Enable debug" "0: When in Debug mode the DMA continues to operate.,1: When in Debug mode the DMA stalls the start of a.." bitfld.long 0x0 0. "EBW,Enable Buffered Writes" "0: The bufferable write signal (hprot[2]) is not..,1: The bufferable write signal (hprot[2]) is.." rgroup.long 0x4++0x3 line.long 0x0 "ES,Error Status Register" bitfld.long 0x0 31. "VLD,ERRH and ERRL status bits" "0: No ERR bits are set.,1: At least one ERR bit is set indicating a valid.." bitfld.long 0x0 17. "UCE,Uncorrectable ECC error" "0: No uncorrectable ECC error,1: The last recorded error was an uncorrectable TCD.." newline bitfld.long 0x0 16. "ECX,Transfer cancelled" "0: No cancelled transfers.,1: The last recorded entry was a cancelled transfer.." bitfld.long 0x0 15. "GPE,Group priority error" "0: No group priority error,1: The last recorded error was a configuration.." newline bitfld.long 0x0 14. "CPE,Channel priority error" "0: No channel priority error,1: The last recorded error was a configuration.." hexmask.long.byte 0x0 8.--13. 1. "ERRCHN,Error channel number or cancelled channel number GPE or last recorded error cancelled transfer." newline bitfld.long 0x0 7. "SAE,Source address error" "0: No source address configuration error.,1: The last recorded error was a configuration.." bitfld.long 0x0 6. "SOE,Source offset error" "0: No source offset configuration error,1: The last recorded error was a configuration.." newline bitfld.long 0x0 5. "DAE,Destination address error" "0: No destination address configuration error,1: The last recorded error was a configuration.." bitfld.long 0x0 4. "DOE,Destination offset error" "0: No destination offset configuration error,1: The last recorded error was a configuration.." newline bitfld.long 0x0 3. "NCE,NBYTES/CITER configuration error" "0: No NBYTES/CITER configuration error,1: The last recorded error was a configuration.." bitfld.long 0x0 2. "SGE,Scatter/gather configuration error" "0: No scatter/gather configuration error,1: The last recorded error was a configuration.." newline bitfld.long 0x0 1. "SBE,Source bus error" "0: No source bus error,1: The last recorded error was a bus error on a.." bitfld.long 0x0 0. "DBE,Destination bus error" "0: No destination bus error,1: The last recorded error was a bus error on a.." group.long 0xC++0x3 line.long 0x0 "ERQL,Enable Request Register Low" bitfld.long 0x0 31. "ERQ31,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 30. "ERQ30,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 29. "ERQ29,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 28. "ERQ28,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 27. "ERQ27,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 26. "ERQ26,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 25. "ERQ25,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 24. "ERQ24,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 23. "ERQ23,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 22. "ERQ22,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 21. "ERQ21,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 20. "ERQ20,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 19. "ERQ19,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 18. "ERQ18,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 17. "ERQ17,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 16. "ERQ16,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 15. "ERQ15,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 14. "ERQ14,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 13. "ERQ13,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 12. "ERQ12,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 11. "ERQ11,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 10. "ERQ10,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 9. "ERQ9,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 8. "ERQ8,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 7. "ERQ7,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 6. "ERQ6,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 5. "ERQ5,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 4. "ERQ4,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 3. "ERQ3,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 2. "ERQ2,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 1. "ERQ1,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 0. "ERQ0,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." group.long 0x14++0x3 line.long 0x0 "EEIL,Enable Error Interrupt Register Low" bitfld.long 0x0 31. "EEI31,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 30. "EEI30,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 29. "EEI29,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 28. "EEI28,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 27. "EEI27,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 26. "EEI26,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 25. "EEI25,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 24. "EEI24,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 23. "EEI23,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 22. "EEI22,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 21. "EEI21,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 20. "EEI20,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 19. "EEI19,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 18. "EEI18,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 17. "EEI17,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 16. "EEI16,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 15. "EEI15,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 14. "EEI14,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 13. "EEI13,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 12. "EEI12,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 11. "EEI11,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 10. "EEI10,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 9. "EEI9,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 8. "EEI8,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 7. "EEI7,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 6. "EEI6,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 5. "EEI5,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 4. "EEI4,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 3. "EEI3,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 2. "EEI2,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x0 1. "EEI1,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x0 0. "EEI0,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." wgroup.byte 0x18++0x7 line.byte 0x0 "CEEI,Clear Enable Error Interrupt Register" bitfld.byte 0x0 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x0 6. "CAEE,Clear all enable error interrupts" "0: Clear only those EEI bits specified in the CEEI..,1: Clear all bits in EEI" newline hexmask.byte 0x0 0.--5. 1. "CEEI,Clear enable error interrupt" line.byte 0x1 "SEEI,Set Enable Error Interrupt Register" bitfld.byte 0x1 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x1 6. "SAEE,Sets all enable error interrupts" "0: Set only those EEI bits specified in the SEEI..,1: Sets all bits in EEI." newline hexmask.byte 0x1 0.--5. 1. "SEEI,Set enable error interrupt" line.byte 0x2 "CERQ,Clear Enable Request Register" bitfld.byte 0x2 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x2 6. "CAER,Clear all enable requests" "0: Clear only those ERQ bits specified in the CERQ..,1: Clear all bits in ERQ" newline hexmask.byte 0x2 0.--5. 1. "CERQ,Clear enable request" line.byte 0x3 "SERQ,Set Enable Request Register" bitfld.byte 0x3 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x3 6. "SAER,Set all enable requests" "0: Set only those ERQ bits specified in the SERQ..,1: Set all bits in ERQ{H L}" newline hexmask.byte 0x3 0.--5. 1. "SERQ,Set enable request" line.byte 0x4 "CDNE,Clear DONE Status Bit Register" bitfld.byte 0x4 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x4 6. "CADN,Clears all DONE bits" "0: Clears only those TCDn_CSR[DONE] bits specified..,1: Clears all bits in TCDn_CSR[DONE]" newline hexmask.byte 0x4 0.--5. 1. "CDNE,Clear DONE bit" line.byte 0x5 "SSRT,Set START Bit Register" bitfld.byte 0x5 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x5 6. "SAST,Set all START bits (activates all channels)" "0: Set only those TCDn_CSR[START] bits specified in..,1: Set all bits in TCDn_CSR[START]" newline hexmask.byte 0x5 0.--5. 1. "SSRT,Set START bit" line.byte 0x6 "CERR,Clear Error Register" bitfld.byte 0x6 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x6 6. "CAEI,Clear all error indicators" "0: Clear only those ERR bits specified in the CERR..,1: Clear all bits in ERR" newline hexmask.byte 0x6 0.--5. 1. "CERR,Clear error indicator" line.byte 0x7 "CINT,Clear Interrupt Request Register" bitfld.byte 0x7 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x7 6. "CAIR,Clear all interrupt requests" "0: Clear only those INT bits specified in the CINT..,1: Clear all bits in INT{H L}" newline hexmask.byte 0x7 0.--5. 1. "CINT,Clear interrupt request" group.long 0x24++0x3 line.long 0x0 "INTL,Interrupt Request Register Low" bitfld.long 0x0 31. "INT31,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 30. "INT30,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 29. "INT29,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 28. "INT28,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 27. "INT27,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 26. "INT26,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 25. "INT25,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 24. "INT24,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 23. "INT23,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 22. "INT22,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 21. "INT21,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 20. "INT20,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 19. "INT19,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 18. "INT18,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 17. "INT17,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 16. "INT16,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 15. "INT15,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 14. "INT14,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 13. "INT13,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 12. "INT12,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 11. "INT11,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 10. "INT10,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 9. "INT9,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 8. "INT8,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 7. "INT7,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 6. "INT6,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 5. "INT5,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 4. "INT4,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 3. "INT3,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 2. "INT2,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 1. "INT1,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 0. "INT0,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." group.long 0x2C++0x3 line.long 0x0 "ERRL,Error Register Low" bitfld.long 0x0 31. "ERR31,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 30. "ERR30,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 29. "ERR29,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 28. "ERR28,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 27. "ERR27,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 26. "ERR26,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 25. "ERR25,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 24. "ERR24,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 23. "ERR23,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 22. "ERR22,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 21. "ERR21,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 20. "ERR20,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 19. "ERR19,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 18. "ERR18,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 17. "ERR17,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 16. "ERR16,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 15. "ERR15,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 14. "ERR14,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 13. "ERR13,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 12. "ERR12,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 11. "ERR11,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 10. "ERR10,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 9. "ERR9,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 8. "ERR8,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 7. "ERR7,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 6. "ERR6,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 5. "ERR5,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 4. "ERR4,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 3. "ERR3,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 2. "ERR2,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x0 1. "ERR1,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x0 0. "ERR0,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." group.long 0x34++0x3 line.long 0x0 "HRSL,Hardware Request Status Register Low" bitfld.long 0x0 31. "HRS31,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 30. "HRS30,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 29. "HRS29,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 28. "HRS28,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 27. "HRS27,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 26. "HRS26,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 25. "HRS25,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 24. "HRS24,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 23. "HRS23,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 22. "HRS22,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 21. "HRS21,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 20. "HRS20,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 19. "HRS19,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 18. "HRS18,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 17. "HRS17,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 16. "HRS16,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 15. "HRS15,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 14. "HRS14,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 13. "HRS13,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 12. "HRS12,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 11. "HRS11,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 10. "HRS10,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 9. "HRS9,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 8. "HRS8,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 7. "HRS7,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 6. "HRS6,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 5. "HRS5,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 4. "HRS4,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 3. "HRS3,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 2. "HRS2,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x0 1. "HRS1,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x0 0. "HRS0,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." group.byte 0x100++0x1F line.byte 0x0 "DCHPRI3,Channel n Priority register" bitfld.byte 0x0 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x0 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x0 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x0 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1 "DCHPRI2,Channel n Priority register" bitfld.byte 0x1 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x2 "DCHPRI1,Channel n Priority register" bitfld.byte 0x2 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x2 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x2 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x2 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x3 "DCHPRI0,Channel n Priority register" bitfld.byte 0x3 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x3 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x3 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x3 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x4 "DCHPRI7,Channel n Priority register" bitfld.byte 0x4 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x4 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x4 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x4 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x5 "DCHPRI6,Channel n Priority register" bitfld.byte 0x5 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x5 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x5 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x5 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x6 "DCHPRI5,Channel n Priority register" bitfld.byte 0x6 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x6 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x6 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x6 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x7 "DCHPRI4,Channel n Priority register" bitfld.byte 0x7 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x7 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x7 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x7 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x8 "DCHPRI11,Channel n Priority register" bitfld.byte 0x8 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x8 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x8 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x8 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x9 "DCHPRI10,Channel n Priority register" bitfld.byte 0x9 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x9 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x9 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x9 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xA "DCHPRI9,Channel n Priority register" bitfld.byte 0xA 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xA 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xA 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xA 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xB "DCHPRI8,Channel n Priority register" bitfld.byte 0xB 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xB 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xB 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xB 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xC "DCHPRI15,Channel n Priority register" bitfld.byte 0xC 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xC 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xC 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xC 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xD "DCHPRI14,Channel n Priority register" bitfld.byte 0xD 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xD 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xD 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xD 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xE "DCHPRI13,Channel n Priority register" bitfld.byte 0xE 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xE 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xE 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xE 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xF "DCHPRI12,Channel n Priority register" bitfld.byte 0xF 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xF 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xF 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xF 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x10 "DCHPRI19,Channel n Priority register" bitfld.byte 0x10 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x10 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x10 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x10 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x11 "DCHPRI18,Channel n Priority register" bitfld.byte 0x11 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x11 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x11 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x11 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x12 "DCHPRI17,Channel n Priority register" bitfld.byte 0x12 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x12 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x12 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x12 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x13 "DCHPRI16,Channel n Priority register" bitfld.byte 0x13 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x13 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x13 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x13 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x14 "DCHPRI23,Channel n Priority register" bitfld.byte 0x14 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x14 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x14 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x14 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x15 "DCHPRI22,Channel n Priority register" bitfld.byte 0x15 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x15 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x15 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x15 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x16 "DCHPRI21,Channel n Priority register" bitfld.byte 0x16 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x16 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x16 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x16 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x17 "DCHPRI20,Channel n Priority register" bitfld.byte 0x17 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x17 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x17 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x17 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x18 "DCHPRI27,Channel n Priority register" bitfld.byte 0x18 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x18 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x18 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x18 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x19 "DCHPRI26,Channel n Priority register" bitfld.byte 0x19 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x19 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x19 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x19 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1A "DCHPRI25,Channel n Priority register" bitfld.byte 0x1A 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1A 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1A 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1A 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1B "DCHPRI24,Channel n Priority register" bitfld.byte 0x1B 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1B 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1B 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1B 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1C "DCHPRI31,Channel n Priority register" bitfld.byte 0x1C 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1C 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1C 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1C 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1D "DCHPRI30,Channel n Priority register" bitfld.byte 0x1D 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1D 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1D 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1D 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1E "DCHPRI29,Channel n Priority register" bitfld.byte 0x1E 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1E 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1E 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1E 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1F "DCHPRI28,Channel n Priority register" bitfld.byte 0x1F 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1F 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1F 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1F 0.--3. 1. "CHPRI,Channel n arbitration priority" group.byte 0x140++0x1F line.byte 0x0 "REQSTR_ID0,Channel 0 Requester ID register" bitfld.byte 0x0 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x0 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x0 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x1 "REQSTR_ID1,Channel 1 Requester ID register" bitfld.byte 0x1 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x1 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x1 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x2 "REQSTR_ID2,Channel 2 Requester ID register" bitfld.byte 0x2 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x2 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x2 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x3 "REQSTR_ID3,Channel 3 Requester ID register" bitfld.byte 0x3 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x3 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x3 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x4 "REQSTR_ID4,Channel 4 Requester ID register" bitfld.byte 0x4 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x4 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x4 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x5 "REQSTR_ID5,Channel 5 Requester ID register" bitfld.byte 0x5 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x5 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x5 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x6 "REQSTR_ID6,Channel 6 Requester ID register" bitfld.byte 0x6 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x6 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x6 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x7 "REQSTR_ID7,Channel 7 Requester ID register" bitfld.byte 0x7 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x7 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x7 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x8 "REQSTR_ID8,Channel 8 Requester ID register" bitfld.byte 0x8 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x8 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x8 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x9 "REQSTR_ID9,Channel 9 Requester ID register" bitfld.byte 0x9 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x9 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x9 0.--5. 1. "REQ_ID,Requester ID" line.byte 0xA "REQSTR_ID10,Channel 10 Requester ID register" bitfld.byte 0xA 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0xA 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0xA 0.--5. 1. "REQ_ID,Requester ID" line.byte 0xB "REQSTR_ID11,Channel 11 Requester ID register" bitfld.byte 0xB 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0xB 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0xB 0.--5. 1. "REQ_ID,Requester ID" line.byte 0xC "REQSTR_ID12,Channel 12 Requester ID register" bitfld.byte 0xC 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0xC 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0xC 0.--5. 1. "REQ_ID,Requester ID" line.byte 0xD "REQSTR_ID13,Channel 13 Requester ID register" bitfld.byte 0xD 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0xD 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0xD 0.--5. 1. "REQ_ID,Requester ID" line.byte 0xE "REQSTR_ID14,Channel 14 Requester ID register" bitfld.byte 0xE 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0xE 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0xE 0.--5. 1. "REQ_ID,Requester ID" line.byte 0xF "REQSTR_ID15,Channel 15 Requester ID register" bitfld.byte 0xF 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0xF 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0xF 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x10 "REQSTR_ID16,Channel 16 Requester ID register" bitfld.byte 0x10 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x10 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x10 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x11 "REQSTR_ID17,Channel 17 Requester ID register" bitfld.byte 0x11 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x11 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x11 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x12 "REQSTR_ID18,Channel 18 Requester ID register" bitfld.byte 0x12 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x12 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x12 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x13 "REQSTR_ID19,Channel 19 Requester ID register" bitfld.byte 0x13 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x13 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x13 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x14 "REQSTR_ID20,Channel 20 Requester ID register" bitfld.byte 0x14 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x14 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x14 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x15 "REQSTR_ID21,Channel 21 Requester ID register" bitfld.byte 0x15 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x15 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x15 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x16 "REQSTR_ID22,Channel 22 Requester ID register" bitfld.byte 0x16 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x16 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x16 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x17 "REQSTR_ID23,Channel 23 Requester ID register" bitfld.byte 0x17 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x17 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x17 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x18 "REQSTR_ID24,Channel 24 Requester ID register" bitfld.byte 0x18 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x18 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x18 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x19 "REQSTR_ID25,Channel 25 Requester ID register" bitfld.byte 0x19 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x19 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x19 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x1A "REQSTR_ID26,Channel 26 Requester ID register" bitfld.byte 0x1A 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x1A 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x1A 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x1B "REQSTR_ID27,Channel 27 Requester ID register" bitfld.byte 0x1B 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x1B 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x1B 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x1C "REQSTR_ID28,Channel 28 Requester ID register" bitfld.byte 0x1C 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x1C 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x1C 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x1D "REQSTR_ID29,Channel 29 Requester ID register" bitfld.byte 0x1D 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x1D 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x1D 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x1E "REQSTR_ID30,Channel 30 Requester ID register" bitfld.byte 0x1E 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x1E 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x1E 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x1F "REQSTR_ID31,Channel 31 Requester ID register" bitfld.byte 0x1F 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x1F 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x1F 0.--5. 1. "REQ_ID,Requester ID" group.long 0x180++0x7 line.long 0x0 "VMID0,Channel 0 to 15 VMID Register" bitfld.long 0x0 8. "VMID_EN,VMID_0 Enable" "0: 8-bit VMID value out disabled.,1: 8-bit VMID value out enabled." hexmask.long.byte 0x0 0.--7. 1. "VMID,VMID_0 value" line.long 0x4 "VMID1,Channel 16 to 31 VMID Register" bitfld.long 0x4 8. "VMID_EN,VMID_1 Enable" "0: 8-bit VMID value out disabled.,1: 8-bit VMID value out enabled." hexmask.long.byte 0x4 0.--7. 1. "VMID,VMID_1 value" group.long 0x190++0x3 line.long 0x0 "VMID_ERR_STATUS,Channel VMID Error Status register" bitfld.long 0x0 0. "VMID_ERR,VMID error" "0: No Non-Hypervisor Access to eDMA_VMID_n register,1: Transfer Error for Non-Hypervisor Access to.." group.long 0x1000++0x3 line.long 0x0 "TCD0_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1004++0x3 line.word 0x0 "TCD0_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD0_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1008++0x3 line.long 0x0 "TCD0_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1008++0x3 line.long 0x0 "TCD0_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1008++0xB line.long 0x0 "TCD0_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD0_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD0_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1014++0x3 line.word 0x0 "TCD0_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1016++0x1 line.word 0x0 "TCD0_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1018++0x3 line.long 0x0 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x101C++0x3 line.word 0x0 "TCD0_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD0_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x101E++0x1 line.word 0x0 "TCD0_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1020++0x3 line.long 0x0 "TCD1_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1024++0x3 line.word 0x0 "TCD1_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD1_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1028++0x3 line.long 0x0 "TCD1_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1028++0x3 line.long 0x0 "TCD1_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1028++0xB line.long 0x0 "TCD1_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD1_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD1_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1034++0x3 line.word 0x0 "TCD1_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1036++0x1 line.word 0x0 "TCD1_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1038++0x3 line.long 0x0 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x103C++0x3 line.word 0x0 "TCD1_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD1_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x103E++0x1 line.word 0x0 "TCD1_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1040++0x3 line.long 0x0 "TCD2_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1044++0x3 line.word 0x0 "TCD2_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD2_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1048++0x3 line.long 0x0 "TCD2_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1048++0x3 line.long 0x0 "TCD2_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1048++0xB line.long 0x0 "TCD2_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD2_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD2_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1054++0x3 line.word 0x0 "TCD2_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1056++0x1 line.word 0x0 "TCD2_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1058++0x3 line.long 0x0 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x105C++0x3 line.word 0x0 "TCD2_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD2_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x105E++0x1 line.word 0x0 "TCD2_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1060++0x3 line.long 0x0 "TCD3_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1064++0x3 line.word 0x0 "TCD3_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD3_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1068++0x3 line.long 0x0 "TCD3_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1068++0x3 line.long 0x0 "TCD3_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1068++0xB line.long 0x0 "TCD3_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD3_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD3_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1074++0x3 line.word 0x0 "TCD3_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1076++0x1 line.word 0x0 "TCD3_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1078++0x3 line.long 0x0 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x107C++0x3 line.word 0x0 "TCD3_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD3_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x107E++0x1 line.word 0x0 "TCD3_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1080++0x3 line.long 0x0 "TCD4_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1084++0x3 line.word 0x0 "TCD4_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD4_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1088++0x3 line.long 0x0 "TCD4_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1088++0x3 line.long 0x0 "TCD4_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1088++0xB line.long 0x0 "TCD4_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD4_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD4_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1094++0x3 line.word 0x0 "TCD4_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD4_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1096++0x1 line.word 0x0 "TCD4_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1098++0x3 line.long 0x0 "TCD4_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x109C++0x3 line.word 0x0 "TCD4_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD4_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x109E++0x1 line.word 0x0 "TCD4_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x10A0++0x3 line.long 0x0 "TCD5_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x10A4++0x3 line.word 0x0 "TCD5_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD5_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x10A8++0x3 line.long 0x0 "TCD5_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x10A8++0x3 line.long 0x0 "TCD5_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x10A8++0xB line.long 0x0 "TCD5_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD5_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD5_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x10B4++0x3 line.word 0x0 "TCD5_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD5_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x10B6++0x1 line.word 0x0 "TCD5_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x10B8++0x3 line.long 0x0 "TCD5_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x10BC++0x3 line.word 0x0 "TCD5_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD5_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x10BE++0x1 line.word 0x0 "TCD5_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x10C0++0x3 line.long 0x0 "TCD6_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x10C4++0x3 line.word 0x0 "TCD6_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD6_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x10C8++0x3 line.long 0x0 "TCD6_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x10C8++0x3 line.long 0x0 "TCD6_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x10C8++0xB line.long 0x0 "TCD6_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD6_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD6_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x10D4++0x3 line.word 0x0 "TCD6_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD6_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x10D6++0x1 line.word 0x0 "TCD6_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x10D8++0x3 line.long 0x0 "TCD6_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x10DC++0x3 line.word 0x0 "TCD6_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD6_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x10DE++0x1 line.word 0x0 "TCD6_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x10E0++0x3 line.long 0x0 "TCD7_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x10E4++0x3 line.word 0x0 "TCD7_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD7_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x10E8++0x3 line.long 0x0 "TCD7_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x10E8++0x3 line.long 0x0 "TCD7_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x10E8++0xB line.long 0x0 "TCD7_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD7_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD7_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x10F4++0x3 line.word 0x0 "TCD7_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD7_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x10F6++0x1 line.word 0x0 "TCD7_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x10F8++0x3 line.long 0x0 "TCD7_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x10FC++0x3 line.word 0x0 "TCD7_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD7_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x10FE++0x1 line.word 0x0 "TCD7_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1100++0x3 line.long 0x0 "TCD8_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1104++0x3 line.word 0x0 "TCD8_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD8_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1108++0x3 line.long 0x0 "TCD8_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1108++0x3 line.long 0x0 "TCD8_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1108++0xB line.long 0x0 "TCD8_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD8_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD8_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1114++0x3 line.word 0x0 "TCD8_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD8_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1116++0x1 line.word 0x0 "TCD8_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1118++0x3 line.long 0x0 "TCD8_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x111C++0x3 line.word 0x0 "TCD8_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD8_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x111E++0x1 line.word 0x0 "TCD8_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1120++0x3 line.long 0x0 "TCD9_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1124++0x3 line.word 0x0 "TCD9_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD9_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1128++0x3 line.long 0x0 "TCD9_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1128++0x3 line.long 0x0 "TCD9_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1128++0xB line.long 0x0 "TCD9_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD9_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD9_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1134++0x3 line.word 0x0 "TCD9_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD9_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1136++0x1 line.word 0x0 "TCD9_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1138++0x3 line.long 0x0 "TCD9_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x113C++0x3 line.word 0x0 "TCD9_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD9_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x113E++0x1 line.word 0x0 "TCD9_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1140++0x3 line.long 0x0 "TCD10_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1144++0x3 line.word 0x0 "TCD10_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD10_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1148++0x3 line.long 0x0 "TCD10_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1148++0x3 line.long 0x0 "TCD10_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1148++0xB line.long 0x0 "TCD10_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD10_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD10_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1154++0x3 line.word 0x0 "TCD10_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD10_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1156++0x1 line.word 0x0 "TCD10_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1158++0x3 line.long 0x0 "TCD10_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x115C++0x3 line.word 0x0 "TCD10_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD10_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x115E++0x1 line.word 0x0 "TCD10_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1160++0x3 line.long 0x0 "TCD11_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1164++0x3 line.word 0x0 "TCD11_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD11_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1168++0x3 line.long 0x0 "TCD11_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1168++0x3 line.long 0x0 "TCD11_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1168++0xB line.long 0x0 "TCD11_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD11_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD11_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1174++0x3 line.word 0x0 "TCD11_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD11_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1176++0x1 line.word 0x0 "TCD11_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1178++0x3 line.long 0x0 "TCD11_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x117C++0x3 line.word 0x0 "TCD11_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD11_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x117E++0x1 line.word 0x0 "TCD11_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1180++0x3 line.long 0x0 "TCD12_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1184++0x3 line.word 0x0 "TCD12_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD12_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1188++0x3 line.long 0x0 "TCD12_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1188++0x3 line.long 0x0 "TCD12_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1188++0xB line.long 0x0 "TCD12_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD12_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD12_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1194++0x3 line.word 0x0 "TCD12_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD12_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1196++0x1 line.word 0x0 "TCD12_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1198++0x3 line.long 0x0 "TCD12_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x119C++0x3 line.word 0x0 "TCD12_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD12_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x119E++0x1 line.word 0x0 "TCD12_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x11A0++0x3 line.long 0x0 "TCD13_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x11A4++0x3 line.word 0x0 "TCD13_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD13_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x11A8++0x3 line.long 0x0 "TCD13_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x11A8++0x3 line.long 0x0 "TCD13_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x11A8++0xB line.long 0x0 "TCD13_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD13_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD13_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x11B4++0x3 line.word 0x0 "TCD13_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD13_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x11B6++0x1 line.word 0x0 "TCD13_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x11B8++0x3 line.long 0x0 "TCD13_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x11BC++0x3 line.word 0x0 "TCD13_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD13_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x11BE++0x1 line.word 0x0 "TCD13_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x11C0++0x3 line.long 0x0 "TCD14_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x11C4++0x3 line.word 0x0 "TCD14_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD14_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x11C8++0x3 line.long 0x0 "TCD14_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x11C8++0x3 line.long 0x0 "TCD14_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x11C8++0xB line.long 0x0 "TCD14_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD14_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD14_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x11D4++0x3 line.word 0x0 "TCD14_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD14_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x11D6++0x1 line.word 0x0 "TCD14_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x11D8++0x3 line.long 0x0 "TCD14_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x11DC++0x3 line.word 0x0 "TCD14_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD14_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x11DE++0x1 line.word 0x0 "TCD14_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x11E0++0x3 line.long 0x0 "TCD15_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x11E4++0x3 line.word 0x0 "TCD15_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD15_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x11E8++0x3 line.long 0x0 "TCD15_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x11E8++0x3 line.long 0x0 "TCD15_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x11E8++0xB line.long 0x0 "TCD15_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD15_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD15_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x11F4++0x3 line.word 0x0 "TCD15_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD15_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x11F6++0x1 line.word 0x0 "TCD15_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x11F8++0x3 line.long 0x0 "TCD15_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x11FC++0x3 line.word 0x0 "TCD15_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD15_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x11FE++0x1 line.word 0x0 "TCD15_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1200++0x3 line.long 0x0 "TCD16_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1204++0x3 line.word 0x0 "TCD16_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD16_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1208++0x3 line.long 0x0 "TCD16_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1208++0x3 line.long 0x0 "TCD16_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1208++0xB line.long 0x0 "TCD16_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD16_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD16_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1214++0x3 line.word 0x0 "TCD16_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD16_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1216++0x1 line.word 0x0 "TCD16_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1218++0x3 line.long 0x0 "TCD16_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x121C++0x3 line.word 0x0 "TCD16_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD16_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x121E++0x1 line.word 0x0 "TCD16_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1220++0x3 line.long 0x0 "TCD17_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1224++0x3 line.word 0x0 "TCD17_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD17_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1228++0x3 line.long 0x0 "TCD17_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1228++0x3 line.long 0x0 "TCD17_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1228++0xB line.long 0x0 "TCD17_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD17_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD17_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1234++0x3 line.word 0x0 "TCD17_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD17_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1236++0x1 line.word 0x0 "TCD17_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1238++0x3 line.long 0x0 "TCD17_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x123C++0x3 line.word 0x0 "TCD17_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD17_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x123E++0x1 line.word 0x0 "TCD17_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1240++0x3 line.long 0x0 "TCD18_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1244++0x3 line.word 0x0 "TCD18_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD18_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1248++0x3 line.long 0x0 "TCD18_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1248++0x3 line.long 0x0 "TCD18_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1248++0xB line.long 0x0 "TCD18_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD18_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD18_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1254++0x3 line.word 0x0 "TCD18_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD18_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1256++0x1 line.word 0x0 "TCD18_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1258++0x3 line.long 0x0 "TCD18_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x125C++0x3 line.word 0x0 "TCD18_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD18_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x125E++0x1 line.word 0x0 "TCD18_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1260++0x3 line.long 0x0 "TCD19_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1264++0x3 line.word 0x0 "TCD19_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD19_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1268++0x3 line.long 0x0 "TCD19_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1268++0x3 line.long 0x0 "TCD19_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1268++0xB line.long 0x0 "TCD19_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD19_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD19_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1274++0x3 line.word 0x0 "TCD19_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD19_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1276++0x1 line.word 0x0 "TCD19_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1278++0x3 line.long 0x0 "TCD19_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x127C++0x3 line.word 0x0 "TCD19_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD19_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x127E++0x1 line.word 0x0 "TCD19_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1280++0x3 line.long 0x0 "TCD20_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1284++0x3 line.word 0x0 "TCD20_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD20_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1288++0x3 line.long 0x0 "TCD20_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1288++0x3 line.long 0x0 "TCD20_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1288++0xB line.long 0x0 "TCD20_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD20_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD20_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1294++0x3 line.word 0x0 "TCD20_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD20_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1296++0x1 line.word 0x0 "TCD20_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1298++0x3 line.long 0x0 "TCD20_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x129C++0x3 line.word 0x0 "TCD20_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD20_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x129E++0x1 line.word 0x0 "TCD20_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x12A0++0x3 line.long 0x0 "TCD21_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x12A4++0x3 line.word 0x0 "TCD21_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD21_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x12A8++0x3 line.long 0x0 "TCD21_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x12A8++0x3 line.long 0x0 "TCD21_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x12A8++0xB line.long 0x0 "TCD21_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD21_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD21_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x12B4++0x3 line.word 0x0 "TCD21_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD21_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x12B6++0x1 line.word 0x0 "TCD21_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x12B8++0x3 line.long 0x0 "TCD21_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x12BC++0x3 line.word 0x0 "TCD21_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD21_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x12BE++0x1 line.word 0x0 "TCD21_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x12C0++0x3 line.long 0x0 "TCD22_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x12C4++0x3 line.word 0x0 "TCD22_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD22_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x12C8++0x3 line.long 0x0 "TCD22_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x12C8++0x3 line.long 0x0 "TCD22_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x12C8++0xB line.long 0x0 "TCD22_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD22_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD22_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x12D4++0x3 line.word 0x0 "TCD22_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD22_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x12D6++0x1 line.word 0x0 "TCD22_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x12D8++0x3 line.long 0x0 "TCD22_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x12DC++0x3 line.word 0x0 "TCD22_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD22_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x12DE++0x1 line.word 0x0 "TCD22_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x12E0++0x3 line.long 0x0 "TCD23_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x12E4++0x3 line.word 0x0 "TCD23_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD23_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x12E8++0x3 line.long 0x0 "TCD23_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x12E8++0x3 line.long 0x0 "TCD23_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x12E8++0xB line.long 0x0 "TCD23_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD23_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD23_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x12F4++0x3 line.word 0x0 "TCD23_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD23_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x12F6++0x1 line.word 0x0 "TCD23_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x12F8++0x3 line.long 0x0 "TCD23_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x12FC++0x3 line.word 0x0 "TCD23_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD23_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x12FE++0x1 line.word 0x0 "TCD23_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1300++0x3 line.long 0x0 "TCD24_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1304++0x3 line.word 0x0 "TCD24_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD24_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1308++0x3 line.long 0x0 "TCD24_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1308++0x3 line.long 0x0 "TCD24_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1308++0xB line.long 0x0 "TCD24_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD24_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD24_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1314++0x3 line.word 0x0 "TCD24_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD24_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1316++0x1 line.word 0x0 "TCD24_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1318++0x3 line.long 0x0 "TCD24_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x131C++0x3 line.word 0x0 "TCD24_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD24_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x131E++0x1 line.word 0x0 "TCD24_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1320++0x3 line.long 0x0 "TCD25_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1324++0x3 line.word 0x0 "TCD25_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD25_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1328++0x3 line.long 0x0 "TCD25_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1328++0x3 line.long 0x0 "TCD25_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1328++0xB line.long 0x0 "TCD25_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD25_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD25_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1334++0x3 line.word 0x0 "TCD25_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD25_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1336++0x1 line.word 0x0 "TCD25_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1338++0x3 line.long 0x0 "TCD25_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x133C++0x3 line.word 0x0 "TCD25_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD25_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x133E++0x1 line.word 0x0 "TCD25_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1340++0x3 line.long 0x0 "TCD26_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1344++0x3 line.word 0x0 "TCD26_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD26_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1348++0x3 line.long 0x0 "TCD26_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1348++0x3 line.long 0x0 "TCD26_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1348++0xB line.long 0x0 "TCD26_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD26_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD26_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1354++0x3 line.word 0x0 "TCD26_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD26_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1356++0x1 line.word 0x0 "TCD26_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1358++0x3 line.long 0x0 "TCD26_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x135C++0x3 line.word 0x0 "TCD26_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD26_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x135E++0x1 line.word 0x0 "TCD26_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1360++0x3 line.long 0x0 "TCD27_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1364++0x3 line.word 0x0 "TCD27_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD27_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1368++0x3 line.long 0x0 "TCD27_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1368++0x3 line.long 0x0 "TCD27_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1368++0xB line.long 0x0 "TCD27_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD27_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD27_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1374++0x3 line.word 0x0 "TCD27_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD27_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1376++0x1 line.word 0x0 "TCD27_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1378++0x3 line.long 0x0 "TCD27_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x137C++0x3 line.word 0x0 "TCD27_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD27_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x137E++0x1 line.word 0x0 "TCD27_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1380++0x3 line.long 0x0 "TCD28_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1384++0x3 line.word 0x0 "TCD28_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD28_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1388++0x3 line.long 0x0 "TCD28_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1388++0x3 line.long 0x0 "TCD28_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1388++0xB line.long 0x0 "TCD28_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD28_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD28_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1394++0x3 line.word 0x0 "TCD28_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD28_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1396++0x1 line.word 0x0 "TCD28_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1398++0x3 line.long 0x0 "TCD28_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x139C++0x3 line.word 0x0 "TCD28_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD28_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x139E++0x1 line.word 0x0 "TCD28_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x13A0++0x3 line.long 0x0 "TCD29_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x13A4++0x3 line.word 0x0 "TCD29_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD29_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x13A8++0x3 line.long 0x0 "TCD29_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x13A8++0x3 line.long 0x0 "TCD29_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x13A8++0xB line.long 0x0 "TCD29_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD29_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD29_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x13B4++0x3 line.word 0x0 "TCD29_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD29_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x13B6++0x1 line.word 0x0 "TCD29_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x13B8++0x3 line.long 0x0 "TCD29_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x13BC++0x3 line.word 0x0 "TCD29_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD29_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x13BE++0x1 line.word 0x0 "TCD29_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x13C0++0x3 line.long 0x0 "TCD30_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x13C4++0x3 line.word 0x0 "TCD30_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD30_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x13C8++0x3 line.long 0x0 "TCD30_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x13C8++0x3 line.long 0x0 "TCD30_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x13C8++0xB line.long 0x0 "TCD30_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD30_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD30_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x13D4++0x3 line.word 0x0 "TCD30_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD30_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x13D6++0x1 line.word 0x0 "TCD30_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x13D8++0x3 line.long 0x0 "TCD30_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x13DC++0x3 line.word 0x0 "TCD30_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD30_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x13DE++0x1 line.word 0x0 "TCD30_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x13E0++0x3 line.long 0x0 "TCD31_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x13E4++0x3 line.word 0x0 "TCD31_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD31_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x13E8++0x3 line.long 0x0 "TCD31_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x13E8++0x3 line.long 0x0 "TCD31_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x13E8++0xB line.long 0x0 "TCD31_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD31_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD31_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x13F4++0x3 line.word 0x0 "TCD31_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD31_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x13F6++0x1 line.word 0x0 "TCD31_CITER_ELINKNO,Refer to Figure34: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table34: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x13F8++0x3 line.long 0x0 "TCD31_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x13FC++0x3 line.word 0x0 "TCD31_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD31_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x13FE++0x1 line.word 0x0 "TCD31_BITER_ELINKNO,Refer to Figure38: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table38: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" tree.end tree "EDMA_3" base ad:0x709D0000 group.long 0x0++0x3 line.long 0x0 "CR,Control Register" bitfld.long 0x0 17. "CX,Cancel transfer" "0: Normal operation,1: Cancel the remaining data transfer. Stop the.." bitfld.long 0x0 16. "ECX,Error cancel transfer" "0: Normal operation,1: Cancel the remaining data transfer in the same.." newline bitfld.long 0x0 14.--15. "GRP3PRI,Channel group 3 priority" "0,1,2,3" bitfld.long 0x0 12.--13. "GRP2PRI,Channel group 2 priority" "0,1,2,3" newline bitfld.long 0x0 10.--11. "GRP1PRI,Channel group 1 priority" "0,1,2,3" bitfld.long 0x0 8.--9. "GRP0PRI,Channel group 0 priority" "0,1,2,3" newline bitfld.long 0x0 7. "EMLM,Enable minor loop mapping" "0: Disabled. TCDn.word2 is defined as a 32-bit..,1: Enabled. TCDn.word2 is redefined to include.." bitfld.long 0x0 6. "CLM,Continuous Link mode" "0: A minor loop channel link made to itself goes..,1: A minor loop channel link made to itself does.." newline bitfld.long 0x0 5. "HALT,Halt DMA operations" "0: Normal operation,1: Stall the start of any new channels. Executing.." bitfld.long 0x0 4. "HOE,Halt on error" "0: Normal operation,1: Any error causes the HALT bit to set." newline bitfld.long 0x0 3. "ERGA,Enable round-robin group arbitration" "0: Fixed-priority arbitration is used for selection..,1: Round-robin arbitration is used for selection.." bitfld.long 0x0 2. "ERCA,Enable round-robin channel arbitration" "0: Fixed-priority arbitration is used for channel..,1: Round-robin arbitration is used for channel.." newline bitfld.long 0x0 1. "EDBG,Enable debug" "0: When in Debug mode the DMA continues to operate.,1: When in Debug mode the DMA stalls the start of a.." bitfld.long 0x0 0. "EBW,Enable Buffered Writes" "0: The bufferable write signal (hprot[2]) is not..,1: The bufferable write signal (hprot[2]) is.." rgroup.long 0x4++0x3 line.long 0x0 "ES,Error Status Register" bitfld.long 0x0 31. "VLD,ERRH and ERRL status bits" "0: No ERR bits are set.,1: At least one ERR bit is set indicating a valid.." bitfld.long 0x0 17. "UCE,Uncorrectable ECC error" "0: No uncorrectable ECC error,1: The last recorded error was an uncorrectable TCD.." newline bitfld.long 0x0 16. "ECX,Transfer cancelled" "0: No cancelled transfers.,1: The last recorded entry was a cancelled transfer.." bitfld.long 0x0 15. "GPE,Group priority error" "0: No group priority error,1: The last recorded error was a configuration.." newline bitfld.long 0x0 14. "CPE,Channel priority error" "0: No channel priority error,1: The last recorded error was a configuration.." hexmask.long.byte 0x0 8.--13. 1. "ERRCHN,Error channel number or cancelled channel number GPE or last recorded error cancelled transfer." newline bitfld.long 0x0 7. "SAE,Source address error" "0: No source address configuration error.,1: The last recorded error was a configuration.." bitfld.long 0x0 6. "SOE,Source offset error" "0: No source offset configuration error,1: The last recorded error was a configuration.." newline bitfld.long 0x0 5. "DAE,Destination address error" "0: No destination address configuration error,1: The last recorded error was a configuration.." bitfld.long 0x0 4. "DOE,Destination offset error" "0: No destination offset configuration error,1: The last recorded error was a configuration.." newline bitfld.long 0x0 3. "NCE,NBYTES/CITER configuration error" "0: No NBYTES/CITER configuration error,1: The last recorded error was a configuration.." bitfld.long 0x0 2. "SGE,Scatter/gather configuration error" "0: No scatter/gather configuration error,1: The last recorded error was a configuration.." newline bitfld.long 0x0 1. "SBE,Source bus error" "0: No source bus error,1: The last recorded error was a bus error on a.." bitfld.long 0x0 0. "DBE,Destination bus error" "0: No destination bus error,1: The last recorded error was a bus error on a.." group.long 0x8++0xF line.long 0x0 "ERQH,Enable Request Register High" bitfld.long 0x0 31. "ERQ63,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 30. "ERQ62,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 29. "ERQ61,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 28. "ERQ60,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 27. "ERQ59,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 26. "ERQ58,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 25. "ERQ57,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 24. "ERQ56,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 23. "ERQ55,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 22. "ERQ54,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 21. "ERQ53,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 20. "ERQ52,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 19. "ERQ51,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 18. "ERQ50,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 17. "ERQ49,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 16. "ERQ48,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 15. "ERQ47,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 14. "ERQ46,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 13. "ERQ45,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 12. "ERQ44,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 11. "ERQ43,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 10. "ERQ42,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 9. "ERQ41,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 8. "ERQ40,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 7. "ERQ39,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 6. "ERQ38,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 5. "ERQ37,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 4. "ERQ36,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 3. "ERQ35,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 2. "ERQ34,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x0 1. "ERQ33,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x0 0. "ERQ32,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." line.long 0x4 "ERQL,Enable Request Register Low" bitfld.long 0x4 31. "ERQ31,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x4 30. "ERQ30,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x4 29. "ERQ29,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x4 28. "ERQ28,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x4 27. "ERQ27,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x4 26. "ERQ26,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x4 25. "ERQ25,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x4 24. "ERQ24,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x4 23. "ERQ23,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x4 22. "ERQ22,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x4 21. "ERQ21,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x4 20. "ERQ20,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x4 19. "ERQ19,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x4 18. "ERQ18,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x4 17. "ERQ17,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x4 16. "ERQ16,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x4 15. "ERQ15,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x4 14. "ERQ14,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x4 13. "ERQ13,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x4 12. "ERQ12,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x4 11. "ERQ11,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x4 10. "ERQ10,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x4 9. "ERQ9,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x4 8. "ERQ8,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x4 7. "ERQ7,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x4 6. "ERQ6,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x4 5. "ERQ5,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x4 4. "ERQ4,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x4 3. "ERQ3,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x4 2. "ERQ2,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." newline bitfld.long 0x4 1. "ERQ1,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." bitfld.long 0x4 0. "ERQ0,Enable DMA Request x" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.." line.long 0x8 "EEIH,Enable Error Interrupt Register High" bitfld.long 0x8 31. "EEI63,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x8 30. "EEI62,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x8 29. "EEI61,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x8 28. "EEI60,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x8 27. "EEI59,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x8 26. "EEI58,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x8 25. "EEI57,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x8 24. "EEI56,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x8 23. "EEI55,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x8 22. "EEI54,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x8 21. "EEI53,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x8 20. "EEI52,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x8 19. "EEI51,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x8 18. "EEI50,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x8 17. "EEI49,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x8 16. "EEI48,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x8 15. "EEI47,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x8 14. "EEI46,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x8 13. "EEI45,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x8 12. "EEI44,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x8 11. "EEI43,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x8 10. "EEI42,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x8 9. "EEI41,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x8 8. "EEI40,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x8 7. "EEI39,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x8 6. "EEI38,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x8 5. "EEI37,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x8 4. "EEI36,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x8 3. "EEI35,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x8 2. "EEI34,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0x8 1. "EEI33,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0x8 0. "EEI32,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." line.long 0xC "EEIL,Enable Error Interrupt Register Low" bitfld.long 0xC 31. "EEI31,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0xC 30. "EEI30,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0xC 29. "EEI29,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0xC 28. "EEI28,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0xC 27. "EEI27,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0xC 26. "EEI26,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0xC 25. "EEI25,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0xC 24. "EEI24,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0xC 23. "EEI23,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0xC 22. "EEI22,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0xC 21. "EEI21,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0xC 20. "EEI20,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0xC 19. "EEI19,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0xC 18. "EEI18,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0xC 17. "EEI17,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0xC 16. "EEI16,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0xC 15. "EEI15,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0xC 14. "EEI14,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0xC 13. "EEI13,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0xC 12. "EEI12,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0xC 11. "EEI11,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0xC 10. "EEI10,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0xC 9. "EEI9,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0xC 8. "EEI8,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0xC 7. "EEI7,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0xC 6. "EEI6,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0xC 5. "EEI5,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0xC 4. "EEI4,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0xC 3. "EEI3,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0xC 2. "EEI2,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." newline bitfld.long 0xC 1. "EEI1,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." bitfld.long 0xC 0. "EEI0,Enable error interrupt x" "0: The error signal for corresponding channel does..,1: The assertion of the error signal for.." wgroup.byte 0x18++0x7 line.byte 0x0 "CEEI,Clear Enable Error Interrupt Register" bitfld.byte 0x0 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x0 6. "CAEE,Clear all enable error interrupts" "0: Clear only those EEI bits specified in the CEEI..,1: Clear all bits in EEI" newline hexmask.byte 0x0 0.--5. 1. "CEEI,Clear enable error interrupt" line.byte 0x1 "SEEI,Set Enable Error Interrupt Register" bitfld.byte 0x1 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x1 6. "SAEE,Sets all enable error interrupts" "0: Set only those EEI bits specified in the SEEI..,1: Sets all bits in EEI." newline hexmask.byte 0x1 0.--5. 1. "SEEI,Set enable error interrupt" line.byte 0x2 "CERQ,Clear Enable Request Register" bitfld.byte 0x2 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x2 6. "CAER,Clear all enable requests" "0: Clear only those ERQ bits specified in the CERQ..,1: Clear all bits in ERQ" newline hexmask.byte 0x2 0.--5. 1. "CERQ,Clear enable request" line.byte 0x3 "SERQ,Set Enable Request Register" bitfld.byte 0x3 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x3 6. "SAER,Set all enable requests" "0: Set only those ERQ bits specified in the SERQ..,1: Set all bits in ERQ{H L}" newline hexmask.byte 0x3 0.--5. 1. "SERQ,Set enable request" line.byte 0x4 "CDNE,Clear DONE Status Bit Register" bitfld.byte 0x4 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x4 6. "CADN,Clears all DONE bits" "0: Clears only those TCDn_CSR[DONE] bits specified..,1: Clears all bits in TCDn_CSR[DONE]" newline hexmask.byte 0x4 0.--5. 1. "CDNE,Clear DONE bit" line.byte 0x5 "SSRT,Set START Bit Register" bitfld.byte 0x5 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x5 6. "SAST,Set all START bits (activates all channels)" "0: Set only those TCDn_CSR[START] bits specified in..,1: Set all bits in TCDn_CSR[START]" newline hexmask.byte 0x5 0.--5. 1. "SSRT,Set START bit" line.byte 0x6 "CERR,Clear Error Register" bitfld.byte 0x6 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x6 6. "CAEI,Clear all error indicators" "0: Clear only those ERR bits specified in the CERR..,1: Clear all bits in ERR" newline hexmask.byte 0x6 0.--5. 1. "CERR,Clear error indicator" line.byte 0x7 "CINT,Clear Interrupt Request Register" bitfld.byte 0x7 7. "NOP,NOP" "0: Normal operation,1: No operation ignore bits 17 of this register" bitfld.byte 0x7 6. "CAIR,Clear all interrupt requests" "0: Clear only those INT bits specified in the CINT..,1: Clear all bits in INT{H L}" newline hexmask.byte 0x7 0.--5. 1. "CINT,Clear interrupt request" group.long 0x20++0x17 line.long 0x0 "INTH,Interrupt Request Register High" bitfld.long 0x0 31. "INT63,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 30. "INT62,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 29. "INT61,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 28. "INT60,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 27. "INT59,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 26. "INT58,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 25. "INT57,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 24. "INT56,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 23. "INT55,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 22. "INT54,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 21. "INT53,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 20. "INT52,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 19. "INT51,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 18. "INT50,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 17. "INT49,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 16. "INT48,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 15. "INT47,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 14. "INT46,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 13. "INT45,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 12. "INT44,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 11. "INT43,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 10. "INT42,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 9. "INT41,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 8. "INT40,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 7. "INT39,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 6. "INT38,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 5. "INT37,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 4. "INT36,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 3. "INT35,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 2. "INT34,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x0 1. "INT33,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x0 0. "INT32,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." line.long 0x4 "INTL,Interrupt Request Register Low" bitfld.long 0x4 31. "INT31,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x4 30. "INT30,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x4 29. "INT29,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x4 28. "INT28,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x4 27. "INT27,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x4 26. "INT26,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x4 25. "INT25,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x4 24. "INT24,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x4 23. "INT23,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x4 22. "INT22,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x4 21. "INT21,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x4 20. "INT20,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x4 19. "INT19,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x4 18. "INT18,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x4 17. "INT17,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x4 16. "INT16,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x4 15. "INT15,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x4 14. "INT14,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x4 13. "INT13,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x4 12. "INT12,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x4 11. "INT11,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x4 10. "INT10,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x4 9. "INT9,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x4 8. "INT8,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x4 7. "INT7,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x4 6. "INT6,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x4 5. "INT5,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x4 4. "INT4,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x4 3. "INT3,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x4 2. "INT2,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." newline bitfld.long 0x4 1. "INT1,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." bitfld.long 0x4 0. "INT0,Interrupt request x" "0: The interrupt request for corresponding channel..,1: The interrupt request for corresponding channel.." line.long 0x8 "ERRH,Error Register High" bitfld.long 0x8 31. "ERR63,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x8 30. "ERR62,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x8 29. "ERR61,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x8 28. "ERR60,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x8 27. "ERR59,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x8 26. "ERR58,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x8 25. "ERR57,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x8 24. "ERR56,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x8 23. "ERR55,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x8 22. "ERR54,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x8 21. "ERR53,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x8 20. "ERR52,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x8 19. "ERR51,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x8 18. "ERR50,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x8 17. "ERR49,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x8 16. "ERR48,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x8 15. "ERR47,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x8 14. "ERR46,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x8 13. "ERR45,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x8 12. "ERR44,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x8 11. "ERR43,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x8 10. "ERR42,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x8 9. "ERR41,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x8 8. "ERR40,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x8 7. "ERR39,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x8 6. "ERR38,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x8 5. "ERR37,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x8 4. "ERR36,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x8 3. "ERR35,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x8 2. "ERR34,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0x8 1. "ERR33,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0x8 0. "ERR32,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." line.long 0xC "ERRL,Error Register Low" bitfld.long 0xC 31. "ERR31,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0xC 30. "ERR30,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0xC 29. "ERR29,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0xC 28. "ERR28,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0xC 27. "ERR27,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0xC 26. "ERR26,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0xC 25. "ERR25,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0xC 24. "ERR24,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0xC 23. "ERR23,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0xC 22. "ERR22,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0xC 21. "ERR21,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0xC 20. "ERR20,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0xC 19. "ERR19,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0xC 18. "ERR18,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0xC 17. "ERR17,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0xC 16. "ERR16,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0xC 15. "ERR15,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0xC 14. "ERR14,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0xC 13. "ERR13,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0xC 12. "ERR12,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0xC 11. "ERR11,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0xC 10. "ERR10,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0xC 9. "ERR9,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0xC 8. "ERR8,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0xC 7. "ERR7,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0xC 6. "ERR6,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0xC 5. "ERR5,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0xC 4. "ERR4,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0xC 3. "ERR3,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0xC 2. "ERR2,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." newline bitfld.long 0xC 1. "ERR1,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." bitfld.long 0xC 0. "ERR0,Error in channel x" "0: An error in the corresponding channel has not..,1: An error in the corresponding channel has.." line.long 0x10 "HRSH,Hardware Request Status Register High" bitfld.long 0x10 31. "HRS63,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x10 30. "HRS62,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x10 29. "HRS61,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x10 28. "HRS60,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x10 27. "HRS59,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x10 26. "HRS58,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x10 25. "HRS57,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x10 24. "HRS56,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x10 23. "HRS55,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x10 22. "HRS54,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x10 21. "HRS53,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x10 20. "HRS52,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x10 19. "HRS51,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x10 18. "HRS50,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x10 17. "HRS49,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x10 16. "HRS48,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x10 15. "HRS47,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x10 14. "HRS46,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x10 13. "HRS45,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x10 12. "HRS44,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x10 11. "HRS43,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x10 10. "HRS42,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x10 9. "HRS41,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x10 8. "HRS40,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x10 7. "HRS39,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x10 6. "HRS38,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x10 5. "HRS37,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x10 4. "HRS36,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x10 3. "HRS35,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x10 2. "HRS34,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x10 1. "HRS33,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x10 0. "HRS32,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." line.long 0x14 "HRSL,Hardware Request Status Register Low" bitfld.long 0x14 31. "HRS31,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x14 30. "HRS30,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x14 29. "HRS29,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x14 28. "HRS28,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x14 27. "HRS27,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x14 26. "HRS26,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x14 25. "HRS25,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x14 24. "HRS24,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x14 23. "HRS23,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x14 22. "HRS22,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x14 21. "HRS21,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x14 20. "HRS20,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x14 19. "HRS19,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x14 18. "HRS18,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x14 17. "HRS17,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x14 16. "HRS16,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x14 15. "HRS15,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x14 14. "HRS14,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x14 13. "HRS13,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x14 12. "HRS12,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x14 11. "HRS11,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x14 10. "HRS10,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x14 9. "HRS9,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x14 8. "HRS8,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x14 7. "HRS7,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x14 6. "HRS6,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x14 5. "HRS5,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x14 4. "HRS4,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x14 3. "HRS3,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x14 2. "HRS2,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." newline bitfld.long 0x14 1. "HRS1,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." bitfld.long 0x14 0. "HRS0,Hardware request status channel x" "0: A hardware service request for the corresponding..,1: A hardware service request for the corresponding.." group.byte 0x100++0x7F line.byte 0x0 "DCHPRI3,Channel n Priority register" bitfld.byte 0x0 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x0 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x0 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x0 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1 "DCHPRI2,Channel n Priority register" bitfld.byte 0x1 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x2 "DCHPRI1,Channel n Priority register" bitfld.byte 0x2 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x2 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x2 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x2 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x3 "DCHPRI0,Channel n Priority register" bitfld.byte 0x3 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x3 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x3 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x3 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x4 "DCHPRI7,Channel n Priority register" bitfld.byte 0x4 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x4 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x4 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x4 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x5 "DCHPRI6,Channel n Priority register" bitfld.byte 0x5 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x5 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x5 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x5 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x6 "DCHPRI5,Channel n Priority register" bitfld.byte 0x6 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x6 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x6 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x6 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x7 "DCHPRI4,Channel n Priority register" bitfld.byte 0x7 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x7 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x7 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x7 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x8 "DCHPRI11,Channel n Priority register" bitfld.byte 0x8 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x8 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x8 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x8 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x9 "DCHPRI10,Channel n Priority register" bitfld.byte 0x9 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x9 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x9 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x9 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xA "DCHPRI9,Channel n Priority register" bitfld.byte 0xA 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xA 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xA 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xA 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xB "DCHPRI8,Channel n Priority register" bitfld.byte 0xB 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xB 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xB 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xB 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xC "DCHPRI15,Channel n Priority register" bitfld.byte 0xC 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xC 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xC 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xC 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xD "DCHPRI14,Channel n Priority register" bitfld.byte 0xD 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xD 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xD 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xD 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xE "DCHPRI13,Channel n Priority register" bitfld.byte 0xE 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xE 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xE 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xE 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0xF "DCHPRI12,Channel n Priority register" bitfld.byte 0xF 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0xF 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0xF 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0xF 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x10 "DCHPRI19,Channel n Priority register" bitfld.byte 0x10 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x10 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x10 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x10 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x11 "DCHPRI18,Channel n Priority register" bitfld.byte 0x11 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x11 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x11 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x11 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x12 "DCHPRI17,Channel n Priority register" bitfld.byte 0x12 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x12 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x12 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x12 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x13 "DCHPRI16,Channel n Priority register" bitfld.byte 0x13 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x13 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x13 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x13 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x14 "DCHPRI23,Channel n Priority register" bitfld.byte 0x14 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x14 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x14 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x14 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x15 "DCHPRI22,Channel n Priority register" bitfld.byte 0x15 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x15 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x15 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x15 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x16 "DCHPRI21,Channel n Priority register" bitfld.byte 0x16 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x16 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x16 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x16 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x17 "DCHPRI20,Channel n Priority register" bitfld.byte 0x17 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x17 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x17 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x17 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x18 "DCHPRI27,Channel n Priority register" bitfld.byte 0x18 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x18 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x18 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x18 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x19 "DCHPRI26,Channel n Priority register" bitfld.byte 0x19 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x19 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x19 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x19 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1A "DCHPRI25,Channel n Priority register" bitfld.byte 0x1A 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1A 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1A 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1A 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1B "DCHPRI24,Channel n Priority register" bitfld.byte 0x1B 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1B 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1B 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1B 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1C "DCHPRI31,Channel n Priority register" bitfld.byte 0x1C 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1C 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1C 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1C 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1D "DCHPRI30,Channel n Priority register" bitfld.byte 0x1D 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1D 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1D 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1D 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1E "DCHPRI29,Channel n Priority register" bitfld.byte 0x1E 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1E 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1E 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1E 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x1F "DCHPRI28,Channel n Priority register" bitfld.byte 0x1F 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x1F 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x1F 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x1F 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x20 "DCHPRI35,Channel n Priority register" bitfld.byte 0x20 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x20 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x20 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x20 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x21 "DCHPRI34,Channel n Priority register" bitfld.byte 0x21 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x21 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x21 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x21 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x22 "DCHPRI33,Channel n Priority register" bitfld.byte 0x22 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x22 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x22 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x22 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x23 "DCHPRI32,Channel n Priority register" bitfld.byte 0x23 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x23 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x23 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x23 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x24 "DCHPRI39,Channel n Priority register" bitfld.byte 0x24 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x24 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x24 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x24 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x25 "DCHPRI38,Channel n Priority register" bitfld.byte 0x25 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x25 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x25 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x25 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x26 "DCHPRI37,Channel n Priority register" bitfld.byte 0x26 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x26 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x26 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x26 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x27 "DCHPRI36,Channel n Priority register" bitfld.byte 0x27 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x27 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x27 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x27 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x28 "DCHPRI43,Channel n Priority register" bitfld.byte 0x28 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x28 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x28 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x28 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x29 "DCHPRI42,Channel n Priority register" bitfld.byte 0x29 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x29 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x29 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x29 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x2A "DCHPRI41,Channel n Priority register" bitfld.byte 0x2A 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x2A 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x2A 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x2A 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x2B "DCHPRI40,Channel n Priority register" bitfld.byte 0x2B 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x2B 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x2B 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x2B 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x2C "DCHPRI47,Channel n Priority register" bitfld.byte 0x2C 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x2C 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x2C 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x2C 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x2D "DCHPRI46,Channel n Priority register" bitfld.byte 0x2D 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x2D 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x2D 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x2D 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x2E "DCHPRI45,Channel n Priority register" bitfld.byte 0x2E 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x2E 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x2E 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x2E 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x2F "DCHPRI44,Channel n Priority register" bitfld.byte 0x2F 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x2F 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x2F 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x2F 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x30 "DCHPRI51,Channel n Priority register" bitfld.byte 0x30 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x30 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x30 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x30 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x31 "DCHPRI50,Channel n Priority register" bitfld.byte 0x31 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x31 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x31 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x31 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x32 "DCHPRI49,Channel n Priority register" bitfld.byte 0x32 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x32 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x32 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x32 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x33 "DCHPRI48,Channel n Priority register" bitfld.byte 0x33 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x33 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x33 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x33 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x34 "DCHPRI55,Channel n Priority register" bitfld.byte 0x34 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x34 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x34 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x34 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x35 "DCHPRI54,Channel n Priority register" bitfld.byte 0x35 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x35 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x35 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x35 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x36 "DCHPRI53,Channel n Priority register" bitfld.byte 0x36 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x36 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x36 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x36 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x37 "DCHPRI52,Channel n Priority register" bitfld.byte 0x37 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x37 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x37 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x37 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x38 "DCHPRI59,Channel n Priority register" bitfld.byte 0x38 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x38 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x38 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x38 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x39 "DCHPRI58,Channel n Priority register" bitfld.byte 0x39 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x39 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x39 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x39 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x3A "DCHPRI57,Channel n Priority register" bitfld.byte 0x3A 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x3A 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x3A 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x3A 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x3B "DCHPRI56,Channel n Priority register" bitfld.byte 0x3B 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x3B 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x3B 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x3B 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x3C "DCHPRI63,Channel n Priority register" bitfld.byte 0x3C 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x3C 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x3C 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x3C 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x3D "DCHPRI62,Channel n Priority register" bitfld.byte 0x3D 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x3D 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x3D 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x3D 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x3E "DCHPRI61,Channel n Priority register" bitfld.byte 0x3E 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x3E 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x3E 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x3E 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x3F "DCHPRI60,Channel n Priority register" bitfld.byte 0x3F 7. "ECP,Enable channel preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.." bitfld.byte 0x3F 6. "DPA,Disable preempt ability" "0: Channel n can suspend a lower priority channel.,1: Channel n cannot suspend any channel regardless.." newline bitfld.byte 0x3F 4.--5. "GRPPRI,Channel n current group priority" "0,1,2,3" hexmask.byte 0x3F 0.--3. 1. "CHPRI,Channel n arbitration priority" line.byte 0x40 "REQSTR_ID0,Channel 0 Requester ID register" bitfld.byte 0x40 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x40 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x40 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x41 "REQSTR_ID1,Channel 1 Requester ID register" bitfld.byte 0x41 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x41 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x41 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x42 "REQSTR_ID2,Channel 2 Requester ID register" bitfld.byte 0x42 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x42 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x42 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x43 "REQSTR_ID3,Channel 3 Requester ID register" bitfld.byte 0x43 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x43 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x43 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x44 "REQSTR_ID4,Channel 4 Requester ID register" bitfld.byte 0x44 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x44 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x44 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x45 "REQSTR_ID5,Channel 5 Requester ID register" bitfld.byte 0x45 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x45 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x45 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x46 "REQSTR_ID6,Channel 6 Requester ID register" bitfld.byte 0x46 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x46 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x46 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x47 "REQSTR_ID7,Channel 7 Requester ID register" bitfld.byte 0x47 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x47 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x47 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x48 "REQSTR_ID8,Channel 8 Requester ID register" bitfld.byte 0x48 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x48 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x48 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x49 "REQSTR_ID9,Channel 9 Requester ID register" bitfld.byte 0x49 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x49 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x49 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x4A "REQSTR_ID10,Channel 10 Requester ID register" bitfld.byte 0x4A 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x4A 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x4A 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x4B "REQSTR_ID11,Channel 11 Requester ID register" bitfld.byte 0x4B 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x4B 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x4B 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x4C "REQSTR_ID12,Channel 12 Requester ID register" bitfld.byte 0x4C 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x4C 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x4C 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x4D "REQSTR_ID13,Channel 13 Requester ID register" bitfld.byte 0x4D 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x4D 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x4D 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x4E "REQSTR_ID14,Channel 14 Requester ID register" bitfld.byte 0x4E 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x4E 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x4E 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x4F "REQSTR_ID15,Channel 15 Requester ID register" bitfld.byte 0x4F 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x4F 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x4F 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x50 "REQSTR_ID16,Channel 16 Requester ID register" bitfld.byte 0x50 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x50 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x50 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x51 "REQSTR_ID17,Channel 17 Requester ID register" bitfld.byte 0x51 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x51 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x51 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x52 "REQSTR_ID18,Channel 18 Requester ID register" bitfld.byte 0x52 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x52 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x52 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x53 "REQSTR_ID19,Channel 19 Requester ID register" bitfld.byte 0x53 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x53 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x53 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x54 "REQSTR_ID20,Channel 20 Requester ID register" bitfld.byte 0x54 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x54 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x54 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x55 "REQSTR_ID21,Channel 21 Requester ID register" bitfld.byte 0x55 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x55 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x55 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x56 "REQSTR_ID22,Channel 22 Requester ID register" bitfld.byte 0x56 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x56 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x56 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x57 "REQSTR_ID23,Channel 23 Requester ID register" bitfld.byte 0x57 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x57 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x57 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x58 "REQSTR_ID24,Channel 24 Requester ID register" bitfld.byte 0x58 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x58 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x58 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x59 "REQSTR_ID25,Channel 25 Requester ID register" bitfld.byte 0x59 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x59 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x59 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x5A "REQSTR_ID26,Channel 26 Requester ID register" bitfld.byte 0x5A 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x5A 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x5A 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x5B "REQSTR_ID27,Channel 27 Requester ID register" bitfld.byte 0x5B 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x5B 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x5B 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x5C "REQSTR_ID28,Channel 28 Requester ID register" bitfld.byte 0x5C 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x5C 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x5C 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x5D "REQSTR_ID29,Channel 29 Requester ID register" bitfld.byte 0x5D 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x5D 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x5D 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x5E "REQSTR_ID30,Channel 30 Requester ID register" bitfld.byte 0x5E 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x5E 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x5E 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x5F "REQSTR_ID31,Channel 31 Requester ID register" bitfld.byte 0x5F 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x5F 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x5F 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x60 "REQSTR_ID32,Channel 32 Requester ID register" bitfld.byte 0x60 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x60 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x60 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x61 "REQSTR_ID33,Channel 33 Requester ID register" bitfld.byte 0x61 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x61 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x61 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x62 "REQSTR_ID34,Channel 34 Requester ID register" bitfld.byte 0x62 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x62 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x62 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x63 "REQSTR_ID35,Channel 35 Requester ID register" bitfld.byte 0x63 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x63 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x63 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x64 "REQSTR_ID36,Channel 36 Requester ID register" bitfld.byte 0x64 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x64 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x64 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x65 "REQSTR_ID37,Channel 37 Requester ID register" bitfld.byte 0x65 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x65 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x65 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x66 "REQSTR_ID38,Channel 38 Requester ID register" bitfld.byte 0x66 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x66 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x66 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x67 "REQSTR_ID39,Channel 39 Requester ID register" bitfld.byte 0x67 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x67 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x67 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x68 "REQSTR_ID40,Channel 40 Requester ID register" bitfld.byte 0x68 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x68 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x68 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x69 "REQSTR_ID41,Channel 41 Requester ID register" bitfld.byte 0x69 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x69 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x69 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x6A "REQSTR_ID42,Channel 42 Requester ID register" bitfld.byte 0x6A 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x6A 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x6A 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x6B "REQSTR_ID43,Channel 43 Requester ID register" bitfld.byte 0x6B 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x6B 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x6B 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x6C "REQSTR_ID44,Channel 44 Requester ID register" bitfld.byte 0x6C 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x6C 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x6C 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x6D "REQSTR_ID45,Channel 45 Requester ID register" bitfld.byte 0x6D 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x6D 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x6D 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x6E "REQSTR_ID46,Channel 46 Requester ID register" bitfld.byte 0x6E 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x6E 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x6E 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x6F "REQSTR_ID47,Channel 47 Requester ID register" bitfld.byte 0x6F 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x6F 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x6F 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x70 "REQSTR_ID48,Channel 48 Requester ID register" bitfld.byte 0x70 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x70 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x70 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x71 "REQSTR_ID49,Channel 49 Requester ID register" bitfld.byte 0x71 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x71 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x71 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x72 "REQSTR_ID50,Channel 50 Requester ID register" bitfld.byte 0x72 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x72 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x72 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x73 "REQSTR_ID51,Channel 51 Requester ID register" bitfld.byte 0x73 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x73 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x73 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x74 "REQSTR_ID52,Channel 52 Requester ID register" bitfld.byte 0x74 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x74 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x74 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x75 "REQSTR_ID53,Channel 53 Requester ID register" bitfld.byte 0x75 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x75 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x75 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x76 "REQSTR_ID54,Channel 54 Requester ID register" bitfld.byte 0x76 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x76 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x76 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x77 "REQSTR_ID55,Channel 55 Requester ID register" bitfld.byte 0x77 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x77 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x77 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x78 "REQSTR_ID56,Channel 56 Requester ID register" bitfld.byte 0x78 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x78 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x78 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x79 "REQSTR_ID57,Channel 57 Requester ID register" bitfld.byte 0x79 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x79 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x79 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x7A "REQSTR_ID58,Channel 58 Requester ID register" bitfld.byte 0x7A 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x7A 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x7A 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x7B "REQSTR_ID59,Channel 59 Requester ID register" bitfld.byte 0x7B 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x7B 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x7B 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x7C "REQSTR_ID60,Channel 60 Requester ID register" bitfld.byte 0x7C 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x7C 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x7C 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x7D "REQSTR_ID61,Channel 61 Requester ID register" bitfld.byte 0x7D 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x7D 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x7D 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x7E "REQSTR_ID62,Channel 62 Requester ID register" bitfld.byte 0x7E 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x7E 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x7E 0.--5. 1. "REQ_ID,Requester ID" line.byte 0x7F "REQSTR_ID63,Channel 63 Requester ID register" bitfld.byte 0x7F 7. "REQ_EN,Requester ID inheritance Enable" "0: Requester ID inheritance disabled.,1: Requester ID inheritance Enabled." bitfld.byte 0x7F 6. "REQ_VLD,Requester ID Valid bit" "0: The inherited 6-bit requester ID is not VALID.,1: The inherited 6-bit requester ID is VALID." newline hexmask.byte 0x7F 0.--5. 1. "REQ_ID,Requester ID" group.long 0x180++0x13 line.long 0x0 "VMID0,Channel 0 to 15 VMID Register" bitfld.long 0x0 8. "VMID_EN,VMID_0 Enable" "0: 8-bit VMID value out disabled.,1: 8-bit VMID value out enabled." hexmask.long.byte 0x0 0.--7. 1. "VMID,VMID_0 value" line.long 0x4 "VMID1,Channel 16 to 31 VMID Register" bitfld.long 0x4 8. "VMID_EN,VMID_1 Enable" "0: 8-bit VMID value out disabled.,1: 8-bit VMID value out enabled." hexmask.long.byte 0x4 0.--7. 1. "VMID,VMID_1 value" line.long 0x8 "VMID2,Channel 32 to 47 VMID Register" bitfld.long 0x8 8. "VMID_EN,VMID Enable" "0: 8-bit VMID value out disabled.,1: 8-bit VMID value out enabled." hexmask.long.byte 0x8 0.--7. 1. "VMID,VMID_2 value" line.long 0xC "VMID3,Channel 48 to 63 VMID Register" bitfld.long 0xC 8. "VMID_EN,VMID Enable" "0: 8-bit VMID value out disabled.,1: 8-bit VMID value out enabled." hexmask.long.byte 0xC 0.--7. 1. "VMID,VMID_3 value" line.long 0x10 "VMID_ERR_STATUS,Channel VMID Error Status register" bitfld.long 0x10 0. "VMID_ERR,VMID error" "0: No Non-Hypervisor Access to eDMA_VMID_n register,1: Transfer Error for Non-Hypervisor Access to.." group.long 0x1000++0x3 line.long 0x0 "TCD0_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1004++0x3 line.word 0x0 "TCD0_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD0_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1008++0x3 line.long 0x0 "TCD0_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1008++0x3 line.long 0x0 "TCD0_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1008++0xB line.long 0x0 "TCD0_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD0_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD0_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1014++0x3 line.word 0x0 "TCD0_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1016++0x1 line.word 0x0 "TCD0_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1018++0x3 line.long 0x0 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x101C++0x3 line.word 0x0 "TCD0_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD0_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x101E++0x1 line.word 0x0 "TCD0_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1020++0x3 line.long 0x0 "TCD1_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1024++0x3 line.word 0x0 "TCD1_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD1_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1028++0x3 line.long 0x0 "TCD1_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1028++0x3 line.long 0x0 "TCD1_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1028++0xB line.long 0x0 "TCD1_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD1_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD1_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1034++0x3 line.word 0x0 "TCD1_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1036++0x1 line.word 0x0 "TCD1_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1038++0x3 line.long 0x0 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x103C++0x3 line.word 0x0 "TCD1_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD1_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x103E++0x1 line.word 0x0 "TCD1_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1040++0x3 line.long 0x0 "TCD2_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1044++0x3 line.word 0x0 "TCD2_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD2_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1048++0x3 line.long 0x0 "TCD2_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1048++0x3 line.long 0x0 "TCD2_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1048++0xB line.long 0x0 "TCD2_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD2_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD2_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1054++0x3 line.word 0x0 "TCD2_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1056++0x1 line.word 0x0 "TCD2_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1058++0x3 line.long 0x0 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x105C++0x3 line.word 0x0 "TCD2_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD2_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x105E++0x1 line.word 0x0 "TCD2_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1060++0x3 line.long 0x0 "TCD3_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1064++0x3 line.word 0x0 "TCD3_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD3_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1068++0x3 line.long 0x0 "TCD3_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1068++0x3 line.long 0x0 "TCD3_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1068++0xB line.long 0x0 "TCD3_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD3_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD3_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1074++0x3 line.word 0x0 "TCD3_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1076++0x1 line.word 0x0 "TCD3_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1078++0x3 line.long 0x0 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x107C++0x3 line.word 0x0 "TCD3_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD3_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x107E++0x1 line.word 0x0 "TCD3_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1080++0x3 line.long 0x0 "TCD4_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1084++0x3 line.word 0x0 "TCD4_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD4_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1088++0x3 line.long 0x0 "TCD4_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1088++0x3 line.long 0x0 "TCD4_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1088++0xB line.long 0x0 "TCD4_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD4_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD4_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1094++0x3 line.word 0x0 "TCD4_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD4_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1096++0x1 line.word 0x0 "TCD4_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1098++0x3 line.long 0x0 "TCD4_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x109C++0x3 line.word 0x0 "TCD4_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD4_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x109E++0x1 line.word 0x0 "TCD4_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x10A0++0x3 line.long 0x0 "TCD5_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x10A4++0x3 line.word 0x0 "TCD5_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD5_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x10A8++0x3 line.long 0x0 "TCD5_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x10A8++0x3 line.long 0x0 "TCD5_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x10A8++0xB line.long 0x0 "TCD5_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD5_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD5_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x10B4++0x3 line.word 0x0 "TCD5_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD5_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x10B6++0x1 line.word 0x0 "TCD5_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x10B8++0x3 line.long 0x0 "TCD5_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x10BC++0x3 line.word 0x0 "TCD5_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD5_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x10BE++0x1 line.word 0x0 "TCD5_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x10C0++0x3 line.long 0x0 "TCD6_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x10C4++0x3 line.word 0x0 "TCD6_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD6_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x10C8++0x3 line.long 0x0 "TCD6_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x10C8++0x3 line.long 0x0 "TCD6_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x10C8++0xB line.long 0x0 "TCD6_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD6_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD6_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x10D4++0x3 line.word 0x0 "TCD6_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD6_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x10D6++0x1 line.word 0x0 "TCD6_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x10D8++0x3 line.long 0x0 "TCD6_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x10DC++0x3 line.word 0x0 "TCD6_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD6_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x10DE++0x1 line.word 0x0 "TCD6_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x10E0++0x3 line.long 0x0 "TCD7_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x10E4++0x3 line.word 0x0 "TCD7_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD7_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x10E8++0x3 line.long 0x0 "TCD7_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x10E8++0x3 line.long 0x0 "TCD7_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x10E8++0xB line.long 0x0 "TCD7_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD7_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD7_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x10F4++0x3 line.word 0x0 "TCD7_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD7_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x10F6++0x1 line.word 0x0 "TCD7_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x10F8++0x3 line.long 0x0 "TCD7_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x10FC++0x3 line.word 0x0 "TCD7_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD7_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x10FE++0x1 line.word 0x0 "TCD7_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1100++0x3 line.long 0x0 "TCD8_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1104++0x3 line.word 0x0 "TCD8_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD8_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1108++0x3 line.long 0x0 "TCD8_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1108++0x3 line.long 0x0 "TCD8_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1108++0xB line.long 0x0 "TCD8_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD8_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD8_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1114++0x3 line.word 0x0 "TCD8_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD8_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1116++0x1 line.word 0x0 "TCD8_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1118++0x3 line.long 0x0 "TCD8_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x111C++0x3 line.word 0x0 "TCD8_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD8_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x111E++0x1 line.word 0x0 "TCD8_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1120++0x3 line.long 0x0 "TCD9_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1124++0x3 line.word 0x0 "TCD9_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD9_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1128++0x3 line.long 0x0 "TCD9_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1128++0x3 line.long 0x0 "TCD9_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1128++0xB line.long 0x0 "TCD9_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD9_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD9_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1134++0x3 line.word 0x0 "TCD9_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD9_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1136++0x1 line.word 0x0 "TCD9_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1138++0x3 line.long 0x0 "TCD9_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x113C++0x3 line.word 0x0 "TCD9_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD9_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x113E++0x1 line.word 0x0 "TCD9_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1140++0x3 line.long 0x0 "TCD10_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1144++0x3 line.word 0x0 "TCD10_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD10_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1148++0x3 line.long 0x0 "TCD10_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1148++0x3 line.long 0x0 "TCD10_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1148++0xB line.long 0x0 "TCD10_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD10_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD10_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1154++0x3 line.word 0x0 "TCD10_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD10_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1156++0x1 line.word 0x0 "TCD10_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1158++0x3 line.long 0x0 "TCD10_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x115C++0x3 line.word 0x0 "TCD10_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD10_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x115E++0x1 line.word 0x0 "TCD10_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1160++0x3 line.long 0x0 "TCD11_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1164++0x3 line.word 0x0 "TCD11_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD11_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1168++0x3 line.long 0x0 "TCD11_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1168++0x3 line.long 0x0 "TCD11_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1168++0xB line.long 0x0 "TCD11_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD11_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD11_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1174++0x3 line.word 0x0 "TCD11_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD11_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1176++0x1 line.word 0x0 "TCD11_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1178++0x3 line.long 0x0 "TCD11_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x117C++0x3 line.word 0x0 "TCD11_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD11_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x117E++0x1 line.word 0x0 "TCD11_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1180++0x3 line.long 0x0 "TCD12_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1184++0x3 line.word 0x0 "TCD12_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD12_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1188++0x3 line.long 0x0 "TCD12_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1188++0x3 line.long 0x0 "TCD12_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1188++0xB line.long 0x0 "TCD12_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD12_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD12_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1194++0x3 line.word 0x0 "TCD12_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD12_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1196++0x1 line.word 0x0 "TCD12_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1198++0x3 line.long 0x0 "TCD12_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x119C++0x3 line.word 0x0 "TCD12_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD12_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x119E++0x1 line.word 0x0 "TCD12_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x11A0++0x3 line.long 0x0 "TCD13_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x11A4++0x3 line.word 0x0 "TCD13_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD13_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x11A8++0x3 line.long 0x0 "TCD13_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x11A8++0x3 line.long 0x0 "TCD13_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x11A8++0xB line.long 0x0 "TCD13_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD13_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD13_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x11B4++0x3 line.word 0x0 "TCD13_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD13_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x11B6++0x1 line.word 0x0 "TCD13_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x11B8++0x3 line.long 0x0 "TCD13_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x11BC++0x3 line.word 0x0 "TCD13_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD13_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x11BE++0x1 line.word 0x0 "TCD13_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x11C0++0x3 line.long 0x0 "TCD14_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x11C4++0x3 line.word 0x0 "TCD14_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD14_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x11C8++0x3 line.long 0x0 "TCD14_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x11C8++0x3 line.long 0x0 "TCD14_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x11C8++0xB line.long 0x0 "TCD14_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD14_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD14_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x11D4++0x3 line.word 0x0 "TCD14_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD14_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x11D6++0x1 line.word 0x0 "TCD14_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x11D8++0x3 line.long 0x0 "TCD14_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x11DC++0x3 line.word 0x0 "TCD14_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD14_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x11DE++0x1 line.word 0x0 "TCD14_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x11E0++0x3 line.long 0x0 "TCD15_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x11E4++0x3 line.word 0x0 "TCD15_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD15_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x11E8++0x3 line.long 0x0 "TCD15_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x11E8++0x3 line.long 0x0 "TCD15_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x11E8++0xB line.long 0x0 "TCD15_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD15_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD15_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x11F4++0x3 line.word 0x0 "TCD15_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD15_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x11F6++0x1 line.word 0x0 "TCD15_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x11F8++0x3 line.long 0x0 "TCD15_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x11FC++0x3 line.word 0x0 "TCD15_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD15_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x11FE++0x1 line.word 0x0 "TCD15_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1200++0x3 line.long 0x0 "TCD16_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1204++0x3 line.word 0x0 "TCD16_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD16_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1208++0x3 line.long 0x0 "TCD16_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1208++0x3 line.long 0x0 "TCD16_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1208++0xB line.long 0x0 "TCD16_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD16_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD16_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1214++0x3 line.word 0x0 "TCD16_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD16_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1216++0x1 line.word 0x0 "TCD16_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1218++0x3 line.long 0x0 "TCD16_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x121C++0x3 line.word 0x0 "TCD16_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD16_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x121E++0x1 line.word 0x0 "TCD16_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1220++0x3 line.long 0x0 "TCD17_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1224++0x3 line.word 0x0 "TCD17_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD17_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1228++0x3 line.long 0x0 "TCD17_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1228++0x3 line.long 0x0 "TCD17_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1228++0xB line.long 0x0 "TCD17_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD17_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD17_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1234++0x3 line.word 0x0 "TCD17_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD17_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1236++0x1 line.word 0x0 "TCD17_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1238++0x3 line.long 0x0 "TCD17_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x123C++0x3 line.word 0x0 "TCD17_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD17_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x123E++0x1 line.word 0x0 "TCD17_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1240++0x3 line.long 0x0 "TCD18_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1244++0x3 line.word 0x0 "TCD18_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD18_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1248++0x3 line.long 0x0 "TCD18_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1248++0x3 line.long 0x0 "TCD18_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1248++0xB line.long 0x0 "TCD18_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD18_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD18_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1254++0x3 line.word 0x0 "TCD18_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD18_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1256++0x1 line.word 0x0 "TCD18_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1258++0x3 line.long 0x0 "TCD18_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x125C++0x3 line.word 0x0 "TCD18_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD18_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x125E++0x1 line.word 0x0 "TCD18_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1260++0x3 line.long 0x0 "TCD19_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1264++0x3 line.word 0x0 "TCD19_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD19_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1268++0x3 line.long 0x0 "TCD19_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1268++0x3 line.long 0x0 "TCD19_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1268++0xB line.long 0x0 "TCD19_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD19_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD19_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1274++0x3 line.word 0x0 "TCD19_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD19_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1276++0x1 line.word 0x0 "TCD19_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1278++0x3 line.long 0x0 "TCD19_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x127C++0x3 line.word 0x0 "TCD19_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD19_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x127E++0x1 line.word 0x0 "TCD19_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1280++0x3 line.long 0x0 "TCD20_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1284++0x3 line.word 0x0 "TCD20_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD20_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1288++0x3 line.long 0x0 "TCD20_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1288++0x3 line.long 0x0 "TCD20_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1288++0xB line.long 0x0 "TCD20_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD20_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD20_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1294++0x3 line.word 0x0 "TCD20_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD20_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1296++0x1 line.word 0x0 "TCD20_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1298++0x3 line.long 0x0 "TCD20_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x129C++0x3 line.word 0x0 "TCD20_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD20_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x129E++0x1 line.word 0x0 "TCD20_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x12A0++0x3 line.long 0x0 "TCD21_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x12A4++0x3 line.word 0x0 "TCD21_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD21_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x12A8++0x3 line.long 0x0 "TCD21_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x12A8++0x3 line.long 0x0 "TCD21_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x12A8++0xB line.long 0x0 "TCD21_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD21_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD21_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x12B4++0x3 line.word 0x0 "TCD21_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD21_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x12B6++0x1 line.word 0x0 "TCD21_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x12B8++0x3 line.long 0x0 "TCD21_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x12BC++0x3 line.word 0x0 "TCD21_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD21_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x12BE++0x1 line.word 0x0 "TCD21_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x12C0++0x3 line.long 0x0 "TCD22_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x12C4++0x3 line.word 0x0 "TCD22_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD22_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x12C8++0x3 line.long 0x0 "TCD22_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x12C8++0x3 line.long 0x0 "TCD22_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x12C8++0xB line.long 0x0 "TCD22_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD22_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD22_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x12D4++0x3 line.word 0x0 "TCD22_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD22_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x12D6++0x1 line.word 0x0 "TCD22_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x12D8++0x3 line.long 0x0 "TCD22_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x12DC++0x3 line.word 0x0 "TCD22_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD22_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x12DE++0x1 line.word 0x0 "TCD22_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x12E0++0x3 line.long 0x0 "TCD23_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x12E4++0x3 line.word 0x0 "TCD23_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD23_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x12E8++0x3 line.long 0x0 "TCD23_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x12E8++0x3 line.long 0x0 "TCD23_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x12E8++0xB line.long 0x0 "TCD23_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD23_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD23_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x12F4++0x3 line.word 0x0 "TCD23_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD23_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x12F6++0x1 line.word 0x0 "TCD23_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x12F8++0x3 line.long 0x0 "TCD23_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x12FC++0x3 line.word 0x0 "TCD23_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD23_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x12FE++0x1 line.word 0x0 "TCD23_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1300++0x3 line.long 0x0 "TCD24_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1304++0x3 line.word 0x0 "TCD24_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD24_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1308++0x3 line.long 0x0 "TCD24_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1308++0x3 line.long 0x0 "TCD24_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1308++0xB line.long 0x0 "TCD24_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD24_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD24_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1314++0x3 line.word 0x0 "TCD24_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD24_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1316++0x1 line.word 0x0 "TCD24_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1318++0x3 line.long 0x0 "TCD24_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x131C++0x3 line.word 0x0 "TCD24_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD24_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x131E++0x1 line.word 0x0 "TCD24_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1320++0x3 line.long 0x0 "TCD25_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1324++0x3 line.word 0x0 "TCD25_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD25_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1328++0x3 line.long 0x0 "TCD25_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1328++0x3 line.long 0x0 "TCD25_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1328++0xB line.long 0x0 "TCD25_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD25_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD25_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1334++0x3 line.word 0x0 "TCD25_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD25_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1336++0x1 line.word 0x0 "TCD25_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1338++0x3 line.long 0x0 "TCD25_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x133C++0x3 line.word 0x0 "TCD25_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD25_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x133E++0x1 line.word 0x0 "TCD25_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1340++0x3 line.long 0x0 "TCD26_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1344++0x3 line.word 0x0 "TCD26_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD26_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1348++0x3 line.long 0x0 "TCD26_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1348++0x3 line.long 0x0 "TCD26_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1348++0xB line.long 0x0 "TCD26_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD26_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD26_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1354++0x3 line.word 0x0 "TCD26_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD26_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1356++0x1 line.word 0x0 "TCD26_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1358++0x3 line.long 0x0 "TCD26_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x135C++0x3 line.word 0x0 "TCD26_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD26_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x135E++0x1 line.word 0x0 "TCD26_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1360++0x3 line.long 0x0 "TCD27_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1364++0x3 line.word 0x0 "TCD27_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD27_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1368++0x3 line.long 0x0 "TCD27_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1368++0x3 line.long 0x0 "TCD27_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1368++0xB line.long 0x0 "TCD27_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD27_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD27_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1374++0x3 line.word 0x0 "TCD27_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD27_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1376++0x1 line.word 0x0 "TCD27_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1378++0x3 line.long 0x0 "TCD27_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x137C++0x3 line.word 0x0 "TCD27_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD27_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x137E++0x1 line.word 0x0 "TCD27_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1380++0x3 line.long 0x0 "TCD28_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1384++0x3 line.word 0x0 "TCD28_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD28_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1388++0x3 line.long 0x0 "TCD28_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1388++0x3 line.long 0x0 "TCD28_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1388++0xB line.long 0x0 "TCD28_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD28_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD28_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1394++0x3 line.word 0x0 "TCD28_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD28_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1396++0x1 line.word 0x0 "TCD28_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1398++0x3 line.long 0x0 "TCD28_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x139C++0x3 line.word 0x0 "TCD28_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD28_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x139E++0x1 line.word 0x0 "TCD28_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x13A0++0x3 line.long 0x0 "TCD29_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x13A4++0x3 line.word 0x0 "TCD29_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD29_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x13A8++0x3 line.long 0x0 "TCD29_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x13A8++0x3 line.long 0x0 "TCD29_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x13A8++0xB line.long 0x0 "TCD29_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD29_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD29_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x13B4++0x3 line.word 0x0 "TCD29_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD29_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x13B6++0x1 line.word 0x0 "TCD29_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x13B8++0x3 line.long 0x0 "TCD29_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x13BC++0x3 line.word 0x0 "TCD29_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD29_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x13BE++0x1 line.word 0x0 "TCD29_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x13C0++0x3 line.long 0x0 "TCD30_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x13C4++0x3 line.word 0x0 "TCD30_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD30_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x13C8++0x3 line.long 0x0 "TCD30_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x13C8++0x3 line.long 0x0 "TCD30_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x13C8++0xB line.long 0x0 "TCD30_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD30_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD30_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x13D4++0x3 line.word 0x0 "TCD30_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD30_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x13D6++0x1 line.word 0x0 "TCD30_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x13D8++0x3 line.long 0x0 "TCD30_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x13DC++0x3 line.word 0x0 "TCD30_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD30_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x13DE++0x1 line.word 0x0 "TCD30_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x13E0++0x3 line.long 0x0 "TCD31_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x13E4++0x3 line.word 0x0 "TCD31_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD31_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x13E8++0x3 line.long 0x0 "TCD31_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x13E8++0x3 line.long 0x0 "TCD31_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x13E8++0xB line.long 0x0 "TCD31_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD31_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD31_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x13F4++0x3 line.word 0x0 "TCD31_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD31_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x13F6++0x1 line.word 0x0 "TCD31_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x13F8++0x3 line.long 0x0 "TCD31_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x13FC++0x3 line.word 0x0 "TCD31_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD31_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x13FE++0x1 line.word 0x0 "TCD31_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1400++0x3 line.long 0x0 "TCD32_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1404++0x3 line.word 0x0 "TCD32_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD32_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1408++0x3 line.long 0x0 "TCD32_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1408++0x3 line.long 0x0 "TCD32_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1408++0xB line.long 0x0 "TCD32_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD32_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD32_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1414++0x3 line.word 0x0 "TCD32_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD32_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1416++0x1 line.word 0x0 "TCD32_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1418++0x3 line.long 0x0 "TCD32_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x141C++0x3 line.word 0x0 "TCD32_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD32_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x141E++0x1 line.word 0x0 "TCD32_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1420++0x3 line.long 0x0 "TCD33_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1424++0x3 line.word 0x0 "TCD33_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD33_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1428++0x3 line.long 0x0 "TCD33_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1428++0x3 line.long 0x0 "TCD33_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1428++0xB line.long 0x0 "TCD33_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD33_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD33_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1434++0x3 line.word 0x0 "TCD33_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD33_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1436++0x1 line.word 0x0 "TCD33_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1438++0x3 line.long 0x0 "TCD33_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x143C++0x3 line.word 0x0 "TCD33_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD33_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x143E++0x1 line.word 0x0 "TCD33_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1440++0x3 line.long 0x0 "TCD34_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1444++0x3 line.word 0x0 "TCD34_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD34_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1448++0x3 line.long 0x0 "TCD34_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1448++0x3 line.long 0x0 "TCD34_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1448++0xB line.long 0x0 "TCD34_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD34_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD34_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1454++0x3 line.word 0x0 "TCD34_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD34_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1456++0x1 line.word 0x0 "TCD34_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1458++0x3 line.long 0x0 "TCD34_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x145C++0x3 line.word 0x0 "TCD34_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD34_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x145E++0x1 line.word 0x0 "TCD34_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1460++0x3 line.long 0x0 "TCD35_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1464++0x3 line.word 0x0 "TCD35_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD35_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1468++0x3 line.long 0x0 "TCD35_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1468++0x3 line.long 0x0 "TCD35_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1468++0xB line.long 0x0 "TCD35_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD35_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD35_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1474++0x3 line.word 0x0 "TCD35_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD35_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1476++0x1 line.word 0x0 "TCD35_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1478++0x3 line.long 0x0 "TCD35_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x147C++0x3 line.word 0x0 "TCD35_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD35_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x147E++0x1 line.word 0x0 "TCD35_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1480++0x3 line.long 0x0 "TCD36_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1484++0x3 line.word 0x0 "TCD36_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD36_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1488++0x3 line.long 0x0 "TCD36_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1488++0x3 line.long 0x0 "TCD36_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1488++0xB line.long 0x0 "TCD36_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD36_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD36_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1494++0x3 line.word 0x0 "TCD36_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD36_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1496++0x1 line.word 0x0 "TCD36_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1498++0x3 line.long 0x0 "TCD36_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x149C++0x3 line.word 0x0 "TCD36_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD36_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x149E++0x1 line.word 0x0 "TCD36_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x14A0++0x3 line.long 0x0 "TCD37_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x14A4++0x3 line.word 0x0 "TCD37_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD37_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x14A8++0x3 line.long 0x0 "TCD37_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x14A8++0x3 line.long 0x0 "TCD37_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x14A8++0xB line.long 0x0 "TCD37_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD37_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD37_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x14B4++0x3 line.word 0x0 "TCD37_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD37_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x14B6++0x1 line.word 0x0 "TCD37_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x14B8++0x3 line.long 0x0 "TCD37_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x14BC++0x3 line.word 0x0 "TCD37_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD37_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x14BE++0x1 line.word 0x0 "TCD37_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x14C0++0x3 line.long 0x0 "TCD38_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x14C4++0x3 line.word 0x0 "TCD38_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD38_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x14C8++0x3 line.long 0x0 "TCD38_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x14C8++0x3 line.long 0x0 "TCD38_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x14C8++0xB line.long 0x0 "TCD38_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD38_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD38_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x14D4++0x3 line.word 0x0 "TCD38_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD38_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x14D6++0x1 line.word 0x0 "TCD38_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x14D8++0x3 line.long 0x0 "TCD38_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x14DC++0x3 line.word 0x0 "TCD38_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD38_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x14DE++0x1 line.word 0x0 "TCD38_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x14E0++0x3 line.long 0x0 "TCD39_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x14E4++0x3 line.word 0x0 "TCD39_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD39_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x14E8++0x3 line.long 0x0 "TCD39_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x14E8++0x3 line.long 0x0 "TCD39_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x14E8++0xB line.long 0x0 "TCD39_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD39_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD39_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x14F4++0x3 line.word 0x0 "TCD39_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD39_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x14F6++0x1 line.word 0x0 "TCD39_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x14F8++0x3 line.long 0x0 "TCD39_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x14FC++0x3 line.word 0x0 "TCD39_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD39_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x14FE++0x1 line.word 0x0 "TCD39_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1500++0x3 line.long 0x0 "TCD40_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1504++0x3 line.word 0x0 "TCD40_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD40_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1508++0x3 line.long 0x0 "TCD40_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1508++0x3 line.long 0x0 "TCD40_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1508++0xB line.long 0x0 "TCD40_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD40_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD40_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1514++0x3 line.word 0x0 "TCD40_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD40_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1516++0x1 line.word 0x0 "TCD40_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1518++0x3 line.long 0x0 "TCD40_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x151C++0x3 line.word 0x0 "TCD40_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD40_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x151E++0x1 line.word 0x0 "TCD40_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1520++0x3 line.long 0x0 "TCD41_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1524++0x3 line.word 0x0 "TCD41_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD41_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1528++0x3 line.long 0x0 "TCD41_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1528++0x3 line.long 0x0 "TCD41_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1528++0xB line.long 0x0 "TCD41_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD41_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD41_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1534++0x3 line.word 0x0 "TCD41_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD41_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1536++0x1 line.word 0x0 "TCD41_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1538++0x3 line.long 0x0 "TCD41_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x153C++0x3 line.word 0x0 "TCD41_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD41_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x153E++0x1 line.word 0x0 "TCD41_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1540++0x3 line.long 0x0 "TCD42_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1544++0x3 line.word 0x0 "TCD42_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD42_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1548++0x3 line.long 0x0 "TCD42_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1548++0x3 line.long 0x0 "TCD42_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1548++0xB line.long 0x0 "TCD42_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD42_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD42_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1554++0x3 line.word 0x0 "TCD42_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD42_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1556++0x1 line.word 0x0 "TCD42_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1558++0x3 line.long 0x0 "TCD42_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x155C++0x3 line.word 0x0 "TCD42_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD42_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x155E++0x1 line.word 0x0 "TCD42_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1560++0x3 line.long 0x0 "TCD43_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1564++0x3 line.word 0x0 "TCD43_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD43_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1568++0x3 line.long 0x0 "TCD43_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1568++0x3 line.long 0x0 "TCD43_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1568++0xB line.long 0x0 "TCD43_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD43_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD43_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1574++0x3 line.word 0x0 "TCD43_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD43_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1576++0x1 line.word 0x0 "TCD43_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1578++0x3 line.long 0x0 "TCD43_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x157C++0x3 line.word 0x0 "TCD43_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD43_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x157E++0x1 line.word 0x0 "TCD43_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1580++0x3 line.long 0x0 "TCD44_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1584++0x3 line.word 0x0 "TCD44_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD44_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1588++0x3 line.long 0x0 "TCD44_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1588++0x3 line.long 0x0 "TCD44_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1588++0xB line.long 0x0 "TCD44_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD44_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD44_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1594++0x3 line.word 0x0 "TCD44_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD44_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1596++0x1 line.word 0x0 "TCD44_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1598++0x3 line.long 0x0 "TCD44_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x159C++0x3 line.word 0x0 "TCD44_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD44_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x159E++0x1 line.word 0x0 "TCD44_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x15A0++0x3 line.long 0x0 "TCD45_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x15A4++0x3 line.word 0x0 "TCD45_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD45_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x15A8++0x3 line.long 0x0 "TCD45_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x15A8++0x3 line.long 0x0 "TCD45_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x15A8++0xB line.long 0x0 "TCD45_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD45_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD45_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x15B4++0x3 line.word 0x0 "TCD45_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD45_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x15B6++0x1 line.word 0x0 "TCD45_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x15B8++0x3 line.long 0x0 "TCD45_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x15BC++0x3 line.word 0x0 "TCD45_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD45_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x15BE++0x1 line.word 0x0 "TCD45_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x15C0++0x3 line.long 0x0 "TCD46_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x15C4++0x3 line.word 0x0 "TCD46_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD46_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x15C8++0x3 line.long 0x0 "TCD46_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x15C8++0x3 line.long 0x0 "TCD46_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x15C8++0xB line.long 0x0 "TCD46_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD46_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD46_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x15D4++0x3 line.word 0x0 "TCD46_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD46_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x15D6++0x1 line.word 0x0 "TCD46_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x15D8++0x3 line.long 0x0 "TCD46_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x15DC++0x3 line.word 0x0 "TCD46_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD46_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x15DE++0x1 line.word 0x0 "TCD46_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x15E0++0x3 line.long 0x0 "TCD47_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x15E4++0x3 line.word 0x0 "TCD47_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD47_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x15E8++0x3 line.long 0x0 "TCD47_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x15E8++0x3 line.long 0x0 "TCD47_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x15E8++0xB line.long 0x0 "TCD47_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD47_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD47_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x15F4++0x3 line.word 0x0 "TCD47_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD47_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x15F6++0x1 line.word 0x0 "TCD47_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x15F8++0x3 line.long 0x0 "TCD47_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x15FC++0x3 line.word 0x0 "TCD47_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD47_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x15FE++0x1 line.word 0x0 "TCD47_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1600++0x3 line.long 0x0 "TCD48_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1604++0x3 line.word 0x0 "TCD48_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD48_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1608++0x3 line.long 0x0 "TCD48_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1608++0x3 line.long 0x0 "TCD48_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1608++0xB line.long 0x0 "TCD48_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD48_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD48_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1614++0x3 line.word 0x0 "TCD48_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD48_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1616++0x1 line.word 0x0 "TCD48_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1618++0x3 line.long 0x0 "TCD48_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x161C++0x3 line.word 0x0 "TCD48_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD48_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x161E++0x1 line.word 0x0 "TCD48_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1620++0x3 line.long 0x0 "TCD49_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1624++0x3 line.word 0x0 "TCD49_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD49_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1628++0x3 line.long 0x0 "TCD49_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1628++0x3 line.long 0x0 "TCD49_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1628++0xB line.long 0x0 "TCD49_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD49_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD49_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1634++0x3 line.word 0x0 "TCD49_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD49_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1636++0x1 line.word 0x0 "TCD49_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1638++0x3 line.long 0x0 "TCD49_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x163C++0x3 line.word 0x0 "TCD49_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD49_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x163E++0x1 line.word 0x0 "TCD49_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1640++0x3 line.long 0x0 "TCD50_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1644++0x3 line.word 0x0 "TCD50_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD50_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1648++0x3 line.long 0x0 "TCD50_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1648++0x3 line.long 0x0 "TCD50_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1648++0xB line.long 0x0 "TCD50_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD50_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD50_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1654++0x3 line.word 0x0 "TCD50_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD50_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1656++0x1 line.word 0x0 "TCD50_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1658++0x3 line.long 0x0 "TCD50_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x165C++0x3 line.word 0x0 "TCD50_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD50_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x165E++0x1 line.word 0x0 "TCD50_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1660++0x3 line.long 0x0 "TCD51_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1664++0x3 line.word 0x0 "TCD51_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD51_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1668++0x3 line.long 0x0 "TCD51_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1668++0x3 line.long 0x0 "TCD51_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1668++0xB line.long 0x0 "TCD51_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD51_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD51_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1674++0x3 line.word 0x0 "TCD51_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD51_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1676++0x1 line.word 0x0 "TCD51_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1678++0x3 line.long 0x0 "TCD51_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x167C++0x3 line.word 0x0 "TCD51_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD51_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x167E++0x1 line.word 0x0 "TCD51_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1680++0x3 line.long 0x0 "TCD52_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1684++0x3 line.word 0x0 "TCD52_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD52_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1688++0x3 line.long 0x0 "TCD52_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1688++0x3 line.long 0x0 "TCD52_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1688++0xB line.long 0x0 "TCD52_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD52_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD52_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1694++0x3 line.word 0x0 "TCD52_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD52_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1696++0x1 line.word 0x0 "TCD52_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1698++0x3 line.long 0x0 "TCD52_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x169C++0x3 line.word 0x0 "TCD52_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD52_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x169E++0x1 line.word 0x0 "TCD52_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x16A0++0x3 line.long 0x0 "TCD53_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x16A4++0x3 line.word 0x0 "TCD53_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD53_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x16A8++0x3 line.long 0x0 "TCD53_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x16A8++0x3 line.long 0x0 "TCD53_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x16A8++0xB line.long 0x0 "TCD53_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD53_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD53_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x16B4++0x3 line.word 0x0 "TCD53_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD53_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x16B6++0x1 line.word 0x0 "TCD53_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x16B8++0x3 line.long 0x0 "TCD53_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x16BC++0x3 line.word 0x0 "TCD53_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD53_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x16BE++0x1 line.word 0x0 "TCD53_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x16C0++0x3 line.long 0x0 "TCD54_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x16C4++0x3 line.word 0x0 "TCD54_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD54_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x16C8++0x3 line.long 0x0 "TCD54_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x16C8++0x3 line.long 0x0 "TCD54_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x16C8++0xB line.long 0x0 "TCD54_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD54_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD54_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x16D4++0x3 line.word 0x0 "TCD54_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD54_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x16D6++0x1 line.word 0x0 "TCD54_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x16D8++0x3 line.long 0x0 "TCD54_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x16DC++0x3 line.word 0x0 "TCD54_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD54_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x16DE++0x1 line.word 0x0 "TCD54_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x16E0++0x3 line.long 0x0 "TCD55_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x16E4++0x3 line.word 0x0 "TCD55_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD55_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x16E8++0x3 line.long 0x0 "TCD55_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x16E8++0x3 line.long 0x0 "TCD55_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x16E8++0xB line.long 0x0 "TCD55_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD55_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD55_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x16F4++0x3 line.word 0x0 "TCD55_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD55_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x16F6++0x1 line.word 0x0 "TCD55_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x16F8++0x3 line.long 0x0 "TCD55_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x16FC++0x3 line.word 0x0 "TCD55_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD55_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x16FE++0x1 line.word 0x0 "TCD55_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1700++0x3 line.long 0x0 "TCD56_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1704++0x3 line.word 0x0 "TCD56_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD56_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1708++0x3 line.long 0x0 "TCD56_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1708++0x3 line.long 0x0 "TCD56_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1708++0xB line.long 0x0 "TCD56_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD56_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD56_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1714++0x3 line.word 0x0 "TCD56_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD56_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1716++0x1 line.word 0x0 "TCD56_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1718++0x3 line.long 0x0 "TCD56_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x171C++0x3 line.word 0x0 "TCD56_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD56_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x171E++0x1 line.word 0x0 "TCD56_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1720++0x3 line.long 0x0 "TCD57_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1724++0x3 line.word 0x0 "TCD57_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD57_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1728++0x3 line.long 0x0 "TCD57_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1728++0x3 line.long 0x0 "TCD57_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1728++0xB line.long 0x0 "TCD57_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD57_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD57_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1734++0x3 line.word 0x0 "TCD57_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD57_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1736++0x1 line.word 0x0 "TCD57_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1738++0x3 line.long 0x0 "TCD57_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x173C++0x3 line.word 0x0 "TCD57_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD57_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x173E++0x1 line.word 0x0 "TCD57_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1740++0x3 line.long 0x0 "TCD58_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1744++0x3 line.word 0x0 "TCD58_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD58_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1748++0x3 line.long 0x0 "TCD58_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1748++0x3 line.long 0x0 "TCD58_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1748++0xB line.long 0x0 "TCD58_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD58_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD58_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1754++0x3 line.word 0x0 "TCD58_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD58_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1756++0x1 line.word 0x0 "TCD58_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1758++0x3 line.long 0x0 "TCD58_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x175C++0x3 line.word 0x0 "TCD58_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD58_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x175E++0x1 line.word 0x0 "TCD58_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1760++0x3 line.long 0x0 "TCD59_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1764++0x3 line.word 0x0 "TCD59_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD59_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1768++0x3 line.long 0x0 "TCD59_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1768++0x3 line.long 0x0 "TCD59_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1768++0xB line.long 0x0 "TCD59_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD59_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD59_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1774++0x3 line.word 0x0 "TCD59_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD59_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1776++0x1 line.word 0x0 "TCD59_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1778++0x3 line.long 0x0 "TCD59_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x177C++0x3 line.word 0x0 "TCD59_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD59_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x177E++0x1 line.word 0x0 "TCD59_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x1780++0x3 line.long 0x0 "TCD60_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x1784++0x3 line.word 0x0 "TCD60_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD60_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x1788++0x3 line.long 0x0 "TCD60_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x1788++0x3 line.long 0x0 "TCD60_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x1788++0xB line.long 0x0 "TCD60_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD60_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD60_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x1794++0x3 line.word 0x0 "TCD60_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD60_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x1796++0x1 line.word 0x0 "TCD60_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x1798++0x3 line.long 0x0 "TCD60_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x179C++0x3 line.word 0x0 "TCD60_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD60_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x179E++0x1 line.word 0x0 "TCD60_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x17A0++0x3 line.long 0x0 "TCD61_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x17A4++0x3 line.word 0x0 "TCD61_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD61_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x17A8++0x3 line.long 0x0 "TCD61_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x17A8++0x3 line.long 0x0 "TCD61_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x17A8++0xB line.long 0x0 "TCD61_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD61_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD61_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x17B4++0x3 line.word 0x0 "TCD61_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD61_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x17B6++0x1 line.word 0x0 "TCD61_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x17B8++0x3 line.long 0x0 "TCD61_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x17BC++0x3 line.word 0x0 "TCD61_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD61_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x17BE++0x1 line.word 0x0 "TCD61_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x17C0++0x3 line.long 0x0 "TCD62_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x17C4++0x3 line.word 0x0 "TCD62_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD62_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x17C8++0x3 line.long 0x0 "TCD62_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x17C8++0x3 line.long 0x0 "TCD62_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x17C8++0xB line.long 0x0 "TCD62_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD62_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD62_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x17D4++0x3 line.word 0x0 "TCD62_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD62_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x17D6++0x1 line.word 0x0 "TCD62_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x17D8++0x3 line.long 0x0 "TCD62_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x17DC++0x3 line.word 0x0 "TCD62_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD62_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x17DE++0x1 line.word 0x0 "TCD62_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" group.long 0x17E0++0x3 line.long 0x0 "TCD63_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source address" group.word 0x17E4++0x3 line.word 0x0 "TCD63_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source address signed offset (in bytes)" line.word 0x2 "TCD63_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source address modulo" bitfld.word 0x2 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,?,?,?,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination address modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7" group.long 0x17E8++0x3 line.long 0x0 "TCD63_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Global Offset Disabled)" hexmask.long 0x0 0.--31. 1. "NBYTES,Minor byte transfer count" group.long 0x17E8++0x3 line.long 0x0 "TCD63_NBYTES_MLOFFNO,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM]=1) andNo offset is applied for.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long 0x0 0.--29. 1. "NBYTES,Minor loop byte transfer count" group.long 0x17E8++0xB line.long 0x0 "TCD63_NBYTES_MLOFFYES,TCD Word 2 is defined as follows if:If global flag (valid for every channel) to apply an offset to either source or destination address offset at the completion of each minor loop is enabled (CR[EMLM] = 1) andMinor loop offset.." bitfld.long 0x0 31. "SMLOE,Source minor loop offset enable" "0: The minor loop offset is not applied to the SADDR.,1: The minor loop offset is applied to the SADDR." bitfld.long 0x0 30. "DMLOE,Destination minor loop offset enable" "0: The minor loop offset is not applied to the DADDR.,1: The minor loop offset is applied to the DADDR." newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes." hexmask.long.word 0x0 0.--9. 1. "NBYTES,Minor byte transfer count" line.long 0x4 "TCD63_SLAST,TCD Last Source Address Adjustment" hexmask.long 0x4 0.--31. 1. "SLAST,Last source address adjustment" line.long 0x8 "TCD63_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination address" group.word 0x17F4++0x3 line.word 0x0 "TCD63_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination address signed offset (in bytes)" line.word 0x2 "TCD63_CITER_ELINKYES,TCD Current Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "CITER,Current major iteration count" group.word 0x17F6++0x1 line.word 0x0 "TCD63_CITER_ELINKNO,Refer to Figure39: TCD Current Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_CITER_ELINKNO) and Table40: eDMA_TCDn_CITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "CITER,Current major iteration count" group.long 0x17F8++0x3 line.long 0x0 "TCD63_DLASTSGA,TCD Last Destination Address Adjustment/Scatter GatherAddress" hexmask.long 0x0 0.--31. 1. "DLASTSGA,Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)." group.word 0x17FC++0x3 line.word 0x0 "TCD63_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each r/w,3: eDMA engine stalls for 8 cycles after each r/w" hexmask.word.byte 0x0 8.--13. 1. "MAJORLINKCH,Link channel number" newline bitfld.word 0x0 7. "DONE,Channel done" "0,1" bitfld.word 0x0 6. "ACTIVE,Channel active" "0,1" newline bitfld.word 0x0 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." bitfld.word 0x0 4. "ESG,Enable scatter/gather processing" "0: The current channel's TCD is normal format.,1: The current channel's TCD specifies a scatter.." newline bitfld.word 0x0 3. "DREQ,Disable request {H L}" "0: The channel's ERQ bit is not affected.,1: The channel's ERQ bit is cleared when the major.." bitfld.word 0x0 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled.,1: The half-point interrupt is enabled." newline bitfld.word 0x0 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled" bitfld.word 0x0 0. "START,Channel start" "0: The channel is not explicitly started.,1: The channel is explicitly started via a software.." line.word 0x2 "TCD63_BITER_ELINKYES,TCD Beginning Minor Loop Link. Major Loop Count (ChannelLinking Enabled)" bitfld.word 0x2 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word.byte 0x2 9.--14. 1. "LINKCH,Link channel number" newline hexmask.word 0x2 0.--8. 1. "BITER,Starting major iteration count" group.word 0x17FE++0x1 line.word 0x0 "TCD63_BITER_ELINKNO,Refer to Figure43: TCD Beginning Minor Loop Link. Major Loop Count (Channel Linking Disabled) (eDMA_TCDn_BITER_ELINKNO) and Table44: eDMA_TCDn_BITER_ELINKNO field descriptions for register details." bitfld.word 0x0 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled.,1: The channel-to-channel linking is enabled." hexmask.word 0x0 0.--14. 1. "BITER,Starting major iteration count" tree.end tree.end tree "ETHERNET" base ad:0x0 tree "ETHERNET_0" base ad:0x71A00000 group.long 0x0++0x17 line.long 0x0 "MAC_CONFIGURATION,MAC configuration register" bitfld.long 0x0 31. "ARPEN,ARP Offload Enable" "0,1" newline bitfld.long 0x0 28.--30. "SARC,Source Address Insertion or Replacement Control" "?,?,2: If Bit 30 is set to 0 the MAC inserts the..,3: If Bit 30 is set to 0 the MAC replaces the..,?,?,?,?" newline bitfld.long 0x0 27. "IPC,Checksum Offload" "0,1" newline bitfld.long 0x0 24.--26. "IPG,Inter-Packet Gap" "0: : 96 bit times IPG,1: : 88 bit times IPG,2: : 80 bit times IPG,3: : 72 bit times IPG,4: : 64 bit times IPG,5: : 56 bit times IPG,6: : 48 bit times IPG,7: : 40 bit times IPG" newline bitfld.long 0x0 23. "GPSLCE,Giant Packet Size Limit Control Enable" "0,1" newline bitfld.long 0x0 22. "S2KP,IEEE 802.3 as Support for 2K Packets" "0,1" newline bitfld.long 0x0 21. "CST,CRC stripping for Type packets" "0,1" newline bitfld.long 0x0 20. "ACS,Automatic Pad or CRC Stripping" "0,1" newline bitfld.long 0x0 19. "WD,Watchdog Disable" "0,1" newline bitfld.long 0x0 17. "JD,Jabber Disable" "0,1" newline bitfld.long 0x0 16. "JE,Jumbo Packet Enable" "0,1" newline bitfld.long 0x0 15. "PS,Port Select" "0: For 1000 Mbps operations,1: For 10 or 100Mbps operations" newline bitfld.long 0x0 14. "FES,Speed" "0: 10Mbps when PS bit is 1 and 1 Gbps when PS bit..,1: 100Mbps when PS bit is 1" newline bitfld.long 0x0 13. "DM,Duplex Mode" "0,1" newline bitfld.long 0x0 12. "LM,Loopback Mode" "0,1" newline bitfld.long 0x0 11. "ECRSFD,Enable Carrier Sense Before Transmission in Full-Duplex Mode" "0,1" newline bitfld.long 0x0 2.--3. "PRELEN,Preamble Length for Transmit packets" "0: 7 bytes of preamble,1: 5 bytes of preamble,2: 3 bytes of preamble,?" newline bitfld.long 0x0 1. "TE,Transmitter Enable" "0,1" newline bitfld.long 0x0 0. "RE,Receiver Enable" "0,1" line.long 0x4 "MAC_EXT_CONFIGURATION,MAC extended configuration register" hexmask.long.byte 0x4 25.--29. 1. "EIPG,Extended Inter-Packet Gap" newline bitfld.long 0x4 24. "EIPGEN,Extended Inter-Packet Gap Enable" "0,1" newline bitfld.long 0x4 20.--22. "HDSMS,Maximum Size for Splitting the Header Data" "0: 64 bytes,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1024 bytes,?,?,?" newline bitfld.long 0x4 19. "PDC,Packet Duplication Control" "0,1" newline bitfld.long 0x4 18. "USP,Unicast Slow Protocol Packet Detect" "0,1" newline bitfld.long 0x4 17. "SPEN,Slow Protocol Detection Enable" "0,1" newline bitfld.long 0x4 16. "DCRCC,Disable CRC Checking for Received Packets" "0,1" newline hexmask.long.word 0x4 0.--13. 1. "GPSL,Giant Packet Size Limit" line.long 0x8 "MAC_PACKET_FILTER,MAC packet filter register" bitfld.long 0x8 31. "RA,Receive All" "0,1" newline bitfld.long 0x8 21. "DNTU,Drop Non-TCP/UDP over IP Packets" "0,1" newline bitfld.long 0x8 20. "IPFE,Layer 3 and Layer 4 Filter Enable" "0,1" newline bitfld.long 0x8 16. "VTFE,VLAN Tag Filter Enable" "0,1" newline bitfld.long 0x8 10. "HPF,Hash or Perfect Filter" "0,1" newline bitfld.long 0x8 9. "SAF,Source Address Filter Enable" "0,1" newline bitfld.long 0x8 8. "SAIF,SA Inverse Filtering" "0,1" newline bitfld.long 0x8 6.--7. "PCF,Pass Control Packets" "0: The MAC filters all control packets from..,1: The MAC forwards all control packets except..,2: The MAC forwards all control packets to the..,3: The MAC forwards the control packets that pass.." newline bitfld.long 0x8 5. "DBF,Disable Broadcast Packets" "0,1" newline bitfld.long 0x8 4. "PM,Pass All Multicast" "0,1" newline bitfld.long 0x8 3. "DAIF,DA Inverse Filtering" "0,1" newline bitfld.long 0x8 2. "HMC,Hash Multicast" "0,1" newline bitfld.long 0x8 1. "HUC,Hash Unicast" "0,1" newline bitfld.long 0x8 0. "PR,Promiscuous Mode" "0,1" line.long 0xC "MAC_WATCHDOG_TIMEOUT,MAC Watchdog Timeout register" bitfld.long 0xC 8. "PWE,Programmable Watchdog Enable" "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "WTO,Watchdog Timeout" line.long 0x10 "MAC_HASH_TABLE_REG0,MAC Hash table register 0" hexmask.long 0x10 0.--31. 1. "HT31T0,This field contains the first 32 Bits [31) 0] of the MAC Hash table." line.long 0x14 "MAC_HASH_TABLE_REG1,MAC Hash Table register 1" hexmask.long 0x14 0.--31. 1. "HT63T32,This field contains the second 32 Bits [31:0] of the MAC Hash table." group.long 0x50++0x7 line.long 0x0 "MAC_VLAN_TAG_CTRL,MAC VLAN tag control register" bitfld.long 0x0 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status" "0,1" newline bitfld.long 0x0 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip" newline bitfld.long 0x0 27. "ERIVLT,Enable Inner VLAN Tag" "0,1" newline bitfld.long 0x0 26. "EDVLP,Enable Double VLAN Processing" "0,1" newline bitfld.long 0x0 25. "VTHM,VLAN Tag Hash Table Match Enable" "0,1" newline bitfld.long 0x0 24. "EVLRXS,Enable VLAN Tag in Rx status" "0,1" newline bitfld.long 0x0 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip" newline bitfld.long 0x0 18. "ESVL,Enable S-VLAN" "0,1" newline bitfld.long 0x0 17. "VTIM,VLAN Tag Inverse Match Enable" "0,1" newline hexmask.long.byte 0x0 2.--6. 1. "OFS,Offset" newline bitfld.long 0x0 1. "CT,Command Type" "0,1" newline bitfld.long 0x0 0. "OB,Operation Busy" "0,1" line.long 0x4 "MAC_VLAN_TAG_DATA,MAC VLAN tag data register" bitfld.long 0x4 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x4 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x4 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x4 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x4 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x4 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x4 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x4 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER0,MAC VLAN tag filter register 0" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER1,MAC VLAN tag filter register 1" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER2,MAC VLAN tag filter register 2" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER3,MAC VLAN tag filter register 3" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER4,MAC VLAN tag filter register 4" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER5,MAC VLAN tag filter register 5" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER6,MAC VLAN tag filter register 6" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER7,MAC VLAN tag filter register 7" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER8,MAC VLAN tag filter register 8" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER9,MAC VLAN tag filter register 9" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER10,MAC VLAN tag filter register 10" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER11,MAC VLAN tag filter register 11" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER12,MAC VLAN tag filter register 12" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER13,MAC VLAN tag filter register 13" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER14,MAC VLAN tag filter register 14" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x7 line.long 0x0 "MAC_VLAN_TAG_FILTER15,MAC VLAN tag filter register 15" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" line.long 0x4 "MAC_VLAN_HASH_TABLE,MAC VLAN hash table register" hexmask.long.word 0x4 0.--15. 1. "VLHT,VLAN Hash Table" group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_INCL,MAC VLAN tag inclusion register" bitfld.long 0x0 31. "BUSY,Busy" "0,1" newline bitfld.long 0x0 30. "RDWR,Read write control" "0,1" newline bitfld.long 0x0 24.--25. "ADDR,Address" "0,1,2,3" newline bitfld.long 0x0 21. "CBTI,Channel based tag insertion" "0,1" newline bitfld.long 0x0 20. "VLTI,VLAN Tag Input" "0,1" newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN" "0,1" newline bitfld.long 0x0 18. "VLP,VLAN Priority Control" "0,1" newline bitfld.long 0x0 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0,1,2,3" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_INCL0,The Tx Queue VLAN tag inclusion register contains the VLAN tag for insertion in the transmit packets from Tx Queue n. It also contains the VLAN tag insertion controls." bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_INCL1,The Tx Queue VLAN tag inclusion register contains the VLAN tag for insertion in the transmit packets from Tx Queue n. It also contains the VLAN tag insertion controls." bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" group.long 0x60++0x7 line.long 0x0 "MAC_VLAN_INCL2,The Tx Queue VLAN tag inclusion register contains the VLAN tag for insertion in the transmit packets from Tx Queue n. It also contains the VLAN tag insertion controls." bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" line.long 0x4 "MAC_INNER_VLAN_INCL,MAC Inner VLAN tag inclusion register" bitfld.long 0x4 20. "VLTI,VLAN Tag Input" "0,1" newline bitfld.long 0x4 19. "CSVL,C-VLAN or S-VLAN" "0,1" newline bitfld.long 0x4 18. "VLP,VLAN Priority Control" "0,1" newline bitfld.long 0x4 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion. The MAC removes the VLAN type..,2: VLAN tag insertion. The MAC inserts VLT in bytes..,3: VLAN tag replacement. The MAC replaces VLT in.." newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" group.long 0x70++0x3 line.long 0x0 "MAC_Q0_TX_FLOW_CTRL,MAC Q0 TX flow control register" hexmask.long.word 0x0 16.--31. 1. "PT,Pause Time" newline bitfld.long 0x0 7. "DZPQ,Disable Zero-Quanta Pause" "0,1" newline bitfld.long 0x0 4.--6. "PLT,Pause Low Threshold" "0: Pause Time minus 4 Slot Times (PT -4 slot times),1: Pause Time minus 28 Slot Times (PT -28 slot times),2: Pause Time minus 36 Slot Times (PT -36 slot times),3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?,?" newline bitfld.long 0x0 1. "TFE,Transmit Flow Control Enable" "0,1" newline bitfld.long 0x0 0. "FCB_BPA,Flow Control Busy or Backpressure Activate" "0,1" group.long 0x90++0x7 line.long 0x0 "MAC_RX_FLOW_CTRL,MAC receive flow control register" bitfld.long 0x0 1. "UP,Unicast Pause Packet Detect" "0,1" newline bitfld.long 0x0 0. "RFE,Receive Flow Control Enable" "0,1" line.long 0x4 "MAC_RXQ_CTRL4,MAC Receive queue control 4 register" bitfld.long 0x4 17.--18. "VFFQ,VLAN Tag Filter Fail Packets Queue" "0,1,2,3" newline bitfld.long 0x4 16. "VFFQE,VLAN Tag Filter Fail Packets Queuing Enable" "0,1" newline bitfld.long 0x4 9.--10. "MFFQ,Multicast Address Filter Fail Packets Queue" "0,1,2,3" newline bitfld.long 0x4 8. "MFFQE,Multicast Address Filter Fail Packets Queuing Enable" "0,1" newline bitfld.long 0x4 1.--2. "UFFQ,Unicast Address Filter Fail Packets Queue" "0,1,2,3" newline bitfld.long 0x4 0. "UFFQE,Unicast Address Filter Fail Packets Queuing Enable" "0,1" group.long 0xA0++0xB line.long 0x0 "MAC_RXQ_CTRL0,MAC Receive queue control 0 register" bitfld.long 0x0 4.--5. "RXQ2EN,Receive Queue 2 Enable" "0: Not enabled,1: Queue 1 enabled for AV,2: Queue 1 enabled for generic,?" newline bitfld.long 0x0 2.--3. "RXQ1EN,Receive Queue 1 Enable" "0: Not enabled,1: Queue 1 enabled for AV,2: Queue 1 enabled for generic,?" newline bitfld.long 0x0 0.--1. "RXQ0EN,Receive Queue 0 Enable" "0: Not enabled,1: Queue 0 enabled for AV,2: Queue 0 enabled for generic,?" line.long 0x4 "MAC_RXQ_CTRL1,MAC Receive queue control 1 register" bitfld.long 0x4 24.--26. "FPRQ,Frame Preemption Residue Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 22.--23. "TPQC,Tagged PTP over Ethernet Packets Queuing Control" "0: VLAN Tagged PTPoE packets are routed as generic..,1: VLAN Tagged PTPoE packets are routed to Rx Queue..,2: VLAN Tagged PTPoE packets are routed to only AV..,?" newline bitfld.long 0x4 21. "TACPQE,Tagged AV Control Packets Queuing Enable" "0,1" newline bitfld.long 0x4 20. "MCBCQEN,Multicast and Broadcast Queue Enable" "0,1" newline bitfld.long 0x4 16.--18. "MCBCQ,Multicast and Broadcast Queue" "0: Rx Queue 0,1: Rx Queue 1,2: Rx Queue 2,?,?,?,?,?" newline bitfld.long 0x4 12.--14. "UPQ,Untagged Packet Queue" "0: Rx Queue 0,1: Rx Queue 1,2: Rx Queue 2,?,?,?,?,?" newline bitfld.long 0x4 4.--6. "PTPQ,AV PTP Packets Queue" "0: Rx Queue 0,1: Rx Queue 1,2: Rx Queue 2,?,?,?,?,?" newline bitfld.long 0x4 0.--2. "AVCPQ,AV Untagged Control Packets Queue" "0: Rx Queue 0,1: Rx Queue 1,2: Rx Queue 2,?,?,?,?,?" line.long 0x8 "MAC_RXQ_CTRL2,MAC Receive queue control 2 register" hexmask.long.byte 0x8 16.--23. 1. "PSRQ2,Priorities Selected in the Receive Queue 2" newline hexmask.long.byte 0x8 8.--15. 1. "PSRQ1,Priorities Selected in the Receive Queue 1" newline hexmask.long.byte 0x8 0.--7. 1. "PSRQ0,Priorities Selected in the Receive Queue 0" rgroup.long 0xB0++0x3 line.long 0x0 "MAC_INTERRUPT_STATUS,MAC Interrupt status register" bitfld.long 0x0 20. "MFRIS,MMC FPE Receive Interrupt Status" "0,1" newline bitfld.long 0x0 19. "MFTIS,MMC FPE Transmit Interrupt Status" "0,1" newline bitfld.long 0x0 18. "MDIOIS,MDIO Interrupt Status" "0,1" newline bitfld.long 0x0 17. "FPEIS,Frame Preemption Interrupt Status" "0,1" newline bitfld.long 0x0 14. "RXSTSIS,Receive Status Interrupt" "0,1" newline bitfld.long 0x0 13. "TXSTSIS,Transmit Status Interrupt" "0,1" newline bitfld.long 0x0 12. "TSIS,Timestamp Interrupt Status" "0,1" newline bitfld.long 0x0 11. "MMCRXIPIS,MMC Receive Checksum Offload Interrupt Status" "0,1" newline bitfld.long 0x0 10. "MMCTXIS,MMC Transmit Interrupt Status" "0,1" newline bitfld.long 0x0 9. "MMCRXIS,MMC Receive Interrupt Status" "0,1" newline bitfld.long 0x0 8. "MMCIS,MMC Interrupt Status" "?,?" newline bitfld.long 0x0 5. "LPIIS,LPI Interrupt Status" "0,1" newline bitfld.long 0x0 4. "PMTIS,PMT Interrupt Status" "0,1" newline bitfld.long 0x0 3. "PHYIS,PHY Interrupt" "0,1" newline bitfld.long 0x0 2. "PCSANCIS,PCS Auto-Negotiation Complete" "0: PCS auto-negotiation has not completed,1: PCS auto-negotiation completed" newline bitfld.long 0x0 1. "PCSLCHGIS,PCS Link Status Changed" "0: PCS link status has not changed,1: PCS link status changed" newline bitfld.long 0x0 0. "RGSMIIIS,RGMII or SMII Interrupt Status" "0,1" group.long 0xB4++0x3 line.long 0x0 "MAC_INTERRUPT_ENABLE,MAC Interrupt enable register" bitfld.long 0x0 18. "MDIOIE,MDIO Interrupt Enable" "0,1" newline bitfld.long 0x0 17. "FPEIE,Frame Preemption Interrupt Enable" "0,1" newline bitfld.long 0x0 14. "RXSTSIE,Receive Status Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TXSTSIE,Transmit Status Interrupt Enable" "0,1" newline bitfld.long 0x0 12. "TSIE,Timestamp Interrupt Enable" "0,1" newline bitfld.long 0x0 5. "LPIIE,LPI Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "PMTIE,PMT Interrupt Enable" "0,1" newline bitfld.long 0x0 3. "PHYIE,PHY Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "PCSANCIE,PCS AN Completion Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "PCSLCHGIE,PCS Link Status Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "RGSMIIIE,RGMII or SMII Interrupt Enable" "0,1" rgroup.long 0xB8++0x3 line.long 0x0 "MAC_RX_TX_STATUS,MAC Receive transmit status register" bitfld.long 0x0 8. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x0 0. "TJT,Transmit Jabber Timeout" "0,1" group.long 0xC0++0x7 line.long 0x0 "MAC_PMT_CONTROL_STATUS,MAC PMT control and status register" bitfld.long 0x0 31. "RWKFILTRST,Remote Wake-Up Packet Filter Register Pointer Reset" "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,Remote Wake-up FIFO Pointer" newline bitfld.long 0x0 10. "RWKPFE,Remote Wake-up Packet Forwarding Enable" "0,1" newline bitfld.long 0x0 9. "GLBLUCAST,Global Unicast" "0,1" newline bitfld.long 0x0 6. "RWKPRCVD,Remote Wake-Up Packet Received" "0,1" newline bitfld.long 0x0 5. "MGKPRCVD,Magic Packet Received" "0,1" newline bitfld.long 0x0 2. "RWKPKTEN,Remote Wake-Up Packet Enable" "0,1" newline bitfld.long 0x0 1. "MGKPKTEN,Magic Packet Enable" "0,1" newline bitfld.long 0x0 0. "PWRDWN,Power Down" "0,1" line.long 0x4 "MAC_RWK_PACKET_FILTER,MAC RWK packet filter register" hexmask.long 0x4 0.--31. 1. "WKUPFRMFTR,RWK Packet Filter" group.long 0xC4++0x3 line.long 0x0 "RWK_FILTER0_BYTE_MASK,Corresponds to registers wkuppktfilter_reg0 described in Table1542." hexmask.long 0x0 0.--31. 1. "FILTER0_BYTE_MASK,Filter{i} 32-bit Mask" group.long 0xC4++0x3 line.long 0x0 "RWK_FILTER1_BYTE_MASK,Corresponds to registers wkuppktfilter_reg1 described in Table1542." hexmask.long 0x0 0.--31. 1. "FILTER1_BYTE_MASK,Filter{i} 32-bit Mask" group.long 0xC4++0x3 line.long 0x0 "RWK_FILTER2_BYTE_MASK,Corresponds to registers wkuppktfilter_reg2 described in Table1542." hexmask.long 0x0 0.--31. 1. "FILTER2_BYTE_MASK,Filter{i} 32-bit Mask" group.long 0xC4++0x3 line.long 0x0 "RWK_FILTER3_BYTE_MASK,Corresponds to registers wkuppktfilter_reg3 described in Table1542." hexmask.long 0x0 0.--31. 1. "FILTER3_BYTE_MASK,Filter{i} 32-bit Mask" group.long 0xC4++0x3 line.long 0x0 "RWK_FILTER0123_COMMAND,Corresponds to registers wkuppktfilter_reg4 described in Table1542." hexmask.long.byte 0x0 24.--27. 1. "FILTER3_COMMAND,Filter{l} Command" newline hexmask.long.byte 0x0 16.--19. 1. "FILTER2_COMMAND,Filter{k} Command" newline hexmask.long.byte 0x0 8.--11. 1. "FILTER1_COMMAND,Filter{j} Command" newline hexmask.long.byte 0x0 0.--3. 1. "FILTER0_COMMAND,Filter{i} Command" group.long 0xC4++0x3 line.long 0x0 "RWK_FILTER0123_OFFSET,Corresponds to registers wkuppktfilter_reg5 described in Table1542." hexmask.long.byte 0x0 24.--31. 1. "FILTER3_OFFSET,Filter{l} Offset" newline hexmask.long.byte 0x0 16.--23. 1. "FILTER2_OFFSET,Filter{k} Offset" newline hexmask.long.byte 0x0 8.--15. 1. "FILTER1_OFFSET,Filter{j} Offset" newline hexmask.long.byte 0x0 0.--7. 1. "FILTER0_OFFSET,Filter{i} Offset" group.long 0xC4++0x3 line.long 0x0 "RWK_FILTER01_CRC,Corresponds to registers wkuppktfilter_reg6 described in Table1542." hexmask.long.word 0x0 16.--31. 1. "FILTER1_CRC,Filter{j} CRC-16" newline hexmask.long.word 0x0 0.--15. 1. "FILTER0_CRC,Filter{i} CRC-16" group.long 0xC4++0x3 line.long 0x0 "RWK_FILTER23_CRC,Corresponds to registers wkuppktfilter_reg7 described in Table1542." hexmask.long.word 0x0 16.--31. 1. "FILTER3_CRC,Refer to the description of Section69.2.2.25." newline hexmask.long.word 0x0 0.--15. 1. "FILTER2_CRC,Refer to the description of Section69.2.2.25." group.long 0xD0++0x13 line.long 0x0 "MAC_LPI_CONTROL_STATUS,MAC LPI control and status register" bitfld.long 0x0 21. "LPITCSE,LPI Tx Clock Stop Enable" "0: LPI Tx Clock Stop is disabled,1: LPI Tx Clock Stop is enabled" newline bitfld.long 0x0 20. "LPIATE,LPI Timer Enable" "0: LPI Timer is disabled,1: LPI Timer is enabled" newline bitfld.long 0x0 19. "LPITXA,LPI Tx Automate" "0: LPI Tx Automate is disabled,1: LPI Tx Automate is enabled" newline bitfld.long 0x0 18. "PLSEN,PHY Link Status Enable" "0: PHY Link Status is disabled,1: PHY Link Status is enabled" newline bitfld.long 0x0 17. "PLS,PHY Link Status" "0: Link is down,1: Link is okay" newline bitfld.long 0x0 16. "LPIEN,LPI Enable" "0: LPI state is disabled,1: LPI state is enabled" newline bitfld.long 0x0 9. "RLPIST,Receive LPI State" "0: Receive LPI state not detected,1: Receive LPI state detected" newline bitfld.long 0x0 8. "TLPIST,Transmit LPI State" "0: Transmit LPI state not detected,1: Transmit LPI state detected" newline bitfld.long 0x0 3. "RLPIEX,Receive LPI Exit" "0: Receive LPI exit not detected,1: Receive LPI exit detected" newline bitfld.long 0x0 2. "RLPIEN,Receive LPI Entry" "0: Receive LPI entry not detected,1: Receive LPI entry detected" newline bitfld.long 0x0 1. "TLPIEX,Transmit LPI Exit" "0: Transmit LPI exit not detected,1: Transmit LPI exit detected" newline bitfld.long 0x0 0. "TLPIEN,Transmit LPI Entry" "0: Transmit LPI entry not detected,1: Transmit LPI entry detected" line.long 0x4 "MAC_LPI_TIMERS_CONTROL,MAC LPI timers control register" hexmask.long.word 0x4 16.--25. 1. "LST,LPI LS TIMER" newline hexmask.long.word 0x4 0.--15. 1. "TWT,LPI TW TIMER" line.long 0x8 "MAC_LPI_ENTRY_TIMER,MAC LPI entry timer register" hexmask.long.tbyte 0x8 3.--19. 1. "LPIET,LPI Entry Timer" line.long 0xC "MAC_1US_TIC_COUNTER,MAC 1US Tic counter register" hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,1US TIC Counter" line.long 0x10 "MAC_AN_CONTROL,MAC Auto-negotiation control register" bitfld.long 0x10 18. "SGMRAL,SGMII RAL Control" "0: SGMII RAL Control is disabled,1: SGMII RAL Control is enabled" newline bitfld.long 0x10 17. "LR,Lock to Reference" "0: Lock to Reference is disabled,1: Lock to Reference is enabled" newline bitfld.long 0x10 16. "ECD,Enable Comma Detect" "0: Comma detect is disabled,1: Comma detect is enabled" newline bitfld.long 0x10 14. "ELE,External Loopback Enable" "0: External Loopback is disabled,1: External Loopback is enabled" newline bitfld.long 0x10 12. "ANE,Auto-Negotiation Enable" "0: Auto-Negotiation is disabled,1: Auto-Negotiation is enabled" newline bitfld.long 0x10 9. "RAN,Restart Auto-Negotiation" "0: Do not Restart Auto-Negotiation,1: Restart Auto-Negotiation" rgroup.long 0xE4++0x3 line.long 0x0 "MAC_AN_STATUS,MAC Auto-negotiation status register" bitfld.long 0x0 8. "ES,Extended Status" "0: No extended status (SGMII without TBI),1: Extended status (TBI or RTBI)" newline bitfld.long 0x0 5. "ANC,Auto-Negotiation Complete" "0: Auto-Negotiation is not complete,1: Auto-Negotiation is complete" newline bitfld.long 0x0 3. "ANA,Auto-Negotiation Ability" "0: MAC does not possess Auto-Negotiation Ability,1: MAC possesses Auto-Negotiation Ability" newline bitfld.long 0x0 2. "LS,Link Status" "0: Link is down,1: Link is up" group.long 0xF8++0x3 line.long 0x0 "MAC_PHYIF_CONTROL_STATUS,MAC PHYIF Control Status register" bitfld.long 0x0 19. "LNKSTS,Link Status" "0,1" newline bitfld.long 0x0 17.--18. "LNKSPEED,Link Speed" "0: 2.5 MHz,1: 25 MHz,2: 125 MHz,?" newline bitfld.long 0x0 16. "LNKMOD,Link Mode" "0: Half-duplex mode,1: Full-duplex mode" newline bitfld.long 0x0 1. "LUD,Link Up or Down" "0: Link Down,1: Link Up" newline bitfld.long 0x0 0. "TC,Transmit Configuration in RGMII" "0,1" rgroup.long 0x110++0x7 line.long 0x0 "MAC_VERSION,MAC Version register" hexmask.long.byte 0x0 8.--15. 1. "USERVER,User IP Version Number" newline hexmask.long.byte 0x0 0.--7. 1. "VENDORVER,Vendor IP Version Number" line.long 0x4 "MAC_DEBUG,MAC Debug register" bitfld.long 0x4 17.--18. "TFCSTS,MAC Transmit Packet Controller Status" "0: Idle state,1: Waiting for one of the following:,2: Generating and transmitting a Pause control..,3: Transferring input packet for transmission" newline bitfld.long 0x4 16. "TPESTS,MAC MII Transmit Protocol Engine Status" "0,1" newline bitfld.long 0x4 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status" "0,1,2,3" newline bitfld.long 0x4 0. "RPESTS,MAC MII Receive Protocol Engine Status" "0,1" rgroup.long 0x11C++0xF line.long 0x0 "MAC_HW_FEATURE0,MAC Hardware feature 0 register" bitfld.long 0x0 28.--30. "ACTPHYSEL,Active PHY Selected" "0: MII,1: RGMII,2: SGMII,?,4: RMII,?,?,?" newline bitfld.long 0x0 27. "SAVLANINS,Source Address or VLAN Insertion Enable" "0,1" newline bitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source" "?,?,?,3: Both internal and external source of Timestamp" newline hexmask.long.byte 0x0 18.--22. 1. "ADDMACADRSEL,MAC Addresses 1-31 Selected" newline bitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload present" "0,1" newline bitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload present" "0,1" newline bitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet present" "0,1" newline bitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp present" "0,1" newline bitfld.long 0x0 9. "ARPOFFSEL,ARP Offload present" "0,1" newline bitfld.long 0x0 8. "MMCSEL,RMON Module Present" "0,1" newline bitfld.long 0x0 7. "MGKSEL,PMT Magic Packet present" "0,1" newline bitfld.long 0x0 6. "RWKSEL,PMT Remote Wake-up Packet Enable" "0,1" newline bitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface present" "0,1" newline bitfld.long 0x0 4. "VLHASH,VLAN Hash Filter selection" "0,1" newline bitfld.long 0x0 3. "PCSSEL,SGMII PCS registers present" "0,1" newline bitfld.long 0x0 2. "HDSEL,Half-duplex support selection" "0: Not selected,1: Selected" newline bitfld.long 0x0 1. "GMIISEL,This bit is set to 1 when 1000 Mbps is selected as the mode of operation." "0,1" newline bitfld.long 0x0 0. "MIISEL,MIISEL" "?,?" line.long 0x4 "MAC_HW_FEATURE1,MAC Hardware feature 1 register" hexmask.long.byte 0x4 27.--30. 1. "L3L4FNUM,Total number of L3 or L4 Filters" newline bitfld.long 0x4 24.--25. "HASHTBLSZ,Hash Table Size" "?,1: 64-bit hash table,?,?" newline bitfld.long 0x4 20. "AVSEL,AV Feature Enabled" "0,1" newline bitfld.long 0x4 19. "DBGMEMA,DMA Debug Registers Enabled" "0,1" newline bitfld.long 0x4 18. "TSOEN,TCP Segmentation Offload Enable" "0,1" newline bitfld.long 0x4 17. "SPHEN,Split Header Feature Enable" "0,1" newline bitfld.long 0x4 14.--15. "ADDR64,Address Width" "0: 32-bit address width,?,?,?" newline bitfld.long 0x4 13. "ADVTHWORD,IEEE 1588 High Word Register Enable" "0,1" newline bitfld.long 0x4 11. "OSTEN,One-Step Timestamping Enable" "0,1" newline hexmask.long.byte 0x4 6.--10. 1. "TXFIFOSIZE,MTL Transmit FIFO Size" newline bitfld.long 0x4 5. "SPRAM,Single Port RAM Enable" "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "RXFIFOSIZE,MTL Receive FIFO Size" line.long 0x8 "MAC_HW_FEATURE2,MAC Hardware feature 2 register" bitfld.long 0x8 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs" "?,?,2: 2 auxiliary inputs,?,?,?,?,?" newline bitfld.long 0x8 24.--26. "PPSOUTNUM,Number of PPS Outputs" "?,1: 1 PPS output,?,?,?,?,?,?" newline hexmask.long.byte 0x8 18.--21. 1. "TXCHCNT,Number of DMA Transmit Channels" newline hexmask.long.byte 0x8 12.--15. 1. "RXCHCNT,Number of DMA Receive Channels" newline hexmask.long.byte 0x8 6.--9. 1. "TXQCNT,Number of MTL Transmit Queues" newline hexmask.long.byte 0x8 0.--3. 1. "RXQCNT,Number of MTL Receive Queues" line.long 0xC "MAC_HW_FEATURE3,MAC Hardware feature 3 register" bitfld.long 0xC 28.--29. "ASP,Automotive Safety Package" "?,?,?,3: Time Based Scheduling Enable feature is selected." newline bitfld.long 0xC 27. "TBSSEL,Time Based Scheduling Enable" "0: Time Based Scheduling Enable feature is not..,1: Time Based Scheduling Enable feature is selected." newline bitfld.long 0xC 26. "FPESEL,Frame Preemption Enable" "0: Frame Preemption Enable feature is not selected.,1: Frame Preemption Enable feature is selected." newline bitfld.long 0xC 20.--21. "ESTWID,Width of the Time Interval field in the Gate Control List" "0: Width not configured,1: 16,2: 20,3: 24" newline bitfld.long 0xC 17.--19. "ESTDEP,Depth of the Gate Control List" "0: No Depth configured,1: 64,2: 128,3: 256,4: 512,5: 1024,?,?" newline bitfld.long 0xC 16. "ESTSEL,Enhancements to Scheduling Traffic Enable" "0: Enable Enhancements to Scheduling Traffic..,1: Enable Enhancements to Scheduling Traffic.." newline bitfld.long 0xC 13.--14. "FRPES,Flexible Receive Parser table Entries Size" "?,?,2: 256 Entries,?" newline bitfld.long 0xC 11.--12. "FRPBS,Flexible Receive Parser Buffer Size" "?,1: 128 Bytes,?,?" newline bitfld.long 0xC 10. "FRPSEL,Flexible Receive Parser Selected" "?,1: FRP supported" newline bitfld.long 0xC 9. "PDUPSEL,Broadcast/Multicast Packet Duplication" "0,1" newline bitfld.long 0xC 5. "DVLAN,Double VLAN feature" "0: Disable,1: Enable" newline bitfld.long 0xC 4. "CBTISEL,Queue/Channel based VLAN tag insertion on Tx Enable" "0,1" newline bitfld.long 0xC 0.--2. "NRVF,Number of Extended VLAN Tag Filters Enabled" "?,?,?,3: 16 Extended Rx VLAN Filters,?,?,?,?" group.long 0x140++0x3 line.long 0x0 "MAC_DPP_FSM_INTERRUPT_STATUS,MAC Data Path Parity FSM interrupt status register" bitfld.long 0x0 24. "FSMPES,FSM State Parity Error Status" "0: FSM State Parity Error Status not detected,1: FSM State Parity Error Status detected" newline bitfld.long 0x0 16. "MSTTES,Master Read/Write Timeout Error Status" "0: Master Read/Write Timeout Error Status not..,1: Master Read/Write Timeout Error Status detected" newline bitfld.long 0x0 14. "R125ES,Rx125 FSM Timeout Error Status" "0: Rx125 FSM Timeout Error Status not detected,1: Rx125 FSM Timeout Error Status detected" newline bitfld.long 0x0 13. "T125ES,Tx125 FSM Timeout Error Status" "0: Tx125 FSM Timeout Error Status not detected,1: Tx125 FSM Timeout Error Status detected" newline bitfld.long 0x0 12. "PTES,PTP FSM Timeout Error Status" "0: PTP FSM Timeout Error Status not detected,1: PTP FSM Timeout Error Status detected" newline bitfld.long 0x0 11. "ATES,APP FSM Timeout Error Status" "0: APP FSM Timeout Error Status not detected,1: APP FSM Timeout Error Status detected" newline bitfld.long 0x0 10. "CTES,CSR FSM Timeout Error Status" "0: CSR FSM Timeout Error Status not detected,1: CSR FSM Timeout Error Status detected" newline bitfld.long 0x0 9. "RTES,Rx FSM Timeout Error Status" "0: Rx FSM Timeout Error Status not detected,1: Rx FSM Timeout Error Status detected" newline bitfld.long 0x0 8. "TTES,Tx FSM Timeout Error Status" "0: Tx FSM Timeout Error Status not detected,1: Tx FSM Timeout Error Status detected" newline bitfld.long 0x0 5. "ARPES,Application Receive interface data path Parity Error Status" "0: Application Receive interface data path Parity..,1: Application Receive interface data path Parity.." newline bitfld.long 0x0 4. "MTSPES,MTL TX Status data path Parity checker Error Status" "0: MTL TX Status data path Parity checker Error..,1: MTL TX Status data path Parity checker Error.." newline bitfld.long 0x0 3. "MPES,MTL data path Parity checker Error Status" "0: MTL data path Parity checker Error Status not..,1: MTL data path Parity checker Error Status detected" newline bitfld.long 0x0 2. "RDPES,Read Descriptor Parity checker Error Status" "0: Read Descriptor Parity checker Error Status not..,1: Read Descriptor Parity checker Error Status.." newline bitfld.long 0x0 1. "TPES,TSO data path Parity checker Error Status" "0: TSO data path Parity checker Error Status not..,1: TSO data path Parity checker Error Status detected" newline bitfld.long 0x0 0. "ATPES,Application Transmit Interface Parity checker Error Status" "0: Application Transmit Interface Parity checker..,1: Application Transmit Interface Parity checker.." group.long 0x148++0x7 line.long 0x0 "MAC_FSM_CONTROL,MAC FSM control register" bitfld.long 0x0 30. "R125LGRNML,Rx125 Large/Normal Mode Select" "0: Normal mode tic generation is used for Rx125..,1: Large mode tic generation is used for Rx125 domain" newline bitfld.long 0x0 29. "T125LGRNML,Tx125 Large/Normal Mode Select" "0: Normal mode tic generation is used for Tx125..,1: Large mode tic generation is used for Tx125 domain" newline bitfld.long 0x0 28. "PLGRNML,PTP Large/Normal Mode Select" "0: Normal mode tic generation is used for PTP domain,1: Large mode tic generation is used for PTP domain" newline bitfld.long 0x0 27. "ALGRNML,APP Large/Normal Mode Select" "0: Normal mode tic generation is used for APP domain,1: Large mode tic generation is used for APP domain" newline bitfld.long 0x0 26. "CLGRNML,CSR Large/Normal Mode Select" "0: Normal mode tic generation is used for CSR domain,1: Large mode tic generation is used for CSR domain" newline bitfld.long 0x0 25. "RLGRNML,Rx Large/Normal Mode Select" "0: Normal mode tic generation is used for Rx domain,1: Large mode tic generation is used for Rx domain" newline bitfld.long 0x0 24. "TLGRNML,Tx Large/Normal Mode Select" "0: Normal mode tic generation is used for Tx domain,1: Large mode tic generation is used for Tx domain" newline bitfld.long 0x0 22. "R125PEIN,Rx125 FSM Parity Error Injection" "0: Rx125 FSM Parity Error Injection is disabled,1: Rx125 FSM Parity Error Injection is enabled" newline bitfld.long 0x0 21. "T125PEIN,Tx125 FSM Parity Error Injection" "0: Tx125 FSM Parity Error Injection is disabled,1: Tx125 FSM Parity Error Injection is enabled" newline bitfld.long 0x0 20. "PPEIN,PTP FSM Parity Error Injection" "0: PTP FSM Parity Error Injection is disabled,1: PTP FSM Parity Error Injection is enabled" newline bitfld.long 0x0 19. "APEIN,APP FSM Parity Error Injection" "0: APP FSM Parity Error Injection is disabled,1: APP FSM Parity Error Injection is enabled" newline bitfld.long 0x0 18. "CPEIN,CSR FSM Parity Error Injection" "0: CSR FSM Parity Error Injection is disabled,1: CSR FSM Parity Error Injection is enabled" newline bitfld.long 0x0 17. "RPEIN,Rx FSM Parity Error Injection" "0: Rx FSM Parity Error Injection is disabled,1: Rx FSM Parity Error Injection is enabled" newline bitfld.long 0x0 16. "TPEIN,Tx FSM Parity Error Injection" "0: Tx FSM Parity Error Injection is disabled,1: Tx FSM Parity Error Injection is enabled" newline bitfld.long 0x0 14. "R125TEIN,Rx125 FSM Timeout Error Injection" "0: Rx125 FSM Timeout Error Injection is disabled,1: Rx125 FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 13. "T125TEIN,Tx125 FSM Timeout Error Injection" "0: Tx125 FSM Timeout Error Injection is disabled,1: Tx125 FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 12. "PTEIN,PTP FSM Timeout Error Injection" "0: PTP FSM Timeout Error Injection is disabled,1: PTP FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 11. "ATEIN,APP FSM Timeout Error Injection" "0: APP FSM Timeout Error Injection is disabled,1: APP FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 10. "CTEIN,CSR FSM Timeout Error Injection" "0: CSR FSM Timeout Error Injection is disabled,1: CSR FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 9. "RTEIN,Rx FSM Timeout Error Injection" "0: Rx FSM Timeout Error Injection is disabled,1: Rx FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 8. "TTEIN,Tx FSM Timeout Error Injection" "0: Tx FSM Timeout Error Injection is disabled,1: Tx FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 1. "PRTYEN,FSM Parity Enable" "0: FSM Parity feature is disabled,1: FSM Parity feature is enabled" newline bitfld.long 0x0 0. "TMOUTEN,FSM Timeout Enable" "0: FSM timeout feature is disabled,1: FSM timeout feature is enabled" line.long 0x4 "MAC_FSM_ACT_TIMER,MAC FSM ACT register" hexmask.long.byte 0x4 20.--23. 1. "LTMRMD,Large Mode Timeout value" newline hexmask.long.byte 0x4 16.--19. 1. "NTMRMD,Normal Mode Timeout Value" newline hexmask.long.word 0x4 0.--9. 1. "TMR,1us Timer Tick" group.long 0x200++0x13 line.long 0x0 "MAC_MDIO_ADDRESS,MAC MDIO address register" bitfld.long 0x0 27. "PSE,Preamble Suppression Enable" "0,1" newline bitfld.long 0x0 26. "BTB,Back to Back transactions" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "PA,Physical Layer Address" newline hexmask.long.byte 0x0 16.--20. 1. "RDA,Register/Device Address" newline bitfld.long 0x0 12.--14. "NTC,Number of Training Clocks" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "CR,CSR Clock Range" newline bitfld.long 0x0 4. "SKAP,Skip Address Packet" "0,1" newline bitfld.long 0x0 2.--3. "GOC,PHY SMA interface Operation Command" "?,1: Write,2: Post Read Increment Address for Clause 45 PHY,3: Read" newline bitfld.long 0x0 1. "C45E,Clause 45 PHY Enable" "0,1" newline bitfld.long 0x0 0. "GB,PHY SMA interface Busy" "0,1" line.long 0x4 "MAC_MDIO_DATA,MAC MDIO data register" hexmask.long.word 0x4 16.--31. 1. "RA,Register Address" newline hexmask.long.word 0x4 0.--15. 1. "GD,PHY management Data" line.long 0x8 "MAC_GPIO_CONTROL,MAC GPIO control register" hexmask.long.word 0x8 16.--31. 1. "GPIT,GPI Type" newline hexmask.long.byte 0x8 0.--3. 1. "GPIE,GPI Interrupt Enable" line.long 0xC "MAC_GPIO_STATUS,MAC GPIO status register" hexmask.long.word 0xC 16.--31. 1. "GPO,General Purpose Output" newline hexmask.long.word 0xC 0.--15. 1. "GPIS,General Purpose Input Status" line.long 0x10 "MAC_ARP_ADDRESS,MAC ARP address register" hexmask.long 0x10 0.--31. 1. "ARPPA,ARP Protocol Address" group.long 0x230++0xB line.long 0x0 "MAC_CSR_SW_CTRL,MAC CSR SW control register" bitfld.long 0x0 0. "RCWE,Register Clear on Write 1 Enable" "0,1" line.long 0x4 "MAC_FPE_CTRL_STS,MAC FPE control STS register" bitfld.long 0x4 19. "TRSP,Transmitted Respond Frame" "0,1" newline bitfld.long 0x4 18. "TVER,Transmitted Verify Frame" "0,1" newline bitfld.long 0x4 17. "RRSP,Received Respond Frame" "0,1" newline bitfld.long 0x4 16. "RVER,Received Verify Frame" "0,1" newline bitfld.long 0x4 3. "S1_SET_0,Synopsys Reserved Must be set to '0'." "0,1" newline bitfld.long 0x4 2. "SRSP,Send Respond mPacket" "0,1" newline bitfld.long 0x4 1. "SVER,Send Verify mPacket" "0,1" newline bitfld.long 0x4 0. "EFPE,Enable Tx Frame Preemption" "0,1" line.long 0x8 "MAC_EXT_CFG1,MAC_Ext_Cfg1 register" bitfld.long 0x8 8.--9. "SPLM,Split Mode" "0: Split at L3/L4 header,1: Split at L2 header with an offset. Always Split..,2: Combination mode: split similar to SPLM=00 for..,?" newline hexmask.long.byte 0x8 0.--6. 1. "SPLOFST,Split Offset" rgroup.long 0x240++0x3 line.long 0x0 "MAC_PRESN_TIME_NS,MAC Presentation Time in Nanoseconds register" hexmask.long 0x0 0.--31. 1. "MPTN,MAC 1722 Presentation Time in ns" group.long 0x244++0x3 line.long 0x0 "MAC_PRESN_TIME_UPDT,MAC Presentation Time Update register" hexmask.long 0x0 0.--31. 1. "MPTU,MAC 1722 Presentation Time Update" group.long 0x300++0xFF line.long 0x0 "MAC_ADDRESS0_HIGH,MAC address 0 high register" bitfld.long 0x0 31. "AE,Address Enable" "0,1" newline bitfld.long 0x0 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "ADDRHI,MAC Address0[47) 32]" line.long 0x4 "MAC_ADDRESS0_LOW,MAC address 0 low register" hexmask.long 0x4 0.--31. 1. "ADDRLO,MAC address 0 [31) 0]" line.long 0x8 "MAC_ADDRESS1_HIGH,MAC address 1 High register" bitfld.long 0x8 31. "AE,Address Enable" "0,1" newline bitfld.long 0x8 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x8 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x8 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xC "MAC_ADDRESS1_LOW,MAC address 1 low register" hexmask.long 0xC 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x10 "MAC_ADDRESS2_HIGH,MAC address 2 High register" bitfld.long 0x10 31. "AE,Address Enable" "0,1" newline bitfld.long 0x10 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x10 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x10 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x14 "MAC_ADDRESS2_LOW,MAC address 2 low register" hexmask.long 0x14 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x18 "MAC_ADDRESS3_HIGH,MAC address 3 High register" bitfld.long 0x18 31. "AE,Address Enable" "0,1" newline bitfld.long 0x18 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x18 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x18 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x18 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x1C "MAC_ADDRESS3_LOW,MAC address 3 low register" hexmask.long 0x1C 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x20 "MAC_ADDRESS4_HIGH,MAC address 4 High register" bitfld.long 0x20 31. "AE,Address Enable" "0,1" newline bitfld.long 0x20 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x20 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x20 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x20 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x24 "MAC_ADDRESS4_LOW,MAC address 4 low register" hexmask.long 0x24 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x28 "MAC_ADDRESS5_HIGH,MAC address 5 High register" bitfld.long 0x28 31. "AE,Address Enable" "0,1" newline bitfld.long 0x28 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x28 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x28 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x28 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x2C "MAC_ADDRESS5_LOW,MAC address 5 low register" hexmask.long 0x2C 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x30 "MAC_ADDRESS6_HIGH,MAC address 6 High register" bitfld.long 0x30 31. "AE,Address Enable" "0,1" newline bitfld.long 0x30 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x30 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x30 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x30 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x34 "MAC_ADDRESS6_LOW,MAC address 6 low register" hexmask.long 0x34 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x38 "MAC_ADDRESS7_HIGH,MAC address 7 High register" bitfld.long 0x38 31. "AE,Address Enable" "0,1" newline bitfld.long 0x38 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x38 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x38 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x38 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x3C "MAC_ADDRESS7_LOW,MAC address 7 low register" hexmask.long 0x3C 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x40 "MAC_ADDRESS8_HIGH,MAC address 8 High register" bitfld.long 0x40 31. "AE,Address Enable" "0,1" newline bitfld.long 0x40 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x40 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x40 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x40 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x44 "MAC_ADDRESS8_LOW,MAC address 8 low register" hexmask.long 0x44 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x48 "MAC_ADDRESS9_HIGH,MAC address 9 High register" bitfld.long 0x48 31. "AE,Address Enable" "0,1" newline bitfld.long 0x48 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x48 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x48 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x48 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x4C "MAC_ADDRESS9_LOW,MAC address 9 low register" hexmask.long 0x4C 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x50 "MAC_ADDRESS10_HIGH,MAC address 10 High register" bitfld.long 0x50 31. "AE,Address Enable" "0,1" newline bitfld.long 0x50 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x50 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x50 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x50 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x54 "MAC_ADDRESS10_LOW,MAC address 10 low register" hexmask.long 0x54 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x58 "MAC_ADDRESS11_HIGH,MAC address 11 High register" bitfld.long 0x58 31. "AE,Address Enable" "0,1" newline bitfld.long 0x58 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x58 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x58 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x58 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x5C "MAC_ADDRESS11_LOW,MAC address 11 low register" hexmask.long 0x5C 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x60 "MAC_ADDRESS12_HIGH,MAC address 12 High register" bitfld.long 0x60 31. "AE,Address Enable" "0,1" newline bitfld.long 0x60 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x60 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x60 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x60 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x64 "MAC_ADDRESS12_LOW,MAC address 12 low register" hexmask.long 0x64 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x68 "MAC_ADDRESS13_HIGH,MAC address 13 High register" bitfld.long 0x68 31. "AE,Address Enable" "0,1" newline bitfld.long 0x68 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x68 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x68 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x68 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x6C "MAC_ADDRESS13_LOW,MAC address 13 low register" hexmask.long 0x6C 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x70 "MAC_ADDRESS14_HIGH,MAC address 14 High register" bitfld.long 0x70 31. "AE,Address Enable" "0,1" newline bitfld.long 0x70 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x70 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x70 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x70 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x74 "MAC_ADDRESS14_LOW,MAC address 14 low register" hexmask.long 0x74 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x78 "MAC_ADDRESS15_HIGH,MAC address 15 High register" bitfld.long 0x78 31. "AE,Address Enable" "0,1" newline bitfld.long 0x78 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x78 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x78 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x78 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x7C "MAC_ADDRESS15_LOW,MAC address 15 low register" hexmask.long 0x7C 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x80 "MAC_ADDRESS16_HIGH,MAC address 16 High register" bitfld.long 0x80 31. "AE,Address Enable" "0,1" newline bitfld.long 0x80 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x80 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x80 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x80 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x84 "MAC_ADDRESS16_LOW,MAC address 16 low register" hexmask.long 0x84 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x88 "MAC_ADDRESS17_HIGH,MAC address 17 High register" bitfld.long 0x88 31. "AE,Address Enable" "0,1" newline bitfld.long 0x88 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x88 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x88 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x88 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x8C "MAC_ADDRESS17_LOW,MAC address 17 low register" hexmask.long 0x8C 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x90 "MAC_ADDRESS18_HIGH,MAC address 18 High register" bitfld.long 0x90 31. "AE,Address Enable" "0,1" newline bitfld.long 0x90 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x90 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x90 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x90 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x94 "MAC_ADDRESS18_LOW,MAC address 18 low register" hexmask.long 0x94 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x98 "MAC_ADDRESS19_HIGH,MAC address 19 High register" bitfld.long 0x98 31. "AE,Address Enable" "0,1" newline bitfld.long 0x98 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x98 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x98 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x98 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x9C "MAC_ADDRESS19_LOW,MAC address 19 low register" hexmask.long 0x9C 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xA0 "MAC_ADDRESS20_HIGH,MAC address 20 High register" bitfld.long 0xA0 31. "AE,Address Enable" "0,1" newline bitfld.long 0xA0 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xA0 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xA0 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xA0 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xA4 "MAC_ADDRESS20_LOW,MAC address 20 low register" hexmask.long 0xA4 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xA8 "MAC_ADDRESS21_HIGH,MAC address 21 High register" bitfld.long 0xA8 31. "AE,Address Enable" "0,1" newline bitfld.long 0xA8 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xA8 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xA8 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xA8 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xAC "MAC_ADDRESS21_LOW,MAC address 21 low register" hexmask.long 0xAC 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xB0 "MAC_ADDRESS22_HIGH,MAC address 22 High register" bitfld.long 0xB0 31. "AE,Address Enable" "0,1" newline bitfld.long 0xB0 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xB0 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xB0 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xB0 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xB4 "MAC_ADDRESS22_LOW,MAC address 22 low register" hexmask.long 0xB4 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xB8 "MAC_ADDRESS23_HIGH,MAC address 23 High register" bitfld.long 0xB8 31. "AE,Address Enable" "0,1" newline bitfld.long 0xB8 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xB8 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xB8 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xB8 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xBC "MAC_ADDRESS23_LOW,MAC address 23 low register" hexmask.long 0xBC 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xC0 "MAC_ADDRESS24_HIGH,MAC address 24 High register" bitfld.long 0xC0 31. "AE,Address Enable" "0,1" newline bitfld.long 0xC0 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xC0 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xC0 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xC0 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xC4 "MAC_ADDRESS24_LOW,MAC address 24 low register" hexmask.long 0xC4 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xC8 "MAC_ADDRESS25_HIGH,MAC address 25 High register" bitfld.long 0xC8 31. "AE,Address Enable" "0,1" newline bitfld.long 0xC8 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xC8 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xC8 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xC8 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xCC "MAC_ADDRESS25_LOW,MAC address 25 low register" hexmask.long 0xCC 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xD0 "MAC_ADDRESS26_HIGH,MAC address 26 High register" bitfld.long 0xD0 31. "AE,Address Enable" "0,1" newline bitfld.long 0xD0 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xD0 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xD0 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xD0 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xD4 "MAC_ADDRESS26_LOW,MAC address 26 low register" hexmask.long 0xD4 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xD8 "MAC_ADDRESS27_HIGH,MAC address 27 High register" bitfld.long 0xD8 31. "AE,Address Enable" "0,1" newline bitfld.long 0xD8 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xD8 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xD8 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xD8 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xDC "MAC_ADDRESS27_LOW,MAC address 27 low register" hexmask.long 0xDC 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xE0 "MAC_ADDRESS28_HIGH,MAC address 28 High register" bitfld.long 0xE0 31. "AE,Address Enable" "0,1" newline bitfld.long 0xE0 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xE0 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xE0 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xE0 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xE4 "MAC_ADDRESS28_LOW,MAC address 28 low register" hexmask.long 0xE4 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xE8 "MAC_ADDRESS29_HIGH,MAC address 29 High register" bitfld.long 0xE8 31. "AE,Address Enable" "0,1" newline bitfld.long 0xE8 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xE8 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xE8 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xE8 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xEC "MAC_ADDRESS29_LOW,MAC address 29 low register" hexmask.long 0xEC 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xF0 "MAC_ADDRESS30_HIGH,MAC address 30 High register" bitfld.long 0xF0 31. "AE,Address Enable" "0,1" newline bitfld.long 0xF0 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xF0 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xF0 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xF0 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xF4 "MAC_ADDRESS30_LOW,MAC address 30 low register" hexmask.long 0xF4 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xF8 "MAC_ADDRESS31_HIGH,MAC address 31 High register" bitfld.long 0xF8 31. "AE,Address Enable" "0,1" newline bitfld.long 0xF8 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xF8 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xF8 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xF8 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xFC "MAC_ADDRESS31_LOW,MAC address 31 low register" hexmask.long 0xFC 0.--31. 1. "ADDRLO,MAC Address n [31:0]" group.long 0x700++0x3 line.long 0x0 "MMC_CONTROL,MMC control register" bitfld.long 0x0 8. "UCDBC,Update MMC Counters for Dropped Broadcast Packets" "0,1" newline bitfld.long 0x0 5. "CNTPRSTLVL,Full-Half Preset" "0,1" newline bitfld.long 0x0 4. "CNTPRST,Counters Preset" "0,1" newline bitfld.long 0x0 3. "CNTFREEZ,MMC Counter Freeze" "0,1" newline bitfld.long 0x0 2. "RSTONRD,Reset on Read" "0,1" newline bitfld.long 0x0 1. "CNTSTOPRO,Counter Stop Rollover" "0,1" newline bitfld.long 0x0 0. "CNTRST,Counters Reset" "0,1" rgroup.long 0x704++0x7 line.long 0x0 "MMC_RX_INTERRUPT,MMC receive interrupt register" bitfld.long 0x0 27. "RXLPITRCIS,MMC Receive LPI Transition Counter Interrupt Status" "0,1" newline bitfld.long 0x0 26. "RXLPIUSCIS,MMC Receive LPI Microsecond Counter Interrupt Status" "0,1" newline bitfld.long 0x0 25. "RXCTRLPIS,MMC Receive Control Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 24. "RXRCVERRPIS,MMC Receive Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 23. "RXWDOGPIS,MMC Receive Watchdog Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 22. "RXVLANGBPIS,MMC Receive VLAN Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 21. "RXFOVPIS,MMC Receive FIFO Overflow Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 20. "RXPAUSPIS,MMC Receive Pause Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 19. "RXORANGEPIS,MMC Receive Out Of Range Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 18. "RXLENERPIS,MMC Receive Length Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 17. "RXUCGPIS,MMC Receive Unicast Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 16. "RX1024TMAXOCTGBPIS,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 15. "RX512T1023OCTGBPIS,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 14. "RX256T511OCTGBPIS,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 13. "RX128T255OCTGBPIS,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 12. "RX65T127OCTGBPIS,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 11. "RX64OCTGBPIS,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 10. "RXOSIZEGPIS,MMC Receive Oversize Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 9. "RXUSIZEGPIS,MMC Receive Undersize Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 8. "RXJABERPIS,MMC Receive Jabber Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 7. "RXRUNTPIS,MMC Receive Runt Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 6. "RXALGNERPIS,MMC Receive Alignment Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIS,MMC Receive CRC Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 4. "RXMCGPIS,MMC Receive Multicast Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 3. "RXBCGPIS,MMC Receive Broadcast Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 2. "RXGOCTIS,MMC Receive Good Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 1. "RXGBOCTIS,MMC Receive Good Bad Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 0. "RXGBPKTIS,MMC Receive Good Bad Packet Counter Interrupt Status" "0,1" line.long 0x4 "MMC_TX_INTERRUPT,MMC Tx interrupt register" bitfld.long 0x4 27. "TXLPITRCIS,MMC Transmit LPI Transition Counter Interrupt Status" "0,1" newline bitfld.long 0x4 26. "TXLPIUSCIS,MMC Transmit LPI Microsecond Counter Interrupt Status" "0,1" newline bitfld.long 0x4 25. "TXOSIZEGPIS,MMC Transmit Oversize Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 24. "TXVLANGPIS,MMC Transmit VLAN Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 23. "TXPAUSPIS,MMC Transmit Pause Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 21. "TXGPKTIS,MMC Transmit Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 20. "TXGOCTIS,MMC Transmit Good Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 13. "TXUFLOWERPIS,MMC Transmit Underflow Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 12. "TXBCGBPIS,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 11. "TXMCGBPIS,MMC Transmit Multicast Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 10. "TXUCGBPIS,MMC Transmit Unicast Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 9. "TX1024TMAXOCTGBPIS,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 8. "TX512T1023OCTGBPIS,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 7. "TX256T511OCTGBPIS,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 6. "TX128T255OCTGBPIS,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 5. "TX65T127OCTGBPIS,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 4. "TX64OCTGBPIS,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 3. "TXMCGPIS,MMC Transmit Multicast Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 2. "TXBCGPIS,MMC Transmit Broadcast Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 1. "TXGBPKTIS,MMC Transmit Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 0. "TXGBOCTIS,MMC Transmit Good Bad Octet Counter Interrupt Status" "0,1" group.long 0x70C++0x7 line.long 0x0 "MMC_RX_INTERRUPT_MASK,MMC Rx interrupt mask register" bitfld.long 0x0 27. "RXLPITRCIM,MMC Receive LPI Transition Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 26. "RXLPIUSCIM,MMC Receive LPI Microsecond Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 25. "RXCTRLPIM,MMC Receive Control Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 24. "RXRCVERRPIM,MMC Receive Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 23. "RXWDOGPIM,MMC Receive Watchdog Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 22. "RXVLANGBPIM,MMC Receive VLAN Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 21. "RXFOVPIM,MMC Receive FIFO Overflow Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 20. "RXPAUSPIM,MMC Receive Pause Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 19. "RXORANGEPIM,MMC Receive Out Of Range Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 18. "RXLENERPIM,MMC Receive Length Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 17. "RXUCGPIM,MMC Receive Unicast Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 16. "RX1024TMAXOCTGBPIM,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 15. "RX512T1023OCTGBPIM,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 14. "RX256T511OCTGBPIM,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 13. "RX128T255OCTGBPIM,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 12. "RX65T127OCTGBPIM,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 11. "RX64OCTGBPIM,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 10. "RXOSIZEGPIM,MMC Receive Oversize Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 9. "RXUSIZEGPIM,MMC Receive Undersize Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 8. "RXJABERPIM,MMC Receive Jabber Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 7. "RXRUNTPIM,MMC Receive Runt Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 6. "RXALGNERPIM,MMC Receive Alignment Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIM,MMC Receive CRC Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 4. "RXMCGPIM,MMC Receive Multicast Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 3. "RXBCGPIM,MMC Receive Broadcast Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 2. "RXGOCTIM,MMC Receive Good Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 1. "RXGBOCTIM,MMC Receive Good Bad Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 0. "RXGBPKTIM,MMC Receive Good Bad Packet Counter Interrupt Mask" "0,1" line.long 0x4 "MMC_TX_INTERRUPT_MASK,MMC Tx interrupt mask register" bitfld.long 0x4 27. "TXLPITRCIM,MMC Transmit LPI Transition Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 26. "TXLPIUSCIM,MMC Transmit LPI Microsecond Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 25. "TXOSIZEGPIM,MMC Transmit Oversize Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 24. "TXVLANGPIM,MMC Transmit VLAN Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 23. "TXPAUSPIM,MMC Transmit Pause Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 21. "TXGPKTIM,MMC Transmit Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 20. "TXGOCTIM,MMC Transmit Good Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 13. "TXUFLOWERPIM,MMC Transmit Underflow Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 12. "TXBCGBPIM,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 11. "TXMCGBPIM,MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 10. "TXUCGBPIM,MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 9. "TX1024TMAXOCTGBPIM,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 8. "TX512T1023OCTGBPIM,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 7. "TX256T511OCTGBPIM,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 6. "TX128T255OCTGBPIM,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 5. "TX65T127OCTGBPIM,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 4. "TX64OCTGBPIM,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 3. "TXMCGPIM,MMC Transmit Multicast Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 2. "TXBCGPIM,MMC Transmit Broadcast Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 1. "TXGBPKTIM,MMC Transmit Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 0. "TXGBOCTIM,MMC Transmit Good Bad Octet Counter Interrupt Mask" "0,1" rgroup.long 0x714++0x37 line.long 0x0 "TX_OCTET_COUNT_GOOD_BAD,Transmit octet count good bad register" hexmask.long 0x0 0.--31. 1. "TXOCTGB,This field indicates the number of bytes transmitted exclusive of preamble and retried bytes in good and bad packets." line.long 0x4 "TX_PACKET_COUNT_GOOD_BAD,Transmit packet count good bad register" hexmask.long 0x4 0.--31. 1. "TXPKTGB,This field indicates the number of good and bad packets transmitted exclusive of retried packets." line.long 0x8 "TX_BROADCAST_PACKETS_GOOD,Transmit broadcast packets good register" hexmask.long 0x8 0.--31. 1. "TXBCASTG,This field indicates the number of good broadcast packets transmitted." line.long 0xC "TX_MULTICAST_PACKETS_GOOD,Transmit multicast packets good register" hexmask.long 0xC 0.--31. 1. "TXMCASTG,This field indicates the number of good multicast packets transmitted." line.long 0x10 "TX_64OCTETS_PACKETS_GOOD_BAD,Transmit 64 octets packets good bad register" hexmask.long 0x10 0.--31. 1. "TX64OCTGB,This field indicates the number of good and bad packets transmitted with length 64 bytes exclusive of preamble and retried packets." line.long 0x14 "TX_65TO127OCTETS_PACKETS_GOOD_BAD,Transmit 65 to 127 octets packets good bad register" hexmask.long 0x14 0.--31. 1. "TX65_127OCTGB,This field indicates the number of good and bad packets transmitted with length between 65 and 127 (inclusive) bytes exclusive of preamble and retried packets." line.long 0x18 "TX_128TO255OCTETS_PACKETS_GOOD_BAD,Transmit 128 to 255 octets packets good bad register" hexmask.long 0x18 0.--31. 1. "TX128_255OCTGB,This field indicates the number of good and bad packets transmitted with length between 128 and 255 (inclusive) bytes exclusive of preamble and retried packets." line.long 0x1C "TX_256TO511OCTETS_PACKETS_GOOD_BAD,Transmit 256 to 511 octets packets good bad register" hexmask.long 0x1C 0.--31. 1. "TX256_511OCTGB,Tx 256To511Octets Packets Good Bad" line.long 0x20 "TX_512TO1023OCTETS_PACKETS_GOOD_BAD,Transmit 512 to 1023 octets packets good bad register" hexmask.long 0x20 0.--31. 1. "TX512_1023OCTGB,Tx 512To1023Octets Packets Good Bad" line.long 0x24 "TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD,Transmit 1024 to Max octets packets good bad register" hexmask.long 0x24 0.--31. 1. "TX1024_MAXOCTGB,Tx 1024ToMaxOctets Packets Good Bad" line.long 0x28 "TX_UNICAST_PACKETS_GOOD_BAD,Transmit unicast packets good bad register" hexmask.long 0x28 0.--31. 1. "TXUCASTGB,Tx Unicast Packets Good Bad" line.long 0x2C "TX_MULTICAST_PACKETS_GOOD_BAD,Transmit multicast packets good bad register" hexmask.long 0x2C 0.--31. 1. "TXMCASTGB,Tx Multicast Packets Good Bad" line.long 0x30 "TX_BROADCAST_PACKETS_GOOD_BAD,Transmit broadcast packets good bad register" hexmask.long 0x30 0.--31. 1. "TXBCASTGB,Tx Broadcast Packets Good Bad" line.long 0x34 "TX_UNDERFLOW_ERROR_PACKETS,Transmit underflow error packets register" hexmask.long 0x34 0.--31. 1. "TXUNDRFLW,Tx Underflow Error Packets" rgroup.long 0x764++0x7 line.long 0x0 "TX_OCTET_COUNT_GOOD,Transmit octet count good register" hexmask.long 0x0 0.--31. 1. "TXOCTG,Tx Octet Count Good" line.long 0x4 "TX_PACKET_COUNT_GOOD,Transmit packet count good register" hexmask.long 0x4 0.--31. 1. "TXPKTG,Tx Packet Count Good" rgroup.long 0x770++0xB line.long 0x0 "TX_PAUSE_PACKETS,Transmit pause packets register" hexmask.long 0x0 0.--31. 1. "TXPAUSE,Tx Pause Packets" line.long 0x4 "TX_VLAN_PACKETS_GOOD,Transmit VLAN packets good register" hexmask.long 0x4 0.--31. 1. "TXVLANG,Tx VLAN Packets Good" line.long 0x8 "TX_OSIZE_PACKETS_GOOD,Transmit O size packets good register" hexmask.long 0x8 0.--31. 1. "TXOSIZG,Tx OSize Packets Good" rgroup.long 0x780++0x67 line.long 0x0 "RX_PACKETS_COUNT_GOOD_BAD,Receive packets count good bad register" hexmask.long 0x0 0.--31. 1. "RXPKTGB,Rx Packets Count Good Bad" line.long 0x4 "RX_OCTET_COUNT_GOOD_BAD,Receive octet count good bad register" hexmask.long 0x4 0.--31. 1. "RXOCTGB,Rx Octet Count Good Bad" line.long 0x8 "RX_OCTET_COUNT_GOOD,Receive octet count good register" hexmask.long 0x8 0.--31. 1. "RXOCTG,Rx Octet Count Good" line.long 0xC "RX_BROADCAST_PACKETS_GOOD,Receive broadcast packets good register" hexmask.long 0xC 0.--31. 1. "RXBCASTG,Rx Broadcast Packets Good" line.long 0x10 "RX_MULTICAST_PACKETS_GOOD,Receive multicast packets good register" hexmask.long 0x10 0.--31. 1. "RXMCASTG,Rx Multicast Packets Good" line.long 0x14 "RX_CRC_ERROR_PACKETS,Receive CRC error packets register" hexmask.long 0x14 0.--31. 1. "RXCRCERR,Rx CRC Error Packets" line.long 0x18 "RX_ALIGNMENT_ERROR_PACKETS,Receive alignment error packets register" hexmask.long 0x18 0.--31. 1. "RXALGNERR,Rx Alignment Error Packets" line.long 0x1C "RX_RUNT_ERROR_PACKETS,Receive runt error packets register" hexmask.long 0x1C 0.--31. 1. "RXRUNTERR,This field indicates the number of packets received with runt (length less than 64 bytes and CRC error) error." line.long 0x20 "RX_JABBER_ERROR_PACKETS,Receive Jabber error packets register" hexmask.long 0x20 0.--31. 1. "RXJABERR,This field indicates the number of giant packets received with length (including CRC) greater than 1518 bytes (1522 bytes for VLAN tagged) and with CRC error. If Jumbo Packet mode is enabled packets of length greater than 9018 bytes (9022 bytes.." line.long 0x24 "RX_UNDERSIZE_PACKETS_GOOD,Receive undersize packets good register" hexmask.long 0x24 0.--31. 1. "RXUNDERSZG,Rx Undersize Packets Good" line.long 0x28 "RX_OVERSIZE_PACKETS_GOOD,Receive oversize packets good register" hexmask.long 0x28 0.--31. 1. "RXOVERSZG,This field indicates the number of packets received without errors with length greater than the maxsize (1518 bytes or 1522 bytes for VLAN tagged packets; 2000 bytes if enabled in the S2KP bit of the MAC_CONFIGURATION register)." line.long 0x2C "RX_64OCTETS_PACKETS_GOOD_BAD,Receive 64 octets packets good bad register" hexmask.long 0x2C 0.--31. 1. "RX64OCTGB,This field indicates the number of good and bad packets received with length 64 bytes exclusive of the preamble." line.long 0x30 "RX_65TO127OCTETS_PACKETS_GOOD_BAD,Receive 65 to 127 octets packets good bad register" hexmask.long 0x30 0.--31. 1. "RX65_127OCTGB,This field indicates the number of good and bad packets received with length between 65 and 127 (inclusive) bytes exclusive of the preamble." line.long 0x34 "RX_128TO255OCTETS_PACKETS_GOOD_BAD,Receive 128 to 255 octets packets good bad register" hexmask.long 0x34 0.--31. 1. "RX128_255OCTGB,This field indicates the number of good and bad packets received with length between 128 and 255 (inclusive) bytes exclusive of the preamble." line.long 0x38 "RX_256TO511OCTETS_PACKETS_GOOD_BAD,Receive 256 to 511 octets packets good bad register" hexmask.long 0x38 0.--31. 1. "RX256_511OCTGB,This field indicates the number of good and bad packets received with length between 256 and 511 (inclusive) bytes exclusive of the preamble." line.long 0x3C "RX_512TO1023OCTETS_PACKETS_GOOD_BAD,Receive 512 to 1023 octets packets good bad register" hexmask.long 0x3C 0.--31. 1. "RX512_1023OCTGB,This field indicates the number of good and bad packets received with length between 512 and 1023 (inclusive) bytes exclusive of the preamble." line.long 0x40 "RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD,Receive 1024 to Max octets packets good bad register" hexmask.long 0x40 0.--31. 1. "RX1024_MAXOCTGB,This field indicates the number of good and bad packets received with length between 1024 and maxsize (inclusive) bytes exclusive of the preamble." line.long 0x44 "RX_UNICAST_PACKETS_GOOD,Receive unicast packets good register" hexmask.long 0x44 0.--31. 1. "RXUCASTG,This field indicates the number of good unicast packets received." line.long 0x48 "RX_LENGTH_ERROR_PACKETS,Receive length error packets" hexmask.long 0x48 0.--31. 1. "RXLENERR,This field indicates the number of packets received with length error (Length Type field not equal to packet size) for all packets with valid length field." line.long 0x4C "RX_OUT_OF_RANGE_TYPE_PACKETS,Receive out of range type packets" hexmask.long 0x4C 0.--31. 1. "RXOUTOFRNG,This field indicates the number of packets received with length field not equal to the valid packet size (greater than 1500 but less than 1536)." line.long 0x50 "RX_PAUSE_PACKETS,Receive pause packets register" hexmask.long 0x50 0.--31. 1. "RXPAUSEPKT,This field indicates the number of good and valid Pause packets received." line.long 0x54 "RX_FIFO_OVERFLOW_PACKETS,Receive FIFO overflow packets register" hexmask.long 0x54 0.--31. 1. "RXFIFOOVFL,This field indicates the number of missed received packets because of FIFO overflow." line.long 0x58 "RX_VLAN_PACKETS_GOOD_BAD,Receive VLAN packets good bad register" hexmask.long 0x58 0.--31. 1. "RXVLANPKTGB,This field indicates the number of good and bad VLAN packets received." line.long 0x5C "RX_WATCHDOG_ERROR_PACKETS,Receive watchdog error packets register" hexmask.long 0x5C 0.--31. 1. "RXWDGERR,This field indicates the number of packets received with error because of watchdog timeout error (packets with a data load larger than 2048 bytes (when JE and WD bits are reset in MAC_CONFIGURATION register) 10240 bytes (when JE bit is set and.." line.long 0x60 "RX_RECEIVE_ERROR_PACKETS,Receive error packets register" hexmask.long 0x60 0.--31. 1. "RXRCVERR,This field indicates the number of packets received with Receive error or Packet Extension error on the MII interface." line.long 0x64 "RX_CONTROL_PACKETS_GOOD,Receive control packets good register" hexmask.long 0x64 0.--31. 1. "RXCTRLG,This field indicates the number of good control packets received." rgroup.long 0x7EC++0xF line.long 0x0 "TX_LPI_USEC_CNTR,Transmit LPI USEC counter" hexmask.long 0x0 0.--31. 1. "TXLPIUSC,This field indicates the number of microseconds Tx LPI is asserted. For every Tx LPI Entry and Exit the Timer value can have an error of +/- 1 microsecond." line.long 0x4 "TX_LPI_TRAN_CNTR,Transmit LPI transaction counter register" hexmask.long 0x4 0.--31. 1. "TXLPITRC,This field indicates the number of times Tx LPI Entry has occurred. Even if Tx LPI Entry occurs in Automate Mode (because of LPITXA bit set in the LPI Control and Status register) the counter increments." line.long 0x8 "RX_LPI_USEC_CNTR,Receive LPI USEC counter" hexmask.long 0x8 0.--31. 1. "RXLPIUSC,This field indicates the number of microseconds Rx LPI is asserted. For every Rx LPI Entry and Exit the Timer value can have an error of +/- 1 microsecond." line.long 0xC "RX_LPI_TRAN_CNTR,Receive LPI transaction counter register" hexmask.long 0xC 0.--31. 1. "RXLPITRC,This field indicates the number of times Rx LPI Entry has occurred." group.long 0x800++0x3 line.long 0x0 "MMC_IPC_RX_INTERRUPT_MASK,MMC IPC receive interrupt mask register" bitfld.long 0x0 29. "RXICMPEROIM,MMC Receive ICMP Error Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 28. "RXICMPGOIM,MMC Receive ICMP Good Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 27. "RXTCPEROIM,MMC Receive TCP Error Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 26. "RXTCPGOIM,MMC Receive TCP Good Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 25. "RXUDPEROIM,MMC Receive UDP Good Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 24. "RXUDPGOIM,MMC Receive IPV6 No Payload Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 23. "RXIPV6NOPAYOIM,MMC Receive IPV6 Header Error Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 22. "RXIPV6HEROIM,MMC Receive IPV6 Good Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 21. "RXIPV6GOIM,MMC Receive IPV6 Good Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 20. "RXIPV4UDSBLOIM,MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 19. "RXIPV4FRAGOIM,MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 18. "RXIPV4NOPAYOIM,MMC Receive IPV4 No Payload Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 17. "RXIPV4HEROIM,MMC Receive IPV4 Header Error Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 16. "RXIPV4GOIM,MMC Receive IPV4 Good Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 13. "RXICMPERPIM,MMC Receive ICMP Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 12. "RXICMPGPIM,MMC Receive ICMP Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 11. "RXTCPERPIM,MMC Receive TCP Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 10. "RXTCPGPIM,MMC Receive TCP Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 9. "RXUDPERPIM,MMC Receive UDP Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 8. "RXUDPGPIM,MMC Receive UDP Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 7. "RXIPV6NOPAYPIM,MMC Receive IPV6 No Payload Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 6. "RXIPV6HERPIM,MMC Receive IPV6 Header Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 5. "RXIPV6GPIM,MMC Receive IPV6 Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 4. "RXIPV4UDSBLPIM,MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 3. "RXIPV4FRAGPIM,MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 2. "RXIPV4NOPAYPIM,MMC Receive IPV4 No Payload Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 1. "RXIPV4HERPIM,MMC Receive IPV4 Header Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 0. "RXIPV4GPIM,MMC Receive IPV4 Good Packet Counter Interrupt Mask" "0,1" rgroup.long 0x808++0x3 line.long 0x0 "MMC_IPC_RX_INTERRUPT,MMC IPC receive interrupt register" bitfld.long 0x0 29. "RXICMPEROIS,MMC Receive ICMP Error Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 28. "RXICMPGOIS,MMC Receive ICMP Good Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 27. "RXTCPEROIS,MMC Receive TCP Error Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 26. "RXTCPGOIS,MMC Receive TCP Good Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 25. "RXUDPEROIS,MMC Receive UDP Error Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 24. "RXUDPGOIS,MMC Receive UDP Good Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 23. "RXIPV6NOPAYOIS,MMC Receive IPV6 No Payload Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 22. "RXIPV6HEROIS,MMC Receive IPV6 Header Error Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 21. "RXIPV6GOIS,MMC Receive IPV6 Good Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 20. "RXIPV4UDSBLOIS,MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 19. "RXIPV4FRAGOIS,MMC Receive IPV4 Fragmented Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 18. "RXIPV4NOPAYOIS,MMC Receive IPV4 No Payload Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 17. "RXIPV4HEROIS,MMC Receive IPV4 Header Error Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 16. "RXIPV4GOIS,MMC Receive IPV4 Good Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 13. "RXICMPERPIS,MMC Receive ICMP Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 12. "RXICMPGPIS,MMC Receive ICMP Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 11. "RXTCPERPIS,MMC Receive TCP Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 10. "RXTCPGPIS,MMC Receive TCP Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 9. "RXUDPERPIS,MMC Receive UDP Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 8. "RXUDPGPIS,MC Receive UDP Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 7. "RXIPV6NOPAYPIS,MMC Receive IPV6 No Payload Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 6. "RXIPV6HERPIS,MMC Receive IPV6 Header Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 5. "RXIPV6GPIS,MMC Receive IPV6 Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 4. "RXIPV4UDSBLPIS,MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 3. "RXIPV4FRAGPIS,MMC Receive IPV4 Fragmented Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 2. "RXIPV4NOPAYPIS,MMC Receive IPV4 No Payload Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 1. "RXIPV4HERPIS,MMC Receive IPV4 Header Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 0. "RXIPV4GPIS,MMC Receive IPV4 Good Packet Counter Interrupt Status" "0,1" rgroup.long 0x810++0x37 line.long 0x0 "RXIPV4_GOOD_PACKETS,Receive IPv4 good packets register" hexmask.long 0x0 0.--31. 1. "RXIPV4GDPKT,This field indicates the number of good IPv4 datagrams received with the TCP UDP or ICMP payload." line.long 0x4 "RXIPV4_HEADER_ERROR_PACKETS,Receive IPv4 header error packets" hexmask.long 0x4 0.--31. 1. "RXIPV4HDRERRPKT,This field indicates the number of IPv4 datagrams received with header (checksum length or version mismatch) errors." line.long 0x8 "RXIPV4_NO_PAYLOAD_PACKETS,Receive IPv4 no payload packets register" hexmask.long 0x8 0.--31. 1. "RXIPV4NOPAYPKT,This field indicates the number of IPv4 datagram packets received that did not have a TCP UDP or ICMP payload." line.long 0xC "RXIPV4_FRAGMENTED_PACKETS,Receive IPv4 fragmented packets register" hexmask.long 0xC 0.--31. 1. "RXIPV4FRAGPKT,This field indicates the number of good IPv4 datagrams received with fragmentation." line.long 0x10 "RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS,Receive IPv4 UDP checksum disabled packets register" hexmask.long 0x10 0.--31. 1. "RXIPV4UDSBLPKT,This field indicates the number of good IPv4 datagrams received that had a UDP payload with checksum disabled." line.long 0x14 "RXIPV6_GOOD_PACKETS,Receive IPv6 good packets register" hexmask.long 0x14 0.--31. 1. "RXIPV6GDPKT,This field indicates the number of good IPv6 datagrams received with the TCP UDP or ICMP payload." line.long 0x18 "RXIPV6_HEADER_ERROR_PACKETS,Receive IPv6 header error packets" hexmask.long 0x18 0.--31. 1. "RXIPV6HDRERRPKT,This field indicates the number of IPv6 datagrams received with header (length or version mismatch) errors." line.long 0x1C "RXIPV6_NO_PAYLOAD_PACKETS,Receive IPv6 payload packets register" hexmask.long 0x1C 0.--31. 1. "RXIPV6NOPAYPKT,This field indicates the number of IPv6 datagram packets received that did not have a TCP UDP or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers." line.long 0x20 "RXUDP_GOOD_PACKETS,Receive UDP good packets register" hexmask.long 0x20 0.--31. 1. "RXUDPGDPKT,This field indicates the number of good IP datagrams received with a good UDP payload. This counter is not updated when the RxIPv4_UDP_Checksum_Disabled_Packets counter is incremented." line.long 0x24 "RXUDP_ERROR_PACKETS,Receive UDP error packets register" hexmask.long 0x24 0.--31. 1. "RXUDPERRPKT,This field indicates the number of good IP datagrams received whose UDP payload has a checksum error." line.long 0x28 "RXTCP_GOOD_PACKETS,Receive TCP good packets register" hexmask.long 0x28 0.--31. 1. "RXTCPGDPKT,This field indicates the number of good IP datagrams received with a good TCP payload." line.long 0x2C "RXTCP_ERROR_PACKETS,Receive TCP error packets register" hexmask.long 0x2C 0.--31. 1. "RXTCPERRPKT,This field indicates the number of good IP datagrams received whose TCP payload has a checksum error." line.long 0x30 "RXICMP_GOOD_PACKETS,Receive ICMP good packets register" hexmask.long 0x30 0.--31. 1. "RXICMPGDPKT,This field indicates the number of good IP datagrams received with a good ICMP payload." line.long 0x34 "RXICMP_ERROR_PACKETS,Receive ICMP error packets register" hexmask.long 0x34 0.--31. 1. "RXICMPERRPKT,This field indicates the number of good IP datagrams received whose ICMP payload has a checksum error." rgroup.long 0x850++0x37 line.long 0x0 "RXIPV4_GOOD_OCTETS,Receive IPv4 Good Octets register" hexmask.long 0x0 0.--31. 1. "RXIPV4GDOCT,This field indicates the number of bytes received in good IPv4 datagrams encapsulating TCP UDP or ICMP data. Ethernet header FCS pad or IP pad bytes are not included in this counter." line.long 0x4 "RXIPV4_HEADER_ERROR_OCTETS,Receive IPv4 header error octets register" hexmask.long 0x4 0.--31. 1. "RXIPV4HDRERROCT,This field indicates the number of bytes received in IPv4 datagrams with header errors (checksum length version mismatch). The value in the Length field of IPv4 header is used to update this counter. Ethernet header FCS pad or IP pad.." line.long 0x8 "RXIPV4_NO_PAYLOAD_OCTETS,Receive IPv4 no payload octets register" hexmask.long 0x8 0.--31. 1. "RXIPV4NOPAYOCT,This field indicates the number of bytes received in IPv4 datagrams that did not have a TCP UDP or ICMP payload. The value in the Length field of IPv4 header is used to update this counter. Ethernet header FCS pad or IP pad bytes are.." line.long 0xC "RXIPV4_FRAGMENTED_OCTETS,Receive IPv4 fragmented octets register" hexmask.long 0xC 0.--31. 1. "RXIPV4FRAGOCT,This field indicates the number of bytes received in fragmented IPv4 datagrams. The value in the Length field of IPv4 header is used to update this counter. Ethernet header FCS pad or IP pad bytes are not included in this counter." line.long 0x10 "RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS,Receive IPv4 UDP checksum disable octets register" hexmask.long 0x10 0.--31. 1. "RXIPV4UDSBLOCT,This field indicates the number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. Ethernet header FCS pad or IP pad bytes are not included in this counter." line.long 0x14 "RXIPV6_GOOD_OCTETS,Receive IPv6 good octets register" hexmask.long 0x14 0.--31. 1. "RXIPV6GDOCT,This field indicates the number of bytes received in good IPv6 datagrams encapsulating TCP UDP or ICMP data. Ethernet header FCS pad or IP pad bytes are not included in this counter." line.long 0x18 "RXIPV6_HEADER_ERROR_OCTETS,Receive header error octets register" hexmask.long 0x18 0.--31. 1. "RXIPV6HDRERROCT,This field indicates the number of bytes received in IPv6 datagrams with header errors (length version mismatch). The value in the Length field of IPv6 header is used to update this counter. Ethernet header FCS pad or IP pad bytes are.." line.long 0x1C "RXIPV6_NO_PAYLOAD_OCTETS,Receive IPv6 no payload octets register" hexmask.long 0x1C 0.--31. 1. "RXIPV6NOPAYOCT,This field indicates the number of bytes received in IPv6 datagrams that did not have a TCP UDP or ICMP payload. The value in the Length field of IPv6 header is used to update this counter. Ethernet header FCS pad or IP pad bytes are.." line.long 0x20 "RXUDP_GOOD_OCTETS,Receive UDP good octets register" hexmask.long 0x20 0.--31. 1. "RXUDPGDOCT,This field indicates the number of bytes received in a good UDP segment. This counter does not count IP header bytes." line.long 0x24 "RXUDP_ERROR_OCTETS,Receive UDP error octets register" hexmask.long 0x24 0.--31. 1. "RXUDPERROCT,This field indicates the number of bytes received in a UDP segment that had checksum errors. This counter does not count IP header bytes." line.long 0x28 "RXTCP_GOOD_OCTETS,Receive TCP good octets register" hexmask.long 0x28 0.--31. 1. "RXTCPGDOCT,This field indicates the number of bytes received in a good TCP segment. This counter does not count IP header bytes." line.long 0x2C "RXTCP_ERROR_OCTETS,Receive TCP error octets register" hexmask.long 0x2C 0.--31. 1. "RXTCPERROCT,This field indicates the number of bytes received in a TCP segment that had checksum errors. This counter does not count IP header bytes." line.long 0x30 "RXICMP_GOOD_OCTETS,Receive ICMP good octets register" hexmask.long 0x30 0.--31. 1. "RXICMPGDOCT,This field indicates the number of bytes received in a good ICMP segment. This counter does not count IP header bytes." line.long 0x34 "RXICMP_ERROR_OCTETS,Receive ICMP error octets register" hexmask.long 0x34 0.--31. 1. "RXICMPERROCT,This field indicates the number of bytes received in a ICMP segment that had checksum errors. This counter does not count IP header bytes." rgroup.long 0x8A0++0x3 line.long 0x0 "MMC_FPE_TX_INTERRUPT,MMC FPE Tx interrupt register" bitfld.long 0x0 1. "HRCIS,MMC Tx Hold Request Counter Interrupt Status" "0,1" newline bitfld.long 0x0 0. "FCIS,MMC Tx FPE Fragment Counter Interrupt status" "0,1" group.long 0x8A4++0x3 line.long 0x0 "MMC_FPE_TX_INTERRUPT_MASK,MMC FPE Tx interrupt mask register" bitfld.long 0x0 1. "HRCIM,MMC Transmit Hold Request Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 0. "FCIM,MMC Transmit Fragment Counter Interrupt Mask" "0,1" rgroup.long 0x8A8++0x7 line.long 0x0 "MMC_TX_FPE_FRAGMENT_CNTR,MMC Tx FPE fragment counter register" hexmask.long 0x0 0.--31. 1. "TXFFC,Tx FPE Fragment counter" line.long 0x4 "MMC_TX_HOLD_REQ_CNTR,MMC Tx hold request counter register" hexmask.long 0x4 0.--31. 1. "TXHRC,Tx Hold Request Counter" rgroup.long 0x8C0++0x3 line.long 0x0 "MMC_FPE_RX_INTERRUPT,MMC FPE Rx interrupt register" bitfld.long 0x0 3. "FCIS,MMC Rx FPE Fragment Counter Interrupt Status" "0,1" newline bitfld.long 0x0 2. "PAOCIS,MMC Rx Packet Assembly OK Counter Interrupt Status" "0,1" newline bitfld.long 0x0 1. "PSECIS,MMC Rx Packet SMD Error Counter Interrupt Status" "0,1" newline bitfld.long 0x0 0. "PAECIS,MMC Rx Packet Assembly Error Counter Interrupt Status" "0,1" group.long 0x8C4++0x3 line.long 0x0 "MMC_FPE_RX_INTERRUPT_MASK,MMC FPE Rx interrupt mask register" bitfld.long 0x0 3. "FCIM,MMC Rx FPE Fragment Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 2. "PAOCIM,MMC Rx Packet Assembly OK Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 1. "PSECIM,MMC Rx Packet SMD Error Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 0. "PAECIM,MMC Rx Packet Assembly Error Counter Interrupt Mask" "0,1" rgroup.long 0x8C8++0xF line.long 0x0 "MMC_RX_PACKET_ASSEMBLY_ERR_CNTR,MMC Rx packet assembly error counter register" hexmask.long 0x0 0.--31. 1. "PAEC,Rx Packet Assembly Error Counter" line.long 0x4 "MMC_RX_PACKET_SMD_ERR_CNTR,MMC Rx packet SMD error counter register" hexmask.long 0x4 0.--31. 1. "PSEC,Rx Packet SMD Error Counter" line.long 0x8 "MMC_RX_PACKET_ASSEMBLY_OK_CNTR,MMC Rx packet assembly OK counter register" hexmask.long 0x8 0.--31. 1. "PAOC,Rx Packet Assembly OK Counter" line.long 0xC "MMC_RX_FPE_FRAGMENT_CNTR,MMC Rx FPE fragment counter register" hexmask.long 0xC 0.--31. 1. "FFC,Rx FPE Fragment Counter" group.long 0x900++0x7 line.long 0x0 "MAC_L3_L4_CONTROL0,Layer 3 and Layer 4 control 0 register" bitfld.long 0x0 28. "DMCHEN0,DMA Channel Select Enable" "0,1" newline bitfld.long 0x0 24.--25. "DMCHN0,DMA Channel Number" "0: Packet is passed by this filter to DMA CH 0,1: Packet is passed by this filter to DMA CH 1,?,?" newline bitfld.long 0x0 21. "L4DPIM0,Layer 4 Destination Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 20. "L4DPM0,Layer 4 Destination Port Match Enable" "0,1" newline bitfld.long 0x0 19. "L4SPIM0,Layer 4 Source Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 18. "L4SPM0,Layer 4 Source Port Match Enable" "0,1" newline bitfld.long 0x0 16. "L4PEN0,Layer 4 Protocol Enable" "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,Layer 3 IP DA Higher Bits Match" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,Layer 3 IP SA Higher Bits Match" newline bitfld.long 0x0 5. "L3DAIM0,Layer 3 IP DA Inverse Match Enable" "0,1" newline bitfld.long 0x0 4. "L3DAM0,Layer 3 IP DA Match Enable" "0,1" newline bitfld.long 0x0 3. "L3SAIM0,Layer 3 IP SA Inverse Match Enable" "0,1" newline bitfld.long 0x0 2. "L3SAM0,Layer 3 IP SA Match Enable" "0,1" newline bitfld.long 0x0 0. "L3PEN0,Layer 3 Protocol Enable" "0,1" line.long 0x4 "MAC_LAYER4_ADDRESS0,Layer 4 address 0 register" hexmask.long.word 0x4 16.--31. 1. "L4DP0,Layer 4 Destination Port Number Field" newline hexmask.long.word 0x4 0.--15. 1. "L4SP0,Layer 4 Source Port Number Field" group.long 0x910++0xF line.long 0x0 "MAC_LAYER3_ADDR0_REG0,Layer 3 address 0 register 0 register" hexmask.long 0x0 0.--31. 1. "L3A00,Layer 3 Address 0 Field" line.long 0x4 "MAC_LAYER3_ADDR1_REG0,Layer3 address1 register 0 register" hexmask.long 0x4 0.--31. 1. "L3A10,Layer 3 Address 1 Field" line.long 0x8 "MAC_LAYER3_ADDR2_REG0,Layer3 address2 register 0 register" hexmask.long 0x8 0.--31. 1. "L3A20,Layer 3 Address 2 Field" line.long 0xC "MAC_LAYER3_ADDR3_REG0,Layer3 address3 register 0 register" hexmask.long 0xC 0.--31. 1. "L3A30,Layer 3 Address 3 Field" group.long 0xB00++0x7 line.long 0x0 "MAC_TIMESTAMP_CONTROL,Timestamp control register" bitfld.long 0x0 28. "AV8021ASMEN,AV 802.1AS Mode Enable" "0,1" newline bitfld.long 0x0 24. "TXTSSTSM,Transmit Timestamp Status Mode" "0,1" newline bitfld.long 0x0 20. "ESTI,External System Time Input" "0,1" newline bitfld.long 0x0 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering" "0,1" newline bitfld.long 0x0 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots" "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master" "0,1" newline bitfld.long 0x0 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages" "0,1" newline bitfld.long 0x0 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP" "0,1" newline bitfld.long 0x0 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over IPv6-UDP" "0,1" newline bitfld.long 0x0 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets" "0,1" newline bitfld.long 0x0 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format" "0,1" newline bitfld.long 0x0 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control" "0,1" newline bitfld.long 0x0 8. "TSENALL,Enable Timestamp for All Packets" "0,1" newline bitfld.long 0x0 6. "PTGE,Presentation Time Generation Enable" "0,1" newline bitfld.long 0x0 5. "TSADDREG,Update Addend Register" "0,1" newline bitfld.long 0x0 3. "TSUPDT,Update Timestamp" "0,1" newline bitfld.long 0x0 2. "TSINIT,Initialize Timestamp" "0,1" newline bitfld.long 0x0 1. "TSCFUPDT,Fine or Coarse Timestamp Update" "0,1" newline bitfld.long 0x0 0. "TSENA,Enable Timestamp" "0,1" line.long 0x4 "MAC_SUB_SECOND_INCREMENT,Sub second increment register" hexmask.long.byte 0x4 16.--23. 1. "SSINC,Sub-second Increment Value" rgroup.long 0xB08++0x7 line.long 0x0 "MAC_SYSTEM_TIME_SECONDS,System time seconds register" hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Second" line.long 0x4 "MAC_SYSTEM_TIME_NANOSECONDS,System time nanoseconds register" hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Seconds" group.long 0xB10++0xF line.long 0x0 "MAC_SYSTEM_TIME_SECONDS_UPDATE,System time seconds update register" hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Seconds" line.long 0x4 "MAC_SYSTEM_TIME_NANOSECONDS_UPDATE,System time nanoseconds update register" bitfld.long 0x4 31. "ADDSUB,Add or Subtract Time" "0,1" newline hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Seconds" line.long 0x8 "MAC_TIMESTAMP_ADDEND,Timestamp addend register" hexmask.long 0x8 0.--31. 1. "TSAR,Timestamp Addend Register" line.long 0xC "MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS,System time higher word seconds register" hexmask.long.word 0xC 0.--15. 1. "TSHWR,Timestamp Higher Word Register" rgroup.long 0xB20++0x3 line.long 0x0 "MAC_TIMESTAMP_STATUS,Timestamp status register" hexmask.long.byte 0x0 25.--29. 1. "ATSNS,Number of Auxiliary Timestamp Snapshots" newline bitfld.long 0x0 24. "ATSSTM,Auxiliary Timestamp Snapshot Trigger Missed" "0,1" newline bitfld.long 0x0 16.--17. "ATSSTN,Auxiliary Timestamp Snapshot Trigger Identifier" "0,1,2,3" newline bitfld.long 0x0 15. "TXTSSIS,Tx Timestamp Status Interrupt Status" "0,1" newline bitfld.long 0x0 3. "TSTRGTERR0,Timestamp Target Time Error" "0,1" newline bitfld.long 0x0 2. "AUXTSTRIG,Auxiliary Timestamp Trigger Snapshot" "0,1" newline bitfld.long 0x0 1. "TSTARGT0,Timestamp Target Time Reached" "0,1" newline bitfld.long 0x0 0. "TSSOVF,Timestamp Seconds Overflow" "0,1" rgroup.long 0xB30++0x7 line.long 0x0 "MAC_TX_TIMESTAMP_STATUS_NANOSECONDS,Transmit timestamp status nanoseconds register" bitfld.long 0x0 31. "TXTSSMIS,Transmit Timestamp Status Missed" "0,1" newline hexmask.long 0x0 0.--30. 1. "TXTSSLO,Transmit Timestamp Status Low" line.long 0x4 "MAC_TX_TIMESTAMP_STATUS_SECONDS,Transmit timestamp status seconds register" hexmask.long 0x4 0.--31. 1. "TXTSSHI,Transmit Timestamp Status High" group.long 0xB40++0x3 line.long 0x0 "MAC_AUXILIARY_CONTROL,Auxiliary control register" bitfld.long 0x0 5. "ATSEN1,Auxiliary Snapshot 1 Enable" "0,1" newline bitfld.long 0x0 4. "ATSEN0,Auxiliary Snapshot 0 Enable" "0,1" newline bitfld.long 0x0 0. "ATSFC,Auxiliary Snapshot FIFO Clear" "0,1" rgroup.long 0xB48++0x7 line.long 0x0 "MAC_AUXILIARY_TIMESTAMP_NANOSECONDS,Auxiliary timestamp nanoseconds register" hexmask.long 0x0 0.--30. 1. "AUXTSLO,Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp." line.long 0x4 "MAC_AUXILIARY_TIMESTAMP_SECONDS,Auxiliary timestamp seconds register" hexmask.long 0x4 0.--31. 1. "AUXTSHI,Contains the lower 32 bits of the Seconds field of the auxiliary timestamp." group.long 0xB50++0xF line.long 0x0 "MAC_TIMESTAMP_INGRESS_ASYM_CORR,Timestamp ingress asymmetry correction register" hexmask.long 0x0 0.--31. 1. "OSTIAC,One-Step Timestamp Ingress Asymmetry Correction" line.long 0x4 "MAC_TIMESTAMP_EGRESS_ASYM_CORR,Timestamp egress asymmetry correction register" hexmask.long 0x4 0.--31. 1. "OSTEAC,One-Step Timestamp Egress Asymmetry Correction" line.long 0x8 "MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND,Timestamp ingress correction nanosecond register" hexmask.long 0x8 0.--31. 1. "TSIC,Timestamp Ingress Correction" line.long 0xC "MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND,Timestamp egress correction nanosecond register" hexmask.long 0xC 0.--31. 1. "TSEC,Timestamp Egress Correction" rgroup.long 0xB68++0x7 line.long 0x0 "MAC_TIMESTAMP_INGRESS_LATENCY,MAC Timestamp ingress latency register" hexmask.long.word 0x0 16.--27. 1. "ITLNS,Ingress Timestamp Latency in sub-nanoseconds" newline hexmask.long.byte 0x0 8.--15. 1. "ITLSNS,Ingress Timestamp Latency in nanoseconds" line.long 0x4 "MAC_TIMESTAMP_EGRESS_LATENCY,MAC timestamp egress latency register" hexmask.long.word 0x4 16.--27. 1. "ETLNS,Egress Timestamp Latency in sub-nanoseconds" newline hexmask.long.byte 0x4 8.--15. 1. "ETLSNS,Egress Timestamp Latency in nanoseconds" group.long 0xB70++0x3 line.long 0x0 "MAC_PPS_CONTROL,MAC PPS control register" bitfld.long 0x0 7. "MCGREN0,MCGR Mode Enable for PPS0 Output" "0: 0th PPS instance is enabled to operate in PPS mode,1: 0th PPS instance is enabled to operate in MCGR.." newline bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS0 Output" "0: Target Time registers are programmed only for..,?,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output Mode Enable" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL_PPSCMD,PPS Output Frequency Control" group.long 0xB80++0xF line.long 0x0 "MAC_PPS0_TARGET_TIME_SECONDS,MAC PPS0 target time seconds register" hexmask.long 0x0 0.--31. 1. "TSTRH0,PPS Target Time Seconds Register" line.long 0x4 "MAC_PPS0_TARGET_TIME_NANOSECONDS,MAC PPS0 target time nanoseconds register" bitfld.long 0x4 31. "TRGTBUSY0,PPS Target Time Register Busy" "0,1" newline hexmask.long 0x4 0.--30. 1. "TTSL0,Target Time Low for PPS Register" line.long 0x8 "MAC_PPS0_INTERVAL,MAC PPS0 interval register" hexmask.long 0x8 0.--31. 1. "PPSINT0,PPS Output Signal Interval" line.long 0xC "MAC_PPS0_WIDTH,MAC PPS0 width register" hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPS Output Signal Width" group.long 0xC00++0x3 line.long 0x0 "MTL_OPERATION_MODE,MTL operation mode register" bitfld.long 0x0 15. "FRPE,Flexible Rx parser Enable" "0: Flexible Rx parser is disabled,1: Flexible Rx parser is enabled" newline bitfld.long 0x0 9. "CNTCLR,Counters Reset" "0: Counters are not reset,1: All counters are reset" newline bitfld.long 0x0 8. "CNTPRST,Counters Preset" "0: Counters Preset is disabled,1: Counters Preset is enabled" newline bitfld.long 0x0 5.--6. "SCHALG,Tx Scheduling Algorithm" "0: WRR algorithm,1: WFQ algorithm when DCB feature is selected,2: DWRR algorithm when DCB feature is selected,3: Strict priority algorithm" newline bitfld.long 0x0 2. "RAA,Receive Arbitration Algorithm" "0: Strict priority (SP),1: Weighted Strict Priority (WSP)" newline bitfld.long 0x0 1. "DTXSTS,Drop Transmit Status" "0: Drop Transmit Status is disabled,1: Drop Transmit Status is enabled" group.long 0xC08++0xB line.long 0x0 "MTL_DBG_CTL,MTL debug access control register" bitfld.long 0x0 17.--18. "EIEC,ECC Inject Error Control for Tx Rx and TSO memories" "0: Insert 1 bit error,1: Insert 2 bit errors,2: Insert 3 bit errors,3: Insert 1 bit error in address field" newline bitfld.long 0x0 16. "EIEE,ECC Inject Error Enable for Tx Rx and TSO memories" "0: ECC Inject Error for Tx Rx and TSO memories is..,1: ECC Inject Error for Tx Rx and TSO memories is.." newline bitfld.long 0x0 15. "STSIE,Transmit Status Available Interrupt Status Enable" "0: Transmit Packet Available Interrupt Status is..,1: Packet Available Interrupt Status is enabled" newline bitfld.long 0x0 14. "PKTIE,Receive Packet Available Interrupt Status Enable" "0: Receive Packet Available Interrupt Status is..,1: Receive Packet Available Interrupt Status is.." newline bitfld.long 0x0 12.--13. "FIFOSEL,FIFO Selected for Access" "0: Tx FIFO,1: Tx Status FIFO (only read access when SLVMOD is..,2: TSO FIFO (cannot be accessed when SLVMOD is set),3: Rx FIFO" newline bitfld.long 0x0 11. "FIFOWREN,FIFO Write Enable" "0: FIFO Write is disabled,1: FIFO Write is enabled" newline bitfld.long 0x0 10. "FIFORDEN,FIFO Read Enable" "0: FIFO Read is disabled,1: FIFO Read is enabled" newline bitfld.long 0x0 9. "RSTSEL,Reset Pointers of Selected FIFO" "0: Reset Pointers of Selected FIFO is disabled,1: Reset Pointers of Selected FIFO is enabled" newline bitfld.long 0x0 8. "RSTALL,Reset All Pointers" "0: Reset All Pointers is disabled,1: Reset All Pointers is enabled" newline bitfld.long 0x0 5.--6. "PKTSTATE,Encoded Packet State" "0: Tx Packet Data / Rx Packet Data,1: Tx Control Word / Rx Normal Status,2: Tx SOP Data / Rx Last Status,3: Tx EOP Data / Rx EOP" newline bitfld.long 0x0 2.--3. "BYTEEN,Byte Enables" "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,2: Byte 0 Byte 1 and Byte 2 are valid,3: All four bytes are valid" newline bitfld.long 0x0 1. "DBGMOD,Debug Mode Access to FIFO" "0: Debug Mode Access to FIFO is disabled,1: Debug Mode Access to FIFO is enabled" newline bitfld.long 0x0 0. "FDBGEN,FIFO Debug Access Enable" "0: FIFO Debug Access is disabled,1: FIFO Debug Access is enabled" line.long 0x4 "MTL_DBG_STS,MTL debug status register" hexmask.long.tbyte 0x4 15.--31. 1. "LOCR,Remaining Locations in the FIFO" newline bitfld.long 0x4 9. "STSI,Transmit Status Available Interrupt Status" "0,1" newline bitfld.long 0x4 8. "PKTI,Receive Packet Available Interrupt Status" "0,1" newline bitfld.long 0x4 3.--4. "BYTEEN,Byte Enables" "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,2: Byte 0 Byte 1 and Byte 2 are valid,3: All four bytes are valid" newline bitfld.long 0x4 1.--2. "PKTSTATE,Encoded Packet State" "0: Tx Packet Data / Rx Packet Data,1: Tx Control Word / Rx Normal Status,2: Tx SOP Data / Rx Last Status,3: Tx EOP Data / Rx EOP" newline bitfld.long 0x4 0. "FIFOBUSY,FIFO Busy" "0,1" line.long 0x8 "MTL_FIFO_DEBUG_DATA,MTL FIFO debug data register" hexmask.long 0x8 0.--31. 1. "FDBGDATA,FIFO Debug Data" rgroup.long 0xC20++0x3 line.long 0x0 "MTL_INTERRUPT_STATUS,MTL interrupt status register" bitfld.long 0x0 23. "MTLPIS,MTL Rx Parser Interrupt Status" "0: MTL Rx Parser Interrupt status not detected,1: MTL Rx Parser Interrupt status detected" newline bitfld.long 0x0 18. "ESTIS,EST (TAS- 802.1Qbv) Interrupt Status" "0: Interrupt status not detected,1: Interrupt status detected" newline bitfld.long 0x0 17. "DBGIS,Debug Interrupt status" "0: Debug Interrupt status not detected,1: Debug Interrupt status detected" newline bitfld.long 0x0 2. "Q2IS,Queue 2 Interrupt status" "0: Queue 2 Interrupt status not detected,1: Queue 2 Interrupt status detected" newline bitfld.long 0x0 1. "Q1IS,Queue 1 Interrupt status" "0: Queue 1 Interrupt status not detected,1: Queue 1 Interrupt status detected" newline bitfld.long 0x0 0. "Q0IS,Queue 0 Interrupt status" "0: Queue 0 Interrupt status not detected,1: Queue 0 Interrupt status detected" group.long 0xC30++0x3 line.long 0x0 "MTL_RXQ_DMA_MAP0,MTL receive queue and DMA channel mapping 0 register" bitfld.long 0x0 20. "Q2DDMACH,Queue 2 Enabled for DA-based DMA Channel Selection" "0,1" newline bitfld.long 0x0 16.--17. "Q2MDMACH,Queue 2 Mapped to DMA Channel" "0: DMA Channel 0,1: DMA Channel 1,2: DMA Channel 2,?" newline bitfld.long 0x0 12. "Q1DDMACH,Queue 1 Enabled for DA-based DMA Channel Selection" "0,1" newline bitfld.long 0x0 8.--9. "Q1MDMACH,Queue 1 Mapped to DMA Channel" "0: DMA Channel 0,1: DMA Channel 1,2: DMA Channel 2,?" newline bitfld.long 0x0 4. "Q0DDMACH,Queue 0 Enabled for DA-based DMA Channel Selection" "0,1" newline bitfld.long 0x0 0.--1. "Q0MDMACH,Queue 0 Mapped to DMA Channel" "0: DMA Channel 0,1: DMA Channel 1,2: DMA Channel 2,?" group.long 0xC40++0x3 line.long 0x0 "MTL_TBS_CTRL,MTL time based scheduling control register" hexmask.long.tbyte 0x0 8.--31. 1. "LEOS,Launch Expiry Offset" newline bitfld.long 0x0 4.--6. "LEGOS,Launch Expiry GSN Offset" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1. "LEOV,Launch Expiry Offset Valid" "0,1" newline bitfld.long 0x0 0. "ESTM,EST offset Mode" "0,1" group.long 0xC50++0x3 line.long 0x0 "MTL_EST_CONTROL,MTL enhancements to scheduled transmission control register" hexmask.long.byte 0x0 24.--31. 1. "PTOV,PTP Time Offset Value" newline hexmask.long.word 0x0 12.--23. 1. "CTOV,Current Time Offset Value" newline bitfld.long 0x0 8.--10. "TILS,Time Interval Left Shift Amount" "0: No left shift needed (equal to x1ns),1: Left shift TI by 1 bit (equal to x2ns),2: Left shift TI by 2 bits (equal to x4ns),3: Left shift TI by 3 bits (equal to x8ns),4: Left shift TI by 4 bits (equal to x16ns),5: Left shift TI by 5 bits (equal to x32ns),6: Left shift TI by 6 bits (equal to x64ns),7: Left shift TI by 7 bits (equal to x128ns)" newline bitfld.long 0x0 6.--7. "LCSE,Loop Count to report Scheduling Error" "0: 4 iterations,1: 8 iterations,2: 16 iterations,3: 32 iterations" newline bitfld.long 0x0 5. "DFBS,Drop Frames causing Scheduling Error" "0,1" newline bitfld.long 0x0 4. "DDBF,Do not Drop frames during Frame Size Error" "0,1" newline bitfld.long 0x0 1. "SSWL,Switch to S/W owned list" "0,1" newline bitfld.long 0x0 0. "EEST,Enable EST" "0,1" group.long 0xC58++0x3 line.long 0x0 "MTL_EST_STATUS,MTL enhancements to scheduled transmission status register" hexmask.long.byte 0x0 16.--19. 1. "CGSN,Current GCL Slot Number" newline hexmask.long.byte 0x0 8.--11. 1. "BTRL,BTR Error Loop Count" newline bitfld.long 0x0 7. "SWOL,S/W owned list" "0,1" newline bitfld.long 0x0 4. "CGCE,Constant Gate Control Error" "0,1" newline bitfld.long 0x0 3. "HLBS,Head-Of-Line Blocking due to Scheduling" "0,1" newline bitfld.long 0x0 2. "HLBF,Head-Of-Line Blocking due to Frame Size" "0,1" newline bitfld.long 0x0 1. "BTRE,BTR Error" "0,1" newline bitfld.long 0x0 0. "SWLC,Switch to S/W owned list Complete" "0,1" group.long 0xC60++0x7 line.long 0x0 "MTL_EST_SCH_ERROR,MTL enhancements to scheduled transmission schedule error register" bitfld.long 0x0 0.--2. "SEQN,Schedule Error Queue Number" "0,1,2,3,4,5,6,7" line.long 0x4 "MTL_EST_FRM_SIZE_ERROR,MTL enhancements to scheduled transmission frame size error register" bitfld.long 0x4 0.--2. "FEQN,Frame Size Error Queue Number" "0,1,2,3,4,5,6,7" rgroup.long 0xC68++0x3 line.long 0x0 "MTL_EST_FRM_SIZE_CAPTURE,MTL enhancements to scheduled transmission frame size capture register" bitfld.long 0x0 16.--17. "HBFQ,Queue Number of HLBF" "0,1,2,3" newline hexmask.long.word 0x0 0.--14. 1. "HBFS,Frame Size of HLBF" group.long 0xC70++0x3 line.long 0x0 "MTL_EST_INTR_ENABLE,MTL enhancements to scheduled transmission interrupt enable register" bitfld.long 0x0 4. "CGCE,Interrupt Enable for CGCE" "0,1" newline bitfld.long 0x0 3. "IEHS,Interrupt Enable for HLBS" "0,1" newline bitfld.long 0x0 2. "IEHF,Interrupt Enable for HLBF" "0,1" newline bitfld.long 0x0 1. "IEBE,Interrupt Enable for BTR Error" "0,1" newline bitfld.long 0x0 0. "IECC,Interrupt Enable for Switch List" "0,1" group.long 0xC80++0x7 line.long 0x0 "MTL_EST_GCL_CONTROL,MTL enhancements to scheduled transmission GCL control register" bitfld.long 0x0 22.--23. "ESTEIEC,ECC Inject Error Control for EST Memory" "0: Insert 1 bit error,1: Insert 2 bit errors,2: Insert 3 bit errors,3: Insert 1 bit error in address field" newline bitfld.long 0x0 21. "ESTEIEE,EST ECC Inject Error Enable" "0: EST ECC Inject Error is disabled,1: EST ECC Inject Error is enabled" newline bitfld.long 0x0 20. "ERR0,When set indicates the last write operation was aborted as software writes to GCL and GCL registers is prohibited when SSWL bit of MTL_EST_CONTROL Register is set." "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "ADDR,Gate Control List Address: (GCLA when GCRR is '0')." newline bitfld.long 0x0 5. "DBGB,Debug Mode Bank Select" "0,1" newline bitfld.long 0x0 4. "DBGM,Debug Mode" "0,1" newline bitfld.long 0x0 2. "GCRR,Gate Control Related Registers" "0,1" newline bitfld.long 0x0 1. "R1W0,Read \q1\q Write \q0\q:" "0,1" newline bitfld.long 0x0 0. "SRWO,Start Read/Write Op" "0,1" line.long 0x4 "MTL_EST_GCL_DATA,MTL enhancements to scheduled transmission gate control data register" hexmask.long 0x4 0.--31. 1. "GCD,Gate Control Data" group.long 0xC90++0x7 line.long 0x0 "MTL_FPE_CTRL_STS,MTL FPE control STS register" bitfld.long 0x0 28. "HRS,Hold/Release Status" "0: Indicates a Set-and-Release-MAC operation was..,1: Indicates a Set-and-Hold-MAC operation was last.." newline bitfld.long 0x0 8.--10. "PEC,Preemption Classification" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--1. "AFSZ,Additional Fragment Size" "0,1,2,3" line.long 0x4 "MTL_FPE_ADVANCE,MTL FPE advance register" hexmask.long.word 0x4 16.--31. 1. "RADV,Release Advance" newline hexmask.long.word 0x4 0.--15. 1. "HADV,Hold Advance" group.long 0xCA0++0x7 line.long 0x0 "MTL_RXP_CONTROL_STATUS,MTL RXP control status register" bitfld.long 0x0 31. "RXPI,RX Parser in Idle state" "0: RX Parser not in Idle state,1: RX Parser in Idle state" newline hexmask.long.byte 0x0 16.--23. 1. "NPE,Number of parsable entries in the Instruction table" newline hexmask.long.byte 0x0 0.--7. 1. "NVE,Number of valid entries in the Instruction table" line.long 0x4 "MTL_RXP_INTERRUPT_CONTROL_STATUS,MTL RXP interrupt control status register" bitfld.long 0x4 19. "PDRFIE,Packet Drop due to RF Interrupt Enable" "0: Packet Drop due to RF Interrupt is disabled,1: Packet Drop due to RF Interrupt is enabled" newline bitfld.long 0x4 18. "FOOVIE,Frame Offset Overflow Interrupt Enable" "0: Frame Offset Overflow Interrupt is disabled,1: Frame Offset Overflow Interrupt is enabled" newline bitfld.long 0x4 17. "NPEOVIE,Number of Parsable Entries Overflow Interrupt Enable" "0: Number of Parsable Entries Overflow Interrupt is..,1: Number of Parsable Entries Overflow Interrupt is.." newline bitfld.long 0x4 16. "NVEOVIE,Number of Valid Entries Overflow Interrupt Enable" "0: Number of Valid Entries Overflow Interrupt is..,1: Number of Valid Entries Overflow Interrupt is.." newline bitfld.long 0x4 3. "PDRFIS,Packet Dropped due to RF Interrupt Status" "0: Packet Dropped due to RF Interrupt Status not..,1: Packet Dropped due to RF Interrupt Status detected" newline bitfld.long 0x4 2. "FOOVIS,Frame Offset Overflow Interrupt Status" "0: Frame Offset Overflow Interrupt Status not..,1: Frame Offset Overflow Interrupt Status detected" newline bitfld.long 0x4 1. "NPEOVIS,Number of Parsable Entries Overflow Interrupt Status" "0: Number of Parsable Entries Overflow Interrupt..,1: Number of Parsable Entries Overflow Interrupt.." newline bitfld.long 0x4 0. "NVEOVIS,Number of Valid Entries Overflow Interrupt Status" "0: Number of Valid Entries Overflow Interrupt..,1: Number of Valid Entries Overflow Interrupt.." rgroup.long 0xCA8++0x7 line.long 0x0 "MTL_RXP_DROP_CNT,MTL RXP drop count register" bitfld.long 0x0 31. "RXPDCOVF,Rx Parser Drop Counter Overflow Bit" "0: Rx Parser Drop count overflow not occurred,1: Rx Parser Drop count overflow occurred" newline hexmask.long 0x0 0.--30. 1. "RXPDC,Rx Parser Drop count" line.long 0x4 "MTL_RXP_ERROR_CNT,MTL RXP error count register" bitfld.long 0x4 31. "RXPECOVF,Rx Parser Error Counter Overflow Bit" "0: Rx Parser Error count overflow not occurred,1: Rx Parser Error count overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPEC,Rx Parser Error count" group.long 0xCB0++0x3 line.long 0x0 "MTL_RXP_INDIRECT_ACC_CONTROL_STATUS,MTL RXP indirect access control status register" bitfld.long 0x0 31. "STARTBUSY,FRP Instruction Table Access Busy" "0: Hardware not busy,1: Hardware is busy (Read/Write operation from/to.." newline bitfld.long 0x0 21.--22. "RXPEIEC,ECC Inject Error Control for Rx Parser Memory" "0: Insert 1 bit error,1: Insert 2 bit errors,2: Insert 3 bit errors,3: Insert 1 bit error in address field" newline bitfld.long 0x0 20. "RXPEIEE,ECC Inject Error Enable for Rx Parser Memory" "0: ECC Inject Error for Rx Parser Memory is disabled,1: ECC Inject Error for Rx Parser Memory is enabled" newline bitfld.long 0x0 16. "WRRDN,Read Write Control" "0: Read operation to the Rx Parser Memory,1: Write operation to the Rx Parser Memory" newline hexmask.long.word 0x0 0.--9. 1. "ADDR,FRP Instruction Table Offset Address" rgroup.long 0xCB4++0x3 line.long 0x0 "MTL_RXP_INDIRECT_ACC_DATA,MTL RXP indirect access data register" hexmask.long 0x0 0.--31. 1. "DATA,FRP Instruction Table Write/Read Data" group.long 0xCC0++0x3 line.long 0x0 "MTL_ECC_CONTROL,MTL ECC Control register" bitfld.long 0x0 8. "MEEAO,MTL ECC Error Address Status Over-ride" "0: MTL ECC Error Address Status Over-ride is disabled,1: MTL ECC Error Address Status Over-ride is enabled" newline bitfld.long 0x0 3. "MRXPEE,MTL Rx Parser ECC Enable" "0: MTL Rx Parser ECC is disabled,1: MTL Rx Parser ECC is enabled" newline bitfld.long 0x0 2. "MESTEE,MTL EST ECC Enable" "0: MTL EST ECC is disabled,1: MTL EST ECC is enabled" newline bitfld.long 0x0 1. "MRXEE,MTL Rx FIFO ECC Enable" "0: MTL Rx FIFO ECC is disabled,1: MTL Rx FIFO ECC is enabled" newline bitfld.long 0x0 0. "MTXEE,MTL Tx FIFO ECC Enable" "0: MTL Tx FIFO ECC is disabled,1: MTL Tx FIFO ECC is enabled" rgroup.long 0xCC4++0x3 line.long 0x0 "MTL_SAFETY_INTERRUPT_STATUS,MTL Safety Interrupt Status register" bitfld.long 0x0 31. "MCSIS,MAC Safety Uncorrectable Interrupt Status" "0: MAC Safety Uncorrectable Interrupt Status not..,1: MAC Safety Uncorrectable Interrupt Status detected" newline bitfld.long 0x0 1. "MEUIS,MTL ECC Uncorrectable error Interrupt Status" "0: MTL ECC Uncorrectable error Interrupt Status not..,1: MTL ECC Uncorrectable error Interrupt Status.." newline bitfld.long 0x0 0. "MECIS,MTL ECC Correctable error Interrupt Status" "0: MTL ECC Correctable error Interrupt Status not..,1: MTL ECC Correctable error Interrupt Status.." group.long 0xCC8++0xB line.long 0x0 "MTL_ECC_INTERRUPT_ENABLE,MTL ECC interrupt enable register" bitfld.long 0x0 12. "RPCEIE,Rx Parser memory Correctable Error Interrupt Enable" "0: Rx Parser memory Correctable Error Interrupt is..,1: Rx Parser memory Correctable Error Interrupt is.." newline bitfld.long 0x0 8. "ECEIE,EST memory Correctable Error Interrupt Enable" "0: EST memory Correctable Error Interrupt is disabled,1: EST memory Correctable Error Interrupt is enabled" newline bitfld.long 0x0 4. "RXCEIE,Rx memory Correctable Error Interrupt Enable" "0: Rx memory Correctable Error Interrupt is disabled,1: Rx memory Correctable Error Interrupt is enabled" newline bitfld.long 0x0 0. "TXCEIE,Tx memory Correctable Error Interrupt Enable" "0: Tx memory Correctable Error Interrupt is disabled,1: Tx memory Correctable Error Interrupt is enabled" line.long 0x4 "MTL_ECC_INTERRUPT_STATUS,MTL ECC interrupt status register" bitfld.long 0x4 14. "RPUES,Rx Parser memory Uncorrectable Error Status" "0: Rx Parser memory Uncorrectable Error Status not..,1: Rx Parser memory Uncorrectable Error Status.." newline bitfld.long 0x4 13. "RPAMS,MTL Rx Parser memory Address Mismatch Status" "0: MTL Rx Parser memory Address Mismatch Status not..,1: MTL Rx Parser memory Address Mismatch Status.." newline bitfld.long 0x4 12. "RPCES,MTL Rx Parser memory Correctable Error Status" "0: MTL Rx Parser memory Correctable Error Status..,1: MTL Rx Parser memory Correctable Error Status.." newline bitfld.long 0x4 10. "EUES,MTL EST memory Uncorrectable Error Status" "0: MTL EST memory Uncorrectable Error Status not..,1: MTL EST memory Uncorrectable Error Status detected" newline bitfld.long 0x4 9. "EAMS,MTL EST memory Address Mismatch Status" "0: MTL EST memory Address Mismatch Status not..,1: MTL EST memory Address Mismatch Status detected" newline bitfld.long 0x4 8. "ECES,MTL EST memory Correctable Error Status" "0: MTL EST memory Correctable Error Status not..,1: MTL EST memory Correctable Error Status detected" newline bitfld.long 0x4 6. "RXUES,MTL Rx memory Uncorrectable Error Status" "0: MTL Rx memory Uncorrectable Error Status not..,1: MTL Rx memory Uncorrectable Error Status detected" newline bitfld.long 0x4 5. "RXAMS,MTL Rx memory Address Mismatch Status" "0: MTL Rx memory Address Mismatch Status not detected,1: MTL Rx memory Address Mismatch Status detected" newline bitfld.long 0x4 4. "RXCES,MTL Rx memory Correctable Error Status" "0: MTL Rx memory correctable Error Status not..,1: MTL Rx memory correctable Error Status detected" newline bitfld.long 0x4 2. "TXUES,MTL Tx memory Uncorrectable Error Status" "0: MTL Tx memory Uncorrectable Error Status not..,1: MTL Tx memory Uncorrectable Error Status detected" newline bitfld.long 0x4 1. "TXAMS,MTL Tx memory Address Mismatch Status" "0: MTL Tx memory Address Mismatch Status not detected,1: MTL Tx memory Address Mismatch Status detected" newline bitfld.long 0x4 0. "TXCES,MTL Tx memory Correctable Error Status" "0: MTL Tx memory Correctable Error Status not..,1: MTL Tx memory Correctable Error Status detected" line.long 0x8 "MTL_ECC_ERR_STS_RCTL,MTL ECC Error Status Rctl register" bitfld.long 0x8 5. "CUES,Clear Uncorrectable Error Status" "0: Clear Uncorrectable Error Status not detected,1: Clear Uncorrectable Error Status detected" newline bitfld.long 0x8 4. "CCES,Clear Correctable Error Status" "0: Clear Correctable Error Status not detected,1: Clear Correctable Error Status detected" newline bitfld.long 0x8 1.--3. "EMS,MTL ECC Memory Selection" "0: MTL Tx memory,1: MTL Rx memory,2: MTL EST memory,3: MTL Rx Parser memory,4: DMA TSO memory,?,?,?" newline bitfld.long 0x8 0. "EESRE,MTL ECC Error Status Read Enable" "0: MTL ECC Error Status Read is disabled,1: MTL ECC Error Status Read is enabled" rgroup.long 0xCD4++0x7 line.long 0x0 "MTL_ECC_ERR_ADDR_STATUS,MTL ECC Error Address Status register" hexmask.long.word 0x0 16.--31. 1. "EUEAS,MTL ECC Uncorrectable Error Address Status" newline hexmask.long.word 0x0 0.--15. 1. "ECEAS,MTL ECC Correctable Error Address Status" line.long 0x4 "MTL_ECC_ERR_CNTR_STATUS,MTL ECC Error Counter Status register" hexmask.long.byte 0x4 16.--19. 1. "EUECS,MTL ECC Uncorrectable Error Counter Status" newline hexmask.long.byte 0x4 0.--7. 1. "ECECS,MTL ECC Correctable Error Counter Status" group.long 0xCE0++0x3 line.long 0x0 "MTL_DPP_CONTROL,MTL Data Parity Protection Control register" bitfld.long 0x0 11. "IPERD,Insert Parity error in Rx write-back Descriptor parity generator" "0: Insert Parity error in Rx write-back Descriptor..,1: Insert Parity error in Rx write-back Descriptor.." newline bitfld.long 0x0 10. "IPETD,Insert Parity error in Tx write-back Descriptor parity generator" "0: Insert Parity error in Tx write-back Descriptor..,1: Insert Parity error in Tx write-back Descriptor.." newline bitfld.long 0x0 9. "IPETSO,Insert Parity Error in DMA TSO parity generator" "0: Insert Parity Error in DMA TSO parity generator..,1: Insert Parity Error in DMA TSO parity generator.." newline bitfld.long 0x0 8. "IPEDDC,Insert Parity Error in DMA DTX Control word parity generator" "0: Insert Parity Error in DMA DTX Control word..,1: Insert Parity Error in DMA DTX Control word.." newline bitfld.long 0x0 7. "IPEMRF,Insert Parity Error in MTL Rx FIFO read control parity generator" "0: Insert Parity Error in MTL Rx FIFO read control..,1: Insert Parity Error in MTL Rx FIFO read control.." newline bitfld.long 0x0 6. "IPEMTS,Insert Parity Error in MTL Tx Status parity generator" "0: Insert Parity Error in MTL Tx Status parity..,1: Insert Parity Error in MTL Tx Status parity.." newline bitfld.long 0x0 5. "IPEMC,Insert Parity Error in MTL checksum parity generator" "0: Insert Parity Error in MTL checksum parity..,1: Insert Parity Error in MTL checksum parity.." newline bitfld.long 0x0 4. "IPEID,Insert Parity Error in Interface Data parity generator" "0: Insert Parity Error in Interface Data parity..,1: Insert Parity Error in Interface Data parity.." newline bitfld.long 0x0 2. "EPSI,Enable Parity on Slave Interface port" "0: Parity on Slave Interface port is disabled,1: Parity on Slave Interface port is enabled" newline bitfld.long 0x0 1. "OPE,Odd Parity Enable" "0: Odd Parity is disabled,1: Odd Parity is enabled" newline bitfld.long 0x0 0. "EDPP,Enable Data path Parity Protection" "0: Data path Parity Protection is disabled,1: Data path Parity Protection is enabled" group.long 0xD00++0x3 line.long 0x0 "MTL_TXQ0_OPERATION_MODE,MTL queue 0 transmit operation mode register" hexmask.long.byte 0x0 16.--21. 1. "TQS,Transmit Queue Size" newline bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable" "0: Not enabled,?,2: Enabled,?" newline bitfld.long 0x0 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0xD04++0x7 line.long 0x0 "MTL_TXQ0_UNDERFLOW,MTL queue 0 underflow counter register" bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "MTL_TXQ0_DEBUG,MTL queue 0 transmit debug register" bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status" "0,1" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status" "0,1" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status" "0,1" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause" "0,1" rgroup.long 0xD14++0x3 line.long 0x0 "MTL_TXQ0_ETS_STATUS,MTL queue 0 ETS status register" hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot" group.long 0xD18++0x3 line.long 0x0 "MTL_TXQ0_QUANTUM_WEIGHT,MTL queue 0 quantum or weights register" hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,When WRR algorithm is enabled for Queue 0 traffic this field contains the weight for this queue. The maximum value is 0x64." group.long 0xD2C++0x7 line.long 0x0 "MTL_Q0_INTERRUPT_CONTROL_STATUS,MTL interrupt control status register" bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status" "0,1" newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable" "0,1" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status" "0,1" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status" "0,1" line.long 0x4 "MTL_RXQ0_OPERATION_MODE,MTL RX queue 0 receive operation mode register" hexmask.long.byte 0x4 20.--25. 1. "RQS,Receive Queue Size" newline hexmask.long.byte 0x4 14.--18. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)" newline hexmask.long.byte 0x4 8.--12. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets" "0,1" newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward" "0,1" newline bitfld.long 0x4 4. "FEP,Forward Error Packets" "0,1" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets" "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control" "0: 64,1: 32,2: 96,3: 128" rgroup.long 0xD34++0x7 line.long 0x0 "MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT,MTL RX Queue 0 missed packet and overflow counter register" bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter" newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter" line.long 0x4 "MTL_RXQ0_DEBUG,MTL RX Queue 0 receive debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue" newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status" "0,1" group.long 0xD3C++0x7 line.long 0x0 "MTL_RXQ0_CONTROL,MTL RX Queue receive control register" bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration" "0,1" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight" "0,1,2,3,4,5,6,7" line.long 0x4 "MTL_TXQ1_OPERATION_MODE,MTL Transmit Qn operation mode register" hexmask.long.byte 0x4 16.--21. 1. "TQS,Transmit Queue Size" newline bitfld.long 0x4 4.--6. "TTC,Transmit Threshold Control" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x4 2.--3. "TXQEN,Transmit Queue Enable" "0: Not enabled,1: Enable in AV mode,2: Enabled,?" newline bitfld.long 0x4 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x4 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0xD44++0x7 line.long 0x0 "MTL_TXQ1_UNDERFLOW,MTL Transmit Qn underflow register" bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "MTL_TXQ1_DEBUG,MTL Transmit Qn debug register" bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status" "0,1" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status" "0,1" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status" "0,1" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause" "0,1" group.long 0xD50++0x3 line.long 0x0 "MTL_TXQ1_ETS_CONTROL,MTL Transmit Qn ETS control register" bitfld.long 0x0 4.--6. "SLC,Slot Count" "0: 1 Slot,1: 2 Slots,2: 4 Slots,3: 8 Slots,4: 16 Slots,?,?,?" newline bitfld.long 0x0 3. "CC,Credit Control" "0,1" newline bitfld.long 0x0 2. "AVALG,AV Algorithm" "0,1" rgroup.long 0xD54++0x3 line.long 0x0 "MTL_TXQ1_ETS_STATUS,MTL Transmit Qn ETS status register" hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot" group.long 0xD58++0xF line.long 0x0 "MTL_TXQ1_QUANTUM_WEIGHT,MTL Transmit Qn quantum weight register" hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights" line.long 0x4 "MTL_TXQ1_SENDSLOPECREDIT,MTL Transmit Qn send slope credit register" hexmask.long.word 0x4 0.--13. 1. "SSC,SendSlopeCredit" line.long 0x8 "MTL_TXQ1_HICREDIT,MTL Transmit Qn high credit register" hexmask.long 0x8 0.--28. 1. "HC,HiCredit" line.long 0xC "MTL_TXQ1_LOCREDIT,MTL Transmit Qn low credit register" hexmask.long 0xC 0.--28. 1. "LC,loCredit" group.long 0xD6C++0x7 line.long 0x0 "MTL_Q1_INTERRUPT_CONTROL_STATUS,MTL Qn interrupt control status register" bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status" "0,1" newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable" "0,1" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status" "0,1" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status" "0,1" line.long 0x4 "MTL_RXQ1_OPERATION_MODE,MTL Receive Qn operation mode register" hexmask.long.byte 0x4 20.--25. 1. "RQS,Receive Queue Size" newline hexmask.long.byte 0x4 14.--18. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)" newline hexmask.long.byte 0x4 8.--12. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex modes)" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets" "0,1" newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward" "0,1" newline bitfld.long 0x4 4. "FEP,Forward Error Packets" "0,1" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets" "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control" "0: 64,1: 32,2: 96,3: 128" rgroup.long 0xD74++0x7 line.long 0x0 "MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT,MTL Receive Qn missed packet and overflow counter register" bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter" newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter" line.long 0x4 "MTL_RXQ1_DEBUG,MTL Receive Qn debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue" newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status" "0,1" group.long 0xD7C++0x7 line.long 0x0 "MTL_RXQ1_CONTROL,MTL Receive Qn control register" bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration" "0,1" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight" "0,1,2,3,4,5,6,7" line.long 0x4 "MTL_TXQ2_OPERATION_MODE,MTL Transmit Qn operation mode register" hexmask.long.byte 0x4 16.--21. 1. "TQS,Transmit Queue Size" newline bitfld.long 0x4 4.--6. "TTC,Transmit Threshold Control" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x4 2.--3. "TXQEN,Transmit Queue Enable" "0: Not enabled,1: Enable in AV mode,2: Enabled,?" newline bitfld.long 0x4 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x4 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0xD84++0x7 line.long 0x0 "MTL_TXQ2_UNDERFLOW,MTL Transmit Qn underflow register" bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "MTL_TXQ2_DEBUG,MTL Transmit Qn debug register" bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status" "0,1" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status" "0,1" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status" "0,1" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause" "0,1" group.long 0xD90++0x3 line.long 0x0 "MTL_TXQ2_ETS_CONTROL,MTL Transmit Qn ETS control register" bitfld.long 0x0 4.--6. "SLC,Slot Count" "0: 1 Slot,1: 2 Slots,2: 4 Slots,3: 8 Slots,4: 16 Slots,?,?,?" newline bitfld.long 0x0 3. "CC,Credit Control" "0,1" newline bitfld.long 0x0 2. "AVALG,AV Algorithm" "0,1" rgroup.long 0xD94++0x3 line.long 0x0 "MTL_TXQ2_ETS_STATUS,MTL Transmit Qn ETS status register" hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot" group.long 0xD98++0xF line.long 0x0 "MTL_TXQ2_QUANTUM_WEIGHT,MTL Transmit Qn quantum weight register" hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights" line.long 0x4 "MTL_TXQ2_SENDSLOPECREDIT,MTL Transmit Qn send slope credit register" hexmask.long.word 0x4 0.--13. 1. "SSC,SendSlopeCredit" line.long 0x8 "MTL_TXQ2_HICREDIT,MTL Transmit Qn high credit register" hexmask.long 0x8 0.--28. 1. "HC,HiCredit" line.long 0xC "MTL_TXQ2_LOCREDIT,MTL Transmit Qn low credit register" hexmask.long 0xC 0.--28. 1. "LC,loCredit" group.long 0xDAC++0x7 line.long 0x0 "MTL_Q2_INTERRUPT_CONTROL_STATUS,MTL Qn interrupt control status register" bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status" "0,1" newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable" "0,1" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status" "0,1" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status" "0,1" line.long 0x4 "MTL_RXQ2_OPERATION_MODE,MTL Receive Qn operation mode register" hexmask.long.byte 0x4 20.--25. 1. "RQS,Receive Queue Size" newline hexmask.long.byte 0x4 14.--18. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)" newline hexmask.long.byte 0x4 8.--12. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex modes)" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets" "0,1" newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward" "0,1" newline bitfld.long 0x4 4. "FEP,Forward Error Packets" "0,1" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets" "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control" "0: 64,1: 32,2: 96,3: 128" rgroup.long 0xDB4++0x7 line.long 0x0 "MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT,MTL Receive Qn missed packet and overflow counter register" bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter" newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter" line.long 0x4 "MTL_RXQ2_DEBUG,MTL Receive Qn debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue" newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status" "0,1" group.long 0xDBC++0x3 line.long 0x0 "MTL_RXQ2_CONTROL,MTL Receive Qn control register" bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration" "0,1" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight" "0,1,2,3,4,5,6,7" group.long 0x1000++0x7 line.long 0x0 "DMA_MODE,DMA mode register" bitfld.long 0x0 16.--17. "INTM,Interrupt Mode" "0: sbd_perch_* are pulse signals for each..,1: sbd_perch_* are level signals asserted on..,2: sbd_perch_* are level signals asserted on..,?" newline bitfld.long 0x0 12.--14. "PR,Priority Ratio" "0: The priority ratio is 1:1,1: The priority ratio is 2:1,2: The priority ratio is 3:1,3: The priority ratio is 4:1,4: The priority ratio is 5:1,5: The priority ratio is 6:1,6: The priority ratio is 7:1,7: The priority ratio is 8:1" newline bitfld.long 0x0 11. "TXPR,Transmit Priority" "0,1" newline bitfld.long 0x0 2.--4. "TAA,Transmit Arbitration Algorithm" "0: Fixed priority,1: Weighted Strict Priority (WSP),2: Weighted Round-Robin (WRR),?,?,?,?,?" newline bitfld.long 0x0 1. "DA,DMA Tx or Rx Arbitration Scheme" "0: Weighted Round-Robin with Rx:Tx or Tx:Rx,1: Fixed Priority" newline bitfld.long 0x0 0. "SWR,Software Reset" "0,1" line.long 0x4 "DMA_SYSBUS_MODE,DMA system bus mode register" bitfld.long 0x4 15. "RB,Rebuild INCRx Burst" "0,1" newline bitfld.long 0x4 14. "MB,Mixed Burst" "0,1" newline bitfld.long 0x4 12. "AAL,Address-Aligned Beats" "0,1" newline bitfld.long 0x4 0. "FB,Fixed Burst Length" "0,1" rgroup.long 0x1008++0x7 line.long 0x0 "DMA_INTERRUPT_STATUS,DMA interrupt status register" bitfld.long 0x0 17. "MACIS,MAC Interrupt Status" "0,1" newline bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status" "0,1" newline bitfld.long 0x0 2. "DC2IS,DMA Channel 2 Interrupt Status" "0,1" newline bitfld.long 0x0 1. "DC1IS,DMA Channel 1 Interrupt Status" "0,1" newline bitfld.long 0x0 0. "DC0IS,DMA Channel 0 Interrupt Status" "0,1" line.long 0x4 "DMA_DEBUG_STATUS0,DMA debug status 0 register" hexmask.long.byte 0x4 28.--31. 1. "TPS2,DMA Channel 2 Transmit Process State" newline hexmask.long.byte 0x4 24.--27. 1. "RPS2,DMA Channel 2 Receive Process State" newline hexmask.long.byte 0x4 20.--23. 1. "TPS1,DMA Channel 1 Transmit Process State" newline hexmask.long.byte 0x4 16.--19. 1. "RPS1,DMA Channel 1 Receive Process State" newline hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel 0 Transmit Process State" newline hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel 0 Receive Process State" newline bitfld.long 0x4 0. "AXWHSTS,AHB Master Status" "0,1" group.long 0x1050++0x3 line.long 0x0 "DMA_TBS_CTRL,DMA TBS control register" hexmask.long.tbyte 0x0 8.--31. 1. "FTOS,Fetch Time Offset" newline bitfld.long 0x0 4.--6. "FGOS,Fetch GSN Offset" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "FTOV,Fetch Time Offset Valid" "0,1" rgroup.long 0x1080++0x3 line.long 0x0 "DMA_SAFETY_INTERRUPT_STATUS,DMA safety interrupt status register" bitfld.long 0x0 31. "MCSIS,MAC Safety Uncorrectable Interrupt Status" "0: MAC Safety Uncorrectable Interrupt Status not..,1: MAC Safety Uncorrectable Interrupt Status detected" newline bitfld.long 0x0 29. "MSUIS,MTL Safety Uncorrectable error Interrupt Status" "0: MTL Safety Uncorrectable error Interrupt Status..,1: MTL Safety Uncorrectable error Interrupt Status.." newline bitfld.long 0x0 28. "MSCIS,MTL Safety Correctable error Interrupt Status" "0: MTL Safety Correctable error Interrupt Status..,1: MTL Safety Correctable error Interrupt Status.." newline bitfld.long 0x0 1. "DEUIS,DMA ECC Uncorrectable error Interrupt Status" "0: DMA ECC Uncorrectable error Interrupt Status not..,1: DMA ECC Uncorrectable error Interrupt Status.." newline bitfld.long 0x0 0. "DECIS,DMA ECC Correctable error Interrupt Status" "0: DMA ECC Correctable error Interrupt Status not..,1: DMA ECC Correctable error Interrupt Status.." group.long 0x1100++0xB line.long 0x0 "DMA_CH0_CONTROL,DMA channel 0 control register" bitfld.long 0x0 24. "SPH,Split Headers" "0,1" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" newline hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "DMA_CH0_TX_CONTROL,DMA channel 0 transmit control register" bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable" "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length" newline bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" newline bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" newline bitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command" "0,1" line.long 0x8 "DMA_CH0_RX_CONTROL,DMA channel 0 receive control register" bitfld.long 0x8 31. "RPF,Rx Packet Flush" "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length" newline hexmask.long.word 0x8 4.--14. 1. "RBSZ_13_Y,Receive Buffer size High" newline bitfld.long 0x8 1.--3. "RBSZ_X_0,Receive Buffer size Low" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1114++0x3 line.long 0x0 "DMA_CH0_TXDESC_LIST_ADDRESS,DMA channel 0 transmit descriptor list address register" hexmask.long 0x0 3.--31. 1. "TDESLA,Start of Transmit List" group.long 0x111C++0x7 line.long 0x0 "DMA_CH0_RXDESC_LIST_ADDRESS,DMA channel 0 receive descriptor list address register" hexmask.long 0x0 3.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "DMA_CH0_TXDESC_TAIL_POINTER,DMA channel 0 transmit descriptor tail pointer register" hexmask.long 0x4 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer" group.long 0x1128++0x17 line.long 0x0 "DMA_CH0_RXDESC_TAIL_POINTER,DMA channel 0 receive descriptor tail pointer" hexmask.long 0x0 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer" line.long 0x4 "DMA_CH0_TXDESC_RING_LENGTH,DMA channel 0 transmit descriptor ring length register" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length" line.long 0x8 "DMA_CH0_RXDESC_RING_LENGTH,DMA channel 0 receive descriptor ring length register" hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length" line.long 0xC "DMA_CH0_INTERRUPT_ENABLE,DMA channel 0 interrupt enable register" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable" "0: : Transmit Interrupt,?" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable" "?,1: : Transmit Process Stopped" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable" "0,1" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable" "0,1" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable" "0,1" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER,DMA channel 0 receive interrupt watchdog timer register" bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units" "0: 256,1: 512,2: 1024,3: 2048" newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count" line.long 0x14 "DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS,DMA channel 0 slot function control status register" hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number" newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value" newline bitfld.long 0x14 1. "ASC,Advance Slot Check" "0,1" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison" "0,1" rgroup.long 0x1144++0x3 line.long 0x0 "DMA_CH0_CURRENT_APP_TXDESC,DMA channel 0 current application transmit descriptor register" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer" rgroup.long 0x114C++0x3 line.long 0x0 "DMA_CH0_CURRENT_APP_RXDESC,DMA channel 0 current application transmit descriptor register" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer" rgroup.long 0x1154++0x3 line.long 0x0 "DMA_CH0_CURRENT_APP_TXBUFFER,DMA channel 0 current application transmit buffer register" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer" rgroup.long 0x115C++0x3 line.long 0x0 "DMA_CH0_CURRENT_APP_RXBUFFER,DMA channel 0 current application receive buffer register" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer" group.long 0x1160++0x3 line.long 0x0 "DMA_CH0_STATUS,DMA channel 0 status register" bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0: : Transmit Interrupt,?" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "?,1: : Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt" "0,1" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" newline bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable" "0,1" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" newline bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x1164++0xB line.long 0x0 "DMA_CH0_MISS_FRAME_CNT,DMA channel 0 miss frame counter register" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MFC,This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CHn_RX_CONTROL register. The counter gets cleared when this register is read." line.long 0x4 "DMA_CH0_RXP_ACCEPT_CNT,DMA Channel 0 RXP Accept Counter register" bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter" line.long 0x8 "DMA_CH0_RX_ERI_CNT,DMA Channel 0 RX Early Receive Interrupt Counter register" hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter" group.long 0x1180++0xB line.long 0x0 "DMA_CH1_CONTROL,DMA channel 1 control register" bitfld.long 0x0 24. "SPH,Split Headers" "0,1" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" line.long 0x4 "DMA_CH1_TX_CONTROL,DMA channel 1 transmit control register" bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable" "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length" newline bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" newline bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" newline bitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command" "0,1" line.long 0x8 "DMA_CH1_RX_CONTROL,DMA channel 1 receive control register" bitfld.long 0x8 31. "RPF,Rx Packet Flush" "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length" newline hexmask.long.word 0x8 4.--14. 1. "RBSZ_13_Y,Receive Buffer size High" newline bitfld.long 0x8 1.--3. "RBSZ_X_0,Receive Buffer size Low" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1194++0x3 line.long 0x0 "DMA_CH1_TXDESC_LIST_ADDRESS,DMA channel 1 transmit descriptor list address register" hexmask.long 0x0 3.--31. 1. "TDESLA,Start of Transmit List" group.long 0x119C++0x7 line.long 0x0 "DMA_CH1_RXDESC_LIST_ADDRESS,DMA channel 1 receive descriptor list address register" hexmask.long 0x0 3.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "DMA_CH1_TXDESC_TAIL_POINTER,DMA channel 1 transmit descriptor tail pointer register" hexmask.long 0x4 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer" group.long 0x11A8++0x17 line.long 0x0 "DMA_CH1_RXDESC_TAIL_POINTER,DMA channel 1 receive descriptor tail pointer" hexmask.long 0x0 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer" line.long 0x4 "DMA_CH1_TXDESC_RING_LENGTH,DMA channel 1 transmit descriptor ring length register" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length" line.long 0x8 "DMA_CH1_RXDESC_RING_LENGTH,DMA channel 1 receive descriptor ring length register" hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length" line.long 0xC "DMA_CH1_INTERRUPT_ENABLE,DMA channel 1 interrupt enable register" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable" "0: : Transmit Interrupt,?" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable" "?,1: : Transmit Process Stopped" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable" "0,1" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable" "0,1" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable" "0,1" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER,DMA channel 1 receive interrupt watchdog timer register" bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units" "0: 256,1: 512,2: 1024,3: 2048" newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count" line.long 0x14 "DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS,DMA channel 1 slot function control status register" hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number" newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value" newline bitfld.long 0x14 1. "ASC,Advance Slot Check" "0,1" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison" "0,1" rgroup.long 0x11C4++0x3 line.long 0x0 "DMA_CH1_CURRENT_APP_TXDESC,DMA channel 1 current application transmit descriptor register" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer" rgroup.long 0x11CC++0x3 line.long 0x0 "DMA_CH1_CURRENT_APP_RXDESC,DMA channel 1 current application transmit descriptor register" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer" rgroup.long 0x11D4++0x3 line.long 0x0 "DMA_CH1_CURRENT_APP_TXBUFFER,DMA channel 1 current application transmit buffer register" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer" rgroup.long 0x11DC++0x3 line.long 0x0 "DMA_CH1_CURRENT_APP_RXBUFFER,DMA channel 1 current application receive buffer register" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer" group.long 0x11E0++0x3 line.long 0x0 "DMA_CH1_STATUS,DMA channel 1 status register" bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0: : Transmit Interrupt,?" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "?,1: : Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt" "0,1" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" newline bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable" "0,1" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" newline bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x11E4++0xB line.long 0x0 "DMA_CH1_MISS_FRAME_CNT,DMA channel 1 miss frame counter register" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MFC,This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CHn_RX_CONTROL register. The counter gets cleared when this register is read." line.long 0x4 "DMA_CH1_RXP_ACCEPT_CNT,DMA Channel 1 RXP Accept Counter register" bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter" line.long 0x8 "DMA_CH1_RX_ERI_CNT,DMA Channel 1 RX Early Receive Interrupt Counter register" hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter" group.long 0x1200++0xB line.long 0x0 "DMA_CH2_CONTROL,DMA channel 2 control register" bitfld.long 0x0 24. "SPH,Split Headers" "0,1" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" line.long 0x4 "DMA_CH2_TX_CONTROL,DMA channel 2 transmit control register" bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable" "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length" newline bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" newline bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" newline bitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command" "0,1" line.long 0x8 "DMA_CH2_RX_CONTROL,DMA channel 2 receive control register" bitfld.long 0x8 31. "RPF,Rx Packet Flush" "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length" newline hexmask.long.word 0x8 4.--14. 1. "RBSZ_13_Y,Receive Buffer size High" newline bitfld.long 0x8 1.--3. "RBSZ_X_0,Receive Buffer size Low" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1214++0x3 line.long 0x0 "DMA_CH2_TXDESC_LIST_ADDRESS,DMA channel 2 transmit descriptor list address register" hexmask.long 0x0 3.--31. 1. "TDESLA,Start of Transmit List" group.long 0x121C++0x7 line.long 0x0 "DMA_CH2_RXDESC_LIST_ADDRESS,DMA channel 2 receive descriptor list address register" hexmask.long 0x0 3.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "DMA_CH2_TXDESC_TAIL_POINTER,DMA channel 2 transmit descriptor tail pointer register" hexmask.long 0x4 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer" group.long 0x1228++0x17 line.long 0x0 "DMA_CH2_RXDESC_TAIL_POINTER,DMA channel 2 receive descriptor tail pointer" hexmask.long 0x0 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer" line.long 0x4 "DMA_CH2_TXDESC_RING_LENGTH,DMA channel 2 transmit descriptor ring length register" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length" line.long 0x8 "DMA_CH2_RXDESC_RING_LENGTH,DMA channel 2 receive descriptor ring length register" hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length" line.long 0xC "DMA_CH2_INTERRUPT_ENABLE,DMA channel 2 interrupt enable register" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable" "0: : Transmit Interrupt,?" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable" "?,1: : Transmit Process Stopped" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable" "0,1" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable" "0,1" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable" "0,1" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "DMA_CH2_RX_INTERRUPT_WATCHDOG_TIMER,DMA channel 2 receive interrupt watchdog timer register" bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units" "0: 256,1: 512,2: 1024,3: 2048" newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count" line.long 0x14 "DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS,DMA channel 2 slot function control status register" hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number" newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value" newline bitfld.long 0x14 1. "ASC,Advance Slot Check" "0,1" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison" "0,1" rgroup.long 0x1244++0x3 line.long 0x0 "DMA_CH2_CURRENT_APP_TXDESC,DMA channel 2 current application transmit descriptor register" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer" rgroup.long 0x124C++0x3 line.long 0x0 "DMA_CH2_CURRENT_APP_RXDESC,DMA channel 2 current application transmit descriptor register" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer" rgroup.long 0x1254++0x3 line.long 0x0 "DMA_CH2_CURRENT_APP_TXBUFFER,DMA channel 2 current application transmit buffer register" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer" rgroup.long 0x125C++0x3 line.long 0x0 "DMA_CH2_CURRENT_APP_RXBUFFER,DMA channel 2 current application receive buffer register" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer" group.long 0x1260++0x3 line.long 0x0 "DMA_CH2_STATUS,DMA channel 2 status register" bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0: : Transmit Interrupt,?" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "?,1: : Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt" "0,1" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" newline bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable" "0,1" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" newline bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x1264++0xB line.long 0x0 "DMA_CH2_MISS_FRAME_CNT,DMA channel 2 miss frame counter register" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MFC,This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CHn_RX_CONTROL register. The counter gets cleared when this register is read." line.long 0x4 "DMA_CH2_RXP_ACCEPT_CNT,DMA Channel 2 RXP Accept Counter register" bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter" line.long 0x8 "DMA_CH2_RX_ERI_CNT,DMA Channel 2 RX Early Receive Interrupt Counter register" hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter" tree.end tree "ETHERNET_1" base ad:0x71A04000 group.long 0x0++0x17 line.long 0x0 "MAC_CONFIGURATION,MAC configuration register" bitfld.long 0x0 31. "ARPEN,ARP Offload Enable" "0,1" newline bitfld.long 0x0 28.--30. "SARC,Source Address Insertion or Replacement Control" "?,?,2: If Bit 30 is set to 0 the MAC inserts the..,3: If Bit 30 is set to 0 the MAC replaces the..,?,?,?,?" newline bitfld.long 0x0 27. "IPC,Checksum Offload" "0,1" newline bitfld.long 0x0 24.--26. "IPG,Inter-Packet Gap" "0: : 96 bit times IPG,1: : 88 bit times IPG,2: : 80 bit times IPG,3: : 72 bit times IPG,4: : 64 bit times IPG,5: : 56 bit times IPG,6: : 48 bit times IPG,7: : 40 bit times IPG" newline bitfld.long 0x0 23. "GPSLCE,Giant Packet Size Limit Control Enable" "0,1" newline bitfld.long 0x0 22. "S2KP,IEEE 802.3 as Support for 2K Packets" "0,1" newline bitfld.long 0x0 21. "CST,CRC stripping for Type packets" "0,1" newline bitfld.long 0x0 20. "ACS,Automatic Pad or CRC Stripping" "0,1" newline bitfld.long 0x0 19. "WD,Watchdog Disable" "0,1" newline bitfld.long 0x0 17. "JD,Jabber Disable" "0,1" newline bitfld.long 0x0 16. "JE,Jumbo Packet Enable" "0,1" newline bitfld.long 0x0 15. "PS,Port Select" "0: For 1000 Mbps operations,1: For 10 or 100Mbps operations" newline bitfld.long 0x0 14. "FES,Speed" "0: 10Mbps when PS bit is 1 and 1 Gbps when PS bit..,1: 100Mbps when PS bit is 1" newline bitfld.long 0x0 13. "DM,Duplex Mode" "0,1" newline bitfld.long 0x0 12. "LM,Loopback Mode" "0,1" newline bitfld.long 0x0 11. "ECRSFD,Enable Carrier Sense Before Transmission in Full-Duplex Mode" "0,1" newline bitfld.long 0x0 2.--3. "PRELEN,Preamble Length for Transmit packets" "0: 7 bytes of preamble,1: 5 bytes of preamble,2: 3 bytes of preamble,?" newline bitfld.long 0x0 1. "TE,Transmitter Enable" "0,1" newline bitfld.long 0x0 0. "RE,Receiver Enable" "0,1" line.long 0x4 "MAC_EXT_CONFIGURATION,MAC extended configuration register" hexmask.long.byte 0x4 25.--29. 1. "EIPG,Extended Inter-Packet Gap" newline bitfld.long 0x4 24. "EIPGEN,Extended Inter-Packet Gap Enable" "0,1" newline bitfld.long 0x4 20.--22. "HDSMS,Maximum Size for Splitting the Header Data" "0: 64 bytes,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1024 bytes,?,?,?" newline bitfld.long 0x4 19. "PDC,Packet Duplication Control" "0,1" newline bitfld.long 0x4 18. "USP,Unicast Slow Protocol Packet Detect" "0,1" newline bitfld.long 0x4 17. "SPEN,Slow Protocol Detection Enable" "0,1" newline bitfld.long 0x4 16. "DCRCC,Disable CRC Checking for Received Packets" "0,1" newline hexmask.long.word 0x4 0.--13. 1. "GPSL,Giant Packet Size Limit" line.long 0x8 "MAC_PACKET_FILTER,MAC packet filter register" bitfld.long 0x8 31. "RA,Receive All" "0,1" newline bitfld.long 0x8 21. "DNTU,Drop Non-TCP/UDP over IP Packets" "0,1" newline bitfld.long 0x8 20. "IPFE,Layer 3 and Layer 4 Filter Enable" "0,1" newline bitfld.long 0x8 16. "VTFE,VLAN Tag Filter Enable" "0,1" newline bitfld.long 0x8 10. "HPF,Hash or Perfect Filter" "0,1" newline bitfld.long 0x8 9. "SAF,Source Address Filter Enable" "0,1" newline bitfld.long 0x8 8. "SAIF,SA Inverse Filtering" "0,1" newline bitfld.long 0x8 6.--7. "PCF,Pass Control Packets" "0: The MAC filters all control packets from..,1: The MAC forwards all control packets except..,2: The MAC forwards all control packets to the..,3: The MAC forwards the control packets that pass.." newline bitfld.long 0x8 5. "DBF,Disable Broadcast Packets" "0,1" newline bitfld.long 0x8 4. "PM,Pass All Multicast" "0,1" newline bitfld.long 0x8 3. "DAIF,DA Inverse Filtering" "0,1" newline bitfld.long 0x8 2. "HMC,Hash Multicast" "0,1" newline bitfld.long 0x8 1. "HUC,Hash Unicast" "0,1" newline bitfld.long 0x8 0. "PR,Promiscuous Mode" "0,1" line.long 0xC "MAC_WATCHDOG_TIMEOUT,MAC Watchdog Timeout register" bitfld.long 0xC 8. "PWE,Programmable Watchdog Enable" "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "WTO,Watchdog Timeout" line.long 0x10 "MAC_HASH_TABLE_REG0,MAC Hash table register 0" hexmask.long 0x10 0.--31. 1. "HT31T0,This field contains the first 32 Bits [31) 0] of the MAC Hash table." line.long 0x14 "MAC_HASH_TABLE_REG1,MAC Hash Table register 1" hexmask.long 0x14 0.--31. 1. "HT63T32,This field contains the second 32 Bits [31:0] of the MAC Hash table." group.long 0x50++0x7 line.long 0x0 "MAC_VLAN_TAG_CTRL,MAC VLAN tag control register" bitfld.long 0x0 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status" "0,1" newline bitfld.long 0x0 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip" newline bitfld.long 0x0 27. "ERIVLT,Enable Inner VLAN Tag" "0,1" newline bitfld.long 0x0 26. "EDVLP,Enable Double VLAN Processing" "0,1" newline bitfld.long 0x0 25. "VTHM,VLAN Tag Hash Table Match Enable" "0,1" newline bitfld.long 0x0 24. "EVLRXS,Enable VLAN Tag in Rx status" "0,1" newline bitfld.long 0x0 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip" newline bitfld.long 0x0 18. "ESVL,Enable S-VLAN" "0,1" newline bitfld.long 0x0 17. "VTIM,VLAN Tag Inverse Match Enable" "0,1" newline hexmask.long.byte 0x0 2.--6. 1. "OFS,Offset" newline bitfld.long 0x0 1. "CT,Command Type" "0,1" newline bitfld.long 0x0 0. "OB,Operation Busy" "0,1" line.long 0x4 "MAC_VLAN_TAG_DATA,MAC VLAN tag data register" bitfld.long 0x4 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x4 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x4 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x4 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x4 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x4 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x4 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x4 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER0,MAC VLAN tag filter register 0" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER1,MAC VLAN tag filter register 1" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER2,MAC VLAN tag filter register 2" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER3,MAC VLAN tag filter register 3" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER4,MAC VLAN tag filter register 4" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER5,MAC VLAN tag filter register 5" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER6,MAC VLAN tag filter register 6" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER7,MAC VLAN tag filter register 7" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER8,MAC VLAN tag filter register 8" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER9,MAC VLAN tag filter register 9" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER10,MAC VLAN tag filter register 10" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER11,MAC VLAN tag filter register 11" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER12,MAC VLAN tag filter register 12" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER13,MAC VLAN tag filter register 13" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_TAG_FILTER14,MAC VLAN tag filter register 14" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" group.long 0x54++0x7 line.long 0x0 "MAC_VLAN_TAG_FILTER15,MAC VLAN tag filter register 15" bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison" "0,1" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID" line.long 0x4 "MAC_VLAN_HASH_TABLE,MAC VLAN hash table register" hexmask.long.word 0x4 0.--15. 1. "VLHT,VLAN Hash Table" group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_INCL,MAC VLAN tag inclusion register" bitfld.long 0x0 31. "BUSY,Busy" "0,1" newline bitfld.long 0x0 30. "RDWR,Read write control" "0,1" newline bitfld.long 0x0 24.--25. "ADDR,Address" "0,1,2,3" newline bitfld.long 0x0 21. "CBTI,Channel based tag insertion" "0,1" newline bitfld.long 0x0 20. "VLTI,VLAN Tag Input" "0,1" newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN" "0,1" newline bitfld.long 0x0 18. "VLP,VLAN Priority Control" "0,1" newline bitfld.long 0x0 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0,1,2,3" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_INCL0,The Tx Queue VLAN tag inclusion register contains the VLAN tag for insertion in the transmit packets from Tx Queue n. It also contains the VLAN tag insertion controls." bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_INCL1,The Tx Queue VLAN tag inclusion register contains the VLAN tag for insertion in the transmit packets from Tx Queue n. It also contains the VLAN tag insertion controls." bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" group.long 0x60++0x7 line.long 0x0 "MAC_VLAN_INCL2,The Tx Queue VLAN tag inclusion register contains the VLAN tag for insertion in the transmit packets from Tx Queue n. It also contains the VLAN tag insertion controls." bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" line.long 0x4 "MAC_INNER_VLAN_INCL,MAC Inner VLAN tag inclusion register" bitfld.long 0x4 20. "VLTI,VLAN Tag Input" "0,1" newline bitfld.long 0x4 19. "CSVL,C-VLAN or S-VLAN" "0,1" newline bitfld.long 0x4 18. "VLP,VLAN Priority Control" "0,1" newline bitfld.long 0x4 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion. The MAC removes the VLAN type..,2: VLAN tag insertion. The MAC inserts VLT in bytes..,3: VLAN tag replacement. The MAC replaces VLT in.." newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" group.long 0x70++0x3 line.long 0x0 "MAC_Q0_TX_FLOW_CTRL,MAC Q0 TX flow control register" hexmask.long.word 0x0 16.--31. 1. "PT,Pause Time" newline bitfld.long 0x0 7. "DZPQ,Disable Zero-Quanta Pause" "0,1" newline bitfld.long 0x0 4.--6. "PLT,Pause Low Threshold" "0: Pause Time minus 4 Slot Times (PT -4 slot times),1: Pause Time minus 28 Slot Times (PT -28 slot times),2: Pause Time minus 36 Slot Times (PT -36 slot times),3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?,?" newline bitfld.long 0x0 1. "TFE,Transmit Flow Control Enable" "0,1" newline bitfld.long 0x0 0. "FCB_BPA,Flow Control Busy or Backpressure Activate" "0,1" group.long 0x90++0x7 line.long 0x0 "MAC_RX_FLOW_CTRL,MAC receive flow control register" bitfld.long 0x0 1. "UP,Unicast Pause Packet Detect" "0,1" newline bitfld.long 0x0 0. "RFE,Receive Flow Control Enable" "0,1" line.long 0x4 "MAC_RXQ_CTRL4,MAC Receive queue control 4 register" bitfld.long 0x4 17.--18. "VFFQ,VLAN Tag Filter Fail Packets Queue" "0,1,2,3" newline bitfld.long 0x4 16. "VFFQE,VLAN Tag Filter Fail Packets Queuing Enable" "0,1" newline bitfld.long 0x4 9.--10. "MFFQ,Multicast Address Filter Fail Packets Queue" "0,1,2,3" newline bitfld.long 0x4 8. "MFFQE,Multicast Address Filter Fail Packets Queuing Enable" "0,1" newline bitfld.long 0x4 1.--2. "UFFQ,Unicast Address Filter Fail Packets Queue" "0,1,2,3" newline bitfld.long 0x4 0. "UFFQE,Unicast Address Filter Fail Packets Queuing Enable" "0,1" group.long 0xA0++0xB line.long 0x0 "MAC_RXQ_CTRL0,MAC Receive queue control 0 register" bitfld.long 0x0 4.--5. "RXQ2EN,Receive Queue 2 Enable" "0: Not enabled,1: Queue 1 enabled for AV,2: Queue 1 enabled for generic,?" newline bitfld.long 0x0 2.--3. "RXQ1EN,Receive Queue 1 Enable" "0: Not enabled,1: Queue 1 enabled for AV,2: Queue 1 enabled for generic,?" newline bitfld.long 0x0 0.--1. "RXQ0EN,Receive Queue 0 Enable" "0: Not enabled,1: Queue 0 enabled for AV,2: Queue 0 enabled for generic,?" line.long 0x4 "MAC_RXQ_CTRL1,MAC Receive queue control 1 register" bitfld.long 0x4 24.--26. "FPRQ,Frame Preemption Residue Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 22.--23. "TPQC,Tagged PTP over Ethernet Packets Queuing Control" "0: VLAN Tagged PTPoE packets are routed as generic..,1: VLAN Tagged PTPoE packets are routed to Rx Queue..,2: VLAN Tagged PTPoE packets are routed to only AV..,?" newline bitfld.long 0x4 21. "TACPQE,Tagged AV Control Packets Queuing Enable" "0,1" newline bitfld.long 0x4 20. "MCBCQEN,Multicast and Broadcast Queue Enable" "0,1" newline bitfld.long 0x4 16.--18. "MCBCQ,Multicast and Broadcast Queue" "0: Rx Queue 0,1: Rx Queue 1,2: Rx Queue 2,?,?,?,?,?" newline bitfld.long 0x4 12.--14. "UPQ,Untagged Packet Queue" "0: Rx Queue 0,1: Rx Queue 1,2: Rx Queue 2,?,?,?,?,?" newline bitfld.long 0x4 4.--6. "PTPQ,AV PTP Packets Queue" "0: Rx Queue 0,1: Rx Queue 1,2: Rx Queue 2,?,?,?,?,?" newline bitfld.long 0x4 0.--2. "AVCPQ,AV Untagged Control Packets Queue" "0: Rx Queue 0,1: Rx Queue 1,2: Rx Queue 2,?,?,?,?,?" line.long 0x8 "MAC_RXQ_CTRL2,MAC Receive queue control 2 register" hexmask.long.byte 0x8 16.--23. 1. "PSRQ2,Priorities Selected in the Receive Queue 2" newline hexmask.long.byte 0x8 8.--15. 1. "PSRQ1,Priorities Selected in the Receive Queue 1" newline hexmask.long.byte 0x8 0.--7. 1. "PSRQ0,Priorities Selected in the Receive Queue 0" rgroup.long 0xB0++0x3 line.long 0x0 "MAC_INTERRUPT_STATUS,MAC Interrupt status register" bitfld.long 0x0 20. "MFRIS,MMC FPE Receive Interrupt Status" "0,1" newline bitfld.long 0x0 19. "MFTIS,MMC FPE Transmit Interrupt Status" "0,1" newline bitfld.long 0x0 18. "MDIOIS,MDIO Interrupt Status" "0,1" newline bitfld.long 0x0 17. "FPEIS,Frame Preemption Interrupt Status" "0,1" newline bitfld.long 0x0 14. "RXSTSIS,Receive Status Interrupt" "0,1" newline bitfld.long 0x0 13. "TXSTSIS,Transmit Status Interrupt" "0,1" newline bitfld.long 0x0 12. "TSIS,Timestamp Interrupt Status" "0,1" newline bitfld.long 0x0 11. "MMCRXIPIS,MMC Receive Checksum Offload Interrupt Status" "0,1" newline bitfld.long 0x0 10. "MMCTXIS,MMC Transmit Interrupt Status" "0,1" newline bitfld.long 0x0 9. "MMCRXIS,MMC Receive Interrupt Status" "0,1" newline bitfld.long 0x0 8. "MMCIS,MMC Interrupt Status" "?,?" newline bitfld.long 0x0 5. "LPIIS,LPI Interrupt Status" "0,1" newline bitfld.long 0x0 4. "PMTIS,PMT Interrupt Status" "0,1" newline bitfld.long 0x0 3. "PHYIS,PHY Interrupt" "0,1" newline bitfld.long 0x0 2. "PCSANCIS,PCS Auto-Negotiation Complete" "0: PCS auto-negotiation has not completed,1: PCS auto-negotiation completed" newline bitfld.long 0x0 1. "PCSLCHGIS,PCS Link Status Changed" "0: PCS link status has not changed,1: PCS link status changed" newline bitfld.long 0x0 0. "RGSMIIIS,RGMII or SMII Interrupt Status" "0,1" group.long 0xB4++0x3 line.long 0x0 "MAC_INTERRUPT_ENABLE,MAC Interrupt enable register" bitfld.long 0x0 18. "MDIOIE,MDIO Interrupt Enable" "0,1" newline bitfld.long 0x0 17. "FPEIE,Frame Preemption Interrupt Enable" "0,1" newline bitfld.long 0x0 14. "RXSTSIE,Receive Status Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TXSTSIE,Transmit Status Interrupt Enable" "0,1" newline bitfld.long 0x0 12. "TSIE,Timestamp Interrupt Enable" "0,1" newline bitfld.long 0x0 5. "LPIIE,LPI Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "PMTIE,PMT Interrupt Enable" "0,1" newline bitfld.long 0x0 3. "PHYIE,PHY Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "PCSANCIE,PCS AN Completion Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "PCSLCHGIE,PCS Link Status Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "RGSMIIIE,RGMII or SMII Interrupt Enable" "0,1" rgroup.long 0xB8++0x3 line.long 0x0 "MAC_RX_TX_STATUS,MAC Receive transmit status register" bitfld.long 0x0 8. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x0 0. "TJT,Transmit Jabber Timeout" "0,1" group.long 0xC0++0x7 line.long 0x0 "MAC_PMT_CONTROL_STATUS,MAC PMT control and status register" bitfld.long 0x0 31. "RWKFILTRST,Remote Wake-Up Packet Filter Register Pointer Reset" "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,Remote Wake-up FIFO Pointer" newline bitfld.long 0x0 10. "RWKPFE,Remote Wake-up Packet Forwarding Enable" "0,1" newline bitfld.long 0x0 9. "GLBLUCAST,Global Unicast" "0,1" newline bitfld.long 0x0 6. "RWKPRCVD,Remote Wake-Up Packet Received" "0,1" newline bitfld.long 0x0 5. "MGKPRCVD,Magic Packet Received" "0,1" newline bitfld.long 0x0 2. "RWKPKTEN,Remote Wake-Up Packet Enable" "0,1" newline bitfld.long 0x0 1. "MGKPKTEN,Magic Packet Enable" "0,1" newline bitfld.long 0x0 0. "PWRDWN,Power Down" "0,1" line.long 0x4 "MAC_RWK_PACKET_FILTER,MAC RWK packet filter register" hexmask.long 0x4 0.--31. 1. "WKUPFRMFTR,RWK Packet Filter" group.long 0xC4++0x3 line.long 0x0 "RWK_FILTER0_BYTE_MASK,Corresponds to registers wkuppktfilter_reg0 described in Table1542." hexmask.long 0x0 0.--31. 1. "FILTER0_BYTE_MASK,Filter{i} 32-bit Mask" group.long 0xC4++0x3 line.long 0x0 "RWK_FILTER1_BYTE_MASK,Corresponds to registers wkuppktfilter_reg1 described in Table1542." hexmask.long 0x0 0.--31. 1. "FILTER1_BYTE_MASK,Filter{i} 32-bit Mask" group.long 0xC4++0x3 line.long 0x0 "RWK_FILTER2_BYTE_MASK,Corresponds to registers wkuppktfilter_reg2 described in Table1542." hexmask.long 0x0 0.--31. 1. "FILTER2_BYTE_MASK,Filter{i} 32-bit Mask" group.long 0xC4++0x3 line.long 0x0 "RWK_FILTER3_BYTE_MASK,Corresponds to registers wkuppktfilter_reg3 described in Table1542." hexmask.long 0x0 0.--31. 1. "FILTER3_BYTE_MASK,Filter{i} 32-bit Mask" group.long 0xC4++0x3 line.long 0x0 "RWK_FILTER0123_COMMAND,Corresponds to registers wkuppktfilter_reg4 described in Table1542." hexmask.long.byte 0x0 24.--27. 1. "FILTER3_COMMAND,Filter{l} Command" newline hexmask.long.byte 0x0 16.--19. 1. "FILTER2_COMMAND,Filter{k} Command" newline hexmask.long.byte 0x0 8.--11. 1. "FILTER1_COMMAND,Filter{j} Command" newline hexmask.long.byte 0x0 0.--3. 1. "FILTER0_COMMAND,Filter{i} Command" group.long 0xC4++0x3 line.long 0x0 "RWK_FILTER0123_OFFSET,Corresponds to registers wkuppktfilter_reg5 described in Table1542." hexmask.long.byte 0x0 24.--31. 1. "FILTER3_OFFSET,Filter{l} Offset" newline hexmask.long.byte 0x0 16.--23. 1. "FILTER2_OFFSET,Filter{k} Offset" newline hexmask.long.byte 0x0 8.--15. 1. "FILTER1_OFFSET,Filter{j} Offset" newline hexmask.long.byte 0x0 0.--7. 1. "FILTER0_OFFSET,Filter{i} Offset" group.long 0xC4++0x3 line.long 0x0 "RWK_FILTER01_CRC,Corresponds to registers wkuppktfilter_reg6 described in Table1542." hexmask.long.word 0x0 16.--31. 1. "FILTER1_CRC,Filter{j} CRC-16" newline hexmask.long.word 0x0 0.--15. 1. "FILTER0_CRC,Filter{i} CRC-16" group.long 0xC4++0x3 line.long 0x0 "RWK_FILTER23_CRC,Corresponds to registers wkuppktfilter_reg7 described in Table1542." hexmask.long.word 0x0 16.--31. 1. "FILTER3_CRC,Refer to the description of Section69.2.2.25." newline hexmask.long.word 0x0 0.--15. 1. "FILTER2_CRC,Refer to the description of Section69.2.2.25." group.long 0xD0++0x13 line.long 0x0 "MAC_LPI_CONTROL_STATUS,MAC LPI control and status register" bitfld.long 0x0 21. "LPITCSE,LPI Tx Clock Stop Enable" "0: LPI Tx Clock Stop is disabled,1: LPI Tx Clock Stop is enabled" newline bitfld.long 0x0 20. "LPIATE,LPI Timer Enable" "0: LPI Timer is disabled,1: LPI Timer is enabled" newline bitfld.long 0x0 19. "LPITXA,LPI Tx Automate" "0: LPI Tx Automate is disabled,1: LPI Tx Automate is enabled" newline bitfld.long 0x0 18. "PLSEN,PHY Link Status Enable" "0: PHY Link Status is disabled,1: PHY Link Status is enabled" newline bitfld.long 0x0 17. "PLS,PHY Link Status" "0: Link is down,1: Link is okay" newline bitfld.long 0x0 16. "LPIEN,LPI Enable" "0: LPI state is disabled,1: LPI state is enabled" newline bitfld.long 0x0 9. "RLPIST,Receive LPI State" "0: Receive LPI state not detected,1: Receive LPI state detected" newline bitfld.long 0x0 8. "TLPIST,Transmit LPI State" "0: Transmit LPI state not detected,1: Transmit LPI state detected" newline bitfld.long 0x0 3. "RLPIEX,Receive LPI Exit" "0: Receive LPI exit not detected,1: Receive LPI exit detected" newline bitfld.long 0x0 2. "RLPIEN,Receive LPI Entry" "0: Receive LPI entry not detected,1: Receive LPI entry detected" newline bitfld.long 0x0 1. "TLPIEX,Transmit LPI Exit" "0: Transmit LPI exit not detected,1: Transmit LPI exit detected" newline bitfld.long 0x0 0. "TLPIEN,Transmit LPI Entry" "0: Transmit LPI entry not detected,1: Transmit LPI entry detected" line.long 0x4 "MAC_LPI_TIMERS_CONTROL,MAC LPI timers control register" hexmask.long.word 0x4 16.--25. 1. "LST,LPI LS TIMER" newline hexmask.long.word 0x4 0.--15. 1. "TWT,LPI TW TIMER" line.long 0x8 "MAC_LPI_ENTRY_TIMER,MAC LPI entry timer register" hexmask.long.tbyte 0x8 3.--19. 1. "LPIET,LPI Entry Timer" line.long 0xC "MAC_1US_TIC_COUNTER,MAC 1US Tic counter register" hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,1US TIC Counter" line.long 0x10 "MAC_AN_CONTROL,MAC Auto-negotiation control register" bitfld.long 0x10 18. "SGMRAL,SGMII RAL Control" "0: SGMII RAL Control is disabled,1: SGMII RAL Control is enabled" newline bitfld.long 0x10 17. "LR,Lock to Reference" "0: Lock to Reference is disabled,1: Lock to Reference is enabled" newline bitfld.long 0x10 16. "ECD,Enable Comma Detect" "0: Comma detect is disabled,1: Comma detect is enabled" newline bitfld.long 0x10 14. "ELE,External Loopback Enable" "0: External Loopback is disabled,1: External Loopback is enabled" newline bitfld.long 0x10 12. "ANE,Auto-Negotiation Enable" "0: Auto-Negotiation is disabled,1: Auto-Negotiation is enabled" newline bitfld.long 0x10 9. "RAN,Restart Auto-Negotiation" "0: Do not Restart Auto-Negotiation,1: Restart Auto-Negotiation" rgroup.long 0xE4++0x3 line.long 0x0 "MAC_AN_STATUS,MAC Auto-negotiation status register" bitfld.long 0x0 8. "ES,Extended Status" "0: No extended status (SGMII without TBI),1: Extended status (TBI or RTBI)" newline bitfld.long 0x0 5. "ANC,Auto-Negotiation Complete" "0: Auto-Negotiation is not complete,1: Auto-Negotiation is complete" newline bitfld.long 0x0 3. "ANA,Auto-Negotiation Ability" "0: MAC does not possess Auto-Negotiation Ability,1: MAC possesses Auto-Negotiation Ability" newline bitfld.long 0x0 2. "LS,Link Status" "0: Link is down,1: Link is up" group.long 0xF8++0x3 line.long 0x0 "MAC_PHYIF_CONTROL_STATUS,MAC PHYIF Control Status register" bitfld.long 0x0 19. "LNKSTS,Link Status" "0,1" newline bitfld.long 0x0 17.--18. "LNKSPEED,Link Speed" "0: 2.5 MHz,1: 25 MHz,2: 125 MHz,?" newline bitfld.long 0x0 16. "LNKMOD,Link Mode" "0: Half-duplex mode,1: Full-duplex mode" newline bitfld.long 0x0 1. "LUD,Link Up or Down" "0: Link Down,1: Link Up" newline bitfld.long 0x0 0. "TC,Transmit Configuration in RGMII" "0,1" rgroup.long 0x110++0x7 line.long 0x0 "MAC_VERSION,MAC Version register" hexmask.long.byte 0x0 8.--15. 1. "USERVER,User IP Version Number" newline hexmask.long.byte 0x0 0.--7. 1. "VENDORVER,Vendor IP Version Number" line.long 0x4 "MAC_DEBUG,MAC Debug register" bitfld.long 0x4 17.--18. "TFCSTS,MAC Transmit Packet Controller Status" "0: Idle state,1: Waiting for one of the following:,2: Generating and transmitting a Pause control..,3: Transferring input packet for transmission" newline bitfld.long 0x4 16. "TPESTS,MAC MII Transmit Protocol Engine Status" "0,1" newline bitfld.long 0x4 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status" "0,1,2,3" newline bitfld.long 0x4 0. "RPESTS,MAC MII Receive Protocol Engine Status" "0,1" rgroup.long 0x11C++0xF line.long 0x0 "MAC_HW_FEATURE0,MAC Hardware feature 0 register" bitfld.long 0x0 28.--30. "ACTPHYSEL,Active PHY Selected" "0: MII,1: RGMII,2: SGMII,?,4: RMII,?,?,?" newline bitfld.long 0x0 27. "SAVLANINS,Source Address or VLAN Insertion Enable" "0,1" newline bitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source" "?,?,?,3: Both internal and external source of Timestamp" newline hexmask.long.byte 0x0 18.--22. 1. "ADDMACADRSEL,MAC Addresses 1-31 Selected" newline bitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload present" "0,1" newline bitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload present" "0,1" newline bitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet present" "0,1" newline bitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp present" "0,1" newline bitfld.long 0x0 9. "ARPOFFSEL,ARP Offload present" "0,1" newline bitfld.long 0x0 8. "MMCSEL,RMON Module Present" "0,1" newline bitfld.long 0x0 7. "MGKSEL,PMT Magic Packet present" "0,1" newline bitfld.long 0x0 6. "RWKSEL,PMT Remote Wake-up Packet Enable" "0,1" newline bitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface present" "0,1" newline bitfld.long 0x0 4. "VLHASH,VLAN Hash Filter selection" "0,1" newline bitfld.long 0x0 3. "PCSSEL,SGMII PCS registers present" "0,1" newline bitfld.long 0x0 2. "HDSEL,Half-duplex support selection" "0: Not selected,1: Selected" newline bitfld.long 0x0 1. "GMIISEL,This bit is set to 1 when 1000 Mbps is selected as the mode of operation." "0,1" newline bitfld.long 0x0 0. "MIISEL,MIISEL" "?,?" line.long 0x4 "MAC_HW_FEATURE1,MAC Hardware feature 1 register" hexmask.long.byte 0x4 27.--30. 1. "L3L4FNUM,Total number of L3 or L4 Filters" newline bitfld.long 0x4 24.--25. "HASHTBLSZ,Hash Table Size" "?,1: 64-bit hash table,?,?" newline bitfld.long 0x4 20. "AVSEL,AV Feature Enabled" "0,1" newline bitfld.long 0x4 19. "DBGMEMA,DMA Debug Registers Enabled" "0,1" newline bitfld.long 0x4 18. "TSOEN,TCP Segmentation Offload Enable" "0,1" newline bitfld.long 0x4 17. "SPHEN,Split Header Feature Enable" "0,1" newline bitfld.long 0x4 14.--15. "ADDR64,Address Width" "0: 32-bit address width,?,?,?" newline bitfld.long 0x4 13. "ADVTHWORD,IEEE 1588 High Word Register Enable" "0,1" newline bitfld.long 0x4 11. "OSTEN,One-Step Timestamping Enable" "0,1" newline hexmask.long.byte 0x4 6.--10. 1. "TXFIFOSIZE,MTL Transmit FIFO Size" newline bitfld.long 0x4 5. "SPRAM,Single Port RAM Enable" "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "RXFIFOSIZE,MTL Receive FIFO Size" line.long 0x8 "MAC_HW_FEATURE2,MAC Hardware feature 2 register" bitfld.long 0x8 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs" "?,?,2: 2 auxiliary inputs,?,?,?,?,?" newline bitfld.long 0x8 24.--26. "PPSOUTNUM,Number of PPS Outputs" "?,1: 1 PPS output,?,?,?,?,?,?" newline hexmask.long.byte 0x8 18.--21. 1. "TXCHCNT,Number of DMA Transmit Channels" newline hexmask.long.byte 0x8 12.--15. 1. "RXCHCNT,Number of DMA Receive Channels" newline hexmask.long.byte 0x8 6.--9. 1. "TXQCNT,Number of MTL Transmit Queues" newline hexmask.long.byte 0x8 0.--3. 1. "RXQCNT,Number of MTL Receive Queues" line.long 0xC "MAC_HW_FEATURE3,MAC Hardware feature 3 register" bitfld.long 0xC 28.--29. "ASP,Automotive Safety Package" "?,?,?,3: Time Based Scheduling Enable feature is selected." newline bitfld.long 0xC 27. "TBSSEL,Time Based Scheduling Enable" "0: Time Based Scheduling Enable feature is not..,1: Time Based Scheduling Enable feature is selected." newline bitfld.long 0xC 26. "FPESEL,Frame Preemption Enable" "0: Frame Preemption Enable feature is not selected.,1: Frame Preemption Enable feature is selected." newline bitfld.long 0xC 20.--21. "ESTWID,Width of the Time Interval field in the Gate Control List" "0: Width not configured,1: 16,2: 20,3: 24" newline bitfld.long 0xC 17.--19. "ESTDEP,Depth of the Gate Control List" "0: No Depth configured,1: 64,2: 128,3: 256,4: 512,5: 1024,?,?" newline bitfld.long 0xC 16. "ESTSEL,Enhancements to Scheduling Traffic Enable" "0: Enable Enhancements to Scheduling Traffic..,1: Enable Enhancements to Scheduling Traffic.." newline bitfld.long 0xC 13.--14. "FRPES,Flexible Receive Parser table Entries Size" "?,?,2: 256 Entries,?" newline bitfld.long 0xC 11.--12. "FRPBS,Flexible Receive Parser Buffer Size" "?,1: 128 Bytes,?,?" newline bitfld.long 0xC 10. "FRPSEL,Flexible Receive Parser Selected" "?,1: FRP supported" newline bitfld.long 0xC 9. "PDUPSEL,Broadcast/Multicast Packet Duplication" "0,1" newline bitfld.long 0xC 5. "DVLAN,Double VLAN feature" "0: Disable,1: Enable" newline bitfld.long 0xC 4. "CBTISEL,Queue/Channel based VLAN tag insertion on Tx Enable" "0,1" newline bitfld.long 0xC 0.--2. "NRVF,Number of Extended VLAN Tag Filters Enabled" "?,?,?,3: 16 Extended Rx VLAN Filters,?,?,?,?" group.long 0x140++0x3 line.long 0x0 "MAC_DPP_FSM_INTERRUPT_STATUS,MAC Data Path Parity FSM interrupt status register" bitfld.long 0x0 24. "FSMPES,FSM State Parity Error Status" "0: FSM State Parity Error Status not detected,1: FSM State Parity Error Status detected" newline bitfld.long 0x0 16. "MSTTES,Master Read/Write Timeout Error Status" "0: Master Read/Write Timeout Error Status not..,1: Master Read/Write Timeout Error Status detected" newline bitfld.long 0x0 14. "R125ES,Rx125 FSM Timeout Error Status" "0: Rx125 FSM Timeout Error Status not detected,1: Rx125 FSM Timeout Error Status detected" newline bitfld.long 0x0 13. "T125ES,Tx125 FSM Timeout Error Status" "0: Tx125 FSM Timeout Error Status not detected,1: Tx125 FSM Timeout Error Status detected" newline bitfld.long 0x0 12. "PTES,PTP FSM Timeout Error Status" "0: PTP FSM Timeout Error Status not detected,1: PTP FSM Timeout Error Status detected" newline bitfld.long 0x0 11. "ATES,APP FSM Timeout Error Status" "0: APP FSM Timeout Error Status not detected,1: APP FSM Timeout Error Status detected" newline bitfld.long 0x0 10. "CTES,CSR FSM Timeout Error Status" "0: CSR FSM Timeout Error Status not detected,1: CSR FSM Timeout Error Status detected" newline bitfld.long 0x0 9. "RTES,Rx FSM Timeout Error Status" "0: Rx FSM Timeout Error Status not detected,1: Rx FSM Timeout Error Status detected" newline bitfld.long 0x0 8. "TTES,Tx FSM Timeout Error Status" "0: Tx FSM Timeout Error Status not detected,1: Tx FSM Timeout Error Status detected" newline bitfld.long 0x0 5. "ARPES,Application Receive interface data path Parity Error Status" "0: Application Receive interface data path Parity..,1: Application Receive interface data path Parity.." newline bitfld.long 0x0 4. "MTSPES,MTL TX Status data path Parity checker Error Status" "0: MTL TX Status data path Parity checker Error..,1: MTL TX Status data path Parity checker Error.." newline bitfld.long 0x0 3. "MPES,MTL data path Parity checker Error Status" "0: MTL data path Parity checker Error Status not..,1: MTL data path Parity checker Error Status detected" newline bitfld.long 0x0 2. "RDPES,Read Descriptor Parity checker Error Status" "0: Read Descriptor Parity checker Error Status not..,1: Read Descriptor Parity checker Error Status.." newline bitfld.long 0x0 1. "TPES,TSO data path Parity checker Error Status" "0: TSO data path Parity checker Error Status not..,1: TSO data path Parity checker Error Status detected" newline bitfld.long 0x0 0. "ATPES,Application Transmit Interface Parity checker Error Status" "0: Application Transmit Interface Parity checker..,1: Application Transmit Interface Parity checker.." group.long 0x148++0x7 line.long 0x0 "MAC_FSM_CONTROL,MAC FSM control register" bitfld.long 0x0 30. "R125LGRNML,Rx125 Large/Normal Mode Select" "0: Normal mode tic generation is used for Rx125..,1: Large mode tic generation is used for Rx125 domain" newline bitfld.long 0x0 29. "T125LGRNML,Tx125 Large/Normal Mode Select" "0: Normal mode tic generation is used for Tx125..,1: Large mode tic generation is used for Tx125 domain" newline bitfld.long 0x0 28. "PLGRNML,PTP Large/Normal Mode Select" "0: Normal mode tic generation is used for PTP domain,1: Large mode tic generation is used for PTP domain" newline bitfld.long 0x0 27. "ALGRNML,APP Large/Normal Mode Select" "0: Normal mode tic generation is used for APP domain,1: Large mode tic generation is used for APP domain" newline bitfld.long 0x0 26. "CLGRNML,CSR Large/Normal Mode Select" "0: Normal mode tic generation is used for CSR domain,1: Large mode tic generation is used for CSR domain" newline bitfld.long 0x0 25. "RLGRNML,Rx Large/Normal Mode Select" "0: Normal mode tic generation is used for Rx domain,1: Large mode tic generation is used for Rx domain" newline bitfld.long 0x0 24. "TLGRNML,Tx Large/Normal Mode Select" "0: Normal mode tic generation is used for Tx domain,1: Large mode tic generation is used for Tx domain" newline bitfld.long 0x0 22. "R125PEIN,Rx125 FSM Parity Error Injection" "0: Rx125 FSM Parity Error Injection is disabled,1: Rx125 FSM Parity Error Injection is enabled" newline bitfld.long 0x0 21. "T125PEIN,Tx125 FSM Parity Error Injection" "0: Tx125 FSM Parity Error Injection is disabled,1: Tx125 FSM Parity Error Injection is enabled" newline bitfld.long 0x0 20. "PPEIN,PTP FSM Parity Error Injection" "0: PTP FSM Parity Error Injection is disabled,1: PTP FSM Parity Error Injection is enabled" newline bitfld.long 0x0 19. "APEIN,APP FSM Parity Error Injection" "0: APP FSM Parity Error Injection is disabled,1: APP FSM Parity Error Injection is enabled" newline bitfld.long 0x0 18. "CPEIN,CSR FSM Parity Error Injection" "0: CSR FSM Parity Error Injection is disabled,1: CSR FSM Parity Error Injection is enabled" newline bitfld.long 0x0 17. "RPEIN,Rx FSM Parity Error Injection" "0: Rx FSM Parity Error Injection is disabled,1: Rx FSM Parity Error Injection is enabled" newline bitfld.long 0x0 16. "TPEIN,Tx FSM Parity Error Injection" "0: Tx FSM Parity Error Injection is disabled,1: Tx FSM Parity Error Injection is enabled" newline bitfld.long 0x0 14. "R125TEIN,Rx125 FSM Timeout Error Injection" "0: Rx125 FSM Timeout Error Injection is disabled,1: Rx125 FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 13. "T125TEIN,Tx125 FSM Timeout Error Injection" "0: Tx125 FSM Timeout Error Injection is disabled,1: Tx125 FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 12. "PTEIN,PTP FSM Timeout Error Injection" "0: PTP FSM Timeout Error Injection is disabled,1: PTP FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 11. "ATEIN,APP FSM Timeout Error Injection" "0: APP FSM Timeout Error Injection is disabled,1: APP FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 10. "CTEIN,CSR FSM Timeout Error Injection" "0: CSR FSM Timeout Error Injection is disabled,1: CSR FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 9. "RTEIN,Rx FSM Timeout Error Injection" "0: Rx FSM Timeout Error Injection is disabled,1: Rx FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 8. "TTEIN,Tx FSM Timeout Error Injection" "0: Tx FSM Timeout Error Injection is disabled,1: Tx FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 1. "PRTYEN,FSM Parity Enable" "0: FSM Parity feature is disabled,1: FSM Parity feature is enabled" newline bitfld.long 0x0 0. "TMOUTEN,FSM Timeout Enable" "0: FSM timeout feature is disabled,1: FSM timeout feature is enabled" line.long 0x4 "MAC_FSM_ACT_TIMER,MAC FSM ACT register" hexmask.long.byte 0x4 20.--23. 1. "LTMRMD,Large Mode Timeout value" newline hexmask.long.byte 0x4 16.--19. 1. "NTMRMD,Normal Mode Timeout Value" newline hexmask.long.word 0x4 0.--9. 1. "TMR,1us Timer Tick" group.long 0x200++0x13 line.long 0x0 "MAC_MDIO_ADDRESS,MAC MDIO address register" bitfld.long 0x0 27. "PSE,Preamble Suppression Enable" "0,1" newline bitfld.long 0x0 26. "BTB,Back to Back transactions" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "PA,Physical Layer Address" newline hexmask.long.byte 0x0 16.--20. 1. "RDA,Register/Device Address" newline bitfld.long 0x0 12.--14. "NTC,Number of Training Clocks" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "CR,CSR Clock Range" newline bitfld.long 0x0 4. "SKAP,Skip Address Packet" "0,1" newline bitfld.long 0x0 2.--3. "GOC,PHY SMA interface Operation Command" "?,1: Write,2: Post Read Increment Address for Clause 45 PHY,3: Read" newline bitfld.long 0x0 1. "C45E,Clause 45 PHY Enable" "0,1" newline bitfld.long 0x0 0. "GB,PHY SMA interface Busy" "0,1" line.long 0x4 "MAC_MDIO_DATA,MAC MDIO data register" hexmask.long.word 0x4 16.--31. 1. "RA,Register Address" newline hexmask.long.word 0x4 0.--15. 1. "GD,PHY management Data" line.long 0x8 "MAC_GPIO_CONTROL,MAC GPIO control register" hexmask.long.word 0x8 16.--31. 1. "GPIT,GPI Type" newline hexmask.long.byte 0x8 0.--3. 1. "GPIE,GPI Interrupt Enable" line.long 0xC "MAC_GPIO_STATUS,MAC GPIO status register" hexmask.long.word 0xC 16.--31. 1. "GPO,General Purpose Output" newline hexmask.long.word 0xC 0.--15. 1. "GPIS,General Purpose Input Status" line.long 0x10 "MAC_ARP_ADDRESS,MAC ARP address register" hexmask.long 0x10 0.--31. 1. "ARPPA,ARP Protocol Address" group.long 0x230++0xB line.long 0x0 "MAC_CSR_SW_CTRL,MAC CSR SW control register" bitfld.long 0x0 0. "RCWE,Register Clear on Write 1 Enable" "0,1" line.long 0x4 "MAC_FPE_CTRL_STS,MAC FPE control STS register" bitfld.long 0x4 19. "TRSP,Transmitted Respond Frame" "0,1" newline bitfld.long 0x4 18. "TVER,Transmitted Verify Frame" "0,1" newline bitfld.long 0x4 17. "RRSP,Received Respond Frame" "0,1" newline bitfld.long 0x4 16. "RVER,Received Verify Frame" "0,1" newline bitfld.long 0x4 3. "S1_SET_0,Synopsys Reserved Must be set to '0'." "0,1" newline bitfld.long 0x4 2. "SRSP,Send Respond mPacket" "0,1" newline bitfld.long 0x4 1. "SVER,Send Verify mPacket" "0,1" newline bitfld.long 0x4 0. "EFPE,Enable Tx Frame Preemption" "0,1" line.long 0x8 "MAC_EXT_CFG1,MAC_Ext_Cfg1 register" bitfld.long 0x8 8.--9. "SPLM,Split Mode" "0: Split at L3/L4 header,1: Split at L2 header with an offset. Always Split..,2: Combination mode: split similar to SPLM=00 for..,?" newline hexmask.long.byte 0x8 0.--6. 1. "SPLOFST,Split Offset" rgroup.long 0x240++0x3 line.long 0x0 "MAC_PRESN_TIME_NS,MAC Presentation Time in Nanoseconds register" hexmask.long 0x0 0.--31. 1. "MPTN,MAC 1722 Presentation Time in ns" group.long 0x244++0x3 line.long 0x0 "MAC_PRESN_TIME_UPDT,MAC Presentation Time Update register" hexmask.long 0x0 0.--31. 1. "MPTU,MAC 1722 Presentation Time Update" group.long 0x300++0xFF line.long 0x0 "MAC_ADDRESS0_HIGH,MAC address 0 high register" bitfld.long 0x0 31. "AE,Address Enable" "0,1" newline bitfld.long 0x0 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "ADDRHI,MAC Address0[47) 32]" line.long 0x4 "MAC_ADDRESS0_LOW,MAC address 0 low register" hexmask.long 0x4 0.--31. 1. "ADDRLO,MAC address 0 [31) 0]" line.long 0x8 "MAC_ADDRESS1_HIGH,MAC address 1 High register" bitfld.long 0x8 31. "AE,Address Enable" "0,1" newline bitfld.long 0x8 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x8 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x8 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xC "MAC_ADDRESS1_LOW,MAC address 1 low register" hexmask.long 0xC 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x10 "MAC_ADDRESS2_HIGH,MAC address 2 High register" bitfld.long 0x10 31. "AE,Address Enable" "0,1" newline bitfld.long 0x10 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x10 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x10 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x14 "MAC_ADDRESS2_LOW,MAC address 2 low register" hexmask.long 0x14 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x18 "MAC_ADDRESS3_HIGH,MAC address 3 High register" bitfld.long 0x18 31. "AE,Address Enable" "0,1" newline bitfld.long 0x18 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x18 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x18 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x18 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x1C "MAC_ADDRESS3_LOW,MAC address 3 low register" hexmask.long 0x1C 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x20 "MAC_ADDRESS4_HIGH,MAC address 4 High register" bitfld.long 0x20 31. "AE,Address Enable" "0,1" newline bitfld.long 0x20 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x20 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x20 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x20 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x24 "MAC_ADDRESS4_LOW,MAC address 4 low register" hexmask.long 0x24 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x28 "MAC_ADDRESS5_HIGH,MAC address 5 High register" bitfld.long 0x28 31. "AE,Address Enable" "0,1" newline bitfld.long 0x28 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x28 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x28 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x28 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x2C "MAC_ADDRESS5_LOW,MAC address 5 low register" hexmask.long 0x2C 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x30 "MAC_ADDRESS6_HIGH,MAC address 6 High register" bitfld.long 0x30 31. "AE,Address Enable" "0,1" newline bitfld.long 0x30 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x30 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x30 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x30 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x34 "MAC_ADDRESS6_LOW,MAC address 6 low register" hexmask.long 0x34 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x38 "MAC_ADDRESS7_HIGH,MAC address 7 High register" bitfld.long 0x38 31. "AE,Address Enable" "0,1" newline bitfld.long 0x38 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x38 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x38 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x38 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x3C "MAC_ADDRESS7_LOW,MAC address 7 low register" hexmask.long 0x3C 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x40 "MAC_ADDRESS8_HIGH,MAC address 8 High register" bitfld.long 0x40 31. "AE,Address Enable" "0,1" newline bitfld.long 0x40 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x40 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x40 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x40 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x44 "MAC_ADDRESS8_LOW,MAC address 8 low register" hexmask.long 0x44 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x48 "MAC_ADDRESS9_HIGH,MAC address 9 High register" bitfld.long 0x48 31. "AE,Address Enable" "0,1" newline bitfld.long 0x48 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x48 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x48 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x48 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x4C "MAC_ADDRESS9_LOW,MAC address 9 low register" hexmask.long 0x4C 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x50 "MAC_ADDRESS10_HIGH,MAC address 10 High register" bitfld.long 0x50 31. "AE,Address Enable" "0,1" newline bitfld.long 0x50 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x50 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x50 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x50 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x54 "MAC_ADDRESS10_LOW,MAC address 10 low register" hexmask.long 0x54 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x58 "MAC_ADDRESS11_HIGH,MAC address 11 High register" bitfld.long 0x58 31. "AE,Address Enable" "0,1" newline bitfld.long 0x58 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x58 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x58 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x58 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x5C "MAC_ADDRESS11_LOW,MAC address 11 low register" hexmask.long 0x5C 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x60 "MAC_ADDRESS12_HIGH,MAC address 12 High register" bitfld.long 0x60 31. "AE,Address Enable" "0,1" newline bitfld.long 0x60 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x60 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x60 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x60 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x64 "MAC_ADDRESS12_LOW,MAC address 12 low register" hexmask.long 0x64 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x68 "MAC_ADDRESS13_HIGH,MAC address 13 High register" bitfld.long 0x68 31. "AE,Address Enable" "0,1" newline bitfld.long 0x68 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x68 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x68 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x68 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x6C "MAC_ADDRESS13_LOW,MAC address 13 low register" hexmask.long 0x6C 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x70 "MAC_ADDRESS14_HIGH,MAC address 14 High register" bitfld.long 0x70 31. "AE,Address Enable" "0,1" newline bitfld.long 0x70 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x70 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x70 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x70 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x74 "MAC_ADDRESS14_LOW,MAC address 14 low register" hexmask.long 0x74 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x78 "MAC_ADDRESS15_HIGH,MAC address 15 High register" bitfld.long 0x78 31. "AE,Address Enable" "0,1" newline bitfld.long 0x78 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x78 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x78 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x78 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x7C "MAC_ADDRESS15_LOW,MAC address 15 low register" hexmask.long 0x7C 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x80 "MAC_ADDRESS16_HIGH,MAC address 16 High register" bitfld.long 0x80 31. "AE,Address Enable" "0,1" newline bitfld.long 0x80 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x80 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x80 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x80 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x84 "MAC_ADDRESS16_LOW,MAC address 16 low register" hexmask.long 0x84 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x88 "MAC_ADDRESS17_HIGH,MAC address 17 High register" bitfld.long 0x88 31. "AE,Address Enable" "0,1" newline bitfld.long 0x88 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x88 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x88 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x88 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x8C "MAC_ADDRESS17_LOW,MAC address 17 low register" hexmask.long 0x8C 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x90 "MAC_ADDRESS18_HIGH,MAC address 18 High register" bitfld.long 0x90 31. "AE,Address Enable" "0,1" newline bitfld.long 0x90 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x90 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x90 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x90 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x94 "MAC_ADDRESS18_LOW,MAC address 18 low register" hexmask.long 0x94 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0x98 "MAC_ADDRESS19_HIGH,MAC address 19 High register" bitfld.long 0x98 31. "AE,Address Enable" "0,1" newline bitfld.long 0x98 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x98 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x98 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x98 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0x9C "MAC_ADDRESS19_LOW,MAC address 19 low register" hexmask.long 0x9C 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xA0 "MAC_ADDRESS20_HIGH,MAC address 20 High register" bitfld.long 0xA0 31. "AE,Address Enable" "0,1" newline bitfld.long 0xA0 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xA0 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xA0 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xA0 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xA4 "MAC_ADDRESS20_LOW,MAC address 20 low register" hexmask.long 0xA4 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xA8 "MAC_ADDRESS21_HIGH,MAC address 21 High register" bitfld.long 0xA8 31. "AE,Address Enable" "0,1" newline bitfld.long 0xA8 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xA8 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xA8 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xA8 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xAC "MAC_ADDRESS21_LOW,MAC address 21 low register" hexmask.long 0xAC 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xB0 "MAC_ADDRESS22_HIGH,MAC address 22 High register" bitfld.long 0xB0 31. "AE,Address Enable" "0,1" newline bitfld.long 0xB0 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xB0 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xB0 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xB0 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xB4 "MAC_ADDRESS22_LOW,MAC address 22 low register" hexmask.long 0xB4 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xB8 "MAC_ADDRESS23_HIGH,MAC address 23 High register" bitfld.long 0xB8 31. "AE,Address Enable" "0,1" newline bitfld.long 0xB8 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xB8 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xB8 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xB8 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xBC "MAC_ADDRESS23_LOW,MAC address 23 low register" hexmask.long 0xBC 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xC0 "MAC_ADDRESS24_HIGH,MAC address 24 High register" bitfld.long 0xC0 31. "AE,Address Enable" "0,1" newline bitfld.long 0xC0 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xC0 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xC0 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xC0 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xC4 "MAC_ADDRESS24_LOW,MAC address 24 low register" hexmask.long 0xC4 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xC8 "MAC_ADDRESS25_HIGH,MAC address 25 High register" bitfld.long 0xC8 31. "AE,Address Enable" "0,1" newline bitfld.long 0xC8 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xC8 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xC8 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xC8 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xCC "MAC_ADDRESS25_LOW,MAC address 25 low register" hexmask.long 0xCC 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xD0 "MAC_ADDRESS26_HIGH,MAC address 26 High register" bitfld.long 0xD0 31. "AE,Address Enable" "0,1" newline bitfld.long 0xD0 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xD0 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xD0 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xD0 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xD4 "MAC_ADDRESS26_LOW,MAC address 26 low register" hexmask.long 0xD4 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xD8 "MAC_ADDRESS27_HIGH,MAC address 27 High register" bitfld.long 0xD8 31. "AE,Address Enable" "0,1" newline bitfld.long 0xD8 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xD8 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xD8 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xD8 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xDC "MAC_ADDRESS27_LOW,MAC address 27 low register" hexmask.long 0xDC 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xE0 "MAC_ADDRESS28_HIGH,MAC address 28 High register" bitfld.long 0xE0 31. "AE,Address Enable" "0,1" newline bitfld.long 0xE0 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xE0 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xE0 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xE0 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xE4 "MAC_ADDRESS28_LOW,MAC address 28 low register" hexmask.long 0xE4 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xE8 "MAC_ADDRESS29_HIGH,MAC address 29 High register" bitfld.long 0xE8 31. "AE,Address Enable" "0,1" newline bitfld.long 0xE8 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xE8 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xE8 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xE8 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xEC "MAC_ADDRESS29_LOW,MAC address 29 low register" hexmask.long 0xEC 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xF0 "MAC_ADDRESS30_HIGH,MAC address 30 High register" bitfld.long 0xF0 31. "AE,Address Enable" "0,1" newline bitfld.long 0xF0 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xF0 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xF0 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xF0 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xF4 "MAC_ADDRESS30_LOW,MAC address 30 low register" hexmask.long 0xF4 0.--31. 1. "ADDRLO,MAC Address n [31:0]" line.long 0xF8 "MAC_ADDRESS31_HIGH,MAC address 31 High register" bitfld.long 0xF8 31. "AE,Address Enable" "0,1" newline bitfld.long 0xF8 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0xF8 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0xF8 16.--18. "DCS,DMA Channel Select" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xF8 0.--15. 1. "ADDRHI,MAC Address n [47) 32]" line.long 0xFC "MAC_ADDRESS31_LOW,MAC address 31 low register" hexmask.long 0xFC 0.--31. 1. "ADDRLO,MAC Address n [31:0]" group.long 0x700++0x3 line.long 0x0 "MMC_CONTROL,MMC control register" bitfld.long 0x0 8. "UCDBC,Update MMC Counters for Dropped Broadcast Packets" "0,1" newline bitfld.long 0x0 5. "CNTPRSTLVL,Full-Half Preset" "0,1" newline bitfld.long 0x0 4. "CNTPRST,Counters Preset" "0,1" newline bitfld.long 0x0 3. "CNTFREEZ,MMC Counter Freeze" "0,1" newline bitfld.long 0x0 2. "RSTONRD,Reset on Read" "0,1" newline bitfld.long 0x0 1. "CNTSTOPRO,Counter Stop Rollover" "0,1" newline bitfld.long 0x0 0. "CNTRST,Counters Reset" "0,1" rgroup.long 0x704++0x7 line.long 0x0 "MMC_RX_INTERRUPT,MMC receive interrupt register" bitfld.long 0x0 27. "RXLPITRCIS,MMC Receive LPI Transition Counter Interrupt Status" "0,1" newline bitfld.long 0x0 26. "RXLPIUSCIS,MMC Receive LPI Microsecond Counter Interrupt Status" "0,1" newline bitfld.long 0x0 25. "RXCTRLPIS,MMC Receive Control Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 24. "RXRCVERRPIS,MMC Receive Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 23. "RXWDOGPIS,MMC Receive Watchdog Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 22. "RXVLANGBPIS,MMC Receive VLAN Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 21. "RXFOVPIS,MMC Receive FIFO Overflow Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 20. "RXPAUSPIS,MMC Receive Pause Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 19. "RXORANGEPIS,MMC Receive Out Of Range Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 18. "RXLENERPIS,MMC Receive Length Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 17. "RXUCGPIS,MMC Receive Unicast Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 16. "RX1024TMAXOCTGBPIS,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 15. "RX512T1023OCTGBPIS,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 14. "RX256T511OCTGBPIS,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 13. "RX128T255OCTGBPIS,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 12. "RX65T127OCTGBPIS,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 11. "RX64OCTGBPIS,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 10. "RXOSIZEGPIS,MMC Receive Oversize Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 9. "RXUSIZEGPIS,MMC Receive Undersize Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 8. "RXJABERPIS,MMC Receive Jabber Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 7. "RXRUNTPIS,MMC Receive Runt Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 6. "RXALGNERPIS,MMC Receive Alignment Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIS,MMC Receive CRC Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 4. "RXMCGPIS,MMC Receive Multicast Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 3. "RXBCGPIS,MMC Receive Broadcast Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 2. "RXGOCTIS,MMC Receive Good Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 1. "RXGBOCTIS,MMC Receive Good Bad Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 0. "RXGBPKTIS,MMC Receive Good Bad Packet Counter Interrupt Status" "0,1" line.long 0x4 "MMC_TX_INTERRUPT,MMC Tx interrupt register" bitfld.long 0x4 27. "TXLPITRCIS,MMC Transmit LPI Transition Counter Interrupt Status" "0,1" newline bitfld.long 0x4 26. "TXLPIUSCIS,MMC Transmit LPI Microsecond Counter Interrupt Status" "0,1" newline bitfld.long 0x4 25. "TXOSIZEGPIS,MMC Transmit Oversize Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 24. "TXVLANGPIS,MMC Transmit VLAN Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 23. "TXPAUSPIS,MMC Transmit Pause Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 21. "TXGPKTIS,MMC Transmit Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 20. "TXGOCTIS,MMC Transmit Good Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 13. "TXUFLOWERPIS,MMC Transmit Underflow Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 12. "TXBCGBPIS,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 11. "TXMCGBPIS,MMC Transmit Multicast Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 10. "TXUCGBPIS,MMC Transmit Unicast Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 9. "TX1024TMAXOCTGBPIS,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 8. "TX512T1023OCTGBPIS,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 7. "TX256T511OCTGBPIS,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 6. "TX128T255OCTGBPIS,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 5. "TX65T127OCTGBPIS,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 4. "TX64OCTGBPIS,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 3. "TXMCGPIS,MMC Transmit Multicast Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 2. "TXBCGPIS,MMC Transmit Broadcast Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 1. "TXGBPKTIS,MMC Transmit Good Bad Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 0. "TXGBOCTIS,MMC Transmit Good Bad Octet Counter Interrupt Status" "0,1" group.long 0x70C++0x7 line.long 0x0 "MMC_RX_INTERRUPT_MASK,MMC Rx interrupt mask register" bitfld.long 0x0 27. "RXLPITRCIM,MMC Receive LPI Transition Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 26. "RXLPIUSCIM,MMC Receive LPI Microsecond Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 25. "RXCTRLPIM,MMC Receive Control Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 24. "RXRCVERRPIM,MMC Receive Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 23. "RXWDOGPIM,MMC Receive Watchdog Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 22. "RXVLANGBPIM,MMC Receive VLAN Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 21. "RXFOVPIM,MMC Receive FIFO Overflow Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 20. "RXPAUSPIM,MMC Receive Pause Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 19. "RXORANGEPIM,MMC Receive Out Of Range Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 18. "RXLENERPIM,MMC Receive Length Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 17. "RXUCGPIM,MMC Receive Unicast Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 16. "RX1024TMAXOCTGBPIM,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 15. "RX512T1023OCTGBPIM,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 14. "RX256T511OCTGBPIM,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 13. "RX128T255OCTGBPIM,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 12. "RX65T127OCTGBPIM,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 11. "RX64OCTGBPIM,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 10. "RXOSIZEGPIM,MMC Receive Oversize Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 9. "RXUSIZEGPIM,MMC Receive Undersize Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 8. "RXJABERPIM,MMC Receive Jabber Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 7. "RXRUNTPIM,MMC Receive Runt Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 6. "RXALGNERPIM,MMC Receive Alignment Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIM,MMC Receive CRC Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 4. "RXMCGPIM,MMC Receive Multicast Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 3. "RXBCGPIM,MMC Receive Broadcast Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 2. "RXGOCTIM,MMC Receive Good Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 1. "RXGBOCTIM,MMC Receive Good Bad Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 0. "RXGBPKTIM,MMC Receive Good Bad Packet Counter Interrupt Mask" "0,1" line.long 0x4 "MMC_TX_INTERRUPT_MASK,MMC Tx interrupt mask register" bitfld.long 0x4 27. "TXLPITRCIM,MMC Transmit LPI Transition Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 26. "TXLPIUSCIM,MMC Transmit LPI Microsecond Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 25. "TXOSIZEGPIM,MMC Transmit Oversize Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 24. "TXVLANGPIM,MMC Transmit VLAN Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 23. "TXPAUSPIM,MMC Transmit Pause Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 21. "TXGPKTIM,MMC Transmit Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 20. "TXGOCTIM,MMC Transmit Good Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 13. "TXUFLOWERPIM,MMC Transmit Underflow Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 12. "TXBCGBPIM,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 11. "TXMCGBPIM,MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 10. "TXUCGBPIM,MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 9. "TX1024TMAXOCTGBPIM,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 8. "TX512T1023OCTGBPIM,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 7. "TX256T511OCTGBPIM,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 6. "TX128T255OCTGBPIM,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 5. "TX65T127OCTGBPIM,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 4. "TX64OCTGBPIM,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 3. "TXMCGPIM,MMC Transmit Multicast Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 2. "TXBCGPIM,MMC Transmit Broadcast Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 1. "TXGBPKTIM,MMC Transmit Good Bad Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 0. "TXGBOCTIM,MMC Transmit Good Bad Octet Counter Interrupt Mask" "0,1" rgroup.long 0x714++0x37 line.long 0x0 "TX_OCTET_COUNT_GOOD_BAD,Transmit octet count good bad register" hexmask.long 0x0 0.--31. 1. "TXOCTGB,This field indicates the number of bytes transmitted exclusive of preamble and retried bytes in good and bad packets." line.long 0x4 "TX_PACKET_COUNT_GOOD_BAD,Transmit packet count good bad register" hexmask.long 0x4 0.--31. 1. "TXPKTGB,This field indicates the number of good and bad packets transmitted exclusive of retried packets." line.long 0x8 "TX_BROADCAST_PACKETS_GOOD,Transmit broadcast packets good register" hexmask.long 0x8 0.--31. 1. "TXBCASTG,This field indicates the number of good broadcast packets transmitted." line.long 0xC "TX_MULTICAST_PACKETS_GOOD,Transmit multicast packets good register" hexmask.long 0xC 0.--31. 1. "TXMCASTG,This field indicates the number of good multicast packets transmitted." line.long 0x10 "TX_64OCTETS_PACKETS_GOOD_BAD,Transmit 64 octets packets good bad register" hexmask.long 0x10 0.--31. 1. "TX64OCTGB,This field indicates the number of good and bad packets transmitted with length 64 bytes exclusive of preamble and retried packets." line.long 0x14 "TX_65TO127OCTETS_PACKETS_GOOD_BAD,Transmit 65 to 127 octets packets good bad register" hexmask.long 0x14 0.--31. 1. "TX65_127OCTGB,This field indicates the number of good and bad packets transmitted with length between 65 and 127 (inclusive) bytes exclusive of preamble and retried packets." line.long 0x18 "TX_128TO255OCTETS_PACKETS_GOOD_BAD,Transmit 128 to 255 octets packets good bad register" hexmask.long 0x18 0.--31. 1. "TX128_255OCTGB,This field indicates the number of good and bad packets transmitted with length between 128 and 255 (inclusive) bytes exclusive of preamble and retried packets." line.long 0x1C "TX_256TO511OCTETS_PACKETS_GOOD_BAD,Transmit 256 to 511 octets packets good bad register" hexmask.long 0x1C 0.--31. 1. "TX256_511OCTGB,Tx 256To511Octets Packets Good Bad" line.long 0x20 "TX_512TO1023OCTETS_PACKETS_GOOD_BAD,Transmit 512 to 1023 octets packets good bad register" hexmask.long 0x20 0.--31. 1. "TX512_1023OCTGB,Tx 512To1023Octets Packets Good Bad" line.long 0x24 "TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD,Transmit 1024 to Max octets packets good bad register" hexmask.long 0x24 0.--31. 1. "TX1024_MAXOCTGB,Tx 1024ToMaxOctets Packets Good Bad" line.long 0x28 "TX_UNICAST_PACKETS_GOOD_BAD,Transmit unicast packets good bad register" hexmask.long 0x28 0.--31. 1. "TXUCASTGB,Tx Unicast Packets Good Bad" line.long 0x2C "TX_MULTICAST_PACKETS_GOOD_BAD,Transmit multicast packets good bad register" hexmask.long 0x2C 0.--31. 1. "TXMCASTGB,Tx Multicast Packets Good Bad" line.long 0x30 "TX_BROADCAST_PACKETS_GOOD_BAD,Transmit broadcast packets good bad register" hexmask.long 0x30 0.--31. 1. "TXBCASTGB,Tx Broadcast Packets Good Bad" line.long 0x34 "TX_UNDERFLOW_ERROR_PACKETS,Transmit underflow error packets register" hexmask.long 0x34 0.--31. 1. "TXUNDRFLW,Tx Underflow Error Packets" rgroup.long 0x764++0x7 line.long 0x0 "TX_OCTET_COUNT_GOOD,Transmit octet count good register" hexmask.long 0x0 0.--31. 1. "TXOCTG,Tx Octet Count Good" line.long 0x4 "TX_PACKET_COUNT_GOOD,Transmit packet count good register" hexmask.long 0x4 0.--31. 1. "TXPKTG,Tx Packet Count Good" rgroup.long 0x770++0xB line.long 0x0 "TX_PAUSE_PACKETS,Transmit pause packets register" hexmask.long 0x0 0.--31. 1. "TXPAUSE,Tx Pause Packets" line.long 0x4 "TX_VLAN_PACKETS_GOOD,Transmit VLAN packets good register" hexmask.long 0x4 0.--31. 1. "TXVLANG,Tx VLAN Packets Good" line.long 0x8 "TX_OSIZE_PACKETS_GOOD,Transmit O size packets good register" hexmask.long 0x8 0.--31. 1. "TXOSIZG,Tx OSize Packets Good" rgroup.long 0x780++0x67 line.long 0x0 "RX_PACKETS_COUNT_GOOD_BAD,Receive packets count good bad register" hexmask.long 0x0 0.--31. 1. "RXPKTGB,Rx Packets Count Good Bad" line.long 0x4 "RX_OCTET_COUNT_GOOD_BAD,Receive octet count good bad register" hexmask.long 0x4 0.--31. 1. "RXOCTGB,Rx Octet Count Good Bad" line.long 0x8 "RX_OCTET_COUNT_GOOD,Receive octet count good register" hexmask.long 0x8 0.--31. 1. "RXOCTG,Rx Octet Count Good" line.long 0xC "RX_BROADCAST_PACKETS_GOOD,Receive broadcast packets good register" hexmask.long 0xC 0.--31. 1. "RXBCASTG,Rx Broadcast Packets Good" line.long 0x10 "RX_MULTICAST_PACKETS_GOOD,Receive multicast packets good register" hexmask.long 0x10 0.--31. 1. "RXMCASTG,Rx Multicast Packets Good" line.long 0x14 "RX_CRC_ERROR_PACKETS,Receive CRC error packets register" hexmask.long 0x14 0.--31. 1. "RXCRCERR,Rx CRC Error Packets" line.long 0x18 "RX_ALIGNMENT_ERROR_PACKETS,Receive alignment error packets register" hexmask.long 0x18 0.--31. 1. "RXALGNERR,Rx Alignment Error Packets" line.long 0x1C "RX_RUNT_ERROR_PACKETS,Receive runt error packets register" hexmask.long 0x1C 0.--31. 1. "RXRUNTERR,This field indicates the number of packets received with runt (length less than 64 bytes and CRC error) error." line.long 0x20 "RX_JABBER_ERROR_PACKETS,Receive Jabber error packets register" hexmask.long 0x20 0.--31. 1. "RXJABERR,This field indicates the number of giant packets received with length (including CRC) greater than 1518 bytes (1522 bytes for VLAN tagged) and with CRC error. If Jumbo Packet mode is enabled packets of length greater than 9018 bytes (9022 bytes.." line.long 0x24 "RX_UNDERSIZE_PACKETS_GOOD,Receive undersize packets good register" hexmask.long 0x24 0.--31. 1. "RXUNDERSZG,Rx Undersize Packets Good" line.long 0x28 "RX_OVERSIZE_PACKETS_GOOD,Receive oversize packets good register" hexmask.long 0x28 0.--31. 1. "RXOVERSZG,This field indicates the number of packets received without errors with length greater than the maxsize (1518 bytes or 1522 bytes for VLAN tagged packets; 2000 bytes if enabled in the S2KP bit of the MAC_CONFIGURATION register)." line.long 0x2C "RX_64OCTETS_PACKETS_GOOD_BAD,Receive 64 octets packets good bad register" hexmask.long 0x2C 0.--31. 1. "RX64OCTGB,This field indicates the number of good and bad packets received with length 64 bytes exclusive of the preamble." line.long 0x30 "RX_65TO127OCTETS_PACKETS_GOOD_BAD,Receive 65 to 127 octets packets good bad register" hexmask.long 0x30 0.--31. 1. "RX65_127OCTGB,This field indicates the number of good and bad packets received with length between 65 and 127 (inclusive) bytes exclusive of the preamble." line.long 0x34 "RX_128TO255OCTETS_PACKETS_GOOD_BAD,Receive 128 to 255 octets packets good bad register" hexmask.long 0x34 0.--31. 1. "RX128_255OCTGB,This field indicates the number of good and bad packets received with length between 128 and 255 (inclusive) bytes exclusive of the preamble." line.long 0x38 "RX_256TO511OCTETS_PACKETS_GOOD_BAD,Receive 256 to 511 octets packets good bad register" hexmask.long 0x38 0.--31. 1. "RX256_511OCTGB,This field indicates the number of good and bad packets received with length between 256 and 511 (inclusive) bytes exclusive of the preamble." line.long 0x3C "RX_512TO1023OCTETS_PACKETS_GOOD_BAD,Receive 512 to 1023 octets packets good bad register" hexmask.long 0x3C 0.--31. 1. "RX512_1023OCTGB,This field indicates the number of good and bad packets received with length between 512 and 1023 (inclusive) bytes exclusive of the preamble." line.long 0x40 "RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD,Receive 1024 to Max octets packets good bad register" hexmask.long 0x40 0.--31. 1. "RX1024_MAXOCTGB,This field indicates the number of good and bad packets received with length between 1024 and maxsize (inclusive) bytes exclusive of the preamble." line.long 0x44 "RX_UNICAST_PACKETS_GOOD,Receive unicast packets good register" hexmask.long 0x44 0.--31. 1. "RXUCASTG,This field indicates the number of good unicast packets received." line.long 0x48 "RX_LENGTH_ERROR_PACKETS,Receive length error packets" hexmask.long 0x48 0.--31. 1. "RXLENERR,This field indicates the number of packets received with length error (Length Type field not equal to packet size) for all packets with valid length field." line.long 0x4C "RX_OUT_OF_RANGE_TYPE_PACKETS,Receive out of range type packets" hexmask.long 0x4C 0.--31. 1. "RXOUTOFRNG,This field indicates the number of packets received with length field not equal to the valid packet size (greater than 1500 but less than 1536)." line.long 0x50 "RX_PAUSE_PACKETS,Receive pause packets register" hexmask.long 0x50 0.--31. 1. "RXPAUSEPKT,This field indicates the number of good and valid Pause packets received." line.long 0x54 "RX_FIFO_OVERFLOW_PACKETS,Receive FIFO overflow packets register" hexmask.long 0x54 0.--31. 1. "RXFIFOOVFL,This field indicates the number of missed received packets because of FIFO overflow." line.long 0x58 "RX_VLAN_PACKETS_GOOD_BAD,Receive VLAN packets good bad register" hexmask.long 0x58 0.--31. 1. "RXVLANPKTGB,This field indicates the number of good and bad VLAN packets received." line.long 0x5C "RX_WATCHDOG_ERROR_PACKETS,Receive watchdog error packets register" hexmask.long 0x5C 0.--31. 1. "RXWDGERR,This field indicates the number of packets received with error because of watchdog timeout error (packets with a data load larger than 2048 bytes (when JE and WD bits are reset in MAC_CONFIGURATION register) 10240 bytes (when JE bit is set and.." line.long 0x60 "RX_RECEIVE_ERROR_PACKETS,Receive error packets register" hexmask.long 0x60 0.--31. 1. "RXRCVERR,This field indicates the number of packets received with Receive error or Packet Extension error on the MII interface." line.long 0x64 "RX_CONTROL_PACKETS_GOOD,Receive control packets good register" hexmask.long 0x64 0.--31. 1. "RXCTRLG,This field indicates the number of good control packets received." rgroup.long 0x7EC++0xF line.long 0x0 "TX_LPI_USEC_CNTR,Transmit LPI USEC counter" hexmask.long 0x0 0.--31. 1. "TXLPIUSC,This field indicates the number of microseconds Tx LPI is asserted. For every Tx LPI Entry and Exit the Timer value can have an error of +/- 1 microsecond." line.long 0x4 "TX_LPI_TRAN_CNTR,Transmit LPI transaction counter register" hexmask.long 0x4 0.--31. 1. "TXLPITRC,This field indicates the number of times Tx LPI Entry has occurred. Even if Tx LPI Entry occurs in Automate Mode (because of LPITXA bit set in the LPI Control and Status register) the counter increments." line.long 0x8 "RX_LPI_USEC_CNTR,Receive LPI USEC counter" hexmask.long 0x8 0.--31. 1. "RXLPIUSC,This field indicates the number of microseconds Rx LPI is asserted. For every Rx LPI Entry and Exit the Timer value can have an error of +/- 1 microsecond." line.long 0xC "RX_LPI_TRAN_CNTR,Receive LPI transaction counter register" hexmask.long 0xC 0.--31. 1. "RXLPITRC,This field indicates the number of times Rx LPI Entry has occurred." group.long 0x800++0x3 line.long 0x0 "MMC_IPC_RX_INTERRUPT_MASK,MMC IPC receive interrupt mask register" bitfld.long 0x0 29. "RXICMPEROIM,MMC Receive ICMP Error Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 28. "RXICMPGOIM,MMC Receive ICMP Good Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 27. "RXTCPEROIM,MMC Receive TCP Error Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 26. "RXTCPGOIM,MMC Receive TCP Good Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 25. "RXUDPEROIM,MMC Receive UDP Good Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 24. "RXUDPGOIM,MMC Receive IPV6 No Payload Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 23. "RXIPV6NOPAYOIM,MMC Receive IPV6 Header Error Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 22. "RXIPV6HEROIM,MMC Receive IPV6 Good Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 21. "RXIPV6GOIM,MMC Receive IPV6 Good Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 20. "RXIPV4UDSBLOIM,MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 19. "RXIPV4FRAGOIM,MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 18. "RXIPV4NOPAYOIM,MMC Receive IPV4 No Payload Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 17. "RXIPV4HEROIM,MMC Receive IPV4 Header Error Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 16. "RXIPV4GOIM,MMC Receive IPV4 Good Octet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 13. "RXICMPERPIM,MMC Receive ICMP Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 12. "RXICMPGPIM,MMC Receive ICMP Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 11. "RXTCPERPIM,MMC Receive TCP Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 10. "RXTCPGPIM,MMC Receive TCP Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 9. "RXUDPERPIM,MMC Receive UDP Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 8. "RXUDPGPIM,MMC Receive UDP Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 7. "RXIPV6NOPAYPIM,MMC Receive IPV6 No Payload Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 6. "RXIPV6HERPIM,MMC Receive IPV6 Header Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 5. "RXIPV6GPIM,MMC Receive IPV6 Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 4. "RXIPV4UDSBLPIM,MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 3. "RXIPV4FRAGPIM,MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 2. "RXIPV4NOPAYPIM,MMC Receive IPV4 No Payload Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 1. "RXIPV4HERPIM,MMC Receive IPV4 Header Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 0. "RXIPV4GPIM,MMC Receive IPV4 Good Packet Counter Interrupt Mask" "0,1" rgroup.long 0x808++0x3 line.long 0x0 "MMC_IPC_RX_INTERRUPT,MMC IPC receive interrupt register" bitfld.long 0x0 29. "RXICMPEROIS,MMC Receive ICMP Error Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 28. "RXICMPGOIS,MMC Receive ICMP Good Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 27. "RXTCPEROIS,MMC Receive TCP Error Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 26. "RXTCPGOIS,MMC Receive TCP Good Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 25. "RXUDPEROIS,MMC Receive UDP Error Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 24. "RXUDPGOIS,MMC Receive UDP Good Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 23. "RXIPV6NOPAYOIS,MMC Receive IPV6 No Payload Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 22. "RXIPV6HEROIS,MMC Receive IPV6 Header Error Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 21. "RXIPV6GOIS,MMC Receive IPV6 Good Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 20. "RXIPV4UDSBLOIS,MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 19. "RXIPV4FRAGOIS,MMC Receive IPV4 Fragmented Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 18. "RXIPV4NOPAYOIS,MMC Receive IPV4 No Payload Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 17. "RXIPV4HEROIS,MMC Receive IPV4 Header Error Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 16. "RXIPV4GOIS,MMC Receive IPV4 Good Octet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 13. "RXICMPERPIS,MMC Receive ICMP Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 12. "RXICMPGPIS,MMC Receive ICMP Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 11. "RXTCPERPIS,MMC Receive TCP Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 10. "RXTCPGPIS,MMC Receive TCP Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 9. "RXUDPERPIS,MMC Receive UDP Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 8. "RXUDPGPIS,MC Receive UDP Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 7. "RXIPV6NOPAYPIS,MMC Receive IPV6 No Payload Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 6. "RXIPV6HERPIS,MMC Receive IPV6 Header Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 5. "RXIPV6GPIS,MMC Receive IPV6 Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 4. "RXIPV4UDSBLPIS,MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 3. "RXIPV4FRAGPIS,MMC Receive IPV4 Fragmented Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 2. "RXIPV4NOPAYPIS,MMC Receive IPV4 No Payload Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 1. "RXIPV4HERPIS,MMC Receive IPV4 Header Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 0. "RXIPV4GPIS,MMC Receive IPV4 Good Packet Counter Interrupt Status" "0,1" rgroup.long 0x810++0x37 line.long 0x0 "RXIPV4_GOOD_PACKETS,Receive IPv4 good packets register" hexmask.long 0x0 0.--31. 1. "RXIPV4GDPKT,This field indicates the number of good IPv4 datagrams received with the TCP UDP or ICMP payload." line.long 0x4 "RXIPV4_HEADER_ERROR_PACKETS,Receive IPv4 header error packets" hexmask.long 0x4 0.--31. 1. "RXIPV4HDRERRPKT,This field indicates the number of IPv4 datagrams received with header (checksum length or version mismatch) errors." line.long 0x8 "RXIPV4_NO_PAYLOAD_PACKETS,Receive IPv4 no payload packets register" hexmask.long 0x8 0.--31. 1. "RXIPV4NOPAYPKT,This field indicates the number of IPv4 datagram packets received that did not have a TCP UDP or ICMP payload." line.long 0xC "RXIPV4_FRAGMENTED_PACKETS,Receive IPv4 fragmented packets register" hexmask.long 0xC 0.--31. 1. "RXIPV4FRAGPKT,This field indicates the number of good IPv4 datagrams received with fragmentation." line.long 0x10 "RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS,Receive IPv4 UDP checksum disabled packets register" hexmask.long 0x10 0.--31. 1. "RXIPV4UDSBLPKT,This field indicates the number of good IPv4 datagrams received that had a UDP payload with checksum disabled." line.long 0x14 "RXIPV6_GOOD_PACKETS,Receive IPv6 good packets register" hexmask.long 0x14 0.--31. 1. "RXIPV6GDPKT,This field indicates the number of good IPv6 datagrams received with the TCP UDP or ICMP payload." line.long 0x18 "RXIPV6_HEADER_ERROR_PACKETS,Receive IPv6 header error packets" hexmask.long 0x18 0.--31. 1. "RXIPV6HDRERRPKT,This field indicates the number of IPv6 datagrams received with header (length or version mismatch) errors." line.long 0x1C "RXIPV6_NO_PAYLOAD_PACKETS,Receive IPv6 payload packets register" hexmask.long 0x1C 0.--31. 1. "RXIPV6NOPAYPKT,This field indicates the number of IPv6 datagram packets received that did not have a TCP UDP or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers." line.long 0x20 "RXUDP_GOOD_PACKETS,Receive UDP good packets register" hexmask.long 0x20 0.--31. 1. "RXUDPGDPKT,This field indicates the number of good IP datagrams received with a good UDP payload. This counter is not updated when the RxIPv4_UDP_Checksum_Disabled_Packets counter is incremented." line.long 0x24 "RXUDP_ERROR_PACKETS,Receive UDP error packets register" hexmask.long 0x24 0.--31. 1. "RXUDPERRPKT,This field indicates the number of good IP datagrams received whose UDP payload has a checksum error." line.long 0x28 "RXTCP_GOOD_PACKETS,Receive TCP good packets register" hexmask.long 0x28 0.--31. 1. "RXTCPGDPKT,This field indicates the number of good IP datagrams received with a good TCP payload." line.long 0x2C "RXTCP_ERROR_PACKETS,Receive TCP error packets register" hexmask.long 0x2C 0.--31. 1. "RXTCPERRPKT,This field indicates the number of good IP datagrams received whose TCP payload has a checksum error." line.long 0x30 "RXICMP_GOOD_PACKETS,Receive ICMP good packets register" hexmask.long 0x30 0.--31. 1. "RXICMPGDPKT,This field indicates the number of good IP datagrams received with a good ICMP payload." line.long 0x34 "RXICMP_ERROR_PACKETS,Receive ICMP error packets register" hexmask.long 0x34 0.--31. 1. "RXICMPERRPKT,This field indicates the number of good IP datagrams received whose ICMP payload has a checksum error." rgroup.long 0x850++0x37 line.long 0x0 "RXIPV4_GOOD_OCTETS,Receive IPv4 Good Octets register" hexmask.long 0x0 0.--31. 1. "RXIPV4GDOCT,This field indicates the number of bytes received in good IPv4 datagrams encapsulating TCP UDP or ICMP data. Ethernet header FCS pad or IP pad bytes are not included in this counter." line.long 0x4 "RXIPV4_HEADER_ERROR_OCTETS,Receive IPv4 header error octets register" hexmask.long 0x4 0.--31. 1. "RXIPV4HDRERROCT,This field indicates the number of bytes received in IPv4 datagrams with header errors (checksum length version mismatch). The value in the Length field of IPv4 header is used to update this counter. Ethernet header FCS pad or IP pad.." line.long 0x8 "RXIPV4_NO_PAYLOAD_OCTETS,Receive IPv4 no payload octets register" hexmask.long 0x8 0.--31. 1. "RXIPV4NOPAYOCT,This field indicates the number of bytes received in IPv4 datagrams that did not have a TCP UDP or ICMP payload. The value in the Length field of IPv4 header is used to update this counter. Ethernet header FCS pad or IP pad bytes are.." line.long 0xC "RXIPV4_FRAGMENTED_OCTETS,Receive IPv4 fragmented octets register" hexmask.long 0xC 0.--31. 1. "RXIPV4FRAGOCT,This field indicates the number of bytes received in fragmented IPv4 datagrams. The value in the Length field of IPv4 header is used to update this counter. Ethernet header FCS pad or IP pad bytes are not included in this counter." line.long 0x10 "RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS,Receive IPv4 UDP checksum disable octets register" hexmask.long 0x10 0.--31. 1. "RXIPV4UDSBLOCT,This field indicates the number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. Ethernet header FCS pad or IP pad bytes are not included in this counter." line.long 0x14 "RXIPV6_GOOD_OCTETS,Receive IPv6 good octets register" hexmask.long 0x14 0.--31. 1. "RXIPV6GDOCT,This field indicates the number of bytes received in good IPv6 datagrams encapsulating TCP UDP or ICMP data. Ethernet header FCS pad or IP pad bytes are not included in this counter." line.long 0x18 "RXIPV6_HEADER_ERROR_OCTETS,Receive header error octets register" hexmask.long 0x18 0.--31. 1. "RXIPV6HDRERROCT,This field indicates the number of bytes received in IPv6 datagrams with header errors (length version mismatch). The value in the Length field of IPv6 header is used to update this counter. Ethernet header FCS pad or IP pad bytes are.." line.long 0x1C "RXIPV6_NO_PAYLOAD_OCTETS,Receive IPv6 no payload octets register" hexmask.long 0x1C 0.--31. 1. "RXIPV6NOPAYOCT,This field indicates the number of bytes received in IPv6 datagrams that did not have a TCP UDP or ICMP payload. The value in the Length field of IPv6 header is used to update this counter. Ethernet header FCS pad or IP pad bytes are.." line.long 0x20 "RXUDP_GOOD_OCTETS,Receive UDP good octets register" hexmask.long 0x20 0.--31. 1. "RXUDPGDOCT,This field indicates the number of bytes received in a good UDP segment. This counter does not count IP header bytes." line.long 0x24 "RXUDP_ERROR_OCTETS,Receive UDP error octets register" hexmask.long 0x24 0.--31. 1. "RXUDPERROCT,This field indicates the number of bytes received in a UDP segment that had checksum errors. This counter does not count IP header bytes." line.long 0x28 "RXTCP_GOOD_OCTETS,Receive TCP good octets register" hexmask.long 0x28 0.--31. 1. "RXTCPGDOCT,This field indicates the number of bytes received in a good TCP segment. This counter does not count IP header bytes." line.long 0x2C "RXTCP_ERROR_OCTETS,Receive TCP error octets register" hexmask.long 0x2C 0.--31. 1. "RXTCPERROCT,This field indicates the number of bytes received in a TCP segment that had checksum errors. This counter does not count IP header bytes." line.long 0x30 "RXICMP_GOOD_OCTETS,Receive ICMP good octets register" hexmask.long 0x30 0.--31. 1. "RXICMPGDOCT,This field indicates the number of bytes received in a good ICMP segment. This counter does not count IP header bytes." line.long 0x34 "RXICMP_ERROR_OCTETS,Receive ICMP error octets register" hexmask.long 0x34 0.--31. 1. "RXICMPERROCT,This field indicates the number of bytes received in a ICMP segment that had checksum errors. This counter does not count IP header bytes." rgroup.long 0x8A0++0x3 line.long 0x0 "MMC_FPE_TX_INTERRUPT,MMC FPE Tx interrupt register" bitfld.long 0x0 1. "HRCIS,MMC Tx Hold Request Counter Interrupt Status" "0,1" newline bitfld.long 0x0 0. "FCIS,MMC Tx FPE Fragment Counter Interrupt status" "0,1" group.long 0x8A4++0x3 line.long 0x0 "MMC_FPE_TX_INTERRUPT_MASK,MMC FPE Tx interrupt mask register" bitfld.long 0x0 1. "HRCIM,MMC Transmit Hold Request Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 0. "FCIM,MMC Transmit Fragment Counter Interrupt Mask" "0,1" rgroup.long 0x8A8++0x7 line.long 0x0 "MMC_TX_FPE_FRAGMENT_CNTR,MMC Tx FPE fragment counter register" hexmask.long 0x0 0.--31. 1. "TXFFC,Tx FPE Fragment counter" line.long 0x4 "MMC_TX_HOLD_REQ_CNTR,MMC Tx hold request counter register" hexmask.long 0x4 0.--31. 1. "TXHRC,Tx Hold Request Counter" rgroup.long 0x8C0++0x3 line.long 0x0 "MMC_FPE_RX_INTERRUPT,MMC FPE Rx interrupt register" bitfld.long 0x0 3. "FCIS,MMC Rx FPE Fragment Counter Interrupt Status" "0,1" newline bitfld.long 0x0 2. "PAOCIS,MMC Rx Packet Assembly OK Counter Interrupt Status" "0,1" newline bitfld.long 0x0 1. "PSECIS,MMC Rx Packet SMD Error Counter Interrupt Status" "0,1" newline bitfld.long 0x0 0. "PAECIS,MMC Rx Packet Assembly Error Counter Interrupt Status" "0,1" group.long 0x8C4++0x3 line.long 0x0 "MMC_FPE_RX_INTERRUPT_MASK,MMC FPE Rx interrupt mask register" bitfld.long 0x0 3. "FCIM,MMC Rx FPE Fragment Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 2. "PAOCIM,MMC Rx Packet Assembly OK Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 1. "PSECIM,MMC Rx Packet SMD Error Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 0. "PAECIM,MMC Rx Packet Assembly Error Counter Interrupt Mask" "0,1" rgroup.long 0x8C8++0xF line.long 0x0 "MMC_RX_PACKET_ASSEMBLY_ERR_CNTR,MMC Rx packet assembly error counter register" hexmask.long 0x0 0.--31. 1. "PAEC,Rx Packet Assembly Error Counter" line.long 0x4 "MMC_RX_PACKET_SMD_ERR_CNTR,MMC Rx packet SMD error counter register" hexmask.long 0x4 0.--31. 1. "PSEC,Rx Packet SMD Error Counter" line.long 0x8 "MMC_RX_PACKET_ASSEMBLY_OK_CNTR,MMC Rx packet assembly OK counter register" hexmask.long 0x8 0.--31. 1. "PAOC,Rx Packet Assembly OK Counter" line.long 0xC "MMC_RX_FPE_FRAGMENT_CNTR,MMC Rx FPE fragment counter register" hexmask.long 0xC 0.--31. 1. "FFC,Rx FPE Fragment Counter" group.long 0x900++0x7 line.long 0x0 "MAC_L3_L4_CONTROL0,Layer 3 and Layer 4 control 0 register" bitfld.long 0x0 28. "DMCHEN0,DMA Channel Select Enable" "0,1" newline bitfld.long 0x0 24.--25. "DMCHN0,DMA Channel Number" "0: Packet is passed by this filter to DMA CH 0,1: Packet is passed by this filter to DMA CH 1,?,?" newline bitfld.long 0x0 21. "L4DPIM0,Layer 4 Destination Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 20. "L4DPM0,Layer 4 Destination Port Match Enable" "0,1" newline bitfld.long 0x0 19. "L4SPIM0,Layer 4 Source Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 18. "L4SPM0,Layer 4 Source Port Match Enable" "0,1" newline bitfld.long 0x0 16. "L4PEN0,Layer 4 Protocol Enable" "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,Layer 3 IP DA Higher Bits Match" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,Layer 3 IP SA Higher Bits Match" newline bitfld.long 0x0 5. "L3DAIM0,Layer 3 IP DA Inverse Match Enable" "0,1" newline bitfld.long 0x0 4. "L3DAM0,Layer 3 IP DA Match Enable" "0,1" newline bitfld.long 0x0 3. "L3SAIM0,Layer 3 IP SA Inverse Match Enable" "0,1" newline bitfld.long 0x0 2. "L3SAM0,Layer 3 IP SA Match Enable" "0,1" newline bitfld.long 0x0 0. "L3PEN0,Layer 3 Protocol Enable" "0,1" line.long 0x4 "MAC_LAYER4_ADDRESS0,Layer 4 address 0 register" hexmask.long.word 0x4 16.--31. 1. "L4DP0,Layer 4 Destination Port Number Field" newline hexmask.long.word 0x4 0.--15. 1. "L4SP0,Layer 4 Source Port Number Field" group.long 0x910++0xF line.long 0x0 "MAC_LAYER3_ADDR0_REG0,Layer 3 address 0 register 0 register" hexmask.long 0x0 0.--31. 1. "L3A00,Layer 3 Address 0 Field" line.long 0x4 "MAC_LAYER3_ADDR1_REG0,Layer3 address1 register 0 register" hexmask.long 0x4 0.--31. 1. "L3A10,Layer 3 Address 1 Field" line.long 0x8 "MAC_LAYER3_ADDR2_REG0,Layer3 address2 register 0 register" hexmask.long 0x8 0.--31. 1. "L3A20,Layer 3 Address 2 Field" line.long 0xC "MAC_LAYER3_ADDR3_REG0,Layer3 address3 register 0 register" hexmask.long 0xC 0.--31. 1. "L3A30,Layer 3 Address 3 Field" group.long 0xB00++0x7 line.long 0x0 "MAC_TIMESTAMP_CONTROL,Timestamp control register" bitfld.long 0x0 28. "AV8021ASMEN,AV 802.1AS Mode Enable" "0,1" newline bitfld.long 0x0 24. "TXTSSTSM,Transmit Timestamp Status Mode" "0,1" newline bitfld.long 0x0 20. "ESTI,External System Time Input" "0,1" newline bitfld.long 0x0 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering" "0,1" newline bitfld.long 0x0 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots" "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master" "0,1" newline bitfld.long 0x0 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages" "0,1" newline bitfld.long 0x0 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP" "0,1" newline bitfld.long 0x0 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over IPv6-UDP" "0,1" newline bitfld.long 0x0 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets" "0,1" newline bitfld.long 0x0 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format" "0,1" newline bitfld.long 0x0 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control" "0,1" newline bitfld.long 0x0 8. "TSENALL,Enable Timestamp for All Packets" "0,1" newline bitfld.long 0x0 6. "PTGE,Presentation Time Generation Enable" "0,1" newline bitfld.long 0x0 5. "TSADDREG,Update Addend Register" "0,1" newline bitfld.long 0x0 3. "TSUPDT,Update Timestamp" "0,1" newline bitfld.long 0x0 2. "TSINIT,Initialize Timestamp" "0,1" newline bitfld.long 0x0 1. "TSCFUPDT,Fine or Coarse Timestamp Update" "0,1" newline bitfld.long 0x0 0. "TSENA,Enable Timestamp" "0,1" line.long 0x4 "MAC_SUB_SECOND_INCREMENT,Sub second increment register" hexmask.long.byte 0x4 16.--23. 1. "SSINC,Sub-second Increment Value" rgroup.long 0xB08++0x7 line.long 0x0 "MAC_SYSTEM_TIME_SECONDS,System time seconds register" hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Second" line.long 0x4 "MAC_SYSTEM_TIME_NANOSECONDS,System time nanoseconds register" hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Seconds" group.long 0xB10++0xF line.long 0x0 "MAC_SYSTEM_TIME_SECONDS_UPDATE,System time seconds update register" hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Seconds" line.long 0x4 "MAC_SYSTEM_TIME_NANOSECONDS_UPDATE,System time nanoseconds update register" bitfld.long 0x4 31. "ADDSUB,Add or Subtract Time" "0,1" newline hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Seconds" line.long 0x8 "MAC_TIMESTAMP_ADDEND,Timestamp addend register" hexmask.long 0x8 0.--31. 1. "TSAR,Timestamp Addend Register" line.long 0xC "MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS,System time higher word seconds register" hexmask.long.word 0xC 0.--15. 1. "TSHWR,Timestamp Higher Word Register" rgroup.long 0xB20++0x3 line.long 0x0 "MAC_TIMESTAMP_STATUS,Timestamp status register" hexmask.long.byte 0x0 25.--29. 1. "ATSNS,Number of Auxiliary Timestamp Snapshots" newline bitfld.long 0x0 24. "ATSSTM,Auxiliary Timestamp Snapshot Trigger Missed" "0,1" newline bitfld.long 0x0 16.--17. "ATSSTN,Auxiliary Timestamp Snapshot Trigger Identifier" "0,1,2,3" newline bitfld.long 0x0 15. "TXTSSIS,Tx Timestamp Status Interrupt Status" "0,1" newline bitfld.long 0x0 3. "TSTRGTERR0,Timestamp Target Time Error" "0,1" newline bitfld.long 0x0 2. "AUXTSTRIG,Auxiliary Timestamp Trigger Snapshot" "0,1" newline bitfld.long 0x0 1. "TSTARGT0,Timestamp Target Time Reached" "0,1" newline bitfld.long 0x0 0. "TSSOVF,Timestamp Seconds Overflow" "0,1" rgroup.long 0xB30++0x7 line.long 0x0 "MAC_TX_TIMESTAMP_STATUS_NANOSECONDS,Transmit timestamp status nanoseconds register" bitfld.long 0x0 31. "TXTSSMIS,Transmit Timestamp Status Missed" "0,1" newline hexmask.long 0x0 0.--30. 1. "TXTSSLO,Transmit Timestamp Status Low" line.long 0x4 "MAC_TX_TIMESTAMP_STATUS_SECONDS,Transmit timestamp status seconds register" hexmask.long 0x4 0.--31. 1. "TXTSSHI,Transmit Timestamp Status High" group.long 0xB40++0x3 line.long 0x0 "MAC_AUXILIARY_CONTROL,Auxiliary control register" bitfld.long 0x0 5. "ATSEN1,Auxiliary Snapshot 1 Enable" "0,1" newline bitfld.long 0x0 4. "ATSEN0,Auxiliary Snapshot 0 Enable" "0,1" newline bitfld.long 0x0 0. "ATSFC,Auxiliary Snapshot FIFO Clear" "0,1" rgroup.long 0xB48++0x7 line.long 0x0 "MAC_AUXILIARY_TIMESTAMP_NANOSECONDS,Auxiliary timestamp nanoseconds register" hexmask.long 0x0 0.--30. 1. "AUXTSLO,Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp." line.long 0x4 "MAC_AUXILIARY_TIMESTAMP_SECONDS,Auxiliary timestamp seconds register" hexmask.long 0x4 0.--31. 1. "AUXTSHI,Contains the lower 32 bits of the Seconds field of the auxiliary timestamp." group.long 0xB50++0xF line.long 0x0 "MAC_TIMESTAMP_INGRESS_ASYM_CORR,Timestamp ingress asymmetry correction register" hexmask.long 0x0 0.--31. 1. "OSTIAC,One-Step Timestamp Ingress Asymmetry Correction" line.long 0x4 "MAC_TIMESTAMP_EGRESS_ASYM_CORR,Timestamp egress asymmetry correction register" hexmask.long 0x4 0.--31. 1. "OSTEAC,One-Step Timestamp Egress Asymmetry Correction" line.long 0x8 "MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND,Timestamp ingress correction nanosecond register" hexmask.long 0x8 0.--31. 1. "TSIC,Timestamp Ingress Correction" line.long 0xC "MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND,Timestamp egress correction nanosecond register" hexmask.long 0xC 0.--31. 1. "TSEC,Timestamp Egress Correction" rgroup.long 0xB68++0x7 line.long 0x0 "MAC_TIMESTAMP_INGRESS_LATENCY,MAC Timestamp ingress latency register" hexmask.long.word 0x0 16.--27. 1. "ITLNS,Ingress Timestamp Latency in sub-nanoseconds" newline hexmask.long.byte 0x0 8.--15. 1. "ITLSNS,Ingress Timestamp Latency in nanoseconds" line.long 0x4 "MAC_TIMESTAMP_EGRESS_LATENCY,MAC timestamp egress latency register" hexmask.long.word 0x4 16.--27. 1. "ETLNS,Egress Timestamp Latency in sub-nanoseconds" newline hexmask.long.byte 0x4 8.--15. 1. "ETLSNS,Egress Timestamp Latency in nanoseconds" group.long 0xB70++0x3 line.long 0x0 "MAC_PPS_CONTROL,MAC PPS control register" bitfld.long 0x0 7. "MCGREN0,MCGR Mode Enable for PPS0 Output" "0: 0th PPS instance is enabled to operate in PPS mode,1: 0th PPS instance is enabled to operate in MCGR.." newline bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS0 Output" "0: Target Time registers are programmed only for..,?,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output Mode Enable" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL_PPSCMD,PPS Output Frequency Control" group.long 0xB80++0xF line.long 0x0 "MAC_PPS0_TARGET_TIME_SECONDS,MAC PPS0 target time seconds register" hexmask.long 0x0 0.--31. 1. "TSTRH0,PPS Target Time Seconds Register" line.long 0x4 "MAC_PPS0_TARGET_TIME_NANOSECONDS,MAC PPS0 target time nanoseconds register" bitfld.long 0x4 31. "TRGTBUSY0,PPS Target Time Register Busy" "0,1" newline hexmask.long 0x4 0.--30. 1. "TTSL0,Target Time Low for PPS Register" line.long 0x8 "MAC_PPS0_INTERVAL,MAC PPS0 interval register" hexmask.long 0x8 0.--31. 1. "PPSINT0,PPS Output Signal Interval" line.long 0xC "MAC_PPS0_WIDTH,MAC PPS0 width register" hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPS Output Signal Width" group.long 0xC00++0x3 line.long 0x0 "MTL_OPERATION_MODE,MTL operation mode register" bitfld.long 0x0 15. "FRPE,Flexible Rx parser Enable" "0: Flexible Rx parser is disabled,1: Flexible Rx parser is enabled" newline bitfld.long 0x0 9. "CNTCLR,Counters Reset" "0: Counters are not reset,1: All counters are reset" newline bitfld.long 0x0 8. "CNTPRST,Counters Preset" "0: Counters Preset is disabled,1: Counters Preset is enabled" newline bitfld.long 0x0 5.--6. "SCHALG,Tx Scheduling Algorithm" "0: WRR algorithm,1: WFQ algorithm when DCB feature is selected,2: DWRR algorithm when DCB feature is selected,3: Strict priority algorithm" newline bitfld.long 0x0 2. "RAA,Receive Arbitration Algorithm" "0: Strict priority (SP),1: Weighted Strict Priority (WSP)" newline bitfld.long 0x0 1. "DTXSTS,Drop Transmit Status" "0: Drop Transmit Status is disabled,1: Drop Transmit Status is enabled" group.long 0xC08++0xB line.long 0x0 "MTL_DBG_CTL,MTL debug access control register" bitfld.long 0x0 17.--18. "EIEC,ECC Inject Error Control for Tx Rx and TSO memories" "0: Insert 1 bit error,1: Insert 2 bit errors,2: Insert 3 bit errors,3: Insert 1 bit error in address field" newline bitfld.long 0x0 16. "EIEE,ECC Inject Error Enable for Tx Rx and TSO memories" "0: ECC Inject Error for Tx Rx and TSO memories is..,1: ECC Inject Error for Tx Rx and TSO memories is.." newline bitfld.long 0x0 15. "STSIE,Transmit Status Available Interrupt Status Enable" "0: Transmit Packet Available Interrupt Status is..,1: Packet Available Interrupt Status is enabled" newline bitfld.long 0x0 14. "PKTIE,Receive Packet Available Interrupt Status Enable" "0: Receive Packet Available Interrupt Status is..,1: Receive Packet Available Interrupt Status is.." newline bitfld.long 0x0 12.--13. "FIFOSEL,FIFO Selected for Access" "0: Tx FIFO,1: Tx Status FIFO (only read access when SLVMOD is..,2: TSO FIFO (cannot be accessed when SLVMOD is set),3: Rx FIFO" newline bitfld.long 0x0 11. "FIFOWREN,FIFO Write Enable" "0: FIFO Write is disabled,1: FIFO Write is enabled" newline bitfld.long 0x0 10. "FIFORDEN,FIFO Read Enable" "0: FIFO Read is disabled,1: FIFO Read is enabled" newline bitfld.long 0x0 9. "RSTSEL,Reset Pointers of Selected FIFO" "0: Reset Pointers of Selected FIFO is disabled,1: Reset Pointers of Selected FIFO is enabled" newline bitfld.long 0x0 8. "RSTALL,Reset All Pointers" "0: Reset All Pointers is disabled,1: Reset All Pointers is enabled" newline bitfld.long 0x0 5.--6. "PKTSTATE,Encoded Packet State" "0: Tx Packet Data / Rx Packet Data,1: Tx Control Word / Rx Normal Status,2: Tx SOP Data / Rx Last Status,3: Tx EOP Data / Rx EOP" newline bitfld.long 0x0 2.--3. "BYTEEN,Byte Enables" "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,2: Byte 0 Byte 1 and Byte 2 are valid,3: All four bytes are valid" newline bitfld.long 0x0 1. "DBGMOD,Debug Mode Access to FIFO" "0: Debug Mode Access to FIFO is disabled,1: Debug Mode Access to FIFO is enabled" newline bitfld.long 0x0 0. "FDBGEN,FIFO Debug Access Enable" "0: FIFO Debug Access is disabled,1: FIFO Debug Access is enabled" line.long 0x4 "MTL_DBG_STS,MTL debug status register" hexmask.long.tbyte 0x4 15.--31. 1. "LOCR,Remaining Locations in the FIFO" newline bitfld.long 0x4 9. "STSI,Transmit Status Available Interrupt Status" "0,1" newline bitfld.long 0x4 8. "PKTI,Receive Packet Available Interrupt Status" "0,1" newline bitfld.long 0x4 3.--4. "BYTEEN,Byte Enables" "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,2: Byte 0 Byte 1 and Byte 2 are valid,3: All four bytes are valid" newline bitfld.long 0x4 1.--2. "PKTSTATE,Encoded Packet State" "0: Tx Packet Data / Rx Packet Data,1: Tx Control Word / Rx Normal Status,2: Tx SOP Data / Rx Last Status,3: Tx EOP Data / Rx EOP" newline bitfld.long 0x4 0. "FIFOBUSY,FIFO Busy" "0,1" line.long 0x8 "MTL_FIFO_DEBUG_DATA,MTL FIFO debug data register" hexmask.long 0x8 0.--31. 1. "FDBGDATA,FIFO Debug Data" rgroup.long 0xC20++0x3 line.long 0x0 "MTL_INTERRUPT_STATUS,MTL interrupt status register" bitfld.long 0x0 23. "MTLPIS,MTL Rx Parser Interrupt Status" "0: MTL Rx Parser Interrupt status not detected,1: MTL Rx Parser Interrupt status detected" newline bitfld.long 0x0 18. "ESTIS,EST (TAS- 802.1Qbv) Interrupt Status" "0: Interrupt status not detected,1: Interrupt status detected" newline bitfld.long 0x0 17. "DBGIS,Debug Interrupt status" "0: Debug Interrupt status not detected,1: Debug Interrupt status detected" newline bitfld.long 0x0 2. "Q2IS,Queue 2 Interrupt status" "0: Queue 2 Interrupt status not detected,1: Queue 2 Interrupt status detected" newline bitfld.long 0x0 1. "Q1IS,Queue 1 Interrupt status" "0: Queue 1 Interrupt status not detected,1: Queue 1 Interrupt status detected" newline bitfld.long 0x0 0. "Q0IS,Queue 0 Interrupt status" "0: Queue 0 Interrupt status not detected,1: Queue 0 Interrupt status detected" group.long 0xC30++0x3 line.long 0x0 "MTL_RXQ_DMA_MAP0,MTL receive queue and DMA channel mapping 0 register" bitfld.long 0x0 20. "Q2DDMACH,Queue 2 Enabled for DA-based DMA Channel Selection" "0,1" newline bitfld.long 0x0 16.--17. "Q2MDMACH,Queue 2 Mapped to DMA Channel" "0: DMA Channel 0,1: DMA Channel 1,2: DMA Channel 2,?" newline bitfld.long 0x0 12. "Q1DDMACH,Queue 1 Enabled for DA-based DMA Channel Selection" "0,1" newline bitfld.long 0x0 8.--9. "Q1MDMACH,Queue 1 Mapped to DMA Channel" "0: DMA Channel 0,1: DMA Channel 1,2: DMA Channel 2,?" newline bitfld.long 0x0 4. "Q0DDMACH,Queue 0 Enabled for DA-based DMA Channel Selection" "0,1" newline bitfld.long 0x0 0.--1. "Q0MDMACH,Queue 0 Mapped to DMA Channel" "0: DMA Channel 0,1: DMA Channel 1,2: DMA Channel 2,?" group.long 0xC40++0x3 line.long 0x0 "MTL_TBS_CTRL,MTL time based scheduling control register" hexmask.long.tbyte 0x0 8.--31. 1. "LEOS,Launch Expiry Offset" newline bitfld.long 0x0 4.--6. "LEGOS,Launch Expiry GSN Offset" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1. "LEOV,Launch Expiry Offset Valid" "0,1" newline bitfld.long 0x0 0. "ESTM,EST offset Mode" "0,1" group.long 0xC50++0x3 line.long 0x0 "MTL_EST_CONTROL,MTL enhancements to scheduled transmission control register" hexmask.long.byte 0x0 24.--31. 1. "PTOV,PTP Time Offset Value" newline hexmask.long.word 0x0 12.--23. 1. "CTOV,Current Time Offset Value" newline bitfld.long 0x0 8.--10. "TILS,Time Interval Left Shift Amount" "0: No left shift needed (equal to x1ns),1: Left shift TI by 1 bit (equal to x2ns),2: Left shift TI by 2 bits (equal to x4ns),3: Left shift TI by 3 bits (equal to x8ns),4: Left shift TI by 4 bits (equal to x16ns),5: Left shift TI by 5 bits (equal to x32ns),6: Left shift TI by 6 bits (equal to x64ns),7: Left shift TI by 7 bits (equal to x128ns)" newline bitfld.long 0x0 6.--7. "LCSE,Loop Count to report Scheduling Error" "0: 4 iterations,1: 8 iterations,2: 16 iterations,3: 32 iterations" newline bitfld.long 0x0 5. "DFBS,Drop Frames causing Scheduling Error" "0,1" newline bitfld.long 0x0 4. "DDBF,Do not Drop frames during Frame Size Error" "0,1" newline bitfld.long 0x0 1. "SSWL,Switch to S/W owned list" "0,1" newline bitfld.long 0x0 0. "EEST,Enable EST" "0,1" group.long 0xC58++0x3 line.long 0x0 "MTL_EST_STATUS,MTL enhancements to scheduled transmission status register" hexmask.long.byte 0x0 16.--19. 1. "CGSN,Current GCL Slot Number" newline hexmask.long.byte 0x0 8.--11. 1. "BTRL,BTR Error Loop Count" newline bitfld.long 0x0 7. "SWOL,S/W owned list" "0,1" newline bitfld.long 0x0 4. "CGCE,Constant Gate Control Error" "0,1" newline bitfld.long 0x0 3. "HLBS,Head-Of-Line Blocking due to Scheduling" "0,1" newline bitfld.long 0x0 2. "HLBF,Head-Of-Line Blocking due to Frame Size" "0,1" newline bitfld.long 0x0 1. "BTRE,BTR Error" "0,1" newline bitfld.long 0x0 0. "SWLC,Switch to S/W owned list Complete" "0,1" group.long 0xC60++0x7 line.long 0x0 "MTL_EST_SCH_ERROR,MTL enhancements to scheduled transmission schedule error register" bitfld.long 0x0 0.--2. "SEQN,Schedule Error Queue Number" "0,1,2,3,4,5,6,7" line.long 0x4 "MTL_EST_FRM_SIZE_ERROR,MTL enhancements to scheduled transmission frame size error register" bitfld.long 0x4 0.--2. "FEQN,Frame Size Error Queue Number" "0,1,2,3,4,5,6,7" rgroup.long 0xC68++0x3 line.long 0x0 "MTL_EST_FRM_SIZE_CAPTURE,MTL enhancements to scheduled transmission frame size capture register" bitfld.long 0x0 16.--17. "HBFQ,Queue Number of HLBF" "0,1,2,3" newline hexmask.long.word 0x0 0.--14. 1. "HBFS,Frame Size of HLBF" group.long 0xC70++0x3 line.long 0x0 "MTL_EST_INTR_ENABLE,MTL enhancements to scheduled transmission interrupt enable register" bitfld.long 0x0 4. "CGCE,Interrupt Enable for CGCE" "0,1" newline bitfld.long 0x0 3. "IEHS,Interrupt Enable for HLBS" "0,1" newline bitfld.long 0x0 2. "IEHF,Interrupt Enable for HLBF" "0,1" newline bitfld.long 0x0 1. "IEBE,Interrupt Enable for BTR Error" "0,1" newline bitfld.long 0x0 0. "IECC,Interrupt Enable for Switch List" "0,1" group.long 0xC80++0x7 line.long 0x0 "MTL_EST_GCL_CONTROL,MTL enhancements to scheduled transmission GCL control register" bitfld.long 0x0 22.--23. "ESTEIEC,ECC Inject Error Control for EST Memory" "0: Insert 1 bit error,1: Insert 2 bit errors,2: Insert 3 bit errors,3: Insert 1 bit error in address field" newline bitfld.long 0x0 21. "ESTEIEE,EST ECC Inject Error Enable" "0: EST ECC Inject Error is disabled,1: EST ECC Inject Error is enabled" newline bitfld.long 0x0 20. "ERR0,When set indicates the last write operation was aborted as software writes to GCL and GCL registers is prohibited when SSWL bit of MTL_EST_CONTROL Register is set." "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "ADDR,Gate Control List Address: (GCLA when GCRR is '0')." newline bitfld.long 0x0 5. "DBGB,Debug Mode Bank Select" "0,1" newline bitfld.long 0x0 4. "DBGM,Debug Mode" "0,1" newline bitfld.long 0x0 2. "GCRR,Gate Control Related Registers" "0,1" newline bitfld.long 0x0 1. "R1W0,Read \q1\q Write \q0\q:" "0,1" newline bitfld.long 0x0 0. "SRWO,Start Read/Write Op" "0,1" line.long 0x4 "MTL_EST_GCL_DATA,MTL enhancements to scheduled transmission gate control data register" hexmask.long 0x4 0.--31. 1. "GCD,Gate Control Data" group.long 0xC90++0x7 line.long 0x0 "MTL_FPE_CTRL_STS,MTL FPE control STS register" bitfld.long 0x0 28. "HRS,Hold/Release Status" "0: Indicates a Set-and-Release-MAC operation was..,1: Indicates a Set-and-Hold-MAC operation was last.." newline bitfld.long 0x0 8.--10. "PEC,Preemption Classification" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--1. "AFSZ,Additional Fragment Size" "0,1,2,3" line.long 0x4 "MTL_FPE_ADVANCE,MTL FPE advance register" hexmask.long.word 0x4 16.--31. 1. "RADV,Release Advance" newline hexmask.long.word 0x4 0.--15. 1. "HADV,Hold Advance" group.long 0xCA0++0x7 line.long 0x0 "MTL_RXP_CONTROL_STATUS,MTL RXP control status register" bitfld.long 0x0 31. "RXPI,RX Parser in Idle state" "0: RX Parser not in Idle state,1: RX Parser in Idle state" newline hexmask.long.byte 0x0 16.--23. 1. "NPE,Number of parsable entries in the Instruction table" newline hexmask.long.byte 0x0 0.--7. 1. "NVE,Number of valid entries in the Instruction table" line.long 0x4 "MTL_RXP_INTERRUPT_CONTROL_STATUS,MTL RXP interrupt control status register" bitfld.long 0x4 19. "PDRFIE,Packet Drop due to RF Interrupt Enable" "0: Packet Drop due to RF Interrupt is disabled,1: Packet Drop due to RF Interrupt is enabled" newline bitfld.long 0x4 18. "FOOVIE,Frame Offset Overflow Interrupt Enable" "0: Frame Offset Overflow Interrupt is disabled,1: Frame Offset Overflow Interrupt is enabled" newline bitfld.long 0x4 17. "NPEOVIE,Number of Parsable Entries Overflow Interrupt Enable" "0: Number of Parsable Entries Overflow Interrupt is..,1: Number of Parsable Entries Overflow Interrupt is.." newline bitfld.long 0x4 16. "NVEOVIE,Number of Valid Entries Overflow Interrupt Enable" "0: Number of Valid Entries Overflow Interrupt is..,1: Number of Valid Entries Overflow Interrupt is.." newline bitfld.long 0x4 3. "PDRFIS,Packet Dropped due to RF Interrupt Status" "0: Packet Dropped due to RF Interrupt Status not..,1: Packet Dropped due to RF Interrupt Status detected" newline bitfld.long 0x4 2. "FOOVIS,Frame Offset Overflow Interrupt Status" "0: Frame Offset Overflow Interrupt Status not..,1: Frame Offset Overflow Interrupt Status detected" newline bitfld.long 0x4 1. "NPEOVIS,Number of Parsable Entries Overflow Interrupt Status" "0: Number of Parsable Entries Overflow Interrupt..,1: Number of Parsable Entries Overflow Interrupt.." newline bitfld.long 0x4 0. "NVEOVIS,Number of Valid Entries Overflow Interrupt Status" "0: Number of Valid Entries Overflow Interrupt..,1: Number of Valid Entries Overflow Interrupt.." rgroup.long 0xCA8++0x7 line.long 0x0 "MTL_RXP_DROP_CNT,MTL RXP drop count register" bitfld.long 0x0 31. "RXPDCOVF,Rx Parser Drop Counter Overflow Bit" "0: Rx Parser Drop count overflow not occurred,1: Rx Parser Drop count overflow occurred" newline hexmask.long 0x0 0.--30. 1. "RXPDC,Rx Parser Drop count" line.long 0x4 "MTL_RXP_ERROR_CNT,MTL RXP error count register" bitfld.long 0x4 31. "RXPECOVF,Rx Parser Error Counter Overflow Bit" "0: Rx Parser Error count overflow not occurred,1: Rx Parser Error count overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPEC,Rx Parser Error count" group.long 0xCB0++0x3 line.long 0x0 "MTL_RXP_INDIRECT_ACC_CONTROL_STATUS,MTL RXP indirect access control status register" bitfld.long 0x0 31. "STARTBUSY,FRP Instruction Table Access Busy" "0: Hardware not busy,1: Hardware is busy (Read/Write operation from/to.." newline bitfld.long 0x0 21.--22. "RXPEIEC,ECC Inject Error Control for Rx Parser Memory" "0: Insert 1 bit error,1: Insert 2 bit errors,2: Insert 3 bit errors,3: Insert 1 bit error in address field" newline bitfld.long 0x0 20. "RXPEIEE,ECC Inject Error Enable for Rx Parser Memory" "0: ECC Inject Error for Rx Parser Memory is disabled,1: ECC Inject Error for Rx Parser Memory is enabled" newline bitfld.long 0x0 16. "WRRDN,Read Write Control" "0: Read operation to the Rx Parser Memory,1: Write operation to the Rx Parser Memory" newline hexmask.long.word 0x0 0.--9. 1. "ADDR,FRP Instruction Table Offset Address" rgroup.long 0xCB4++0x3 line.long 0x0 "MTL_RXP_INDIRECT_ACC_DATA,MTL RXP indirect access data register" hexmask.long 0x0 0.--31. 1. "DATA,FRP Instruction Table Write/Read Data" group.long 0xCC0++0x3 line.long 0x0 "MTL_ECC_CONTROL,MTL ECC Control register" bitfld.long 0x0 8. "MEEAO,MTL ECC Error Address Status Over-ride" "0: MTL ECC Error Address Status Over-ride is disabled,1: MTL ECC Error Address Status Over-ride is enabled" newline bitfld.long 0x0 3. "MRXPEE,MTL Rx Parser ECC Enable" "0: MTL Rx Parser ECC is disabled,1: MTL Rx Parser ECC is enabled" newline bitfld.long 0x0 2. "MESTEE,MTL EST ECC Enable" "0: MTL EST ECC is disabled,1: MTL EST ECC is enabled" newline bitfld.long 0x0 1. "MRXEE,MTL Rx FIFO ECC Enable" "0: MTL Rx FIFO ECC is disabled,1: MTL Rx FIFO ECC is enabled" newline bitfld.long 0x0 0. "MTXEE,MTL Tx FIFO ECC Enable" "0: MTL Tx FIFO ECC is disabled,1: MTL Tx FIFO ECC is enabled" rgroup.long 0xCC4++0x3 line.long 0x0 "MTL_SAFETY_INTERRUPT_STATUS,MTL Safety Interrupt Status register" bitfld.long 0x0 31. "MCSIS,MAC Safety Uncorrectable Interrupt Status" "0: MAC Safety Uncorrectable Interrupt Status not..,1: MAC Safety Uncorrectable Interrupt Status detected" newline bitfld.long 0x0 1. "MEUIS,MTL ECC Uncorrectable error Interrupt Status" "0: MTL ECC Uncorrectable error Interrupt Status not..,1: MTL ECC Uncorrectable error Interrupt Status.." newline bitfld.long 0x0 0. "MECIS,MTL ECC Correctable error Interrupt Status" "0: MTL ECC Correctable error Interrupt Status not..,1: MTL ECC Correctable error Interrupt Status.." group.long 0xCC8++0xB line.long 0x0 "MTL_ECC_INTERRUPT_ENABLE,MTL ECC interrupt enable register" bitfld.long 0x0 12. "RPCEIE,Rx Parser memory Correctable Error Interrupt Enable" "0: Rx Parser memory Correctable Error Interrupt is..,1: Rx Parser memory Correctable Error Interrupt is.." newline bitfld.long 0x0 8. "ECEIE,EST memory Correctable Error Interrupt Enable" "0: EST memory Correctable Error Interrupt is disabled,1: EST memory Correctable Error Interrupt is enabled" newline bitfld.long 0x0 4. "RXCEIE,Rx memory Correctable Error Interrupt Enable" "0: Rx memory Correctable Error Interrupt is disabled,1: Rx memory Correctable Error Interrupt is enabled" newline bitfld.long 0x0 0. "TXCEIE,Tx memory Correctable Error Interrupt Enable" "0: Tx memory Correctable Error Interrupt is disabled,1: Tx memory Correctable Error Interrupt is enabled" line.long 0x4 "MTL_ECC_INTERRUPT_STATUS,MTL ECC interrupt status register" bitfld.long 0x4 14. "RPUES,Rx Parser memory Uncorrectable Error Status" "0: Rx Parser memory Uncorrectable Error Status not..,1: Rx Parser memory Uncorrectable Error Status.." newline bitfld.long 0x4 13. "RPAMS,MTL Rx Parser memory Address Mismatch Status" "0: MTL Rx Parser memory Address Mismatch Status not..,1: MTL Rx Parser memory Address Mismatch Status.." newline bitfld.long 0x4 12. "RPCES,MTL Rx Parser memory Correctable Error Status" "0: MTL Rx Parser memory Correctable Error Status..,1: MTL Rx Parser memory Correctable Error Status.." newline bitfld.long 0x4 10. "EUES,MTL EST memory Uncorrectable Error Status" "0: MTL EST memory Uncorrectable Error Status not..,1: MTL EST memory Uncorrectable Error Status detected" newline bitfld.long 0x4 9. "EAMS,MTL EST memory Address Mismatch Status" "0: MTL EST memory Address Mismatch Status not..,1: MTL EST memory Address Mismatch Status detected" newline bitfld.long 0x4 8. "ECES,MTL EST memory Correctable Error Status" "0: MTL EST memory Correctable Error Status not..,1: MTL EST memory Correctable Error Status detected" newline bitfld.long 0x4 6. "RXUES,MTL Rx memory Uncorrectable Error Status" "0: MTL Rx memory Uncorrectable Error Status not..,1: MTL Rx memory Uncorrectable Error Status detected" newline bitfld.long 0x4 5. "RXAMS,MTL Rx memory Address Mismatch Status" "0: MTL Rx memory Address Mismatch Status not detected,1: MTL Rx memory Address Mismatch Status detected" newline bitfld.long 0x4 4. "RXCES,MTL Rx memory Correctable Error Status" "0: MTL Rx memory correctable Error Status not..,1: MTL Rx memory correctable Error Status detected" newline bitfld.long 0x4 2. "TXUES,MTL Tx memory Uncorrectable Error Status" "0: MTL Tx memory Uncorrectable Error Status not..,1: MTL Tx memory Uncorrectable Error Status detected" newline bitfld.long 0x4 1. "TXAMS,MTL Tx memory Address Mismatch Status" "0: MTL Tx memory Address Mismatch Status not detected,1: MTL Tx memory Address Mismatch Status detected" newline bitfld.long 0x4 0. "TXCES,MTL Tx memory Correctable Error Status" "0: MTL Tx memory Correctable Error Status not..,1: MTL Tx memory Correctable Error Status detected" line.long 0x8 "MTL_ECC_ERR_STS_RCTL,MTL ECC Error Status Rctl register" bitfld.long 0x8 5. "CUES,Clear Uncorrectable Error Status" "0: Clear Uncorrectable Error Status not detected,1: Clear Uncorrectable Error Status detected" newline bitfld.long 0x8 4. "CCES,Clear Correctable Error Status" "0: Clear Correctable Error Status not detected,1: Clear Correctable Error Status detected" newline bitfld.long 0x8 1.--3. "EMS,MTL ECC Memory Selection" "0: MTL Tx memory,1: MTL Rx memory,2: MTL EST memory,3: MTL Rx Parser memory,4: DMA TSO memory,?,?,?" newline bitfld.long 0x8 0. "EESRE,MTL ECC Error Status Read Enable" "0: MTL ECC Error Status Read is disabled,1: MTL ECC Error Status Read is enabled" rgroup.long 0xCD4++0x7 line.long 0x0 "MTL_ECC_ERR_ADDR_STATUS,MTL ECC Error Address Status register" hexmask.long.word 0x0 16.--31. 1. "EUEAS,MTL ECC Uncorrectable Error Address Status" newline hexmask.long.word 0x0 0.--15. 1. "ECEAS,MTL ECC Correctable Error Address Status" line.long 0x4 "MTL_ECC_ERR_CNTR_STATUS,MTL ECC Error Counter Status register" hexmask.long.byte 0x4 16.--19. 1. "EUECS,MTL ECC Uncorrectable Error Counter Status" newline hexmask.long.byte 0x4 0.--7. 1. "ECECS,MTL ECC Correctable Error Counter Status" group.long 0xCE0++0x3 line.long 0x0 "MTL_DPP_CONTROL,MTL Data Parity Protection Control register" bitfld.long 0x0 11. "IPERD,Insert Parity error in Rx write-back Descriptor parity generator" "0: Insert Parity error in Rx write-back Descriptor..,1: Insert Parity error in Rx write-back Descriptor.." newline bitfld.long 0x0 10. "IPETD,Insert Parity error in Tx write-back Descriptor parity generator" "0: Insert Parity error in Tx write-back Descriptor..,1: Insert Parity error in Tx write-back Descriptor.." newline bitfld.long 0x0 9. "IPETSO,Insert Parity Error in DMA TSO parity generator" "0: Insert Parity Error in DMA TSO parity generator..,1: Insert Parity Error in DMA TSO parity generator.." newline bitfld.long 0x0 8. "IPEDDC,Insert Parity Error in DMA DTX Control word parity generator" "0: Insert Parity Error in DMA DTX Control word..,1: Insert Parity Error in DMA DTX Control word.." newline bitfld.long 0x0 7. "IPEMRF,Insert Parity Error in MTL Rx FIFO read control parity generator" "0: Insert Parity Error in MTL Rx FIFO read control..,1: Insert Parity Error in MTL Rx FIFO read control.." newline bitfld.long 0x0 6. "IPEMTS,Insert Parity Error in MTL Tx Status parity generator" "0: Insert Parity Error in MTL Tx Status parity..,1: Insert Parity Error in MTL Tx Status parity.." newline bitfld.long 0x0 5. "IPEMC,Insert Parity Error in MTL checksum parity generator" "0: Insert Parity Error in MTL checksum parity..,1: Insert Parity Error in MTL checksum parity.." newline bitfld.long 0x0 4. "IPEID,Insert Parity Error in Interface Data parity generator" "0: Insert Parity Error in Interface Data parity..,1: Insert Parity Error in Interface Data parity.." newline bitfld.long 0x0 2. "EPSI,Enable Parity on Slave Interface port" "0: Parity on Slave Interface port is disabled,1: Parity on Slave Interface port is enabled" newline bitfld.long 0x0 1. "OPE,Odd Parity Enable" "0: Odd Parity is disabled,1: Odd Parity is enabled" newline bitfld.long 0x0 0. "EDPP,Enable Data path Parity Protection" "0: Data path Parity Protection is disabled,1: Data path Parity Protection is enabled" group.long 0xD00++0x3 line.long 0x0 "MTL_TXQ0_OPERATION_MODE,MTL queue 0 transmit operation mode register" hexmask.long.byte 0x0 16.--21. 1. "TQS,Transmit Queue Size" newline bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable" "0: Not enabled,?,2: Enabled,?" newline bitfld.long 0x0 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0xD04++0x7 line.long 0x0 "MTL_TXQ0_UNDERFLOW,MTL queue 0 underflow counter register" bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "MTL_TXQ0_DEBUG,MTL queue 0 transmit debug register" bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status" "0,1" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status" "0,1" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status" "0,1" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause" "0,1" rgroup.long 0xD14++0x3 line.long 0x0 "MTL_TXQ0_ETS_STATUS,MTL queue 0 ETS status register" hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot" group.long 0xD18++0x3 line.long 0x0 "MTL_TXQ0_QUANTUM_WEIGHT,MTL queue 0 quantum or weights register" hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,When WRR algorithm is enabled for Queue 0 traffic this field contains the weight for this queue. The maximum value is 0x64." group.long 0xD2C++0x7 line.long 0x0 "MTL_Q0_INTERRUPT_CONTROL_STATUS,MTL interrupt control status register" bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status" "0,1" newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable" "0,1" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status" "0,1" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status" "0,1" line.long 0x4 "MTL_RXQ0_OPERATION_MODE,MTL RX queue 0 receive operation mode register" hexmask.long.byte 0x4 20.--25. 1. "RQS,Receive Queue Size" newline hexmask.long.byte 0x4 14.--18. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)" newline hexmask.long.byte 0x4 8.--12. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets" "0,1" newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward" "0,1" newline bitfld.long 0x4 4. "FEP,Forward Error Packets" "0,1" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets" "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control" "0: 64,1: 32,2: 96,3: 128" rgroup.long 0xD34++0x7 line.long 0x0 "MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT,MTL RX Queue 0 missed packet and overflow counter register" bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter" newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter" line.long 0x4 "MTL_RXQ0_DEBUG,MTL RX Queue 0 receive debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue" newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status" "0,1" group.long 0xD3C++0x7 line.long 0x0 "MTL_RXQ0_CONTROL,MTL RX Queue receive control register" bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration" "0,1" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight" "0,1,2,3,4,5,6,7" line.long 0x4 "MTL_TXQ1_OPERATION_MODE,MTL Transmit Qn operation mode register" hexmask.long.byte 0x4 16.--21. 1. "TQS,Transmit Queue Size" newline bitfld.long 0x4 4.--6. "TTC,Transmit Threshold Control" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x4 2.--3. "TXQEN,Transmit Queue Enable" "0: Not enabled,1: Enable in AV mode,2: Enabled,?" newline bitfld.long 0x4 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x4 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0xD44++0x7 line.long 0x0 "MTL_TXQ1_UNDERFLOW,MTL Transmit Qn underflow register" bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "MTL_TXQ1_DEBUG,MTL Transmit Qn debug register" bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status" "0,1" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status" "0,1" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status" "0,1" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause" "0,1" group.long 0xD50++0x3 line.long 0x0 "MTL_TXQ1_ETS_CONTROL,MTL Transmit Qn ETS control register" bitfld.long 0x0 4.--6. "SLC,Slot Count" "0: 1 Slot,1: 2 Slots,2: 4 Slots,3: 8 Slots,4: 16 Slots,?,?,?" newline bitfld.long 0x0 3. "CC,Credit Control" "0,1" newline bitfld.long 0x0 2. "AVALG,AV Algorithm" "0,1" rgroup.long 0xD54++0x3 line.long 0x0 "MTL_TXQ1_ETS_STATUS,MTL Transmit Qn ETS status register" hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot" group.long 0xD58++0xF line.long 0x0 "MTL_TXQ1_QUANTUM_WEIGHT,MTL Transmit Qn quantum weight register" hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights" line.long 0x4 "MTL_TXQ1_SENDSLOPECREDIT,MTL Transmit Qn send slope credit register" hexmask.long.word 0x4 0.--13. 1. "SSC,SendSlopeCredit" line.long 0x8 "MTL_TXQ1_HICREDIT,MTL Transmit Qn high credit register" hexmask.long 0x8 0.--28. 1. "HC,HiCredit" line.long 0xC "MTL_TXQ1_LOCREDIT,MTL Transmit Qn low credit register" hexmask.long 0xC 0.--28. 1. "LC,loCredit" group.long 0xD6C++0x7 line.long 0x0 "MTL_Q1_INTERRUPT_CONTROL_STATUS,MTL Qn interrupt control status register" bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status" "0,1" newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable" "0,1" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status" "0,1" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status" "0,1" line.long 0x4 "MTL_RXQ1_OPERATION_MODE,MTL Receive Qn operation mode register" hexmask.long.byte 0x4 20.--25. 1. "RQS,Receive Queue Size" newline hexmask.long.byte 0x4 14.--18. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)" newline hexmask.long.byte 0x4 8.--12. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex modes)" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets" "0,1" newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward" "0,1" newline bitfld.long 0x4 4. "FEP,Forward Error Packets" "0,1" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets" "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control" "0: 64,1: 32,2: 96,3: 128" rgroup.long 0xD74++0x7 line.long 0x0 "MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT,MTL Receive Qn missed packet and overflow counter register" bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter" newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter" line.long 0x4 "MTL_RXQ1_DEBUG,MTL Receive Qn debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue" newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status" "0,1" group.long 0xD7C++0x7 line.long 0x0 "MTL_RXQ1_CONTROL,MTL Receive Qn control register" bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration" "0,1" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight" "0,1,2,3,4,5,6,7" line.long 0x4 "MTL_TXQ2_OPERATION_MODE,MTL Transmit Qn operation mode register" hexmask.long.byte 0x4 16.--21. 1. "TQS,Transmit Queue Size" newline bitfld.long 0x4 4.--6. "TTC,Transmit Threshold Control" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x4 2.--3. "TXQEN,Transmit Queue Enable" "0: Not enabled,1: Enable in AV mode,2: Enabled,?" newline bitfld.long 0x4 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x4 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0xD84++0x7 line.long 0x0 "MTL_TXQ2_UNDERFLOW,MTL Transmit Qn underflow register" bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "MTL_TXQ2_DEBUG,MTL Transmit Qn debug register" bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status" "0,1" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status" "0,1" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status" "0,1" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause" "0,1" group.long 0xD90++0x3 line.long 0x0 "MTL_TXQ2_ETS_CONTROL,MTL Transmit Qn ETS control register" bitfld.long 0x0 4.--6. "SLC,Slot Count" "0: 1 Slot,1: 2 Slots,2: 4 Slots,3: 8 Slots,4: 16 Slots,?,?,?" newline bitfld.long 0x0 3. "CC,Credit Control" "0,1" newline bitfld.long 0x0 2. "AVALG,AV Algorithm" "0,1" rgroup.long 0xD94++0x3 line.long 0x0 "MTL_TXQ2_ETS_STATUS,MTL Transmit Qn ETS status register" hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot" group.long 0xD98++0xF line.long 0x0 "MTL_TXQ2_QUANTUM_WEIGHT,MTL Transmit Qn quantum weight register" hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights" line.long 0x4 "MTL_TXQ2_SENDSLOPECREDIT,MTL Transmit Qn send slope credit register" hexmask.long.word 0x4 0.--13. 1. "SSC,SendSlopeCredit" line.long 0x8 "MTL_TXQ2_HICREDIT,MTL Transmit Qn high credit register" hexmask.long 0x8 0.--28. 1. "HC,HiCredit" line.long 0xC "MTL_TXQ2_LOCREDIT,MTL Transmit Qn low credit register" hexmask.long 0xC 0.--28. 1. "LC,loCredit" group.long 0xDAC++0x7 line.long 0x0 "MTL_Q2_INTERRUPT_CONTROL_STATUS,MTL Qn interrupt control status register" bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status" "0,1" newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable" "0,1" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status" "0,1" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status" "0,1" line.long 0x4 "MTL_RXQ2_OPERATION_MODE,MTL Receive Qn operation mode register" hexmask.long.byte 0x4 20.--25. 1. "RQS,Receive Queue Size" newline hexmask.long.byte 0x4 14.--18. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)" newline hexmask.long.byte 0x4 8.--12. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex modes)" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets" "0,1" newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward" "0,1" newline bitfld.long 0x4 4. "FEP,Forward Error Packets" "0,1" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets" "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control" "0: 64,1: 32,2: 96,3: 128" rgroup.long 0xDB4++0x7 line.long 0x0 "MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT,MTL Receive Qn missed packet and overflow counter register" bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter" newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter" line.long 0x4 "MTL_RXQ2_DEBUG,MTL Receive Qn debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue" newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status" "0,1" group.long 0xDBC++0x3 line.long 0x0 "MTL_RXQ2_CONTROL,MTL Receive Qn control register" bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration" "0,1" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight" "0,1,2,3,4,5,6,7" group.long 0x1000++0x7 line.long 0x0 "DMA_MODE,DMA mode register" bitfld.long 0x0 16.--17. "INTM,Interrupt Mode" "0: sbd_perch_* are pulse signals for each..,1: sbd_perch_* are level signals asserted on..,2: sbd_perch_* are level signals asserted on..,?" newline bitfld.long 0x0 12.--14. "PR,Priority Ratio" "0: The priority ratio is 1:1,1: The priority ratio is 2:1,2: The priority ratio is 3:1,3: The priority ratio is 4:1,4: The priority ratio is 5:1,5: The priority ratio is 6:1,6: The priority ratio is 7:1,7: The priority ratio is 8:1" newline bitfld.long 0x0 11. "TXPR,Transmit Priority" "0,1" newline bitfld.long 0x0 2.--4. "TAA,Transmit Arbitration Algorithm" "0: Fixed priority,1: Weighted Strict Priority (WSP),2: Weighted Round-Robin (WRR),?,?,?,?,?" newline bitfld.long 0x0 1. "DA,DMA Tx or Rx Arbitration Scheme" "0: Weighted Round-Robin with Rx:Tx or Tx:Rx,1: Fixed Priority" newline bitfld.long 0x0 0. "SWR,Software Reset" "0,1" line.long 0x4 "DMA_SYSBUS_MODE,DMA system bus mode register" bitfld.long 0x4 15. "RB,Rebuild INCRx Burst" "0,1" newline bitfld.long 0x4 14. "MB,Mixed Burst" "0,1" newline bitfld.long 0x4 12. "AAL,Address-Aligned Beats" "0,1" newline bitfld.long 0x4 0. "FB,Fixed Burst Length" "0,1" rgroup.long 0x1008++0x7 line.long 0x0 "DMA_INTERRUPT_STATUS,DMA interrupt status register" bitfld.long 0x0 17. "MACIS,MAC Interrupt Status" "0,1" newline bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status" "0,1" newline bitfld.long 0x0 2. "DC2IS,DMA Channel 2 Interrupt Status" "0,1" newline bitfld.long 0x0 1. "DC1IS,DMA Channel 1 Interrupt Status" "0,1" newline bitfld.long 0x0 0. "DC0IS,DMA Channel 0 Interrupt Status" "0,1" line.long 0x4 "DMA_DEBUG_STATUS0,DMA debug status 0 register" hexmask.long.byte 0x4 28.--31. 1. "TPS2,DMA Channel 2 Transmit Process State" newline hexmask.long.byte 0x4 24.--27. 1. "RPS2,DMA Channel 2 Receive Process State" newline hexmask.long.byte 0x4 20.--23. 1. "TPS1,DMA Channel 1 Transmit Process State" newline hexmask.long.byte 0x4 16.--19. 1. "RPS1,DMA Channel 1 Receive Process State" newline hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel 0 Transmit Process State" newline hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel 0 Receive Process State" newline bitfld.long 0x4 0. "AXWHSTS,AHB Master Status" "0,1" group.long 0x1050++0x3 line.long 0x0 "DMA_TBS_CTRL,DMA TBS control register" hexmask.long.tbyte 0x0 8.--31. 1. "FTOS,Fetch Time Offset" newline bitfld.long 0x0 4.--6. "FGOS,Fetch GSN Offset" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "FTOV,Fetch Time Offset Valid" "0,1" rgroup.long 0x1080++0x3 line.long 0x0 "DMA_SAFETY_INTERRUPT_STATUS,DMA safety interrupt status register" bitfld.long 0x0 31. "MCSIS,MAC Safety Uncorrectable Interrupt Status" "0: MAC Safety Uncorrectable Interrupt Status not..,1: MAC Safety Uncorrectable Interrupt Status detected" newline bitfld.long 0x0 29. "MSUIS,MTL Safety Uncorrectable error Interrupt Status" "0: MTL Safety Uncorrectable error Interrupt Status..,1: MTL Safety Uncorrectable error Interrupt Status.." newline bitfld.long 0x0 28. "MSCIS,MTL Safety Correctable error Interrupt Status" "0: MTL Safety Correctable error Interrupt Status..,1: MTL Safety Correctable error Interrupt Status.." newline bitfld.long 0x0 1. "DEUIS,DMA ECC Uncorrectable error Interrupt Status" "0: DMA ECC Uncorrectable error Interrupt Status not..,1: DMA ECC Uncorrectable error Interrupt Status.." newline bitfld.long 0x0 0. "DECIS,DMA ECC Correctable error Interrupt Status" "0: DMA ECC Correctable error Interrupt Status not..,1: DMA ECC Correctable error Interrupt Status.." group.long 0x1100++0xB line.long 0x0 "DMA_CH0_CONTROL,DMA channel 0 control register" bitfld.long 0x0 24. "SPH,Split Headers" "0,1" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" newline hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "DMA_CH0_TX_CONTROL,DMA channel 0 transmit control register" bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable" "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length" newline bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" newline bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" newline bitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command" "0,1" line.long 0x8 "DMA_CH0_RX_CONTROL,DMA channel 0 receive control register" bitfld.long 0x8 31. "RPF,Rx Packet Flush" "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length" newline hexmask.long.word 0x8 4.--14. 1. "RBSZ_13_Y,Receive Buffer size High" newline bitfld.long 0x8 1.--3. "RBSZ_X_0,Receive Buffer size Low" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1114++0x3 line.long 0x0 "DMA_CH0_TXDESC_LIST_ADDRESS,DMA channel 0 transmit descriptor list address register" hexmask.long 0x0 3.--31. 1. "TDESLA,Start of Transmit List" group.long 0x111C++0x7 line.long 0x0 "DMA_CH0_RXDESC_LIST_ADDRESS,DMA channel 0 receive descriptor list address register" hexmask.long 0x0 3.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "DMA_CH0_TXDESC_TAIL_POINTER,DMA channel 0 transmit descriptor tail pointer register" hexmask.long 0x4 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer" group.long 0x1128++0x17 line.long 0x0 "DMA_CH0_RXDESC_TAIL_POINTER,DMA channel 0 receive descriptor tail pointer" hexmask.long 0x0 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer" line.long 0x4 "DMA_CH0_TXDESC_RING_LENGTH,DMA channel 0 transmit descriptor ring length register" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length" line.long 0x8 "DMA_CH0_RXDESC_RING_LENGTH,DMA channel 0 receive descriptor ring length register" hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length" line.long 0xC "DMA_CH0_INTERRUPT_ENABLE,DMA channel 0 interrupt enable register" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable" "0: : Transmit Interrupt,?" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable" "?,1: : Transmit Process Stopped" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable" "0,1" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable" "0,1" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable" "0,1" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER,DMA channel 0 receive interrupt watchdog timer register" bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units" "0: 256,1: 512,2: 1024,3: 2048" newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count" line.long 0x14 "DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS,DMA channel 0 slot function control status register" hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number" newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value" newline bitfld.long 0x14 1. "ASC,Advance Slot Check" "0,1" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison" "0,1" rgroup.long 0x1144++0x3 line.long 0x0 "DMA_CH0_CURRENT_APP_TXDESC,DMA channel 0 current application transmit descriptor register" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer" rgroup.long 0x114C++0x3 line.long 0x0 "DMA_CH0_CURRENT_APP_RXDESC,DMA channel 0 current application transmit descriptor register" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer" rgroup.long 0x1154++0x3 line.long 0x0 "DMA_CH0_CURRENT_APP_TXBUFFER,DMA channel 0 current application transmit buffer register" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer" rgroup.long 0x115C++0x3 line.long 0x0 "DMA_CH0_CURRENT_APP_RXBUFFER,DMA channel 0 current application receive buffer register" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer" group.long 0x1160++0x3 line.long 0x0 "DMA_CH0_STATUS,DMA channel 0 status register" bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0: : Transmit Interrupt,?" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "?,1: : Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt" "0,1" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" newline bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable" "0,1" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" newline bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x1164++0xB line.long 0x0 "DMA_CH0_MISS_FRAME_CNT,DMA channel 0 miss frame counter register" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MFC,This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CHn_RX_CONTROL register. The counter gets cleared when this register is read." line.long 0x4 "DMA_CH0_RXP_ACCEPT_CNT,DMA Channel 0 RXP Accept Counter register" bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter" line.long 0x8 "DMA_CH0_RX_ERI_CNT,DMA Channel 0 RX Early Receive Interrupt Counter register" hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter" group.long 0x1180++0xB line.long 0x0 "DMA_CH1_CONTROL,DMA channel 1 control register" bitfld.long 0x0 24. "SPH,Split Headers" "0,1" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" line.long 0x4 "DMA_CH1_TX_CONTROL,DMA channel 1 transmit control register" bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable" "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length" newline bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" newline bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" newline bitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command" "0,1" line.long 0x8 "DMA_CH1_RX_CONTROL,DMA channel 1 receive control register" bitfld.long 0x8 31. "RPF,Rx Packet Flush" "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length" newline hexmask.long.word 0x8 4.--14. 1. "RBSZ_13_Y,Receive Buffer size High" newline bitfld.long 0x8 1.--3. "RBSZ_X_0,Receive Buffer size Low" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1194++0x3 line.long 0x0 "DMA_CH1_TXDESC_LIST_ADDRESS,DMA channel 1 transmit descriptor list address register" hexmask.long 0x0 3.--31. 1. "TDESLA,Start of Transmit List" group.long 0x119C++0x7 line.long 0x0 "DMA_CH1_RXDESC_LIST_ADDRESS,DMA channel 1 receive descriptor list address register" hexmask.long 0x0 3.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "DMA_CH1_TXDESC_TAIL_POINTER,DMA channel 1 transmit descriptor tail pointer register" hexmask.long 0x4 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer" group.long 0x11A8++0x17 line.long 0x0 "DMA_CH1_RXDESC_TAIL_POINTER,DMA channel 1 receive descriptor tail pointer" hexmask.long 0x0 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer" line.long 0x4 "DMA_CH1_TXDESC_RING_LENGTH,DMA channel 1 transmit descriptor ring length register" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length" line.long 0x8 "DMA_CH1_RXDESC_RING_LENGTH,DMA channel 1 receive descriptor ring length register" hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length" line.long 0xC "DMA_CH1_INTERRUPT_ENABLE,DMA channel 1 interrupt enable register" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable" "0: : Transmit Interrupt,?" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable" "?,1: : Transmit Process Stopped" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable" "0,1" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable" "0,1" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable" "0,1" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER,DMA channel 1 receive interrupt watchdog timer register" bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units" "0: 256,1: 512,2: 1024,3: 2048" newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count" line.long 0x14 "DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS,DMA channel 1 slot function control status register" hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number" newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value" newline bitfld.long 0x14 1. "ASC,Advance Slot Check" "0,1" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison" "0,1" rgroup.long 0x11C4++0x3 line.long 0x0 "DMA_CH1_CURRENT_APP_TXDESC,DMA channel 1 current application transmit descriptor register" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer" rgroup.long 0x11CC++0x3 line.long 0x0 "DMA_CH1_CURRENT_APP_RXDESC,DMA channel 1 current application transmit descriptor register" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer" rgroup.long 0x11D4++0x3 line.long 0x0 "DMA_CH1_CURRENT_APP_TXBUFFER,DMA channel 1 current application transmit buffer register" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer" rgroup.long 0x11DC++0x3 line.long 0x0 "DMA_CH1_CURRENT_APP_RXBUFFER,DMA channel 1 current application receive buffer register" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer" group.long 0x11E0++0x3 line.long 0x0 "DMA_CH1_STATUS,DMA channel 1 status register" bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0: : Transmit Interrupt,?" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "?,1: : Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt" "0,1" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" newline bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable" "0,1" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" newline bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x11E4++0xB line.long 0x0 "DMA_CH1_MISS_FRAME_CNT,DMA channel 1 miss frame counter register" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MFC,This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CHn_RX_CONTROL register. The counter gets cleared when this register is read." line.long 0x4 "DMA_CH1_RXP_ACCEPT_CNT,DMA Channel 1 RXP Accept Counter register" bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter" line.long 0x8 "DMA_CH1_RX_ERI_CNT,DMA Channel 1 RX Early Receive Interrupt Counter register" hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter" group.long 0x1200++0xB line.long 0x0 "DMA_CH2_CONTROL,DMA channel 2 control register" bitfld.long 0x0 24. "SPH,Split Headers" "0,1" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" line.long 0x4 "DMA_CH2_TX_CONTROL,DMA channel 2 transmit control register" bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable" "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length" newline bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" newline bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" newline bitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command" "0,1" line.long 0x8 "DMA_CH2_RX_CONTROL,DMA channel 2 receive control register" bitfld.long 0x8 31. "RPF,Rx Packet Flush" "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length" newline hexmask.long.word 0x8 4.--14. 1. "RBSZ_13_Y,Receive Buffer size High" newline bitfld.long 0x8 1.--3. "RBSZ_X_0,Receive Buffer size Low" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1214++0x3 line.long 0x0 "DMA_CH2_TXDESC_LIST_ADDRESS,DMA channel 2 transmit descriptor list address register" hexmask.long 0x0 3.--31. 1. "TDESLA,Start of Transmit List" group.long 0x121C++0x7 line.long 0x0 "DMA_CH2_RXDESC_LIST_ADDRESS,DMA channel 2 receive descriptor list address register" hexmask.long 0x0 3.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "DMA_CH2_TXDESC_TAIL_POINTER,DMA channel 2 transmit descriptor tail pointer register" hexmask.long 0x4 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer" group.long 0x1228++0x17 line.long 0x0 "DMA_CH2_RXDESC_TAIL_POINTER,DMA channel 2 receive descriptor tail pointer" hexmask.long 0x0 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer" line.long 0x4 "DMA_CH2_TXDESC_RING_LENGTH,DMA channel 2 transmit descriptor ring length register" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length" line.long 0x8 "DMA_CH2_RXDESC_RING_LENGTH,DMA channel 2 receive descriptor ring length register" hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length" line.long 0xC "DMA_CH2_INTERRUPT_ENABLE,DMA channel 2 interrupt enable register" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable" "0: : Transmit Interrupt,?" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable" "?,1: : Transmit Process Stopped" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable" "0,1" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable" "0,1" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable" "0,1" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "DMA_CH2_RX_INTERRUPT_WATCHDOG_TIMER,DMA channel 2 receive interrupt watchdog timer register" bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units" "0: 256,1: 512,2: 1024,3: 2048" newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count" line.long 0x14 "DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS,DMA channel 2 slot function control status register" hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number" newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value" newline bitfld.long 0x14 1. "ASC,Advance Slot Check" "0,1" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison" "0,1" rgroup.long 0x1244++0x3 line.long 0x0 "DMA_CH2_CURRENT_APP_TXDESC,DMA channel 2 current application transmit descriptor register" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer" rgroup.long 0x124C++0x3 line.long 0x0 "DMA_CH2_CURRENT_APP_RXDESC,DMA channel 2 current application transmit descriptor register" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer" rgroup.long 0x1254++0x3 line.long 0x0 "DMA_CH2_CURRENT_APP_TXBUFFER,DMA channel 2 current application transmit buffer register" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer" rgroup.long 0x125C++0x3 line.long 0x0 "DMA_CH2_CURRENT_APP_RXBUFFER,DMA channel 2 current application receive buffer register" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer" group.long 0x1260++0x3 line.long 0x0 "DMA_CH2_STATUS,DMA channel 2 status register" bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0: : Transmit Interrupt,?" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "?,1: : Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt" "0,1" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" newline bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable" "0,1" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" newline bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x1264++0xB line.long 0x0 "DMA_CH2_MISS_FRAME_CNT,DMA channel 2 miss frame counter register" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MFC,This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CHn_RX_CONTROL register. The counter gets cleared when this register is read." line.long 0x4 "DMA_CH2_RXP_ACCEPT_CNT,DMA Channel 2 RXP Accept Counter register" bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter" line.long 0x8 "DMA_CH2_RX_ERI_CNT,DMA Channel 2 RX Early Receive Interrupt Counter register" hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter" tree.end tree.end tree "FCCU2 (Fault Collection and Control Unit)" base ad:0x71738000 group.long 0x0++0xB line.long 0x0 "CTRL,FCCU2 Control register" bitfld.long 0x0 31. "FILTER_BYPASS,Glitch Filter bypass" "0: glitch filter not bypassed,1: glitch filter bypassed" newline bitfld.long 0x0 29.--30. "FILTER_WIDTH,Glitch Filter width" "0: filters glitches up to 50 µ s,1: filters glitches up to 75 µ s,2: filters glitches up to 100 µ s,3: filters glitches up to 100 µ s" newline bitfld.long 0x0 16. "NSCP_RST_EN,Non Safety Critical Pin Enable" "0: disable,1: enable" newline bitfld.long 0x0 15. "IRQ_EOUT_EN,It enables the FCCU2_REACTION_STAT.IRQ_EOUT." "0: IRQ_EOUT disabled.,1: RQ_EOUT enabled." newline bitfld.long 0x0 14. "CFG_TO_IEN,Configuration Timeout Interrupt Enable" "0: Configuration timeout interrupt disabled.,1: Configuration timeout interrupt enabled." newline bitfld.long 0x0 10. "DEBUG_OUT_EN,Enable the debug Request from FCCU2" "0: Disabled,1: Enabled" newline bitfld.long 0x0 9. "DEBUG_IN_EN,Debug mode entry" "0: Normal operation,1: Put FCCU2 into debug mode" newline bitfld.long 0x0 6.--7. "OPS,Operation status" "0: Idle,1: In progress/Busy,2: Aborted,3: Successful" newline hexmask.long.byte 0x0 0.--4. 1. "OPR,Operation run" line.long 0x4 "CTRLK,FCCU2 CTRL Key register" hexmask.long 0x4 0.--31. 1. "CTRLK_VAL,Control register key" line.long 0x8 "CFG,FCCU2 Configuration register" hexmask.long.byte 0x8 25.--31. 1. "TGL,EOUT toggling time(3)" newline bitfld.long 0x8 24. "EOUT_EN_AFTR_RST,This bit controls the enable of the o/p error pin after reset is de-asserted" "0: FCCU2 Error indication is not functioning and..,1: FCCU2 Error indication enabled." newline bitfld.long 0x8 22.--23. "EOUT_SET_OR_CLEAR,Error pin state can be controlled by these bits" "0: FCCU2 acts independent of SW control.,1: Error Pin driven to logic FCCU2_CFG.PS for a..,2: Error Pin driven to logic ~FCCU2_CFG.PS (write..,3: FCCU2 acts independent of above SW control (same.." newline bitfld.long 0x8 21. "RCCE1,RCC1 enable" "0: RCC1 disabled,1: RCC1 enabled" newline bitfld.long 0x8 20. "RCCE0,RCC0 enable" "0: RCC0 disabled,1: RCC0 enabled" newline hexmask.long.byte 0x8 16.--19. 1. "SMRT,Safe Mode Request Timer" newline bitfld.long 0x8 15. "OD,Open Drain" "0: push-pull,1: OD" newline bitfld.long 0x8 14. "CM,Config mode" "0: Configuration labeling: a specific EOUT..,1: Configuration transparency: the EOUT protocol is.." newline bitfld.long 0x8 13. "SM,Switching mode" "0: EOUT protocol (dual rail time switching) slow..,1: EOUT protocol (dual rail time switching) fast.." newline bitfld.long 0x8 12. "PS,Polarity selection" "0: FCCU2 Error output[1] active high FCCU2 Error..,1: FCCU2 Error output[1] active low FCCU2 Error.." newline bitfld.long 0x8 10.--11. "FOME,Fault Output Mode Extension" "0: current behave (default),1: option #1,2: option #2,3: option #3 (only active if CFG.FOM = 000)" newline bitfld.long 0x8 7.--9. "FOM,Fault Output Mode selection" "0: Dual Rail [FCCU2 Error output[1:0]= outputs],1: Time Switching [FCCU2 Error output[1:0]= output..,2: Differential Bi-stable (default) [FCCU2 Error..,3: Single-ended Bi-stable protocol [FCCU2 Error..,?,5: Test0 (controlled by FCCU2_EINOUT register)..,6: Test1 (controlled by FCCU2_EINOUT register)..,7: Test2 (controlled by FCCU2_EINOUT register).." newline hexmask.long.byte 0x8 0.--6. 1. "FOP,Fault Output Prescaler" group.long 0x100++0x7 line.long 0x0 "UF_CONF0,FCCU2 UF Channel Configuration register 0" hexmask.long.byte 0x0 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3. Refer to Section1.6.27: FCCU2 Reaction Configuration register n (FCCU2_REACT_CNFGn) for details. For example writing a value 011011 selects contents of FCCU2_REACT_CNFG27.." newline hexmask.long.byte 0x0 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2. Refer to Section1.6.27: FCCU2 Reaction Configuration register n (FCCU2_REACT_CNFGn) for details. For example writing a value 011011 selects contents of FCCU2_REACT_CNFG27.." newline hexmask.long.byte 0x0 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 + 1. Refer to Section1.6.27: FCCU2 Reaction Configuration register n (FCCU2_REACT_CNFGn) for details. For example writing a value 011011 selects contents of FCCU2_REACT_CNFG27.." newline hexmask.long.byte 0x0 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4. Refer to Section1.6.27: FCCU2 Reaction Configuration register n (FCCU2_REACT_CNFGn) for details. For example writing a value 011011 selects contents of FCCU2_REACT_CNFG27 as.." line.long 0x4 "UF_CONF1,FCCU2 UF Channel Configuration register 1" hexmask.long.byte 0x4 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3. Refer to Section1.6.27: FCCU2 Reaction Configuration register n (FCCU2_REACT_CNFGn) for details. For example writing a value 011011 selects contents of FCCU2_REACT_CNFG27.." newline hexmask.long.byte 0x4 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2. Refer to Section1.6.27: FCCU2 Reaction Configuration register n (FCCU2_REACT_CNFGn) for details. For example writing a value 011011 selects contents of FCCU2_REACT_CNFG27.." newline hexmask.long.byte 0x4 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 + 1. Refer to Section1.6.27: FCCU2 Reaction Configuration register n (FCCU2_REACT_CNFGn) for details. For example writing a value 011011 selects contents of FCCU2_REACT_CNFG27.." newline hexmask.long.byte 0x4 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4. Refer to Section1.6.27: FCCU2 Reaction Configuration register n (FCCU2_REACT_CNFGn) for details. For example writing a value 011011 selects contents of FCCU2_REACT_CNFG27 as.." group.long 0x500++0xB7 line.long 0x0 "RF_CONF0,FCCU2 RF channel configuration register 0" hexmask.long.byte 0x0 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x0 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x0 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x0 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x4 "RF_CONF1,FCCU2 RF channel configuration register 1" hexmask.long.byte 0x4 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x4 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x4 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x4 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x8 "RF_CONF2,FCCU2 RF channel configuration register 2" hexmask.long.byte 0x8 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x8 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x8 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x8 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0xC "RF_CONF3,FCCU2 RF channel configuration register 3" hexmask.long.byte 0xC 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0xC 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0xC 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0xC 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x10 "RF_CONF4,FCCU2 RF channel configuration register 4" hexmask.long.byte 0x10 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x10 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x10 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x10 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x14 "RF_CONF5,FCCU2 RF channel configuration register 5" hexmask.long.byte 0x14 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x14 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x14 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x14 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x18 "RF_CONF6,FCCU2 RF channel configuration register 6" hexmask.long.byte 0x18 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x18 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x18 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x18 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x1C "RF_CONF7,FCCU2 RF channel configuration register 7" hexmask.long.byte 0x1C 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x1C 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x1C 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x1C 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x20 "RF_CONF8,FCCU2 RF channel configuration register 8" hexmask.long.byte 0x20 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x20 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x20 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x20 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x24 "RF_CONF9,FCCU2 RF channel configuration register 9" hexmask.long.byte 0x24 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x24 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x24 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x24 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x28 "RF_CONF10,FCCU2 RF channel configuration register 10" hexmask.long.byte 0x28 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x28 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x28 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x28 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x2C "RF_CONF11,FCCU2 RF channel configuration register 11" hexmask.long.byte 0x2C 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x2C 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x2C 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x2C 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x30 "RF_CONF12,FCCU2 RF channel configuration register 12" hexmask.long.byte 0x30 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x30 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x30 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x30 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x34 "RF_CONF13,FCCU2 RF channel configuration register 13" hexmask.long.byte 0x34 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x34 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x34 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x34 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x38 "RF_CONF14,FCCU2 RF channel configuration register 14" hexmask.long.byte 0x38 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x38 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x38 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x38 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x3C "RF_CONF15,FCCU2 RF channel configuration register 15" hexmask.long.byte 0x3C 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x3C 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x3C 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x3C 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x40 "RF_CONF16,FCCU2 RF channel configuration register 16" hexmask.long.byte 0x40 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x40 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x40 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x40 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x44 "RF_CONF17,FCCU2 RF channel configuration register 17" hexmask.long.byte 0x44 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x44 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x44 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x44 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x48 "RF_CONF18,FCCU2 RF channel configuration register 18" hexmask.long.byte 0x48 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x48 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x48 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x48 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x4C "RF_CONF19,FCCU2 RF channel configuration register 19" hexmask.long.byte 0x4C 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x4C 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x4C 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x4C 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x50 "RF_CONF20,FCCU2 RF channel configuration register 20" hexmask.long.byte 0x50 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x50 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x50 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x50 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x54 "RF_CONF21,FCCU2 RF channel configuration register 21" hexmask.long.byte 0x54 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x54 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x54 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x54 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x58 "RF_CONF22,FCCU2 RF channel configuration register 22" hexmask.long.byte 0x58 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x58 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x58 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x58 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x5C "RF_CONF23,FCCU2 RF channel configuration register 23" hexmask.long.byte 0x5C 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x5C 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x5C 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x5C 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x60 "RF_CONF24,FCCU2 RF channel configuration register 24" hexmask.long.byte 0x60 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x60 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x60 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x60 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x64 "RF_CONF25,FCCU2 RF channel configuration register 25" hexmask.long.byte 0x64 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x64 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x64 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x64 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x68 "RF_CONF26,FCCU2 RF channel configuration register 26" hexmask.long.byte 0x68 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x68 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x68 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x68 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x6C "RF_CONF27,FCCU2 RF channel configuration register 27" hexmask.long.byte 0x6C 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x6C 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x6C 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x6C 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x70 "RF_CONF28,FCCU2 RF channel configuration register 28" hexmask.long.byte 0x70 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x70 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x70 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x70 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x74 "RF_CONF29,FCCU2 RF channel configuration register 29" hexmask.long.byte 0x74 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x74 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x74 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x74 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x78 "RF_CONF30,FCCU2 RF channel configuration register 30" hexmask.long.byte 0x78 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x78 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x78 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x78 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x7C "RF_CONF31,FCCU2 RF channel configuration register 31" hexmask.long.byte 0x7C 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x7C 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x7C 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x7C 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x80 "RF_CONF32,FCCU2 RF channel configuration register 32" hexmask.long.byte 0x80 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x80 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x80 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x80 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x84 "RF_CONF33,FCCU2 RF channel configuration register 33" hexmask.long.byte 0x84 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x84 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x84 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x84 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x88 "RF_CONF34,FCCU2 RF channel configuration register 34" hexmask.long.byte 0x88 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x88 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x88 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x88 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x8C "RF_CONF35,FCCU2 RF channel configuration register 35" hexmask.long.byte 0x8C 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x8C 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x8C 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x8C 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x90 "RF_CONF36,FCCU2 RF channel configuration register 36" hexmask.long.byte 0x90 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x90 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x90 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x90 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x94 "RF_CONF37,FCCU2 RF channel configuration register 37" hexmask.long.byte 0x94 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x94 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x94 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x94 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x98 "RF_CONF38,FCCU2 RF channel configuration register 38" hexmask.long.byte 0x98 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x98 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x98 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x98 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0x9C "RF_CONF39,FCCU2 RF channel configuration register 39" hexmask.long.byte 0x9C 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0x9C 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0x9C 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0x9C 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0xA0 "RF_CONF40,FCCU2 RF channel configuration register 40" hexmask.long.byte 0xA0 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0xA0 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0xA0 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0xA0 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0xA4 "RF_CONF41,FCCU2 RF channel configuration register 41" hexmask.long.byte 0xA4 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0xA4 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0xA4 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0xA4 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0xA8 "RF_CONF42,FCCU2 RF channel configuration register 42" hexmask.long.byte 0xA8 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0xA8 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0xA8 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0xA8 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0xAC "RF_CONF43,FCCU2 RF channel configuration register 43" hexmask.long.byte 0xAC 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0xAC 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0xAC 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0xAC 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0xB0 "RF_CONF44,FCCU2 RF channel configuration register 44" hexmask.long.byte 0xB0 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0xB0 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0xB0 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0xB0 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" line.long 0xB4 "RF_CONF45,FCCU2 RF channel configuration register 45" hexmask.long.byte 0xB4 24.--29. 1. "RCT_CNFG3,Reaction Configuration register number/index for fault channel n*4 + 3" newline hexmask.long.byte 0xB4 16.--21. 1. "RCT_CNFG2,Reaction Configuration register number/index for fault channel n*4 + 2" newline hexmask.long.byte 0xB4 8.--13. 1. "RCT_CNFG1,Reaction Configuration register number/index for fault channel n*4 +1" newline hexmask.long.byte 0xB4 0.--5. 1. "RCT_CNFG0,Reaction Configuration register number/index for fault channel n*4" group.long 0x900++0x3 line.long 0x0 "UF_S0,FCCU2 UF Status register 0" bitfld.long 0x0 31. "UFS31,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 30. "UFS30,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 29. "UFS29,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 28. "UFS28,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 27. "UFS27,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 26. "UFS26,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 25. "UFS25,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 24. "UFS24,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 23. "UFS23,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 22. "UFS22,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 21. "UFS21,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 20. "UFS20,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 19. "UFS19,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 18. "UFS18,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 17. "UFS17,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 16. "UFS16,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 15. "UFS15,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 14. "UFS14,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 13. "UFS13,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 12. "UFS12,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 11. "UFS11,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 10. "UFS10,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 9. "UFS9,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 8. "UFS8,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 7. "UFS7,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 6. "UFS6,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 5. "UFS5,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 4. "UFS4,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 3. "UFS3,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 2. "UFS2,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 1. "UFS1,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." newline bitfld.long 0x0 0. "UFS0,Unrecoverable fault status" "0: No unrecoverable fault latched.,1: Unrecoverable fault latched." group.long 0x1100++0x17 line.long 0x0 "RF_S0,FCCU2 RF Status register 0" bitfld.long 0x0 31. "RFS31,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 30. "RFS30,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 29. "RFS29,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 28. "RFS28,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 27. "RFS27,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 26. "RFS26,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 25. "RFS25,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 24. "RFS24,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 23. "RFS23,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 22. "RFS22,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 21. "RFS21,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 20. "RFS20,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 19. "RFS19,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 18. "RFS18,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 17. "RFS17,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 16. "RFS16,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 15. "RFS15,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 14. "RFS14,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 13. "RFS13,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 12. "RFS12,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 11. "RFS11,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 10. "RFS10,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 9. "RFS9,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 8. "RFS8,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 7. "RFS7,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 6. "RFS6,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 5. "RFS5,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 4. "RFS4,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 3. "RFS3,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 2. "RFS2,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 1. "RFS1,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x0 0. "RFS0,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." line.long 0x4 "RF_S1,FCCU2 RF Status register 1" bitfld.long 0x4 31. "RFS31,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 30. "RFS30,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 29. "RFS29,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 28. "RFS28,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 27. "RFS27,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 26. "RFS26,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 25. "RFS25,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 24. "RFS24,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 23. "RFS23,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 22. "RFS22,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 21. "RFS21,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 20. "RFS20,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 19. "RFS19,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 18. "RFS18,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 17. "RFS17,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 16. "RFS16,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 15. "RFS15,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 14. "RFS14,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 13. "RFS13,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 12. "RFS12,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 11. "RFS11,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 10. "RFS10,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 9. "RFS9,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 8. "RFS8,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 7. "RFS7,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 6. "RFS6,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 5. "RFS5,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 4. "RFS4,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 3. "RFS3,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 2. "RFS2,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 1. "RFS1,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x4 0. "RFS0,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." line.long 0x8 "RF_S2,FCCU2 RF Status register 2" bitfld.long 0x8 31. "RFS31,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 30. "RFS30,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 29. "RFS29,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 28. "RFS28,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 27. "RFS27,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 26. "RFS26,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 25. "RFS25,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 24. "RFS24,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 23. "RFS23,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 22. "RFS22,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 21. "RFS21,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 20. "RFS20,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 19. "RFS19,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 18. "RFS18,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 17. "RFS17,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 16. "RFS16,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 15. "RFS15,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 14. "RFS14,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 13. "RFS13,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 12. "RFS12,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 11. "RFS11,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 10. "RFS10,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 9. "RFS9,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 8. "RFS8,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 7. "RFS7,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 6. "RFS6,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 5. "RFS5,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 4. "RFS4,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 3. "RFS3,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 2. "RFS2,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 1. "RFS1,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x8 0. "RFS0,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." line.long 0xC "RF_S3,FCCU2 RF Status register 3" bitfld.long 0xC 31. "RFS31,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 30. "RFS30,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 29. "RFS29,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 28. "RFS28,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 27. "RFS27,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 26. "RFS26,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 25. "RFS25,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 24. "RFS24,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 23. "RFS23,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 22. "RFS22,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 21. "RFS21,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 20. "RFS20,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 19. "RFS19,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 18. "RFS18,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 17. "RFS17,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 16. "RFS16,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 15. "RFS15,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 14. "RFS14,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 13. "RFS13,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 12. "RFS12,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 11. "RFS11,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 10. "RFS10,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 9. "RFS9,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 8. "RFS8,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 7. "RFS7,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 6. "RFS6,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 5. "RFS5,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 4. "RFS4,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 3. "RFS3,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 2. "RFS2,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 1. "RFS1,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0xC 0. "RFS0,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." line.long 0x10 "RF_S4,FCCU2 RF Status register 4" bitfld.long 0x10 31. "RFS31,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 30. "RFS30,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 29. "RFS29,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 28. "RFS28,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 27. "RFS27,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 26. "RFS26,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 25. "RFS25,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 24. "RFS24,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 23. "RFS23,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 22. "RFS22,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 21. "RFS21,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 20. "RFS20,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 19. "RFS19,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 18. "RFS18,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 17. "RFS17,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 16. "RFS16,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 15. "RFS15,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 14. "RFS14,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 13. "RFS13,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 12. "RFS12,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 11. "RFS11,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 10. "RFS10,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 9. "RFS9,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 8. "RFS8,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 7. "RFS7,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 6. "RFS6,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 5. "RFS5,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 4. "RFS4,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 3. "RFS3,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 2. "RFS2,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 1. "RFS1,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x10 0. "RFS0,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." line.long 0x14 "RF_S5,FCCU2 RF Status register 5" bitfld.long 0x14 31. "RFS31,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 30. "RFS30,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 29. "RFS29,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 28. "RFS28,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 27. "RFS27,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 26. "RFS26,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 25. "RFS25,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 24. "RFS24,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 23. "RFS23,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 22. "RFS22,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 21. "RFS21,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 20. "RFS20,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 19. "RFS19,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 18. "RFS18,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 17. "RFS17,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 16. "RFS16,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 15. "RFS15,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 14. "RFS14,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 13. "RFS13,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 12. "RFS12,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 11. "RFS11,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 10. "RFS10,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 9. "RFS9,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 8. "RFS8,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 7. "RFS7,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 6. "RFS6,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 5. "RFS5,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 4. "RFS4,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 3. "RFS3,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 2. "RFS2,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 1. "RFS1,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." newline bitfld.long 0x14 0. "RFS0,Recoverable fault status" "0: No recoverable fault latched.,1: Recoverable fault latched." group.long 0x1180++0x7 line.long 0x0 "UFK,FCCU2 UF Key register" hexmask.long 0x0 0.--31. 1. "UFK_VAL,Unrecoverable fault key = 0x618B_7A50" line.long 0x4 "RFK,FCCU2 RF Key register" hexmask.long 0x4 0.--31. 1. "RFK_VAL,Recoverable fault key = 0xAB34_98FE" group.long 0x11B8++0x7 line.long 0x0 "CFG_TO,FCCU2 CFG Timeout register" hexmask.long.byte 0x0 0.--3. 1. "TO,Configuration timeout" line.long 0x4 "EINOUT,FCCU2 IO Control register" bitfld.long 0x4 7. "EIN3,Error input 3" "0: when FCCU2 Error input[3] = 0,1: when FCCU2 Error input[3] = 1" newline bitfld.long 0x4 6. "EIN2,Error input 2" "0: when FCCU2 Error input[2] = 0,1: when FCCU2 Error input[2] = 1" newline bitfld.long 0x4 5. "EIN1,Error input 1" "0: when FCCU2 Error input[1] = 0,1: when FCCU2 Error input[1] = 1" newline bitfld.long 0x4 4. "EIN0,Error input 0" "0: when FCCU2 Error input[0] = 0,1: when FCCU2 Error input[0] = 1" newline bitfld.long 0x4 3. "EOUT3,Error out 3 (significant only if the FCCU2_CFG.FOM = Test1 or Test0 FCCU2 Error output[3] configured in output mode)." "0: force FCCU2 Error output[3] = 0,1: force FCCU2 Error output[3] = 1" newline bitfld.long 0x4 2. "EOUT2,Error out 2(significative only if the FCCU2_CFG.FOM = Test1 or Test2 FCCU2 Error output[2] configured in output mode)" "0: force FCCU2 Error output[2] = 0,1: force FCCU2 Error output[2] = 1" newline bitfld.long 0x4 1. "EOUT1,Error out 1 (significant only if the FCCU2_CFG.FOM = Test1 or Test0 FCCU2 Error output[1] configured in output mode)." "0: force FCCU2 Error output[1] = 0,1: force FCCU2 Error output[1] = 1" newline bitfld.long 0x4 0. "EOUT0,Error out 0 (significant only if the FCCU2_CFG.FOM = Test1 or Test2 FCCU2 Error output[0] configured in output mode)" "0: force FCCU2 Error output[0] = 0,1: force FCCU2 Error output[0] = 1" rgroup.long 0x11C0++0x13 line.long 0x0 "STAT,FCCU2 Status register" bitfld.long 0x0 17. "RCCS1,RCC1 Status" "0: No mis-compares.,1: A mis-compare has been detected. The interrupt.." newline bitfld.long 0x0 16. "RCCS0,RCC0 Status" "0: No mis-compares.,1: A mis-compare has been detected. The interrupt.." newline hexmask.long.byte 0x0 4.--7. 1. "EOUT,EOUT state" newline hexmask.long.byte 0x0 0.--3. 1. "FSM_STATUS,FCCU2 FSM Status" line.long 0x4 "N2AF_STATUS,FCCU2 NA Freeze Status register" hexmask.long.word 0x4 0.--9. 1. "NAFS,Normal to Alarm Frozen Status" line.long 0x8 "A2FF_STATUS,FCCU2 AF Freeze Status register" bitfld.long 0x8 10.--11. "AF_SRC,Fault source" "0: No fault,?,2: Recoverable fault,?" newline hexmask.long.word 0x8 0.--9. 1. "AFFS,Alarm to Fault Frozen Status" line.long 0xC "N2FF_STATUS,FCCU2 NF Freeze Status register" bitfld.long 0xC 10.--11. "NF_SRC,Fault source" "0: No fault,?,2: Recoverable fault,?" newline hexmask.long.word 0xC 0.--9. 1. "NFFS,Normal to Fault Frozen Status" line.long 0x10 "F2AF_STATUS,FCCU2 FA Freeze Status register" hexmask.long.word 0x10 0.--9. 1. "FAFS,Fault to Normal Frozen Status" group.long 0x11E0++0x3 line.long 0x0 "REACTION_STAT,FCCU2 Reaction Status register" hexmask.long.byte 0x0 24.--31. 1. "VFEI_STAT,Virtual Fault Event Interrupt Status" newline hexmask.long.byte 0x0 16.--23. 1. "FEI_STAT,Fault Event Interrupt Status" newline hexmask.long.word 0x0 7.--15. 1. "IRQ_STAT,Alarm Interrupt Status" newline bitfld.long 0x0 4. "DMA_REQ,Status bit asserted when EOUT counter = T_TRG in NORMAL/ALARM mode" "0,1" newline bitfld.long 0x0 3. "IRQ_EOUT,Interrupt status bit asserted when EOUT counter = T_TRG in NORMAL/ALARM mode." "0,1" newline bitfld.long 0x0 0. "CFG_TO_STAT,Configuration Timeout Status" "0: No configuration timeout error.,1: Configuration timeout error" rgroup.long 0x11E8++0x7 line.long 0x0 "XTMR,FCCU2 XTMR register" hexmask.long 0x0 0.--31. 1. "XTMR_VAL,Alarm/Watchdog/Safe request timer" line.long 0x4 "MCS,FCCU2 MCS register" bitfld.long 0x4 31. "VL3,Valid" "0: MCS3 FS3 fields are not significant.,1: MCS3 FS3 fields are significant." newline bitfld.long 0x4 30. "FS3,Fault status" "0: MCS3 field captured in any state different from..,1: MCS3 field captured in FAULT state." newline hexmask.long.byte 0x4 24.--27. 1. "MCS3,State of MC modules" newline bitfld.long 0x4 23. "VL2,Valid" "0: MCS2 FS2 fields are not significant.,1: MCS2 FS2 fields are significant." newline bitfld.long 0x4 22. "FS2,Fault status" "0: MCS2 field captured in any state different from..,1: MCS2 field captured in FAULT state." newline hexmask.long.byte 0x4 16.--19. 1. "MCS2,State of MC modules" newline bitfld.long 0x4 15. "VL1,Valid" "0: MCS1 FS1 fields are not significant.,1: MCS1 FS1 fields are significant." newline bitfld.long 0x4 14. "FS1,Fault status" "0: MCS1 field captured in any state different from..,1: MCS field captured in FAULT state." newline hexmask.long.byte 0x4 8.--11. 1. "MCS1,State of MC modules" newline bitfld.long 0x4 7. "VL0,Valid" "0: MCS0 FS0 fields are not significant.,1: MCS0 FS0 fields are significant." newline bitfld.long 0x4 6. "FS0,Fault status" "0: MCS0 field captured in any state different from..,1: MCS0 field captured in FAULT state." newline hexmask.long.byte 0x4 0.--3. 1. "MCS0,State of MC modules" group.long 0x11F0++0xB line.long 0x0 "TRANS_UNLOCK,FCCU2 Transient register" hexmask.long 0x0 0.--31. 1. "TRANSKEY,Transition Unlocking Key value" line.long 0x4 "PERMNT_LOCK,FCCU2 Permanent Lock register" hexmask.long 0x4 0.--31. 1. "PERMNTKEY,Transition Locking Key value" line.long 0x8 "DELTA_T,FCCU2 Delta T register" hexmask.long.word 0x8 16.--29. 1. "T_TRG,IRQ/DMA trigger time" newline hexmask.long.word 0x8 0.--15. 1. "DELTA_T_VAL,Value of Delta_T (in microseconds)" group.long 0x1200++0x3 line.long 0x0 "RF_TO,FCCU2 RF Timeout register" hexmask.long.tbyte 0x0 0.--19. 1. "ALARM_TO,Recoverable fault global Alarm Timeout" rgroup.long 0x1300++0xF line.long 0x0 "ALARM_TMR0,FCCU2 Alarm Timer Read register 0" bitfld.long 0x0 31. "VLD_RUN,Valid Run" "0: Alarm timer n is not active.,1: Alarm timer n is active." newline hexmask.long.tbyte 0x0 0.--19. 1. "ALARM_TMR_VAL,Alarm n timer value" line.long 0x4 "ALARM_TMR1,FCCU2 Alarm Timer Read register 1" bitfld.long 0x4 31. "VLD_RUN,Valid Run" "0: Alarm timer n is not active.,1: Alarm timer n is active." newline hexmask.long.tbyte 0x4 0.--19. 1. "ALARM_TMR_VAL,Alarm n timer value" line.long 0x8 "ALARM_TMR2,FCCU2 Alarm Timer Read register 2" bitfld.long 0x8 31. "VLD_RUN,Valid Run" "0: Alarm timer n is not active.,1: Alarm timer n is active." newline hexmask.long.tbyte 0x8 0.--19. 1. "ALARM_TMR_VAL,Alarm n timer value" line.long 0xC "ALARM_TMR3,FCCU2 Alarm Timer Read register 3" bitfld.long 0xC 31. "VLD_RUN,Valid Run" "0: Alarm timer n is not active.,1: Alarm timer n is active." newline hexmask.long.tbyte 0xC 0.--19. 1. "ALARM_TMR_VAL,Alarm n timer value" rgroup.long 0x1330++0xF line.long 0x0 "ALARM_TMR_INDX0,FCCU2 Alarm Timer Fault Channel Index Register 0" hexmask.long.word 0x0 0.--8. 1. "ALARM_FAULT_INDEX,Alarm n Fault Index" line.long 0x4 "ALARM_TMR_INDX1,FCCU2 Alarm Timer Fault Channel Index Register 1" hexmask.long.word 0x4 0.--8. 1. "ALARM_FAULT_INDEX,Alarm n Fault Index" line.long 0x8 "ALARM_TMR_INDX2,FCCU2 Alarm Timer Fault Channel Index Register 2" hexmask.long.word 0x8 0.--8. 1. "ALARM_FAULT_INDEX,Alarm n Fault Index" line.long 0xC "ALARM_TMR_INDX3,FCCU2 Alarm Timer Fault Channel Index Register 3" hexmask.long.word 0xC 0.--8. 1. "ALARM_FAULT_INDEX,Alarm n Fault Index" group.long 0x1360++0x1F line.long 0x0 "SCP_CONF0_EOUT0,FCCU2 SCP Configuration 0 EOUTn register" bitfld.long 0x0 31. "PRE31,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 30. "PRE30,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 29. "PRE29,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 28. "PRE28,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 27. "PRE27,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 26. "PRE26,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 25. "PRE25,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 24. "PRE24,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 23. "PRE23,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 22. "PRE22,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 21. "PRE21,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 20. "PRE20,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 19. "PRE19,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 18. "PRE18,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 17. "PRE17,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 16. "PRE16,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 15. "PRE15,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 14. "PRE14,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 13. "PRE13,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 12. "PRE12,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 11. "PRE11,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 10. "PRE10,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 9. "PRE9,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 8. "PRE8,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 7. "PRE7,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 6. "PRE6,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 5. "PRE5,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 4. "PRE4,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 3. "PRE3,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 2. "PRE2,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 1. "PRE1,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x0 0. "PRE0,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" line.long 0x4 "SCP_CONF1_EOUT0,FCCU2 SCP Configuration 1 EOUTn register" bitfld.long 0x4 31. "PRE63,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 30. "PRE62,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 29. "PRE61,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 28. "PRE60,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 27. "PRE59,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 26. "PRE58,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 25. "PRE57,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 24. "PRE56,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 23. "PRE55,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 22. "PRE54,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 21. "PRE53,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 20. "PRE52,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 19. "PRE51,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 18. "PRE50,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 17. "PRE49,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 16. "PRE48,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 15. "PRE47,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 14. "PRE46,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 13. "PRE45,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 12. "PRE44,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 11. "PRE43,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 10. "PRE42,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 9. "PRE41,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 8. "PRE40,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 7. "PRE39,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 6. "PRE38,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 5. "PRE37,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 4. "PRE36,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 3. "PRE35,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 2. "PRE34,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 1. "PRE33,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x4 0. "PRE32,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" line.long 0x8 "SCP_CONF0_EOUT1,FCCU2 SCP Configuration 0 EOUTn register" bitfld.long 0x8 31. "PRE31,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 30. "PRE30,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 29. "PRE29,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 28. "PRE28,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 27. "PRE27,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 26. "PRE26,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 25. "PRE25,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 24. "PRE24,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 23. "PRE23,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 22. "PRE22,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 21. "PRE21,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 20. "PRE20,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 19. "PRE19,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 18. "PRE18,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 17. "PRE17,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 16. "PRE16,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 15. "PRE15,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 14. "PRE14,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 13. "PRE13,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 12. "PRE12,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 11. "PRE11,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 10. "PRE10,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 9. "PRE9,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 8. "PRE8,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 7. "PRE7,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 6. "PRE6,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 5. "PRE5,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 4. "PRE4,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 3. "PRE3,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 2. "PRE2,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 1. "PRE1,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x8 0. "PRE0,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" line.long 0xC "SCP_CONF1_EOUT1,FCCU2 SCP Configuration 1 EOUTn register" bitfld.long 0xC 31. "PRE63,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 30. "PRE62,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 29. "PRE61,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 28. "PRE60,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 27. "PRE59,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 26. "PRE58,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 25. "PRE57,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 24. "PRE56,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 23. "PRE55,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 22. "PRE54,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 21. "PRE53,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 20. "PRE52,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 19. "PRE51,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 18. "PRE50,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 17. "PRE49,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 16. "PRE48,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 15. "PRE47,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 14. "PRE46,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 13. "PRE45,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 12. "PRE44,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 11. "PRE43,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 10. "PRE42,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 9. "PRE41,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 8. "PRE40,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 7. "PRE39,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 6. "PRE38,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 5. "PRE37,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 4. "PRE36,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 3. "PRE35,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 2. "PRE34,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 1. "PRE33,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0xC 0. "PRE32,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" line.long 0x10 "SCP_CONF0_EOUT2,FCCU2 SCP Configuration 0 EOUTn register" bitfld.long 0x10 31. "PRE31,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 30. "PRE30,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 29. "PRE29,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 28. "PRE28,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 27. "PRE27,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 26. "PRE26,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 25. "PRE25,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 24. "PRE24,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 23. "PRE23,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 22. "PRE22,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 21. "PRE21,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 20. "PRE20,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 19. "PRE19,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 18. "PRE18,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 17. "PRE17,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 16. "PRE16,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 15. "PRE15,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 14. "PRE14,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 13. "PRE13,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 12. "PRE12,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 11. "PRE11,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 10. "PRE10,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 9. "PRE9,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 8. "PRE8,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 7. "PRE7,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 6. "PRE6,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 5. "PRE5,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 4. "PRE4,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 3. "PRE3,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 2. "PRE2,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 1. "PRE1,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x10 0. "PRE0,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" line.long 0x14 "SCP_CONF1_EOUT2,FCCU2 SCP Configuration 1 EOUTn register" bitfld.long 0x14 31. "PRE63,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 30. "PRE62,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 29. "PRE61,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 28. "PRE60,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 27. "PRE59,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 26. "PRE58,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 25. "PRE57,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 24. "PRE56,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 23. "PRE55,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 22. "PRE54,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 21. "PRE53,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 20. "PRE52,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 19. "PRE51,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 18. "PRE50,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 17. "PRE49,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 16. "PRE48,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 15. "PRE47,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 14. "PRE46,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 13. "PRE45,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 12. "PRE44,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 11. "PRE43,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 10. "PRE42,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 9. "PRE41,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 8. "PRE40,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 7. "PRE39,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 6. "PRE38,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 5. "PRE37,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 4. "PRE36,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 3. "PRE35,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 2. "PRE34,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 1. "PRE33,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x14 0. "PRE32,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" line.long 0x18 "SCP_CONF0_EOUT3,FCCU2 SCP Configuration 0 EOUTn register" bitfld.long 0x18 31. "PRE31,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 30. "PRE30,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 29. "PRE29,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 28. "PRE28,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 27. "PRE27,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 26. "PRE26,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 25. "PRE25,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 24. "PRE24,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 23. "PRE23,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 22. "PRE22,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 21. "PRE21,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 20. "PRE20,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 19. "PRE19,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 18. "PRE18,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 17. "PRE17,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 16. "PRE16,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 15. "PRE15,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 14. "PRE14,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 13. "PRE13,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 12. "PRE12,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 11. "PRE11,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 10. "PRE10,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 9. "PRE9,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 8. "PRE8,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 7. "PRE7,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 6. "PRE6,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 5. "PRE5,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 4. "PRE4,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 3. "PRE3,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 2. "PRE2,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 1. "PRE1,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x18 0. "PRE0,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" line.long 0x1C "SCP_CONF1_EOUT3,FCCU2 SCP Configuration 1 EOUTn register" bitfld.long 0x1C 31. "PRE63,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 30. "PRE62,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 29. "PRE61,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 28. "PRE60,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 27. "PRE59,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 26. "PRE58,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 25. "PRE57,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 24. "PRE56,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 23. "PRE55,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 22. "PRE54,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 21. "PRE53,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 20. "PRE52,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 19. "PRE51,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 18. "PRE50,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 17. "PRE49,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 16. "PRE48,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 15. "PRE47,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 14. "PRE46,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 13. "PRE45,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 12. "PRE44,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 11. "PRE43,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 10. "PRE42,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 9. "PRE41,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 8. "PRE40,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 7. "PRE39,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 6. "PRE38,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 5. "PRE37,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 4. "PRE36,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 3. "PRE35,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 2. "PRE34,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 1. "PRE33,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" newline bitfld.long 0x1C 0. "PRE32,Pad Reset Enable" "0: Do not reset the pad i,1: Reset pad i" group.long 0x1500++0xFF line.long 0x0 "REACT_CNFG0,FCCU2 Reaction Configuration register 0" bitfld.long 0x0 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x0 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x0 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x0 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x0 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x0 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x0 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x0 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x0 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x0 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x0 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x0 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x0 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x4 "REACT_CNFG1,FCCU2 Reaction Configuration register 1" bitfld.long 0x4 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x4 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x4 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x4 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x4 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x4 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x4 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x4 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x4 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x4 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x4 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x4 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x4 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x8 "REACT_CNFG2,FCCU2 Reaction Configuration register 2" bitfld.long 0x8 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x8 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x8 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x8 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x8 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x8 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x8 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x8 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x8 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x8 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x8 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x8 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x8 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xC "REACT_CNFG3,FCCU2 Reaction Configuration register 3" bitfld.long 0xC 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xC 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xC 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xC 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xC 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xC 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xC 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xC 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xC 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xC 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xC 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xC 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xC 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x10 "REACT_CNFG4,FCCU2 Reaction Configuration register 4" bitfld.long 0x10 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x10 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x10 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x10 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x10 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x10 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x10 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x10 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x10 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x10 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x10 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x10 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x10 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x14 "REACT_CNFG5,FCCU2 Reaction Configuration register 5" bitfld.long 0x14 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x14 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x14 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x14 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x14 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x14 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x14 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x14 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x14 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x14 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x14 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x14 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x14 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x18 "REACT_CNFG6,FCCU2 Reaction Configuration register 6" bitfld.long 0x18 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x18 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x18 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x18 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x18 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x18 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x18 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x18 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x18 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x18 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x18 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x18 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x18 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x1C "REACT_CNFG7,FCCU2 Reaction Configuration register 7" bitfld.long 0x1C 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x1C 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x1C 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x1C 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x1C 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x1C 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x1C 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x1C 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x1C 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x1C 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x1C 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x1C 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x1C 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x20 "REACT_CNFG8,FCCU2 Reaction Configuration register 8" bitfld.long 0x20 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x20 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x20 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x20 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x20 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x20 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x20 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x20 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x20 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x20 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x20 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x20 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x20 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x24 "REACT_CNFG9,FCCU2 Reaction Configuration register 9" bitfld.long 0x24 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x24 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x24 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x24 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x24 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x24 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x24 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x24 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x24 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x24 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x24 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x24 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x24 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x28 "REACT_CNFG10,FCCU2 Reaction Configuration register 10" bitfld.long 0x28 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x28 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x28 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x28 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x28 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x28 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x28 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x28 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x28 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x28 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x28 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x28 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x28 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x2C "REACT_CNFG11,FCCU2 Reaction Configuration register 11" bitfld.long 0x2C 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x2C 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x2C 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x2C 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x2C 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x2C 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x2C 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x2C 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x2C 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x2C 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x2C 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x2C 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x2C 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x30 "REACT_CNFG12,FCCU2 Reaction Configuration register 12" bitfld.long 0x30 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x30 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x30 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x30 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x30 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x30 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x30 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x30 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x30 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x30 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x30 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x30 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x30 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x34 "REACT_CNFG13,FCCU2 Reaction Configuration register 13" bitfld.long 0x34 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x34 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x34 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x34 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x34 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x34 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x34 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x34 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x34 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x34 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x34 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x34 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x34 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x38 "REACT_CNFG14,FCCU2 Reaction Configuration register 14" bitfld.long 0x38 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x38 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x38 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x38 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x38 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x38 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x38 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x38 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x38 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x38 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x38 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x38 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x38 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x3C "REACT_CNFG15,FCCU2 Reaction Configuration register 15" bitfld.long 0x3C 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x3C 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x3C 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x3C 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x3C 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x3C 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x3C 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x3C 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x3C 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x3C 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x3C 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x3C 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x3C 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x40 "REACT_CNFG16,FCCU2 Reaction Configuration register 16" bitfld.long 0x40 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x40 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x40 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x40 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x40 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x40 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x40 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x40 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x40 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x40 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x40 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x40 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x40 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x44 "REACT_CNFG17,FCCU2 Reaction Configuration register 17" bitfld.long 0x44 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x44 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x44 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x44 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x44 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x44 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x44 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x44 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x44 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x44 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x44 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x44 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x44 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x48 "REACT_CNFG18,FCCU2 Reaction Configuration register 18" bitfld.long 0x48 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x48 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x48 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x48 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x48 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x48 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x48 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x48 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x48 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x48 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x48 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x48 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x48 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x4C "REACT_CNFG19,FCCU2 Reaction Configuration register 19" bitfld.long 0x4C 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x4C 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x4C 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x4C 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x4C 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x4C 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x4C 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x4C 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x4C 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x4C 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x4C 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x4C 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x4C 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x50 "REACT_CNFG20,FCCU2 Reaction Configuration register 20" bitfld.long 0x50 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x50 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x50 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x50 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x50 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x50 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x50 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x50 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x50 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x50 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x50 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x50 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x50 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x54 "REACT_CNFG21,FCCU2 Reaction Configuration register 21" bitfld.long 0x54 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x54 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x54 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x54 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x54 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x54 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x54 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x54 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x54 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x54 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x54 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x54 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x54 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x58 "REACT_CNFG22,FCCU2 Reaction Configuration register 22" bitfld.long 0x58 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x58 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x58 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x58 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x58 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x58 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x58 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x58 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x58 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x58 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x58 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x58 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x58 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x5C "REACT_CNFG23,FCCU2 Reaction Configuration register 23" bitfld.long 0x5C 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x5C 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x5C 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x5C 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x5C 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x5C 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x5C 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x5C 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x5C 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x5C 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x5C 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x5C 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x5C 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x60 "REACT_CNFG24,FCCU2 Reaction Configuration register 24" bitfld.long 0x60 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x60 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x60 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x60 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x60 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x60 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x60 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x60 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x60 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x60 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x60 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x60 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x60 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x64 "REACT_CNFG25,FCCU2 Reaction Configuration register 25" bitfld.long 0x64 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x64 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x64 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x64 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x64 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x64 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x64 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x64 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x64 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x64 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x64 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x64 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x64 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x68 "REACT_CNFG26,FCCU2 Reaction Configuration register 26" bitfld.long 0x68 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x68 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x68 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x68 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x68 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x68 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x68 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x68 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x68 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x68 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x68 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x68 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x68 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x6C "REACT_CNFG27,FCCU2 Reaction Configuration register 27" bitfld.long 0x6C 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x6C 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x6C 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x6C 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x6C 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x6C 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x6C 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x6C 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x6C 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x6C 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x6C 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x6C 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x6C 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x70 "REACT_CNFG28,FCCU2 Reaction Configuration register 28" bitfld.long 0x70 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x70 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x70 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x70 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x70 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x70 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x70 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x70 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x70 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x70 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x70 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x70 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x70 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x74 "REACT_CNFG29,FCCU2 Reaction Configuration register 29" bitfld.long 0x74 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x74 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x74 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x74 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x74 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x74 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x74 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x74 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x74 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x74 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x74 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x74 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x74 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x78 "REACT_CNFG30,FCCU2 Reaction Configuration register 30" bitfld.long 0x78 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x78 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x78 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x78 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x78 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x78 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x78 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x78 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x78 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x78 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x78 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x78 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x78 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x7C "REACT_CNFG31,FCCU2 Reaction Configuration register 31" bitfld.long 0x7C 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x7C 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x7C 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x7C 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x7C 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x7C 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x7C 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x7C 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x7C 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x7C 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x7C 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x7C 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x7C 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x80 "REACT_CNFG32,FCCU2 Reaction Configuration register 32" bitfld.long 0x80 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x80 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x80 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x80 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x80 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x80 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x80 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x80 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x80 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x80 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x80 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x80 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x80 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x84 "REACT_CNFG33,FCCU2 Reaction Configuration register 33" bitfld.long 0x84 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x84 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x84 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x84 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x84 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x84 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x84 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x84 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x84 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x84 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x84 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x84 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x84 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x88 "REACT_CNFG34,FCCU2 Reaction Configuration register 34" bitfld.long 0x88 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x88 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x88 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x88 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x88 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x88 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x88 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x88 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x88 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x88 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x88 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x88 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x88 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x8C "REACT_CNFG35,FCCU2 Reaction Configuration register 35" bitfld.long 0x8C 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x8C 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x8C 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x8C 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x8C 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x8C 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x8C 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x8C 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x8C 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x8C 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x8C 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x8C 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x8C 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x90 "REACT_CNFG36,FCCU2 Reaction Configuration register 36" bitfld.long 0x90 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x90 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x90 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x90 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x90 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x90 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x90 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x90 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x90 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x90 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x90 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x90 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x90 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x94 "REACT_CNFG37,FCCU2 Reaction Configuration register 37" bitfld.long 0x94 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x94 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x94 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x94 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x94 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x94 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x94 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x94 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x94 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x94 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x94 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x94 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x94 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x98 "REACT_CNFG38,FCCU2 Reaction Configuration register 38" bitfld.long 0x98 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x98 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x98 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x98 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x98 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x98 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x98 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x98 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x98 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x98 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x98 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x98 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x98 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0x9C "REACT_CNFG39,FCCU2 Reaction Configuration register 39" bitfld.long 0x9C 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0x9C 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0x9C 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0x9C 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0x9C 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0x9C 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0x9C 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0x9C 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0x9C 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0x9C 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0x9C 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0x9C 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0x9C 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xA0 "REACT_CNFG40,FCCU2 Reaction Configuration register 40" bitfld.long 0xA0 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xA0 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xA0 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xA0 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xA0 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xA0 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xA0 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xA0 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xA0 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xA0 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xA0 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xA0 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xA0 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xA4 "REACT_CNFG41,FCCU2 Reaction Configuration register 41" bitfld.long 0xA4 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xA4 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xA4 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xA4 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xA4 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xA4 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xA4 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xA4 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xA4 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xA4 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xA4 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xA4 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xA4 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xA8 "REACT_CNFG42,FCCU2 Reaction Configuration register 42" bitfld.long 0xA8 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xA8 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xA8 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xA8 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xA8 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xA8 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xA8 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xA8 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xA8 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xA8 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xA8 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xA8 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xA8 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xAC "REACT_CNFG43,FCCU2 Reaction Configuration register 43" bitfld.long 0xAC 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xAC 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xAC 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xAC 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xAC 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xAC 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xAC 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xAC 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xAC 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xAC 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xAC 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xAC 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xAC 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xB0 "REACT_CNFG44,FCCU2 Reaction Configuration register 44" bitfld.long 0xB0 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xB0 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xB0 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xB0 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xB0 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xB0 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xB0 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xB0 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xB0 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xB0 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xB0 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xB0 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xB0 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xB4 "REACT_CNFG45,FCCU2 Reaction Configuration register 45" bitfld.long 0xB4 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xB4 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xB4 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xB4 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xB4 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xB4 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xB4 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xB4 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xB4 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xB4 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xB4 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xB4 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xB4 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xB8 "REACT_CNFG46,FCCU2 Reaction Configuration register 46" bitfld.long 0xB8 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xB8 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xB8 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xB8 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xB8 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xB8 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xB8 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xB8 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xB8 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xB8 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xB8 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xB8 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xB8 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xBC "REACT_CNFG47,FCCU2 Reaction Configuration register 47" bitfld.long 0xBC 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xBC 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xBC 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xBC 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xBC 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xBC 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xBC 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xBC 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xBC 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xBC 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xBC 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xBC 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xBC 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xC0 "REACT_CNFG48,FCCU2 Reaction Configuration register 48" bitfld.long 0xC0 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xC0 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xC0 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xC0 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xC0 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xC0 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xC0 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xC0 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xC0 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xC0 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xC0 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xC0 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xC0 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xC4 "REACT_CNFG49,FCCU2 Reaction Configuration register 49" bitfld.long 0xC4 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xC4 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xC4 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xC4 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xC4 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xC4 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xC4 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xC4 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xC4 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xC4 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xC4 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xC4 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xC4 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xC8 "REACT_CNFG50,FCCU2 Reaction Configuration register 50" bitfld.long 0xC8 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xC8 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xC8 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xC8 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xC8 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xC8 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xC8 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xC8 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xC8 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xC8 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xC8 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xC8 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xC8 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xCC "REACT_CNFG51,FCCU2 Reaction Configuration register 51" bitfld.long 0xCC 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xCC 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xCC 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xCC 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xCC 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xCC 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xCC 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xCC 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xCC 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xCC 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xCC 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xCC 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xCC 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xD0 "REACT_CNFG52,FCCU2 Reaction Configuration register 52" bitfld.long 0xD0 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xD0 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xD0 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xD0 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xD0 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xD0 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xD0 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xD0 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xD0 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xD0 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xD0 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xD0 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xD0 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xD4 "REACT_CNFG53,FCCU2 Reaction Configuration register 53" bitfld.long 0xD4 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xD4 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xD4 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xD4 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xD4 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xD4 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xD4 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xD4 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xD4 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xD4 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xD4 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xD4 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xD4 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xD8 "REACT_CNFG54,FCCU2 Reaction Configuration register 54" bitfld.long 0xD8 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xD8 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xD8 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xD8 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xD8 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xD8 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xD8 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xD8 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xD8 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xD8 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xD8 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xD8 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xD8 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xDC "REACT_CNFG55,FCCU2 Reaction Configuration register 55" bitfld.long 0xDC 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xDC 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xDC 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xDC 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xDC 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xDC 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xDC 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xDC 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xDC 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xDC 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xDC 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xDC 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xDC 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xE0 "REACT_CNFG56,FCCU2 Reaction Configuration register 56" bitfld.long 0xE0 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xE0 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xE0 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xE0 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xE0 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xE0 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xE0 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xE0 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xE0 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xE0 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xE0 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xE0 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xE0 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xE4 "REACT_CNFG57,FCCU2 Reaction Configuration register 57" bitfld.long 0xE4 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xE4 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xE4 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xE4 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xE4 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xE4 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xE4 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xE4 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xE4 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xE4 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xE4 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xE4 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xE4 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xE8 "REACT_CNFG58,FCCU2 Reaction Configuration register 58" bitfld.long 0xE8 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xE8 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xE8 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xE8 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xE8 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xE8 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xE8 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xE8 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xE8 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xE8 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xE8 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xE8 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xE8 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xEC "REACT_CNFG59,FCCU2 Reaction Configuration register 59" bitfld.long 0xEC 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xEC 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xEC 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xEC 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xEC 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xEC 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xEC 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xEC 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xEC 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xEC 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xEC 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xEC 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xEC 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xF0 "REACT_CNFG60,FCCU2 Reaction Configuration register 60" bitfld.long 0xF0 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xF0 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xF0 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xF0 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xF0 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xF0 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xF0 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xF0 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xF0 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xF0 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xF0 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xF0 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xF0 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xF4 "REACT_CNFG61,FCCU2 Reaction Configuration register 61" bitfld.long 0xF4 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xF4 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xF4 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xF4 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xF4 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xF4 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xF4 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xF4 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xF4 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xF4 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xF4 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xF4 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xF4 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xF8 "REACT_CNFG62,FCCU2 Reaction Configuration register 62" bitfld.long 0xF8 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xF8 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xF8 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xF8 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xF8 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xF8 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xF8 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xF8 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xF8 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xF8 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xF8 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xF8 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xF8 0.--3. 1. "EOUT_EN,The EOUT pin enabled" line.long 0xFC "REACT_CNFG63,FCCU2 Reaction Configuration register 63" bitfld.long 0xFC 31. "HSM,HSM interrupt enable corresponds to index 8 of the reaction that is FEI/VFEI/ALARM[8] activated." "0: No IRQ to HSM,1: IRQ sent to HSM" newline bitfld.long 0xFC 30. "DME,DME corresponds to index 7 of the reaction that is FEI/VFEI/ALARM[7] activated." "0: No FEI IRQ to DME,1: FEI routed to DME also if enabled via.." newline bitfld.long 0xFC 29. "DSPH,DSPH corresponds to index 6 of the reaction that is FEI/VFEI/ALARM[6] activated." "0: No FEI/IRQ to DSPH,1: FEI routed to DSPH if enabled (via.." newline bitfld.long 0xFC 21. "CLS2_CPU1,Cluster 2 CPU0 corresponds to index 5 of the reaction that is FEI/VFEI/ALARM[5] activated." "0: CLS2 CPU1 does not get the internal reaction(s).,1: CLS2 CPU1 gets the internal reaction(s)." newline bitfld.long 0xFC 20. "CLS2_CPU0,Cluster 2 CPU0 corresponds to index 4 of the reaction that is FEI/VFEI/ALARM[4] activated." "0: CLS2 CPU0 does not get the internal reaction(s).,1: CLS2 CPU0 gets the internal reaction(s)." newline bitfld.long 0xFC 19. "CLS1_CPU1,Cluster 1 CPU1 corresponds to index 3 of the reaction that is FEI/VFEI/ALARM[3] activated." "0: CLS1 CPU1 does not get the internal reaction(s).,1: CLS1 CPU1 gets the internal reaction(s)." newline bitfld.long 0xFC 18. "CLS1_CPU0,Cluster 1 CPU0 corresponds to index 2 of the reaction that is FEI/VFEI/ALARM[2] activated." "0: CLS1 CPU0 does not get the internal reaction(s).,1: CLS1 CPU0 gets the internal reaction(s)." newline bitfld.long 0xFC 17. "CLS0_CPU1,Cluster 0 CPU1 corresponds to index 1 of the reaction that is FEI/VFEI/ALARM[1] activated." "0: CLS0 CPU1 does not get the internal reaction(s).,1: CLS0 CPU1 gets the internal reaction(s)." newline bitfld.long 0xFC 16. "CLS0_CPU0,Cluster 0 CPU0 corresponds to index 0 of the reaction that is FEI/VFEI/ALARM[0] activated." "0: CLS0 CPU0 does not get the internal reaction(s).,1: CLS0 CPU0 gets the internal reaction(s)." newline bitfld.long 0xFC 14.--15. "RF_ALTO_EN,Recoverable Fault Alarm Timeout Enable" "0: FCCU2 moves directly to ALARM state on..,1: FCCU2 stays in NORMAL state on occurrence of RF..,2: FCCU2 stays in NORMAL state on occurrence of RF..,3: FCCU2 moves to FAULT state on occurrence of RF" newline bitfld.long 0xFC 9.--11. "INT_REACT_TYPE,Internal reaction type" "0: No reaction / Reserved,1: Debug request,2: Fault Event Interrupt (FEI) sent according to..,3: Virtual Fault Event Interrupt (VFEI) sent..,4: No reaction / Reserved,5: Long functional reset,6: Safe mode request,7: Short functional reset" newline bitfld.long 0xFC 8. "IRQ_EN,Alarm interrupt enable" "0: Disable,1: Enable. Interrupt is routed according to the.." newline hexmask.long.byte 0xFC 0.--3. 1. "EOUT_EN,The EOUT pin enabled" tree.end tree "FIREWALL (FlexNoC Firewall)" base ad:0x0 tree "FIREWALL_CONFIG" tree "AESLIGHT1_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B630100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "AESLIGHT2_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B640100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "AESLIGHT3_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B650100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "AIPS0_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B660100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "AIPS1_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B670100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "AIPS2_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B680100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "AIPS3_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B690100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "AIPS4_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B6A0100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "DAP_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B6B0100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "DFA_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B790100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "DME_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B6C0100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "DSPH_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B6D0100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "FIREWALL_CONFIG_ADR" base ad:0x7B620100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "GTM_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B740100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "HSM_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B750100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "KITE0_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B770100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "KITE1_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B7A0100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "KITE2_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B7C0100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "NVM_WR_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B760100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "OCT_SPI_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B720100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "PCIE0_CFG_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B6E0100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "PCIE0_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B600100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "PCIE1_CFG_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B6F0100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "PCIE1_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B610100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "SDMMC_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B730100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "SYSRAM0_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B700100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "SYSRAM1_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B710100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "TMC0_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B780100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "TMC1_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B7B0100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree "TMC2_FIREWALL_CORE_FIREWALL_CONFIG_ADR" base ad:0x7B7D0100 group.long 0x0++0xB line.long 0x0 "FW_CONFIG_REG,FW Configuration Register" bitfld.long 0x0 0. "FW_EN,To enable the Firewall access check this bit needs to programmed to 1." "0,1" line.long 0x4 "FW_EL2_CONFIG_REG,EL2 Configuration Register" bitfld.long 0x4 0. "EL2_EN,To enable the EL2 check need to program the bit to 1." "0,1" line.long 0x8 "FW_EL1_CONFIG_REG,EL1 Configuration Register" bitfld.long 0x8 0. "EL1_EN,To enable the EL1 check need to program the bit to 1." "0,1" tree.end tree.end tree "FIREWALL_EL1" tree "AESLIGHT1_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B631000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "AESLIGHT2_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B641000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "AESLIGHT3_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B651000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "AIPS0_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B661000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "AIPS1_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B671000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "AIPS2_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B681000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "AIPS3_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B691000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "AIPS4_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B6A1000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "DAP_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B6B1000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "DFA_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B791000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x10++0xB line.long 0x0 "EL1_CONF_REG_1,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_1,EL1 Region 1 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_1,EL1 Region 1 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "DME_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B6C1000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x10++0xB line.long 0x0 "EL1_CONF_REG_1,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_1,EL1 Region 1 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_1,EL1 Region 1 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "DSPH_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B6D1000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x10++0xB line.long 0x0 "EL1_CONF_REG_1,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_1,EL1 Region 1 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_1,EL1 Region 1 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "FIREWALL_EL1_ADR" base ad:0x7B621000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "GTM_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B741000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x10++0xB line.long 0x0 "EL1_CONF_REG_1,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_1,EL1 Region 1 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_1,EL1 Region 1 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x20++0xB line.long 0x0 "EL1_CONF_REG_2,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_2,EL1 Region 2 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_2,EL1 Region 2 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x30++0xB line.long 0x0 "EL1_CONF_REG_3,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_3,EL1 Region 3 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_3,EL1 Region 3 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "HSM_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B751000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x10++0xB line.long 0x0 "EL1_CONF_REG_1,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_1,EL1 Region 1 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_1,EL1 Region 1 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "KITE0_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B771000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x10++0xB line.long 0x0 "EL1_CONF_REG_1,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_1,EL1 Region 1 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_1,EL1 Region 1 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x20++0xB line.long 0x0 "EL1_CONF_REG_2,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_2,EL1 Region 2 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_2,EL1 Region 2 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x30++0xB line.long 0x0 "EL1_CONF_REG_3,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_3,EL1 Region 3 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_3,EL1 Region 3 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x40++0xB line.long 0x0 "EL1_CONF_REG_4,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_4,EL1 Region 4 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_4,EL1 Region 4 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x50++0xB line.long 0x0 "EL1_CONF_REG_5,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_5,EL1 Region 5 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_5,EL1 Region 5 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x60++0xB line.long 0x0 "EL1_CONF_REG_6,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_6,EL1 Region 6 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_6,EL1 Region 6 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x70++0xB line.long 0x0 "EL1_CONF_REG_7,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_7,EL1 Region 7 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_7,EL1 Region 7 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "KITE1_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B7A1000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x10++0xB line.long 0x0 "EL1_CONF_REG_1,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_1,EL1 Region 1 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_1,EL1 Region 1 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x20++0xB line.long 0x0 "EL1_CONF_REG_2,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_2,EL1 Region 2 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_2,EL1 Region 2 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x30++0xB line.long 0x0 "EL1_CONF_REG_3,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_3,EL1 Region 3 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_3,EL1 Region 3 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x40++0xB line.long 0x0 "EL1_CONF_REG_4,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_4,EL1 Region 4 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_4,EL1 Region 4 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x50++0xB line.long 0x0 "EL1_CONF_REG_5,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_5,EL1 Region 5 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_5,EL1 Region 5 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x60++0xB line.long 0x0 "EL1_CONF_REG_6,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_6,EL1 Region 6 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_6,EL1 Region 6 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x70++0xB line.long 0x0 "EL1_CONF_REG_7,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_7,EL1 Region 7 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_7,EL1 Region 7 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "KITE2_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B7C1000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x10++0xB line.long 0x0 "EL1_CONF_REG_1,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_1,EL1 Region 1 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_1,EL1 Region 1 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x20++0xB line.long 0x0 "EL1_CONF_REG_2,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_2,EL1 Region 2 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_2,EL1 Region 2 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x30++0xB line.long 0x0 "EL1_CONF_REG_3,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_3,EL1 Region 3 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_3,EL1 Region 3 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x40++0xB line.long 0x0 "EL1_CONF_REG_4,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_4,EL1 Region 4 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_4,EL1 Region 4 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x50++0xB line.long 0x0 "EL1_CONF_REG_5,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_5,EL1 Region 5 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_5,EL1 Region 5 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x60++0xB line.long 0x0 "EL1_CONF_REG_6,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_6,EL1 Region 6 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_6,EL1 Region 6 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x70++0xB line.long 0x0 "EL1_CONF_REG_7,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_7,EL1 Region 7 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_7,EL1 Region 7 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "NVM_WR_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B761000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x10++0xB line.long 0x0 "EL1_CONF_REG_1,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_1,EL1 Region 1 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_1,EL1 Region 1 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x20++0xB line.long 0x0 "EL1_CONF_REG_2,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_2,EL1 Region 2 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_2,EL1 Region 2 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x30++0xB line.long 0x0 "EL1_CONF_REG_3,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_3,EL1 Region 3 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_3,EL1 Region 3 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "OCT_SPI_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B721000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "PCIE0_CFG_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B6E1000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x10++0xB line.long 0x0 "EL1_CONF_REG_1,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_1,EL1 Region 1 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_1,EL1 Region 1 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x20++0xB line.long 0x0 "EL1_CONF_REG_2,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_2,EL1 Region 2 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_2,EL1 Region 2 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "PCIE0_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B601000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x10++0xB line.long 0x0 "EL1_CONF_REG_1,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_1,EL1 Region 1 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_1,EL1 Region 1 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x20++0xB line.long 0x0 "EL1_CONF_REG_2,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_2,EL1 Region 2 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_2,EL1 Region 2 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "PCIE1_CFG_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B6F1000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x10++0xB line.long 0x0 "EL1_CONF_REG_1,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_1,EL1 Region 1 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_1,EL1 Region 1 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x20++0xB line.long 0x0 "EL1_CONF_REG_2,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_2,EL1 Region 2 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_2,EL1 Region 2 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "PCIE1_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B611000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x10++0xB line.long 0x0 "EL1_CONF_REG_1,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_1,EL1 Region 1 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_1,EL1 Region 1 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x20++0xB line.long 0x0 "EL1_CONF_REG_2,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_2,EL1 Region 2 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_2,EL1 Region 2 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "SDMMC_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B731000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "SYSRAM0_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B701000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x10++0xB line.long 0x0 "EL1_CONF_REG_1,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_1,EL1 Region 1 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_1,EL1 Region 1 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x20++0xB line.long 0x0 "EL1_CONF_REG_2,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_2,EL1 Region 2 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_2,EL1 Region 2 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x30++0xB line.long 0x0 "EL1_CONF_REG_3,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_3,EL1 Region 3 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_3,EL1 Region 3 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x40++0xB line.long 0x0 "EL1_CONF_REG_4,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_4,EL1 Region 4 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_4,EL1 Region 4 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x50++0xB line.long 0x0 "EL1_CONF_REG_5,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_5,EL1 Region 5 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_5,EL1 Region 5 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x60++0xB line.long 0x0 "EL1_CONF_REG_6,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_6,EL1 Region 6 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_6,EL1 Region 6 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x70++0xB line.long 0x0 "EL1_CONF_REG_7,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_7,EL1 Region 7 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_7,EL1 Region 7 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "SYSRAM1_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B711000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x10++0xB line.long 0x0 "EL1_CONF_REG_1,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_1,EL1 Region 1 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_1,EL1 Region 1 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x20++0xB line.long 0x0 "EL1_CONF_REG_2,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_2,EL1 Region 2 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_2,EL1 Region 2 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x30++0xB line.long 0x0 "EL1_CONF_REG_3,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_3,EL1 Region 3 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_3,EL1 Region 3 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x40++0xB line.long 0x0 "EL1_CONF_REG_4,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_4,EL1 Region 4 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_4,EL1 Region 4 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x50++0xB line.long 0x0 "EL1_CONF_REG_5,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_5,EL1 Region 5 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_5,EL1 Region 5 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x60++0xB line.long 0x0 "EL1_CONF_REG_6,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_6,EL1 Region 6 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_6,EL1 Region 6 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x70++0xB line.long 0x0 "EL1_CONF_REG_7,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_7,EL1 Region 7 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_7,EL1 Region 7 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "TMC0_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B781000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x10++0xB line.long 0x0 "EL1_CONF_REG_1,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_1,EL1 Region 1 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_1,EL1 Region 1 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "TMC1_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B7B1000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x10++0xB line.long 0x0 "EL1_CONF_REG_1,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_1,EL1 Region 1 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_1,EL1 Region 1 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree "TMC2_FIREWALL_CORE_FIREWALL_EL1_ADR" base ad:0x7B7D1000 group.long 0x0++0xB line.long 0x0 "EL1_CONF_REG_0,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_0,EL1 Region 0 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_0,EL1 Region 0 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." group.long 0x10++0xB line.long 0x0 "EL1_CONF_REG_1,EL1 Configuration Register" bitfld.long 0x0 0. "EL1_VLD,To enable the EL1 region need to reset it while dynamically reprogramming region attributes." "0,1" line.long 0x4 "EL1_ADDR_START_1,EL1 Region 1 Start Address Register" hexmask.long 0x4 6.--31. 1. "EL1_ADDR_START,Defines [31:6] bits of start address bound for region." line.long 0x8 "EL1_ADDR_SIZE_1,EL1 Region 1 Address Size Register" hexmask.long 0x8 6.--31. 1. "EL1_ADDR_SIZE,Defines the address size [31:6] bits for region." tree.end tree.end tree "FIREWALL_EL1_ACC" tree "AESLIGHT1_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B631200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x7 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0xF line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "AESLIGHT2_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B641200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x7 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0xF line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "AESLIGHT3_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B651200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x7 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0xF line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "AIPS0_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B661200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x7 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x90++0x7 line.long 0x0 "EL1_MSTR_36_0,EL1 Region 0 Master 36 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_37_0,EL1 Region 0 Master 37 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0xF line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xF8++0x3 line.long 0x0 "EL1_MSTR_62_0,EL1 Region 0 Master 62 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "AIPS1_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B671200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x7 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x90++0x7 line.long 0x0 "EL1_MSTR_36_0,EL1 Region 0 Master 36 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_37_0,EL1 Region 0 Master 37 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0xF line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xF8++0x3 line.long 0x0 "EL1_MSTR_62_0,EL1 Region 0 Master 62 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "AIPS2_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B681200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x7 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x90++0x7 line.long 0x0 "EL1_MSTR_36_0,EL1 Region 0 Master 36 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_37_0,EL1 Region 0 Master 37 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0xF line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xF8++0x3 line.long 0x0 "EL1_MSTR_62_0,EL1 Region 0 Master 62 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "AIPS3_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B691200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x7 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x90++0x7 line.long 0x0 "EL1_MSTR_36_0,EL1 Region 0 Master 36 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_37_0,EL1 Region 0 Master 37 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0xF line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xF8++0x3 line.long 0x0 "EL1_MSTR_62_0,EL1 Region 0 Master 62 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "AIPS4_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B6A1200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x7 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x90++0x7 line.long 0x0 "EL1_MSTR_36_0,EL1 Region 0 Master 36 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_37_0,EL1 Region 0 Master 37 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0xF line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xF8++0x3 line.long 0x0 "EL1_MSTR_62_0,EL1 Region 0 Master 62 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "DAP_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B6B1200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x90++0x7 line.long 0x0 "EL1_MSTR_36_0,EL1 Region 0 Master 36 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_37_0,EL1 Region 0 Master 37 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0xF line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "DFA_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B791200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x7 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0xF line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x100++0x2F line.long 0x0 "EL1_MSTR_0_1,EL1 Region 1 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_1,EL1 Region 1 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_1,EL1 Region 1 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_1,EL1 Region 1 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_1,EL1 Region 1 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_1,EL1 Region 1 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_1,EL1 Region 1 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_1,EL1 Region 1 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_1,EL1 Region 1 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_1,EL1 Region 1 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_1,EL1 Region 1 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_1,EL1 Region 1 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x148++0x3 line.long 0x0 "EL1_MSTR_18_1,EL1 Region 1 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x158++0x3 line.long 0x0 "EL1_MSTR_22_1,EL1 Region 1 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x160++0x3 line.long 0x0 "EL1_MSTR_24_1,EL1 Region 1 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x180++0x7 line.long 0x0 "EL1_MSTR_32_1,EL1 Region 1 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_1,EL1 Region 1 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1E0++0xF line.long 0x0 "EL1_MSTR_56_1,EL1 Region 1 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_1,EL1 Region 1 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_1,EL1 Region 1 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_1,EL1 Region 1 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "DME_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B6C1200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x7 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0xF line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x100++0x2F line.long 0x0 "EL1_MSTR_0_1,EL1 Region 1 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_1,EL1 Region 1 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_1,EL1 Region 1 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_1,EL1 Region 1 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_1,EL1 Region 1 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_1,EL1 Region 1 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_1,EL1 Region 1 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_1,EL1 Region 1 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_1,EL1 Region 1 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_1,EL1 Region 1 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_1,EL1 Region 1 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_1,EL1 Region 1 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x158++0x3 line.long 0x0 "EL1_MSTR_22_1,EL1 Region 1 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x160++0x3 line.long 0x0 "EL1_MSTR_24_1,EL1 Region 1 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x180++0x7 line.long 0x0 "EL1_MSTR_32_1,EL1 Region 1 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_1,EL1 Region 1 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1E0++0xF line.long 0x0 "EL1_MSTR_56_1,EL1 Region 1 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_1,EL1 Region 1 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_1,EL1 Region 1 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_1,EL1 Region 1 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "DSPH_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B6D1200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x7 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x90++0x7 line.long 0x0 "EL1_MSTR_36_0,EL1 Region 0 Master 36 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_37_0,EL1 Region 0 Master 37 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0xF line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xF8++0x3 line.long 0x0 "EL1_MSTR_62_0,EL1 Region 0 Master 62 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x100++0x2F line.long 0x0 "EL1_MSTR_0_1,EL1 Region 1 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_1,EL1 Region 1 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_1,EL1 Region 1 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_1,EL1 Region 1 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_1,EL1 Region 1 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_1,EL1 Region 1 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_1,EL1 Region 1 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_1,EL1 Region 1 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_1,EL1 Region 1 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_1,EL1 Region 1 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_1,EL1 Region 1 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_1,EL1 Region 1 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x148++0x3 line.long 0x0 "EL1_MSTR_18_1,EL1 Region 1 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x160++0x3 line.long 0x0 "EL1_MSTR_24_1,EL1 Region 1 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x180++0x7 line.long 0x0 "EL1_MSTR_32_1,EL1 Region 1 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_1,EL1 Region 1 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x190++0x7 line.long 0x0 "EL1_MSTR_36_1,EL1 Region 1 Master 36 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_37_1,EL1 Region 1 Master 37 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1E0++0xF line.long 0x0 "EL1_MSTR_56_1,EL1 Region 1 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_1,EL1 Region 1 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_1,EL1 Region 1 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_1,EL1 Region 1 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1F8++0x3 line.long 0x0 "EL1_MSTR_62_1,EL1 Region 1 Master 62 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "FIREWALL_EL1_ACC_ADR" base ad:0x7B621200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x7 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0xF line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "GTM_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B741200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x7 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0xF line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x100++0x2F line.long 0x0 "EL1_MSTR_0_1,EL1 Region 1 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_1,EL1 Region 1 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_1,EL1 Region 1 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_1,EL1 Region 1 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_1,EL1 Region 1 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_1,EL1 Region 1 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_1,EL1 Region 1 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_1,EL1 Region 1 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_1,EL1 Region 1 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_1,EL1 Region 1 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_1,EL1 Region 1 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_1,EL1 Region 1 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x148++0x3 line.long 0x0 "EL1_MSTR_18_1,EL1 Region 1 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x158++0x3 line.long 0x0 "EL1_MSTR_22_1,EL1 Region 1 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x160++0x3 line.long 0x0 "EL1_MSTR_24_1,EL1 Region 1 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x180++0x7 line.long 0x0 "EL1_MSTR_32_1,EL1 Region 1 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_1,EL1 Region 1 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1E0++0xF line.long 0x0 "EL1_MSTR_56_1,EL1 Region 1 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_1,EL1 Region 1 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_1,EL1 Region 1 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_1,EL1 Region 1 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x200++0x2F line.long 0x0 "EL1_MSTR_0_2,EL1 Region 2 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_2,EL1 Region 2 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_2,EL1 Region 2 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_2,EL1 Region 2 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_2,EL1 Region 2 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_2,EL1 Region 2 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_2,EL1 Region 2 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_2,EL1 Region 2 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_2,EL1 Region 2 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_2,EL1 Region 2 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_2,EL1 Region 2 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_2,EL1 Region 2 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x248++0x3 line.long 0x0 "EL1_MSTR_18_2,EL1 Region 2 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x258++0x3 line.long 0x0 "EL1_MSTR_22_2,EL1 Region 2 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x260++0x3 line.long 0x0 "EL1_MSTR_24_2,EL1 Region 2 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x280++0x7 line.long 0x0 "EL1_MSTR_32_2,EL1 Region 2 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_2,EL1 Region 2 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x2E0++0xF line.long 0x0 "EL1_MSTR_56_2,EL1 Region 2 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_2,EL1 Region 2 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_2,EL1 Region 2 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_2,EL1 Region 2 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x300++0x2F line.long 0x0 "EL1_MSTR_0_3,EL1 Region 3 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_3,EL1 Region 3 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_3,EL1 Region 3 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_3,EL1 Region 3 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_3,EL1 Region 3 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_3,EL1 Region 3 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_3,EL1 Region 3 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_3,EL1 Region 3 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_3,EL1 Region 3 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_3,EL1 Region 3 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_3,EL1 Region 3 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_3,EL1 Region 3 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x348++0x3 line.long 0x0 "EL1_MSTR_18_3,EL1 Region 3 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x358++0x3 line.long 0x0 "EL1_MSTR_22_3,EL1 Region 3 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x360++0x3 line.long 0x0 "EL1_MSTR_24_3,EL1 Region 3 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x380++0x7 line.long 0x0 "EL1_MSTR_32_3,EL1 Region 3 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_3,EL1 Region 3 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x3E0++0xF line.long 0x0 "EL1_MSTR_56_3,EL1 Region 3 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_3,EL1 Region 3 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_3,EL1 Region 3 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_3,EL1 Region 3 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "HSM_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B751200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x7 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x9C++0x3 line.long 0x0 "EL1_MSTR_39_0,EL1 Region 0 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0xF line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x100++0x2F line.long 0x0 "EL1_MSTR_0_1,EL1 Region 1 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_1,EL1 Region 1 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_1,EL1 Region 1 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_1,EL1 Region 1 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_1,EL1 Region 1 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_1,EL1 Region 1 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_1,EL1 Region 1 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_1,EL1 Region 1 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_1,EL1 Region 1 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_1,EL1 Region 1 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_1,EL1 Region 1 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_1,EL1 Region 1 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x148++0x3 line.long 0x0 "EL1_MSTR_18_1,EL1 Region 1 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x158++0x3 line.long 0x0 "EL1_MSTR_22_1,EL1 Region 1 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x180++0x7 line.long 0x0 "EL1_MSTR_32_1,EL1 Region 1 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_1,EL1 Region 1 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x19C++0x3 line.long 0x0 "EL1_MSTR_39_1,EL1 Region 1 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1E0++0xF line.long 0x0 "EL1_MSTR_56_1,EL1 Region 1 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_1,EL1 Region 1 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_1,EL1 Region 1 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_1,EL1 Region 1 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "KITE0_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B771200 group.long 0x10++0x1F line.long 0x0 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x17 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_0,EL1 Region 0 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_0,EL1 Region 0 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_0,EL1 Region 0 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_0,EL1 Region 0 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x9C++0x3 line.long 0x0 "EL1_MSTR_39_0,EL1 Region 0 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xD0++0x7 line.long 0x0 "EL1_MSTR_52_0,EL1 Region 0 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_0,EL1 Region 0 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0x1F line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_0,EL1 Region 0 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_0,EL1 Region 0 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_0,EL1 Region 0 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_0,EL1 Region 0 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x110++0x1F line.long 0x0 "EL1_MSTR_4_1,EL1 Region 1 Master 4 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_5_1,EL1 Region 1 Master 5 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_6_1,EL1 Region 1 Master 6 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_7_1,EL1 Region 1 Master 7 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_8_1,EL1 Region 1 Master 8 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_9_1,EL1 Region 1 Master 9 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_10_1,EL1 Region 1 Master 10 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_11_1,EL1 Region 1 Master 11 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x148++0x3 line.long 0x0 "EL1_MSTR_18_1,EL1 Region 1 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x158++0x3 line.long 0x0 "EL1_MSTR_22_1,EL1 Region 1 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x160++0x3 line.long 0x0 "EL1_MSTR_24_1,EL1 Region 1 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x180++0x17 line.long 0x0 "EL1_MSTR_32_1,EL1 Region 1 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_1,EL1 Region 1 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_1,EL1 Region 1 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_1,EL1 Region 1 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_1,EL1 Region 1 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_1,EL1 Region 1 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x19C++0x3 line.long 0x0 "EL1_MSTR_39_1,EL1 Region 1 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1D0++0x7 line.long 0x0 "EL1_MSTR_52_1,EL1 Region 1 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_1,EL1 Region 1 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1E0++0x1F line.long 0x0 "EL1_MSTR_56_1,EL1 Region 1 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_1,EL1 Region 1 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_1,EL1 Region 1 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_1,EL1 Region 1 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_1,EL1 Region 1 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_1,EL1 Region 1 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_1,EL1 Region 1 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_1,EL1 Region 1 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x210++0x1F line.long 0x0 "EL1_MSTR_4_2,EL1 Region 2 Master 4 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_5_2,EL1 Region 2 Master 5 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_6_2,EL1 Region 2 Master 6 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_7_2,EL1 Region 2 Master 7 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_8_2,EL1 Region 2 Master 8 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_9_2,EL1 Region 2 Master 9 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_10_2,EL1 Region 2 Master 10 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_11_2,EL1 Region 2 Master 11 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x248++0x3 line.long 0x0 "EL1_MSTR_18_2,EL1 Region 2 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x258++0x3 line.long 0x0 "EL1_MSTR_22_2,EL1 Region 2 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x260++0x3 line.long 0x0 "EL1_MSTR_24_2,EL1 Region 2 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x280++0x17 line.long 0x0 "EL1_MSTR_32_2,EL1 Region 2 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_2,EL1 Region 2 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_2,EL1 Region 2 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_2,EL1 Region 2 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_2,EL1 Region 2 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_2,EL1 Region 2 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x29C++0x3 line.long 0x0 "EL1_MSTR_39_2,EL1 Region 2 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x2D0++0x7 line.long 0x0 "EL1_MSTR_52_2,EL1 Region 2 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_2,EL1 Region 2 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x2E0++0x1F line.long 0x0 "EL1_MSTR_56_2,EL1 Region 2 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_2,EL1 Region 2 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_2,EL1 Region 2 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_2,EL1 Region 2 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_2,EL1 Region 2 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_2,EL1 Region 2 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_2,EL1 Region 2 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_2,EL1 Region 2 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x310++0x1F line.long 0x0 "EL1_MSTR_4_3,EL1 Region 3 Master 4 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_5_3,EL1 Region 3 Master 5 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_6_3,EL1 Region 3 Master 6 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_7_3,EL1 Region 3 Master 7 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_8_3,EL1 Region 3 Master 8 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_9_3,EL1 Region 3 Master 9 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_10_3,EL1 Region 3 Master 10 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_11_3,EL1 Region 3 Master 11 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x348++0x3 line.long 0x0 "EL1_MSTR_18_3,EL1 Region 3 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x358++0x3 line.long 0x0 "EL1_MSTR_22_3,EL1 Region 3 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x360++0x3 line.long 0x0 "EL1_MSTR_24_3,EL1 Region 3 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x380++0x17 line.long 0x0 "EL1_MSTR_32_3,EL1 Region 3 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_3,EL1 Region 3 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_3,EL1 Region 3 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_3,EL1 Region 3 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_3,EL1 Region 3 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_3,EL1 Region 3 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x39C++0x3 line.long 0x0 "EL1_MSTR_39_3,EL1 Region 3 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x3D0++0x7 line.long 0x0 "EL1_MSTR_52_3,EL1 Region 3 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_3,EL1 Region 3 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x3E0++0x1F line.long 0x0 "EL1_MSTR_56_3,EL1 Region 3 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_3,EL1 Region 3 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_3,EL1 Region 3 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_3,EL1 Region 3 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_3,EL1 Region 3 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_3,EL1 Region 3 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_3,EL1 Region 3 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_3,EL1 Region 3 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x410++0x1F line.long 0x0 "EL1_MSTR_4_4,EL1 Region 4 Master 4 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_5_4,EL1 Region 4 Master 5 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_6_4,EL1 Region 4 Master 6 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_7_4,EL1 Region 4 Master 7 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_8_4,EL1 Region 4 Master 8 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_9_4,EL1 Region 4 Master 9 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_10_4,EL1 Region 4 Master 10 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_11_4,EL1 Region 4 Master 11 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x448++0x3 line.long 0x0 "EL1_MSTR_18_4,EL1 Region 4 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x458++0x3 line.long 0x0 "EL1_MSTR_22_4,EL1 Region 4 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x460++0x3 line.long 0x0 "EL1_MSTR_24_4,EL1 Region 4 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x480++0x17 line.long 0x0 "EL1_MSTR_32_4,EL1 Region 4 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_4,EL1 Region 4 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_4,EL1 Region 4 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_4,EL1 Region 4 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_4,EL1 Region 4 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_4,EL1 Region 4 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x49C++0x3 line.long 0x0 "EL1_MSTR_39_4,EL1 Region 4 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x4D0++0x7 line.long 0x0 "EL1_MSTR_52_4,EL1 Region 4 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_4,EL1 Region 4 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x4E0++0x1F line.long 0x0 "EL1_MSTR_56_4,EL1 Region 4 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_4,EL1 Region 4 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_4,EL1 Region 4 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_4,EL1 Region 4 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_4,EL1 Region 4 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_4,EL1 Region 4 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_4,EL1 Region 4 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_4,EL1 Region 4 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x510++0x1F line.long 0x0 "EL1_MSTR_4_5,EL1 Region 5 Master 4 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_5_5,EL1 Region 5 Master 5 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_6_5,EL1 Region 5 Master 6 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_7_5,EL1 Region 5 Master 7 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_8_5,EL1 Region 5 Master 8 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_9_5,EL1 Region 5 Master 9 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_10_5,EL1 Region 5 Master 10 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_11_5,EL1 Region 5 Master 11 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x548++0x3 line.long 0x0 "EL1_MSTR_18_5,EL1 Region 5 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x558++0x3 line.long 0x0 "EL1_MSTR_22_5,EL1 Region 5 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x560++0x3 line.long 0x0 "EL1_MSTR_24_5,EL1 Region 5 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x580++0x17 line.long 0x0 "EL1_MSTR_32_5,EL1 Region 5 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_5,EL1 Region 5 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_5,EL1 Region 5 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_5,EL1 Region 5 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_5,EL1 Region 5 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_5,EL1 Region 5 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x59C++0x3 line.long 0x0 "EL1_MSTR_39_5,EL1 Region 5 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x5D0++0x7 line.long 0x0 "EL1_MSTR_52_5,EL1 Region 5 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_5,EL1 Region 5 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x5E0++0x1F line.long 0x0 "EL1_MSTR_56_5,EL1 Region 5 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_5,EL1 Region 5 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_5,EL1 Region 5 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_5,EL1 Region 5 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_5,EL1 Region 5 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_5,EL1 Region 5 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_5,EL1 Region 5 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_5,EL1 Region 5 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x610++0x1F line.long 0x0 "EL1_MSTR_4_6,EL1 Region 6 Master 4 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_5_6,EL1 Region 6 Master 5 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_6_6,EL1 Region 6 Master 6 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_7_6,EL1 Region 6 Master 7 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_8_6,EL1 Region 6 Master 8 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_9_6,EL1 Region 6 Master 9 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_10_6,EL1 Region 6 Master 10 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_11_6,EL1 Region 6 Master 11 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x648++0x3 line.long 0x0 "EL1_MSTR_18_6,EL1 Region 6 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x658++0x3 line.long 0x0 "EL1_MSTR_22_6,EL1 Region 6 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x660++0x3 line.long 0x0 "EL1_MSTR_24_6,EL1 Region 6 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x680++0x17 line.long 0x0 "EL1_MSTR_32_6,EL1 Region 6 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_6,EL1 Region 6 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_6,EL1 Region 6 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_6,EL1 Region 6 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_6,EL1 Region 6 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_6,EL1 Region 6 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x69C++0x3 line.long 0x0 "EL1_MSTR_39_6,EL1 Region 6 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x6D0++0x7 line.long 0x0 "EL1_MSTR_52_6,EL1 Region 6 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_6,EL1 Region 6 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x6E0++0x1F line.long 0x0 "EL1_MSTR_56_6,EL1 Region 6 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_6,EL1 Region 6 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_6,EL1 Region 6 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_6,EL1 Region 6 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_6,EL1 Region 6 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_6,EL1 Region 6 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_6,EL1 Region 6 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_6,EL1 Region 6 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x710++0x1F line.long 0x0 "EL1_MSTR_4_7,EL1 Region 7 Master 4 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_5_7,EL1 Region 7 Master 5 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_6_7,EL1 Region 7 Master 6 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_7_7,EL1 Region 7 Master 7 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_8_7,EL1 Region 7 Master 8 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_9_7,EL1 Region 7 Master 9 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_10_7,EL1 Region 7 Master 10 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_11_7,EL1 Region 7 Master 11 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x748++0x3 line.long 0x0 "EL1_MSTR_18_7,EL1 Region 7 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x758++0x3 line.long 0x0 "EL1_MSTR_22_7,EL1 Region 7 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x760++0x3 line.long 0x0 "EL1_MSTR_24_7,EL1 Region 7 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x780++0x17 line.long 0x0 "EL1_MSTR_32_7,EL1 Region 7 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_7,EL1 Region 7 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_7,EL1 Region 7 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_7,EL1 Region 7 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_7,EL1 Region 7 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_7,EL1 Region 7 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x79C++0x3 line.long 0x0 "EL1_MSTR_39_7,EL1 Region 7 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x7D0++0x7 line.long 0x0 "EL1_MSTR_52_7,EL1 Region 7 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_7,EL1 Region 7 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x7E0++0x1F line.long 0x0 "EL1_MSTR_56_7,EL1 Region 7 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_7,EL1 Region 7 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_7,EL1 Region 7 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_7,EL1 Region 7 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_7,EL1 Region 7 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_7,EL1 Region 7 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_7,EL1 Region 7 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_7,EL1 Region 7 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "KITE1_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B7A1200 group.long 0x0++0xF line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x20++0xF line.long 0x0 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x17 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_0,EL1 Region 0 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_0,EL1 Region 0 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_0,EL1 Region 0 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_0,EL1 Region 0 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x9C++0x3 line.long 0x0 "EL1_MSTR_39_0,EL1 Region 0 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xD0++0x7 line.long 0x0 "EL1_MSTR_52_0,EL1 Region 0 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_0,EL1 Region 0 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0x2F line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_0,EL1 Region 0 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_0,EL1 Region 0 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_0,EL1 Region 0 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_0,EL1 Region 0 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_1,EL1 Region 1 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_1,EL1 Region 1 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_1,EL1 Region 1 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_1,EL1 Region 1 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x120++0xF line.long 0x0 "EL1_MSTR_8_1,EL1 Region 1 Master 8 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_9_1,EL1 Region 1 Master 9 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_10_1,EL1 Region 1 Master 10 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_11_1,EL1 Region 1 Master 11 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x148++0x3 line.long 0x0 "EL1_MSTR_18_1,EL1 Region 1 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x158++0x3 line.long 0x0 "EL1_MSTR_22_1,EL1 Region 1 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x160++0x3 line.long 0x0 "EL1_MSTR_24_1,EL1 Region 1 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x180++0x17 line.long 0x0 "EL1_MSTR_32_1,EL1 Region 1 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_1,EL1 Region 1 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_1,EL1 Region 1 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_1,EL1 Region 1 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_1,EL1 Region 1 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_1,EL1 Region 1 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x19C++0x3 line.long 0x0 "EL1_MSTR_39_1,EL1 Region 1 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1D0++0x7 line.long 0x0 "EL1_MSTR_52_1,EL1 Region 1 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_1,EL1 Region 1 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1E0++0x2F line.long 0x0 "EL1_MSTR_56_1,EL1 Region 1 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_1,EL1 Region 1 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_1,EL1 Region 1 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_1,EL1 Region 1 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_1,EL1 Region 1 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_1,EL1 Region 1 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_1,EL1 Region 1 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_1,EL1 Region 1 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_2,EL1 Region 2 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_2,EL1 Region 2 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_2,EL1 Region 2 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_2,EL1 Region 2 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x220++0xF line.long 0x0 "EL1_MSTR_8_2,EL1 Region 2 Master 8 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_9_2,EL1 Region 2 Master 9 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_10_2,EL1 Region 2 Master 10 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_11_2,EL1 Region 2 Master 11 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x248++0x3 line.long 0x0 "EL1_MSTR_18_2,EL1 Region 2 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x258++0x3 line.long 0x0 "EL1_MSTR_22_2,EL1 Region 2 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x260++0x3 line.long 0x0 "EL1_MSTR_24_2,EL1 Region 2 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x280++0x17 line.long 0x0 "EL1_MSTR_32_2,EL1 Region 2 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_2,EL1 Region 2 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_2,EL1 Region 2 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_2,EL1 Region 2 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_2,EL1 Region 2 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_2,EL1 Region 2 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x29C++0x3 line.long 0x0 "EL1_MSTR_39_2,EL1 Region 2 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x2D0++0x7 line.long 0x0 "EL1_MSTR_52_2,EL1 Region 2 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_2,EL1 Region 2 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x2E0++0x2F line.long 0x0 "EL1_MSTR_56_2,EL1 Region 2 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_2,EL1 Region 2 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_2,EL1 Region 2 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_2,EL1 Region 2 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_2,EL1 Region 2 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_2,EL1 Region 2 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_2,EL1 Region 2 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_2,EL1 Region 2 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_3,EL1 Region 3 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_3,EL1 Region 3 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_3,EL1 Region 3 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_3,EL1 Region 3 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x320++0xF line.long 0x0 "EL1_MSTR_8_3,EL1 Region 3 Master 8 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_9_3,EL1 Region 3 Master 9 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_10_3,EL1 Region 3 Master 10 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_11_3,EL1 Region 3 Master 11 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x348++0x3 line.long 0x0 "EL1_MSTR_18_3,EL1 Region 3 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x358++0x3 line.long 0x0 "EL1_MSTR_22_3,EL1 Region 3 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x360++0x3 line.long 0x0 "EL1_MSTR_24_3,EL1 Region 3 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x380++0x17 line.long 0x0 "EL1_MSTR_32_3,EL1 Region 3 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_3,EL1 Region 3 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_3,EL1 Region 3 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_3,EL1 Region 3 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_3,EL1 Region 3 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_3,EL1 Region 3 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x39C++0x3 line.long 0x0 "EL1_MSTR_39_3,EL1 Region 3 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x3D0++0x7 line.long 0x0 "EL1_MSTR_52_3,EL1 Region 3 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_3,EL1 Region 3 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x3E0++0x2F line.long 0x0 "EL1_MSTR_56_3,EL1 Region 3 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_3,EL1 Region 3 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_3,EL1 Region 3 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_3,EL1 Region 3 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_3,EL1 Region 3 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_3,EL1 Region 3 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_3,EL1 Region 3 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_3,EL1 Region 3 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_4,EL1 Region 4 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_4,EL1 Region 4 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_4,EL1 Region 4 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_4,EL1 Region 4 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x420++0xF line.long 0x0 "EL1_MSTR_8_4,EL1 Region 4 Master 8 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_9_4,EL1 Region 4 Master 9 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_10_4,EL1 Region 4 Master 10 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_11_4,EL1 Region 4 Master 11 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x448++0x3 line.long 0x0 "EL1_MSTR_18_4,EL1 Region 4 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x458++0x3 line.long 0x0 "EL1_MSTR_22_4,EL1 Region 4 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x460++0x3 line.long 0x0 "EL1_MSTR_24_4,EL1 Region 4 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x480++0x17 line.long 0x0 "EL1_MSTR_32_4,EL1 Region 4 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_4,EL1 Region 4 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_4,EL1 Region 4 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_4,EL1 Region 4 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_4,EL1 Region 4 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_4,EL1 Region 4 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x49C++0x3 line.long 0x0 "EL1_MSTR_39_4,EL1 Region 4 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x4D0++0x7 line.long 0x0 "EL1_MSTR_52_4,EL1 Region 4 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_4,EL1 Region 4 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x4E0++0x2F line.long 0x0 "EL1_MSTR_56_4,EL1 Region 4 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_4,EL1 Region 4 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_4,EL1 Region 4 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_4,EL1 Region 4 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_4,EL1 Region 4 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_4,EL1 Region 4 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_4,EL1 Region 4 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_4,EL1 Region 4 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_5,EL1 Region 5 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_5,EL1 Region 5 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_5,EL1 Region 5 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_5,EL1 Region 5 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x520++0xF line.long 0x0 "EL1_MSTR_8_5,EL1 Region 5 Master 8 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_9_5,EL1 Region 5 Master 9 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_10_5,EL1 Region 5 Master 10 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_11_5,EL1 Region 5 Master 11 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x548++0x3 line.long 0x0 "EL1_MSTR_18_5,EL1 Region 5 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x558++0x3 line.long 0x0 "EL1_MSTR_22_5,EL1 Region 5 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x560++0x3 line.long 0x0 "EL1_MSTR_24_5,EL1 Region 5 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x580++0x17 line.long 0x0 "EL1_MSTR_32_5,EL1 Region 5 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_5,EL1 Region 5 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_5,EL1 Region 5 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_5,EL1 Region 5 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_5,EL1 Region 5 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_5,EL1 Region 5 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x59C++0x3 line.long 0x0 "EL1_MSTR_39_5,EL1 Region 5 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x5D0++0x7 line.long 0x0 "EL1_MSTR_52_5,EL1 Region 5 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_5,EL1 Region 5 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x5E0++0x2F line.long 0x0 "EL1_MSTR_56_5,EL1 Region 5 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_5,EL1 Region 5 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_5,EL1 Region 5 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_5,EL1 Region 5 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_5,EL1 Region 5 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_5,EL1 Region 5 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_5,EL1 Region 5 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_5,EL1 Region 5 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_6,EL1 Region 6 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_6,EL1 Region 6 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_6,EL1 Region 6 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_6,EL1 Region 6 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x620++0xF line.long 0x0 "EL1_MSTR_8_6,EL1 Region 6 Master 8 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_9_6,EL1 Region 6 Master 9 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_10_6,EL1 Region 6 Master 10 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_11_6,EL1 Region 6 Master 11 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x648++0x3 line.long 0x0 "EL1_MSTR_18_6,EL1 Region 6 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x658++0x3 line.long 0x0 "EL1_MSTR_22_6,EL1 Region 6 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x660++0x3 line.long 0x0 "EL1_MSTR_24_6,EL1 Region 6 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x680++0x17 line.long 0x0 "EL1_MSTR_32_6,EL1 Region 6 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_6,EL1 Region 6 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_6,EL1 Region 6 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_6,EL1 Region 6 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_6,EL1 Region 6 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_6,EL1 Region 6 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x69C++0x3 line.long 0x0 "EL1_MSTR_39_6,EL1 Region 6 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x6D0++0x7 line.long 0x0 "EL1_MSTR_52_6,EL1 Region 6 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_6,EL1 Region 6 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x6E0++0x2F line.long 0x0 "EL1_MSTR_56_6,EL1 Region 6 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_6,EL1 Region 6 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_6,EL1 Region 6 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_6,EL1 Region 6 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_6,EL1 Region 6 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_6,EL1 Region 6 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_6,EL1 Region 6 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_6,EL1 Region 6 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_7,EL1 Region 7 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_7,EL1 Region 7 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_7,EL1 Region 7 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_7,EL1 Region 7 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x720++0xF line.long 0x0 "EL1_MSTR_8_7,EL1 Region 7 Master 8 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_9_7,EL1 Region 7 Master 9 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_10_7,EL1 Region 7 Master 10 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_11_7,EL1 Region 7 Master 11 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x748++0x3 line.long 0x0 "EL1_MSTR_18_7,EL1 Region 7 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x758++0x3 line.long 0x0 "EL1_MSTR_22_7,EL1 Region 7 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x760++0x3 line.long 0x0 "EL1_MSTR_24_7,EL1 Region 7 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x780++0x17 line.long 0x0 "EL1_MSTR_32_7,EL1 Region 7 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_7,EL1 Region 7 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_7,EL1 Region 7 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_7,EL1 Region 7 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_7,EL1 Region 7 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_7,EL1 Region 7 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x79C++0x3 line.long 0x0 "EL1_MSTR_39_7,EL1 Region 7 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x7D0++0x7 line.long 0x0 "EL1_MSTR_52_7,EL1 Region 7 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_7,EL1 Region 7 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x7E0++0x1F line.long 0x0 "EL1_MSTR_56_7,EL1 Region 7 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_7,EL1 Region 7 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_7,EL1 Region 7 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_7,EL1 Region 7 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_7,EL1 Region 7 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_7,EL1 Region 7 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_7,EL1 Region 7 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_7,EL1 Region 7 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "KITE2_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B7C1200 group.long 0x0++0x1F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x17 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_0,EL1 Region 0 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_0,EL1 Region 0 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_0,EL1 Region 0 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_0,EL1 Region 0 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x9C++0x3 line.long 0x0 "EL1_MSTR_39_0,EL1 Region 0 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xD0++0x7 line.long 0x0 "EL1_MSTR_52_0,EL1 Region 0 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_0,EL1 Region 0 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0x3F line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_0,EL1 Region 0 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_0,EL1 Region 0 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_0,EL1 Region 0 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_0,EL1 Region 0 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_1,EL1 Region 1 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_1,EL1 Region 1 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_1,EL1 Region 1 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_1,EL1 Region 1 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x30 "EL1_MSTR_4_1,EL1 Region 1 Master 4 Access Register" bitfld.long 0x30 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x30 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x30 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x34 "EL1_MSTR_5_1,EL1 Region 1 Master 5 Access Register" bitfld.long 0x34 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x34 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x34 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x38 "EL1_MSTR_6_1,EL1 Region 1 Master 6 Access Register" bitfld.long 0x38 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x38 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x38 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x3C "EL1_MSTR_7_1,EL1 Region 1 Master 7 Access Register" bitfld.long 0x3C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x3C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x3C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x148++0x3 line.long 0x0 "EL1_MSTR_18_1,EL1 Region 1 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x158++0x3 line.long 0x0 "EL1_MSTR_22_1,EL1 Region 1 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x160++0x3 line.long 0x0 "EL1_MSTR_24_1,EL1 Region 1 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x180++0x17 line.long 0x0 "EL1_MSTR_32_1,EL1 Region 1 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_1,EL1 Region 1 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_1,EL1 Region 1 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_1,EL1 Region 1 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_1,EL1 Region 1 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_1,EL1 Region 1 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x19C++0x3 line.long 0x0 "EL1_MSTR_39_1,EL1 Region 1 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1D0++0x7 line.long 0x0 "EL1_MSTR_52_1,EL1 Region 1 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_1,EL1 Region 1 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1E0++0x3F line.long 0x0 "EL1_MSTR_56_1,EL1 Region 1 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_1,EL1 Region 1 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_1,EL1 Region 1 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_1,EL1 Region 1 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_1,EL1 Region 1 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_1,EL1 Region 1 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_1,EL1 Region 1 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_1,EL1 Region 1 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_2,EL1 Region 2 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_2,EL1 Region 2 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_2,EL1 Region 2 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_2,EL1 Region 2 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x30 "EL1_MSTR_4_2,EL1 Region 2 Master 4 Access Register" bitfld.long 0x30 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x30 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x30 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x34 "EL1_MSTR_5_2,EL1 Region 2 Master 5 Access Register" bitfld.long 0x34 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x34 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x34 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x38 "EL1_MSTR_6_2,EL1 Region 2 Master 6 Access Register" bitfld.long 0x38 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x38 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x38 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x3C "EL1_MSTR_7_2,EL1 Region 2 Master 7 Access Register" bitfld.long 0x3C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x3C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x3C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x248++0x3 line.long 0x0 "EL1_MSTR_18_2,EL1 Region 2 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x258++0x3 line.long 0x0 "EL1_MSTR_22_2,EL1 Region 2 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x260++0x3 line.long 0x0 "EL1_MSTR_24_2,EL1 Region 2 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x280++0x17 line.long 0x0 "EL1_MSTR_32_2,EL1 Region 2 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_2,EL1 Region 2 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_2,EL1 Region 2 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_2,EL1 Region 2 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_2,EL1 Region 2 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_2,EL1 Region 2 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x29C++0x3 line.long 0x0 "EL1_MSTR_39_2,EL1 Region 2 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x2D0++0x7 line.long 0x0 "EL1_MSTR_52_2,EL1 Region 2 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_2,EL1 Region 2 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x2E0++0x3F line.long 0x0 "EL1_MSTR_56_2,EL1 Region 2 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_2,EL1 Region 2 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_2,EL1 Region 2 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_2,EL1 Region 2 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_2,EL1 Region 2 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_2,EL1 Region 2 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_2,EL1 Region 2 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_2,EL1 Region 2 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_3,EL1 Region 3 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_3,EL1 Region 3 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_3,EL1 Region 3 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_3,EL1 Region 3 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x30 "EL1_MSTR_4_3,EL1 Region 3 Master 4 Access Register" bitfld.long 0x30 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x30 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x30 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x34 "EL1_MSTR_5_3,EL1 Region 3 Master 5 Access Register" bitfld.long 0x34 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x34 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x34 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x38 "EL1_MSTR_6_3,EL1 Region 3 Master 6 Access Register" bitfld.long 0x38 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x38 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x38 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x3C "EL1_MSTR_7_3,EL1 Region 3 Master 7 Access Register" bitfld.long 0x3C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x3C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x3C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x348++0x3 line.long 0x0 "EL1_MSTR_18_3,EL1 Region 3 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x358++0x3 line.long 0x0 "EL1_MSTR_22_3,EL1 Region 3 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x360++0x3 line.long 0x0 "EL1_MSTR_24_3,EL1 Region 3 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x380++0x17 line.long 0x0 "EL1_MSTR_32_3,EL1 Region 3 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_3,EL1 Region 3 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_3,EL1 Region 3 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_3,EL1 Region 3 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_3,EL1 Region 3 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_3,EL1 Region 3 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x39C++0x3 line.long 0x0 "EL1_MSTR_39_3,EL1 Region 3 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x3D0++0x7 line.long 0x0 "EL1_MSTR_52_3,EL1 Region 3 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_3,EL1 Region 3 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x3E0++0x3F line.long 0x0 "EL1_MSTR_56_3,EL1 Region 3 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_3,EL1 Region 3 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_3,EL1 Region 3 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_3,EL1 Region 3 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_3,EL1 Region 3 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_3,EL1 Region 3 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_3,EL1 Region 3 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_3,EL1 Region 3 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_4,EL1 Region 4 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_4,EL1 Region 4 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_4,EL1 Region 4 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_4,EL1 Region 4 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x30 "EL1_MSTR_4_4,EL1 Region 4 Master 4 Access Register" bitfld.long 0x30 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x30 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x30 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x34 "EL1_MSTR_5_4,EL1 Region 4 Master 5 Access Register" bitfld.long 0x34 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x34 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x34 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x38 "EL1_MSTR_6_4,EL1 Region 4 Master 6 Access Register" bitfld.long 0x38 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x38 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x38 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x3C "EL1_MSTR_7_4,EL1 Region 4 Master 7 Access Register" bitfld.long 0x3C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x3C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x3C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x448++0x3 line.long 0x0 "EL1_MSTR_18_4,EL1 Region 4 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x458++0x3 line.long 0x0 "EL1_MSTR_22_4,EL1 Region 4 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x460++0x3 line.long 0x0 "EL1_MSTR_24_4,EL1 Region 4 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x480++0x17 line.long 0x0 "EL1_MSTR_32_4,EL1 Region 4 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_4,EL1 Region 4 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_4,EL1 Region 4 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_4,EL1 Region 4 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_4,EL1 Region 4 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_4,EL1 Region 4 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x49C++0x3 line.long 0x0 "EL1_MSTR_39_4,EL1 Region 4 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x4D0++0x7 line.long 0x0 "EL1_MSTR_52_4,EL1 Region 4 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_4,EL1 Region 4 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x4E0++0x3F line.long 0x0 "EL1_MSTR_56_4,EL1 Region 4 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_4,EL1 Region 4 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_4,EL1 Region 4 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_4,EL1 Region 4 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_4,EL1 Region 4 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_4,EL1 Region 4 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_4,EL1 Region 4 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_4,EL1 Region 4 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_5,EL1 Region 5 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_5,EL1 Region 5 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_5,EL1 Region 5 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_5,EL1 Region 5 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x30 "EL1_MSTR_4_5,EL1 Region 5 Master 4 Access Register" bitfld.long 0x30 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x30 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x30 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x34 "EL1_MSTR_5_5,EL1 Region 5 Master 5 Access Register" bitfld.long 0x34 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x34 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x34 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x38 "EL1_MSTR_6_5,EL1 Region 5 Master 6 Access Register" bitfld.long 0x38 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x38 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x38 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x3C "EL1_MSTR_7_5,EL1 Region 5 Master 7 Access Register" bitfld.long 0x3C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x3C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x3C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x548++0x3 line.long 0x0 "EL1_MSTR_18_5,EL1 Region 5 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x558++0x3 line.long 0x0 "EL1_MSTR_22_5,EL1 Region 5 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x560++0x3 line.long 0x0 "EL1_MSTR_24_5,EL1 Region 5 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x580++0x17 line.long 0x0 "EL1_MSTR_32_5,EL1 Region 5 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_5,EL1 Region 5 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_5,EL1 Region 5 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_5,EL1 Region 5 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_5,EL1 Region 5 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_5,EL1 Region 5 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x59C++0x3 line.long 0x0 "EL1_MSTR_39_5,EL1 Region 5 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x5D0++0x7 line.long 0x0 "EL1_MSTR_52_5,EL1 Region 5 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_5,EL1 Region 5 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x5E0++0x3F line.long 0x0 "EL1_MSTR_56_5,EL1 Region 5 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_5,EL1 Region 5 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_5,EL1 Region 5 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_5,EL1 Region 5 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_5,EL1 Region 5 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_5,EL1 Region 5 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_5,EL1 Region 5 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_5,EL1 Region 5 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_6,EL1 Region 6 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_6,EL1 Region 6 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_6,EL1 Region 6 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_6,EL1 Region 6 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x30 "EL1_MSTR_4_6,EL1 Region 6 Master 4 Access Register" bitfld.long 0x30 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x30 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x30 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x34 "EL1_MSTR_5_6,EL1 Region 6 Master 5 Access Register" bitfld.long 0x34 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x34 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x34 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x38 "EL1_MSTR_6_6,EL1 Region 6 Master 6 Access Register" bitfld.long 0x38 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x38 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x38 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x3C "EL1_MSTR_7_6,EL1 Region 6 Master 7 Access Register" bitfld.long 0x3C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x3C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x3C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x648++0x3 line.long 0x0 "EL1_MSTR_18_6,EL1 Region 6 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x658++0x3 line.long 0x0 "EL1_MSTR_22_6,EL1 Region 6 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x660++0x3 line.long 0x0 "EL1_MSTR_24_6,EL1 Region 6 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x680++0x17 line.long 0x0 "EL1_MSTR_32_6,EL1 Region 6 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_6,EL1 Region 6 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_6,EL1 Region 6 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_6,EL1 Region 6 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_6,EL1 Region 6 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_6,EL1 Region 6 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x69C++0x3 line.long 0x0 "EL1_MSTR_39_6,EL1 Region 6 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x6D0++0x7 line.long 0x0 "EL1_MSTR_52_6,EL1 Region 6 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_6,EL1 Region 6 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x6E0++0x3F line.long 0x0 "EL1_MSTR_56_6,EL1 Region 6 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_6,EL1 Region 6 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_6,EL1 Region 6 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_6,EL1 Region 6 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_6,EL1 Region 6 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_6,EL1 Region 6 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_6,EL1 Region 6 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_6,EL1 Region 6 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_7,EL1 Region 7 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_7,EL1 Region 7 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_7,EL1 Region 7 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_7,EL1 Region 7 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x30 "EL1_MSTR_4_7,EL1 Region 7 Master 4 Access Register" bitfld.long 0x30 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x30 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x30 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x34 "EL1_MSTR_5_7,EL1 Region 7 Master 5 Access Register" bitfld.long 0x34 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x34 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x34 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x38 "EL1_MSTR_6_7,EL1 Region 7 Master 6 Access Register" bitfld.long 0x38 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x38 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x38 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x3C "EL1_MSTR_7_7,EL1 Region 7 Master 7 Access Register" bitfld.long 0x3C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x3C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x3C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x748++0x3 line.long 0x0 "EL1_MSTR_18_7,EL1 Region 7 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x758++0x3 line.long 0x0 "EL1_MSTR_22_7,EL1 Region 7 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x760++0x3 line.long 0x0 "EL1_MSTR_24_7,EL1 Region 7 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x780++0x17 line.long 0x0 "EL1_MSTR_32_7,EL1 Region 7 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_7,EL1 Region 7 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_7,EL1 Region 7 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_7,EL1 Region 7 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_7,EL1 Region 7 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_7,EL1 Region 7 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x79C++0x3 line.long 0x0 "EL1_MSTR_39_7,EL1 Region 7 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x7D0++0x7 line.long 0x0 "EL1_MSTR_52_7,EL1 Region 7 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_7,EL1 Region 7 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x7E0++0x1F line.long 0x0 "EL1_MSTR_56_7,EL1 Region 7 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_7,EL1 Region 7 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_7,EL1 Region 7 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_7,EL1 Region 7 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_7,EL1 Region 7 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_7,EL1 Region 7 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_7,EL1 Region 7 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_7,EL1 Region 7 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "NVM_WR_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B761200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x7 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x100++0x2F line.long 0x0 "EL1_MSTR_0_1,EL1 Region 1 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_1,EL1 Region 1 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_1,EL1 Region 1 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_1,EL1 Region 1 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_1,EL1 Region 1 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_1,EL1 Region 1 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_1,EL1 Region 1 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_1,EL1 Region 1 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_1,EL1 Region 1 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_1,EL1 Region 1 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_1,EL1 Region 1 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_1,EL1 Region 1 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x148++0x3 line.long 0x0 "EL1_MSTR_18_1,EL1 Region 1 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x158++0x3 line.long 0x0 "EL1_MSTR_22_1,EL1 Region 1 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x160++0x3 line.long 0x0 "EL1_MSTR_24_1,EL1 Region 1 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x180++0x7 line.long 0x0 "EL1_MSTR_32_1,EL1 Region 1 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_1,EL1 Region 1 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x200++0x2F line.long 0x0 "EL1_MSTR_0_2,EL1 Region 2 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_2,EL1 Region 2 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_2,EL1 Region 2 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_2,EL1 Region 2 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_2,EL1 Region 2 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_2,EL1 Region 2 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_2,EL1 Region 2 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_2,EL1 Region 2 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_2,EL1 Region 2 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_2,EL1 Region 2 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_2,EL1 Region 2 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_2,EL1 Region 2 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x248++0x3 line.long 0x0 "EL1_MSTR_18_2,EL1 Region 2 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x258++0x3 line.long 0x0 "EL1_MSTR_22_2,EL1 Region 2 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x260++0x3 line.long 0x0 "EL1_MSTR_24_2,EL1 Region 2 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x280++0x7 line.long 0x0 "EL1_MSTR_32_2,EL1 Region 2 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_2,EL1 Region 2 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x300++0x2F line.long 0x0 "EL1_MSTR_0_3,EL1 Region 3 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_3,EL1 Region 3 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_3,EL1 Region 3 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_3,EL1 Region 3 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_3,EL1 Region 3 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_3,EL1 Region 3 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_3,EL1 Region 3 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_3,EL1 Region 3 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_3,EL1 Region 3 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_3,EL1 Region 3 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_3,EL1 Region 3 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_3,EL1 Region 3 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x348++0x3 line.long 0x0 "EL1_MSTR_18_3,EL1 Region 3 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x358++0x3 line.long 0x0 "EL1_MSTR_22_3,EL1 Region 3 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x360++0x3 line.long 0x0 "EL1_MSTR_24_3,EL1 Region 3 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x380++0x7 line.long 0x0 "EL1_MSTR_32_3,EL1 Region 3 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_3,EL1 Region 3 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "OCT_SPI_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B721200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x7 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x9C++0x3 line.long 0x0 "EL1_MSTR_39_0,EL1 Region 0 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0xF line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "PCIE0_CFG_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B6E1200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x7 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x100++0x2F line.long 0x0 "EL1_MSTR_0_1,EL1 Region 1 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_1,EL1 Region 1 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_1,EL1 Region 1 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_1,EL1 Region 1 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_1,EL1 Region 1 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_1,EL1 Region 1 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_1,EL1 Region 1 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_1,EL1 Region 1 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_1,EL1 Region 1 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_1,EL1 Region 1 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_1,EL1 Region 1 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_1,EL1 Region 1 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x148++0x3 line.long 0x0 "EL1_MSTR_18_1,EL1 Region 1 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x158++0x3 line.long 0x0 "EL1_MSTR_22_1,EL1 Region 1 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x160++0x3 line.long 0x0 "EL1_MSTR_24_1,EL1 Region 1 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x180++0x7 line.long 0x0 "EL1_MSTR_32_1,EL1 Region 1 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_1,EL1 Region 1 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x200++0x2F line.long 0x0 "EL1_MSTR_0_2,EL1 Region 2 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_2,EL1 Region 2 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_2,EL1 Region 2 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_2,EL1 Region 2 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_2,EL1 Region 2 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_2,EL1 Region 2 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_2,EL1 Region 2 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_2,EL1 Region 2 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_2,EL1 Region 2 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_2,EL1 Region 2 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_2,EL1 Region 2 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_2,EL1 Region 2 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x248++0x3 line.long 0x0 "EL1_MSTR_18_2,EL1 Region 2 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x258++0x3 line.long 0x0 "EL1_MSTR_22_2,EL1 Region 2 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x260++0x3 line.long 0x0 "EL1_MSTR_24_2,EL1 Region 2 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x280++0x7 line.long 0x0 "EL1_MSTR_32_2,EL1 Region 2 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_2,EL1 Region 2 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "PCIE0_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B601200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x7 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0xF line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x100++0x2F line.long 0x0 "EL1_MSTR_0_1,EL1 Region 1 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_1,EL1 Region 1 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_1,EL1 Region 1 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_1,EL1 Region 1 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_1,EL1 Region 1 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_1,EL1 Region 1 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_1,EL1 Region 1 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_1,EL1 Region 1 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_1,EL1 Region 1 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_1,EL1 Region 1 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_1,EL1 Region 1 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_1,EL1 Region 1 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x148++0x3 line.long 0x0 "EL1_MSTR_18_1,EL1 Region 1 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x158++0x3 line.long 0x0 "EL1_MSTR_22_1,EL1 Region 1 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x160++0x3 line.long 0x0 "EL1_MSTR_24_1,EL1 Region 1 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x180++0x7 line.long 0x0 "EL1_MSTR_32_1,EL1 Region 1 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_1,EL1 Region 1 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1E0++0xF line.long 0x0 "EL1_MSTR_56_1,EL1 Region 1 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_1,EL1 Region 1 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_1,EL1 Region 1 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_1,EL1 Region 1 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x200++0x2F line.long 0x0 "EL1_MSTR_0_2,EL1 Region 2 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_2,EL1 Region 2 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_2,EL1 Region 2 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_2,EL1 Region 2 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_2,EL1 Region 2 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_2,EL1 Region 2 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_2,EL1 Region 2 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_2,EL1 Region 2 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_2,EL1 Region 2 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_2,EL1 Region 2 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_2,EL1 Region 2 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_2,EL1 Region 2 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x248++0x3 line.long 0x0 "EL1_MSTR_18_2,EL1 Region 2 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x258++0x3 line.long 0x0 "EL1_MSTR_22_2,EL1 Region 2 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x260++0x3 line.long 0x0 "EL1_MSTR_24_2,EL1 Region 2 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x280++0x7 line.long 0x0 "EL1_MSTR_32_2,EL1 Region 2 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_2,EL1 Region 2 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x2E0++0xF line.long 0x0 "EL1_MSTR_56_2,EL1 Region 2 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_2,EL1 Region 2 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_2,EL1 Region 2 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_2,EL1 Region 2 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "PCIE1_CFG_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B6F1200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x7 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x100++0x2F line.long 0x0 "EL1_MSTR_0_1,EL1 Region 1 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_1,EL1 Region 1 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_1,EL1 Region 1 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_1,EL1 Region 1 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_1,EL1 Region 1 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_1,EL1 Region 1 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_1,EL1 Region 1 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_1,EL1 Region 1 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_1,EL1 Region 1 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_1,EL1 Region 1 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_1,EL1 Region 1 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_1,EL1 Region 1 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x148++0x3 line.long 0x0 "EL1_MSTR_18_1,EL1 Region 1 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x158++0x3 line.long 0x0 "EL1_MSTR_22_1,EL1 Region 1 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x160++0x3 line.long 0x0 "EL1_MSTR_24_1,EL1 Region 1 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x180++0x7 line.long 0x0 "EL1_MSTR_32_1,EL1 Region 1 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_1,EL1 Region 1 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x200++0x2F line.long 0x0 "EL1_MSTR_0_2,EL1 Region 2 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_2,EL1 Region 2 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_2,EL1 Region 2 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_2,EL1 Region 2 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_2,EL1 Region 2 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_2,EL1 Region 2 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_2,EL1 Region 2 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_2,EL1 Region 2 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_2,EL1 Region 2 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_2,EL1 Region 2 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_2,EL1 Region 2 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_2,EL1 Region 2 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x248++0x3 line.long 0x0 "EL1_MSTR_18_2,EL1 Region 2 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x258++0x3 line.long 0x0 "EL1_MSTR_22_2,EL1 Region 2 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x260++0x3 line.long 0x0 "EL1_MSTR_24_2,EL1 Region 2 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x280++0x7 line.long 0x0 "EL1_MSTR_32_2,EL1 Region 2 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_2,EL1 Region 2 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "PCIE1_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B611200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x7 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0xF line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x100++0x2F line.long 0x0 "EL1_MSTR_0_1,EL1 Region 1 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_1,EL1 Region 1 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_1,EL1 Region 1 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_1,EL1 Region 1 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_1,EL1 Region 1 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_1,EL1 Region 1 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_1,EL1 Region 1 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_1,EL1 Region 1 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_1,EL1 Region 1 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_1,EL1 Region 1 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_1,EL1 Region 1 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_1,EL1 Region 1 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x148++0x3 line.long 0x0 "EL1_MSTR_18_1,EL1 Region 1 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x158++0x3 line.long 0x0 "EL1_MSTR_22_1,EL1 Region 1 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x160++0x3 line.long 0x0 "EL1_MSTR_24_1,EL1 Region 1 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x180++0x7 line.long 0x0 "EL1_MSTR_32_1,EL1 Region 1 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_1,EL1 Region 1 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1E0++0xF line.long 0x0 "EL1_MSTR_56_1,EL1 Region 1 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_1,EL1 Region 1 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_1,EL1 Region 1 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_1,EL1 Region 1 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x200++0x2F line.long 0x0 "EL1_MSTR_0_2,EL1 Region 2 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_2,EL1 Region 2 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_2,EL1 Region 2 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_2,EL1 Region 2 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_2,EL1 Region 2 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_2,EL1 Region 2 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_2,EL1 Region 2 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_2,EL1 Region 2 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_2,EL1 Region 2 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_2,EL1 Region 2 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_2,EL1 Region 2 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_2,EL1 Region 2 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x248++0x3 line.long 0x0 "EL1_MSTR_18_2,EL1 Region 2 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x258++0x3 line.long 0x0 "EL1_MSTR_22_2,EL1 Region 2 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x260++0x3 line.long 0x0 "EL1_MSTR_24_2,EL1 Region 2 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x280++0x7 line.long 0x0 "EL1_MSTR_32_2,EL1 Region 2 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_2,EL1 Region 2 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x2E0++0xF line.long 0x0 "EL1_MSTR_56_2,EL1 Region 2 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_2,EL1 Region 2 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_2,EL1 Region 2 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_2,EL1 Region 2 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "SDMMC_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B731200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x7 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "SYSRAM0_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B701200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x17 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_0,EL1 Region 0 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_0,EL1 Region 0 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_0,EL1 Region 0 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_0,EL1 Region 0 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x9C++0x3 line.long 0x0 "EL1_MSTR_39_0,EL1 Region 0 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xC0++0x3 line.long 0x0 "EL1_MSTR_48_0,EL1 Region 0 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xD0++0x7 line.long 0x0 "EL1_MSTR_52_0,EL1 Region 0 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_0,EL1 Region 0 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0x4F line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_0,EL1 Region 0 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_0,EL1 Region 0 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_0,EL1 Region 0 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_0,EL1 Region 0 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_1,EL1 Region 1 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_1,EL1 Region 1 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_1,EL1 Region 1 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_1,EL1 Region 1 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x30 "EL1_MSTR_4_1,EL1 Region 1 Master 4 Access Register" bitfld.long 0x30 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x30 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x30 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x34 "EL1_MSTR_5_1,EL1 Region 1 Master 5 Access Register" bitfld.long 0x34 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x34 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x34 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x38 "EL1_MSTR_6_1,EL1 Region 1 Master 6 Access Register" bitfld.long 0x38 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x38 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x38 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x3C "EL1_MSTR_7_1,EL1 Region 1 Master 7 Access Register" bitfld.long 0x3C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x3C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x3C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x40 "EL1_MSTR_8_1,EL1 Region 1 Master 8 Access Register" bitfld.long 0x40 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x40 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x40 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x44 "EL1_MSTR_9_1,EL1 Region 1 Master 9 Access Register" bitfld.long 0x44 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x44 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x44 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x48 "EL1_MSTR_10_1,EL1 Region 1 Master 10 Access Register" bitfld.long 0x48 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x48 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x48 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4C "EL1_MSTR_11_1,EL1 Region 1 Master 11 Access Register" bitfld.long 0x4C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x148++0x3 line.long 0x0 "EL1_MSTR_18_1,EL1 Region 1 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x158++0x3 line.long 0x0 "EL1_MSTR_22_1,EL1 Region 1 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x160++0x3 line.long 0x0 "EL1_MSTR_24_1,EL1 Region 1 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x180++0x17 line.long 0x0 "EL1_MSTR_32_1,EL1 Region 1 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_1,EL1 Region 1 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_1,EL1 Region 1 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_1,EL1 Region 1 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_1,EL1 Region 1 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_1,EL1 Region 1 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x19C++0x3 line.long 0x0 "EL1_MSTR_39_1,EL1 Region 1 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1C0++0x3 line.long 0x0 "EL1_MSTR_48_1,EL1 Region 1 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1D0++0x7 line.long 0x0 "EL1_MSTR_52_1,EL1 Region 1 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_1,EL1 Region 1 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1E0++0x4F line.long 0x0 "EL1_MSTR_56_1,EL1 Region 1 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_1,EL1 Region 1 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_1,EL1 Region 1 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_1,EL1 Region 1 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_1,EL1 Region 1 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_1,EL1 Region 1 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_1,EL1 Region 1 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_1,EL1 Region 1 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_2,EL1 Region 2 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_2,EL1 Region 2 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_2,EL1 Region 2 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_2,EL1 Region 2 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x30 "EL1_MSTR_4_2,EL1 Region 2 Master 4 Access Register" bitfld.long 0x30 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x30 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x30 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x34 "EL1_MSTR_5_2,EL1 Region 2 Master 5 Access Register" bitfld.long 0x34 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x34 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x34 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x38 "EL1_MSTR_6_2,EL1 Region 2 Master 6 Access Register" bitfld.long 0x38 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x38 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x38 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x3C "EL1_MSTR_7_2,EL1 Region 2 Master 7 Access Register" bitfld.long 0x3C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x3C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x3C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x40 "EL1_MSTR_8_2,EL1 Region 2 Master 8 Access Register" bitfld.long 0x40 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x40 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x40 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x44 "EL1_MSTR_9_2,EL1 Region 2 Master 9 Access Register" bitfld.long 0x44 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x44 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x44 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x48 "EL1_MSTR_10_2,EL1 Region 2 Master 10 Access Register" bitfld.long 0x48 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x48 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x48 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4C "EL1_MSTR_11_2,EL1 Region 2 Master 11 Access Register" bitfld.long 0x4C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x248++0x3 line.long 0x0 "EL1_MSTR_18_2,EL1 Region 2 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x258++0x3 line.long 0x0 "EL1_MSTR_22_2,EL1 Region 2 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x260++0x3 line.long 0x0 "EL1_MSTR_24_2,EL1 Region 2 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x280++0x17 line.long 0x0 "EL1_MSTR_32_2,EL1 Region 2 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_2,EL1 Region 2 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_2,EL1 Region 2 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_2,EL1 Region 2 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_2,EL1 Region 2 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_2,EL1 Region 2 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x29C++0x3 line.long 0x0 "EL1_MSTR_39_2,EL1 Region 2 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x2C0++0x3 line.long 0x0 "EL1_MSTR_48_2,EL1 Region 2 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x2D0++0x7 line.long 0x0 "EL1_MSTR_52_2,EL1 Region 2 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_2,EL1 Region 2 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x2E0++0x4F line.long 0x0 "EL1_MSTR_56_2,EL1 Region 2 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_2,EL1 Region 2 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_2,EL1 Region 2 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_2,EL1 Region 2 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_2,EL1 Region 2 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_2,EL1 Region 2 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_2,EL1 Region 2 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_2,EL1 Region 2 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_3,EL1 Region 3 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_3,EL1 Region 3 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_3,EL1 Region 3 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_3,EL1 Region 3 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x30 "EL1_MSTR_4_3,EL1 Region 3 Master 4 Access Register" bitfld.long 0x30 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x30 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x30 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x34 "EL1_MSTR_5_3,EL1 Region 3 Master 5 Access Register" bitfld.long 0x34 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x34 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x34 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x38 "EL1_MSTR_6_3,EL1 Region 3 Master 6 Access Register" bitfld.long 0x38 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x38 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x38 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x3C "EL1_MSTR_7_3,EL1 Region 3 Master 7 Access Register" bitfld.long 0x3C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x3C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x3C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x40 "EL1_MSTR_8_3,EL1 Region 3 Master 8 Access Register" bitfld.long 0x40 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x40 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x40 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x44 "EL1_MSTR_9_3,EL1 Region 3 Master 9 Access Register" bitfld.long 0x44 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x44 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x44 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x48 "EL1_MSTR_10_3,EL1 Region 3 Master 10 Access Register" bitfld.long 0x48 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x48 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x48 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4C "EL1_MSTR_11_3,EL1 Region 3 Master 11 Access Register" bitfld.long 0x4C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x348++0x3 line.long 0x0 "EL1_MSTR_18_3,EL1 Region 3 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x358++0x3 line.long 0x0 "EL1_MSTR_22_3,EL1 Region 3 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x360++0x3 line.long 0x0 "EL1_MSTR_24_3,EL1 Region 3 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x380++0x17 line.long 0x0 "EL1_MSTR_32_3,EL1 Region 3 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_3,EL1 Region 3 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_3,EL1 Region 3 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_3,EL1 Region 3 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_3,EL1 Region 3 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_3,EL1 Region 3 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x39C++0x3 line.long 0x0 "EL1_MSTR_39_3,EL1 Region 3 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x3C0++0x3 line.long 0x0 "EL1_MSTR_48_3,EL1 Region 3 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x3D0++0x7 line.long 0x0 "EL1_MSTR_52_3,EL1 Region 3 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_3,EL1 Region 3 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x3E0++0x4F line.long 0x0 "EL1_MSTR_56_3,EL1 Region 3 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_3,EL1 Region 3 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_3,EL1 Region 3 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_3,EL1 Region 3 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_3,EL1 Region 3 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_3,EL1 Region 3 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_3,EL1 Region 3 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_3,EL1 Region 3 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_4,EL1 Region 4 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_4,EL1 Region 4 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_4,EL1 Region 4 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_4,EL1 Region 4 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x30 "EL1_MSTR_4_4,EL1 Region 4 Master 4 Access Register" bitfld.long 0x30 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x30 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x30 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x34 "EL1_MSTR_5_4,EL1 Region 4 Master 5 Access Register" bitfld.long 0x34 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x34 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x34 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x38 "EL1_MSTR_6_4,EL1 Region 4 Master 6 Access Register" bitfld.long 0x38 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x38 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x38 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x3C "EL1_MSTR_7_4,EL1 Region 4 Master 7 Access Register" bitfld.long 0x3C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x3C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x3C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x40 "EL1_MSTR_8_4,EL1 Region 4 Master 8 Access Register" bitfld.long 0x40 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x40 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x40 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x44 "EL1_MSTR_9_4,EL1 Region 4 Master 9 Access Register" bitfld.long 0x44 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x44 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x44 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x48 "EL1_MSTR_10_4,EL1 Region 4 Master 10 Access Register" bitfld.long 0x48 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x48 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x48 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4C "EL1_MSTR_11_4,EL1 Region 4 Master 11 Access Register" bitfld.long 0x4C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x448++0x3 line.long 0x0 "EL1_MSTR_18_4,EL1 Region 4 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x458++0x3 line.long 0x0 "EL1_MSTR_22_4,EL1 Region 4 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x460++0x3 line.long 0x0 "EL1_MSTR_24_4,EL1 Region 4 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x480++0x17 line.long 0x0 "EL1_MSTR_32_4,EL1 Region 4 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_4,EL1 Region 4 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_4,EL1 Region 4 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_4,EL1 Region 4 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_4,EL1 Region 4 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_4,EL1 Region 4 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x49C++0x3 line.long 0x0 "EL1_MSTR_39_4,EL1 Region 4 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x4C0++0x3 line.long 0x0 "EL1_MSTR_48_4,EL1 Region 4 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x4D0++0x7 line.long 0x0 "EL1_MSTR_52_4,EL1 Region 4 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_4,EL1 Region 4 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x4E0++0x4F line.long 0x0 "EL1_MSTR_56_4,EL1 Region 4 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_4,EL1 Region 4 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_4,EL1 Region 4 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_4,EL1 Region 4 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_4,EL1 Region 4 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_4,EL1 Region 4 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_4,EL1 Region 4 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_4,EL1 Region 4 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_5,EL1 Region 5 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_5,EL1 Region 5 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_5,EL1 Region 5 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_5,EL1 Region 5 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x30 "EL1_MSTR_4_5,EL1 Region 5 Master 4 Access Register" bitfld.long 0x30 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x30 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x30 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x34 "EL1_MSTR_5_5,EL1 Region 5 Master 5 Access Register" bitfld.long 0x34 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x34 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x34 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x38 "EL1_MSTR_6_5,EL1 Region 5 Master 6 Access Register" bitfld.long 0x38 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x38 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x38 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x3C "EL1_MSTR_7_5,EL1 Region 5 Master 7 Access Register" bitfld.long 0x3C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x3C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x3C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x40 "EL1_MSTR_8_5,EL1 Region 5 Master 8 Access Register" bitfld.long 0x40 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x40 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x40 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x44 "EL1_MSTR_9_5,EL1 Region 5 Master 9 Access Register" bitfld.long 0x44 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x44 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x44 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x48 "EL1_MSTR_10_5,EL1 Region 5 Master 10 Access Register" bitfld.long 0x48 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x48 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x48 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4C "EL1_MSTR_11_5,EL1 Region 5 Master 11 Access Register" bitfld.long 0x4C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x548++0x3 line.long 0x0 "EL1_MSTR_18_5,EL1 Region 5 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x558++0x3 line.long 0x0 "EL1_MSTR_22_5,EL1 Region 5 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x560++0x3 line.long 0x0 "EL1_MSTR_24_5,EL1 Region 5 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x580++0x17 line.long 0x0 "EL1_MSTR_32_5,EL1 Region 5 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_5,EL1 Region 5 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_5,EL1 Region 5 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_5,EL1 Region 5 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_5,EL1 Region 5 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_5,EL1 Region 5 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x59C++0x3 line.long 0x0 "EL1_MSTR_39_5,EL1 Region 5 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x5C0++0x3 line.long 0x0 "EL1_MSTR_48_5,EL1 Region 5 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x5D0++0x7 line.long 0x0 "EL1_MSTR_52_5,EL1 Region 5 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_5,EL1 Region 5 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x5E0++0x4F line.long 0x0 "EL1_MSTR_56_5,EL1 Region 5 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_5,EL1 Region 5 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_5,EL1 Region 5 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_5,EL1 Region 5 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_5,EL1 Region 5 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_5,EL1 Region 5 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_5,EL1 Region 5 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_5,EL1 Region 5 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_6,EL1 Region 6 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_6,EL1 Region 6 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_6,EL1 Region 6 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_6,EL1 Region 6 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x30 "EL1_MSTR_4_6,EL1 Region 6 Master 4 Access Register" bitfld.long 0x30 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x30 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x30 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x34 "EL1_MSTR_5_6,EL1 Region 6 Master 5 Access Register" bitfld.long 0x34 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x34 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x34 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x38 "EL1_MSTR_6_6,EL1 Region 6 Master 6 Access Register" bitfld.long 0x38 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x38 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x38 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x3C "EL1_MSTR_7_6,EL1 Region 6 Master 7 Access Register" bitfld.long 0x3C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x3C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x3C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x40 "EL1_MSTR_8_6,EL1 Region 6 Master 8 Access Register" bitfld.long 0x40 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x40 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x40 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x44 "EL1_MSTR_9_6,EL1 Region 6 Master 9 Access Register" bitfld.long 0x44 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x44 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x44 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x48 "EL1_MSTR_10_6,EL1 Region 6 Master 10 Access Register" bitfld.long 0x48 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x48 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x48 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4C "EL1_MSTR_11_6,EL1 Region 6 Master 11 Access Register" bitfld.long 0x4C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x648++0x3 line.long 0x0 "EL1_MSTR_18_6,EL1 Region 6 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x658++0x3 line.long 0x0 "EL1_MSTR_22_6,EL1 Region 6 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x660++0x3 line.long 0x0 "EL1_MSTR_24_6,EL1 Region 6 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x680++0x17 line.long 0x0 "EL1_MSTR_32_6,EL1 Region 6 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_6,EL1 Region 6 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_6,EL1 Region 6 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_6,EL1 Region 6 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_6,EL1 Region 6 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_6,EL1 Region 6 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x69C++0x3 line.long 0x0 "EL1_MSTR_39_6,EL1 Region 6 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x6C0++0x3 line.long 0x0 "EL1_MSTR_48_6,EL1 Region 6 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x6D0++0x7 line.long 0x0 "EL1_MSTR_52_6,EL1 Region 6 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_6,EL1 Region 6 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x6E0++0x4F line.long 0x0 "EL1_MSTR_56_6,EL1 Region 6 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_6,EL1 Region 6 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_6,EL1 Region 6 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_6,EL1 Region 6 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_6,EL1 Region 6 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_6,EL1 Region 6 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_6,EL1 Region 6 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_6,EL1 Region 6 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_7,EL1 Region 7 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_7,EL1 Region 7 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_7,EL1 Region 7 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_7,EL1 Region 7 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x30 "EL1_MSTR_4_7,EL1 Region 7 Master 4 Access Register" bitfld.long 0x30 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x30 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x30 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x34 "EL1_MSTR_5_7,EL1 Region 7 Master 5 Access Register" bitfld.long 0x34 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x34 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x34 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x38 "EL1_MSTR_6_7,EL1 Region 7 Master 6 Access Register" bitfld.long 0x38 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x38 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x38 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x3C "EL1_MSTR_7_7,EL1 Region 7 Master 7 Access Register" bitfld.long 0x3C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x3C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x3C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x40 "EL1_MSTR_8_7,EL1 Region 7 Master 8 Access Register" bitfld.long 0x40 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x40 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x40 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x44 "EL1_MSTR_9_7,EL1 Region 7 Master 9 Access Register" bitfld.long 0x44 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x44 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x44 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x48 "EL1_MSTR_10_7,EL1 Region 7 Master 10 Access Register" bitfld.long 0x48 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x48 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x48 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4C "EL1_MSTR_11_7,EL1 Region 7 Master 11 Access Register" bitfld.long 0x4C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x748++0x3 line.long 0x0 "EL1_MSTR_18_7,EL1 Region 7 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x758++0x3 line.long 0x0 "EL1_MSTR_22_7,EL1 Region 7 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x760++0x3 line.long 0x0 "EL1_MSTR_24_7,EL1 Region 7 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x780++0x17 line.long 0x0 "EL1_MSTR_32_7,EL1 Region 7 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_7,EL1 Region 7 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_7,EL1 Region 7 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_7,EL1 Region 7 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_7,EL1 Region 7 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_7,EL1 Region 7 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x79C++0x3 line.long 0x0 "EL1_MSTR_39_7,EL1 Region 7 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x7C0++0x3 line.long 0x0 "EL1_MSTR_48_7,EL1 Region 7 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x7D0++0x7 line.long 0x0 "EL1_MSTR_52_7,EL1 Region 7 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_7,EL1 Region 7 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x7E0++0x1F line.long 0x0 "EL1_MSTR_56_7,EL1 Region 7 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_7,EL1 Region 7 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_7,EL1 Region 7 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_7,EL1 Region 7 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_7,EL1 Region 7 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_7,EL1 Region 7 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_7,EL1 Region 7 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_7,EL1 Region 7 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "SYSRAM1_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B711200 group.long 0x0++0x2F line.long 0x0 "EL1_MSTR_0_0,EL1 Region 0 Master 0 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_1_0,EL1 Region 0 Master 1 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_2_0,EL1 Region 0 Master 2 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_3_0,EL1 Region 0 Master 3 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_4_0,EL1 Region 0 Master 4 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_5_0,EL1 Region 0 Master 5 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_6_0,EL1 Region 0 Master 6 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_7_0,EL1 Region 0 Master 7 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_8_0,EL1 Region 0 Master 8 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_9_0,EL1 Region 0 Master 9 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_10_0,EL1 Region 0 Master 10 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_11_0,EL1 Region 0 Master 11 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x48++0x3 line.long 0x0 "EL1_MSTR_18_0,EL1 Region 0 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x58++0x3 line.long 0x0 "EL1_MSTR_22_0,EL1 Region 0 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x60++0x3 line.long 0x0 "EL1_MSTR_24_0,EL1 Region 0 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x80++0x17 line.long 0x0 "EL1_MSTR_32_0,EL1 Region 0 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_0,EL1 Region 0 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_0,EL1 Region 0 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_0,EL1 Region 0 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_0,EL1 Region 0 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_0,EL1 Region 0 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x9C++0x3 line.long 0x0 "EL1_MSTR_39_0,EL1 Region 0 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xC0++0x3 line.long 0x0 "EL1_MSTR_48_0,EL1 Region 0 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xD0++0x7 line.long 0x0 "EL1_MSTR_52_0,EL1 Region 0 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_0,EL1 Region 0 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0xE0++0x4F line.long 0x0 "EL1_MSTR_56_0,EL1 Region 0 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_0,EL1 Region 0 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_0,EL1 Region 0 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_0,EL1 Region 0 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_0,EL1 Region 0 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_0,EL1 Region 0 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_0,EL1 Region 0 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_0,EL1 Region 0 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_1,EL1 Region 1 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_1,EL1 Region 1 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_1,EL1 Region 1 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_1,EL1 Region 1 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x30 "EL1_MSTR_4_1,EL1 Region 1 Master 4 Access Register" bitfld.long 0x30 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x30 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x30 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x34 "EL1_MSTR_5_1,EL1 Region 1 Master 5 Access Register" bitfld.long 0x34 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x34 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x34 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x38 "EL1_MSTR_6_1,EL1 Region 1 Master 6 Access Register" bitfld.long 0x38 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x38 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x38 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x3C "EL1_MSTR_7_1,EL1 Region 1 Master 7 Access Register" bitfld.long 0x3C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x3C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x3C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x40 "EL1_MSTR_8_1,EL1 Region 1 Master 8 Access Register" bitfld.long 0x40 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x40 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x40 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x44 "EL1_MSTR_9_1,EL1 Region 1 Master 9 Access Register" bitfld.long 0x44 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x44 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x44 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x48 "EL1_MSTR_10_1,EL1 Region 1 Master 10 Access Register" bitfld.long 0x48 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x48 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x48 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4C "EL1_MSTR_11_1,EL1 Region 1 Master 11 Access Register" bitfld.long 0x4C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x148++0x3 line.long 0x0 "EL1_MSTR_18_1,EL1 Region 1 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x158++0x3 line.long 0x0 "EL1_MSTR_22_1,EL1 Region 1 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x160++0x3 line.long 0x0 "EL1_MSTR_24_1,EL1 Region 1 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x180++0x17 line.long 0x0 "EL1_MSTR_32_1,EL1 Region 1 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_1,EL1 Region 1 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_1,EL1 Region 1 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_1,EL1 Region 1 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_1,EL1 Region 1 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_1,EL1 Region 1 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x19C++0x3 line.long 0x0 "EL1_MSTR_39_1,EL1 Region 1 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1C0++0x3 line.long 0x0 "EL1_MSTR_48_1,EL1 Region 1 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1D0++0x7 line.long 0x0 "EL1_MSTR_52_1,EL1 Region 1 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_1,EL1 Region 1 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1E0++0x4F line.long 0x0 "EL1_MSTR_56_1,EL1 Region 1 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_1,EL1 Region 1 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_1,EL1 Region 1 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_1,EL1 Region 1 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_1,EL1 Region 1 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_1,EL1 Region 1 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_1,EL1 Region 1 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_1,EL1 Region 1 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_2,EL1 Region 2 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_2,EL1 Region 2 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_2,EL1 Region 2 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_2,EL1 Region 2 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x30 "EL1_MSTR_4_2,EL1 Region 2 Master 4 Access Register" bitfld.long 0x30 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x30 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x30 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x34 "EL1_MSTR_5_2,EL1 Region 2 Master 5 Access Register" bitfld.long 0x34 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x34 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x34 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x38 "EL1_MSTR_6_2,EL1 Region 2 Master 6 Access Register" bitfld.long 0x38 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x38 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x38 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x3C "EL1_MSTR_7_2,EL1 Region 2 Master 7 Access Register" bitfld.long 0x3C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x3C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x3C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x40 "EL1_MSTR_8_2,EL1 Region 2 Master 8 Access Register" bitfld.long 0x40 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x40 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x40 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x44 "EL1_MSTR_9_2,EL1 Region 2 Master 9 Access Register" bitfld.long 0x44 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x44 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x44 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x48 "EL1_MSTR_10_2,EL1 Region 2 Master 10 Access Register" bitfld.long 0x48 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x48 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x48 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4C "EL1_MSTR_11_2,EL1 Region 2 Master 11 Access Register" bitfld.long 0x4C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x248++0x3 line.long 0x0 "EL1_MSTR_18_2,EL1 Region 2 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x258++0x3 line.long 0x0 "EL1_MSTR_22_2,EL1 Region 2 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x260++0x3 line.long 0x0 "EL1_MSTR_24_2,EL1 Region 2 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x280++0x17 line.long 0x0 "EL1_MSTR_32_2,EL1 Region 2 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_2,EL1 Region 2 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_2,EL1 Region 2 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_2,EL1 Region 2 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_2,EL1 Region 2 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_2,EL1 Region 2 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x29C++0x3 line.long 0x0 "EL1_MSTR_39_2,EL1 Region 2 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x2C0++0x3 line.long 0x0 "EL1_MSTR_48_2,EL1 Region 2 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x2D0++0x7 line.long 0x0 "EL1_MSTR_52_2,EL1 Region 2 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_2,EL1 Region 2 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x2E0++0x4F line.long 0x0 "EL1_MSTR_56_2,EL1 Region 2 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_2,EL1 Region 2 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_2,EL1 Region 2 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_2,EL1 Region 2 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_2,EL1 Region 2 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_2,EL1 Region 2 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_2,EL1 Region 2 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_2,EL1 Region 2 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_3,EL1 Region 3 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_3,EL1 Region 3 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_3,EL1 Region 3 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_3,EL1 Region 3 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x30 "EL1_MSTR_4_3,EL1 Region 3 Master 4 Access Register" bitfld.long 0x30 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x30 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x30 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x34 "EL1_MSTR_5_3,EL1 Region 3 Master 5 Access Register" bitfld.long 0x34 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x34 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x34 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x38 "EL1_MSTR_6_3,EL1 Region 3 Master 6 Access Register" bitfld.long 0x38 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x38 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x38 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x3C "EL1_MSTR_7_3,EL1 Region 3 Master 7 Access Register" bitfld.long 0x3C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x3C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x3C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x40 "EL1_MSTR_8_3,EL1 Region 3 Master 8 Access Register" bitfld.long 0x40 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x40 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x40 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x44 "EL1_MSTR_9_3,EL1 Region 3 Master 9 Access Register" bitfld.long 0x44 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x44 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x44 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x48 "EL1_MSTR_10_3,EL1 Region 3 Master 10 Access Register" bitfld.long 0x48 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x48 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x48 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4C "EL1_MSTR_11_3,EL1 Region 3 Master 11 Access Register" bitfld.long 0x4C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x348++0x3 line.long 0x0 "EL1_MSTR_18_3,EL1 Region 3 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x358++0x3 line.long 0x0 "EL1_MSTR_22_3,EL1 Region 3 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x360++0x3 line.long 0x0 "EL1_MSTR_24_3,EL1 Region 3 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x380++0x17 line.long 0x0 "EL1_MSTR_32_3,EL1 Region 3 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_3,EL1 Region 3 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_3,EL1 Region 3 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_3,EL1 Region 3 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_3,EL1 Region 3 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_3,EL1 Region 3 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x39C++0x3 line.long 0x0 "EL1_MSTR_39_3,EL1 Region 3 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x3C0++0x3 line.long 0x0 "EL1_MSTR_48_3,EL1 Region 3 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x3D0++0x7 line.long 0x0 "EL1_MSTR_52_3,EL1 Region 3 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_3,EL1 Region 3 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x3E0++0x4F line.long 0x0 "EL1_MSTR_56_3,EL1 Region 3 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_3,EL1 Region 3 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_3,EL1 Region 3 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_3,EL1 Region 3 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_3,EL1 Region 3 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_3,EL1 Region 3 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_3,EL1 Region 3 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_3,EL1 Region 3 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_4,EL1 Region 4 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_4,EL1 Region 4 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_4,EL1 Region 4 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_4,EL1 Region 4 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x30 "EL1_MSTR_4_4,EL1 Region 4 Master 4 Access Register" bitfld.long 0x30 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x30 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x30 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x34 "EL1_MSTR_5_4,EL1 Region 4 Master 5 Access Register" bitfld.long 0x34 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x34 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x34 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x38 "EL1_MSTR_6_4,EL1 Region 4 Master 6 Access Register" bitfld.long 0x38 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x38 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x38 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x3C "EL1_MSTR_7_4,EL1 Region 4 Master 7 Access Register" bitfld.long 0x3C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x3C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x3C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x40 "EL1_MSTR_8_4,EL1 Region 4 Master 8 Access Register" bitfld.long 0x40 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x40 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x40 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x44 "EL1_MSTR_9_4,EL1 Region 4 Master 9 Access Register" bitfld.long 0x44 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x44 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x44 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x48 "EL1_MSTR_10_4,EL1 Region 4 Master 10 Access Register" bitfld.long 0x48 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x48 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x48 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4C "EL1_MSTR_11_4,EL1 Region 4 Master 11 Access Register" bitfld.long 0x4C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x448++0x3 line.long 0x0 "EL1_MSTR_18_4,EL1 Region 4 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x458++0x3 line.long 0x0 "EL1_MSTR_22_4,EL1 Region 4 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x460++0x3 line.long 0x0 "EL1_MSTR_24_4,EL1 Region 4 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x480++0x17 line.long 0x0 "EL1_MSTR_32_4,EL1 Region 4 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_4,EL1 Region 4 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_4,EL1 Region 4 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_4,EL1 Region 4 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_4,EL1 Region 4 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_4,EL1 Region 4 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x49C++0x3 line.long 0x0 "EL1_MSTR_39_4,EL1 Region 4 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x4C0++0x3 line.long 0x0 "EL1_MSTR_48_4,EL1 Region 4 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x4D0++0x7 line.long 0x0 "EL1_MSTR_52_4,EL1 Region 4 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_4,EL1 Region 4 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x4E0++0x4F line.long 0x0 "EL1_MSTR_56_4,EL1 Region 4 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_4,EL1 Region 4 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_4,EL1 Region 4 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_4,EL1 Region 4 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_4,EL1 Region 4 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_4,EL1 Region 4 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_4,EL1 Region 4 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_4,EL1 Region 4 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_5,EL1 Region 5 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_5,EL1 Region 5 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_5,EL1 Region 5 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_5,EL1 Region 5 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x30 "EL1_MSTR_4_5,EL1 Region 5 Master 4 Access Register" bitfld.long 0x30 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x30 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x30 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x34 "EL1_MSTR_5_5,EL1 Region 5 Master 5 Access Register" bitfld.long 0x34 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x34 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x34 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x38 "EL1_MSTR_6_5,EL1 Region 5 Master 6 Access Register" bitfld.long 0x38 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x38 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x38 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x3C "EL1_MSTR_7_5,EL1 Region 5 Master 7 Access Register" bitfld.long 0x3C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x3C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x3C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x40 "EL1_MSTR_8_5,EL1 Region 5 Master 8 Access Register" bitfld.long 0x40 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x40 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x40 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x44 "EL1_MSTR_9_5,EL1 Region 5 Master 9 Access Register" bitfld.long 0x44 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x44 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x44 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x48 "EL1_MSTR_10_5,EL1 Region 5 Master 10 Access Register" bitfld.long 0x48 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x48 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x48 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4C "EL1_MSTR_11_5,EL1 Region 5 Master 11 Access Register" bitfld.long 0x4C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x548++0x3 line.long 0x0 "EL1_MSTR_18_5,EL1 Region 5 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x558++0x3 line.long 0x0 "EL1_MSTR_22_5,EL1 Region 5 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x560++0x3 line.long 0x0 "EL1_MSTR_24_5,EL1 Region 5 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x580++0x17 line.long 0x0 "EL1_MSTR_32_5,EL1 Region 5 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_5,EL1 Region 5 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_5,EL1 Region 5 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_5,EL1 Region 5 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_5,EL1 Region 5 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_5,EL1 Region 5 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x59C++0x3 line.long 0x0 "EL1_MSTR_39_5,EL1 Region 5 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x5C0++0x3 line.long 0x0 "EL1_MSTR_48_5,EL1 Region 5 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x5D0++0x7 line.long 0x0 "EL1_MSTR_52_5,EL1 Region 5 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_5,EL1 Region 5 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x5E0++0x4F line.long 0x0 "EL1_MSTR_56_5,EL1 Region 5 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_5,EL1 Region 5 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_5,EL1 Region 5 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_5,EL1 Region 5 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_5,EL1 Region 5 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_5,EL1 Region 5 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_5,EL1 Region 5 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_5,EL1 Region 5 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_6,EL1 Region 6 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_6,EL1 Region 6 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_6,EL1 Region 6 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_6,EL1 Region 6 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x30 "EL1_MSTR_4_6,EL1 Region 6 Master 4 Access Register" bitfld.long 0x30 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x30 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x30 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x34 "EL1_MSTR_5_6,EL1 Region 6 Master 5 Access Register" bitfld.long 0x34 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x34 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x34 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x38 "EL1_MSTR_6_6,EL1 Region 6 Master 6 Access Register" bitfld.long 0x38 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x38 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x38 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x3C "EL1_MSTR_7_6,EL1 Region 6 Master 7 Access Register" bitfld.long 0x3C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x3C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x3C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x40 "EL1_MSTR_8_6,EL1 Region 6 Master 8 Access Register" bitfld.long 0x40 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x40 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x40 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x44 "EL1_MSTR_9_6,EL1 Region 6 Master 9 Access Register" bitfld.long 0x44 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x44 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x44 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x48 "EL1_MSTR_10_6,EL1 Region 6 Master 10 Access Register" bitfld.long 0x48 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x48 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x48 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4C "EL1_MSTR_11_6,EL1 Region 6 Master 11 Access Register" bitfld.long 0x4C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x648++0x3 line.long 0x0 "EL1_MSTR_18_6,EL1 Region 6 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x658++0x3 line.long 0x0 "EL1_MSTR_22_6,EL1 Region 6 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x660++0x3 line.long 0x0 "EL1_MSTR_24_6,EL1 Region 6 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x680++0x17 line.long 0x0 "EL1_MSTR_32_6,EL1 Region 6 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_6,EL1 Region 6 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_6,EL1 Region 6 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_6,EL1 Region 6 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_6,EL1 Region 6 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_6,EL1 Region 6 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x69C++0x3 line.long 0x0 "EL1_MSTR_39_6,EL1 Region 6 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x6C0++0x3 line.long 0x0 "EL1_MSTR_48_6,EL1 Region 6 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x6D0++0x7 line.long 0x0 "EL1_MSTR_52_6,EL1 Region 6 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_6,EL1 Region 6 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x6E0++0x4F line.long 0x0 "EL1_MSTR_56_6,EL1 Region 6 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_6,EL1 Region 6 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_6,EL1 Region 6 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_6,EL1 Region 6 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_6,EL1 Region 6 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_6,EL1 Region 6 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_6,EL1 Region 6 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_6,EL1 Region 6 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x20 "EL1_MSTR_0_7,EL1 Region 7 Master 0 Access Register" bitfld.long 0x20 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x20 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x20 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x24 "EL1_MSTR_1_7,EL1 Region 7 Master 1 Access Register" bitfld.long 0x24 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x24 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x24 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x28 "EL1_MSTR_2_7,EL1 Region 7 Master 2 Access Register" bitfld.long 0x28 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x28 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x28 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x2C "EL1_MSTR_3_7,EL1 Region 7 Master 3 Access Register" bitfld.long 0x2C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x2C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x2C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x30 "EL1_MSTR_4_7,EL1 Region 7 Master 4 Access Register" bitfld.long 0x30 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x30 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x30 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x34 "EL1_MSTR_5_7,EL1 Region 7 Master 5 Access Register" bitfld.long 0x34 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x34 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x34 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x38 "EL1_MSTR_6_7,EL1 Region 7 Master 6 Access Register" bitfld.long 0x38 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x38 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x38 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x3C "EL1_MSTR_7_7,EL1 Region 7 Master 7 Access Register" bitfld.long 0x3C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x3C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x3C 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x40 "EL1_MSTR_8_7,EL1 Region 7 Master 8 Access Register" bitfld.long 0x40 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x40 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x40 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x44 "EL1_MSTR_9_7,EL1 Region 7 Master 9 Access Register" bitfld.long 0x44 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x44 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x44 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x48 "EL1_MSTR_10_7,EL1 Region 7 Master 10 Access Register" bitfld.long 0x48 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x48 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x48 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4C "EL1_MSTR_11_7,EL1 Region 7 Master 11 Access Register" bitfld.long 0x4C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4C 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x748++0x3 line.long 0x0 "EL1_MSTR_18_7,EL1 Region 7 Master 18 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x758++0x3 line.long 0x0 "EL1_MSTR_22_7,EL1 Region 7 Master 22 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x760++0x3 line.long 0x0 "EL1_MSTR_24_7,EL1 Region 7 Master 24 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x780++0x17 line.long 0x0 "EL1_MSTR_32_7,EL1 Region 7 Master 32 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_33_7,EL1 Region 7 Master 33 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_34_7,EL1 Region 7 Master 34 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_35_7,EL1 Region 7 Master 35 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_36_7,EL1 Region 7 Master 36 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_37_7,EL1 Region 7 Master 37 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x79C++0x3 line.long 0x0 "EL1_MSTR_39_7,EL1 Region 7 Master 39 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x7C0++0x3 line.long 0x0 "EL1_MSTR_48_7,EL1 Region 7 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x7D0++0x7 line.long 0x0 "EL1_MSTR_52_7,EL1 Region 7 Master 52 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_53_7,EL1 Region 7 Master 53 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x7E0++0x1F line.long 0x0 "EL1_MSTR_56_7,EL1 Region 7 Master 56 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x4 "EL1_MSTR_57_7,EL1 Region 7 Master 57 Access Register" bitfld.long 0x4 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x4 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x4 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x8 "EL1_MSTR_58_7,EL1 Region 7 Master 58 Access Register" bitfld.long 0x8 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x8 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x8 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0xC "EL1_MSTR_59_7,EL1 Region 7 Master 59 Access Register" bitfld.long 0xC 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0xC 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0xC 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x10 "EL1_MSTR_60_7,EL1 Region 7 Master 60 Access Register" bitfld.long 0x10 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x10 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x10 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x14 "EL1_MSTR_61_7,EL1 Region 7 Master 61 Access Register" bitfld.long 0x14 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x14 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x18 "EL1_MSTR_62_7,EL1 Region 7 Master 62 Access Register" bitfld.long 0x18 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x18 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x18 0. "EL1_RD_ACC,User mode read permission." "0,1" line.long 0x1C "EL1_MSTR_63_7,EL1 Region 7 Master 63 Access Register" bitfld.long 0x1C 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x1C 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x1C 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "TMC0_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B781200 group.long 0xC0++0x3 line.long 0x0 "EL1_MSTR_48_0,EL1 Region 0 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1C0++0x3 line.long 0x0 "EL1_MSTR_48_1,EL1 Region 1 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "TMC1_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B7B1200 group.long 0xC0++0x3 line.long 0x0 "EL1_MSTR_48_0,EL1 Region 0 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1C0++0x3 line.long 0x0 "EL1_MSTR_48_1,EL1 Region 1 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree "TMC2_FIREWALL_CORE_FIREWALL_EL1_ACC_ADR" base ad:0x7B7D1200 group.long 0xC0++0x3 line.long 0x0 "EL1_MSTR_48_0,EL1 Region 0 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" group.long 0x1C0++0x3 line.long 0x0 "EL1_MSTR_48_1,EL1 Region 1 Master 48 Access Register" bitfld.long 0x0 2. "EL1_X_ACC,User mode execute permission." "0,1" bitfld.long 0x0 1. "EL1_WR_ACC,User mode write permission." "0,1" bitfld.long 0x0 0. "EL1_RD_ACC,User mode read permission." "0,1" tree.end tree.end tree "FIREWALL_EL2" tree "AESLIGHT1_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B630200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "AESLIGHT2_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B640200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "AESLIGHT3_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B650200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "AIPS0_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B660200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "AIPS1_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B670200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "AIPS2_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B680200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "AIPS3_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B690200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "AIPS4_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B6A0200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "DAP_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B6B0200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "DFA_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B790200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x40++0x27 line.long 0x0 "EL2_ADDR_START_1,EL2 Start Address Register Region_1" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_1,EL2 Region 1 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_1,EL2 Region 1 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_1,EL2 Region 1 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_1,EL2 Region 1 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_1,EL2 Region 1 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_1,EL2 Region 1 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_1,EL2 Region 1 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_1,EL2 Region 1 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_1,EL2 Region 1 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "DME_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B6C0200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x40++0x27 line.long 0x0 "EL2_ADDR_START_1,EL2 Start Address Register Region_1" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_1,EL2 Region 1 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_1,EL2 Region 1 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_1,EL2 Region 1 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_1,EL2 Region 1 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_1,EL2 Region 1 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_1,EL2 Region 1 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_1,EL2 Region 1 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_1,EL2 Region 1 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_1,EL2 Region 1 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "DSPH_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B6D0200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x40++0x27 line.long 0x0 "EL2_ADDR_START_1,EL2 Start Address Register Region_1" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_1,EL2 Region 1 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_1,EL2 Region 1 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_1,EL2 Region 1 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_1,EL2 Region 1 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_1,EL2 Region 1 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_1,EL2 Region 1 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_1,EL2 Region 1 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_1,EL2 Region 1 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_1,EL2 Region 1 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "FIREWALL_EL2_ADR" base ad:0x7B620200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "GTM_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B740200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x40++0x27 line.long 0x0 "EL2_ADDR_START_1,EL2 Start Address Register Region_1" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_1,EL2 Region 1 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_1,EL2 Region 1 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_1,EL2 Region 1 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_1,EL2 Region 1 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_1,EL2 Region 1 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_1,EL2 Region 1 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_1,EL2 Region 1 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_1,EL2 Region 1 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_1,EL2 Region 1 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x80++0x27 line.long 0x0 "EL2_ADDR_START_2,EL2 Start Address Register Region_2" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_2,EL2 Region 2 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_2,EL2 Region 2 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_2,EL2 Region 2 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_2,EL2 Region 2 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_2,EL2 Region 2 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_2,EL2 Region 2 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_2,EL2 Region 2 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_2,EL2 Region 2 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_2,EL2 Region 2 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0xC0++0x27 line.long 0x0 "EL2_ADDR_START_3,EL2 Start Address Register Region_3" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_3,EL2 Region 3 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_3,EL2 Region 3 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_3,EL2 Region 3 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_3,EL2 Region 3 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_3,EL2 Region 3 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_3,EL2 Region 3 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_3,EL2 Region 3 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_3,EL2 Region 3 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_3,EL2 Region 3 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "HSM_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B750200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x40++0x27 line.long 0x0 "EL2_ADDR_START_1,EL2 Start Address Register Region_1" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_1,EL2 Region 1 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_1,EL2 Region 1 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_1,EL2 Region 1 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_1,EL2 Region 1 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_1,EL2 Region 1 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_1,EL2 Region 1 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_1,EL2 Region 1 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_1,EL2 Region 1 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_1,EL2 Region 1 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "KITE0_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B770200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x40++0x27 line.long 0x0 "EL2_ADDR_START_1,EL2 Start Address Register Region_1" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_1,EL2 Region 1 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_1,EL2 Region 1 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_1,EL2 Region 1 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_1,EL2 Region 1 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_1,EL2 Region 1 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_1,EL2 Region 1 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_1,EL2 Region 1 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_1,EL2 Region 1 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_1,EL2 Region 1 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x80++0x27 line.long 0x0 "EL2_ADDR_START_2,EL2 Start Address Register Region_2" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_2,EL2 Region 2 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_2,EL2 Region 2 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_2,EL2 Region 2 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_2,EL2 Region 2 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_2,EL2 Region 2 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_2,EL2 Region 2 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_2,EL2 Region 2 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_2,EL2 Region 2 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_2,EL2 Region 2 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0xC0++0x27 line.long 0x0 "EL2_ADDR_START_3,EL2 Start Address Register Region_3" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_3,EL2 Region 3 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_3,EL2 Region 3 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_3,EL2 Region 3 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_3,EL2 Region 3 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_3,EL2 Region 3 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_3,EL2 Region 3 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_3,EL2 Region 3 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_3,EL2 Region 3 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_3,EL2 Region 3 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x100++0x27 line.long 0x0 "EL2_ADDR_START_4,EL2 Start Address Register Region_4" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_4,EL2 Region 4 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_4,EL2 Region 4 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_4,EL2 Region 4 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_4,EL2 Region 4 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_4,EL2 Region 4 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_4,EL2 Region 4 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_4,EL2 Region 4 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_4,EL2 Region 4 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_4,EL2 Region 4 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x140++0x27 line.long 0x0 "EL2_ADDR_START_5,EL2 Start Address Register Region_5" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_5,EL2 Region 5 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_5,EL2 Region 5 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_5,EL2 Region 5 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_5,EL2 Region 5 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_5,EL2 Region 5 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_5,EL2 Region 5 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_5,EL2 Region 5 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_5,EL2 Region 5 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_5,EL2 Region 5 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x180++0x27 line.long 0x0 "EL2_ADDR_START_6,EL2 Start Address Register Region_6" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_6,EL2 Region 6 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_6,EL2 Region 6 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_6,EL2 Region 6 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_6,EL2 Region 6 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_6,EL2 Region 6 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_6,EL2 Region 6 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_6,EL2 Region 6 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_6,EL2 Region 6 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_6,EL2 Region 6 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x1C0++0x27 line.long 0x0 "EL2_ADDR_START_7,EL2 Start Address Register Region_7" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_7,EL2 Region 7 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_7,EL2 Region 7 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_7,EL2 Region 7 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_7,EL2 Region 7 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_7,EL2 Region 7 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_7,EL2 Region 7 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_7,EL2 Region 7 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_7,EL2 Region 7 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_7,EL2 Region 7 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "KITE1_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B7A0200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x40++0x27 line.long 0x0 "EL2_ADDR_START_1,EL2 Start Address Register Region_1" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_1,EL2 Region 1 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_1,EL2 Region 1 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_1,EL2 Region 1 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_1,EL2 Region 1 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_1,EL2 Region 1 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_1,EL2 Region 1 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_1,EL2 Region 1 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_1,EL2 Region 1 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_1,EL2 Region 1 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x80++0x27 line.long 0x0 "EL2_ADDR_START_2,EL2 Start Address Register Region_2" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_2,EL2 Region 2 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_2,EL2 Region 2 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_2,EL2 Region 2 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_2,EL2 Region 2 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_2,EL2 Region 2 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_2,EL2 Region 2 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_2,EL2 Region 2 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_2,EL2 Region 2 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_2,EL2 Region 2 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0xC0++0x27 line.long 0x0 "EL2_ADDR_START_3,EL2 Start Address Register Region_3" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_3,EL2 Region 3 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_3,EL2 Region 3 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_3,EL2 Region 3 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_3,EL2 Region 3 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_3,EL2 Region 3 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_3,EL2 Region 3 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_3,EL2 Region 3 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_3,EL2 Region 3 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_3,EL2 Region 3 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x100++0x27 line.long 0x0 "EL2_ADDR_START_4,EL2 Start Address Register Region_4" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_4,EL2 Region 4 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_4,EL2 Region 4 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_4,EL2 Region 4 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_4,EL2 Region 4 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_4,EL2 Region 4 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_4,EL2 Region 4 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_4,EL2 Region 4 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_4,EL2 Region 4 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_4,EL2 Region 4 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x140++0x27 line.long 0x0 "EL2_ADDR_START_5,EL2 Start Address Register Region_5" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_5,EL2 Region 5 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_5,EL2 Region 5 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_5,EL2 Region 5 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_5,EL2 Region 5 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_5,EL2 Region 5 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_5,EL2 Region 5 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_5,EL2 Region 5 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_5,EL2 Region 5 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_5,EL2 Region 5 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x180++0x27 line.long 0x0 "EL2_ADDR_START_6,EL2 Start Address Register Region_6" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_6,EL2 Region 6 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_6,EL2 Region 6 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_6,EL2 Region 6 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_6,EL2 Region 6 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_6,EL2 Region 6 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_6,EL2 Region 6 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_6,EL2 Region 6 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_6,EL2 Region 6 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_6,EL2 Region 6 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x1C0++0x27 line.long 0x0 "EL2_ADDR_START_7,EL2 Start Address Register Region_7" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_7,EL2 Region 7 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_7,EL2 Region 7 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_7,EL2 Region 7 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_7,EL2 Region 7 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_7,EL2 Region 7 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_7,EL2 Region 7 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_7,EL2 Region 7 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_7,EL2 Region 7 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_7,EL2 Region 7 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "KITE2_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B7C0200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x40++0x27 line.long 0x0 "EL2_ADDR_START_1,EL2 Start Address Register Region_1" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_1,EL2 Region 1 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_1,EL2 Region 1 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_1,EL2 Region 1 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_1,EL2 Region 1 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_1,EL2 Region 1 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_1,EL2 Region 1 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_1,EL2 Region 1 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_1,EL2 Region 1 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_1,EL2 Region 1 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x80++0x27 line.long 0x0 "EL2_ADDR_START_2,EL2 Start Address Register Region_2" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_2,EL2 Region 2 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_2,EL2 Region 2 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_2,EL2 Region 2 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_2,EL2 Region 2 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_2,EL2 Region 2 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_2,EL2 Region 2 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_2,EL2 Region 2 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_2,EL2 Region 2 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_2,EL2 Region 2 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0xC0++0x27 line.long 0x0 "EL2_ADDR_START_3,EL2 Start Address Register Region_3" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_3,EL2 Region 3 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_3,EL2 Region 3 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_3,EL2 Region 3 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_3,EL2 Region 3 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_3,EL2 Region 3 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_3,EL2 Region 3 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_3,EL2 Region 3 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_3,EL2 Region 3 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_3,EL2 Region 3 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x100++0x27 line.long 0x0 "EL2_ADDR_START_4,EL2 Start Address Register Region_4" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_4,EL2 Region 4 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_4,EL2 Region 4 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_4,EL2 Region 4 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_4,EL2 Region 4 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_4,EL2 Region 4 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_4,EL2 Region 4 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_4,EL2 Region 4 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_4,EL2 Region 4 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_4,EL2 Region 4 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x140++0x27 line.long 0x0 "EL2_ADDR_START_5,EL2 Start Address Register Region_5" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_5,EL2 Region 5 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_5,EL2 Region 5 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_5,EL2 Region 5 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_5,EL2 Region 5 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_5,EL2 Region 5 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_5,EL2 Region 5 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_5,EL2 Region 5 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_5,EL2 Region 5 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_5,EL2 Region 5 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x180++0x27 line.long 0x0 "EL2_ADDR_START_6,EL2 Start Address Register Region_6" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_6,EL2 Region 6 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_6,EL2 Region 6 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_6,EL2 Region 6 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_6,EL2 Region 6 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_6,EL2 Region 6 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_6,EL2 Region 6 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_6,EL2 Region 6 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_6,EL2 Region 6 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_6,EL2 Region 6 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x1C0++0x27 line.long 0x0 "EL2_ADDR_START_7,EL2 Start Address Register Region_7" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_7,EL2 Region 7 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_7,EL2 Region 7 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_7,EL2 Region 7 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_7,EL2 Region 7 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_7,EL2 Region 7 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_7,EL2 Region 7 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_7,EL2 Region 7 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_7,EL2 Region 7 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_7,EL2 Region 7 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "NVM_WR_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B760200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x40++0x27 line.long 0x0 "EL2_ADDR_START_1,EL2 Start Address Register Region_1" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_1,EL2 Region 1 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_1,EL2 Region 1 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_1,EL2 Region 1 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_1,EL2 Region 1 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_1,EL2 Region 1 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_1,EL2 Region 1 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_1,EL2 Region 1 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_1,EL2 Region 1 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_1,EL2 Region 1 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x80++0x27 line.long 0x0 "EL2_ADDR_START_2,EL2 Start Address Register Region_2" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_2,EL2 Region 2 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_2,EL2 Region 2 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_2,EL2 Region 2 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_2,EL2 Region 2 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_2,EL2 Region 2 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_2,EL2 Region 2 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_2,EL2 Region 2 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_2,EL2 Region 2 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_2,EL2 Region 2 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0xC0++0x27 line.long 0x0 "EL2_ADDR_START_3,EL2 Start Address Register Region_3" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_3,EL2 Region 3 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_3,EL2 Region 3 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_3,EL2 Region 3 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_3,EL2 Region 3 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_3,EL2 Region 3 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_3,EL2 Region 3 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_3,EL2 Region 3 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_3,EL2 Region 3 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_3,EL2 Region 3 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "OCT_SPI_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B720200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "PCIE0_CFG_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B6E0200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x40++0x27 line.long 0x0 "EL2_ADDR_START_1,EL2 Start Address Register Region_1" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_1,EL2 Region 1 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_1,EL2 Region 1 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_1,EL2 Region 1 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_1,EL2 Region 1 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_1,EL2 Region 1 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_1,EL2 Region 1 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_1,EL2 Region 1 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_1,EL2 Region 1 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_1,EL2 Region 1 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x80++0x27 line.long 0x0 "EL2_ADDR_START_2,EL2 Start Address Register Region_2" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_2,EL2 Region 2 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_2,EL2 Region 2 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_2,EL2 Region 2 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_2,EL2 Region 2 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_2,EL2 Region 2 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_2,EL2 Region 2 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_2,EL2 Region 2 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_2,EL2 Region 2 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_2,EL2 Region 2 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "PCIE0_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B600200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x40++0x27 line.long 0x0 "EL2_ADDR_START_1,EL2 Start Address Register Region_1" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_1,EL2 Region 1 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_1,EL2 Region 1 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_1,EL2 Region 1 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_1,EL2 Region 1 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_1,EL2 Region 1 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_1,EL2 Region 1 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_1,EL2 Region 1 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_1,EL2 Region 1 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_1,EL2 Region 1 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x80++0x27 line.long 0x0 "EL2_ADDR_START_2,EL2 Start Address Register Region_2" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_2,EL2 Region 2 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_2,EL2 Region 2 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_2,EL2 Region 2 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_2,EL2 Region 2 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_2,EL2 Region 2 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_2,EL2 Region 2 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_2,EL2 Region 2 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_2,EL2 Region 2 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_2,EL2 Region 2 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "PCIE1_CFG_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B6F0200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x40++0x27 line.long 0x0 "EL2_ADDR_START_1,EL2 Start Address Register Region_1" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_1,EL2 Region 1 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_1,EL2 Region 1 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_1,EL2 Region 1 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_1,EL2 Region 1 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_1,EL2 Region 1 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_1,EL2 Region 1 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_1,EL2 Region 1 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_1,EL2 Region 1 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_1,EL2 Region 1 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x80++0x27 line.long 0x0 "EL2_ADDR_START_2,EL2 Start Address Register Region_2" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_2,EL2 Region 2 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_2,EL2 Region 2 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_2,EL2 Region 2 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_2,EL2 Region 2 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_2,EL2 Region 2 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_2,EL2 Region 2 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_2,EL2 Region 2 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_2,EL2 Region 2 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_2,EL2 Region 2 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "PCIE1_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B610200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x40++0x27 line.long 0x0 "EL2_ADDR_START_1,EL2 Start Address Register Region_1" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_1,EL2 Region 1 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_1,EL2 Region 1 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_1,EL2 Region 1 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_1,EL2 Region 1 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_1,EL2 Region 1 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_1,EL2 Region 1 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_1,EL2 Region 1 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_1,EL2 Region 1 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_1,EL2 Region 1 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x80++0x27 line.long 0x0 "EL2_ADDR_START_2,EL2 Start Address Register Region_2" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_2,EL2 Region 2 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_2,EL2 Region 2 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_2,EL2 Region 2 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_2,EL2 Region 2 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_2,EL2 Region 2 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_2,EL2 Region 2 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_2,EL2 Region 2 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_2,EL2 Region 2 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_2,EL2 Region 2 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "SDMMC_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B730200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "SYSRAM0_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B700200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x40++0x27 line.long 0x0 "EL2_ADDR_START_1,EL2 Start Address Register Region_1" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_1,EL2 Region 1 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_1,EL2 Region 1 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_1,EL2 Region 1 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_1,EL2 Region 1 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_1,EL2 Region 1 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_1,EL2 Region 1 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_1,EL2 Region 1 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_1,EL2 Region 1 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_1,EL2 Region 1 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x80++0x27 line.long 0x0 "EL2_ADDR_START_2,EL2 Start Address Register Region_2" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_2,EL2 Region 2 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_2,EL2 Region 2 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_2,EL2 Region 2 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_2,EL2 Region 2 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_2,EL2 Region 2 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_2,EL2 Region 2 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_2,EL2 Region 2 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_2,EL2 Region 2 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_2,EL2 Region 2 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0xC0++0x27 line.long 0x0 "EL2_ADDR_START_3,EL2 Start Address Register Region_3" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_3,EL2 Region 3 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_3,EL2 Region 3 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_3,EL2 Region 3 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_3,EL2 Region 3 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_3,EL2 Region 3 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_3,EL2 Region 3 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_3,EL2 Region 3 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_3,EL2 Region 3 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_3,EL2 Region 3 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x100++0x27 line.long 0x0 "EL2_ADDR_START_4,EL2 Start Address Register Region_4" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_4,EL2 Region 4 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_4,EL2 Region 4 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_4,EL2 Region 4 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_4,EL2 Region 4 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_4,EL2 Region 4 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_4,EL2 Region 4 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_4,EL2 Region 4 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_4,EL2 Region 4 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_4,EL2 Region 4 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x140++0x27 line.long 0x0 "EL2_ADDR_START_5,EL2 Start Address Register Region_5" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_5,EL2 Region 5 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_5,EL2 Region 5 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_5,EL2 Region 5 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_5,EL2 Region 5 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_5,EL2 Region 5 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_5,EL2 Region 5 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_5,EL2 Region 5 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_5,EL2 Region 5 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_5,EL2 Region 5 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x180++0x27 line.long 0x0 "EL2_ADDR_START_6,EL2 Start Address Register Region_6" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_6,EL2 Region 6 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_6,EL2 Region 6 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_6,EL2 Region 6 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_6,EL2 Region 6 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_6,EL2 Region 6 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_6,EL2 Region 6 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_6,EL2 Region 6 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_6,EL2 Region 6 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_6,EL2 Region 6 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x1C0++0x27 line.long 0x0 "EL2_ADDR_START_7,EL2 Start Address Register Region_7" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_7,EL2 Region 7 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_7,EL2 Region 7 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_7,EL2 Region 7 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_7,EL2 Region 7 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_7,EL2 Region 7 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_7,EL2 Region 7 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_7,EL2 Region 7 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_7,EL2 Region 7 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_7,EL2 Region 7 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "SYSRAM1_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B710200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x40++0x27 line.long 0x0 "EL2_ADDR_START_1,EL2 Start Address Register Region_1" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_1,EL2 Region 1 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_1,EL2 Region 1 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_1,EL2 Region 1 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_1,EL2 Region 1 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_1,EL2 Region 1 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_1,EL2 Region 1 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_1,EL2 Region 1 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_1,EL2 Region 1 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_1,EL2 Region 1 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x80++0x27 line.long 0x0 "EL2_ADDR_START_2,EL2 Start Address Register Region_2" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_2,EL2 Region 2 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_2,EL2 Region 2 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_2,EL2 Region 2 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_2,EL2 Region 2 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_2,EL2 Region 2 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_2,EL2 Region 2 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_2,EL2 Region 2 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_2,EL2 Region 2 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_2,EL2 Region 2 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0xC0++0x27 line.long 0x0 "EL2_ADDR_START_3,EL2 Start Address Register Region_3" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_3,EL2 Region 3 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_3,EL2 Region 3 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_3,EL2 Region 3 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_3,EL2 Region 3 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_3,EL2 Region 3 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_3,EL2 Region 3 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_3,EL2 Region 3 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_3,EL2 Region 3 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_3,EL2 Region 3 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x100++0x27 line.long 0x0 "EL2_ADDR_START_4,EL2 Start Address Register Region_4" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_4,EL2 Region 4 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_4,EL2 Region 4 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_4,EL2 Region 4 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_4,EL2 Region 4 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_4,EL2 Region 4 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_4,EL2 Region 4 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_4,EL2 Region 4 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_4,EL2 Region 4 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_4,EL2 Region 4 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x140++0x27 line.long 0x0 "EL2_ADDR_START_5,EL2 Start Address Register Region_5" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_5,EL2 Region 5 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_5,EL2 Region 5 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_5,EL2 Region 5 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_5,EL2 Region 5 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_5,EL2 Region 5 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_5,EL2 Region 5 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_5,EL2 Region 5 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_5,EL2 Region 5 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_5,EL2 Region 5 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x180++0x27 line.long 0x0 "EL2_ADDR_START_6,EL2 Start Address Register Region_6" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_6,EL2 Region 6 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_6,EL2 Region 6 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_6,EL2 Region 6 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_6,EL2 Region 6 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_6,EL2 Region 6 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_6,EL2 Region 6 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_6,EL2 Region 6 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_6,EL2 Region 6 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_6,EL2 Region 6 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x1C0++0x27 line.long 0x0 "EL2_ADDR_START_7,EL2 Start Address Register Region_7" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_7,EL2 Region 7 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_7,EL2 Region 7 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_7,EL2 Region 7 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_7,EL2 Region 7 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_7,EL2 Region 7 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_7,EL2 Region 7 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_7,EL2 Region 7 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_7,EL2 Region 7 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_7,EL2 Region 7 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "TMC0_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B780200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x40++0x27 line.long 0x0 "EL2_ADDR_START_1,EL2 Start Address Register Region_1" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_1,EL2 Region 1 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_1,EL2 Region 1 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_1,EL2 Region 1 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_1,EL2 Region 1 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_1,EL2 Region 1 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_1,EL2 Region 1 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_1,EL2 Region 1 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_1,EL2 Region 1 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_1,EL2 Region 1 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "TMC1_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B7B0200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x40++0x27 line.long 0x0 "EL2_ADDR_START_1,EL2 Start Address Register Region_1" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_1,EL2 Region 1 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_1,EL2 Region 1 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_1,EL2 Region 1 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_1,EL2 Region 1 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_1,EL2 Region 1 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_1,EL2 Region 1 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_1,EL2 Region 1 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_1,EL2 Region 1 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_1,EL2 Region 1 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree "TMC2_FIREWALL_CORE_FIREWALL_EL2_ADR" base ad:0x7B7D0200 group.long 0x0++0x27 line.long 0x0 "EL2_ADDR_START_0,EL2 Start Address Register Region_0" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_0,EL2 Region 0 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_0,EL2 Region 0 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_0,EL2 Region 0 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_0,EL2 Region 0 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_0,EL2 Region 0 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_0,EL2 Region 0 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_0,EL2 Region 0 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_0,EL2 Region 0 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_0,EL2 Region 0 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" group.long 0x40++0x27 line.long 0x0 "EL2_ADDR_START_1,EL2 Start Address Register Region_1" hexmask.long 0x0 6.--31. 1. "EL2_ADDR_START,Defines [31:6] bits of start address bound for Region." line.long 0x4 "EL2_ADDR_SIZE_1,EL2 Region 1 Address Size Register" hexmask.long 0x4 6.--31. 1. "EL2_ADDR_SIZE,Defines the address size [31:6] bits for Region." line.long 0x8 "EL2_VMID_WR_1,EL2 Region 1 VMID Write Access Register" hexmask.long.byte 0x8 0.--7. 1. "EL2_VMID_WR,VMID which is having permission to write in region." line.long 0xC "EL2_VMID_0_RD_1,EL2 Region 1 VMID 0 Read Access Register" hexmask.long.byte 0xC 0.--7. 1. "EL2_VMID_0_RD,VMID which is having permission to read in region." line.long 0x10 "EL2_VMID_1_RD_1,EL2 Region 1 VMID 1 Read Access Register" hexmask.long.byte 0x10 0.--7. 1. "EL2_VMID_1_RD,VMID which is having permission to read in region." line.long 0x14 "EL2_VMID_2_RD_1,EL2 Region 1 VMID 2 Read Access Register" hexmask.long.byte 0x14 0.--7. 1. "EL2_VMID_2_RD,VMID which is having permission to read in region." line.long 0x18 "EL2_VMID_3_RD_1,EL2 Region 1 VMID 3 Read Access Register" hexmask.long.byte 0x18 0.--7. 1. "EL2_VMID_3_RD,VMID which is having permission to read in region." line.long 0x1C "EL2_VMID_4_RD_1,EL2 Region 1 VMID 4 Read Access Register" hexmask.long.byte 0x1C 0.--7. 1. "EL2_VMID_4_RD,VMID which is having permission to read in region." line.long 0x20 "EL2_VMID_5_RD_1,EL2 Region 1 VMID 5 Read Access Register" hexmask.long.byte 0x20 0.--7. 1. "EL2_VMID_5_RD,VMID which is having permission to read in region." line.long 0x24 "EL2_REGION_CONF_1,EL2 Region 1 Region Configuration Register" hexmask.long.byte 0x24 4.--7. 1. "EL2_RGN_MEM_TYPE,Region Memory type" bitfld.long 0x24 3. "EL2_RGN_SAFE,EL2 region Safe bit" "0,1" bitfld.long 0x24 1.--2. "EL2_RGN_SHRBL,EL2 region-read share ability among different virtual machines" "0,1,2,3" bitfld.long 0x24 0. "EL2_REGION_VLD,EL2 Region enable bit" "0,1" tree.end tree.end tree "FIREWALL_STS" tree "AESLIGHT1_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B630000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "AESLIGHT2_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B640000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "AESLIGHT3_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B650000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "AIPS0_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B660000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "AIPS1_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B670000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "AIPS2_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B680000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "AIPS3_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B690000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "AIPS4_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B6A0000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "DAP_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B6B0000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "DFA_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B790000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "DME_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B6C0000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "DSPH_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B6D0000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "FIREWALL_STS_ADR" base ad:0x7B620000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "GTM_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B740000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "HSM_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B750000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "KITE0_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B770000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "KITE1_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B7A0000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "KITE2_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B7C0000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "NVM_WR_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B760000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "OCT_SPI_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B720000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "PCIE0_CFG_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B6E0000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "PCIE0_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B600000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "PCIE1_CFG_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B6F0000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "PCIE1_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B610000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "SDMMC_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B730000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "SYSRAM0_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B700000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "SYSRAM1_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B710000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "TMC0_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B780000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "TMC1_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B7B0000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree "TMC2_FIREWALL_CORE_FIREWALL_STS_ADR" base ad:0x7B7D0000 group.long 0x0++0x3 line.long 0x0 "FW_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "FW_ERROR,Firewall EL2/1/0 or ECC access error occurs." "0,1" rgroup.long 0x10++0x1F line.long 0x0 "FW_EL2_ERROR_STATUS,Firewall EL2 Error Status Register" bitfld.long 0x0 0. "EL2_ERROR,EL2 access error occurs." "0,1" line.long 0x4 "FW_EL2_ERROR_TYPE_STATUS,Firewall EL2 Error Type Status Register" bitfld.long 0x4 8. "EL2_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x4 7. "EL2_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x4 6. "EL2_UNSAFE_MSTR_ACC,If non Hypervisor unsafe R52 is trying to access the safe region." "0,1" bitfld.long 0x4 5. "EL2_UNSAFE_HV_ACC,If privileged Hypervisor with unsafe R52 is trying to access the safe region." "0,1" newline bitfld.long 0x4 4. "EL2_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x4 3. "EL2_VMID_PRIV_MISM,Hypervisor is not having privilege access." "0,1" bitfld.long 0x4 2. "EL2_MEM_MISM,The R52 MPU setting does not match the EL2_RGN_MEM_TYPE field of EL2_REGION_CONF_n register." "0,1" bitfld.long 0x4 1. "EL2_ILLEGAL_VMID,Access from non R52 masters having same VMID as DCF_HV_VMID." "0,1" newline bitfld.long 0x4 0. "EL2_PARTITION_ERR,Initiator Masters VMID does not have read/write access to the region." "0,1" line.long 0x8 "FW_EL2_ERROR_ID_STATUS,Firewall EL2 Error ID Status Register" hexmask.long.byte 0x8 8.--13. 1. "EL2_ERROR_MSTR_ID,Core Master ID of the master blocked by the EL2 Firewall." hexmask.long.byte 0x8 0.--7. 1. "EL2_ERROR_VMID,Virtual Machine ID of the master blocked by the EL2 Firewall." line.long 0xC "FW_EL2_ERROR_ADDR_STATUS,Firewall EL2 Error ADDR Status Register" hexmask.long 0xC 0.--31. 1. "EL2_ERR_ADDR,address which has EL2 access Error." line.long 0x10 "FW_EL1_ERROR_STATUS,Firewall EL1 Error Status Register" bitfld.long 0x10 0. "EL1_ERROR,EL1 access error" "0,1" line.long 0x14 "FW_EL1_ERROR_TYPE_STATUS,Firewall EL1 Error Type Status Register" bitfld.long 0x14 5. "EL1_MULTI_RGN_ERR,Multiple Firewall regions are configured to include the transaction address." "0,1" bitfld.long 0x14 4. "EL1_TX_INVALID,If the Master is initiating read/write access to outside of the boundary of the region." "0,1" bitfld.long 0x14 3. "EL1_RGN_NOT_HIT,No Firewall region are configured to include the transaction address." "0,1" bitfld.long 0x14 2. "EL1_EXE_ACC_ERR,Master is not having Execute Access to the region." "0,1" newline bitfld.long 0x14 1. "EL1_WR_ACC_ERR,Master is not having Write Access to the region." "0,1" bitfld.long 0x14 0. "EL1_RD_ACC_ERR,Master is not having Read Access to the region." "0,1" line.long 0x18 "FW_EL1_ERROR_ID_STATUS,Firewall EL1 Error ID Status Register" hexmask.long.byte 0x18 8.--13. 1. "EL1_ERROR_MSTR_ID,Core Master ID which has EL1 access Error." hexmask.long.byte 0x18 0.--7. 1. "EL1_ERROR_VMID,Virtual Machine ID which has EL1 access Error." line.long 0x1C "FW_EL1_ERROR_ADDR_STATUS,Firewall EL1 Error ADDR Status Register" hexmask.long 0x1C 0.--31. 1. "EL1_ERR_ADDR,address which has EL2 access Error." group.long 0x30++0x3 line.long 0x0 "FW_ECC_ERROR_STATUS,Firewall ECC Error Status Register" bitfld.long 0x0 0. "ECC_ERROR_STATUS,VMID ECC error status" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "FW_ECC_ERR_VMID,Firewall ECC error VMID Register" hexmask.long.byte 0x0 0.--7. 1. "ECC_ERR_VMID,Virtual Machine ID which has ECC Error" tree.end tree.end tree.end tree "FLEXRAY (FlexRay Communication Controller)" base ad:0x0 tree "FLEXRAY_0" base ad:0x70E18000 rgroup.word 0x0++0x1 line.word 0x0 "MVR,Module Version Register" hexmask.word.byte 0x0 8.--15. 1. "CHIVER,CHI Version Number" newline hexmask.word.byte 0x0 0.--7. 1. "PEVER,PE Version Number" group.word 0x2++0x1F line.word 0x0 "MCR,Module Configuration Register" bitfld.word 0x0 15. "MEN,Module Enable" "0: Write: only during POC:default config CC disable,1: Write: enable CC" newline bitfld.word 0x0 14. "SBFF,System Bus Failure Freeze" "0: Continue normal operation,1: Transition to Freeze mode" newline bitfld.word 0x0 13. "SCM,Single Channel Device Mode" "0: CC works in Dual-Channel Device mode,1: CC works in Single-Channel Device mode" newline bitfld.word 0x0 12. "CHB,Channel Enable" "0,1" newline bitfld.word 0x0 11. "CHA,Channel Enable" "0,1" newline bitfld.word 0x0 10. "SFFE,Synchronization Frame Filter Enable" "0: Synchronization frame filtering disabled,1: Synchronization frame filtering enabled" newline bitfld.word 0x0 9. "ECCE,ECC Functionality Enable" "0: ECC functionality (injection detection reporting..,1: ECC functionality enabled" newline bitfld.word 0x0 7. "FUM,FIFO Update Mode" "0: FIFOA/FIFOB is updated on writing 1 to..,1: FIFOA/FIFOB) is not updated on writing 1 to.." newline bitfld.word 0x0 6. "FAM,FIFO Address Mode" "0: FIFO Base Address located in Section1.5.2.5:..,1: FIFO Base Address located in Section1.5.2.76:.." newline bitfld.word 0x0 4. "CLKSEL,Protocol Engine Clock Source Select" "0: PE clock source is generated by on-chip crystal..,1: PE clock source is generated by on-chip PLL." newline bitfld.word 0x0 1.--3. "BITRATE,FlexRay Bus Bit Rate" "0: 10.0 Mbit/s,1: 5.0 Mbit/s,2: 2.5 Mbit/s,3: 8.0 Mbit/s,?,?,?,?" line.word 0x2 "SYMBADHR,System Memory Base Address Register" hexmask.word 0x2 0.--15. 1. "SMBA,System Memory Base Address" line.word 0x4 "SYMBADLR,System Memory Base Address Register" hexmask.word 0x4 4.--15. 1. "SMBA,System Memory Base Address" line.word 0x6 "STBSCR,Strobe Signal Control Register" bitfld.word 0x6 15. "WMD,Write Mode" "0: Write to all fields in this register on write..,1: Write to SEL field only on write access." newline hexmask.word.byte 0x6 8.--11. 1. "SEL,Strobe Signal Select" newline bitfld.word 0x6 4. "ENB,Strobe Signal Enable" "0: Strobe signal is disabled and not assigned to..,1: Strobe signal is enabled and assigned to the.." newline bitfld.word 0x6 0.--1. "STBPSEL,Strobe Port Select" "0: Assign selected signal to FR_DBG[0].,1: Assign selected signal to FR_DBG[1].,2: Assign selected signal to FR_DBG[2].,3: Assign selected signal to FR_DBG[3]." line.word 0x8 "STBPCR,Strobe Port Control Register" bitfld.word 0x8 3. "STB3EN,Strobe Port 3 Enable" "0: Strobe port FR_DBG[3] disabled,1: Strobe port FR_DBG[3] enabled" newline bitfld.word 0x8 2. "STB2EN,Strobe Port 2 Enable" "0: Strobe port FR_DBG[2] disabled,1: Strobe port FR_DBG[2] enabled" newline bitfld.word 0x8 1. "STB1EN,Strobe Port 1 Enable" "0: Strobe port FR_DBG[1] disabled,1: Strobe port FR_DBG[1] enabled" newline bitfld.word 0x8 0. "STB0EN,Strobe Port 0 Enable" "0: Strobe port FR_DBG[0] disabled,1: Strobe port FR_DBG[0] enabled" line.word 0xA "MBDSR,Message Buffer Data Size Register" hexmask.word.byte 0xA 8.--14. 1. "MBSEG2DS,Message Buffer Segment 2 Data Size" newline hexmask.word.byte 0xA 0.--6. 1. "MBSEG1DS,Message Buffer Segment 1 Data Size" line.word 0xC "MBSSUTR,Message Buffer Segment Size and Utilization Register" hexmask.word.byte 0xC 8.--15. 1. "LAST_MB_SEG1,Last Message Buffer In Segment 1" newline hexmask.word.byte 0xC 0.--7. 1. "LAST_MB_UTIL,Last Message Buffer Utilized" line.word 0xE "PEDRAR,PE DRAM Access Register" hexmask.word.byte 0xE 12.--15. 1. "INST,PE DRAM Access Instruction" newline hexmask.word 0xE 1.--11. 1. "ADDR,PE DRAM Access Address" newline bitfld.word 0xE 0. "DAD,PE DRAM Access Done" "0: PE DRAM access running,1: PE DRAM access done" line.word 0x10 "PEDRDR,PE DRAM Data Register" hexmask.word 0x10 0.--15. 1. "DATA,Data" line.word 0x12 "POCR,Protocol Operation Control Register" bitfld.word 0x12 15. "WME,Write Mode External Correction" "0: Write to EOC_AP and ERC_AP fields on register..,1: No write to EOC_AP and ERC_AP fields on register.." newline bitfld.word 0x12 10.--11. "EOC_AP,External Offset Correction Application" "0: Do not apply external offset correction value,?,2: Subtract external offset correction value,3: Add external offset correction value" newline bitfld.word 0x12 8.--9. "ERC_AP,External Rate Correction Application" "0: Do not apply external rate correction value,?,2: Subtract external rate correction value,3: Add external rate correction value" newline bitfld.word 0x12 7. "BSY_WMC,Protocol Control Command Write Busy (BSY)" "0,1" newline hexmask.word.byte 0x12 0.--3. 1. "POCCMD,Protocol Control Command" line.word 0x14 "GIFER,Global Interrupt Flag and Enable Register" bitfld.word 0x14 15. "MIF,Module Interrupt Flag" "0: No interrupt flag and related interrupt enable..,1: At least one of the other interrupt flags in.." newline bitfld.word 0x14 14. "PRIF,Protocol Interrupt Flag" "0: No individual protocol interrupt flag and..,1: At least one of the individual protocol.." newline bitfld.word 0x14 13. "CHIF,CHI Interrupt Flag" "0: All CHI error flags are equal to 0 or the CHI..,1: At least one CHI error flag and the CHI error.." newline bitfld.word 0x14 12. "WUPIF,Wakeup Interrupt Flag" "0: No wakeup symbol received on FlexRay bus,1: Wakeup symbol received on FlexRay bus" newline bitfld.word 0x14 11. "FAFBIF,Receive FIFO Channel B Almost Full Interrupt Flag" "0: No such event,1: FIFO B almost full event has occurred" newline bitfld.word 0x14 10. "FAFAIF,Receive FIFO Channel A Almost Full Interrupt Flag" "0: No such event,1: FIFO A almost full event has occurred" newline bitfld.word 0x14 9. "RBIF,Receive Message Buffer Interrupt Flag" "0: None of the individual receive message buffers..,1: At least one individual receive message buffer.." newline bitfld.word 0x14 8. "TBIF,Transmit Message Buffer Interrupt Flag" "0: None of the individual transmit message buffers..,1: At least one individual transmit message buffer.." newline bitfld.word 0x14 7. "MIE,Module Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" newline bitfld.word 0x14 6. "PRIE,Protocol Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" newline bitfld.word 0x14 5. "CHIE,CHI Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" newline bitfld.word 0x14 4. "WUPIE,Wakeup Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" newline bitfld.word 0x14 3. "FAFBIE,Receive FIFO Channel B Almost Full Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" newline bitfld.word 0x14 2. "FAFAIE,Receive FIFO Channel A Almost Full Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" newline bitfld.word 0x14 1. "RBIE,Receive Message Buffer Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" newline bitfld.word 0x14 0. "TBIE,Transmit Message Buffer Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" line.word 0x16 "PIFR0,Protocol Interrupt Flag Register 0" bitfld.word 0x16 15. "FATL_IF,Fatal Protocol Error Interrupt Flag" "0: No such event,1: Fatal protocol error detected" newline bitfld.word 0x16 14. "INTL_IF,Internal Protocol Error Interrupt Flag" "0: No such event,1: Internal protocol error detected" newline bitfld.word 0x16 13. "ILCF_IF,Illegal Protocol Configuration Interrupt Flag" "0: No such event,1: Illegal protocol configuration detected" newline bitfld.word 0x16 12. "CSA_IF,Cold Start Abort Interrupt Flag" "0: No such event,1: Cold start aborted and no more coldstart.." newline bitfld.word 0x16 11. "MRC_IF,Missing Rate Correction Interrupt Flag" "0: No such event,1: Insufficient number of measurements for rate.." newline bitfld.word 0x16 10. "MOC_IF,Missing Offset Correction Interrupt Flag" "0: No such event,1: Insufficient number of measurements for offset.." newline bitfld.word 0x16 9. "CCL_IF,Clock Correction Limit Reached Interrupt Flag" "0: No such event,1: Offset or rate correction limit reached" newline bitfld.word 0x16 8. "MXS_IF,Max Sync Frames Detected Interrupt Flag" "0: No such event,1: More than node_sync_max sync frames detected" newline bitfld.word 0x16 7. "MTX_IF,Media Access Test Symbol Received Interrupt Flag" "0: No such event,1: MTS symbol received" newline bitfld.word 0x16 6. "LTXB_IF,pLatestTx Violation on Channel B Interrupt Flag" "0: No such event,1: pLatestTx violation occurred on channel B" newline bitfld.word 0x16 5. "LTXA_IF,pLatestTx Violation on Channel A Interrupt Flag" "0: No such event,1: pLatestTx violation occurred on channel A" newline bitfld.word 0x16 4. "TBVB_IF,Transmission across boundary on channel B Interrupt Flag" "0: No such event,1: Transmission across boundary violation occurred.." newline bitfld.word 0x16 3. "TBVA_IF,Transmission across boundary on channel A Interrupt Flag" "0: No such event,1: Transmission across boundary violation occurred.." newline bitfld.word 0x16 2. "TI2_IF,Timer 2 Expired Interrupt Flag" "0: No such event,1: Timer 2 has reached its time limit" newline bitfld.word 0x16 1. "TI1_IF,Timer 1 Expired Interrupt Flag" "0: No such event,1: Timer 1 has reached its time limit" newline bitfld.word 0x16 0. "CYS_IF,Cycle Start Interrupt Flag" "0: No such event,1: Communication cycle started" line.word 0x18 "PIFR1,Protocol Interrupt Flag Register 1" bitfld.word 0x18 15. "EMC_IF,Error Mode Changed Interrupt Flag" "0: No such event,1: ERRMODE field changed" newline bitfld.word 0x18 14. "IPC_IF,Illegal Protocol Control Command Interrupt Flag" "0: No such event,1: Illegal protocol control command detected" newline bitfld.word 0x18 13. "PECF_IF,Protocol Engine Communication Failure Interrupt Flag" "0: No such event,1: Protocol Engine Communication Failure detected" newline bitfld.word 0x18 12. "PSC_IF,Protocol State Changed Interrupt Flag" "0: No such event,1: Protocol state changed" newline bitfld.word 0x18 11. "SSI3_IF,Slot Status Counter Incremented Interrupt Flag" "0: No such event,1: The corresponding slot status counter has.." newline bitfld.word 0x18 10. "SSI2_IF,Slot Status Counter Incremented Interrupt Flag" "0: No such event,1: The corresponding slot status counter has.." newline bitfld.word 0x18 9. "SSI1_IF,Slot Status Counter Incremented Interrupt Flag" "0: No such event,1: The corresponding slot status counter has.." newline bitfld.word 0x18 8. "SSI0_IF,Slot Status Counter Incremented Interrupt Flag" "0: No such event,1: The corresponding slot status counter has.." newline bitfld.word 0x18 5. "EVT_IF,Even Cycle Table Written Interrupt Flag" "0: No such event,1: Sync frame measurement table written" newline bitfld.word 0x18 4. "ODT_IF,Odd Cycle Table Written Interrupt Flag" "0: No such event,1: Sync frame measurement table written" line.word 0x1A "PIER0,Protocol Interrupt Enable Register 0" bitfld.word 0x1A 15. "FATL_IE,Fatal Protocol Error Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 14. "INTL_IE,Internal Protocol Error Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 13. "ILCF_IE,Illegal Protocol Configuration Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 12. "CSA_IE,Cold Start Abort Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 11. "MRC_IE,Missing Rate Correction Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 10. "MOC_IE,Missing Offset Correction Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 9. "CCL_IE,Clock Correction Limit Reached Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 8. "MXS_IE,Max Sync Frames Detected Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 7. "MTX_IE,Media Access Test Symbol Received Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 6. "LTXB_IE,pLatestTx Violation on Channel B Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 5. "LTXA_IE,pLatestTx Violation on Channel A Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 4. "TBVB_IE,Transmission across boundary on channel B Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 3. "TBVA_IE,Transmission across boundary on channel A Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 2. "TI2_IE,Timer 2 Expired Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 1. "TI1_IE,Timer 1 Expired Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 0. "CYS_IE,Cycle Start Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" line.word 0x1C "PIER1,Protocol Interrupt Enable Register 1" bitfld.word 0x1C 15. "EMC_IE,Error Mode Changed Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1C 14. "IPC_IE,Illegal Protocol Control Command Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1C 13. "PECF_IE,Protocol Engine Communication Failure Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1C 12. "PSC_IE,Protocol State Changed Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1C 11. "SSI3_IE,Slot Status Counter Incremented Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1C 10. "SSI2_IE,Slot Status Counter Incremented Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1C 9. "SSI1_IE,Slot Status Counter Incremented Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1C 8. "SSI0_IE,Slot Status Counter Incremented Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1C 5. "EVT_IE,Even Cycle Table Written Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1C 4. "ODT_IE,Odd Cycle Table Written Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" line.word 0x1E "CHIERFR,CHI Error Flag Register" bitfld.word 0x1E 15. "FRLB_EF,Frame Lost Channel B Error Flag" "0: No such event,1: Frame lost on channel B detected" newline bitfld.word 0x1E 14. "FRLA_EF,Frame Lost Channel A Error Flag" "0: No such error,1: Frame lost on channel A detected" newline bitfld.word 0x1E 13. "PCMI_EF,Protocol Command Ignored Error Flag" "0: No such error,1: POC command ignored" newline bitfld.word 0x1E 12. "FOVB_EF,Receive FIFO Overrun Channel B Error Flag" "0: No such error,1: FIFO overrun on channel B has been detected" newline bitfld.word 0x1E 11. "FOVA_EF,Receive FIFO Overrun Channel A Error Flag" "0: No such error,1: FIFO overrun on channel B has been detected" newline bitfld.word 0x1E 10. "MBS_EF,Message Buffer Search Error Flag" "0: No such event,1: Search engine active while search start appears.." newline bitfld.word 0x1E 9. "MBU_EF,Message Buffer Utilization Error Flag" "0: No such event,1: Non-utilized message buffer enabled" newline bitfld.word 0x1E 8. "LCK_EF,Lock Error Flag" "0: No such error,1: Lock error detected" newline bitfld.word 0x1E 6. "SBCF_EF,System Bus Communication Failure Error Flag" "0: No such event,1: System bus access not finished in time" newline bitfld.word 0x1E 5. "FID_EF,Frame ID Error Flag" "0: No such error occurred,1: Frame ID error occurred" newline bitfld.word 0x1E 4. "DPL_EF,Dynamic Payload Length Error Flag" "0: No such error occurred,1: Dynamic payload length error occurred" newline bitfld.word 0x1E 3. "SPL_EF,Static Payload Length Error Flag" "0: No such error occurred,1: Static payload length error occurred" newline bitfld.word 0x1E 2. "NML_EF,Network Management Length Error Flag" "0: No such error occurred,1: Network management length error occurred" newline bitfld.word 0x1E 1. "NMF_EF,Network Management Frame Error Flag" "0: No such error occurred,1: Network management frame error occurred" newline bitfld.word 0x1E 0. "ILSA_EF,Illegal System Bus Address Error Flag" "0: No such event,1: System bus illegal address access" rgroup.word 0x22++0x7 line.word 0x0 "MBIVEC,Message Buffer Interrupt Vector Register" hexmask.word.byte 0x0 8.--15. 1. "TBIVEC,Transmit Buffer Interrupt Vector" newline hexmask.word.byte 0x0 0.--7. 1. "RBIVEC,Receive Buffer Interrupt Vector" line.word 0x2 "CASERCR,Channel A Status Error Counter Register" hexmask.word 0x2 0.--15. 1. "CHAERSCNT,Channel Status Error Counter" line.word 0x4 "CBSERCR,Channel B Status Error Counter Register" hexmask.word 0x4 0.--15. 1. "CHBERSCNT,Channel Status Error Counter" line.word 0x6 "PSR0,Protocol Status Register 0" bitfld.word 0x6 14.--15. "ERRMODE,Error Mode" "0: ACTIVE,1: PASSIVE,2: COMM_HALT,?" newline bitfld.word 0x6 12.--13. "SLOTMODE,Slot Mode" "0: SINGLE,1: ALL_PENDING,2: ALL,?" newline bitfld.word 0x6 8.--10. "PROTSTATE,Protocol State" "0: POC:default config,1: POC:config,2: POC:wakeup,3: POC:ready,4: POC:normal passive,5: POC:normal active,6: POC:halt,7: POC:startup" newline hexmask.word.byte 0x6 4.--7. 1. "STARTUPSTATE,Startup State" newline bitfld.word 0x6 0.--2. "WAKEUPSTATUS,Wakeup Status" "0: UNDEFINED,1: RECEIVED_HEADER,2: RECEIVED_WUP,3: COLLISION_HEADER,4: COLLISION_WUP,5: COLLISION_UNKNOWN,6: TRANSMITTED,?" group.word 0x2A++0x1 line.word 0x0 "PSR1,Protocol Status Register 1" bitfld.word 0x0 15. "CSAA,Cold Start Attempt Aborted Flag" "0: No such event,1: Cold start attempt aborted" newline bitfld.word 0x0 14. "CSP,Leading Cold Start Path" "0: No such event,1: POC:normal active reached from POC:startup state.." newline hexmask.word.byte 0x0 8.--12. 1. "REMCSAT,Remaining Coldstart Attempts" newline bitfld.word 0x0 7. "CPN,Leading Cold Start Path Noiseprotocol-related variable: vPOC!ColdstartNoise." "0: No such event,1: POC:normal active state was reached from.." newline bitfld.word 0x0 6. "HHR,Host Halt Request Pending" "0: No such event,1: HALT command received" newline bitfld.word 0x0 5. "FRZ,Freeze Occurred" "0: No such event,1: Immediate halt due to FREEZE or internal error.." newline hexmask.word.byte 0x0 0.--4. 1. "APTAC,Allow Passive to Active Counter" rgroup.word 0x2C++0x1 line.word 0x0 "PSR2,Protocol Status Register 2" bitfld.word 0x0 15. "NBVB,NIT Boundary Violation on Channel B" "0: No such event,1: Media activity at boundaries detected" newline bitfld.word 0x0 14. "NSEB,NIT Syntax Error on Channel B" "0: No such event,1: Syntax error detected" newline bitfld.word 0x0 13. "STCB,Symbol Window Transmit Conflict on Channel B" "0: No such event,1: Transmission conflict detected" newline bitfld.word 0x0 12. "SBVB,Symbol Window Boundary Violation on Channel B" "0: No such event,1: Media activity at boundaries detected" newline bitfld.word 0x0 11. "SSEB,Symbol Window Syntax Error on Channel B" "0: No such event,1: Syntax error detected" newline bitfld.word 0x0 10. "MTB,Media Access Test Symbol MTS Received on Channel B" "0: No such event,1: MTS symbol received" newline bitfld.word 0x0 9. "NBVA,NIT Boundary Violation on Channel A" "0: No such event,1: Media activity at boundaries detected" newline bitfld.word 0x0 8. "NSEA,NIT Syntax Error on Channel A" "0: No such event,1: Syntax error detected" newline bitfld.word 0x0 7. "STCA,Symbol Window Transmit Conflict on Channel A" "0: No such event,1: Transmission conflict detected" newline bitfld.word 0x0 6. "SBVA,Symbol Window Boundary Violation on Channel A" "0: No such event,1: Media activity at boundaries detected" newline bitfld.word 0x0 5. "SSEA,Symbol Window Syntax Error on Channel A" "0: No such event,1: Syntax error detected" newline bitfld.word 0x0 4. "MTA,Media Access Test Symbol MTS Received on Channel A" "0: No such event,1: MTS symbol received" newline hexmask.word.byte 0x0 0.--3. 1. "CKCORFCNT,Clock Correction Failed Counter" group.word 0x2E++0x1 line.word 0x0 "PSR3,Protocol Status Register 3" bitfld.word 0x0 13. "WUB,Wakeup Symbol Received on Channel B" "0: No wakeup symbol received,1: Wakeup symbol received" newline bitfld.word 0x0 12. "ABVB,Aggregated Boundary Violation on Channel B" "0: No boundary violation detected,1: Boundary violation detected" newline bitfld.word 0x0 11. "AACB,Aggregated Additional Communication on Channel B" "0: No additional communication detected,1: Additional communication detected" newline bitfld.word 0x0 10. "ACEB,Aggregated Content Error on Channel B" "0: No content error detected,1: Content error detected" newline bitfld.word 0x0 9. "ASEB,Aggregated Syntax Error on Channel B" "0: No syntax error detected,1: Syntax errors detected" newline bitfld.word 0x0 8. "AVFB,Aggregated Valid Frame on Channel B" "0: No syntactically valid frames received,1: At least one syntactically valid frame received" newline bitfld.word 0x0 5. "WUA,Wakeup Symbol Received on Channel A" "0: No wakeup symbol received,1: Wakeup symbol received" newline bitfld.word 0x0 4. "ABVA,Aggregated Boundary Violation on Channel A" "0: No boundary violation detected,1: Boundary violation detected" newline bitfld.word 0x0 3. "AACA,Aggregated Additional Communication on Channel A" "0: No additional communication detected,1: Additional communication detected" newline bitfld.word 0x0 2. "ACEA,Aggregated Content Error on Channel A" "0: No content error detected,1: Content error detected" newline bitfld.word 0x0 1. "ASEA,Aggregated Syntax Error on Channel A" "0: No syntax error detected,1: Syntax errors detected" newline bitfld.word 0x0 0. "AVFA,Aggregated Valid Frame on Channel A" "0: No syntactically valid frames received,1: At least one syntactically valid frame received" rgroup.word 0x30++0xD line.word 0x0 "MTCTR,Macrotick Counter Register" hexmask.word 0x0 0.--13. 1. "MTCT,Macrotick Counter" line.word 0x2 "CYCTR,Cycle Counter Register" hexmask.word.byte 0x2 0.--5. 1. "CYCCNT,Cycle Counter" line.word 0x4 "SLTCTAR,Slot Counter Channel A Register" hexmask.word 0x4 0.--10. 1. "SLOTCNTA,Slot Counter Value for Channel A" line.word 0x6 "SLTCTBR,Slot Counter Channel B Register" hexmask.word 0x6 0.--10. 1. "SLOTCNTB,Slot Counter Value for Channel B" line.word 0x8 "RTCORVR,Rate Correction Value Register" hexmask.word 0x8 0.--15. 1. "RATECORR,Rate Correction Value" line.word 0xA "OFCORVR,Offset Correction Value Register" hexmask.word 0xA 0.--15. 1. "OFFSETCORR,Offset Correction Value" line.word 0xC "CIFR,Combined Interrupt Flag Register" bitfld.word 0xC 7. "MIF,Module Interrupt Flag" "0: No interrupt source has its interrupt flag..,1: At least one interrupt source has its interrupt.." newline bitfld.word 0xC 6. "PRIF,Protocol Interrupt Flag" "0: All individual protocol interrupt flags are..,1: At least one of the individual protocol.." newline bitfld.word 0xC 5. "CHIF,CHI Interrupt Flag" "0: All CHI error flags are equal to 0,1: At least one CHI error flag is equal to 1" newline bitfld.word 0xC 4. "WUPIF,Wakeup Interrupt Flag" "0,1" newline bitfld.word 0xC 3. "FAFBIF,Receive FIFO Channel B Almost Full Interrupt Flag" "0,1" newline bitfld.word 0xC 2. "FAFAIF,Receive FIFO Channel A Almost Full Interrupt Flag" "0,1" newline bitfld.word 0xC 1. "RBIF,Receive Message Buffer Interrupt Flag" "0: None of the individual receive message buffers..,1: At least one individual receive message buffers.." newline bitfld.word 0xC 0. "TBIF,Transmit Message Buffer Interrupt Flag" "0: None of the individual transmit message buffers..,1: At least one individual transmit message buffers.." group.word 0x3E++0x1 line.word 0x0 "SYMATOR,System Memory Access Timeout Register" hexmask.word.byte 0x0 0.--7. 1. "TIMEOUT,System Memory Access Timeout" rgroup.word 0x40++0x1 line.word 0x0 "SFCNTR,Sync Frame Counter Register" hexmask.word.byte 0x0 12.--15. 1. "SFEVB,Sync Frames Channel B even cycle" newline hexmask.word.byte 0x0 8.--11. 1. "SFEVA,Sync Frames Channel A even cycle" newline hexmask.word.byte 0x0 4.--7. 1. "SFODB,Sync Frames Channel B odd cycle" newline hexmask.word.byte 0x0 0.--3. 1. "SFODA,Sync Frames Channel A odd cycle" group.word 0x42++0x9 line.word 0x0 "SFTOR,Sync Frame Table Offset Register" hexmask.word 0x0 1.--15. 1. "SFT_OFFSET,Sync Frame Table Offset" line.word 0x2 "SFTCCSR,Sync Frame Table Configuration. Control. Status Register" bitfld.word 0x2 15. "ELKT,Even Cycle Tables Lock/Unlock Trigger" "0: No effect,1: Triggers lock/unlock of the even cycle tables" newline bitfld.word 0x2 14. "OLKT,Odd Cycle Tables Lock/Unlock Trigger" "0: No effect,1: Triggers lock/unlock of the odd cycle tables" newline hexmask.word.byte 0x2 8.--13. 1. "CYCNUM,Cycle Number" newline bitfld.word 0x2 7. "ELKS,Even Cycle Tables Lock Status" "0: Application has not locked the even cycle tables,1: Application has locked the even cycle tables" newline bitfld.word 0x2 6. "OLKS,Odd Cycle Tables Lock Status" "0: Application has not locked the odd cycle tables,1: Application has locked the odd cycle tables" newline bitfld.word 0x2 5. "EVAL,Even Cycle Tables Valid" "0: Tables are not valid (update is ongoing),1: Tables are valid (consistent)" newline bitfld.word 0x2 4. "OVAL,Odd Cycle Tables Valid" "0: Tables are not valid (update is ongoing),1: Tables are valid (consistent)" newline bitfld.word 0x2 2. "OPT,One Pair Trigger" "0: Write continuously pairs of enabled Sync Frame..,1: Write only one pair of enabled Sync Frame Tables.." newline bitfld.word 0x2 1. "SDVEN,Sync Frame Deviation Table Enable" "0: Do not write Sync Frame Deviation Tables,1: Write Sync Frame Deviation Tables into FlexRay.." newline bitfld.word 0x2 0. "SIDEN,Sync Frame ID Table Enable" "0: Do not write Sync Frame ID Tables,1: Write Sync Frame ID Tables into FlexRay memory.." line.word 0x4 "SFIDRFR,Sync Frame ID Rejection Filter Register" hexmask.word 0x4 0.--9. 1. "SYNFRID,Sync Frame Rejection ID" line.word 0x6 "SFIDAFVR,Sync Frame ID Acceptance Filter Value Register" hexmask.word 0x6 0.--9. 1. "FVAL,Filter Value" line.word 0x8 "SFIDAFMR,Sync Frame ID Acceptance Filter Mask Register" hexmask.word 0x8 0.--9. 1. "FMSK,Filter Mask" rgroup.word 0x4C++0xB line.word 0x0 "NMVR0,Network Management Vector Registers" hexmask.word 0x0 0.--15. 1. "NMVP,Network Management Vector Part" line.word 0x2 "NMVR1,Network Management Vector Registers" hexmask.word 0x2 0.--15. 1. "NMVP,Network Management Vector Part" line.word 0x4 "NMVR2,Network Management Vector Registers" hexmask.word 0x4 0.--15. 1. "NMVP,Network Management Vector Part" line.word 0x6 "NMVR3,Network Management Vector Registers" hexmask.word 0x6 0.--15. 1. "NMVP,Network Management Vector Part" line.word 0x8 "NMVR4,Network Management Vector Registers" hexmask.word 0x8 0.--15. 1. "NMVP,Network Management Vector Part" line.word 0xA "NMVR5,Network Management Vector Registers" hexmask.word 0xA 0.--15. 1. "NMVP,Network Management Vector Part" group.word 0x58++0x9 line.word 0x0 "NMVLR,Network Management Vector Length Register" hexmask.word.byte 0x0 0.--3. 1. "NMVL,Network Management Vector Length" line.word 0x2 "TICCR,Timer Configuration and Control Register" bitfld.word 0x2 13. "T2_CFG,Timer T2 Configuration" "0: T2 is absolute timer.,1: T2 is relative timer." newline bitfld.word 0x2 12. "T2_REP,Timer T2 Repetitive Mode" "0: T2 is non repetitive.,1: T2 is repetitive." newline bitfld.word 0x2 10. "T2SP,Timer T2 Stop" "0: No effect,1: Stop timer T2" newline bitfld.word 0x2 9. "T2TR,Timer T2 Trigger" "0: No effect,1: Start timer T2" newline bitfld.word 0x2 8. "T2ST,Timer T2 State" "0: Timer T2 is idle.,1: Timer T2 is running." newline bitfld.word 0x2 4. "T1_REP,Timer T1 Repetitive Mode" "0: T1 is non repetitive.,1: T1 is repetitive." newline bitfld.word 0x2 2. "T1SP,Timer T1 Stop" "0: No effect,1: Stop timer T1" newline bitfld.word 0x2 1. "T1TR,Timer T1 Trigger" "0: No effect,1: Start timer T1" newline bitfld.word 0x2 0. "T1ST,Timer T1 State" "0: Timer T1 is idle.,1: Timer T1 is running." line.word 0x4 "TI1CYSR,Timer 1 Cycle Set Register" hexmask.word.byte 0x4 8.--13. 1. "T1_CYC_VAL,Timer T1 Cycle Filter Value" newline hexmask.word.byte 0x4 0.--5. 1. "T1_CYC_MSK,Timer T1 Cycle Filter Mask" line.word 0x6 "TI1MTOR,Timer 1 Macrotick Offset Register" hexmask.word 0x6 0.--13. 1. "T1_MTOFFSET,Timer 1 Macrotick Offset" line.word 0x8 "TI2CR0_T2CFG_0,Timer 2 Configuration Register 0" hexmask.word.byte 0x8 8.--13. 1. "T2_CYC_VAL,Timer T2 Cycle Filter Value" newline hexmask.word.byte 0x8 0.--5. 1. "T2_CYC_MSK,Timer T2 Cycle Filter Mask" group.word 0x60++0x3 line.word 0x0 "TI2CR0_T2CFG_1,The content of this register depends on the value of the T2_CFG bit in the Timer Configuration and Control Register (FR_TICCR). For a detailed description of timer T2. refer to Section1.6.17.2: Absolute/relative timer T2." hexmask.word 0x0 0.--15. 1. "T2_MTCNT,Timer T2 Macrotick High Word" line.word 0x2 "TI2CR1_T2CFG_0,Timer 2 Configuration Register 1" hexmask.word 0x2 0.--13. 1. "T2_MTOFFSET,Timer T2 Macrotick Offset" group.word 0x62++0x5 line.word 0x0 "TI2CR1_T2CFG_1,The content of this register depends on the value of the T2_CFG bit in the Timer Configuration and Control Register (FR_TICCR). For a detailed description of timer T2. refer to Section1.6.17.2: Absolute/relative timer T2." hexmask.word 0x0 0.--15. 1. "T2_MTCNT,Timer T2 Macrotick Low Word" line.word 0x2 "SSSR,Slot Status Selection Register" bitfld.word 0x2 15. "WMD,Write Mode" "0: Write to all fields in this register on write..,1: Write to SEL field only on write access" newline bitfld.word 0x2 12.--13. "SEL,Selector" "0: Select FR_SSSR0,1: Select FR_SSSR1,2: Select FR_SSSR2,3: Select FR_SSSR3" newline hexmask.word 0x2 0.--10. 1. "SLOTNUMBER,Slot Number" line.word 0x4 "SSCCR,Slot Status Counter Condition Register" bitfld.word 0x4 15. "WMD,Write Mode" "0: Write to all fields in this register on write..,1: Write to SEL field only on write access." newline bitfld.word 0x4 12.--13. "SEL,Selector" "0: select FR_SSCCR0,1: select FR_SSCCR1,2: select FR_SSCCR2,3: select FR_SSCCR3" newline bitfld.word 0x4 9.--10. "CNTCFG,Counter Configuration" "0: Increment by 1 if condition is fulfilled on..,1: Increment by 1 if condition is fulfilled on..,2: Increment by 1 if condition is fulfilled on at..,3: Increment by 2 if condition is fulfilled on both.." newline bitfld.word 0x4 8. "MCY,Multi Cycle Selection" "0: The Slot Status Counter provides information for..,1: The Slot Status Counter accumulates over.." newline bitfld.word 0x4 7. "VFR,Valid Frame Restriction" "0: The counter is not restricted to valid frames..,1: The counter is restricted to valid frames only." newline bitfld.word 0x4 6. "SYF,Sync Frame Restriction" "0: The counter is not restricted with respect to..,1: The counter is restricted to frames with the.." newline bitfld.word 0x4 5. "NUF," "0,1" newline bitfld.word 0x4 4. "SUF,Startup Frame Restriction" "0: The counter is not restricted with respect to..,1: The counter is restricted to received frames.." newline hexmask.word.byte 0x4 0.--3. 1. "STATUSMASK,Slot Status Mask" rgroup.word 0x68++0x17 line.word 0x0 "SSR0,Slot Status Registers" bitfld.word 0x0 15. "VFB,Valid Frame on Channel B" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x0 14. "SYB,Sync Frame Indicator Channel B" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x0 13. "NFB,Null Frame Indicator Channel B" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x0 12. "SUB,Startup Frame Indicator Channel B" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x0 11. "SEB,Syntax Error on Channel B" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x0 10. "CEB,Content Error on Channel B" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x0 9. "BVB,Boundary Violation on Channel B" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x0 8. "TCB,Transmission Conflict on Channel B" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" newline bitfld.word 0x0 7. "VFA,Valid Frame on Channel A" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x0 6. "SYA,Sync Frame Indicator Channel A" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x0 5. "NFA,Null Frame Indicator Channel A" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x0 4. "SUA,Startup Frame Indicator Channel A" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x0 3. "SEA,Syntax Error on Channel A" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x0 2. "CEA,Content Error on Channel A" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x0 1. "BVA,Boundary Violation on Channel A" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x0 0. "TCA,Transmission Conflict on Channel A" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" line.word 0x2 "SSR1,Slot Status Registers" bitfld.word 0x2 15. "VFB,Valid Frame on Channel B" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x2 14. "SYB,Sync Frame Indicator Channel B" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x2 13. "NFB,Null Frame Indicator Channel B" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x2 12. "SUB,Startup Frame Indicator Channel B" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x2 11. "SEB,Syntax Error on Channel B" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x2 10. "CEB,Content Error on Channel B" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x2 9. "BVB,Boundary Violation on Channel B" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x2 8. "TCB,Transmission Conflict on Channel B" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" newline bitfld.word 0x2 7. "VFA,Valid Frame on Channel A" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x2 6. "SYA,Sync Frame Indicator Channel A" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x2 5. "NFA,Null Frame Indicator Channel A" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x2 4. "SUA,Startup Frame Indicator Channel A" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x2 3. "SEA,Syntax Error on Channel A" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x2 2. "CEA,Content Error on Channel A" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x2 1. "BVA,Boundary Violation on Channel A" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x2 0. "TCA,Transmission Conflict on Channel A" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" line.word 0x4 "SSR2,Slot Status Registers" bitfld.word 0x4 15. "VFB,Valid Frame on Channel B" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x4 14. "SYB,Sync Frame Indicator Channel B" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x4 13. "NFB,Null Frame Indicator Channel B" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x4 12. "SUB,Startup Frame Indicator Channel B" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x4 11. "SEB,Syntax Error on Channel B" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x4 10. "CEB,Content Error on Channel B" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x4 9. "BVB,Boundary Violation on Channel B" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x4 8. "TCB,Transmission Conflict on Channel B" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" newline bitfld.word 0x4 7. "VFA,Valid Frame on Channel A" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x4 6. "SYA,Sync Frame Indicator Channel A" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x4 5. "NFA,Null Frame Indicator Channel A" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x4 4. "SUA,Startup Frame Indicator Channel A" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x4 3. "SEA,Syntax Error on Channel A" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x4 2. "CEA,Content Error on Channel A" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x4 1. "BVA,Boundary Violation on Channel A" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x4 0. "TCA,Transmission Conflict on Channel A" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" line.word 0x6 "SSR3,Slot Status Registers" bitfld.word 0x6 15. "VFB,Valid Frame on Channel B" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x6 14. "SYB,Sync Frame Indicator Channel B" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x6 13. "NFB,Null Frame Indicator Channel B" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x6 12. "SUB,Startup Frame Indicator Channel B" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x6 11. "SEB,Syntax Error on Channel B" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x6 10. "CEB,Content Error on Channel B" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x6 9. "BVB,Boundary Violation on Channel B" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x6 8. "TCB,Transmission Conflict on Channel B" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" newline bitfld.word 0x6 7. "VFA,Valid Frame on Channel A" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x6 6. "SYA,Sync Frame Indicator Channel A" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x6 5. "NFA,Null Frame Indicator Channel A" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x6 4. "SUA,Startup Frame Indicator Channel A" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x6 3. "SEA,Syntax Error on Channel A" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x6 2. "CEA,Content Error on Channel A" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x6 1. "BVA,Boundary Violation on Channel A" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x6 0. "TCA,Transmission Conflict on Channel A" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" line.word 0x8 "SSR4,Slot Status Registers" bitfld.word 0x8 15. "VFB,Valid Frame on Channel B" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x8 14. "SYB,Sync Frame Indicator Channel B" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x8 13. "NFB,Null Frame Indicator Channel B" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x8 12. "SUB,Startup Frame Indicator Channel B" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x8 11. "SEB,Syntax Error on Channel B" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x8 10. "CEB,Content Error on Channel B" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x8 9. "BVB,Boundary Violation on Channel B" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x8 8. "TCB,Transmission Conflict on Channel B" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" newline bitfld.word 0x8 7. "VFA,Valid Frame on Channel A" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x8 6. "SYA,Sync Frame Indicator Channel A" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x8 5. "NFA,Null Frame Indicator Channel A" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x8 4. "SUA,Startup Frame Indicator Channel A" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x8 3. "SEA,Syntax Error on Channel A" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x8 2. "CEA,Content Error on Channel A" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x8 1. "BVA,Boundary Violation on Channel A" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x8 0. "TCA,Transmission Conflict on Channel A" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" line.word 0xA "SSR5,Slot Status Registers" bitfld.word 0xA 15. "VFB,Valid Frame on Channel B" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0xA 14. "SYB,Sync Frame Indicator Channel B" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0xA 13. "NFB,Null Frame Indicator Channel B" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0xA 12. "SUB,Startup Frame Indicator Channel B" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0xA 11. "SEB,Syntax Error on Channel B" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0xA 10. "CEB,Content Error on Channel B" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0xA 9. "BVB,Boundary Violation on Channel B" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0xA 8. "TCB,Transmission Conflict on Channel B" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" newline bitfld.word 0xA 7. "VFA,Valid Frame on Channel A" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0xA 6. "SYA,Sync Frame Indicator Channel A" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0xA 5. "NFA,Null Frame Indicator Channel A" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0xA 4. "SUA,Startup Frame Indicator Channel A" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0xA 3. "SEA,Syntax Error on Channel A" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0xA 2. "CEA,Content Error on Channel A" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0xA 1. "BVA,Boundary Violation on Channel A" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0xA 0. "TCA,Transmission Conflict on Channel A" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" line.word 0xC "SSR6,Slot Status Registers" bitfld.word 0xC 15. "VFB,Valid Frame on Channel B" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0xC 14. "SYB,Sync Frame Indicator Channel B" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0xC 13. "NFB,Null Frame Indicator Channel B" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0xC 12. "SUB,Startup Frame Indicator Channel B" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0xC 11. "SEB,Syntax Error on Channel B" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0xC 10. "CEB,Content Error on Channel B" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0xC 9. "BVB,Boundary Violation on Channel B" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0xC 8. "TCB,Transmission Conflict on Channel B" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" newline bitfld.word 0xC 7. "VFA,Valid Frame on Channel A" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0xC 6. "SYA,Sync Frame Indicator Channel A" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0xC 5. "NFA,Null Frame Indicator Channel A" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0xC 4. "SUA,Startup Frame Indicator Channel A" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0xC 3. "SEA,Syntax Error on Channel A" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0xC 2. "CEA,Content Error on Channel A" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0xC 1. "BVA,Boundary Violation on Channel A" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0xC 0. "TCA,Transmission Conflict on Channel A" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" line.word 0xE "SSR7,Slot Status Registers" bitfld.word 0xE 15. "VFB,Valid Frame on Channel B" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0xE 14. "SYB,Sync Frame Indicator Channel B" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0xE 13. "NFB,Null Frame Indicator Channel B" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0xE 12. "SUB,Startup Frame Indicator Channel B" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0xE 11. "SEB,Syntax Error on Channel B" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0xE 10. "CEB,Content Error on Channel B" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0xE 9. "BVB,Boundary Violation on Channel B" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0xE 8. "TCB,Transmission Conflict on Channel B" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" newline bitfld.word 0xE 7. "VFA,Valid Frame on Channel A" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0xE 6. "SYA,Sync Frame Indicator Channel A" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0xE 5. "NFA,Null Frame Indicator Channel A" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0xE 4. "SUA,Startup Frame Indicator Channel A" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0xE 3. "SEA,Syntax Error on Channel A" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0xE 2. "CEA,Content Error on Channel A" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0xE 1. "BVA,Boundary Violation on Channel A" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0xE 0. "TCA,Transmission Conflict on Channel A" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" line.word 0x10 "SSCR0,Slot Status Counter Registers" hexmask.word 0x10 0.--15. 1. "SLOTSTATUSCNT,Slot Status Counter" line.word 0x12 "SSCR1,Slot Status Counter Registers" hexmask.word 0x12 0.--15. 1. "SLOTSTATUSCNT,Slot Status Counter" line.word 0x14 "SSCR2,Slot Status Counter Registers" hexmask.word 0x14 0.--15. 1. "SLOTSTATUSCNT,Slot Status Counter" line.word 0x16 "SSCR3,Slot Status Counter Registers" hexmask.word 0x16 0.--15. 1. "SLOTSTATUSCNT,Slot Status Counter" group.word 0x80++0xB line.word 0x0 "MTSACFR,MTS A Configuration Register" bitfld.word 0x0 15. "MTE,Media Access Test Symbol Transmission Enable" "0: MTS transmission disabled,1: MTS transmission enabled" newline hexmask.word.byte 0x0 8.--13. 1. "CYCCNTMSK,Cycle Counter Mask" newline hexmask.word.byte 0x0 0.--5. 1. "CYCCNTVAL,Cycle Counter Value" line.word 0x2 "MTSBCFR,MTS B Configuration Register" bitfld.word 0x2 15. "MTE,Media Access Test Symbol Transmission Enable" "0: MTS transmission disabled,1: MTS transmission enabled" newline hexmask.word.byte 0x2 8.--13. 1. "CYCCNTMSK,Cycle Counter Mask" newline hexmask.word.byte 0x2 0.--5. 1. "CYCCNTVAL,Cycle Counter Value" line.word 0x4 "RSBIR,Receive Shadow Buffer Index Register" bitfld.word 0x4 15. "WMD,Write Mode" "0: Update SEL and RSBIDX field on register write,1: Update only SEL field on register write" newline bitfld.word 0x4 12.--13. "SEL,Selector" "0: FR_RSBIR_A1: receive shadow buffer index..,1: FR_RSBIR_A2: receive shadow buffer index..,2: FR_RSBIR_B1: receive shadow buffer index..,3: FR_RSBIR_B2: receive shadow buffer index.." newline hexmask.word 0x4 0.--8. 1. "RSBIDXA1_RSBIDXA2_RSBIDXB1_RSBIDXB2,Receive Shadow Buffer Index" line.word 0x6 "RFWMSR,Receive FIFO Watermark and Selection Register" hexmask.word.byte 0x6 8.--15. 1. "WMA_WMB,Watermark" newline bitfld.word 0x6 0. "SEL,Select" "0: Receiver FIFO for channel A selected,1: Receiver FIFO for channel B selected" line.word 0x8 "RFSIR,Receive FIFO Start Index Register" hexmask.word 0x8 0.--9. 1. "SIDXA_SIDXB,Start Index" line.word 0xA "RFDSR,Receive FIFO Depth and Size Register" hexmask.word.byte 0xA 8.--15. 1. "FIFO_DEPTHA_FIFO_DEPTHB,FIFO Depth" newline hexmask.word.byte 0xA 0.--6. 1. "ENTRY_SIZEA_ENTRY_SIZEB,Entry Size" rgroup.word 0x8C++0x3 line.word 0x0 "RFARIR,Receive FIFO A Read Index Register" hexmask.word 0x0 0.--9. 1. "RDIDX,Read Index" line.word 0x2 "RFBRIR,Receive FIFO B Read Index Register" hexmask.word 0x2 0.--9. 1. "RDIDX,Read Index" group.word 0x90++0xB line.word 0x0 "RFMIDAFVR,Receive FIFO Message ID Acceptance Filter Value Register" hexmask.word 0x0 0.--15. 1. "MIDAFVALA_MIDAFVALB,Message ID Acceptance Filter Value" line.word 0x2 "RFMIDAFMR,Receive FIFO Message ID Acceptance Filter Mask Register" hexmask.word 0x2 0.--15. 1. "MIDAFMSKA_MIDAFMSKB,Message ID Acceptance Filter Mask" line.word 0x4 "RFFIDRFVR,Receive FIFO Frame ID Rejection Filter Value Register" hexmask.word 0x4 0.--10. 1. "FIDRFVALA_FIDRFVALB,Frame ID Rejection Filter Value" line.word 0x6 "RFFIDRFMR,Receive FIFO Frame ID Rejection Filter Mask Register" hexmask.word 0x6 0.--10. 1. "FIDRFMSKA_FIDRFMSKB,Frame ID Rejection Filter Mask" line.word 0x8 "RFRFCFR,Receive FIFO Range Filter Configuration Register" bitfld.word 0x8 15. "WMD,Write Mode" "0: Write to all fields in this register on write..,1: Write to SEL and IBD field only on write access" newline bitfld.word 0x8 14. "IBD,Interval Boundary" "0: Program lower interval boundary,1: Program upper interval boundary" newline bitfld.word 0x8 12.--13. "SEL,Filter Selector" "0: Select frame ID range filter 0,1: Select frame ID range filter 1,2: Select frame ID range filter 2,3: Select frame ID range filter 3" newline hexmask.word 0x8 0.--10. 1. "SIDA_SIDB,Slot ID" line.word 0xA "RFRFCTR,Receive FIFO Range Filter Control Register" bitfld.word 0xA 11. "F3MD,Range Filter 3 Mode" "0: Range filter 3 runs as acceptance filter,1: Range filter 3 runs as rejection filter" newline bitfld.word 0xA 10. "F2MD,Range Filter 2 Mode" "0: Range filter 2 runs as acceptance filter,1: Range filter 2 runs as rejection filter" newline bitfld.word 0xA 9. "F1MD,Range Filter 1 Mode" "0: Range filter 1 runs as acceptance filter,1: Range filter 1 runs as rejection filter" newline bitfld.word 0xA 8. "F0MD,Range Filter 0 Mode" "0: Range filter 0 runs as acceptance filter,1: Range filter 0 runs as rejection filter" newline bitfld.word 0xA 3. "F3EN,Range Filter 3 Enable" "0: Range filter 3 disabled,1: Range filter 3 enabled" newline bitfld.word 0xA 2. "F2EN,Range Filter 2 Enable" "0: Range filter 2 disabled,1: Range filter 2 enabled" newline bitfld.word 0xA 1. "F1EN,Range Filter 1 Enable" "0: Range filter 1 disabled,1: Range filter 1 enabled" newline bitfld.word 0xA 0. "F0EN,Range Filter 0 Enable" "0: Range filter 0 disabled,1: Range filter 0 enabled" rgroup.word 0x9C++0x3 line.word 0x0 "LDTXSLAR,Last Dynamic Transmit Slot Channel A Register" hexmask.word 0x0 0.--10. 1. "LDYNTXSLOTA,Last Dynamic Transmission Slot Channel A" line.word 0x2 "LDTXSLBR,Last Dynamic Transmit Slot Channel B Register" hexmask.word 0x2 0.--10. 1. "LDYNTXSLOTB,Last Dynamic Transmission Slot Channel B" group.word 0xA0++0x3D line.word 0x0 "PCR0,Protocol Configuration Register 0" hexmask.word.byte 0x0 10.--15. 1. "ACTION_POINT_OFFSET,gdActionPointOffset - 1" newline hexmask.word 0x0 0.--9. 1. "STATIC_SLOT_LENGTH,gdStaticSlot" line.word 0x2 "PCR1,Protocol Configuration Register 1" hexmask.word 0x2 0.--13. 1. "MACRO_AFTER_FIRST_STATIC_SLOT,gMacroPerCycle - gdStaticSlot" line.word 0x4 "PCR2,Protocol Configuration Register 2" hexmask.word.byte 0x4 10.--15. 1. "MINISLOT_AFTER_ACTION_POINT,gdMinislot - gdMinislotActionPointOffset - 1" newline hexmask.word 0x4 0.--9. 1. "NUMBER_OF_STATIC_SLOTS,gNumberOfStaticSlots" line.word 0x6 "PCR3,Protocol Configuration Register 3" hexmask.word.byte 0x6 10.--15. 1. "WAKEUP_SYMBOL_RX_LOW,gdWakeupSymbolRxLow" newline hexmask.word.byte 0x6 5.--9. 1. "MINISLOT_ACTION_POINT_OFFSET,gdMinislotActionPointOffset - 1" newline hexmask.word.byte 0x6 0.--4. 1. "COLDSTART_ATTEMPTS,gColdstartAttempts" line.word 0x8 "PCR4,Protocol Configuration Register 4" hexmask.word.byte 0x8 9.--15. 1. "CAS_RX_LOW_MAX,gdCASRxLowMax - 1" newline hexmask.word 0x8 0.--8. 1. "WAKEUP_SYMBOL_RX_WINDOW,gdWakeupSymbolRxWindow" line.word 0xA "PCR5,Protocol Configuration Register 5" hexmask.word.byte 0xA 12.--15. 1. "TSS_TRANSMITTER,gdTSSTransmitter" newline hexmask.word.byte 0xA 6.--11. 1. "WAKEUP_SYMBOL_TX_LOW,gdWakeupSymbolTxLow" newline hexmask.word.byte 0xA 0.--5. 1. "WAKEUP_SYMBOL_RX_IDLE,gdWakeupSymbolRxIdle" line.word 0xC "PCR6,Protocol Configuration Register 6" hexmask.word.byte 0xC 7.--14. 1. "SYMBOL_WINDOW_AFTER_ACTION_POINT,gdSymbolWindow - gdActionPointOffset - 0x1:" newline hexmask.word.byte 0xC 0.--6. 1. "MACRO_INITIAL_OFFSET_A,pMacroInitialOffset[A]" line.word 0xE "PCR7,Protocol Configuration Register 7" hexmask.word 0xE 7.--15. 1. "DECODING_CORRECTION_B,pDecodingCorrection + pDelayCompensation[B] + 2" newline hexmask.word.byte 0xE 0.--6. 1. "MICRO_PER_MACRO_NOM_HALF,round(pMicroPerMacroNom / 2)" line.word 0x10 "PCR8,Protocol Configuration Register 8" hexmask.word.byte 0x10 12.--15. 1. "MAX_WITHOUT_CLOCK_CORRECTION_FATAL,gMaxWithoutClockCorrectionFatal" newline hexmask.word.byte 0x10 8.--11. 1. "MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE,gMaxWithoutClockCorrectionPassive" newline hexmask.word.byte 0x10 0.--7. 1. "WAKEUP_SYMBOL_TX_IDLE,gdWakeupSymbolTxIdle" line.word 0x12 "PCR9,Protocol Configuration Register 9" bitfld.word 0x12 15. "MINISLOT_EXISTS,gNumberOfMinislots!=0" "0,1" newline bitfld.word 0x12 14. "SYMBOL_WINDOW_EXISTS,gdSymbolWindow!=0" "0,1" newline hexmask.word 0x12 0.--13. 1. "OFFSET_CORRECTION_OUT,pOffsetCorrectionOut" line.word 0x14 "PCR10,Protocol Configuration Register 10" bitfld.word 0x14 15. "SINGLE_SLOT_ENABLED,pSingleSlotEnabled" "0,1" newline bitfld.word 0x14 14. "WAKEUP_CHANNEL,pWakeupChannel" "0,1" newline hexmask.word 0x14 0.--13. 1. "MACRO_PER_CYCLE,gMacroPerCycle" line.word 0x16 "PCR11,Protocol Configuration Register 11" bitfld.word 0x16 15. "KEY_SLOT_USED_FOR_STARTUP,pKeySlotUsedForStartup" "0,1" newline bitfld.word 0x16 14. "KEY_SLOT_USED_FOR_SYNC,pKeySlotUsedForSync" "0,1" newline hexmask.word 0x16 0.--13. 1. "OFFSET_CORRECTION_START,gOffsetCorrectionStart" line.word 0x18 "PCR12,Protocol Configuration Register 12" hexmask.word.byte 0x18 11.--15. 1. "ALLOW_PASSIVE_TO_ACTIVE,pAllowPassiveToActive" newline hexmask.word 0x18 0.--10. 1. "KEY_SLOT_HEADER_CRC,header CRC for key slot" line.word 0x1A "PCR13,Protocol Configuration Register 13" hexmask.word.byte 0x1A 10.--15. 1. "FIRST_MINISLOT_ACTION_POINT_OFFSET,max(gdActionPointOffset gdMinislotActionPointOffset) - 1" newline hexmask.word 0x1A 0.--9. 1. "STATIC_SLOT_AFTER_ACTION_POINT,gdStaticSlot - gdActionPointOffset - 1" line.word 0x1C "PCR14,Protocol Configuration Register 14" hexmask.word 0x1C 5.--15. 1. "RATE_CORRECTION_OUT,pRateCorrectionOut" newline hexmask.word.byte 0x1C 0.--4. 1. "LISTEN_TIMEOUT,[20:16]" line.word 0x1E "PCR15,Protocol Configuration Register 15" hexmask.word 0x1E 0.--15. 1. "LISTEN_TIMEOUT,[15:0]" line.word 0x20 "PCR16,Protocol Configuration Register 16" hexmask.word.byte 0x20 9.--15. 1. "MACRO_INITIAL_OFFSET_B,pMacroInitialOffset[B]" newline hexmask.word 0x20 0.--8. 1. "NOISE_LISTEN_TIMEOUT,[24:16]" line.word 0x22 "PCR17,Protocol Configuration Register 17" hexmask.word 0x22 0.--15. 1. "NOISE_LISTEN_TIMEOUT,[15:0]" line.word 0x24 "PCR18,Protocol Configuration Register 18" hexmask.word.byte 0x24 10.--15. 1. "WAKEUP_PATTERN,pWakeupPattern" newline hexmask.word 0x24 0.--9. 1. "KEY_SLOT_ID,pKeySlotId" line.word 0x26 "PCR19,Protocol Configuration Register 19" hexmask.word 0x26 7.--15. 1. "DECODING_CORRECTION_A,pDecodingCorrection + pDelayCompensation[A] + 2" newline hexmask.word.byte 0x26 0.--6. 1. "PAYLOAD_LENGTH_STATIC,gPayloadLengthStatic" line.word 0x28 "PCR20,Protocol Configuration Register 20" hexmask.word.byte 0x28 8.--15. 1. "MICRO_INITIAL_OFFSET_B,pMicroInitialOffset[B]" newline hexmask.word.byte 0x28 0.--7. 1. "MICRO_INITIAL_OFFSET_A,pMicroInitialOffset[A]" line.word 0x2A "PCR21,Protocol Configuration Register 21" bitfld.word 0x2A 13.--15. "EXTERN_RATE_CORRECTION,pExternRateCorrection" "0,1,2,3,4,5,6,7" newline hexmask.word 0x2A 0.--12. 1. "LATEST_TX,gNumberOfMinislots - pLatestTx" line.word 0x2C "PCR22,Protocol Configuration Register 22" hexmask.word 0x2C 4.--14. 1. "COMP_ACCEPTED_STARTUP_RANGE_A,pdAcceptedStartupRange - pDelayCompensation[A]" newline hexmask.word.byte 0x2C 0.--3. 1. "MICRO_PER_CYCLE,[19:16]" line.word 0x2E "PCR23,Protocol Configuration Register 23" hexmask.word 0x2E 0.--15. 1. "MICRO_PER_CYCLE,[15:0]" line.word 0x30 "PCR24,Protocol Configuration Register 24" hexmask.word.byte 0x30 11.--15. 1. "CLUSTER_DRIFT_DAMPING,pClusterDriftDamping" newline hexmask.word.byte 0x30 4.--10. 1. "MAX_PAYLOAD_LENGTH_DYNAMIC,pPayloadLengthDynMax" newline hexmask.word.byte 0x30 0.--3. 1. "MICRO_PER_CYCLE_MIN,[19:16]" line.word 0x32 "PCR25,Protocol Configuration Register 25" hexmask.word 0x32 0.--15. 1. "MICRO_PER_CYCLE_MIN,[15:0]" line.word 0x34 "PCR26,Protocol Configuration Register 26" bitfld.word 0x34 15. "ALLOW_HALT_DUE_TO_CLOCK,pAllowHaltDueToClock" "0,1" newline hexmask.word 0x34 4.--14. 1. "COMP_ACCEPTED_STARTUP_RANGE_B,pdAcceptedStartupRange - pDelayCompensation[B]" newline hexmask.word.byte 0x34 0.--3. 1. "MICRO_PER_CYCLE_MAX,[19:16]" line.word 0x36 "PCR27,Protocol Configuration Register 27" hexmask.word 0x36 0.--15. 1. "MICRO_PER_CYCLE_MAX,[15:0]" line.word 0x38 "PCR28,Protocol Configuration Register 28" bitfld.word 0x38 14.--15. "DYNAMIC_SLOT_IDLE_PHASE,gdDynamicSlotIdlePhase" "0,1,2,3" newline hexmask.word 0x38 0.--13. 1. "MACRO_AFTER_OFFSET_CORRECTION,gMacroPerCycle - gOffsetCorrectionStart" line.word 0x3A "PCR29,Protocol Configuration Register 29" bitfld.word 0x3A 13.--15. "EXTERN_OFFSET_CORRECTION,pExternOffsetCorrection" "0,1,2,3,4,5,6,7" newline hexmask.word 0x3A 0.--12. 1. "MINISLOTS_MAX,gNumberOfMinislots - 1" line.word 0x3C "PCR30,Protocol Configuration Register 30" hexmask.word.byte 0x3C 0.--3. 1. "SYNC_NODE_MAX,gSyncNodeMax" rgroup.word 0xDE++0x3 line.word 0x0 "STPWRHR,Stop Watch Count Register" hexmask.word 0x0 0.--15. 1. "STPW,Stop Watch Count Register" line.word 0x2 "STPWRLR,Stop Watch Count Register" hexmask.word 0x2 0.--15. 1. "STPW,Stop Watch Count Register" group.word 0xE2++0x1 line.word 0x0 "PEOER,Protocol Event Output Enable and StopWatch Control Register" bitfld.word 0x0 8. "STPW_EN,Stop watch count Enable" "0: Stopwatch counter disabled,1: Stopwatch counter enabled" newline bitfld.word 0x0 2. "TIM2_EE,Timer 2 expired Event Output Enable" "0: Timer 2 expired event out disabled,1: Timer 2 expired event out enabled" newline bitfld.word 0x0 1. "TIM1_EE,Timer 1 expired Event Output Enable" "0: Timer 1 expired event out disabled,1: Timer 1 expired event out enabled" newline bitfld.word 0x0 0. "CYS_EE,Cycle Start Event Output Enable" "0: Cycle start event out disabled,1: Cycle start event out enabled" group.word 0xE6++0xD line.word 0x0 "RFSDOR,Receive FIFO Start Data Offset Register" hexmask.word 0x0 0.--15. 1. "SDOA_SDOB,Start Data Field Offset" line.word 0x2 "RFSYMBADRHR,Receive FIFO System Memory Base Address Register" hexmask.word 0x2 0.--15. 1. "SMBA,System Memory Base Address" line.word 0x4 "RFSYMBADRLR,Receive FIFO System Memory Base Address Register" hexmask.word 0x4 4.--15. 1. "SMBA,System Memory Base Address" line.word 0x6 "RFPTR,Receive FIFO Periodic Timer Register" hexmask.word 0x6 0.--13. 1. "PTD,Periodic Timer Duration" line.word 0x8 "RFFLPCR,Receive FIFO Fill Level and POP Count Register" hexmask.word.byte 0x8 8.--15. 1. "FLB_PCB,Fill Level FIFO B (FLB)" newline hexmask.word.byte 0x8 0.--7. 1. "FLA_PCA,Fill Level FIFO A (FLA)" line.word 0xA "EEIFER,ECC Error Interrupt Flag and Enable Register" bitfld.word 0xA 15. "LRNE_OF,LRAM Non-Corrected Error Overflow Flag" "0: No such event,1: Non-Corrected Error overflow detected on CHI LRAM" newline bitfld.word 0xA 14. "LRCE_OF,LRAM Corrected Error Overflow Flag" "0: No such event,1: Corrected Error overflow detected on CHI LRAM" newline bitfld.word 0xA 13. "DRNE_OF,DRAM Non-Corrected Error Overflow Flag" "0: No such event,1: Non-Corrected Error overflow detected on PE DRAM" newline bitfld.word 0xA 12. "DRCE_OF,DRAM Corrected Error Overflow Flag" "0: No such event,1: Corrected Error overflow detected on PE DRAM" newline bitfld.word 0xA 11. "LRNE_IF,LRAM Non-Corrected Error Interrupt Flag" "0: No such event,1: Non-Corrected Error detected on CHI LRAM" newline bitfld.word 0xA 10. "LRCE_IF,LRAM Corrected Error Interrupt Flag" "0: No such event,1: Corrected Error detected on CHI LRAM" newline bitfld.word 0xA 9. "DRNE_IF,DRAM Non-Corrected Error Interrupt Flag" "0: No such event,1: Non-Corrected Error detected on PE DRAM" newline bitfld.word 0xA 8. "DRCE_IF,DRAM Corrected Error Interrupt Flag" "0: No such event,1: Corrected Error detected on PE DRAM" newline bitfld.word 0xA 3. "LRNE_IE,LRAM Non-Corrected Error Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" newline bitfld.word 0xA 2. "LRCE_IE,LRAM Corrected Error Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" newline bitfld.word 0xA 1. "DRNE_IE,DRAM Non-Corrected Error Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" newline bitfld.word 0xA 0. "DRCE_IE,DRAM Corrected Error Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" line.word 0xC "EERICR,ECC Error Report and Injection Control Register" bitfld.word 0xC 15. "BSY,Register Update Busy" "0: ECC configuration is idle,1: ECC configuration is running" newline bitfld.word 0xC 8.--9. "ERS,Error Report Select" "0: Show PE DRAM non-corrected error information,1: Show PE DRAM corrected error information,2: Show CHI LRAM non-corrected error information,3: Show CHI LRAM corrected error information" newline bitfld.word 0xC 4. "ERM,Error Report Mode" "0: Store data and code as delivered by ECC decoding..,1: Store data and code as read from the memory" newline bitfld.word 0xC 1. "EIM,Error Injection Mode" "0: Use FR_EEIDR[DATA] and FR_EEICR[CODE] as XOR..,1: Use FR_EEIDR[DATA] and FR_EEICR[CODE] as write.." newline bitfld.word 0xC 0. "EIE,Error Injection Enable" "0: Error injection disabled,1: Error injection enabled" rgroup.word 0xF4++0x5 line.word 0x0 "EERAR,ECC Error Report Address Register" bitfld.word 0x0 15. "MID,Memory Identifier" "0: PE DRAM,1: CHI LRAM" newline bitfld.word 0x0 12.--14. "BANK,Memory Bank" "0: PE DRAM [7:0],1: PE DRAM [15:8],?,?,?,?,?,7: Reset value indicates no error found after reset." newline hexmask.word 0x0 0.--11. 1. "ADDR,Memory Address" line.word 0x2 "EERDR,ECC Error Report Data Register" hexmask.word 0x2 0.--15. 1. "DATA,Data" line.word 0x4 "EERCR,ECC Error Report Code Register" hexmask.word.byte 0x4 0.--4. 1. "CODE,Code" group.word 0xFA++0x5 line.word 0x0 "EEIAR,ECC Error Injection Address Register" bitfld.word 0x0 15. "MID,Memory Identifier" "0: PE DRAM,1: CHI LRAM" newline bitfld.word 0x0 12.--14. "BANK,Memory Bank" "0: BANK0: PE DRAM [7:0],1: BANK1: PE DRAM [15:8],?,?,?,?,?,?" newline hexmask.word 0x0 0.--11. 1. "ADDR,Memory Address" line.word 0x2 "EEIDR,ECC Error Injection Data Register" hexmask.word 0x2 0.--15. 1. "DATA,Data" line.word 0x4 "EEICR,ECC Error Injection Code Register" hexmask.word.byte 0x4 0.--4. 1. "CODE,Code" group.word 0x800++0xA07 line.word 0x0 "MBCCSR0,Message Buffer Configuratio0. Control and Status Register 0" bitfld.word 0x0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2 "MBCCFR0,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4 "MBFIDR0,Message Buffer Frame ID Registers" hexmask.word 0x4 0.--10. 1. "FID,Frame ID" line.word 0x6 "MBIDXR0,Message Buffer Index Registers" hexmask.word 0x6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x8 "MBCCSR1,Message Buffer Configuratio1. Control and Status Register 1" bitfld.word 0x8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xA "MBCCFR1,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xC "MBFIDR1,Message Buffer Frame ID Registers" hexmask.word 0xC 0.--10. 1. "FID,Frame ID" line.word 0xE "MBIDXR1,Message Buffer Index Registers" hexmask.word 0xE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x10 "MBCCSR2,Message Buffer Configuratio2. Control and Status Register 2" bitfld.word 0x10 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x10 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x10 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x10 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x10 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x10 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x10 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x10 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x10 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x10 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x12 "MBCCFR2,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x12 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x12 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x12 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x12 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x12 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x12 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x14 "MBFIDR2,Message Buffer Frame ID Registers" hexmask.word 0x14 0.--10. 1. "FID,Frame ID" line.word 0x16 "MBIDXR2,Message Buffer Index Registers" hexmask.word 0x16 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x18 "MBCCSR3,Message Buffer Configuratio3. Control and Status Register 3" bitfld.word 0x18 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x18 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x18 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x18 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x18 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x18 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x18 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x18 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x18 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x18 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1A "MBCCFR3,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1C "MBFIDR3,Message Buffer Frame ID Registers" hexmask.word 0x1C 0.--10. 1. "FID,Frame ID" line.word 0x1E "MBIDXR3,Message Buffer Index Registers" hexmask.word 0x1E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x20 "MBCCSR4,Message Buffer Configuratio4. Control and Status Register 4" bitfld.word 0x20 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x20 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x20 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x20 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x20 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x20 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x20 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x20 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x20 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x20 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x22 "MBCCFR4,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x22 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x22 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x22 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x22 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x22 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x22 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x24 "MBFIDR4,Message Buffer Frame ID Registers" hexmask.word 0x24 0.--10. 1. "FID,Frame ID" line.word 0x26 "MBIDXR4,Message Buffer Index Registers" hexmask.word 0x26 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x28 "MBCCSR5,Message Buffer Configuratio5. Control and Status Register 5" bitfld.word 0x28 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x28 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x28 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x28 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x28 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x28 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x28 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x28 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x28 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x28 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2A "MBCCFR5,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2C "MBFIDR5,Message Buffer Frame ID Registers" hexmask.word 0x2C 0.--10. 1. "FID,Frame ID" line.word 0x2E "MBIDXR5,Message Buffer Index Registers" hexmask.word 0x2E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x30 "MBCCSR6,Message Buffer Configuratio6. Control and Status Register 6" bitfld.word 0x30 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x30 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x30 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x30 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x30 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x30 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x30 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x30 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x30 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x30 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x32 "MBCCFR6,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x32 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x32 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x32 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x32 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x32 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x32 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x34 "MBFIDR6,Message Buffer Frame ID Registers" hexmask.word 0x34 0.--10. 1. "FID,Frame ID" line.word 0x36 "MBIDXR6,Message Buffer Index Registers" hexmask.word 0x36 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x38 "MBCCSR7,Message Buffer Configuratio7. Control and Status Register 7" bitfld.word 0x38 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x38 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x38 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x38 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x38 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x38 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x38 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x38 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x38 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x38 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3A "MBCCFR7,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3C "MBFIDR7,Message Buffer Frame ID Registers" hexmask.word 0x3C 0.--10. 1. "FID,Frame ID" line.word 0x3E "MBIDXR7,Message Buffer Index Registers" hexmask.word 0x3E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x40 "MBCCSR8,Message Buffer Configuratio8. Control and Status Register 8" bitfld.word 0x40 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x40 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x40 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x40 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x40 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x40 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x40 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x40 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x40 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x40 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x42 "MBCCFR8,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x42 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x42 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x42 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x42 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x42 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x42 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x44 "MBFIDR8,Message Buffer Frame ID Registers" hexmask.word 0x44 0.--10. 1. "FID,Frame ID" line.word 0x46 "MBIDXR8,Message Buffer Index Registers" hexmask.word 0x46 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x48 "MBCCSR9,Message Buffer Configuratio9. Control and Status Register 9" bitfld.word 0x48 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x48 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x48 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x48 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x48 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x48 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x48 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x48 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x48 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x48 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4A "MBCCFR9,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4C "MBFIDR9,Message Buffer Frame ID Registers" hexmask.word 0x4C 0.--10. 1. "FID,Frame ID" line.word 0x4E "MBIDXR9,Message Buffer Index Registers" hexmask.word 0x4E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x50 "MBCCSR10,Message Buffer Configuratio10. Control and Status Register 10" bitfld.word 0x50 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x50 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x50 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x50 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x50 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x50 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x50 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x50 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x50 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x50 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x52 "MBCCFR10,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x52 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x52 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x52 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x52 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x52 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x52 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x54 "MBFIDR10,Message Buffer Frame ID Registers" hexmask.word 0x54 0.--10. 1. "FID,Frame ID" line.word 0x56 "MBIDXR10,Message Buffer Index Registers" hexmask.word 0x56 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x58 "MBCCSR11,Message Buffer Configuratio11. Control and Status Register 11" bitfld.word 0x58 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x58 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x58 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x58 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x58 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x58 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x58 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x58 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x58 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x58 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5A "MBCCFR11,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5C "MBFIDR11,Message Buffer Frame ID Registers" hexmask.word 0x5C 0.--10. 1. "FID,Frame ID" line.word 0x5E "MBIDXR11,Message Buffer Index Registers" hexmask.word 0x5E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x60 "MBCCSR12,Message Buffer Configuratio12. Control and Status Register 12" bitfld.word 0x60 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x60 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x60 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x60 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x60 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x60 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x60 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x60 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x60 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x60 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x62 "MBCCFR12,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x62 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x62 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x62 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x62 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x62 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x62 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x64 "MBFIDR12,Message Buffer Frame ID Registers" hexmask.word 0x64 0.--10. 1. "FID,Frame ID" line.word 0x66 "MBIDXR12,Message Buffer Index Registers" hexmask.word 0x66 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x68 "MBCCSR13,Message Buffer Configuratio13. Control and Status Register 13" bitfld.word 0x68 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x68 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x68 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x68 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x68 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x68 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x68 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x68 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x68 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x68 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6A "MBCCFR13,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6C "MBFIDR13,Message Buffer Frame ID Registers" hexmask.word 0x6C 0.--10. 1. "FID,Frame ID" line.word 0x6E "MBIDXR13,Message Buffer Index Registers" hexmask.word 0x6E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x70 "MBCCSR14,Message Buffer Configuratio14. Control and Status Register 14" bitfld.word 0x70 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x70 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x70 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x70 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x70 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x70 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x70 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x70 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x70 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x70 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x72 "MBCCFR14,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x72 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x72 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x72 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x72 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x72 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x72 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x74 "MBFIDR14,Message Buffer Frame ID Registers" hexmask.word 0x74 0.--10. 1. "FID,Frame ID" line.word 0x76 "MBIDXR14,Message Buffer Index Registers" hexmask.word 0x76 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x78 "MBCCSR15,Message Buffer Configuratio15. Control and Status Register 15" bitfld.word 0x78 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x78 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x78 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x78 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x78 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x78 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x78 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x78 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x78 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x78 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7A "MBCCFR15,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7C "MBFIDR15,Message Buffer Frame ID Registers" hexmask.word 0x7C 0.--10. 1. "FID,Frame ID" line.word 0x7E "MBIDXR15,Message Buffer Index Registers" hexmask.word 0x7E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x80 "MBCCSR16,Message Buffer Configuratio16. Control and Status Register 16" bitfld.word 0x80 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x80 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x80 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x80 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x80 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x80 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x80 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x80 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x80 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x80 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x82 "MBCCFR16,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x82 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x82 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x82 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x82 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x82 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x82 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x84 "MBFIDR16,Message Buffer Frame ID Registers" hexmask.word 0x84 0.--10. 1. "FID,Frame ID" line.word 0x86 "MBIDXR16,Message Buffer Index Registers" hexmask.word 0x86 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x88 "MBCCSR17,Message Buffer Configuratio17. Control and Status Register 17" bitfld.word 0x88 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x88 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x88 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x88 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x88 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x88 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x88 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x88 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x88 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x88 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x8A "MBCCFR17,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x8A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x8A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x8A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x8A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x8A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x8A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x8C "MBFIDR17,Message Buffer Frame ID Registers" hexmask.word 0x8C 0.--10. 1. "FID,Frame ID" line.word 0x8E "MBIDXR17,Message Buffer Index Registers" hexmask.word 0x8E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x90 "MBCCSR18,Message Buffer Configuratio18. Control and Status Register 18" bitfld.word 0x90 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x90 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x90 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x90 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x90 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x90 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x90 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x90 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x90 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x90 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x92 "MBCCFR18,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x92 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x92 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x92 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x92 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x92 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x92 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x94 "MBFIDR18,Message Buffer Frame ID Registers" hexmask.word 0x94 0.--10. 1. "FID,Frame ID" line.word 0x96 "MBIDXR18,Message Buffer Index Registers" hexmask.word 0x96 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x98 "MBCCSR19,Message Buffer Configuratio19. Control and Status Register 19" bitfld.word 0x98 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x98 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x98 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x98 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x98 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x98 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x98 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x98 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x98 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x98 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x9A "MBCCFR19,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x9A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x9A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x9A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x9A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x9A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x9A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x9C "MBFIDR19,Message Buffer Frame ID Registers" hexmask.word 0x9C 0.--10. 1. "FID,Frame ID" line.word 0x9E "MBIDXR19,Message Buffer Index Registers" hexmask.word 0x9E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xA0 "MBCCSR20,Message Buffer Configuratio20. Control and Status Register 20" bitfld.word 0xA0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xA0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xA0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xA0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xA0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xA0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xA0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xA0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xA0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xA0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xA2 "MBCCFR20,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xA2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xA2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xA2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xA2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xA2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xA2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xA4 "MBFIDR20,Message Buffer Frame ID Registers" hexmask.word 0xA4 0.--10. 1. "FID,Frame ID" line.word 0xA6 "MBIDXR20,Message Buffer Index Registers" hexmask.word 0xA6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xA8 "MBCCSR21,Message Buffer Configuratio21. Control and Status Register 21" bitfld.word 0xA8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xA8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xA8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xA8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xA8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xA8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xA8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xA8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xA8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xA8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xAA "MBCCFR21,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xAA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xAA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xAA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xAA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xAA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xAA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xAC "MBFIDR21,Message Buffer Frame ID Registers" hexmask.word 0xAC 0.--10. 1. "FID,Frame ID" line.word 0xAE "MBIDXR21,Message Buffer Index Registers" hexmask.word 0xAE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xB0 "MBCCSR22,Message Buffer Configuratio22. Control and Status Register 22" bitfld.word 0xB0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xB0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xB0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xB0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xB0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xB0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xB0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xB0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xB0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xB0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xB2 "MBCCFR22,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xB2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xB2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xB2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xB2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xB2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xB2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xB4 "MBFIDR22,Message Buffer Frame ID Registers" hexmask.word 0xB4 0.--10. 1. "FID,Frame ID" line.word 0xB6 "MBIDXR22,Message Buffer Index Registers" hexmask.word 0xB6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xB8 "MBCCSR23,Message Buffer Configuratio23. Control and Status Register 23" bitfld.word 0xB8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xB8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xB8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xB8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xB8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xB8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xB8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xB8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xB8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xB8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xBA "MBCCFR23,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xBA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xBA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xBA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xBA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xBA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xBA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xBC "MBFIDR23,Message Buffer Frame ID Registers" hexmask.word 0xBC 0.--10. 1. "FID,Frame ID" line.word 0xBE "MBIDXR23,Message Buffer Index Registers" hexmask.word 0xBE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xC0 "MBCCSR24,Message Buffer Configuratio24. Control and Status Register 24" bitfld.word 0xC0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xC0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xC0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xC0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xC0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xC0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xC0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xC0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xC0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xC0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xC2 "MBCCFR24,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xC2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xC2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xC2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xC2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xC2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xC2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xC4 "MBFIDR24,Message Buffer Frame ID Registers" hexmask.word 0xC4 0.--10. 1. "FID,Frame ID" line.word 0xC6 "MBIDXR24,Message Buffer Index Registers" hexmask.word 0xC6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xC8 "MBCCSR25,Message Buffer Configuratio25. Control and Status Register 25" bitfld.word 0xC8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xC8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xC8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xC8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xC8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xC8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xC8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xC8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xC8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xC8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xCA "MBCCFR25,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xCA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xCA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xCA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xCA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xCA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xCA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xCC "MBFIDR25,Message Buffer Frame ID Registers" hexmask.word 0xCC 0.--10. 1. "FID,Frame ID" line.word 0xCE "MBIDXR25,Message Buffer Index Registers" hexmask.word 0xCE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xD0 "MBCCSR26,Message Buffer Configuratio26. Control and Status Register 26" bitfld.word 0xD0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xD0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xD0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xD0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xD0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xD0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xD0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xD0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xD0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xD0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xD2 "MBCCFR26,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xD2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xD2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xD2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xD2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xD2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xD2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xD4 "MBFIDR26,Message Buffer Frame ID Registers" hexmask.word 0xD4 0.--10. 1. "FID,Frame ID" line.word 0xD6 "MBIDXR26,Message Buffer Index Registers" hexmask.word 0xD6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xD8 "MBCCSR27,Message Buffer Configuratio27. Control and Status Register 27" bitfld.word 0xD8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xD8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xD8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xD8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xD8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xD8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xD8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xD8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xD8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xD8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xDA "MBCCFR27,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xDA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xDA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xDA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xDA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xDA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xDA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xDC "MBFIDR27,Message Buffer Frame ID Registers" hexmask.word 0xDC 0.--10. 1. "FID,Frame ID" line.word 0xDE "MBIDXR27,Message Buffer Index Registers" hexmask.word 0xDE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xE0 "MBCCSR28,Message Buffer Configuratio28. Control and Status Register 28" bitfld.word 0xE0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xE0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xE0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xE0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xE0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xE0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xE0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xE0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xE0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xE0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xE2 "MBCCFR28,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xE2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xE2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xE2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xE2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xE2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xE2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xE4 "MBFIDR28,Message Buffer Frame ID Registers" hexmask.word 0xE4 0.--10. 1. "FID,Frame ID" line.word 0xE6 "MBIDXR28,Message Buffer Index Registers" hexmask.word 0xE6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xE8 "MBCCSR29,Message Buffer Configuratio29. Control and Status Register 29" bitfld.word 0xE8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xE8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xE8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xE8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xE8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xE8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xE8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xE8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xE8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xE8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xEA "MBCCFR29,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xEA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xEA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xEA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xEA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xEA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xEA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xEC "MBFIDR29,Message Buffer Frame ID Registers" hexmask.word 0xEC 0.--10. 1. "FID,Frame ID" line.word 0xEE "MBIDXR29,Message Buffer Index Registers" hexmask.word 0xEE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xF0 "MBCCSR30,Message Buffer Configuratio30. Control and Status Register 30" bitfld.word 0xF0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xF0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xF0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xF0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xF0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xF0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xF0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xF0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xF0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xF0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xF2 "MBCCFR30,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xF2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xF2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xF2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xF2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xF2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xF2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xF4 "MBFIDR30,Message Buffer Frame ID Registers" hexmask.word 0xF4 0.--10. 1. "FID,Frame ID" line.word 0xF6 "MBIDXR30,Message Buffer Index Registers" hexmask.word 0xF6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xF8 "MBCCSR31,Message Buffer Configuratio31. Control and Status Register 31" bitfld.word 0xF8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xF8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xF8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xF8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xF8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xF8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xF8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xF8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xF8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xF8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xFA "MBCCFR31,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xFA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xFA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xFA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xFA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xFA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xFA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xFC "MBFIDR31,Message Buffer Frame ID Registers" hexmask.word 0xFC 0.--10. 1. "FID,Frame ID" line.word 0xFE "MBIDXR31,Message Buffer Index Registers" hexmask.word 0xFE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x100 "MBCCSR32,Message Buffer Configuratio32. Control and Status Register 32" bitfld.word 0x100 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x100 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x100 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x100 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x100 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x100 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x100 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x100 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x100 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x100 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x102 "MBCCFR32,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x102 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x102 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x102 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x102 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x102 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x102 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x104 "MBFIDR32,Message Buffer Frame ID Registers" hexmask.word 0x104 0.--10. 1. "FID,Frame ID" line.word 0x106 "MBIDXR32,Message Buffer Index Registers" hexmask.word 0x106 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x108 "MBCCSR33,Message Buffer Configuratio33. Control and Status Register 33" bitfld.word 0x108 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x108 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x108 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x108 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x108 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x108 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x108 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x108 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x108 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x108 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x10A "MBCCFR33,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x10A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x10A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x10A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x10A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x10A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x10A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x10C "MBFIDR33,Message Buffer Frame ID Registers" hexmask.word 0x10C 0.--10. 1. "FID,Frame ID" line.word 0x10E "MBIDXR33,Message Buffer Index Registers" hexmask.word 0x10E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x110 "MBCCSR34,Message Buffer Configuratio34. Control and Status Register 34" bitfld.word 0x110 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x110 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x110 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x110 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x110 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x110 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x110 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x110 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x110 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x110 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x112 "MBCCFR34,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x112 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x112 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x112 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x112 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x112 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x112 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x114 "MBFIDR34,Message Buffer Frame ID Registers" hexmask.word 0x114 0.--10. 1. "FID,Frame ID" line.word 0x116 "MBIDXR34,Message Buffer Index Registers" hexmask.word 0x116 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x118 "MBCCSR35,Message Buffer Configuratio35. Control and Status Register 35" bitfld.word 0x118 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x118 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x118 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x118 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x118 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x118 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x118 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x118 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x118 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x118 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x11A "MBCCFR35,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x11A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x11A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x11A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x11A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x11A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x11A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x11C "MBFIDR35,Message Buffer Frame ID Registers" hexmask.word 0x11C 0.--10. 1. "FID,Frame ID" line.word 0x11E "MBIDXR35,Message Buffer Index Registers" hexmask.word 0x11E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x120 "MBCCSR36,Message Buffer Configuratio36. Control and Status Register 36" bitfld.word 0x120 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x120 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x120 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x120 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x120 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x120 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x120 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x120 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x120 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x120 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x122 "MBCCFR36,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x122 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x122 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x122 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x122 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x122 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x122 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x124 "MBFIDR36,Message Buffer Frame ID Registers" hexmask.word 0x124 0.--10. 1. "FID,Frame ID" line.word 0x126 "MBIDXR36,Message Buffer Index Registers" hexmask.word 0x126 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x128 "MBCCSR37,Message Buffer Configuratio37. Control and Status Register 37" bitfld.word 0x128 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x128 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x128 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x128 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x128 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x128 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x128 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x128 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x128 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x128 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x12A "MBCCFR37,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x12A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x12A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x12A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x12A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x12A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x12A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x12C "MBFIDR37,Message Buffer Frame ID Registers" hexmask.word 0x12C 0.--10. 1. "FID,Frame ID" line.word 0x12E "MBIDXR37,Message Buffer Index Registers" hexmask.word 0x12E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x130 "MBCCSR38,Message Buffer Configuratio38. Control and Status Register 38" bitfld.word 0x130 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x130 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x130 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x130 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x130 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x130 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x130 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x130 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x130 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x130 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x132 "MBCCFR38,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x132 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x132 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x132 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x132 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x132 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x132 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x134 "MBFIDR38,Message Buffer Frame ID Registers" hexmask.word 0x134 0.--10. 1. "FID,Frame ID" line.word 0x136 "MBIDXR38,Message Buffer Index Registers" hexmask.word 0x136 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x138 "MBCCSR39,Message Buffer Configuratio39. Control and Status Register 39" bitfld.word 0x138 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x138 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x138 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x138 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x138 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x138 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x138 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x138 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x138 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x138 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x13A "MBCCFR39,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x13A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x13A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x13A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x13A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x13A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x13A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x13C "MBFIDR39,Message Buffer Frame ID Registers" hexmask.word 0x13C 0.--10. 1. "FID,Frame ID" line.word 0x13E "MBIDXR39,Message Buffer Index Registers" hexmask.word 0x13E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x140 "MBCCSR40,Message Buffer Configuratio40. Control and Status Register 40" bitfld.word 0x140 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x140 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x140 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x140 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x140 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x140 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x140 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x140 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x140 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x140 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x142 "MBCCFR40,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x142 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x142 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x142 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x142 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x142 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x142 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x144 "MBFIDR40,Message Buffer Frame ID Registers" hexmask.word 0x144 0.--10. 1. "FID,Frame ID" line.word 0x146 "MBIDXR40,Message Buffer Index Registers" hexmask.word 0x146 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x148 "MBCCSR41,Message Buffer Configuratio41. Control and Status Register 41" bitfld.word 0x148 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x148 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x148 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x148 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x148 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x148 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x148 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x148 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x148 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x148 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x14A "MBCCFR41,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x14A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x14A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x14A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x14A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x14A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x14A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x14C "MBFIDR41,Message Buffer Frame ID Registers" hexmask.word 0x14C 0.--10. 1. "FID,Frame ID" line.word 0x14E "MBIDXR41,Message Buffer Index Registers" hexmask.word 0x14E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x150 "MBCCSR42,Message Buffer Configuratio42. Control and Status Register 42" bitfld.word 0x150 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x150 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x150 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x150 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x150 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x150 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x150 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x150 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x150 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x150 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x152 "MBCCFR42,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x152 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x152 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x152 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x152 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x152 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x152 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x154 "MBFIDR42,Message Buffer Frame ID Registers" hexmask.word 0x154 0.--10. 1. "FID,Frame ID" line.word 0x156 "MBIDXR42,Message Buffer Index Registers" hexmask.word 0x156 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x158 "MBCCSR43,Message Buffer Configuratio43. Control and Status Register 43" bitfld.word 0x158 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x158 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x158 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x158 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x158 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x158 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x158 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x158 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x158 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x158 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x15A "MBCCFR43,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x15A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x15A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x15A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x15A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x15A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x15A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x15C "MBFIDR43,Message Buffer Frame ID Registers" hexmask.word 0x15C 0.--10. 1. "FID,Frame ID" line.word 0x15E "MBIDXR43,Message Buffer Index Registers" hexmask.word 0x15E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x160 "MBCCSR44,Message Buffer Configuratio44. Control and Status Register 44" bitfld.word 0x160 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x160 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x160 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x160 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x160 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x160 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x160 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x160 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x160 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x160 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x162 "MBCCFR44,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x162 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x162 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x162 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x162 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x162 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x162 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x164 "MBFIDR44,Message Buffer Frame ID Registers" hexmask.word 0x164 0.--10. 1. "FID,Frame ID" line.word 0x166 "MBIDXR44,Message Buffer Index Registers" hexmask.word 0x166 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x168 "MBCCSR45,Message Buffer Configuratio45. Control and Status Register 45" bitfld.word 0x168 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x168 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x168 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x168 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x168 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x168 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x168 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x168 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x168 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x168 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x16A "MBCCFR45,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x16A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x16A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x16A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x16A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x16A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x16A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x16C "MBFIDR45,Message Buffer Frame ID Registers" hexmask.word 0x16C 0.--10. 1. "FID,Frame ID" line.word 0x16E "MBIDXR45,Message Buffer Index Registers" hexmask.word 0x16E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x170 "MBCCSR46,Message Buffer Configuratio46. Control and Status Register 46" bitfld.word 0x170 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x170 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x170 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x170 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x170 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x170 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x170 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x170 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x170 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x170 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x172 "MBCCFR46,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x172 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x172 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x172 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x172 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x172 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x172 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x174 "MBFIDR46,Message Buffer Frame ID Registers" hexmask.word 0x174 0.--10. 1. "FID,Frame ID" line.word 0x176 "MBIDXR46,Message Buffer Index Registers" hexmask.word 0x176 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x178 "MBCCSR47,Message Buffer Configuratio47. Control and Status Register 47" bitfld.word 0x178 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x178 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x178 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x178 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x178 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x178 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x178 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x178 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x178 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x178 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x17A "MBCCFR47,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x17A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x17A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x17A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x17A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x17A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x17A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x17C "MBFIDR47,Message Buffer Frame ID Registers" hexmask.word 0x17C 0.--10. 1. "FID,Frame ID" line.word 0x17E "MBIDXR47,Message Buffer Index Registers" hexmask.word 0x17E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x180 "MBCCSR48,Message Buffer Configuratio48. Control and Status Register 48" bitfld.word 0x180 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x180 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x180 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x180 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x180 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x180 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x180 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x180 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x180 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x180 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x182 "MBCCFR48,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x182 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x182 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x182 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x182 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x182 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x182 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x184 "MBFIDR48,Message Buffer Frame ID Registers" hexmask.word 0x184 0.--10. 1. "FID,Frame ID" line.word 0x186 "MBIDXR48,Message Buffer Index Registers" hexmask.word 0x186 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x188 "MBCCSR49,Message Buffer Configuratio49. Control and Status Register 49" bitfld.word 0x188 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x188 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x188 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x188 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x188 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x188 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x188 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x188 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x188 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x188 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x18A "MBCCFR49,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x18A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x18A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x18A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x18A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x18A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x18A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x18C "MBFIDR49,Message Buffer Frame ID Registers" hexmask.word 0x18C 0.--10. 1. "FID,Frame ID" line.word 0x18E "MBIDXR49,Message Buffer Index Registers" hexmask.word 0x18E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x190 "MBCCSR50,Message Buffer Configuratio50. Control and Status Register 50" bitfld.word 0x190 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x190 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x190 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x190 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x190 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x190 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x190 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x190 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x190 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x190 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x192 "MBCCFR50,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x192 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x192 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x192 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x192 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x192 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x192 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x194 "MBFIDR50,Message Buffer Frame ID Registers" hexmask.word 0x194 0.--10. 1. "FID,Frame ID" line.word 0x196 "MBIDXR50,Message Buffer Index Registers" hexmask.word 0x196 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x198 "MBCCSR51,Message Buffer Configuratio51. Control and Status Register 51" bitfld.word 0x198 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x198 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x198 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x198 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x198 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x198 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x198 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x198 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x198 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x198 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x19A "MBCCFR51,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x19A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x19A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x19A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x19A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x19A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x19A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x19C "MBFIDR51,Message Buffer Frame ID Registers" hexmask.word 0x19C 0.--10. 1. "FID,Frame ID" line.word 0x19E "MBIDXR51,Message Buffer Index Registers" hexmask.word 0x19E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1A0 "MBCCSR52,Message Buffer Configuratio52. Control and Status Register 52" bitfld.word 0x1A0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1A0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1A0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1A0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1A0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1A0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1A0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1A0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1A0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1A0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1A2 "MBCCFR52,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1A2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1A2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1A2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1A2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1A2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1A2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1A4 "MBFIDR52,Message Buffer Frame ID Registers" hexmask.word 0x1A4 0.--10. 1. "FID,Frame ID" line.word 0x1A6 "MBIDXR52,Message Buffer Index Registers" hexmask.word 0x1A6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1A8 "MBCCSR53,Message Buffer Configuratio53. Control and Status Register 53" bitfld.word 0x1A8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1A8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1A8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1A8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1A8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1A8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1A8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1A8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1A8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1A8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1AA "MBCCFR53,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1AA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1AA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1AA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1AA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1AA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1AA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1AC "MBFIDR53,Message Buffer Frame ID Registers" hexmask.word 0x1AC 0.--10. 1. "FID,Frame ID" line.word 0x1AE "MBIDXR53,Message Buffer Index Registers" hexmask.word 0x1AE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1B0 "MBCCSR54,Message Buffer Configuratio54. Control and Status Register 54" bitfld.word 0x1B0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1B0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1B0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1B0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1B0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1B0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1B0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1B0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1B0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1B0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1B2 "MBCCFR54,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1B2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1B2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1B2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1B2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1B2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1B2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1B4 "MBFIDR54,Message Buffer Frame ID Registers" hexmask.word 0x1B4 0.--10. 1. "FID,Frame ID" line.word 0x1B6 "MBIDXR54,Message Buffer Index Registers" hexmask.word 0x1B6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1B8 "MBCCSR55,Message Buffer Configuratio55. Control and Status Register 55" bitfld.word 0x1B8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1B8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1B8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1B8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1B8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1B8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1B8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1B8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1B8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1B8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1BA "MBCCFR55,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1BA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1BA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1BA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1BA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1BA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1BA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1BC "MBFIDR55,Message Buffer Frame ID Registers" hexmask.word 0x1BC 0.--10. 1. "FID,Frame ID" line.word 0x1BE "MBIDXR55,Message Buffer Index Registers" hexmask.word 0x1BE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1C0 "MBCCSR56,Message Buffer Configuratio56. Control and Status Register 56" bitfld.word 0x1C0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1C0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1C0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1C0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1C0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1C0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1C0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1C0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1C0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1C0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1C2 "MBCCFR56,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1C2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1C2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1C2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1C2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1C2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1C2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1C4 "MBFIDR56,Message Buffer Frame ID Registers" hexmask.word 0x1C4 0.--10. 1. "FID,Frame ID" line.word 0x1C6 "MBIDXR56,Message Buffer Index Registers" hexmask.word 0x1C6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1C8 "MBCCSR57,Message Buffer Configuratio57. Control and Status Register 57" bitfld.word 0x1C8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1C8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1C8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1C8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1C8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1C8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1C8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1C8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1C8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1C8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1CA "MBCCFR57,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1CA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1CA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1CA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1CA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1CA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1CA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1CC "MBFIDR57,Message Buffer Frame ID Registers" hexmask.word 0x1CC 0.--10. 1. "FID,Frame ID" line.word 0x1CE "MBIDXR57,Message Buffer Index Registers" hexmask.word 0x1CE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1D0 "MBCCSR58,Message Buffer Configuratio58. Control and Status Register 58" bitfld.word 0x1D0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1D0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1D0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1D0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1D0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1D0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1D0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1D0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1D0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1D0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1D2 "MBCCFR58,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1D2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1D2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1D2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1D2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1D2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1D2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1D4 "MBFIDR58,Message Buffer Frame ID Registers" hexmask.word 0x1D4 0.--10. 1. "FID,Frame ID" line.word 0x1D6 "MBIDXR58,Message Buffer Index Registers" hexmask.word 0x1D6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1D8 "MBCCSR59,Message Buffer Configuratio59. Control and Status Register 59" bitfld.word 0x1D8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1D8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1D8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1D8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1D8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1D8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1D8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1D8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1D8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1D8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1DA "MBCCFR59,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1DA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1DA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1DA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1DA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1DA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1DA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1DC "MBFIDR59,Message Buffer Frame ID Registers" hexmask.word 0x1DC 0.--10. 1. "FID,Frame ID" line.word 0x1DE "MBIDXR59,Message Buffer Index Registers" hexmask.word 0x1DE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1E0 "MBCCSR60,Message Buffer Configuratio60. Control and Status Register 60" bitfld.word 0x1E0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1E0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1E0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1E0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1E0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1E0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1E0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1E0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1E0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1E0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1E2 "MBCCFR60,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1E2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1E2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1E2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1E2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1E2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1E2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1E4 "MBFIDR60,Message Buffer Frame ID Registers" hexmask.word 0x1E4 0.--10. 1. "FID,Frame ID" line.word 0x1E6 "MBIDXR60,Message Buffer Index Registers" hexmask.word 0x1E6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1E8 "MBCCSR61,Message Buffer Configuratio61. Control and Status Register 61" bitfld.word 0x1E8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1E8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1E8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1E8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1E8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1E8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1E8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1E8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1E8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1E8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1EA "MBCCFR61,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1EA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1EA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1EA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1EA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1EA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1EA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1EC "MBFIDR61,Message Buffer Frame ID Registers" hexmask.word 0x1EC 0.--10. 1. "FID,Frame ID" line.word 0x1EE "MBIDXR61,Message Buffer Index Registers" hexmask.word 0x1EE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1F0 "MBCCSR62,Message Buffer Configuratio62. Control and Status Register 62" bitfld.word 0x1F0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1F0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1F0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1F0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1F0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1F0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1F0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1F0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1F0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1F0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1F2 "MBCCFR62,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1F2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1F2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1F2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1F2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1F2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1F2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1F4 "MBFIDR62,Message Buffer Frame ID Registers" hexmask.word 0x1F4 0.--10. 1. "FID,Frame ID" line.word 0x1F6 "MBIDXR62,Message Buffer Index Registers" hexmask.word 0x1F6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1F8 "MBCCSR63,Message Buffer Configuratio63. Control and Status Register 63" bitfld.word 0x1F8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1F8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1F8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1F8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1F8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1F8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1F8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1F8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1F8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1F8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1FA "MBCCFR63,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1FA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1FA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1FA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1FA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1FA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1FA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1FC "MBFIDR63,Message Buffer Frame ID Registers" hexmask.word 0x1FC 0.--10. 1. "FID,Frame ID" line.word 0x1FE "MBIDXR63,Message Buffer Index Registers" hexmask.word 0x1FE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x200 "MBCCSR64,Message Buffer Configuratio64. Control and Status Register 64" bitfld.word 0x200 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x200 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x200 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x200 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x200 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x200 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x200 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x200 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x200 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x200 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x202 "MBCCFR64,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x202 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x202 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x202 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x202 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x202 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x202 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x204 "MBFIDR64,Message Buffer Frame ID Registers" hexmask.word 0x204 0.--10. 1. "FID,Frame ID" line.word 0x206 "MBIDXR64,Message Buffer Index Registers" hexmask.word 0x206 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x208 "MBCCSR65,Message Buffer Configuratio65. Control and Status Register 65" bitfld.word 0x208 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x208 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x208 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x208 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x208 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x208 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x208 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x208 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x208 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x208 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x20A "MBCCFR65,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x20A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x20A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x20A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x20A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x20A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x20A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x20C "MBFIDR65,Message Buffer Frame ID Registers" hexmask.word 0x20C 0.--10. 1. "FID,Frame ID" line.word 0x20E "MBIDXR65,Message Buffer Index Registers" hexmask.word 0x20E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x210 "MBCCSR66,Message Buffer Configuratio66. Control and Status Register 66" bitfld.word 0x210 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x210 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x210 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x210 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x210 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x210 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x210 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x210 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x210 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x210 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x212 "MBCCFR66,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x212 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x212 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x212 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x212 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x212 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x212 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x214 "MBFIDR66,Message Buffer Frame ID Registers" hexmask.word 0x214 0.--10. 1. "FID,Frame ID" line.word 0x216 "MBIDXR66,Message Buffer Index Registers" hexmask.word 0x216 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x218 "MBCCSR67,Message Buffer Configuratio67. Control and Status Register 67" bitfld.word 0x218 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x218 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x218 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x218 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x218 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x218 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x218 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x218 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x218 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x218 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x21A "MBCCFR67,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x21A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x21A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x21A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x21A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x21A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x21A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x21C "MBFIDR67,Message Buffer Frame ID Registers" hexmask.word 0x21C 0.--10. 1. "FID,Frame ID" line.word 0x21E "MBIDXR67,Message Buffer Index Registers" hexmask.word 0x21E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x220 "MBCCSR68,Message Buffer Configuratio68. Control and Status Register 68" bitfld.word 0x220 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x220 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x220 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x220 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x220 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x220 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x220 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x220 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x220 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x220 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x222 "MBCCFR68,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x222 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x222 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x222 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x222 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x222 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x222 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x224 "MBFIDR68,Message Buffer Frame ID Registers" hexmask.word 0x224 0.--10. 1. "FID,Frame ID" line.word 0x226 "MBIDXR68,Message Buffer Index Registers" hexmask.word 0x226 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x228 "MBCCSR69,Message Buffer Configuratio69. Control and Status Register 69" bitfld.word 0x228 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x228 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x228 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x228 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x228 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x228 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x228 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x228 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x228 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x228 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x22A "MBCCFR69,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x22A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x22A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x22A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x22A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x22A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x22A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x22C "MBFIDR69,Message Buffer Frame ID Registers" hexmask.word 0x22C 0.--10. 1. "FID,Frame ID" line.word 0x22E "MBIDXR69,Message Buffer Index Registers" hexmask.word 0x22E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x230 "MBCCSR70,Message Buffer Configuratio70. Control and Status Register 70" bitfld.word 0x230 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x230 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x230 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x230 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x230 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x230 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x230 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x230 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x230 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x230 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x232 "MBCCFR70,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x232 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x232 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x232 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x232 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x232 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x232 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x234 "MBFIDR70,Message Buffer Frame ID Registers" hexmask.word 0x234 0.--10. 1. "FID,Frame ID" line.word 0x236 "MBIDXR70,Message Buffer Index Registers" hexmask.word 0x236 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x238 "MBCCSR71,Message Buffer Configuratio71. Control and Status Register 71" bitfld.word 0x238 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x238 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x238 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x238 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x238 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x238 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x238 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x238 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x238 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x238 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x23A "MBCCFR71,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x23A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x23A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x23A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x23A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x23A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x23A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x23C "MBFIDR71,Message Buffer Frame ID Registers" hexmask.word 0x23C 0.--10. 1. "FID,Frame ID" line.word 0x23E "MBIDXR71,Message Buffer Index Registers" hexmask.word 0x23E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x240 "MBCCSR72,Message Buffer Configuratio72. Control and Status Register 72" bitfld.word 0x240 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x240 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x240 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x240 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x240 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x240 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x240 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x240 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x240 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x240 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x242 "MBCCFR72,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x242 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x242 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x242 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x242 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x242 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x242 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x244 "MBFIDR72,Message Buffer Frame ID Registers" hexmask.word 0x244 0.--10. 1. "FID,Frame ID" line.word 0x246 "MBIDXR72,Message Buffer Index Registers" hexmask.word 0x246 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x248 "MBCCSR73,Message Buffer Configuratio73. Control and Status Register 73" bitfld.word 0x248 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x248 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x248 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x248 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x248 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x248 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x248 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x248 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x248 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x248 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x24A "MBCCFR73,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x24A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x24A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x24A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x24A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x24A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x24A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x24C "MBFIDR73,Message Buffer Frame ID Registers" hexmask.word 0x24C 0.--10. 1. "FID,Frame ID" line.word 0x24E "MBIDXR73,Message Buffer Index Registers" hexmask.word 0x24E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x250 "MBCCSR74,Message Buffer Configuratio74. Control and Status Register 74" bitfld.word 0x250 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x250 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x250 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x250 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x250 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x250 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x250 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x250 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x250 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x250 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x252 "MBCCFR74,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x252 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x252 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x252 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x252 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x252 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x252 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x254 "MBFIDR74,Message Buffer Frame ID Registers" hexmask.word 0x254 0.--10. 1. "FID,Frame ID" line.word 0x256 "MBIDXR74,Message Buffer Index Registers" hexmask.word 0x256 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x258 "MBCCSR75,Message Buffer Configuratio75. Control and Status Register 75" bitfld.word 0x258 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x258 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x258 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x258 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x258 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x258 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x258 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x258 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x258 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x258 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x25A "MBCCFR75,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x25A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x25A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x25A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x25A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x25A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x25A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x25C "MBFIDR75,Message Buffer Frame ID Registers" hexmask.word 0x25C 0.--10. 1. "FID,Frame ID" line.word 0x25E "MBIDXR75,Message Buffer Index Registers" hexmask.word 0x25E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x260 "MBCCSR76,Message Buffer Configuratio76. Control and Status Register 76" bitfld.word 0x260 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x260 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x260 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x260 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x260 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x260 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x260 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x260 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x260 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x260 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x262 "MBCCFR76,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x262 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x262 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x262 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x262 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x262 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x262 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x264 "MBFIDR76,Message Buffer Frame ID Registers" hexmask.word 0x264 0.--10. 1. "FID,Frame ID" line.word 0x266 "MBIDXR76,Message Buffer Index Registers" hexmask.word 0x266 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x268 "MBCCSR77,Message Buffer Configuratio77. Control and Status Register 77" bitfld.word 0x268 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x268 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x268 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x268 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x268 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x268 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x268 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x268 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x268 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x268 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x26A "MBCCFR77,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x26A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x26A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x26A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x26A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x26A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x26A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x26C "MBFIDR77,Message Buffer Frame ID Registers" hexmask.word 0x26C 0.--10. 1. "FID,Frame ID" line.word 0x26E "MBIDXR77,Message Buffer Index Registers" hexmask.word 0x26E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x270 "MBCCSR78,Message Buffer Configuratio78. Control and Status Register 78" bitfld.word 0x270 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x270 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x270 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x270 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x270 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x270 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x270 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x270 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x270 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x270 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x272 "MBCCFR78,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x272 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x272 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x272 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x272 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x272 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x272 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x274 "MBFIDR78,Message Buffer Frame ID Registers" hexmask.word 0x274 0.--10. 1. "FID,Frame ID" line.word 0x276 "MBIDXR78,Message Buffer Index Registers" hexmask.word 0x276 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x278 "MBCCSR79,Message Buffer Configuratio79. Control and Status Register 79" bitfld.word 0x278 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x278 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x278 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x278 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x278 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x278 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x278 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x278 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x278 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x278 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x27A "MBCCFR79,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x27A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x27A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x27A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x27A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x27A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x27A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x27C "MBFIDR79,Message Buffer Frame ID Registers" hexmask.word 0x27C 0.--10. 1. "FID,Frame ID" line.word 0x27E "MBIDXR79,Message Buffer Index Registers" hexmask.word 0x27E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x280 "MBCCSR80,Message Buffer Configuratio80. Control and Status Register 80" bitfld.word 0x280 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x280 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x280 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x280 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x280 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x280 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x280 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x280 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x280 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x280 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x282 "MBCCFR80,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x282 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x282 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x282 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x282 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x282 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x282 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x284 "MBFIDR80,Message Buffer Frame ID Registers" hexmask.word 0x284 0.--10. 1. "FID,Frame ID" line.word 0x286 "MBIDXR80,Message Buffer Index Registers" hexmask.word 0x286 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x288 "MBCCSR81,Message Buffer Configuratio81. Control and Status Register 81" bitfld.word 0x288 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x288 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x288 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x288 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x288 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x288 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x288 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x288 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x288 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x288 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x28A "MBCCFR81,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x28A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x28A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x28A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x28A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x28A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x28A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x28C "MBFIDR81,Message Buffer Frame ID Registers" hexmask.word 0x28C 0.--10. 1. "FID,Frame ID" line.word 0x28E "MBIDXR81,Message Buffer Index Registers" hexmask.word 0x28E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x290 "MBCCSR82,Message Buffer Configuratio82. Control and Status Register 82" bitfld.word 0x290 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x290 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x290 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x290 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x290 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x290 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x290 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x290 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x290 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x290 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x292 "MBCCFR82,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x292 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x292 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x292 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x292 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x292 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x292 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x294 "MBFIDR82,Message Buffer Frame ID Registers" hexmask.word 0x294 0.--10. 1. "FID,Frame ID" line.word 0x296 "MBIDXR82,Message Buffer Index Registers" hexmask.word 0x296 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x298 "MBCCSR83,Message Buffer Configuratio83. Control and Status Register 83" bitfld.word 0x298 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x298 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x298 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x298 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x298 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x298 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x298 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x298 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x298 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x298 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x29A "MBCCFR83,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x29A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x29A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x29A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x29A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x29A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x29A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x29C "MBFIDR83,Message Buffer Frame ID Registers" hexmask.word 0x29C 0.--10. 1. "FID,Frame ID" line.word 0x29E "MBIDXR83,Message Buffer Index Registers" hexmask.word 0x29E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2A0 "MBCCSR84,Message Buffer Configuratio84. Control and Status Register 84" bitfld.word 0x2A0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2A0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2A0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2A0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2A0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2A0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2A0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2A0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2A0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2A0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2A2 "MBCCFR84,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2A2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2A2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2A2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2A2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2A2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2A2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2A4 "MBFIDR84,Message Buffer Frame ID Registers" hexmask.word 0x2A4 0.--10. 1. "FID,Frame ID" line.word 0x2A6 "MBIDXR84,Message Buffer Index Registers" hexmask.word 0x2A6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2A8 "MBCCSR85,Message Buffer Configuratio85. Control and Status Register 85" bitfld.word 0x2A8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2A8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2A8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2A8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2A8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2A8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2A8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2A8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2A8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2A8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2AA "MBCCFR85,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2AA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2AA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2AA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2AA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2AA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2AA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2AC "MBFIDR85,Message Buffer Frame ID Registers" hexmask.word 0x2AC 0.--10. 1. "FID,Frame ID" line.word 0x2AE "MBIDXR85,Message Buffer Index Registers" hexmask.word 0x2AE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2B0 "MBCCSR86,Message Buffer Configuratio86. Control and Status Register 86" bitfld.word 0x2B0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2B0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2B0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2B0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2B0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2B0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2B0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2B0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2B0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2B0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2B2 "MBCCFR86,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2B2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2B2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2B2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2B2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2B2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2B2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2B4 "MBFIDR86,Message Buffer Frame ID Registers" hexmask.word 0x2B4 0.--10. 1. "FID,Frame ID" line.word 0x2B6 "MBIDXR86,Message Buffer Index Registers" hexmask.word 0x2B6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2B8 "MBCCSR87,Message Buffer Configuratio87. Control and Status Register 87" bitfld.word 0x2B8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2B8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2B8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2B8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2B8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2B8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2B8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2B8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2B8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2B8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2BA "MBCCFR87,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2BA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2BA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2BA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2BA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2BA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2BA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2BC "MBFIDR87,Message Buffer Frame ID Registers" hexmask.word 0x2BC 0.--10. 1. "FID,Frame ID" line.word 0x2BE "MBIDXR87,Message Buffer Index Registers" hexmask.word 0x2BE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2C0 "MBCCSR88,Message Buffer Configuratio88. Control and Status Register 88" bitfld.word 0x2C0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2C0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2C0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2C0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2C0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2C0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2C0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2C0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2C0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2C0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2C2 "MBCCFR88,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2C2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2C2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2C2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2C2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2C2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2C2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2C4 "MBFIDR88,Message Buffer Frame ID Registers" hexmask.word 0x2C4 0.--10. 1. "FID,Frame ID" line.word 0x2C6 "MBIDXR88,Message Buffer Index Registers" hexmask.word 0x2C6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2C8 "MBCCSR89,Message Buffer Configuratio89. Control and Status Register 89" bitfld.word 0x2C8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2C8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2C8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2C8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2C8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2C8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2C8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2C8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2C8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2C8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2CA "MBCCFR89,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2CA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2CA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2CA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2CA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2CA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2CA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2CC "MBFIDR89,Message Buffer Frame ID Registers" hexmask.word 0x2CC 0.--10. 1. "FID,Frame ID" line.word 0x2CE "MBIDXR89,Message Buffer Index Registers" hexmask.word 0x2CE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2D0 "MBCCSR90,Message Buffer Configuratio90. Control and Status Register 90" bitfld.word 0x2D0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2D0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2D0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2D0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2D0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2D0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2D0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2D0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2D0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2D0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2D2 "MBCCFR90,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2D2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2D2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2D2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2D2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2D2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2D2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2D4 "MBFIDR90,Message Buffer Frame ID Registers" hexmask.word 0x2D4 0.--10. 1. "FID,Frame ID" line.word 0x2D6 "MBIDXR90,Message Buffer Index Registers" hexmask.word 0x2D6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2D8 "MBCCSR91,Message Buffer Configuratio91. Control and Status Register 91" bitfld.word 0x2D8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2D8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2D8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2D8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2D8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2D8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2D8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2D8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2D8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2D8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2DA "MBCCFR91,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2DA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2DA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2DA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2DA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2DA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2DA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2DC "MBFIDR91,Message Buffer Frame ID Registers" hexmask.word 0x2DC 0.--10. 1. "FID,Frame ID" line.word 0x2DE "MBIDXR91,Message Buffer Index Registers" hexmask.word 0x2DE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2E0 "MBCCSR92,Message Buffer Configuratio92. Control and Status Register 92" bitfld.word 0x2E0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2E0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2E0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2E0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2E0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2E0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2E0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2E0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2E0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2E0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2E2 "MBCCFR92,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2E2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2E2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2E2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2E2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2E2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2E2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2E4 "MBFIDR92,Message Buffer Frame ID Registers" hexmask.word 0x2E4 0.--10. 1. "FID,Frame ID" line.word 0x2E6 "MBIDXR92,Message Buffer Index Registers" hexmask.word 0x2E6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2E8 "MBCCSR93,Message Buffer Configuratio93. Control and Status Register 93" bitfld.word 0x2E8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2E8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2E8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2E8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2E8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2E8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2E8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2E8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2E8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2E8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2EA "MBCCFR93,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2EA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2EA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2EA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2EA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2EA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2EA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2EC "MBFIDR93,Message Buffer Frame ID Registers" hexmask.word 0x2EC 0.--10. 1. "FID,Frame ID" line.word 0x2EE "MBIDXR93,Message Buffer Index Registers" hexmask.word 0x2EE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2F0 "MBCCSR94,Message Buffer Configuratio94. Control and Status Register 94" bitfld.word 0x2F0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2F0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2F0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2F0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2F0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2F0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2F0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2F0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2F0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2F0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2F2 "MBCCFR94,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2F2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2F2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2F2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2F2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2F2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2F2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2F4 "MBFIDR94,Message Buffer Frame ID Registers" hexmask.word 0x2F4 0.--10. 1. "FID,Frame ID" line.word 0x2F6 "MBIDXR94,Message Buffer Index Registers" hexmask.word 0x2F6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2F8 "MBCCSR95,Message Buffer Configuratio95. Control and Status Register 95" bitfld.word 0x2F8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2F8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2F8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2F8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2F8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2F8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2F8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2F8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2F8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2F8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2FA "MBCCFR95,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2FA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2FA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2FA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2FA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2FA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2FA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2FC "MBFIDR95,Message Buffer Frame ID Registers" hexmask.word 0x2FC 0.--10. 1. "FID,Frame ID" line.word 0x2FE "MBIDXR95,Message Buffer Index Registers" hexmask.word 0x2FE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x300 "MBCCSR96,Message Buffer Configuratio96. Control and Status Register 96" bitfld.word 0x300 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x300 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x300 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x300 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x300 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x300 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x300 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x300 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x300 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x300 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x302 "MBCCFR96,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x302 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x302 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x302 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x302 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x302 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x302 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x304 "MBFIDR96,Message Buffer Frame ID Registers" hexmask.word 0x304 0.--10. 1. "FID,Frame ID" line.word 0x306 "MBIDXR96,Message Buffer Index Registers" hexmask.word 0x306 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x308 "MBCCSR97,Message Buffer Configuratio97. Control and Status Register 97" bitfld.word 0x308 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x308 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x308 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x308 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x308 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x308 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x308 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x308 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x308 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x308 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x30A "MBCCFR97,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x30A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x30A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x30A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x30A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x30A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x30A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x30C "MBFIDR97,Message Buffer Frame ID Registers" hexmask.word 0x30C 0.--10. 1. "FID,Frame ID" line.word 0x30E "MBIDXR97,Message Buffer Index Registers" hexmask.word 0x30E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x310 "MBCCSR98,Message Buffer Configuratio98. Control and Status Register 98" bitfld.word 0x310 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x310 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x310 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x310 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x310 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x310 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x310 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x310 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x310 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x310 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x312 "MBCCFR98,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x312 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x312 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x312 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x312 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x312 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x312 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x314 "MBFIDR98,Message Buffer Frame ID Registers" hexmask.word 0x314 0.--10. 1. "FID,Frame ID" line.word 0x316 "MBIDXR98,Message Buffer Index Registers" hexmask.word 0x316 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x318 "MBCCSR99,Message Buffer Configuratio99. Control and Status Register 99" bitfld.word 0x318 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x318 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x318 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x318 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x318 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x318 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x318 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x318 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x318 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x318 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x31A "MBCCFR99,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x31A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x31A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x31A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x31A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x31A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x31A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x31C "MBFIDR99,Message Buffer Frame ID Registers" hexmask.word 0x31C 0.--10. 1. "FID,Frame ID" line.word 0x31E "MBIDXR99,Message Buffer Index Registers" hexmask.word 0x31E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x320 "MBCCSR100,Message Buffer Configuratio100. Control and Status Register 100" bitfld.word 0x320 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x320 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x320 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x320 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x320 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x320 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x320 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x320 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x320 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x320 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x322 "MBCCFR100,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x322 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x322 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x322 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x322 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x322 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x322 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x324 "MBFIDR100,Message Buffer Frame ID Registers" hexmask.word 0x324 0.--10. 1. "FID,Frame ID" line.word 0x326 "MBIDXR100,Message Buffer Index Registers" hexmask.word 0x326 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x328 "MBCCSR101,Message Buffer Configuratio101. Control and Status Register 101" bitfld.word 0x328 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x328 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x328 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x328 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x328 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x328 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x328 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x328 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x328 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x328 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x32A "MBCCFR101,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x32A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x32A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x32A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x32A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x32A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x32A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x32C "MBFIDR101,Message Buffer Frame ID Registers" hexmask.word 0x32C 0.--10. 1. "FID,Frame ID" line.word 0x32E "MBIDXR101,Message Buffer Index Registers" hexmask.word 0x32E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x330 "MBCCSR102,Message Buffer Configuratio102. Control and Status Register 102" bitfld.word 0x330 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x330 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x330 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x330 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x330 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x330 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x330 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x330 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x330 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x330 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x332 "MBCCFR102,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x332 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x332 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x332 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x332 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x332 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x332 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x334 "MBFIDR102,Message Buffer Frame ID Registers" hexmask.word 0x334 0.--10. 1. "FID,Frame ID" line.word 0x336 "MBIDXR102,Message Buffer Index Registers" hexmask.word 0x336 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x338 "MBCCSR103,Message Buffer Configuratio103. Control and Status Register 103" bitfld.word 0x338 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x338 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x338 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x338 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x338 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x338 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x338 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x338 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x338 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x338 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x33A "MBCCFR103,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x33A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x33A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x33A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x33A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x33A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x33A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x33C "MBFIDR103,Message Buffer Frame ID Registers" hexmask.word 0x33C 0.--10. 1. "FID,Frame ID" line.word 0x33E "MBIDXR103,Message Buffer Index Registers" hexmask.word 0x33E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x340 "MBCCSR104,Message Buffer Configuratio104. Control and Status Register 104" bitfld.word 0x340 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x340 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x340 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x340 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x340 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x340 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x340 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x340 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x340 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x340 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x342 "MBCCFR104,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x342 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x342 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x342 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x342 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x342 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x342 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x344 "MBFIDR104,Message Buffer Frame ID Registers" hexmask.word 0x344 0.--10. 1. "FID,Frame ID" line.word 0x346 "MBIDXR104,Message Buffer Index Registers" hexmask.word 0x346 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x348 "MBCCSR105,Message Buffer Configuratio105. Control and Status Register 105" bitfld.word 0x348 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x348 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x348 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x348 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x348 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x348 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x348 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x348 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x348 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x348 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x34A "MBCCFR105,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x34A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x34A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x34A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x34A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x34A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x34A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x34C "MBFIDR105,Message Buffer Frame ID Registers" hexmask.word 0x34C 0.--10. 1. "FID,Frame ID" line.word 0x34E "MBIDXR105,Message Buffer Index Registers" hexmask.word 0x34E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x350 "MBCCSR106,Message Buffer Configuratio106. Control and Status Register 106" bitfld.word 0x350 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x350 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x350 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x350 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x350 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x350 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x350 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x350 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x350 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x350 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x352 "MBCCFR106,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x352 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x352 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x352 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x352 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x352 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x352 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x354 "MBFIDR106,Message Buffer Frame ID Registers" hexmask.word 0x354 0.--10. 1. "FID,Frame ID" line.word 0x356 "MBIDXR106,Message Buffer Index Registers" hexmask.word 0x356 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x358 "MBCCSR107,Message Buffer Configuratio107. Control and Status Register 107" bitfld.word 0x358 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x358 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x358 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x358 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x358 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x358 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x358 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x358 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x358 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x358 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x35A "MBCCFR107,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x35A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x35A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x35A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x35A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x35A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x35A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x35C "MBFIDR107,Message Buffer Frame ID Registers" hexmask.word 0x35C 0.--10. 1. "FID,Frame ID" line.word 0x35E "MBIDXR107,Message Buffer Index Registers" hexmask.word 0x35E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x360 "MBCCSR108,Message Buffer Configuratio108. Control and Status Register 108" bitfld.word 0x360 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x360 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x360 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x360 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x360 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x360 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x360 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x360 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x360 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x360 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x362 "MBCCFR108,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x362 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x362 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x362 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x362 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x362 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x362 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x364 "MBFIDR108,Message Buffer Frame ID Registers" hexmask.word 0x364 0.--10. 1. "FID,Frame ID" line.word 0x366 "MBIDXR108,Message Buffer Index Registers" hexmask.word 0x366 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x368 "MBCCSR109,Message Buffer Configuratio109. Control and Status Register 109" bitfld.word 0x368 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x368 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x368 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x368 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x368 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x368 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x368 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x368 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x368 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x368 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x36A "MBCCFR109,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x36A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x36A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x36A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x36A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x36A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x36A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x36C "MBFIDR109,Message Buffer Frame ID Registers" hexmask.word 0x36C 0.--10. 1. "FID,Frame ID" line.word 0x36E "MBIDXR109,Message Buffer Index Registers" hexmask.word 0x36E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x370 "MBCCSR110,Message Buffer Configuratio110. Control and Status Register 110" bitfld.word 0x370 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x370 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x370 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x370 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x370 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x370 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x370 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x370 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x370 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x370 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x372 "MBCCFR110,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x372 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x372 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x372 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x372 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x372 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x372 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x374 "MBFIDR110,Message Buffer Frame ID Registers" hexmask.word 0x374 0.--10. 1. "FID,Frame ID" line.word 0x376 "MBIDXR110,Message Buffer Index Registers" hexmask.word 0x376 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x378 "MBCCSR111,Message Buffer Configuratio111. Control and Status Register 111" bitfld.word 0x378 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x378 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x378 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x378 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x378 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x378 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x378 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x378 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x378 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x378 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x37A "MBCCFR111,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x37A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x37A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x37A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x37A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x37A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x37A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x37C "MBFIDR111,Message Buffer Frame ID Registers" hexmask.word 0x37C 0.--10. 1. "FID,Frame ID" line.word 0x37E "MBIDXR111,Message Buffer Index Registers" hexmask.word 0x37E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x380 "MBCCSR112,Message Buffer Configuratio112. Control and Status Register 112" bitfld.word 0x380 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x380 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x380 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x380 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x380 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x380 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x380 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x380 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x380 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x380 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x382 "MBCCFR112,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x382 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x382 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x382 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x382 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x382 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x382 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x384 "MBFIDR112,Message Buffer Frame ID Registers" hexmask.word 0x384 0.--10. 1. "FID,Frame ID" line.word 0x386 "MBIDXR112,Message Buffer Index Registers" hexmask.word 0x386 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x388 "MBCCSR113,Message Buffer Configuratio113. Control and Status Register 113" bitfld.word 0x388 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x388 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x388 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x388 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x388 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x388 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x388 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x388 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x388 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x388 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x38A "MBCCFR113,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x38A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x38A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x38A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x38A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x38A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x38A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x38C "MBFIDR113,Message Buffer Frame ID Registers" hexmask.word 0x38C 0.--10. 1. "FID,Frame ID" line.word 0x38E "MBIDXR113,Message Buffer Index Registers" hexmask.word 0x38E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x390 "MBCCSR114,Message Buffer Configuratio114. Control and Status Register 114" bitfld.word 0x390 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x390 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x390 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x390 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x390 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x390 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x390 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x390 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x390 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x390 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x392 "MBCCFR114,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x392 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x392 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x392 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x392 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x392 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x392 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x394 "MBFIDR114,Message Buffer Frame ID Registers" hexmask.word 0x394 0.--10. 1. "FID,Frame ID" line.word 0x396 "MBIDXR114,Message Buffer Index Registers" hexmask.word 0x396 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x398 "MBCCSR115,Message Buffer Configuratio115. Control and Status Register 115" bitfld.word 0x398 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x398 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x398 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x398 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x398 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x398 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x398 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x398 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x398 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x398 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x39A "MBCCFR115,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x39A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x39A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x39A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x39A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x39A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x39A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x39C "MBFIDR115,Message Buffer Frame ID Registers" hexmask.word 0x39C 0.--10. 1. "FID,Frame ID" line.word 0x39E "MBIDXR115,Message Buffer Index Registers" hexmask.word 0x39E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3A0 "MBCCSR116,Message Buffer Configuratio116. Control and Status Register 116" bitfld.word 0x3A0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3A0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3A0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3A0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3A0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3A0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3A0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3A0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3A0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3A0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3A2 "MBCCFR116,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3A2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3A2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3A2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3A2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3A2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3A2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3A4 "MBFIDR116,Message Buffer Frame ID Registers" hexmask.word 0x3A4 0.--10. 1. "FID,Frame ID" line.word 0x3A6 "MBIDXR116,Message Buffer Index Registers" hexmask.word 0x3A6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3A8 "MBCCSR117,Message Buffer Configuratio117. Control and Status Register 117" bitfld.word 0x3A8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3A8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3A8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3A8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3A8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3A8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3A8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3A8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3A8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3A8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3AA "MBCCFR117,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3AA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3AA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3AA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3AA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3AA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3AA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3AC "MBFIDR117,Message Buffer Frame ID Registers" hexmask.word 0x3AC 0.--10. 1. "FID,Frame ID" line.word 0x3AE "MBIDXR117,Message Buffer Index Registers" hexmask.word 0x3AE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3B0 "MBCCSR118,Message Buffer Configuratio118. Control and Status Register 118" bitfld.word 0x3B0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3B0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3B0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3B0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3B0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3B0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3B0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3B0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3B0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3B0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3B2 "MBCCFR118,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3B2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3B2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3B2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3B2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3B2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3B2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3B4 "MBFIDR118,Message Buffer Frame ID Registers" hexmask.word 0x3B4 0.--10. 1. "FID,Frame ID" line.word 0x3B6 "MBIDXR118,Message Buffer Index Registers" hexmask.word 0x3B6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3B8 "MBCCSR119,Message Buffer Configuratio119. Control and Status Register 119" bitfld.word 0x3B8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3B8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3B8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3B8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3B8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3B8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3B8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3B8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3B8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3B8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3BA "MBCCFR119,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3BA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3BA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3BA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3BA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3BA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3BA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3BC "MBFIDR119,Message Buffer Frame ID Registers" hexmask.word 0x3BC 0.--10. 1. "FID,Frame ID" line.word 0x3BE "MBIDXR119,Message Buffer Index Registers" hexmask.word 0x3BE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3C0 "MBCCSR120,Message Buffer Configuratio120. Control and Status Register 120" bitfld.word 0x3C0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3C0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3C0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3C0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3C0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3C0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3C0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3C0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3C0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3C0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3C2 "MBCCFR120,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3C2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3C2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3C2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3C2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3C2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3C2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3C4 "MBFIDR120,Message Buffer Frame ID Registers" hexmask.word 0x3C4 0.--10. 1. "FID,Frame ID" line.word 0x3C6 "MBIDXR120,Message Buffer Index Registers" hexmask.word 0x3C6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3C8 "MBCCSR121,Message Buffer Configuratio121. Control and Status Register 121" bitfld.word 0x3C8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3C8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3C8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3C8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3C8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3C8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3C8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3C8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3C8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3C8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3CA "MBCCFR121,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3CA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3CA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3CA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3CA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3CA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3CA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3CC "MBFIDR121,Message Buffer Frame ID Registers" hexmask.word 0x3CC 0.--10. 1. "FID,Frame ID" line.word 0x3CE "MBIDXR121,Message Buffer Index Registers" hexmask.word 0x3CE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3D0 "MBCCSR122,Message Buffer Configuratio122. Control and Status Register 122" bitfld.word 0x3D0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3D0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3D0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3D0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3D0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3D0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3D0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3D0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3D0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3D0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3D2 "MBCCFR122,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3D2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3D2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3D2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3D2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3D2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3D2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3D4 "MBFIDR122,Message Buffer Frame ID Registers" hexmask.word 0x3D4 0.--10. 1. "FID,Frame ID" line.word 0x3D6 "MBIDXR122,Message Buffer Index Registers" hexmask.word 0x3D6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3D8 "MBCCSR123,Message Buffer Configuratio123. Control and Status Register 123" bitfld.word 0x3D8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3D8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3D8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3D8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3D8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3D8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3D8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3D8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3D8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3D8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3DA "MBCCFR123,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3DA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3DA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3DA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3DA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3DA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3DA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3DC "MBFIDR123,Message Buffer Frame ID Registers" hexmask.word 0x3DC 0.--10. 1. "FID,Frame ID" line.word 0x3DE "MBIDXR123,Message Buffer Index Registers" hexmask.word 0x3DE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3E0 "MBCCSR124,Message Buffer Configuratio124. Control and Status Register 124" bitfld.word 0x3E0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3E0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3E0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3E0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3E0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3E0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3E0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3E0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3E0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3E0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3E2 "MBCCFR124,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3E2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3E2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3E2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3E2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3E2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3E2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3E4 "MBFIDR124,Message Buffer Frame ID Registers" hexmask.word 0x3E4 0.--10. 1. "FID,Frame ID" line.word 0x3E6 "MBIDXR124,Message Buffer Index Registers" hexmask.word 0x3E6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3E8 "MBCCSR125,Message Buffer Configuratio125. Control and Status Register 125" bitfld.word 0x3E8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3E8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3E8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3E8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3E8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3E8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3E8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3E8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3E8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3E8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3EA "MBCCFR125,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3EA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3EA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3EA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3EA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3EA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3EA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3EC "MBFIDR125,Message Buffer Frame ID Registers" hexmask.word 0x3EC 0.--10. 1. "FID,Frame ID" line.word 0x3EE "MBIDXR125,Message Buffer Index Registers" hexmask.word 0x3EE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3F0 "MBCCSR126,Message Buffer Configuratio126. Control and Status Register 126" bitfld.word 0x3F0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3F0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3F0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3F0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3F0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3F0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3F0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3F0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3F0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3F0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3F2 "MBCCFR126,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3F2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3F2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3F2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3F2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3F2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3F2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3F4 "MBFIDR126,Message Buffer Frame ID Registers" hexmask.word 0x3F4 0.--10. 1. "FID,Frame ID" line.word 0x3F6 "MBIDXR126,Message Buffer Index Registers" hexmask.word 0x3F6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3F8 "MBCCSR127,Message Buffer Configuratio127. Control and Status Register 127" bitfld.word 0x3F8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3F8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3F8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3F8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3F8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3F8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3F8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3F8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3F8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3F8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3FA "MBCCFR127,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3FA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3FA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3FA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3FA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3FA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3FA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3FC "MBFIDR127,Message Buffer Frame ID Registers" hexmask.word 0x3FC 0.--10. 1. "FID,Frame ID" line.word 0x3FE "MBIDXR127,Message Buffer Index Registers" hexmask.word 0x3FE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x400 "MBCCSR128,Message Buffer Configuratio128. Control and Status Register 128" bitfld.word 0x400 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x400 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x400 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x400 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x400 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x400 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x400 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x400 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x400 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x400 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x402 "MBCCFR128,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x402 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x402 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x402 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x402 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x402 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x402 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x404 "MBFIDR128,Message Buffer Frame ID Registers" hexmask.word 0x404 0.--10. 1. "FID,Frame ID" line.word 0x406 "MBIDXR128,Message Buffer Index Registers" hexmask.word 0x406 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x408 "MBCCSR129,Message Buffer Configuratio129. Control and Status Register 129" bitfld.word 0x408 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x408 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x408 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x408 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x408 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x408 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x408 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x408 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x408 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x408 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x40A "MBCCFR129,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x40A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x40A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x40A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x40A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x40A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x40A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x40C "MBFIDR129,Message Buffer Frame ID Registers" hexmask.word 0x40C 0.--10. 1. "FID,Frame ID" line.word 0x40E "MBIDXR129,Message Buffer Index Registers" hexmask.word 0x40E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x410 "MBCCSR130,Message Buffer Configuratio130. Control and Status Register 130" bitfld.word 0x410 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x410 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x410 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x410 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x410 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x410 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x410 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x410 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x410 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x410 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x412 "MBCCFR130,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x412 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x412 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x412 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x412 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x412 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x412 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x414 "MBFIDR130,Message Buffer Frame ID Registers" hexmask.word 0x414 0.--10. 1. "FID,Frame ID" line.word 0x416 "MBIDXR130,Message Buffer Index Registers" hexmask.word 0x416 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x418 "MBCCSR131,Message Buffer Configuratio131. Control and Status Register 131" bitfld.word 0x418 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x418 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x418 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x418 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x418 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x418 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x418 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x418 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x418 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x418 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x41A "MBCCFR131,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x41A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x41A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x41A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x41A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x41A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x41A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x41C "MBFIDR131,Message Buffer Frame ID Registers" hexmask.word 0x41C 0.--10. 1. "FID,Frame ID" line.word 0x41E "MBIDXR131,Message Buffer Index Registers" hexmask.word 0x41E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x420 "MBCCSR132,Message Buffer Configuratio132. Control and Status Register 132" bitfld.word 0x420 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x420 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x420 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x420 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x420 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x420 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x420 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x420 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x420 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x420 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x422 "MBCCFR132,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x422 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x422 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x422 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x422 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x422 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x422 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x424 "MBFIDR132,Message Buffer Frame ID Registers" hexmask.word 0x424 0.--10. 1. "FID,Frame ID" line.word 0x426 "MBIDXR132,Message Buffer Index Registers" hexmask.word 0x426 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x428 "MBCCSR133,Message Buffer Configuratio133. Control and Status Register 133" bitfld.word 0x428 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x428 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x428 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x428 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x428 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x428 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x428 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x428 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x428 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x428 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x42A "MBCCFR133,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x42A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x42A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x42A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x42A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x42A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x42A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x42C "MBFIDR133,Message Buffer Frame ID Registers" hexmask.word 0x42C 0.--10. 1. "FID,Frame ID" line.word 0x42E "MBIDXR133,Message Buffer Index Registers" hexmask.word 0x42E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x430 "MBCCSR134,Message Buffer Configuratio134. Control and Status Register 134" bitfld.word 0x430 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x430 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x430 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x430 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x430 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x430 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x430 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x430 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x430 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x430 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x432 "MBCCFR134,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x432 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x432 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x432 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x432 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x432 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x432 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x434 "MBFIDR134,Message Buffer Frame ID Registers" hexmask.word 0x434 0.--10. 1. "FID,Frame ID" line.word 0x436 "MBIDXR134,Message Buffer Index Registers" hexmask.word 0x436 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x438 "MBCCSR135,Message Buffer Configuratio135. Control and Status Register 135" bitfld.word 0x438 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x438 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x438 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x438 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x438 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x438 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x438 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x438 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x438 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x438 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x43A "MBCCFR135,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x43A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x43A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x43A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x43A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x43A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x43A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x43C "MBFIDR135,Message Buffer Frame ID Registers" hexmask.word 0x43C 0.--10. 1. "FID,Frame ID" line.word 0x43E "MBIDXR135,Message Buffer Index Registers" hexmask.word 0x43E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x440 "MBCCSR136,Message Buffer Configuratio136. Control and Status Register 136" bitfld.word 0x440 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x440 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x440 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x440 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x440 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x440 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x440 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x440 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x440 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x440 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x442 "MBCCFR136,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x442 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x442 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x442 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x442 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x442 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x442 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x444 "MBFIDR136,Message Buffer Frame ID Registers" hexmask.word 0x444 0.--10. 1. "FID,Frame ID" line.word 0x446 "MBIDXR136,Message Buffer Index Registers" hexmask.word 0x446 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x448 "MBCCSR137,Message Buffer Configuratio137. Control and Status Register 137" bitfld.word 0x448 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x448 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x448 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x448 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x448 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x448 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x448 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x448 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x448 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x448 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x44A "MBCCFR137,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x44A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x44A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x44A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x44A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x44A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x44A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x44C "MBFIDR137,Message Buffer Frame ID Registers" hexmask.word 0x44C 0.--10. 1. "FID,Frame ID" line.word 0x44E "MBIDXR137,Message Buffer Index Registers" hexmask.word 0x44E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x450 "MBCCSR138,Message Buffer Configuratio138. Control and Status Register 138" bitfld.word 0x450 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x450 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x450 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x450 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x450 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x450 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x450 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x450 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x450 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x450 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x452 "MBCCFR138,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x452 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x452 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x452 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x452 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x452 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x452 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x454 "MBFIDR138,Message Buffer Frame ID Registers" hexmask.word 0x454 0.--10. 1. "FID,Frame ID" line.word 0x456 "MBIDXR138,Message Buffer Index Registers" hexmask.word 0x456 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x458 "MBCCSR139,Message Buffer Configuratio139. Control and Status Register 139" bitfld.word 0x458 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x458 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x458 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x458 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x458 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x458 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x458 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x458 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x458 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x458 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x45A "MBCCFR139,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x45A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x45A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x45A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x45A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x45A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x45A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x45C "MBFIDR139,Message Buffer Frame ID Registers" hexmask.word 0x45C 0.--10. 1. "FID,Frame ID" line.word 0x45E "MBIDXR139,Message Buffer Index Registers" hexmask.word 0x45E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x460 "MBCCSR140,Message Buffer Configuratio140. Control and Status Register 140" bitfld.word 0x460 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x460 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x460 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x460 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x460 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x460 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x460 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x460 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x460 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x460 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x462 "MBCCFR140,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x462 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x462 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x462 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x462 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x462 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x462 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x464 "MBFIDR140,Message Buffer Frame ID Registers" hexmask.word 0x464 0.--10. 1. "FID,Frame ID" line.word 0x466 "MBIDXR140,Message Buffer Index Registers" hexmask.word 0x466 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x468 "MBCCSR141,Message Buffer Configuratio141. Control and Status Register 141" bitfld.word 0x468 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x468 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x468 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x468 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x468 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x468 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x468 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x468 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x468 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x468 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x46A "MBCCFR141,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x46A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x46A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x46A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x46A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x46A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x46A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x46C "MBFIDR141,Message Buffer Frame ID Registers" hexmask.word 0x46C 0.--10. 1. "FID,Frame ID" line.word 0x46E "MBIDXR141,Message Buffer Index Registers" hexmask.word 0x46E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x470 "MBCCSR142,Message Buffer Configuratio142. Control and Status Register 142" bitfld.word 0x470 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x470 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x470 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x470 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x470 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x470 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x470 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x470 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x470 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x470 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x472 "MBCCFR142,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x472 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x472 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x472 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x472 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x472 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x472 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x474 "MBFIDR142,Message Buffer Frame ID Registers" hexmask.word 0x474 0.--10. 1. "FID,Frame ID" line.word 0x476 "MBIDXR142,Message Buffer Index Registers" hexmask.word 0x476 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x478 "MBCCSR143,Message Buffer Configuratio143. Control and Status Register 143" bitfld.word 0x478 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x478 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x478 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x478 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x478 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x478 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x478 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x478 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x478 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x478 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x47A "MBCCFR143,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x47A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x47A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x47A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x47A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x47A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x47A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x47C "MBFIDR143,Message Buffer Frame ID Registers" hexmask.word 0x47C 0.--10. 1. "FID,Frame ID" line.word 0x47E "MBIDXR143,Message Buffer Index Registers" hexmask.word 0x47E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x480 "MBCCSR144,Message Buffer Configuratio144. Control and Status Register 144" bitfld.word 0x480 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x480 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x480 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x480 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x480 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x480 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x480 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x480 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x480 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x480 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x482 "MBCCFR144,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x482 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x482 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x482 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x482 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x482 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x482 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x484 "MBFIDR144,Message Buffer Frame ID Registers" hexmask.word 0x484 0.--10. 1. "FID,Frame ID" line.word 0x486 "MBIDXR144,Message Buffer Index Registers" hexmask.word 0x486 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x488 "MBCCSR145,Message Buffer Configuratio145. Control and Status Register 145" bitfld.word 0x488 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x488 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x488 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x488 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x488 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x488 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x488 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x488 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x488 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x488 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x48A "MBCCFR145,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x48A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x48A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x48A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x48A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x48A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x48A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x48C "MBFIDR145,Message Buffer Frame ID Registers" hexmask.word 0x48C 0.--10. 1. "FID,Frame ID" line.word 0x48E "MBIDXR145,Message Buffer Index Registers" hexmask.word 0x48E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x490 "MBCCSR146,Message Buffer Configuratio146. Control and Status Register 146" bitfld.word 0x490 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x490 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x490 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x490 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x490 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x490 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x490 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x490 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x490 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x490 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x492 "MBCCFR146,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x492 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x492 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x492 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x492 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x492 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x492 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x494 "MBFIDR146,Message Buffer Frame ID Registers" hexmask.word 0x494 0.--10. 1. "FID,Frame ID" line.word 0x496 "MBIDXR146,Message Buffer Index Registers" hexmask.word 0x496 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x498 "MBCCSR147,Message Buffer Configuratio147. Control and Status Register 147" bitfld.word 0x498 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x498 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x498 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x498 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x498 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x498 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x498 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x498 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x498 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x498 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x49A "MBCCFR147,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x49A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x49A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x49A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x49A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x49A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x49A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x49C "MBFIDR147,Message Buffer Frame ID Registers" hexmask.word 0x49C 0.--10. 1. "FID,Frame ID" line.word 0x49E "MBIDXR147,Message Buffer Index Registers" hexmask.word 0x49E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4A0 "MBCCSR148,Message Buffer Configuratio148. Control and Status Register 148" bitfld.word 0x4A0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4A0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4A0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4A0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4A0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4A0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4A0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4A0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4A0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4A0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4A2 "MBCCFR148,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4A2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4A2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4A2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4A2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4A2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4A2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4A4 "MBFIDR148,Message Buffer Frame ID Registers" hexmask.word 0x4A4 0.--10. 1. "FID,Frame ID" line.word 0x4A6 "MBIDXR148,Message Buffer Index Registers" hexmask.word 0x4A6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4A8 "MBCCSR149,Message Buffer Configuratio149. Control and Status Register 149" bitfld.word 0x4A8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4A8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4A8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4A8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4A8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4A8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4A8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4A8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4A8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4A8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4AA "MBCCFR149,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4AA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4AA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4AA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4AA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4AA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4AA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4AC "MBFIDR149,Message Buffer Frame ID Registers" hexmask.word 0x4AC 0.--10. 1. "FID,Frame ID" line.word 0x4AE "MBIDXR149,Message Buffer Index Registers" hexmask.word 0x4AE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4B0 "MBCCSR150,Message Buffer Configuratio150. Control and Status Register 150" bitfld.word 0x4B0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4B0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4B0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4B0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4B0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4B0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4B0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4B0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4B0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4B0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4B2 "MBCCFR150,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4B2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4B2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4B2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4B2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4B2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4B2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4B4 "MBFIDR150,Message Buffer Frame ID Registers" hexmask.word 0x4B4 0.--10. 1. "FID,Frame ID" line.word 0x4B6 "MBIDXR150,Message Buffer Index Registers" hexmask.word 0x4B6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4B8 "MBCCSR151,Message Buffer Configuratio151. Control and Status Register 151" bitfld.word 0x4B8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4B8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4B8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4B8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4B8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4B8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4B8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4B8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4B8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4B8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4BA "MBCCFR151,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4BA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4BA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4BA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4BA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4BA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4BA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4BC "MBFIDR151,Message Buffer Frame ID Registers" hexmask.word 0x4BC 0.--10. 1. "FID,Frame ID" line.word 0x4BE "MBIDXR151,Message Buffer Index Registers" hexmask.word 0x4BE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4C0 "MBCCSR152,Message Buffer Configuratio152. Control and Status Register 152" bitfld.word 0x4C0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4C0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4C0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4C0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4C0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4C0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4C0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4C0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4C0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4C0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4C2 "MBCCFR152,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4C2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4C2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4C2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4C2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4C2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4C2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4C4 "MBFIDR152,Message Buffer Frame ID Registers" hexmask.word 0x4C4 0.--10. 1. "FID,Frame ID" line.word 0x4C6 "MBIDXR152,Message Buffer Index Registers" hexmask.word 0x4C6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4C8 "MBCCSR153,Message Buffer Configuratio153. Control and Status Register 153" bitfld.word 0x4C8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4C8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4C8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4C8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4C8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4C8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4C8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4C8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4C8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4C8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4CA "MBCCFR153,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4CA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4CA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4CA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4CA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4CA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4CA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4CC "MBFIDR153,Message Buffer Frame ID Registers" hexmask.word 0x4CC 0.--10. 1. "FID,Frame ID" line.word 0x4CE "MBIDXR153,Message Buffer Index Registers" hexmask.word 0x4CE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4D0 "MBCCSR154,Message Buffer Configuratio154. Control and Status Register 154" bitfld.word 0x4D0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4D0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4D0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4D0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4D0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4D0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4D0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4D0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4D0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4D0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4D2 "MBCCFR154,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4D2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4D2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4D2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4D2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4D2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4D2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4D4 "MBFIDR154,Message Buffer Frame ID Registers" hexmask.word 0x4D4 0.--10. 1. "FID,Frame ID" line.word 0x4D6 "MBIDXR154,Message Buffer Index Registers" hexmask.word 0x4D6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4D8 "MBCCSR155,Message Buffer Configuratio155. Control and Status Register 155" bitfld.word 0x4D8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4D8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4D8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4D8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4D8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4D8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4D8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4D8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4D8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4D8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4DA "MBCCFR155,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4DA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4DA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4DA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4DA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4DA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4DA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4DC "MBFIDR155,Message Buffer Frame ID Registers" hexmask.word 0x4DC 0.--10. 1. "FID,Frame ID" line.word 0x4DE "MBIDXR155,Message Buffer Index Registers" hexmask.word 0x4DE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4E0 "MBCCSR156,Message Buffer Configuratio156. Control and Status Register 156" bitfld.word 0x4E0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4E0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4E0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4E0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4E0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4E0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4E0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4E0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4E0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4E0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4E2 "MBCCFR156,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4E2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4E2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4E2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4E2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4E2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4E2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4E4 "MBFIDR156,Message Buffer Frame ID Registers" hexmask.word 0x4E4 0.--10. 1. "FID,Frame ID" line.word 0x4E6 "MBIDXR156,Message Buffer Index Registers" hexmask.word 0x4E6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4E8 "MBCCSR157,Message Buffer Configuratio157. Control and Status Register 157" bitfld.word 0x4E8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4E8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4E8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4E8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4E8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4E8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4E8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4E8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4E8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4E8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4EA "MBCCFR157,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4EA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4EA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4EA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4EA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4EA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4EA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4EC "MBFIDR157,Message Buffer Frame ID Registers" hexmask.word 0x4EC 0.--10. 1. "FID,Frame ID" line.word 0x4EE "MBIDXR157,Message Buffer Index Registers" hexmask.word 0x4EE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4F0 "MBCCSR158,Message Buffer Configuratio158. Control and Status Register 158" bitfld.word 0x4F0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4F0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4F0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4F0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4F0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4F0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4F0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4F0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4F0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4F0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4F2 "MBCCFR158,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4F2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4F2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4F2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4F2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4F2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4F2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4F4 "MBFIDR158,Message Buffer Frame ID Registers" hexmask.word 0x4F4 0.--10. 1. "FID,Frame ID" line.word 0x4F6 "MBIDXR158,Message Buffer Index Registers" hexmask.word 0x4F6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4F8 "MBCCSR159,Message Buffer Configuratio159. Control and Status Register 159" bitfld.word 0x4F8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4F8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4F8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4F8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4F8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4F8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4F8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4F8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4F8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4F8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4FA "MBCCFR159,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4FA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4FA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4FA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4FA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4FA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4FA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4FC "MBFIDR159,Message Buffer Frame ID Registers" hexmask.word 0x4FC 0.--10. 1. "FID,Frame ID" line.word 0x4FE "MBIDXR159,Message Buffer Index Registers" hexmask.word 0x4FE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x500 "MBCCSR160,Message Buffer Configuratio160. Control and Status Register 160" bitfld.word 0x500 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x500 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x500 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x500 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x500 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x500 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x500 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x500 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x500 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x500 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x502 "MBCCFR160,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x502 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x502 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x502 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x502 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x502 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x502 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x504 "MBFIDR160,Message Buffer Frame ID Registers" hexmask.word 0x504 0.--10. 1. "FID,Frame ID" line.word 0x506 "MBIDXR160,Message Buffer Index Registers" hexmask.word 0x506 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x508 "MBCCSR161,Message Buffer Configuratio161. Control and Status Register 161" bitfld.word 0x508 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x508 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x508 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x508 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x508 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x508 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x508 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x508 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x508 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x508 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x50A "MBCCFR161,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x50A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x50A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x50A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x50A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x50A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x50A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x50C "MBFIDR161,Message Buffer Frame ID Registers" hexmask.word 0x50C 0.--10. 1. "FID,Frame ID" line.word 0x50E "MBIDXR161,Message Buffer Index Registers" hexmask.word 0x50E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x510 "MBCCSR162,Message Buffer Configuratio162. Control and Status Register 162" bitfld.word 0x510 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x510 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x510 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x510 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x510 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x510 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x510 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x510 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x510 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x510 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x512 "MBCCFR162,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x512 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x512 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x512 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x512 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x512 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x512 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x514 "MBFIDR162,Message Buffer Frame ID Registers" hexmask.word 0x514 0.--10. 1. "FID,Frame ID" line.word 0x516 "MBIDXR162,Message Buffer Index Registers" hexmask.word 0x516 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x518 "MBCCSR163,Message Buffer Configuratio163. Control and Status Register 163" bitfld.word 0x518 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x518 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x518 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x518 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x518 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x518 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x518 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x518 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x518 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x518 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x51A "MBCCFR163,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x51A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x51A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x51A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x51A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x51A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x51A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x51C "MBFIDR163,Message Buffer Frame ID Registers" hexmask.word 0x51C 0.--10. 1. "FID,Frame ID" line.word 0x51E "MBIDXR163,Message Buffer Index Registers" hexmask.word 0x51E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x520 "MBCCSR164,Message Buffer Configuratio164. Control and Status Register 164" bitfld.word 0x520 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x520 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x520 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x520 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x520 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x520 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x520 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x520 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x520 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x520 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x522 "MBCCFR164,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x522 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x522 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x522 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x522 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x522 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x522 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x524 "MBFIDR164,Message Buffer Frame ID Registers" hexmask.word 0x524 0.--10. 1. "FID,Frame ID" line.word 0x526 "MBIDXR164,Message Buffer Index Registers" hexmask.word 0x526 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x528 "MBCCSR165,Message Buffer Configuratio165. Control and Status Register 165" bitfld.word 0x528 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x528 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x528 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x528 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x528 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x528 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x528 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x528 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x528 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x528 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x52A "MBCCFR165,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x52A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x52A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x52A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x52A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x52A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x52A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x52C "MBFIDR165,Message Buffer Frame ID Registers" hexmask.word 0x52C 0.--10. 1. "FID,Frame ID" line.word 0x52E "MBIDXR165,Message Buffer Index Registers" hexmask.word 0x52E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x530 "MBCCSR166,Message Buffer Configuratio166. Control and Status Register 166" bitfld.word 0x530 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x530 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x530 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x530 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x530 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x530 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x530 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x530 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x530 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x530 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x532 "MBCCFR166,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x532 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x532 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x532 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x532 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x532 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x532 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x534 "MBFIDR166,Message Buffer Frame ID Registers" hexmask.word 0x534 0.--10. 1. "FID,Frame ID" line.word 0x536 "MBIDXR166,Message Buffer Index Registers" hexmask.word 0x536 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x538 "MBCCSR167,Message Buffer Configuratio167. Control and Status Register 167" bitfld.word 0x538 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x538 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x538 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x538 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x538 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x538 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x538 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x538 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x538 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x538 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x53A "MBCCFR167,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x53A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x53A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x53A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x53A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x53A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x53A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x53C "MBFIDR167,Message Buffer Frame ID Registers" hexmask.word 0x53C 0.--10. 1. "FID,Frame ID" line.word 0x53E "MBIDXR167,Message Buffer Index Registers" hexmask.word 0x53E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x540 "MBCCSR168,Message Buffer Configuratio168. Control and Status Register 168" bitfld.word 0x540 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x540 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x540 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x540 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x540 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x540 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x540 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x540 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x540 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x540 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x542 "MBCCFR168,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x542 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x542 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x542 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x542 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x542 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x542 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x544 "MBFIDR168,Message Buffer Frame ID Registers" hexmask.word 0x544 0.--10. 1. "FID,Frame ID" line.word 0x546 "MBIDXR168,Message Buffer Index Registers" hexmask.word 0x546 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x548 "MBCCSR169,Message Buffer Configuratio169. Control and Status Register 169" bitfld.word 0x548 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x548 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x548 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x548 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x548 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x548 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x548 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x548 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x548 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x548 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x54A "MBCCFR169,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x54A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x54A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x54A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x54A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x54A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x54A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x54C "MBFIDR169,Message Buffer Frame ID Registers" hexmask.word 0x54C 0.--10. 1. "FID,Frame ID" line.word 0x54E "MBIDXR169,Message Buffer Index Registers" hexmask.word 0x54E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x550 "MBCCSR170,Message Buffer Configuratio170. Control and Status Register 170" bitfld.word 0x550 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x550 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x550 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x550 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x550 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x550 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x550 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x550 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x550 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x550 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x552 "MBCCFR170,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x552 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x552 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x552 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x552 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x552 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x552 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x554 "MBFIDR170,Message Buffer Frame ID Registers" hexmask.word 0x554 0.--10. 1. "FID,Frame ID" line.word 0x556 "MBIDXR170,Message Buffer Index Registers" hexmask.word 0x556 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x558 "MBCCSR171,Message Buffer Configuratio171. Control and Status Register 171" bitfld.word 0x558 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x558 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x558 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x558 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x558 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x558 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x558 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x558 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x558 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x558 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x55A "MBCCFR171,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x55A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x55A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x55A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x55A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x55A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x55A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x55C "MBFIDR171,Message Buffer Frame ID Registers" hexmask.word 0x55C 0.--10. 1. "FID,Frame ID" line.word 0x55E "MBIDXR171,Message Buffer Index Registers" hexmask.word 0x55E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x560 "MBCCSR172,Message Buffer Configuratio172. Control and Status Register 172" bitfld.word 0x560 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x560 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x560 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x560 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x560 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x560 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x560 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x560 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x560 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x560 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x562 "MBCCFR172,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x562 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x562 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x562 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x562 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x562 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x562 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x564 "MBFIDR172,Message Buffer Frame ID Registers" hexmask.word 0x564 0.--10. 1. "FID,Frame ID" line.word 0x566 "MBIDXR172,Message Buffer Index Registers" hexmask.word 0x566 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x568 "MBCCSR173,Message Buffer Configuratio173. Control and Status Register 173" bitfld.word 0x568 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x568 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x568 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x568 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x568 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x568 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x568 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x568 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x568 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x568 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x56A "MBCCFR173,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x56A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x56A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x56A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x56A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x56A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x56A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x56C "MBFIDR173,Message Buffer Frame ID Registers" hexmask.word 0x56C 0.--10. 1. "FID,Frame ID" line.word 0x56E "MBIDXR173,Message Buffer Index Registers" hexmask.word 0x56E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x570 "MBCCSR174,Message Buffer Configuratio174. Control and Status Register 174" bitfld.word 0x570 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x570 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x570 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x570 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x570 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x570 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x570 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x570 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x570 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x570 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x572 "MBCCFR174,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x572 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x572 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x572 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x572 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x572 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x572 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x574 "MBFIDR174,Message Buffer Frame ID Registers" hexmask.word 0x574 0.--10. 1. "FID,Frame ID" line.word 0x576 "MBIDXR174,Message Buffer Index Registers" hexmask.word 0x576 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x578 "MBCCSR175,Message Buffer Configuratio175. Control and Status Register 175" bitfld.word 0x578 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x578 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x578 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x578 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x578 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x578 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x578 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x578 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x578 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x578 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x57A "MBCCFR175,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x57A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x57A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x57A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x57A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x57A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x57A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x57C "MBFIDR175,Message Buffer Frame ID Registers" hexmask.word 0x57C 0.--10. 1. "FID,Frame ID" line.word 0x57E "MBIDXR175,Message Buffer Index Registers" hexmask.word 0x57E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x580 "MBCCSR176,Message Buffer Configuratio176. Control and Status Register 176" bitfld.word 0x580 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x580 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x580 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x580 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x580 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x580 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x580 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x580 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x580 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x580 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x582 "MBCCFR176,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x582 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x582 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x582 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x582 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x582 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x582 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x584 "MBFIDR176,Message Buffer Frame ID Registers" hexmask.word 0x584 0.--10. 1. "FID,Frame ID" line.word 0x586 "MBIDXR176,Message Buffer Index Registers" hexmask.word 0x586 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x588 "MBCCSR177,Message Buffer Configuratio177. Control and Status Register 177" bitfld.word 0x588 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x588 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x588 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x588 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x588 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x588 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x588 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x588 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x588 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x588 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x58A "MBCCFR177,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x58A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x58A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x58A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x58A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x58A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x58A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x58C "MBFIDR177,Message Buffer Frame ID Registers" hexmask.word 0x58C 0.--10. 1. "FID,Frame ID" line.word 0x58E "MBIDXR177,Message Buffer Index Registers" hexmask.word 0x58E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x590 "MBCCSR178,Message Buffer Configuratio178. Control and Status Register 178" bitfld.word 0x590 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x590 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x590 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x590 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x590 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x590 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x590 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x590 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x590 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x590 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x592 "MBCCFR178,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x592 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x592 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x592 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x592 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x592 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x592 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x594 "MBFIDR178,Message Buffer Frame ID Registers" hexmask.word 0x594 0.--10. 1. "FID,Frame ID" line.word 0x596 "MBIDXR178,Message Buffer Index Registers" hexmask.word 0x596 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x598 "MBCCSR179,Message Buffer Configuratio179. Control and Status Register 179" bitfld.word 0x598 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x598 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x598 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x598 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x598 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x598 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x598 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x598 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x598 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x598 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x59A "MBCCFR179,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x59A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x59A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x59A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x59A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x59A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x59A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x59C "MBFIDR179,Message Buffer Frame ID Registers" hexmask.word 0x59C 0.--10. 1. "FID,Frame ID" line.word 0x59E "MBIDXR179,Message Buffer Index Registers" hexmask.word 0x59E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5A0 "MBCCSR180,Message Buffer Configuratio180. Control and Status Register 180" bitfld.word 0x5A0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5A0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5A0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5A0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5A0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5A0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5A0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5A0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5A0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5A0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5A2 "MBCCFR180,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5A2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5A2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5A2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5A2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5A2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5A2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5A4 "MBFIDR180,Message Buffer Frame ID Registers" hexmask.word 0x5A4 0.--10. 1. "FID,Frame ID" line.word 0x5A6 "MBIDXR180,Message Buffer Index Registers" hexmask.word 0x5A6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5A8 "MBCCSR181,Message Buffer Configuratio181. Control and Status Register 181" bitfld.word 0x5A8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5A8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5A8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5A8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5A8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5A8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5A8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5A8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5A8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5A8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5AA "MBCCFR181,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5AA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5AA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5AA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5AA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5AA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5AA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5AC "MBFIDR181,Message Buffer Frame ID Registers" hexmask.word 0x5AC 0.--10. 1. "FID,Frame ID" line.word 0x5AE "MBIDXR181,Message Buffer Index Registers" hexmask.word 0x5AE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5B0 "MBCCSR182,Message Buffer Configuratio182. Control and Status Register 182" bitfld.word 0x5B0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5B0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5B0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5B0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5B0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5B0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5B0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5B0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5B0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5B0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5B2 "MBCCFR182,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5B2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5B2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5B2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5B2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5B2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5B2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5B4 "MBFIDR182,Message Buffer Frame ID Registers" hexmask.word 0x5B4 0.--10. 1. "FID,Frame ID" line.word 0x5B6 "MBIDXR182,Message Buffer Index Registers" hexmask.word 0x5B6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5B8 "MBCCSR183,Message Buffer Configuratio183. Control and Status Register 183" bitfld.word 0x5B8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5B8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5B8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5B8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5B8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5B8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5B8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5B8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5B8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5B8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5BA "MBCCFR183,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5BA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5BA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5BA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5BA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5BA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5BA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5BC "MBFIDR183,Message Buffer Frame ID Registers" hexmask.word 0x5BC 0.--10. 1. "FID,Frame ID" line.word 0x5BE "MBIDXR183,Message Buffer Index Registers" hexmask.word 0x5BE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5C0 "MBCCSR184,Message Buffer Configuratio184. Control and Status Register 184" bitfld.word 0x5C0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5C0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5C0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5C0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5C0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5C0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5C0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5C0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5C0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5C0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5C2 "MBCCFR184,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5C2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5C2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5C2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5C2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5C2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5C2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5C4 "MBFIDR184,Message Buffer Frame ID Registers" hexmask.word 0x5C4 0.--10. 1. "FID,Frame ID" line.word 0x5C6 "MBIDXR184,Message Buffer Index Registers" hexmask.word 0x5C6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5C8 "MBCCSR185,Message Buffer Configuratio185. Control and Status Register 185" bitfld.word 0x5C8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5C8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5C8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5C8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5C8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5C8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5C8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5C8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5C8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5C8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5CA "MBCCFR185,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5CA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5CA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5CA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5CA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5CA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5CA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5CC "MBFIDR185,Message Buffer Frame ID Registers" hexmask.word 0x5CC 0.--10. 1. "FID,Frame ID" line.word 0x5CE "MBIDXR185,Message Buffer Index Registers" hexmask.word 0x5CE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5D0 "MBCCSR186,Message Buffer Configuratio186. Control and Status Register 186" bitfld.word 0x5D0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5D0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5D0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5D0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5D0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5D0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5D0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5D0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5D0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5D0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5D2 "MBCCFR186,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5D2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5D2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5D2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5D2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5D2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5D2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5D4 "MBFIDR186,Message Buffer Frame ID Registers" hexmask.word 0x5D4 0.--10. 1. "FID,Frame ID" line.word 0x5D6 "MBIDXR186,Message Buffer Index Registers" hexmask.word 0x5D6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5D8 "MBCCSR187,Message Buffer Configuratio187. Control and Status Register 187" bitfld.word 0x5D8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5D8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5D8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5D8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5D8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5D8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5D8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5D8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5D8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5D8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5DA "MBCCFR187,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5DA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5DA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5DA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5DA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5DA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5DA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5DC "MBFIDR187,Message Buffer Frame ID Registers" hexmask.word 0x5DC 0.--10. 1. "FID,Frame ID" line.word 0x5DE "MBIDXR187,Message Buffer Index Registers" hexmask.word 0x5DE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5E0 "MBCCSR188,Message Buffer Configuratio188. Control and Status Register 188" bitfld.word 0x5E0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5E0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5E0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5E0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5E0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5E0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5E0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5E0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5E0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5E0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5E2 "MBCCFR188,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5E2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5E2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5E2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5E2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5E2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5E2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5E4 "MBFIDR188,Message Buffer Frame ID Registers" hexmask.word 0x5E4 0.--10. 1. "FID,Frame ID" line.word 0x5E6 "MBIDXR188,Message Buffer Index Registers" hexmask.word 0x5E6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5E8 "MBCCSR189,Message Buffer Configuratio189. Control and Status Register 189" bitfld.word 0x5E8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5E8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5E8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5E8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5E8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5E8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5E8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5E8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5E8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5E8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5EA "MBCCFR189,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5EA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5EA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5EA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5EA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5EA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5EA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5EC "MBFIDR189,Message Buffer Frame ID Registers" hexmask.word 0x5EC 0.--10. 1. "FID,Frame ID" line.word 0x5EE "MBIDXR189,Message Buffer Index Registers" hexmask.word 0x5EE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5F0 "MBCCSR190,Message Buffer Configuratio190. Control and Status Register 190" bitfld.word 0x5F0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5F0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5F0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5F0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5F0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5F0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5F0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5F0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5F0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5F0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5F2 "MBCCFR190,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5F2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5F2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5F2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5F2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5F2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5F2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5F4 "MBFIDR190,Message Buffer Frame ID Registers" hexmask.word 0x5F4 0.--10. 1. "FID,Frame ID" line.word 0x5F6 "MBIDXR190,Message Buffer Index Registers" hexmask.word 0x5F6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5F8 "MBCCSR191,Message Buffer Configuratio191. Control and Status Register 191" bitfld.word 0x5F8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5F8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5F8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5F8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5F8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5F8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5F8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5F8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5F8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5F8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5FA "MBCCFR191,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5FA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5FA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5FA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5FA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5FA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5FA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5FC "MBFIDR191,Message Buffer Frame ID Registers" hexmask.word 0x5FC 0.--10. 1. "FID,Frame ID" line.word 0x5FE "MBIDXR191,Message Buffer Index Registers" hexmask.word 0x5FE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x600 "MBCCSR192,Message Buffer Configuratio192. Control and Status Register 192" bitfld.word 0x600 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x600 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x600 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x600 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x600 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x600 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x600 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x600 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x600 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x600 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x602 "MBCCFR192,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x602 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x602 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x602 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x602 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x602 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x602 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x604 "MBFIDR192,Message Buffer Frame ID Registers" hexmask.word 0x604 0.--10. 1. "FID,Frame ID" line.word 0x606 "MBIDXR192,Message Buffer Index Registers" hexmask.word 0x606 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x608 "MBCCSR193,Message Buffer Configuratio193. Control and Status Register 193" bitfld.word 0x608 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x608 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x608 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x608 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x608 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x608 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x608 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x608 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x608 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x608 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x60A "MBCCFR193,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x60A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x60A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x60A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x60A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x60A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x60A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x60C "MBFIDR193,Message Buffer Frame ID Registers" hexmask.word 0x60C 0.--10. 1. "FID,Frame ID" line.word 0x60E "MBIDXR193,Message Buffer Index Registers" hexmask.word 0x60E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x610 "MBCCSR194,Message Buffer Configuratio194. Control and Status Register 194" bitfld.word 0x610 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x610 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x610 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x610 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x610 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x610 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x610 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x610 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x610 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x610 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x612 "MBCCFR194,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x612 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x612 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x612 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x612 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x612 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x612 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x614 "MBFIDR194,Message Buffer Frame ID Registers" hexmask.word 0x614 0.--10. 1. "FID,Frame ID" line.word 0x616 "MBIDXR194,Message Buffer Index Registers" hexmask.word 0x616 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x618 "MBCCSR195,Message Buffer Configuratio195. Control and Status Register 195" bitfld.word 0x618 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x618 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x618 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x618 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x618 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x618 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x618 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x618 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x618 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x618 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x61A "MBCCFR195,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x61A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x61A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x61A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x61A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x61A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x61A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x61C "MBFIDR195,Message Buffer Frame ID Registers" hexmask.word 0x61C 0.--10. 1. "FID,Frame ID" line.word 0x61E "MBIDXR195,Message Buffer Index Registers" hexmask.word 0x61E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x620 "MBCCSR196,Message Buffer Configuratio196. Control and Status Register 196" bitfld.word 0x620 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x620 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x620 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x620 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x620 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x620 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x620 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x620 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x620 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x620 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x622 "MBCCFR196,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x622 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x622 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x622 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x622 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x622 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x622 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x624 "MBFIDR196,Message Buffer Frame ID Registers" hexmask.word 0x624 0.--10. 1. "FID,Frame ID" line.word 0x626 "MBIDXR196,Message Buffer Index Registers" hexmask.word 0x626 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x628 "MBCCSR197,Message Buffer Configuratio197. Control and Status Register 197" bitfld.word 0x628 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x628 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x628 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x628 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x628 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x628 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x628 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x628 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x628 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x628 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x62A "MBCCFR197,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x62A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x62A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x62A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x62A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x62A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x62A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x62C "MBFIDR197,Message Buffer Frame ID Registers" hexmask.word 0x62C 0.--10. 1. "FID,Frame ID" line.word 0x62E "MBIDXR197,Message Buffer Index Registers" hexmask.word 0x62E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x630 "MBCCSR198,Message Buffer Configuratio198. Control and Status Register 198" bitfld.word 0x630 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x630 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x630 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x630 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x630 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x630 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x630 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x630 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x630 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x630 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x632 "MBCCFR198,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x632 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x632 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x632 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x632 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x632 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x632 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x634 "MBFIDR198,Message Buffer Frame ID Registers" hexmask.word 0x634 0.--10. 1. "FID,Frame ID" line.word 0x636 "MBIDXR198,Message Buffer Index Registers" hexmask.word 0x636 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x638 "MBCCSR199,Message Buffer Configuratio199. Control and Status Register 199" bitfld.word 0x638 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x638 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x638 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x638 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x638 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x638 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x638 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x638 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x638 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x638 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x63A "MBCCFR199,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x63A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x63A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x63A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x63A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x63A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x63A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x63C "MBFIDR199,Message Buffer Frame ID Registers" hexmask.word 0x63C 0.--10. 1. "FID,Frame ID" line.word 0x63E "MBIDXR199,Message Buffer Index Registers" hexmask.word 0x63E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x640 "MBCCSR200,Message Buffer Configuratio200. Control and Status Register 200" bitfld.word 0x640 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x640 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x640 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x640 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x640 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x640 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x640 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x640 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x640 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x640 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x642 "MBCCFR200,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x642 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x642 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x642 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x642 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x642 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x642 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x644 "MBFIDR200,Message Buffer Frame ID Registers" hexmask.word 0x644 0.--10. 1. "FID,Frame ID" line.word 0x646 "MBIDXR200,Message Buffer Index Registers" hexmask.word 0x646 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x648 "MBCCSR201,Message Buffer Configuratio201. Control and Status Register 201" bitfld.word 0x648 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x648 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x648 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x648 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x648 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x648 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x648 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x648 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x648 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x648 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x64A "MBCCFR201,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x64A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x64A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x64A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x64A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x64A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x64A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x64C "MBFIDR201,Message Buffer Frame ID Registers" hexmask.word 0x64C 0.--10. 1. "FID,Frame ID" line.word 0x64E "MBIDXR201,Message Buffer Index Registers" hexmask.word 0x64E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x650 "MBCCSR202,Message Buffer Configuratio202. Control and Status Register 202" bitfld.word 0x650 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x650 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x650 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x650 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x650 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x650 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x650 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x650 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x650 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x650 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x652 "MBCCFR202,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x652 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x652 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x652 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x652 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x652 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x652 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x654 "MBFIDR202,Message Buffer Frame ID Registers" hexmask.word 0x654 0.--10. 1. "FID,Frame ID" line.word 0x656 "MBIDXR202,Message Buffer Index Registers" hexmask.word 0x656 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x658 "MBCCSR203,Message Buffer Configuratio203. Control and Status Register 203" bitfld.word 0x658 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x658 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x658 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x658 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x658 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x658 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x658 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x658 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x658 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x658 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x65A "MBCCFR203,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x65A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x65A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x65A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x65A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x65A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x65A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x65C "MBFIDR203,Message Buffer Frame ID Registers" hexmask.word 0x65C 0.--10. 1. "FID,Frame ID" line.word 0x65E "MBIDXR203,Message Buffer Index Registers" hexmask.word 0x65E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x660 "MBCCSR204,Message Buffer Configuratio204. Control and Status Register 204" bitfld.word 0x660 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x660 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x660 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x660 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x660 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x660 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x660 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x660 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x660 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x660 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x662 "MBCCFR204,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x662 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x662 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x662 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x662 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x662 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x662 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x664 "MBFIDR204,Message Buffer Frame ID Registers" hexmask.word 0x664 0.--10. 1. "FID,Frame ID" line.word 0x666 "MBIDXR204,Message Buffer Index Registers" hexmask.word 0x666 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x668 "MBCCSR205,Message Buffer Configuratio205. Control and Status Register 205" bitfld.word 0x668 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x668 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x668 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x668 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x668 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x668 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x668 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x668 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x668 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x668 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x66A "MBCCFR205,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x66A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x66A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x66A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x66A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x66A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x66A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x66C "MBFIDR205,Message Buffer Frame ID Registers" hexmask.word 0x66C 0.--10. 1. "FID,Frame ID" line.word 0x66E "MBIDXR205,Message Buffer Index Registers" hexmask.word 0x66E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x670 "MBCCSR206,Message Buffer Configuratio206. Control and Status Register 206" bitfld.word 0x670 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x670 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x670 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x670 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x670 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x670 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x670 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x670 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x670 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x670 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x672 "MBCCFR206,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x672 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x672 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x672 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x672 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x672 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x672 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x674 "MBFIDR206,Message Buffer Frame ID Registers" hexmask.word 0x674 0.--10. 1. "FID,Frame ID" line.word 0x676 "MBIDXR206,Message Buffer Index Registers" hexmask.word 0x676 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x678 "MBCCSR207,Message Buffer Configuratio207. Control and Status Register 207" bitfld.word 0x678 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x678 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x678 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x678 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x678 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x678 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x678 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x678 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x678 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x678 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x67A "MBCCFR207,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x67A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x67A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x67A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x67A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x67A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x67A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x67C "MBFIDR207,Message Buffer Frame ID Registers" hexmask.word 0x67C 0.--10. 1. "FID,Frame ID" line.word 0x67E "MBIDXR207,Message Buffer Index Registers" hexmask.word 0x67E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x680 "MBCCSR208,Message Buffer Configuratio208. Control and Status Register 208" bitfld.word 0x680 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x680 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x680 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x680 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x680 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x680 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x680 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x680 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x680 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x680 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x682 "MBCCFR208,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x682 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x682 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x682 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x682 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x682 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x682 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x684 "MBFIDR208,Message Buffer Frame ID Registers" hexmask.word 0x684 0.--10. 1. "FID,Frame ID" line.word 0x686 "MBIDXR208,Message Buffer Index Registers" hexmask.word 0x686 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x688 "MBCCSR209,Message Buffer Configuratio209. Control and Status Register 209" bitfld.word 0x688 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x688 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x688 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x688 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x688 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x688 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x688 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x688 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x688 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x688 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x68A "MBCCFR209,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x68A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x68A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x68A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x68A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x68A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x68A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x68C "MBFIDR209,Message Buffer Frame ID Registers" hexmask.word 0x68C 0.--10. 1. "FID,Frame ID" line.word 0x68E "MBIDXR209,Message Buffer Index Registers" hexmask.word 0x68E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x690 "MBCCSR210,Message Buffer Configuratio210. Control and Status Register 210" bitfld.word 0x690 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x690 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x690 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x690 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x690 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x690 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x690 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x690 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x690 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x690 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x692 "MBCCFR210,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x692 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x692 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x692 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x692 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x692 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x692 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x694 "MBFIDR210,Message Buffer Frame ID Registers" hexmask.word 0x694 0.--10. 1. "FID,Frame ID" line.word 0x696 "MBIDXR210,Message Buffer Index Registers" hexmask.word 0x696 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x698 "MBCCSR211,Message Buffer Configuratio211. Control and Status Register 211" bitfld.word 0x698 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x698 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x698 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x698 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x698 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x698 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x698 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x698 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x698 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x698 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x69A "MBCCFR211,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x69A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x69A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x69A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x69A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x69A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x69A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x69C "MBFIDR211,Message Buffer Frame ID Registers" hexmask.word 0x69C 0.--10. 1. "FID,Frame ID" line.word 0x69E "MBIDXR211,Message Buffer Index Registers" hexmask.word 0x69E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6A0 "MBCCSR212,Message Buffer Configuratio212. Control and Status Register 212" bitfld.word 0x6A0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6A0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6A0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6A0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6A0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6A0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6A0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6A0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6A0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6A0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6A2 "MBCCFR212,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6A2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6A2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6A2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6A2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6A2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6A2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6A4 "MBFIDR212,Message Buffer Frame ID Registers" hexmask.word 0x6A4 0.--10. 1. "FID,Frame ID" line.word 0x6A6 "MBIDXR212,Message Buffer Index Registers" hexmask.word 0x6A6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6A8 "MBCCSR213,Message Buffer Configuratio213. Control and Status Register 213" bitfld.word 0x6A8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6A8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6A8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6A8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6A8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6A8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6A8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6A8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6A8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6A8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6AA "MBCCFR213,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6AA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6AA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6AA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6AA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6AA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6AA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6AC "MBFIDR213,Message Buffer Frame ID Registers" hexmask.word 0x6AC 0.--10. 1. "FID,Frame ID" line.word 0x6AE "MBIDXR213,Message Buffer Index Registers" hexmask.word 0x6AE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6B0 "MBCCSR214,Message Buffer Configuratio214. Control and Status Register 214" bitfld.word 0x6B0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6B0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6B0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6B0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6B0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6B0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6B0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6B0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6B0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6B0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6B2 "MBCCFR214,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6B2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6B2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6B2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6B2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6B2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6B2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6B4 "MBFIDR214,Message Buffer Frame ID Registers" hexmask.word 0x6B4 0.--10. 1. "FID,Frame ID" line.word 0x6B6 "MBIDXR214,Message Buffer Index Registers" hexmask.word 0x6B6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6B8 "MBCCSR215,Message Buffer Configuratio215. Control and Status Register 215" bitfld.word 0x6B8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6B8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6B8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6B8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6B8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6B8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6B8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6B8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6B8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6B8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6BA "MBCCFR215,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6BA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6BA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6BA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6BA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6BA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6BA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6BC "MBFIDR215,Message Buffer Frame ID Registers" hexmask.word 0x6BC 0.--10. 1. "FID,Frame ID" line.word 0x6BE "MBIDXR215,Message Buffer Index Registers" hexmask.word 0x6BE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6C0 "MBCCSR216,Message Buffer Configuratio216. Control and Status Register 216" bitfld.word 0x6C0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6C0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6C0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6C0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6C0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6C0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6C0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6C0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6C0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6C0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6C2 "MBCCFR216,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6C2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6C2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6C2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6C2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6C2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6C2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6C4 "MBFIDR216,Message Buffer Frame ID Registers" hexmask.word 0x6C4 0.--10. 1. "FID,Frame ID" line.word 0x6C6 "MBIDXR216,Message Buffer Index Registers" hexmask.word 0x6C6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6C8 "MBCCSR217,Message Buffer Configuratio217. Control and Status Register 217" bitfld.word 0x6C8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6C8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6C8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6C8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6C8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6C8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6C8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6C8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6C8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6C8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6CA "MBCCFR217,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6CA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6CA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6CA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6CA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6CA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6CA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6CC "MBFIDR217,Message Buffer Frame ID Registers" hexmask.word 0x6CC 0.--10. 1. "FID,Frame ID" line.word 0x6CE "MBIDXR217,Message Buffer Index Registers" hexmask.word 0x6CE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6D0 "MBCCSR218,Message Buffer Configuratio218. Control and Status Register 218" bitfld.word 0x6D0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6D0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6D0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6D0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6D0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6D0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6D0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6D0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6D0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6D0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6D2 "MBCCFR218,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6D2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6D2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6D2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6D2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6D2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6D2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6D4 "MBFIDR218,Message Buffer Frame ID Registers" hexmask.word 0x6D4 0.--10. 1. "FID,Frame ID" line.word 0x6D6 "MBIDXR218,Message Buffer Index Registers" hexmask.word 0x6D6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6D8 "MBCCSR219,Message Buffer Configuratio219. Control and Status Register 219" bitfld.word 0x6D8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6D8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6D8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6D8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6D8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6D8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6D8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6D8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6D8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6D8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6DA "MBCCFR219,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6DA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6DA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6DA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6DA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6DA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6DA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6DC "MBFIDR219,Message Buffer Frame ID Registers" hexmask.word 0x6DC 0.--10. 1. "FID,Frame ID" line.word 0x6DE "MBIDXR219,Message Buffer Index Registers" hexmask.word 0x6DE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6E0 "MBCCSR220,Message Buffer Configuratio220. Control and Status Register 220" bitfld.word 0x6E0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6E0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6E0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6E0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6E0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6E0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6E0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6E0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6E0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6E0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6E2 "MBCCFR220,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6E2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6E2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6E2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6E2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6E2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6E2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6E4 "MBFIDR220,Message Buffer Frame ID Registers" hexmask.word 0x6E4 0.--10. 1. "FID,Frame ID" line.word 0x6E6 "MBIDXR220,Message Buffer Index Registers" hexmask.word 0x6E6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6E8 "MBCCSR221,Message Buffer Configuratio221. Control and Status Register 221" bitfld.word 0x6E8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6E8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6E8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6E8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6E8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6E8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6E8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6E8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6E8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6E8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6EA "MBCCFR221,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6EA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6EA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6EA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6EA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6EA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6EA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6EC "MBFIDR221,Message Buffer Frame ID Registers" hexmask.word 0x6EC 0.--10. 1. "FID,Frame ID" line.word 0x6EE "MBIDXR221,Message Buffer Index Registers" hexmask.word 0x6EE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6F0 "MBCCSR222,Message Buffer Configuratio222. Control and Status Register 222" bitfld.word 0x6F0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6F0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6F0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6F0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6F0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6F0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6F0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6F0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6F0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6F0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6F2 "MBCCFR222,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6F2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6F2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6F2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6F2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6F2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6F2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6F4 "MBFIDR222,Message Buffer Frame ID Registers" hexmask.word 0x6F4 0.--10. 1. "FID,Frame ID" line.word 0x6F6 "MBIDXR222,Message Buffer Index Registers" hexmask.word 0x6F6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6F8 "MBCCSR223,Message Buffer Configuratio223. Control and Status Register 223" bitfld.word 0x6F8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6F8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6F8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6F8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6F8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6F8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6F8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6F8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6F8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6F8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6FA "MBCCFR223,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6FA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6FA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6FA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6FA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6FA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6FA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6FC "MBFIDR223,Message Buffer Frame ID Registers" hexmask.word 0x6FC 0.--10. 1. "FID,Frame ID" line.word 0x6FE "MBIDXR223,Message Buffer Index Registers" hexmask.word 0x6FE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x700 "MBCCSR224,Message Buffer Configuratio224. Control and Status Register 224" bitfld.word 0x700 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x700 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x700 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x700 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x700 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x700 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x700 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x700 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x700 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x700 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x702 "MBCCFR224,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x702 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x702 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x702 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x702 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x702 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x702 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x704 "MBFIDR224,Message Buffer Frame ID Registers" hexmask.word 0x704 0.--10. 1. "FID,Frame ID" line.word 0x706 "MBIDXR224,Message Buffer Index Registers" hexmask.word 0x706 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x708 "MBCCSR225,Message Buffer Configuratio225. Control and Status Register 225" bitfld.word 0x708 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x708 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x708 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x708 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x708 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x708 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x708 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x708 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x708 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x708 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x70A "MBCCFR225,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x70A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x70A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x70A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x70A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x70A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x70A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x70C "MBFIDR225,Message Buffer Frame ID Registers" hexmask.word 0x70C 0.--10. 1. "FID,Frame ID" line.word 0x70E "MBIDXR225,Message Buffer Index Registers" hexmask.word 0x70E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x710 "MBCCSR226,Message Buffer Configuratio226. Control and Status Register 226" bitfld.word 0x710 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x710 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x710 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x710 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x710 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x710 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x710 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x710 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x710 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x710 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x712 "MBCCFR226,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x712 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x712 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x712 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x712 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x712 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x712 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x714 "MBFIDR226,Message Buffer Frame ID Registers" hexmask.word 0x714 0.--10. 1. "FID,Frame ID" line.word 0x716 "MBIDXR226,Message Buffer Index Registers" hexmask.word 0x716 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x718 "MBCCSR227,Message Buffer Configuratio227. Control and Status Register 227" bitfld.word 0x718 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x718 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x718 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x718 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x718 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x718 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x718 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x718 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x718 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x718 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x71A "MBCCFR227,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x71A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x71A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x71A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x71A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x71A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x71A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x71C "MBFIDR227,Message Buffer Frame ID Registers" hexmask.word 0x71C 0.--10. 1. "FID,Frame ID" line.word 0x71E "MBIDXR227,Message Buffer Index Registers" hexmask.word 0x71E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x720 "MBCCSR228,Message Buffer Configuratio228. Control and Status Register 228" bitfld.word 0x720 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x720 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x720 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x720 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x720 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x720 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x720 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x720 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x720 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x720 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x722 "MBCCFR228,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x722 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x722 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x722 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x722 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x722 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x722 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x724 "MBFIDR228,Message Buffer Frame ID Registers" hexmask.word 0x724 0.--10. 1. "FID,Frame ID" line.word 0x726 "MBIDXR228,Message Buffer Index Registers" hexmask.word 0x726 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x728 "MBCCSR229,Message Buffer Configuratio229. Control and Status Register 229" bitfld.word 0x728 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x728 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x728 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x728 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x728 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x728 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x728 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x728 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x728 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x728 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x72A "MBCCFR229,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x72A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x72A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x72A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x72A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x72A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x72A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x72C "MBFIDR229,Message Buffer Frame ID Registers" hexmask.word 0x72C 0.--10. 1. "FID,Frame ID" line.word 0x72E "MBIDXR229,Message Buffer Index Registers" hexmask.word 0x72E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x730 "MBCCSR230,Message Buffer Configuratio230. Control and Status Register 230" bitfld.word 0x730 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x730 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x730 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x730 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x730 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x730 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x730 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x730 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x730 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x730 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x732 "MBCCFR230,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x732 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x732 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x732 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x732 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x732 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x732 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x734 "MBFIDR230,Message Buffer Frame ID Registers" hexmask.word 0x734 0.--10. 1. "FID,Frame ID" line.word 0x736 "MBIDXR230,Message Buffer Index Registers" hexmask.word 0x736 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x738 "MBCCSR231,Message Buffer Configuratio231. Control and Status Register 231" bitfld.word 0x738 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x738 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x738 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x738 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x738 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x738 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x738 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x738 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x738 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x738 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x73A "MBCCFR231,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x73A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x73A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x73A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x73A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x73A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x73A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x73C "MBFIDR231,Message Buffer Frame ID Registers" hexmask.word 0x73C 0.--10. 1. "FID,Frame ID" line.word 0x73E "MBIDXR231,Message Buffer Index Registers" hexmask.word 0x73E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x740 "MBCCSR232,Message Buffer Configuratio232. Control and Status Register 232" bitfld.word 0x740 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x740 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x740 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x740 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x740 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x740 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x740 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x740 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x740 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x740 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x742 "MBCCFR232,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x742 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x742 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x742 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x742 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x742 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x742 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x744 "MBFIDR232,Message Buffer Frame ID Registers" hexmask.word 0x744 0.--10. 1. "FID,Frame ID" line.word 0x746 "MBIDXR232,Message Buffer Index Registers" hexmask.word 0x746 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x748 "MBCCSR233,Message Buffer Configuratio233. Control and Status Register 233" bitfld.word 0x748 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x748 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x748 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x748 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x748 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x748 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x748 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x748 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x748 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x748 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x74A "MBCCFR233,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x74A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x74A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x74A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x74A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x74A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x74A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x74C "MBFIDR233,Message Buffer Frame ID Registers" hexmask.word 0x74C 0.--10. 1. "FID,Frame ID" line.word 0x74E "MBIDXR233,Message Buffer Index Registers" hexmask.word 0x74E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x750 "MBCCSR234,Message Buffer Configuratio234. Control and Status Register 234" bitfld.word 0x750 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x750 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x750 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x750 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x750 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x750 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x750 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x750 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x750 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x750 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x752 "MBCCFR234,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x752 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x752 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x752 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x752 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x752 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x752 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x754 "MBFIDR234,Message Buffer Frame ID Registers" hexmask.word 0x754 0.--10. 1. "FID,Frame ID" line.word 0x756 "MBIDXR234,Message Buffer Index Registers" hexmask.word 0x756 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x758 "MBCCSR235,Message Buffer Configuratio235. Control and Status Register 235" bitfld.word 0x758 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x758 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x758 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x758 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x758 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x758 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x758 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x758 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x758 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x758 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x75A "MBCCFR235,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x75A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x75A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x75A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x75A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x75A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x75A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x75C "MBFIDR235,Message Buffer Frame ID Registers" hexmask.word 0x75C 0.--10. 1. "FID,Frame ID" line.word 0x75E "MBIDXR235,Message Buffer Index Registers" hexmask.word 0x75E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x760 "MBCCSR236,Message Buffer Configuratio236. Control and Status Register 236" bitfld.word 0x760 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x760 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x760 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x760 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x760 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x760 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x760 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x760 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x760 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x760 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x762 "MBCCFR236,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x762 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x762 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x762 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x762 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x762 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x762 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x764 "MBFIDR236,Message Buffer Frame ID Registers" hexmask.word 0x764 0.--10. 1. "FID,Frame ID" line.word 0x766 "MBIDXR236,Message Buffer Index Registers" hexmask.word 0x766 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x768 "MBCCSR237,Message Buffer Configuratio237. Control and Status Register 237" bitfld.word 0x768 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x768 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x768 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x768 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x768 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x768 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x768 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x768 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x768 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x768 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x76A "MBCCFR237,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x76A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x76A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x76A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x76A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x76A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x76A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x76C "MBFIDR237,Message Buffer Frame ID Registers" hexmask.word 0x76C 0.--10. 1. "FID,Frame ID" line.word 0x76E "MBIDXR237,Message Buffer Index Registers" hexmask.word 0x76E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x770 "MBCCSR238,Message Buffer Configuratio238. Control and Status Register 238" bitfld.word 0x770 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x770 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x770 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x770 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x770 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x770 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x770 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x770 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x770 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x770 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x772 "MBCCFR238,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x772 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x772 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x772 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x772 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x772 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x772 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x774 "MBFIDR238,Message Buffer Frame ID Registers" hexmask.word 0x774 0.--10. 1. "FID,Frame ID" line.word 0x776 "MBIDXR238,Message Buffer Index Registers" hexmask.word 0x776 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x778 "MBCCSR239,Message Buffer Configuratio239. Control and Status Register 239" bitfld.word 0x778 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x778 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x778 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x778 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x778 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x778 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x778 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x778 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x778 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x778 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x77A "MBCCFR239,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x77A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x77A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x77A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x77A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x77A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x77A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x77C "MBFIDR239,Message Buffer Frame ID Registers" hexmask.word 0x77C 0.--10. 1. "FID,Frame ID" line.word 0x77E "MBIDXR239,Message Buffer Index Registers" hexmask.word 0x77E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x780 "MBCCSR240,Message Buffer Configuratio240. Control and Status Register 240" bitfld.word 0x780 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x780 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x780 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x780 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x780 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x780 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x780 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x780 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x780 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x780 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x782 "MBCCFR240,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x782 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x782 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x782 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x782 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x782 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x782 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x784 "MBFIDR240,Message Buffer Frame ID Registers" hexmask.word 0x784 0.--10. 1. "FID,Frame ID" line.word 0x786 "MBIDXR240,Message Buffer Index Registers" hexmask.word 0x786 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x788 "MBCCSR241,Message Buffer Configuratio241. Control and Status Register 241" bitfld.word 0x788 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x788 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x788 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x788 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x788 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x788 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x788 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x788 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x788 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x788 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x78A "MBCCFR241,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x78A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x78A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x78A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x78A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x78A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x78A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x78C "MBFIDR241,Message Buffer Frame ID Registers" hexmask.word 0x78C 0.--10. 1. "FID,Frame ID" line.word 0x78E "MBIDXR241,Message Buffer Index Registers" hexmask.word 0x78E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x790 "MBCCSR242,Message Buffer Configuratio242. Control and Status Register 242" bitfld.word 0x790 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x790 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x790 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x790 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x790 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x790 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x790 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x790 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x790 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x790 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x792 "MBCCFR242,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x792 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x792 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x792 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x792 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x792 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x792 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x794 "MBFIDR242,Message Buffer Frame ID Registers" hexmask.word 0x794 0.--10. 1. "FID,Frame ID" line.word 0x796 "MBIDXR242,Message Buffer Index Registers" hexmask.word 0x796 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x798 "MBCCSR243,Message Buffer Configuratio243. Control and Status Register 243" bitfld.word 0x798 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x798 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x798 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x798 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x798 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x798 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x798 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x798 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x798 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x798 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x79A "MBCCFR243,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x79A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x79A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x79A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x79A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x79A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x79A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x79C "MBFIDR243,Message Buffer Frame ID Registers" hexmask.word 0x79C 0.--10. 1. "FID,Frame ID" line.word 0x79E "MBIDXR243,Message Buffer Index Registers" hexmask.word 0x79E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7A0 "MBCCSR244,Message Buffer Configuratio244. Control and Status Register 244" bitfld.word 0x7A0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7A0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7A0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7A0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7A0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7A0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7A0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7A0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7A0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7A0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7A2 "MBCCFR244,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7A2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7A2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7A2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7A2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7A2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7A2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7A4 "MBFIDR244,Message Buffer Frame ID Registers" hexmask.word 0x7A4 0.--10. 1. "FID,Frame ID" line.word 0x7A6 "MBIDXR244,Message Buffer Index Registers" hexmask.word 0x7A6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7A8 "MBCCSR245,Message Buffer Configuratio245. Control and Status Register 245" bitfld.word 0x7A8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7A8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7A8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7A8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7A8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7A8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7A8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7A8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7A8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7A8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7AA "MBCCFR245,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7AA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7AA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7AA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7AA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7AA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7AA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7AC "MBFIDR245,Message Buffer Frame ID Registers" hexmask.word 0x7AC 0.--10. 1. "FID,Frame ID" line.word 0x7AE "MBIDXR245,Message Buffer Index Registers" hexmask.word 0x7AE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7B0 "MBCCSR246,Message Buffer Configuratio246. Control and Status Register 246" bitfld.word 0x7B0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7B0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7B0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7B0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7B0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7B0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7B0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7B0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7B0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7B0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7B2 "MBCCFR246,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7B2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7B2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7B2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7B2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7B2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7B2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7B4 "MBFIDR246,Message Buffer Frame ID Registers" hexmask.word 0x7B4 0.--10. 1. "FID,Frame ID" line.word 0x7B6 "MBIDXR246,Message Buffer Index Registers" hexmask.word 0x7B6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7B8 "MBCCSR247,Message Buffer Configuratio247. Control and Status Register 247" bitfld.word 0x7B8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7B8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7B8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7B8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7B8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7B8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7B8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7B8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7B8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7B8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7BA "MBCCFR247,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7BA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7BA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7BA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7BA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7BA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7BA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7BC "MBFIDR247,Message Buffer Frame ID Registers" hexmask.word 0x7BC 0.--10. 1. "FID,Frame ID" line.word 0x7BE "MBIDXR247,Message Buffer Index Registers" hexmask.word 0x7BE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7C0 "MBCCSR248,Message Buffer Configuratio248. Control and Status Register 248" bitfld.word 0x7C0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7C0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7C0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7C0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7C0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7C0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7C0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7C0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7C0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7C0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7C2 "MBCCFR248,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7C2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7C2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7C2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7C2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7C2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7C2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7C4 "MBFIDR248,Message Buffer Frame ID Registers" hexmask.word 0x7C4 0.--10. 1. "FID,Frame ID" line.word 0x7C6 "MBIDXR248,Message Buffer Index Registers" hexmask.word 0x7C6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7C8 "MBCCSR249,Message Buffer Configuratio249. Control and Status Register 249" bitfld.word 0x7C8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7C8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7C8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7C8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7C8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7C8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7C8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7C8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7C8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7C8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7CA "MBCCFR249,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7CA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7CA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7CA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7CA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7CA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7CA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7CC "MBFIDR249,Message Buffer Frame ID Registers" hexmask.word 0x7CC 0.--10. 1. "FID,Frame ID" line.word 0x7CE "MBIDXR249,Message Buffer Index Registers" hexmask.word 0x7CE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7D0 "MBCCSR250,Message Buffer Configuratio250. Control and Status Register 250" bitfld.word 0x7D0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7D0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7D0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7D0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7D0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7D0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7D0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7D0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7D0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7D0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7D2 "MBCCFR250,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7D2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7D2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7D2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7D2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7D2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7D2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7D4 "MBFIDR250,Message Buffer Frame ID Registers" hexmask.word 0x7D4 0.--10. 1. "FID,Frame ID" line.word 0x7D6 "MBIDXR250,Message Buffer Index Registers" hexmask.word 0x7D6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7D8 "MBCCSR251,Message Buffer Configuratio251. Control and Status Register 251" bitfld.word 0x7D8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7D8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7D8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7D8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7D8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7D8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7D8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7D8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7D8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7D8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7DA "MBCCFR251,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7DA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7DA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7DA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7DA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7DA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7DA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7DC "MBFIDR251,Message Buffer Frame ID Registers" hexmask.word 0x7DC 0.--10. 1. "FID,Frame ID" line.word 0x7DE "MBIDXR251,Message Buffer Index Registers" hexmask.word 0x7DE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7E0 "MBCCSR252,Message Buffer Configuratio252. Control and Status Register 252" bitfld.word 0x7E0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7E0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7E0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7E0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7E0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7E0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7E0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7E0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7E0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7E0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7E2 "MBCCFR252,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7E2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7E2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7E2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7E2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7E2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7E2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7E4 "MBFIDR252,Message Buffer Frame ID Registers" hexmask.word 0x7E4 0.--10. 1. "FID,Frame ID" line.word 0x7E6 "MBIDXR252,Message Buffer Index Registers" hexmask.word 0x7E6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7E8 "MBCCSR253,Message Buffer Configuratio253. Control and Status Register 253" bitfld.word 0x7E8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7E8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7E8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7E8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7E8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7E8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7E8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7E8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7E8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7E8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7EA "MBCCFR253,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7EA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7EA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7EA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7EA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7EA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7EA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7EC "MBFIDR253,Message Buffer Frame ID Registers" hexmask.word 0x7EC 0.--10. 1. "FID,Frame ID" line.word 0x7EE "MBIDXR253,Message Buffer Index Registers" hexmask.word 0x7EE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7F0 "MBCCSR254,Message Buffer Configuratio254. Control and Status Register 254" bitfld.word 0x7F0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7F0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7F0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7F0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7F0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7F0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7F0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7F0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7F0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7F0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7F2 "MBCCFR254,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7F2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7F2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7F2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7F2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7F2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7F2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7F4 "MBFIDR254,Message Buffer Frame ID Registers" hexmask.word 0x7F4 0.--10. 1. "FID,Frame ID" line.word 0x7F6 "MBIDXR254,Message Buffer Index Registers" hexmask.word 0x7F6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7F8 "MBCCSR255,Message Buffer Configuratio255. Control and Status Register 255" bitfld.word 0x7F8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7F8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7F8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7F8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7F8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7F8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7F8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7F8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7F8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7F8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7FA "MBCCFR255,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7FA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7FA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7FA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7FA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7FA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7FA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7FC "MBFIDR255,Message Buffer Frame ID Registers" hexmask.word 0x7FC 0.--10. 1. "FID,Frame ID" line.word 0x7FE "MBIDXR255,Message Buffer Index Registers" hexmask.word 0x7FE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x800 "MBDOR0,Message Buffer Data Field Offset Registers" hexmask.word 0x800 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x802 "MBDOR1,Message Buffer Data Field Offset Registers" hexmask.word 0x802 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x804 "MBDOR2,Message Buffer Data Field Offset Registers" hexmask.word 0x804 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x806 "MBDOR3,Message Buffer Data Field Offset Registers" hexmask.word 0x806 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x808 "MBDOR4,Message Buffer Data Field Offset Registers" hexmask.word 0x808 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x80A "MBDOR5,Message Buffer Data Field Offset Registers" hexmask.word 0x80A 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x80C "MBDOR6,Message Buffer Data Field Offset Registers" hexmask.word 0x80C 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x80E "MBDOR7,Message Buffer Data Field Offset Registers" hexmask.word 0x80E 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x810 "MBDOR8,Message Buffer Data Field Offset Registers" hexmask.word 0x810 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x812 "MBDOR9,Message Buffer Data Field Offset Registers" hexmask.word 0x812 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x814 "MBDOR10,Message Buffer Data Field Offset Registers" hexmask.word 0x814 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x816 "MBDOR11,Message Buffer Data Field Offset Registers" hexmask.word 0x816 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x818 "MBDOR12,Message Buffer Data Field Offset Registers" hexmask.word 0x818 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x81A "MBDOR13,Message Buffer Data Field Offset Registers" hexmask.word 0x81A 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x81C "MBDOR14,Message Buffer Data Field Offset Registers" hexmask.word 0x81C 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x81E "MBDOR15,Message Buffer Data Field Offset Registers" hexmask.word 0x81E 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x820 "MBDOR16,Message Buffer Data Field Offset Registers" hexmask.word 0x820 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x822 "MBDOR17,Message Buffer Data Field Offset Registers" hexmask.word 0x822 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x824 "MBDOR18,Message Buffer Data Field Offset Registers" hexmask.word 0x824 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x826 "MBDOR19,Message Buffer Data Field Offset Registers" hexmask.word 0x826 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x828 "MBDOR20,Message Buffer Data Field Offset Registers" hexmask.word 0x828 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x82A "MBDOR21,Message Buffer Data Field Offset Registers" hexmask.word 0x82A 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x82C "MBDOR22,Message Buffer Data Field Offset Registers" hexmask.word 0x82C 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x82E "MBDOR23,Message Buffer Data Field Offset Registers" hexmask.word 0x82E 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x830 "MBDOR24,Message Buffer Data Field Offset Registers" hexmask.word 0x830 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x832 "MBDOR25,Message Buffer Data Field Offset Registers" hexmask.word 0x832 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x834 "MBDOR26,Message Buffer Data Field Offset Registers" hexmask.word 0x834 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x836 "MBDOR27,Message Buffer Data Field Offset Registers" hexmask.word 0x836 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x838 "MBDOR28,Message Buffer Data Field Offset Registers" hexmask.word 0x838 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x83A "MBDOR29,Message Buffer Data Field Offset Registers" hexmask.word 0x83A 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x83C "MBDOR30,Message Buffer Data Field Offset Registers" hexmask.word 0x83C 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x83E "MBDOR31,Message Buffer Data Field Offset Registers" hexmask.word 0x83E 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x840 "MBDOR32,Message Buffer Data Field Offset Registers" hexmask.word 0x840 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x842 "MBDOR33,Message Buffer Data Field Offset Registers" hexmask.word 0x842 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x844 "MBDOR34,Message Buffer Data Field Offset Registers" hexmask.word 0x844 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x846 "MBDOR35,Message Buffer Data Field Offset Registers" hexmask.word 0x846 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x848 "MBDOR36,Message Buffer Data Field Offset Registers" hexmask.word 0x848 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x84A "MBDOR37,Message Buffer Data Field Offset Registers" hexmask.word 0x84A 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x84C "MBDOR38,Message Buffer Data Field Offset Registers" hexmask.word 0x84C 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x84E "MBDOR39,Message Buffer Data Field Offset Registers" hexmask.word 0x84E 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x850 "MBDOR40,Message Buffer Data Field Offset Registers" hexmask.word 0x850 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x852 "MBDOR41,Message Buffer Data Field Offset Registers" hexmask.word 0x852 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x854 "MBDOR42,Message Buffer Data Field Offset Registers" hexmask.word 0x854 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x856 "MBDOR43,Message Buffer Data Field Offset Registers" hexmask.word 0x856 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x858 "MBDOR44,Message Buffer Data Field Offset Registers" hexmask.word 0x858 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x85A "MBDOR45,Message Buffer Data Field Offset Registers" hexmask.word 0x85A 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x85C "MBDOR46,Message Buffer Data Field Offset Registers" hexmask.word 0x85C 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x85E "MBDOR47,Message Buffer Data Field Offset Registers" hexmask.word 0x85E 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x860 "MBDOR48,Message Buffer Data Field Offset Registers" hexmask.word 0x860 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x862 "MBDOR49,Message Buffer Data Field Offset Registers" hexmask.word 0x862 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x864 "MBDOR50,Message Buffer Data Field Offset Registers" hexmask.word 0x864 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x866 "MBDOR51,Message Buffer Data Field Offset Registers" hexmask.word 0x866 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x868 "MBDOR52,Message Buffer Data Field Offset Registers" hexmask.word 0x868 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x86A "MBDOR53,Message Buffer Data Field Offset Registers" hexmask.word 0x86A 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x86C "MBDOR54,Message Buffer Data Field Offset Registers" hexmask.word 0x86C 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x86E "MBDOR55,Message Buffer Data Field Offset Registers" hexmask.word 0x86E 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x870 "MBDOR56,Message Buffer Data Field Offset Registers" hexmask.word 0x870 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x872 "MBDOR57,Message Buffer Data Field Offset Registers" hexmask.word 0x872 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x874 "MBDOR58,Message Buffer Data Field Offset Registers" hexmask.word 0x874 0.--15. 1. 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"MBDO,Message Buffer Data Field Offset" line.word 0x99C "MBDOR206,Message Buffer Data Field Offset Registers" hexmask.word 0x99C 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x99E "MBDOR207,Message Buffer Data Field Offset Registers" hexmask.word 0x99E 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9A0 "MBDOR208,Message Buffer Data Field Offset Registers" hexmask.word 0x9A0 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9A2 "MBDOR209,Message Buffer Data Field Offset Registers" hexmask.word 0x9A2 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9A4 "MBDOR210,Message Buffer Data Field Offset Registers" hexmask.word 0x9A4 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9A6 "MBDOR211,Message Buffer Data Field Offset Registers" hexmask.word 0x9A6 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9A8 "MBDOR212,Message Buffer Data Field Offset Registers" hexmask.word 0x9A8 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9AA "MBDOR213,Message Buffer Data Field Offset Registers" hexmask.word 0x9AA 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9AC "MBDOR214,Message Buffer Data Field Offset Registers" hexmask.word 0x9AC 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9AE "MBDOR215,Message Buffer Data Field Offset Registers" hexmask.word 0x9AE 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9B0 "MBDOR216,Message Buffer Data Field Offset Registers" hexmask.word 0x9B0 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9B2 "MBDOR217,Message Buffer Data Field Offset Registers" hexmask.word 0x9B2 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9B4 "MBDOR218,Message Buffer Data Field Offset Registers" hexmask.word 0x9B4 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9B6 "MBDOR219,Message Buffer Data Field Offset Registers" hexmask.word 0x9B6 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9B8 "MBDOR220,Message Buffer Data Field Offset Registers" hexmask.word 0x9B8 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9BA "MBDOR221,Message Buffer Data Field Offset Registers" hexmask.word 0x9BA 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9BC "MBDOR222,Message Buffer Data Field Offset Registers" hexmask.word 0x9BC 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9BE "MBDOR223,Message Buffer Data Field Offset Registers" hexmask.word 0x9BE 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9C0 "MBDOR224,Message Buffer Data Field Offset Registers" hexmask.word 0x9C0 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9C2 "MBDOR225,Message Buffer Data Field Offset Registers" hexmask.word 0x9C2 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9C4 "MBDOR226,Message Buffer Data Field Offset Registers" hexmask.word 0x9C4 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9C6 "MBDOR227,Message Buffer Data Field Offset Registers" hexmask.word 0x9C6 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9C8 "MBDOR228,Message Buffer Data Field Offset Registers" hexmask.word 0x9C8 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9CA "MBDOR229,Message Buffer Data Field Offset Registers" hexmask.word 0x9CA 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9CC "MBDOR230,Message Buffer Data Field Offset Registers" hexmask.word 0x9CC 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9CE "MBDOR231,Message Buffer Data Field Offset Registers" hexmask.word 0x9CE 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9D0 "MBDOR232,Message Buffer Data Field Offset Registers" hexmask.word 0x9D0 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9D2 "MBDOR233,Message Buffer Data Field Offset Registers" hexmask.word 0x9D2 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9D4 "MBDOR234,Message Buffer Data Field Offset Registers" hexmask.word 0x9D4 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9D6 "MBDOR235,Message Buffer Data Field Offset Registers" hexmask.word 0x9D6 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9D8 "MBDOR236,Message Buffer Data Field Offset Registers" hexmask.word 0x9D8 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9DA "MBDOR237,Message Buffer Data Field Offset Registers" hexmask.word 0x9DA 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9DC "MBDOR238,Message Buffer Data Field Offset Registers" hexmask.word 0x9DC 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9DE "MBDOR239,Message Buffer Data Field Offset Registers" hexmask.word 0x9DE 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9E0 "MBDOR240,Message Buffer Data Field Offset Registers" hexmask.word 0x9E0 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9E2 "MBDOR241,Message Buffer Data Field Offset Registers" hexmask.word 0x9E2 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9E4 "MBDOR242,Message Buffer Data Field Offset Registers" hexmask.word 0x9E4 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9E6 "MBDOR243,Message Buffer Data Field Offset Registers" hexmask.word 0x9E6 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9E8 "MBDOR244,Message Buffer Data Field Offset Registers" hexmask.word 0x9E8 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9EA "MBDOR245,Message Buffer Data Field Offset Registers" hexmask.word 0x9EA 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9EC "MBDOR246,Message Buffer Data Field Offset Registers" hexmask.word 0x9EC 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9EE "MBDOR247,Message Buffer Data Field Offset Registers" hexmask.word 0x9EE 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9F0 "MBDOR248,Message Buffer Data Field Offset Registers" hexmask.word 0x9F0 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9F2 "MBDOR249,Message Buffer Data Field Offset Registers" hexmask.word 0x9F2 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9F4 "MBDOR250,Message Buffer Data Field Offset Registers" hexmask.word 0x9F4 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9F6 "MBDOR251,Message Buffer Data Field Offset Registers" hexmask.word 0x9F6 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9F8 "MBDOR252,Message Buffer Data Field Offset Registers" hexmask.word 0x9F8 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9FA "MBDOR253,Message Buffer Data Field Offset Registers" hexmask.word 0x9FA 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9FC "MBDOR254,Message Buffer Data Field Offset Registers" hexmask.word 0x9FC 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9FE "MBDOR255,Message Buffer Data Field Offset Registers" hexmask.word 0x9FE 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0xA00 "MBDOR256,Message Buffer Data Field Offset Registers" hexmask.word 0xA00 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0xA02 "MBDOR257,Message Buffer Data Field Offset Registers" hexmask.word 0xA02 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0xA04 "MBDOR258,Message Buffer Data Field Offset Registers" hexmask.word 0xA04 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0xA06 "MBDOR259,Message Buffer Data Field Offset Registers" hexmask.word 0xA06 0.--15. 1. "MBDO,Message Buffer Data Field Offset" group.word 0x1210++0xB line.word 0x0 "LEETR0,LRAM ECC Error Test Registers" hexmask.word 0x0 0.--15. 1. "LEETD,LRAM ECC Error Test Data" line.word 0x2 "LEETR1,LRAM ECC Error Test Registers" hexmask.word 0x2 0.--15. 1. "LEETD,LRAM ECC Error Test Data" line.word 0x4 "LEETR2,LRAM ECC Error Test Registers" hexmask.word 0x4 0.--15. 1. "LEETD,LRAM ECC Error Test Data" line.word 0x6 "LEETR3,LRAM ECC Error Test Registers" hexmask.word 0x6 0.--15. 1. "LEETD,LRAM ECC Error Test Data" line.word 0x8 "LEETR4,LRAM ECC Error Test Registers" hexmask.word 0x8 0.--15. 1. "LEETD,LRAM ECC Error Test Data" line.word 0xA "LEETR5,LRAM ECC Error Test Registers" hexmask.word 0xA 0.--15. 1. "LEETD,LRAM ECC Error Test Data" tree.end tree "FLEXRAY_1" base ad:0x71418000 rgroup.word 0x0++0x1 line.word 0x0 "MVR,Module Version Register" hexmask.word.byte 0x0 8.--15. 1. "CHIVER,CHI Version Number" newline hexmask.word.byte 0x0 0.--7. 1. "PEVER,PE Version Number" group.word 0x2++0x1F line.word 0x0 "MCR,Module Configuration Register" bitfld.word 0x0 15. "MEN,Module Enable" "0: Write: only during POC:default config CC disable,1: Write: enable CC" newline bitfld.word 0x0 14. "SBFF,System Bus Failure Freeze" "0: Continue normal operation,1: Transition to Freeze mode" newline bitfld.word 0x0 13. "SCM,Single Channel Device Mode" "0: CC works in Dual-Channel Device mode,1: CC works in Single-Channel Device mode" newline bitfld.word 0x0 12. "CHB,Channel Enable" "0,1" newline bitfld.word 0x0 11. "CHA,Channel Enable" "0,1" newline bitfld.word 0x0 10. "SFFE,Synchronization Frame Filter Enable" "0: Synchronization frame filtering disabled,1: Synchronization frame filtering enabled" newline bitfld.word 0x0 9. "ECCE,ECC Functionality Enable" "0: ECC functionality (injection detection reporting..,1: ECC functionality enabled" newline bitfld.word 0x0 7. "FUM,FIFO Update Mode" "0: FIFOA/FIFOB is updated on writing 1 to..,1: FIFOA/FIFOB) is not updated on writing 1 to.." newline bitfld.word 0x0 6. "FAM,FIFO Address Mode" "0: FIFO Base Address located in Section1.5.2.5:..,1: FIFO Base Address located in Section1.5.2.76:.." newline bitfld.word 0x0 4. "CLKSEL,Protocol Engine Clock Source Select" "0: PE clock source is generated by on-chip crystal..,1: PE clock source is generated by on-chip PLL." newline bitfld.word 0x0 1.--3. "BITRATE,FlexRay Bus Bit Rate" "0: 10.0 Mbit/s,1: 5.0 Mbit/s,2: 2.5 Mbit/s,3: 8.0 Mbit/s,?,?,?,?" line.word 0x2 "SYMBADHR,System Memory Base Address Register" hexmask.word 0x2 0.--15. 1. "SMBA,System Memory Base Address" line.word 0x4 "SYMBADLR,System Memory Base Address Register" hexmask.word 0x4 4.--15. 1. "SMBA,System Memory Base Address" line.word 0x6 "STBSCR,Strobe Signal Control Register" bitfld.word 0x6 15. "WMD,Write Mode" "0: Write to all fields in this register on write..,1: Write to SEL field only on write access." newline hexmask.word.byte 0x6 8.--11. 1. "SEL,Strobe Signal Select" newline bitfld.word 0x6 4. "ENB,Strobe Signal Enable" "0: Strobe signal is disabled and not assigned to..,1: Strobe signal is enabled and assigned to the.." newline bitfld.word 0x6 0.--1. "STBPSEL,Strobe Port Select" "0: Assign selected signal to FR_DBG[0].,1: Assign selected signal to FR_DBG[1].,2: Assign selected signal to FR_DBG[2].,3: Assign selected signal to FR_DBG[3]." line.word 0x8 "STBPCR,Strobe Port Control Register" bitfld.word 0x8 3. "STB3EN,Strobe Port 3 Enable" "0: Strobe port FR_DBG[3] disabled,1: Strobe port FR_DBG[3] enabled" newline bitfld.word 0x8 2. "STB2EN,Strobe Port 2 Enable" "0: Strobe port FR_DBG[2] disabled,1: Strobe port FR_DBG[2] enabled" newline bitfld.word 0x8 1. "STB1EN,Strobe Port 1 Enable" "0: Strobe port FR_DBG[1] disabled,1: Strobe port FR_DBG[1] enabled" newline bitfld.word 0x8 0. "STB0EN,Strobe Port 0 Enable" "0: Strobe port FR_DBG[0] disabled,1: Strobe port FR_DBG[0] enabled" line.word 0xA "MBDSR,Message Buffer Data Size Register" hexmask.word.byte 0xA 8.--14. 1. "MBSEG2DS,Message Buffer Segment 2 Data Size" newline hexmask.word.byte 0xA 0.--6. 1. "MBSEG1DS,Message Buffer Segment 1 Data Size" line.word 0xC "MBSSUTR,Message Buffer Segment Size and Utilization Register" hexmask.word.byte 0xC 8.--15. 1. "LAST_MB_SEG1,Last Message Buffer In Segment 1" newline hexmask.word.byte 0xC 0.--7. 1. "LAST_MB_UTIL,Last Message Buffer Utilized" line.word 0xE "PEDRAR,PE DRAM Access Register" hexmask.word.byte 0xE 12.--15. 1. "INST,PE DRAM Access Instruction" newline hexmask.word 0xE 1.--11. 1. "ADDR,PE DRAM Access Address" newline bitfld.word 0xE 0. "DAD,PE DRAM Access Done" "0: PE DRAM access running,1: PE DRAM access done" line.word 0x10 "PEDRDR,PE DRAM Data Register" hexmask.word 0x10 0.--15. 1. "DATA,Data" line.word 0x12 "POCR,Protocol Operation Control Register" bitfld.word 0x12 15. "WME,Write Mode External Correction" "0: Write to EOC_AP and ERC_AP fields on register..,1: No write to EOC_AP and ERC_AP fields on register.." newline bitfld.word 0x12 10.--11. "EOC_AP,External Offset Correction Application" "0: Do not apply external offset correction value,?,2: Subtract external offset correction value,3: Add external offset correction value" newline bitfld.word 0x12 8.--9. "ERC_AP,External Rate Correction Application" "0: Do not apply external rate correction value,?,2: Subtract external rate correction value,3: Add external rate correction value" newline bitfld.word 0x12 7. "BSY_WMC,Protocol Control Command Write Busy (BSY)" "0,1" newline hexmask.word.byte 0x12 0.--3. 1. "POCCMD,Protocol Control Command" line.word 0x14 "GIFER,Global Interrupt Flag and Enable Register" bitfld.word 0x14 15. "MIF,Module Interrupt Flag" "0: No interrupt flag and related interrupt enable..,1: At least one of the other interrupt flags in.." newline bitfld.word 0x14 14. "PRIF,Protocol Interrupt Flag" "0: No individual protocol interrupt flag and..,1: At least one of the individual protocol.." newline bitfld.word 0x14 13. "CHIF,CHI Interrupt Flag" "0: All CHI error flags are equal to 0 or the CHI..,1: At least one CHI error flag and the CHI error.." newline bitfld.word 0x14 12. "WUPIF,Wakeup Interrupt Flag" "0: No wakeup symbol received on FlexRay bus,1: Wakeup symbol received on FlexRay bus" newline bitfld.word 0x14 11. "FAFBIF,Receive FIFO Channel B Almost Full Interrupt Flag" "0: No such event,1: FIFO B almost full event has occurred" newline bitfld.word 0x14 10. "FAFAIF,Receive FIFO Channel A Almost Full Interrupt Flag" "0: No such event,1: FIFO A almost full event has occurred" newline bitfld.word 0x14 9. "RBIF,Receive Message Buffer Interrupt Flag" "0: None of the individual receive message buffers..,1: At least one individual receive message buffer.." newline bitfld.word 0x14 8. "TBIF,Transmit Message Buffer Interrupt Flag" "0: None of the individual transmit message buffers..,1: At least one individual transmit message buffer.." newline bitfld.word 0x14 7. "MIE,Module Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" newline bitfld.word 0x14 6. "PRIE,Protocol Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" newline bitfld.word 0x14 5. "CHIE,CHI Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" newline bitfld.word 0x14 4. "WUPIE,Wakeup Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" newline bitfld.word 0x14 3. "FAFBIE,Receive FIFO Channel B Almost Full Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" newline bitfld.word 0x14 2. "FAFAIE,Receive FIFO Channel A Almost Full Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" newline bitfld.word 0x14 1. "RBIE,Receive Message Buffer Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" newline bitfld.word 0x14 0. "TBIE,Transmit Message Buffer Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" line.word 0x16 "PIFR0,Protocol Interrupt Flag Register 0" bitfld.word 0x16 15. "FATL_IF,Fatal Protocol Error Interrupt Flag" "0: No such event,1: Fatal protocol error detected" newline bitfld.word 0x16 14. "INTL_IF,Internal Protocol Error Interrupt Flag" "0: No such event,1: Internal protocol error detected" newline bitfld.word 0x16 13. "ILCF_IF,Illegal Protocol Configuration Interrupt Flag" "0: No such event,1: Illegal protocol configuration detected" newline bitfld.word 0x16 12. "CSA_IF,Cold Start Abort Interrupt Flag" "0: No such event,1: Cold start aborted and no more coldstart.." newline bitfld.word 0x16 11. "MRC_IF,Missing Rate Correction Interrupt Flag" "0: No such event,1: Insufficient number of measurements for rate.." newline bitfld.word 0x16 10. "MOC_IF,Missing Offset Correction Interrupt Flag" "0: No such event,1: Insufficient number of measurements for offset.." newline bitfld.word 0x16 9. "CCL_IF,Clock Correction Limit Reached Interrupt Flag" "0: No such event,1: Offset or rate correction limit reached" newline bitfld.word 0x16 8. "MXS_IF,Max Sync Frames Detected Interrupt Flag" "0: No such event,1: More than node_sync_max sync frames detected" newline bitfld.word 0x16 7. "MTX_IF,Media Access Test Symbol Received Interrupt Flag" "0: No such event,1: MTS symbol received" newline bitfld.word 0x16 6. "LTXB_IF,pLatestTx Violation on Channel B Interrupt Flag" "0: No such event,1: pLatestTx violation occurred on channel B" newline bitfld.word 0x16 5. "LTXA_IF,pLatestTx Violation on Channel A Interrupt Flag" "0: No such event,1: pLatestTx violation occurred on channel A" newline bitfld.word 0x16 4. "TBVB_IF,Transmission across boundary on channel B Interrupt Flag" "0: No such event,1: Transmission across boundary violation occurred.." newline bitfld.word 0x16 3. "TBVA_IF,Transmission across boundary on channel A Interrupt Flag" "0: No such event,1: Transmission across boundary violation occurred.." newline bitfld.word 0x16 2. "TI2_IF,Timer 2 Expired Interrupt Flag" "0: No such event,1: Timer 2 has reached its time limit" newline bitfld.word 0x16 1. "TI1_IF,Timer 1 Expired Interrupt Flag" "0: No such event,1: Timer 1 has reached its time limit" newline bitfld.word 0x16 0. "CYS_IF,Cycle Start Interrupt Flag" "0: No such event,1: Communication cycle started" line.word 0x18 "PIFR1,Protocol Interrupt Flag Register 1" bitfld.word 0x18 15. "EMC_IF,Error Mode Changed Interrupt Flag" "0: No such event,1: ERRMODE field changed" newline bitfld.word 0x18 14. "IPC_IF,Illegal Protocol Control Command Interrupt Flag" "0: No such event,1: Illegal protocol control command detected" newline bitfld.word 0x18 13. "PECF_IF,Protocol Engine Communication Failure Interrupt Flag" "0: No such event,1: Protocol Engine Communication Failure detected" newline bitfld.word 0x18 12. "PSC_IF,Protocol State Changed Interrupt Flag" "0: No such event,1: Protocol state changed" newline bitfld.word 0x18 11. "SSI3_IF,Slot Status Counter Incremented Interrupt Flag" "0: No such event,1: The corresponding slot status counter has.." newline bitfld.word 0x18 10. "SSI2_IF,Slot Status Counter Incremented Interrupt Flag" "0: No such event,1: The corresponding slot status counter has.." newline bitfld.word 0x18 9. "SSI1_IF,Slot Status Counter Incremented Interrupt Flag" "0: No such event,1: The corresponding slot status counter has.." newline bitfld.word 0x18 8. "SSI0_IF,Slot Status Counter Incremented Interrupt Flag" "0: No such event,1: The corresponding slot status counter has.." newline bitfld.word 0x18 5. "EVT_IF,Even Cycle Table Written Interrupt Flag" "0: No such event,1: Sync frame measurement table written" newline bitfld.word 0x18 4. "ODT_IF,Odd Cycle Table Written Interrupt Flag" "0: No such event,1: Sync frame measurement table written" line.word 0x1A "PIER0,Protocol Interrupt Enable Register 0" bitfld.word 0x1A 15. "FATL_IE,Fatal Protocol Error Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 14. "INTL_IE,Internal Protocol Error Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 13. "ILCF_IE,Illegal Protocol Configuration Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 12. "CSA_IE,Cold Start Abort Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 11. "MRC_IE,Missing Rate Correction Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 10. "MOC_IE,Missing Offset Correction Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 9. "CCL_IE,Clock Correction Limit Reached Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 8. "MXS_IE,Max Sync Frames Detected Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 7. "MTX_IE,Media Access Test Symbol Received Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 6. "LTXB_IE,pLatestTx Violation on Channel B Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 5. "LTXA_IE,pLatestTx Violation on Channel A Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 4. "TBVB_IE,Transmission across boundary on channel B Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 3. "TBVA_IE,Transmission across boundary on channel A Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 2. "TI2_IE,Timer 2 Expired Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 1. "TI1_IE,Timer 1 Expired Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1A 0. "CYS_IE,Cycle Start Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" line.word 0x1C "PIER1,Protocol Interrupt Enable Register 1" bitfld.word 0x1C 15. "EMC_IE,Error Mode Changed Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1C 14. "IPC_IE,Illegal Protocol Control Command Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1C 13. "PECF_IE,Protocol Engine Communication Failure Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1C 12. "PSC_IE,Protocol State Changed Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1C 11. "SSI3_IE,Slot Status Counter Incremented Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1C 10. "SSI2_IE,Slot Status Counter Incremented Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1C 9. "SSI1_IE,Slot Status Counter Incremented Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1C 8. "SSI0_IE,Slot Status Counter Incremented Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1C 5. "EVT_IE,Even Cycle Table Written Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" newline bitfld.word 0x1C 4. "ODT_IE,Odd Cycle Table Written Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled" line.word 0x1E "CHIERFR,CHI Error Flag Register" bitfld.word 0x1E 15. "FRLB_EF,Frame Lost Channel B Error Flag" "0: No such event,1: Frame lost on channel B detected" newline bitfld.word 0x1E 14. "FRLA_EF,Frame Lost Channel A Error Flag" "0: No such error,1: Frame lost on channel A detected" newline bitfld.word 0x1E 13. "PCMI_EF,Protocol Command Ignored Error Flag" "0: No such error,1: POC command ignored" newline bitfld.word 0x1E 12. "FOVB_EF,Receive FIFO Overrun Channel B Error Flag" "0: No such error,1: FIFO overrun on channel B has been detected" newline bitfld.word 0x1E 11. "FOVA_EF,Receive FIFO Overrun Channel A Error Flag" "0: No such error,1: FIFO overrun on channel B has been detected" newline bitfld.word 0x1E 10. "MBS_EF,Message Buffer Search Error Flag" "0: No such event,1: Search engine active while search start appears.." newline bitfld.word 0x1E 9. "MBU_EF,Message Buffer Utilization Error Flag" "0: No such event,1: Non-utilized message buffer enabled" newline bitfld.word 0x1E 8. "LCK_EF,Lock Error Flag" "0: No such error,1: Lock error detected" newline bitfld.word 0x1E 6. "SBCF_EF,System Bus Communication Failure Error Flag" "0: No such event,1: System bus access not finished in time" newline bitfld.word 0x1E 5. "FID_EF,Frame ID Error Flag" "0: No such error occurred,1: Frame ID error occurred" newline bitfld.word 0x1E 4. "DPL_EF,Dynamic Payload Length Error Flag" "0: No such error occurred,1: Dynamic payload length error occurred" newline bitfld.word 0x1E 3. "SPL_EF,Static Payload Length Error Flag" "0: No such error occurred,1: Static payload length error occurred" newline bitfld.word 0x1E 2. "NML_EF,Network Management Length Error Flag" "0: No such error occurred,1: Network management length error occurred" newline bitfld.word 0x1E 1. "NMF_EF,Network Management Frame Error Flag" "0: No such error occurred,1: Network management frame error occurred" newline bitfld.word 0x1E 0. "ILSA_EF,Illegal System Bus Address Error Flag" "0: No such event,1: System bus illegal address access" rgroup.word 0x22++0x7 line.word 0x0 "MBIVEC,Message Buffer Interrupt Vector Register" hexmask.word.byte 0x0 8.--15. 1. "TBIVEC,Transmit Buffer Interrupt Vector" newline hexmask.word.byte 0x0 0.--7. 1. "RBIVEC,Receive Buffer Interrupt Vector" line.word 0x2 "CASERCR,Channel A Status Error Counter Register" hexmask.word 0x2 0.--15. 1. "CHAERSCNT,Channel Status Error Counter" line.word 0x4 "CBSERCR,Channel B Status Error Counter Register" hexmask.word 0x4 0.--15. 1. "CHBERSCNT,Channel Status Error Counter" line.word 0x6 "PSR0,Protocol Status Register 0" bitfld.word 0x6 14.--15. "ERRMODE,Error Mode" "0: ACTIVE,1: PASSIVE,2: COMM_HALT,?" newline bitfld.word 0x6 12.--13. "SLOTMODE,Slot Mode" "0: SINGLE,1: ALL_PENDING,2: ALL,?" newline bitfld.word 0x6 8.--10. "PROTSTATE,Protocol State" "0: POC:default config,1: POC:config,2: POC:wakeup,3: POC:ready,4: POC:normal passive,5: POC:normal active,6: POC:halt,7: POC:startup" newline hexmask.word.byte 0x6 4.--7. 1. "STARTUPSTATE,Startup State" newline bitfld.word 0x6 0.--2. "WAKEUPSTATUS,Wakeup Status" "0: UNDEFINED,1: RECEIVED_HEADER,2: RECEIVED_WUP,3: COLLISION_HEADER,4: COLLISION_WUP,5: COLLISION_UNKNOWN,6: TRANSMITTED,?" group.word 0x2A++0x1 line.word 0x0 "PSR1,Protocol Status Register 1" bitfld.word 0x0 15. "CSAA,Cold Start Attempt Aborted Flag" "0: No such event,1: Cold start attempt aborted" newline bitfld.word 0x0 14. "CSP,Leading Cold Start Path" "0: No such event,1: POC:normal active reached from POC:startup state.." newline hexmask.word.byte 0x0 8.--12. 1. "REMCSAT,Remaining Coldstart Attempts" newline bitfld.word 0x0 7. "CPN,Leading Cold Start Path Noiseprotocol-related variable: vPOC!ColdstartNoise." "0: No such event,1: POC:normal active state was reached from.." newline bitfld.word 0x0 6. "HHR,Host Halt Request Pending" "0: No such event,1: HALT command received" newline bitfld.word 0x0 5. "FRZ,Freeze Occurred" "0: No such event,1: Immediate halt due to FREEZE or internal error.." newline hexmask.word.byte 0x0 0.--4. 1. "APTAC,Allow Passive to Active Counter" rgroup.word 0x2C++0x1 line.word 0x0 "PSR2,Protocol Status Register 2" bitfld.word 0x0 15. "NBVB,NIT Boundary Violation on Channel B" "0: No such event,1: Media activity at boundaries detected" newline bitfld.word 0x0 14. "NSEB,NIT Syntax Error on Channel B" "0: No such event,1: Syntax error detected" newline bitfld.word 0x0 13. "STCB,Symbol Window Transmit Conflict on Channel B" "0: No such event,1: Transmission conflict detected" newline bitfld.word 0x0 12. "SBVB,Symbol Window Boundary Violation on Channel B" "0: No such event,1: Media activity at boundaries detected" newline bitfld.word 0x0 11. "SSEB,Symbol Window Syntax Error on Channel B" "0: No such event,1: Syntax error detected" newline bitfld.word 0x0 10. "MTB,Media Access Test Symbol MTS Received on Channel B" "0: No such event,1: MTS symbol received" newline bitfld.word 0x0 9. "NBVA,NIT Boundary Violation on Channel A" "0: No such event,1: Media activity at boundaries detected" newline bitfld.word 0x0 8. "NSEA,NIT Syntax Error on Channel A" "0: No such event,1: Syntax error detected" newline bitfld.word 0x0 7. "STCA,Symbol Window Transmit Conflict on Channel A" "0: No such event,1: Transmission conflict detected" newline bitfld.word 0x0 6. "SBVA,Symbol Window Boundary Violation on Channel A" "0: No such event,1: Media activity at boundaries detected" newline bitfld.word 0x0 5. "SSEA,Symbol Window Syntax Error on Channel A" "0: No such event,1: Syntax error detected" newline bitfld.word 0x0 4. "MTA,Media Access Test Symbol MTS Received on Channel A" "0: No such event,1: MTS symbol received" newline hexmask.word.byte 0x0 0.--3. 1. "CKCORFCNT,Clock Correction Failed Counter" group.word 0x2E++0x1 line.word 0x0 "PSR3,Protocol Status Register 3" bitfld.word 0x0 13. "WUB,Wakeup Symbol Received on Channel B" "0: No wakeup symbol received,1: Wakeup symbol received" newline bitfld.word 0x0 12. "ABVB,Aggregated Boundary Violation on Channel B" "0: No boundary violation detected,1: Boundary violation detected" newline bitfld.word 0x0 11. "AACB,Aggregated Additional Communication on Channel B" "0: No additional communication detected,1: Additional communication detected" newline bitfld.word 0x0 10. "ACEB,Aggregated Content Error on Channel B" "0: No content error detected,1: Content error detected" newline bitfld.word 0x0 9. "ASEB,Aggregated Syntax Error on Channel B" "0: No syntax error detected,1: Syntax errors detected" newline bitfld.word 0x0 8. "AVFB,Aggregated Valid Frame on Channel B" "0: No syntactically valid frames received,1: At least one syntactically valid frame received" newline bitfld.word 0x0 5. "WUA,Wakeup Symbol Received on Channel A" "0: No wakeup symbol received,1: Wakeup symbol received" newline bitfld.word 0x0 4. "ABVA,Aggregated Boundary Violation on Channel A" "0: No boundary violation detected,1: Boundary violation detected" newline bitfld.word 0x0 3. "AACA,Aggregated Additional Communication on Channel A" "0: No additional communication detected,1: Additional communication detected" newline bitfld.word 0x0 2. "ACEA,Aggregated Content Error on Channel A" "0: No content error detected,1: Content error detected" newline bitfld.word 0x0 1. "ASEA,Aggregated Syntax Error on Channel A" "0: No syntax error detected,1: Syntax errors detected" newline bitfld.word 0x0 0. "AVFA,Aggregated Valid Frame on Channel A" "0: No syntactically valid frames received,1: At least one syntactically valid frame received" rgroup.word 0x30++0xD line.word 0x0 "MTCTR,Macrotick Counter Register" hexmask.word 0x0 0.--13. 1. "MTCT,Macrotick Counter" line.word 0x2 "CYCTR,Cycle Counter Register" hexmask.word.byte 0x2 0.--5. 1. "CYCCNT,Cycle Counter" line.word 0x4 "SLTCTAR,Slot Counter Channel A Register" hexmask.word 0x4 0.--10. 1. "SLOTCNTA,Slot Counter Value for Channel A" line.word 0x6 "SLTCTBR,Slot Counter Channel B Register" hexmask.word 0x6 0.--10. 1. "SLOTCNTB,Slot Counter Value for Channel B" line.word 0x8 "RTCORVR,Rate Correction Value Register" hexmask.word 0x8 0.--15. 1. "RATECORR,Rate Correction Value" line.word 0xA "OFCORVR,Offset Correction Value Register" hexmask.word 0xA 0.--15. 1. "OFFSETCORR,Offset Correction Value" line.word 0xC "CIFR,Combined Interrupt Flag Register" bitfld.word 0xC 7. "MIF,Module Interrupt Flag" "0: No interrupt source has its interrupt flag..,1: At least one interrupt source has its interrupt.." newline bitfld.word 0xC 6. "PRIF,Protocol Interrupt Flag" "0: All individual protocol interrupt flags are..,1: At least one of the individual protocol.." newline bitfld.word 0xC 5. "CHIF,CHI Interrupt Flag" "0: All CHI error flags are equal to 0,1: At least one CHI error flag is equal to 1" newline bitfld.word 0xC 4. "WUPIF,Wakeup Interrupt Flag" "0,1" newline bitfld.word 0xC 3. "FAFBIF,Receive FIFO Channel B Almost Full Interrupt Flag" "0,1" newline bitfld.word 0xC 2. "FAFAIF,Receive FIFO Channel A Almost Full Interrupt Flag" "0,1" newline bitfld.word 0xC 1. "RBIF,Receive Message Buffer Interrupt Flag" "0: None of the individual receive message buffers..,1: At least one individual receive message buffers.." newline bitfld.word 0xC 0. "TBIF,Transmit Message Buffer Interrupt Flag" "0: None of the individual transmit message buffers..,1: At least one individual transmit message buffers.." group.word 0x3E++0x1 line.word 0x0 "SYMATOR,System Memory Access Timeout Register" hexmask.word.byte 0x0 0.--7. 1. "TIMEOUT,System Memory Access Timeout" rgroup.word 0x40++0x1 line.word 0x0 "SFCNTR,Sync Frame Counter Register" hexmask.word.byte 0x0 12.--15. 1. "SFEVB,Sync Frames Channel B even cycle" newline hexmask.word.byte 0x0 8.--11. 1. "SFEVA,Sync Frames Channel A even cycle" newline hexmask.word.byte 0x0 4.--7. 1. "SFODB,Sync Frames Channel B odd cycle" newline hexmask.word.byte 0x0 0.--3. 1. "SFODA,Sync Frames Channel A odd cycle" group.word 0x42++0x9 line.word 0x0 "SFTOR,Sync Frame Table Offset Register" hexmask.word 0x0 1.--15. 1. "SFT_OFFSET,Sync Frame Table Offset" line.word 0x2 "SFTCCSR,Sync Frame Table Configuration. Control. Status Register" bitfld.word 0x2 15. "ELKT,Even Cycle Tables Lock/Unlock Trigger" "0: No effect,1: Triggers lock/unlock of the even cycle tables" newline bitfld.word 0x2 14. "OLKT,Odd Cycle Tables Lock/Unlock Trigger" "0: No effect,1: Triggers lock/unlock of the odd cycle tables" newline hexmask.word.byte 0x2 8.--13. 1. "CYCNUM,Cycle Number" newline bitfld.word 0x2 7. "ELKS,Even Cycle Tables Lock Status" "0: Application has not locked the even cycle tables,1: Application has locked the even cycle tables" newline bitfld.word 0x2 6. "OLKS,Odd Cycle Tables Lock Status" "0: Application has not locked the odd cycle tables,1: Application has locked the odd cycle tables" newline bitfld.word 0x2 5. "EVAL,Even Cycle Tables Valid" "0: Tables are not valid (update is ongoing),1: Tables are valid (consistent)" newline bitfld.word 0x2 4. "OVAL,Odd Cycle Tables Valid" "0: Tables are not valid (update is ongoing),1: Tables are valid (consistent)" newline bitfld.word 0x2 2. "OPT,One Pair Trigger" "0: Write continuously pairs of enabled Sync Frame..,1: Write only one pair of enabled Sync Frame Tables.." newline bitfld.word 0x2 1. "SDVEN,Sync Frame Deviation Table Enable" "0: Do not write Sync Frame Deviation Tables,1: Write Sync Frame Deviation Tables into FlexRay.." newline bitfld.word 0x2 0. "SIDEN,Sync Frame ID Table Enable" "0: Do not write Sync Frame ID Tables,1: Write Sync Frame ID Tables into FlexRay memory.." line.word 0x4 "SFIDRFR,Sync Frame ID Rejection Filter Register" hexmask.word 0x4 0.--9. 1. "SYNFRID,Sync Frame Rejection ID" line.word 0x6 "SFIDAFVR,Sync Frame ID Acceptance Filter Value Register" hexmask.word 0x6 0.--9. 1. "FVAL,Filter Value" line.word 0x8 "SFIDAFMR,Sync Frame ID Acceptance Filter Mask Register" hexmask.word 0x8 0.--9. 1. "FMSK,Filter Mask" rgroup.word 0x4C++0xB line.word 0x0 "NMVR0,Network Management Vector Registers" hexmask.word 0x0 0.--15. 1. "NMVP,Network Management Vector Part" line.word 0x2 "NMVR1,Network Management Vector Registers" hexmask.word 0x2 0.--15. 1. "NMVP,Network Management Vector Part" line.word 0x4 "NMVR2,Network Management Vector Registers" hexmask.word 0x4 0.--15. 1. "NMVP,Network Management Vector Part" line.word 0x6 "NMVR3,Network Management Vector Registers" hexmask.word 0x6 0.--15. 1. "NMVP,Network Management Vector Part" line.word 0x8 "NMVR4,Network Management Vector Registers" hexmask.word 0x8 0.--15. 1. "NMVP,Network Management Vector Part" line.word 0xA "NMVR5,Network Management Vector Registers" hexmask.word 0xA 0.--15. 1. "NMVP,Network Management Vector Part" group.word 0x58++0x9 line.word 0x0 "NMVLR,Network Management Vector Length Register" hexmask.word.byte 0x0 0.--3. 1. "NMVL,Network Management Vector Length" line.word 0x2 "TICCR,Timer Configuration and Control Register" bitfld.word 0x2 13. "T2_CFG,Timer T2 Configuration" "0: T2 is absolute timer.,1: T2 is relative timer." newline bitfld.word 0x2 12. "T2_REP,Timer T2 Repetitive Mode" "0: T2 is non repetitive.,1: T2 is repetitive." newline bitfld.word 0x2 10. "T2SP,Timer T2 Stop" "0: No effect,1: Stop timer T2" newline bitfld.word 0x2 9. "T2TR,Timer T2 Trigger" "0: No effect,1: Start timer T2" newline bitfld.word 0x2 8. "T2ST,Timer T2 State" "0: Timer T2 is idle.,1: Timer T2 is running." newline bitfld.word 0x2 4. "T1_REP,Timer T1 Repetitive Mode" "0: T1 is non repetitive.,1: T1 is repetitive." newline bitfld.word 0x2 2. "T1SP,Timer T1 Stop" "0: No effect,1: Stop timer T1" newline bitfld.word 0x2 1. "T1TR,Timer T1 Trigger" "0: No effect,1: Start timer T1" newline bitfld.word 0x2 0. "T1ST,Timer T1 State" "0: Timer T1 is idle.,1: Timer T1 is running." line.word 0x4 "TI1CYSR,Timer 1 Cycle Set Register" hexmask.word.byte 0x4 8.--13. 1. "T1_CYC_VAL,Timer T1 Cycle Filter Value" newline hexmask.word.byte 0x4 0.--5. 1. "T1_CYC_MSK,Timer T1 Cycle Filter Mask" line.word 0x6 "TI1MTOR,Timer 1 Macrotick Offset Register" hexmask.word 0x6 0.--13. 1. "T1_MTOFFSET,Timer 1 Macrotick Offset" line.word 0x8 "TI2CR0_T2CFG_0,Timer 2 Configuration Register 0" hexmask.word.byte 0x8 8.--13. 1. "T2_CYC_VAL,Timer T2 Cycle Filter Value" newline hexmask.word.byte 0x8 0.--5. 1. "T2_CYC_MSK,Timer T2 Cycle Filter Mask" group.word 0x60++0x3 line.word 0x0 "TI2CR0_T2CFG_1,The content of this register depends on the value of the T2_CFG bit in the Timer Configuration and Control Register (FR_TICCR). For a detailed description of timer T2. refer to Section1.6.17.2: Absolute/relative timer T2." hexmask.word 0x0 0.--15. 1. "T2_MTCNT,Timer T2 Macrotick High Word" line.word 0x2 "TI2CR1_T2CFG_0,Timer 2 Configuration Register 1" hexmask.word 0x2 0.--13. 1. "T2_MTOFFSET,Timer T2 Macrotick Offset" group.word 0x62++0x5 line.word 0x0 "TI2CR1_T2CFG_1,The content of this register depends on the value of the T2_CFG bit in the Timer Configuration and Control Register (FR_TICCR). For a detailed description of timer T2. refer to Section1.6.17.2: Absolute/relative timer T2." hexmask.word 0x0 0.--15. 1. "T2_MTCNT,Timer T2 Macrotick Low Word" line.word 0x2 "SSSR,Slot Status Selection Register" bitfld.word 0x2 15. "WMD,Write Mode" "0: Write to all fields in this register on write..,1: Write to SEL field only on write access" newline bitfld.word 0x2 12.--13. "SEL,Selector" "0: Select FR_SSSR0,1: Select FR_SSSR1,2: Select FR_SSSR2,3: Select FR_SSSR3" newline hexmask.word 0x2 0.--10. 1. "SLOTNUMBER,Slot Number" line.word 0x4 "SSCCR,Slot Status Counter Condition Register" bitfld.word 0x4 15. "WMD,Write Mode" "0: Write to all fields in this register on write..,1: Write to SEL field only on write access." newline bitfld.word 0x4 12.--13. "SEL,Selector" "0: select FR_SSCCR0,1: select FR_SSCCR1,2: select FR_SSCCR2,3: select FR_SSCCR3" newline bitfld.word 0x4 9.--10. "CNTCFG,Counter Configuration" "0: Increment by 1 if condition is fulfilled on..,1: Increment by 1 if condition is fulfilled on..,2: Increment by 1 if condition is fulfilled on at..,3: Increment by 2 if condition is fulfilled on both.." newline bitfld.word 0x4 8. "MCY,Multi Cycle Selection" "0: The Slot Status Counter provides information for..,1: The Slot Status Counter accumulates over.." newline bitfld.word 0x4 7. "VFR,Valid Frame Restriction" "0: The counter is not restricted to valid frames..,1: The counter is restricted to valid frames only." newline bitfld.word 0x4 6. "SYF,Sync Frame Restriction" "0: The counter is not restricted with respect to..,1: The counter is restricted to frames with the.." newline bitfld.word 0x4 5. "NUF," "0,1" newline bitfld.word 0x4 4. "SUF,Startup Frame Restriction" "0: The counter is not restricted with respect to..,1: The counter is restricted to received frames.." newline hexmask.word.byte 0x4 0.--3. 1. "STATUSMASK,Slot Status Mask" rgroup.word 0x68++0x17 line.word 0x0 "SSR0,Slot Status Registers" bitfld.word 0x0 15. "VFB,Valid Frame on Channel B" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x0 14. "SYB,Sync Frame Indicator Channel B" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x0 13. "NFB,Null Frame Indicator Channel B" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x0 12. "SUB,Startup Frame Indicator Channel B" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x0 11. "SEB,Syntax Error on Channel B" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x0 10. "CEB,Content Error on Channel B" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x0 9. "BVB,Boundary Violation on Channel B" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x0 8. "TCB,Transmission Conflict on Channel B" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" newline bitfld.word 0x0 7. "VFA,Valid Frame on Channel A" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x0 6. "SYA,Sync Frame Indicator Channel A" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x0 5. "NFA,Null Frame Indicator Channel A" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x0 4. "SUA,Startup Frame Indicator Channel A" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x0 3. "SEA,Syntax Error on Channel A" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x0 2. "CEA,Content Error on Channel A" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x0 1. "BVA,Boundary Violation on Channel A" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x0 0. "TCA,Transmission Conflict on Channel A" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" line.word 0x2 "SSR1,Slot Status Registers" bitfld.word 0x2 15. "VFB,Valid Frame on Channel B" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x2 14. "SYB,Sync Frame Indicator Channel B" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x2 13. "NFB,Null Frame Indicator Channel B" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x2 12. "SUB,Startup Frame Indicator Channel B" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x2 11. "SEB,Syntax Error on Channel B" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x2 10. "CEB,Content Error on Channel B" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x2 9. "BVB,Boundary Violation on Channel B" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x2 8. "TCB,Transmission Conflict on Channel B" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" newline bitfld.word 0x2 7. "VFA,Valid Frame on Channel A" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x2 6. "SYA,Sync Frame Indicator Channel A" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x2 5. "NFA,Null Frame Indicator Channel A" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x2 4. "SUA,Startup Frame Indicator Channel A" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x2 3. "SEA,Syntax Error on Channel A" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x2 2. "CEA,Content Error on Channel A" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x2 1. "BVA,Boundary Violation on Channel A" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x2 0. "TCA,Transmission Conflict on Channel A" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" line.word 0x4 "SSR2,Slot Status Registers" bitfld.word 0x4 15. "VFB,Valid Frame on Channel B" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x4 14. "SYB,Sync Frame Indicator Channel B" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x4 13. "NFB,Null Frame Indicator Channel B" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x4 12. "SUB,Startup Frame Indicator Channel B" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x4 11. "SEB,Syntax Error on Channel B" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x4 10. "CEB,Content Error on Channel B" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x4 9. "BVB,Boundary Violation on Channel B" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x4 8. "TCB,Transmission Conflict on Channel B" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" newline bitfld.word 0x4 7. "VFA,Valid Frame on Channel A" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x4 6. "SYA,Sync Frame Indicator Channel A" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x4 5. "NFA,Null Frame Indicator Channel A" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x4 4. "SUA,Startup Frame Indicator Channel A" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x4 3. "SEA,Syntax Error on Channel A" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x4 2. "CEA,Content Error on Channel A" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x4 1. "BVA,Boundary Violation on Channel A" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x4 0. "TCA,Transmission Conflict on Channel A" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" line.word 0x6 "SSR3,Slot Status Registers" bitfld.word 0x6 15. "VFB,Valid Frame on Channel B" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x6 14. "SYB,Sync Frame Indicator Channel B" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x6 13. "NFB,Null Frame Indicator Channel B" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x6 12. "SUB,Startup Frame Indicator Channel B" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x6 11. "SEB,Syntax Error on Channel B" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x6 10. "CEB,Content Error on Channel B" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x6 9. "BVB,Boundary Violation on Channel B" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x6 8. "TCB,Transmission Conflict on Channel B" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" newline bitfld.word 0x6 7. "VFA,Valid Frame on Channel A" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x6 6. "SYA,Sync Frame Indicator Channel A" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x6 5. "NFA,Null Frame Indicator Channel A" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x6 4. "SUA,Startup Frame Indicator Channel A" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x6 3. "SEA,Syntax Error on Channel A" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x6 2. "CEA,Content Error on Channel A" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x6 1. "BVA,Boundary Violation on Channel A" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x6 0. "TCA,Transmission Conflict on Channel A" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" line.word 0x8 "SSR4,Slot Status Registers" bitfld.word 0x8 15. "VFB,Valid Frame on Channel B" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x8 14. "SYB,Sync Frame Indicator Channel B" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x8 13. "NFB,Null Frame Indicator Channel B" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x8 12. "SUB,Startup Frame Indicator Channel B" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x8 11. "SEB,Syntax Error on Channel B" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x8 10. "CEB,Content Error on Channel B" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x8 9. "BVB,Boundary Violation on Channel B" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x8 8. "TCB,Transmission Conflict on Channel B" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" newline bitfld.word 0x8 7. "VFA,Valid Frame on Channel A" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x8 6. "SYA,Sync Frame Indicator Channel A" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x8 5. "NFA,Null Frame Indicator Channel A" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x8 4. "SUA,Startup Frame Indicator Channel A" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x8 3. "SEA,Syntax Error on Channel A" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x8 2. "CEA,Content Error on Channel A" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x8 1. "BVA,Boundary Violation on Channel A" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x8 0. "TCA,Transmission Conflict on Channel A" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" line.word 0xA "SSR5,Slot Status Registers" bitfld.word 0xA 15. "VFB,Valid Frame on Channel B" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0xA 14. "SYB,Sync Frame Indicator Channel B" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0xA 13. "NFB,Null Frame Indicator Channel B" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0xA 12. "SUB,Startup Frame Indicator Channel B" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0xA 11. "SEB,Syntax Error on Channel B" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0xA 10. "CEB,Content Error on Channel B" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0xA 9. "BVB,Boundary Violation on Channel B" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0xA 8. "TCB,Transmission Conflict on Channel B" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" newline bitfld.word 0xA 7. "VFA,Valid Frame on Channel A" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0xA 6. "SYA,Sync Frame Indicator Channel A" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0xA 5. "NFA,Null Frame Indicator Channel A" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0xA 4. "SUA,Startup Frame Indicator Channel A" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0xA 3. "SEA,Syntax Error on Channel A" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0xA 2. "CEA,Content Error on Channel A" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0xA 1. "BVA,Boundary Violation on Channel A" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0xA 0. "TCA,Transmission Conflict on Channel A" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" line.word 0xC "SSR6,Slot Status Registers" bitfld.word 0xC 15. "VFB,Valid Frame on Channel B" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0xC 14. "SYB,Sync Frame Indicator Channel B" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0xC 13. "NFB,Null Frame Indicator Channel B" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0xC 12. "SUB,Startup Frame Indicator Channel B" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0xC 11. "SEB,Syntax Error on Channel B" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0xC 10. "CEB,Content Error on Channel B" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0xC 9. "BVB,Boundary Violation on Channel B" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0xC 8. "TCB,Transmission Conflict on Channel B" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" newline bitfld.word 0xC 7. "VFA,Valid Frame on Channel A" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0xC 6. "SYA,Sync Frame Indicator Channel A" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0xC 5. "NFA,Null Frame Indicator Channel A" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0xC 4. "SUA,Startup Frame Indicator Channel A" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0xC 3. "SEA,Syntax Error on Channel A" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0xC 2. "CEA,Content Error on Channel A" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0xC 1. "BVA,Boundary Violation on Channel A" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0xC 0. "TCA,Transmission Conflict on Channel A" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" line.word 0xE "SSR7,Slot Status Registers" bitfld.word 0xE 15. "VFB,Valid Frame on Channel B" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0xE 14. "SYB,Sync Frame Indicator Channel B" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0xE 13. "NFB,Null Frame Indicator Channel B" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0xE 12. "SUB,Startup Frame Indicator Channel B" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0xE 11. "SEB,Syntax Error on Channel B" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0xE 10. "CEB,Content Error on Channel B" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0xE 9. "BVB,Boundary Violation on Channel B" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0xE 8. "TCB,Transmission Conflict on Channel B" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" newline bitfld.word 0xE 7. "VFA,Valid Frame on Channel A" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0xE 6. "SYA,Sync Frame Indicator Channel A" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0xE 5. "NFA,Null Frame Indicator Channel A" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0xE 4. "SUA,Startup Frame Indicator Channel A" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0xE 3. "SEA,Syntax Error on Channel A" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0xE 2. "CEA,Content Error on Channel A" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0xE 1. "BVA,Boundary Violation on Channel A" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0xE 0. "TCA,Transmission Conflict on Channel A" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" line.word 0x10 "SSCR0,Slot Status Counter Registers" hexmask.word 0x10 0.--15. 1. "SLOTSTATUSCNT,Slot Status Counter" line.word 0x12 "SSCR1,Slot Status Counter Registers" hexmask.word 0x12 0.--15. 1. "SLOTSTATUSCNT,Slot Status Counter" line.word 0x14 "SSCR2,Slot Status Counter Registers" hexmask.word 0x14 0.--15. 1. "SLOTSTATUSCNT,Slot Status Counter" line.word 0x16 "SSCR3,Slot Status Counter Registers" hexmask.word 0x16 0.--15. 1. "SLOTSTATUSCNT,Slot Status Counter" group.word 0x80++0xB line.word 0x0 "MTSACFR,MTS A Configuration Register" bitfld.word 0x0 15. "MTE,Media Access Test Symbol Transmission Enable" "0: MTS transmission disabled,1: MTS transmission enabled" newline hexmask.word.byte 0x0 8.--13. 1. "CYCCNTMSK,Cycle Counter Mask" newline hexmask.word.byte 0x0 0.--5. 1. "CYCCNTVAL,Cycle Counter Value" line.word 0x2 "MTSBCFR,MTS B Configuration Register" bitfld.word 0x2 15. "MTE,Media Access Test Symbol Transmission Enable" "0: MTS transmission disabled,1: MTS transmission enabled" newline hexmask.word.byte 0x2 8.--13. 1. "CYCCNTMSK,Cycle Counter Mask" newline hexmask.word.byte 0x2 0.--5. 1. "CYCCNTVAL,Cycle Counter Value" line.word 0x4 "RSBIR,Receive Shadow Buffer Index Register" bitfld.word 0x4 15. "WMD,Write Mode" "0: Update SEL and RSBIDX field on register write,1: Update only SEL field on register write" newline bitfld.word 0x4 12.--13. "SEL,Selector" "0: FR_RSBIR_A1: receive shadow buffer index..,1: FR_RSBIR_A2: receive shadow buffer index..,2: FR_RSBIR_B1: receive shadow buffer index..,3: FR_RSBIR_B2: receive shadow buffer index.." newline hexmask.word 0x4 0.--8. 1. "RSBIDXA1_RSBIDXA2_RSBIDXB1_RSBIDXB2,Receive Shadow Buffer Index" line.word 0x6 "RFWMSR,Receive FIFO Watermark and Selection Register" hexmask.word.byte 0x6 8.--15. 1. "WMA_WMB,Watermark" newline bitfld.word 0x6 0. "SEL,Select" "0: Receiver FIFO for channel A selected,1: Receiver FIFO for channel B selected" line.word 0x8 "RFSIR,Receive FIFO Start Index Register" hexmask.word 0x8 0.--9. 1. "SIDXA_SIDXB,Start Index" line.word 0xA "RFDSR,Receive FIFO Depth and Size Register" hexmask.word.byte 0xA 8.--15. 1. "FIFO_DEPTHA_FIFO_DEPTHB,FIFO Depth" newline hexmask.word.byte 0xA 0.--6. 1. "ENTRY_SIZEA_ENTRY_SIZEB,Entry Size" rgroup.word 0x8C++0x3 line.word 0x0 "RFARIR,Receive FIFO A Read Index Register" hexmask.word 0x0 0.--9. 1. "RDIDX,Read Index" line.word 0x2 "RFBRIR,Receive FIFO B Read Index Register" hexmask.word 0x2 0.--9. 1. "RDIDX,Read Index" group.word 0x90++0xB line.word 0x0 "RFMIDAFVR,Receive FIFO Message ID Acceptance Filter Value Register" hexmask.word 0x0 0.--15. 1. "MIDAFVALA_MIDAFVALB,Message ID Acceptance Filter Value" line.word 0x2 "RFMIDAFMR,Receive FIFO Message ID Acceptance Filter Mask Register" hexmask.word 0x2 0.--15. 1. "MIDAFMSKA_MIDAFMSKB,Message ID Acceptance Filter Mask" line.word 0x4 "RFFIDRFVR,Receive FIFO Frame ID Rejection Filter Value Register" hexmask.word 0x4 0.--10. 1. "FIDRFVALA_FIDRFVALB,Frame ID Rejection Filter Value" line.word 0x6 "RFFIDRFMR,Receive FIFO Frame ID Rejection Filter Mask Register" hexmask.word 0x6 0.--10. 1. "FIDRFMSKA_FIDRFMSKB,Frame ID Rejection Filter Mask" line.word 0x8 "RFRFCFR,Receive FIFO Range Filter Configuration Register" bitfld.word 0x8 15. "WMD,Write Mode" "0: Write to all fields in this register on write..,1: Write to SEL and IBD field only on write access" newline bitfld.word 0x8 14. "IBD,Interval Boundary" "0: Program lower interval boundary,1: Program upper interval boundary" newline bitfld.word 0x8 12.--13. "SEL,Filter Selector" "0: Select frame ID range filter 0,1: Select frame ID range filter 1,2: Select frame ID range filter 2,3: Select frame ID range filter 3" newline hexmask.word 0x8 0.--10. 1. "SIDA_SIDB,Slot ID" line.word 0xA "RFRFCTR,Receive FIFO Range Filter Control Register" bitfld.word 0xA 11. "F3MD,Range Filter 3 Mode" "0: Range filter 3 runs as acceptance filter,1: Range filter 3 runs as rejection filter" newline bitfld.word 0xA 10. "F2MD,Range Filter 2 Mode" "0: Range filter 2 runs as acceptance filter,1: Range filter 2 runs as rejection filter" newline bitfld.word 0xA 9. "F1MD,Range Filter 1 Mode" "0: Range filter 1 runs as acceptance filter,1: Range filter 1 runs as rejection filter" newline bitfld.word 0xA 8. "F0MD,Range Filter 0 Mode" "0: Range filter 0 runs as acceptance filter,1: Range filter 0 runs as rejection filter" newline bitfld.word 0xA 3. "F3EN,Range Filter 3 Enable" "0: Range filter 3 disabled,1: Range filter 3 enabled" newline bitfld.word 0xA 2. "F2EN,Range Filter 2 Enable" "0: Range filter 2 disabled,1: Range filter 2 enabled" newline bitfld.word 0xA 1. "F1EN,Range Filter 1 Enable" "0: Range filter 1 disabled,1: Range filter 1 enabled" newline bitfld.word 0xA 0. "F0EN,Range Filter 0 Enable" "0: Range filter 0 disabled,1: Range filter 0 enabled" rgroup.word 0x9C++0x3 line.word 0x0 "LDTXSLAR,Last Dynamic Transmit Slot Channel A Register" hexmask.word 0x0 0.--10. 1. "LDYNTXSLOTA,Last Dynamic Transmission Slot Channel A" line.word 0x2 "LDTXSLBR,Last Dynamic Transmit Slot Channel B Register" hexmask.word 0x2 0.--10. 1. "LDYNTXSLOTB,Last Dynamic Transmission Slot Channel B" group.word 0xA0++0x3D line.word 0x0 "PCR0,Protocol Configuration Register 0" hexmask.word.byte 0x0 10.--15. 1. "ACTION_POINT_OFFSET,gdActionPointOffset - 1" newline hexmask.word 0x0 0.--9. 1. "STATIC_SLOT_LENGTH,gdStaticSlot" line.word 0x2 "PCR1,Protocol Configuration Register 1" hexmask.word 0x2 0.--13. 1. "MACRO_AFTER_FIRST_STATIC_SLOT,gMacroPerCycle - gdStaticSlot" line.word 0x4 "PCR2,Protocol Configuration Register 2" hexmask.word.byte 0x4 10.--15. 1. "MINISLOT_AFTER_ACTION_POINT,gdMinislot - gdMinislotActionPointOffset - 1" newline hexmask.word 0x4 0.--9. 1. "NUMBER_OF_STATIC_SLOTS,gNumberOfStaticSlots" line.word 0x6 "PCR3,Protocol Configuration Register 3" hexmask.word.byte 0x6 10.--15. 1. "WAKEUP_SYMBOL_RX_LOW,gdWakeupSymbolRxLow" newline hexmask.word.byte 0x6 5.--9. 1. "MINISLOT_ACTION_POINT_OFFSET,gdMinislotActionPointOffset - 1" newline hexmask.word.byte 0x6 0.--4. 1. "COLDSTART_ATTEMPTS,gColdstartAttempts" line.word 0x8 "PCR4,Protocol Configuration Register 4" hexmask.word.byte 0x8 9.--15. 1. "CAS_RX_LOW_MAX,gdCASRxLowMax - 1" newline hexmask.word 0x8 0.--8. 1. "WAKEUP_SYMBOL_RX_WINDOW,gdWakeupSymbolRxWindow" line.word 0xA "PCR5,Protocol Configuration Register 5" hexmask.word.byte 0xA 12.--15. 1. "TSS_TRANSMITTER,gdTSSTransmitter" newline hexmask.word.byte 0xA 6.--11. 1. "WAKEUP_SYMBOL_TX_LOW,gdWakeupSymbolTxLow" newline hexmask.word.byte 0xA 0.--5. 1. "WAKEUP_SYMBOL_RX_IDLE,gdWakeupSymbolRxIdle" line.word 0xC "PCR6,Protocol Configuration Register 6" hexmask.word.byte 0xC 7.--14. 1. "SYMBOL_WINDOW_AFTER_ACTION_POINT,gdSymbolWindow - gdActionPointOffset - 0x1:" newline hexmask.word.byte 0xC 0.--6. 1. "MACRO_INITIAL_OFFSET_A,pMacroInitialOffset[A]" line.word 0xE "PCR7,Protocol Configuration Register 7" hexmask.word 0xE 7.--15. 1. "DECODING_CORRECTION_B,pDecodingCorrection + pDelayCompensation[B] + 2" newline hexmask.word.byte 0xE 0.--6. 1. "MICRO_PER_MACRO_NOM_HALF,round(pMicroPerMacroNom / 2)" line.word 0x10 "PCR8,Protocol Configuration Register 8" hexmask.word.byte 0x10 12.--15. 1. "MAX_WITHOUT_CLOCK_CORRECTION_FATAL,gMaxWithoutClockCorrectionFatal" newline hexmask.word.byte 0x10 8.--11. 1. "MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE,gMaxWithoutClockCorrectionPassive" newline hexmask.word.byte 0x10 0.--7. 1. "WAKEUP_SYMBOL_TX_IDLE,gdWakeupSymbolTxIdle" line.word 0x12 "PCR9,Protocol Configuration Register 9" bitfld.word 0x12 15. "MINISLOT_EXISTS,gNumberOfMinislots!=0" "0,1" newline bitfld.word 0x12 14. "SYMBOL_WINDOW_EXISTS,gdSymbolWindow!=0" "0,1" newline hexmask.word 0x12 0.--13. 1. "OFFSET_CORRECTION_OUT,pOffsetCorrectionOut" line.word 0x14 "PCR10,Protocol Configuration Register 10" bitfld.word 0x14 15. "SINGLE_SLOT_ENABLED,pSingleSlotEnabled" "0,1" newline bitfld.word 0x14 14. "WAKEUP_CHANNEL,pWakeupChannel" "0,1" newline hexmask.word 0x14 0.--13. 1. "MACRO_PER_CYCLE,gMacroPerCycle" line.word 0x16 "PCR11,Protocol Configuration Register 11" bitfld.word 0x16 15. "KEY_SLOT_USED_FOR_STARTUP,pKeySlotUsedForStartup" "0,1" newline bitfld.word 0x16 14. "KEY_SLOT_USED_FOR_SYNC,pKeySlotUsedForSync" "0,1" newline hexmask.word 0x16 0.--13. 1. "OFFSET_CORRECTION_START,gOffsetCorrectionStart" line.word 0x18 "PCR12,Protocol Configuration Register 12" hexmask.word.byte 0x18 11.--15. 1. "ALLOW_PASSIVE_TO_ACTIVE,pAllowPassiveToActive" newline hexmask.word 0x18 0.--10. 1. "KEY_SLOT_HEADER_CRC,header CRC for key slot" line.word 0x1A "PCR13,Protocol Configuration Register 13" hexmask.word.byte 0x1A 10.--15. 1. "FIRST_MINISLOT_ACTION_POINT_OFFSET,max(gdActionPointOffset gdMinislotActionPointOffset) - 1" newline hexmask.word 0x1A 0.--9. 1. "STATIC_SLOT_AFTER_ACTION_POINT,gdStaticSlot - gdActionPointOffset - 1" line.word 0x1C "PCR14,Protocol Configuration Register 14" hexmask.word 0x1C 5.--15. 1. "RATE_CORRECTION_OUT,pRateCorrectionOut" newline hexmask.word.byte 0x1C 0.--4. 1. "LISTEN_TIMEOUT,[20:16]" line.word 0x1E "PCR15,Protocol Configuration Register 15" hexmask.word 0x1E 0.--15. 1. "LISTEN_TIMEOUT,[15:0]" line.word 0x20 "PCR16,Protocol Configuration Register 16" hexmask.word.byte 0x20 9.--15. 1. "MACRO_INITIAL_OFFSET_B,pMacroInitialOffset[B]" newline hexmask.word 0x20 0.--8. 1. "NOISE_LISTEN_TIMEOUT,[24:16]" line.word 0x22 "PCR17,Protocol Configuration Register 17" hexmask.word 0x22 0.--15. 1. "NOISE_LISTEN_TIMEOUT,[15:0]" line.word 0x24 "PCR18,Protocol Configuration Register 18" hexmask.word.byte 0x24 10.--15. 1. "WAKEUP_PATTERN,pWakeupPattern" newline hexmask.word 0x24 0.--9. 1. "KEY_SLOT_ID,pKeySlotId" line.word 0x26 "PCR19,Protocol Configuration Register 19" hexmask.word 0x26 7.--15. 1. "DECODING_CORRECTION_A,pDecodingCorrection + pDelayCompensation[A] + 2" newline hexmask.word.byte 0x26 0.--6. 1. "PAYLOAD_LENGTH_STATIC,gPayloadLengthStatic" line.word 0x28 "PCR20,Protocol Configuration Register 20" hexmask.word.byte 0x28 8.--15. 1. "MICRO_INITIAL_OFFSET_B,pMicroInitialOffset[B]" newline hexmask.word.byte 0x28 0.--7. 1. "MICRO_INITIAL_OFFSET_A,pMicroInitialOffset[A]" line.word 0x2A "PCR21,Protocol Configuration Register 21" bitfld.word 0x2A 13.--15. "EXTERN_RATE_CORRECTION,pExternRateCorrection" "0,1,2,3,4,5,6,7" newline hexmask.word 0x2A 0.--12. 1. "LATEST_TX,gNumberOfMinislots - pLatestTx" line.word 0x2C "PCR22,Protocol Configuration Register 22" hexmask.word 0x2C 4.--14. 1. "COMP_ACCEPTED_STARTUP_RANGE_A,pdAcceptedStartupRange - pDelayCompensation[A]" newline hexmask.word.byte 0x2C 0.--3. 1. "MICRO_PER_CYCLE,[19:16]" line.word 0x2E "PCR23,Protocol Configuration Register 23" hexmask.word 0x2E 0.--15. 1. "MICRO_PER_CYCLE,[15:0]" line.word 0x30 "PCR24,Protocol Configuration Register 24" hexmask.word.byte 0x30 11.--15. 1. "CLUSTER_DRIFT_DAMPING,pClusterDriftDamping" newline hexmask.word.byte 0x30 4.--10. 1. "MAX_PAYLOAD_LENGTH_DYNAMIC,pPayloadLengthDynMax" newline hexmask.word.byte 0x30 0.--3. 1. "MICRO_PER_CYCLE_MIN,[19:16]" line.word 0x32 "PCR25,Protocol Configuration Register 25" hexmask.word 0x32 0.--15. 1. "MICRO_PER_CYCLE_MIN,[15:0]" line.word 0x34 "PCR26,Protocol Configuration Register 26" bitfld.word 0x34 15. "ALLOW_HALT_DUE_TO_CLOCK,pAllowHaltDueToClock" "0,1" newline hexmask.word 0x34 4.--14. 1. "COMP_ACCEPTED_STARTUP_RANGE_B,pdAcceptedStartupRange - pDelayCompensation[B]" newline hexmask.word.byte 0x34 0.--3. 1. "MICRO_PER_CYCLE_MAX,[19:16]" line.word 0x36 "PCR27,Protocol Configuration Register 27" hexmask.word 0x36 0.--15. 1. "MICRO_PER_CYCLE_MAX,[15:0]" line.word 0x38 "PCR28,Protocol Configuration Register 28" bitfld.word 0x38 14.--15. "DYNAMIC_SLOT_IDLE_PHASE,gdDynamicSlotIdlePhase" "0,1,2,3" newline hexmask.word 0x38 0.--13. 1. "MACRO_AFTER_OFFSET_CORRECTION,gMacroPerCycle - gOffsetCorrectionStart" line.word 0x3A "PCR29,Protocol Configuration Register 29" bitfld.word 0x3A 13.--15. "EXTERN_OFFSET_CORRECTION,pExternOffsetCorrection" "0,1,2,3,4,5,6,7" newline hexmask.word 0x3A 0.--12. 1. "MINISLOTS_MAX,gNumberOfMinislots - 1" line.word 0x3C "PCR30,Protocol Configuration Register 30" hexmask.word.byte 0x3C 0.--3. 1. "SYNC_NODE_MAX,gSyncNodeMax" rgroup.word 0xDE++0x3 line.word 0x0 "STPWRHR,Stop Watch Count Register" hexmask.word 0x0 0.--15. 1. "STPW,Stop Watch Count Register" line.word 0x2 "STPWRLR,Stop Watch Count Register" hexmask.word 0x2 0.--15. 1. "STPW,Stop Watch Count Register" group.word 0xE2++0x1 line.word 0x0 "PEOER,Protocol Event Output Enable and StopWatch Control Register" bitfld.word 0x0 8. "STPW_EN,Stop watch count Enable" "0: Stopwatch counter disabled,1: Stopwatch counter enabled" newline bitfld.word 0x0 2. "TIM2_EE,Timer 2 expired Event Output Enable" "0: Timer 2 expired event out disabled,1: Timer 2 expired event out enabled" newline bitfld.word 0x0 1. "TIM1_EE,Timer 1 expired Event Output Enable" "0: Timer 1 expired event out disabled,1: Timer 1 expired event out enabled" newline bitfld.word 0x0 0. "CYS_EE,Cycle Start Event Output Enable" "0: Cycle start event out disabled,1: Cycle start event out enabled" group.word 0xE6++0xD line.word 0x0 "RFSDOR,Receive FIFO Start Data Offset Register" hexmask.word 0x0 0.--15. 1. "SDOA_SDOB,Start Data Field Offset" line.word 0x2 "RFSYMBADRHR,Receive FIFO System Memory Base Address Register" hexmask.word 0x2 0.--15. 1. "SMBA,System Memory Base Address" line.word 0x4 "RFSYMBADRLR,Receive FIFO System Memory Base Address Register" hexmask.word 0x4 4.--15. 1. "SMBA,System Memory Base Address" line.word 0x6 "RFPTR,Receive FIFO Periodic Timer Register" hexmask.word 0x6 0.--13. 1. "PTD,Periodic Timer Duration" line.word 0x8 "RFFLPCR,Receive FIFO Fill Level and POP Count Register" hexmask.word.byte 0x8 8.--15. 1. "FLB_PCB,Fill Level FIFO B (FLB)" newline hexmask.word.byte 0x8 0.--7. 1. "FLA_PCA,Fill Level FIFO A (FLA)" line.word 0xA "EEIFER,ECC Error Interrupt Flag and Enable Register" bitfld.word 0xA 15. "LRNE_OF,LRAM Non-Corrected Error Overflow Flag" "0: No such event,1: Non-Corrected Error overflow detected on CHI LRAM" newline bitfld.word 0xA 14. "LRCE_OF,LRAM Corrected Error Overflow Flag" "0: No such event,1: Corrected Error overflow detected on CHI LRAM" newline bitfld.word 0xA 13. "DRNE_OF,DRAM Non-Corrected Error Overflow Flag" "0: No such event,1: Non-Corrected Error overflow detected on PE DRAM" newline bitfld.word 0xA 12. "DRCE_OF,DRAM Corrected Error Overflow Flag" "0: No such event,1: Corrected Error overflow detected on PE DRAM" newline bitfld.word 0xA 11. "LRNE_IF,LRAM Non-Corrected Error Interrupt Flag" "0: No such event,1: Non-Corrected Error detected on CHI LRAM" newline bitfld.word 0xA 10. "LRCE_IF,LRAM Corrected Error Interrupt Flag" "0: No such event,1: Corrected Error detected on CHI LRAM" newline bitfld.word 0xA 9. "DRNE_IF,DRAM Non-Corrected Error Interrupt Flag" "0: No such event,1: Non-Corrected Error detected on PE DRAM" newline bitfld.word 0xA 8. "DRCE_IF,DRAM Corrected Error Interrupt Flag" "0: No such event,1: Corrected Error detected on PE DRAM" newline bitfld.word 0xA 3. "LRNE_IE,LRAM Non-Corrected Error Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" newline bitfld.word 0xA 2. "LRCE_IE,LRAM Corrected Error Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" newline bitfld.word 0xA 1. "DRNE_IE,DRAM Non-Corrected Error Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" newline bitfld.word 0xA 0. "DRCE_IE,DRAM Corrected Error Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line" line.word 0xC "EERICR,ECC Error Report and Injection Control Register" bitfld.word 0xC 15. "BSY,Register Update Busy" "0: ECC configuration is idle,1: ECC configuration is running" newline bitfld.word 0xC 8.--9. "ERS,Error Report Select" "0: Show PE DRAM non-corrected error information,1: Show PE DRAM corrected error information,2: Show CHI LRAM non-corrected error information,3: Show CHI LRAM corrected error information" newline bitfld.word 0xC 4. "ERM,Error Report Mode" "0: Store data and code as delivered by ECC decoding..,1: Store data and code as read from the memory" newline bitfld.word 0xC 1. "EIM,Error Injection Mode" "0: Use FR_EEIDR[DATA] and FR_EEICR[CODE] as XOR..,1: Use FR_EEIDR[DATA] and FR_EEICR[CODE] as write.." newline bitfld.word 0xC 0. "EIE,Error Injection Enable" "0: Error injection disabled,1: Error injection enabled" rgroup.word 0xF4++0x5 line.word 0x0 "EERAR,ECC Error Report Address Register" bitfld.word 0x0 15. "MID,Memory Identifier" "0: PE DRAM,1: CHI LRAM" newline bitfld.word 0x0 12.--14. "BANK,Memory Bank" "0: PE DRAM [7:0],1: PE DRAM [15:8],?,?,?,?,?,7: Reset value indicates no error found after reset." newline hexmask.word 0x0 0.--11. 1. "ADDR,Memory Address" line.word 0x2 "EERDR,ECC Error Report Data Register" hexmask.word 0x2 0.--15. 1. "DATA,Data" line.word 0x4 "EERCR,ECC Error Report Code Register" hexmask.word.byte 0x4 0.--4. 1. "CODE,Code" group.word 0xFA++0x5 line.word 0x0 "EEIAR,ECC Error Injection Address Register" bitfld.word 0x0 15. "MID,Memory Identifier" "0: PE DRAM,1: CHI LRAM" newline bitfld.word 0x0 12.--14. "BANK,Memory Bank" "0: BANK0: PE DRAM [7:0],1: BANK1: PE DRAM [15:8],?,?,?,?,?,?" newline hexmask.word 0x0 0.--11. 1. "ADDR,Memory Address" line.word 0x2 "EEIDR,ECC Error Injection Data Register" hexmask.word 0x2 0.--15. 1. "DATA,Data" line.word 0x4 "EEICR,ECC Error Injection Code Register" hexmask.word.byte 0x4 0.--4. 1. "CODE,Code" group.word 0x800++0xA07 line.word 0x0 "MBCCSR0,Message Buffer Configuratio0. Control and Status Register 0" bitfld.word 0x0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2 "MBCCFR0,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4 "MBFIDR0,Message Buffer Frame ID Registers" hexmask.word 0x4 0.--10. 1. "FID,Frame ID" line.word 0x6 "MBIDXR0,Message Buffer Index Registers" hexmask.word 0x6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x8 "MBCCSR1,Message Buffer Configuratio1. Control and Status Register 1" bitfld.word 0x8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xA "MBCCFR1,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xC "MBFIDR1,Message Buffer Frame ID Registers" hexmask.word 0xC 0.--10. 1. "FID,Frame ID" line.word 0xE "MBIDXR1,Message Buffer Index Registers" hexmask.word 0xE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x10 "MBCCSR2,Message Buffer Configuratio2. Control and Status Register 2" bitfld.word 0x10 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x10 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x10 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x10 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x10 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x10 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x10 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x10 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x10 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x10 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x12 "MBCCFR2,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x12 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x12 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x12 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x12 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x12 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x12 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x14 "MBFIDR2,Message Buffer Frame ID Registers" hexmask.word 0x14 0.--10. 1. "FID,Frame ID" line.word 0x16 "MBIDXR2,Message Buffer Index Registers" hexmask.word 0x16 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x18 "MBCCSR3,Message Buffer Configuratio3. Control and Status Register 3" bitfld.word 0x18 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x18 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x18 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x18 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x18 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x18 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x18 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x18 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x18 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x18 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1A "MBCCFR3,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1C "MBFIDR3,Message Buffer Frame ID Registers" hexmask.word 0x1C 0.--10. 1. "FID,Frame ID" line.word 0x1E "MBIDXR3,Message Buffer Index Registers" hexmask.word 0x1E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x20 "MBCCSR4,Message Buffer Configuratio4. Control and Status Register 4" bitfld.word 0x20 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x20 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x20 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x20 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x20 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x20 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x20 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x20 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x20 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x20 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x22 "MBCCFR4,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x22 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x22 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x22 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x22 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x22 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x22 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x24 "MBFIDR4,Message Buffer Frame ID Registers" hexmask.word 0x24 0.--10. 1. "FID,Frame ID" line.word 0x26 "MBIDXR4,Message Buffer Index Registers" hexmask.word 0x26 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x28 "MBCCSR5,Message Buffer Configuratio5. Control and Status Register 5" bitfld.word 0x28 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x28 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x28 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x28 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x28 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x28 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x28 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x28 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x28 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x28 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2A "MBCCFR5,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2C "MBFIDR5,Message Buffer Frame ID Registers" hexmask.word 0x2C 0.--10. 1. "FID,Frame ID" line.word 0x2E "MBIDXR5,Message Buffer Index Registers" hexmask.word 0x2E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x30 "MBCCSR6,Message Buffer Configuratio6. Control and Status Register 6" bitfld.word 0x30 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x30 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x30 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x30 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x30 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x30 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x30 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x30 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x30 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x30 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x32 "MBCCFR6,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x32 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x32 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x32 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x32 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x32 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x32 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x34 "MBFIDR6,Message Buffer Frame ID Registers" hexmask.word 0x34 0.--10. 1. "FID,Frame ID" line.word 0x36 "MBIDXR6,Message Buffer Index Registers" hexmask.word 0x36 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x38 "MBCCSR7,Message Buffer Configuratio7. Control and Status Register 7" bitfld.word 0x38 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x38 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x38 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x38 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x38 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x38 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x38 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x38 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x38 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x38 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3A "MBCCFR7,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3C "MBFIDR7,Message Buffer Frame ID Registers" hexmask.word 0x3C 0.--10. 1. "FID,Frame ID" line.word 0x3E "MBIDXR7,Message Buffer Index Registers" hexmask.word 0x3E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x40 "MBCCSR8,Message Buffer Configuratio8. Control and Status Register 8" bitfld.word 0x40 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x40 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x40 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x40 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x40 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x40 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x40 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x40 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x40 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x40 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x42 "MBCCFR8,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x42 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x42 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x42 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x42 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x42 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x42 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x44 "MBFIDR8,Message Buffer Frame ID Registers" hexmask.word 0x44 0.--10. 1. "FID,Frame ID" line.word 0x46 "MBIDXR8,Message Buffer Index Registers" hexmask.word 0x46 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x48 "MBCCSR9,Message Buffer Configuratio9. Control and Status Register 9" bitfld.word 0x48 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x48 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x48 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x48 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x48 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x48 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x48 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x48 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x48 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x48 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4A "MBCCFR9,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4C "MBFIDR9,Message Buffer Frame ID Registers" hexmask.word 0x4C 0.--10. 1. "FID,Frame ID" line.word 0x4E "MBIDXR9,Message Buffer Index Registers" hexmask.word 0x4E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x50 "MBCCSR10,Message Buffer Configuratio10. Control and Status Register 10" bitfld.word 0x50 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x50 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x50 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x50 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x50 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x50 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x50 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x50 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x50 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x50 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x52 "MBCCFR10,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x52 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x52 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x52 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x52 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x52 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x52 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x54 "MBFIDR10,Message Buffer Frame ID Registers" hexmask.word 0x54 0.--10. 1. "FID,Frame ID" line.word 0x56 "MBIDXR10,Message Buffer Index Registers" hexmask.word 0x56 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x58 "MBCCSR11,Message Buffer Configuratio11. Control and Status Register 11" bitfld.word 0x58 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x58 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x58 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x58 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x58 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x58 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x58 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x58 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x58 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x58 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5A "MBCCFR11,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5C "MBFIDR11,Message Buffer Frame ID Registers" hexmask.word 0x5C 0.--10. 1. "FID,Frame ID" line.word 0x5E "MBIDXR11,Message Buffer Index Registers" hexmask.word 0x5E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x60 "MBCCSR12,Message Buffer Configuratio12. Control and Status Register 12" bitfld.word 0x60 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x60 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x60 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x60 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x60 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x60 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x60 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x60 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x60 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x60 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x62 "MBCCFR12,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x62 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x62 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x62 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x62 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x62 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x62 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x64 "MBFIDR12,Message Buffer Frame ID Registers" hexmask.word 0x64 0.--10. 1. "FID,Frame ID" line.word 0x66 "MBIDXR12,Message Buffer Index Registers" hexmask.word 0x66 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x68 "MBCCSR13,Message Buffer Configuratio13. Control and Status Register 13" bitfld.word 0x68 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x68 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x68 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x68 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x68 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x68 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x68 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x68 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x68 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x68 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6A "MBCCFR13,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6C "MBFIDR13,Message Buffer Frame ID Registers" hexmask.word 0x6C 0.--10. 1. "FID,Frame ID" line.word 0x6E "MBIDXR13,Message Buffer Index Registers" hexmask.word 0x6E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x70 "MBCCSR14,Message Buffer Configuratio14. Control and Status Register 14" bitfld.word 0x70 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x70 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x70 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x70 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x70 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x70 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x70 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x70 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x70 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x70 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x72 "MBCCFR14,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x72 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x72 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x72 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x72 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x72 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x72 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x74 "MBFIDR14,Message Buffer Frame ID Registers" hexmask.word 0x74 0.--10. 1. "FID,Frame ID" line.word 0x76 "MBIDXR14,Message Buffer Index Registers" hexmask.word 0x76 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x78 "MBCCSR15,Message Buffer Configuratio15. Control and Status Register 15" bitfld.word 0x78 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x78 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x78 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x78 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x78 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x78 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x78 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x78 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x78 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x78 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7A "MBCCFR15,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7C "MBFIDR15,Message Buffer Frame ID Registers" hexmask.word 0x7C 0.--10. 1. "FID,Frame ID" line.word 0x7E "MBIDXR15,Message Buffer Index Registers" hexmask.word 0x7E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x80 "MBCCSR16,Message Buffer Configuratio16. Control and Status Register 16" bitfld.word 0x80 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x80 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x80 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x80 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x80 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x80 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x80 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x80 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x80 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x80 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x82 "MBCCFR16,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x82 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x82 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x82 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x82 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x82 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x82 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x84 "MBFIDR16,Message Buffer Frame ID Registers" hexmask.word 0x84 0.--10. 1. "FID,Frame ID" line.word 0x86 "MBIDXR16,Message Buffer Index Registers" hexmask.word 0x86 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x88 "MBCCSR17,Message Buffer Configuratio17. Control and Status Register 17" bitfld.word 0x88 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x88 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x88 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x88 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x88 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x88 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x88 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x88 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x88 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x88 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x8A "MBCCFR17,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x8A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x8A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x8A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x8A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x8A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x8A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x8C "MBFIDR17,Message Buffer Frame ID Registers" hexmask.word 0x8C 0.--10. 1. "FID,Frame ID" line.word 0x8E "MBIDXR17,Message Buffer Index Registers" hexmask.word 0x8E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x90 "MBCCSR18,Message Buffer Configuratio18. Control and Status Register 18" bitfld.word 0x90 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x90 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x90 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x90 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x90 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x90 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x90 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x90 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x90 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x90 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x92 "MBCCFR18,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x92 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x92 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x92 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x92 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x92 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x92 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x94 "MBFIDR18,Message Buffer Frame ID Registers" hexmask.word 0x94 0.--10. 1. "FID,Frame ID" line.word 0x96 "MBIDXR18,Message Buffer Index Registers" hexmask.word 0x96 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x98 "MBCCSR19,Message Buffer Configuratio19. Control and Status Register 19" bitfld.word 0x98 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x98 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x98 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x98 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x98 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x98 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x98 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x98 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x98 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x98 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x9A "MBCCFR19,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x9A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x9A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x9A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x9A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x9A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x9A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x9C "MBFIDR19,Message Buffer Frame ID Registers" hexmask.word 0x9C 0.--10. 1. "FID,Frame ID" line.word 0x9E "MBIDXR19,Message Buffer Index Registers" hexmask.word 0x9E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xA0 "MBCCSR20,Message Buffer Configuratio20. Control and Status Register 20" bitfld.word 0xA0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xA0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xA0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xA0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xA0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xA0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xA0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xA0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xA0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xA0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xA2 "MBCCFR20,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xA2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xA2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xA2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xA2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xA2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xA2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xA4 "MBFIDR20,Message Buffer Frame ID Registers" hexmask.word 0xA4 0.--10. 1. "FID,Frame ID" line.word 0xA6 "MBIDXR20,Message Buffer Index Registers" hexmask.word 0xA6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xA8 "MBCCSR21,Message Buffer Configuratio21. Control and Status Register 21" bitfld.word 0xA8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xA8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xA8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xA8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xA8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xA8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xA8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xA8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xA8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xA8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xAA "MBCCFR21,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xAA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xAA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xAA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xAA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xAA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xAA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xAC "MBFIDR21,Message Buffer Frame ID Registers" hexmask.word 0xAC 0.--10. 1. "FID,Frame ID" line.word 0xAE "MBIDXR21,Message Buffer Index Registers" hexmask.word 0xAE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xB0 "MBCCSR22,Message Buffer Configuratio22. Control and Status Register 22" bitfld.word 0xB0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xB0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xB0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xB0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xB0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xB0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xB0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xB0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xB0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xB0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xB2 "MBCCFR22,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xB2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xB2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xB2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xB2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xB2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xB2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xB4 "MBFIDR22,Message Buffer Frame ID Registers" hexmask.word 0xB4 0.--10. 1. "FID,Frame ID" line.word 0xB6 "MBIDXR22,Message Buffer Index Registers" hexmask.word 0xB6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xB8 "MBCCSR23,Message Buffer Configuratio23. Control and Status Register 23" bitfld.word 0xB8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xB8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xB8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xB8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xB8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xB8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xB8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xB8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xB8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xB8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xBA "MBCCFR23,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xBA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xBA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xBA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xBA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xBA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xBA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xBC "MBFIDR23,Message Buffer Frame ID Registers" hexmask.word 0xBC 0.--10. 1. "FID,Frame ID" line.word 0xBE "MBIDXR23,Message Buffer Index Registers" hexmask.word 0xBE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xC0 "MBCCSR24,Message Buffer Configuratio24. Control and Status Register 24" bitfld.word 0xC0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xC0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xC0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xC0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xC0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xC0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xC0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xC0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xC0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xC0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xC2 "MBCCFR24,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xC2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xC2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xC2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xC2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xC2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xC2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xC4 "MBFIDR24,Message Buffer Frame ID Registers" hexmask.word 0xC4 0.--10. 1. "FID,Frame ID" line.word 0xC6 "MBIDXR24,Message Buffer Index Registers" hexmask.word 0xC6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xC8 "MBCCSR25,Message Buffer Configuratio25. Control and Status Register 25" bitfld.word 0xC8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xC8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xC8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xC8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xC8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xC8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xC8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xC8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xC8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xC8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xCA "MBCCFR25,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xCA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xCA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xCA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xCA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xCA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xCA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xCC "MBFIDR25,Message Buffer Frame ID Registers" hexmask.word 0xCC 0.--10. 1. "FID,Frame ID" line.word 0xCE "MBIDXR25,Message Buffer Index Registers" hexmask.word 0xCE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xD0 "MBCCSR26,Message Buffer Configuratio26. Control and Status Register 26" bitfld.word 0xD0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xD0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xD0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xD0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xD0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xD0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xD0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xD0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xD0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xD0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xD2 "MBCCFR26,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xD2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xD2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xD2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xD2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xD2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xD2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xD4 "MBFIDR26,Message Buffer Frame ID Registers" hexmask.word 0xD4 0.--10. 1. "FID,Frame ID" line.word 0xD6 "MBIDXR26,Message Buffer Index Registers" hexmask.word 0xD6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xD8 "MBCCSR27,Message Buffer Configuratio27. Control and Status Register 27" bitfld.word 0xD8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xD8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xD8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xD8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xD8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xD8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xD8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xD8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xD8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xD8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xDA "MBCCFR27,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xDA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xDA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xDA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xDA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xDA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xDA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xDC "MBFIDR27,Message Buffer Frame ID Registers" hexmask.word 0xDC 0.--10. 1. "FID,Frame ID" line.word 0xDE "MBIDXR27,Message Buffer Index Registers" hexmask.word 0xDE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xE0 "MBCCSR28,Message Buffer Configuratio28. Control and Status Register 28" bitfld.word 0xE0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xE0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xE0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xE0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xE0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xE0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xE0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xE0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xE0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xE0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xE2 "MBCCFR28,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xE2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xE2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xE2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xE2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xE2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xE2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xE4 "MBFIDR28,Message Buffer Frame ID Registers" hexmask.word 0xE4 0.--10. 1. "FID,Frame ID" line.word 0xE6 "MBIDXR28,Message Buffer Index Registers" hexmask.word 0xE6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xE8 "MBCCSR29,Message Buffer Configuratio29. Control and Status Register 29" bitfld.word 0xE8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xE8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xE8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xE8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xE8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xE8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xE8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xE8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xE8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xE8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xEA "MBCCFR29,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xEA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xEA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xEA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xEA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xEA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xEA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xEC "MBFIDR29,Message Buffer Frame ID Registers" hexmask.word 0xEC 0.--10. 1. "FID,Frame ID" line.word 0xEE "MBIDXR29,Message Buffer Index Registers" hexmask.word 0xEE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xF0 "MBCCSR30,Message Buffer Configuratio30. Control and Status Register 30" bitfld.word 0xF0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xF0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xF0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xF0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xF0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xF0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xF0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xF0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xF0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xF0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xF2 "MBCCFR30,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xF2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xF2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xF2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xF2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xF2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xF2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xF4 "MBFIDR30,Message Buffer Frame ID Registers" hexmask.word 0xF4 0.--10. 1. "FID,Frame ID" line.word 0xF6 "MBIDXR30,Message Buffer Index Registers" hexmask.word 0xF6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0xF8 "MBCCSR31,Message Buffer Configuratio31. Control and Status Register 31" bitfld.word 0xF8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0xF8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0xF8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0xF8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0xF8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0xF8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0xF8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0xF8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0xF8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0xF8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0xFA "MBCCFR31,Message Buffer Cycle Counter Filter Registers" bitfld.word 0xFA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0xFA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0xFA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0xFA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0xFA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0xFA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0xFC "MBFIDR31,Message Buffer Frame ID Registers" hexmask.word 0xFC 0.--10. 1. "FID,Frame ID" line.word 0xFE "MBIDXR31,Message Buffer Index Registers" hexmask.word 0xFE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x100 "MBCCSR32,Message Buffer Configuratio32. Control and Status Register 32" bitfld.word 0x100 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x100 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x100 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x100 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x100 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x100 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x100 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x100 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x100 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x100 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x102 "MBCCFR32,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x102 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x102 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x102 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x102 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x102 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x102 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x104 "MBFIDR32,Message Buffer Frame ID Registers" hexmask.word 0x104 0.--10. 1. "FID,Frame ID" line.word 0x106 "MBIDXR32,Message Buffer Index Registers" hexmask.word 0x106 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x108 "MBCCSR33,Message Buffer Configuratio33. Control and Status Register 33" bitfld.word 0x108 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x108 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x108 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x108 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x108 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x108 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x108 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x108 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x108 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x108 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x10A "MBCCFR33,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x10A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x10A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x10A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x10A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x10A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x10A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x10C "MBFIDR33,Message Buffer Frame ID Registers" hexmask.word 0x10C 0.--10. 1. "FID,Frame ID" line.word 0x10E "MBIDXR33,Message Buffer Index Registers" hexmask.word 0x10E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x110 "MBCCSR34,Message Buffer Configuratio34. Control and Status Register 34" bitfld.word 0x110 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x110 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x110 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x110 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x110 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x110 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x110 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x110 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x110 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x110 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x112 "MBCCFR34,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x112 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x112 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x112 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x112 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x112 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x112 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x114 "MBFIDR34,Message Buffer Frame ID Registers" hexmask.word 0x114 0.--10. 1. "FID,Frame ID" line.word 0x116 "MBIDXR34,Message Buffer Index Registers" hexmask.word 0x116 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x118 "MBCCSR35,Message Buffer Configuratio35. Control and Status Register 35" bitfld.word 0x118 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x118 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x118 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x118 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x118 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x118 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x118 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x118 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x118 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x118 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x11A "MBCCFR35,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x11A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x11A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x11A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x11A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x11A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x11A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x11C "MBFIDR35,Message Buffer Frame ID Registers" hexmask.word 0x11C 0.--10. 1. "FID,Frame ID" line.word 0x11E "MBIDXR35,Message Buffer Index Registers" hexmask.word 0x11E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x120 "MBCCSR36,Message Buffer Configuratio36. Control and Status Register 36" bitfld.word 0x120 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x120 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x120 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x120 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x120 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x120 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x120 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x120 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x120 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x120 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x122 "MBCCFR36,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x122 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x122 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x122 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x122 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x122 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x122 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x124 "MBFIDR36,Message Buffer Frame ID Registers" hexmask.word 0x124 0.--10. 1. "FID,Frame ID" line.word 0x126 "MBIDXR36,Message Buffer Index Registers" hexmask.word 0x126 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x128 "MBCCSR37,Message Buffer Configuratio37. Control and Status Register 37" bitfld.word 0x128 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x128 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x128 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x128 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x128 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x128 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x128 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x128 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x128 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x128 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x12A "MBCCFR37,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x12A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x12A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x12A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x12A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x12A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x12A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x12C "MBFIDR37,Message Buffer Frame ID Registers" hexmask.word 0x12C 0.--10. 1. "FID,Frame ID" line.word 0x12E "MBIDXR37,Message Buffer Index Registers" hexmask.word 0x12E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x130 "MBCCSR38,Message Buffer Configuratio38. Control and Status Register 38" bitfld.word 0x130 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x130 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x130 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x130 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x130 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x130 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x130 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x130 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x130 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x130 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x132 "MBCCFR38,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x132 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x132 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x132 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x132 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x132 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x132 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x134 "MBFIDR38,Message Buffer Frame ID Registers" hexmask.word 0x134 0.--10. 1. "FID,Frame ID" line.word 0x136 "MBIDXR38,Message Buffer Index Registers" hexmask.word 0x136 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x138 "MBCCSR39,Message Buffer Configuratio39. Control and Status Register 39" bitfld.word 0x138 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x138 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x138 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x138 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x138 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x138 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x138 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x138 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x138 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x138 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x13A "MBCCFR39,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x13A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x13A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x13A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x13A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x13A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x13A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x13C "MBFIDR39,Message Buffer Frame ID Registers" hexmask.word 0x13C 0.--10. 1. "FID,Frame ID" line.word 0x13E "MBIDXR39,Message Buffer Index Registers" hexmask.word 0x13E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x140 "MBCCSR40,Message Buffer Configuratio40. Control and Status Register 40" bitfld.word 0x140 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x140 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x140 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x140 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x140 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x140 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x140 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x140 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x140 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x140 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x142 "MBCCFR40,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x142 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x142 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x142 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x142 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x142 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x142 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x144 "MBFIDR40,Message Buffer Frame ID Registers" hexmask.word 0x144 0.--10. 1. "FID,Frame ID" line.word 0x146 "MBIDXR40,Message Buffer Index Registers" hexmask.word 0x146 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x148 "MBCCSR41,Message Buffer Configuratio41. Control and Status Register 41" bitfld.word 0x148 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x148 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x148 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x148 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x148 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x148 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x148 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x148 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x148 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x148 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x14A "MBCCFR41,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x14A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x14A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x14A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x14A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x14A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x14A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x14C "MBFIDR41,Message Buffer Frame ID Registers" hexmask.word 0x14C 0.--10. 1. "FID,Frame ID" line.word 0x14E "MBIDXR41,Message Buffer Index Registers" hexmask.word 0x14E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x150 "MBCCSR42,Message Buffer Configuratio42. Control and Status Register 42" bitfld.word 0x150 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x150 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x150 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x150 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x150 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x150 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x150 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x150 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x150 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x150 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x152 "MBCCFR42,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x152 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x152 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x152 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x152 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x152 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x152 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x154 "MBFIDR42,Message Buffer Frame ID Registers" hexmask.word 0x154 0.--10. 1. "FID,Frame ID" line.word 0x156 "MBIDXR42,Message Buffer Index Registers" hexmask.word 0x156 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x158 "MBCCSR43,Message Buffer Configuratio43. Control and Status Register 43" bitfld.word 0x158 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x158 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x158 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x158 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x158 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x158 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x158 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x158 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x158 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x158 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x15A "MBCCFR43,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x15A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x15A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x15A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x15A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x15A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x15A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x15C "MBFIDR43,Message Buffer Frame ID Registers" hexmask.word 0x15C 0.--10. 1. "FID,Frame ID" line.word 0x15E "MBIDXR43,Message Buffer Index Registers" hexmask.word 0x15E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x160 "MBCCSR44,Message Buffer Configuratio44. Control and Status Register 44" bitfld.word 0x160 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x160 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x160 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x160 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x160 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x160 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x160 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x160 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x160 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x160 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x162 "MBCCFR44,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x162 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x162 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x162 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x162 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x162 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x162 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x164 "MBFIDR44,Message Buffer Frame ID Registers" hexmask.word 0x164 0.--10. 1. "FID,Frame ID" line.word 0x166 "MBIDXR44,Message Buffer Index Registers" hexmask.word 0x166 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x168 "MBCCSR45,Message Buffer Configuratio45. Control and Status Register 45" bitfld.word 0x168 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x168 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x168 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x168 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x168 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x168 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x168 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x168 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x168 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x168 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x16A "MBCCFR45,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x16A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x16A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x16A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x16A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x16A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x16A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x16C "MBFIDR45,Message Buffer Frame ID Registers" hexmask.word 0x16C 0.--10. 1. "FID,Frame ID" line.word 0x16E "MBIDXR45,Message Buffer Index Registers" hexmask.word 0x16E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x170 "MBCCSR46,Message Buffer Configuratio46. Control and Status Register 46" bitfld.word 0x170 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x170 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x170 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x170 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x170 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x170 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x170 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x170 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x170 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x170 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x172 "MBCCFR46,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x172 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x172 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x172 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x172 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x172 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x172 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x174 "MBFIDR46,Message Buffer Frame ID Registers" hexmask.word 0x174 0.--10. 1. "FID,Frame ID" line.word 0x176 "MBIDXR46,Message Buffer Index Registers" hexmask.word 0x176 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x178 "MBCCSR47,Message Buffer Configuratio47. Control and Status Register 47" bitfld.word 0x178 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x178 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x178 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x178 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x178 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x178 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x178 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x178 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x178 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x178 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x17A "MBCCFR47,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x17A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x17A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x17A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x17A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x17A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x17A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x17C "MBFIDR47,Message Buffer Frame ID Registers" hexmask.word 0x17C 0.--10. 1. "FID,Frame ID" line.word 0x17E "MBIDXR47,Message Buffer Index Registers" hexmask.word 0x17E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x180 "MBCCSR48,Message Buffer Configuratio48. Control and Status Register 48" bitfld.word 0x180 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x180 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x180 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x180 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x180 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x180 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x180 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x180 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x180 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x180 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x182 "MBCCFR48,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x182 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x182 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x182 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x182 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x182 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x182 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x184 "MBFIDR48,Message Buffer Frame ID Registers" hexmask.word 0x184 0.--10. 1. "FID,Frame ID" line.word 0x186 "MBIDXR48,Message Buffer Index Registers" hexmask.word 0x186 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x188 "MBCCSR49,Message Buffer Configuratio49. Control and Status Register 49" bitfld.word 0x188 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x188 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x188 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x188 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x188 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x188 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x188 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x188 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x188 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x188 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x18A "MBCCFR49,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x18A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x18A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x18A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x18A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x18A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x18A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x18C "MBFIDR49,Message Buffer Frame ID Registers" hexmask.word 0x18C 0.--10. 1. "FID,Frame ID" line.word 0x18E "MBIDXR49,Message Buffer Index Registers" hexmask.word 0x18E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x190 "MBCCSR50,Message Buffer Configuratio50. Control and Status Register 50" bitfld.word 0x190 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x190 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x190 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x190 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x190 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x190 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x190 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x190 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x190 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x190 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x192 "MBCCFR50,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x192 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x192 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x192 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x192 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x192 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x192 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x194 "MBFIDR50,Message Buffer Frame ID Registers" hexmask.word 0x194 0.--10. 1. "FID,Frame ID" line.word 0x196 "MBIDXR50,Message Buffer Index Registers" hexmask.word 0x196 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x198 "MBCCSR51,Message Buffer Configuratio51. Control and Status Register 51" bitfld.word 0x198 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x198 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x198 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x198 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x198 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x198 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x198 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x198 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x198 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x198 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x19A "MBCCFR51,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x19A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x19A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x19A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x19A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x19A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x19A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x19C "MBFIDR51,Message Buffer Frame ID Registers" hexmask.word 0x19C 0.--10. 1. "FID,Frame ID" line.word 0x19E "MBIDXR51,Message Buffer Index Registers" hexmask.word 0x19E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1A0 "MBCCSR52,Message Buffer Configuratio52. Control and Status Register 52" bitfld.word 0x1A0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1A0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1A0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1A0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1A0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1A0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1A0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1A0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1A0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1A0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1A2 "MBCCFR52,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1A2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1A2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1A2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1A2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1A2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1A2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1A4 "MBFIDR52,Message Buffer Frame ID Registers" hexmask.word 0x1A4 0.--10. 1. "FID,Frame ID" line.word 0x1A6 "MBIDXR52,Message Buffer Index Registers" hexmask.word 0x1A6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1A8 "MBCCSR53,Message Buffer Configuratio53. Control and Status Register 53" bitfld.word 0x1A8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1A8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1A8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1A8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1A8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1A8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1A8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1A8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1A8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1A8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1AA "MBCCFR53,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1AA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1AA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1AA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1AA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1AA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1AA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1AC "MBFIDR53,Message Buffer Frame ID Registers" hexmask.word 0x1AC 0.--10. 1. "FID,Frame ID" line.word 0x1AE "MBIDXR53,Message Buffer Index Registers" hexmask.word 0x1AE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1B0 "MBCCSR54,Message Buffer Configuratio54. Control and Status Register 54" bitfld.word 0x1B0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1B0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1B0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1B0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1B0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1B0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1B0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1B0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1B0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1B0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1B2 "MBCCFR54,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1B2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1B2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1B2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1B2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1B2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1B2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1B4 "MBFIDR54,Message Buffer Frame ID Registers" hexmask.word 0x1B4 0.--10. 1. "FID,Frame ID" line.word 0x1B6 "MBIDXR54,Message Buffer Index Registers" hexmask.word 0x1B6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1B8 "MBCCSR55,Message Buffer Configuratio55. Control and Status Register 55" bitfld.word 0x1B8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1B8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1B8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1B8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1B8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1B8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1B8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1B8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1B8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1B8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1BA "MBCCFR55,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1BA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1BA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1BA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1BA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1BA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1BA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1BC "MBFIDR55,Message Buffer Frame ID Registers" hexmask.word 0x1BC 0.--10. 1. "FID,Frame ID" line.word 0x1BE "MBIDXR55,Message Buffer Index Registers" hexmask.word 0x1BE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1C0 "MBCCSR56,Message Buffer Configuratio56. Control and Status Register 56" bitfld.word 0x1C0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1C0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1C0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1C0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1C0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1C0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1C0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1C0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1C0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1C0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1C2 "MBCCFR56,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1C2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1C2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1C2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1C2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1C2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1C2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1C4 "MBFIDR56,Message Buffer Frame ID Registers" hexmask.word 0x1C4 0.--10. 1. "FID,Frame ID" line.word 0x1C6 "MBIDXR56,Message Buffer Index Registers" hexmask.word 0x1C6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1C8 "MBCCSR57,Message Buffer Configuratio57. Control and Status Register 57" bitfld.word 0x1C8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1C8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1C8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1C8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1C8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1C8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1C8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1C8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1C8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1C8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1CA "MBCCFR57,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1CA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1CA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1CA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1CA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1CA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1CA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1CC "MBFIDR57,Message Buffer Frame ID Registers" hexmask.word 0x1CC 0.--10. 1. "FID,Frame ID" line.word 0x1CE "MBIDXR57,Message Buffer Index Registers" hexmask.word 0x1CE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1D0 "MBCCSR58,Message Buffer Configuratio58. Control and Status Register 58" bitfld.word 0x1D0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1D0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1D0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1D0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1D0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1D0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1D0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1D0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1D0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1D0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1D2 "MBCCFR58,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1D2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1D2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1D2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1D2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1D2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1D2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1D4 "MBFIDR58,Message Buffer Frame ID Registers" hexmask.word 0x1D4 0.--10. 1. "FID,Frame ID" line.word 0x1D6 "MBIDXR58,Message Buffer Index Registers" hexmask.word 0x1D6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1D8 "MBCCSR59,Message Buffer Configuratio59. Control and Status Register 59" bitfld.word 0x1D8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1D8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1D8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1D8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1D8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1D8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1D8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1D8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1D8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1D8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1DA "MBCCFR59,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1DA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1DA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1DA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1DA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1DA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1DA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1DC "MBFIDR59,Message Buffer Frame ID Registers" hexmask.word 0x1DC 0.--10. 1. "FID,Frame ID" line.word 0x1DE "MBIDXR59,Message Buffer Index Registers" hexmask.word 0x1DE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1E0 "MBCCSR60,Message Buffer Configuratio60. Control and Status Register 60" bitfld.word 0x1E0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1E0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1E0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1E0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1E0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1E0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1E0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1E0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1E0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1E0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1E2 "MBCCFR60,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1E2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1E2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1E2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1E2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1E2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1E2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1E4 "MBFIDR60,Message Buffer Frame ID Registers" hexmask.word 0x1E4 0.--10. 1. "FID,Frame ID" line.word 0x1E6 "MBIDXR60,Message Buffer Index Registers" hexmask.word 0x1E6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1E8 "MBCCSR61,Message Buffer Configuratio61. Control and Status Register 61" bitfld.word 0x1E8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1E8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1E8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1E8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1E8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1E8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1E8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1E8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1E8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1E8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1EA "MBCCFR61,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1EA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1EA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1EA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1EA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1EA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1EA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1EC "MBFIDR61,Message Buffer Frame ID Registers" hexmask.word 0x1EC 0.--10. 1. "FID,Frame ID" line.word 0x1EE "MBIDXR61,Message Buffer Index Registers" hexmask.word 0x1EE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1F0 "MBCCSR62,Message Buffer Configuratio62. Control and Status Register 62" bitfld.word 0x1F0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1F0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1F0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1F0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1F0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1F0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1F0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1F0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1F0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1F0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1F2 "MBCCFR62,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1F2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1F2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1F2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1F2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1F2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1F2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1F4 "MBFIDR62,Message Buffer Frame ID Registers" hexmask.word 0x1F4 0.--10. 1. "FID,Frame ID" line.word 0x1F6 "MBIDXR62,Message Buffer Index Registers" hexmask.word 0x1F6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x1F8 "MBCCSR63,Message Buffer Configuratio63. Control and Status Register 63" bitfld.word 0x1F8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x1F8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x1F8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x1F8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x1F8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x1F8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x1F8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x1F8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x1F8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x1F8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x1FA "MBCCFR63,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x1FA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x1FA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x1FA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x1FA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x1FA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x1FA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x1FC "MBFIDR63,Message Buffer Frame ID Registers" hexmask.word 0x1FC 0.--10. 1. "FID,Frame ID" line.word 0x1FE "MBIDXR63,Message Buffer Index Registers" hexmask.word 0x1FE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x200 "MBCCSR64,Message Buffer Configuratio64. Control and Status Register 64" bitfld.word 0x200 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x200 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x200 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x200 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x200 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x200 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x200 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x200 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x200 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x200 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x202 "MBCCFR64,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x202 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x202 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x202 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x202 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x202 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x202 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x204 "MBFIDR64,Message Buffer Frame ID Registers" hexmask.word 0x204 0.--10. 1. "FID,Frame ID" line.word 0x206 "MBIDXR64,Message Buffer Index Registers" hexmask.word 0x206 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x208 "MBCCSR65,Message Buffer Configuratio65. Control and Status Register 65" bitfld.word 0x208 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x208 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x208 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x208 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x208 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x208 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x208 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x208 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x208 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x208 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x20A "MBCCFR65,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x20A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x20A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x20A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x20A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x20A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x20A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x20C "MBFIDR65,Message Buffer Frame ID Registers" hexmask.word 0x20C 0.--10. 1. "FID,Frame ID" line.word 0x20E "MBIDXR65,Message Buffer Index Registers" hexmask.word 0x20E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x210 "MBCCSR66,Message Buffer Configuratio66. Control and Status Register 66" bitfld.word 0x210 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x210 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x210 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x210 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x210 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x210 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x210 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x210 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x210 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x210 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x212 "MBCCFR66,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x212 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x212 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x212 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x212 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x212 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x212 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x214 "MBFIDR66,Message Buffer Frame ID Registers" hexmask.word 0x214 0.--10. 1. "FID,Frame ID" line.word 0x216 "MBIDXR66,Message Buffer Index Registers" hexmask.word 0x216 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x218 "MBCCSR67,Message Buffer Configuratio67. Control and Status Register 67" bitfld.word 0x218 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x218 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x218 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x218 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x218 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x218 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x218 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x218 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x218 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x218 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x21A "MBCCFR67,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x21A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x21A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x21A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x21A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x21A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x21A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x21C "MBFIDR67,Message Buffer Frame ID Registers" hexmask.word 0x21C 0.--10. 1. "FID,Frame ID" line.word 0x21E "MBIDXR67,Message Buffer Index Registers" hexmask.word 0x21E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x220 "MBCCSR68,Message Buffer Configuratio68. Control and Status Register 68" bitfld.word 0x220 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x220 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x220 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x220 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x220 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x220 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x220 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x220 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x220 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x220 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x222 "MBCCFR68,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x222 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x222 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x222 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x222 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x222 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x222 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x224 "MBFIDR68,Message Buffer Frame ID Registers" hexmask.word 0x224 0.--10. 1. "FID,Frame ID" line.word 0x226 "MBIDXR68,Message Buffer Index Registers" hexmask.word 0x226 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x228 "MBCCSR69,Message Buffer Configuratio69. Control and Status Register 69" bitfld.word 0x228 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x228 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x228 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x228 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x228 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x228 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x228 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x228 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x228 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x228 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x22A "MBCCFR69,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x22A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x22A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x22A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x22A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x22A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x22A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x22C "MBFIDR69,Message Buffer Frame ID Registers" hexmask.word 0x22C 0.--10. 1. "FID,Frame ID" line.word 0x22E "MBIDXR69,Message Buffer Index Registers" hexmask.word 0x22E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x230 "MBCCSR70,Message Buffer Configuratio70. Control and Status Register 70" bitfld.word 0x230 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x230 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x230 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x230 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x230 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x230 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x230 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x230 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x230 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x230 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x232 "MBCCFR70,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x232 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x232 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x232 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x232 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x232 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x232 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x234 "MBFIDR70,Message Buffer Frame ID Registers" hexmask.word 0x234 0.--10. 1. "FID,Frame ID" line.word 0x236 "MBIDXR70,Message Buffer Index Registers" hexmask.word 0x236 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x238 "MBCCSR71,Message Buffer Configuratio71. Control and Status Register 71" bitfld.word 0x238 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x238 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x238 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x238 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x238 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x238 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x238 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x238 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x238 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x238 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x23A "MBCCFR71,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x23A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x23A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x23A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x23A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x23A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x23A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x23C "MBFIDR71,Message Buffer Frame ID Registers" hexmask.word 0x23C 0.--10. 1. "FID,Frame ID" line.word 0x23E "MBIDXR71,Message Buffer Index Registers" hexmask.word 0x23E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x240 "MBCCSR72,Message Buffer Configuratio72. Control and Status Register 72" bitfld.word 0x240 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x240 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x240 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x240 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x240 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x240 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x240 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x240 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x240 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x240 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x242 "MBCCFR72,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x242 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x242 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x242 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x242 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x242 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x242 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x244 "MBFIDR72,Message Buffer Frame ID Registers" hexmask.word 0x244 0.--10. 1. "FID,Frame ID" line.word 0x246 "MBIDXR72,Message Buffer Index Registers" hexmask.word 0x246 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x248 "MBCCSR73,Message Buffer Configuratio73. Control and Status Register 73" bitfld.word 0x248 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x248 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x248 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x248 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x248 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x248 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x248 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x248 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x248 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x248 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x24A "MBCCFR73,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x24A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x24A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x24A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x24A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x24A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x24A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x24C "MBFIDR73,Message Buffer Frame ID Registers" hexmask.word 0x24C 0.--10. 1. "FID,Frame ID" line.word 0x24E "MBIDXR73,Message Buffer Index Registers" hexmask.word 0x24E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x250 "MBCCSR74,Message Buffer Configuratio74. Control and Status Register 74" bitfld.word 0x250 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x250 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x250 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x250 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x250 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x250 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x250 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x250 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x250 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x250 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x252 "MBCCFR74,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x252 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x252 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x252 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x252 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x252 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x252 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x254 "MBFIDR74,Message Buffer Frame ID Registers" hexmask.word 0x254 0.--10. 1. "FID,Frame ID" line.word 0x256 "MBIDXR74,Message Buffer Index Registers" hexmask.word 0x256 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x258 "MBCCSR75,Message Buffer Configuratio75. Control and Status Register 75" bitfld.word 0x258 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x258 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x258 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x258 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x258 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x258 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x258 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x258 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x258 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x258 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x25A "MBCCFR75,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x25A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x25A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x25A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x25A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x25A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x25A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x25C "MBFIDR75,Message Buffer Frame ID Registers" hexmask.word 0x25C 0.--10. 1. "FID,Frame ID" line.word 0x25E "MBIDXR75,Message Buffer Index Registers" hexmask.word 0x25E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x260 "MBCCSR76,Message Buffer Configuratio76. Control and Status Register 76" bitfld.word 0x260 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x260 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x260 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x260 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x260 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x260 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x260 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x260 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x260 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x260 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x262 "MBCCFR76,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x262 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x262 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x262 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x262 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x262 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x262 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x264 "MBFIDR76,Message Buffer Frame ID Registers" hexmask.word 0x264 0.--10. 1. "FID,Frame ID" line.word 0x266 "MBIDXR76,Message Buffer Index Registers" hexmask.word 0x266 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x268 "MBCCSR77,Message Buffer Configuratio77. Control and Status Register 77" bitfld.word 0x268 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x268 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x268 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x268 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x268 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x268 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x268 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x268 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x268 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x268 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x26A "MBCCFR77,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x26A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x26A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x26A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x26A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x26A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x26A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x26C "MBFIDR77,Message Buffer Frame ID Registers" hexmask.word 0x26C 0.--10. 1. "FID,Frame ID" line.word 0x26E "MBIDXR77,Message Buffer Index Registers" hexmask.word 0x26E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x270 "MBCCSR78,Message Buffer Configuratio78. Control and Status Register 78" bitfld.word 0x270 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x270 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x270 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x270 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x270 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x270 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x270 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x270 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x270 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x270 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x272 "MBCCFR78,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x272 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x272 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x272 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x272 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x272 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x272 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x274 "MBFIDR78,Message Buffer Frame ID Registers" hexmask.word 0x274 0.--10. 1. "FID,Frame ID" line.word 0x276 "MBIDXR78,Message Buffer Index Registers" hexmask.word 0x276 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x278 "MBCCSR79,Message Buffer Configuratio79. Control and Status Register 79" bitfld.word 0x278 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x278 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x278 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x278 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x278 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x278 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x278 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x278 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x278 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x278 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x27A "MBCCFR79,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x27A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x27A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x27A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x27A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x27A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x27A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x27C "MBFIDR79,Message Buffer Frame ID Registers" hexmask.word 0x27C 0.--10. 1. "FID,Frame ID" line.word 0x27E "MBIDXR79,Message Buffer Index Registers" hexmask.word 0x27E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x280 "MBCCSR80,Message Buffer Configuratio80. Control and Status Register 80" bitfld.word 0x280 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x280 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x280 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x280 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x280 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x280 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x280 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x280 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x280 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x280 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x282 "MBCCFR80,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x282 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x282 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x282 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x282 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x282 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x282 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x284 "MBFIDR80,Message Buffer Frame ID Registers" hexmask.word 0x284 0.--10. 1. "FID,Frame ID" line.word 0x286 "MBIDXR80,Message Buffer Index Registers" hexmask.word 0x286 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x288 "MBCCSR81,Message Buffer Configuratio81. Control and Status Register 81" bitfld.word 0x288 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x288 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x288 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x288 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x288 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x288 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x288 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x288 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x288 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x288 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x28A "MBCCFR81,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x28A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x28A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x28A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x28A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x28A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x28A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x28C "MBFIDR81,Message Buffer Frame ID Registers" hexmask.word 0x28C 0.--10. 1. "FID,Frame ID" line.word 0x28E "MBIDXR81,Message Buffer Index Registers" hexmask.word 0x28E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x290 "MBCCSR82,Message Buffer Configuratio82. Control and Status Register 82" bitfld.word 0x290 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x290 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x290 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x290 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x290 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x290 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x290 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x290 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x290 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x290 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x292 "MBCCFR82,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x292 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x292 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x292 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x292 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x292 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x292 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x294 "MBFIDR82,Message Buffer Frame ID Registers" hexmask.word 0x294 0.--10. 1. "FID,Frame ID" line.word 0x296 "MBIDXR82,Message Buffer Index Registers" hexmask.word 0x296 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x298 "MBCCSR83,Message Buffer Configuratio83. Control and Status Register 83" bitfld.word 0x298 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x298 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x298 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x298 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x298 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x298 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x298 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x298 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x298 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x298 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x29A "MBCCFR83,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x29A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x29A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x29A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x29A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x29A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x29A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x29C "MBFIDR83,Message Buffer Frame ID Registers" hexmask.word 0x29C 0.--10. 1. "FID,Frame ID" line.word 0x29E "MBIDXR83,Message Buffer Index Registers" hexmask.word 0x29E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2A0 "MBCCSR84,Message Buffer Configuratio84. Control and Status Register 84" bitfld.word 0x2A0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2A0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2A0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2A0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2A0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2A0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2A0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2A0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2A0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2A0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2A2 "MBCCFR84,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2A2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2A2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2A2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2A2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2A2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2A2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2A4 "MBFIDR84,Message Buffer Frame ID Registers" hexmask.word 0x2A4 0.--10. 1. "FID,Frame ID" line.word 0x2A6 "MBIDXR84,Message Buffer Index Registers" hexmask.word 0x2A6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2A8 "MBCCSR85,Message Buffer Configuratio85. Control and Status Register 85" bitfld.word 0x2A8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2A8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2A8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2A8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2A8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2A8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2A8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2A8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2A8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2A8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2AA "MBCCFR85,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2AA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2AA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2AA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2AA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2AA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2AA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2AC "MBFIDR85,Message Buffer Frame ID Registers" hexmask.word 0x2AC 0.--10. 1. "FID,Frame ID" line.word 0x2AE "MBIDXR85,Message Buffer Index Registers" hexmask.word 0x2AE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2B0 "MBCCSR86,Message Buffer Configuratio86. Control and Status Register 86" bitfld.word 0x2B0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2B0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2B0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2B0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2B0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2B0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2B0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2B0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2B0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2B0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2B2 "MBCCFR86,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2B2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2B2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2B2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2B2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2B2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2B2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2B4 "MBFIDR86,Message Buffer Frame ID Registers" hexmask.word 0x2B4 0.--10. 1. "FID,Frame ID" line.word 0x2B6 "MBIDXR86,Message Buffer Index Registers" hexmask.word 0x2B6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2B8 "MBCCSR87,Message Buffer Configuratio87. Control and Status Register 87" bitfld.word 0x2B8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2B8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2B8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2B8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2B8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2B8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2B8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2B8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2B8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2B8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2BA "MBCCFR87,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2BA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2BA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2BA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2BA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2BA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2BA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2BC "MBFIDR87,Message Buffer Frame ID Registers" hexmask.word 0x2BC 0.--10. 1. "FID,Frame ID" line.word 0x2BE "MBIDXR87,Message Buffer Index Registers" hexmask.word 0x2BE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2C0 "MBCCSR88,Message Buffer Configuratio88. Control and Status Register 88" bitfld.word 0x2C0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2C0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2C0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2C0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2C0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2C0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2C0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2C0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2C0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2C0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2C2 "MBCCFR88,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2C2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2C2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2C2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2C2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2C2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2C2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2C4 "MBFIDR88,Message Buffer Frame ID Registers" hexmask.word 0x2C4 0.--10. 1. "FID,Frame ID" line.word 0x2C6 "MBIDXR88,Message Buffer Index Registers" hexmask.word 0x2C6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2C8 "MBCCSR89,Message Buffer Configuratio89. Control and Status Register 89" bitfld.word 0x2C8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2C8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2C8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2C8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2C8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2C8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2C8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2C8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2C8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2C8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2CA "MBCCFR89,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2CA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2CA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2CA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2CA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2CA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2CA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2CC "MBFIDR89,Message Buffer Frame ID Registers" hexmask.word 0x2CC 0.--10. 1. "FID,Frame ID" line.word 0x2CE "MBIDXR89,Message Buffer Index Registers" hexmask.word 0x2CE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2D0 "MBCCSR90,Message Buffer Configuratio90. Control and Status Register 90" bitfld.word 0x2D0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2D0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2D0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2D0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2D0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2D0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2D0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2D0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2D0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2D0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2D2 "MBCCFR90,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2D2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2D2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2D2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2D2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2D2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2D2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2D4 "MBFIDR90,Message Buffer Frame ID Registers" hexmask.word 0x2D4 0.--10. 1. "FID,Frame ID" line.word 0x2D6 "MBIDXR90,Message Buffer Index Registers" hexmask.word 0x2D6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2D8 "MBCCSR91,Message Buffer Configuratio91. Control and Status Register 91" bitfld.word 0x2D8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2D8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2D8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2D8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2D8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2D8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2D8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2D8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2D8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2D8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2DA "MBCCFR91,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2DA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2DA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2DA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2DA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2DA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2DA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2DC "MBFIDR91,Message Buffer Frame ID Registers" hexmask.word 0x2DC 0.--10. 1. "FID,Frame ID" line.word 0x2DE "MBIDXR91,Message Buffer Index Registers" hexmask.word 0x2DE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2E0 "MBCCSR92,Message Buffer Configuratio92. Control and Status Register 92" bitfld.word 0x2E0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2E0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2E0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2E0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2E0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2E0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2E0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2E0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2E0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2E0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2E2 "MBCCFR92,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2E2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2E2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2E2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2E2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2E2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2E2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2E4 "MBFIDR92,Message Buffer Frame ID Registers" hexmask.word 0x2E4 0.--10. 1. "FID,Frame ID" line.word 0x2E6 "MBIDXR92,Message Buffer Index Registers" hexmask.word 0x2E6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2E8 "MBCCSR93,Message Buffer Configuratio93. Control and Status Register 93" bitfld.word 0x2E8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2E8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2E8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2E8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2E8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2E8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2E8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2E8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2E8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2E8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2EA "MBCCFR93,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2EA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2EA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2EA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2EA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2EA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2EA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2EC "MBFIDR93,Message Buffer Frame ID Registers" hexmask.word 0x2EC 0.--10. 1. "FID,Frame ID" line.word 0x2EE "MBIDXR93,Message Buffer Index Registers" hexmask.word 0x2EE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2F0 "MBCCSR94,Message Buffer Configuratio94. Control and Status Register 94" bitfld.word 0x2F0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2F0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2F0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2F0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2F0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2F0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2F0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2F0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2F0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2F0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2F2 "MBCCFR94,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2F2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2F2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2F2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2F2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2F2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2F2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2F4 "MBFIDR94,Message Buffer Frame ID Registers" hexmask.word 0x2F4 0.--10. 1. "FID,Frame ID" line.word 0x2F6 "MBIDXR94,Message Buffer Index Registers" hexmask.word 0x2F6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x2F8 "MBCCSR95,Message Buffer Configuratio95. Control and Status Register 95" bitfld.word 0x2F8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x2F8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x2F8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x2F8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x2F8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x2F8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x2F8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x2F8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x2F8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x2F8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x2FA "MBCCFR95,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x2FA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x2FA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x2FA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x2FA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x2FA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x2FA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x2FC "MBFIDR95,Message Buffer Frame ID Registers" hexmask.word 0x2FC 0.--10. 1. "FID,Frame ID" line.word 0x2FE "MBIDXR95,Message Buffer Index Registers" hexmask.word 0x2FE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x300 "MBCCSR96,Message Buffer Configuratio96. Control and Status Register 96" bitfld.word 0x300 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x300 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x300 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x300 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x300 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x300 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x300 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x300 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x300 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x300 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x302 "MBCCFR96,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x302 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x302 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x302 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x302 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x302 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x302 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x304 "MBFIDR96,Message Buffer Frame ID Registers" hexmask.word 0x304 0.--10. 1. "FID,Frame ID" line.word 0x306 "MBIDXR96,Message Buffer Index Registers" hexmask.word 0x306 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x308 "MBCCSR97,Message Buffer Configuratio97. Control and Status Register 97" bitfld.word 0x308 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x308 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x308 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x308 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x308 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x308 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x308 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x308 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x308 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x308 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x30A "MBCCFR97,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x30A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x30A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x30A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x30A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x30A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x30A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x30C "MBFIDR97,Message Buffer Frame ID Registers" hexmask.word 0x30C 0.--10. 1. "FID,Frame ID" line.word 0x30E "MBIDXR97,Message Buffer Index Registers" hexmask.word 0x30E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x310 "MBCCSR98,Message Buffer Configuratio98. Control and Status Register 98" bitfld.word 0x310 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x310 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x310 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x310 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x310 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x310 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x310 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x310 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x310 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x310 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x312 "MBCCFR98,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x312 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x312 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x312 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x312 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x312 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x312 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x314 "MBFIDR98,Message Buffer Frame ID Registers" hexmask.word 0x314 0.--10. 1. "FID,Frame ID" line.word 0x316 "MBIDXR98,Message Buffer Index Registers" hexmask.word 0x316 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x318 "MBCCSR99,Message Buffer Configuratio99. Control and Status Register 99" bitfld.word 0x318 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x318 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x318 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x318 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x318 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x318 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x318 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x318 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x318 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x318 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x31A "MBCCFR99,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x31A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x31A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x31A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x31A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x31A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x31A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x31C "MBFIDR99,Message Buffer Frame ID Registers" hexmask.word 0x31C 0.--10. 1. "FID,Frame ID" line.word 0x31E "MBIDXR99,Message Buffer Index Registers" hexmask.word 0x31E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x320 "MBCCSR100,Message Buffer Configuratio100. Control and Status Register 100" bitfld.word 0x320 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x320 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x320 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x320 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x320 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x320 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x320 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x320 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x320 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x320 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x322 "MBCCFR100,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x322 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x322 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x322 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x322 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x322 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x322 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x324 "MBFIDR100,Message Buffer Frame ID Registers" hexmask.word 0x324 0.--10. 1. "FID,Frame ID" line.word 0x326 "MBIDXR100,Message Buffer Index Registers" hexmask.word 0x326 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x328 "MBCCSR101,Message Buffer Configuratio101. Control and Status Register 101" bitfld.word 0x328 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x328 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x328 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x328 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x328 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x328 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x328 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x328 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x328 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x328 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x32A "MBCCFR101,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x32A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x32A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x32A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x32A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x32A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x32A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x32C "MBFIDR101,Message Buffer Frame ID Registers" hexmask.word 0x32C 0.--10. 1. "FID,Frame ID" line.word 0x32E "MBIDXR101,Message Buffer Index Registers" hexmask.word 0x32E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x330 "MBCCSR102,Message Buffer Configuratio102. Control and Status Register 102" bitfld.word 0x330 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x330 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x330 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x330 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x330 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x330 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x330 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x330 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x330 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x330 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x332 "MBCCFR102,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x332 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x332 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x332 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x332 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x332 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x332 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x334 "MBFIDR102,Message Buffer Frame ID Registers" hexmask.word 0x334 0.--10. 1. "FID,Frame ID" line.word 0x336 "MBIDXR102,Message Buffer Index Registers" hexmask.word 0x336 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x338 "MBCCSR103,Message Buffer Configuratio103. Control and Status Register 103" bitfld.word 0x338 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x338 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x338 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x338 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x338 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x338 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x338 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x338 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x338 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x338 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x33A "MBCCFR103,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x33A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x33A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x33A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x33A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x33A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x33A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x33C "MBFIDR103,Message Buffer Frame ID Registers" hexmask.word 0x33C 0.--10. 1. "FID,Frame ID" line.word 0x33E "MBIDXR103,Message Buffer Index Registers" hexmask.word 0x33E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x340 "MBCCSR104,Message Buffer Configuratio104. Control and Status Register 104" bitfld.word 0x340 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x340 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x340 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x340 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x340 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x340 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x340 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x340 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x340 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x340 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x342 "MBCCFR104,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x342 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x342 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x342 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x342 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x342 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x342 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x344 "MBFIDR104,Message Buffer Frame ID Registers" hexmask.word 0x344 0.--10. 1. "FID,Frame ID" line.word 0x346 "MBIDXR104,Message Buffer Index Registers" hexmask.word 0x346 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x348 "MBCCSR105,Message Buffer Configuratio105. Control and Status Register 105" bitfld.word 0x348 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x348 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x348 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x348 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x348 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x348 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x348 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x348 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x348 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x348 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x34A "MBCCFR105,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x34A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x34A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x34A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x34A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x34A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x34A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x34C "MBFIDR105,Message Buffer Frame ID Registers" hexmask.word 0x34C 0.--10. 1. "FID,Frame ID" line.word 0x34E "MBIDXR105,Message Buffer Index Registers" hexmask.word 0x34E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x350 "MBCCSR106,Message Buffer Configuratio106. Control and Status Register 106" bitfld.word 0x350 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x350 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x350 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x350 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x350 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x350 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x350 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x350 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x350 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x350 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x352 "MBCCFR106,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x352 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x352 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x352 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x352 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x352 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x352 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x354 "MBFIDR106,Message Buffer Frame ID Registers" hexmask.word 0x354 0.--10. 1. "FID,Frame ID" line.word 0x356 "MBIDXR106,Message Buffer Index Registers" hexmask.word 0x356 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x358 "MBCCSR107,Message Buffer Configuratio107. Control and Status Register 107" bitfld.word 0x358 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x358 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x358 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x358 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x358 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x358 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x358 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x358 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x358 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x358 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x35A "MBCCFR107,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x35A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x35A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x35A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x35A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x35A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x35A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x35C "MBFIDR107,Message Buffer Frame ID Registers" hexmask.word 0x35C 0.--10. 1. "FID,Frame ID" line.word 0x35E "MBIDXR107,Message Buffer Index Registers" hexmask.word 0x35E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x360 "MBCCSR108,Message Buffer Configuratio108. Control and Status Register 108" bitfld.word 0x360 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x360 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x360 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x360 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x360 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x360 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x360 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x360 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x360 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x360 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x362 "MBCCFR108,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x362 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x362 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x362 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x362 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x362 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x362 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x364 "MBFIDR108,Message Buffer Frame ID Registers" hexmask.word 0x364 0.--10. 1. "FID,Frame ID" line.word 0x366 "MBIDXR108,Message Buffer Index Registers" hexmask.word 0x366 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x368 "MBCCSR109,Message Buffer Configuratio109. Control and Status Register 109" bitfld.word 0x368 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x368 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x368 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x368 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x368 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x368 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x368 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x368 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x368 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x368 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x36A "MBCCFR109,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x36A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x36A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x36A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x36A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x36A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x36A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x36C "MBFIDR109,Message Buffer Frame ID Registers" hexmask.word 0x36C 0.--10. 1. "FID,Frame ID" line.word 0x36E "MBIDXR109,Message Buffer Index Registers" hexmask.word 0x36E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x370 "MBCCSR110,Message Buffer Configuratio110. Control and Status Register 110" bitfld.word 0x370 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x370 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x370 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x370 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x370 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x370 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x370 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x370 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x370 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x370 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x372 "MBCCFR110,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x372 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x372 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x372 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x372 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x372 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x372 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x374 "MBFIDR110,Message Buffer Frame ID Registers" hexmask.word 0x374 0.--10. 1. "FID,Frame ID" line.word 0x376 "MBIDXR110,Message Buffer Index Registers" hexmask.word 0x376 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x378 "MBCCSR111,Message Buffer Configuratio111. Control and Status Register 111" bitfld.word 0x378 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x378 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x378 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x378 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x378 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x378 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x378 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x378 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x378 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x378 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x37A "MBCCFR111,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x37A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x37A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x37A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x37A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x37A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x37A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x37C "MBFIDR111,Message Buffer Frame ID Registers" hexmask.word 0x37C 0.--10. 1. "FID,Frame ID" line.word 0x37E "MBIDXR111,Message Buffer Index Registers" hexmask.word 0x37E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x380 "MBCCSR112,Message Buffer Configuratio112. Control and Status Register 112" bitfld.word 0x380 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x380 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x380 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x380 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x380 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x380 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x380 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x380 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x380 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x380 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x382 "MBCCFR112,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x382 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x382 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x382 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x382 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x382 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x382 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x384 "MBFIDR112,Message Buffer Frame ID Registers" hexmask.word 0x384 0.--10. 1. "FID,Frame ID" line.word 0x386 "MBIDXR112,Message Buffer Index Registers" hexmask.word 0x386 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x388 "MBCCSR113,Message Buffer Configuratio113. Control and Status Register 113" bitfld.word 0x388 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x388 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x388 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x388 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x388 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x388 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x388 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x388 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x388 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x388 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x38A "MBCCFR113,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x38A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x38A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x38A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x38A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x38A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x38A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x38C "MBFIDR113,Message Buffer Frame ID Registers" hexmask.word 0x38C 0.--10. 1. "FID,Frame ID" line.word 0x38E "MBIDXR113,Message Buffer Index Registers" hexmask.word 0x38E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x390 "MBCCSR114,Message Buffer Configuratio114. Control and Status Register 114" bitfld.word 0x390 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x390 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x390 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x390 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x390 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x390 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x390 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x390 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x390 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x390 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x392 "MBCCFR114,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x392 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x392 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x392 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x392 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x392 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x392 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x394 "MBFIDR114,Message Buffer Frame ID Registers" hexmask.word 0x394 0.--10. 1. "FID,Frame ID" line.word 0x396 "MBIDXR114,Message Buffer Index Registers" hexmask.word 0x396 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x398 "MBCCSR115,Message Buffer Configuratio115. Control and Status Register 115" bitfld.word 0x398 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x398 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x398 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x398 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x398 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x398 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x398 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x398 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x398 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x398 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x39A "MBCCFR115,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x39A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x39A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x39A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x39A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x39A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x39A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x39C "MBFIDR115,Message Buffer Frame ID Registers" hexmask.word 0x39C 0.--10. 1. "FID,Frame ID" line.word 0x39E "MBIDXR115,Message Buffer Index Registers" hexmask.word 0x39E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3A0 "MBCCSR116,Message Buffer Configuratio116. Control and Status Register 116" bitfld.word 0x3A0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3A0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3A0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3A0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3A0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3A0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3A0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3A0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3A0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3A0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3A2 "MBCCFR116,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3A2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3A2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3A2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3A2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3A2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3A2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3A4 "MBFIDR116,Message Buffer Frame ID Registers" hexmask.word 0x3A4 0.--10. 1. "FID,Frame ID" line.word 0x3A6 "MBIDXR116,Message Buffer Index Registers" hexmask.word 0x3A6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3A8 "MBCCSR117,Message Buffer Configuratio117. Control and Status Register 117" bitfld.word 0x3A8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3A8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3A8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3A8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3A8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3A8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3A8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3A8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3A8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3A8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3AA "MBCCFR117,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3AA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3AA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3AA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3AA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3AA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3AA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3AC "MBFIDR117,Message Buffer Frame ID Registers" hexmask.word 0x3AC 0.--10. 1. "FID,Frame ID" line.word 0x3AE "MBIDXR117,Message Buffer Index Registers" hexmask.word 0x3AE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3B0 "MBCCSR118,Message Buffer Configuratio118. Control and Status Register 118" bitfld.word 0x3B0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3B0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3B0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3B0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3B0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3B0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3B0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3B0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3B0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3B0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3B2 "MBCCFR118,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3B2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3B2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3B2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3B2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3B2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3B2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3B4 "MBFIDR118,Message Buffer Frame ID Registers" hexmask.word 0x3B4 0.--10. 1. "FID,Frame ID" line.word 0x3B6 "MBIDXR118,Message Buffer Index Registers" hexmask.word 0x3B6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3B8 "MBCCSR119,Message Buffer Configuratio119. Control and Status Register 119" bitfld.word 0x3B8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3B8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3B8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3B8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3B8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3B8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3B8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3B8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3B8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3B8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3BA "MBCCFR119,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3BA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3BA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3BA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3BA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3BA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3BA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3BC "MBFIDR119,Message Buffer Frame ID Registers" hexmask.word 0x3BC 0.--10. 1. "FID,Frame ID" line.word 0x3BE "MBIDXR119,Message Buffer Index Registers" hexmask.word 0x3BE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3C0 "MBCCSR120,Message Buffer Configuratio120. Control and Status Register 120" bitfld.word 0x3C0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3C0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3C0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3C0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3C0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3C0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3C0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3C0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3C0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3C0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3C2 "MBCCFR120,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3C2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3C2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3C2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3C2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3C2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3C2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3C4 "MBFIDR120,Message Buffer Frame ID Registers" hexmask.word 0x3C4 0.--10. 1. "FID,Frame ID" line.word 0x3C6 "MBIDXR120,Message Buffer Index Registers" hexmask.word 0x3C6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3C8 "MBCCSR121,Message Buffer Configuratio121. Control and Status Register 121" bitfld.word 0x3C8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3C8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3C8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3C8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3C8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3C8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3C8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3C8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3C8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3C8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3CA "MBCCFR121,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3CA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3CA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3CA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3CA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3CA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3CA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3CC "MBFIDR121,Message Buffer Frame ID Registers" hexmask.word 0x3CC 0.--10. 1. "FID,Frame ID" line.word 0x3CE "MBIDXR121,Message Buffer Index Registers" hexmask.word 0x3CE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3D0 "MBCCSR122,Message Buffer Configuratio122. Control and Status Register 122" bitfld.word 0x3D0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3D0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3D0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3D0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3D0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3D0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3D0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3D0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3D0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3D0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3D2 "MBCCFR122,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3D2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3D2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3D2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3D2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3D2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3D2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3D4 "MBFIDR122,Message Buffer Frame ID Registers" hexmask.word 0x3D4 0.--10. 1. "FID,Frame ID" line.word 0x3D6 "MBIDXR122,Message Buffer Index Registers" hexmask.word 0x3D6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3D8 "MBCCSR123,Message Buffer Configuratio123. Control and Status Register 123" bitfld.word 0x3D8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3D8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3D8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3D8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3D8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3D8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3D8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3D8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3D8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3D8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3DA "MBCCFR123,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3DA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3DA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3DA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3DA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3DA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3DA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3DC "MBFIDR123,Message Buffer Frame ID Registers" hexmask.word 0x3DC 0.--10. 1. "FID,Frame ID" line.word 0x3DE "MBIDXR123,Message Buffer Index Registers" hexmask.word 0x3DE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3E0 "MBCCSR124,Message Buffer Configuratio124. Control and Status Register 124" bitfld.word 0x3E0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3E0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3E0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3E0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3E0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3E0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3E0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3E0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3E0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3E0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3E2 "MBCCFR124,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3E2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3E2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3E2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3E2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3E2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3E2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3E4 "MBFIDR124,Message Buffer Frame ID Registers" hexmask.word 0x3E4 0.--10. 1. "FID,Frame ID" line.word 0x3E6 "MBIDXR124,Message Buffer Index Registers" hexmask.word 0x3E6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3E8 "MBCCSR125,Message Buffer Configuratio125. Control and Status Register 125" bitfld.word 0x3E8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3E8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3E8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3E8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3E8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3E8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3E8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3E8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3E8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3E8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3EA "MBCCFR125,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3EA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3EA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3EA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3EA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3EA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3EA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3EC "MBFIDR125,Message Buffer Frame ID Registers" hexmask.word 0x3EC 0.--10. 1. "FID,Frame ID" line.word 0x3EE "MBIDXR125,Message Buffer Index Registers" hexmask.word 0x3EE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3F0 "MBCCSR126,Message Buffer Configuratio126. Control and Status Register 126" bitfld.word 0x3F0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3F0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3F0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3F0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3F0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3F0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3F0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3F0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3F0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3F0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3F2 "MBCCFR126,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3F2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3F2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3F2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3F2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3F2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3F2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3F4 "MBFIDR126,Message Buffer Frame ID Registers" hexmask.word 0x3F4 0.--10. 1. "FID,Frame ID" line.word 0x3F6 "MBIDXR126,Message Buffer Index Registers" hexmask.word 0x3F6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x3F8 "MBCCSR127,Message Buffer Configuratio127. Control and Status Register 127" bitfld.word 0x3F8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x3F8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x3F8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x3F8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x3F8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x3F8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x3F8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x3F8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x3F8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x3F8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x3FA "MBCCFR127,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x3FA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x3FA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x3FA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x3FA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x3FA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x3FA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x3FC "MBFIDR127,Message Buffer Frame ID Registers" hexmask.word 0x3FC 0.--10. 1. "FID,Frame ID" line.word 0x3FE "MBIDXR127,Message Buffer Index Registers" hexmask.word 0x3FE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x400 "MBCCSR128,Message Buffer Configuratio128. Control and Status Register 128" bitfld.word 0x400 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x400 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x400 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x400 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x400 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x400 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x400 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x400 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x400 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x400 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x402 "MBCCFR128,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x402 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x402 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x402 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x402 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x402 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x402 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x404 "MBFIDR128,Message Buffer Frame ID Registers" hexmask.word 0x404 0.--10. 1. "FID,Frame ID" line.word 0x406 "MBIDXR128,Message Buffer Index Registers" hexmask.word 0x406 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x408 "MBCCSR129,Message Buffer Configuratio129. Control and Status Register 129" bitfld.word 0x408 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x408 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x408 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x408 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x408 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x408 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x408 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x408 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x408 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x408 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x40A "MBCCFR129,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x40A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x40A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x40A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x40A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x40A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x40A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x40C "MBFIDR129,Message Buffer Frame ID Registers" hexmask.word 0x40C 0.--10. 1. "FID,Frame ID" line.word 0x40E "MBIDXR129,Message Buffer Index Registers" hexmask.word 0x40E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x410 "MBCCSR130,Message Buffer Configuratio130. Control and Status Register 130" bitfld.word 0x410 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x410 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x410 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x410 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x410 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x410 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x410 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x410 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x410 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x410 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x412 "MBCCFR130,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x412 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x412 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x412 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x412 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x412 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x412 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x414 "MBFIDR130,Message Buffer Frame ID Registers" hexmask.word 0x414 0.--10. 1. "FID,Frame ID" line.word 0x416 "MBIDXR130,Message Buffer Index Registers" hexmask.word 0x416 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x418 "MBCCSR131,Message Buffer Configuratio131. Control and Status Register 131" bitfld.word 0x418 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x418 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x418 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x418 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x418 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x418 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x418 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x418 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x418 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x418 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x41A "MBCCFR131,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x41A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x41A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x41A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x41A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x41A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x41A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x41C "MBFIDR131,Message Buffer Frame ID Registers" hexmask.word 0x41C 0.--10. 1. "FID,Frame ID" line.word 0x41E "MBIDXR131,Message Buffer Index Registers" hexmask.word 0x41E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x420 "MBCCSR132,Message Buffer Configuratio132. Control and Status Register 132" bitfld.word 0x420 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x420 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x420 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x420 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x420 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x420 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x420 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x420 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x420 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x420 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x422 "MBCCFR132,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x422 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x422 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x422 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x422 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x422 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x422 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x424 "MBFIDR132,Message Buffer Frame ID Registers" hexmask.word 0x424 0.--10. 1. "FID,Frame ID" line.word 0x426 "MBIDXR132,Message Buffer Index Registers" hexmask.word 0x426 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x428 "MBCCSR133,Message Buffer Configuratio133. Control and Status Register 133" bitfld.word 0x428 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x428 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x428 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x428 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x428 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x428 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x428 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x428 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x428 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x428 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x42A "MBCCFR133,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x42A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x42A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x42A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x42A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x42A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x42A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x42C "MBFIDR133,Message Buffer Frame ID Registers" hexmask.word 0x42C 0.--10. 1. "FID,Frame ID" line.word 0x42E "MBIDXR133,Message Buffer Index Registers" hexmask.word 0x42E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x430 "MBCCSR134,Message Buffer Configuratio134. Control and Status Register 134" bitfld.word 0x430 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x430 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x430 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x430 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x430 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x430 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x430 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x430 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x430 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x430 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x432 "MBCCFR134,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x432 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x432 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x432 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x432 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x432 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x432 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x434 "MBFIDR134,Message Buffer Frame ID Registers" hexmask.word 0x434 0.--10. 1. "FID,Frame ID" line.word 0x436 "MBIDXR134,Message Buffer Index Registers" hexmask.word 0x436 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x438 "MBCCSR135,Message Buffer Configuratio135. Control and Status Register 135" bitfld.word 0x438 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x438 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x438 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x438 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x438 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x438 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x438 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x438 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x438 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x438 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x43A "MBCCFR135,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x43A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x43A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x43A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x43A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x43A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x43A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x43C "MBFIDR135,Message Buffer Frame ID Registers" hexmask.word 0x43C 0.--10. 1. "FID,Frame ID" line.word 0x43E "MBIDXR135,Message Buffer Index Registers" hexmask.word 0x43E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x440 "MBCCSR136,Message Buffer Configuratio136. Control and Status Register 136" bitfld.word 0x440 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x440 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x440 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x440 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x440 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x440 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x440 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x440 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x440 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x440 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x442 "MBCCFR136,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x442 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x442 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x442 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x442 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x442 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x442 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x444 "MBFIDR136,Message Buffer Frame ID Registers" hexmask.word 0x444 0.--10. 1. "FID,Frame ID" line.word 0x446 "MBIDXR136,Message Buffer Index Registers" hexmask.word 0x446 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x448 "MBCCSR137,Message Buffer Configuratio137. Control and Status Register 137" bitfld.word 0x448 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x448 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x448 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x448 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x448 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x448 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x448 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x448 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x448 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x448 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x44A "MBCCFR137,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x44A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x44A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x44A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x44A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x44A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x44A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x44C "MBFIDR137,Message Buffer Frame ID Registers" hexmask.word 0x44C 0.--10. 1. "FID,Frame ID" line.word 0x44E "MBIDXR137,Message Buffer Index Registers" hexmask.word 0x44E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x450 "MBCCSR138,Message Buffer Configuratio138. Control and Status Register 138" bitfld.word 0x450 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x450 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x450 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x450 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x450 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x450 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x450 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x450 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x450 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x450 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x452 "MBCCFR138,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x452 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x452 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x452 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x452 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x452 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x452 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x454 "MBFIDR138,Message Buffer Frame ID Registers" hexmask.word 0x454 0.--10. 1. "FID,Frame ID" line.word 0x456 "MBIDXR138,Message Buffer Index Registers" hexmask.word 0x456 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x458 "MBCCSR139,Message Buffer Configuratio139. Control and Status Register 139" bitfld.word 0x458 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x458 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x458 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x458 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x458 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x458 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x458 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x458 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x458 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x458 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x45A "MBCCFR139,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x45A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x45A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x45A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x45A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x45A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x45A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x45C "MBFIDR139,Message Buffer Frame ID Registers" hexmask.word 0x45C 0.--10. 1. "FID,Frame ID" line.word 0x45E "MBIDXR139,Message Buffer Index Registers" hexmask.word 0x45E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x460 "MBCCSR140,Message Buffer Configuratio140. Control and Status Register 140" bitfld.word 0x460 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x460 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x460 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x460 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x460 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x460 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x460 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x460 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x460 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x460 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x462 "MBCCFR140,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x462 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x462 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x462 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x462 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x462 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x462 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x464 "MBFIDR140,Message Buffer Frame ID Registers" hexmask.word 0x464 0.--10. 1. "FID,Frame ID" line.word 0x466 "MBIDXR140,Message Buffer Index Registers" hexmask.word 0x466 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x468 "MBCCSR141,Message Buffer Configuratio141. Control and Status Register 141" bitfld.word 0x468 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x468 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x468 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x468 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x468 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x468 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x468 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x468 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x468 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x468 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x46A "MBCCFR141,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x46A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x46A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x46A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x46A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x46A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x46A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x46C "MBFIDR141,Message Buffer Frame ID Registers" hexmask.word 0x46C 0.--10. 1. "FID,Frame ID" line.word 0x46E "MBIDXR141,Message Buffer Index Registers" hexmask.word 0x46E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x470 "MBCCSR142,Message Buffer Configuratio142. Control and Status Register 142" bitfld.word 0x470 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x470 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x470 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x470 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x470 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x470 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x470 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x470 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x470 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x470 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x472 "MBCCFR142,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x472 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x472 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x472 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x472 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x472 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x472 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x474 "MBFIDR142,Message Buffer Frame ID Registers" hexmask.word 0x474 0.--10. 1. "FID,Frame ID" line.word 0x476 "MBIDXR142,Message Buffer Index Registers" hexmask.word 0x476 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x478 "MBCCSR143,Message Buffer Configuratio143. Control and Status Register 143" bitfld.word 0x478 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x478 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x478 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x478 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x478 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x478 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x478 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x478 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x478 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x478 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x47A "MBCCFR143,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x47A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x47A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x47A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x47A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x47A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x47A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x47C "MBFIDR143,Message Buffer Frame ID Registers" hexmask.word 0x47C 0.--10. 1. "FID,Frame ID" line.word 0x47E "MBIDXR143,Message Buffer Index Registers" hexmask.word 0x47E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x480 "MBCCSR144,Message Buffer Configuratio144. Control and Status Register 144" bitfld.word 0x480 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x480 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x480 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x480 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x480 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x480 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x480 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x480 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x480 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x480 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x482 "MBCCFR144,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x482 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x482 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x482 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x482 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x482 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x482 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x484 "MBFIDR144,Message Buffer Frame ID Registers" hexmask.word 0x484 0.--10. 1. "FID,Frame ID" line.word 0x486 "MBIDXR144,Message Buffer Index Registers" hexmask.word 0x486 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x488 "MBCCSR145,Message Buffer Configuratio145. Control and Status Register 145" bitfld.word 0x488 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x488 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x488 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x488 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x488 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x488 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x488 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x488 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x488 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x488 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x48A "MBCCFR145,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x48A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x48A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x48A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x48A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x48A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x48A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x48C "MBFIDR145,Message Buffer Frame ID Registers" hexmask.word 0x48C 0.--10. 1. "FID,Frame ID" line.word 0x48E "MBIDXR145,Message Buffer Index Registers" hexmask.word 0x48E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x490 "MBCCSR146,Message Buffer Configuratio146. Control and Status Register 146" bitfld.word 0x490 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x490 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x490 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x490 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x490 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x490 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x490 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x490 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x490 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x490 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x492 "MBCCFR146,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x492 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x492 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x492 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x492 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x492 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x492 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x494 "MBFIDR146,Message Buffer Frame ID Registers" hexmask.word 0x494 0.--10. 1. "FID,Frame ID" line.word 0x496 "MBIDXR146,Message Buffer Index Registers" hexmask.word 0x496 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x498 "MBCCSR147,Message Buffer Configuratio147. Control and Status Register 147" bitfld.word 0x498 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x498 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x498 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x498 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x498 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x498 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x498 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x498 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x498 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x498 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x49A "MBCCFR147,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x49A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x49A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x49A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x49A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x49A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x49A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x49C "MBFIDR147,Message Buffer Frame ID Registers" hexmask.word 0x49C 0.--10. 1. "FID,Frame ID" line.word 0x49E "MBIDXR147,Message Buffer Index Registers" hexmask.word 0x49E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4A0 "MBCCSR148,Message Buffer Configuratio148. Control and Status Register 148" bitfld.word 0x4A0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4A0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4A0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4A0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4A0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4A0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4A0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4A0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4A0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4A0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4A2 "MBCCFR148,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4A2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4A2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4A2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4A2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4A2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4A2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4A4 "MBFIDR148,Message Buffer Frame ID Registers" hexmask.word 0x4A4 0.--10. 1. "FID,Frame ID" line.word 0x4A6 "MBIDXR148,Message Buffer Index Registers" hexmask.word 0x4A6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4A8 "MBCCSR149,Message Buffer Configuratio149. Control and Status Register 149" bitfld.word 0x4A8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4A8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4A8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4A8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4A8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4A8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4A8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4A8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4A8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4A8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4AA "MBCCFR149,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4AA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4AA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4AA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4AA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4AA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4AA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4AC "MBFIDR149,Message Buffer Frame ID Registers" hexmask.word 0x4AC 0.--10. 1. "FID,Frame ID" line.word 0x4AE "MBIDXR149,Message Buffer Index Registers" hexmask.word 0x4AE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4B0 "MBCCSR150,Message Buffer Configuratio150. Control and Status Register 150" bitfld.word 0x4B0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4B0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4B0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4B0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4B0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4B0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4B0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4B0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4B0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4B0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4B2 "MBCCFR150,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4B2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4B2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4B2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4B2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4B2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4B2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4B4 "MBFIDR150,Message Buffer Frame ID Registers" hexmask.word 0x4B4 0.--10. 1. "FID,Frame ID" line.word 0x4B6 "MBIDXR150,Message Buffer Index Registers" hexmask.word 0x4B6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4B8 "MBCCSR151,Message Buffer Configuratio151. Control and Status Register 151" bitfld.word 0x4B8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4B8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4B8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4B8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4B8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4B8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4B8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4B8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4B8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4B8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4BA "MBCCFR151,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4BA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4BA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4BA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4BA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4BA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4BA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4BC "MBFIDR151,Message Buffer Frame ID Registers" hexmask.word 0x4BC 0.--10. 1. "FID,Frame ID" line.word 0x4BE "MBIDXR151,Message Buffer Index Registers" hexmask.word 0x4BE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4C0 "MBCCSR152,Message Buffer Configuratio152. Control and Status Register 152" bitfld.word 0x4C0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4C0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4C0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4C0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4C0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4C0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4C0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4C0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4C0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4C0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4C2 "MBCCFR152,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4C2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4C2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4C2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4C2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4C2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4C2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4C4 "MBFIDR152,Message Buffer Frame ID Registers" hexmask.word 0x4C4 0.--10. 1. "FID,Frame ID" line.word 0x4C6 "MBIDXR152,Message Buffer Index Registers" hexmask.word 0x4C6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4C8 "MBCCSR153,Message Buffer Configuratio153. Control and Status Register 153" bitfld.word 0x4C8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4C8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4C8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4C8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4C8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4C8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4C8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4C8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4C8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4C8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4CA "MBCCFR153,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4CA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4CA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4CA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4CA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4CA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4CA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4CC "MBFIDR153,Message Buffer Frame ID Registers" hexmask.word 0x4CC 0.--10. 1. "FID,Frame ID" line.word 0x4CE "MBIDXR153,Message Buffer Index Registers" hexmask.word 0x4CE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4D0 "MBCCSR154,Message Buffer Configuratio154. Control and Status Register 154" bitfld.word 0x4D0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4D0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4D0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4D0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4D0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4D0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4D0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4D0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4D0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4D0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4D2 "MBCCFR154,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4D2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4D2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4D2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4D2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4D2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4D2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4D4 "MBFIDR154,Message Buffer Frame ID Registers" hexmask.word 0x4D4 0.--10. 1. "FID,Frame ID" line.word 0x4D6 "MBIDXR154,Message Buffer Index Registers" hexmask.word 0x4D6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4D8 "MBCCSR155,Message Buffer Configuratio155. Control and Status Register 155" bitfld.word 0x4D8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4D8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4D8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4D8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4D8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4D8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4D8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4D8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4D8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4D8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4DA "MBCCFR155,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4DA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4DA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4DA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4DA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4DA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4DA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4DC "MBFIDR155,Message Buffer Frame ID Registers" hexmask.word 0x4DC 0.--10. 1. "FID,Frame ID" line.word 0x4DE "MBIDXR155,Message Buffer Index Registers" hexmask.word 0x4DE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4E0 "MBCCSR156,Message Buffer Configuratio156. Control and Status Register 156" bitfld.word 0x4E0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4E0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4E0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4E0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4E0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4E0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4E0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4E0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4E0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4E0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4E2 "MBCCFR156,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4E2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4E2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4E2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4E2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4E2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4E2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4E4 "MBFIDR156,Message Buffer Frame ID Registers" hexmask.word 0x4E4 0.--10. 1. "FID,Frame ID" line.word 0x4E6 "MBIDXR156,Message Buffer Index Registers" hexmask.word 0x4E6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4E8 "MBCCSR157,Message Buffer Configuratio157. Control and Status Register 157" bitfld.word 0x4E8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4E8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4E8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4E8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4E8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4E8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4E8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4E8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4E8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4E8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4EA "MBCCFR157,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4EA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4EA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4EA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4EA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4EA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4EA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4EC "MBFIDR157,Message Buffer Frame ID Registers" hexmask.word 0x4EC 0.--10. 1. "FID,Frame ID" line.word 0x4EE "MBIDXR157,Message Buffer Index Registers" hexmask.word 0x4EE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4F0 "MBCCSR158,Message Buffer Configuratio158. Control and Status Register 158" bitfld.word 0x4F0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4F0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4F0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4F0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4F0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4F0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4F0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4F0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4F0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4F0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4F2 "MBCCFR158,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4F2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4F2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4F2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4F2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4F2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4F2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4F4 "MBFIDR158,Message Buffer Frame ID Registers" hexmask.word 0x4F4 0.--10. 1. "FID,Frame ID" line.word 0x4F6 "MBIDXR158,Message Buffer Index Registers" hexmask.word 0x4F6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x4F8 "MBCCSR159,Message Buffer Configuratio159. Control and Status Register 159" bitfld.word 0x4F8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x4F8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x4F8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x4F8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x4F8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x4F8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x4F8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x4F8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x4F8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x4F8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x4FA "MBCCFR159,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x4FA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x4FA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x4FA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x4FA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x4FA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x4FA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4FC "MBFIDR159,Message Buffer Frame ID Registers" hexmask.word 0x4FC 0.--10. 1. "FID,Frame ID" line.word 0x4FE "MBIDXR159,Message Buffer Index Registers" hexmask.word 0x4FE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x500 "MBCCSR160,Message Buffer Configuratio160. Control and Status Register 160" bitfld.word 0x500 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x500 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x500 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x500 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x500 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x500 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x500 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x500 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x500 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x500 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x502 "MBCCFR160,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x502 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x502 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x502 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x502 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x502 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x502 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x504 "MBFIDR160,Message Buffer Frame ID Registers" hexmask.word 0x504 0.--10. 1. "FID,Frame ID" line.word 0x506 "MBIDXR160,Message Buffer Index Registers" hexmask.word 0x506 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x508 "MBCCSR161,Message Buffer Configuratio161. Control and Status Register 161" bitfld.word 0x508 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x508 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x508 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x508 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x508 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x508 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x508 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x508 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x508 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x508 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x50A "MBCCFR161,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x50A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x50A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x50A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x50A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x50A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x50A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x50C "MBFIDR161,Message Buffer Frame ID Registers" hexmask.word 0x50C 0.--10. 1. "FID,Frame ID" line.word 0x50E "MBIDXR161,Message Buffer Index Registers" hexmask.word 0x50E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x510 "MBCCSR162,Message Buffer Configuratio162. Control and Status Register 162" bitfld.word 0x510 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x510 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x510 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x510 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x510 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x510 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x510 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x510 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x510 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x510 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x512 "MBCCFR162,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x512 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x512 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x512 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x512 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x512 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x512 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x514 "MBFIDR162,Message Buffer Frame ID Registers" hexmask.word 0x514 0.--10. 1. "FID,Frame ID" line.word 0x516 "MBIDXR162,Message Buffer Index Registers" hexmask.word 0x516 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x518 "MBCCSR163,Message Buffer Configuratio163. Control and Status Register 163" bitfld.word 0x518 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x518 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x518 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x518 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x518 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x518 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x518 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x518 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x518 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x518 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x51A "MBCCFR163,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x51A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x51A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x51A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x51A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x51A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x51A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x51C "MBFIDR163,Message Buffer Frame ID Registers" hexmask.word 0x51C 0.--10. 1. "FID,Frame ID" line.word 0x51E "MBIDXR163,Message Buffer Index Registers" hexmask.word 0x51E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x520 "MBCCSR164,Message Buffer Configuratio164. Control and Status Register 164" bitfld.word 0x520 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x520 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x520 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x520 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x520 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x520 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x520 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x520 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x520 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x520 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x522 "MBCCFR164,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x522 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x522 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x522 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x522 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x522 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x522 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x524 "MBFIDR164,Message Buffer Frame ID Registers" hexmask.word 0x524 0.--10. 1. "FID,Frame ID" line.word 0x526 "MBIDXR164,Message Buffer Index Registers" hexmask.word 0x526 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x528 "MBCCSR165,Message Buffer Configuratio165. Control and Status Register 165" bitfld.word 0x528 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x528 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x528 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x528 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x528 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x528 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x528 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x528 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x528 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x528 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x52A "MBCCFR165,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x52A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x52A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x52A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x52A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x52A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x52A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x52C "MBFIDR165,Message Buffer Frame ID Registers" hexmask.word 0x52C 0.--10. 1. "FID,Frame ID" line.word 0x52E "MBIDXR165,Message Buffer Index Registers" hexmask.word 0x52E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x530 "MBCCSR166,Message Buffer Configuratio166. Control and Status Register 166" bitfld.word 0x530 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x530 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x530 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x530 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x530 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x530 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x530 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x530 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x530 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x530 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x532 "MBCCFR166,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x532 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x532 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x532 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x532 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x532 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x532 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x534 "MBFIDR166,Message Buffer Frame ID Registers" hexmask.word 0x534 0.--10. 1. "FID,Frame ID" line.word 0x536 "MBIDXR166,Message Buffer Index Registers" hexmask.word 0x536 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x538 "MBCCSR167,Message Buffer Configuratio167. Control and Status Register 167" bitfld.word 0x538 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x538 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x538 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x538 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x538 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x538 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x538 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x538 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x538 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x538 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x53A "MBCCFR167,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x53A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x53A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x53A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x53A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x53A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x53A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x53C "MBFIDR167,Message Buffer Frame ID Registers" hexmask.word 0x53C 0.--10. 1. "FID,Frame ID" line.word 0x53E "MBIDXR167,Message Buffer Index Registers" hexmask.word 0x53E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x540 "MBCCSR168,Message Buffer Configuratio168. Control and Status Register 168" bitfld.word 0x540 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x540 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x540 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x540 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x540 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x540 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x540 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x540 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x540 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x540 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x542 "MBCCFR168,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x542 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x542 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x542 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x542 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x542 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x542 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x544 "MBFIDR168,Message Buffer Frame ID Registers" hexmask.word 0x544 0.--10. 1. "FID,Frame ID" line.word 0x546 "MBIDXR168,Message Buffer Index Registers" hexmask.word 0x546 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x548 "MBCCSR169,Message Buffer Configuratio169. Control and Status Register 169" bitfld.word 0x548 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x548 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x548 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x548 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x548 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x548 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x548 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x548 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x548 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x548 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x54A "MBCCFR169,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x54A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x54A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x54A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x54A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x54A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x54A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x54C "MBFIDR169,Message Buffer Frame ID Registers" hexmask.word 0x54C 0.--10. 1. "FID,Frame ID" line.word 0x54E "MBIDXR169,Message Buffer Index Registers" hexmask.word 0x54E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x550 "MBCCSR170,Message Buffer Configuratio170. Control and Status Register 170" bitfld.word 0x550 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x550 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x550 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x550 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x550 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x550 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x550 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x550 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x550 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x550 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x552 "MBCCFR170,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x552 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x552 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x552 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x552 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x552 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x552 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x554 "MBFIDR170,Message Buffer Frame ID Registers" hexmask.word 0x554 0.--10. 1. "FID,Frame ID" line.word 0x556 "MBIDXR170,Message Buffer Index Registers" hexmask.word 0x556 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x558 "MBCCSR171,Message Buffer Configuratio171. Control and Status Register 171" bitfld.word 0x558 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x558 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x558 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x558 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x558 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x558 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x558 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x558 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x558 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x558 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x55A "MBCCFR171,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x55A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x55A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x55A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x55A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x55A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x55A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x55C "MBFIDR171,Message Buffer Frame ID Registers" hexmask.word 0x55C 0.--10. 1. "FID,Frame ID" line.word 0x55E "MBIDXR171,Message Buffer Index Registers" hexmask.word 0x55E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x560 "MBCCSR172,Message Buffer Configuratio172. Control and Status Register 172" bitfld.word 0x560 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x560 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x560 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x560 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x560 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x560 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x560 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x560 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x560 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x560 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x562 "MBCCFR172,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x562 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x562 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x562 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x562 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x562 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x562 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x564 "MBFIDR172,Message Buffer Frame ID Registers" hexmask.word 0x564 0.--10. 1. "FID,Frame ID" line.word 0x566 "MBIDXR172,Message Buffer Index Registers" hexmask.word 0x566 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x568 "MBCCSR173,Message Buffer Configuratio173. Control and Status Register 173" bitfld.word 0x568 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x568 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x568 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x568 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x568 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x568 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x568 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x568 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x568 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x568 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x56A "MBCCFR173,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x56A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x56A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x56A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x56A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x56A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x56A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x56C "MBFIDR173,Message Buffer Frame ID Registers" hexmask.word 0x56C 0.--10. 1. "FID,Frame ID" line.word 0x56E "MBIDXR173,Message Buffer Index Registers" hexmask.word 0x56E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x570 "MBCCSR174,Message Buffer Configuratio174. Control and Status Register 174" bitfld.word 0x570 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x570 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x570 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x570 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x570 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x570 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x570 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x570 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x570 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x570 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x572 "MBCCFR174,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x572 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x572 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x572 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x572 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x572 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x572 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x574 "MBFIDR174,Message Buffer Frame ID Registers" hexmask.word 0x574 0.--10. 1. "FID,Frame ID" line.word 0x576 "MBIDXR174,Message Buffer Index Registers" hexmask.word 0x576 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x578 "MBCCSR175,Message Buffer Configuratio175. Control and Status Register 175" bitfld.word 0x578 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x578 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x578 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x578 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x578 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x578 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x578 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x578 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x578 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x578 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x57A "MBCCFR175,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x57A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x57A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x57A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x57A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x57A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x57A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x57C "MBFIDR175,Message Buffer Frame ID Registers" hexmask.word 0x57C 0.--10. 1. "FID,Frame ID" line.word 0x57E "MBIDXR175,Message Buffer Index Registers" hexmask.word 0x57E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x580 "MBCCSR176,Message Buffer Configuratio176. Control and Status Register 176" bitfld.word 0x580 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x580 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x580 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x580 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x580 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x580 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x580 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x580 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x580 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x580 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x582 "MBCCFR176,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x582 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x582 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x582 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x582 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x582 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x582 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x584 "MBFIDR176,Message Buffer Frame ID Registers" hexmask.word 0x584 0.--10. 1. "FID,Frame ID" line.word 0x586 "MBIDXR176,Message Buffer Index Registers" hexmask.word 0x586 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x588 "MBCCSR177,Message Buffer Configuratio177. Control and Status Register 177" bitfld.word 0x588 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x588 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x588 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x588 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x588 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x588 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x588 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x588 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x588 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x588 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x58A "MBCCFR177,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x58A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x58A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x58A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x58A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x58A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x58A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x58C "MBFIDR177,Message Buffer Frame ID Registers" hexmask.word 0x58C 0.--10. 1. "FID,Frame ID" line.word 0x58E "MBIDXR177,Message Buffer Index Registers" hexmask.word 0x58E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x590 "MBCCSR178,Message Buffer Configuratio178. Control and Status Register 178" bitfld.word 0x590 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x590 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x590 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x590 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x590 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x590 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x590 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x590 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x590 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x590 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x592 "MBCCFR178,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x592 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x592 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x592 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x592 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x592 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x592 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x594 "MBFIDR178,Message Buffer Frame ID Registers" hexmask.word 0x594 0.--10. 1. "FID,Frame ID" line.word 0x596 "MBIDXR178,Message Buffer Index Registers" hexmask.word 0x596 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x598 "MBCCSR179,Message Buffer Configuratio179. Control and Status Register 179" bitfld.word 0x598 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x598 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x598 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x598 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x598 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x598 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x598 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x598 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x598 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x598 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x59A "MBCCFR179,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x59A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x59A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x59A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x59A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x59A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x59A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x59C "MBFIDR179,Message Buffer Frame ID Registers" hexmask.word 0x59C 0.--10. 1. "FID,Frame ID" line.word 0x59E "MBIDXR179,Message Buffer Index Registers" hexmask.word 0x59E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5A0 "MBCCSR180,Message Buffer Configuratio180. Control and Status Register 180" bitfld.word 0x5A0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5A0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5A0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5A0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5A0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5A0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5A0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5A0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5A0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5A0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5A2 "MBCCFR180,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5A2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5A2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5A2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5A2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5A2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5A2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5A4 "MBFIDR180,Message Buffer Frame ID Registers" hexmask.word 0x5A4 0.--10. 1. "FID,Frame ID" line.word 0x5A6 "MBIDXR180,Message Buffer Index Registers" hexmask.word 0x5A6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5A8 "MBCCSR181,Message Buffer Configuratio181. Control and Status Register 181" bitfld.word 0x5A8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5A8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5A8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5A8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5A8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5A8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5A8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5A8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5A8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5A8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5AA "MBCCFR181,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5AA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5AA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5AA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5AA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5AA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5AA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5AC "MBFIDR181,Message Buffer Frame ID Registers" hexmask.word 0x5AC 0.--10. 1. "FID,Frame ID" line.word 0x5AE "MBIDXR181,Message Buffer Index Registers" hexmask.word 0x5AE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5B0 "MBCCSR182,Message Buffer Configuratio182. Control and Status Register 182" bitfld.word 0x5B0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5B0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5B0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5B0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5B0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5B0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5B0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5B0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5B0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5B0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5B2 "MBCCFR182,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5B2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5B2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5B2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5B2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5B2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5B2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5B4 "MBFIDR182,Message Buffer Frame ID Registers" hexmask.word 0x5B4 0.--10. 1. "FID,Frame ID" line.word 0x5B6 "MBIDXR182,Message Buffer Index Registers" hexmask.word 0x5B6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5B8 "MBCCSR183,Message Buffer Configuratio183. Control and Status Register 183" bitfld.word 0x5B8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5B8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5B8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5B8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5B8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5B8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5B8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5B8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5B8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5B8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5BA "MBCCFR183,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5BA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5BA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5BA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5BA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5BA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5BA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5BC "MBFIDR183,Message Buffer Frame ID Registers" hexmask.word 0x5BC 0.--10. 1. "FID,Frame ID" line.word 0x5BE "MBIDXR183,Message Buffer Index Registers" hexmask.word 0x5BE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5C0 "MBCCSR184,Message Buffer Configuratio184. Control and Status Register 184" bitfld.word 0x5C0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5C0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5C0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5C0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5C0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5C0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5C0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5C0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5C0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5C0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5C2 "MBCCFR184,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5C2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5C2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5C2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5C2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5C2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5C2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5C4 "MBFIDR184,Message Buffer Frame ID Registers" hexmask.word 0x5C4 0.--10. 1. "FID,Frame ID" line.word 0x5C6 "MBIDXR184,Message Buffer Index Registers" hexmask.word 0x5C6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5C8 "MBCCSR185,Message Buffer Configuratio185. Control and Status Register 185" bitfld.word 0x5C8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5C8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5C8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5C8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5C8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5C8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5C8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5C8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5C8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5C8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5CA "MBCCFR185,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5CA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5CA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5CA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5CA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5CA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5CA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5CC "MBFIDR185,Message Buffer Frame ID Registers" hexmask.word 0x5CC 0.--10. 1. "FID,Frame ID" line.word 0x5CE "MBIDXR185,Message Buffer Index Registers" hexmask.word 0x5CE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5D0 "MBCCSR186,Message Buffer Configuratio186. Control and Status Register 186" bitfld.word 0x5D0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5D0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5D0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5D0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5D0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5D0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5D0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5D0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5D0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5D0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5D2 "MBCCFR186,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5D2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5D2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5D2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5D2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5D2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5D2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5D4 "MBFIDR186,Message Buffer Frame ID Registers" hexmask.word 0x5D4 0.--10. 1. "FID,Frame ID" line.word 0x5D6 "MBIDXR186,Message Buffer Index Registers" hexmask.word 0x5D6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5D8 "MBCCSR187,Message Buffer Configuratio187. Control and Status Register 187" bitfld.word 0x5D8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5D8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5D8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5D8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5D8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5D8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5D8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5D8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5D8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5D8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5DA "MBCCFR187,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5DA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5DA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5DA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5DA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5DA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5DA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5DC "MBFIDR187,Message Buffer Frame ID Registers" hexmask.word 0x5DC 0.--10. 1. "FID,Frame ID" line.word 0x5DE "MBIDXR187,Message Buffer Index Registers" hexmask.word 0x5DE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5E0 "MBCCSR188,Message Buffer Configuratio188. Control and Status Register 188" bitfld.word 0x5E0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5E0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5E0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5E0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5E0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5E0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5E0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5E0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5E0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5E0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5E2 "MBCCFR188,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5E2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5E2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5E2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5E2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5E2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5E2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5E4 "MBFIDR188,Message Buffer Frame ID Registers" hexmask.word 0x5E4 0.--10. 1. "FID,Frame ID" line.word 0x5E6 "MBIDXR188,Message Buffer Index Registers" hexmask.word 0x5E6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5E8 "MBCCSR189,Message Buffer Configuratio189. Control and Status Register 189" bitfld.word 0x5E8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5E8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5E8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5E8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5E8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5E8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5E8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5E8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5E8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5E8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5EA "MBCCFR189,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5EA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5EA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5EA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5EA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5EA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5EA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5EC "MBFIDR189,Message Buffer Frame ID Registers" hexmask.word 0x5EC 0.--10. 1. "FID,Frame ID" line.word 0x5EE "MBIDXR189,Message Buffer Index Registers" hexmask.word 0x5EE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5F0 "MBCCSR190,Message Buffer Configuratio190. Control and Status Register 190" bitfld.word 0x5F0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5F0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5F0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5F0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5F0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5F0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5F0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5F0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5F0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5F0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5F2 "MBCCFR190,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5F2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5F2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5F2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5F2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5F2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5F2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5F4 "MBFIDR190,Message Buffer Frame ID Registers" hexmask.word 0x5F4 0.--10. 1. "FID,Frame ID" line.word 0x5F6 "MBIDXR190,Message Buffer Index Registers" hexmask.word 0x5F6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x5F8 "MBCCSR191,Message Buffer Configuratio191. Control and Status Register 191" bitfld.word 0x5F8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x5F8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x5F8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x5F8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x5F8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x5F8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x5F8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x5F8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x5F8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x5F8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x5FA "MBCCFR191,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x5FA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x5FA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x5FA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x5FA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x5FA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x5FA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x5FC "MBFIDR191,Message Buffer Frame ID Registers" hexmask.word 0x5FC 0.--10. 1. "FID,Frame ID" line.word 0x5FE "MBIDXR191,Message Buffer Index Registers" hexmask.word 0x5FE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x600 "MBCCSR192,Message Buffer Configuratio192. Control and Status Register 192" bitfld.word 0x600 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x600 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x600 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x600 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x600 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x600 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x600 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x600 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x600 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x600 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x602 "MBCCFR192,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x602 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x602 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x602 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x602 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x602 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x602 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x604 "MBFIDR192,Message Buffer Frame ID Registers" hexmask.word 0x604 0.--10. 1. "FID,Frame ID" line.word 0x606 "MBIDXR192,Message Buffer Index Registers" hexmask.word 0x606 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x608 "MBCCSR193,Message Buffer Configuratio193. Control and Status Register 193" bitfld.word 0x608 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x608 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x608 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x608 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x608 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x608 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x608 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x608 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x608 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x608 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x60A "MBCCFR193,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x60A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x60A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x60A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x60A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x60A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x60A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x60C "MBFIDR193,Message Buffer Frame ID Registers" hexmask.word 0x60C 0.--10. 1. "FID,Frame ID" line.word 0x60E "MBIDXR193,Message Buffer Index Registers" hexmask.word 0x60E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x610 "MBCCSR194,Message Buffer Configuratio194. Control and Status Register 194" bitfld.word 0x610 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x610 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x610 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x610 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x610 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x610 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x610 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x610 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x610 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x610 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x612 "MBCCFR194,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x612 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x612 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x612 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x612 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x612 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x612 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x614 "MBFIDR194,Message Buffer Frame ID Registers" hexmask.word 0x614 0.--10. 1. "FID,Frame ID" line.word 0x616 "MBIDXR194,Message Buffer Index Registers" hexmask.word 0x616 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x618 "MBCCSR195,Message Buffer Configuratio195. Control and Status Register 195" bitfld.word 0x618 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x618 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x618 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x618 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x618 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x618 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x618 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x618 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x618 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x618 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x61A "MBCCFR195,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x61A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x61A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x61A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x61A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x61A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x61A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x61C "MBFIDR195,Message Buffer Frame ID Registers" hexmask.word 0x61C 0.--10. 1. "FID,Frame ID" line.word 0x61E "MBIDXR195,Message Buffer Index Registers" hexmask.word 0x61E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x620 "MBCCSR196,Message Buffer Configuratio196. Control and Status Register 196" bitfld.word 0x620 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x620 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x620 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x620 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x620 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x620 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x620 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x620 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x620 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x620 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x622 "MBCCFR196,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x622 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x622 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x622 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x622 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x622 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x622 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x624 "MBFIDR196,Message Buffer Frame ID Registers" hexmask.word 0x624 0.--10. 1. "FID,Frame ID" line.word 0x626 "MBIDXR196,Message Buffer Index Registers" hexmask.word 0x626 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x628 "MBCCSR197,Message Buffer Configuratio197. Control and Status Register 197" bitfld.word 0x628 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x628 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x628 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x628 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x628 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x628 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x628 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x628 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x628 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x628 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x62A "MBCCFR197,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x62A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x62A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x62A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x62A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x62A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x62A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x62C "MBFIDR197,Message Buffer Frame ID Registers" hexmask.word 0x62C 0.--10. 1. "FID,Frame ID" line.word 0x62E "MBIDXR197,Message Buffer Index Registers" hexmask.word 0x62E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x630 "MBCCSR198,Message Buffer Configuratio198. Control and Status Register 198" bitfld.word 0x630 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x630 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x630 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x630 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x630 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x630 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x630 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x630 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x630 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x630 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x632 "MBCCFR198,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x632 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x632 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x632 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x632 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x632 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x632 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x634 "MBFIDR198,Message Buffer Frame ID Registers" hexmask.word 0x634 0.--10. 1. "FID,Frame ID" line.word 0x636 "MBIDXR198,Message Buffer Index Registers" hexmask.word 0x636 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x638 "MBCCSR199,Message Buffer Configuratio199. Control and Status Register 199" bitfld.word 0x638 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x638 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x638 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x638 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x638 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x638 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x638 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x638 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x638 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x638 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x63A "MBCCFR199,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x63A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x63A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x63A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x63A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x63A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x63A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x63C "MBFIDR199,Message Buffer Frame ID Registers" hexmask.word 0x63C 0.--10. 1. "FID,Frame ID" line.word 0x63E "MBIDXR199,Message Buffer Index Registers" hexmask.word 0x63E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x640 "MBCCSR200,Message Buffer Configuratio200. Control and Status Register 200" bitfld.word 0x640 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x640 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x640 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x640 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x640 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x640 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x640 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x640 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x640 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x640 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x642 "MBCCFR200,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x642 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x642 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x642 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x642 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x642 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x642 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x644 "MBFIDR200,Message Buffer Frame ID Registers" hexmask.word 0x644 0.--10. 1. "FID,Frame ID" line.word 0x646 "MBIDXR200,Message Buffer Index Registers" hexmask.word 0x646 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x648 "MBCCSR201,Message Buffer Configuratio201. Control and Status Register 201" bitfld.word 0x648 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x648 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x648 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x648 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x648 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x648 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x648 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x648 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x648 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x648 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x64A "MBCCFR201,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x64A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x64A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x64A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x64A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x64A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x64A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x64C "MBFIDR201,Message Buffer Frame ID Registers" hexmask.word 0x64C 0.--10. 1. "FID,Frame ID" line.word 0x64E "MBIDXR201,Message Buffer Index Registers" hexmask.word 0x64E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x650 "MBCCSR202,Message Buffer Configuratio202. Control and Status Register 202" bitfld.word 0x650 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x650 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x650 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x650 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x650 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x650 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x650 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x650 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x650 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x650 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x652 "MBCCFR202,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x652 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x652 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x652 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x652 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x652 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x652 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x654 "MBFIDR202,Message Buffer Frame ID Registers" hexmask.word 0x654 0.--10. 1. "FID,Frame ID" line.word 0x656 "MBIDXR202,Message Buffer Index Registers" hexmask.word 0x656 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x658 "MBCCSR203,Message Buffer Configuratio203. Control and Status Register 203" bitfld.word 0x658 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x658 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x658 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x658 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x658 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x658 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x658 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x658 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x658 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x658 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x65A "MBCCFR203,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x65A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x65A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x65A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x65A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x65A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x65A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x65C "MBFIDR203,Message Buffer Frame ID Registers" hexmask.word 0x65C 0.--10. 1. "FID,Frame ID" line.word 0x65E "MBIDXR203,Message Buffer Index Registers" hexmask.word 0x65E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x660 "MBCCSR204,Message Buffer Configuratio204. Control and Status Register 204" bitfld.word 0x660 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x660 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x660 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x660 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x660 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x660 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x660 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x660 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x660 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x660 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x662 "MBCCFR204,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x662 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x662 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x662 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x662 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x662 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x662 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x664 "MBFIDR204,Message Buffer Frame ID Registers" hexmask.word 0x664 0.--10. 1. "FID,Frame ID" line.word 0x666 "MBIDXR204,Message Buffer Index Registers" hexmask.word 0x666 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x668 "MBCCSR205,Message Buffer Configuratio205. Control and Status Register 205" bitfld.word 0x668 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x668 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x668 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x668 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x668 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x668 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x668 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x668 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x668 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x668 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x66A "MBCCFR205,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x66A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x66A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x66A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x66A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x66A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x66A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x66C "MBFIDR205,Message Buffer Frame ID Registers" hexmask.word 0x66C 0.--10. 1. "FID,Frame ID" line.word 0x66E "MBIDXR205,Message Buffer Index Registers" hexmask.word 0x66E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x670 "MBCCSR206,Message Buffer Configuratio206. Control and Status Register 206" bitfld.word 0x670 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x670 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x670 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x670 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x670 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x670 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x670 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x670 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x670 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x670 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x672 "MBCCFR206,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x672 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x672 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x672 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x672 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x672 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x672 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x674 "MBFIDR206,Message Buffer Frame ID Registers" hexmask.word 0x674 0.--10. 1. "FID,Frame ID" line.word 0x676 "MBIDXR206,Message Buffer Index Registers" hexmask.word 0x676 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x678 "MBCCSR207,Message Buffer Configuratio207. Control and Status Register 207" bitfld.word 0x678 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x678 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x678 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x678 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x678 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x678 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x678 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x678 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x678 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x678 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x67A "MBCCFR207,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x67A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x67A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x67A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x67A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x67A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x67A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x67C "MBFIDR207,Message Buffer Frame ID Registers" hexmask.word 0x67C 0.--10. 1. "FID,Frame ID" line.word 0x67E "MBIDXR207,Message Buffer Index Registers" hexmask.word 0x67E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x680 "MBCCSR208,Message Buffer Configuratio208. Control and Status Register 208" bitfld.word 0x680 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x680 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x680 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x680 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x680 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x680 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x680 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x680 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x680 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x680 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x682 "MBCCFR208,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x682 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x682 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x682 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x682 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x682 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x682 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x684 "MBFIDR208,Message Buffer Frame ID Registers" hexmask.word 0x684 0.--10. 1. "FID,Frame ID" line.word 0x686 "MBIDXR208,Message Buffer Index Registers" hexmask.word 0x686 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x688 "MBCCSR209,Message Buffer Configuratio209. Control and Status Register 209" bitfld.word 0x688 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x688 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x688 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x688 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x688 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x688 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x688 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x688 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x688 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x688 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x68A "MBCCFR209,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x68A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x68A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x68A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x68A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x68A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x68A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x68C "MBFIDR209,Message Buffer Frame ID Registers" hexmask.word 0x68C 0.--10. 1. "FID,Frame ID" line.word 0x68E "MBIDXR209,Message Buffer Index Registers" hexmask.word 0x68E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x690 "MBCCSR210,Message Buffer Configuratio210. Control and Status Register 210" bitfld.word 0x690 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x690 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x690 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x690 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x690 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x690 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x690 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x690 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x690 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x690 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x692 "MBCCFR210,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x692 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x692 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x692 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x692 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x692 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x692 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x694 "MBFIDR210,Message Buffer Frame ID Registers" hexmask.word 0x694 0.--10. 1. "FID,Frame ID" line.word 0x696 "MBIDXR210,Message Buffer Index Registers" hexmask.word 0x696 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x698 "MBCCSR211,Message Buffer Configuratio211. Control and Status Register 211" bitfld.word 0x698 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x698 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x698 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x698 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x698 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x698 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x698 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x698 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x698 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x698 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x69A "MBCCFR211,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x69A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x69A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x69A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x69A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x69A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x69A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x69C "MBFIDR211,Message Buffer Frame ID Registers" hexmask.word 0x69C 0.--10. 1. "FID,Frame ID" line.word 0x69E "MBIDXR211,Message Buffer Index Registers" hexmask.word 0x69E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6A0 "MBCCSR212,Message Buffer Configuratio212. Control and Status Register 212" bitfld.word 0x6A0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6A0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6A0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6A0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6A0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6A0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6A0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6A0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6A0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6A0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6A2 "MBCCFR212,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6A2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6A2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6A2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6A2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6A2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6A2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6A4 "MBFIDR212,Message Buffer Frame ID Registers" hexmask.word 0x6A4 0.--10. 1. "FID,Frame ID" line.word 0x6A6 "MBIDXR212,Message Buffer Index Registers" hexmask.word 0x6A6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6A8 "MBCCSR213,Message Buffer Configuratio213. Control and Status Register 213" bitfld.word 0x6A8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6A8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6A8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6A8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6A8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6A8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6A8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6A8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6A8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6A8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6AA "MBCCFR213,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6AA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6AA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6AA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6AA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6AA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6AA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6AC "MBFIDR213,Message Buffer Frame ID Registers" hexmask.word 0x6AC 0.--10. 1. "FID,Frame ID" line.word 0x6AE "MBIDXR213,Message Buffer Index Registers" hexmask.word 0x6AE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6B0 "MBCCSR214,Message Buffer Configuratio214. Control and Status Register 214" bitfld.word 0x6B0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6B0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6B0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6B0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6B0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6B0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6B0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6B0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6B0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6B0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6B2 "MBCCFR214,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6B2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6B2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6B2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6B2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6B2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6B2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6B4 "MBFIDR214,Message Buffer Frame ID Registers" hexmask.word 0x6B4 0.--10. 1. "FID,Frame ID" line.word 0x6B6 "MBIDXR214,Message Buffer Index Registers" hexmask.word 0x6B6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6B8 "MBCCSR215,Message Buffer Configuratio215. Control and Status Register 215" bitfld.word 0x6B8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6B8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6B8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6B8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6B8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6B8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6B8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6B8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6B8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6B8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6BA "MBCCFR215,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6BA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6BA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6BA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6BA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6BA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6BA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6BC "MBFIDR215,Message Buffer Frame ID Registers" hexmask.word 0x6BC 0.--10. 1. "FID,Frame ID" line.word 0x6BE "MBIDXR215,Message Buffer Index Registers" hexmask.word 0x6BE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6C0 "MBCCSR216,Message Buffer Configuratio216. Control and Status Register 216" bitfld.word 0x6C0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6C0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6C0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6C0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6C0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6C0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6C0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6C0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6C0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6C0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6C2 "MBCCFR216,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6C2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6C2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6C2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6C2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6C2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6C2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6C4 "MBFIDR216,Message Buffer Frame ID Registers" hexmask.word 0x6C4 0.--10. 1. "FID,Frame ID" line.word 0x6C6 "MBIDXR216,Message Buffer Index Registers" hexmask.word 0x6C6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6C8 "MBCCSR217,Message Buffer Configuratio217. Control and Status Register 217" bitfld.word 0x6C8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6C8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6C8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6C8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6C8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6C8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6C8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6C8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6C8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6C8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6CA "MBCCFR217,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6CA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6CA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6CA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6CA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6CA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6CA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6CC "MBFIDR217,Message Buffer Frame ID Registers" hexmask.word 0x6CC 0.--10. 1. "FID,Frame ID" line.word 0x6CE "MBIDXR217,Message Buffer Index Registers" hexmask.word 0x6CE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6D0 "MBCCSR218,Message Buffer Configuratio218. Control and Status Register 218" bitfld.word 0x6D0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6D0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6D0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6D0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6D0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6D0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6D0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6D0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6D0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6D0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6D2 "MBCCFR218,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6D2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6D2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6D2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6D2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6D2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6D2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6D4 "MBFIDR218,Message Buffer Frame ID Registers" hexmask.word 0x6D4 0.--10. 1. "FID,Frame ID" line.word 0x6D6 "MBIDXR218,Message Buffer Index Registers" hexmask.word 0x6D6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6D8 "MBCCSR219,Message Buffer Configuratio219. Control and Status Register 219" bitfld.word 0x6D8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6D8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6D8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6D8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6D8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6D8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6D8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6D8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6D8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6D8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6DA "MBCCFR219,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6DA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6DA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6DA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6DA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6DA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6DA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6DC "MBFIDR219,Message Buffer Frame ID Registers" hexmask.word 0x6DC 0.--10. 1. "FID,Frame ID" line.word 0x6DE "MBIDXR219,Message Buffer Index Registers" hexmask.word 0x6DE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6E0 "MBCCSR220,Message Buffer Configuratio220. Control and Status Register 220" bitfld.word 0x6E0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6E0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6E0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6E0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6E0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6E0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6E0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6E0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6E0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6E0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6E2 "MBCCFR220,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6E2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6E2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6E2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6E2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6E2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6E2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6E4 "MBFIDR220,Message Buffer Frame ID Registers" hexmask.word 0x6E4 0.--10. 1. "FID,Frame ID" line.word 0x6E6 "MBIDXR220,Message Buffer Index Registers" hexmask.word 0x6E6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6E8 "MBCCSR221,Message Buffer Configuratio221. Control and Status Register 221" bitfld.word 0x6E8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6E8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6E8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6E8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6E8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6E8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6E8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6E8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6E8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6E8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6EA "MBCCFR221,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6EA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6EA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6EA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6EA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6EA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6EA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6EC "MBFIDR221,Message Buffer Frame ID Registers" hexmask.word 0x6EC 0.--10. 1. "FID,Frame ID" line.word 0x6EE "MBIDXR221,Message Buffer Index Registers" hexmask.word 0x6EE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6F0 "MBCCSR222,Message Buffer Configuratio222. Control and Status Register 222" bitfld.word 0x6F0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6F0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6F0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6F0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6F0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6F0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6F0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6F0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6F0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6F0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6F2 "MBCCFR222,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6F2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6F2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6F2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6F2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6F2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6F2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6F4 "MBFIDR222,Message Buffer Frame ID Registers" hexmask.word 0x6F4 0.--10. 1. "FID,Frame ID" line.word 0x6F6 "MBIDXR222,Message Buffer Index Registers" hexmask.word 0x6F6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x6F8 "MBCCSR223,Message Buffer Configuratio223. Control and Status Register 223" bitfld.word 0x6F8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x6F8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x6F8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x6F8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x6F8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x6F8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x6F8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x6F8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x6F8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x6F8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x6FA "MBCCFR223,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x6FA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x6FA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x6FA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x6FA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x6FA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x6FA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x6FC "MBFIDR223,Message Buffer Frame ID Registers" hexmask.word 0x6FC 0.--10. 1. "FID,Frame ID" line.word 0x6FE "MBIDXR223,Message Buffer Index Registers" hexmask.word 0x6FE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x700 "MBCCSR224,Message Buffer Configuratio224. Control and Status Register 224" bitfld.word 0x700 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x700 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x700 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x700 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x700 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x700 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x700 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x700 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x700 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x700 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x702 "MBCCFR224,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x702 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x702 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x702 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x702 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x702 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x702 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x704 "MBFIDR224,Message Buffer Frame ID Registers" hexmask.word 0x704 0.--10. 1. "FID,Frame ID" line.word 0x706 "MBIDXR224,Message Buffer Index Registers" hexmask.word 0x706 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x708 "MBCCSR225,Message Buffer Configuratio225. Control and Status Register 225" bitfld.word 0x708 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x708 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x708 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x708 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x708 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x708 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x708 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x708 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x708 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x708 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x70A "MBCCFR225,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x70A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x70A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x70A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x70A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x70A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x70A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x70C "MBFIDR225,Message Buffer Frame ID Registers" hexmask.word 0x70C 0.--10. 1. "FID,Frame ID" line.word 0x70E "MBIDXR225,Message Buffer Index Registers" hexmask.word 0x70E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x710 "MBCCSR226,Message Buffer Configuratio226. Control and Status Register 226" bitfld.word 0x710 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x710 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x710 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x710 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x710 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x710 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x710 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x710 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x710 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x710 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x712 "MBCCFR226,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x712 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x712 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x712 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x712 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x712 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x712 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x714 "MBFIDR226,Message Buffer Frame ID Registers" hexmask.word 0x714 0.--10. 1. "FID,Frame ID" line.word 0x716 "MBIDXR226,Message Buffer Index Registers" hexmask.word 0x716 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x718 "MBCCSR227,Message Buffer Configuratio227. Control and Status Register 227" bitfld.word 0x718 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x718 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x718 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x718 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x718 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x718 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x718 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x718 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x718 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x718 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x71A "MBCCFR227,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x71A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x71A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x71A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x71A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x71A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x71A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x71C "MBFIDR227,Message Buffer Frame ID Registers" hexmask.word 0x71C 0.--10. 1. "FID,Frame ID" line.word 0x71E "MBIDXR227,Message Buffer Index Registers" hexmask.word 0x71E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x720 "MBCCSR228,Message Buffer Configuratio228. Control and Status Register 228" bitfld.word 0x720 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x720 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x720 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x720 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x720 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x720 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x720 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x720 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x720 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x720 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x722 "MBCCFR228,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x722 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x722 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x722 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x722 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x722 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x722 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x724 "MBFIDR228,Message Buffer Frame ID Registers" hexmask.word 0x724 0.--10. 1. "FID,Frame ID" line.word 0x726 "MBIDXR228,Message Buffer Index Registers" hexmask.word 0x726 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x728 "MBCCSR229,Message Buffer Configuratio229. Control and Status Register 229" bitfld.word 0x728 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x728 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x728 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x728 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x728 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x728 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x728 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x728 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x728 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x728 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x72A "MBCCFR229,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x72A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x72A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x72A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x72A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x72A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x72A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x72C "MBFIDR229,Message Buffer Frame ID Registers" hexmask.word 0x72C 0.--10. 1. "FID,Frame ID" line.word 0x72E "MBIDXR229,Message Buffer Index Registers" hexmask.word 0x72E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x730 "MBCCSR230,Message Buffer Configuratio230. Control and Status Register 230" bitfld.word 0x730 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x730 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x730 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x730 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x730 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x730 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x730 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x730 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x730 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x730 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x732 "MBCCFR230,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x732 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x732 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x732 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x732 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x732 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x732 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x734 "MBFIDR230,Message Buffer Frame ID Registers" hexmask.word 0x734 0.--10. 1. "FID,Frame ID" line.word 0x736 "MBIDXR230,Message Buffer Index Registers" hexmask.word 0x736 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x738 "MBCCSR231,Message Buffer Configuratio231. Control and Status Register 231" bitfld.word 0x738 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x738 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x738 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x738 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x738 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x738 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x738 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x738 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x738 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x738 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x73A "MBCCFR231,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x73A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x73A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x73A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x73A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x73A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x73A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x73C "MBFIDR231,Message Buffer Frame ID Registers" hexmask.word 0x73C 0.--10. 1. "FID,Frame ID" line.word 0x73E "MBIDXR231,Message Buffer Index Registers" hexmask.word 0x73E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x740 "MBCCSR232,Message Buffer Configuratio232. Control and Status Register 232" bitfld.word 0x740 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x740 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x740 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x740 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x740 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x740 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x740 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x740 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x740 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x740 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x742 "MBCCFR232,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x742 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x742 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x742 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x742 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x742 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x742 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x744 "MBFIDR232,Message Buffer Frame ID Registers" hexmask.word 0x744 0.--10. 1. "FID,Frame ID" line.word 0x746 "MBIDXR232,Message Buffer Index Registers" hexmask.word 0x746 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x748 "MBCCSR233,Message Buffer Configuratio233. Control and Status Register 233" bitfld.word 0x748 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x748 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x748 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x748 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x748 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x748 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x748 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x748 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x748 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x748 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x74A "MBCCFR233,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x74A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x74A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x74A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x74A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x74A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x74A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x74C "MBFIDR233,Message Buffer Frame ID Registers" hexmask.word 0x74C 0.--10. 1. "FID,Frame ID" line.word 0x74E "MBIDXR233,Message Buffer Index Registers" hexmask.word 0x74E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x750 "MBCCSR234,Message Buffer Configuratio234. Control and Status Register 234" bitfld.word 0x750 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x750 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x750 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x750 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x750 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x750 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x750 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x750 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x750 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x750 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x752 "MBCCFR234,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x752 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x752 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x752 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x752 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x752 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x752 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x754 "MBFIDR234,Message Buffer Frame ID Registers" hexmask.word 0x754 0.--10. 1. "FID,Frame ID" line.word 0x756 "MBIDXR234,Message Buffer Index Registers" hexmask.word 0x756 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x758 "MBCCSR235,Message Buffer Configuratio235. Control and Status Register 235" bitfld.word 0x758 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x758 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x758 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x758 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x758 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x758 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x758 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x758 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x758 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x758 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x75A "MBCCFR235,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x75A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x75A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x75A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x75A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x75A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x75A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x75C "MBFIDR235,Message Buffer Frame ID Registers" hexmask.word 0x75C 0.--10. 1. "FID,Frame ID" line.word 0x75E "MBIDXR235,Message Buffer Index Registers" hexmask.word 0x75E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x760 "MBCCSR236,Message Buffer Configuratio236. Control and Status Register 236" bitfld.word 0x760 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x760 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x760 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x760 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x760 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x760 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x760 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x760 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x760 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x760 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x762 "MBCCFR236,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x762 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x762 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x762 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x762 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x762 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x762 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x764 "MBFIDR236,Message Buffer Frame ID Registers" hexmask.word 0x764 0.--10. 1. "FID,Frame ID" line.word 0x766 "MBIDXR236,Message Buffer Index Registers" hexmask.word 0x766 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x768 "MBCCSR237,Message Buffer Configuratio237. Control and Status Register 237" bitfld.word 0x768 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x768 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x768 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x768 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x768 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x768 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x768 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x768 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x768 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x768 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x76A "MBCCFR237,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x76A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x76A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x76A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x76A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x76A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x76A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x76C "MBFIDR237,Message Buffer Frame ID Registers" hexmask.word 0x76C 0.--10. 1. "FID,Frame ID" line.word 0x76E "MBIDXR237,Message Buffer Index Registers" hexmask.word 0x76E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x770 "MBCCSR238,Message Buffer Configuratio238. Control and Status Register 238" bitfld.word 0x770 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x770 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x770 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x770 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x770 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x770 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x770 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x770 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x770 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x770 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x772 "MBCCFR238,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x772 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x772 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x772 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x772 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x772 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x772 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x774 "MBFIDR238,Message Buffer Frame ID Registers" hexmask.word 0x774 0.--10. 1. "FID,Frame ID" line.word 0x776 "MBIDXR238,Message Buffer Index Registers" hexmask.word 0x776 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x778 "MBCCSR239,Message Buffer Configuratio239. Control and Status Register 239" bitfld.word 0x778 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x778 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x778 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x778 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x778 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x778 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x778 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x778 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x778 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x778 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x77A "MBCCFR239,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x77A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x77A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x77A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x77A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x77A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x77A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x77C "MBFIDR239,Message Buffer Frame ID Registers" hexmask.word 0x77C 0.--10. 1. "FID,Frame ID" line.word 0x77E "MBIDXR239,Message Buffer Index Registers" hexmask.word 0x77E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x780 "MBCCSR240,Message Buffer Configuratio240. Control and Status Register 240" bitfld.word 0x780 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x780 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x780 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x780 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x780 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x780 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x780 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x780 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x780 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x780 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x782 "MBCCFR240,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x782 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x782 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x782 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x782 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x782 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x782 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x784 "MBFIDR240,Message Buffer Frame ID Registers" hexmask.word 0x784 0.--10. 1. "FID,Frame ID" line.word 0x786 "MBIDXR240,Message Buffer Index Registers" hexmask.word 0x786 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x788 "MBCCSR241,Message Buffer Configuratio241. Control and Status Register 241" bitfld.word 0x788 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x788 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x788 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x788 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x788 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x788 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x788 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x788 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x788 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x788 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x78A "MBCCFR241,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x78A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x78A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x78A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x78A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x78A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x78A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x78C "MBFIDR241,Message Buffer Frame ID Registers" hexmask.word 0x78C 0.--10. 1. "FID,Frame ID" line.word 0x78E "MBIDXR241,Message Buffer Index Registers" hexmask.word 0x78E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x790 "MBCCSR242,Message Buffer Configuratio242. Control and Status Register 242" bitfld.word 0x790 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x790 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x790 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x790 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x790 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x790 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x790 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x790 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x790 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x790 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x792 "MBCCFR242,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x792 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x792 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x792 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x792 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x792 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x792 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x794 "MBFIDR242,Message Buffer Frame ID Registers" hexmask.word 0x794 0.--10. 1. "FID,Frame ID" line.word 0x796 "MBIDXR242,Message Buffer Index Registers" hexmask.word 0x796 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x798 "MBCCSR243,Message Buffer Configuratio243. Control and Status Register 243" bitfld.word 0x798 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x798 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x798 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x798 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x798 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x798 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x798 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x798 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x798 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x798 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x79A "MBCCFR243,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x79A 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x79A 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x79A 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x79A 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x79A 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x79A 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x79C "MBFIDR243,Message Buffer Frame ID Registers" hexmask.word 0x79C 0.--10. 1. "FID,Frame ID" line.word 0x79E "MBIDXR243,Message Buffer Index Registers" hexmask.word 0x79E 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7A0 "MBCCSR244,Message Buffer Configuratio244. Control and Status Register 244" bitfld.word 0x7A0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7A0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7A0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7A0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7A0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7A0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7A0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7A0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7A0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7A0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7A2 "MBCCFR244,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7A2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7A2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7A2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7A2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7A2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7A2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7A4 "MBFIDR244,Message Buffer Frame ID Registers" hexmask.word 0x7A4 0.--10. 1. "FID,Frame ID" line.word 0x7A6 "MBIDXR244,Message Buffer Index Registers" hexmask.word 0x7A6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7A8 "MBCCSR245,Message Buffer Configuratio245. Control and Status Register 245" bitfld.word 0x7A8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7A8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7A8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7A8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7A8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7A8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7A8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7A8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7A8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7A8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7AA "MBCCFR245,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7AA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7AA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7AA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7AA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7AA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7AA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7AC "MBFIDR245,Message Buffer Frame ID Registers" hexmask.word 0x7AC 0.--10. 1. "FID,Frame ID" line.word 0x7AE "MBIDXR245,Message Buffer Index Registers" hexmask.word 0x7AE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7B0 "MBCCSR246,Message Buffer Configuratio246. Control and Status Register 246" bitfld.word 0x7B0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7B0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7B0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7B0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7B0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7B0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7B0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7B0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7B0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7B0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7B2 "MBCCFR246,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7B2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7B2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7B2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7B2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7B2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7B2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7B4 "MBFIDR246,Message Buffer Frame ID Registers" hexmask.word 0x7B4 0.--10. 1. "FID,Frame ID" line.word 0x7B6 "MBIDXR246,Message Buffer Index Registers" hexmask.word 0x7B6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7B8 "MBCCSR247,Message Buffer Configuratio247. Control and Status Register 247" bitfld.word 0x7B8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7B8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7B8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7B8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7B8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7B8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7B8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7B8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7B8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7B8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7BA "MBCCFR247,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7BA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7BA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7BA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7BA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7BA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7BA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7BC "MBFIDR247,Message Buffer Frame ID Registers" hexmask.word 0x7BC 0.--10. 1. "FID,Frame ID" line.word 0x7BE "MBIDXR247,Message Buffer Index Registers" hexmask.word 0x7BE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7C0 "MBCCSR248,Message Buffer Configuratio248. Control and Status Register 248" bitfld.word 0x7C0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7C0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7C0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7C0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7C0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7C0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7C0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7C0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7C0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7C0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7C2 "MBCCFR248,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7C2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7C2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7C2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7C2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7C2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7C2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7C4 "MBFIDR248,Message Buffer Frame ID Registers" hexmask.word 0x7C4 0.--10. 1. "FID,Frame ID" line.word 0x7C6 "MBIDXR248,Message Buffer Index Registers" hexmask.word 0x7C6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7C8 "MBCCSR249,Message Buffer Configuratio249. Control and Status Register 249" bitfld.word 0x7C8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7C8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7C8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7C8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7C8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7C8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7C8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7C8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7C8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7C8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7CA "MBCCFR249,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7CA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7CA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7CA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7CA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7CA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7CA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7CC "MBFIDR249,Message Buffer Frame ID Registers" hexmask.word 0x7CC 0.--10. 1. "FID,Frame ID" line.word 0x7CE "MBIDXR249,Message Buffer Index Registers" hexmask.word 0x7CE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7D0 "MBCCSR250,Message Buffer Configuratio250. Control and Status Register 250" bitfld.word 0x7D0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7D0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7D0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7D0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7D0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7D0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7D0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7D0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7D0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7D0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7D2 "MBCCFR250,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7D2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7D2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7D2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7D2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7D2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7D2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7D4 "MBFIDR250,Message Buffer Frame ID Registers" hexmask.word 0x7D4 0.--10. 1. "FID,Frame ID" line.word 0x7D6 "MBIDXR250,Message Buffer Index Registers" hexmask.word 0x7D6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7D8 "MBCCSR251,Message Buffer Configuratio251. Control and Status Register 251" bitfld.word 0x7D8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7D8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7D8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7D8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7D8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7D8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7D8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7D8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7D8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7D8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7DA "MBCCFR251,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7DA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7DA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7DA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7DA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7DA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7DA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7DC "MBFIDR251,Message Buffer Frame ID Registers" hexmask.word 0x7DC 0.--10. 1. "FID,Frame ID" line.word 0x7DE "MBIDXR251,Message Buffer Index Registers" hexmask.word 0x7DE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7E0 "MBCCSR252,Message Buffer Configuratio252. Control and Status Register 252" bitfld.word 0x7E0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7E0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7E0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7E0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7E0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7E0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7E0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7E0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7E0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7E0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7E2 "MBCCFR252,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7E2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7E2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7E2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7E2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7E2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7E2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7E4 "MBFIDR252,Message Buffer Frame ID Registers" hexmask.word 0x7E4 0.--10. 1. "FID,Frame ID" line.word 0x7E6 "MBIDXR252,Message Buffer Index Registers" hexmask.word 0x7E6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7E8 "MBCCSR253,Message Buffer Configuratio253. Control and Status Register 253" bitfld.word 0x7E8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7E8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7E8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7E8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7E8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7E8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7E8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7E8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7E8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7E8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7EA "MBCCFR253,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7EA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7EA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7EA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7EA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7EA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7EA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7EC "MBFIDR253,Message Buffer Frame ID Registers" hexmask.word 0x7EC 0.--10. 1. "FID,Frame ID" line.word 0x7EE "MBIDXR253,Message Buffer Index Registers" hexmask.word 0x7EE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7F0 "MBCCSR254,Message Buffer Configuratio254. Control and Status Register 254" bitfld.word 0x7F0 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7F0 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7F0 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7F0 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7F0 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7F0 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7F0 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7F0 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7F0 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7F0 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7F2 "MBCCFR254,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7F2 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7F2 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7F2 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7F2 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7F2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7F2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7F4 "MBFIDR254,Message Buffer Frame ID Registers" hexmask.word 0x7F4 0.--10. 1. "FID,Frame ID" line.word 0x7F6 "MBIDXR254,Message Buffer Index Registers" hexmask.word 0x7F6 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x7F8 "MBCCSR255,Message Buffer Configuratio255. Control and Status Register 255" bitfld.word 0x7F8 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer" newline bitfld.word 0x7F8 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission" newline bitfld.word 0x7F8 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered" newline bitfld.word 0x7F8 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered" newline bitfld.word 0x7F8 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled" newline bitfld.word 0x7F8 4. "DUP,Data Updated" "0: Frame Header and message buffer data field not..,1: Frame Header and message buffer data field updated" newline bitfld.word 0x7F8 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid frame..,1: Receive message buffer contains valid frame data.." newline bitfld.word 0x7F8 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled" newline bitfld.word 0x7F8 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application" newline bitfld.word 0x7F8 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.." line.word 0x7FA "MBCCFR255,Message Buffer Cycle Counter Filter Registers" bitfld.word 0x7FA 15. "MTM,Message Buffer Transmission Mode" "0: Event Transmission mode,1: State Transmission mode" newline bitfld.word 0x7FA 14. "CHA,Channel Assignment" "0,1" newline bitfld.word 0x7FA 13. "CHB,Channel Assignment" "0,1" newline bitfld.word 0x7FA 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled" newline hexmask.word.byte 0x7FA 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" newline hexmask.word.byte 0x7FA 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x7FC "MBFIDR255,Message Buffer Frame ID Registers" hexmask.word 0x7FC 0.--10. 1. "FID,Frame ID" line.word 0x7FE "MBIDXR255,Message Buffer Index Registers" hexmask.word 0x7FE 0.--8. 1. "MBIDX,Message Buffer Index" line.word 0x800 "MBDOR0,Message Buffer Data Field Offset Registers" hexmask.word 0x800 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x802 "MBDOR1,Message Buffer Data Field Offset Registers" hexmask.word 0x802 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x804 "MBDOR2,Message Buffer Data Field Offset Registers" hexmask.word 0x804 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x806 "MBDOR3,Message Buffer Data Field Offset Registers" hexmask.word 0x806 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x808 "MBDOR4,Message Buffer Data Field Offset Registers" hexmask.word 0x808 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x80A "MBDOR5,Message Buffer Data Field Offset Registers" hexmask.word 0x80A 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x80C "MBDOR6,Message Buffer Data Field Offset Registers" hexmask.word 0x80C 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x80E "MBDOR7,Message Buffer Data Field Offset Registers" hexmask.word 0x80E 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x810 "MBDOR8,Message Buffer Data Field Offset Registers" hexmask.word 0x810 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x812 "MBDOR9,Message Buffer Data Field Offset Registers" hexmask.word 0x812 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x814 "MBDOR10,Message Buffer Data Field Offset Registers" hexmask.word 0x814 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x816 "MBDOR11,Message Buffer Data Field Offset Registers" hexmask.word 0x816 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x818 "MBDOR12,Message Buffer Data Field Offset Registers" hexmask.word 0x818 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x81A "MBDOR13,Message Buffer Data Field Offset Registers" hexmask.word 0x81A 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x81C "MBDOR14,Message Buffer Data Field Offset Registers" hexmask.word 0x81C 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x81E "MBDOR15,Message Buffer Data Field Offset Registers" hexmask.word 0x81E 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x820 "MBDOR16,Message Buffer Data Field Offset Registers" hexmask.word 0x820 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x822 "MBDOR17,Message Buffer Data Field Offset Registers" hexmask.word 0x822 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x824 "MBDOR18,Message Buffer Data Field Offset Registers" hexmask.word 0x824 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x826 "MBDOR19,Message Buffer Data Field Offset Registers" hexmask.word 0x826 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x828 "MBDOR20,Message Buffer Data Field Offset Registers" hexmask.word 0x828 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x82A "MBDOR21,Message Buffer Data Field Offset Registers" hexmask.word 0x82A 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x82C "MBDOR22,Message Buffer Data Field Offset Registers" hexmask.word 0x82C 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x82E "MBDOR23,Message Buffer Data Field Offset Registers" hexmask.word 0x82E 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x830 "MBDOR24,Message Buffer Data Field Offset Registers" hexmask.word 0x830 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x832 "MBDOR25,Message Buffer Data Field Offset Registers" hexmask.word 0x832 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x834 "MBDOR26,Message Buffer Data Field Offset Registers" hexmask.word 0x834 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x836 "MBDOR27,Message Buffer Data Field Offset Registers" hexmask.word 0x836 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x838 "MBDOR28,Message Buffer Data Field Offset Registers" hexmask.word 0x838 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x83A "MBDOR29,Message Buffer Data Field Offset Registers" hexmask.word 0x83A 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x83C "MBDOR30,Message Buffer Data Field Offset Registers" hexmask.word 0x83C 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x83E "MBDOR31,Message Buffer Data Field Offset Registers" hexmask.word 0x83E 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x840 "MBDOR32,Message Buffer Data Field Offset Registers" hexmask.word 0x840 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x842 "MBDOR33,Message Buffer Data Field Offset Registers" hexmask.word 0x842 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x844 "MBDOR34,Message Buffer Data Field Offset Registers" hexmask.word 0x844 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x846 "MBDOR35,Message Buffer Data Field Offset Registers" hexmask.word 0x846 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x848 "MBDOR36,Message Buffer Data Field Offset Registers" hexmask.word 0x848 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x84A "MBDOR37,Message Buffer Data Field Offset Registers" hexmask.word 0x84A 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x84C "MBDOR38,Message Buffer Data Field Offset Registers" hexmask.word 0x84C 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x84E "MBDOR39,Message Buffer Data Field Offset Registers" hexmask.word 0x84E 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x850 "MBDOR40,Message Buffer Data Field Offset Registers" hexmask.word 0x850 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x852 "MBDOR41,Message Buffer Data Field Offset Registers" hexmask.word 0x852 0.--15. 1. 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"MBDO,Message Buffer Data Field Offset" line.word 0x862 "MBDOR49,Message Buffer Data Field Offset Registers" hexmask.word 0x862 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x864 "MBDOR50,Message Buffer Data Field Offset Registers" hexmask.word 0x864 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x866 "MBDOR51,Message Buffer Data Field Offset Registers" hexmask.word 0x866 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x868 "MBDOR52,Message Buffer Data Field Offset Registers" hexmask.word 0x868 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x86A "MBDOR53,Message Buffer Data Field Offset Registers" hexmask.word 0x86A 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x86C "MBDOR54,Message Buffer Data Field Offset Registers" hexmask.word 0x86C 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x86E "MBDOR55,Message Buffer Data Field Offset Registers" hexmask.word 0x86E 0.--15. 1. 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"MBDO,Message Buffer Data Field Offset" line.word 0x942 "MBDOR161,Message Buffer Data Field Offset Registers" hexmask.word 0x942 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x944 "MBDOR162,Message Buffer Data Field Offset Registers" hexmask.word 0x944 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x946 "MBDOR163,Message Buffer Data Field Offset Registers" hexmask.word 0x946 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x948 "MBDOR164,Message Buffer Data Field Offset Registers" hexmask.word 0x948 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x94A "MBDOR165,Message Buffer Data Field Offset Registers" hexmask.word 0x94A 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x94C "MBDOR166,Message Buffer Data Field Offset Registers" hexmask.word 0x94C 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x94E "MBDOR167,Message Buffer Data Field Offset Registers" hexmask.word 0x94E 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x950 "MBDOR168,Message Buffer Data Field Offset Registers" hexmask.word 0x950 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x952 "MBDOR169,Message Buffer Data Field Offset Registers" hexmask.word 0x952 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x954 "MBDOR170,Message Buffer Data Field Offset Registers" hexmask.word 0x954 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x956 "MBDOR171,Message Buffer Data Field Offset Registers" hexmask.word 0x956 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x958 "MBDOR172,Message Buffer Data Field Offset Registers" hexmask.word 0x958 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x95A "MBDOR173,Message Buffer Data Field Offset Registers" hexmask.word 0x95A 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x95C "MBDOR174,Message Buffer Data Field Offset Registers" hexmask.word 0x95C 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x95E "MBDOR175,Message Buffer Data Field Offset Registers" hexmask.word 0x95E 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x960 "MBDOR176,Message Buffer Data Field Offset Registers" hexmask.word 0x960 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x962 "MBDOR177,Message Buffer Data Field Offset Registers" hexmask.word 0x962 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x964 "MBDOR178,Message Buffer Data Field Offset Registers" hexmask.word 0x964 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x966 "MBDOR179,Message Buffer Data Field Offset Registers" hexmask.word 0x966 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x968 "MBDOR180,Message Buffer Data Field Offset Registers" hexmask.word 0x968 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x96A "MBDOR181,Message Buffer Data Field Offset Registers" hexmask.word 0x96A 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x96C "MBDOR182,Message Buffer Data Field Offset Registers" hexmask.word 0x96C 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x96E "MBDOR183,Message Buffer Data Field Offset Registers" hexmask.word 0x96E 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x970 "MBDOR184,Message Buffer Data Field Offset Registers" hexmask.word 0x970 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x972 "MBDOR185,Message Buffer Data Field Offset Registers" hexmask.word 0x972 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x974 "MBDOR186,Message Buffer Data Field Offset Registers" hexmask.word 0x974 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x976 "MBDOR187,Message Buffer Data Field Offset Registers" hexmask.word 0x976 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x978 "MBDOR188,Message Buffer Data Field Offset Registers" hexmask.word 0x978 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x97A "MBDOR189,Message Buffer Data Field Offset Registers" hexmask.word 0x97A 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x97C "MBDOR190,Message Buffer Data Field Offset Registers" hexmask.word 0x97C 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x97E "MBDOR191,Message Buffer Data Field Offset Registers" hexmask.word 0x97E 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x980 "MBDOR192,Message Buffer Data Field Offset Registers" hexmask.word 0x980 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x982 "MBDOR193,Message Buffer Data Field Offset Registers" hexmask.word 0x982 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x984 "MBDOR194,Message Buffer Data Field Offset Registers" hexmask.word 0x984 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x986 "MBDOR195,Message Buffer Data Field Offset Registers" hexmask.word 0x986 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x988 "MBDOR196,Message Buffer Data Field Offset Registers" hexmask.word 0x988 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x98A "MBDOR197,Message Buffer Data Field Offset Registers" hexmask.word 0x98A 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x98C "MBDOR198,Message Buffer Data Field Offset Registers" hexmask.word 0x98C 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x98E "MBDOR199,Message Buffer Data Field Offset Registers" hexmask.word 0x98E 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x990 "MBDOR200,Message Buffer Data Field Offset Registers" hexmask.word 0x990 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x992 "MBDOR201,Message Buffer Data Field Offset Registers" hexmask.word 0x992 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x994 "MBDOR202,Message Buffer Data Field Offset Registers" hexmask.word 0x994 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x996 "MBDOR203,Message Buffer Data Field Offset Registers" hexmask.word 0x996 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x998 "MBDOR204,Message Buffer Data Field Offset Registers" hexmask.word 0x998 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x99A "MBDOR205,Message Buffer Data Field Offset Registers" hexmask.word 0x99A 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x99C "MBDOR206,Message Buffer Data Field Offset Registers" hexmask.word 0x99C 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x99E "MBDOR207,Message Buffer Data Field Offset Registers" hexmask.word 0x99E 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9A0 "MBDOR208,Message Buffer Data Field Offset Registers" hexmask.word 0x9A0 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9A2 "MBDOR209,Message Buffer Data Field Offset Registers" hexmask.word 0x9A2 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9A4 "MBDOR210,Message Buffer Data Field Offset Registers" hexmask.word 0x9A4 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9A6 "MBDOR211,Message Buffer Data Field Offset Registers" hexmask.word 0x9A6 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9A8 "MBDOR212,Message Buffer Data Field Offset Registers" hexmask.word 0x9A8 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9AA "MBDOR213,Message Buffer Data Field Offset Registers" hexmask.word 0x9AA 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9AC "MBDOR214,Message Buffer Data Field Offset Registers" hexmask.word 0x9AC 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9AE "MBDOR215,Message Buffer Data Field Offset Registers" hexmask.word 0x9AE 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9B0 "MBDOR216,Message Buffer Data Field Offset Registers" hexmask.word 0x9B0 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9B2 "MBDOR217,Message Buffer Data Field Offset Registers" hexmask.word 0x9B2 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9B4 "MBDOR218,Message Buffer Data Field Offset Registers" hexmask.word 0x9B4 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9B6 "MBDOR219,Message Buffer Data Field Offset Registers" hexmask.word 0x9B6 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9B8 "MBDOR220,Message Buffer Data Field Offset Registers" hexmask.word 0x9B8 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9BA "MBDOR221,Message Buffer Data Field Offset Registers" hexmask.word 0x9BA 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9BC "MBDOR222,Message Buffer Data Field Offset Registers" hexmask.word 0x9BC 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9BE "MBDOR223,Message Buffer Data Field Offset Registers" hexmask.word 0x9BE 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9C0 "MBDOR224,Message Buffer Data Field Offset Registers" hexmask.word 0x9C0 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9C2 "MBDOR225,Message Buffer Data Field Offset Registers" hexmask.word 0x9C2 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9C4 "MBDOR226,Message Buffer Data Field Offset Registers" hexmask.word 0x9C4 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9C6 "MBDOR227,Message Buffer Data Field Offset Registers" hexmask.word 0x9C6 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9C8 "MBDOR228,Message Buffer Data Field Offset Registers" hexmask.word 0x9C8 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9CA "MBDOR229,Message Buffer Data Field Offset Registers" hexmask.word 0x9CA 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9CC "MBDOR230,Message Buffer Data Field Offset Registers" hexmask.word 0x9CC 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9CE "MBDOR231,Message Buffer Data Field Offset Registers" hexmask.word 0x9CE 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9D0 "MBDOR232,Message Buffer Data Field Offset Registers" hexmask.word 0x9D0 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9D2 "MBDOR233,Message Buffer Data Field Offset Registers" hexmask.word 0x9D2 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9D4 "MBDOR234,Message Buffer Data Field Offset Registers" hexmask.word 0x9D4 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9D6 "MBDOR235,Message Buffer Data Field Offset Registers" hexmask.word 0x9D6 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9D8 "MBDOR236,Message Buffer Data Field Offset Registers" hexmask.word 0x9D8 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9DA "MBDOR237,Message Buffer Data Field Offset Registers" hexmask.word 0x9DA 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9DC "MBDOR238,Message Buffer Data Field Offset Registers" hexmask.word 0x9DC 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9DE "MBDOR239,Message Buffer Data Field Offset Registers" hexmask.word 0x9DE 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9E0 "MBDOR240,Message Buffer Data Field Offset Registers" hexmask.word 0x9E0 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9E2 "MBDOR241,Message Buffer Data Field Offset Registers" hexmask.word 0x9E2 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9E4 "MBDOR242,Message Buffer Data Field Offset Registers" hexmask.word 0x9E4 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9E6 "MBDOR243,Message Buffer Data Field Offset Registers" hexmask.word 0x9E6 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9E8 "MBDOR244,Message Buffer Data Field Offset Registers" hexmask.word 0x9E8 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9EA "MBDOR245,Message Buffer Data Field Offset Registers" hexmask.word 0x9EA 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9EC "MBDOR246,Message Buffer Data Field Offset Registers" hexmask.word 0x9EC 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9EE "MBDOR247,Message Buffer Data Field Offset Registers" hexmask.word 0x9EE 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9F0 "MBDOR248,Message Buffer Data Field Offset Registers" hexmask.word 0x9F0 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9F2 "MBDOR249,Message Buffer Data Field Offset Registers" hexmask.word 0x9F2 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9F4 "MBDOR250,Message Buffer Data Field Offset Registers" hexmask.word 0x9F4 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9F6 "MBDOR251,Message Buffer Data Field Offset Registers" hexmask.word 0x9F6 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9F8 "MBDOR252,Message Buffer Data Field Offset Registers" hexmask.word 0x9F8 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9FA "MBDOR253,Message Buffer Data Field Offset Registers" hexmask.word 0x9FA 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9FC "MBDOR254,Message Buffer Data Field Offset Registers" hexmask.word 0x9FC 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0x9FE "MBDOR255,Message Buffer Data Field Offset Registers" hexmask.word 0x9FE 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0xA00 "MBDOR256,Message Buffer Data Field Offset Registers" hexmask.word 0xA00 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0xA02 "MBDOR257,Message Buffer Data Field Offset Registers" hexmask.word 0xA02 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0xA04 "MBDOR258,Message Buffer Data Field Offset Registers" hexmask.word 0xA04 0.--15. 1. "MBDO,Message Buffer Data Field Offset" line.word 0xA06 "MBDOR259,Message Buffer Data Field Offset Registers" hexmask.word 0xA06 0.--15. 1. "MBDO,Message Buffer Data Field Offset" group.word 0x1210++0xB line.word 0x0 "LEETR0,LRAM ECC Error Test Registers" hexmask.word 0x0 0.--15. 1. "LEETD,LRAM ECC Error Test Data" line.word 0x2 "LEETR1,LRAM ECC Error Test Registers" hexmask.word 0x2 0.--15. 1. "LEETD,LRAM ECC Error Test Data" line.word 0x4 "LEETR2,LRAM ECC Error Test Registers" hexmask.word 0x4 0.--15. 1. "LEETD,LRAM ECC Error Test Data" line.word 0x6 "LEETR3,LRAM ECC Error Test Registers" hexmask.word 0x6 0.--15. 1. "LEETD,LRAM ECC Error Test Data" line.word 0x8 "LEETR4,LRAM ECC Error Test Registers" hexmask.word 0x8 0.--15. 1. "LEETD,LRAM ECC Error Test Data" line.word 0xA "LEETR5,LRAM ECC Error Test Registers" hexmask.word 0xA 0.--15. 1. "LEETD,LRAM ECC Error Test Data" tree.end tree.end tree "GST (Global System Timer)" base ad:0x70468000 group.long 0x0++0x7 line.long 0x0 "NSC_DEBUG_CFG,NSC debug config register" bitfld.long 0x0 4. "NSC_FRZ_IN_DEBUG,NSC freeze in Debug mode" "0: NSC increments in debug mode as well,1: NSC stops incrementing in debug mode" line.long 0x4 "NSC_CFG,NSC config register" bitfld.long 0x4 0. "NSC_RELOAD_CTRL,NSC Reload control" "0: NSC is updated with Reload value only when..,1: NSC is updated with Reload value as soon as the.." rgroup.long 0x8++0x3 line.long 0x0 "NSC_STATUS,NSC status register" bitfld.long 0x0 8. "NSC_READ_REG_STATUS,NSC Current Value Read Register Status" "0: NSC Value read registers are not latched. A new..,1: NSC Value read registers are latched due to a.." group.long 0xC++0x3 line.long 0x0 "NSC_CTRL,NSC control register" bitfld.long 0x0 8. "CLR_READ_REG,NSC Clear Read Register from latched values" "0,1" newline bitfld.long 0x0 0. "FORCE_RELOAD,NSC Force Reload" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "NSC_LWORD_READ,NSC lower word read register" hexmask.long 0x0 0.--31. 1. "NSC_READ_DATA31_0,NSC Lower Word Read register" line.long 0x4 "NSC_HWORD_READ,NSC HWORD read register" hexmask.long 0x4 0.--31. 1. "NSC_READ_DATA63_32,NSC Higher Word Read register" group.long 0x18++0xB line.long 0x0 "NSC_LWORD_RELOAD,NSC lower word [31:0] reload register" hexmask.long 0x0 0.--31. 1. "NSC_RELOAD_DATA31_0,NSC Lower word Reload value" line.long 0x4 "NSC_HWORD_RELOAD,NSC higher word [63:32] reload register" hexmask.long 0x4 0.--31. 1. "NSC_RELOAD_DATA63_32,NSC Higher word Reload value" line.long 0x8 "NSC_INCSTEP_CFG,NSC increment step config register" hexmask.long.word 0x8 0.--15. 1. "NSC_INCSTEP_VAL,NSC Increment Step size Value" rgroup.long 0x24++0x3 line.long 0x0 "NSC_STATUS_CH2,NSC status of read register for channel 2" bitfld.long 0x0 8. "NSC_READ_REG_STATUS_CH2,NSC Current Value Read Register Status for channel 2 of read register" "0: NSC Value read registers of CH2 are not latched.,1: NSC Value read registers of CH2 are latched due.." group.long 0x28++0x3 line.long 0x0 "NSC_CTRL_CH2,NSC control of read register for channel 2" bitfld.long 0x0 8. "CLR_READ_REG_CH2,NSC Clear Read Register of channel 2 from latched values" "0,1" rgroup.long 0x2C++0x17 line.long 0x0 "NSC_LWORD_READ_CH2,NSC lower word read register for channel 2" hexmask.long 0x0 0.--31. 1. "NSC_READ_CH2_DATA31_0,NSC Lower Word Read register for channel 2" line.long 0x4 "NSC_HWORD_READ_CH2,NSC higher word read register for channel 2" hexmask.long 0x4 0.--31. 1. "NSC_READ_CH2_DATA63_32,NSC Higher Word Read register for channel 2" line.long 0x8 "NSC_LWORD_READ_NOLATCH,NSC lower word read register without latch" hexmask.long 0x8 0.--31. 1. "NSC_READ_DATA31_0_NOLATCH,NSC Lower Word Read register without latching mechanism" line.long 0xC "NSC_HWORD_READ_NOLATCH,NSC higher word read register without latch" hexmask.long 0xC 0.--31. 1. "NSC_READ_DATA63_32_NOLATCH,NSC Higher Word Read register without latching mechanism" line.long 0x10 "NSC_LWORD_READ_CH2_NOLATCH,NSC lower word read register without latching for channel 2" hexmask.long 0x10 0.--31. 1. "NSC_READ_CH2_DATA31_0_NOLATCH,NSC Lower Word Read register without latching mechanism for channel 2" line.long 0x14 "NSC_HWORD_READ_CH2_NOLATCH,NSC higher word read register without latching for channel 2" hexmask.long 0x14 0.--31. 1. "NSC_READ_CH2_DATA63_32_NOLATCH,NSC Higher Word Read register without latching mechanism for channel 2" group.long 0x100++0x7 line.long 0x0 "EXNTP_DEBUG_CFG,ExNTP debug config register" bitfld.long 0x0 4. "EXNTP_FRZ_IN_DEBUG,ExNTP Freeze in Debug Mode" "0: ExNTP increments in debug mode as well,1: ExNTP stops incrementing in debug mode" line.long 0x4 "EXNTP_CFG,ExNTP config register" bitfld.long 0x4 12. "UPDATE_EVENT_SEL,ExNTP Update Event Selection" "0: ExNTP is incremented on positive edge of GST..,1: ExNTP is updated on positive edge of GST CLOCK.." newline bitfld.long 0x4 0. "EXNTP_RELOAD_CTRL,ExNTP Reload control" "0: ExNTP is updated with Reload value only when..,1: ExNTP is updated with Reload value as soon as.." rgroup.long 0x108++0x3 line.long 0x0 "EXNTP_STATUS,ExNTP status register" bitfld.long 0x0 8. "EXNTP_READ_REG_STATUS,ExNTP timer read register latched status" "0: ExNTP Read register are not latched.,1: ExNTP Read register are latched." group.long 0x10C++0x3 line.long 0x0 "EXNTP_CTRL,ExNTP control register" bitfld.long 0x0 8. "CLR_READ_REG,ExNTP Clear Read Register from latched values" "0,1" newline bitfld.long 0x0 0. "FORCE_RELOAD,ExNTP Force Reload" "0,1" rgroup.long 0x110++0xB line.long 0x0 "EXNTP_READ_NANOSECOND,ExNTP read nanosecond register" hexmask.long 0x0 0.--31. 1. "EXNTP_READ_DATA31_0,ExNTP Nanosecond Read register" line.long 0x4 "EXNTP_READ_SECOND,ExNTP read seconds register" hexmask.long 0x4 0.--31. 1. "EXNTP_READ_DATA63_32,ExNTP Second Read register" line.long 0x8 "EXNTP_READ_EXSECOND,ExNTP read extended seconds field register" hexmask.long 0x8 0.--31. 1. "EXNTP_READ_DATA79_64,ExNTP Extended Second Read register" group.long 0x11C++0x13 line.long 0x0 "EXNTP_RELOAD_NANOSECOND,ExNTP reload nanosecond field [31:0] register" hexmask.long 0x0 0.--31. 1. "EXNTP_RELOAD_DATA31_0,ExNTP timer Nanosecond field Reload value" line.long 0x4 "EXNTP_RELOAD_SECOND,ExNTP reload second field [63:32] register" hexmask.long 0x4 0.--31. 1. "EXNTP_RELOAD_DATA63_32,ExNTP timer Second field Reload value" line.long 0x8 "EXNTP_RELOAD_EXSECOND,ExNTP reload extended second field [79:64] register" hexmask.long.word 0x8 0.--15. 1. "EXNTP_RELOAD_DATA79_64,ExNTP timer extended second field Reload value" line.long 0xC "EXNTP_INCSTEP_CFG,ExNTP increment step config register" hexmask.long.word 0xC 0.--15. 1. "EXNTP_INCSTEP_VAL,ExNTP timer increment step size value." line.long 0x10 "EXNTP_EVENT_GEN_CFG,ExNTP event generator config register" hexmask.long.word 0x10 16.--31. 1. "PRESCALER_VAL,ExNTP Event Generator GST CLOCK Prescaler Value" newline bitfld.long 0x10 4.--6. "AUX_SOURCE_SYNC_MODE,ExNTP Event Generator AUX Source Sync Mode" "0: Positive edge of Aux Source (synchronized to GST..,1: Negative edge of Aux Source (synchronized to GST..,2: Both Positive edge and Negative edge of Aux..,3: AUX Source is synchronized to GST clock.,?,?,?,?" newline bitfld.long 0x10 0. "EVENT_SOURCE_SEL,ExNTP Event Generator Source Selection" "0: GST Clock is selected as source for ExNTP EVENT..,1: Auxiliary Source is selected as source for ExNTP.." rgroup.long 0x130++0xB line.long 0x0 "EXNTP_READ_NANOSECOND_NOLATCH,ExNTP Read Nanosecond register without latching" hexmask.long 0x0 0.--31. 1. "EXNTP_READ_DATA31_0_NOLATCH,ExNTP Nanoseconds Read register without latching mechanism" line.long 0x4 "EXNTP_READ_SECOND_NOLATCH,ExNTP Read Seconds register without latching" hexmask.long 0x4 0.--31. 1. "EXNTP_READ_DATA63_32_NOLATCH,ExNTP seconds Read register without latching mechanism" line.long 0x8 "EXNTP_READ_EXSECOND_NOLATCH,ExNTP Read Extended Seconds register without latching" hexmask.long 0x8 0.--31. 1. "EXNTP_READ_DATA79_64_NOLATCH,ExNTP extended seconds Read register without latching mechanism" group.long 0x140++0x7 line.long 0x0 "OTC0_DEBUG_CFG,OTCn debug config register" bitfld.long 0x0 4. "OTC_FRZ_IN_DEBUG,OTCn Freeze in Debug Mode" "0: OTCn increments in debug mode as well,1: OTCn stops incrementing in debug mode" line.long 0x4 "OTC0_CFG,OTCn config register" bitfld.long 0x4 12. "OTC_UPDATE_EVENT_SEL,OTCn Update Event Selection" "0: OTCn is incremented on the positive edge of GST..,1: OTCn is incremented on the positive edge of GST.." newline bitfld.long 0x4 0. "OTC_RELOAD_CTRL,OTCn Reload Control" "0: OTCn is updated with Reload value only when..,1: OTC is updated with Reload value as soon as the.." rgroup.long 0x148++0x3 line.long 0x0 "OTC0_STATUS,OTCn status register" bitfld.long 0x0 16. "OTC_RUN_STATUS,OTC RUN Status" "0: OTCn counter has received a valid STOP request..,1: OTCn counter has not received a valid \qSTOP\q.." newline bitfld.long 0x0 8. "OTC_READ_REG_STATUS,OTC Current Value Read Register Status" "0: OTCn Value read registers are not latched. A new..,1: OTCn Value read registers are latched due to a.." group.long 0x14C++0x3 line.long 0x0 "OTC0_CTRL,OTCn control register" bitfld.long 0x0 20. "OTC_FORCE_STOP,OTCn Force stop" "?,1: has no impact if OTC counter was already stopped" newline bitfld.long 0x0 16. "OTC_FORCE_START,OTCn Force start" "0,1" newline bitfld.long 0x0 8. "CLR_READ_REG,OTCn Clear Read Register from latched values" "0,1" newline bitfld.long 0x0 0. "FORCE_RELOAD,OTCn Force Reload" "0,1" rgroup.long 0x150++0x7 line.long 0x0 "OTC0_LWORD_READ,OTCn lower word read register" hexmask.long 0x0 0.--31. 1. "OTC_READ_DATA31_0,OTCn Lower Word Read register" line.long 0x4 "OTC0_HWORD_READ,OTCn higher word read register" hexmask.long 0x4 0.--31. 1. "OTC_READ_DATA63_32,OTCn Higher Word Read register" group.long 0x158++0xF line.long 0x0 "OTC0_LWORD_RELOAD,OTCn lower word [31:0] reload register" hexmask.long 0x0 0.--31. 1. "OTC_RELOAD_DATA31_0,OTCn Lower Word Reload value" line.long 0x4 "OTC0_HWORD_RELOAD,OTCn higher word [63:32] reload register" hexmask.long 0x4 0.--31. 1. "OTC_RELOAD_DATA63_32,OTCn Higher Word Reload value" line.long 0x8 "OTC0_EVENT_GEN_CFG,OTCn event generator config register" hexmask.long.word 0x8 16.--31. 1. "PRESCALER_VAL,OTCn Event Generator GST CLOCK Prescaler Value" newline bitfld.long 0x8 4.--6. "AUX_SOURCE_SYNC_MODE,OTCn Event Generator AUX Source Sync Mode" "0: Positive edge of Aux Source (synchronized to GST..,1: Negative edge of Aux Source (synchronized to GST..,2: Both Positive edge and Negative edge of Aux..,3: AUX Source is synchronized to GST clock.,?,?,?,?" newline bitfld.long 0x8 0. "EVENT_SOURCE_SEL,OTCn Event Generator Source Selection" "0: GST Clock is selected as source for OTCn EVENT..,1: Auxiliary Source is selected as source for OTCn.." line.long 0xC "OTC0_INCSTEP_CFG,OTCn increment step config register" hexmask.long.word 0xC 0.--15. 1. "OTC_INCSTEP_VAL,OTCn Increment step Value" rgroup.long 0x168++0x7 line.long 0x0 "OTC0_LWORD_READ_NOLATCH,OTCn current lower word read register without latch" hexmask.long 0x0 0.--31. 1. "OTC0_READ_DATA31_0_NOLATCH,OTCn Lower Word Read register without latching mechanism" line.long 0x4 "OTC0_HWORD_READ_NOLATCH,OTCn current higher word read register without latch" hexmask.long 0x4 0.--31. 1. "OTC0_READ_DATA63_32_NOLATCH,OTCn Higher Word Read register without latching mechanism" group.long 0x180++0x7 line.long 0x0 "OTC1_DEBUG_CFG,OTCn debug config register" bitfld.long 0x0 4. "OTC_FRZ_IN_DEBUG,OTCn Freeze in Debug Mode" "0: OTCn increments in debug mode as well,1: OTCn stops incrementing in debug mode" line.long 0x4 "OTC1_CFG,OTCn config register" bitfld.long 0x4 12. "OTC_UPDATE_EVENT_SEL,OTCn Update Event Selection" "0: OTCn is incremented on the positive edge of GST..,1: OTCn is incremented on the positive edge of GST.." newline bitfld.long 0x4 0. "OTC_RELOAD_CTRL,OTCn Reload Control" "0: OTCn is updated with Reload value only when..,1: OTC is updated with Reload value as soon as the.." rgroup.long 0x188++0x3 line.long 0x0 "OTC1_STATUS,OTCn status register" bitfld.long 0x0 16. "OTC_RUN_STATUS,OTC RUN Status" "0: OTCn counter has received a valid STOP request..,1: OTCn counter has not received a valid \qSTOP\q.." newline bitfld.long 0x0 8. "OTC_READ_REG_STATUS,OTC Current Value Read Register Status" "0: OTCn Value read registers are not latched. A new..,1: OTCn Value read registers are latched due to a.." group.long 0x18C++0x3 line.long 0x0 "OTC1_CTRL,OTCn control register" bitfld.long 0x0 20. "OTC_FORCE_STOP,OTCn Force stop" "?,1: has no impact if OTC counter was already stopped" newline bitfld.long 0x0 16. "OTC_FORCE_START,OTCn Force start" "0,1" newline bitfld.long 0x0 8. "CLR_READ_REG,OTCn Clear Read Register from latched values" "0,1" newline bitfld.long 0x0 0. "FORCE_RELOAD,OTCn Force Reload" "0,1" rgroup.long 0x190++0x7 line.long 0x0 "OTC1_LWORD_READ,OTCn lower word read register" hexmask.long 0x0 0.--31. 1. "OTC_READ_DATA31_0,OTCn Lower Word Read register" line.long 0x4 "OTC1_HWORD_READ,OTCn higher word read register" hexmask.long 0x4 0.--31. 1. "OTC_READ_DATA63_32,OTCn Higher Word Read register" group.long 0x198++0xF line.long 0x0 "OTC1_LWORD_RELOAD,OTCn lower word [31:0] reload register" hexmask.long 0x0 0.--31. 1. "OTC_RELOAD_DATA31_0,OTCn Lower Word Reload value" line.long 0x4 "OTC1_HWORD_RELOAD,OTCn higher word [63:32] reload register" hexmask.long 0x4 0.--31. 1. "OTC_RELOAD_DATA63_32,OTCn Higher Word Reload value" line.long 0x8 "OTC1_EVENT_GEN_CFG,OTCn event generator config register" hexmask.long.word 0x8 16.--31. 1. "PRESCALER_VAL,OTCn Event Generator GST CLOCK Prescaler Value" newline bitfld.long 0x8 4.--6. "AUX_SOURCE_SYNC_MODE,OTCn Event Generator AUX Source Sync Mode" "0: Positive edge of Aux Source (synchronized to GST..,1: Negative edge of Aux Source (synchronized to GST..,2: Both Positive edge and Negative edge of Aux..,3: AUX Source is synchronized to GST clock.,?,?,?,?" newline bitfld.long 0x8 0. "EVENT_SOURCE_SEL,OTCn Event Generator Source Selection" "0: GST Clock is selected as source for OTCn EVENT..,1: Auxiliary Source is selected as source for OTCn.." line.long 0xC "OTC1_INCSTEP_CFG,OTCn increment step config register" hexmask.long.word 0xC 0.--15. 1. "OTC_INCSTEP_VAL,OTCn Increment step Value" rgroup.long 0x1A8++0x7 line.long 0x0 "OTC1_LWORD_READ_NOLATCH,OTCn current lower word read register without latch" hexmask.long 0x0 0.--31. 1. "OTC1_READ_DATA31_0_NOLATCH,OTCn Lower Word Read register without latching mechanism" line.long 0x4 "OTC1_HWORD_READ_NOLATCH,OTCn current higher word read register without latch" hexmask.long 0x4 0.--31. 1. "OTC1_READ_DATA63_32_NOLATCH,OTCn Higher Word Read register without latching mechanism" group.long 0x1C0++0x7 line.long 0x0 "OTC2_DEBUG_CFG,OTCn debug config register" bitfld.long 0x0 4. "OTC_FRZ_IN_DEBUG,OTCn Freeze in Debug Mode" "0: OTCn increments in debug mode as well,1: OTCn stops incrementing in debug mode" line.long 0x4 "OTC2_CFG,OTCn config register" bitfld.long 0x4 12. "OTC_UPDATE_EVENT_SEL,OTCn Update Event Selection" "0: OTCn is incremented on the positive edge of GST..,1: OTCn is incremented on the positive edge of GST.." newline bitfld.long 0x4 0. "OTC_RELOAD_CTRL,OTCn Reload Control" "0: OTCn is updated with Reload value only when..,1: OTC is updated with Reload value as soon as the.." rgroup.long 0x1C8++0x3 line.long 0x0 "OTC2_STATUS,OTCn status register" bitfld.long 0x0 16. "OTC_RUN_STATUS,OTC RUN Status" "0: OTCn counter has received a valid STOP request..,1: OTCn counter has not received a valid \qSTOP\q.." newline bitfld.long 0x0 8. "OTC_READ_REG_STATUS,OTC Current Value Read Register Status" "0: OTCn Value read registers are not latched. A new..,1: OTCn Value read registers are latched due to a.." group.long 0x1CC++0x3 line.long 0x0 "OTC2_CTRL,OTCn control register" bitfld.long 0x0 20. "OTC_FORCE_STOP,OTCn Force stop" "?,1: has no impact if OTC counter was already stopped" newline bitfld.long 0x0 16. "OTC_FORCE_START,OTCn Force start" "0,1" newline bitfld.long 0x0 8. "CLR_READ_REG,OTCn Clear Read Register from latched values" "0,1" newline bitfld.long 0x0 0. "FORCE_RELOAD,OTCn Force Reload" "0,1" rgroup.long 0x1D0++0x7 line.long 0x0 "OTC2_LWORD_READ,OTCn lower word read register" hexmask.long 0x0 0.--31. 1. "OTC_READ_DATA31_0,OTCn Lower Word Read register" line.long 0x4 "OTC2_HWORD_READ,OTCn higher word read register" hexmask.long 0x4 0.--31. 1. "OTC_READ_DATA63_32,OTCn Higher Word Read register" group.long 0x1D8++0xF line.long 0x0 "OTC2_LWORD_RELOAD,OTCn lower word [31:0] reload register" hexmask.long 0x0 0.--31. 1. "OTC_RELOAD_DATA31_0,OTCn Lower Word Reload value" line.long 0x4 "OTC2_HWORD_RELOAD,OTCn higher word [63:32] reload register" hexmask.long 0x4 0.--31. 1. "OTC_RELOAD_DATA63_32,OTCn Higher Word Reload value" line.long 0x8 "OTC2_EVENT_GEN_CFG,OTCn event generator config register" hexmask.long.word 0x8 16.--31. 1. "PRESCALER_VAL,OTCn Event Generator GST CLOCK Prescaler Value" newline bitfld.long 0x8 4.--6. "AUX_SOURCE_SYNC_MODE,OTCn Event Generator AUX Source Sync Mode" "0: Positive edge of Aux Source (synchronized to GST..,1: Negative edge of Aux Source (synchronized to GST..,2: Both Positive edge and Negative edge of Aux..,3: AUX Source is synchronized to GST clock.,?,?,?,?" newline bitfld.long 0x8 0. "EVENT_SOURCE_SEL,OTCn Event Generator Source Selection" "0: GST Clock is selected as source for OTCn EVENT..,1: Auxiliary Source is selected as source for OTCn.." line.long 0xC "OTC2_INCSTEP_CFG,OTCn increment step config register" hexmask.long.word 0xC 0.--15. 1. "OTC_INCSTEP_VAL,OTCn Increment step Value" rgroup.long 0x1E8++0x7 line.long 0x0 "OTC2_LWORD_READ_NOLATCH,OTCn current lower word read register without latch" hexmask.long 0x0 0.--31. 1. "OTC2_READ_DATA31_0_NOLATCH,OTCn Lower Word Read register without latching mechanism" line.long 0x4 "OTC2_HWORD_READ_NOLATCH,OTCn current higher word read register without latch" hexmask.long 0x4 0.--31. 1. "OTC2_READ_DATA63_32_NOLATCH,OTCn Higher Word Read register without latching mechanism" group.long 0x200++0x7 line.long 0x0 "OTC3_DEBUG_CFG,OTCn debug config register" bitfld.long 0x0 4. "OTC_FRZ_IN_DEBUG,OTCn Freeze in Debug Mode" "0: OTCn increments in debug mode as well,1: OTCn stops incrementing in debug mode" line.long 0x4 "OTC3_CFG,OTCn config register" bitfld.long 0x4 12. "OTC_UPDATE_EVENT_SEL,OTCn Update Event Selection" "0: OTCn is incremented on the positive edge of GST..,1: OTCn is incremented on the positive edge of GST.." newline bitfld.long 0x4 0. "OTC_RELOAD_CTRL,OTCn Reload Control" "0: OTCn is updated with Reload value only when..,1: OTC is updated with Reload value as soon as the.." rgroup.long 0x208++0x3 line.long 0x0 "OTC3_STATUS,OTCn status register" bitfld.long 0x0 16. "OTC_RUN_STATUS,OTC RUN Status" "0: OTCn counter has received a valid STOP request..,1: OTCn counter has not received a valid \qSTOP\q.." newline bitfld.long 0x0 8. "OTC_READ_REG_STATUS,OTC Current Value Read Register Status" "0: OTCn Value read registers are not latched. A new..,1: OTCn Value read registers are latched due to a.." group.long 0x20C++0x3 line.long 0x0 "OTC3_CTRL,OTCn control register" bitfld.long 0x0 20. "OTC_FORCE_STOP,OTCn Force stop" "?,1: has no impact if OTC counter was already stopped" newline bitfld.long 0x0 16. "OTC_FORCE_START,OTCn Force start" "0,1" newline bitfld.long 0x0 8. "CLR_READ_REG,OTCn Clear Read Register from latched values" "0,1" newline bitfld.long 0x0 0. "FORCE_RELOAD,OTCn Force Reload" "0,1" rgroup.long 0x210++0x7 line.long 0x0 "OTC3_LWORD_READ,OTCn lower word read register" hexmask.long 0x0 0.--31. 1. "OTC_READ_DATA31_0,OTCn Lower Word Read register" line.long 0x4 "OTC3_HWORD_READ,OTCn higher word read register" hexmask.long 0x4 0.--31. 1. "OTC_READ_DATA63_32,OTCn Higher Word Read register" group.long 0x218++0xF line.long 0x0 "OTC3_LWORD_RELOAD,OTCn lower word [31:0] reload register" hexmask.long 0x0 0.--31. 1. "OTC_RELOAD_DATA31_0,OTCn Lower Word Reload value" line.long 0x4 "OTC3_HWORD_RELOAD,OTCn higher word [63:32] reload register" hexmask.long 0x4 0.--31. 1. "OTC_RELOAD_DATA63_32,OTCn Higher Word Reload value" line.long 0x8 "OTC3_EVENT_GEN_CFG,OTCn event generator config register" hexmask.long.word 0x8 16.--31. 1. "PRESCALER_VAL,OTCn Event Generator GST CLOCK Prescaler Value" newline bitfld.long 0x8 4.--6. "AUX_SOURCE_SYNC_MODE,OTCn Event Generator AUX Source Sync Mode" "0: Positive edge of Aux Source (synchronized to GST..,1: Negative edge of Aux Source (synchronized to GST..,2: Both Positive edge and Negative edge of Aux..,3: AUX Source is synchronized to GST clock.,?,?,?,?" newline bitfld.long 0x8 0. "EVENT_SOURCE_SEL,OTCn Event Generator Source Selection" "0: GST Clock is selected as source for OTCn EVENT..,1: Auxiliary Source is selected as source for OTCn.." line.long 0xC "OTC3_INCSTEP_CFG,OTCn increment step config register" hexmask.long.word 0xC 0.--15. 1. "OTC_INCSTEP_VAL,OTCn Increment step Value" rgroup.long 0x228++0x7 line.long 0x0 "OTC3_LWORD_READ_NOLATCH,OTCn current lower word read register without latch" hexmask.long 0x0 0.--31. 1. "OTC3_READ_DATA31_0_NOLATCH,OTCn Lower Word Read register without latching mechanism" line.long 0x4 "OTC3_HWORD_READ_NOLATCH,OTCn current higher word read register without latch" hexmask.long 0x4 0.--31. 1. "OTC3_READ_DATA63_32_NOLATCH,OTCn Higher Word Read register without latching mechanism" group.long 0x240++0x7 line.long 0x0 "ARC0_DEBUG_CFG,ARCm debug config register" bitfld.long 0x0 4. "ARC_FRZ_IN_DEBUG,ARCm Freeze in Debug Mode" "0: ARC increments/decrements in debug mode as well,1: ARC stops incrementing/decrementing in debug mode" line.long 0x4 "ARC0_CFG,ARCm config register" bitfld.long 0x4 16. "ARC_RUN,ARCm Run Mode" "0: ARCm is set in One Time Mode,1: ARCm is set in Auto Reload Mode" newline bitfld.long 0x4 14.--15. "ARC_UPDATE_EVENT,ARCm Update Event" "0: Increment ARC on GST CLOCK PosEdge,1: Decrement ARC on GST CLOCK PosEdge,2: Increment ARC on GST CLOCK PosEDGE IF UPDATE..,3: Decrement ARC on GST CLOCK PosEDGE IF UPDATE.." rgroup.long 0x248++0x3 line.long 0x0 "ARC0_STATUS,ARCm status register" bitfld.long 0x0 12. "ARC_START_STATUS,ARCm Start Status" "0: ARC counter has not received a valid \qSTART\q..,1: ARC counter has received a valid \qSTART\q.." group.long 0x24C++0x1F line.long 0x0 "ARC0_CTRL,ARCm control register" bitfld.long 0x0 20. "ARC_STOP_REQ,ARCm Stop request" "0,1" newline bitfld.long 0x0 16. "ARC_START_REQ,ARCm Start request" "0,1" line.long 0x4 "ARC0_RELOAD_VALUE,ARCm reload config register" hexmask.long 0x4 0.--31. 1. "ARC_RELOAD_VALUE,ARCm Reload Value" line.long 0x8 "ARC0_EXPIRY_CFG,ARCm expiry config register" hexmask.long 0x8 0.--31. 1. "ARC_EXPIRY_VALUE,ARCm Expiry Value" line.long 0xC "ARC0_COMPARE_1_CFG,ARCm compare 1 config register" hexmask.long 0xC 0.--31. 1. "ARC_COMPARE_1_VALUE,ARCm Compare register 1" line.long 0x10 "ARC0_COMPARE_2_CFG,ARCm compare 2 config register" hexmask.long 0x10 0.--31. 1. "ARC_COMPARE_2_VALUE,ARCm Compare register 2" line.long 0x14 "ARC0_COMPARE_3_CFG,ARCm compare 3 config register" hexmask.long 0x14 0.--31. 1. "ARC_COMPARE_3_VALUE,ARCm Compare register 3" line.long 0x18 "ARC0_COMPARE_4_CFG,ARCm compare 4 config register" hexmask.long 0x18 0.--31. 1. "ARC_COMPARE_4_VALUE,ARCm Compare register 4" line.long 0x1C "ARC0_INT_PULSE_EN_CFG,ARCm interrupt or pulse enable configuration register" bitfld.long 0x1C 8.--9. "ARC_INT_PULSE_EXPIRY_EN,ARCm counter interrupt or pulse on Counter Expiry Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding counter expiry is..,2: The pulse corresponding counter expiry is enabled.,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 6.--7. "ARC_INT_PULSE_C4_EN,ARCm counter interrupt or pulse on compare 4 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 4..,2: The pulse corresponding compare register 4 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 4.--5. "ARC_INT_PULSE_C3_EN,ARCm counter interrupt or pulse on compare 3 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 3..,2: The pulse corresponding compare register 3 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 2.--3. "ARC_INT_PULSE_C2_EN,ARCm counter interrupt or pulse on compare 2 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 2..,2: The pulse corresponding compare register 2 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 0.--1. "ARC_INT_PULSE_C1_EN,ARCm counter interrupt or pulse on compare 1 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 1..,2: The pulse corresponding compare register 1 on..,3: Neither interrupt nor pulse is generated based.." rgroup.long 0x26C++0x3 line.long 0x0 "ARC0_INT_STATUS,ARCm interrupt status register" bitfld.long 0x0 4. "ARC_INT_EXPIRY,ARCm counter interrupt on Expiry status" "0: The interrupt corresponding to ARCm Expiry is..,1: The interrupt corresponding to ARCm Expiry is.." newline bitfld.long 0x0 3. "ARC_INT_C4,ARCm counter interrupt on compare 1 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 2. "ARC_INT_C3,ARCm counter interrupt on compare 3 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 1. "ARC_INT_C2,ARCm counter interrupt on compare 2 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 0. "ARC_INT_C1,ARCm counter interrupt on compare 1 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." group.long 0x270++0x7 line.long 0x0 "ARC0_INT_CLR,ARCm interrupt clear register" bitfld.long 0x0 4. "ARC_INT_EXPIRY_CLR,ARCm counter clear interrupt on Expiry" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 3. "ARC_INT_C4_CLR,ARCm counter clear interrupt on compare 4 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 2. "ARC_INT_C3_CLR,ARCm counter clear interrupt on compare 3 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 1. "ARC_INT_C2_CLR,ARCm counter clear interrupt on compare 2 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 0. "ARC_INT_C1_CLR,ARCm counter clear interrupt on compare 1 result" "?,1: Writing to this bit clears.." line.long 0x4 "ARC0_EVENT_GEN_CFG,ARCm event generator config register" hexmask.long.word 0x4 16.--31. 1. "PRESCALER_VAL,ARCm Event Generator GST CLOCK Prescaler Value" newline bitfld.long 0x4 4.--6. "AUX_SOURCE_SYNC_MODE,ARCm Event Generator AUX Source Sync Mode" "0: Positive edge of Aux source (synchronized to GST..,1: Negative edge of Aux source (synchronized to GST..,2: Both Positive edge and Negative edge of Aux..,3: AUX source is synchronized to GST clock.,?,?,?,?" newline bitfld.long 0x4 0. "EVENT_SOURCE_SEL,ARCm Event Generator Source Selection" "0: GST Clock is selected as source for ARCm EVENT..,1: Auxiliary source is selected as source for ARCm.." rgroup.long 0x278++0x3 line.long 0x0 "ARC0_READ,ARCm read register" hexmask.long 0x0 0.--31. 1. "ARC_READ,ARCm Read value" group.long 0x280++0x7 line.long 0x0 "ARC1_DEBUG_CFG,ARCm debug config register" bitfld.long 0x0 4. "ARC_FRZ_IN_DEBUG,ARCm Freeze in Debug Mode" "0: ARC increments/decrements in debug mode as well,1: ARC stops incrementing/decrementing in debug mode" line.long 0x4 "ARC1_CFG,ARCm config register" bitfld.long 0x4 16. "ARC_RUN,ARCm Run Mode" "0: ARCm is set in One Time Mode,1: ARCm is set in Auto Reload Mode" newline bitfld.long 0x4 14.--15. "ARC_UPDATE_EVENT,ARCm Update Event" "0: Increment ARC on GST CLOCK PosEdge,1: Decrement ARC on GST CLOCK PosEdge,2: Increment ARC on GST CLOCK PosEDGE IF UPDATE..,3: Decrement ARC on GST CLOCK PosEDGE IF UPDATE.." rgroup.long 0x288++0x3 line.long 0x0 "ARC1_STATUS,ARCm status register" bitfld.long 0x0 12. "ARC_START_STATUS,ARCm Start Status" "0: ARC counter has not received a valid \qSTART\q..,1: ARC counter has received a valid \qSTART\q.." group.long 0x28C++0x1F line.long 0x0 "ARC1_CTRL,ARCm control register" bitfld.long 0x0 20. "ARC_STOP_REQ,ARCm Stop request" "0,1" newline bitfld.long 0x0 16. "ARC_START_REQ,ARCm Start request" "0,1" line.long 0x4 "ARC1_RELOAD_VALUE,ARCm reload config register" hexmask.long 0x4 0.--31. 1. "ARC_RELOAD_VALUE,ARCm Reload Value" line.long 0x8 "ARC1_EXPIRY_CFG,ARCm expiry config register" hexmask.long 0x8 0.--31. 1. "ARC_EXPIRY_VALUE,ARCm Expiry Value" line.long 0xC "ARC1_COMPARE_1_CFG,ARCm compare 1 config register" hexmask.long 0xC 0.--31. 1. "ARC_COMPARE_1_VALUE,ARCm Compare register 1" line.long 0x10 "ARC1_COMPARE_2_CFG,ARCm compare 2 config register" hexmask.long 0x10 0.--31. 1. "ARC_COMPARE_2_VALUE,ARCm Compare register 2" line.long 0x14 "ARC1_COMPARE_3_CFG,ARCm compare 3 config register" hexmask.long 0x14 0.--31. 1. "ARC_COMPARE_3_VALUE,ARCm Compare register 3" line.long 0x18 "ARC1_COMPARE_4_CFG,ARCm compare 4 config register" hexmask.long 0x18 0.--31. 1. "ARC_COMPARE_4_VALUE,ARCm Compare register 4" line.long 0x1C "ARC1_INT_PULSE_EN_CFG,ARCm interrupt or pulse enable configuration register" bitfld.long 0x1C 8.--9. "ARC_INT_PULSE_EXPIRY_EN,ARCm counter interrupt or pulse on Counter Expiry Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding counter expiry is..,2: The pulse corresponding counter expiry is enabled.,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 6.--7. "ARC_INT_PULSE_C4_EN,ARCm counter interrupt or pulse on compare 4 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 4..,2: The pulse corresponding compare register 4 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 4.--5. "ARC_INT_PULSE_C3_EN,ARCm counter interrupt or pulse on compare 3 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 3..,2: The pulse corresponding compare register 3 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 2.--3. "ARC_INT_PULSE_C2_EN,ARCm counter interrupt or pulse on compare 2 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 2..,2: The pulse corresponding compare register 2 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 0.--1. "ARC_INT_PULSE_C1_EN,ARCm counter interrupt or pulse on compare 1 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 1..,2: The pulse corresponding compare register 1 on..,3: Neither interrupt nor pulse is generated based.." rgroup.long 0x2AC++0x3 line.long 0x0 "ARC1_INT_STATUS,ARCm interrupt status register" bitfld.long 0x0 4. "ARC_INT_EXPIRY,ARCm counter interrupt on Expiry status" "0: The interrupt corresponding to ARCm Expiry is..,1: The interrupt corresponding to ARCm Expiry is.." newline bitfld.long 0x0 3. "ARC_INT_C4,ARCm counter interrupt on compare 1 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 2. "ARC_INT_C3,ARCm counter interrupt on compare 3 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 1. "ARC_INT_C2,ARCm counter interrupt on compare 2 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 0. "ARC_INT_C1,ARCm counter interrupt on compare 1 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." group.long 0x2B0++0x7 line.long 0x0 "ARC1_INT_CLR,ARCm interrupt clear register" bitfld.long 0x0 4. "ARC_INT_EXPIRY_CLR,ARCm counter clear interrupt on Expiry" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 3. "ARC_INT_C4_CLR,ARCm counter clear interrupt on compare 4 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 2. "ARC_INT_C3_CLR,ARCm counter clear interrupt on compare 3 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 1. "ARC_INT_C2_CLR,ARCm counter clear interrupt on compare 2 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 0. "ARC_INT_C1_CLR,ARCm counter clear interrupt on compare 1 result" "?,1: Writing to this bit clears.." line.long 0x4 "ARC1_EVENT_GEN_CFG,ARCm event generator config register" hexmask.long.word 0x4 16.--31. 1. "PRESCALER_VAL,ARCm Event Generator GST CLOCK Prescaler Value" newline bitfld.long 0x4 4.--6. "AUX_SOURCE_SYNC_MODE,ARCm Event Generator AUX Source Sync Mode" "0: Positive edge of Aux source (synchronized to GST..,1: Negative edge of Aux source (synchronized to GST..,2: Both Positive edge and Negative edge of Aux..,3: AUX source is synchronized to GST clock.,?,?,?,?" newline bitfld.long 0x4 0. "EVENT_SOURCE_SEL,ARCm Event Generator Source Selection" "0: GST Clock is selected as source for ARCm EVENT..,1: Auxiliary source is selected as source for ARCm.." rgroup.long 0x2B8++0x3 line.long 0x0 "ARC1_READ,ARCm read register" hexmask.long 0x0 0.--31. 1. "ARC_READ,ARCm Read value" group.long 0x2C0++0x7 line.long 0x0 "ARC2_DEBUG_CFG,ARCm debug config register" bitfld.long 0x0 4. "ARC_FRZ_IN_DEBUG,ARCm Freeze in Debug Mode" "0: ARC increments/decrements in debug mode as well,1: ARC stops incrementing/decrementing in debug mode" line.long 0x4 "ARC2_CFG,ARCm config register" bitfld.long 0x4 16. "ARC_RUN,ARCm Run Mode" "0: ARCm is set in One Time Mode,1: ARCm is set in Auto Reload Mode" newline bitfld.long 0x4 14.--15. "ARC_UPDATE_EVENT,ARCm Update Event" "0: Increment ARC on GST CLOCK PosEdge,1: Decrement ARC on GST CLOCK PosEdge,2: Increment ARC on GST CLOCK PosEDGE IF UPDATE..,3: Decrement ARC on GST CLOCK PosEDGE IF UPDATE.." rgroup.long 0x2C8++0x3 line.long 0x0 "ARC2_STATUS,ARCm status register" bitfld.long 0x0 12. "ARC_START_STATUS,ARCm Start Status" "0: ARC counter has not received a valid \qSTART\q..,1: ARC counter has received a valid \qSTART\q.." group.long 0x2CC++0x1F line.long 0x0 "ARC2_CTRL,ARCm control register" bitfld.long 0x0 20. "ARC_STOP_REQ,ARCm Stop request" "0,1" newline bitfld.long 0x0 16. "ARC_START_REQ,ARCm Start request" "0,1" line.long 0x4 "ARC2_RELOAD_VALUE,ARCm reload config register" hexmask.long 0x4 0.--31. 1. "ARC_RELOAD_VALUE,ARCm Reload Value" line.long 0x8 "ARC2_EXPIRY_CFG,ARCm expiry config register" hexmask.long 0x8 0.--31. 1. "ARC_EXPIRY_VALUE,ARCm Expiry Value" line.long 0xC "ARC2_COMPARE_1_CFG,ARCm compare 1 config register" hexmask.long 0xC 0.--31. 1. "ARC_COMPARE_1_VALUE,ARCm Compare register 1" line.long 0x10 "ARC2_COMPARE_2_CFG,ARCm compare 2 config register" hexmask.long 0x10 0.--31. 1. "ARC_COMPARE_2_VALUE,ARCm Compare register 2" line.long 0x14 "ARC2_COMPARE_3_CFG,ARCm compare 3 config register" hexmask.long 0x14 0.--31. 1. "ARC_COMPARE_3_VALUE,ARCm Compare register 3" line.long 0x18 "ARC2_COMPARE_4_CFG,ARCm compare 4 config register" hexmask.long 0x18 0.--31. 1. "ARC_COMPARE_4_VALUE,ARCm Compare register 4" line.long 0x1C "ARC2_INT_PULSE_EN_CFG,ARCm interrupt or pulse enable configuration register" bitfld.long 0x1C 8.--9. "ARC_INT_PULSE_EXPIRY_EN,ARCm counter interrupt or pulse on Counter Expiry Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding counter expiry is..,2: The pulse corresponding counter expiry is enabled.,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 6.--7. "ARC_INT_PULSE_C4_EN,ARCm counter interrupt or pulse on compare 4 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 4..,2: The pulse corresponding compare register 4 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 4.--5. "ARC_INT_PULSE_C3_EN,ARCm counter interrupt or pulse on compare 3 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 3..,2: The pulse corresponding compare register 3 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 2.--3. "ARC_INT_PULSE_C2_EN,ARCm counter interrupt or pulse on compare 2 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 2..,2: The pulse corresponding compare register 2 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 0.--1. "ARC_INT_PULSE_C1_EN,ARCm counter interrupt or pulse on compare 1 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 1..,2: The pulse corresponding compare register 1 on..,3: Neither interrupt nor pulse is generated based.." rgroup.long 0x2EC++0x3 line.long 0x0 "ARC2_INT_STATUS,ARCm interrupt status register" bitfld.long 0x0 4. "ARC_INT_EXPIRY,ARCm counter interrupt on Expiry status" "0: The interrupt corresponding to ARCm Expiry is..,1: The interrupt corresponding to ARCm Expiry is.." newline bitfld.long 0x0 3. "ARC_INT_C4,ARCm counter interrupt on compare 1 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 2. "ARC_INT_C3,ARCm counter interrupt on compare 3 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 1. "ARC_INT_C2,ARCm counter interrupt on compare 2 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 0. "ARC_INT_C1,ARCm counter interrupt on compare 1 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." group.long 0x2F0++0x7 line.long 0x0 "ARC2_INT_CLR,ARCm interrupt clear register" bitfld.long 0x0 4. "ARC_INT_EXPIRY_CLR,ARCm counter clear interrupt on Expiry" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 3. "ARC_INT_C4_CLR,ARCm counter clear interrupt on compare 4 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 2. "ARC_INT_C3_CLR,ARCm counter clear interrupt on compare 3 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 1. "ARC_INT_C2_CLR,ARCm counter clear interrupt on compare 2 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 0. "ARC_INT_C1_CLR,ARCm counter clear interrupt on compare 1 result" "?,1: Writing to this bit clears.." line.long 0x4 "ARC2_EVENT_GEN_CFG,ARCm event generator config register" hexmask.long.word 0x4 16.--31. 1. "PRESCALER_VAL,ARCm Event Generator GST CLOCK Prescaler Value" newline bitfld.long 0x4 4.--6. "AUX_SOURCE_SYNC_MODE,ARCm Event Generator AUX Source Sync Mode" "0: Positive edge of Aux source (synchronized to GST..,1: Negative edge of Aux source (synchronized to GST..,2: Both Positive edge and Negative edge of Aux..,3: AUX source is synchronized to GST clock.,?,?,?,?" newline bitfld.long 0x4 0. "EVENT_SOURCE_SEL,ARCm Event Generator Source Selection" "0: GST Clock is selected as source for ARCm EVENT..,1: Auxiliary source is selected as source for ARCm.." rgroup.long 0x2F8++0x3 line.long 0x0 "ARC2_READ,ARCm read register" hexmask.long 0x0 0.--31. 1. "ARC_READ,ARCm Read value" group.long 0x300++0x7 line.long 0x0 "ARC3_DEBUG_CFG,ARCm debug config register" bitfld.long 0x0 4. "ARC_FRZ_IN_DEBUG,ARCm Freeze in Debug Mode" "0: ARC increments/decrements in debug mode as well,1: ARC stops incrementing/decrementing in debug mode" line.long 0x4 "ARC3_CFG,ARCm config register" bitfld.long 0x4 16. "ARC_RUN,ARCm Run Mode" "0: ARCm is set in One Time Mode,1: ARCm is set in Auto Reload Mode" newline bitfld.long 0x4 14.--15. "ARC_UPDATE_EVENT,ARCm Update Event" "0: Increment ARC on GST CLOCK PosEdge,1: Decrement ARC on GST CLOCK PosEdge,2: Increment ARC on GST CLOCK PosEDGE IF UPDATE..,3: Decrement ARC on GST CLOCK PosEDGE IF UPDATE.." rgroup.long 0x308++0x3 line.long 0x0 "ARC3_STATUS,ARCm status register" bitfld.long 0x0 12. "ARC_START_STATUS,ARCm Start Status" "0: ARC counter has not received a valid \qSTART\q..,1: ARC counter has received a valid \qSTART\q.." group.long 0x30C++0x1F line.long 0x0 "ARC3_CTRL,ARCm control register" bitfld.long 0x0 20. "ARC_STOP_REQ,ARCm Stop request" "0,1" newline bitfld.long 0x0 16. "ARC_START_REQ,ARCm Start request" "0,1" line.long 0x4 "ARC3_RELOAD_VALUE,ARCm reload config register" hexmask.long 0x4 0.--31. 1. "ARC_RELOAD_VALUE,ARCm Reload Value" line.long 0x8 "ARC3_EXPIRY_CFG,ARCm expiry config register" hexmask.long 0x8 0.--31. 1. "ARC_EXPIRY_VALUE,ARCm Expiry Value" line.long 0xC "ARC3_COMPARE_1_CFG,ARCm compare 1 config register" hexmask.long 0xC 0.--31. 1. "ARC_COMPARE_1_VALUE,ARCm Compare register 1" line.long 0x10 "ARC3_COMPARE_2_CFG,ARCm compare 2 config register" hexmask.long 0x10 0.--31. 1. "ARC_COMPARE_2_VALUE,ARCm Compare register 2" line.long 0x14 "ARC3_COMPARE_3_CFG,ARCm compare 3 config register" hexmask.long 0x14 0.--31. 1. "ARC_COMPARE_3_VALUE,ARCm Compare register 3" line.long 0x18 "ARC3_COMPARE_4_CFG,ARCm compare 4 config register" hexmask.long 0x18 0.--31. 1. "ARC_COMPARE_4_VALUE,ARCm Compare register 4" line.long 0x1C "ARC3_INT_PULSE_EN_CFG,ARCm interrupt or pulse enable configuration register" bitfld.long 0x1C 8.--9. "ARC_INT_PULSE_EXPIRY_EN,ARCm counter interrupt or pulse on Counter Expiry Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding counter expiry is..,2: The pulse corresponding counter expiry is enabled.,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 6.--7. "ARC_INT_PULSE_C4_EN,ARCm counter interrupt or pulse on compare 4 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 4..,2: The pulse corresponding compare register 4 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 4.--5. "ARC_INT_PULSE_C3_EN,ARCm counter interrupt or pulse on compare 3 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 3..,2: The pulse corresponding compare register 3 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 2.--3. "ARC_INT_PULSE_C2_EN,ARCm counter interrupt or pulse on compare 2 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 2..,2: The pulse corresponding compare register 2 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 0.--1. "ARC_INT_PULSE_C1_EN,ARCm counter interrupt or pulse on compare 1 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 1..,2: The pulse corresponding compare register 1 on..,3: Neither interrupt nor pulse is generated based.." rgroup.long 0x32C++0x3 line.long 0x0 "ARC3_INT_STATUS,ARCm interrupt status register" bitfld.long 0x0 4. "ARC_INT_EXPIRY,ARCm counter interrupt on Expiry status" "0: The interrupt corresponding to ARCm Expiry is..,1: The interrupt corresponding to ARCm Expiry is.." newline bitfld.long 0x0 3. "ARC_INT_C4,ARCm counter interrupt on compare 1 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 2. "ARC_INT_C3,ARCm counter interrupt on compare 3 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 1. "ARC_INT_C2,ARCm counter interrupt on compare 2 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 0. "ARC_INT_C1,ARCm counter interrupt on compare 1 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." group.long 0x330++0x7 line.long 0x0 "ARC3_INT_CLR,ARCm interrupt clear register" bitfld.long 0x0 4. "ARC_INT_EXPIRY_CLR,ARCm counter clear interrupt on Expiry" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 3. "ARC_INT_C4_CLR,ARCm counter clear interrupt on compare 4 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 2. "ARC_INT_C3_CLR,ARCm counter clear interrupt on compare 3 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 1. "ARC_INT_C2_CLR,ARCm counter clear interrupt on compare 2 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 0. "ARC_INT_C1_CLR,ARCm counter clear interrupt on compare 1 result" "?,1: Writing to this bit clears.." line.long 0x4 "ARC3_EVENT_GEN_CFG,ARCm event generator config register" hexmask.long.word 0x4 16.--31. 1. "PRESCALER_VAL,ARCm Event Generator GST CLOCK Prescaler Value" newline bitfld.long 0x4 4.--6. "AUX_SOURCE_SYNC_MODE,ARCm Event Generator AUX Source Sync Mode" "0: Positive edge of Aux source (synchronized to GST..,1: Negative edge of Aux source (synchronized to GST..,2: Both Positive edge and Negative edge of Aux..,3: AUX source is synchronized to GST clock.,?,?,?,?" newline bitfld.long 0x4 0. "EVENT_SOURCE_SEL,ARCm Event Generator Source Selection" "0: GST Clock is selected as source for ARCm EVENT..,1: Auxiliary source is selected as source for ARCm.." rgroup.long 0x338++0x3 line.long 0x0 "ARC3_READ,ARCm read register" hexmask.long 0x0 0.--31. 1. "ARC_READ,ARCm Read value" group.long 0x340++0x7 line.long 0x0 "ARC4_DEBUG_CFG,ARCm debug config register" bitfld.long 0x0 4. "ARC_FRZ_IN_DEBUG,ARCm Freeze in Debug Mode" "0: ARC increments/decrements in debug mode as well,1: ARC stops incrementing/decrementing in debug mode" line.long 0x4 "ARC4_CFG,ARCm config register" bitfld.long 0x4 16. "ARC_RUN,ARCm Run Mode" "0: ARCm is set in One Time Mode,1: ARCm is set in Auto Reload Mode" newline bitfld.long 0x4 14.--15. "ARC_UPDATE_EVENT,ARCm Update Event" "0: Increment ARC on GST CLOCK PosEdge,1: Decrement ARC on GST CLOCK PosEdge,2: Increment ARC on GST CLOCK PosEDGE IF UPDATE..,3: Decrement ARC on GST CLOCK PosEDGE IF UPDATE.." rgroup.long 0x348++0x3 line.long 0x0 "ARC4_STATUS,ARCm status register" bitfld.long 0x0 12. "ARC_START_STATUS,ARCm Start Status" "0: ARC counter has not received a valid \qSTART\q..,1: ARC counter has received a valid \qSTART\q.." group.long 0x34C++0x1F line.long 0x0 "ARC4_CTRL,ARCm control register" bitfld.long 0x0 20. "ARC_STOP_REQ,ARCm Stop request" "0,1" newline bitfld.long 0x0 16. "ARC_START_REQ,ARCm Start request" "0,1" line.long 0x4 "ARC4_RELOAD_VALUE,ARCm reload config register" hexmask.long 0x4 0.--31. 1. "ARC_RELOAD_VALUE,ARCm Reload Value" line.long 0x8 "ARC4_EXPIRY_CFG,ARCm expiry config register" hexmask.long 0x8 0.--31. 1. "ARC_EXPIRY_VALUE,ARCm Expiry Value" line.long 0xC "ARC4_COMPARE_1_CFG,ARCm compare 1 config register" hexmask.long 0xC 0.--31. 1. "ARC_COMPARE_1_VALUE,ARCm Compare register 1" line.long 0x10 "ARC4_COMPARE_2_CFG,ARCm compare 2 config register" hexmask.long 0x10 0.--31. 1. "ARC_COMPARE_2_VALUE,ARCm Compare register 2" line.long 0x14 "ARC4_COMPARE_3_CFG,ARCm compare 3 config register" hexmask.long 0x14 0.--31. 1. "ARC_COMPARE_3_VALUE,ARCm Compare register 3" line.long 0x18 "ARC4_COMPARE_4_CFG,ARCm compare 4 config register" hexmask.long 0x18 0.--31. 1. "ARC_COMPARE_4_VALUE,ARCm Compare register 4" line.long 0x1C "ARC4_INT_PULSE_EN_CFG,ARCm interrupt or pulse enable configuration register" bitfld.long 0x1C 8.--9. "ARC_INT_PULSE_EXPIRY_EN,ARCm counter interrupt or pulse on Counter Expiry Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding counter expiry is..,2: The pulse corresponding counter expiry is enabled.,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 6.--7. "ARC_INT_PULSE_C4_EN,ARCm counter interrupt or pulse on compare 4 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 4..,2: The pulse corresponding compare register 4 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 4.--5. "ARC_INT_PULSE_C3_EN,ARCm counter interrupt or pulse on compare 3 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 3..,2: The pulse corresponding compare register 3 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 2.--3. "ARC_INT_PULSE_C2_EN,ARCm counter interrupt or pulse on compare 2 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 2..,2: The pulse corresponding compare register 2 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 0.--1. "ARC_INT_PULSE_C1_EN,ARCm counter interrupt or pulse on compare 1 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 1..,2: The pulse corresponding compare register 1 on..,3: Neither interrupt nor pulse is generated based.." rgroup.long 0x36C++0x3 line.long 0x0 "ARC4_INT_STATUS,ARCm interrupt status register" bitfld.long 0x0 4. "ARC_INT_EXPIRY,ARCm counter interrupt on Expiry status" "0: The interrupt corresponding to ARCm Expiry is..,1: The interrupt corresponding to ARCm Expiry is.." newline bitfld.long 0x0 3. "ARC_INT_C4,ARCm counter interrupt on compare 1 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 2. "ARC_INT_C3,ARCm counter interrupt on compare 3 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 1. "ARC_INT_C2,ARCm counter interrupt on compare 2 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 0. "ARC_INT_C1,ARCm counter interrupt on compare 1 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." group.long 0x370++0x7 line.long 0x0 "ARC4_INT_CLR,ARCm interrupt clear register" bitfld.long 0x0 4. "ARC_INT_EXPIRY_CLR,ARCm counter clear interrupt on Expiry" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 3. "ARC_INT_C4_CLR,ARCm counter clear interrupt on compare 4 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 2. "ARC_INT_C3_CLR,ARCm counter clear interrupt on compare 3 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 1. "ARC_INT_C2_CLR,ARCm counter clear interrupt on compare 2 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 0. "ARC_INT_C1_CLR,ARCm counter clear interrupt on compare 1 result" "?,1: Writing to this bit clears.." line.long 0x4 "ARC4_EVENT_GEN_CFG,ARCm event generator config register" hexmask.long.word 0x4 16.--31. 1. "PRESCALER_VAL,ARCm Event Generator GST CLOCK Prescaler Value" newline bitfld.long 0x4 4.--6. "AUX_SOURCE_SYNC_MODE,ARCm Event Generator AUX Source Sync Mode" "0: Positive edge of Aux source (synchronized to GST..,1: Negative edge of Aux source (synchronized to GST..,2: Both Positive edge and Negative edge of Aux..,3: AUX source is synchronized to GST clock.,?,?,?,?" newline bitfld.long 0x4 0. "EVENT_SOURCE_SEL,ARCm Event Generator Source Selection" "0: GST Clock is selected as source for ARCm EVENT..,1: Auxiliary source is selected as source for ARCm.." rgroup.long 0x378++0x3 line.long 0x0 "ARC4_READ,ARCm read register" hexmask.long 0x0 0.--31. 1. "ARC_READ,ARCm Read value" group.long 0x380++0x7 line.long 0x0 "ARC5_DEBUG_CFG,ARCm debug config register" bitfld.long 0x0 4. "ARC_FRZ_IN_DEBUG,ARCm Freeze in Debug Mode" "0: ARC increments/decrements in debug mode as well,1: ARC stops incrementing/decrementing in debug mode" line.long 0x4 "ARC5_CFG,ARCm config register" bitfld.long 0x4 16. "ARC_RUN,ARCm Run Mode" "0: ARCm is set in One Time Mode,1: ARCm is set in Auto Reload Mode" newline bitfld.long 0x4 14.--15. "ARC_UPDATE_EVENT,ARCm Update Event" "0: Increment ARC on GST CLOCK PosEdge,1: Decrement ARC on GST CLOCK PosEdge,2: Increment ARC on GST CLOCK PosEDGE IF UPDATE..,3: Decrement ARC on GST CLOCK PosEDGE IF UPDATE.." rgroup.long 0x388++0x3 line.long 0x0 "ARC5_STATUS,ARCm status register" bitfld.long 0x0 12. "ARC_START_STATUS,ARCm Start Status" "0: ARC counter has not received a valid \qSTART\q..,1: ARC counter has received a valid \qSTART\q.." group.long 0x38C++0x1F line.long 0x0 "ARC5_CTRL,ARCm control register" bitfld.long 0x0 20. "ARC_STOP_REQ,ARCm Stop request" "0,1" newline bitfld.long 0x0 16. "ARC_START_REQ,ARCm Start request" "0,1" line.long 0x4 "ARC5_RELOAD_VALUE,ARCm reload config register" hexmask.long 0x4 0.--31. 1. "ARC_RELOAD_VALUE,ARCm Reload Value" line.long 0x8 "ARC5_EXPIRY_CFG,ARCm expiry config register" hexmask.long 0x8 0.--31. 1. "ARC_EXPIRY_VALUE,ARCm Expiry Value" line.long 0xC "ARC5_COMPARE_1_CFG,ARCm compare 1 config register" hexmask.long 0xC 0.--31. 1. "ARC_COMPARE_1_VALUE,ARCm Compare register 1" line.long 0x10 "ARC5_COMPARE_2_CFG,ARCm compare 2 config register" hexmask.long 0x10 0.--31. 1. "ARC_COMPARE_2_VALUE,ARCm Compare register 2" line.long 0x14 "ARC5_COMPARE_3_CFG,ARCm compare 3 config register" hexmask.long 0x14 0.--31. 1. "ARC_COMPARE_3_VALUE,ARCm Compare register 3" line.long 0x18 "ARC5_COMPARE_4_CFG,ARCm compare 4 config register" hexmask.long 0x18 0.--31. 1. "ARC_COMPARE_4_VALUE,ARCm Compare register 4" line.long 0x1C "ARC5_INT_PULSE_EN_CFG,ARCm interrupt or pulse enable configuration register" bitfld.long 0x1C 8.--9. "ARC_INT_PULSE_EXPIRY_EN,ARCm counter interrupt or pulse on Counter Expiry Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding counter expiry is..,2: The pulse corresponding counter expiry is enabled.,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 6.--7. "ARC_INT_PULSE_C4_EN,ARCm counter interrupt or pulse on compare 4 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 4..,2: The pulse corresponding compare register 4 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 4.--5. "ARC_INT_PULSE_C3_EN,ARCm counter interrupt or pulse on compare 3 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 3..,2: The pulse corresponding compare register 3 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 2.--3. "ARC_INT_PULSE_C2_EN,ARCm counter interrupt or pulse on compare 2 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 2..,2: The pulse corresponding compare register 2 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 0.--1. "ARC_INT_PULSE_C1_EN,ARCm counter interrupt or pulse on compare 1 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 1..,2: The pulse corresponding compare register 1 on..,3: Neither interrupt nor pulse is generated based.." rgroup.long 0x3AC++0x3 line.long 0x0 "ARC5_INT_STATUS,ARCm interrupt status register" bitfld.long 0x0 4. "ARC_INT_EXPIRY,ARCm counter interrupt on Expiry status" "0: The interrupt corresponding to ARCm Expiry is..,1: The interrupt corresponding to ARCm Expiry is.." newline bitfld.long 0x0 3. "ARC_INT_C4,ARCm counter interrupt on compare 1 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 2. "ARC_INT_C3,ARCm counter interrupt on compare 3 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 1. "ARC_INT_C2,ARCm counter interrupt on compare 2 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 0. "ARC_INT_C1,ARCm counter interrupt on compare 1 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." group.long 0x3B0++0x7 line.long 0x0 "ARC5_INT_CLR,ARCm interrupt clear register" bitfld.long 0x0 4. "ARC_INT_EXPIRY_CLR,ARCm counter clear interrupt on Expiry" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 3. "ARC_INT_C4_CLR,ARCm counter clear interrupt on compare 4 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 2. "ARC_INT_C3_CLR,ARCm counter clear interrupt on compare 3 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 1. "ARC_INT_C2_CLR,ARCm counter clear interrupt on compare 2 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 0. "ARC_INT_C1_CLR,ARCm counter clear interrupt on compare 1 result" "?,1: Writing to this bit clears.." line.long 0x4 "ARC5_EVENT_GEN_CFG,ARCm event generator config register" hexmask.long.word 0x4 16.--31. 1. "PRESCALER_VAL,ARCm Event Generator GST CLOCK Prescaler Value" newline bitfld.long 0x4 4.--6. "AUX_SOURCE_SYNC_MODE,ARCm Event Generator AUX Source Sync Mode" "0: Positive edge of Aux source (synchronized to GST..,1: Negative edge of Aux source (synchronized to GST..,2: Both Positive edge and Negative edge of Aux..,3: AUX source is synchronized to GST clock.,?,?,?,?" newline bitfld.long 0x4 0. "EVENT_SOURCE_SEL,ARCm Event Generator Source Selection" "0: GST Clock is selected as source for ARCm EVENT..,1: Auxiliary source is selected as source for ARCm.." rgroup.long 0x3B8++0x3 line.long 0x0 "ARC5_READ,ARCm read register" hexmask.long 0x0 0.--31. 1. "ARC_READ,ARCm Read value" group.long 0x3C0++0x7 line.long 0x0 "ARC6_DEBUG_CFG,ARCm debug config register" bitfld.long 0x0 4. "ARC_FRZ_IN_DEBUG,ARCm Freeze in Debug Mode" "0: ARC increments/decrements in debug mode as well,1: ARC stops incrementing/decrementing in debug mode" line.long 0x4 "ARC6_CFG,ARCm config register" bitfld.long 0x4 16. "ARC_RUN,ARCm Run Mode" "0: ARCm is set in One Time Mode,1: ARCm is set in Auto Reload Mode" newline bitfld.long 0x4 14.--15. "ARC_UPDATE_EVENT,ARCm Update Event" "0: Increment ARC on GST CLOCK PosEdge,1: Decrement ARC on GST CLOCK PosEdge,2: Increment ARC on GST CLOCK PosEDGE IF UPDATE..,3: Decrement ARC on GST CLOCK PosEDGE IF UPDATE.." rgroup.long 0x3C8++0x3 line.long 0x0 "ARC6_STATUS,ARCm status register" bitfld.long 0x0 12. "ARC_START_STATUS,ARCm Start Status" "0: ARC counter has not received a valid \qSTART\q..,1: ARC counter has received a valid \qSTART\q.." group.long 0x3CC++0x1F line.long 0x0 "ARC6_CTRL,ARCm control register" bitfld.long 0x0 20. "ARC_STOP_REQ,ARCm Stop request" "0,1" newline bitfld.long 0x0 16. "ARC_START_REQ,ARCm Start request" "0,1" line.long 0x4 "ARC6_RELOAD_VALUE,ARCm reload config register" hexmask.long 0x4 0.--31. 1. "ARC_RELOAD_VALUE,ARCm Reload Value" line.long 0x8 "ARC6_EXPIRY_CFG,ARCm expiry config register" hexmask.long 0x8 0.--31. 1. "ARC_EXPIRY_VALUE,ARCm Expiry Value" line.long 0xC "ARC6_COMPARE_1_CFG,ARCm compare 1 config register" hexmask.long 0xC 0.--31. 1. "ARC_COMPARE_1_VALUE,ARCm Compare register 1" line.long 0x10 "ARC6_COMPARE_2_CFG,ARCm compare 2 config register" hexmask.long 0x10 0.--31. 1. "ARC_COMPARE_2_VALUE,ARCm Compare register 2" line.long 0x14 "ARC6_COMPARE_3_CFG,ARCm compare 3 config register" hexmask.long 0x14 0.--31. 1. "ARC_COMPARE_3_VALUE,ARCm Compare register 3" line.long 0x18 "ARC6_COMPARE_4_CFG,ARCm compare 4 config register" hexmask.long 0x18 0.--31. 1. "ARC_COMPARE_4_VALUE,ARCm Compare register 4" line.long 0x1C "ARC6_INT_PULSE_EN_CFG,ARCm interrupt or pulse enable configuration register" bitfld.long 0x1C 8.--9. "ARC_INT_PULSE_EXPIRY_EN,ARCm counter interrupt or pulse on Counter Expiry Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding counter expiry is..,2: The pulse corresponding counter expiry is enabled.,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 6.--7. "ARC_INT_PULSE_C4_EN,ARCm counter interrupt or pulse on compare 4 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 4..,2: The pulse corresponding compare register 4 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 4.--5. "ARC_INT_PULSE_C3_EN,ARCm counter interrupt or pulse on compare 3 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 3..,2: The pulse corresponding compare register 3 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 2.--3. "ARC_INT_PULSE_C2_EN,ARCm counter interrupt or pulse on compare 2 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 2..,2: The pulse corresponding compare register 2 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 0.--1. "ARC_INT_PULSE_C1_EN,ARCm counter interrupt or pulse on compare 1 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 1..,2: The pulse corresponding compare register 1 on..,3: Neither interrupt nor pulse is generated based.." rgroup.long 0x3EC++0x3 line.long 0x0 "ARC6_INT_STATUS,ARCm interrupt status register" bitfld.long 0x0 4. "ARC_INT_EXPIRY,ARCm counter interrupt on Expiry status" "0: The interrupt corresponding to ARCm Expiry is..,1: The interrupt corresponding to ARCm Expiry is.." newline bitfld.long 0x0 3. "ARC_INT_C4,ARCm counter interrupt on compare 1 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 2. "ARC_INT_C3,ARCm counter interrupt on compare 3 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 1. "ARC_INT_C2,ARCm counter interrupt on compare 2 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 0. "ARC_INT_C1,ARCm counter interrupt on compare 1 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." group.long 0x3F0++0x7 line.long 0x0 "ARC6_INT_CLR,ARCm interrupt clear register" bitfld.long 0x0 4. "ARC_INT_EXPIRY_CLR,ARCm counter clear interrupt on Expiry" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 3. "ARC_INT_C4_CLR,ARCm counter clear interrupt on compare 4 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 2. "ARC_INT_C3_CLR,ARCm counter clear interrupt on compare 3 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 1. "ARC_INT_C2_CLR,ARCm counter clear interrupt on compare 2 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 0. "ARC_INT_C1_CLR,ARCm counter clear interrupt on compare 1 result" "?,1: Writing to this bit clears.." line.long 0x4 "ARC6_EVENT_GEN_CFG,ARCm event generator config register" hexmask.long.word 0x4 16.--31. 1. "PRESCALER_VAL,ARCm Event Generator GST CLOCK Prescaler Value" newline bitfld.long 0x4 4.--6. "AUX_SOURCE_SYNC_MODE,ARCm Event Generator AUX Source Sync Mode" "0: Positive edge of Aux source (synchronized to GST..,1: Negative edge of Aux source (synchronized to GST..,2: Both Positive edge and Negative edge of Aux..,3: AUX source is synchronized to GST clock.,?,?,?,?" newline bitfld.long 0x4 0. "EVENT_SOURCE_SEL,ARCm Event Generator Source Selection" "0: GST Clock is selected as source for ARCm EVENT..,1: Auxiliary source is selected as source for ARCm.." rgroup.long 0x3F8++0x3 line.long 0x0 "ARC6_READ,ARCm read register" hexmask.long 0x0 0.--31. 1. "ARC_READ,ARCm Read value" group.long 0x400++0x7 line.long 0x0 "ARC7_DEBUG_CFG,ARCm debug config register" bitfld.long 0x0 4. "ARC_FRZ_IN_DEBUG,ARCm Freeze in Debug Mode" "0: ARC increments/decrements in debug mode as well,1: ARC stops incrementing/decrementing in debug mode" line.long 0x4 "ARC7_CFG,ARCm config register" bitfld.long 0x4 16. "ARC_RUN,ARCm Run Mode" "0: ARCm is set in One Time Mode,1: ARCm is set in Auto Reload Mode" newline bitfld.long 0x4 14.--15. "ARC_UPDATE_EVENT,ARCm Update Event" "0: Increment ARC on GST CLOCK PosEdge,1: Decrement ARC on GST CLOCK PosEdge,2: Increment ARC on GST CLOCK PosEDGE IF UPDATE..,3: Decrement ARC on GST CLOCK PosEDGE IF UPDATE.." rgroup.long 0x408++0x3 line.long 0x0 "ARC7_STATUS,ARCm status register" bitfld.long 0x0 12. "ARC_START_STATUS,ARCm Start Status" "0: ARC counter has not received a valid 'START'..,1: ARC counter has received a valid 'START' request.." group.long 0x40C++0x1F line.long 0x0 "ARC7_CTRL,ARCm control register" bitfld.long 0x0 20. "ARC_STOP_REQ,ARCm Stop request" "0,1" newline bitfld.long 0x0 16. "ARC_START_REQ,ARCm Start request" "0,1" line.long 0x4 "ARC7_RELOAD_VALUE,ARCm reload config register" hexmask.long 0x4 0.--31. 1. "ARC_RELOAD_VALUE,ARCm Reload Value" line.long 0x8 "ARC7_EXPIRY_CFG,ARCm expiry config register" hexmask.long 0x8 0.--31. 1. "ARC_EXPIRY_VALUE,ARCm Expiry Value" line.long 0xC "ARC7_COMPARE_1_CFG,ARCm compare 1 config register" hexmask.long 0xC 0.--31. 1. "ARC_COMPARE_1_VALUE,ARCm Compare register 1" line.long 0x10 "ARC7_COMPARE_2_CFG,ARCm compare 2 config register" hexmask.long 0x10 0.--31. 1. "ARC_COMPARE_2_VALUE,ARCm Compare register 2" line.long 0x14 "ARC7_COMPARE_3_CFG,ARCm compare 3 config register" hexmask.long 0x14 0.--31. 1. "ARC_COMPARE_3_VALUE,ARCm Compare register 3" line.long 0x18 "ARC7_COMPARE_4_CFG,ARCm compare 4 config register" hexmask.long 0x18 0.--31. 1. "ARC_COMPARE_4_VALUE,ARCm Compare register 4" line.long 0x1C "ARC7_INT_PULSE_EN_CFG,ARCm interrupt or pulse enable configuration register" bitfld.long 0x1C 8.--9. "ARC_INT_PULSE_EXPIRY_EN,ARCm counter interrupt or pulse on Counter Expiry Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding counter expiry is..,2: The pulse corresponding counter expiry is enabled.,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 6.--7. "ARC_INT_PULSE_C4_EN,ARCm counter interrupt or pulse on compare 4 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 4..,2: The pulse corresponding compare register 4 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 4.--5. "ARC_INT_PULSE_C3_EN,ARCm counter interrupt or pulse on compare 3 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 3..,2: The pulse corresponding compare register 3 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 2.--3. "ARC_INT_PULSE_C2_EN,ARCm counter interrupt or pulse on compare 2 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 2..,2: The pulse corresponding compare register 2 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 0.--1. "ARC_INT_PULSE_C1_EN,ARCm counter interrupt or pulse on compare 1 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 1..,2: The pulse corresponding compare register 1 on..,3: Neither interrupt nor pulse is generated based.." rgroup.long 0x42C++0x3 line.long 0x0 "ARC7_INT_STATUS,ARCm interrupt status register" bitfld.long 0x0 4. "ARC_INT_EXPIRY,ARCm counter interrupt on Expiry status" "0: The interrupt corresponding to ARCm Expiry is..,1: The interrupt corresponding to ARCm Expiry is.." newline bitfld.long 0x0 3. "ARC_INT_C4,ARCm counter interrupt on compare 1 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 2. "ARC_INT_C3,ARCm counter interrupt on compare 3 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 1. "ARC_INT_C2,ARCm counter interrupt on compare 2 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 0. "ARC_INT_C1,ARCm counter interrupt on compare 1 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." group.long 0x430++0x7 line.long 0x0 "ARC7_INT_CLR,ARCm interrupt clear register" bitfld.long 0x0 4. "ARC_INT_EXPIRY_CLR,ARCm counter clear interrupt on Expiry" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 3. "ARC_INT_C4_CLR,ARCm counter clear interrupt on compare 4 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 2. "ARC_INT_C3_CLR,ARCm counter clear interrupt on compare 3 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 1. "ARC_INT_C2_CLR,ARCm counter clear interrupt on compare 2 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 0. "ARC_INT_C1_CLR,ARCm counter clear interrupt on compare 1 result" "?,1: Writing to this bit clears.." line.long 0x4 "ARC7_EVENT_GEN_CFG,ARCm event generator config register" hexmask.long.word 0x4 16.--31. 1. "PRESCALER_VAL,ARCm Event Generator GST CLOCK Prescaler Value" newline bitfld.long 0x4 4.--6. "AUX_SOURCE_SYNC_MODE,ARCm Event Generator AUX Source Sync Mode" "0: Positive edge of Aux source (synchronized to GST..,1: Negative edge of Aux source (synchronized to GST..,2: Both Positive edge and Negative edge of Aux..,3: AUX source is synchronized to GST clock.,?,?,?,?" newline bitfld.long 0x4 0. "EVENT_SOURCE_SEL,ARCm Event Generator Source Selection" "0: GST Clock is selected as source for ARCm EVENT..,1: Auxiliary source is selected as source for ARCm.." rgroup.long 0x438++0x3 line.long 0x0 "ARC7_READ,ARCm read register" hexmask.long 0x0 0.--31. 1. "ARC_READ,ARCm Read value" group.long 0x440++0x7 line.long 0x0 "ARC8_DEBUG_CFG,ARCm debug config register" bitfld.long 0x0 4. "ARC_FRZ_IN_DEBUG,ARCm Freeze in Debug Mode" "0: ARC increments/decrements in debug mode as well,1: ARC stops incrementing/decrementing in debug mode" line.long 0x4 "ARC8_CFG,ARCm config register" bitfld.long 0x4 16. "ARC_RUN,ARCm Run Mode" "0: ARCm is set in One Time Mode,1: ARCm is set in Auto Reload Mode" newline bitfld.long 0x4 14.--15. "ARC_UPDATE_EVENT,ARCm Update Event" "0: Increment ARC on GST CLOCK PosEdge,1: Decrement ARC on GST CLOCK PosEdge,2: Increment ARC on GST CLOCK PosEDGE IF UPDATE..,3: Decrement ARC on GST CLOCK PosEDGE IF UPDATE.." rgroup.long 0x448++0x3 line.long 0x0 "ARC8_STATUS,ARCm status register" bitfld.long 0x0 12. "ARC_START_STATUS,ARCm Start Status" "0: ARC counter has not received a valid \qSTART\q..,1: ARC counter has received a valid \qSTART\q.." group.long 0x44C++0x1F line.long 0x0 "ARC8_CTRL,ARCm control register" bitfld.long 0x0 20. "ARC_STOP_REQ,ARCm Stop request" "0,1" newline bitfld.long 0x0 16. "ARC_START_REQ,ARCm Start request" "0,1" line.long 0x4 "ARC8_RELOAD_VALUE,ARCm reload config register" hexmask.long 0x4 0.--31. 1. "ARC_RELOAD_VALUE,ARCm Reload Value" line.long 0x8 "ARC8_EXPIRY_CFG,ARCm expiry config register" hexmask.long 0x8 0.--31. 1. "ARC_EXPIRY_VALUE,ARCm Expiry Value" line.long 0xC "ARC8_COMPARE_1_CFG,ARCm compare 1 config register" hexmask.long 0xC 0.--31. 1. "ARC_COMPARE_1_VALUE,ARCm Compare register 1" line.long 0x10 "ARC8_COMPARE_2_CFG,ARCm compare 2 config register" hexmask.long 0x10 0.--31. 1. "ARC_COMPARE_2_VALUE,ARCm Compare register 2" line.long 0x14 "ARC8_COMPARE_3_CFG,ARCm compare 3 config register" hexmask.long 0x14 0.--31. 1. "ARC_COMPARE_3_VALUE,ARCm Compare register 3" line.long 0x18 "ARC8_COMPARE_4_CFG,ARCm compare 4 config register" hexmask.long 0x18 0.--31. 1. "ARC_COMPARE_4_VALUE,ARCm Compare register 4" line.long 0x1C "ARC8_INT_PULSE_EN_CFG,ARCm interrupt or pulse enable configuration register" bitfld.long 0x1C 8.--9. "ARC_INT_PULSE_EXPIRY_EN,ARCm counter interrupt or pulse on Counter Expiry Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding counter expiry is..,2: The pulse corresponding counter expiry is enabled.,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 6.--7. "ARC_INT_PULSE_C4_EN,ARCm counter interrupt or pulse on compare 4 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 4..,2: The pulse corresponding compare register 4 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 4.--5. "ARC_INT_PULSE_C3_EN,ARCm counter interrupt or pulse on compare 3 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 3..,2: The pulse corresponding compare register 3 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 2.--3. "ARC_INT_PULSE_C2_EN,ARCm counter interrupt or pulse on compare 2 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 2..,2: The pulse corresponding compare register 2 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 0.--1. "ARC_INT_PULSE_C1_EN,ARCm counter interrupt or pulse on compare 1 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 1..,2: The pulse corresponding compare register 1 on..,3: Neither interrupt nor pulse is generated based.." rgroup.long 0x46C++0x3 line.long 0x0 "ARC8_INT_STATUS,ARCm interrupt status register" bitfld.long 0x0 4. "ARC_INT_EXPIRY,ARCm counter interrupt on Expiry status" "0: The interrupt corresponding to ARCm Expiry is..,1: The interrupt corresponding to ARCm Expiry is.." newline bitfld.long 0x0 3. "ARC_INT_C4,ARCm counter interrupt on compare 1 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 2. "ARC_INT_C3,ARCm counter interrupt on compare 3 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 1. "ARC_INT_C2,ARCm counter interrupt on compare 2 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 0. "ARC_INT_C1,ARCm counter interrupt on compare 1 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." group.long 0x470++0x7 line.long 0x0 "ARC8_INT_CLR,ARCm interrupt clear register" bitfld.long 0x0 4. "ARC_INT_EXPIRY_CLR,ARCm counter clear interrupt on Expiry" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 3. "ARC_INT_C4_CLR,ARCm counter clear interrupt on compare 4 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 2. "ARC_INT_C3_CLR,ARCm counter clear interrupt on compare 3 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 1. "ARC_INT_C2_CLR,ARCm counter clear interrupt on compare 2 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 0. "ARC_INT_C1_CLR,ARCm counter clear interrupt on compare 1 result" "?,1: Writing to this bit clears.." line.long 0x4 "ARC8_EVENT_GEN_CFG,ARCm event generator config register" hexmask.long.word 0x4 16.--31. 1. "PRESCALER_VAL,ARCm Event Generator GST CLOCK Prescaler Value" newline bitfld.long 0x4 4.--6. "AUX_SOURCE_SYNC_MODE,ARCm Event Generator AUX Source Sync Mode" "0: Positive edge of Aux source (synchronized to GST..,1: Negative edge of Aux source (synchronized to GST..,2: Both Positive edge and Negative edge of Aux..,3: AUX source is synchronized to GST clock.,?,?,?,?" newline bitfld.long 0x4 0. "EVENT_SOURCE_SEL,ARCm Event Generator Source Selection" "0: GST Clock is selected as source for ARCm EVENT..,1: Auxiliary source is selected as source for ARCm.." rgroup.long 0x478++0x3 line.long 0x0 "ARC8_READ,ARCm read register" hexmask.long 0x0 0.--31. 1. "ARC_READ,ARCm Read value" group.long 0x480++0x7 line.long 0x0 "ARC9_DEBUG_CFG,ARCm debug config register" bitfld.long 0x0 4. "ARC_FRZ_IN_DEBUG,ARCm Freeze in Debug Mode" "0: ARC increments/decrements in debug mode as well,1: ARC stops incrementing/decrementing in debug mode" line.long 0x4 "ARC9_CFG,ARCm config register" bitfld.long 0x4 16. "ARC_RUN,ARCm Run Mode" "0: ARCm is set in One Time Mode,1: ARCm is set in Auto Reload Mode" newline bitfld.long 0x4 14.--15. "ARC_UPDATE_EVENT,ARCm Update Event" "0: Increment ARC on GST CLOCK PosEdge,1: Decrement ARC on GST CLOCK PosEdge,2: Increment ARC on GST CLOCK PosEDGE IF UPDATE..,3: Decrement ARC on GST CLOCK PosEDGE IF UPDATE.." rgroup.long 0x488++0x3 line.long 0x0 "ARC9_STATUS,ARCm status register" bitfld.long 0x0 12. "ARC_START_STATUS,ARCm Start Status" "0: ARC counter has not received a valid \qSTART\q..,1: ARC counter has received a valid \qSTART\q.." group.long 0x48C++0x1F line.long 0x0 "ARC9_CTRL,ARCm control register" bitfld.long 0x0 20. "ARC_STOP_REQ,ARCm Stop request" "0,1" newline bitfld.long 0x0 16. "ARC_START_REQ,ARCm Start request" "0,1" line.long 0x4 "ARC9_RELOAD_VALUE,ARCm reload config register" hexmask.long 0x4 0.--31. 1. "ARC_RELOAD_VALUE,ARCm Reload Value" line.long 0x8 "ARC9_EXPIRY_CFG,ARCm expiry config register" hexmask.long 0x8 0.--31. 1. "ARC_EXPIRY_VALUE,ARCm Expiry Value" line.long 0xC "ARC9_COMPARE_1_CFG,ARCm compare 1 config register" hexmask.long 0xC 0.--31. 1. "ARC_COMPARE_1_VALUE,ARCm Compare register 1" line.long 0x10 "ARC9_COMPARE_2_CFG,ARCm compare 2 config register" hexmask.long 0x10 0.--31. 1. "ARC_COMPARE_2_VALUE,ARCm Compare register 2" line.long 0x14 "ARC9_COMPARE_3_CFG,ARCm compare 3 config register" hexmask.long 0x14 0.--31. 1. "ARC_COMPARE_3_VALUE,ARCm Compare register 3" line.long 0x18 "ARC9_COMPARE_4_CFG,ARCm compare 4 config register" hexmask.long 0x18 0.--31. 1. "ARC_COMPARE_4_VALUE,ARCm Compare register 4" line.long 0x1C "ARC9_INT_PULSE_EN_CFG,ARCm interrupt or pulse enable configuration register" bitfld.long 0x1C 8.--9. "ARC_INT_PULSE_EXPIRY_EN,ARCm counter interrupt or pulse on Counter Expiry Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding counter expiry is..,2: The pulse corresponding counter expiry is enabled.,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 6.--7. "ARC_INT_PULSE_C4_EN,ARCm counter interrupt or pulse on compare 4 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 4..,2: The pulse corresponding compare register 4 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 4.--5. "ARC_INT_PULSE_C3_EN,ARCm counter interrupt or pulse on compare 3 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 3..,2: The pulse corresponding compare register 3 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 2.--3. "ARC_INT_PULSE_C2_EN,ARCm counter interrupt or pulse on compare 2 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 2..,2: The pulse corresponding compare register 2 on..,3: Neither interrupt nor pulse is generated based.." newline bitfld.long 0x1C 0.--1. "ARC_INT_PULSE_C1_EN,ARCm counter interrupt or pulse on compare 1 result Enable" "0: Neither interrupt nor pulse is generated based..,1: The interrupt corresponding compare register 1..,2: The pulse corresponding compare register 1 on..,3: Neither interrupt nor pulse is generated based.." rgroup.long 0x4AC++0x3 line.long 0x0 "ARC9_INT_STATUS,ARCm interrupt status register" bitfld.long 0x0 4. "ARC_INT_EXPIRY,ARCm counter interrupt on Expiry status" "0: The interrupt corresponding to ARCm Expiry is..,1: The interrupt corresponding to ARCm Expiry is.." newline bitfld.long 0x0 3. "ARC_INT_C4,ARCm counter interrupt on compare 1 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 2. "ARC_INT_C3,ARCm counter interrupt on compare 3 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 1. "ARC_INT_C2,ARCm counter interrupt on compare 2 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." newline bitfld.long 0x0 0. "ARC_INT_C1,ARCm counter interrupt on compare 1 result status" "0: The interrupt corresponding to compare register..,1: The interrupt corresponding to compare register.." group.long 0x4B0++0x7 line.long 0x0 "ARC9_INT_CLR,ARCm interrupt clear register" bitfld.long 0x0 4. "ARC_INT_EXPIRY_CLR,ARCm counter clear interrupt on Expiry" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 3. "ARC_INT_C4_CLR,ARCm counter clear interrupt on compare 4 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 2. "ARC_INT_C3_CLR,ARCm counter clear interrupt on compare 3 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 1. "ARC_INT_C2_CLR,ARCm counter clear interrupt on compare 2 result" "?,1: Writing to this bit clears.." newline bitfld.long 0x0 0. "ARC_INT_C1_CLR,ARCm counter clear interrupt on compare 1 result" "?,1: Writing to this bit clears.." line.long 0x4 "ARC9_EVENT_GEN_CFG,ARCm event generator config register" hexmask.long.word 0x4 16.--31. 1. "PRESCALER_VAL,ARCm Event Generator GST CLOCK Prescaler Value" newline bitfld.long 0x4 4.--6. "AUX_SOURCE_SYNC_MODE,ARCm Event Generator AUX Source Sync Mode" "0: Positive edge of Aux source (synchronized to GST..,1: Negative edge of Aux source (synchronized to GST..,2: Both Positive edge and Negative edge of Aux..,3: AUX source is synchronized to GST clock.,?,?,?,?" newline bitfld.long 0x4 0. "EVENT_SOURCE_SEL,ARCm Event Generator Source Selection" "0: GST Clock is selected as source for ARCm EVENT..,1: Auxiliary source is selected as source for ARCm.." rgroup.long 0x4B8++0x3 line.long 0x0 "ARC9_READ,ARCm read register" hexmask.long 0x0 0.--31. 1. "ARC_READ,ARCm Read value" group.long 0xA40++0xB line.long 0x0 "TS0_UPDATE_EVENT_STRETCH_CFG,Timestamp channel 0 update event stretch register" hexmask.long.byte 0x0 8.--15. 1. "TS_UPDATE_EVENT_STRETCH_CYCLE,Timestamp channel k Update Event Stretch Cycle" newline bitfld.long 0x0 0. "TS_UP_EVENT_STRETCH_EN,Timestamp Channel k Update Event Stretch Enable" "0: Update Event is not stretched,1: Update Event is stretched" line.long 0x4 "TS0_SOURCE_SEL_CFG,Timestamp channel 0 source select register" bitfld.long 0x4 0.--1. "TS_SOURCE_SEL,Timestamp Channel k Source Select" "0: TBU or timestamp channel is based on NSC bus,1: TBU or timestamp channel is based on External..,2: TBU or timestamp channel is based on External..,3: TBU or timestamp channel is based on NSC bus" line.long 0x8 "TS0_BIT_SEL_CFG,Timestamp channel 0 bit select register" hexmask.long.byte 0x8 0.--7. 1. "TS_SOURCE_LSB,Timestamp Channel k Source LSB" group.long 0xA50++0xB line.long 0x0 "TS1_UPDATE_EVENT_STRETCH_CFG,Timestamp channel 1 update event stretch register" hexmask.long.byte 0x0 8.--15. 1. "TS_UPDATE_EVENT_STRETCH_CYCLE,Timestamp channel k Update Event Stretch Cycle" newline bitfld.long 0x0 0. "TS_UP_EVENT_STRETCH_EN,Timestamp Channel k Update Event Stretch Enable" "0: Update Event is not stretched,1: Update Event is stretched" line.long 0x4 "TS1_SOURCE_SEL_CFG,Timestamp channel 1 source select register" bitfld.long 0x4 0.--1. "TS_SOURCE_SEL,Timestamp Channel k Source Select" "0: TBU or timestamp channel is based on NSC bus,1: TBU or timestamp channel is based on External..,2: TBU or timestamp channel is based on External..,3: TBU or timestamp channel is based on NSC bus" line.long 0x8 "TS1_BIT_SEL_CFG,Timestamp channel 1 bit select register" hexmask.long.byte 0x8 0.--7. 1. "TS_SOURCE_LSB,Timestamp Channel k Source LSB" group.long 0xA60++0xB line.long 0x0 "TS2_UPDATE_EVENT_STRETCH_CFG,Timestamp channel 2 update event stretch register" hexmask.long.byte 0x0 8.--15. 1. "TS_UPDATE_EVENT_STRETCH_CYCLE,Timestamp channel k Update Event Stretch Cycle" newline bitfld.long 0x0 0. "TS_UP_EVENT_STRETCH_EN,Timestamp Channel k Update Event Stretch Enable" "0: Update Event is not stretched,1: Update Event is stretched" line.long 0x4 "TS2_SOURCE_SEL_CFG,Timestamp channel 2 source select register" bitfld.long 0x4 0.--1. "TS_SOURCE_SEL,Timestamp Channel k Source Select" "0: TBU or timestamp channel is based on NSC bus,1: TBU or timestamp channel is based on External..,2: TBU or timestamp channel is based on External..,3: TBU or timestamp channel is based on NSC bus" line.long 0x8 "TS2_BIT_SEL_CFG,Timestamp channel 2 bit select register" hexmask.long.byte 0x8 0.--7. 1. "TS_SOURCE_LSB,Timestamp Channel k Source LSB" group.long 0xA70++0xB line.long 0x0 "TS3_UPDATE_EVENT_STRETCH_CFG,Timestamp channel 3 update event stretch register" hexmask.long.byte 0x0 8.--15. 1. "TS_UPDATE_EVENT_STRETCH_CYCLE,Timestamp channel k Update Event Stretch Cycle" newline bitfld.long 0x0 0. "TS_UP_EVENT_STRETCH_EN,Timestamp Channel k Update Event Stretch Enable" "0: Update Event is not stretched,1: Update Event is stretched" line.long 0x4 "TS3_SOURCE_SEL_CFG,Timestamp channel 3 source select register" bitfld.long 0x4 0.--1. "TS_SOURCE_SEL,Timestamp Channel k Source Select" "0: TBU or timestamp channel is based on NSC bus,1: TBU or timestamp channel is based on External..,2: TBU or timestamp channel is based on External..,3: TBU or timestamp channel is based on NSC bus" line.long 0x8 "TS3_BIT_SEL_CFG,Timestamp channel 3 bit select register" hexmask.long.byte 0x8 0.--7. 1. "TS_SOURCE_LSB,Timestamp Channel k Source LSB" group.long 0xA80++0xB line.long 0x0 "TS4_UPDATE_EVENT_STRETCH_CFG,Timestamp channel 4 update event stretch register" hexmask.long.byte 0x0 8.--15. 1. "TS_UPDATE_EVENT_STRETCH_CYCLE,Timestamp channel k Update Event Stretch Cycle" newline bitfld.long 0x0 0. "TS_UP_EVENT_STRETCH_EN,Timestamp Channel k Update Event Stretch Enable" "0: Update Event is not stretched,1: Update Event is stretched" line.long 0x4 "TS4_SOURCE_SEL_CFG,Timestamp channel 4 source select register" bitfld.long 0x4 0.--1. "TS_SOURCE_SEL,Timestamp Channel k Source Select" "0: TBU or timestamp channel is based on NSC bus,1: TBU or timestamp channel is based on External..,2: TBU or timestamp channel is based on External..,3: TBU or timestamp channel is based on NSC bus" line.long 0x8 "TS4_BIT_SEL_CFG,Timestamp channel 4 bit select register" hexmask.long.byte 0x8 0.--7. 1. "TS_SOURCE_LSB,Timestamp Channel k Source LSB" group.long 0xA90++0xB line.long 0x0 "TS5_UPDATE_EVENT_STRETCH_CFG,Timestamp channel 5 update event stretch register" hexmask.long.byte 0x0 8.--15. 1. "TS_UPDATE_EVENT_STRETCH_CYCLE,Timestamp channel k Update Event Stretch Cycle" newline bitfld.long 0x0 0. "TS_UP_EVENT_STRETCH_EN,Timestamp Channel k Update Event Stretch Enable" "0: Update Event is not stretched,1: Update Event is stretched" line.long 0x4 "TS5_SOURCE_SEL_CFG,Timestamp channel 5 source select register" bitfld.long 0x4 0.--1. "TS_SOURCE_SEL,Timestamp Channel k Source Select" "0: TBU or timestamp channel is based on NSC bus,1: TBU or timestamp channel is based on External..,2: TBU or timestamp channel is based on External..,3: TBU or timestamp channel is based on NSC bus" line.long 0x8 "TS5_BIT_SEL_CFG,Timestamp channel 5 bit select register" hexmask.long.byte 0x8 0.--7. 1. "TS_SOURCE_LSB,Timestamp Channel k Source LSB" group.long 0xAC0++0x13 line.long 0x0 "GLBL_FRZ_IN_DBG_1_CFG,Global freeze in debug 1 config register" bitfld.long 0x0 31. "GST_FRZ_IN_STOP_MODE,GST freeze in STOP MODE" "0: Counters/Timers in GST do not stop/freeze in..,1: All counters/timers in GST stops/freezes in STOP.." newline bitfld.long 0x0 20. "OTC3_FRZ_IN_DEBUG,OTC3 Freeze in Debug Mode" "0: OTC3 increments in debug mode as well,1: OTC3 stops incrementing in debug mode" newline bitfld.long 0x0 16. "OTC2_FRZ_IN_DEBUG,OTC2 Freeze in Debug Mode" "0: OTC2 increments in debug mode as well,1: OTC2 stops incrementing in debug mode" newline bitfld.long 0x0 12. "OTC1_FRZ_IN_DEBUG,OTC1 Freeze in Debug Mode" "0: OTC1 increments in debug mode as well,1: OTC1 stops incrementing in debug mode" newline bitfld.long 0x0 8. "OTC0_FRZ_IN_DEBUG,OTC0 Freeze in Debug Mode" "0: OTC0 increments in debug mode as well,1: OTC0 stops incrementing in debug mode" newline bitfld.long 0x0 4. "EXNTP_FRZ_IN_DEBUG,ExNTP Freeze in Debug Mode" "0: ExNTP increments in debug mode as well,1: ExNTP stops incrementing in debug mode" newline bitfld.long 0x0 0. "NSC_FRZ_IN_DEBUG_GLBL,NSC Freeze in Debug Mode" "0: NSC increments in debug mode as well,1: NSC stops incrementing in debug mode" line.long 0x4 "GLBL_FRZ_IN_DBG_2_CFG,Global freeze in debug 2 config register" bitfld.long 0x4 9. "ARC9_FRZ_IN_DEBUG,ARC9 Freeze in Debug Mode" "0: ARC increments/decrements in debug mode as well,1: ARC stops incrementing/decrementing in debug mode" newline bitfld.long 0x4 8. "ARC8_FRZ_IN_DEBUG,ARC8 Freeze in Debug Mode" "0: ARC increments/decrements in debug mode as well,1: ARC stops incrementing/decrementing in debug mode" newline bitfld.long 0x4 7. "ARC7_FRZ_IN_DEBUG,ARC7 Freeze in Debug Mode" "0: ARC increments/decrements in debug mode as well,1: ARC stops incrementing/decrementing in debug mode" newline bitfld.long 0x4 6. "ARC6_FRZ_IN_DEBUG,ARC6 Freeze in Debug Mode" "0: ARC increments/decrements in debug mode as well,1: ARC stops incrementing/decrementing in debug mode" newline bitfld.long 0x4 5. "ARC5_FRZ_IN_DEBUG,ARC5 Freeze in Debug Mode" "0: ARC increments/decrements in debug mode as well,1: ARC stops incrementing/decrementing in debug mode" newline bitfld.long 0x4 4. "ARC4_FRZ_IN_DEBUG,ARC4 Freeze in Debug Mode" "0: ARC increments/decrements in debug mode as well,1: ARC stops incrementing/decrementing in debug mode" newline bitfld.long 0x4 3. "ARC3_FRZ_IN_DEBUG,ARC3 Freeze in Debug Mode" "0: ARC increments/decrements in debug mode as well,1: ARC stops incrementing/decrementing in debug mode" newline bitfld.long 0x4 2. "ARC2_FRZ_IN_DEBUG,ARC2 Freeze in Debug Mode" "0: ARC increments/decrements in debug mode as well,1: ARC stops incrementing/decrementing in debug mode" newline bitfld.long 0x4 1. "ARC1_FRZ_IN_DEBUG,ARC1 Freeze in Debug Mode" "0: ARC increments/decrements in debug mode as well,1: ARC stops incrementing/decrementing in debug mode" newline bitfld.long 0x4 0. "ARC0_FRZ_IN_DEBUG,ARC0 Freeze in Debug Mode" "0: ARC increments/decrements in debug mode as well,1: ARC stops incrementing/decrementing in debug mode" line.long 0x8 "GLBL_LATCH_CTRL,Global control to latch counter/timer current value" bitfld.long 0x8 20. "EXNTP_LATCH_CTRL,ExNTP Latch control" "?,1: Writing 1 on this bit latches the current value.." newline bitfld.long 0x8 16. "NSC_LATCH_CTRL,NSC Latch control" "?,1: Writing 1 on this bit latches the current value.." newline bitfld.long 0x8 12. "OTC3_LATCH_CTRL,OTC3 Latch control" "?,1: Writing 1 on this bit latches the current value.." newline bitfld.long 0x8 8. "OTC2_LATCH_CTRL,OTC2 Latch control" "?,1: Writing 1 on this bit latches the current value.." newline bitfld.long 0x8 4. "OTC1_LATCH_CTRL,OTC1 Latch control" "?,1: Writing 1 on this bit latches the current value.." newline bitfld.long 0x8 0. "OTC0_LATCH_CTRL,OTC0 Latch control" "?,1: Writing 1 on this bit latches the current value.." line.long 0xC "GLBL_LATCH_CLR,Global control to clear latch counter/timer current value register" bitfld.long 0xC 20. "EXNTP_LATCH_CLR,ExNTP Latch clear control" "?,1: Writing 1 on this field clears the latch on the.." newline bitfld.long 0xC 16. "NSC_LATCH_CLR,NSC Latch clear control" "?,1: Writing 1 on this field clears the latch on the.." newline bitfld.long 0xC 12. "OTC3_LATCH_CLR,OTC3 Latch Clear control" "?,1: Writing 1 on this bit clears the latched value.." newline bitfld.long 0xC 8. "OTC2_LATCH_CLR,OTC2 Latch Clear control" "?,1: Writing 1 on this bit clears the latched value.." newline bitfld.long 0xC 4. "OTC1_LATCH_CLR,OTC1 Latch Clear control" "?,1: Writing 1 on this bit clears the latched value.." newline bitfld.long 0xC 0. "OTC0_LATCH_CLR,OTC0 Latch Clear control" "?,1: Writing 1 on this field clears the latch on the.." line.long 0x10 "CLK_CTRL,Clock control register" bitfld.long 0x10 0. "CLK_SEL,Clock control register" "0: The software should program this bit to 0 if it..,1: The software should program this bit to 1 if it.." group.long 0xB00++0xB line.long 0x0 "OCU_COMPARE_START_LWORD,OCU lower word compare start register" hexmask.long 0x0 0.--31. 1. "OCU_COMPARE_START_LWORD_VAL,OCU Compare Start Lower word value" line.long 0x4 "OCU_COMPARE_START_HWORD,OCU higher word compare start register" hexmask.long 0x4 0.--31. 1. "OCU_COMPARE_START_HWORD_VAL,OCU Compare Start Higher word value" line.long 0x8 "OCU_COMPARE_DELTA_CFG,OCU compare delta configuration register" hexmask.long 0x8 0.--31. 1. "OCU_COMPARE_DELTA_VAL,OCU Compare Delta value" group.long 0xC00++0xB line.long 0x0 "ARC0_TRIG_STRETCH_CYCLE_CFG1,ARCm trigger pulse stretch cycle config 1 register" hexmask.long.byte 0x0 24.--31. 1. "ARC_C4_TRIG_STRETCH_CYCLE,ARCm Compare Register 4 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 16.--23. 1. "ARC_C3_TRIG_STRETCH_CYCLE,ARCm Compare Register 3 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 8.--15. 1. "ARC_C2_TRIG_STRETCH_CYCLE,ARCm Compare Register 2 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 0.--7. 1. "ARC_C1_TRIG_STRETCH_CYCLE,ARCm Compare Register 1 Trigger Pulse Stretch Cycle" line.long 0x4 "ARC0_TRIG_STRETCH_CYCLE_CFG2,ARCm trigger pulse stretch cycle config 2 register" hexmask.long.byte 0x4 0.--7. 1. "ARC_CEXPIRY_TRIG_STRETCH_CYCLE,ARCm Counter Expiry Trigger Pulse Stretch Cycle" line.long 0x8 "ARC0_TRIG_STRETCH_EN_CFG,ARCm trigger pulse stretch enable config register" bitfld.long 0x8 4. "ARC_CEXPIRY_TRIG_STRETCH_EN,ARCm Expiry event trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 3. "ARC_C4_TRIG_STRETCH_EN,ARCm C4 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 2. "ARC_C3_TRIG_STRETCH_EN,ARCm C3 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 1. "ARC_C2_TRIG_STRETCH_EN,ARCm C2 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 0. "ARC_C1_TRIG_STRETCH_EN,ARCm C1 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" group.long 0xC20++0xB line.long 0x0 "ARC1_TRIG_STRETCH_CYCLE_CFG1,ARCm trigger pulse stretch cycle config 1 register" hexmask.long.byte 0x0 24.--31. 1. "ARC_C4_TRIG_STRETCH_CYCLE,ARCm Compare Register 4 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 16.--23. 1. "ARC_C3_TRIG_STRETCH_CYCLE,ARCm Compare Register 3 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 8.--15. 1. "ARC_C2_TRIG_STRETCH_CYCLE,ARCm Compare Register 2 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 0.--7. 1. "ARC_C1_TRIG_STRETCH_CYCLE,ARCm Compare Register 1 Trigger Pulse Stretch Cycle" line.long 0x4 "ARC1_TRIG_STRETCH_CYCLE_CFG2,ARCm trigger pulse stretch cycle config 2 register" hexmask.long.byte 0x4 0.--7. 1. "ARC_CEXPIRY_TRIG_STRETCH_CYCLE,ARCm Counter Expiry Trigger Pulse Stretch Cycle" line.long 0x8 "ARC1_TRIG_STRETCH_EN_CFG,ARCm trigger pulse stretch enable config register" bitfld.long 0x8 4. "ARC_CEXPIRY_TRIG_STRETCH_EN,ARCm Expiry event trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 3. "ARC_C4_TRIG_STRETCH_EN,ARCm C4 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 2. "ARC_C3_TRIG_STRETCH_EN,ARCm C3 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 1. "ARC_C2_TRIG_STRETCH_EN,ARCm C2 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 0. "ARC_C1_TRIG_STRETCH_EN,ARCm C1 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" group.long 0xC40++0xB line.long 0x0 "ARC2_TRIG_STRETCH_CYCLE_CFG1,ARCm trigger pulse stretch cycle config 1 register" hexmask.long.byte 0x0 24.--31. 1. "ARC_C4_TRIG_STRETCH_CYCLE,ARCm Compare Register 4 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 16.--23. 1. "ARC_C3_TRIG_STRETCH_CYCLE,ARCm Compare Register 3 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 8.--15. 1. "ARC_C2_TRIG_STRETCH_CYCLE,ARCm Compare Register 2 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 0.--7. 1. "ARC_C1_TRIG_STRETCH_CYCLE,ARCm Compare Register 1 Trigger Pulse Stretch Cycle" line.long 0x4 "ARC2_TRIG_STRETCH_CYCLE_CFG2,ARCm trigger pulse stretch cycle config 2 register" hexmask.long.byte 0x4 0.--7. 1. "ARC_CEXPIRY_TRIG_STRETCH_CYCLE,ARCm Counter Expiry Trigger Pulse Stretch Cycle" line.long 0x8 "ARC2_TRIG_STRETCH_EN_CFG,ARCm trigger pulse stretch enable config register" bitfld.long 0x8 4. "ARC_CEXPIRY_TRIG_STRETCH_EN,ARCm Expiry event trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 3. "ARC_C4_TRIG_STRETCH_EN,ARCm C4 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 2. "ARC_C3_TRIG_STRETCH_EN,ARCm C3 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 1. "ARC_C2_TRIG_STRETCH_EN,ARCm C2 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 0. "ARC_C1_TRIG_STRETCH_EN,ARCm C1 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" group.long 0xC60++0xB line.long 0x0 "ARC3_TRIG_STRETCH_CYCLE_CFG1,ARCm trigger pulse stretch cycle config 1 register" hexmask.long.byte 0x0 24.--31. 1. "ARC_C4_TRIG_STRETCH_CYCLE,ARCm Compare Register 4 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 16.--23. 1. "ARC_C3_TRIG_STRETCH_CYCLE,ARCm Compare Register 3 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 8.--15. 1. "ARC_C2_TRIG_STRETCH_CYCLE,ARCm Compare Register 2 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 0.--7. 1. "ARC_C1_TRIG_STRETCH_CYCLE,ARCm Compare Register 1 Trigger Pulse Stretch Cycle" line.long 0x4 "ARC3_TRIG_STRETCH_CYCLE_CFG2,ARCm trigger pulse stretch cycle config 2 register" hexmask.long.byte 0x4 0.--7. 1. "ARC_CEXPIRY_TRIG_STRETCH_CYCLE,ARCm Counter Expiry Trigger Pulse Stretch Cycle" line.long 0x8 "ARC3_TRIG_STRETCH_EN_CFG,ARCm trigger pulse stretch enable config register" bitfld.long 0x8 4. "ARC_CEXPIRY_TRIG_STRETCH_EN,ARCm Expiry event trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 3. "ARC_C4_TRIG_STRETCH_EN,ARCm C4 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 2. "ARC_C3_TRIG_STRETCH_EN,ARCm C3 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 1. "ARC_C2_TRIG_STRETCH_EN,ARCm C2 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 0. "ARC_C1_TRIG_STRETCH_EN,ARCm C1 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" group.long 0xC80++0xB line.long 0x0 "ARC4_TRIG_STRETCH_CYCLE_CFG1,ARCm trigger pulse stretch cycle config 1 register" hexmask.long.byte 0x0 24.--31. 1. "ARC_C4_TRIG_STRETCH_CYCLE,ARCm Compare Register 4 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 16.--23. 1. "ARC_C3_TRIG_STRETCH_CYCLE,ARCm Compare Register 3 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 8.--15. 1. "ARC_C2_TRIG_STRETCH_CYCLE,ARCm Compare Register 2 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 0.--7. 1. "ARC_C1_TRIG_STRETCH_CYCLE,ARCm Compare Register 1 Trigger Pulse Stretch Cycle" line.long 0x4 "ARC4_TRIG_STRETCH_CYCLE_CFG2,ARCm trigger pulse stretch cycle config 2 register" hexmask.long.byte 0x4 0.--7. 1. "ARC_CEXPIRY_TRIG_STRETCH_CYCLE,ARCm Counter Expiry Trigger Pulse Stretch Cycle" line.long 0x8 "ARC4_TRIG_STRETCH_EN_CFG,ARCm trigger pulse stretch enable config register" bitfld.long 0x8 4. "ARC_CEXPIRY_TRIG_STRETCH_EN,ARCm Expiry event trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 3. "ARC_C4_TRIG_STRETCH_EN,ARCm C4 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 2. "ARC_C3_TRIG_STRETCH_EN,ARCm C3 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 1. "ARC_C2_TRIG_STRETCH_EN,ARCm C2 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 0. "ARC_C1_TRIG_STRETCH_EN,ARCm C1 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" group.long 0xCA0++0xB line.long 0x0 "ARC5_TRIG_STRETCH_CYCLE_CFG1,ARCm trigger pulse stretch cycle config 1 register" hexmask.long.byte 0x0 24.--31. 1. "ARC_C4_TRIG_STRETCH_CYCLE,ARCm Compare Register 4 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 16.--23. 1. "ARC_C3_TRIG_STRETCH_CYCLE,ARCm Compare Register 3 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 8.--15. 1. "ARC_C2_TRIG_STRETCH_CYCLE,ARCm Compare Register 2 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 0.--7. 1. "ARC_C1_TRIG_STRETCH_CYCLE,ARCm Compare Register 1 Trigger Pulse Stretch Cycle" line.long 0x4 "ARC5_TRIG_STRETCH_CYCLE_CFG2,ARCm trigger pulse stretch cycle config 2 register" hexmask.long.byte 0x4 0.--7. 1. "ARC_CEXPIRY_TRIG_STRETCH_CYCLE,ARCm Counter Expiry Trigger Pulse Stretch Cycle" line.long 0x8 "ARC5_TRIG_STRETCH_EN_CFG,ARCm trigger pulse stretch enable config register" bitfld.long 0x8 4. "ARC_CEXPIRY_TRIG_STRETCH_EN,ARCm Expiry event trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 3. "ARC_C4_TRIG_STRETCH_EN,ARCm C4 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 2. "ARC_C3_TRIG_STRETCH_EN,ARCm C3 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 1. "ARC_C2_TRIG_STRETCH_EN,ARCm C2 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 0. "ARC_C1_TRIG_STRETCH_EN,ARCm C1 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" group.long 0xCC0++0xB line.long 0x0 "ARC6_TRIG_STRETCH_CYCLE_CFG1,ARCm trigger pulse stretch cycle config 1 register" hexmask.long.byte 0x0 24.--31. 1. "ARC_C4_TRIG_STRETCH_CYCLE,ARCm Compare Register 4 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 16.--23. 1. "ARC_C3_TRIG_STRETCH_CYCLE,ARCm Compare Register 3 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 8.--15. 1. "ARC_C2_TRIG_STRETCH_CYCLE,ARCm Compare Register 2 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 0.--7. 1. "ARC_C1_TRIG_STRETCH_CYCLE,ARCm Compare Register 1 Trigger Pulse Stretch Cycle" line.long 0x4 "ARC6_TRIG_STRETCH_CYCLE_CFG2,ARCm trigger pulse stretch cycle config 2 register" hexmask.long.byte 0x4 0.--7. 1. "ARC_CEXPIRY_TRIG_STRETCH_CYCLE,ARCm Counter Expiry Trigger Pulse Stretch Cycle" line.long 0x8 "ARC6_TRIG_STRETCH_EN_CFG,ARCm trigger pulse stretch enable config register" bitfld.long 0x8 4. "ARC_CEXPIRY_TRIG_STRETCH_EN,ARCm Expiry event trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 3. "ARC_C4_TRIG_STRETCH_EN,ARCm C4 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 2. "ARC_C3_TRIG_STRETCH_EN,ARCm C3 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 1. "ARC_C2_TRIG_STRETCH_EN,ARCm C2 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 0. "ARC_C1_TRIG_STRETCH_EN,ARCm C1 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" group.long 0xCE0++0xB line.long 0x0 "ARC7_TRIG_STRETCH_CYCLE_CFG1,ARCm trigger pulse stretch cycle config 1 register" hexmask.long.byte 0x0 24.--31. 1. "ARC_C4_TRIG_STRETCH_CYCLE,ARCm Compare Register 4 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 16.--23. 1. "ARC_C3_TRIG_STRETCH_CYCLE,ARCm Compare Register 3 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 8.--15. 1. "ARC_C2_TRIG_STRETCH_CYCLE,ARCm Compare Register 2 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 0.--7. 1. "ARC_C1_TRIG_STRETCH_CYCLE,ARCm Compare Register 1 Trigger Pulse Stretch Cycle" line.long 0x4 "ARC7_TRIG_STRETCH_CYCLE_CFG2,ARCm trigger pulse stretch cycle config 2 register" hexmask.long.byte 0x4 0.--7. 1. "ARC_CEXPIRY_TRIG_STRETCH_CYCLE,ARCm Counter Expiry Trigger Pulse Stretch Cycle" line.long 0x8 "ARC7_TRIG_STRETCH_EN_CFG,ARCm trigger pulse stretch enable config register" bitfld.long 0x8 4. "ARC_CEXPIRY_TRIG_STRETCH_EN,ARCm Expiry event trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 3. "ARC_C4_TRIG_STRETCH_EN,ARCm C4 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 2. "ARC_C3_TRIG_STRETCH_EN,ARCm C3 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 1. "ARC_C2_TRIG_STRETCH_EN,ARCm C2 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 0. "ARC_C1_TRIG_STRETCH_EN,ARCm C1 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" group.long 0xD00++0xB line.long 0x0 "ARC8_TRIG_STRETCH_CYCLE_CFG1,ARCm trigger pulse stretch cycle config 1 register" hexmask.long.byte 0x0 24.--31. 1. "ARC_C4_TRIG_STRETCH_CYCLE,ARCm Compare Register 4 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 16.--23. 1. "ARC_C3_TRIG_STRETCH_CYCLE,ARCm Compare Register 3 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 8.--15. 1. "ARC_C2_TRIG_STRETCH_CYCLE,ARCm Compare Register 2 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 0.--7. 1. "ARC_C1_TRIG_STRETCH_CYCLE,ARCm Compare Register 1 Trigger Pulse Stretch Cycle" line.long 0x4 "ARC8_TRIG_STRETCH_CYCLE_CFG2,ARCm trigger pulse stretch cycle config 2 register" hexmask.long.byte 0x4 0.--7. 1. "ARC_CEXPIRY_TRIG_STRETCH_CYCLE,ARCm Counter Expiry Trigger Pulse Stretch Cycle" line.long 0x8 "ARC8_TRIG_STRETCH_EN_CFG,ARCm trigger pulse stretch enable config register" bitfld.long 0x8 4. "ARC_CEXPIRY_TRIG_STRETCH_EN,ARCm Expiry event trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 3. "ARC_C4_TRIG_STRETCH_EN,ARCm C4 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 2. "ARC_C3_TRIG_STRETCH_EN,ARCm C3 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 1. "ARC_C2_TRIG_STRETCH_EN,ARCm C2 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 0. "ARC_C1_TRIG_STRETCH_EN,ARCm C1 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" group.long 0xD20++0xB line.long 0x0 "ARC9_TRIG_STRETCH_CYCLE_CFG1,ARCm trigger pulse stretch cycle config 1 register" hexmask.long.byte 0x0 24.--31. 1. "ARC_C4_TRIG_STRETCH_CYCLE,ARCm Compare Register 4 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 16.--23. 1. "ARC_C3_TRIG_STRETCH_CYCLE,ARCm Compare Register 3 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 8.--15. 1. "ARC_C2_TRIG_STRETCH_CYCLE,ARCm Compare Register 2 Trigger Pulse Stretch Cycle" newline hexmask.long.byte 0x0 0.--7. 1. "ARC_C1_TRIG_STRETCH_CYCLE,ARCm Compare Register 1 Trigger Pulse Stretch Cycle" line.long 0x4 "ARC9_TRIG_STRETCH_CYCLE_CFG2,ARCm trigger pulse stretch cycle config 2 register" hexmask.long.byte 0x4 0.--7. 1. "ARC_CEXPIRY_TRIG_STRETCH_CYCLE,ARCm Counter Expiry Trigger Pulse Stretch Cycle" line.long 0x8 "ARC9_TRIG_STRETCH_EN_CFG,ARCm trigger pulse stretch enable config register" bitfld.long 0x8 4. "ARC_CEXPIRY_TRIG_STRETCH_EN,ARCm Expiry event trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 3. "ARC_C4_TRIG_STRETCH_EN,ARCm C4 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 2. "ARC_C3_TRIG_STRETCH_EN,ARCm C3 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 1. "ARC_C2_TRIG_STRETCH_EN,ARCm C2 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" newline bitfld.long 0x8 0. "ARC_C1_TRIG_STRETCH_EN,ARCm C1 trigger pulse Stretch Enable" "0: Trigger pulse is not stretched,1: Trigger pulse is stretched" tree.end tree "GTM (Generic Timer Module)" base ad:0x0 tree "GTM_1_GTM_CLS0" base ad:0x70B00000 group.long 0x0++0x33 line.long 0x0 "GTM_REV," hexmask.long.byte 0x0 28.--31. 1. "VER_MAJOR,Major version number" hexmask.long.byte 0x0 24.--27. 1. "VER_MINOR,Minor version number" hexmask.long.byte 0x0 20.--23. 1. "DEVICE_CODE,Device encoding digit 0." newline hexmask.long.byte 0x0 16.--19. 1. "VENDOR_CODE,Device encoding digit 1." hexmask.long.byte 0x0 4.--11. 1. "REL_BASE,Release step" hexmask.long.byte 0x0 0.--3. 1. "REL_ITER,Delivery number" line.long 0x4 "GTM_RST," bitfld.long 0x4 27. "BRIDGE_MODE_WRDIS,BRIDGE_MODE write disable." "0,1" bitfld.long 0x4 0. "RST,GTM-IP Reset." "0,1" line.long 0x8 "GTM_CTRL," hexmask.long.byte 0x8 12.--15. 1. "AEIM_CLUSTER,AEIM cluster number" hexmask.long.byte 0x8 4.--11. 1. "TO_VAL,AEI timeout value." bitfld.long 0x8 1.--2. "TO_MODE,AEI timeout mode." "0,1,2,3" newline bitfld.long 0x8 0. "RF_PROT,RST and FORCINT protection." "0,1" line.long 0xC "GTM_CFG," bitfld.long 0xC 0. "SRC_IN_MUX,GTM_TIM[i]_AUX_IN input source selection" "0,1" line.long 0x10 "GTM_AEI_ADDR_XPT," bitfld.long 0x10 24. "TO_W1R0,AEI timeout Read/Write flag." "0,1" hexmask.long.tbyte 0x10 0.--20. 1. "TO_ADDR,AEI timeout address." line.long 0x14 "GTM_AEI_STA_XPT," bitfld.long 0x14 24. "W1R0,AEI exception Read/Write flag." "0,1" hexmask.long.tbyte 0x14 0.--20. 1. "ADDR,AEI exception address." line.long 0x18 "GTM_IRQ_NOTIFY," bitfld.long 0x18 28.--29. "CLK_EN_EXP_STATE,Expected clock enable state." "0,1,2,3" bitfld.long 0x18 24.--25. "CLK_EN_ERR_STATE,Erroneous clock enable state." "0,1,2,3" bitfld.long 0x18 8. "CLK_PER_ERR,Clock period error interrupt." "0,1" newline bitfld.long 0x18 7. "CLK_EN_ERR,Clock enable error interrupt." "0,1" bitfld.long 0x18 6. "AEIM_USP_BE,AEI master port unsupported byte enable interrupt." "0,1" bitfld.long 0x18 5. "AEIM_IM_ADDR,AEI master port illegal Module address interrupt." "0,1" newline bitfld.long 0x18 4. "AEIM_USP_ADDR,AEI master port unsupported address interrupt." "0,1" bitfld.long 0x18 3. "AEI_USP_BE,AEI unsupported byte enable interrupt." "0,1" bitfld.long 0x18 2. "AEI_IM_ADDR,AEI illegal Module address interrupt." "0,1" newline bitfld.long 0x18 1. "AEI_USP_ADDR,AEI unsupported address interrupt." "0,1" bitfld.long 0x18 0. "AEI_TO_XPT,AEI timeout exception occurred." "0,1" line.long 0x1C "GTM_IRQ_EN," bitfld.long 0x1C 8. "CLK_PER_ERR_IRQ_EN,CLK_PER_ERR_IRQ interrupt enable." "0,1" bitfld.long 0x1C 7. "CLK_EN_ERR_IRQ_EN,CLK_EN_ERR_IRQ interrupt enable." "0,1" bitfld.long 0x1C 6. "AEIM_USP_BE_IRQ_EN,AEIM_USP_BE_IRQ interrupt enable." "0,1" newline bitfld.long 0x1C 5. "AEIM_IM_ADDR_IRQ_EN,AEIM_IM_ADDR_IRQ interrupt enable." "0,1" bitfld.long 0x1C 4. "AEIM_USP_ADDR_IRQ_EN,AEI_MUSP_ADDR_IRQ interrupt enable." "0,1" bitfld.long 0x1C 3. "AEI_USP_BE_IRQ_EN,AEI_USP_BE_IRQ interrupt enable." "0,1" newline bitfld.long 0x1C 2. "AEI_IM_ADDR_IRQ_EN,AEI_IM_ADDR_IRQ interrupt enable." "0,1" bitfld.long 0x1C 1. "AEI_USP_ADDR_IRQ_EN,AEI_USP_ADDR_IRQ interrupt enable." "0,1" bitfld.long 0x1C 0. "AEI_TO_XPT_IRQ_EN,AEI_TO_XPT_IRQ interrupt enable." "0,1" line.long 0x20 "GTM_EIRQ_EN," bitfld.long 0x20 8. "CLK_PER_ERR_EIRQ_EN,CLK_PER_ERR_EIRQ interrupt enable." "0,1" bitfld.long 0x20 7. "CLK_EN_ERR_EIRQ_EN,CLK_EN_ERR_EIRQ interrupt enable." "0,1" bitfld.long 0x20 6. "AEIM_USP_BE_EIRQ_EN,AEIM_USP_BE_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x20 5. "AEIM_IM_ADDR_EIRQ_EN,AEIM_IM_ADDR_EIRQ error interrupt enable." "0,1" bitfld.long 0x20 4. "AEIM_USP_ADDR_EIRQ_EN,AEIM_USP_ADDR_EIRQ error interrupt enable." "0,1" bitfld.long 0x20 3. "AEI_USP_BE_EIRQ_EN,AEI_USP_BE_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x20 2. "AEI_IM_ADDR_EIRQ_EN,AEI_IM_ADDR_EIRQ error interrupt enable." "0,1" bitfld.long 0x20 1. "AEI_USP_ADDR_EIRQ_EN,AEI_USP_ADDR_EIRQ error interrupt enable." "0,1" bitfld.long 0x20 0. "AEI_TO_XPT_EIRQ_EN,AEI_TO_XPT_EIRQ error interrupt enable." "0,1" line.long 0x24 "GTM_IRQ_FORCINT," bitfld.long 0x24 8. "TRG_CLK_PER_ERR,Trigger CLK_PER_ERR_IRQ interrupt by software." "0,1" bitfld.long 0x24 7. "TRG_CLK_EN_ERR,Trigger CLK_EN_ERR_IRQ interrupt by software." "0,1" bitfld.long 0x24 6. "TRG_AEIM_USP_BE,Trigger AEIM_USP_BE_IRQ interrupt by software." "0,1" newline bitfld.long 0x24 5. "TRG_AEIM_IM_ADDR,Trigger AEIM_IM_ADDR_IRQ interrupt by software." "0,1" bitfld.long 0x24 4. "TRG_AEIM_USP_ADDR,Trigger AEIM_USP_ADDR_IRQ interrupt by software." "0,1" bitfld.long 0x24 3. "TRG_AEI_USP_BE,Trigger AEI_USP_BE_IRQ interrupt by software." "0,1" newline bitfld.long 0x24 2. "TRG_AEI_IM_ADDR,Trigger AEI_IM_ADDR_IRQ interrupt by software." "0,1" bitfld.long 0x24 1. "TRG_AEI_USP_ADDR,Trigger AEI_USP_ADDR_IRQ interrupt by software." "0,1" bitfld.long 0x24 0. "TRG_AEI_TO_XPT,Trigger AEI_TO_XPT_IRQ interrupt by software." "0,1" line.long 0x28 "GTM_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,Interrupt strategy mode selection for the AEI timeout and address monitoring interrupts." "0,1,2,3" line.long 0x2C "GTM_CLS_CLK_CFG," bitfld.long 0x2C 22.--23. "CLS11_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" bitfld.long 0x2C 20.--21. "CLS10_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" bitfld.long 0x2C 18.--19. "CLS9_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" newline bitfld.long 0x2C 16.--17. "CLS8_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" bitfld.long 0x2C 14.--15. "CLS7_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" bitfld.long 0x2C 12.--13. "CLS6_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" newline bitfld.long 0x2C 10.--11. "CLS5_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" bitfld.long 0x2C 8.--9. "CLS4_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" bitfld.long 0x2C 6.--7. "CLS3_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" newline bitfld.long 0x2C 4.--5. "CLS2_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" bitfld.long 0x2C 2.--3. "CLS1_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" bitfld.long 0x2C 0.--1. "CLS0_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" line.long 0x30 "GTM_ARU_COM_DIS," bitfld.long 0x30 1. "CLS1_DIS,Disable cluster [j] ARU communication" "0,1" bitfld.long 0x30 0. "CLS0_DIS,Disable cluster [j] ARU communication" "0,1" group.long 0x40++0xB line.long 0x0 "BRIDGE_MODE," hexmask.long.byte 0x0 24.--31. 1. "BUFF_DPT,Buffer depth of AEI bridge." bitfld.long 0x0 16. "BRG_RST,Bridge software reset." "0,1" bitfld.long 0x0 12. "SYNC_INPUT_REG,additional pipelined stage in synchronous bridge mode" "0,1" newline bitfld.long 0x0 9. "BUFF_OVL,Buffer overflow register." "0,1" bitfld.long 0x0 8. "MODE_UP_PGR,Mode update in progress." "0,1" bitfld.long 0x0 2. "BYPASS_SYNC,Bypass synchronizer flipflops." "0,1" newline bitfld.long 0x0 1. "MSK_WR_RSP,Mask write response." "0,1" bitfld.long 0x0 0. "BRG_MODE,Defines the operation mode for the AEI bridge." "0,1" line.long 0x4 "BRIDGE_PTR1," hexmask.long.byte 0x4 26.--31. 1. "RSP_TRAN_RDY,Response transactions ready." hexmask.long.byte 0x4 20.--25. 1. "FBC,Free buffer count." hexmask.long.byte 0x4 15.--19. 1. "ABT_TRAN_PGR,Aborted transaction in progress pointer." newline hexmask.long.byte 0x4 10.--14. 1. "TRAN_IN_PGR,Transaction in progress pointer (acquire)" hexmask.long.byte 0x4 5.--9. 1. "FIRST_RSP_PTR,First response pointer." hexmask.long.byte 0x4 0.--4. 1. "NEW_TRAN_PTR,New transaction pointer." line.long 0x8 "BRIDGE_PTR2," hexmask.long.byte 0x8 0.--4. 1. "TRAN_IN_PGR2,Transaction in progress pointer (aquire2)" group.long 0x80++0x4F line.long 0x0 "CMU_CLK_EN," bitfld.long 0x0 22.--23. "EN_FXCLK,Enable all CMU_FXCLK see bits 1:0" "?,1: 0,?,?" bitfld.long 0x0 20.--21. "EN_ECLK2,Enable ECLK z generation sub-unit see bits 1:0" "?,1: 0,?,?" bitfld.long 0x0 18.--19. "EN_ECLK1,Enable ECLK z generation sub-unit see bits 1:0" "?,1: 0,?,?" newline bitfld.long 0x0 16.--17. "EN_ECLK0,Enable ECLK z generation sub-unit see bits 1:0" "?,1: 0,?,?" bitfld.long 0x0 14.--15. "EN_CLK7,Enable clock source x" "0,1,2,3" bitfld.long 0x0 12.--13. "EN_CLK6,Enable clock source x" "0,1,2,3" newline bitfld.long 0x0 10.--11. "EN_CLK5,Enable clock source x" "0,1,2,3" bitfld.long 0x0 8.--9. "EN_CLK4,Enable clock source x" "0,1,2,3" bitfld.long 0x0 6.--7. "EN_CLK3,Enable clock source x" "0,1,2,3" newline bitfld.long 0x0 4.--5. "EN_CLK2,Enable clock source x" "0,1,2,3" bitfld.long 0x0 2.--3. "EN_CLK1,Enable clock source x" "0,1,2,3" bitfld.long 0x0 0.--1. "EN_CLK0,Enable clock source x" "0,1,2,3" line.long 0x4 "CMU_GCLK_NUM," hexmask.long.tbyte 0x4 0.--23. 1. "GCLK_NUM,Numerator for global clock divider. Defines numerator of the fractional divider." line.long 0x8 "CMU_GCLK_DEN," hexmask.long.tbyte 0x8 0.--23. 1. "GCLK_DEN,Denominator for global clock divider. Defines denominator of the fractional divider" line.long 0xC "CMU_CLK_0_CTRL," hexmask.long.tbyte 0xC 0.--23. 1. "CLK_CNT,Clock count. Defines count value for the clock divider." line.long 0x10 "CMU_CLK_1_CTRL," hexmask.long.tbyte 0x10 0.--23. 1. "CLK_CNT,Clock count. Defines count value for the clock divider." line.long 0x14 "CMU_CLK_2_CTRL," hexmask.long.tbyte 0x14 0.--23. 1. "CLK_CNT,Clock count. Defines count value for the clock divider." line.long 0x18 "CMU_CLK_3_CTRL," hexmask.long.tbyte 0x18 0.--23. 1. "CLK_CNT,Clock count. Defines count value for the clock divider." line.long 0x1C "CMU_CLK_4_CTRL," hexmask.long.tbyte 0x1C 0.--23. 1. "CLK_CNT,Clock count. Defines count value for the clock divider." line.long 0x20 "CMU_CLK_5_CTRL," hexmask.long.tbyte 0x20 0.--23. 1. "CLK_CNT,Clock count. Defines count value for the clock divider." line.long 0x24 "CMU_CLK_6_CTRL," bitfld.long 0x24 24.--25. "CLK_SEL,Clock source selection." "0,1,2,3" hexmask.long.tbyte 0x24 0.--23. 1. "CLK_CNT,Clock count. Define count value for the clock divider of clock source CMU_CLK6." line.long 0x28 "CMU_CLK_7_CTRL," bitfld.long 0x28 24.--25. "CLK_SEL,Clock source selection." "0,1,2,3" hexmask.long.tbyte 0x28 0.--23. 1. "CLK_CNT,Clock count. Define count value for the clock divider of clock source CMU_CLK7." line.long 0x2C "CMU_ECLK_0_NUM," hexmask.long.tbyte 0x2C 0.--23. 1. "ECLK_NUM,Numerator for external clock divider. Defines numerator of the fractional divider." line.long 0x30 "CMU_ECLK_0_DEN," hexmask.long.tbyte 0x30 0.--23. 1. "ECLK_DEN,Denominator for external clock divider. Defines denominator of the fractional divider" line.long 0x34 "CMU_ECLK_1_NUM," hexmask.long.tbyte 0x34 0.--23. 1. "ECLK_NUM,Numerator for external clock divider. Defines numerator of the fractional divider." line.long 0x38 "CMU_ECLK_1_DEN," hexmask.long.tbyte 0x38 0.--23. 1. "ECLK_DEN,Denominator for external clock divider. Defines denominator of the fractional divider" line.long 0x3C "CMU_ECLK_2_NUM," hexmask.long.tbyte 0x3C 0.--23. 1. "ECLK_NUM,Numerator for external clock divider. Defines numerator of the fractional divider." line.long 0x40 "CMU_ECLK_2_DEN," hexmask.long.tbyte 0x40 0.--23. 1. "ECLK_DEN,Denominator for external clock divider. Defines denominator of the fractional divider" line.long 0x44 "CMU_FXCLK_CTRL," hexmask.long.byte 0x44 0.--3. 1. "FXCLK_SEL,Input clock selection for EN_FXCLK line." line.long 0x48 "CMU_GLB_CTRL," bitfld.long 0x48 0. "ARU_ADDR_RSTGLB,Reset ARU caddr counter and ARU dynamic route counter" "0,1" line.long 0x4C "CMU_CLK_CTRL," bitfld.long 0x4C 8. "CLK8_EXT_DIVIDER,Clock source selection for CMU_CLK8." "0,1" bitfld.long 0x4C 7. "CLK7_EXT_DIVIDER,Clock source selection for CMU_CLK_[x]_CTRL." "0,1" bitfld.long 0x4C 6. "CLK6_EXT_DIVIDER,Clock source selection for CMU_CLK_[x]_CTRL." "0,1" newline bitfld.long 0x4C 5. "CLK5_EXT_DIVIDER,Clock source selection for CMU_CLK_[x]_CTRL." "0,1" bitfld.long 0x4C 4. "CLK4_EXT_DIVIDER,Clock source selection for CMU_CLK_[x]_CTRL." "0,1" bitfld.long 0x4C 3. "CLK3_EXT_DIVIDER,Clock source selection for CMU_CLK_[x]_CTRL." "0,1" newline bitfld.long 0x4C 2. "CLK2_EXT_DIVIDER,Clock source selection for CMU_CLK_[x]_CTRL." "0,1" bitfld.long 0x4C 1. "CLK1_EXT_DIVIDER,Clock source selection for CMU_CLK_[x]_CTRL." "0,1" bitfld.long 0x4C 0. "CLK0_EXT_DIVIDER,Clock source selection for CMU_CLK_[x]_CTRL." "0,1" group.long 0x100++0x1B line.long 0x0 "TBU_CHEN," bitfld.long 0x0 6.--7. "ENDIS_CH3,TBU channel y enable/disable control." "0,1,2,3" bitfld.long 0x0 4.--5. "ENDIS_CH2,TBU channel y enable/disable control." "0,1,2,3" bitfld.long 0x0 2.--3. "ENDIS_CH1,TBU channel y enable/disable control." "0,1,2,3" newline bitfld.long 0x0 0.--1. "ENDIS_CH0,TBU channel y enable/disable control." "0,1,2,3" line.long 0x4 "TBU_CH0_CTRL," bitfld.long 0x4 1.--3. "CH_CLK_SRC,Clock source for channel x (x:0...2) time base counter" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "LOW_RES,TBU_CH0_BASE register resolution." "0,1" line.long 0x8 "TBU_CH0_BASE," hexmask.long 0x8 0.--26. 1. "BASE,Time base value for channel 0." line.long 0xC "TBU_CH1_CTRL," bitfld.long 0xC 1.--3. "CH_CLK_SRC,Clock source for channel 1 time base counter" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0. "CH_MODE,Channel mode" "0,1" line.long 0x10 "TBU_CH1_BASE," hexmask.long.tbyte 0x10 0.--23. 1. "BASE,Time base value for channel x (x: 1 2)" line.long 0x14 "TBU_CH2_CTRL," bitfld.long 0x14 1.--3. "CH_CLK_SRC,Clock source for channel 2 time base counter" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0. "CH_MODE,Channel mode" "0,1" line.long 0x18 "TBU_CH2_BASE," hexmask.long.tbyte 0x18 0.--23. 1. "BASE,Time base value for channel x (x: 1 2)" group.long 0x180++0x37 line.long 0x0 "ARU_ACCESS," bitfld.long 0x0 13. "WREQ,Initiate write request" "0,1" bitfld.long 0x0 12. "RREQ,Initiate read request" "0,1" hexmask.long.word 0x0 0.--8. 1. "ADDR,ARU address" line.long 0x4 "ARU_DATA_H," hexmask.long 0x4 0.--28. 1. "DATA,Upper ARU data word" line.long 0x8 "ARU_DATA_L," hexmask.long 0x8 0.--28. 1. "DATA,Lower ARU data word" line.long 0xC "ARU_DBG_ACCESS0," hexmask.long.word 0xC 0.--8. 1. "ADDR,ARU debugging address" line.long 0x10 "ARU_DBG_DATA0_H," hexmask.long 0x10 0.--28. 1. "DATA,Upper debug data word" line.long 0x14 "ARU_DBG_DATA0_L," hexmask.long 0x14 0.--28. 1. "DATA,Lower debug data word" line.long 0x18 "ARU_DBG_ACCESS1," hexmask.long.word 0x18 0.--8. 1. "ADDR,ARU debugging address" line.long 0x1C "ARU_DBG_DATA1_H," hexmask.long 0x1C 0.--28. 1. "DATA,Upper debug data word" line.long 0x20 "ARU_DBG_DATA1_L," hexmask.long 0x20 0.--28. 1. "DATA,Lower debug data word" line.long 0x24 "ARU_IRQ_NOTIFY," bitfld.long 0x24 2. "ACC_ACK,AEI to ARU access finished on read access data are valid" "0,1" bitfld.long 0x24 1. "NEW_DATA1,Data was transferred for addr ARU_DBG_ACCESS1" "0,1" bitfld.long 0x24 0. "NEW_DATA0,Data was transferred for addr ARU_DBG_ACCESS0" "0,1" line.long 0x28 "ARU_IRQ_EN," bitfld.long 0x28 2. "ACC_ACK_IRQ_EN,ACC_ACK_IRQ interrupt enable" "0,1" bitfld.long 0x28 1. "NEW_DATA1_IRQ_EN,ARU_NEW_DATA1_IRQ interrupt enable" "0,1" bitfld.long 0x28 0. "NEW_DATA0_IRQ_EN,ARU_NEW_DATA0_IRQ interrupt enable" "0,1" line.long 0x2C "ARU_IRQ_FORCINT," bitfld.long 0x2C 2. "TRG_ACC_ACK,Trigger ACC_ACK interrupt" "0,1" bitfld.long 0x2C 1. "TRG_NEW_DATA1,Trigger new data k interrupt" "0,1" bitfld.long 0x2C 0. "TRG_NEW_DATA0,Trigger new data k interrupt" "0,1" line.long 0x30 "ARU_IRQ_MODE," bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "ARU_CADDR_END," hexmask.long.byte 0x34 0.--6. 1. "CADDR_END,Set end value of ARU caddr counter" group.long 0x1BC++0x33 line.long 0x0 "ARU_CTRL," bitfld.long 0x0 4. "ARU_DYN_RING_MODE,Enable dynamic routing ring mode" "0,1" bitfld.long 0x0 2.--3. "ARU_1_DYN_EN,Enable dynamic routing for ARU-k" "0,1,2,3" bitfld.long 0x0 0.--1. "ARU_0_DYN_EN,Enable dynamic routing for ARU-k" "0,1,2,3" line.long 0x4 "ARU_0_DYN_CTRL," bitfld.long 0x4 1. "DYN_ROUTE_SWAP,Enable swapping DYN_ROUTE_SR with DYN_ROUTE register" "0,1" bitfld.long 0x4 0. "DYN_ARU_UPDATE_EN,Enable reload of DYN_ROUTE register from ARU itself" "0,1" line.long 0x8 "ARU_1_DYN_CTRL," bitfld.long 0x8 1. "DYN_ROUTE_SWAP,Enable swapping DYN_ROUTE_SR with DYN_ROUTE register" "0,1" bitfld.long 0x8 0. "DYN_ARU_UPDATE_EN,Enable reload of DYN_ROUTE register from ARU itself" "0,1" line.long 0xC "ARU_0_DYN_ROUTE_LOW," hexmask.long.byte 0xC 16.--23. 1. "DYN_READ_ID2,ARU read ID 2" hexmask.long.byte 0xC 8.--15. 1. "DYN_READ_ID1,ARU read ID 1" hexmask.long.byte 0xC 0.--7. 1. "DYN_READ_ID0,ARU read ID 0" line.long 0x10 "ARU_1_DYN_ROUTE_LOW," hexmask.long.byte 0x10 16.--23. 1. "DYN_READ_ID2,ARU read ID 2" hexmask.long.byte 0x10 8.--15. 1. "DYN_READ_ID1,ARU read ID 1" hexmask.long.byte 0x10 0.--7. 1. "DYN_READ_ID0,ARU read ID 0" line.long 0x14 "ARU_0_DYN_ROUTE_HIGH," hexmask.long.byte 0x14 24.--27. 1. "DYN_CLK_WAIT,Number of clk cycles for dynamic routing" hexmask.long.byte 0x14 16.--23. 1. "DYN_READ_ID5,ARU read ID 5" hexmask.long.byte 0x14 8.--15. 1. "DYN_READ_ID4,ARU read ID 4" newline hexmask.long.byte 0x14 0.--7. 1. "DYN_READ_ID3,ARU read ID 3" line.long 0x18 "ARU_1_DYN_ROUTE_HIGH," hexmask.long.byte 0x18 24.--27. 1. "DYN_CLK_WAIT,Number of clk cycles for dynamic routing" hexmask.long.byte 0x18 16.--23. 1. "DYN_READ_ID5,ARU read ID 5" hexmask.long.byte 0x18 8.--15. 1. "DYN_READ_ID4,ARU read ID 4" newline hexmask.long.byte 0x18 0.--7. 1. "DYN_READ_ID3,ARU read ID 3" line.long 0x1C "ARU_0_DYN_ROUTE_SR_LOW," hexmask.long.byte 0x1C 16.--23. 1. "DYN_READ_ID8,ARU read ID 8" hexmask.long.byte 0x1C 8.--15. 1. "DYN_READ_ID7,ARU read ID 7" hexmask.long.byte 0x1C 0.--7. 1. "DYN_READ_ID6,ARU read ID 6" line.long 0x20 "ARU_1_DYN_ROUTE_SR_LOW," hexmask.long.byte 0x20 16.--23. 1. "DYN_READ_ID8,ARU read ID 8" hexmask.long.byte 0x20 8.--15. 1. "DYN_READ_ID7,ARU read ID 7" hexmask.long.byte 0x20 0.--7. 1. "DYN_READ_ID6,ARU read ID 6" line.long 0x24 "ARU_0_DYN_ROUTE_SR_HIGH," bitfld.long 0x24 28. "DYN_UPDATE_EN,Update enable from shadow register" "0,1" hexmask.long.byte 0x24 24.--27. 1. "DYN_CLK_WAIT,Number of clk cycles for dynamic routing" hexmask.long.byte 0x24 16.--23. 1. "DYN_READ_ID11,ARU read ID 11" newline hexmask.long.byte 0x24 8.--15. 1. "DYN_READ_ID10,ARU read ID 10" hexmask.long.byte 0x24 0.--7. 1. "DYN_READ_ID9,ARU read ID 9" line.long 0x28 "ARU_1_DYN_ROUTE_SR_HIGH," bitfld.long 0x28 28. "DYN_UPDATE_EN,Update enable from shadow register" "0,1" hexmask.long.byte 0x28 24.--27. 1. "DYN_CLK_WAIT,Number of clk cycles for dynamic routing" hexmask.long.byte 0x28 16.--23. 1. "DYN_READ_ID11,ARU read ID 11" newline hexmask.long.byte 0x28 8.--15. 1. "DYN_READ_ID10,ARU read ID 10" hexmask.long.byte 0x28 0.--7. 1. "DYN_READ_ID9,ARU read ID 9" line.long 0x2C "ARU_0_DYN_RDADDR," hexmask.long.word 0x2C 0.--8. 1. "DYN_ARU_RDADDR,ARU read address ID to reload the DYN_ROUTE register" line.long 0x30 "ARU_1_DYN_RDADDR," hexmask.long.word 0x30 0.--8. 1. "DYN_ARU_RDADDR,ARU read address ID to reload the DYN_ROUTE register" group.long 0x1FC++0x7B line.long 0x0 "ARU_CADDR," hexmask.long.byte 0x0 16.--22. 1. "CADDR_1,Value of ARU-1 caddr counter" hexmask.long.byte 0x0 0.--6. 1. "CADDR_0,Value of ARU-0 caddr counter" line.long 0x4 "BRC_SRC_0_ADDR," bitfld.long 0x4 12. "BRC_MODE,BRC Operation mode select." "0,1" hexmask.long.word 0x4 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x8 "BRC_SRC_0_DEST," bitfld.long 0x8 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" bitfld.long 0x8 21. "EN_DEST21,Enable BRC destination address z" "0,1" bitfld.long 0x8 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 19. "EN_DEST19,Enable BRC destination address z" "0,1" bitfld.long 0x8 18. "EN_DEST18,Enable BRC destination address z" "0,1" bitfld.long 0x8 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 16. "EN_DEST16,Enable BRC destination address z" "0,1" bitfld.long 0x8 15. "EN_DEST15,Enable BRC destination address z" "0,1" bitfld.long 0x8 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 13. "EN_DEST13,Enable BRC destination address z" "0,1" bitfld.long 0x8 12. "EN_DEST12,Enable BRC destination address z" "0,1" bitfld.long 0x8 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 10. "EN_DEST10,Enable BRC destination address z" "0,1" bitfld.long 0x8 9. "EN_DEST9,Enable BRC destination address z" "0,1" bitfld.long 0x8 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 7. "EN_DEST7,Enable BRC destination address z" "0,1" bitfld.long 0x8 6. "EN_DEST6,Enable BRC destination address z" "0,1" bitfld.long 0x8 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 4. "EN_DEST4,Enable BRC destination address z" "0,1" bitfld.long 0x8 3. "EN_DEST3,Enable BRC destination address z" "0,1" bitfld.long 0x8 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 1. "EN_DEST1,Enable BRC destination address z" "0,1" bitfld.long 0x8 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0xC "BRC_SRC_1_ADDR," bitfld.long 0xC 12. "BRC_MODE,BRC Operation mode select." "0,1" hexmask.long.word 0xC 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x10 "BRC_SRC_1_DEST," bitfld.long 0x10 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" bitfld.long 0x10 21. "EN_DEST21,Enable BRC destination address z" "0,1" bitfld.long 0x10 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 19. "EN_DEST19,Enable BRC destination address z" "0,1" bitfld.long 0x10 18. "EN_DEST18,Enable BRC destination address z" "0,1" bitfld.long 0x10 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 16. "EN_DEST16,Enable BRC destination address z" "0,1" bitfld.long 0x10 15. "EN_DEST15,Enable BRC destination address z" "0,1" bitfld.long 0x10 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 13. "EN_DEST13,Enable BRC destination address z" "0,1" bitfld.long 0x10 12. "EN_DEST12,Enable BRC destination address z" "0,1" bitfld.long 0x10 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 10. "EN_DEST10,Enable BRC destination address z" "0,1" bitfld.long 0x10 9. "EN_DEST9,Enable BRC destination address z" "0,1" bitfld.long 0x10 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 7. "EN_DEST7,Enable BRC destination address z" "0,1" bitfld.long 0x10 6. "EN_DEST6,Enable BRC destination address z" "0,1" bitfld.long 0x10 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 4. "EN_DEST4,Enable BRC destination address z" "0,1" bitfld.long 0x10 3. "EN_DEST3,Enable BRC destination address z" "0,1" bitfld.long 0x10 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 1. "EN_DEST1,Enable BRC destination address z" "0,1" bitfld.long 0x10 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x14 "BRC_SRC_2_ADDR," bitfld.long 0x14 12. "BRC_MODE,BRC Operation mode select." "0,1" hexmask.long.word 0x14 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x18 "BRC_SRC_2_DEST," bitfld.long 0x18 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" bitfld.long 0x18 21. "EN_DEST21,Enable BRC destination address z" "0,1" bitfld.long 0x18 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 19. "EN_DEST19,Enable BRC destination address z" "0,1" bitfld.long 0x18 18. "EN_DEST18,Enable BRC destination address z" "0,1" bitfld.long 0x18 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 16. "EN_DEST16,Enable BRC destination address z" "0,1" bitfld.long 0x18 15. "EN_DEST15,Enable BRC destination address z" "0,1" bitfld.long 0x18 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 13. "EN_DEST13,Enable BRC destination address z" "0,1" bitfld.long 0x18 12. "EN_DEST12,Enable BRC destination address z" "0,1" bitfld.long 0x18 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 10. "EN_DEST10,Enable BRC destination address z" "0,1" bitfld.long 0x18 9. "EN_DEST9,Enable BRC destination address z" "0,1" bitfld.long 0x18 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 7. "EN_DEST7,Enable BRC destination address z" "0,1" bitfld.long 0x18 6. "EN_DEST6,Enable BRC destination address z" "0,1" bitfld.long 0x18 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 4. "EN_DEST4,Enable BRC destination address z" "0,1" bitfld.long 0x18 3. "EN_DEST3,Enable BRC destination address z" "0,1" bitfld.long 0x18 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 1. "EN_DEST1,Enable BRC destination address z" "0,1" bitfld.long 0x18 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x1C "BRC_SRC_3_ADDR," bitfld.long 0x1C 12. "BRC_MODE,BRC Operation mode select." "0,1" hexmask.long.word 0x1C 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x20 "BRC_SRC_3_DEST," bitfld.long 0x20 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" bitfld.long 0x20 21. "EN_DEST21,Enable BRC destination address z" "0,1" bitfld.long 0x20 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 19. "EN_DEST19,Enable BRC destination address z" "0,1" bitfld.long 0x20 18. "EN_DEST18,Enable BRC destination address z" "0,1" bitfld.long 0x20 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 16. "EN_DEST16,Enable BRC destination address z" "0,1" bitfld.long 0x20 15. "EN_DEST15,Enable BRC destination address z" "0,1" bitfld.long 0x20 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 13. "EN_DEST13,Enable BRC destination address z" "0,1" bitfld.long 0x20 12. "EN_DEST12,Enable BRC destination address z" "0,1" bitfld.long 0x20 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 10. "EN_DEST10,Enable BRC destination address z" "0,1" bitfld.long 0x20 9. "EN_DEST9,Enable BRC destination address z" "0,1" bitfld.long 0x20 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 7. "EN_DEST7,Enable BRC destination address z" "0,1" bitfld.long 0x20 6. "EN_DEST6,Enable BRC destination address z" "0,1" bitfld.long 0x20 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 4. "EN_DEST4,Enable BRC destination address z" "0,1" bitfld.long 0x20 3. "EN_DEST3,Enable BRC destination address z" "0,1" bitfld.long 0x20 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 1. "EN_DEST1,Enable BRC destination address z" "0,1" bitfld.long 0x20 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x24 "BRC_SRC_4_ADDR," bitfld.long 0x24 12. "BRC_MODE,BRC Operation mode select." "0,1" hexmask.long.word 0x24 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x28 "BRC_SRC_4_DEST," bitfld.long 0x28 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" bitfld.long 0x28 21. "EN_DEST21,Enable BRC destination address z" "0,1" bitfld.long 0x28 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 19. "EN_DEST19,Enable BRC destination address z" "0,1" bitfld.long 0x28 18. "EN_DEST18,Enable BRC destination address z" "0,1" bitfld.long 0x28 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 16. "EN_DEST16,Enable BRC destination address z" "0,1" bitfld.long 0x28 15. "EN_DEST15,Enable BRC destination address z" "0,1" bitfld.long 0x28 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 13. "EN_DEST13,Enable BRC destination address z" "0,1" bitfld.long 0x28 12. "EN_DEST12,Enable BRC destination address z" "0,1" bitfld.long 0x28 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 10. "EN_DEST10,Enable BRC destination address z" "0,1" bitfld.long 0x28 9. "EN_DEST9,Enable BRC destination address z" "0,1" bitfld.long 0x28 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 7. "EN_DEST7,Enable BRC destination address z" "0,1" bitfld.long 0x28 6. "EN_DEST6,Enable BRC destination address z" "0,1" bitfld.long 0x28 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 4. "EN_DEST4,Enable BRC destination address z" "0,1" bitfld.long 0x28 3. "EN_DEST3,Enable BRC destination address z" "0,1" bitfld.long 0x28 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 1. "EN_DEST1,Enable BRC destination address z" "0,1" bitfld.long 0x28 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x2C "BRC_SRC_5_ADDR," bitfld.long 0x2C 12. "BRC_MODE,BRC Operation mode select." "0,1" hexmask.long.word 0x2C 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x30 "BRC_SRC_5_DEST," bitfld.long 0x30 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" bitfld.long 0x30 21. "EN_DEST21,Enable BRC destination address z" "0,1" bitfld.long 0x30 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 19. "EN_DEST19,Enable BRC destination address z" "0,1" bitfld.long 0x30 18. "EN_DEST18,Enable BRC destination address z" "0,1" bitfld.long 0x30 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 16. "EN_DEST16,Enable BRC destination address z" "0,1" bitfld.long 0x30 15. "EN_DEST15,Enable BRC destination address z" "0,1" bitfld.long 0x30 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 13. "EN_DEST13,Enable BRC destination address z" "0,1" bitfld.long 0x30 12. "EN_DEST12,Enable BRC destination address z" "0,1" bitfld.long 0x30 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 10. "EN_DEST10,Enable BRC destination address z" "0,1" bitfld.long 0x30 9. "EN_DEST9,Enable BRC destination address z" "0,1" bitfld.long 0x30 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 7. "EN_DEST7,Enable BRC destination address z" "0,1" bitfld.long 0x30 6. "EN_DEST6,Enable BRC destination address z" "0,1" bitfld.long 0x30 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 4. "EN_DEST4,Enable BRC destination address z" "0,1" bitfld.long 0x30 3. "EN_DEST3,Enable BRC destination address z" "0,1" bitfld.long 0x30 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 1. "EN_DEST1,Enable BRC destination address z" "0,1" bitfld.long 0x30 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x34 "BRC_SRC_6_ADDR," bitfld.long 0x34 12. "BRC_MODE,BRC Operation mode select." "0,1" hexmask.long.word 0x34 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x38 "BRC_SRC_6_DEST," bitfld.long 0x38 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" bitfld.long 0x38 21. "EN_DEST21,Enable BRC destination address z" "0,1" bitfld.long 0x38 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 19. "EN_DEST19,Enable BRC destination address z" "0,1" bitfld.long 0x38 18. "EN_DEST18,Enable BRC destination address z" "0,1" bitfld.long 0x38 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 16. "EN_DEST16,Enable BRC destination address z" "0,1" bitfld.long 0x38 15. "EN_DEST15,Enable BRC destination address z" "0,1" bitfld.long 0x38 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 13. "EN_DEST13,Enable BRC destination address z" "0,1" bitfld.long 0x38 12. "EN_DEST12,Enable BRC destination address z" "0,1" bitfld.long 0x38 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 10. "EN_DEST10,Enable BRC destination address z" "0,1" bitfld.long 0x38 9. "EN_DEST9,Enable BRC destination address z" "0,1" bitfld.long 0x38 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 7. "EN_DEST7,Enable BRC destination address z" "0,1" bitfld.long 0x38 6. "EN_DEST6,Enable BRC destination address z" "0,1" bitfld.long 0x38 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 4. "EN_DEST4,Enable BRC destination address z" "0,1" bitfld.long 0x38 3. "EN_DEST3,Enable BRC destination address z" "0,1" bitfld.long 0x38 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 1. "EN_DEST1,Enable BRC destination address z" "0,1" bitfld.long 0x38 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x3C "BRC_SRC_7_ADDR," bitfld.long 0x3C 12. "BRC_MODE,BRC Operation mode select." "0,1" hexmask.long.word 0x3C 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x40 "BRC_SRC_7_DEST," bitfld.long 0x40 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" bitfld.long 0x40 21. "EN_DEST21,Enable BRC destination address z" "0,1" bitfld.long 0x40 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 19. "EN_DEST19,Enable BRC destination address z" "0,1" bitfld.long 0x40 18. "EN_DEST18,Enable BRC destination address z" "0,1" bitfld.long 0x40 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 16. "EN_DEST16,Enable BRC destination address z" "0,1" bitfld.long 0x40 15. "EN_DEST15,Enable BRC destination address z" "0,1" bitfld.long 0x40 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 13. "EN_DEST13,Enable BRC destination address z" "0,1" bitfld.long 0x40 12. "EN_DEST12,Enable BRC destination address z" "0,1" bitfld.long 0x40 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 10. "EN_DEST10,Enable BRC destination address z" "0,1" bitfld.long 0x40 9. "EN_DEST9,Enable BRC destination address z" "0,1" bitfld.long 0x40 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 7. "EN_DEST7,Enable BRC destination address z" "0,1" bitfld.long 0x40 6. "EN_DEST6,Enable BRC destination address z" "0,1" bitfld.long 0x40 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 4. "EN_DEST4,Enable BRC destination address z" "0,1" bitfld.long 0x40 3. "EN_DEST3,Enable BRC destination address z" "0,1" bitfld.long 0x40 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 1. "EN_DEST1,Enable BRC destination address z" "0,1" bitfld.long 0x40 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x44 "BRC_SRC_8_ADDR," bitfld.long 0x44 12. "BRC_MODE,BRC Operation mode select." "0,1" hexmask.long.word 0x44 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x48 "BRC_SRC_8_DEST," bitfld.long 0x48 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" bitfld.long 0x48 21. "EN_DEST21,Enable BRC destination address z" "0,1" bitfld.long 0x48 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 19. "EN_DEST19,Enable BRC destination address z" "0,1" bitfld.long 0x48 18. "EN_DEST18,Enable BRC destination address z" "0,1" bitfld.long 0x48 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 16. "EN_DEST16,Enable BRC destination address z" "0,1" bitfld.long 0x48 15. "EN_DEST15,Enable BRC destination address z" "0,1" bitfld.long 0x48 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 13. "EN_DEST13,Enable BRC destination address z" "0,1" bitfld.long 0x48 12. "EN_DEST12,Enable BRC destination address z" "0,1" bitfld.long 0x48 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 10. "EN_DEST10,Enable BRC destination address z" "0,1" bitfld.long 0x48 9. "EN_DEST9,Enable BRC destination address z" "0,1" bitfld.long 0x48 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 7. "EN_DEST7,Enable BRC destination address z" "0,1" bitfld.long 0x48 6. "EN_DEST6,Enable BRC destination address z" "0,1" bitfld.long 0x48 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 4. "EN_DEST4,Enable BRC destination address z" "0,1" bitfld.long 0x48 3. "EN_DEST3,Enable BRC destination address z" "0,1" bitfld.long 0x48 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 1. "EN_DEST1,Enable BRC destination address z" "0,1" bitfld.long 0x48 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x4C "BRC_SRC_9_ADDR," bitfld.long 0x4C 12. "BRC_MODE,BRC Operation mode select." "0,1" hexmask.long.word 0x4C 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x50 "BRC_SRC_9_DEST," bitfld.long 0x50 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" bitfld.long 0x50 21. "EN_DEST21,Enable BRC destination address z" "0,1" bitfld.long 0x50 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 19. "EN_DEST19,Enable BRC destination address z" "0,1" bitfld.long 0x50 18. "EN_DEST18,Enable BRC destination address z" "0,1" bitfld.long 0x50 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 16. "EN_DEST16,Enable BRC destination address z" "0,1" bitfld.long 0x50 15. "EN_DEST15,Enable BRC destination address z" "0,1" bitfld.long 0x50 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 13. "EN_DEST13,Enable BRC destination address z" "0,1" bitfld.long 0x50 12. "EN_DEST12,Enable BRC destination address z" "0,1" bitfld.long 0x50 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 10. "EN_DEST10,Enable BRC destination address z" "0,1" bitfld.long 0x50 9. "EN_DEST9,Enable BRC destination address z" "0,1" bitfld.long 0x50 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 7. "EN_DEST7,Enable BRC destination address z" "0,1" bitfld.long 0x50 6. "EN_DEST6,Enable BRC destination address z" "0,1" bitfld.long 0x50 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 4. "EN_DEST4,Enable BRC destination address z" "0,1" bitfld.long 0x50 3. "EN_DEST3,Enable BRC destination address z" "0,1" bitfld.long 0x50 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 1. "EN_DEST1,Enable BRC destination address z" "0,1" bitfld.long 0x50 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x54 "BRC_SRC_10_ADDR," bitfld.long 0x54 12. "BRC_MODE,BRC Operation mode select." "0,1" hexmask.long.word 0x54 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x58 "BRC_SRC_10_DEST," bitfld.long 0x58 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" bitfld.long 0x58 21. "EN_DEST21,Enable BRC destination address z" "0,1" bitfld.long 0x58 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 19. "EN_DEST19,Enable BRC destination address z" "0,1" bitfld.long 0x58 18. "EN_DEST18,Enable BRC destination address z" "0,1" bitfld.long 0x58 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 16. "EN_DEST16,Enable BRC destination address z" "0,1" bitfld.long 0x58 15. "EN_DEST15,Enable BRC destination address z" "0,1" bitfld.long 0x58 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 13. "EN_DEST13,Enable BRC destination address z" "0,1" bitfld.long 0x58 12. "EN_DEST12,Enable BRC destination address z" "0,1" bitfld.long 0x58 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 10. "EN_DEST10,Enable BRC destination address z" "0,1" bitfld.long 0x58 9. "EN_DEST9,Enable BRC destination address z" "0,1" bitfld.long 0x58 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 7. "EN_DEST7,Enable BRC destination address z" "0,1" bitfld.long 0x58 6. "EN_DEST6,Enable BRC destination address z" "0,1" bitfld.long 0x58 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 4. "EN_DEST4,Enable BRC destination address z" "0,1" bitfld.long 0x58 3. "EN_DEST3,Enable BRC destination address z" "0,1" bitfld.long 0x58 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 1. "EN_DEST1,Enable BRC destination address z" "0,1" bitfld.long 0x58 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x5C "BRC_SRC_11_ADDR," bitfld.long 0x5C 12. "BRC_MODE,BRC Operation mode select." "0,1" hexmask.long.word 0x5C 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x60 "BRC_SRC_11_DEST," bitfld.long 0x60 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" bitfld.long 0x60 21. "EN_DEST21,Enable BRC destination address z" "0,1" bitfld.long 0x60 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 19. "EN_DEST19,Enable BRC destination address z" "0,1" bitfld.long 0x60 18. "EN_DEST18,Enable BRC destination address z" "0,1" bitfld.long 0x60 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 16. "EN_DEST16,Enable BRC destination address z" "0,1" bitfld.long 0x60 15. "EN_DEST15,Enable BRC destination address z" "0,1" bitfld.long 0x60 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 13. "EN_DEST13,Enable BRC destination address z" "0,1" bitfld.long 0x60 12. "EN_DEST12,Enable BRC destination address z" "0,1" bitfld.long 0x60 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 10. "EN_DEST10,Enable BRC destination address z" "0,1" bitfld.long 0x60 9. "EN_DEST9,Enable BRC destination address z" "0,1" bitfld.long 0x60 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 7. "EN_DEST7,Enable BRC destination address z" "0,1" bitfld.long 0x60 6. "EN_DEST6,Enable BRC destination address z" "0,1" bitfld.long 0x60 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 4. "EN_DEST4,Enable BRC destination address z" "0,1" bitfld.long 0x60 3. "EN_DEST3,Enable BRC destination address z" "0,1" bitfld.long 0x60 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 1. "EN_DEST1,Enable BRC destination address z" "0,1" bitfld.long 0x60 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x64 "BRC_IRQ_NOTIFY," bitfld.long 0x64 12. "DID11,Data inconsistency occurred in MTM mode for channel [y]." "0,1" bitfld.long 0x64 11. "DID10,Data inconsistency occurred in MTM mode for channel [y]." "0,1" bitfld.long 0x64 10. "DID9,Data inconsistency occurred in MTM mode for channel [y]." "0,1" newline bitfld.long 0x64 9. "DID8,Data inconsistency occurred in MTM mode for channel [y]." "0,1" bitfld.long 0x64 8. "DID7,Data inconsistency occurred in MTM mode for channel [y]." "0,1" bitfld.long 0x64 7. "DID6,Data inconsistency occurred in MTM mode for channel [y]." "0,1" newline bitfld.long 0x64 6. "DID5,Data inconsistency occurred in MTM mode for channel [y]." "0,1" bitfld.long 0x64 5. "DID4,Data inconsistency occurred in MTM mode for channel [y]." "0,1" bitfld.long 0x64 4. "DID3,Data inconsistency occurred in MTM mode for channel [y]." "0,1" newline bitfld.long 0x64 3. "DID2,Data inconsistency occurred in MTM mode for channel [y]." "0,1" bitfld.long 0x64 2. "DID1,Data inconsistency occurred in MTM mode for channel [y]." "0,1" bitfld.long 0x64 1. "DID0,Data inconsistency occurred in MTM mode for channel [y]." "0,1" newline bitfld.long 0x64 0. "DEST_ERR,Configuration error interrupt for BRC sub-module" "0,1" line.long 0x68 "BRC_IRQ_EN," bitfld.long 0x68 12. "DID_IRQ_EN11,Enable BRC_DID_IRQ for channel [y]" "0,1" bitfld.long 0x68 11. "DID_IRQ_EN10,Enable BRC_DID_IRQ for channel [y]" "0,1" bitfld.long 0x68 10. "DID_IRQ_EN9,Enable BRC_DID_IRQ for channel [y]" "0,1" newline bitfld.long 0x68 9. "DID_IRQ_EN8,Enable BRC_DID_IRQ for channel [y]" "0,1" bitfld.long 0x68 8. "DID_IRQ_EN7,Enable BRC_DID_IRQ for channel [y]" "0,1" bitfld.long 0x68 7. "DID_IRQ_EN6,Enable BRC_DID_IRQ for channel [y]" "0,1" newline bitfld.long 0x68 6. "DID_IRQ_EN5,Enable BRC_DID_IRQ for channel [y]" "0,1" bitfld.long 0x68 5. "DID_IRQ_EN4,Enable BRC_DID_IRQ for channel [y]" "0,1" bitfld.long 0x68 4. "DID_IRQ_EN3,Enable BRC_DID_IRQ for channel [y]" "0,1" newline bitfld.long 0x68 3. "DID_IRQ_EN2,Enable BRC_DID_IRQ for channel [y]" "0,1" bitfld.long 0x68 2. "DID_IRQ_EN1,Enable BRC_DID_IRQ for channel [y]" "0,1" bitfld.long 0x68 1. "DID_IRQ_EN0,Enable BRC_DID_IRQ for channel [y]" "0,1" newline bitfld.long 0x68 0. "DEST_ERR_IRQ_EN,BRC_DEST_ERR_IRQ interrupt enable" "0,1" line.long 0x6C "BRC_IRQ_FORCINT," bitfld.long 0x6C 12. "TRG_DID11,Trigger DID channel [y] interrupt" "0,1" bitfld.long 0x6C 11. "TRG_DID10,Trigger DID channel [y] interrupt" "0,1" bitfld.long 0x6C 10. "TRG_DID9,Trigger DID channel [y] interrupt" "0,1" newline bitfld.long 0x6C 9. "TRG_DID8,Trigger DID channel [y] interrupt" "0,1" bitfld.long 0x6C 8. "TRG_DID7,Trigger DID channel [y] interrupt" "0,1" bitfld.long 0x6C 7. "TRG_DID6,Trigger DID channel [y] interrupt" "0,1" newline bitfld.long 0x6C 6. "TRG_DID5,Trigger DID channel [y] interrupt" "0,1" bitfld.long 0x6C 5. "TRG_DID4,Trigger DID channel [y] interrupt" "0,1" bitfld.long 0x6C 4. "TRG_DID3,Trigger DID channel [y] interrupt" "0,1" newline bitfld.long 0x6C 3. "TRG_DID2,Trigger DID channel [y] interrupt" "0,1" bitfld.long 0x6C 2. "TRG_DID1,Trigger DID channel [y] interrupt" "0,1" bitfld.long 0x6C 1. "TRG_DID0,Trigger DID channel [y] interrupt" "0,1" newline bitfld.long 0x6C 0. "TRG_DEST_ERR,Trigger destination error interrupt." "0,1" line.long 0x70 "BRC_IRQ_MODE," bitfld.long 0x70 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x74 "BRC_RST," bitfld.long 0x74 0. "RST,Software reset" "0,1" line.long 0x78 "BRC_EIRQ_EN," bitfld.long 0x78 12. "DID_EIRQ_EN11,Enable BRC_DID_EIRQ for channel y" "0,1" bitfld.long 0x78 11. "DID_EIRQ_EN10,Enable BRC_DID_EIRQ for channel y" "0,1" bitfld.long 0x78 10. "DID_EIRQ_EN9,Enable BRC_DID_EIRQ for channel y" "0,1" newline bitfld.long 0x78 9. "DID_EIRQ_EN8,Enable BRC_DID_EIRQ for channel y" "0,1" bitfld.long 0x78 8. "DID_EIRQ_EN7,Enable BRC_DID_EIRQ for channel y" "0,1" bitfld.long 0x78 7. "DID_EIRQ_EN6,Enable BRC_DID_EIRQ for channel y" "0,1" newline bitfld.long 0x78 6. "DID_EIRQ_EN5,Enable BRC_DID_EIRQ for channel y" "0,1" bitfld.long 0x78 5. "DID_EIRQ_EN4,Enable BRC_DID_EIRQ for channel y" "0,1" bitfld.long 0x78 4. "DID_EIRQ_EN3,Enable BRC_DID_EIRQ for channel y" "0,1" newline bitfld.long 0x78 3. "DID_EIRQ_EN2,Enable BRC_DID_EIRQ for channel y" "0,1" bitfld.long 0x78 2. "DID_EIRQ_EN1,Enable BRC_DID_EIRQ for channel y" "0,1" bitfld.long 0x78 1. "DID_EIRQ_EN0,Enable BRC_DID_EIRQ for channel y" "0,1" newline bitfld.long 0x78 0. "DEST_ERR_EIRQ_EN,BRC_DEST_ERR_EIRQ error interrupt enable" "0,1" group.long 0x400++0x3 line.long 0x0 "ICM_IRQG_0," bitfld.long 0x0 31. "PSM1_CH7_IRQ,PSM1 shared sub-module channel x interrupt." "0,1" bitfld.long 0x0 30. "PSM1_CH6_IRQ,PSM1 shared sub-module channel x interrupt." "0,1" bitfld.long 0x0 29. "PSM1_CH5_IRQ,PSM1 shared sub-module channel x interrupt." "0,1" newline bitfld.long 0x0 28. "PSM1_CH4_IRQ,PSM1 shared sub-module channel x interrupt." "0,1" bitfld.long 0x0 27. "PSM1_CH3_IRQ,PSM1 shared sub-module channel x interrupt." "0,1" bitfld.long 0x0 26. "PSM1_CH2_IRQ,PSM1 shared sub-module channel x interrupt." "0,1" newline bitfld.long 0x0 25. "PSM1_CH1_IRQ,PSM1 shared sub-module channel x interrupt." "0,1" bitfld.long 0x0 24. "PSM1_CH0_IRQ,PSM1 shared sub-module channel x interrupt." "0,1" bitfld.long 0x0 23. "PSM0_CH7_IRQ,PSM0 shared sub-module channel x interrupt." "0,1" newline bitfld.long 0x0 22. "PSM0_CH6_IRQ,PSM0 shared sub-module channel x interrupt." "0,1" bitfld.long 0x0 21. "PSM0_CH5_IRQ,PSM0 shared sub-module channel x interrupt." "0,1" bitfld.long 0x0 20. "PSM0_CH4_IRQ,PSM0 shared sub-module channel x interrupt." "0,1" newline bitfld.long 0x0 19. "PSM0_CH3_IRQ,PSM0 shared sub-module channel x interrupt." "0,1" bitfld.long 0x0 18. "PSM0_CH2_IRQ,PSM0 shared sub-module channel x interrupt." "0,1" bitfld.long 0x0 17. "PSM0_CH1_IRQ,PSM0 shared sub-module channel x interrupt." "0,1" newline bitfld.long 0x0 16. "PSM0_CH0_IRQ,PSM0 shared sub-module channel x interrupt." "0,1" bitfld.long 0x0 13. "SPE7_IRQ,SPE[j] shared sub-module interrupt." "0,1" bitfld.long 0x0 12. "SPE6_IRQ,SPE[j] shared sub-module interrupt." "0,1" newline bitfld.long 0x0 11. "SPE5_IRQ,SPE[j] shared sub-module interrupt." "0,1" bitfld.long 0x0 10. "SPE4_IRQ,SPE[j] shared sub-module interrupt." "0,1" bitfld.long 0x0 9. "SPE3_IRQ,SPE[j] shared sub-module interrupt." "0,1" newline bitfld.long 0x0 8. "SPE2_IRQ,SPE[j] shared sub-module interrupt." "0,1" bitfld.long 0x0 7. "SPE1_IRQ,SPE[j] shared sub-module interrupt." "0,1" bitfld.long 0x0 6. "SPE0_IRQ,SPE[j] shared sub-module interrupt." "0,1" newline bitfld.long 0x0 5. "CMP_IRQ,CMP shared sub-module interrupt." "0,1" bitfld.long 0x0 4. "AEI_IRQ,AEI_IRQ: AEI_IRQ interrupt." "0,1" bitfld.long 0x0 3. "BRC_IRQ,BRC shared sub-module interrupt." "0,1" newline bitfld.long 0x0 2. "ARU_ACC_ACK_IRQ,ARU_ACC_ACK interrupt." "0,1" bitfld.long 0x0 1. "ARU_NEW_DATA1_IRQ,ARU_NEW_DATA1 interrupt." "0,1" bitfld.long 0x0 0. "ARU_NEW_DATA0_IRQ,ARU_NEW_DATA0 interrupt" "0,1" group.long 0x408++0x3 line.long 0x0 "ICM_IRQG_2," bitfld.long 0x0 31. "TIM3_CH7_IRQ,TIM3 shared interrupt channel x." "0,1" bitfld.long 0x0 30. "TIM3_CH6_IRQ,TIM3 shared interrupt channel x." "0,1" bitfld.long 0x0 29. "TIM3_CH5_IRQ,TIM3 shared interrupt channel x." "0,1" newline bitfld.long 0x0 28. "TIM3_CH4_IRQ,TIM3 shared interrupt channel x." "0,1" bitfld.long 0x0 27. "TIM3_CH3_IRQ,TIM3 shared interrupt channel x." "0,1" bitfld.long 0x0 26. "TIM3_CH2_IRQ,TIM3 shared interrupt channel x." "0,1" newline bitfld.long 0x0 25. "TIM3_CH1_IRQ,TIM3 shared interrupt channel x." "0,1" bitfld.long 0x0 24. "TIM3_CH0_IRQ,TIM3 shared interrupt channel x." "0,1" bitfld.long 0x0 23. "TIM2_CH7_IRQ,TIM2 shared interrupt channel x." "0,1" newline bitfld.long 0x0 22. "TIM2_CH6_IRQ,TIM2 shared interrupt channel x." "0,1" bitfld.long 0x0 21. "TIM2_CH5_IRQ,TIM2 shared interrupt channel x." "0,1" bitfld.long 0x0 20. "TIM2_CH4_IRQ,TIM2 shared interrupt channel x." "0,1" newline bitfld.long 0x0 19. "TIM2_CH3_IRQ,TIM2 shared interrupt channel x." "0,1" bitfld.long 0x0 18. "TIM2_CH2_IRQ,TIM2 shared interrupt channel x." "0,1" bitfld.long 0x0 17. "TIM2_CH1_IRQ,TIM2 shared interrupt channel x." "0,1" newline bitfld.long 0x0 16. "TIM2_CH0_IRQ,TIM2 shared interrupt channel x." "0,1" bitfld.long 0x0 15. "TIM1_CH7_IRQ,TIM1 shared interrupt channel x." "0,1" bitfld.long 0x0 14. "TIM1_CH6_IRQ,TIM1 shared interrupt channel x." "0,1" newline bitfld.long 0x0 13. "TIM1_CH5_IRQ,TIM1 shared interrupt channel x." "0,1" bitfld.long 0x0 12. "TIM1_CH4_IRQ,TIM1 shared interrupt channel x." "0,1" bitfld.long 0x0 11. "TIM1_CH3_IRQ,TIM1 shared interrupt channel x." "0,1" newline bitfld.long 0x0 10. "TIM1_CH2_IRQ,TIM1 shared interrupt channel x." "0,1" bitfld.long 0x0 9. "TIM1_CH1_IRQ,TIM1 shared interrupt channel x." "0,1" bitfld.long 0x0 8. "TIM1_CH0_IRQ,TIM1 shared interrupt channel x." "0,1" newline bitfld.long 0x0 7. "TIM0_CH7_IRQ,TIM0 shared interrupt channel x." "0,1" bitfld.long 0x0 6. "TIM0_CH6_IRQ,TIM0 shared interrupt channel x." "0,1" bitfld.long 0x0 5. "TIM0_CH5_IRQ,TIM0 shared interrupt channel x." "0,1" newline bitfld.long 0x0 4. "TIM0_CH4_IRQ,TIM0 shared interrupt channel x." "0,1" bitfld.long 0x0 3. "TIM0_CH3_IRQ,TIM0 shared interrupt channel x." "0,1" bitfld.long 0x0 2. "TIM0_CH2_IRQ,TIM0 shared interrupt channel x." "0,1" newline bitfld.long 0x0 1. "TIM0_CH1_IRQ,TIM0 shared interrupt channel x." "0,1" bitfld.long 0x0 0. "TIM0_CH0_IRQ,TIM0 shared interrupt channel x." "0,1" group.long 0x430++0xB line.long 0x0 "ICM_IRQG_MEI," bitfld.long 0x0 25. "DPLL_EIRQ,DPLL error interrupt." "0,1" bitfld.long 0x0 24. "CMP_EIRQ,CMP error interrupt." "0,1" bitfld.long 0x0 23. "SPE3_EIRQ,SPE[j] error interrupt." "0,1" newline bitfld.long 0x0 22. "SPE2_EIRQ,SPE[j] error interrupt." "0,1" bitfld.long 0x0 21. "SPE1_EIRQ,SPE[j] error interrupt." "0,1" bitfld.long 0x0 20. "SPE0_EIRQ,SPE[j] error interrupt." "0,1" newline bitfld.long 0x0 19. "MCS7_EIRQ,MCS[j] error interrupt." "0,1" bitfld.long 0x0 18. "MCS6_EIRQ,MCS[j] error interrupt." "0,1" bitfld.long 0x0 17. "MCS5_EIRQ,MCS[j] error interrupt." "0,1" newline bitfld.long 0x0 16. "MCS4_EIRQ,MCS[j] error interrupt." "0,1" bitfld.long 0x0 15. "MCS3_EIRQ,MCS[j] error interrupt." "0,1" bitfld.long 0x0 14. "MCS2_EIRQ,MCS[j] error interrupt." "0,1" newline bitfld.long 0x0 13. "MCS1_EIRQ,MCS[j] error interrupt." "0,1" bitfld.long 0x0 12. "MCS0_EIRQ,MCS[j] error interrupt." "0,1" bitfld.long 0x0 11. "TIM7_EIRQ,TIM[j] error interrupt." "0,1" newline bitfld.long 0x0 10. "TIM6_EIRQ,TIM[j] error interrupt." "0,1" bitfld.long 0x0 9. "TIM5_EIRQ,TIM[j] error interrupt." "0,1" bitfld.long 0x0 8. "TIM4_EIRQ,TIM[j] error interrupt." "0,1" newline bitfld.long 0x0 7. "TIM3_EIRQ,TIM[j] error interrupt." "0,1" bitfld.long 0x0 6. "TIM2_EIRQ,TIM[j] error interrupt." "0,1" bitfld.long 0x0 5. "TIM1_EIRQ,TIM[j] error interrupt." "0,1" newline bitfld.long 0x0 4. "TIM0_EIRQ,TIM[j] error interrupt." "0,1" bitfld.long 0x0 3. "FIFO1_EIRQ,FIFO[j] error interrupt." "0,1" bitfld.long 0x0 2. "FIFO0_EIRQ,FIFO[j] error interrupt." "0,1" newline bitfld.long 0x0 1. "BRC_EIRQ,BRC error interrupt." "0,1" bitfld.long 0x0 0. "GTM_EIRQ,AEI Error interrupt request" "0,1" line.long 0x4 "ICM_IRQG_CEI0," bitfld.long 0x4 23. "FIFO2_CH7_EIRQ,FIFO2 channel x error interrupt." "0,1" bitfld.long 0x4 22. "FIFO2_CH6_EIRQ,FIFO2 channel x error interrupt." "0,1" bitfld.long 0x4 21. "FIFO2_CH5_EIRQ,FIFO2 channel x error interrupt." "0,1" newline bitfld.long 0x4 20. "FIFO2_CH4_EIRQ,FIFO2 channel x error interrupt." "0,1" bitfld.long 0x4 19. "FIFO2_CH3_EIRQ,FIFO2 channel x error interrupt." "0,1" bitfld.long 0x4 18. "FIFO2_CH2_EIRQ,FIFO2 channel x error interrupt." "0,1" newline bitfld.long 0x4 17. "FIFO2_CH1_EIRQ,FIFO2 channel x error interrupt." "0,1" bitfld.long 0x4 16. "FIFO2_CH0_EIRQ,FIFO2 channel x error interrupt." "0,1" bitfld.long 0x4 15. "FIFO1_CH7_EIRQ,FIFO1 channel x error interrupt." "0,1" newline bitfld.long 0x4 14. "FIFO1_CH6_EIRQ,FIFO1 channel x error interrupt." "0,1" bitfld.long 0x4 13. "FIFO1_CH5_EIRQ,FIFO1 channel x error interrupt." "0,1" bitfld.long 0x4 12. "FIFO1_CH4_EIRQ,FIFO1 channel x error interrupt." "0,1" newline bitfld.long 0x4 11. "FIFO1_CH3_EIRQ,FIFO1 channel x error interrupt." "0,1" bitfld.long 0x4 10. "FIFO1_CH2_EIRQ,FIFO1 channel x error interrupt." "0,1" bitfld.long 0x4 9. "FIFO1_CH1_EIRQ,FIFO1 channel x error interrupt." "0,1" newline bitfld.long 0x4 8. "FIFO1_CH0_EIRQ,FIFO1 channel x error interrupt." "0,1" bitfld.long 0x4 7. "FIFO0_CH7_EIRQ,FIFO0 channel x error interrupt" "0,1" bitfld.long 0x4 6. "FIFO0_CH6_EIRQ,FIFO0 channel x error interrupt" "0,1" newline bitfld.long 0x4 5. "FIFO0_CH5_EIRQ,FIFO0 channel x error interrupt" "0,1" bitfld.long 0x4 4. "FIFO0_CH4_EIRQ,FIFO0 channel x error interrupt" "0,1" bitfld.long 0x4 3. "FIFO0_CH3_EIRQ,FIFO0 channel x error interrupt" "0,1" newline bitfld.long 0x4 2. "FIFO0_CH2_EIRQ,FIFO0 channel x error interrupt" "0,1" bitfld.long 0x4 1. "FIFO0_CH1_EIRQ,FIFO0 channel x error interrupt" "0,1" bitfld.long 0x4 0. "FIFO0_CH0_EIRQ,FIFO0 channel x error interrupt" "0,1" line.long 0x8 "ICM_IRQG_CEI1," bitfld.long 0x8 31. "TIM3_CH7_EIRQ,TIM3 channel x error interrupt." "0,1" bitfld.long 0x8 30. "TIM3_CH6_EIRQ,TIM3 channel x error interrupt." "0,1" bitfld.long 0x8 29. "TIM3_CH5_EIRQ,TIM3 channel x error interrupt." "0,1" newline bitfld.long 0x8 28. "TIM3_CH4_EIRQ,TIM3 channel x error interrupt." "0,1" bitfld.long 0x8 27. "TIM3_CH3_EIRQ,TIM3 channel x error interrupt." "0,1" bitfld.long 0x8 26. "TIM3_CH2_EIRQ,TIM3 channel x error interrupt." "0,1" newline bitfld.long 0x8 25. "TIM3_CH1_EIRQ,TIM3 channel x error interrupt." "0,1" bitfld.long 0x8 24. "TIM3_CH0_EIRQ,TIM3 channel x error interrupt." "0,1" bitfld.long 0x8 23. "TIM2_CH7_EIRQ,TIM2 channel x error interrupt." "0,1" newline bitfld.long 0x8 22. "TIM2_CH6_EIRQ,TIM2 channel x error interrupt." "0,1" bitfld.long 0x8 21. "TIM2_CH5_EIRQ,TIM2 channel x error interrupt." "0,1" bitfld.long 0x8 20. "TIM2_CH4_EIRQ,TIM2 channel x error interrupt." "0,1" newline bitfld.long 0x8 19. "TIM2_CH3_EIRQ,TIM2 channel x error interrupt." "0,1" bitfld.long 0x8 18. "TIM2_CH2_EIRQ,TIM2 channel x error interrupt." "0,1" bitfld.long 0x8 17. "TIM2_CH1_EIRQ,TIM2 channel x error interrupt." "0,1" newline bitfld.long 0x8 16. "TIM2_CH0_EIRQ,TIM2 channel x error interrupt." "0,1" bitfld.long 0x8 15. "TIM1_CH7_EIRQ,TIM1 channel x error interrupt." "0,1" bitfld.long 0x8 14. "TIM1_CH6_EIRQ,TIM1 channel x error interrupt." "0,1" newline bitfld.long 0x8 13. "TIM1_CH5_EIRQ,TIM1 channel x error interrupt." "0,1" bitfld.long 0x8 12. "TIM1_CH4_EIRQ,TIM1 channel x error interrupt." "0,1" bitfld.long 0x8 11. "TIM1_CH3_EIRQ,TIM1 channel x error interrupt." "0,1" newline bitfld.long 0x8 10. "TIM1_CH2_EIRQ,TIM1 channel x error interrupt." "0,1" bitfld.long 0x8 9. "TIM1_CH1_EIRQ,TIM1 channel x error interrupt." "0,1" bitfld.long 0x8 8. "TIM1_CH0_EIRQ,TIM1 channel x error interrupt." "0,1" newline bitfld.long 0x8 7. "TIM0_CH7_EIRQ,TIM0 channel x error interrupt" "0,1" bitfld.long 0x8 6. "TIM0_CH6_EIRQ,TIM0 channel x error interrupt" "0,1" bitfld.long 0x8 5. "TIM0_CH5_EIRQ,TIM0 channel x error interrupt" "0,1" newline bitfld.long 0x8 4. "TIM0_CH4_EIRQ,TIM0 channel x error interrupt" "0,1" bitfld.long 0x8 3. "TIM0_CH3_EIRQ,TIM0 channel x error interrupt" "0,1" bitfld.long 0x8 2. "TIM0_CH2_EIRQ,TIM0 channel x error interrupt" "0,1" newline bitfld.long 0x8 1. "TIM0_CH1_EIRQ,TIM0 channel x error interrupt" "0,1" bitfld.long 0x8 0. "TIM0_CH0_EIRQ,TIM0 channel x error interrupt" "0,1" group.long 0x4A4++0x3 line.long 0x0 "ICM_IRQG_PSM_0_CEI," bitfld.long 0x0 23. "PSM_M2_CH7_EIRQ,PSMm channel x error interrupt (m=4*0+2)." "0,1" bitfld.long 0x0 22. "PSM_M2_CH6_EIRQ,PSMm channel x error interrupt (m=4*0+2)." "0,1" bitfld.long 0x0 21. "PSM_M2_CH5_EIRQ,PSMm channel x error interrupt (m=4*0+2)." "0,1" newline bitfld.long 0x0 20. "PSM_M2_CH4_EIRQ,PSMm channel x error interrupt (m=4*0+2)." "0,1" bitfld.long 0x0 19. "PSM_M2_CH3_EIRQ,PSMm channel x error interrupt (m=4*0+2)." "0,1" bitfld.long 0x0 18. "PSM_M2_CH2_EIRQ,PSMm channel x error interrupt (m=4*0+2)." "0,1" newline bitfld.long 0x0 17. "PSM_M2_CH1_EIRQ,PSMm channel x error interrupt (m=4*0+2)." "0,1" bitfld.long 0x0 16. "PSM_M2_CH0_EIRQ,PSMm channel x error interrupt (m=4*0+2)." "0,1" bitfld.long 0x0 15. "PSM_M1_CH7_EIRQ,PSMm channel x error interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 14. "PSM_M1_CH6_EIRQ,PSMm channel x error interrupt (m=4*0+1)." "0,1" bitfld.long 0x0 13. "PSM_M1_CH5_EIRQ,PSMm channel x error interrupt (m=4*0+1)." "0,1" bitfld.long 0x0 12. "PSM_M1_CH4_EIRQ,PSMm channel x error interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 11. "PSM_M1_CH3_EIRQ,PSMm channel x error interrupt (m=4*0+1)." "0,1" bitfld.long 0x0 10. "PSM_M1_CH2_EIRQ,PSMm channel x error interrupt (m=4*0+1)." "0,1" bitfld.long 0x0 9. "PSM_M1_CH1_EIRQ,PSMm channel x error interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 8. "PSM_M1_CH0_EIRQ,PSMm channel x error interrupt (m=4*0+1)." "0,1" bitfld.long 0x0 7. "PSM_M0_CH7_EIRQ,PSMm channel x error interrupt (m=4*0+0)." "0,1" bitfld.long 0x0 6. "PSM_M0_CH6_EIRQ,PSMm channel x error interrupt (m=4*0+0)." "0,1" newline bitfld.long 0x0 5. "PSM_M0_CH5_EIRQ,PSMm channel x error interrupt (m=4*0+0)." "0,1" bitfld.long 0x0 4. "PSM_M0_CH4_EIRQ,PSMm channel x error interrupt (m=4*0+0)." "0,1" bitfld.long 0x0 3. "PSM_M0_CH3_EIRQ,PSMm channel x error interrupt (m=4*0+0)." "0,1" newline bitfld.long 0x0 2. "PSM_M0_CH2_EIRQ,PSMm channel x error interrupt (m=4*0+0)." "0,1" bitfld.long 0x0 1. "PSM_M0_CH1_EIRQ,PSMm channel x error interrupt (m=4*0+0)." "0,1" bitfld.long 0x0 0. "PSM_M0_CH0_EIRQ,PSMm channel x error interrupt (m=4*0+0)." "0,1" group.long 0x510++0x3 line.long 0x0 "ICM_IRQG_CLS_0_MEI," bitfld.long 0x0 27. "FIFO_M3_EIRQ,Error interrupt FIFOm_EIRQ (m=4*g+2)." "0,1" bitfld.long 0x0 26. "SPE_M3_EIRQ,Error interrupt SPEm_EIRQ (m=4*g+3)." "0,1" bitfld.long 0x0 25. "MCS_M3_EIRQ,Error interrupt MCSm_EIRQ (m=4*g+3)." "0,1" newline bitfld.long 0x0 24. "TIM_M3_EIRQ,Error interrupt TIMm_EIRQ (m=4*g+3)." "0,1" bitfld.long 0x0 19. "FIFO_M2_EIRQ,Error interrupt FIFOm_EIRQ (m=4*g+2)." "0,1" bitfld.long 0x0 18. "SPE_M2_EIRQ,Error interrupt SPEm_EIRQ (m=4*g+2)." "0,1" newline bitfld.long 0x0 17. "MCS_M2_EIRQ,Error interrupt MCSm_EIRQ (m=4*g+2)." "0,1" bitfld.long 0x0 16. "TIM_M2_EIRQ,Error interrupt TIMm_EIRQ (m=4*g+2)." "0,1" bitfld.long 0x0 11. "FIFO_M1_EIRQ,Error interrupt FIFOm_EIRQ (m=4*g+1)." "0,1" newline bitfld.long 0x0 10. "SPE_M1_EIRQ,Error interrupt SPEm_EIRQ (m=4*g+1)." "0,1" bitfld.long 0x0 9. "MCS_M1_EIRQ,Error interrupt MCSm_EIRQ (m=4*g+1)." "0,1" bitfld.long 0x0 8. "TIM_M1_EIRQ,Error interrupt TIMm_EIRQ (m=4*g+1)." "0,1" newline bitfld.long 0x0 3. "FIFO_M0_EIRQ,Error interrupt FIFOm_EIRQ (m=4*g+0)." "0,1" bitfld.long 0x0 2. "SPE_M0_EIRQ,Error interrupt SPEm_EIRQ (m=4*g+0)." "0,1" bitfld.long 0x0 1. "MCS_M0_EIRQ,Error interrupt MCSm_EIRQ (m=4*g+0)." "0,1" newline bitfld.long 0x0 0. "TIM_M0_EIRQ,Error interrupt TIMm_EIRQ (m=4*g+0)." "0,1" group.long 0x560++0x3 line.long 0x0 "ICM_IRQG_PSM_0_CI," bitfld.long 0x0 23. "PSM_M2_CH7_IRQ,PSMm channel x shared interrupt (m=4*0+2)." "0,1" bitfld.long 0x0 22. "PSM_M2_CH6_IRQ,PSMm channel x shared interrupt (m=4*0+2)." "0,1" bitfld.long 0x0 21. "PSM_M2_CH5_IRQ,PSMm channel x shared interrupt (m=4*0+2)." "0,1" newline bitfld.long 0x0 20. "PSM_M2_CH4_IRQ,PSMm channel x shared interrupt (m=4*0+2)." "0,1" bitfld.long 0x0 19. "PSM_M2_CH3_IRQ,PSMm channel x shared interrupt (m=4*0+2)." "0,1" bitfld.long 0x0 18. "PSM_M2_CH2_IRQ,PSMm channel x shared interrupt (m=4*0+2)." "0,1" newline bitfld.long 0x0 17. "PSM_M2_CH1_IRQ,PSMm channel x shared interrupt (m=4*0+2)." "0,1" bitfld.long 0x0 16. "PSM_M2_CH0_IRQ,PSMm channel x shared interrupt (m=4*0+2)." "0,1" bitfld.long 0x0 15. "PSM_M1_CH7_IRQ,PSMm channel x shared interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 14. "PSM_M1_CH6_IRQ,PSMm channel x shared interrupt (m=4*0+1)." "0,1" bitfld.long 0x0 13. "PSM_M1_CH5_IRQ,PSMm channel x shared interrupt (m=4*0+1)." "0,1" bitfld.long 0x0 12. "PSM_M1_CH4_IRQ,PSMm channel x shared interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 11. "PSM_M1_CH3_IRQ,PSMm channel x shared interrupt (m=4*0+1)." "0,1" bitfld.long 0x0 10. "PSM_M1_CH2_IRQ,PSMm channel x shared interrupt (m=4*0+1)." "0,1" bitfld.long 0x0 9. "PSM_M1_CH1_IRQ,PSMm channel x shared interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 8. "PSM_M1_CH0_IRQ,PSMm channel x shared interrupt (m=4*0+1)." "0,1" bitfld.long 0x0 7. "PSM_M0_CH7_IRQ,PSMm channel x shared interrupt (m=4*0+0)." "0,1" bitfld.long 0x0 6. "PSM_M0_CH6_IRQ,PSMm channel x shared interrupt (m=4*0+0)." "0,1" newline bitfld.long 0x0 5. "PSM_M0_CH5_IRQ,PSMm channel x shared interrupt (m=4*0+0)." "0,1" bitfld.long 0x0 4. "PSM_M0_CH4_IRQ,PSMm channel x shared interrupt (m=4*0+0)." "0,1" bitfld.long 0x0 3. "PSM_M0_CH3_IRQ,PSMm channel x shared interrupt (m=4*0+0)." "0,1" newline bitfld.long 0x0 2. "PSM_M0_CH2_IRQ,PSMm channel x shared interrupt (m=4*0+0)." "0,1" bitfld.long 0x0 1. "PSM_M0_CH1_IRQ,PSMm channel x shared interrupt (m=4*0+0)." "0,1" bitfld.long 0x0 0. "PSM_M0_CH0_IRQ,PSMm channel x shared interrupt (m=4*0+0)." "0,1" group.long 0x590++0x3 line.long 0x0 "ICM_IRQG_ATOM_0_CI," bitfld.long 0x0 31. "ATOM_M3_CH7_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" bitfld.long 0x0 30. "ATOM_M3_CH6_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" bitfld.long 0x0 29. "ATOM_M3_CH5_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x0 28. "ATOM_M3_CH4_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" bitfld.long 0x0 27. "ATOM_M3_CH3_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" bitfld.long 0x0 26. "ATOM_M3_CH2_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x0 25. "ATOM_M3_CH1_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" bitfld.long 0x0 24. "ATOM_M3_CH0_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" bitfld.long 0x0 23. "ATOM_M2_CH7_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x0 22. "ATOM_M2_CH6_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" bitfld.long 0x0 21. "ATOM_M2_CH5_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" bitfld.long 0x0 20. "ATOM_M2_CH4_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x0 19. "ATOM_M2_CH3_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" bitfld.long 0x0 18. "ATOM_M2_CH2_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" bitfld.long 0x0 17. "ATOM_M2_CH1_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x0 16. "ATOM_M2_CH0_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" bitfld.long 0x0 15. "ATOM_M1_CH7_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" bitfld.long 0x0 14. "ATOM_M1_CH6_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x0 13. "ATOM_M1_CH5_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" bitfld.long 0x0 12. "ATOM_M1_CH4_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" bitfld.long 0x0 11. "ATOM_M1_CH3_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x0 10. "ATOM_M1_CH2_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" bitfld.long 0x0 9. "ATOM_M1_CH1_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" bitfld.long 0x0 8. "ATOM_M1_CH0_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x0 7. "ATOM_M0_CH7_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" bitfld.long 0x0 6. "ATOM_M0_CH6_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" bitfld.long 0x0 5. "ATOM_M0_CH5_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x0 4. "ATOM_M0_CH4_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" bitfld.long 0x0 3. "ATOM_M0_CH3_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" bitfld.long 0x0 2. "ATOM_M0_CH2_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x0 1. "ATOM_M0_CH1_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" bitfld.long 0x0 0. "ATOM_M0_CH0_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" group.long 0x5A0++0x3 line.long 0x0 "ICM_IRQG_TOM_0_CI," bitfld.long 0x0 31. "TOM_M1_CH15_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" bitfld.long 0x0 30. "TOM_M1_CH14_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" bitfld.long 0x0 29. "TOM_M1_CH13_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x0 28. "TOM_M1_CH12_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" bitfld.long 0x0 27. "TOM_M1_CH11_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" bitfld.long 0x0 26. "TOM_M1_CH10_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x0 25. "TOM_M1_CH9_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" bitfld.long 0x0 24. "TOM_M1_CH8_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" bitfld.long 0x0 23. "TOM_M1_CH7_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x0 22. "TOM_M1_CH6_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" bitfld.long 0x0 21. "TOM_M1_CH5_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" bitfld.long 0x0 20. "TOM_M1_CH4_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x0 19. "TOM_M1_CH3_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" bitfld.long 0x0 18. "TOM_M1_CH2_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" bitfld.long 0x0 17. "TOM_M1_CH1_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x0 16. "TOM_M1_CH0_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" bitfld.long 0x0 15. "TOM_M0_CH15_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" bitfld.long 0x0 14. "TOM_M0_CH14_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x0 13. "TOM_M0_CH13_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" bitfld.long 0x0 12. "TOM_M0_CH12_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" bitfld.long 0x0 11. "TOM_M0_CH11_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x0 10. "TOM_M0_CH10_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" bitfld.long 0x0 9. "TOM_M0_CH9_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" bitfld.long 0x0 8. "TOM_M0_CH8_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x0 7. "TOM_M0_CH7_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" bitfld.long 0x0 6. "TOM_M0_CH6_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" bitfld.long 0x0 5. "TOM_M0_CH5_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x0 4. "TOM_M0_CH4_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" bitfld.long 0x0 3. "TOM_M0_CH3_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" bitfld.long 0x0 2. "TOM_M0_CH2_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x0 1. "TOM_M0_CH1_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" bitfld.long 0x0 0. "TOM_M0_CH0_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" group.long 0x800++0x3F line.long 0x0 "TIM0_CH0_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM0_CH0_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM0_CH0_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM0_CH0_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM0_CH0_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM0_CH0_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM0_CH0_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM0_CH0_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM0_CH0_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM0_CH0_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM0_CH0_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM0_CH0_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM0_CH0_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM0_CH0_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM0_CH0_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM0_CH0_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x880++0x3F line.long 0x0 "TIM0_CH1_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM0_CH1_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM0_CH1_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM0_CH1_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM0_CH1_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM0_CH1_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM0_CH1_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM0_CH1_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM0_CH1_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM0_CH1_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM0_CH1_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM0_CH1_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM0_CH1_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM0_CH1_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM0_CH1_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM0_CH1_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x900++0x3F line.long 0x0 "TIM0_CH2_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM0_CH2_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM0_CH2_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM0_CH2_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM0_CH2_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM0_CH2_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM0_CH2_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM0_CH2_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM0_CH2_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM0_CH2_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM0_CH2_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM0_CH2_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM0_CH2_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM0_CH2_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM0_CH2_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM0_CH2_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x980++0x3F line.long 0x0 "TIM0_CH3_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM0_CH3_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM0_CH3_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM0_CH3_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM0_CH3_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM0_CH3_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM0_CH3_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM0_CH3_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM0_CH3_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM0_CH3_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM0_CH3_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM0_CH3_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM0_CH3_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM0_CH3_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM0_CH3_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM0_CH3_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xA00++0x3F line.long 0x0 "TIM0_CH4_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM0_CH4_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM0_CH4_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM0_CH4_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM0_CH4_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM0_CH4_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM0_CH4_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM0_CH4_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM0_CH4_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM0_CH4_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM0_CH4_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM0_CH4_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM0_CH4_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM0_CH4_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM0_CH4_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM0_CH4_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xA80++0x3F line.long 0x0 "TIM0_CH5_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM0_CH5_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM0_CH5_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM0_CH5_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM0_CH5_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM0_CH5_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM0_CH5_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM0_CH5_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM0_CH5_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM0_CH5_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM0_CH5_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM0_CH5_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM0_CH5_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM0_CH5_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM0_CH5_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM0_CH5_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xB00++0x3F line.long 0x0 "TIM0_CH6_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM0_CH6_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM0_CH6_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM0_CH6_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM0_CH6_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM0_CH6_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM0_CH6_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM0_CH6_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM0_CH6_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM0_CH6_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM0_CH6_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM0_CH6_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM0_CH6_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM0_CH6_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM0_CH6_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM0_CH6_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xB80++0x3F line.long 0x0 "TIM0_CH7_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM0_CH7_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM0_CH7_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM0_CH7_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM0_CH7_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM0_CH7_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM0_CH7_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM0_CH7_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM0_CH7_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM0_CH7_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM0_CH7_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM0_CH7_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM0_CH7_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM0_CH7_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM0_CH7_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM0_CH7_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xC00++0xB line.long 0x0 "TIM0_INP_VAL," bitfld.long 0x0 23. "TIM_IN7,Signal channel x after TIM input signal synchronization" "0,1" bitfld.long 0x0 22. "TIM_IN6,Signal channel x after TIM input signal synchronization" "0,1" bitfld.long 0x0 21. "TIM_IN5,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 20. "TIM_IN4,Signal channel x after TIM input signal synchronization" "0,1" bitfld.long 0x0 19. "TIM_IN3,Signal channel x after TIM input signal synchronization" "0,1" bitfld.long 0x0 18. "TIM_IN2,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 17. "TIM_IN1,Signal channel x after TIM input signal synchronization" "0,1" bitfld.long 0x0 16. "TIM_IN0,Signal channel x after TIM input signal synchronization" "0,1" bitfld.long 0x0 15. "F_IN7,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 14. "F_IN6,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" bitfld.long 0x0 13. "F_IN5,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" bitfld.long 0x0 12. "F_IN4,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 11. "F_IN3,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" bitfld.long 0x0 10. "F_IN2,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" bitfld.long 0x0 9. "F_IN1,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 8. "F_IN0,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" bitfld.long 0x0 7. "F_OUT7,Signal channel x after TIM FLT unit" "0,1" bitfld.long 0x0 6. "F_OUT6,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 5. "F_OUT5,Signal channel x after TIM FLT unit" "0,1" bitfld.long 0x0 4. "F_OUT4,Signal channel x after TIM FLT unit" "0,1" bitfld.long 0x0 3. "F_OUT3,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 2. "F_OUT2,Signal channel x after TIM FLT unit" "0,1" bitfld.long 0x0 1. "F_OUT1,Signal channel x after TIM FLT unit" "0,1" bitfld.long 0x0 0. "F_OUT0,Signal channel x after TIM FLT unit" "0,1" line.long 0x4 "TIM0_IN_SRC," bitfld.long 0x4 30.--31. "MODE_7,Input source to Channel x" "0,1,2,3" bitfld.long 0x4 28.--29. "VAL_7,Value to be fed to channel [x]" "0,1,2,3" bitfld.long 0x4 26.--27. "MODE_6,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 24.--25. "VAL_6,Value to be fed to channel [x]" "0,1,2,3" bitfld.long 0x4 22.--23. "MODE_5,Input source to Channel x" "0,1,2,3" bitfld.long 0x4 20.--21. "VAL_5,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 18.--19. "MODE_4,Input source to Channel x" "0,1,2,3" bitfld.long 0x4 16.--17. "VAL_4,Value to be fed to channel [x]" "0,1,2,3" bitfld.long 0x4 14.--15. "MODE_3,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 12.--13. "VAL_3,Value to be fed to channel [x]" "0,1,2,3" bitfld.long 0x4 10.--11. "MODE_2,Input source to Channel x" "0,1,2,3" bitfld.long 0x4 8.--9. "VAL_2,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 6.--7. "MODE_1,Input source to Channel x" "0,1,2,3" bitfld.long 0x4 4.--5. "VAL_1,Value to be fed to channel [x]" "0,1,2,3" bitfld.long 0x4 2.--3. "MODE_0,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 0.--1. "VAL_0,Value to be fed to channel [x]" "0,1,2,3" line.long 0x8 "TIM0_RST," bitfld.long 0x8 7. "RST_CH7,Software reset of channel [x]" "0,1" bitfld.long 0x8 6. "RST_CH6,Software reset of channel [x]" "0,1" bitfld.long 0x8 5. "RST_CH5,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 4. "RST_CH4,Software reset of channel [x]" "0,1" bitfld.long 0x8 3. "RST_CH3,Software reset of channel [x]" "0,1" bitfld.long 0x8 2. "RST_CH2,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 1. "RST_CH1,Software reset of channel [x]" "0,1" bitfld.long 0x8 0. "RST_CH0,Software reset of channel [x]" "0,1" group.long 0x1000++0x2B line.long 0x0 "TOM0_CH0_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH0_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH0_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH0_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH0_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH0_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH0_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH0_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH0_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH0_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH0_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1030++0x3 line.long 0x0 "TOM0_CH0_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1040++0x2B line.long 0x0 "TOM0_CH1_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH1_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH1_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH1_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH1_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH1_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH1_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH1_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH1_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH1_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH1_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1070++0x3 line.long 0x0 "TOM0_CH1_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1080++0x2B line.long 0x0 "TOM0_CH2_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH2_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH2_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH2_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH2_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH2_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH2_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH2_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH2_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH2_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH2_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x10B0++0x3 line.long 0x0 "TOM0_CH2_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x10C0++0x2B line.long 0x0 "TOM0_CH3_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH3_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH3_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH3_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH3_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH3_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH3_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH3_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH3_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH3_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH3_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x10F0++0x3 line.long 0x0 "TOM0_CH3_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1100++0x2B line.long 0x0 "TOM0_CH4_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH4_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH4_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH4_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH4_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH4_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH4_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH4_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH4_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH4_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH4_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1130++0x3 line.long 0x0 "TOM0_CH4_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1140++0x2B line.long 0x0 "TOM0_CH5_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH5_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH5_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH5_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH5_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH5_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH5_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH5_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH5_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH5_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH5_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1170++0x3 line.long 0x0 "TOM0_CH5_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1180++0x2B line.long 0x0 "TOM0_CH6_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH6_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH6_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH6_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH6_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH6_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH6_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH6_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH6_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH6_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH6_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x11B0++0x3 line.long 0x0 "TOM0_CH6_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x11C0++0x2B line.long 0x0 "TOM0_CH7_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH7_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH7_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH7_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH7_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH7_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH7_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH7_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH7_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH7_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH7_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x11F0++0x3 line.long 0x0 "TOM0_CH7_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1200++0x2B line.long 0x0 "TOM0_CH8_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH8_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH8_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH8_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH8_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH8_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH8_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH8_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH8_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH8_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH8_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1230++0x3 line.long 0x0 "TOM0_CH8_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1240++0x2B line.long 0x0 "TOM0_CH9_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH9_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH9_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH9_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH9_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH9_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH9_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH9_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH9_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH9_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH9_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1270++0x3 line.long 0x0 "TOM0_CH9_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1280++0x2B line.long 0x0 "TOM0_CH10_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH10_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH10_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH10_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH10_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH10_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH10_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH10_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH10_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH10_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH10_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x12B0++0x3 line.long 0x0 "TOM0_CH10_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x12C0++0x2B line.long 0x0 "TOM0_CH11_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH11_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH11_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH11_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH11_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH11_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH11_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH11_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH11_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH11_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH11_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x12F0++0x3 line.long 0x0 "TOM0_CH11_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1300++0x2B line.long 0x0 "TOM0_CH12_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH12_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH12_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH12_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH12_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH12_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH12_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH12_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH12_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH12_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH12_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1330++0x3 line.long 0x0 "TOM0_CH12_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1340++0x2B line.long 0x0 "TOM0_CH13_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH13_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH13_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH13_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH13_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH13_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH13_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH13_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH13_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH13_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH13_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1370++0x3 line.long 0x0 "TOM0_CH13_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1380++0x2B line.long 0x0 "TOM0_CH14_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH14_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH14_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH14_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH14_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH14_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH14_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH14_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH14_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH14_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH14_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x13B0++0x3 line.long 0x0 "TOM0_CH14_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x13C0++0x2B line.long 0x0 "TOM0_CH15_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH15_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH15_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH15_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH15_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH15_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH15_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH15_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH15_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH15_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH15_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x13F0++0x3 line.long 0x0 "TOM0_CH15_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1430++0xF line.long 0x0 "TOM0_TGC0_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 28.--29. "UPEN_CTRL6,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 26.--27. "UPEN_CTRL5,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 24.--25. "UPEN_CTRL4,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 22.--23. "UPEN_CTRL3,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 20.--21. "UPEN_CTRL2,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 16.--17. "UPEN_CTRL0,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 15. "RST_CH7,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 14. "RST_CH6,Software reset of channel x = c + g*8" "0,1" bitfld.long 0x0 13. "RST_CH5,Software reset of channel x = c + g*8" "0,1" bitfld.long 0x0 12. "RST_CH4,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel x = c + g*8" "0,1" bitfld.long 0x0 10. "RST_CH2,Software reset of channel x = c + g*8" "0,1" bitfld.long 0x0 9. "RST_CH1,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 8. "RST_CH0,Software reset of channel x = c + g*8" "0,1" bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see TGC0 TGC1) to update the register TOM[i]_TGC[g]_ENDIS_STAT and TOM[i]_TGC[g]_OUTEN_STAT" "0,1" line.long 0x4 "TOM0_TGC0_ACT_TB," bitfld.long 0x4 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" bitfld.long 0x4 24. "TB_TRIG,Set trigger request" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[y] y=0..2. If selected TBU_TS[y] value is in the interval [TOM[i]_TGC[g]_ACT_TB.ACT_TB-007FFFFFh TOM[i]_TGC[g]_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x8 "TOM0_TGC0_FUPD_CTRL," bitfld.long 0x8 30.--31. "RSTCN0_CH7,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" bitfld.long 0x8 28.--29. "RSTCN0_CH6,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" bitfld.long 0x8 26.--27. "RSTCN0_CH5,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 24.--25. "RSTCN0_CH4,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" bitfld.long 0x8 22.--23. "RSTCN0_CH3,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" bitfld.long 0x8 20.--21. "RSTCN0_CH2,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 18.--19. "RSTCN0_CH1,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" bitfld.long 0x8 16.--17. "RSTCN0_CH0,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" bitfld.long 0x8 14.--15. "FUPD_CTRL7,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 12.--13. "FUPD_CTRL6,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" bitfld.long 0x8 10.--11. "FUPD_CTRL5,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" bitfld.long 0x8 8.--9. "FUPD_CTRL4,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 6.--7. "FUPD_CTRL3,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" bitfld.long 0x8 4.--5. "FUPD_CTRL2,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" bitfld.long 0x8 2.--3. "FUPD_CTRL1,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 0.--1. "FUPD_CTRL0,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" line.long 0xC "TOM0_TGC0_INT_TRIG," bitfld.long 0xC 14.--15. "INT_TRIG7,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" bitfld.long 0xC 12.--13. "INT_TRIG6,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" bitfld.long 0xC 10.--11. "INT_TRIG5,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "INT_TRIG4,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" bitfld.long 0xC 6.--7. "INT_TRIG3,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" bitfld.long 0xC 4.--5. "INT_TRIG2,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "INT_TRIG1,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" bitfld.long 0xC 0.--1. "INT_TRIG0,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" group.long 0x1470++0xF line.long 0x0 "TOM0_TGC0_ENDIS_CTRL," bitfld.long 0x0 14.--15. "ENDIS_CTRL7,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" bitfld.long 0x0 12.--13. "ENDIS_CTRL6,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" bitfld.long 0x0 10.--11. "ENDIS_CTRL5,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 8.--9. "ENDIS_CTRL4,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" bitfld.long 0x0 6.--7. "ENDIS_CTRL3,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" bitfld.long 0x0 4.--5. "ENDIS_CTRL2,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 2.--3. "ENDIS_CTRL1,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" bitfld.long 0x0 0.--1. "ENDIS_CTRL0,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" line.long 0x4 "TOM0_TGC0_ENDIS_STAT," bitfld.long 0x4 14.--15. "ENDIS_STAT7,TOM channel x=c + g*8 enable/disable" "0,1,2,3" bitfld.long 0x4 12.--13. "ENDIS_STAT6,TOM channel x=c + g*8 enable/disable" "0,1,2,3" bitfld.long 0x4 10.--11. "ENDIS_STAT5,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 8.--9. "ENDIS_STAT4,TOM channel x=c + g*8 enable/disable" "0,1,2,3" bitfld.long 0x4 6.--7. "ENDIS_STAT3,TOM channel x=c + g*8 enable/disable" "0,1,2,3" bitfld.long 0x4 4.--5. "ENDIS_STAT2,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_STAT1,TOM channel x=c + g*8 enable/disable" "0,1,2,3" bitfld.long 0x4 0.--1. "ENDIS_STAT0,TOM channel x=c + g*8 enable/disable" "0,1,2,3" line.long 0x8 "TOM0_TGC0_OUTEN_CTRL," bitfld.long 0x8 14.--15. "OUTEN_CTRL7,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" bitfld.long 0x8 12.--13. "OUTEN_CTRL6,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" bitfld.long 0x8 10.--11. "OUTEN_CTRL5,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 8.--9. "OUTEN_CTRL4,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" bitfld.long 0x8 6.--7. "OUTEN_CTRL3,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" bitfld.long 0x8 4.--5. "OUTEN_CTRL2,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OUTEN_CTRL1,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" bitfld.long 0x8 0.--1. "OUTEN_CTRL0,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" line.long 0xC "TOM0_TGC0_OUTEN_STAT," bitfld.long 0xC 14.--15. "OUTEN_STAT7,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" bitfld.long 0xC 12.--13. "OUTEN_STAT6,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" bitfld.long 0xC 10.--11. "OUTEN_STAT5,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "OUTEN_STAT4,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" bitfld.long 0xC 6.--7. "OUTEN_STAT3,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" bitfld.long 0xC 4.--5. "OUTEN_STAT2,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "OUTEN_STAT1,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" bitfld.long 0xC 0.--1. "OUTEN_STAT0,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" group.long 0x14B0++0xF line.long 0x0 "TOM0_TGC1_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 28.--29. "UPEN_CTRL6,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 26.--27. "UPEN_CTRL5,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 24.--25. "UPEN_CTRL4,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 22.--23. "UPEN_CTRL3,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 20.--21. "UPEN_CTRL2,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 16.--17. "UPEN_CTRL0,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 15. "RST_CH7,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 14. "RST_CH6,Software reset of channel x = c + g*8" "0,1" bitfld.long 0x0 13. "RST_CH5,Software reset of channel x = c + g*8" "0,1" bitfld.long 0x0 12. "RST_CH4,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel x = c + g*8" "0,1" bitfld.long 0x0 10. "RST_CH2,Software reset of channel x = c + g*8" "0,1" bitfld.long 0x0 9. "RST_CH1,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 8. "RST_CH0,Software reset of channel x = c + g*8" "0,1" bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see TGC0 TGC1) to update the register TOM[i]_TGC[g]_ENDIS_STAT and TOM[i]_TGC[g]_OUTEN_STAT" "0,1" line.long 0x4 "TOM0_TGC1_ACT_TB," bitfld.long 0x4 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" bitfld.long 0x4 24. "TB_TRIG,Set trigger request" "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[y] y=0..2. If selected TBU_TS[y] value is in the interval [TOM[i]_TGC[g]_ACT_TB.ACT_TB-007FFFFFh TOM[i]_TGC[g]_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x8 "TOM0_TGC1_FUPD_CTRL," bitfld.long 0x8 30.--31. "RSTCN0_CH7,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" bitfld.long 0x8 28.--29. "RSTCN0_CH6,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" bitfld.long 0x8 26.--27. "RSTCN0_CH5,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 24.--25. "RSTCN0_CH4,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" bitfld.long 0x8 22.--23. "RSTCN0_CH3,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" bitfld.long 0x8 20.--21. "RSTCN0_CH2,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 18.--19. "RSTCN0_CH1,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" bitfld.long 0x8 16.--17. "RSTCN0_CH0,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" bitfld.long 0x8 14.--15. "FUPD_CTRL7,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 12.--13. "FUPD_CTRL6,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" bitfld.long 0x8 10.--11. "FUPD_CTRL5,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" bitfld.long 0x8 8.--9. "FUPD_CTRL4,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 6.--7. "FUPD_CTRL3,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" bitfld.long 0x8 4.--5. "FUPD_CTRL2,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" bitfld.long 0x8 2.--3. "FUPD_CTRL1,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 0.--1. "FUPD_CTRL0,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" line.long 0xC "TOM0_TGC1_INT_TRIG," bitfld.long 0xC 14.--15. "INT_TRIG7,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" bitfld.long 0xC 12.--13. "INT_TRIG6,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" bitfld.long 0xC 10.--11. "INT_TRIG5,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "INT_TRIG4,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" bitfld.long 0xC 6.--7. "INT_TRIG3,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" bitfld.long 0xC 4.--5. "INT_TRIG2,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "INT_TRIG1,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" bitfld.long 0xC 0.--1. "INT_TRIG0,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" group.long 0x14F0++0xF line.long 0x0 "TOM0_TGC1_ENDIS_CTRL," bitfld.long 0x0 14.--15. "ENDIS_CTRL7,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" bitfld.long 0x0 12.--13. "ENDIS_CTRL6,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" bitfld.long 0x0 10.--11. "ENDIS_CTRL5,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 8.--9. "ENDIS_CTRL4,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" bitfld.long 0x0 6.--7. "ENDIS_CTRL3,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" bitfld.long 0x0 4.--5. "ENDIS_CTRL2,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 2.--3. "ENDIS_CTRL1,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" bitfld.long 0x0 0.--1. "ENDIS_CTRL0,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" line.long 0x4 "TOM0_TGC1_ENDIS_STAT," bitfld.long 0x4 14.--15. "ENDIS_STAT7,TOM channel x=c + g*8 enable/disable" "0,1,2,3" bitfld.long 0x4 12.--13. "ENDIS_STAT6,TOM channel x=c + g*8 enable/disable" "0,1,2,3" bitfld.long 0x4 10.--11. "ENDIS_STAT5,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 8.--9. "ENDIS_STAT4,TOM channel x=c + g*8 enable/disable" "0,1,2,3" bitfld.long 0x4 6.--7. "ENDIS_STAT3,TOM channel x=c + g*8 enable/disable" "0,1,2,3" bitfld.long 0x4 4.--5. "ENDIS_STAT2,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_STAT1,TOM channel x=c + g*8 enable/disable" "0,1,2,3" bitfld.long 0x4 0.--1. "ENDIS_STAT0,TOM channel x=c + g*8 enable/disable" "0,1,2,3" line.long 0x8 "TOM0_TGC1_OUTEN_CTRL," bitfld.long 0x8 14.--15. "OUTEN_CTRL7,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" bitfld.long 0x8 12.--13. "OUTEN_CTRL6,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" bitfld.long 0x8 10.--11. "OUTEN_CTRL5,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 8.--9. "OUTEN_CTRL4,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" bitfld.long 0x8 6.--7. "OUTEN_CTRL3,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" bitfld.long 0x8 4.--5. "OUTEN_CTRL2,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OUTEN_CTRL1,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" bitfld.long 0x8 0.--1. "OUTEN_CTRL0,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" line.long 0xC "TOM0_TGC1_OUTEN_STAT," bitfld.long 0xC 14.--15. "OUTEN_STAT7,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" bitfld.long 0xC 12.--13. "OUTEN_STAT6,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" bitfld.long 0xC 10.--11. "OUTEN_STAT5,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "OUTEN_STAT4,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" bitfld.long 0xC 6.--7. "OUTEN_STAT3,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" bitfld.long 0xC 4.--5. "OUTEN_STAT2,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "OUTEN_STAT1,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" bitfld.long 0xC 0.--1. "OUTEN_STAT0,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" group.long 0x1800++0x2F line.long 0x0 "ATOM0_CH0_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM0_CH0_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM0_CH0_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM0_CH0_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM0_CH0_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM0_CH0_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM0_CH0_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM0_CH0_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM0_CH0_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM0_CH0_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM0_CH0_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM0_CH0_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1834++0x3 line.long 0x0 "ATOM0_CH0_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1880++0x2F line.long 0x0 "ATOM0_CH1_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM0_CH1_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM0_CH1_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM0_CH1_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM0_CH1_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM0_CH1_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM0_CH1_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM0_CH1_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM0_CH1_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM0_CH1_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM0_CH1_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM0_CH1_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x18B4++0x3 line.long 0x0 "ATOM0_CH1_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1900++0x2F line.long 0x0 "ATOM0_CH2_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM0_CH2_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM0_CH2_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM0_CH2_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM0_CH2_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM0_CH2_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM0_CH2_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM0_CH2_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM0_CH2_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM0_CH2_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM0_CH2_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM0_CH2_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1934++0x3 line.long 0x0 "ATOM0_CH2_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1980++0x2F line.long 0x0 "ATOM0_CH3_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM0_CH3_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM0_CH3_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM0_CH3_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM0_CH3_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM0_CH3_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM0_CH3_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM0_CH3_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM0_CH3_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM0_CH3_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM0_CH3_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM0_CH3_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x19B4++0x3 line.long 0x0 "ATOM0_CH3_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A00++0x2F line.long 0x0 "ATOM0_CH4_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM0_CH4_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM0_CH4_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM0_CH4_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM0_CH4_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM0_CH4_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM0_CH4_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM0_CH4_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM0_CH4_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM0_CH4_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM0_CH4_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM0_CH4_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1A34++0x3 line.long 0x0 "ATOM0_CH4_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A80++0x2F line.long 0x0 "ATOM0_CH5_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM0_CH5_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM0_CH5_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM0_CH5_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM0_CH5_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM0_CH5_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM0_CH5_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM0_CH5_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM0_CH5_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM0_CH5_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM0_CH5_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM0_CH5_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1AB4++0x3 line.long 0x0 "ATOM0_CH5_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B00++0x2F line.long 0x0 "ATOM0_CH6_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM0_CH6_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM0_CH6_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM0_CH6_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM0_CH6_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM0_CH6_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM0_CH6_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM0_CH6_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM0_CH6_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM0_CH6_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM0_CH6_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM0_CH6_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1B34++0x3 line.long 0x0 "ATOM0_CH6_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B80++0x2F line.long 0x0 "ATOM0_CH7_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM0_CH7_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM0_CH7_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM0_CH7_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM0_CH7_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM0_CH7_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM0_CH7_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM0_CH7_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM0_CH7_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM0_CH7_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM0_CH7_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM0_CH7_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1BB4++0x3 line.long 0x0 "ATOM0_CH7_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1C40++0x1F line.long 0x0 "ATOM0_AGC_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 28.--29. "UPEN_CTRL6,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 26.--27. "UPEN_CTRL5,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 24.--25. "UPEN_CTRL4,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 22.--23. "UPEN_CTRL3,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 20.--21. "UPEN_CTRL2,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 16.--17. "UPEN_CTRL0,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 15. "RST_CH7,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 14. "RST_CH6,Software reset of channel [k]" "0,1" bitfld.long 0x0 13. "RST_CH5,Software reset of channel [k]" "0,1" bitfld.long 0x0 12. "RST_CH4,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel [k]" "0,1" bitfld.long 0x0 10. "RST_CH2,Software reset of channel [k]" "0,1" bitfld.long 0x0 9. "RST_CH1,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 8. "RST_CH0,Software reset of channel [k]" "0,1" bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see AGC) to update the register ATOM[i]_AGC_ENDIS_STAT and ATOM[i]_AGC_OUTEN_STAT" "0,1" line.long 0x4 "ATOM0_AGC_ENDIS_CTRL," bitfld.long 0x4 14.--15. "ENDIS_CTRL7,ATOM channel [k] enable/disable update value." "0,1,2,3" bitfld.long 0x4 12.--13. "ENDIS_CTRL6,ATOM channel [k] enable/disable update value." "0,1,2,3" bitfld.long 0x4 10.--11. "ENDIS_CTRL5,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 8.--9. "ENDIS_CTRL4,ATOM channel [k] enable/disable update value." "0,1,2,3" bitfld.long 0x4 6.--7. "ENDIS_CTRL3,ATOM channel [k] enable/disable update value." "0,1,2,3" bitfld.long 0x4 4.--5. "ENDIS_CTRL2,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_CTRL1,ATOM channel [k] enable/disable update value." "0,1,2,3" bitfld.long 0x4 0.--1. "ENDIS_CTRL0,ATOM channel [k] enable/disable update value." "0,1,2,3" line.long 0x8 "ATOM0_AGC_ENDIS_STAT," bitfld.long 0x8 14.--15. "ENDIS_STAT7,ATOM channel [k] enable/disable" "0,1,2,3" bitfld.long 0x8 12.--13. "ENDIS_STAT6,ATOM channel [k] enable/disable" "0,1,2,3" bitfld.long 0x8 10.--11. "ENDIS_STAT5,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 8.--9. "ENDIS_STAT4,ATOM channel [k] enable/disable" "0,1,2,3" bitfld.long 0x8 6.--7. "ENDIS_STAT3,ATOM channel [k] enable/disable" "0,1,2,3" bitfld.long 0x8 4.--5. "ENDIS_STAT2,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 2.--3. "ENDIS_STAT1,ATOM channel [k] enable/disable" "0,1,2,3" bitfld.long 0x8 0.--1. "ENDIS_STAT0,ATOM channel [k] enable/disable" "0,1,2,3" line.long 0xC "ATOM0_AGC_ACT_TB," bitfld.long 0xC 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" bitfld.long 0xC 24. "TB_TRIG,Set trigger request" "0,1" hexmask.long.tbyte 0xC 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[x] x=0..2. If selected TBU_TS[x] value is in the interval [ATOM[i]_AGC_ACT_TB.ACT_TB-007FFFFFh ATOM[i]_AGC_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x10 "ATOM0_AGC_OUTEN_CTRL," bitfld.long 0x10 14.--15. "OUTEN_CTRL7,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" bitfld.long 0x10 12.--13. "OUTEN_CTRL6,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" bitfld.long 0x10 10.--11. "OUTEN_CTRL5,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 8.--9. "OUTEN_CTRL4,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" bitfld.long 0x10 6.--7. "OUTEN_CTRL3,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" bitfld.long 0x10 4.--5. "OUTEN_CTRL2,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 2.--3. "OUTEN_CTRL1,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" bitfld.long 0x10 0.--1. "OUTEN_CTRL0,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" line.long 0x14 "ATOM0_AGC_OUTEN_STAT," bitfld.long 0x14 14.--15. "OUTEN_STAT7,Control/status of output ATOM_OUT [k]" "0,1,2,3" bitfld.long 0x14 12.--13. "OUTEN_STAT6,Control/status of output ATOM_OUT [k]" "0,1,2,3" bitfld.long 0x14 10.--11. "OUTEN_STAT5,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 8.--9. "OUTEN_STAT4,Control/status of output ATOM_OUT [k]" "0,1,2,3" bitfld.long 0x14 6.--7. "OUTEN_STAT3,Control/status of output ATOM_OUT [k]" "0,1,2,3" bitfld.long 0x14 4.--5. "OUTEN_STAT2,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 2.--3. "OUTEN_STAT1,Control/status of output ATOM_OUT [k]" "0,1,2,3" bitfld.long 0x14 0.--1. "OUTEN_STAT0,Control/status of output ATOM_OUT [k]" "0,1,2,3" line.long 0x18 "ATOM0_AGC_FUPD_CTRL," bitfld.long 0x18 30.--31. "RSTCN0_CH7,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" bitfld.long 0x18 28.--29. "RSTCN0_CH6,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" bitfld.long 0x18 26.--27. "RSTCN0_CH5,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 24.--25. "RSTCN0_CH4,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" bitfld.long 0x18 22.--23. "RSTCN0_CH3,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" bitfld.long 0x18 20.--21. "RSTCN0_CH2,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 18.--19. "RSTCN0_CH1,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" bitfld.long 0x18 16.--17. "RSTCN0_CH0,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" bitfld.long 0x18 14.--15. "FUPD_CTRL7,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 12.--13. "FUPD_CTRL6,Force update of ATOM channel [k] operation registers" "0,1,2,3" bitfld.long 0x18 10.--11. "FUPD_CTRL5,Force update of ATOM channel [k] operation registers" "0,1,2,3" bitfld.long 0x18 8.--9. "FUPD_CTRL4,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 6.--7. "FUPD_CTRL3,Force update of ATOM channel [k] operation registers" "0,1,2,3" bitfld.long 0x18 4.--5. "FUPD_CTRL2,Force update of ATOM channel [k] operation registers" "0,1,2,3" bitfld.long 0x18 2.--3. "FUPD_CTRL1,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 0.--1. "FUPD_CTRL0,Force update of ATOM channel [k] operation registers" "0,1,2,3" line.long 0x1C "ATOM0_AGC_INT_TRIG," bitfld.long 0x1C 14.--15. "INT_TRIG7,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" bitfld.long 0x1C 12.--13. "INT_TRIG6,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" bitfld.long 0x1C 10.--11. "INT_TRIG5,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 8.--9. "INT_TRIG4,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" bitfld.long 0x1C 6.--7. "INT_TRIG3,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" bitfld.long 0x1C 4.--5. "INT_TRIG2,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 2.--3. "INT_TRIG1,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" bitfld.long 0x1C 0.--1. "INT_TRIG0,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" group.long 0x41D4++0x3 line.long 0x0 "CCM0_HW_CONF2," bitfld.long 0x0 18. "AXIM_DATA_SIZE,Defines the data bus width of the AXI master interface" "0,1" bitfld.long 0x0 16. "AXIS_DATA_SIZE,Defines the data bus width of the AXI slave interface" "0,1" bitfld.long 0x0 9. "TIO_OUT_RST,TIO_OUT reset level" "0,1" newline bitfld.long 0x0 7. "AXIM_POSTED_WRITE,Write transaction without response" "0,1" bitfld.long 0x0 6. "AXIM_SEC_ACC,Secure AXI master access constant" "0,1" bitfld.long 0x0 5. "AXIM_PRIV_ACC,Privileged AXI master access constant" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "AXIM_ID_WIDTH,Defines which LSB of AXIM_ID are send to the bus" group.long 0x41DC++0x7 line.long 0x0 "CCM0_HW_CONF," bitfld.long 0x0 31. "AEI_RDATA_PIPELINE_STAGE,Read data pipeline stage implemented" "0,1" bitfld.long 0x0 30. "AEI_ADDR_PIPELINE_STAGE,Address pipeline stage implemented" "0,1" bitfld.long 0x0 29. "INT_CLK_EN_GEN,Internal clock enable generation" "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "TOM_TRIG_INTCHAIN,TOM internal trigger chain length without synchronization register" hexmask.long.byte 0x0 20.--23. 1. "ATOM_TRIG_INTCHAIN,ATOM internal trigger chain length without synchronization register" bitfld.long 0x0 19. "IRQ_MODE_SINGLE_PULSE,Signalize availability of Single Pulse IRQ mode" "0,1" newline bitfld.long 0x0 18. "IRQ_MODE_PULSE_NOTIFY,Signalize availability of Pulse Notoify IRQ mode" "0,1" bitfld.long 0x0 17. "IRQ_MODE_PULSE,Signalize availability of Pulse IRQ mode" "0,1" bitfld.long 0x0 16. "IRQ_MODE_LEVEL,Signalize availability of Level IRQ mode" "0,1" newline bitfld.long 0x0 15. "RESET_ACTIVE,Active level of asynchronous reset" "0,1" bitfld.long 0x0 13. "ERM,Enable RAM1 MSB for available MCS modules" "0,1" bitfld.long 0x0 12. "RAM_INIT_RST,RAM initialization from reset" "0,1" newline bitfld.long 0x0 9.--11. "TOM_TRIG_CHAIN,TOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "TOM_OUT_RST,TOM_OUT reset level" "0,1" bitfld.long 0x0 5.--7. "ATOM_TRIG_CHAIN,ATOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "ATOM_OUT_RST,ATOM_OUT reset level" "0,1" bitfld.long 0x0 3. "CFG_CLOCK_RATE,Clocks per ARU transfer" "0,1" bitfld.long 0x0 2. "SYNC_INPUT_REG,Additional pipelined stage in synchronous bridge mode" "0,1" newline bitfld.long 0x0 1. "BRIDGE_MODE_RST,Bridge mode after reset" "0,1" bitfld.long 0x0 0. "GRSTEN,Global Reset Enable" "0,1" line.long 0x4 "CCM0_TIM_AUX_IN_SRC," bitfld.long 0x4 23. "SEL_OUT_N_CH7,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" bitfld.long 0x4 22. "SEL_OUT_N_CH6,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" bitfld.long 0x4 21. "SEL_OUT_N_CH5,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0x4 20. "SEL_OUT_N_CH4,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" bitfld.long 0x4 19. "SEL_OUT_N_CH3,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" bitfld.long 0x4 18. "SEL_OUT_N_CH2,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0x4 17. "SEL_OUT_N_CH1,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" bitfld.long 0x4 16. "SEL_OUT_N_CH0,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" bitfld.long 0x4 7. "SRC_CH7,Defines AUX_IN source of TIM[i] channel 7" "0,1" newline bitfld.long 0x4 6. "SRC_CH6,Defines AUX_IN source of TIM[i] channel 6" "0,1" bitfld.long 0x4 5. "SRC_CH5,Defines AUX_IN source of TIM[i] channel 5" "0,1" bitfld.long 0x4 4. "SRC_CH4,Defines AUX_IN source of TIM[i] channel 4" "0,1" newline bitfld.long 0x4 3. "SRC_CH3,Defines AUX_IN source of TIM[i] channel 3" "0,1" bitfld.long 0x4 2. "SRC_CH2,Defines AUX_IN source of TIM[i] channel 2" "0,1" bitfld.long 0x4 1. "SRC_CH1,Defines AUX_IN source of TIM[i] channel 1" "0,1" newline bitfld.long 0x4 0. "SRC_CH0,Defines AUX_IN source of TIM[i] channel 0" "0,1" group.long 0x41E8++0x17 line.long 0x0 "CCM0_TOM_OUT," bitfld.long 0x0 31. "TOM_OUT_N15,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 30. "TOM_OUT_N14,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 29. "TOM_OUT_N13,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 28. "TOM_OUT_N12,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 27. "TOM_OUT_N11,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 26. "TOM_OUT_N10,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 25. "TOM_OUT_N9,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 24. "TOM_OUT_N8,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 23. "TOM_OUT_N7,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 22. "TOM_OUT_N6,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 21. "TOM_OUT_N5,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 20. "TOM_OUT_N4,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 19. "TOM_OUT_N3,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 18. "TOM_OUT_N2,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 17. "TOM_OUT_N1,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 16. "TOM_OUT_N0,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 15. "TOM_OUT15,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 14. "TOM_OUT14,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 13. "TOM_OUT13,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 12. "TOM_OUT12,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 11. "TOM_OUT11,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 10. "TOM_OUT10,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 9. "TOM_OUT9,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 8. "TOM_OUT8,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 7. "TOM_OUT7,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 6. "TOM_OUT6,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 5. "TOM_OUT5,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 4. "TOM_OUT4,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 3. "TOM_OUT3,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 2. "TOM_OUT2,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 1. "TOM_OUT1,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 0. "TOM_OUT0,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" line.long 0x4 "CCM0_ATOM_OUT," bitfld.long 0x4 31. "ATOM_IP1_OUT_N7,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" bitfld.long 0x4 30. "ATOM_IP1_OUT_N6,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" bitfld.long 0x4 29. "ATOM_IP1_OUT_N5,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x4 28. "ATOM_IP1_OUT_N4,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" bitfld.long 0x4 27. "ATOM_IP1_OUT_N3,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" bitfld.long 0x4 26. "ATOM_IP1_OUT_N2,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x4 25. "ATOM_IP1_OUT_N1,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" bitfld.long 0x4 24. "ATOM_IP1_OUT_N0,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" bitfld.long 0x4 23. "ATOM_IP1_OUT7,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x4 22. "ATOM_IP1_OUT6,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" bitfld.long 0x4 21. "ATOM_IP1_OUT5,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" bitfld.long 0x4 20. "ATOM_IP1_OUT4,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x4 19. "ATOM_IP1_OUT3,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" bitfld.long 0x4 18. "ATOM_IP1_OUT2,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" bitfld.long 0x4 17. "ATOM_IP1_OUT1,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x4 16. "ATOM_IP1_OUT0,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" bitfld.long 0x4 15. "ATOM_I_OUT_N7,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x4 14. "ATOM_I_OUT_N6,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x4 13. "ATOM_I_OUT_N5,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x4 12. "ATOM_I_OUT_N4,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x4 11. "ATOM_I_OUT_N3,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x4 10. "ATOM_I_OUT_N2,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x4 9. "ATOM_I_OUT_N1,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x4 8. "ATOM_I_OUT_N0,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x4 7. "ATOM_I_OUT7,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" bitfld.long 0x4 6. "ATOM_I_OUT6,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" bitfld.long 0x4 5. "ATOM_I_OUT5,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x4 4. "ATOM_I_OUT4,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" bitfld.long 0x4 3. "ATOM_I_OUT3,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" bitfld.long 0x4 2. "ATOM_I_OUT2,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x4 1. "ATOM_I_OUT1,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" bitfld.long 0x4 0. "ATOM_I_OUT0,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" line.long 0x8 "CCM0_CMU_CLK_CFG," bitfld.long 0x8 28.--29. "CLK7_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x8 24.--25. "CLK6_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x8 20.--21. "CLK5_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x8 16.--17. "CLK4_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x8 12.--13. "CLK3_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x8 8.--9. "CLK2_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x8 4.--5. "CLK1_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x8 0.--1. "CLK0_SRC,Clock y source signal selector" "0,1,2,3" line.long 0xC "CCM0_CMU_FXCLK_CFG," hexmask.long.byte 0xC 0.--3. 1. "FXCLK0_SRC,Fixed clock 0 source signal selector" line.long 0x10 "CCM0_CFG," bitfld.long 0x10 31. "TBU_DIR2,DIR1 input signal of module TBU timebase [z]." "0,1" bitfld.long 0x10 30. "TBU_DIR1,DIR1 input signal of module TBU timebase [z]." "0,1" bitfld.long 0x10 16.--17. "CLS_CLK_DIV,Cluster Clock Divider." "0,1,2,3" newline bitfld.long 0x10 8. "EN_TIO_DTM,Enable TIO and connected DTM" "0,1" bitfld.long 0x10 7. "EN_CMP_MON,Enable CMP and MON" "0,1" bitfld.long 0x10 6. "EN_PSM,Enable PSM" "0,1" newline bitfld.long 0x10 5. "EN_BRC,Enable BRC" "0,1" bitfld.long 0x10 4. "EN_DPLL_MAP,Enable DPLL and MAP" "0,1" bitfld.long 0x10 3. "EN_MCS,Enable MCS" "0,1" newline bitfld.long 0x10 2. "EN_ATOM_ADTM,Enable ATOM and ADTM" "0,1" bitfld.long 0x10 1. "EN_TOM_SPE_TDTM,Enable TOM SPE and TDTM" "0,1" bitfld.long 0x10 0. "EN_TIM,Enable TIM" "0,1" line.long 0x14 "CCM0_PROT," bitfld.long 0x14 0. "CLS_PROT,Cluster Protection" "0,1" group.long 0x4800++0x47 line.long 0x0 "F2A0_CH0_ARU_RD_FIFO," hexmask.long.word 0x0 0.--8. 1. "ADDR,ARU Read address" line.long 0x4 "F2A0_CH1_ARU_RD_FIFO," hexmask.long.word 0x4 0.--8. 1. "ADDR,ARU Read address" line.long 0x8 "F2A0_CH2_ARU_RD_FIFO," hexmask.long.word 0x8 0.--8. 1. "ADDR,ARU Read address" line.long 0xC "F2A0_CH3_ARU_RD_FIFO," hexmask.long.word 0xC 0.--8. 1. "ADDR,ARU Read address" line.long 0x10 "F2A0_CH4_ARU_RD_FIFO," hexmask.long.word 0x10 0.--8. 1. "ADDR,ARU Read address" line.long 0x14 "F2A0_CH5_ARU_RD_FIFO," hexmask.long.word 0x14 0.--8. 1. "ADDR,ARU Read address" line.long 0x18 "F2A0_CH6_ARU_RD_FIFO," hexmask.long.word 0x18 0.--8. 1. "ADDR,ARU Read address" line.long 0x1C "F2A0_CH7_ARU_RD_FIFO," hexmask.long.word 0x1C 0.--8. 1. "ADDR,ARU Read address" line.long 0x20 "F2A0_CH0_STR_CFG," bitfld.long 0x20 18. "DIR,Data transfer direction" "0,1" bitfld.long 0x20 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x24 "F2A0_CH1_STR_CFG," bitfld.long 0x24 18. "DIR,Data transfer direction" "0,1" bitfld.long 0x24 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x28 "F2A0_CH2_STR_CFG," bitfld.long 0x28 18. "DIR,Data transfer direction" "0,1" bitfld.long 0x28 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x2C "F2A0_CH3_STR_CFG," bitfld.long 0x2C 18. "DIR,Data transfer direction" "0,1" bitfld.long 0x2C 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x30 "F2A0_CH4_STR_CFG," bitfld.long 0x30 18. "DIR,Data transfer direction" "0,1" bitfld.long 0x30 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x34 "F2A0_CH5_STR_CFG," bitfld.long 0x34 18. "DIR,Data transfer direction" "0,1" bitfld.long 0x34 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x38 "F2A0_CH6_STR_CFG," bitfld.long 0x38 18. "DIR,Data transfer direction" "0,1" bitfld.long 0x38 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x3C "F2A0_CH7_STR_CFG," bitfld.long 0x3C 18. "DIR,Data transfer direction" "0,1" bitfld.long 0x3C 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x40 "F2A0_ENABLE," bitfld.long 0x40 14.--15. "STR7_EN,Enable/disable stream y" "0,1,2,3" bitfld.long 0x40 12.--13. "STR6_EN,Enable/disable stream y" "0,1,2,3" bitfld.long 0x40 10.--11. "STR5_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 8.--9. "STR4_EN,Enable/disable stream y" "0,1,2,3" bitfld.long 0x40 6.--7. "STR3_EN,Enable/disable stream y" "0,1,2,3" bitfld.long 0x40 4.--5. "STR2_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 2.--3. "STR1_EN,Enable/disable stream y" "0,1,2,3" bitfld.long 0x40 0.--1. "STR0_EN,Enable/disable stream y" "0,1,2,3" line.long 0x44 "F2A0_CTRL," bitfld.long 0x44 6.--7. "STR7_CONF,Reconfiguration of stream y to FIFO channel y-4" "0,1,2,3" bitfld.long 0x44 4.--5. "STR6_CONF,Reconfiguration of stream y to FIFO channel y-4" "0,1,2,3" bitfld.long 0x44 2.--3. "STR5_CONF,Reconfiguration of stream y to FIFO channel y-4" "0,1,2,3" newline bitfld.long 0x44 0.--1. "STR4_CONF,Reconfiguration of stream y to FIFO channel y-4" "0,1,2,3" group.long 0x4880++0x3 line.long 0x0 "AFD0_CH0_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x4890++0x3 line.long 0x0 "AFD0_CH1_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48A0++0x3 line.long 0x0 "AFD0_CH2_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48B0++0x3 line.long 0x0 "AFD0_CH3_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48C0++0x3 line.long 0x0 "AFD0_CH4_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48D0++0x3 line.long 0x0 "AFD0_CH5_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48E0++0x3 line.long 0x0 "AFD0_CH6_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48F0++0x3 line.long 0x0 "AFD0_CH7_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x4A00++0x37 line.long 0x0 "FIFO0_CH0_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO0_CH0_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO0_CH0_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO0_CH0_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO0_CH0_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO0_CH0_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO0_CH0_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO0_CH0_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO0_CH0_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO0_CH0_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO0_CH0_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO0_CH0_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO0_CH0_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO0_CH0_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4A40++0x37 line.long 0x0 "FIFO0_CH1_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO0_CH1_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO0_CH1_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO0_CH1_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO0_CH1_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO0_CH1_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO0_CH1_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO0_CH1_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO0_CH1_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO0_CH1_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO0_CH1_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO0_CH1_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO0_CH1_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO0_CH1_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4A80++0x37 line.long 0x0 "FIFO0_CH2_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO0_CH2_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO0_CH2_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO0_CH2_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO0_CH2_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO0_CH2_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO0_CH2_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO0_CH2_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO0_CH2_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO0_CH2_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO0_CH2_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO0_CH2_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO0_CH2_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO0_CH2_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4AC0++0x37 line.long 0x0 "FIFO0_CH3_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO0_CH3_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO0_CH3_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO0_CH3_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO0_CH3_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO0_CH3_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO0_CH3_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO0_CH3_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO0_CH3_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO0_CH3_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO0_CH3_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO0_CH3_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO0_CH3_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO0_CH3_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4B00++0x37 line.long 0x0 "FIFO0_CH4_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO0_CH4_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO0_CH4_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO0_CH4_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO0_CH4_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO0_CH4_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO0_CH4_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO0_CH4_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO0_CH4_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO0_CH4_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO0_CH4_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO0_CH4_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO0_CH4_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO0_CH4_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4B40++0x37 line.long 0x0 "FIFO0_CH5_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO0_CH5_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO0_CH5_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO0_CH5_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO0_CH5_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO0_CH5_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO0_CH5_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO0_CH5_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO0_CH5_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO0_CH5_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO0_CH5_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO0_CH5_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO0_CH5_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO0_CH5_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4B80++0x37 line.long 0x0 "FIFO0_CH6_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO0_CH6_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO0_CH6_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO0_CH6_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO0_CH6_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO0_CH6_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO0_CH6_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO0_CH6_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO0_CH6_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO0_CH6_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO0_CH6_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO0_CH6_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO0_CH6_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO0_CH6_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4BC0++0x37 line.long 0x0 "FIFO0_CH7_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO0_CH7_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO0_CH7_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO0_CH7_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO0_CH7_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO0_CH7_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO0_CH7_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO0_CH7_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO0_CH7_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO0_CH7_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO0_CH7_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO0_CH7_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO0_CH7_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO0_CH7_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" repeat 1024. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6000)++0x3 line.long 0x0 "FIFO0_MEMORY[$1]," hexmask.long 0x0 0.--28. 1. "DATA,FIFO memory location." repeat.end tree.end tree "GTM_1_GTM_CLS1" base ad:0x70B20000 group.long 0x680++0x3 line.long 0x0 "MON_STATUS," bitfld.long 0x0 29. "MCS9_ERR,Error detected at MCS[j]" "0,1" bitfld.long 0x0 28. "MCS8_ERR,Error detected at MCS[j]" "0,1" bitfld.long 0x0 27. "MCS7_ERR,Error detected at MCS[j]" "0,1" newline bitfld.long 0x0 26. "MCS6_ERR,Error detected at MCS[j]" "0,1" bitfld.long 0x0 25. "MCS5_ERR,Error detected at MCS[j]" "0,1" bitfld.long 0x0 24. "MCS4_ERR,Error detected at MCS[j]" "0,1" newline bitfld.long 0x0 23. "MCS3_ERR,Error detected at MCS[j]" "0,1" bitfld.long 0x0 22. "MCS2_ERR,Error detected at MCS[j]" "0,1" bitfld.long 0x0 21. "MCS1_ERR,Error detected at MCS[j]" "0,1" newline bitfld.long 0x0 20. "MCS0_ERR,Error detected at MCS[j]" "0,1" bitfld.long 0x0 16. "CMP_ERR,Error detected at CMP" "0,1" bitfld.long 0x0 14. "ACT_CMU8,CMU_CLK8 activity" "0,1" newline bitfld.long 0x0 12. "ACT_CMUFX4,CMU_CLKFX[y] activity" "0,1" bitfld.long 0x0 11. "ACT_CMUFX3,CMU_CLKFX[y] activity" "0,1" bitfld.long 0x0 10. "ACT_CMUFX2,CMU_CLKFX[y] activity" "0,1" newline bitfld.long 0x0 9. "ACT_CMUFX1,CMU_CLKFX[y] activity" "0,1" bitfld.long 0x0 8. "ACT_CMUFX0,CMU_CLKFX[y] activity" "0,1" bitfld.long 0x0 7. "ACT_CMU7,CMU_CLK[x] activity" "0,1" newline bitfld.long 0x0 6. "ACT_CMU6,CMU_CLK[x] activity" "0,1" bitfld.long 0x0 5. "ACT_CMU5,CMU_CLK[x] activity" "0,1" bitfld.long 0x0 4. "ACT_CMU4,CMU_CLK[x] activity" "0,1" newline bitfld.long 0x0 3. "ACT_CMU3,CMU_CLK[x] activity" "0,1" bitfld.long 0x0 2. "ACT_CMU2,CMU_CLK[x] activity" "0,1" bitfld.long 0x0 1. "ACT_CMU1,CMU_CLK[x] activity" "0,1" newline bitfld.long 0x0 0. "ACT_CMU0,CMU_CLK[x] activity" "0,1" group.long 0x6C0++0x17 line.long 0x0 "CMP_EN," bitfld.long 0x0 23. "TBWC11_EN,Enable comparator channel [c] in TBWC" "0,1" bitfld.long 0x0 22. "TBWC10_EN,Enable comparator channel [c] in TBWC" "0,1" bitfld.long 0x0 21. "TBWC9_EN,Enable comparator channel [c] in TBWC" "0,1" newline bitfld.long 0x0 20. "TBWC8_EN,Enable comparator channel [c] in TBWC" "0,1" bitfld.long 0x0 19. "TBWC7_EN,Enable comparator channel [c] in TBWC" "0,1" bitfld.long 0x0 18. "TBWC6_EN,Enable comparator channel [c] in TBWC" "0,1" newline bitfld.long 0x0 17. "TBWC5_EN,Enable comparator channel [c] in TBWC" "0,1" bitfld.long 0x0 16. "TBWC4_EN,Enable comparator channel [c] in TBWC" "0,1" bitfld.long 0x0 15. "TBWC3_EN,Enable comparator channel [c] in TBWC" "0,1" newline bitfld.long 0x0 14. "TBWC2_EN,Enable comparator channel [c] in TBWC" "0,1" bitfld.long 0x0 13. "TBWC1_EN,Enable comparator channel [c] in TBWC" "0,1" bitfld.long 0x0 12. "TBWC0_EN,Enable comparator channel [c] in TBWC" "0,1" newline bitfld.long 0x0 11. "ABWC11_EN,Enable comparator channel [c] in ABWC" "0,1" bitfld.long 0x0 10. "ABWC10_EN,Enable comparator channel [c] in ABWC" "0,1" bitfld.long 0x0 9. "ABWC9_EN,Enable comparator channel [c] in ABWC" "0,1" newline bitfld.long 0x0 8. "ABWC8_EN,Enable comparator channel [c] in ABWC" "0,1" bitfld.long 0x0 7. "ABWC7_EN,Enable comparator channel [c] in ABWC" "0,1" bitfld.long 0x0 6. "ABWC6_EN,Enable comparator channel [c] in ABWC" "0,1" newline bitfld.long 0x0 5. "ABWC5_EN,Enable comparator channel [c] in ABWC" "0,1" bitfld.long 0x0 4. "ABWC4_EN,Enable comparator channel [c] in ABWC" "0,1" bitfld.long 0x0 3. "ABWC3_EN,Enable comparator channel [c] in ABWC" "0,1" newline bitfld.long 0x0 2. "ABWC2_EN,Enable comparator channel [c] in ABWC" "0,1" bitfld.long 0x0 1. "ABWC1_EN,Enable comparator channel [c] in ABWC" "0,1" bitfld.long 0x0 0. "ABWC0_EN,Enable comparator channel [c] in ABWC" "0,1" line.long 0x4 "CMP_IRQ_NOTIFY," bitfld.long 0x4 23. "TBWC11,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" bitfld.long 0x4 22. "TBWC10,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" bitfld.long 0x4 21. "TBWC9,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 20. "TBWC8,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" bitfld.long 0x4 19. "TBWC7,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" bitfld.long 0x4 18. "TBWC6,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 17. "TBWC5,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" bitfld.long 0x4 16. "TBWC4,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" bitfld.long 0x4 15. "TBWC3,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 14. "TBWC2,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" bitfld.long 0x4 13. "TBWC1,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" bitfld.long 0x4 12. "TBWC0,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 11. "ABWC11,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" bitfld.long 0x4 10. "ABWC10,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" bitfld.long 0x4 9. "ABWC9,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 8. "ABWC8,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" bitfld.long 0x4 7. "ABWC7,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" bitfld.long 0x4 6. "ABWC6,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 5. "ABWC5,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" bitfld.long 0x4 4. "ABWC4,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" bitfld.long 0x4 3. "ABWC3,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 2. "ABWC2,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" bitfld.long 0x4 1. "ABWC1,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" bitfld.long 0x4 0. "ABWC0,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" line.long 0x8 "CMP_IRQ_EN," bitfld.long 0x8 23. "TBWC11_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" bitfld.long 0x8 22. "TBWC10_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" bitfld.long 0x8 21. "TBWC9_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 20. "TBWC8_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" bitfld.long 0x8 19. "TBWC7_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" bitfld.long 0x8 18. "TBWC6_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 17. "TBWC5_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" bitfld.long 0x8 16. "TBWC4_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" bitfld.long 0x8 15. "TBWC3_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 14. "TBWC2_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" bitfld.long 0x8 13. "TBWC1_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" bitfld.long 0x8 12. "TBWC0_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 11. "ABWC11_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" bitfld.long 0x8 10. "ABWC10_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" bitfld.long 0x8 9. "ABWC9_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 8. "ABWC8_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" bitfld.long 0x8 7. "ABWC7_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" bitfld.long 0x8 6. "ABWC6_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 5. "ABWC5_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" bitfld.long 0x8 4. "ABWC4_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" bitfld.long 0x8 3. "ABWC3_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 2. "ABWC2_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" bitfld.long 0x8 1. "ABWC1_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" bitfld.long 0x8 0. "ABWC0_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" line.long 0xC "CMP_IRQ_FORCINT," bitfld.long 0xC 23. "TRG_TBWC11,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 22. "TRG_TBWC10,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 21. "TRG_TBWC9,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 20. "TRG_TBWC8,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 19. "TRG_TBWC7,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 18. "TRG_TBWC6,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 17. "TRG_TBWC5,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 16. "TRG_TBWC4,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 15. "TRG_TBWC3,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 14. "TRG_TBWC2,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 13. "TRG_TBWC1,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 12. "TRG_TBWC0,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 11. "TRG_ABWC11,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 10. "TRG_ABWC10,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 9. "TRG_ABWC9,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 8. "TRG_ABWC8,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 7. "TRG_ABWC7,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 6. "TRG_ABWC6,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 5. "TRG_ABWC5,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 4. "TRG_ABWC4,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 3. "TRG_ABWC3,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 2. "TRG_ABWC2,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 1. "TRG_ABWC1,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_ABWC0,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "CMP_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "CMP_EIRQ_EN," bitfld.long 0x14 23. "TBWC11_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" bitfld.long 0x14 22. "TBWC10_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" bitfld.long 0x14 21. "TBWC9_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 20. "TBWC8_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" bitfld.long 0x14 19. "TBWC7_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" bitfld.long 0x14 18. "TBWC6_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 17. "TBWC5_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" bitfld.long 0x14 16. "TBWC4_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" bitfld.long 0x14 15. "TBWC3_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 14. "TBWC2_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" bitfld.long 0x14 13. "TBWC1_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" bitfld.long 0x14 12. "TBWC0_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 11. "ABWC11_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" bitfld.long 0x14 10. "ABWC10_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" bitfld.long 0x14 9. "ABWC9_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 8. "ABWC8_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" bitfld.long 0x14 7. "ABWC7_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" bitfld.long 0x14 6. "ABWC6_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 5. "ABWC5_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" bitfld.long 0x14 4. "ABWC4_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" bitfld.long 0x14 3. "ABWC3_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 2. "ABWC2_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" bitfld.long 0x14 1. "ABWC1_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" bitfld.long 0x14 0. "ABWC0_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" group.long 0x800++0x3F line.long 0x0 "TIM1_CH0_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM1_CH0_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM1_CH0_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM1_CH0_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM1_CH0_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM1_CH0_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM1_CH0_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM1_CH0_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM1_CH0_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM1_CH0_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM1_CH0_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM1_CH0_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM1_CH0_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM1_CH0_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM1_CH0_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM1_CH0_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x880++0x3F line.long 0x0 "TIM1_CH1_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM1_CH1_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM1_CH1_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM1_CH1_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM1_CH1_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM1_CH1_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM1_CH1_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM1_CH1_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM1_CH1_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM1_CH1_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM1_CH1_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM1_CH1_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM1_CH1_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM1_CH1_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM1_CH1_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM1_CH1_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x900++0x3F line.long 0x0 "TIM1_CH2_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM1_CH2_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM1_CH2_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM1_CH2_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM1_CH2_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM1_CH2_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM1_CH2_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM1_CH2_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM1_CH2_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM1_CH2_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM1_CH2_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM1_CH2_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM1_CH2_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM1_CH2_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM1_CH2_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM1_CH2_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x980++0x3F line.long 0x0 "TIM1_CH3_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM1_CH3_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM1_CH3_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM1_CH3_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM1_CH3_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM1_CH3_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM1_CH3_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM1_CH3_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM1_CH3_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM1_CH3_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM1_CH3_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM1_CH3_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM1_CH3_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM1_CH3_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM1_CH3_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM1_CH3_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xA00++0x3F line.long 0x0 "TIM1_CH4_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM1_CH4_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM1_CH4_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM1_CH4_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM1_CH4_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM1_CH4_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM1_CH4_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM1_CH4_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM1_CH4_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM1_CH4_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM1_CH4_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM1_CH4_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM1_CH4_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM1_CH4_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM1_CH4_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM1_CH4_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xA80++0x3F line.long 0x0 "TIM1_CH5_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM1_CH5_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM1_CH5_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM1_CH5_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM1_CH5_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM1_CH5_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM1_CH5_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM1_CH5_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM1_CH5_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM1_CH5_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM1_CH5_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM1_CH5_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM1_CH5_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM1_CH5_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM1_CH5_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM1_CH5_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xB00++0x3F line.long 0x0 "TIM1_CH6_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM1_CH6_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM1_CH6_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM1_CH6_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM1_CH6_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM1_CH6_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM1_CH6_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM1_CH6_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM1_CH6_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM1_CH6_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM1_CH6_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM1_CH6_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM1_CH6_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM1_CH6_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM1_CH6_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM1_CH6_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xB80++0x3F line.long 0x0 "TIM1_CH7_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM1_CH7_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM1_CH7_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM1_CH7_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM1_CH7_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM1_CH7_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM1_CH7_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM1_CH7_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM1_CH7_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM1_CH7_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM1_CH7_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM1_CH7_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM1_CH7_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM1_CH7_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM1_CH7_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM1_CH7_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xC00++0xB line.long 0x0 "TIM1_INP_VAL," bitfld.long 0x0 23. "TIM_IN7,Signal channel x after TIM input signal synchronization" "0,1" bitfld.long 0x0 22. "TIM_IN6,Signal channel x after TIM input signal synchronization" "0,1" bitfld.long 0x0 21. "TIM_IN5,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 20. "TIM_IN4,Signal channel x after TIM input signal synchronization" "0,1" bitfld.long 0x0 19. "TIM_IN3,Signal channel x after TIM input signal synchronization" "0,1" bitfld.long 0x0 18. "TIM_IN2,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 17. "TIM_IN1,Signal channel x after TIM input signal synchronization" "0,1" bitfld.long 0x0 16. "TIM_IN0,Signal channel x after TIM input signal synchronization" "0,1" bitfld.long 0x0 15. "F_IN7,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 14. "F_IN6,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" bitfld.long 0x0 13. "F_IN5,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" bitfld.long 0x0 12. "F_IN4,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 11. "F_IN3,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" bitfld.long 0x0 10. "F_IN2,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" bitfld.long 0x0 9. "F_IN1,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 8. "F_IN0,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" bitfld.long 0x0 7. "F_OUT7,Signal channel x after TIM FLT unit" "0,1" bitfld.long 0x0 6. "F_OUT6,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 5. "F_OUT5,Signal channel x after TIM FLT unit" "0,1" bitfld.long 0x0 4. "F_OUT4,Signal channel x after TIM FLT unit" "0,1" bitfld.long 0x0 3. "F_OUT3,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 2. "F_OUT2,Signal channel x after TIM FLT unit" "0,1" bitfld.long 0x0 1. "F_OUT1,Signal channel x after TIM FLT unit" "0,1" bitfld.long 0x0 0. "F_OUT0,Signal channel x after TIM FLT unit" "0,1" line.long 0x4 "TIM1_IN_SRC," bitfld.long 0x4 30.--31. "MODE_7,Input source to Channel x" "0,1,2,3" bitfld.long 0x4 28.--29. "VAL_7,Value to be fed to channel [x]" "0,1,2,3" bitfld.long 0x4 26.--27. "MODE_6,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 24.--25. "VAL_6,Value to be fed to channel [x]" "0,1,2,3" bitfld.long 0x4 22.--23. "MODE_5,Input source to Channel x" "0,1,2,3" bitfld.long 0x4 20.--21. "VAL_5,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 18.--19. "MODE_4,Input source to Channel x" "0,1,2,3" bitfld.long 0x4 16.--17. "VAL_4,Value to be fed to channel [x]" "0,1,2,3" bitfld.long 0x4 14.--15. "MODE_3,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 12.--13. "VAL_3,Value to be fed to channel [x]" "0,1,2,3" bitfld.long 0x4 10.--11. "MODE_2,Input source to Channel x" "0,1,2,3" bitfld.long 0x4 8.--9. "VAL_2,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 6.--7. "MODE_1,Input source to Channel x" "0,1,2,3" bitfld.long 0x4 4.--5. "VAL_1,Value to be fed to channel [x]" "0,1,2,3" bitfld.long 0x4 2.--3. "MODE_0,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 0.--1. "VAL_0,Value to be fed to channel [x]" "0,1,2,3" line.long 0x8 "TIM1_RST," bitfld.long 0x8 7. "RST_CH7,Software reset of channel [x]" "0,1" bitfld.long 0x8 6. "RST_CH6,Software reset of channel [x]" "0,1" bitfld.long 0x8 5. "RST_CH5,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 4. "RST_CH4,Software reset of channel [x]" "0,1" bitfld.long 0x8 3. "RST_CH3,Software reset of channel [x]" "0,1" bitfld.long 0x8 2. "RST_CH2,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 1. "RST_CH1,Software reset of channel [x]" "0,1" bitfld.long 0x8 0. "RST_CH0,Software reset of channel [x]" "0,1" group.long 0x41D4++0x3 line.long 0x0 "CCM1_HW_CONF2," bitfld.long 0x0 18. "AXIM_DATA_SIZE,Defines the data bus width of the AXI master interface" "0,1" bitfld.long 0x0 16. "AXIS_DATA_SIZE,Defines the data bus width of the AXI slave interface" "0,1" bitfld.long 0x0 9. "TIO_OUT_RST,TIO_OUT reset level" "0,1" newline bitfld.long 0x0 7. "AXIM_POSTED_WRITE,Write transaction without response" "0,1" bitfld.long 0x0 6. "AXIM_SEC_ACC,Secure AXI master access constant" "0,1" bitfld.long 0x0 5. "AXIM_PRIV_ACC,Privileged AXI master access constant" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "AXIM_ID_WIDTH,Defines which LSB of AXIM_ID are send to the bus" group.long 0x41DC++0x7 line.long 0x0 "CCM1_HW_CONF," bitfld.long 0x0 31. "AEI_RDATA_PIPELINE_STAGE,Read data pipeline stage implemented" "0,1" bitfld.long 0x0 30. "AEI_ADDR_PIPELINE_STAGE,Address pipeline stage implemented" "0,1" bitfld.long 0x0 29. "INT_CLK_EN_GEN,Internal clock enable generation" "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "TOM_TRIG_INTCHAIN,TOM internal trigger chain length without synchronization register" hexmask.long.byte 0x0 20.--23. 1. "ATOM_TRIG_INTCHAIN,ATOM internal trigger chain length without synchronization register" bitfld.long 0x0 19. "IRQ_MODE_SINGLE_PULSE,Signalize availability of Single Pulse IRQ mode" "0,1" newline bitfld.long 0x0 18. "IRQ_MODE_PULSE_NOTIFY,Signalize availability of Pulse Notoify IRQ mode" "0,1" bitfld.long 0x0 17. "IRQ_MODE_PULSE,Signalize availability of Pulse IRQ mode" "0,1" bitfld.long 0x0 16. "IRQ_MODE_LEVEL,Signalize availability of Level IRQ mode" "0,1" newline bitfld.long 0x0 15. "RESET_ACTIVE,Active level of asynchronous reset" "0,1" bitfld.long 0x0 13. "ERM,Enable RAM1 MSB for available MCS modules" "0,1" bitfld.long 0x0 12. "RAM_INIT_RST,RAM initialization from reset" "0,1" newline bitfld.long 0x0 9.--11. "TOM_TRIG_CHAIN,TOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "TOM_OUT_RST,TOM_OUT reset level" "0,1" bitfld.long 0x0 5.--7. "ATOM_TRIG_CHAIN,ATOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "ATOM_OUT_RST,ATOM_OUT reset level" "0,1" bitfld.long 0x0 3. "CFG_CLOCK_RATE,Clocks per ARU transfer" "0,1" bitfld.long 0x0 2. "SYNC_INPUT_REG,Additional pipelined stage in synchronous bridge mode" "0,1" newline bitfld.long 0x0 1. "BRIDGE_MODE_RST,Bridge mode after reset" "0,1" bitfld.long 0x0 0. "GRSTEN,Global Reset Enable" "0,1" line.long 0x4 "CCM1_TIM_AUX_IN_SRC," bitfld.long 0x4 23. "SEL_OUT_N_CH7,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" bitfld.long 0x4 22. "SEL_OUT_N_CH6,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" bitfld.long 0x4 21. "SEL_OUT_N_CH5,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0x4 20. "SEL_OUT_N_CH4,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" bitfld.long 0x4 19. "SEL_OUT_N_CH3,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" bitfld.long 0x4 18. "SEL_OUT_N_CH2,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0x4 17. "SEL_OUT_N_CH1,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" bitfld.long 0x4 16. "SEL_OUT_N_CH0,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" bitfld.long 0x4 7. "SRC_CH7,Defines AUX_IN source of TIM[i] channel 7" "0,1" newline bitfld.long 0x4 6. "SRC_CH6,Defines AUX_IN source of TIM[i] channel 6" "0,1" bitfld.long 0x4 5. "SRC_CH5,Defines AUX_IN source of TIM[i] channel 5" "0,1" bitfld.long 0x4 4. "SRC_CH4,Defines AUX_IN source of TIM[i] channel 4" "0,1" newline bitfld.long 0x4 3. "SRC_CH3,Defines AUX_IN source of TIM[i] channel 3" "0,1" bitfld.long 0x4 2. "SRC_CH2,Defines AUX_IN source of TIM[i] channel 2" "0,1" bitfld.long 0x4 1. "SRC_CH1,Defines AUX_IN source of TIM[i] channel 1" "0,1" newline bitfld.long 0x4 0. "SRC_CH0,Defines AUX_IN source of TIM[i] channel 0" "0,1" group.long 0x41F0++0x3 line.long 0x0 "CCM1_CMU_CLK_CFG," bitfld.long 0x0 28.--29. "CLK7_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x0 24.--25. "CLK6_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x0 20.--21. "CLK5_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x0 16.--17. "CLK4_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x0 12.--13. "CLK3_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x0 8.--9. "CLK2_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x0 4.--5. "CLK1_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x0 0.--1. "CLK0_SRC,Clock y source signal selector" "0,1,2,3" group.long 0x41F8++0x7 line.long 0x0 "CCM1_CFG," bitfld.long 0x0 31. "TBU_DIR2,DIR1 input signal of module TBU timebase [z]." "0,1" bitfld.long 0x0 30. "TBU_DIR1,DIR1 input signal of module TBU timebase [z]." "0,1" bitfld.long 0x0 16.--17. "CLS_CLK_DIV,Cluster Clock Divider." "0,1,2,3" newline bitfld.long 0x0 8. "EN_TIO_DTM,Enable TIO and connected DTM" "0,1" bitfld.long 0x0 7. "EN_CMP_MON,Enable CMP and MON" "0,1" bitfld.long 0x0 6. "EN_PSM,Enable PSM" "0,1" newline bitfld.long 0x0 5. "EN_BRC,Enable BRC" "0,1" bitfld.long 0x0 4. "EN_DPLL_MAP,Enable DPLL and MAP" "0,1" bitfld.long 0x0 3. "EN_MCS,Enable MCS" "0,1" newline bitfld.long 0x0 2. "EN_ATOM_ADTM,Enable ATOM and ADTM" "0,1" bitfld.long 0x0 1. "EN_TOM_SPE_TDTM,Enable TOM SPE and TDTM" "0,1" bitfld.long 0x0 0. "EN_TIM,Enable TIM" "0,1" line.long 0x4 "CCM1_PROT," bitfld.long 0x4 0. "CLS_PROT,Cluster Protection" "0,1" tree.end tree "GTM_CLS0" base ad:0x74000000 group.long 0x0++0x33 line.long 0x0 "GTM_REV," hexmask.long.byte 0x0 28.--31. 1. "VER_MAJOR,Major version number" newline hexmask.long.byte 0x0 24.--27. 1. "VER_MINOR,Minor version number" newline hexmask.long.byte 0x0 20.--23. 1. "DEVICE_CODE,Device encoding digit 0." newline hexmask.long.byte 0x0 16.--19. 1. "VENDOR_CODE,Device encoding digit 1." newline hexmask.long.byte 0x0 4.--11. 1. "REL_BASE,Release step" newline hexmask.long.byte 0x0 0.--3. 1. "REL_ITER,Delivery number" line.long 0x4 "GTM_RST," bitfld.long 0x4 27. "BRIDGE_MODE_WRDIS,BRIDGE_MODE write disable." "0,1" newline bitfld.long 0x4 0. "RST,GTM-IP Reset." "0,1" line.long 0x8 "GTM_CTRL," hexmask.long.byte 0x8 12.--15. 1. "AEIM_CLUSTER,AEIM cluster number" newline hexmask.long.byte 0x8 4.--11. 1. "TO_VAL,AEI timeout value." newline bitfld.long 0x8 1.--2. "TO_MODE,AEI timeout mode." "0,1,2,3" newline bitfld.long 0x8 0. "RF_PROT,RST and FORCINT protection." "0,1" line.long 0xC "GTM_CFG," bitfld.long 0xC 0. "SRC_IN_MUX,GTM_TIM[i]_AUX_IN input source selection" "0,1" line.long 0x10 "GTM_AEI_ADDR_XPT," bitfld.long 0x10 24. "TO_W1R0,AEI timeout Read/Write flag." "0,1" newline hexmask.long.tbyte 0x10 0.--20. 1. "TO_ADDR,AEI timeout address." line.long 0x14 "GTM_AEI_STA_XPT," bitfld.long 0x14 24. "W1R0,AEI exception Read/Write flag." "0,1" newline hexmask.long.tbyte 0x14 0.--20. 1. "ADDR,AEI exception address." line.long 0x18 "GTM_IRQ_NOTIFY," bitfld.long 0x18 28.--29. "CLK_EN_EXP_STATE,Expected clock enable state." "0,1,2,3" newline bitfld.long 0x18 24.--25. "CLK_EN_ERR_STATE,Erroneous clock enable state." "0,1,2,3" newline bitfld.long 0x18 8. "CLK_PER_ERR,Clock period error interrupt." "0,1" newline bitfld.long 0x18 7. "CLK_EN_ERR,Clock enable error interrupt." "0,1" newline bitfld.long 0x18 6. "AEIM_USP_BE,AEI master port unsupported byte enable interrupt." "0,1" newline bitfld.long 0x18 5. "AEIM_IM_ADDR,AEI master port illegal Module address interrupt." "0,1" newline bitfld.long 0x18 4. "AEIM_USP_ADDR,AEI master port unsupported address interrupt." "0,1" newline bitfld.long 0x18 3. "AEI_USP_BE,AEI unsupported byte enable interrupt." "0,1" newline bitfld.long 0x18 2. "AEI_IM_ADDR,AEI illegal Module address interrupt." "0,1" newline bitfld.long 0x18 1. "AEI_USP_ADDR,AEI unsupported address interrupt." "0,1" newline bitfld.long 0x18 0. "AEI_TO_XPT,AEI timeout exception occurred." "0,1" line.long 0x1C "GTM_IRQ_EN," bitfld.long 0x1C 8. "CLK_PER_ERR_IRQ_EN,CLK_PER_ERR_IRQ interrupt enable." "0,1" newline bitfld.long 0x1C 7. "CLK_EN_ERR_IRQ_EN,CLK_EN_ERR_IRQ interrupt enable." "0,1" newline bitfld.long 0x1C 6. "AEIM_USP_BE_IRQ_EN,AEIM_USP_BE_IRQ interrupt enable." "0,1" newline bitfld.long 0x1C 5. "AEIM_IM_ADDR_IRQ_EN,AEIM_IM_ADDR_IRQ interrupt enable." "0,1" newline bitfld.long 0x1C 4. "AEIM_USP_ADDR_IRQ_EN,AEI_MUSP_ADDR_IRQ interrupt enable." "0,1" newline bitfld.long 0x1C 3. "AEI_USP_BE_IRQ_EN,AEI_USP_BE_IRQ interrupt enable." "0,1" newline bitfld.long 0x1C 2. "AEI_IM_ADDR_IRQ_EN,AEI_IM_ADDR_IRQ interrupt enable." "0,1" newline bitfld.long 0x1C 1. "AEI_USP_ADDR_IRQ_EN,AEI_USP_ADDR_IRQ interrupt enable." "0,1" newline bitfld.long 0x1C 0. "AEI_TO_XPT_IRQ_EN,AEI_TO_XPT_IRQ interrupt enable." "0,1" line.long 0x20 "GTM_EIRQ_EN," bitfld.long 0x20 8. "CLK_PER_ERR_EIRQ_EN,CLK_PER_ERR_EIRQ interrupt enable." "0,1" newline bitfld.long 0x20 7. "CLK_EN_ERR_EIRQ_EN,CLK_EN_ERR_EIRQ interrupt enable." "0,1" newline bitfld.long 0x20 6. "AEIM_USP_BE_EIRQ_EN,AEIM_USP_BE_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x20 5. "AEIM_IM_ADDR_EIRQ_EN,AEIM_IM_ADDR_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x20 4. "AEIM_USP_ADDR_EIRQ_EN,AEIM_USP_ADDR_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x20 3. "AEI_USP_BE_EIRQ_EN,AEI_USP_BE_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x20 2. "AEI_IM_ADDR_EIRQ_EN,AEI_IM_ADDR_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x20 1. "AEI_USP_ADDR_EIRQ_EN,AEI_USP_ADDR_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x20 0. "AEI_TO_XPT_EIRQ_EN,AEI_TO_XPT_EIRQ error interrupt enable." "0,1" line.long 0x24 "GTM_IRQ_FORCINT," bitfld.long 0x24 8. "TRG_CLK_PER_ERR,Trigger CLK_PER_ERR_IRQ interrupt by software." "0,1" newline bitfld.long 0x24 7. "TRG_CLK_EN_ERR,Trigger CLK_EN_ERR_IRQ interrupt by software." "0,1" newline bitfld.long 0x24 6. "TRG_AEIM_USP_BE,Trigger AEIM_USP_BE_IRQ interrupt by software." "0,1" newline bitfld.long 0x24 5. "TRG_AEIM_IM_ADDR,Trigger AEIM_IM_ADDR_IRQ interrupt by software." "0,1" newline bitfld.long 0x24 4. "TRG_AEIM_USP_ADDR,Trigger AEIM_USP_ADDR_IRQ interrupt by software." "0,1" newline bitfld.long 0x24 3. "TRG_AEI_USP_BE,Trigger AEI_USP_BE_IRQ interrupt by software." "0,1" newline bitfld.long 0x24 2. "TRG_AEI_IM_ADDR,Trigger AEI_IM_ADDR_IRQ interrupt by software." "0,1" newline bitfld.long 0x24 1. "TRG_AEI_USP_ADDR,Trigger AEI_USP_ADDR_IRQ interrupt by software." "0,1" newline bitfld.long 0x24 0. "TRG_AEI_TO_XPT,Trigger AEI_TO_XPT_IRQ interrupt by software." "0,1" line.long 0x28 "GTM_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,Interrupt strategy mode selection for the AEI timeout and address monitoring interrupts." "0,1,2,3" line.long 0x2C "GTM_CLS_CLK_CFG," bitfld.long 0x2C 22.--23. "CLS11_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" newline bitfld.long 0x2C 20.--21. "CLS10_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" newline bitfld.long 0x2C 18.--19. "CLS9_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" newline bitfld.long 0x2C 16.--17. "CLS8_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" newline bitfld.long 0x2C 14.--15. "CLS7_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" newline bitfld.long 0x2C 12.--13. "CLS6_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" newline bitfld.long 0x2C 10.--11. "CLS5_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" newline bitfld.long 0x2C 8.--9. "CLS4_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" newline bitfld.long 0x2C 6.--7. "CLS3_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" newline bitfld.long 0x2C 4.--5. "CLS2_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" newline bitfld.long 0x2C 2.--3. "CLS1_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" newline bitfld.long 0x2C 0.--1. "CLS0_CLK_DIV,Cluster [j] Clock Divider" "0,1,2,3" line.long 0x30 "GTM_ARU_COM_DIS," bitfld.long 0x30 9. "CLS9_DIS,Disable cluster [j] ARU communication" "0,1" newline bitfld.long 0x30 8. "CLS8_DIS,Disable cluster [j] ARU communication" "0,1" newline bitfld.long 0x30 7. "CLS7_DIS,Disable cluster [j] ARU communication" "0,1" newline bitfld.long 0x30 6. "CLS6_DIS,Disable cluster [j] ARU communication" "0,1" newline bitfld.long 0x30 5. "CLS5_DIS,Disable cluster [j] ARU communication" "0,1" newline bitfld.long 0x30 4. "CLS4_DIS,Disable cluster [j] ARU communication" "0,1" newline bitfld.long 0x30 3. "CLS3_DIS,Disable cluster [j] ARU communication" "0,1" newline bitfld.long 0x30 2. "CLS2_DIS,Disable cluster [j] ARU communication" "0,1" newline bitfld.long 0x30 1. "CLS1_DIS,Disable cluster [j] ARU communication" "0,1" newline bitfld.long 0x30 0. "CLS0_DIS,Disable cluster [j] ARU communication" "0,1" group.long 0x40++0xF line.long 0x0 "BRIDGE_MODE," hexmask.long.byte 0x0 24.--31. 1. "BUFF_DPT,Buffer depth of AEI bridge." newline bitfld.long 0x0 16. "BRG_RST,Bridge software reset." "0,1" newline bitfld.long 0x0 12. "SYNC_INPUT_REG,additional pipelined stage in synchronous bridge mode" "0,1" newline bitfld.long 0x0 9. "BUFF_OVL,Buffer overflow register." "0,1" newline bitfld.long 0x0 8. "MODE_UP_PGR,Mode update in progress." "0,1" newline bitfld.long 0x0 2. "BYPASS_SYNC,Bypass synchronizer flipflops." "0,1" newline bitfld.long 0x0 1. "MSK_WR_RSP,Mask write response." "0,1" newline bitfld.long 0x0 0. "BRG_MODE,Defines the operation mode for the AEI bridge." "0,1" line.long 0x4 "BRIDGE_PTR1," hexmask.long.byte 0x4 26.--31. 1. "RSP_TRAN_RDY,Response transactions ready." newline hexmask.long.byte 0x4 20.--25. 1. "FBC,Free buffer count." newline hexmask.long.byte 0x4 15.--19. 1. "ABT_TRAN_PGR,Aborted transaction in progress pointer." newline hexmask.long.byte 0x4 10.--14. 1. "TRAN_IN_PGR,Transaction in progress pointer (acquire)" newline hexmask.long.byte 0x4 5.--9. 1. "FIRST_RSP_PTR,First response pointer." newline hexmask.long.byte 0x4 0.--4. 1. "NEW_TRAN_PTR,New transaction pointer." line.long 0x8 "BRIDGE_PTR2," hexmask.long.byte 0x8 0.--4. 1. "TRAN_IN_PGR2,Transaction in progress pointer (aquire2)" line.long 0xC "MCS_AEM_DIS," bitfld.long 0xC 18.--19. "DIS_CLS9,Disable MCS AEIM access in cluster j" "0,1,2,3" newline bitfld.long 0xC 16.--17. "DIS_CLS8,Disable MCS AEIM access in cluster j" "0,1,2,3" newline bitfld.long 0xC 14.--15. "DIS_CLS7,Disable MCS AEIM access in cluster j" "0,1,2,3" newline bitfld.long 0xC 12.--13. "DIS_CLS6,Disable MCS AEIM access in cluster j" "0,1,2,3" newline bitfld.long 0xC 10.--11. "DIS_CLS5,Disable MCS AEIM access in cluster j" "0,1,2,3" newline bitfld.long 0xC 8.--9. "DIS_CLS4,Disable MCS AEIM access in cluster j" "0,1,2,3" newline bitfld.long 0xC 6.--7. "DIS_CLS3,Disable MCS AEIM access in cluster j" "0,1,2,3" newline bitfld.long 0xC 4.--5. "DIS_CLS2,Disable MCS AEIM access in cluster j" "0,1,2,3" newline bitfld.long 0xC 2.--3. "DIS_CLS1,Disable MCS AEIM access in cluster j" "0,1,2,3" newline bitfld.long 0xC 0.--1. "DIS_CLS0,Disable MCS AEIM access in cluster j" "0,1,2,3" group.long 0x80++0x4F line.long 0x0 "CMU_CLK_EN," bitfld.long 0x0 22.--23. "EN_FXCLK,Enable all CMU_FXCLK see bits 1:0" "?,1: 0,?,?" newline bitfld.long 0x0 20.--21. "EN_ECLK2,Enable ECLK z generation sub-unit see bits 1:0" "?,1: 0,?,?" newline bitfld.long 0x0 18.--19. "EN_ECLK1,Enable ECLK z generation sub-unit see bits 1:0" "?,1: 0,?,?" newline bitfld.long 0x0 16.--17. "EN_ECLK0,Enable ECLK z generation sub-unit see bits 1:0" "?,1: 0,?,?" newline bitfld.long 0x0 14.--15. "EN_CLK7,Enable clock source x" "0,1,2,3" newline bitfld.long 0x0 12.--13. "EN_CLK6,Enable clock source x" "0,1,2,3" newline bitfld.long 0x0 10.--11. "EN_CLK5,Enable clock source x" "0,1,2,3" newline bitfld.long 0x0 8.--9. "EN_CLK4,Enable clock source x" "0,1,2,3" newline bitfld.long 0x0 6.--7. "EN_CLK3,Enable clock source x" "0,1,2,3" newline bitfld.long 0x0 4.--5. "EN_CLK2,Enable clock source x" "0,1,2,3" newline bitfld.long 0x0 2.--3. "EN_CLK1,Enable clock source x" "0,1,2,3" newline bitfld.long 0x0 0.--1. "EN_CLK0,Enable clock source x" "0,1,2,3" line.long 0x4 "CMU_GCLK_NUM," hexmask.long.tbyte 0x4 0.--23. 1. "GCLK_NUM,Numerator for global clock divider. Defines numerator of the fractional divider." line.long 0x8 "CMU_GCLK_DEN," hexmask.long.tbyte 0x8 0.--23. 1. "GCLK_DEN,Denominator for global clock divider. Defines denominator of the fractional divider" line.long 0xC "CMU_CLK_0_CTRL," hexmask.long.tbyte 0xC 0.--23. 1. "CLK_CNT,Clock count. Defines count value for the clock divider." line.long 0x10 "CMU_CLK_1_CTRL," hexmask.long.tbyte 0x10 0.--23. 1. "CLK_CNT,Clock count. Defines count value for the clock divider." line.long 0x14 "CMU_CLK_2_CTRL," hexmask.long.tbyte 0x14 0.--23. 1. "CLK_CNT,Clock count. Defines count value for the clock divider." line.long 0x18 "CMU_CLK_3_CTRL," hexmask.long.tbyte 0x18 0.--23. 1. "CLK_CNT,Clock count. Defines count value for the clock divider." line.long 0x1C "CMU_CLK_4_CTRL," hexmask.long.tbyte 0x1C 0.--23. 1. "CLK_CNT,Clock count. Defines count value for the clock divider." line.long 0x20 "CMU_CLK_5_CTRL," hexmask.long.tbyte 0x20 0.--23. 1. "CLK_CNT,Clock count. Defines count value for the clock divider." line.long 0x24 "CMU_CLK_6_CTRL," bitfld.long 0x24 24.--25. "CLK_SEL,Clock source selection." "0,1,2,3" newline hexmask.long.tbyte 0x24 0.--23. 1. "CLK_CNT,Clock count. Define count value for the clock divider of clock source CMU_CLK6." line.long 0x28 "CMU_CLK_7_CTRL," bitfld.long 0x28 24.--25. "CLK_SEL,Clock source selection." "0,1,2,3" newline hexmask.long.tbyte 0x28 0.--23. 1. "CLK_CNT,Clock count. Define count value for the clock divider of clock source CMU_CLK7." line.long 0x2C "CMU_ECLK_0_NUM," hexmask.long.tbyte 0x2C 0.--23. 1. "ECLK_NUM,Numerator for external clock divider. Defines numerator of the fractional divider." line.long 0x30 "CMU_ECLK_0_DEN," hexmask.long.tbyte 0x30 0.--23. 1. "ECLK_DEN,Denominator for external clock divider. Defines denominator of the fractional divider" line.long 0x34 "CMU_ECLK_1_NUM," hexmask.long.tbyte 0x34 0.--23. 1. "ECLK_NUM,Numerator for external clock divider. Defines numerator of the fractional divider." line.long 0x38 "CMU_ECLK_1_DEN," hexmask.long.tbyte 0x38 0.--23. 1. "ECLK_DEN,Denominator for external clock divider. Defines denominator of the fractional divider" line.long 0x3C "CMU_ECLK_2_NUM," hexmask.long.tbyte 0x3C 0.--23. 1. "ECLK_NUM,Numerator for external clock divider. Defines numerator of the fractional divider." line.long 0x40 "CMU_ECLK_2_DEN," hexmask.long.tbyte 0x40 0.--23. 1. "ECLK_DEN,Denominator for external clock divider. Defines denominator of the fractional divider" line.long 0x44 "CMU_FXCLK_CTRL," hexmask.long.byte 0x44 0.--3. 1. "FXCLK_SEL,Input clock selection for EN_FXCLK line." line.long 0x48 "CMU_GLB_CTRL," bitfld.long 0x48 0. "ARU_ADDR_RSTGLB,Reset ARU caddr counter and ARU dynamic route counter" "0,1" line.long 0x4C "CMU_CLK_CTRL," bitfld.long 0x4C 8. "CLK8_EXT_DIVIDER,Clock source selection for CMU_CLK8." "0,1" newline bitfld.long 0x4C 7. "CLK7_EXT_DIVIDER,Clock source selection for CMU_CLK_[x]_CTRL." "0,1" newline bitfld.long 0x4C 6. "CLK6_EXT_DIVIDER,Clock source selection for CMU_CLK_[x]_CTRL." "0,1" newline bitfld.long 0x4C 5. "CLK5_EXT_DIVIDER,Clock source selection for CMU_CLK_[x]_CTRL." "0,1" newline bitfld.long 0x4C 4. "CLK4_EXT_DIVIDER,Clock source selection for CMU_CLK_[x]_CTRL." "0,1" newline bitfld.long 0x4C 3. "CLK3_EXT_DIVIDER,Clock source selection for CMU_CLK_[x]_CTRL." "0,1" newline bitfld.long 0x4C 2. "CLK2_EXT_DIVIDER,Clock source selection for CMU_CLK_[x]_CTRL." "0,1" newline bitfld.long 0x4C 1. "CLK1_EXT_DIVIDER,Clock source selection for CMU_CLK_[x]_CTRL." "0,1" newline bitfld.long 0x4C 0. "CLK0_EXT_DIVIDER,Clock source selection for CMU_CLK_[x]_CTRL." "0,1" group.long 0x100++0x1B line.long 0x0 "TBU_CHEN," bitfld.long 0x0 6.--7. "ENDIS_CH3,TBU channel y enable/disable control." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ENDIS_CH2,TBU channel y enable/disable control." "0,1,2,3" newline bitfld.long 0x0 2.--3. "ENDIS_CH1,TBU channel y enable/disable control." "0,1,2,3" newline bitfld.long 0x0 0.--1. "ENDIS_CH0,TBU channel y enable/disable control." "0,1,2,3" line.long 0x4 "TBU_CH0_CTRL," bitfld.long 0x4 1.--3. "CH_CLK_SRC,Clock source for channel x (x:0...2) time base counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "LOW_RES,TBU_CH0_BASE register resolution." "0,1" line.long 0x8 "TBU_CH0_BASE," hexmask.long 0x8 0.--26. 1. "BASE,Time base value for channel 0." line.long 0xC "TBU_CH1_CTRL," bitfld.long 0xC 1.--3. "CH_CLK_SRC,Clock source for channel 1 time base counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "CH_MODE,Channel mode" "0,1" line.long 0x10 "TBU_CH1_BASE," hexmask.long.tbyte 0x10 0.--23. 1. "BASE,Time base value for channel x (x: 1 2)" line.long 0x14 "TBU_CH2_CTRL," bitfld.long 0x14 1.--3. "CH_CLK_SRC,Clock source for channel 2 time base counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 0. "CH_MODE,Channel mode" "0,1" line.long 0x18 "TBU_CH2_BASE," hexmask.long.tbyte 0x18 0.--23. 1. "BASE,Time base value for channel x (x: 1 2)" group.long 0x180++0x37 line.long 0x0 "ARU_ACCESS," bitfld.long 0x0 13. "WREQ,Initiate write request" "0,1" newline bitfld.long 0x0 12. "RREQ,Initiate read request" "0,1" newline hexmask.long.word 0x0 0.--8. 1. "ADDR,ARU address" line.long 0x4 "ARU_DATA_H," hexmask.long 0x4 0.--28. 1. "DATA,Upper ARU data word" line.long 0x8 "ARU_DATA_L," hexmask.long 0x8 0.--28. 1. "DATA,Lower ARU data word" line.long 0xC "ARU_DBG_ACCESS0," hexmask.long.word 0xC 0.--8. 1. "ADDR,ARU debugging address" line.long 0x10 "ARU_DBG_DATA0_H," hexmask.long 0x10 0.--28. 1. "DATA,Upper debug data word" line.long 0x14 "ARU_DBG_DATA0_L," hexmask.long 0x14 0.--28. 1. "DATA,Lower debug data word" line.long 0x18 "ARU_DBG_ACCESS1," hexmask.long.word 0x18 0.--8. 1. "ADDR,ARU debugging address" line.long 0x1C "ARU_DBG_DATA1_H," hexmask.long 0x1C 0.--28. 1. "DATA,Upper debug data word" line.long 0x20 "ARU_DBG_DATA1_L," hexmask.long 0x20 0.--28. 1. "DATA,Lower debug data word" line.long 0x24 "ARU_IRQ_NOTIFY," bitfld.long 0x24 2. "ACC_ACK,AEI to ARU access finished on read access data are valid" "0,1" newline bitfld.long 0x24 1. "NEW_DATA1,Data was transferred for addr ARU_DBG_ACCESS1" "0,1" newline bitfld.long 0x24 0. "NEW_DATA0,Data was transferred for addr ARU_DBG_ACCESS0" "0,1" line.long 0x28 "ARU_IRQ_EN," bitfld.long 0x28 2. "ACC_ACK_IRQ_EN,ACC_ACK_IRQ interrupt enable" "0,1" newline bitfld.long 0x28 1. "NEW_DATA1_IRQ_EN,ARU_NEW_DATA1_IRQ interrupt enable" "0,1" newline bitfld.long 0x28 0. "NEW_DATA0_IRQ_EN,ARU_NEW_DATA0_IRQ interrupt enable" "0,1" line.long 0x2C "ARU_IRQ_FORCINT," bitfld.long 0x2C 2. "TRG_ACC_ACK,Trigger ACC_ACK interrupt" "0,1" newline bitfld.long 0x2C 1. "TRG_NEW_DATA1,Trigger new data k interrupt" "0,1" newline bitfld.long 0x2C 0. "TRG_NEW_DATA0,Trigger new data k interrupt" "0,1" line.long 0x30 "ARU_IRQ_MODE," bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "ARU_CADDR_END," hexmask.long.byte 0x34 0.--6. 1. "CADDR_END,Set end value of ARU caddr counter" group.long 0x1BC++0x33 line.long 0x0 "ARU_CTRL," bitfld.long 0x0 4. "ARU_DYN_RING_MODE,Enable dynamic routing ring mode" "0,1" newline bitfld.long 0x0 2.--3. "ARU_1_DYN_EN,Enable dynamic routing for ARU-k" "0,1,2,3" newline bitfld.long 0x0 0.--1. "ARU_0_DYN_EN,Enable dynamic routing for ARU-k" "0,1,2,3" line.long 0x4 "ARU_0_DYN_CTRL," bitfld.long 0x4 1. "DYN_ROUTE_SWAP,Enable swapping DYN_ROUTE_SR with DYN_ROUTE register" "0,1" newline bitfld.long 0x4 0. "DYN_ARU_UPDATE_EN,Enable reload of DYN_ROUTE register from ARU itself" "0,1" line.long 0x8 "ARU_1_DYN_CTRL," bitfld.long 0x8 1. "DYN_ROUTE_SWAP,Enable swapping DYN_ROUTE_SR with DYN_ROUTE register" "0,1" newline bitfld.long 0x8 0. "DYN_ARU_UPDATE_EN,Enable reload of DYN_ROUTE register from ARU itself" "0,1" line.long 0xC "ARU_0_DYN_ROUTE_LOW," hexmask.long.byte 0xC 16.--23. 1. "DYN_READ_ID2,ARU read ID 2" newline hexmask.long.byte 0xC 8.--15. 1. "DYN_READ_ID1,ARU read ID 1" newline hexmask.long.byte 0xC 0.--7. 1. "DYN_READ_ID0,ARU read ID 0" line.long 0x10 "ARU_1_DYN_ROUTE_LOW," hexmask.long.byte 0x10 16.--23. 1. "DYN_READ_ID2,ARU read ID 2" newline hexmask.long.byte 0x10 8.--15. 1. "DYN_READ_ID1,ARU read ID 1" newline hexmask.long.byte 0x10 0.--7. 1. "DYN_READ_ID0,ARU read ID 0" line.long 0x14 "ARU_0_DYN_ROUTE_HIGH," hexmask.long.byte 0x14 24.--27. 1. "DYN_CLK_WAIT,Number of clk cycles for dynamic routing" newline hexmask.long.byte 0x14 16.--23. 1. "DYN_READ_ID5,ARU read ID 5" newline hexmask.long.byte 0x14 8.--15. 1. "DYN_READ_ID4,ARU read ID 4" newline hexmask.long.byte 0x14 0.--7. 1. "DYN_READ_ID3,ARU read ID 3" line.long 0x18 "ARU_1_DYN_ROUTE_HIGH," hexmask.long.byte 0x18 24.--27. 1. "DYN_CLK_WAIT,Number of clk cycles for dynamic routing" newline hexmask.long.byte 0x18 16.--23. 1. "DYN_READ_ID5,ARU read ID 5" newline hexmask.long.byte 0x18 8.--15. 1. "DYN_READ_ID4,ARU read ID 4" newline hexmask.long.byte 0x18 0.--7. 1. "DYN_READ_ID3,ARU read ID 3" line.long 0x1C "ARU_0_DYN_ROUTE_SR_LOW," hexmask.long.byte 0x1C 16.--23. 1. "DYN_READ_ID8,ARU read ID 8" newline hexmask.long.byte 0x1C 8.--15. 1. "DYN_READ_ID7,ARU read ID 7" newline hexmask.long.byte 0x1C 0.--7. 1. "DYN_READ_ID6,ARU read ID 6" line.long 0x20 "ARU_1_DYN_ROUTE_SR_LOW," hexmask.long.byte 0x20 16.--23. 1. "DYN_READ_ID8,ARU read ID 8" newline hexmask.long.byte 0x20 8.--15. 1. "DYN_READ_ID7,ARU read ID 7" newline hexmask.long.byte 0x20 0.--7. 1. "DYN_READ_ID6,ARU read ID 6" line.long 0x24 "ARU_0_DYN_ROUTE_SR_HIGH," bitfld.long 0x24 28. "DYN_UPDATE_EN,Update enable from shadow register" "0,1" newline hexmask.long.byte 0x24 24.--27. 1. "DYN_CLK_WAIT,Number of clk cycles for dynamic routing" newline hexmask.long.byte 0x24 16.--23. 1. "DYN_READ_ID11,ARU read ID 11" newline hexmask.long.byte 0x24 8.--15. 1. "DYN_READ_ID10,ARU read ID 10" newline hexmask.long.byte 0x24 0.--7. 1. "DYN_READ_ID9,ARU read ID 9" line.long 0x28 "ARU_1_DYN_ROUTE_SR_HIGH," bitfld.long 0x28 28. "DYN_UPDATE_EN,Update enable from shadow register" "0,1" newline hexmask.long.byte 0x28 24.--27. 1. "DYN_CLK_WAIT,Number of clk cycles for dynamic routing" newline hexmask.long.byte 0x28 16.--23. 1. "DYN_READ_ID11,ARU read ID 11" newline hexmask.long.byte 0x28 8.--15. 1. "DYN_READ_ID10,ARU read ID 10" newline hexmask.long.byte 0x28 0.--7. 1. "DYN_READ_ID9,ARU read ID 9" line.long 0x2C "ARU_0_DYN_RDADDR," hexmask.long.word 0x2C 0.--8. 1. "DYN_ARU_RDADDR,ARU read address ID to reload the DYN_ROUTE register" line.long 0x30 "ARU_1_DYN_RDADDR," hexmask.long.word 0x30 0.--8. 1. "DYN_ARU_RDADDR,ARU read address ID to reload the DYN_ROUTE register" group.long 0x1FC++0x7B line.long 0x0 "ARU_CADDR," hexmask.long.byte 0x0 16.--22. 1. "CADDR_1,Value of ARU-1 caddr counter" newline hexmask.long.byte 0x0 0.--6. 1. "CADDR_0,Value of ARU-0 caddr counter" line.long 0x4 "BRC_SRC_0_ADDR," bitfld.long 0x4 12. "BRC_MODE,BRC Operation mode select." "0,1" newline hexmask.long.word 0x4 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x8 "BRC_SRC_0_DEST," bitfld.long 0x8 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" newline bitfld.long 0x8 21. "EN_DEST21,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 19. "EN_DEST19,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 18. "EN_DEST18,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 16. "EN_DEST16,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 15. "EN_DEST15,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 13. "EN_DEST13,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 12. "EN_DEST12,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 10. "EN_DEST10,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 9. "EN_DEST9,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 7. "EN_DEST7,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 6. "EN_DEST6,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 4. "EN_DEST4,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 3. "EN_DEST3,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 1. "EN_DEST1,Enable BRC destination address z" "0,1" newline bitfld.long 0x8 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0xC "BRC_SRC_1_ADDR," bitfld.long 0xC 12. "BRC_MODE,BRC Operation mode select." "0,1" newline hexmask.long.word 0xC 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x10 "BRC_SRC_1_DEST," bitfld.long 0x10 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" newline bitfld.long 0x10 21. "EN_DEST21,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 19. "EN_DEST19,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 18. "EN_DEST18,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 16. "EN_DEST16,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 15. "EN_DEST15,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 13. "EN_DEST13,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 12. "EN_DEST12,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 10. "EN_DEST10,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 9. "EN_DEST9,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 7. "EN_DEST7,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 6. "EN_DEST6,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 4. "EN_DEST4,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 3. "EN_DEST3,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 1. "EN_DEST1,Enable BRC destination address z" "0,1" newline bitfld.long 0x10 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x14 "BRC_SRC_2_ADDR," bitfld.long 0x14 12. "BRC_MODE,BRC Operation mode select." "0,1" newline hexmask.long.word 0x14 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x18 "BRC_SRC_2_DEST," bitfld.long 0x18 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" newline bitfld.long 0x18 21. "EN_DEST21,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 19. "EN_DEST19,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 18. "EN_DEST18,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 16. "EN_DEST16,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 15. "EN_DEST15,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 13. "EN_DEST13,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 12. "EN_DEST12,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 10. "EN_DEST10,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 9. "EN_DEST9,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 7. "EN_DEST7,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 6. "EN_DEST6,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 4. "EN_DEST4,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 3. "EN_DEST3,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 1. "EN_DEST1,Enable BRC destination address z" "0,1" newline bitfld.long 0x18 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x1C "BRC_SRC_3_ADDR," bitfld.long 0x1C 12. "BRC_MODE,BRC Operation mode select." "0,1" newline hexmask.long.word 0x1C 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x20 "BRC_SRC_3_DEST," bitfld.long 0x20 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" newline bitfld.long 0x20 21. "EN_DEST21,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 19. "EN_DEST19,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 18. "EN_DEST18,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 16. "EN_DEST16,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 15. "EN_DEST15,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 13. "EN_DEST13,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 12. "EN_DEST12,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 10. "EN_DEST10,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 9. "EN_DEST9,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 7. "EN_DEST7,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 6. "EN_DEST6,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 4. "EN_DEST4,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 3. "EN_DEST3,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 1. "EN_DEST1,Enable BRC destination address z" "0,1" newline bitfld.long 0x20 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x24 "BRC_SRC_4_ADDR," bitfld.long 0x24 12. "BRC_MODE,BRC Operation mode select." "0,1" newline hexmask.long.word 0x24 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x28 "BRC_SRC_4_DEST," bitfld.long 0x28 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" newline bitfld.long 0x28 21. "EN_DEST21,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 19. "EN_DEST19,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 18. "EN_DEST18,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 16. "EN_DEST16,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 15. "EN_DEST15,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 13. "EN_DEST13,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 12. "EN_DEST12,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 10. "EN_DEST10,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 9. "EN_DEST9,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 7. "EN_DEST7,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 6. "EN_DEST6,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 4. "EN_DEST4,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 3. "EN_DEST3,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 1. "EN_DEST1,Enable BRC destination address z" "0,1" newline bitfld.long 0x28 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x2C "BRC_SRC_5_ADDR," bitfld.long 0x2C 12. "BRC_MODE,BRC Operation mode select." "0,1" newline hexmask.long.word 0x2C 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x30 "BRC_SRC_5_DEST," bitfld.long 0x30 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" newline bitfld.long 0x30 21. "EN_DEST21,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 19. "EN_DEST19,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 18. "EN_DEST18,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 16. "EN_DEST16,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 15. "EN_DEST15,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 13. "EN_DEST13,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 12. "EN_DEST12,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 10. "EN_DEST10,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 9. "EN_DEST9,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 7. "EN_DEST7,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 6. "EN_DEST6,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 4. "EN_DEST4,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 3. "EN_DEST3,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 1. "EN_DEST1,Enable BRC destination address z" "0,1" newline bitfld.long 0x30 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x34 "BRC_SRC_6_ADDR," bitfld.long 0x34 12. "BRC_MODE,BRC Operation mode select." "0,1" newline hexmask.long.word 0x34 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x38 "BRC_SRC_6_DEST," bitfld.long 0x38 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" newline bitfld.long 0x38 21. "EN_DEST21,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 19. "EN_DEST19,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 18. "EN_DEST18,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 16. "EN_DEST16,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 15. "EN_DEST15,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 13. "EN_DEST13,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 12. "EN_DEST12,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 10. "EN_DEST10,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 9. "EN_DEST9,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 7. "EN_DEST7,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 6. "EN_DEST6,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 4. "EN_DEST4,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 3. "EN_DEST3,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 1. "EN_DEST1,Enable BRC destination address z" "0,1" newline bitfld.long 0x38 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x3C "BRC_SRC_7_ADDR," bitfld.long 0x3C 12. "BRC_MODE,BRC Operation mode select." "0,1" newline hexmask.long.word 0x3C 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x40 "BRC_SRC_7_DEST," bitfld.long 0x40 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" newline bitfld.long 0x40 21. "EN_DEST21,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 19. "EN_DEST19,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 18. "EN_DEST18,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 16. "EN_DEST16,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 15. "EN_DEST15,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 13. "EN_DEST13,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 12. "EN_DEST12,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 10. "EN_DEST10,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 9. "EN_DEST9,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 7. "EN_DEST7,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 6. "EN_DEST6,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 4. "EN_DEST4,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 3. "EN_DEST3,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 1. "EN_DEST1,Enable BRC destination address z" "0,1" newline bitfld.long 0x40 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x44 "BRC_SRC_8_ADDR," bitfld.long 0x44 12. "BRC_MODE,BRC Operation mode select." "0,1" newline hexmask.long.word 0x44 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x48 "BRC_SRC_8_DEST," bitfld.long 0x48 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" newline bitfld.long 0x48 21. "EN_DEST21,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 19. "EN_DEST19,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 18. "EN_DEST18,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 16. "EN_DEST16,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 15. "EN_DEST15,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 13. "EN_DEST13,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 12. "EN_DEST12,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 10. "EN_DEST10,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 9. "EN_DEST9,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 7. "EN_DEST7,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 6. "EN_DEST6,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 4. "EN_DEST4,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 3. "EN_DEST3,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 1. "EN_DEST1,Enable BRC destination address z" "0,1" newline bitfld.long 0x48 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x4C "BRC_SRC_9_ADDR," bitfld.long 0x4C 12. "BRC_MODE,BRC Operation mode select." "0,1" newline hexmask.long.word 0x4C 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x50 "BRC_SRC_9_DEST," bitfld.long 0x50 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" newline bitfld.long 0x50 21. "EN_DEST21,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 19. "EN_DEST19,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 18. "EN_DEST18,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 16. "EN_DEST16,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 15. "EN_DEST15,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 13. "EN_DEST13,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 12. "EN_DEST12,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 10. "EN_DEST10,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 9. "EN_DEST9,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 7. "EN_DEST7,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 6. "EN_DEST6,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 4. "EN_DEST4,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 3. "EN_DEST3,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 1. "EN_DEST1,Enable BRC destination address z" "0,1" newline bitfld.long 0x50 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x54 "BRC_SRC_10_ADDR," bitfld.long 0x54 12. "BRC_MODE,BRC Operation mode select." "0,1" newline hexmask.long.word 0x54 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x58 "BRC_SRC_10_DEST," bitfld.long 0x58 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" newline bitfld.long 0x58 21. "EN_DEST21,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 19. "EN_DEST19,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 18. "EN_DEST18,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 16. "EN_DEST16,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 15. "EN_DEST15,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 13. "EN_DEST13,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 12. "EN_DEST12,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 10. "EN_DEST10,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 9. "EN_DEST9,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 7. "EN_DEST7,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 6. "EN_DEST6,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 4. "EN_DEST4,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 3. "EN_DEST3,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 1. "EN_DEST1,Enable BRC destination address z" "0,1" newline bitfld.long 0x58 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x5C "BRC_SRC_11_ADDR," bitfld.long 0x5C 12. "BRC_MODE,BRC Operation mode select." "0,1" newline hexmask.long.word 0x5C 0.--8. 1. "ADDR,Source ARU address. Define an ARU read address used as data source for input channel x (x:0...11)." line.long 0x60 "BRC_SRC_11_DEST," bitfld.long 0x60 22. "EN_TRASHBIN,Control trash bin functionality." "0,1" newline bitfld.long 0x60 21. "EN_DEST21,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 20. "EN_DEST20,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 19. "EN_DEST19,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 18. "EN_DEST18,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 17. "EN_DEST17,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 16. "EN_DEST16,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 15. "EN_DEST15,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 14. "EN_DEST14,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 13. "EN_DEST13,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 12. "EN_DEST12,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 11. "EN_DEST11,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 10. "EN_DEST10,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 9. "EN_DEST9,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 8. "EN_DEST8,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 7. "EN_DEST7,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 6. "EN_DEST6,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 5. "EN_DEST5,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 4. "EN_DEST4,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 3. "EN_DEST3,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 2. "EN_DEST2,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 1. "EN_DEST1,Enable BRC destination address z" "0,1" newline bitfld.long 0x60 0. "EN_DEST0,Enable BRC destination address z" "0,1" line.long 0x64 "BRC_IRQ_NOTIFY," bitfld.long 0x64 12. "DID11,Data inconsistency occurred in MTM mode for channel [y]." "0,1" newline bitfld.long 0x64 11. "DID10,Data inconsistency occurred in MTM mode for channel [y]." "0,1" newline bitfld.long 0x64 10. "DID9,Data inconsistency occurred in MTM mode for channel [y]." "0,1" newline bitfld.long 0x64 9. "DID8,Data inconsistency occurred in MTM mode for channel [y]." "0,1" newline bitfld.long 0x64 8. "DID7,Data inconsistency occurred in MTM mode for channel [y]." "0,1" newline bitfld.long 0x64 7. "DID6,Data inconsistency occurred in MTM mode for channel [y]." "0,1" newline bitfld.long 0x64 6. "DID5,Data inconsistency occurred in MTM mode for channel [y]." "0,1" newline bitfld.long 0x64 5. "DID4,Data inconsistency occurred in MTM mode for channel [y]." "0,1" newline bitfld.long 0x64 4. "DID3,Data inconsistency occurred in MTM mode for channel [y]." "0,1" newline bitfld.long 0x64 3. "DID2,Data inconsistency occurred in MTM mode for channel [y]." "0,1" newline bitfld.long 0x64 2. "DID1,Data inconsistency occurred in MTM mode for channel [y]." "0,1" newline bitfld.long 0x64 1. "DID0,Data inconsistency occurred in MTM mode for channel [y]." "0,1" newline bitfld.long 0x64 0. "DEST_ERR,Configuration error interrupt for BRC sub-module" "0,1" line.long 0x68 "BRC_IRQ_EN," bitfld.long 0x68 12. "DID_IRQ_EN11,Enable BRC_DID_IRQ for channel [y]" "0,1" newline bitfld.long 0x68 11. "DID_IRQ_EN10,Enable BRC_DID_IRQ for channel [y]" "0,1" newline bitfld.long 0x68 10. "DID_IRQ_EN9,Enable BRC_DID_IRQ for channel [y]" "0,1" newline bitfld.long 0x68 9. "DID_IRQ_EN8,Enable BRC_DID_IRQ for channel [y]" "0,1" newline bitfld.long 0x68 8. "DID_IRQ_EN7,Enable BRC_DID_IRQ for channel [y]" "0,1" newline bitfld.long 0x68 7. "DID_IRQ_EN6,Enable BRC_DID_IRQ for channel [y]" "0,1" newline bitfld.long 0x68 6. "DID_IRQ_EN5,Enable BRC_DID_IRQ for channel [y]" "0,1" newline bitfld.long 0x68 5. "DID_IRQ_EN4,Enable BRC_DID_IRQ for channel [y]" "0,1" newline bitfld.long 0x68 4. "DID_IRQ_EN3,Enable BRC_DID_IRQ for channel [y]" "0,1" newline bitfld.long 0x68 3. "DID_IRQ_EN2,Enable BRC_DID_IRQ for channel [y]" "0,1" newline bitfld.long 0x68 2. "DID_IRQ_EN1,Enable BRC_DID_IRQ for channel [y]" "0,1" newline bitfld.long 0x68 1. "DID_IRQ_EN0,Enable BRC_DID_IRQ for channel [y]" "0,1" newline bitfld.long 0x68 0. "DEST_ERR_IRQ_EN,BRC_DEST_ERR_IRQ interrupt enable" "0,1" line.long 0x6C "BRC_IRQ_FORCINT," bitfld.long 0x6C 12. "TRG_DID11,Trigger DID channel [y] interrupt" "0,1" newline bitfld.long 0x6C 11. "TRG_DID10,Trigger DID channel [y] interrupt" "0,1" newline bitfld.long 0x6C 10. "TRG_DID9,Trigger DID channel [y] interrupt" "0,1" newline bitfld.long 0x6C 9. "TRG_DID8,Trigger DID channel [y] interrupt" "0,1" newline bitfld.long 0x6C 8. "TRG_DID7,Trigger DID channel [y] interrupt" "0,1" newline bitfld.long 0x6C 7. "TRG_DID6,Trigger DID channel [y] interrupt" "0,1" newline bitfld.long 0x6C 6. "TRG_DID5,Trigger DID channel [y] interrupt" "0,1" newline bitfld.long 0x6C 5. "TRG_DID4,Trigger DID channel [y] interrupt" "0,1" newline bitfld.long 0x6C 4. "TRG_DID3,Trigger DID channel [y] interrupt" "0,1" newline bitfld.long 0x6C 3. "TRG_DID2,Trigger DID channel [y] interrupt" "0,1" newline bitfld.long 0x6C 2. "TRG_DID1,Trigger DID channel [y] interrupt" "0,1" newline bitfld.long 0x6C 1. "TRG_DID0,Trigger DID channel [y] interrupt" "0,1" newline bitfld.long 0x6C 0. "TRG_DEST_ERR,Trigger destination error interrupt." "0,1" line.long 0x70 "BRC_IRQ_MODE," bitfld.long 0x70 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x74 "BRC_RST," bitfld.long 0x74 0. "RST,Software reset" "0,1" line.long 0x78 "BRC_EIRQ_EN," bitfld.long 0x78 12. "DID_EIRQ_EN11,Enable BRC_DID_EIRQ for channel y" "0,1" newline bitfld.long 0x78 11. "DID_EIRQ_EN10,Enable BRC_DID_EIRQ for channel y" "0,1" newline bitfld.long 0x78 10. "DID_EIRQ_EN9,Enable BRC_DID_EIRQ for channel y" "0,1" newline bitfld.long 0x78 9. "DID_EIRQ_EN8,Enable BRC_DID_EIRQ for channel y" "0,1" newline bitfld.long 0x78 8. "DID_EIRQ_EN7,Enable BRC_DID_EIRQ for channel y" "0,1" newline bitfld.long 0x78 7. "DID_EIRQ_EN6,Enable BRC_DID_EIRQ for channel y" "0,1" newline bitfld.long 0x78 6. "DID_EIRQ_EN5,Enable BRC_DID_EIRQ for channel y" "0,1" newline bitfld.long 0x78 5. "DID_EIRQ_EN4,Enable BRC_DID_EIRQ for channel y" "0,1" newline bitfld.long 0x78 4. "DID_EIRQ_EN3,Enable BRC_DID_EIRQ for channel y" "0,1" newline bitfld.long 0x78 3. "DID_EIRQ_EN2,Enable BRC_DID_EIRQ for channel y" "0,1" newline bitfld.long 0x78 2. "DID_EIRQ_EN1,Enable BRC_DID_EIRQ for channel y" "0,1" newline bitfld.long 0x78 1. "DID_EIRQ_EN0,Enable BRC_DID_EIRQ for channel y" "0,1" newline bitfld.long 0x78 0. "DEST_ERR_EIRQ_EN,BRC_DEST_ERR_EIRQ error interrupt enable" "0,1" group.long 0x400++0x17 line.long 0x0 "ICM_IRQG_0," bitfld.long 0x0 31. "PSM1_CH7_IRQ,PSM1 shared sub-module channel x interrupt." "0,1" newline bitfld.long 0x0 30. "PSM1_CH6_IRQ,PSM1 shared sub-module channel x interrupt." "0,1" newline bitfld.long 0x0 29. "PSM1_CH5_IRQ,PSM1 shared sub-module channel x interrupt." "0,1" newline bitfld.long 0x0 28. "PSM1_CH4_IRQ,PSM1 shared sub-module channel x interrupt." "0,1" newline bitfld.long 0x0 27. "PSM1_CH3_IRQ,PSM1 shared sub-module channel x interrupt." "0,1" newline bitfld.long 0x0 26. "PSM1_CH2_IRQ,PSM1 shared sub-module channel x interrupt." "0,1" newline bitfld.long 0x0 25. "PSM1_CH1_IRQ,PSM1 shared sub-module channel x interrupt." "0,1" newline bitfld.long 0x0 24. "PSM1_CH0_IRQ,PSM1 shared sub-module channel x interrupt." "0,1" newline bitfld.long 0x0 23. "PSM0_CH7_IRQ,PSM0 shared sub-module channel x interrupt." "0,1" newline bitfld.long 0x0 22. "PSM0_CH6_IRQ,PSM0 shared sub-module channel x interrupt." "0,1" newline bitfld.long 0x0 21. "PSM0_CH5_IRQ,PSM0 shared sub-module channel x interrupt." "0,1" newline bitfld.long 0x0 20. "PSM0_CH4_IRQ,PSM0 shared sub-module channel x interrupt." "0,1" newline bitfld.long 0x0 19. "PSM0_CH3_IRQ,PSM0 shared sub-module channel x interrupt." "0,1" newline bitfld.long 0x0 18. "PSM0_CH2_IRQ,PSM0 shared sub-module channel x interrupt." "0,1" newline bitfld.long 0x0 17. "PSM0_CH1_IRQ,PSM0 shared sub-module channel x interrupt." "0,1" newline bitfld.long 0x0 16. "PSM0_CH0_IRQ,PSM0 shared sub-module channel x interrupt." "0,1" newline bitfld.long 0x0 13. "SPE7_IRQ,SPE[j] shared sub-module interrupt." "0,1" newline bitfld.long 0x0 12. "SPE6_IRQ,SPE[j] shared sub-module interrupt." "0,1" newline bitfld.long 0x0 11. "SPE5_IRQ,SPE[j] shared sub-module interrupt." "0,1" newline bitfld.long 0x0 10. "SPE4_IRQ,SPE[j] shared sub-module interrupt." "0,1" newline bitfld.long 0x0 9. "SPE3_IRQ,SPE[j] shared sub-module interrupt." "0,1" newline bitfld.long 0x0 8. "SPE2_IRQ,SPE[j] shared sub-module interrupt." "0,1" newline bitfld.long 0x0 7. "SPE1_IRQ,SPE[j] shared sub-module interrupt." "0,1" newline bitfld.long 0x0 6. "SPE0_IRQ,SPE[j] shared sub-module interrupt." "0,1" newline bitfld.long 0x0 5. "CMP_IRQ,CMP shared sub-module interrupt." "0,1" newline bitfld.long 0x0 4. "AEI_IRQ,AEI_IRQ: AEI_IRQ interrupt." "0,1" newline bitfld.long 0x0 3. "BRC_IRQ,BRC shared sub-module interrupt." "0,1" newline bitfld.long 0x0 2. "ARU_ACC_ACK_IRQ,ARU_ACC_ACK interrupt." "0,1" newline bitfld.long 0x0 1. "ARU_NEW_DATA1_IRQ,ARU_NEW_DATA1 interrupt." "0,1" newline bitfld.long 0x0 0. "ARU_NEW_DATA0_IRQ,ARU_NEW_DATA0 interrupt" "0,1" line.long 0x4 "ICM_IRQG_1," bitfld.long 0x4 26. "DPLL_SORI_IRQ,DPLL calculated duration interrupt for state." "0,1" newline bitfld.long 0x4 25. "DPLL_TORI_IRQ,DPLL calculated duration interrupt for state." "0,1" newline bitfld.long 0x4 24. "DPLL_CDSI_IRQ,DPLL calculated duration interrupt for state." "0,1" newline bitfld.long 0x4 23. "DPLL_CDTI_IRQ,DPLL calculated duration interrupt for trigger." "0,1" newline bitfld.long 0x4 22. "DPLL_TE4I_IRQ,TRIGGER event interrupt 4." "0,1" newline bitfld.long 0x4 21. "DPLL_TE3I_IRQ,TRIGGER event interrupt 3." "0,1" newline bitfld.long 0x4 20. "DPLL_TE2I_IRQ,TRIGGER event interrupt 2." "0,1" newline bitfld.long 0x4 19. "DPLL_TE1I_IRQ,TRIGGER event interrupt 1." "0,1" newline bitfld.long 0x4 18. "DPLL_TE0I_IRQ,TRIGGER event interrupt 0." "0,1" newline bitfld.long 0x4 17. "DPLL_LL2I_IRQ,Lost of lock interrupt for SUB_INC2." "0,1" newline bitfld.long 0x4 16. "DPLL_GL2I_IRQ,Get of lock interrupt for SUB_INC2." "0,1" newline bitfld.long 0x4 15. "DPLL_EI_IRQ,Error interrupt." "0,1" newline bitfld.long 0x4 14. "DPLL_LL1I_IRQ,Lost of lock interrupt for SUB_INC1." "0,1" newline bitfld.long 0x4 13. "DPLL_GL1I_IRQ,Get of lock interrupt for SUB_INC1." "0,1" newline bitfld.long 0x4 12. "DPLL_W1I_IRQ,Write access to RAM region 1b or 1c interrupt." "0,1" newline bitfld.long 0x4 11. "DPLL_W2I_IRQ,Write access to RAM region 2 interrupt." "0,1" newline bitfld.long 0x4 10. "DPLL_PWI_IRQ,Plausibility window (PVT) violation interrupt of TRIGGER." "0,1" newline bitfld.long 0x4 9. "DPLL_TASI_IRQ,TRIGGER active slope detected while NTI_CNT is zero." "0,1" newline bitfld.long 0x4 8. "DPLL_SASI_IRQ,STATE active slope detected." "0,1" newline bitfld.long 0x4 7. "DPLL_MTI_IRQ,Missing TRIGGER interrupt." "0,1" newline bitfld.long 0x4 6. "DPLL_MSI_IRQ,Missing STATE interrupt." "0,1" newline bitfld.long 0x4 5. "DPLL_TISI_IRQ,TRIGGER inactive slope detected interrupt." "0,1" newline bitfld.long 0x4 4. "DPLL_SISI_IRQ,STATE inactive slope detected interrupt." "0,1" newline bitfld.long 0x4 3. "DPLL_TAXI_IRQ,TRIGGER maximum hold time (THMA) violation detected interrupt." "0,1" newline bitfld.long 0x4 2. "DPLL_TINI_IRQ,TRIGGER minimum hold time (THMI) violation detected interrupt." "0,1" newline bitfld.long 0x4 1. "DPLL_EDI_IRQ,DPLL enable/disable interrupt." "0,1" newline bitfld.long 0x4 0. "DPLL_DCGI_IRQ,TRIGGER direction change detected." "0,1" line.long 0x8 "ICM_IRQG_2," bitfld.long 0x8 31. "TIM3_CH7_IRQ,TIM3 shared interrupt channel x." "0,1" newline bitfld.long 0x8 30. "TIM3_CH6_IRQ,TIM3 shared interrupt channel x." "0,1" newline bitfld.long 0x8 29. "TIM3_CH5_IRQ,TIM3 shared interrupt channel x." "0,1" newline bitfld.long 0x8 28. "TIM3_CH4_IRQ,TIM3 shared interrupt channel x." "0,1" newline bitfld.long 0x8 27. "TIM3_CH3_IRQ,TIM3 shared interrupt channel x." "0,1" newline bitfld.long 0x8 26. "TIM3_CH2_IRQ,TIM3 shared interrupt channel x." "0,1" newline bitfld.long 0x8 25. "TIM3_CH1_IRQ,TIM3 shared interrupt channel x." "0,1" newline bitfld.long 0x8 24. "TIM3_CH0_IRQ,TIM3 shared interrupt channel x." "0,1" newline bitfld.long 0x8 23. "TIM2_CH7_IRQ,TIM2 shared interrupt channel x." "0,1" newline bitfld.long 0x8 22. "TIM2_CH6_IRQ,TIM2 shared interrupt channel x." "0,1" newline bitfld.long 0x8 21. "TIM2_CH5_IRQ,TIM2 shared interrupt channel x." "0,1" newline bitfld.long 0x8 20. "TIM2_CH4_IRQ,TIM2 shared interrupt channel x." "0,1" newline bitfld.long 0x8 19. "TIM2_CH3_IRQ,TIM2 shared interrupt channel x." "0,1" newline bitfld.long 0x8 18. "TIM2_CH2_IRQ,TIM2 shared interrupt channel x." "0,1" newline bitfld.long 0x8 17. "TIM2_CH1_IRQ,TIM2 shared interrupt channel x." "0,1" newline bitfld.long 0x8 16. "TIM2_CH0_IRQ,TIM2 shared interrupt channel x." "0,1" newline bitfld.long 0x8 15. "TIM1_CH7_IRQ,TIM1 shared interrupt channel x." "0,1" newline bitfld.long 0x8 14. "TIM1_CH6_IRQ,TIM1 shared interrupt channel x." "0,1" newline bitfld.long 0x8 13. "TIM1_CH5_IRQ,TIM1 shared interrupt channel x." "0,1" newline bitfld.long 0x8 12. "TIM1_CH4_IRQ,TIM1 shared interrupt channel x." "0,1" newline bitfld.long 0x8 11. "TIM1_CH3_IRQ,TIM1 shared interrupt channel x." "0,1" newline bitfld.long 0x8 10. "TIM1_CH2_IRQ,TIM1 shared interrupt channel x." "0,1" newline bitfld.long 0x8 9. "TIM1_CH1_IRQ,TIM1 shared interrupt channel x." "0,1" newline bitfld.long 0x8 8. "TIM1_CH0_IRQ,TIM1 shared interrupt channel x." "0,1" newline bitfld.long 0x8 7. "TIM0_CH7_IRQ,TIM0 shared interrupt channel x." "0,1" newline bitfld.long 0x8 6. "TIM0_CH6_IRQ,TIM0 shared interrupt channel x." "0,1" newline bitfld.long 0x8 5. "TIM0_CH5_IRQ,TIM0 shared interrupt channel x." "0,1" newline bitfld.long 0x8 4. "TIM0_CH4_IRQ,TIM0 shared interrupt channel x." "0,1" newline bitfld.long 0x8 3. "TIM0_CH3_IRQ,TIM0 shared interrupt channel x." "0,1" newline bitfld.long 0x8 2. "TIM0_CH2_IRQ,TIM0 shared interrupt channel x." "0,1" newline bitfld.long 0x8 1. "TIM0_CH1_IRQ,TIM0 shared interrupt channel x." "0,1" newline bitfld.long 0x8 0. "TIM0_CH0_IRQ,TIM0 shared interrupt channel x." "0,1" line.long 0xC "ICM_IRQG_3," bitfld.long 0xC 31. "TIM7_CH7_IRQ,TIM7 shared interrupt channel x." "0,1" newline bitfld.long 0xC 30. "TIM7_CH6_IRQ,TIM7 shared interrupt channel x." "0,1" newline bitfld.long 0xC 29. "TIM7_CH5_IRQ,TIM7 shared interrupt channel x." "0,1" newline bitfld.long 0xC 28. "TIM7_CH4_IRQ,TIM7 shared interrupt channel x." "0,1" newline bitfld.long 0xC 27. "TIM7_CH3_IRQ,TIM7 shared interrupt channel x." "0,1" newline bitfld.long 0xC 26. "TIM7_CH2_IRQ,TIM7 shared interrupt channel x." "0,1" newline bitfld.long 0xC 25. "TIM7_CH1_IRQ,TIM7 shared interrupt channel x." "0,1" newline bitfld.long 0xC 24. "TIM7_CH0_IRQ,TIM7 shared interrupt channel x." "0,1" newline bitfld.long 0xC 23. "TIM6_CH7_IRQ,TIM6 shared interrupt channel x." "0,1" newline bitfld.long 0xC 22. "TIM6_CH6_IRQ,TIM6 shared interrupt channel x." "0,1" newline bitfld.long 0xC 21. "TIM6_CH5_IRQ,TIM6 shared interrupt channel x." "0,1" newline bitfld.long 0xC 20. "TIM6_CH4_IRQ,TIM6 shared interrupt channel x." "0,1" newline bitfld.long 0xC 19. "TIM6_CH3_IRQ,TIM6 shared interrupt channel x." "0,1" newline bitfld.long 0xC 18. "TIM6_CH2_IRQ,TIM6 shared interrupt channel x." "0,1" newline bitfld.long 0xC 17. "TIM6_CH1_IRQ,TIM6 shared interrupt channel x." "0,1" newline bitfld.long 0xC 16. "TIM6_CH0_IRQ,TIM6 shared interrupt channel x." "0,1" newline bitfld.long 0xC 15. "TIM5_CH7_IRQ,TIM5 shared interrupt channel x." "0,1" newline bitfld.long 0xC 14. "TIM5_CH6_IRQ,TIM5 shared interrupt channel x." "0,1" newline bitfld.long 0xC 13. "TIM5_CH5_IRQ,TIM5 shared interrupt channel x." "0,1" newline bitfld.long 0xC 12. "TIM5_CH4_IRQ,TIM5 shared interrupt channel x." "0,1" newline bitfld.long 0xC 11. "TIM5_CH3_IRQ,TIM5 shared interrupt channel x." "0,1" newline bitfld.long 0xC 10. "TIM5_CH2_IRQ,TIM5 shared interrupt channel x." "0,1" newline bitfld.long 0xC 9. "TIM5_CH1_IRQ,TIM5 shared interrupt channel x." "0,1" newline bitfld.long 0xC 8. "TIM5_CH0_IRQ,TIM5 shared interrupt channel x." "0,1" newline bitfld.long 0xC 7. "TIM4_CH7_IRQ,TIM4 shared interrupt channel x." "0,1" newline bitfld.long 0xC 6. "TIM4_CH6_IRQ,TIM4 shared interrupt channel x." "0,1" newline bitfld.long 0xC 5. "TIM4_CH5_IRQ,TIM4 shared interrupt channel x." "0,1" newline bitfld.long 0xC 4. "TIM4_CH4_IRQ,TIM4 shared interrupt channel x." "0,1" newline bitfld.long 0xC 3. "TIM4_CH3_IRQ,TIM4 shared interrupt channel x." "0,1" newline bitfld.long 0xC 2. "TIM4_CH2_IRQ,TIM4 shared interrupt channel x." "0,1" newline bitfld.long 0xC 1. "TIM4_CH1_IRQ,TIM4 shared interrupt channel x." "0,1" newline bitfld.long 0xC 0. "TIM4_CH0_IRQ,TIM4 shared interrupt channel x." "0,1" line.long 0x10 "ICM_IRQG_4," bitfld.long 0x10 31. "MCS3_CH7_IRQ,MCS3 channel x interrupt." "0,1" newline bitfld.long 0x10 30. "MCS3_CH6_IRQ,MCS3 channel x interrupt." "0,1" newline bitfld.long 0x10 29. "MCS3_CH5_IRQ,MCS3 channel x interrupt." "0,1" newline bitfld.long 0x10 28. "MCS3_CH4_IRQ,MCS3 channel x interrupt." "0,1" newline bitfld.long 0x10 27. "MCS3_CH3_IRQ,MCS3 channel x interrupt." "0,1" newline bitfld.long 0x10 26. "MCS3_CH2_IRQ,MCS3 channel x interrupt." "0,1" newline bitfld.long 0x10 25. "MCS3_CH1_IRQ,MCS3 channel x interrupt." "0,1" newline bitfld.long 0x10 24. "MCS3_CH0_IRQ,MCS3 channel x interrupt." "0,1" newline bitfld.long 0x10 23. "MCS2_CH7_IRQ,MCS2 channel x interrupt." "0,1" newline bitfld.long 0x10 22. "MCS2_CH6_IRQ,MCS2 channel x interrupt." "0,1" newline bitfld.long 0x10 21. "MCS2_CH5_IRQ,MCS2 channel x interrupt." "0,1" newline bitfld.long 0x10 20. "MCS2_CH4_IRQ,MCS2 channel x interrupt." "0,1" newline bitfld.long 0x10 19. "MCS2_CH3_IRQ,MCS2 channel x interrupt." "0,1" newline bitfld.long 0x10 18. "MCS2_CH2_IRQ,MCS2 channel x interrupt." "0,1" newline bitfld.long 0x10 17. "MCS2_CH1_IRQ,MCS2 channel x interrupt." "0,1" newline bitfld.long 0x10 16. "MCS2_CH0_IRQ,MCS2 channel x interrupt." "0,1" newline bitfld.long 0x10 15. "MCS1_CH7_IRQ,MCS1 channel x interrupt." "0,1" newline bitfld.long 0x10 14. "MCS1_CH6_IRQ,MCS1 channel x interrupt." "0,1" newline bitfld.long 0x10 13. "MCS1_CH5_IRQ,MCS1 channel x interrupt." "0,1" newline bitfld.long 0x10 12. "MCS1_CH4_IRQ,MCS1 channel x interrupt." "0,1" newline bitfld.long 0x10 11. "MCS1_CH3_IRQ,MCS1 channel x interrupt." "0,1" newline bitfld.long 0x10 10. "MCS1_CH2_IRQ,MCS1 channel x interrupt." "0,1" newline bitfld.long 0x10 9. "MCS1_CH1_IRQ,MCS1 channel x interrupt." "0,1" newline bitfld.long 0x10 8. "MCS1_CH0_IRQ,MCS1 channel x interrupt." "0,1" newline bitfld.long 0x10 7. "MCS0_CH7_IRQ,MCS0 channel x interrupt" "0,1" newline bitfld.long 0x10 6. "MCS0_CH6_IRQ,MCS0 channel x interrupt" "0,1" newline bitfld.long 0x10 5. "MCS0_CH5_IRQ,MCS0 channel x interrupt" "0,1" newline bitfld.long 0x10 4. "MCS0_CH4_IRQ,MCS0 channel x interrupt" "0,1" newline bitfld.long 0x10 3. "MCS0_CH3_IRQ,MCS0 channel x interrupt" "0,1" newline bitfld.long 0x10 2. "MCS0_CH2_IRQ,MCS0 channel x interrupt" "0,1" newline bitfld.long 0x10 1. "MCS0_CH1_IRQ,MCS0 channel x interrupt" "0,1" newline bitfld.long 0x10 0. "MCS0_CH0_IRQ,MCS0 channel x interrupt" "0,1" line.long 0x14 "ICM_IRQG_5," bitfld.long 0x14 31. "MCS7_CH7_IRQ,MCS7 channel x interrupt." "0,1" newline bitfld.long 0x14 30. "MCS7_CH6_IRQ,MCS7 channel x interrupt." "0,1" newline bitfld.long 0x14 29. "MCS7_CH5_IRQ,MCS7 channel x interrupt." "0,1" newline bitfld.long 0x14 28. "MCS7_CH4_IRQ,MCS7 channel x interrupt." "0,1" newline bitfld.long 0x14 27. "MCS7_CH3_IRQ,MCS7 channel x interrupt." "0,1" newline bitfld.long 0x14 26. "MCS7_CH2_IRQ,MCS7 channel x interrupt." "0,1" newline bitfld.long 0x14 25. "MCS7_CH1_IRQ,MCS7 channel x interrupt." "0,1" newline bitfld.long 0x14 24. "MCS7_CH0_IRQ,MCS7 channel x interrupt." "0,1" newline bitfld.long 0x14 23. "MCS6_CH7_IRQ,MCS1 channel x interrupt." "0,1" newline bitfld.long 0x14 22. "MCS6_CH6_IRQ,MCS1 channel x interrupt." "0,1" newline bitfld.long 0x14 21. "MCS6_CH5_IRQ,MCS1 channel x interrupt." "0,1" newline bitfld.long 0x14 20. "MCS6_CH4_IRQ,MCS1 channel x interrupt." "0,1" newline bitfld.long 0x14 19. "MCS6_CH3_IRQ,MCS1 channel x interrupt." "0,1" newline bitfld.long 0x14 18. "MCS6_CH2_IRQ,MCS1 channel x interrupt." "0,1" newline bitfld.long 0x14 17. "MCS6_CH1_IRQ,MCS1 channel x interrupt." "0,1" newline bitfld.long 0x14 16. "MCS6_CH0_IRQ,MCS1 channel x interrupt." "0,1" newline bitfld.long 0x14 15. "MCS5_CH7_IRQ,MCS5 channel x interrupt." "0,1" newline bitfld.long 0x14 14. "MCS5_CH6_IRQ,MCS5 channel x interrupt." "0,1" newline bitfld.long 0x14 13. "MCS5_CH5_IRQ,MCS5 channel x interrupt." "0,1" newline bitfld.long 0x14 12. "MCS5_CH4_IRQ,MCS5 channel x interrupt." "0,1" newline bitfld.long 0x14 11. "MCS5_CH3_IRQ,MCS5 channel x interrupt." "0,1" newline bitfld.long 0x14 10. "MCS5_CH2_IRQ,MCS5 channel x interrupt." "0,1" newline bitfld.long 0x14 9. "MCS5_CH1_IRQ,MCS5 channel x interrupt." "0,1" newline bitfld.long 0x14 8. "MCS5_CH0_IRQ,MCS5 channel x interrupt." "0,1" newline bitfld.long 0x14 7. "MCS4_CH7_IRQ,MCS4 channel x interrupt" "0,1" newline bitfld.long 0x14 6. "MCS4_CH6_IRQ,MCS4 channel x interrupt" "0,1" newline bitfld.long 0x14 5. "MCS4_CH5_IRQ,MCS4 channel x interrupt" "0,1" newline bitfld.long 0x14 4. "MCS4_CH4_IRQ,MCS4 channel x interrupt" "0,1" newline bitfld.long 0x14 3. "MCS4_CH3_IRQ,MCS4 channel x interrupt" "0,1" newline bitfld.long 0x14 2. "MCS4_CH2_IRQ,MCS4 channel x interrupt" "0,1" newline bitfld.long 0x14 1. "MCS4_CH1_IRQ,MCS4 channel x interrupt" "0,1" newline bitfld.long 0x14 0. "MCS4_CH0_IRQ,MCS4 channel x interrupt" "0,1" group.long 0x430++0x17 line.long 0x0 "ICM_IRQG_MEI," bitfld.long 0x0 25. "DPLL_EIRQ,DPLL error interrupt." "0,1" newline bitfld.long 0x0 24. "CMP_EIRQ,CMP error interrupt." "0,1" newline bitfld.long 0x0 23. "SPE3_EIRQ,SPE[j] error interrupt." "0,1" newline bitfld.long 0x0 22. "SPE2_EIRQ,SPE[j] error interrupt." "0,1" newline bitfld.long 0x0 21. "SPE1_EIRQ,SPE[j] error interrupt." "0,1" newline bitfld.long 0x0 20. "SPE0_EIRQ,SPE[j] error interrupt." "0,1" newline bitfld.long 0x0 19. "MCS7_EIRQ,MCS[j] error interrupt." "0,1" newline bitfld.long 0x0 18. "MCS6_EIRQ,MCS[j] error interrupt." "0,1" newline bitfld.long 0x0 17. "MCS5_EIRQ,MCS[j] error interrupt." "0,1" newline bitfld.long 0x0 16. "MCS4_EIRQ,MCS[j] error interrupt." "0,1" newline bitfld.long 0x0 15. "MCS3_EIRQ,MCS[j] error interrupt." "0,1" newline bitfld.long 0x0 14. "MCS2_EIRQ,MCS[j] error interrupt." "0,1" newline bitfld.long 0x0 13. "MCS1_EIRQ,MCS[j] error interrupt." "0,1" newline bitfld.long 0x0 12. "MCS0_EIRQ,MCS[j] error interrupt." "0,1" newline bitfld.long 0x0 11. "TIM7_EIRQ,TIM[j] error interrupt." "0,1" newline bitfld.long 0x0 10. "TIM6_EIRQ,TIM[j] error interrupt." "0,1" newline bitfld.long 0x0 9. "TIM5_EIRQ,TIM[j] error interrupt." "0,1" newline bitfld.long 0x0 8. "TIM4_EIRQ,TIM[j] error interrupt." "0,1" newline bitfld.long 0x0 7. "TIM3_EIRQ,TIM[j] error interrupt." "0,1" newline bitfld.long 0x0 6. "TIM2_EIRQ,TIM[j] error interrupt." "0,1" newline bitfld.long 0x0 5. "TIM1_EIRQ,TIM[j] error interrupt." "0,1" newline bitfld.long 0x0 4. "TIM0_EIRQ,TIM[j] error interrupt." "0,1" newline bitfld.long 0x0 3. "FIFO1_EIRQ,FIFO[j] error interrupt." "0,1" newline bitfld.long 0x0 2. "FIFO0_EIRQ,FIFO[j] error interrupt." "0,1" newline bitfld.long 0x0 1. "BRC_EIRQ,BRC error interrupt." "0,1" newline bitfld.long 0x0 0. "GTM_EIRQ,AEI Error interrupt request" "0,1" line.long 0x4 "ICM_IRQG_CEI0," bitfld.long 0x4 23. "FIFO2_CH7_EIRQ,FIFO2 channel x error interrupt." "0,1" newline bitfld.long 0x4 22. "FIFO2_CH6_EIRQ,FIFO2 channel x error interrupt." "0,1" newline bitfld.long 0x4 21. "FIFO2_CH5_EIRQ,FIFO2 channel x error interrupt." "0,1" newline bitfld.long 0x4 20. "FIFO2_CH4_EIRQ,FIFO2 channel x error interrupt." "0,1" newline bitfld.long 0x4 19. "FIFO2_CH3_EIRQ,FIFO2 channel x error interrupt." "0,1" newline bitfld.long 0x4 18. "FIFO2_CH2_EIRQ,FIFO2 channel x error interrupt." "0,1" newline bitfld.long 0x4 17. "FIFO2_CH1_EIRQ,FIFO2 channel x error interrupt." "0,1" newline bitfld.long 0x4 16. "FIFO2_CH0_EIRQ,FIFO2 channel x error interrupt." "0,1" newline bitfld.long 0x4 15. "FIFO1_CH7_EIRQ,FIFO1 channel x error interrupt." "0,1" newline bitfld.long 0x4 14. "FIFO1_CH6_EIRQ,FIFO1 channel x error interrupt." "0,1" newline bitfld.long 0x4 13. "FIFO1_CH5_EIRQ,FIFO1 channel x error interrupt." "0,1" newline bitfld.long 0x4 12. "FIFO1_CH4_EIRQ,FIFO1 channel x error interrupt." "0,1" newline bitfld.long 0x4 11. "FIFO1_CH3_EIRQ,FIFO1 channel x error interrupt." "0,1" newline bitfld.long 0x4 10. "FIFO1_CH2_EIRQ,FIFO1 channel x error interrupt." "0,1" newline bitfld.long 0x4 9. "FIFO1_CH1_EIRQ,FIFO1 channel x error interrupt." "0,1" newline bitfld.long 0x4 8. "FIFO1_CH0_EIRQ,FIFO1 channel x error interrupt." "0,1" newline bitfld.long 0x4 7. "FIFO0_CH7_EIRQ,FIFO0 channel x error interrupt" "0,1" newline bitfld.long 0x4 6. "FIFO0_CH6_EIRQ,FIFO0 channel x error interrupt" "0,1" newline bitfld.long 0x4 5. "FIFO0_CH5_EIRQ,FIFO0 channel x error interrupt" "0,1" newline bitfld.long 0x4 4. "FIFO0_CH4_EIRQ,FIFO0 channel x error interrupt" "0,1" newline bitfld.long 0x4 3. "FIFO0_CH3_EIRQ,FIFO0 channel x error interrupt" "0,1" newline bitfld.long 0x4 2. "FIFO0_CH2_EIRQ,FIFO0 channel x error interrupt" "0,1" newline bitfld.long 0x4 1. "FIFO0_CH1_EIRQ,FIFO0 channel x error interrupt" "0,1" newline bitfld.long 0x4 0. "FIFO0_CH0_EIRQ,FIFO0 channel x error interrupt" "0,1" line.long 0x8 "ICM_IRQG_CEI1," bitfld.long 0x8 31. "TIM3_CH7_EIRQ,TIM3 channel x error interrupt." "0,1" newline bitfld.long 0x8 30. "TIM3_CH6_EIRQ,TIM3 channel x error interrupt." "0,1" newline bitfld.long 0x8 29. "TIM3_CH5_EIRQ,TIM3 channel x error interrupt." "0,1" newline bitfld.long 0x8 28. "TIM3_CH4_EIRQ,TIM3 channel x error interrupt." "0,1" newline bitfld.long 0x8 27. "TIM3_CH3_EIRQ,TIM3 channel x error interrupt." "0,1" newline bitfld.long 0x8 26. "TIM3_CH2_EIRQ,TIM3 channel x error interrupt." "0,1" newline bitfld.long 0x8 25. "TIM3_CH1_EIRQ,TIM3 channel x error interrupt." "0,1" newline bitfld.long 0x8 24. "TIM3_CH0_EIRQ,TIM3 channel x error interrupt." "0,1" newline bitfld.long 0x8 23. "TIM2_CH7_EIRQ,TIM2 channel x error interrupt." "0,1" newline bitfld.long 0x8 22. "TIM2_CH6_EIRQ,TIM2 channel x error interrupt." "0,1" newline bitfld.long 0x8 21. "TIM2_CH5_EIRQ,TIM2 channel x error interrupt." "0,1" newline bitfld.long 0x8 20. "TIM2_CH4_EIRQ,TIM2 channel x error interrupt." "0,1" newline bitfld.long 0x8 19. "TIM2_CH3_EIRQ,TIM2 channel x error interrupt." "0,1" newline bitfld.long 0x8 18. "TIM2_CH2_EIRQ,TIM2 channel x error interrupt." "0,1" newline bitfld.long 0x8 17. "TIM2_CH1_EIRQ,TIM2 channel x error interrupt." "0,1" newline bitfld.long 0x8 16. "TIM2_CH0_EIRQ,TIM2 channel x error interrupt." "0,1" newline bitfld.long 0x8 15. "TIM1_CH7_EIRQ,TIM1 channel x error interrupt." "0,1" newline bitfld.long 0x8 14. "TIM1_CH6_EIRQ,TIM1 channel x error interrupt." "0,1" newline bitfld.long 0x8 13. "TIM1_CH5_EIRQ,TIM1 channel x error interrupt." "0,1" newline bitfld.long 0x8 12. "TIM1_CH4_EIRQ,TIM1 channel x error interrupt." "0,1" newline bitfld.long 0x8 11. "TIM1_CH3_EIRQ,TIM1 channel x error interrupt." "0,1" newline bitfld.long 0x8 10. "TIM1_CH2_EIRQ,TIM1 channel x error interrupt." "0,1" newline bitfld.long 0x8 9. "TIM1_CH1_EIRQ,TIM1 channel x error interrupt." "0,1" newline bitfld.long 0x8 8. "TIM1_CH0_EIRQ,TIM1 channel x error interrupt." "0,1" newline bitfld.long 0x8 7. "TIM0_CH7_EIRQ,TIM0 channel x error interrupt" "0,1" newline bitfld.long 0x8 6. "TIM0_CH6_EIRQ,TIM0 channel x error interrupt" "0,1" newline bitfld.long 0x8 5. "TIM0_CH5_EIRQ,TIM0 channel x error interrupt" "0,1" newline bitfld.long 0x8 4. "TIM0_CH4_EIRQ,TIM0 channel x error interrupt" "0,1" newline bitfld.long 0x8 3. "TIM0_CH3_EIRQ,TIM0 channel x error interrupt" "0,1" newline bitfld.long 0x8 2. "TIM0_CH2_EIRQ,TIM0 channel x error interrupt" "0,1" newline bitfld.long 0x8 1. "TIM0_CH1_EIRQ,TIM0 channel x error interrupt" "0,1" newline bitfld.long 0x8 0. "TIM0_CH0_EIRQ,TIM0 channel x error interrupt" "0,1" line.long 0xC "ICM_IRQG_CEI2," bitfld.long 0xC 31. "TIM7_CH7_EIRQ,TIM7 channel x error interrupt." "0,1" newline bitfld.long 0xC 30. "TIM7_CH6_EIRQ,TIM7 channel x error interrupt." "0,1" newline bitfld.long 0xC 29. "TIM7_CH5_EIRQ,TIM7 channel x error interrupt." "0,1" newline bitfld.long 0xC 28. "TIM7_CH4_EIRQ,TIM7 channel x error interrupt." "0,1" newline bitfld.long 0xC 27. "TIM7_CH3_EIRQ,TIM7 channel x error interrupt." "0,1" newline bitfld.long 0xC 26. "TIM7_CH2_EIRQ,TIM7 channel x error interrupt." "0,1" newline bitfld.long 0xC 25. "TIM7_CH1_EIRQ,TIM7 channel x error interrupt." "0,1" newline bitfld.long 0xC 24. "TIM7_CH0_EIRQ,TIM7 channel x error interrupt." "0,1" newline bitfld.long 0xC 23. "TIM6_CH7_EIRQ,TIM6 channel x error interrupt." "0,1" newline bitfld.long 0xC 22. "TIM6_CH6_EIRQ,TIM6 channel x error interrupt." "0,1" newline bitfld.long 0xC 21. "TIM6_CH5_EIRQ,TIM6 channel x error interrupt." "0,1" newline bitfld.long 0xC 20. "TIM6_CH4_EIRQ,TIM6 channel x error interrupt." "0,1" newline bitfld.long 0xC 19. "TIM6_CH3_EIRQ,TIM6 channel x error interrupt." "0,1" newline bitfld.long 0xC 18. "TIM6_CH2_EIRQ,TIM6 channel x error interrupt." "0,1" newline bitfld.long 0xC 17. "TIM6_CH1_EIRQ,TIM6 channel x error interrupt." "0,1" newline bitfld.long 0xC 16. "TIM6_CH0_EIRQ,TIM6 channel x error interrupt." "0,1" newline bitfld.long 0xC 15. "TIM5_CH7_EIRQ,TIM5 channel x error interrupt." "0,1" newline bitfld.long 0xC 14. "TIM5_CH6_EIRQ,TIM5 channel x error interrupt." "0,1" newline bitfld.long 0xC 13. "TIM5_CH5_EIRQ,TIM5 channel x error interrupt." "0,1" newline bitfld.long 0xC 12. "TIM5_CH4_EIRQ,TIM5 channel x error interrupt." "0,1" newline bitfld.long 0xC 11. "TIM5_CH3_EIRQ,TIM5 channel x error interrupt." "0,1" newline bitfld.long 0xC 10. "TIM5_CH2_EIRQ,TIM5 channel x error interrupt." "0,1" newline bitfld.long 0xC 9. "TIM5_CH1_EIRQ,TIM5 channel x error interrupt." "0,1" newline bitfld.long 0xC 8. "TIM5_CH0_EIRQ,TIM5 channel x error interrupt." "0,1" newline bitfld.long 0xC 7. "TIM4_CH7_EIRQ,TIM4 channel x error interrupt" "0,1" newline bitfld.long 0xC 6. "TIM4_CH6_EIRQ,TIM4 channel x error interrupt" "0,1" newline bitfld.long 0xC 5. "TIM4_CH5_EIRQ,TIM4 channel x error interrupt" "0,1" newline bitfld.long 0xC 4. "TIM4_CH4_EIRQ,TIM4 channel x error interrupt" "0,1" newline bitfld.long 0xC 3. "TIM4_CH3_EIRQ,TIM4 channel x error interrupt" "0,1" newline bitfld.long 0xC 2. "TIM4_CH2_EIRQ,TIM4 channel x error interrupt" "0,1" newline bitfld.long 0xC 1. "TIM4_CH1_EIRQ,TIM4 channel x error interrupt" "0,1" newline bitfld.long 0xC 0. "TIM4_CH0_EIRQ,TIM4 channel x error interrupt" "0,1" line.long 0x10 "ICM_IRQG_CEI3," bitfld.long 0x10 31. "MCS3_CH7_EIRQ,MCS3 channel x error interrupt." "0,1" newline bitfld.long 0x10 30. "MCS3_CH6_EIRQ,MCS3 channel x error interrupt." "0,1" newline bitfld.long 0x10 29. "MCS3_CH5_EIRQ,MCS3 channel x error interrupt." "0,1" newline bitfld.long 0x10 28. "MCS3_CH4_EIRQ,MCS3 channel x error interrupt." "0,1" newline bitfld.long 0x10 27. "MCS3_CH3_EIRQ,MCS3 channel x error interrupt." "0,1" newline bitfld.long 0x10 26. "MCS3_CH2_EIRQ,MCS3 channel x error interrupt." "0,1" newline bitfld.long 0x10 25. "MCS3_CH1_EIRQ,MCS3 channel x error interrupt." "0,1" newline bitfld.long 0x10 24. "MCS3_CH0_EIRQ,MCS3 channel x error interrupt." "0,1" newline bitfld.long 0x10 23. "MCS2_CH7_EIRQ,MCS2 channel x error interrupt." "0,1" newline bitfld.long 0x10 22. "MCS2_CH6_EIRQ,MCS2 channel x error interrupt." "0,1" newline bitfld.long 0x10 21. "MCS2_CH5_EIRQ,MCS2 channel x error interrupt." "0,1" newline bitfld.long 0x10 20. "MCS2_CH4_EIRQ,MCS2 channel x error interrupt." "0,1" newline bitfld.long 0x10 19. "MCS2_CH3_EIRQ,MCS2 channel x error interrupt." "0,1" newline bitfld.long 0x10 18. "MCS2_CH2_EIRQ,MCS2 channel x error interrupt." "0,1" newline bitfld.long 0x10 17. "MCS2_CH1_EIRQ,MCS2 channel x error interrupt." "0,1" newline bitfld.long 0x10 16. "MCS2_CH0_EIRQ,MCS2 channel x error interrupt." "0,1" newline bitfld.long 0x10 15. "MCS1_CH7_EIRQ,MCS1 channel x error interrupt." "0,1" newline bitfld.long 0x10 14. "MCS1_CH6_EIRQ,MCS1 channel x error interrupt." "0,1" newline bitfld.long 0x10 13. "MCS1_CH5_EIRQ,MCS1 channel x error interrupt." "0,1" newline bitfld.long 0x10 12. "MCS1_CH4_EIRQ,MCS1 channel x error interrupt." "0,1" newline bitfld.long 0x10 11. "MCS1_CH3_EIRQ,MCS1 channel x error interrupt." "0,1" newline bitfld.long 0x10 10. "MCS1_CH2_EIRQ,MCS1 channel x error interrupt." "0,1" newline bitfld.long 0x10 9. "MCS1_CH1_EIRQ,MCS1 channel x error interrupt." "0,1" newline bitfld.long 0x10 8. "MCS1_CH0_EIRQ,MCS1 channel x error interrupt." "0,1" newline bitfld.long 0x10 7. "MCS0_CH7_EIRQ,MCS0 channel x error interrupt" "0,1" newline bitfld.long 0x10 6. "MCS0_CH6_EIRQ,MCS0 channel x error interrupt" "0,1" newline bitfld.long 0x10 5. "MCS0_CH5_EIRQ,MCS0 channel x error interrupt" "0,1" newline bitfld.long 0x10 4. "MCS0_CH4_EIRQ,MCS0 channel x error interrupt" "0,1" newline bitfld.long 0x10 3. "MCS0_CH3_EIRQ,MCS0 channel x error interrupt" "0,1" newline bitfld.long 0x10 2. "MCS0_CH2_EIRQ,MCS0 channel x error interrupt" "0,1" newline bitfld.long 0x10 1. "MCS0_CH1_EIRQ,MCS0 channel x error interrupt" "0,1" newline bitfld.long 0x10 0. "MCS0_CH0_EIRQ,MCS0 channel x error interrupt" "0,1" line.long 0x14 "ICM_IRQG_CEI4," bitfld.long 0x14 31. "MCS7_CH7_EIRQ,MCS7 channel [x] error interrupt." "0,1" newline bitfld.long 0x14 30. "MCS7_CH6_EIRQ,MCS7 channel [x] error interrupt." "0,1" newline bitfld.long 0x14 29. "MCS7_CH5_EIRQ,MCS7 channel [x] error interrupt." "0,1" newline bitfld.long 0x14 28. "MCS7_CH4_EIRQ,MCS7 channel [x] error interrupt." "0,1" newline bitfld.long 0x14 27. "MCS7_CH3_EIRQ,MCS7 channel [x] error interrupt." "0,1" newline bitfld.long 0x14 26. "MCS7_CH2_EIRQ,MCS7 channel [x] error interrupt." "0,1" newline bitfld.long 0x14 25. "MCS7_CH1_EIRQ,MCS7 channel [x] error interrupt." "0,1" newline bitfld.long 0x14 24. "MCS7_CH0_EIRQ,MCS7 channel [x] error interrupt." "0,1" newline bitfld.long 0x14 23. "MCS6_CH7_EIRQ,MCS6 channel x error interrupt." "0,1" newline bitfld.long 0x14 22. "MCS6_CH6_EIRQ,MCS6 channel x error interrupt." "0,1" newline bitfld.long 0x14 21. "MCS6_CH5_EIRQ,MCS6 channel x error interrupt." "0,1" newline bitfld.long 0x14 20. "MCS6_CH4_EIRQ,MCS6 channel x error interrupt." "0,1" newline bitfld.long 0x14 19. "MCS6_CH3_EIRQ,MCS6 channel x error interrupt." "0,1" newline bitfld.long 0x14 18. "MCS6_CH2_EIRQ,MCS6 channel x error interrupt." "0,1" newline bitfld.long 0x14 17. "MCS6_CH1_EIRQ,MCS6 channel x error interrupt." "0,1" newline bitfld.long 0x14 16. "MCS6_CH0_EIRQ,MCS6 channel x error interrupt." "0,1" newline bitfld.long 0x14 15. "MCS5_CH7_EIRQ,MCS5 channel x error interrupt." "0,1" newline bitfld.long 0x14 14. "MCS5_CH6_EIRQ,MCS5 channel x error interrupt." "0,1" newline bitfld.long 0x14 13. "MCS5_CH5_EIRQ,MCS5 channel x error interrupt." "0,1" newline bitfld.long 0x14 12. "MCS5_CH4_EIRQ,MCS5 channel x error interrupt." "0,1" newline bitfld.long 0x14 11. "MCS5_CH3_EIRQ,MCS5 channel x error interrupt." "0,1" newline bitfld.long 0x14 10. "MCS5_CH2_EIRQ,MCS5 channel x error interrupt." "0,1" newline bitfld.long 0x14 9. "MCS5_CH1_EIRQ,MCS5 channel x error interrupt." "0,1" newline bitfld.long 0x14 8. "MCS5_CH0_EIRQ,MCS5 channel x error interrupt." "0,1" newline bitfld.long 0x14 7. "MCS4_CH7_EIRQ,MCS4 channel x error interrupt" "0,1" newline bitfld.long 0x14 6. "MCS4_CH6_EIRQ,MCS4 channel x error interrupt" "0,1" newline bitfld.long 0x14 5. "MCS4_CH5_EIRQ,MCS4 channel x error interrupt" "0,1" newline bitfld.long 0x14 4. "MCS4_CH4_EIRQ,MCS4 channel x error interrupt" "0,1" newline bitfld.long 0x14 3. "MCS4_CH3_EIRQ,MCS4 channel x error interrupt" "0,1" newline bitfld.long 0x14 2. "MCS4_CH2_EIRQ,MCS4 channel x error interrupt" "0,1" newline bitfld.long 0x14 1. "MCS4_CH1_EIRQ,MCS4 channel x error interrupt" "0,1" newline bitfld.long 0x14 0. "MCS4_CH0_EIRQ,MCS4 channel x error interrupt" "0,1" group.long 0x464++0x27 line.long 0x0 "ICM_IRQG_MCS0_CEI," bitfld.long 0x0 7. "MCS_CH7_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x0 6. "MCS_CH6_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x0 5. "MCS_CH5_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x0 4. "MCS_CH4_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x0 3. "MCS_CH3_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x0 2. "MCS_CH2_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x0 1. "MCS_CH1_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x0 0. "MCS_CH0_EIRQ,MCS channel [x] error interrupt." "0,1" line.long 0x4 "ICM_IRQG_MCS1_CEI," bitfld.long 0x4 7. "MCS_CH7_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x4 6. "MCS_CH6_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x4 5. "MCS_CH5_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x4 4. "MCS_CH4_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x4 3. "MCS_CH3_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x4 2. "MCS_CH2_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x4 1. "MCS_CH1_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_CH0_EIRQ,MCS channel [x] error interrupt." "0,1" line.long 0x8 "ICM_IRQG_MCS2_CEI," bitfld.long 0x8 7. "MCS_CH7_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x8 6. "MCS_CH6_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x8 5. "MCS_CH5_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x8 4. "MCS_CH4_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x8 3. "MCS_CH3_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x8 2. "MCS_CH2_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x8 1. "MCS_CH1_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x8 0. "MCS_CH0_EIRQ,MCS channel [x] error interrupt." "0,1" line.long 0xC "ICM_IRQG_MCS3_CEI," bitfld.long 0xC 7. "MCS_CH7_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0xC 6. "MCS_CH6_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0xC 5. "MCS_CH5_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0xC 4. "MCS_CH4_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0xC 3. "MCS_CH3_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0xC 2. "MCS_CH2_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0xC 1. "MCS_CH1_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0xC 0. "MCS_CH0_EIRQ,MCS channel [x] error interrupt." "0,1" line.long 0x10 "ICM_IRQG_MCS4_CEI," bitfld.long 0x10 7. "MCS_CH7_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x10 6. "MCS_CH6_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x10 5. "MCS_CH5_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x10 4. "MCS_CH4_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x10 3. "MCS_CH3_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x10 2. "MCS_CH2_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x10 1. "MCS_CH1_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x10 0. "MCS_CH0_EIRQ,MCS channel [x] error interrupt." "0,1" line.long 0x14 "ICM_IRQG_MCS5_CEI," bitfld.long 0x14 7. "MCS_CH7_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x14 6. "MCS_CH6_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x14 5. "MCS_CH5_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x14 4. "MCS_CH4_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x14 3. "MCS_CH3_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x14 2. "MCS_CH2_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x14 1. "MCS_CH1_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x14 0. "MCS_CH0_EIRQ,MCS channel [x] error interrupt." "0,1" line.long 0x18 "ICM_IRQG_MCS6_CEI," bitfld.long 0x18 7. "MCS_CH7_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x18 6. "MCS_CH6_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x18 5. "MCS_CH5_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x18 4. "MCS_CH4_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x18 3. "MCS_CH3_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x18 2. "MCS_CH2_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x18 1. "MCS_CH1_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x18 0. "MCS_CH0_EIRQ,MCS channel [x] error interrupt." "0,1" line.long 0x1C "ICM_IRQG_MCS7_CEI," bitfld.long 0x1C 7. "MCS_CH7_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x1C 6. "MCS_CH6_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x1C 5. "MCS_CH5_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x1C 4. "MCS_CH4_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x1C 3. "MCS_CH3_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x1C 2. "MCS_CH2_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x1C 1. "MCS_CH1_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x1C 0. "MCS_CH0_EIRQ,MCS channel [x] error interrupt." "0,1" line.long 0x20 "ICM_IRQG_MCS8_CEI," bitfld.long 0x20 7. "MCS_CH7_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x20 6. "MCS_CH6_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x20 5. "MCS_CH5_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x20 4. "MCS_CH4_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x20 3. "MCS_CH3_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x20 2. "MCS_CH2_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x20 1. "MCS_CH1_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x20 0. "MCS_CH0_EIRQ,MCS channel [x] error interrupt." "0,1" line.long 0x24 "ICM_IRQG_MCS9_CEI," bitfld.long 0x24 7. "MCS_CH7_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x24 6. "MCS_CH6_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x24 5. "MCS_CH5_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x24 4. "MCS_CH4_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x24 3. "MCS_CH3_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x24 2. "MCS_CH2_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x24 1. "MCS_CH1_EIRQ,MCS channel [x] error interrupt." "0,1" newline bitfld.long 0x24 0. "MCS_CH0_EIRQ,MCS channel [x] error interrupt." "0,1" group.long 0x4A4++0x3 line.long 0x0 "ICM_IRQG_PSM_0_CEI," bitfld.long 0x0 23. "PSM_M2_CH7_EIRQ,PSMm channel x error interrupt (m=4*0+2)." "0,1" newline bitfld.long 0x0 22. "PSM_M2_CH6_EIRQ,PSMm channel x error interrupt (m=4*0+2)." "0,1" newline bitfld.long 0x0 21. "PSM_M2_CH5_EIRQ,PSMm channel x error interrupt (m=4*0+2)." "0,1" newline bitfld.long 0x0 20. "PSM_M2_CH4_EIRQ,PSMm channel x error interrupt (m=4*0+2)." "0,1" newline bitfld.long 0x0 19. "PSM_M2_CH3_EIRQ,PSMm channel x error interrupt (m=4*0+2)." "0,1" newline bitfld.long 0x0 18. "PSM_M2_CH2_EIRQ,PSMm channel x error interrupt (m=4*0+2)." "0,1" newline bitfld.long 0x0 17. "PSM_M2_CH1_EIRQ,PSMm channel x error interrupt (m=4*0+2)." "0,1" newline bitfld.long 0x0 16. "PSM_M2_CH0_EIRQ,PSMm channel x error interrupt (m=4*0+2)." "0,1" newline bitfld.long 0x0 15. "PSM_M1_CH7_EIRQ,PSMm channel x error interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 14. "PSM_M1_CH6_EIRQ,PSMm channel x error interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 13. "PSM_M1_CH5_EIRQ,PSMm channel x error interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 12. "PSM_M1_CH4_EIRQ,PSMm channel x error interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 11. "PSM_M1_CH3_EIRQ,PSMm channel x error interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 10. "PSM_M1_CH2_EIRQ,PSMm channel x error interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 9. "PSM_M1_CH1_EIRQ,PSMm channel x error interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 8. "PSM_M1_CH0_EIRQ,PSMm channel x error interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 7. "PSM_M0_CH7_EIRQ,PSMm channel x error interrupt (m=4*0+0)." "0,1" newline bitfld.long 0x0 6. "PSM_M0_CH6_EIRQ,PSMm channel x error interrupt (m=4*0+0)." "0,1" newline bitfld.long 0x0 5. "PSM_M0_CH5_EIRQ,PSMm channel x error interrupt (m=4*0+0)." "0,1" newline bitfld.long 0x0 4. "PSM_M0_CH4_EIRQ,PSMm channel x error interrupt (m=4*0+0)." "0,1" newline bitfld.long 0x0 3. "PSM_M0_CH3_EIRQ,PSMm channel x error interrupt (m=4*0+0)." "0,1" newline bitfld.long 0x0 2. "PSM_M0_CH2_EIRQ,PSMm channel x error interrupt (m=4*0+0)." "0,1" newline bitfld.long 0x0 1. "PSM_M0_CH1_EIRQ,PSMm channel x error interrupt (m=4*0+0)." "0,1" newline bitfld.long 0x0 0. "PSM_M0_CH0_EIRQ,PSMm channel x error interrupt (m=4*0+0)." "0,1" group.long 0x4B4++0x3 line.long 0x0 "ICM_IRQG_SPE_CEI," bitfld.long 0x0 4. "SPE4_EIRQ,SPE instance j error interrupt." "0,1" newline bitfld.long 0x0 3. "SPE3_EIRQ,SPE instance j error interrupt." "0,1" newline bitfld.long 0x0 2. "SPE2_EIRQ,SPE instance j error interrupt." "0,1" newline bitfld.long 0x0 1. "SPE1_EIRQ,SPE instance j error interrupt." "0,1" newline bitfld.long 0x0 0. "SPE0_EIRQ,SPE instance j error interrupt." "0,1" group.long 0x510++0xB line.long 0x0 "ICM_IRQG_CLS_0_MEI," bitfld.long 0x0 27. "FIFO_M3_EIRQ,Error interrupt FIFOm_EIRQ (m=4*g+2)." "0,1" newline bitfld.long 0x0 26. "SPE_M3_EIRQ,Error interrupt SPEm_EIRQ (m=4*g+3)." "0,1" newline bitfld.long 0x0 25. "MCS_M3_EIRQ,Error interrupt MCSm_EIRQ (m=4*g+3)." "0,1" newline bitfld.long 0x0 24. "TIM_M3_EIRQ,Error interrupt TIMm_EIRQ (m=4*g+3)." "0,1" newline bitfld.long 0x0 19. "FIFO_M2_EIRQ,Error interrupt FIFOm_EIRQ (m=4*g+2)." "0,1" newline bitfld.long 0x0 18. "SPE_M2_EIRQ,Error interrupt SPEm_EIRQ (m=4*g+2)." "0,1" newline bitfld.long 0x0 17. "MCS_M2_EIRQ,Error interrupt MCSm_EIRQ (m=4*g+2)." "0,1" newline bitfld.long 0x0 16. "TIM_M2_EIRQ,Error interrupt TIMm_EIRQ (m=4*g+2)." "0,1" newline bitfld.long 0x0 11. "FIFO_M1_EIRQ,Error interrupt FIFOm_EIRQ (m=4*g+1)." "0,1" newline bitfld.long 0x0 10. "SPE_M1_EIRQ,Error interrupt SPEm_EIRQ (m=4*g+1)." "0,1" newline bitfld.long 0x0 9. "MCS_M1_EIRQ,Error interrupt MCSm_EIRQ (m=4*g+1)." "0,1" newline bitfld.long 0x0 8. "TIM_M1_EIRQ,Error interrupt TIMm_EIRQ (m=4*g+1)." "0,1" newline bitfld.long 0x0 3. "FIFO_M0_EIRQ,Error interrupt FIFOm_EIRQ (m=4*g+0)." "0,1" newline bitfld.long 0x0 2. "SPE_M0_EIRQ,Error interrupt SPEm_EIRQ (m=4*g+0)." "0,1" newline bitfld.long 0x0 1. "MCS_M0_EIRQ,Error interrupt MCSm_EIRQ (m=4*g+0)." "0,1" newline bitfld.long 0x0 0. "TIM_M0_EIRQ,Error interrupt TIMm_EIRQ (m=4*g+0)." "0,1" line.long 0x4 "ICM_IRQG_CLS_1_MEI," bitfld.long 0x4 27. "FIFO_M3_EIRQ,Error interrupt FIFOm_EIRQ (m=4*g+2)." "0,1" newline bitfld.long 0x4 26. "SPE_M3_EIRQ,Error interrupt SPEm_EIRQ (m=4*g+3)." "0,1" newline bitfld.long 0x4 25. "MCS_M3_EIRQ,Error interrupt MCSm_EIRQ (m=4*g+3)." "0,1" newline bitfld.long 0x4 24. "TIM_M3_EIRQ,Error interrupt TIMm_EIRQ (m=4*g+3)." "0,1" newline bitfld.long 0x4 19. "FIFO_M2_EIRQ,Error interrupt FIFOm_EIRQ (m=4*g+2)." "0,1" newline bitfld.long 0x4 18. "SPE_M2_EIRQ,Error interrupt SPEm_EIRQ (m=4*g+2)." "0,1" newline bitfld.long 0x4 17. "MCS_M2_EIRQ,Error interrupt MCSm_EIRQ (m=4*g+2)." "0,1" newline bitfld.long 0x4 16. "TIM_M2_EIRQ,Error interrupt TIMm_EIRQ (m=4*g+2)." "0,1" newline bitfld.long 0x4 11. "FIFO_M1_EIRQ,Error interrupt FIFOm_EIRQ (m=4*g+1)." "0,1" newline bitfld.long 0x4 10. "SPE_M1_EIRQ,Error interrupt SPEm_EIRQ (m=4*g+1)." "0,1" newline bitfld.long 0x4 9. "MCS_M1_EIRQ,Error interrupt MCSm_EIRQ (m=4*g+1)." "0,1" newline bitfld.long 0x4 8. "TIM_M1_EIRQ,Error interrupt TIMm_EIRQ (m=4*g+1)." "0,1" newline bitfld.long 0x4 3. "FIFO_M0_EIRQ,Error interrupt FIFOm_EIRQ (m=4*g+0)." "0,1" newline bitfld.long 0x4 2. "SPE_M0_EIRQ,Error interrupt SPEm_EIRQ (m=4*g+0)." "0,1" newline bitfld.long 0x4 1. "MCS_M0_EIRQ,Error interrupt MCSm_EIRQ (m=4*g+0)." "0,1" newline bitfld.long 0x4 0. "TIM_M0_EIRQ,Error interrupt TIMm_EIRQ (m=4*g+0)." "0,1" line.long 0x8 "ICM_IRQG_CLS_2_MEI," bitfld.long 0x8 27. "FIFO_M3_EIRQ,Error interrupt FIFOm_EIRQ (m=4*g+2)." "0,1" newline bitfld.long 0x8 26. "SPE_M3_EIRQ,Error interrupt SPEm_EIRQ (m=4*g+3)." "0,1" newline bitfld.long 0x8 25. "MCS_M3_EIRQ,Error interrupt MCSm_EIRQ (m=4*g+3)." "0,1" newline bitfld.long 0x8 24. "TIM_M3_EIRQ,Error interrupt TIMm_EIRQ (m=4*g+3)." "0,1" newline bitfld.long 0x8 19. "FIFO_M2_EIRQ,Error interrupt FIFOm_EIRQ (m=4*g+2)." "0,1" newline bitfld.long 0x8 18. "SPE_M2_EIRQ,Error interrupt SPEm_EIRQ (m=4*g+2)." "0,1" newline bitfld.long 0x8 17. "MCS_M2_EIRQ,Error interrupt MCSm_EIRQ (m=4*g+2)." "0,1" newline bitfld.long 0x8 16. "TIM_M2_EIRQ,Error interrupt TIMm_EIRQ (m=4*g+2)." "0,1" newline bitfld.long 0x8 11. "FIFO_M1_EIRQ,Error interrupt FIFOm_EIRQ (m=4*g+1)." "0,1" newline bitfld.long 0x8 10. "SPE_M1_EIRQ,Error interrupt SPEm_EIRQ (m=4*g+1)." "0,1" newline bitfld.long 0x8 9. "MCS_M1_EIRQ,Error interrupt MCSm_EIRQ (m=4*g+1)." "0,1" newline bitfld.long 0x8 8. "TIM_M1_EIRQ,Error interrupt TIMm_EIRQ (m=4*g+1)." "0,1" newline bitfld.long 0x8 3. "FIFO_M0_EIRQ,Error interrupt FIFOm_EIRQ (m=4*g+0)." "0,1" newline bitfld.long 0x8 2. "SPE_M0_EIRQ,Error interrupt SPEm_EIRQ (m=4*g+0)." "0,1" newline bitfld.long 0x8 1. "MCS_M0_EIRQ,Error interrupt MCSm_EIRQ (m=4*g+0)." "0,1" newline bitfld.long 0x8 0. "TIM_M0_EIRQ,Error interrupt TIMm_EIRQ (m=4*g+0)." "0,1" group.long 0x520++0x27 line.long 0x0 "ICM_IRQG_MCS0_CI," bitfld.long 0x0 7. "MCS_CH7_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x0 6. "MCS_CH6_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x0 5. "MCS_CH5_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x0 4. "MCS_CH4_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x0 3. "MCS_CH3_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x0 2. "MCS_CH2_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x0 1. "MCS_CH1_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x0 0. "MCS_CH0_IRQ,MCS channel [x] interrupt." "0,1" line.long 0x4 "ICM_IRQG_MCS1_CI," bitfld.long 0x4 7. "MCS_CH7_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x4 6. "MCS_CH6_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x4 5. "MCS_CH5_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x4 4. "MCS_CH4_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x4 3. "MCS_CH3_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x4 2. "MCS_CH2_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x4 1. "MCS_CH1_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_CH0_IRQ,MCS channel [x] interrupt." "0,1" line.long 0x8 "ICM_IRQG_MCS2_CI," bitfld.long 0x8 7. "MCS_CH7_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x8 6. "MCS_CH6_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x8 5. "MCS_CH5_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x8 4. "MCS_CH4_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x8 3. "MCS_CH3_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x8 2. "MCS_CH2_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x8 1. "MCS_CH1_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x8 0. "MCS_CH0_IRQ,MCS channel [x] interrupt." "0,1" line.long 0xC "ICM_IRQG_MCS3_CI," bitfld.long 0xC 7. "MCS_CH7_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0xC 6. "MCS_CH6_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0xC 5. "MCS_CH5_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0xC 4. "MCS_CH4_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0xC 3. "MCS_CH3_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0xC 2. "MCS_CH2_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0xC 1. "MCS_CH1_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0xC 0. "MCS_CH0_IRQ,MCS channel [x] interrupt." "0,1" line.long 0x10 "ICM_IRQG_MCS4_CI," bitfld.long 0x10 7. "MCS_CH7_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x10 6. "MCS_CH6_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x10 5. "MCS_CH5_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x10 4. "MCS_CH4_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x10 3. "MCS_CH3_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x10 2. "MCS_CH2_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x10 1. "MCS_CH1_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x10 0. "MCS_CH0_IRQ,MCS channel [x] interrupt." "0,1" line.long 0x14 "ICM_IRQG_MCS5_CI," bitfld.long 0x14 7. "MCS_CH7_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x14 6. "MCS_CH6_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x14 5. "MCS_CH5_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x14 4. "MCS_CH4_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x14 3. "MCS_CH3_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x14 2. "MCS_CH2_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x14 1. "MCS_CH1_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x14 0. "MCS_CH0_IRQ,MCS channel [x] interrupt." "0,1" line.long 0x18 "ICM_IRQG_MCS6_CI," bitfld.long 0x18 7. "MCS_CH7_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x18 6. "MCS_CH6_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x18 5. "MCS_CH5_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x18 4. "MCS_CH4_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x18 3. "MCS_CH3_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x18 2. "MCS_CH2_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x18 1. "MCS_CH1_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x18 0. "MCS_CH0_IRQ,MCS channel [x] interrupt." "0,1" line.long 0x1C "ICM_IRQG_MCS7_CI," bitfld.long 0x1C 7. "MCS_CH7_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x1C 6. "MCS_CH6_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x1C 5. "MCS_CH5_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x1C 4. "MCS_CH4_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x1C 3. "MCS_CH3_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x1C 2. "MCS_CH2_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x1C 1. "MCS_CH1_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x1C 0. "MCS_CH0_IRQ,MCS channel [x] interrupt." "0,1" line.long 0x20 "ICM_IRQG_MCS8_CI," bitfld.long 0x20 7. "MCS_CH7_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x20 6. "MCS_CH6_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x20 5. "MCS_CH5_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x20 4. "MCS_CH4_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x20 3. "MCS_CH3_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x20 2. "MCS_CH2_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x20 1. "MCS_CH1_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x20 0. "MCS_CH0_IRQ,MCS channel [x] interrupt." "0,1" line.long 0x24 "ICM_IRQG_MCS9_CI," bitfld.long 0x24 7. "MCS_CH7_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x24 6. "MCS_CH6_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x24 5. "MCS_CH5_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x24 4. "MCS_CH4_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x24 3. "MCS_CH3_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x24 2. "MCS_CH2_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x24 1. "MCS_CH1_IRQ,MCS channel [x] interrupt." "0,1" newline bitfld.long 0x24 0. "MCS_CH0_IRQ,MCS channel [x] interrupt." "0,1" group.long 0x560++0x3 line.long 0x0 "ICM_IRQG_PSM_0_CI," bitfld.long 0x0 23. "PSM_M2_CH7_IRQ,PSMm channel x shared interrupt (m=4*0+2)." "0,1" newline bitfld.long 0x0 22. "PSM_M2_CH6_IRQ,PSMm channel x shared interrupt (m=4*0+2)." "0,1" newline bitfld.long 0x0 21. "PSM_M2_CH5_IRQ,PSMm channel x shared interrupt (m=4*0+2)." "0,1" newline bitfld.long 0x0 20. "PSM_M2_CH4_IRQ,PSMm channel x shared interrupt (m=4*0+2)." "0,1" newline bitfld.long 0x0 19. "PSM_M2_CH3_IRQ,PSMm channel x shared interrupt (m=4*0+2)." "0,1" newline bitfld.long 0x0 18. "PSM_M2_CH2_IRQ,PSMm channel x shared interrupt (m=4*0+2)." "0,1" newline bitfld.long 0x0 17. "PSM_M2_CH1_IRQ,PSMm channel x shared interrupt (m=4*0+2)." "0,1" newline bitfld.long 0x0 16. "PSM_M2_CH0_IRQ,PSMm channel x shared interrupt (m=4*0+2)." "0,1" newline bitfld.long 0x0 15. "PSM_M1_CH7_IRQ,PSMm channel x shared interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 14. "PSM_M1_CH6_IRQ,PSMm channel x shared interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 13. "PSM_M1_CH5_IRQ,PSMm channel x shared interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 12. "PSM_M1_CH4_IRQ,PSMm channel x shared interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 11. "PSM_M1_CH3_IRQ,PSMm channel x shared interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 10. "PSM_M1_CH2_IRQ,PSMm channel x shared interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 9. "PSM_M1_CH1_IRQ,PSMm channel x shared interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 8. "PSM_M1_CH0_IRQ,PSMm channel x shared interrupt (m=4*0+1)." "0,1" newline bitfld.long 0x0 7. "PSM_M0_CH7_IRQ,PSMm channel x shared interrupt (m=4*0+0)." "0,1" newline bitfld.long 0x0 6. "PSM_M0_CH6_IRQ,PSMm channel x shared interrupt (m=4*0+0)." "0,1" newline bitfld.long 0x0 5. "PSM_M0_CH5_IRQ,PSMm channel x shared interrupt (m=4*0+0)." "0,1" newline bitfld.long 0x0 4. "PSM_M0_CH4_IRQ,PSMm channel x shared interrupt (m=4*0+0)." "0,1" newline bitfld.long 0x0 3. "PSM_M0_CH3_IRQ,PSMm channel x shared interrupt (m=4*0+0)." "0,1" newline bitfld.long 0x0 2. "PSM_M0_CH2_IRQ,PSMm channel x shared interrupt (m=4*0+0)." "0,1" newline bitfld.long 0x0 1. "PSM_M0_CH1_IRQ,PSMm channel x shared interrupt (m=4*0+0)." "0,1" newline bitfld.long 0x0 0. "PSM_M0_CH0_IRQ,PSMm channel x shared interrupt (m=4*0+0)." "0,1" group.long 0x570++0x3 line.long 0x0 "ICM_IRQG_SPE_CI," bitfld.long 0x0 4. "SPE4_IRQ,SPE instance j interrupt." "0,1" newline bitfld.long 0x0 3. "SPE3_IRQ,SPE instance j interrupt." "0,1" newline bitfld.long 0x0 2. "SPE2_IRQ,SPE instance j interrupt." "0,1" newline bitfld.long 0x0 1. "SPE1_IRQ,SPE instance j interrupt." "0,1" newline bitfld.long 0x0 0. "SPE0_IRQ,SPE instance j interrupt." "0,1" group.long 0x590++0xB line.long 0x0 "ICM_IRQG_ATOM_0_CI," bitfld.long 0x0 31. "ATOM_M3_CH7_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x0 30. "ATOM_M3_CH6_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x0 29. "ATOM_M3_CH5_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x0 28. "ATOM_M3_CH4_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x0 27. "ATOM_M3_CH3_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x0 26. "ATOM_M3_CH2_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x0 25. "ATOM_M3_CH1_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x0 24. "ATOM_M3_CH0_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x0 23. "ATOM_M2_CH7_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x0 22. "ATOM_M2_CH6_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x0 21. "ATOM_M2_CH5_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x0 20. "ATOM_M2_CH4_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x0 19. "ATOM_M2_CH3_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x0 18. "ATOM_M2_CH2_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x0 17. "ATOM_M2_CH1_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x0 16. "ATOM_M2_CH0_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x0 15. "ATOM_M1_CH7_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x0 14. "ATOM_M1_CH6_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x0 13. "ATOM_M1_CH5_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x0 12. "ATOM_M1_CH4_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x0 11. "ATOM_M1_CH3_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x0 10. "ATOM_M1_CH2_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x0 9. "ATOM_M1_CH1_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x0 8. "ATOM_M1_CH0_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x0 7. "ATOM_M0_CH7_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x0 6. "ATOM_M0_CH6_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x0 5. "ATOM_M0_CH5_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x0 4. "ATOM_M0_CH4_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x0 3. "ATOM_M0_CH3_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x0 2. "ATOM_M0_CH2_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x0 1. "ATOM_M0_CH1_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x0 0. "ATOM_M0_CH0_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" line.long 0x4 "ICM_IRQG_ATOM_1_CI," bitfld.long 0x4 31. "ATOM_M3_CH7_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x4 30. "ATOM_M3_CH6_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x4 29. "ATOM_M3_CH5_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x4 28. "ATOM_M3_CH4_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x4 27. "ATOM_M3_CH3_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x4 26. "ATOM_M3_CH2_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x4 25. "ATOM_M3_CH1_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x4 24. "ATOM_M3_CH0_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x4 23. "ATOM_M2_CH7_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x4 22. "ATOM_M2_CH6_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x4 21. "ATOM_M2_CH5_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x4 20. "ATOM_M2_CH4_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x4 19. "ATOM_M2_CH3_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x4 18. "ATOM_M2_CH2_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x4 17. "ATOM_M2_CH1_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x4 16. "ATOM_M2_CH0_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x4 15. "ATOM_M1_CH7_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x4 14. "ATOM_M1_CH6_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x4 13. "ATOM_M1_CH5_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x4 12. "ATOM_M1_CH4_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x4 11. "ATOM_M1_CH3_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x4 10. "ATOM_M1_CH2_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x4 9. "ATOM_M1_CH1_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x4 8. "ATOM_M1_CH0_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x4 7. "ATOM_M0_CH7_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x4 6. "ATOM_M0_CH6_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x4 5. "ATOM_M0_CH5_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x4 4. "ATOM_M0_CH4_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x4 3. "ATOM_M0_CH3_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x4 2. "ATOM_M0_CH2_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x4 1. "ATOM_M0_CH1_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x4 0. "ATOM_M0_CH0_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" line.long 0x8 "ICM_IRQG_ATOM_2_CI," bitfld.long 0x8 31. "ATOM_M3_CH7_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x8 30. "ATOM_M3_CH6_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x8 29. "ATOM_M3_CH5_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x8 28. "ATOM_M3_CH4_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x8 27. "ATOM_M3_CH3_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x8 26. "ATOM_M3_CH2_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x8 25. "ATOM_M3_CH1_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x8 24. "ATOM_M3_CH0_IRQ,ATOMm channel x interrupt (m=4*g+3)." "0,1" newline bitfld.long 0x8 23. "ATOM_M2_CH7_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x8 22. "ATOM_M2_CH6_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x8 21. "ATOM_M2_CH5_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x8 20. "ATOM_M2_CH4_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x8 19. "ATOM_M2_CH3_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x8 18. "ATOM_M2_CH2_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x8 17. "ATOM_M2_CH1_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x8 16. "ATOM_M2_CH0_IRQ,ATOMm channel x interrupt (m=4*g+2)." "0,1" newline bitfld.long 0x8 15. "ATOM_M1_CH7_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x8 14. "ATOM_M1_CH6_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x8 13. "ATOM_M1_CH5_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x8 12. "ATOM_M1_CH4_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x8 11. "ATOM_M1_CH3_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x8 10. "ATOM_M1_CH2_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x8 9. "ATOM_M1_CH1_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x8 8. "ATOM_M1_CH0_IRQ,ATOMm channel x interrupt (m=4*g+1)." "0,1" newline bitfld.long 0x8 7. "ATOM_M0_CH7_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x8 6. "ATOM_M0_CH6_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x8 5. "ATOM_M0_CH5_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x8 4. "ATOM_M0_CH4_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x8 3. "ATOM_M0_CH3_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x8 2. "ATOM_M0_CH2_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x8 1. "ATOM_M0_CH1_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" newline bitfld.long 0x8 0. "ATOM_M0_CH0_IRQ,ATOMm channel x interrupt (m=4*g+0)." "0,1" group.long 0x5A0++0xB line.long 0x0 "ICM_IRQG_TOM_0_CI," bitfld.long 0x0 31. "TOM_M1_CH15_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x0 30. "TOM_M1_CH14_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x0 29. "TOM_M1_CH13_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x0 28. "TOM_M1_CH12_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x0 27. "TOM_M1_CH11_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x0 26. "TOM_M1_CH10_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x0 25. "TOM_M1_CH9_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x0 24. "TOM_M1_CH8_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x0 23. "TOM_M1_CH7_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x0 22. "TOM_M1_CH6_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x0 21. "TOM_M1_CH5_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x0 20. "TOM_M1_CH4_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x0 19. "TOM_M1_CH3_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x0 18. "TOM_M1_CH2_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x0 17. "TOM_M1_CH1_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x0 16. "TOM_M1_CH0_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x0 15. "TOM_M0_CH15_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x0 14. "TOM_M0_CH14_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x0 13. "TOM_M0_CH13_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x0 12. "TOM_M0_CH12_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x0 11. "TOM_M0_CH11_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x0 10. "TOM_M0_CH10_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x0 9. "TOM_M0_CH9_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x0 8. "TOM_M0_CH8_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x0 7. "TOM_M0_CH7_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x0 6. "TOM_M0_CH6_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x0 5. "TOM_M0_CH5_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x0 4. "TOM_M0_CH4_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x0 3. "TOM_M0_CH3_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x0 2. "TOM_M0_CH2_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x0 1. "TOM_M0_CH1_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x0 0. "TOM_M0_CH0_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" line.long 0x4 "ICM_IRQG_TOM_1_CI," bitfld.long 0x4 31. "TOM_M1_CH15_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x4 30. "TOM_M1_CH14_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x4 29. "TOM_M1_CH13_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x4 28. "TOM_M1_CH12_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x4 27. "TOM_M1_CH11_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x4 26. "TOM_M1_CH10_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x4 25. "TOM_M1_CH9_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x4 24. "TOM_M1_CH8_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x4 23. "TOM_M1_CH7_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x4 22. "TOM_M1_CH6_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x4 21. "TOM_M1_CH5_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x4 20. "TOM_M1_CH4_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x4 19. "TOM_M1_CH3_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x4 18. "TOM_M1_CH2_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x4 17. "TOM_M1_CH1_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x4 16. "TOM_M1_CH0_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x4 15. "TOM_M0_CH15_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x4 14. "TOM_M0_CH14_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x4 13. "TOM_M0_CH13_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x4 12. "TOM_M0_CH12_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x4 11. "TOM_M0_CH11_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x4 10. "TOM_M0_CH10_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x4 9. "TOM_M0_CH9_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x4 8. "TOM_M0_CH8_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x4 7. "TOM_M0_CH7_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x4 6. "TOM_M0_CH6_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x4 5. "TOM_M0_CH5_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x4 4. "TOM_M0_CH4_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x4 3. "TOM_M0_CH3_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x4 2. "TOM_M0_CH2_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x4 1. "TOM_M0_CH1_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x4 0. "TOM_M0_CH0_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" line.long 0x8 "ICM_IRQG_TOM_2_CI," bitfld.long 0x8 31. "TOM_M1_CH15_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x8 30. "TOM_M1_CH14_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x8 29. "TOM_M1_CH13_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x8 28. "TOM_M1_CH12_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x8 27. "TOM_M1_CH11_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x8 26. "TOM_M1_CH10_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x8 25. "TOM_M1_CH9_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x8 24. "TOM_M1_CH8_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x8 23. "TOM_M1_CH7_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x8 22. "TOM_M1_CH6_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x8 21. "TOM_M1_CH5_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x8 20. "TOM_M1_CH4_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x8 19. "TOM_M1_CH3_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x8 18. "TOM_M1_CH2_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x8 17. "TOM_M1_CH1_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x8 16. "TOM_M1_CH0_IRQ,TOMm channel x interrupt (m=2*g+1)." "0,1" newline bitfld.long 0x8 15. "TOM_M0_CH15_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x8 14. "TOM_M0_CH14_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x8 13. "TOM_M0_CH13_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x8 12. "TOM_M0_CH12_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x8 11. "TOM_M0_CH11_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x8 10. "TOM_M0_CH10_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x8 9. "TOM_M0_CH9_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x8 8. "TOM_M0_CH8_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x8 7. "TOM_M0_CH7_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x8 6. "TOM_M0_CH6_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x8 5. "TOM_M0_CH5_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x8 4. "TOM_M0_CH4_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x8 3. "TOM_M0_CH3_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x8 2. "TOM_M0_CH2_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x8 1. "TOM_M0_CH1_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" newline bitfld.long 0x8 0. "TOM_M0_CH0_IRQ,TOMm channel x interrupt (m=2*g+0)." "0,1" group.long 0x640++0x3 line.long 0x0 "MAP_CTRL," bitfld.long 0x0 30. "TSPP1_I2V,Disable of TSPP1 TIM0_CHz(48) input line." "0,1" newline bitfld.long 0x0 29. "TSPP1_I1V,Disable of TSPP1 TIM0_CHy(48) input line." "0,1" newline bitfld.long 0x0 28. "TSPP1_I0V,Disable of TSPP1 TIM0_CHx(48) input line." "0,1" newline bitfld.long 0x0 25. "TSPP1_DLD,DIR level definition bit." "0,1" newline bitfld.long 0x0 24. "TSPP1_EN,Enable of TSPP1 subunit." "0,1" newline bitfld.long 0x0 22. "TSPP0_I2V,Disable of TSPP0 TIM0_CHz(48) input line." "0,1" newline bitfld.long 0x0 21. "TSPP0_I1V,Disable of TSPP0 TIM0_CHy(48) input line." "0,1" newline bitfld.long 0x0 20. "TSPP0_I0V,Disable of TSPP0 TIM0_CHx(48) input line." "0,1" newline bitfld.long 0x0 17. "TSPP0_DLD,DIR level definition bit." "0,1" newline bitfld.long 0x0 16. "TSPP0_EN,Enable of TSPP0 subunit." "0,1" newline bitfld.long 0x0 4. "LSEL,TIM0_IN6 input level selection" "0,1" newline bitfld.long 0x0 1.--3. "SSL,STATE signal output select." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TSEL,TRIGGER signal output select." "0,1" group.long 0x800++0x3F line.long 0x0 "TIM0_CH0_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM0_CH0_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM0_CH0_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM0_CH0_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM0_CH0_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM0_CH0_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM0_CH0_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM0_CH0_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM0_CH0_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM0_CH0_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM0_CH0_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM0_CH0_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM0_CH0_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM0_CH0_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM0_CH0_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM0_CH0_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x880++0x3F line.long 0x0 "TIM0_CH1_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM0_CH1_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM0_CH1_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM0_CH1_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM0_CH1_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM0_CH1_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM0_CH1_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM0_CH1_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM0_CH1_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM0_CH1_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM0_CH1_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM0_CH1_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM0_CH1_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM0_CH1_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM0_CH1_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM0_CH1_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x900++0x3F line.long 0x0 "TIM0_CH2_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM0_CH2_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM0_CH2_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM0_CH2_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM0_CH2_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM0_CH2_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM0_CH2_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM0_CH2_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM0_CH2_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM0_CH2_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM0_CH2_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM0_CH2_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM0_CH2_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM0_CH2_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM0_CH2_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM0_CH2_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x980++0x3F line.long 0x0 "TIM0_CH3_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM0_CH3_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM0_CH3_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM0_CH3_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM0_CH3_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM0_CH3_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM0_CH3_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM0_CH3_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM0_CH3_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM0_CH3_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM0_CH3_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM0_CH3_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM0_CH3_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM0_CH3_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM0_CH3_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM0_CH3_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xA00++0x3F line.long 0x0 "TIM0_CH4_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM0_CH4_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM0_CH4_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM0_CH4_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM0_CH4_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM0_CH4_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM0_CH4_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM0_CH4_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM0_CH4_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM0_CH4_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM0_CH4_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM0_CH4_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM0_CH4_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM0_CH4_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM0_CH4_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM0_CH4_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xA80++0x3F line.long 0x0 "TIM0_CH5_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM0_CH5_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM0_CH5_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM0_CH5_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM0_CH5_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM0_CH5_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM0_CH5_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM0_CH5_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM0_CH5_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM0_CH5_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM0_CH5_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM0_CH5_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM0_CH5_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM0_CH5_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM0_CH5_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM0_CH5_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xB00++0x3F line.long 0x0 "TIM0_CH6_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM0_CH6_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM0_CH6_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM0_CH6_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM0_CH6_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM0_CH6_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM0_CH6_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM0_CH6_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM0_CH6_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM0_CH6_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM0_CH6_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM0_CH6_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM0_CH6_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM0_CH6_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM0_CH6_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM0_CH6_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xB80++0x3F line.long 0x0 "TIM0_CH7_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM0_CH7_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM0_CH7_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM0_CH7_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM0_CH7_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM0_CH7_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM0_CH7_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM0_CH7_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM0_CH7_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM0_CH7_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM0_CH7_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM0_CH7_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM0_CH7_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM0_CH7_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM0_CH7_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM0_CH7_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xC00++0xB line.long 0x0 "TIM0_INP_VAL," bitfld.long 0x0 23. "TIM_IN7,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 22. "TIM_IN6,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 21. "TIM_IN5,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 20. "TIM_IN4,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 19. "TIM_IN3,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 18. "TIM_IN2,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 17. "TIM_IN1,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 16. "TIM_IN0,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 15. "F_IN7,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 14. "F_IN6,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 13. "F_IN5,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 12. "F_IN4,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 11. "F_IN3,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 10. "F_IN2,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 9. "F_IN1,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 8. "F_IN0,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 7. "F_OUT7,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 6. "F_OUT6,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 5. "F_OUT5,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 4. "F_OUT4,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 3. "F_OUT3,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 2. "F_OUT2,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 1. "F_OUT1,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 0. "F_OUT0,Signal channel x after TIM FLT unit" "0,1" line.long 0x4 "TIM0_IN_SRC," bitfld.long 0x4 30.--31. "MODE_7,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 28.--29. "VAL_7,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 26.--27. "MODE_6,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 24.--25. "VAL_6,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 22.--23. "MODE_5,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 20.--21. "VAL_5,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 18.--19. "MODE_4,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 16.--17. "VAL_4,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 14.--15. "MODE_3,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 12.--13. "VAL_3,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 10.--11. "MODE_2,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 8.--9. "VAL_2,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 6.--7. "MODE_1,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 4.--5. "VAL_1,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 2.--3. "MODE_0,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 0.--1. "VAL_0,Value to be fed to channel [x]" "0,1,2,3" line.long 0x8 "TIM0_RST," bitfld.long 0x8 7. "RST_CH7,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 6. "RST_CH6,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 5. "RST_CH5,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 4. "RST_CH4,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 3. "RST_CH3,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 2. "RST_CH2,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 1. "RST_CH1,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 0. "RST_CH0,Software reset of channel [x]" "0,1" group.long 0x1000++0x2B line.long 0x0 "TOM0_CH0_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH0_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH0_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH0_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH0_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH0_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH0_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH0_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH0_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH0_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH0_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1030++0x3 line.long 0x0 "TOM0_CH0_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1040++0x2B line.long 0x0 "TOM0_CH1_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH1_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH1_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH1_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH1_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH1_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH1_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH1_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH1_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH1_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH1_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1070++0x3 line.long 0x0 "TOM0_CH1_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1080++0x2B line.long 0x0 "TOM0_CH2_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH2_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH2_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH2_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH2_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH2_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH2_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH2_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH2_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH2_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH2_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x10B0++0x3 line.long 0x0 "TOM0_CH2_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x10C0++0x2B line.long 0x0 "TOM0_CH3_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH3_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH3_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH3_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH3_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH3_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH3_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH3_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH3_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH3_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH3_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x10F0++0x3 line.long 0x0 "TOM0_CH3_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1100++0x2B line.long 0x0 "TOM0_CH4_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH4_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH4_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH4_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH4_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH4_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH4_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH4_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH4_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH4_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH4_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1130++0x3 line.long 0x0 "TOM0_CH4_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1140++0x2B line.long 0x0 "TOM0_CH5_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH5_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH5_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH5_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH5_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH5_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH5_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH5_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH5_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH5_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH5_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1170++0x3 line.long 0x0 "TOM0_CH5_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1180++0x2B line.long 0x0 "TOM0_CH6_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH6_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH6_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH6_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH6_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH6_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH6_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH6_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH6_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH6_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH6_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x11B0++0x3 line.long 0x0 "TOM0_CH6_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x11C0++0x2B line.long 0x0 "TOM0_CH7_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH7_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH7_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH7_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH7_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH7_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH7_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH7_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH7_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH7_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH7_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x11F0++0x3 line.long 0x0 "TOM0_CH7_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1200++0x2B line.long 0x0 "TOM0_CH8_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH8_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH8_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH8_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH8_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH8_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH8_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH8_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH8_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH8_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH8_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1230++0x3 line.long 0x0 "TOM0_CH8_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1240++0x2B line.long 0x0 "TOM0_CH9_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH9_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH9_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH9_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH9_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH9_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH9_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH9_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH9_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH9_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH9_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1270++0x3 line.long 0x0 "TOM0_CH9_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1280++0x2B line.long 0x0 "TOM0_CH10_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH10_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH10_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH10_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH10_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH10_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH10_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH10_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH10_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH10_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH10_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x12B0++0x3 line.long 0x0 "TOM0_CH10_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x12C0++0x2B line.long 0x0 "TOM0_CH11_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH11_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH11_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH11_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH11_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH11_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH11_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH11_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH11_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH11_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH11_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x12F0++0x3 line.long 0x0 "TOM0_CH11_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1300++0x2B line.long 0x0 "TOM0_CH12_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH12_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH12_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH12_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH12_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH12_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH12_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH12_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH12_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH12_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH12_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1330++0x3 line.long 0x0 "TOM0_CH12_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1340++0x2B line.long 0x0 "TOM0_CH13_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH13_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH13_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH13_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH13_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH13_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH13_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH13_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH13_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH13_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH13_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1370++0x3 line.long 0x0 "TOM0_CH13_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1380++0x2B line.long 0x0 "TOM0_CH14_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH14_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH14_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH14_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH14_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH14_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH14_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH14_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH14_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH14_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH14_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x13B0++0x3 line.long 0x0 "TOM0_CH14_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x13C0++0x2B line.long 0x0 "TOM0_CH15_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM0_CH15_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM0_CH15_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM0_CH15_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM0_CH15_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM0_CH15_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM0_CH15_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM0_CH15_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM0_CH15_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM0_CH15_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM0_CH15_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x13F0++0x3 line.long 0x0 "TOM0_CH15_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1430++0xF line.long 0x0 "TOM0_TGC0_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 28.--29. "UPEN_CTRL6,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 26.--27. "UPEN_CTRL5,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 24.--25. "UPEN_CTRL4,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 22.--23. "UPEN_CTRL3,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 20.--21. "UPEN_CTRL2,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 16.--17. "UPEN_CTRL0,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 15. "RST_CH7,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 14. "RST_CH6,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 13. "RST_CH5,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 12. "RST_CH4,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 10. "RST_CH2,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 9. "RST_CH1,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 8. "RST_CH0,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see TGC0 TGC1) to update the register TOM[i]_TGC[g]_ENDIS_STAT and TOM[i]_TGC[g]_OUTEN_STAT" "0,1" line.long 0x4 "TOM0_TGC0_ACT_TB," bitfld.long 0x4 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" newline bitfld.long 0x4 24. "TB_TRIG,Set trigger request" "0,1" newline hexmask.long.tbyte 0x4 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[y] y=0..2. If selected TBU_TS[y] value is in the interval [TOM[i]_TGC[g]_ACT_TB.ACT_TB-007FFFFFh TOM[i]_TGC[g]_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x8 "TOM0_TGC0_FUPD_CTRL," bitfld.long 0x8 30.--31. "RSTCN0_CH7,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 28.--29. "RSTCN0_CH6,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 26.--27. "RSTCN0_CH5,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 24.--25. "RSTCN0_CH4,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 22.--23. "RSTCN0_CH3,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 20.--21. "RSTCN0_CH2,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 18.--19. "RSTCN0_CH1,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 16.--17. "RSTCN0_CH0,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 14.--15. "FUPD_CTRL7,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 12.--13. "FUPD_CTRL6,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 10.--11. "FUPD_CTRL5,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 8.--9. "FUPD_CTRL4,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 6.--7. "FUPD_CTRL3,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 4.--5. "FUPD_CTRL2,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 2.--3. "FUPD_CTRL1,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 0.--1. "FUPD_CTRL0,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" line.long 0xC "TOM0_TGC0_INT_TRIG," bitfld.long 0xC 14.--15. "INT_TRIG7,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 12.--13. "INT_TRIG6,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 10.--11. "INT_TRIG5,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "INT_TRIG4,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 6.--7. "INT_TRIG3,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 4.--5. "INT_TRIG2,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "INT_TRIG1,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 0.--1. "INT_TRIG0,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" group.long 0x1470++0xF line.long 0x0 "TOM0_TGC0_ENDIS_CTRL," bitfld.long 0x0 14.--15. "ENDIS_CTRL7,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 12.--13. "ENDIS_CTRL6,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 10.--11. "ENDIS_CTRL5,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 8.--9. "ENDIS_CTRL4,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 6.--7. "ENDIS_CTRL3,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ENDIS_CTRL2,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 2.--3. "ENDIS_CTRL1,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 0.--1. "ENDIS_CTRL0,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" line.long 0x4 "TOM0_TGC0_ENDIS_STAT," bitfld.long 0x4 14.--15. "ENDIS_STAT7,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 12.--13. "ENDIS_STAT6,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 10.--11. "ENDIS_STAT5,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 8.--9. "ENDIS_STAT4,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 6.--7. "ENDIS_STAT3,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 4.--5. "ENDIS_STAT2,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_STAT1,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 0.--1. "ENDIS_STAT0,TOM channel x=c + g*8 enable/disable" "0,1,2,3" line.long 0x8 "TOM0_TGC0_OUTEN_CTRL," bitfld.long 0x8 14.--15. "OUTEN_CTRL7,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 12.--13. "OUTEN_CTRL6,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OUTEN_CTRL5,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 8.--9. "OUTEN_CTRL4,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OUTEN_CTRL3,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 4.--5. "OUTEN_CTRL2,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OUTEN_CTRL1,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 0.--1. "OUTEN_CTRL0,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" line.long 0xC "TOM0_TGC0_OUTEN_STAT," bitfld.long 0xC 14.--15. "OUTEN_STAT7,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 12.--13. "OUTEN_STAT6,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 10.--11. "OUTEN_STAT5,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "OUTEN_STAT4,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 6.--7. "OUTEN_STAT3,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 4.--5. "OUTEN_STAT2,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "OUTEN_STAT1,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 0.--1. "OUTEN_STAT0,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" group.long 0x14B0++0xF line.long 0x0 "TOM0_TGC1_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 28.--29. "UPEN_CTRL6,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 26.--27. "UPEN_CTRL5,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 24.--25. "UPEN_CTRL4,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 22.--23. "UPEN_CTRL3,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 20.--21. "UPEN_CTRL2,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 16.--17. "UPEN_CTRL0,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 15. "RST_CH7,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 14. "RST_CH6,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 13. "RST_CH5,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 12. "RST_CH4,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 10. "RST_CH2,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 9. "RST_CH1,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 8. "RST_CH0,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see TGC0 TGC1) to update the register TOM[i]_TGC[g]_ENDIS_STAT and TOM[i]_TGC[g]_OUTEN_STAT" "0,1" line.long 0x4 "TOM0_TGC1_ACT_TB," bitfld.long 0x4 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" newline bitfld.long 0x4 24. "TB_TRIG,Set trigger request" "0,1" newline hexmask.long.tbyte 0x4 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[y] y=0..2. If selected TBU_TS[y] value is in the interval [TOM[i]_TGC[g]_ACT_TB.ACT_TB-007FFFFFh TOM[i]_TGC[g]_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x8 "TOM0_TGC1_FUPD_CTRL," bitfld.long 0x8 30.--31. "RSTCN0_CH7,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 28.--29. "RSTCN0_CH6,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 26.--27. "RSTCN0_CH5,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 24.--25. "RSTCN0_CH4,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 22.--23. "RSTCN0_CH3,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 20.--21. "RSTCN0_CH2,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 18.--19. "RSTCN0_CH1,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 16.--17. "RSTCN0_CH0,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 14.--15. "FUPD_CTRL7,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 12.--13. "FUPD_CTRL6,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 10.--11. "FUPD_CTRL5,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 8.--9. "FUPD_CTRL4,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 6.--7. "FUPD_CTRL3,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 4.--5. "FUPD_CTRL2,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 2.--3. "FUPD_CTRL1,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 0.--1. "FUPD_CTRL0,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" line.long 0xC "TOM0_TGC1_INT_TRIG," bitfld.long 0xC 14.--15. "INT_TRIG7,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 12.--13. "INT_TRIG6,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 10.--11. "INT_TRIG5,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "INT_TRIG4,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 6.--7. "INT_TRIG3,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 4.--5. "INT_TRIG2,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "INT_TRIG1,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 0.--1. "INT_TRIG0,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" group.long 0x14F0++0xF line.long 0x0 "TOM0_TGC1_ENDIS_CTRL," bitfld.long 0x0 14.--15. "ENDIS_CTRL7,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 12.--13. "ENDIS_CTRL6,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 10.--11. "ENDIS_CTRL5,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 8.--9. "ENDIS_CTRL4,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 6.--7. "ENDIS_CTRL3,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ENDIS_CTRL2,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 2.--3. "ENDIS_CTRL1,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 0.--1. "ENDIS_CTRL0,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" line.long 0x4 "TOM0_TGC1_ENDIS_STAT," bitfld.long 0x4 14.--15. "ENDIS_STAT7,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 12.--13. "ENDIS_STAT6,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 10.--11. "ENDIS_STAT5,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 8.--9. "ENDIS_STAT4,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 6.--7. "ENDIS_STAT3,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 4.--5. "ENDIS_STAT2,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_STAT1,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 0.--1. "ENDIS_STAT0,TOM channel x=c + g*8 enable/disable" "0,1,2,3" line.long 0x8 "TOM0_TGC1_OUTEN_CTRL," bitfld.long 0x8 14.--15. "OUTEN_CTRL7,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 12.--13. "OUTEN_CTRL6,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OUTEN_CTRL5,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 8.--9. "OUTEN_CTRL4,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OUTEN_CTRL3,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 4.--5. "OUTEN_CTRL2,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OUTEN_CTRL1,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 0.--1. "OUTEN_CTRL0,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" line.long 0xC "TOM0_TGC1_OUTEN_STAT," bitfld.long 0xC 14.--15. "OUTEN_STAT7,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 12.--13. "OUTEN_STAT6,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 10.--11. "OUTEN_STAT5,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "OUTEN_STAT4,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 6.--7. "OUTEN_STAT3,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 4.--5. "OUTEN_STAT2,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "OUTEN_STAT1,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 0.--1. "OUTEN_STAT0,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" group.long 0x1800++0x2F line.long 0x0 "ATOM0_CH0_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM0_CH0_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM0_CH0_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM0_CH0_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM0_CH0_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM0_CH0_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM0_CH0_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM0_CH0_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM0_CH0_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM0_CH0_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM0_CH0_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM0_CH0_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1834++0x3 line.long 0x0 "ATOM0_CH0_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1880++0x2F line.long 0x0 "ATOM0_CH1_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM0_CH1_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM0_CH1_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM0_CH1_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM0_CH1_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM0_CH1_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM0_CH1_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM0_CH1_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM0_CH1_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM0_CH1_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM0_CH1_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM0_CH1_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x18B4++0x3 line.long 0x0 "ATOM0_CH1_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1900++0x2F line.long 0x0 "ATOM0_CH2_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM0_CH2_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM0_CH2_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM0_CH2_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM0_CH2_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM0_CH2_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM0_CH2_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM0_CH2_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM0_CH2_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM0_CH2_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM0_CH2_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM0_CH2_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1934++0x3 line.long 0x0 "ATOM0_CH2_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1980++0x2F line.long 0x0 "ATOM0_CH3_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM0_CH3_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM0_CH3_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM0_CH3_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM0_CH3_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM0_CH3_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM0_CH3_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM0_CH3_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM0_CH3_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM0_CH3_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM0_CH3_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM0_CH3_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x19B4++0x3 line.long 0x0 "ATOM0_CH3_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A00++0x2F line.long 0x0 "ATOM0_CH4_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM0_CH4_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM0_CH4_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM0_CH4_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM0_CH4_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM0_CH4_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM0_CH4_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM0_CH4_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM0_CH4_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM0_CH4_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM0_CH4_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM0_CH4_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1A34++0x3 line.long 0x0 "ATOM0_CH4_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A80++0x2F line.long 0x0 "ATOM0_CH5_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM0_CH5_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM0_CH5_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM0_CH5_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM0_CH5_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM0_CH5_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM0_CH5_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM0_CH5_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM0_CH5_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM0_CH5_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM0_CH5_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM0_CH5_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1AB4++0x3 line.long 0x0 "ATOM0_CH5_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B00++0x2F line.long 0x0 "ATOM0_CH6_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM0_CH6_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM0_CH6_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM0_CH6_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM0_CH6_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM0_CH6_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM0_CH6_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM0_CH6_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM0_CH6_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM0_CH6_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM0_CH6_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM0_CH6_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1B34++0x3 line.long 0x0 "ATOM0_CH6_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B80++0x2F line.long 0x0 "ATOM0_CH7_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM0_CH7_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM0_CH7_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM0_CH7_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM0_CH7_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM0_CH7_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM0_CH7_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM0_CH7_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM0_CH7_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM0_CH7_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM0_CH7_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM0_CH7_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1BB4++0x3 line.long 0x0 "ATOM0_CH7_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1C40++0x1F line.long 0x0 "ATOM0_AGC_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 28.--29. "UPEN_CTRL6,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 26.--27. "UPEN_CTRL5,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 24.--25. "UPEN_CTRL4,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 22.--23. "UPEN_CTRL3,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 20.--21. "UPEN_CTRL2,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 16.--17. "UPEN_CTRL0,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 15. "RST_CH7,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 14. "RST_CH6,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 13. "RST_CH5,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 12. "RST_CH4,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 10. "RST_CH2,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 9. "RST_CH1,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 8. "RST_CH0,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see AGC) to update the register ATOM[i]_AGC_ENDIS_STAT and ATOM[i]_AGC_OUTEN_STAT" "0,1" line.long 0x4 "ATOM0_AGC_ENDIS_CTRL," bitfld.long 0x4 14.--15. "ENDIS_CTRL7,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 12.--13. "ENDIS_CTRL6,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 10.--11. "ENDIS_CTRL5,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 8.--9. "ENDIS_CTRL4,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 6.--7. "ENDIS_CTRL3,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 4.--5. "ENDIS_CTRL2,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_CTRL1,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 0.--1. "ENDIS_CTRL0,ATOM channel [k] enable/disable update value." "0,1,2,3" line.long 0x8 "ATOM0_AGC_ENDIS_STAT," bitfld.long 0x8 14.--15. "ENDIS_STAT7,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 12.--13. "ENDIS_STAT6,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 10.--11. "ENDIS_STAT5,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 8.--9. "ENDIS_STAT4,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 6.--7. "ENDIS_STAT3,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 4.--5. "ENDIS_STAT2,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 2.--3. "ENDIS_STAT1,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 0.--1. "ENDIS_STAT0,ATOM channel [k] enable/disable" "0,1,2,3" line.long 0xC "ATOM0_AGC_ACT_TB," bitfld.long 0xC 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" newline bitfld.long 0xC 24. "TB_TRIG,Set trigger request" "0,1" newline hexmask.long.tbyte 0xC 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[x] x=0..2. If selected TBU_TS[x] value is in the interval [ATOM[i]_AGC_ACT_TB.ACT_TB-007FFFFFh ATOM[i]_AGC_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x10 "ATOM0_AGC_OUTEN_CTRL," bitfld.long 0x10 14.--15. "OUTEN_CTRL7,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 12.--13. "OUTEN_CTRL6,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 10.--11. "OUTEN_CTRL5,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 8.--9. "OUTEN_CTRL4,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 6.--7. "OUTEN_CTRL3,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 4.--5. "OUTEN_CTRL2,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 2.--3. "OUTEN_CTRL1,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 0.--1. "OUTEN_CTRL0,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" line.long 0x14 "ATOM0_AGC_OUTEN_STAT," bitfld.long 0x14 14.--15. "OUTEN_STAT7,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 12.--13. "OUTEN_STAT6,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 10.--11. "OUTEN_STAT5,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 8.--9. "OUTEN_STAT4,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 6.--7. "OUTEN_STAT3,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 4.--5. "OUTEN_STAT2,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 2.--3. "OUTEN_STAT1,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 0.--1. "OUTEN_STAT0,Control/status of output ATOM_OUT [k]" "0,1,2,3" line.long 0x18 "ATOM0_AGC_FUPD_CTRL," bitfld.long 0x18 30.--31. "RSTCN0_CH7,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 28.--29. "RSTCN0_CH6,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 26.--27. "RSTCN0_CH5,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 24.--25. "RSTCN0_CH4,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 22.--23. "RSTCN0_CH3,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 20.--21. "RSTCN0_CH2,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 18.--19. "RSTCN0_CH1,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 16.--17. "RSTCN0_CH0,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 14.--15. "FUPD_CTRL7,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 12.--13. "FUPD_CTRL6,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 10.--11. "FUPD_CTRL5,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 8.--9. "FUPD_CTRL4,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 6.--7. "FUPD_CTRL3,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 4.--5. "FUPD_CTRL2,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 2.--3. "FUPD_CTRL1,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 0.--1. "FUPD_CTRL0,Force update of ATOM channel [k] operation registers" "0,1,2,3" line.long 0x1C "ATOM0_AGC_INT_TRIG," bitfld.long 0x1C 14.--15. "INT_TRIG7,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 12.--13. "INT_TRIG6,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 10.--11. "INT_TRIG5,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 8.--9. "INT_TRIG4,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 6.--7. "INT_TRIG3,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 4.--5. "INT_TRIG2,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 2.--3. "INT_TRIG1,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "INT_TRIG0,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" group.long 0x2000++0x27 line.long 0x0 "MCS0_CH0_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS0_CH0_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS0_CH0_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS0_CH0_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS0_CH0_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS0_CH0_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS0_CH0_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS0_CH0_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS0_CH0_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS0_CH0_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x203C++0x3 line.long 0x0 "MCS0_CH0_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x20E0++0x17 line.long 0x0 "MCS0_CH0_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS0_CH0_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS0_CH0_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS0_CH0_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS0_CH0_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS0_CH0_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2100++0x27 line.long 0x0 "MCS0_CH1_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS0_CH1_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS0_CH1_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS0_CH1_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS0_CH1_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS0_CH1_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS0_CH1_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS0_CH1_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS0_CH1_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS0_CH1_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x213C++0x3 line.long 0x0 "MCS0_CH1_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x21E0++0x17 line.long 0x0 "MCS0_CH1_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS0_CH1_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS0_CH1_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS0_CH1_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS0_CH1_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS0_CH1_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2200++0x27 line.long 0x0 "MCS0_CH2_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS0_CH2_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS0_CH2_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS0_CH2_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS0_CH2_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS0_CH2_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS0_CH2_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS0_CH2_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS0_CH2_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS0_CH2_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x223C++0x3 line.long 0x0 "MCS0_CH2_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x22E0++0x17 line.long 0x0 "MCS0_CH2_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS0_CH2_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS0_CH2_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS0_CH2_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS0_CH2_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS0_CH2_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2300++0x27 line.long 0x0 "MCS0_CH3_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS0_CH3_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS0_CH3_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS0_CH3_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS0_CH3_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS0_CH3_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS0_CH3_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS0_CH3_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS0_CH3_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS0_CH3_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x233C++0x3 line.long 0x0 "MCS0_CH3_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x23E0++0x17 line.long 0x0 "MCS0_CH3_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS0_CH3_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS0_CH3_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS0_CH3_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS0_CH3_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS0_CH3_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2400++0x27 line.long 0x0 "MCS0_CH4_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS0_CH4_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS0_CH4_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS0_CH4_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS0_CH4_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS0_CH4_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS0_CH4_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS0_CH4_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS0_CH4_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS0_CH4_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x243C++0x3 line.long 0x0 "MCS0_CH4_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x24E0++0x17 line.long 0x0 "MCS0_CH4_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS0_CH4_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS0_CH4_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS0_CH4_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS0_CH4_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS0_CH4_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2500++0x27 line.long 0x0 "MCS0_CH5_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS0_CH5_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS0_CH5_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS0_CH5_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS0_CH5_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS0_CH5_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS0_CH5_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS0_CH5_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS0_CH5_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS0_CH5_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x253C++0x3 line.long 0x0 "MCS0_CH5_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x25E0++0x17 line.long 0x0 "MCS0_CH5_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS0_CH5_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS0_CH5_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS0_CH5_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS0_CH5_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS0_CH5_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2600++0x27 line.long 0x0 "MCS0_CH6_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS0_CH6_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS0_CH6_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS0_CH6_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS0_CH6_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS0_CH6_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS0_CH6_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS0_CH6_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS0_CH6_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS0_CH6_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x263C++0x3 line.long 0x0 "MCS0_CH6_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x26E0++0x17 line.long 0x0 "MCS0_CH6_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS0_CH6_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS0_CH6_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS0_CH6_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS0_CH6_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS0_CH6_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2700++0x27 line.long 0x0 "MCS0_CH7_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS0_CH7_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS0_CH7_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS0_CH7_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS0_CH7_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS0_CH7_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS0_CH7_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS0_CH7_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS0_CH7_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS0_CH7_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x273C++0x3 line.long 0x0 "MCS0_CH7_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x27E0++0x17 line.long 0x0 "MCS0_CH7_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS0_CH7_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS0_CH7_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS0_CH7_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS0_CH7_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS0_CH7_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2E28++0x7 line.long 0x0 "MCS0_CTRG," bitfld.long 0x0 23. "TRG23,Trigger bit o." "0,1" newline bitfld.long 0x0 22. "TRG22,Trigger bit o." "0,1" newline bitfld.long 0x0 21. "TRG21,Trigger bit o." "0,1" newline bitfld.long 0x0 20. "TRG20,Trigger bit o." "0,1" newline bitfld.long 0x0 19. "TRG19,Trigger bit o." "0,1" newline bitfld.long 0x0 18. "TRG18,Trigger bit o." "0,1" newline bitfld.long 0x0 17. "TRG17,Trigger bit o." "0,1" newline bitfld.long 0x0 16. "TRG16,Trigger bit o." "0,1" newline bitfld.long 0x0 15. "TRG15,Trigger bit n." "0,1" newline bitfld.long 0x0 14. "TRG14,Trigger bit n." "0,1" newline bitfld.long 0x0 13. "TRG13,Trigger bit n." "0,1" newline bitfld.long 0x0 12. "TRG12,Trigger bit n." "0,1" newline bitfld.long 0x0 11. "TRG11,Trigger bit n." "0,1" newline bitfld.long 0x0 10. "TRG10,Trigger bit n." "0,1" newline bitfld.long 0x0 9. "TRG9,Trigger bit n." "0,1" newline bitfld.long 0x0 8. "TRG8,Trigger bit n." "0,1" newline bitfld.long 0x0 7. "TRG7,Trigger bit m." "0,1" newline bitfld.long 0x0 6. "TRG6,Trigger bit m." "0,1" newline bitfld.long 0x0 5. "TRG5,Trigger bit m." "0,1" newline bitfld.long 0x0 4. "TRG4,Trigger bit m." "0,1" newline bitfld.long 0x0 3. "TRG3,Trigger bit m." "0,1" newline bitfld.long 0x0 2. "TRG2,Trigger bit m." "0,1" newline bitfld.long 0x0 1. "TRG1,Trigger bit m." "0,1" newline bitfld.long 0x0 0. "TRG0,Trigger bit m." "0,1" line.long 0x4 "MCS0_STRG," bitfld.long 0x4 23. "TRG23,Trigger bit k." "0,1" newline bitfld.long 0x4 22. "TRG22,Trigger bit k." "0,1" newline bitfld.long 0x4 21. "TRG21,Trigger bit k." "0,1" newline bitfld.long 0x4 20. "TRG20,Trigger bit k." "0,1" newline bitfld.long 0x4 19. "TRG19,Trigger bit k." "0,1" newline bitfld.long 0x4 18. "TRG18,Trigger bit k." "0,1" newline bitfld.long 0x4 17. "TRG17,Trigger bit k." "0,1" newline bitfld.long 0x4 16. "TRG16,Trigger bit k." "0,1" newline bitfld.long 0x4 15. "TRG15,Trigger bit k." "0,1" newline bitfld.long 0x4 14. "TRG14,Trigger bit k." "0,1" newline bitfld.long 0x4 13. "TRG13,Trigger bit k." "0,1" newline bitfld.long 0x4 12. "TRG12,Trigger bit k." "0,1" newline bitfld.long 0x4 11. "TRG11,Trigger bit k." "0,1" newline bitfld.long 0x4 10. "TRG10,Trigger bit k." "0,1" newline bitfld.long 0x4 9. "TRG9,Trigger bit k." "0,1" newline bitfld.long 0x4 8. "TRG8,Trigger bit k." "0,1" newline bitfld.long 0x4 7. "TRG7,Trigger bit k." "0,1" newline bitfld.long 0x4 6. "TRG6,Trigger bit k." "0,1" newline bitfld.long 0x4 5. "TRG5,Trigger bit k." "0,1" newline bitfld.long 0x4 4. "TRG4,Trigger bit k." "0,1" newline bitfld.long 0x4 3. "TRG3,Trigger bit k." "0,1" newline bitfld.long 0x4 2. "TRG2,Trigger bit k." "0,1" newline bitfld.long 0x4 1. "TRG1,Trigger bit k." "0,1" newline bitfld.long 0x4 0. "TRG0,Trigger bit k." "0,1" group.long 0x2F00++0x13 line.long 0x0 "MCS0_CTRL_STAT," bitfld.long 0x0 26. "HLT_AEIM_ERR,Halt on AEI bus master error." "0,1" newline bitfld.long 0x0 25. "EN_HVD,Enable Modified Harvard architecture." "0,1" newline bitfld.long 0x0 24. "EN_TIM_FOUT,Enable routing of TIM[i]_CH[x]_F_OUT signal." "0,1" newline bitfld.long 0x0 20.--22. "ERR_SRC_ID,Error source identifier." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "RAM_RST,RAM reset bit." "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "SCD_CH,Channel selection for scheduling algorithm." newline bitfld.long 0x0 0.--1. "SCD_MODE,Select MCS scheduling mode" "0,1,2,3" line.long 0x4 "MCS0_RESET," bitfld.long 0x4 7. "RST7,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 6. "RST6,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 5. "RST5,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 4. "RST4,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 3. "RST3,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 2. "RST2,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 1. "RST1,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 0. "RST0,Software reset of channel [k]" "0,1" line.long 0x8 "MCS0_CAT," bitfld.long 0x8 7. "CAT7,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 6. "CAT6,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 5. "CAT5,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 4. "CAT4,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 3. "CAT3,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 2. "CAT2,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 1. "CAT1,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 0. "CAT0,Cancel ARU transfer of channel [k]." "0,1" line.long 0xC "MCS0_CWT," bitfld.long 0xC 7. "CWT7,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 6. "CWT6,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 5. "CWT5,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 4. "CWT4,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 3. "CWT3,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 2. "CWT2,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 1. "CWT1,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 0. "CWT0,Cancel waiting instruction for channel [k]." "0,1" line.long 0x10 "MCS0_ERR," bitfld.long 0x10 7. "ERR7,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 6. "ERR6,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 5. "ERR5,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 4. "ERR4,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 3. "ERR3,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 2. "ERR2,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 1. "ERR1,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 0. "ERR0,Error State of MCS-channel [k]." "0,1" group.long 0x2F1C++0x13 line.long 0x0 "MCS0_REG_PROT," bitfld.long 0x0 14.--15. "WPROT7,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 12.--13. "WPROT6,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 10.--11. "WPROT5,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 8.--9. "WPROT4,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 6.--7. "WPROT3,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 4.--5. "WPROT2,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 2.--3. "WPROT1,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 0.--1. "WPROT0,Register Write Protection of MCS-channel k." "0,1,2,3" line.long 0x4 "MCS0_SINT_IRQ_NOTIFY," bitfld.long 0x4 7. "S_IRQ7,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 6. "S_IRQ6,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 5. "S_IRQ5,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 4. "S_IRQ4,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 3. "S_IRQ3,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 2. "S_IRQ2,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 1. "S_IRQ1,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 0. "S_IRQ0,Shared interrupt [k] notify flag." "0,1" line.long 0x8 "MCS0_SINT_IRQ_EN," bitfld.long 0x8 7. "S_IRQ7_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 6. "S_IRQ6_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 5. "S_IRQ5_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 4. "S_IRQ4_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 3. "S_IRQ3_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 2. "S_IRQ2_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 1. "S_IRQ1_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 0. "S_IRQ0_EN,Shared interrupt [k]" "0,1" line.long 0xC "MCS0_SINT_IRQ_FORCINT," bitfld.long 0xC 7. "TRG_S_IRQ7,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 6. "TRG_S_IRQ6,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 5. "TRG_S_IRQ5,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 4. "TRG_S_IRQ4,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 3. "TRG_S_IRQ3,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 2. "TRG_S_IRQ2,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 1. "TRG_S_IRQ1,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 0. "TRG_S_IRQ0,Trigger IRQ [k] in shared interrupt register" "0,1" line.long 0x10 "MCS0_SINT_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x2F40++0x1B line.long 0x0 "MCS0_HBP0_CTRL," bitfld.long 0x0 17. "NOT,Logical negation of h-th hardware break point." "0,1" newline bitfld.long 0x0 16. "AND,Logical AND conjunction of h-th hardware break point." "0,1" newline bitfld.long 0x0 12.--14. "TYPE,Define type of h-th hardware break point." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--9. "SCOPE,Define scope of h-th hardware break point." "0,1,2,3" newline bitfld.long 0x0 7. "EN_CH7,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 6. "EN_CH6,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 5. "EN_CH5,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 4. "EN_CH4,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 3. "EN_CH3,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 2. "EN_CH2,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 1. "EN_CH1,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 0. "EN_CH0,Enable h-th hardware break point for channel x." "0,1" line.long 0x4 "MCS0_HBP0_PATTERN," hexmask.long 0x4 0.--31. 1. "DATA,Define pattern or address of h-th hardware break point." line.long 0x8 "MCS0_HBP0_STATUS," bitfld.long 0x8 7. "HALT_CH7,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 6. "HALT_CH6,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 5. "HALT_CH5,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 4. "HALT_CH4,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 3. "HALT_CH3,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 2. "HALT_CH2,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 1. "HALT_CH1,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 0. "HALT_CH0,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" line.long 0xC "MCS0_HBP0_IRQ_NOTIFY," bitfld.long 0xC 0. "HBP_IRQ,Interrupt notify flag of the h-th hardware break point." "0,1" line.long 0x10 "MCS0_HBP0_IRQ_EN," bitfld.long 0x10 0. "HBP_IRQ_EN,Interrupt Enable bit of the h-th hardware break point." "0,1" line.long 0x14 "MCS0_HBP0_IRQ_FORCINT," bitfld.long 0x14 0. "TRG_HBP_IRQ,Trigger IRQ of the h-th hardware break point." "0,1" line.long 0x18 "MCS0_HBP0_IRQ_MODE," bitfld.long 0x18 0.--1. "IRQ_MODE,IRQ mode selection for all break point interrupts." "0,1,2,3" group.long 0x2F60++0x1B line.long 0x0 "MCS0_HBP1_CTRL," bitfld.long 0x0 17. "NOT,Logical negation of h-th hardware break point." "0,1" newline bitfld.long 0x0 16. "AND,Logical AND conjunction of h-th hardware break point." "0,1" newline bitfld.long 0x0 12.--14. "TYPE,Define type of h-th hardware break point." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--9. "SCOPE,Define scope of h-th hardware break point." "0,1,2,3" newline bitfld.long 0x0 7. "EN_CH7,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 6. "EN_CH6,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 5. "EN_CH5,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 4. "EN_CH4,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 3. "EN_CH3,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 2. "EN_CH2,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 1. "EN_CH1,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 0. "EN_CH0,Enable h-th hardware break point for channel x." "0,1" line.long 0x4 "MCS0_HBP1_PATTERN," hexmask.long 0x4 0.--31. 1. "DATA,Define pattern or address of h-th hardware break point." line.long 0x8 "MCS0_HBP1_STATUS," bitfld.long 0x8 7. "HALT_CH7,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 6. "HALT_CH6,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 5. "HALT_CH5,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 4. "HALT_CH4,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 3. "HALT_CH3,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 2. "HALT_CH2,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 1. "HALT_CH1,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 0. "HALT_CH0,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" line.long 0xC "MCS0_HBP1_IRQ_NOTIFY," bitfld.long 0xC 0. "HBP_IRQ,Interrupt notify flag of the h-th hardware break point." "0,1" line.long 0x10 "MCS0_HBP1_IRQ_EN," bitfld.long 0x10 0. "HBP_IRQ_EN,Interrupt Enable bit of the h-th hardware break point." "0,1" line.long 0x14 "MCS0_HBP1_IRQ_FORCINT," bitfld.long 0x14 0. "TRG_HBP_IRQ,Trigger IRQ of the h-th hardware break point." "0,1" line.long 0x18 "MCS0_HBP1_IRQ_MODE," bitfld.long 0x18 0.--1. "IRQ_MODE,IRQ mode selection for all break point interrupts." "0,1,2,3" group.long 0x4000++0x4F line.long 0x0 "CCM0_ARP0_CTRL," bitfld.long 0x0 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x0 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x0 0.--15. 1. "ADDR,ARP base address." line.long 0x4 "CCM0_ARP0_PROT," bitfld.long 0x4 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x8 "CCM0_ARP1_CTRL," bitfld.long 0x8 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x8 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x8 0.--15. 1. "ADDR,ARP base address." line.long 0xC "CCM0_ARP1_PROT," bitfld.long 0xC 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x10 "CCM0_ARP2_CTRL," bitfld.long 0x10 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x10 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x10 0.--15. 1. "ADDR,ARP base address." line.long 0x14 "CCM0_ARP2_PROT," bitfld.long 0x14 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x18 "CCM0_ARP3_CTRL," bitfld.long 0x18 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x18 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x18 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x18 0.--15. 1. "ADDR,ARP base address." line.long 0x1C "CCM0_ARP3_PROT," bitfld.long 0x1C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x20 "CCM0_ARP4_CTRL," bitfld.long 0x20 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x20 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x20 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x20 0.--15. 1. "ADDR,ARP base address." line.long 0x24 "CCM0_ARP4_PROT," bitfld.long 0x24 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x28 "CCM0_ARP5_CTRL," bitfld.long 0x28 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x28 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x28 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x28 0.--15. 1. "ADDR,ARP base address." line.long 0x2C "CCM0_ARP5_PROT," bitfld.long 0x2C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x30 "CCM0_ARP6_CTRL," bitfld.long 0x30 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x30 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x30 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x30 0.--15. 1. "ADDR,ARP base address." line.long 0x34 "CCM0_ARP6_PROT," bitfld.long 0x34 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x38 "CCM0_ARP7_CTRL," bitfld.long 0x38 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x38 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x38 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x38 0.--15. 1. "ADDR,ARP base address." line.long 0x3C "CCM0_ARP7_PROT," bitfld.long 0x3C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x40 "CCM0_ARP8_CTRL," bitfld.long 0x40 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x40 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x40 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x40 0.--15. 1. "ADDR,ARP base address." line.long 0x44 "CCM0_ARP8_PROT," bitfld.long 0x44 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x48 "CCM0_ARP9_CTRL," bitfld.long 0x48 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x48 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x48 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x48 0.--15. 1. "ADDR,ARP base address." line.long 0x4C "CCM0_ARP9_PROT," bitfld.long 0x4C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 0. "WPROT0,Write Protection MCS channel x." "0,1" group.long 0x41D4++0x2B line.long 0x0 "CCM0_HW_CONF2," bitfld.long 0x0 18. "AXIM_DATA_SIZE,Defines the data bus width of the AXI master interface" "0,1" newline bitfld.long 0x0 16. "AXIS_DATA_SIZE,Defines the data bus width of the AXI slave interface" "0,1" newline bitfld.long 0x0 9. "TIO_OUT_RST,TIO_OUT reset level" "0,1" newline bitfld.long 0x0 7. "AXIM_POSTED_WRITE,Write transaction without response" "0,1" newline bitfld.long 0x0 6. "AXIM_SEC_ACC,Secure AXI master access constant" "0,1" newline bitfld.long 0x0 5. "AXIM_PRIV_ACC,Privileged AXI master access constant" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "AXIM_ID_WIDTH,Defines which LSB of AXIM_ID are send to the bus" line.long 0x4 "CCM0_AEIM_STA," bitfld.long 0x4 24.--25. "AEIM_XPT_STA,AEIM Exception status." "0,1,2,3" newline hexmask.long.word 0x4 0.--15. 1. "AEIM_XPT_ADDR,Exception Address." line.long 0x8 "CCM0_HW_CONF," bitfld.long 0x8 31. "AEI_RDATA_PIPELINE_STAGE,Read data pipeline stage implemented" "0,1" newline bitfld.long 0x8 30. "AEI_ADDR_PIPELINE_STAGE,Address pipeline stage implemented" "0,1" newline bitfld.long 0x8 29. "INT_CLK_EN_GEN,Internal clock enable generation" "0,1" newline hexmask.long.byte 0x8 24.--28. 1. "TOM_TRIG_INTCHAIN,TOM internal trigger chain length without synchronization register" newline hexmask.long.byte 0x8 20.--23. 1. "ATOM_TRIG_INTCHAIN,ATOM internal trigger chain length without synchronization register" newline bitfld.long 0x8 19. "IRQ_MODE_SINGLE_PULSE,Signalize availability of Single Pulse IRQ mode" "0,1" newline bitfld.long 0x8 18. "IRQ_MODE_PULSE_NOTIFY,Signalize availability of Pulse Notoify IRQ mode" "0,1" newline bitfld.long 0x8 17. "IRQ_MODE_PULSE,Signalize availability of Pulse IRQ mode" "0,1" newline bitfld.long 0x8 16. "IRQ_MODE_LEVEL,Signalize availability of Level IRQ mode" "0,1" newline bitfld.long 0x8 15. "RESET_ACTIVE,Active level of asynchronous reset" "0,1" newline bitfld.long 0x8 13. "ERM,Enable RAM1 MSB for available MCS modules" "0,1" newline bitfld.long 0x8 12. "RAM_INIT_RST,RAM initialization from reset" "0,1" newline bitfld.long 0x8 9.--11. "TOM_TRIG_CHAIN,TOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "TOM_OUT_RST,TOM_OUT reset level" "0,1" newline bitfld.long 0x8 5.--7. "ATOM_TRIG_CHAIN,ATOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "ATOM_OUT_RST,ATOM_OUT reset level" "0,1" newline bitfld.long 0x8 3. "CFG_CLOCK_RATE,Clocks per ARU transfer" "0,1" newline bitfld.long 0x8 2. "SYNC_INPUT_REG,Additional pipelined stage in synchronous bridge mode" "0,1" newline bitfld.long 0x8 1. "BRIDGE_MODE_RST,Bridge mode after reset" "0,1" newline bitfld.long 0x8 0. "GRSTEN,Global Reset Enable" "0,1" line.long 0xC "CCM0_TIM_AUX_IN_SRC," bitfld.long 0xC 23. "SEL_OUT_N_CH7,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 22. "SEL_OUT_N_CH6,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 21. "SEL_OUT_N_CH5,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 20. "SEL_OUT_N_CH4,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 19. "SEL_OUT_N_CH3,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 18. "SEL_OUT_N_CH2,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 17. "SEL_OUT_N_CH1,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 16. "SEL_OUT_N_CH0,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 7. "SRC_CH7,Defines AUX_IN source of TIM[i] channel 7" "0,1" newline bitfld.long 0xC 6. "SRC_CH6,Defines AUX_IN source of TIM[i] channel 6" "0,1" newline bitfld.long 0xC 5. "SRC_CH5,Defines AUX_IN source of TIM[i] channel 5" "0,1" newline bitfld.long 0xC 4. "SRC_CH4,Defines AUX_IN source of TIM[i] channel 4" "0,1" newline bitfld.long 0xC 3. "SRC_CH3,Defines AUX_IN source of TIM[i] channel 3" "0,1" newline bitfld.long 0xC 2. "SRC_CH2,Defines AUX_IN source of TIM[i] channel 2" "0,1" newline bitfld.long 0xC 1. "SRC_CH1,Defines AUX_IN source of TIM[i] channel 1" "0,1" newline bitfld.long 0xC 0. "SRC_CH0,Defines AUX_IN source of TIM[i] channel 0" "0,1" line.long 0x10 "CCM0_EXT_CAP_EN," bitfld.long 0x10 15. "TIM_IP1_EXT_CAP_EN7,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 14. "TIM_IP1_EXT_CAP_EN6,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 13. "TIM_IP1_EXT_CAP_EN5,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 12. "TIM_IP1_EXT_CAP_EN4,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 11. "TIM_IP1_EXT_CAP_EN3,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 10. "TIM_IP1_EXT_CAP_EN2,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 9. "TIM_IP1_EXT_CAP_EN1,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 8. "TIM_IP1_EXT_CAP_EN0,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 7. "TIM_I_EXT_CAP_EN7,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 6. "TIM_I_EXT_CAP_EN6,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 5. "TIM_I_EXT_CAP_EN5,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 4. "TIM_I_EXT_CAP_EN4,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 3. "TIM_I_EXT_CAP_EN3,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 2. "TIM_I_EXT_CAP_EN2,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 1. "TIM_I_EXT_CAP_EN1,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 0. "TIM_I_EXT_CAP_EN0,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" line.long 0x14 "CCM0_TOM_OUT," bitfld.long 0x14 31. "TOM_OUT_N15,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 30. "TOM_OUT_N14,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 29. "TOM_OUT_N13,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 28. "TOM_OUT_N12,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 27. "TOM_OUT_N11,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 26. "TOM_OUT_N10,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 25. "TOM_OUT_N9,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 24. "TOM_OUT_N8,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 23. "TOM_OUT_N7,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 22. "TOM_OUT_N6,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 21. "TOM_OUT_N5,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 20. "TOM_OUT_N4,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 19. "TOM_OUT_N3,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 18. "TOM_OUT_N2,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 17. "TOM_OUT_N1,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 16. "TOM_OUT_N0,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 15. "TOM_OUT15,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 14. "TOM_OUT14,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 13. "TOM_OUT13,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 12. "TOM_OUT12,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 11. "TOM_OUT11,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 10. "TOM_OUT10,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 9. "TOM_OUT9,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 8. "TOM_OUT8,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 7. "TOM_OUT7,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 6. "TOM_OUT6,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 5. "TOM_OUT5,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 4. "TOM_OUT4,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 3. "TOM_OUT3,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 2. "TOM_OUT2,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 1. "TOM_OUT1,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 0. "TOM_OUT0,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" line.long 0x18 "CCM0_ATOM_OUT," bitfld.long 0x18 31. "ATOM_IP1_OUT_N7,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 30. "ATOM_IP1_OUT_N6,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 29. "ATOM_IP1_OUT_N5,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 28. "ATOM_IP1_OUT_N4,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 27. "ATOM_IP1_OUT_N3,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 26. "ATOM_IP1_OUT_N2,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 25. "ATOM_IP1_OUT_N1,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 24. "ATOM_IP1_OUT_N0,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 23. "ATOM_IP1_OUT7,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 22. "ATOM_IP1_OUT6,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 21. "ATOM_IP1_OUT5,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 20. "ATOM_IP1_OUT4,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 19. "ATOM_IP1_OUT3,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 18. "ATOM_IP1_OUT2,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 17. "ATOM_IP1_OUT1,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 16. "ATOM_IP1_OUT0,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 15. "ATOM_I_OUT_N7,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 14. "ATOM_I_OUT_N6,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 13. "ATOM_I_OUT_N5,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 12. "ATOM_I_OUT_N4,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 11. "ATOM_I_OUT_N3,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 10. "ATOM_I_OUT_N2,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 9. "ATOM_I_OUT_N1,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 8. "ATOM_I_OUT_N0,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 7. "ATOM_I_OUT7,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 6. "ATOM_I_OUT6,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 5. "ATOM_I_OUT5,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 4. "ATOM_I_OUT4,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 3. "ATOM_I_OUT3,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 2. "ATOM_I_OUT2,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 1. "ATOM_I_OUT1,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 0. "ATOM_I_OUT0,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" line.long 0x1C "CCM0_CMU_CLK_CFG," bitfld.long 0x1C 28.--29. "CLK7_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 24.--25. "CLK6_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 20.--21. "CLK5_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 16.--17. "CLK4_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 12.--13. "CLK3_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 8.--9. "CLK2_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 4.--5. "CLK1_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "CLK0_SRC,Clock y source signal selector" "0,1,2,3" line.long 0x20 "CCM0_CMU_FXCLK_CFG," hexmask.long.byte 0x20 0.--3. 1. "FXCLK0_SRC,Fixed clock 0 source signal selector" line.long 0x24 "CCM0_CFG," bitfld.long 0x24 31. "TBU_DIR2,DIR1 input signal of module TBU timebase [z]." "0,1" newline bitfld.long 0x24 30. "TBU_DIR1,DIR1 input signal of module TBU timebase [z]." "0,1" newline bitfld.long 0x24 16.--17. "CLS_CLK_DIV,Cluster Clock Divider." "0,1,2,3" newline bitfld.long 0x24 8. "EN_TIO_DTM,Enable TIO and connected DTM" "0,1" newline bitfld.long 0x24 7. "EN_CMP_MON,Enable CMP and MON" "0,1" newline bitfld.long 0x24 6. "EN_PSM,Enable PSM" "0,1" newline bitfld.long 0x24 5. "EN_BRC,Enable BRC" "0,1" newline bitfld.long 0x24 4. "EN_DPLL_MAP,Enable DPLL and MAP" "0,1" newline bitfld.long 0x24 3. "EN_MCS,Enable MCS" "0,1" newline bitfld.long 0x24 2. "EN_ATOM_ADTM,Enable ATOM and ADTM" "0,1" newline bitfld.long 0x24 1. "EN_TOM_SPE_TDTM,Enable TOM SPE and TDTM" "0,1" newline bitfld.long 0x24 0. "EN_TIM,Enable TIM" "0,1" line.long 0x28 "CCM0_PROT," bitfld.long 0x28 0. "CLS_PROT,Cluster Protection" "0,1" group.long 0x4400++0x7F line.long 0x0 "CDTM0_DTM0_CTRL," bitfld.long 0x0 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x0 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x0 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x0 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x0 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x4 "CDTM0_DTM0_CH_CTRL1," bitfld.long 0x4 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x4 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x4 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x4 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x4 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x4 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x4 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x4 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x4 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x4 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x4 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x4 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x4 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x4 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x4 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x4 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x4 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x8 "CDTM0_DTM0_CH_CTRL2," bitfld.long 0x8 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x8 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x8 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x8 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x8 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x8 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x8 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x8 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x8 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x8 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x8 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x8 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x8 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x8 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x8 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x8 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x8 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x8 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x8 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x8 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x8 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x8 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x8 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x8 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x8 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x8 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x8 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x8 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x8 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x8 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x8 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x8 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0xC "CDTM0_DTM0_CH_CTRL2_SR," bitfld.long 0xC 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x10 "CDTM0_DTM0_PS_CTRL," bitfld.long 0x10 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x10 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x10 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x10 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x10 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x14 "CDTM0_DTM0_CH0_DTV," bitfld.long 0x14 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x14 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x14 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x18 "CDTM0_DTM0_CH1_DTV," bitfld.long 0x18 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x18 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x18 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x1C "CDTM0_DTM0_CH2_DTV," bitfld.long 0x1C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x1C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x1C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x20 "CDTM0_DTM0_CH3_DTV," bitfld.long 0x20 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x20 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x20 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x24 "CDTM0_DTM0_CH_SR," bitfld.long 0x24 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x24 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x24 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x24 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x24 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x24 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x24 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x24 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x28 "CDTM0_DTM0_CH_CTRL3," bitfld.long 0x28 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x28 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x28 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x28 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x28 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x28 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x28 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x28 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x2C "CDTM0_DTM0_CTRL2," bitfld.long 0x2C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x2C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x2C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x2C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x2C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x2C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x2C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x2C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x2C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x2C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x2C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x2C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x2C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x2C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x2C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x2C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x2C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x2C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x2C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x2C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x30 "CDTM0_DTM0_CH0_DTV_SR," bitfld.long 0x30 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x30 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x30 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x30 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x30 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x30 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x34 "CDTM0_DTM0_CH1_DTV_SR," bitfld.long 0x34 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x34 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x34 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x34 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x34 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x34 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x38 "CDTM0_DTM0_CH2_DTV_SR," bitfld.long 0x38 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x38 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x38 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x38 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x38 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x38 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x3C "CDTM0_DTM0_CH3_DTV_SR," bitfld.long 0x3C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x3C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x3C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x3C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x3C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x3C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x40 "CDTM0_DTM1_CTRL," bitfld.long 0x40 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x40 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x40 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x40 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x40 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x44 "CDTM0_DTM1_CH_CTRL1," bitfld.long 0x44 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x44 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x44 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x44 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x44 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x44 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x44 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x44 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x44 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x44 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x44 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x44 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x44 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x44 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x44 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x44 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x44 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x48 "CDTM0_DTM1_CH_CTRL2," bitfld.long 0x48 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x48 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x48 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x48 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x48 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x48 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x48 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x48 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x48 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x48 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x48 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x48 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x48 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x48 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x48 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x48 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x48 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x48 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x48 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x48 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x48 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x48 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x48 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x48 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x48 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x48 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x48 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x48 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x48 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x48 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x48 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x48 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0x4C "CDTM0_DTM1_CH_CTRL2_SR," bitfld.long 0x4C 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x50 "CDTM0_DTM1_PS_CTRL," bitfld.long 0x50 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x50 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x50 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x50 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x50 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x54 "CDTM0_DTM1_CH0_DTV," bitfld.long 0x54 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x54 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x54 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x58 "CDTM0_DTM1_CH1_DTV," bitfld.long 0x58 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x58 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x58 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x5C "CDTM0_DTM1_CH2_DTV," bitfld.long 0x5C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x5C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x5C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x60 "CDTM0_DTM1_CH3_DTV," bitfld.long 0x60 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x60 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x60 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x64 "CDTM0_DTM1_CH_SR," bitfld.long 0x64 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x64 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x64 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x64 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x64 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x64 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x64 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x64 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x68 "CDTM0_DTM1_CH_CTRL3," bitfld.long 0x68 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x68 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x68 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x68 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x68 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x68 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x68 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x68 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x6C "CDTM0_DTM1_CTRL2," bitfld.long 0x6C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x6C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x6C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x6C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x6C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x6C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x6C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x6C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x6C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x6C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x6C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x6C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x6C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x6C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x6C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x6C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x6C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x6C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x6C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x6C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x70 "CDTM0_DTM1_CH0_DTV_SR," bitfld.long 0x70 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x70 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x70 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x70 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x70 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x70 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x74 "CDTM0_DTM1_CH1_DTV_SR," bitfld.long 0x74 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x74 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x74 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x74 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x74 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x74 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x78 "CDTM0_DTM1_CH2_DTV_SR," bitfld.long 0x78 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x78 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x78 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x78 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x78 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x78 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x7C "CDTM0_DTM1_CH3_DTV_SR," bitfld.long 0x7C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x7C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x7C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x7C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x7C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x7C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" group.long 0x4500++0x7F line.long 0x0 "CDTM0_DTM4_CTRL," bitfld.long 0x0 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x0 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x0 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x0 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x0 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x4 "CDTM0_DTM4_CH_CTRL1," bitfld.long 0x4 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x4 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x4 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x4 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x4 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x4 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x4 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x4 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x4 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x4 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x4 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x4 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x4 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x4 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x4 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x4 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x4 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x8 "CDTM0_DTM4_CH_CTRL2," bitfld.long 0x8 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x8 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x8 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x8 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x8 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x8 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x8 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x8 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x8 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x8 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x8 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x8 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x8 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x8 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x8 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x8 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x8 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x8 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x8 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x8 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x8 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x8 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x8 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x8 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x8 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x8 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x8 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x8 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x8 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x8 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x8 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x8 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0xC "CDTM0_DTM4_CH_CTRL2_SR," bitfld.long 0xC 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x10 "CDTM0_DTM4_PS_CTRL," bitfld.long 0x10 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x10 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x10 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x10 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x10 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x14 "CDTM0_DTM4_CH0_DTV," bitfld.long 0x14 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x14 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x14 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x18 "CDTM0_DTM4_CH1_DTV," bitfld.long 0x18 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x18 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x18 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x1C "CDTM0_DTM4_CH2_DTV," bitfld.long 0x1C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x1C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x1C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x20 "CDTM0_DTM4_CH3_DTV," bitfld.long 0x20 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x20 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x20 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x24 "CDTM0_DTM4_CH_SR," bitfld.long 0x24 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x24 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x24 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x24 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x24 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x24 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x24 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x24 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x28 "CDTM0_DTM4_CH_CTRL3," bitfld.long 0x28 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x28 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x28 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x28 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x28 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x28 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x28 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x28 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x2C "CDTM0_DTM4_CTRL2," bitfld.long 0x2C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x2C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x2C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x2C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x2C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x2C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x2C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x2C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x2C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x2C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x2C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x2C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x2C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x2C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x2C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x2C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x2C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x2C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x2C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x2C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x30 "CDTM0_DTM4_CH0_DTV_SR," bitfld.long 0x30 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x30 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x30 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x30 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x30 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x30 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x34 "CDTM0_DTM4_CH1_DTV_SR," bitfld.long 0x34 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x34 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x34 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x34 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x34 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x34 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x38 "CDTM0_DTM4_CH2_DTV_SR," bitfld.long 0x38 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x38 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x38 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x38 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x38 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x38 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x3C "CDTM0_DTM4_CH3_DTV_SR," bitfld.long 0x3C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x3C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x3C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x3C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x3C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x3C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x40 "CDTM0_DTM5_CTRL," bitfld.long 0x40 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x40 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x40 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x40 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x40 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x44 "CDTM0_DTM5_CH_CTRL1," bitfld.long 0x44 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x44 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x44 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x44 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x44 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x44 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x44 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x44 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x44 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x44 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x44 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x44 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x44 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x44 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x44 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x44 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x44 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x48 "CDTM0_DTM5_CH_CTRL2," bitfld.long 0x48 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x48 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x48 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x48 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x48 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x48 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x48 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x48 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x48 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x48 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x48 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x48 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x48 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x48 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x48 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x48 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x48 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x48 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x48 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x48 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x48 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x48 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x48 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x48 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x48 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x48 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x48 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x48 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x48 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x48 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x48 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x48 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0x4C "CDTM0_DTM5_CH_CTRL2_SR," bitfld.long 0x4C 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x50 "CDTM0_DTM5_PS_CTRL," bitfld.long 0x50 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x50 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x50 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x50 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x50 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x54 "CDTM0_DTM5_CH0_DTV," bitfld.long 0x54 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x54 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x54 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x58 "CDTM0_DTM5_CH1_DTV," bitfld.long 0x58 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x58 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x58 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x5C "CDTM0_DTM5_CH2_DTV," bitfld.long 0x5C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x5C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x5C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x60 "CDTM0_DTM5_CH3_DTV," bitfld.long 0x60 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x60 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x60 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x64 "CDTM0_DTM5_CH_SR," bitfld.long 0x64 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x64 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x64 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x64 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x64 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x64 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x64 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x64 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x68 "CDTM0_DTM5_CH_CTRL3," bitfld.long 0x68 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x68 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x68 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x68 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x68 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x68 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x68 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x68 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x6C "CDTM0_DTM5_CTRL2," bitfld.long 0x6C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x6C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x6C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x6C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x6C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x6C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x6C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x6C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x6C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x6C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x6C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x6C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x6C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x6C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x6C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x6C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x6C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x6C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x6C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x6C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x70 "CDTM0_DTM5_CH0_DTV_SR," bitfld.long 0x70 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x70 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x70 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x70 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x70 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x70 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x74 "CDTM0_DTM5_CH1_DTV_SR," bitfld.long 0x74 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x74 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x74 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x74 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x74 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x74 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x78 "CDTM0_DTM5_CH2_DTV_SR," bitfld.long 0x78 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x78 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x78 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x78 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x78 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x78 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x7C "CDTM0_DTM5_CH3_DTV_SR," bitfld.long 0x7C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x7C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x7C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x7C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x7C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x7C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" group.long 0x4800++0x47 line.long 0x0 "F2A0_CH0_ARU_RD_FIFO," hexmask.long.word 0x0 0.--8. 1. "ADDR,ARU Read address" line.long 0x4 "F2A0_CH1_ARU_RD_FIFO," hexmask.long.word 0x4 0.--8. 1. "ADDR,ARU Read address" line.long 0x8 "F2A0_CH2_ARU_RD_FIFO," hexmask.long.word 0x8 0.--8. 1. "ADDR,ARU Read address" line.long 0xC "F2A0_CH3_ARU_RD_FIFO," hexmask.long.word 0xC 0.--8. 1. "ADDR,ARU Read address" line.long 0x10 "F2A0_CH4_ARU_RD_FIFO," hexmask.long.word 0x10 0.--8. 1. "ADDR,ARU Read address" line.long 0x14 "F2A0_CH5_ARU_RD_FIFO," hexmask.long.word 0x14 0.--8. 1. "ADDR,ARU Read address" line.long 0x18 "F2A0_CH6_ARU_RD_FIFO," hexmask.long.word 0x18 0.--8. 1. "ADDR,ARU Read address" line.long 0x1C "F2A0_CH7_ARU_RD_FIFO," hexmask.long.word 0x1C 0.--8. 1. "ADDR,ARU Read address" line.long 0x20 "F2A0_CH0_STR_CFG," bitfld.long 0x20 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x20 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x24 "F2A0_CH1_STR_CFG," bitfld.long 0x24 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x24 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x28 "F2A0_CH2_STR_CFG," bitfld.long 0x28 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x28 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x2C "F2A0_CH3_STR_CFG," bitfld.long 0x2C 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x2C 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x30 "F2A0_CH4_STR_CFG," bitfld.long 0x30 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x30 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x34 "F2A0_CH5_STR_CFG," bitfld.long 0x34 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x34 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x38 "F2A0_CH6_STR_CFG," bitfld.long 0x38 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x38 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x3C "F2A0_CH7_STR_CFG," bitfld.long 0x3C 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x3C 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x40 "F2A0_ENABLE," bitfld.long 0x40 14.--15. "STR7_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 12.--13. "STR6_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 10.--11. "STR5_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 8.--9. "STR4_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 6.--7. "STR3_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 4.--5. "STR2_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 2.--3. "STR1_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 0.--1. "STR0_EN,Enable/disable stream y" "0,1,2,3" line.long 0x44 "F2A0_CTRL," bitfld.long 0x44 6.--7. "STR7_CONF,Reconfiguration of stream y to FIFO channel y-4" "0,1,2,3" newline bitfld.long 0x44 4.--5. "STR6_CONF,Reconfiguration of stream y to FIFO channel y-4" "0,1,2,3" newline bitfld.long 0x44 2.--3. "STR5_CONF,Reconfiguration of stream y to FIFO channel y-4" "0,1,2,3" newline bitfld.long 0x44 0.--1. "STR4_CONF,Reconfiguration of stream y to FIFO channel y-4" "0,1,2,3" group.long 0x4880++0x3 line.long 0x0 "AFD0_CH0_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x4890++0x3 line.long 0x0 "AFD0_CH1_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48A0++0x3 line.long 0x0 "AFD0_CH2_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48B0++0x3 line.long 0x0 "AFD0_CH3_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48C0++0x3 line.long 0x0 "AFD0_CH4_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48D0++0x3 line.long 0x0 "AFD0_CH5_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48E0++0x3 line.long 0x0 "AFD0_CH6_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48F0++0x3 line.long 0x0 "AFD0_CH7_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x4A00++0x37 line.long 0x0 "FIFO0_CH0_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO0_CH0_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO0_CH0_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO0_CH0_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO0_CH0_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO0_CH0_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO0_CH0_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO0_CH0_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO0_CH0_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO0_CH0_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO0_CH0_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO0_CH0_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO0_CH0_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO0_CH0_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4A40++0x37 line.long 0x0 "FIFO0_CH1_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO0_CH1_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO0_CH1_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO0_CH1_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO0_CH1_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO0_CH1_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO0_CH1_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO0_CH1_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO0_CH1_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO0_CH1_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO0_CH1_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO0_CH1_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO0_CH1_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO0_CH1_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4A80++0x37 line.long 0x0 "FIFO0_CH2_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO0_CH2_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO0_CH2_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO0_CH2_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO0_CH2_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO0_CH2_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO0_CH2_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO0_CH2_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO0_CH2_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO0_CH2_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO0_CH2_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO0_CH2_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO0_CH2_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO0_CH2_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4AC0++0x37 line.long 0x0 "FIFO0_CH3_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO0_CH3_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO0_CH3_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO0_CH3_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO0_CH3_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO0_CH3_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO0_CH3_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO0_CH3_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO0_CH3_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO0_CH3_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO0_CH3_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO0_CH3_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO0_CH3_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO0_CH3_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4B00++0x37 line.long 0x0 "FIFO0_CH4_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO0_CH4_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO0_CH4_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO0_CH4_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO0_CH4_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO0_CH4_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO0_CH4_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO0_CH4_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO0_CH4_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO0_CH4_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO0_CH4_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO0_CH4_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO0_CH4_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO0_CH4_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4B40++0x37 line.long 0x0 "FIFO0_CH5_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO0_CH5_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO0_CH5_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO0_CH5_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO0_CH5_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO0_CH5_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO0_CH5_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO0_CH5_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO0_CH5_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO0_CH5_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO0_CH5_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO0_CH5_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO0_CH5_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO0_CH5_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4B80++0x37 line.long 0x0 "FIFO0_CH6_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO0_CH6_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO0_CH6_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO0_CH6_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO0_CH6_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO0_CH6_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO0_CH6_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO0_CH6_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO0_CH6_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO0_CH6_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO0_CH6_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO0_CH6_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO0_CH6_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO0_CH6_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4BC0++0x37 line.long 0x0 "FIFO0_CH7_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO0_CH7_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO0_CH7_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO0_CH7_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO0_CH7_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO0_CH7_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO0_CH7_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO0_CH7_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO0_CH7_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO0_CH7_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO0_CH7_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO0_CH7_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO0_CH7_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO0_CH7_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4C00++0x4F line.long 0x0 "SPE0_CTRL_STAT," hexmask.long.byte 0x0 24.--31. 1. "FSOL,Fast Shutoff Level for TOM[i] channel 0 to 7" newline bitfld.long 0x0 23. "ETRIG_SEL,Extended trigger selection of signal SPE[i]_CTRL_STAT.TRIG_SEL" "0,1" newline bitfld.long 0x0 20.--22. "NIP,New input pattern that was detected." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "PDIR,Previous rotation direction." "0,1" newline bitfld.long 0x0 16.--18. "PIP,Previous input pattern that was detected by a regular input pattern change." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "ADIR,Rotation direction. Will be reflected in the signal SPE(i)_DIR." "0,1" newline bitfld.long 0x0 12.--14. "AIP,Input pattern that was detected by a regular input pattern change." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "SPE_PAT_PTR,Pattern selector for TOM output signals." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "FSOM,Fast Shutoff Mode" "0,1" newline bitfld.long 0x0 6. "TIM_SEL,Select TIM input signal" "0,1" newline bitfld.long 0x0 4.--5. "TRIG_SEL,Select trigger input signal." "0,1,2,3" newline bitfld.long 0x0 3. "SIE2,SPE Input enable for TIM_CHx(48)." "0,1" newline bitfld.long 0x0 2. "SIE1,SPE Input enable for TIM_CHx(48)." "0,1" newline bitfld.long 0x0 1. "SIE0,SPE Input enable for TIM_CHx(48)." "0,1" newline bitfld.long 0x0 0. "EN,SPE Submodule enable." "0,1" line.long 0x4 "SPE0_PAT," bitfld.long 0x4 29.--31. "IP7_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "IP7_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 25.--27. "IP6_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 24. "IP6_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 21.--23. "IP5_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "IP5_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 17.--19. "IP4_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "IP4_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 13.--15. "IP3_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12. "IP3_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 9.--11. "IP2_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "IP2_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 5.--7. "IP1_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4. "IP1_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 1.--3. "IP0_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "IP0_VAL,Input pattern t is a valid pattern." "0,1" line.long 0x8 "SPE0_OUT_PAT0," bitfld.long 0x8 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0xC "SPE0_OUT_PAT1," bitfld.long 0xC 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x10 "SPE0_OUT_PAT2," bitfld.long 0x10 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x14 "SPE0_OUT_PAT3," bitfld.long 0x14 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x18 "SPE0_OUT_PAT4," bitfld.long 0x18 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x1C "SPE0_OUT_PAT5," bitfld.long 0x1C 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x20 "SPE0_OUT_PAT6," bitfld.long 0x20 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x24 "SPE0_OUT_PAT7," bitfld.long 0x24 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x28 "SPE0_OUT_CTRL," bitfld.long 0x28 14.--15. "SPE_OUT_CTRL7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 12.--13. "SPE_OUT_CTRL6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 10.--11. "SPE_OUT_CTRL5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 8.--9. "SPE_OUT_CTRL4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 6.--7. "SPE_OUT_CTRL3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 4.--5. "SPE_OUT_CTRL2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 2.--3. "SPE_OUT_CTRL1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 0.--1. "SPE_OUT_CTRL0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x2C "SPE0_IRQ_NOTIFY," bitfld.long 0x2C 4. "SPE_RCMP,SPE revolution counter match event." "0,1" newline bitfld.long 0x2C 3. "SPE_BIS,Bouncing input signal detected." "0,1" newline bitfld.long 0x2C 2. "SPE_PERR,Wrong or invalid pattern detected at input." "0,1" newline bitfld.long 0x2C 1. "SPE_DCHG,SPE_DIR bit changed on behalf of new input pattern." "0,1" newline bitfld.long 0x2C 0. "SPE_NIPD,New input pattern interrupt occurred." "0,1" line.long 0x30 "SPE0_IRQ_EN," bitfld.long 0x30 4. "SPE_RCMP_IRQ_EN,SPE_RCMP_IRQ interrupt enable." "0,1" newline bitfld.long 0x30 3. "SPE_BIS_IRQ_EN,SPE_BIS_IRQ interrupt enable." "0,1" newline bitfld.long 0x30 2. "SPE_PERR_IRQ_EN,SPE_PERR_IRQ interrupt enable." "0,1" newline bitfld.long 0x30 1. "SPE_DCHG_IRQ_EN,SPE_DCHG_IRQ interrupt enable." "0,1" newline bitfld.long 0x30 0. "SPE_NIPD_IRQ_EN,SPE_NIPD_IRQ interrupt enable." "0,1" line.long 0x34 "SPE0_IRQ_FORCINT," bitfld.long 0x34 4. "TRG_SPE_RCMP,Force interrupt of SPE_RCMP." "0,1" newline bitfld.long 0x34 3. "TRG_SPE_BIS,Force interrupt of SPE_BIS." "0,1" newline bitfld.long 0x34 2. "TRG_SPE_PERR,Force interrupt of SPE_PERR." "0,1" newline bitfld.long 0x34 1. "TRG_SPE_DCHG,Force interrupt of SPE_DCHG." "0,1" newline bitfld.long 0x34 0. "TRG_SPE_NIPD,Force interrupt of SPE_NIPD." "0,1" line.long 0x38 "SPE0_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x3C "SPE0_EIRQ_EN," bitfld.long 0x3C 4. "SPE_RCMP_EIRQ_EN,SPE_RCMP_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x3C 3. "SPE_BIS_EIRQ_EN,SPE_BIS_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x3C 2. "SPE_PERR_EIRQ_EN,SPE_PERR_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x3C 1. "SPE_DCHG_EIRQ_EN,SPE_DCHG_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x3C 0. "SPE_NIPD_EIRQ_EN,SPE_NIPD_EIRQ interrupt enable." "0,1" line.long 0x40 "SPE0_REV_CNT," hexmask.long.tbyte 0x40 0.--23. 1. "REV_CNT,Input signal revolution counter" line.long 0x44 "SPE0_REV_CMP," hexmask.long.tbyte 0x44 0.--23. 1. "REV_CMP,Input signal revolution counter compare value" line.long 0x48 "SPE0_CTRL_STAT2," bitfld.long 0x48 8.--10. "SPE_PAT_PTR_BWD,Pattern selector for TOM output signals in case of SPE[i]_CMD.SPE_CTRL_CMD = 0b01 (e.g. backward direction)." "0,1,2,3,4,5,6,7" line.long 0x4C "SPE0_CMD," bitfld.long 0x4C 16. "SPE_UPD_TRIG,SPE updater trigger" "0,1" newline bitfld.long 0x4C 0.--1. "SPE_CTRL_CMD,SPE control command" "0,1,2,3" group.long 0x5000++0xB line.long 0x0 "AXIM0_FREE," bitfld.long 0x0 3. "FREE3,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 2. "FREE2,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 1. "FREE1,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 0. "FREE0,This bit represents the allocation status of the slot [t]" "0,1" line.long 0x4 "AXIM0_REQUEST," hexmask.long.byte 0x4 24.--31. 1. "REQID,This bit field shows the new allocated slot as binary encoded index. If no slot could be allocated this bit field is read as all 1 (0xff)." newline bitfld.long 0x4 3. "REQ1HOT3,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 2. "REQ1HOT2,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 1. "REQ1HOT1,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 0. "REQ1HOT0,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" line.long 0x8 "AXIM0_RELEASE," bitfld.long 0x8 3. "RELREQ3,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 2. "RELREQ2,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 1. "RELREQ1,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 0. "RELREQ0,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" group.long 0x5020++0x3 line.long 0x0 "AXIM0_SLOT0_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5028++0x3 line.long 0x0 "AXIM0_SLOT0_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5030++0xB line.long 0x0 "AXIM0_SLOT0_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM0_SLOT0_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM0_SLOT0_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5040++0x3 line.long 0x0 "AXIM0_SLOT1_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5048++0x3 line.long 0x0 "AXIM0_SLOT1_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5050++0xB line.long 0x0 "AXIM0_SLOT1_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM0_SLOT1_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM0_SLOT1_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5060++0x3 line.long 0x0 "AXIM0_SLOT2_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5068++0x3 line.long 0x0 "AXIM0_SLOT2_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5070++0xB line.long 0x0 "AXIM0_SLOT2_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM0_SLOT2_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM0_SLOT2_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5080++0x3 line.long 0x0 "AXIM0_SLOT3_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5088++0x3 line.long 0x0 "AXIM0_SLOT3_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5090++0xB line.long 0x0 "AXIM0_SLOT3_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM0_SLOT3_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM0_SLOT3_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" repeat 1024. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6000)++0x3 line.long 0x0 "FIFO0_MEMORY[$1]," hexmask.long 0x0 0.--28. 1. "DATA,FIFO memory location." repeat.end group.long 0x8000++0x53 line.long 0x0 "DPLL_CTRL_0," bitfld.long 0x0 31. "RMO,Reference mode." "0,1" newline bitfld.long 0x0 30. "TEN,TRIGGER enable." "0,1" newline bitfld.long 0x0 29. "SEN,STATE enable." "0,1" newline bitfld.long 0x0 28. "IDT,Input delay TRIGGER." "0,1" newline bitfld.long 0x0 27. "IDS,Input delay STATE." "0,1" newline bitfld.long 0x0 26. "AMT,Adapt mode TRIGGER." "0,1" newline bitfld.long 0x0 25. "AMS,Adapt mode STATE." "0,1" newline hexmask.long.word 0x0 16.--24. 1. "TNU,TRIGGER number." newline hexmask.long.byte 0x0 11.--15. 1. "SNU,STATE number." newline bitfld.long 0x0 10. "IFP,Input filter position." "0,1" newline hexmask.long.word 0x0 0.--9. 1. "MLT,Multiplier for TRIGGER." line.long 0x4 "DPLL_CTRL_1," bitfld.long 0x4 30.--31. "TSL,TRIGGER slope select; Definition of active slope for signal TRIGGER each active slope is an event defined by DPLL_CTRL_0.TNU. Set by DPLL_CTRL_1.DEN=0 only." "0,1,2,3" newline bitfld.long 0x4 28.--29. "SSL,STATE slope select; Definition of active slope for signal STATE each active slope is an event defined by DPLL_CTRL_0.SNU. Set by DPLL_CTRL_1.DEN=0 only." "0,1,2,3" newline bitfld.long 0x4 27. "SMC,Synchronous Motor Control" "0,1" newline bitfld.long 0x4 26. "TS0_HRT,Time stamp high resolution TRIGGER" "0,1" newline bitfld.long 0x4 25. "TS0_HRS,Time stamp high resolution STATE" "0,1" newline bitfld.long 0x4 24. "SYSF,DPLL_CTRL_EXT.SYN_NS for FULL_SCALE" "0,1" newline bitfld.long 0x4 23. "SWR,Software reset" "0,1" newline bitfld.long 0x4 22. "LCD,Locking condition definition" "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "SYN_NT,Synchronization number of TRIGGER; summarized number of virtual increments in HALF_SCALE." newline hexmask.long.byte 0x4 11.--15. 1. "SYN_NS,Synchronization number of STATE; summarized number of virtual increments in HALF_SCALE." newline bitfld.long 0x4 10. "PCM2,Pulse Correction Mode for SUB_INC2 generation." "0,1" newline bitfld.long 0x4 9. "DLM2,Direct Load Mode for SUB_INC2 generation." "0,1" newline bitfld.long 0x4 8. "SGE2,SUB_INC2 generator enable." "0,1" newline bitfld.long 0x4 7. "PCM1,Pulse Correction Mode for SUB_INC1 generation." "0,1" newline bitfld.long 0x4 6. "DLM1,Direct Load Mode for SUB_INC1 generation." "0,1" newline bitfld.long 0x4 5. "SGE1,SUB_INC1 generator enable." "0,1" newline bitfld.long 0x4 4. "PIT,Plausibility value PVT to next active TRIGGER is time related." "0,1" newline bitfld.long 0x4 3. "COA,Correction strategy in automatic end mode (DPLL_CTRL_1.DMO=0)." "0,1" newline bitfld.long 0x4 2. "IDDS,Input direction detection strategy in the case of DPLL_CTRL_1.SMC=0." "0,1" newline bitfld.long 0x4 1. "DEN,DPLL enable." "0,1" newline bitfld.long 0x4 0. "DMO,DPLL mode select." "0,1" line.long 0x8 "DPLL_CTRL_2," bitfld.long 0x8 23. "WAD7,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x8 22. "WAD6,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x8 21. "WAD5,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x8 20. "WAD4,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x8 19. "WAD3,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x8 18. "WAD2,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x8 17. "WAD1,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x8 16. "WAD0,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x8 15. "AEN7,ACTION [n] enable." "0,1" newline bitfld.long 0x8 14. "AEN6,ACTION [n] enable." "0,1" newline bitfld.long 0x8 13. "AEN5,ACTION [n] enable." "0,1" newline bitfld.long 0x8 12. "AEN4,ACTION [n] enable." "0,1" newline bitfld.long 0x8 11. "AEN3,ACTION [n] enable." "0,1" newline bitfld.long 0x8 10. "AEN2,ACTION [n] enable." "0,1" newline bitfld.long 0x8 9. "AEN1,ACTION [n] enable." "0,1" newline bitfld.long 0x8 8. "AEN0,ACTION [n] enable." "0,1" line.long 0xC "DPLL_CTRL_3," bitfld.long 0xC 23. "WAD15,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0xC 22. "WAD14,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0xC 21. "WAD13,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0xC 20. "WAD12,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0xC 19. "WAD11,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0xC 18. "WAD10,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0xC 17. "WAD9,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0xC 16. "WAD8,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0xC 15. "AEN15,ACTION [n] enable." "0,1" newline bitfld.long 0xC 14. "AEN14,ACTION [n] enable." "0,1" newline bitfld.long 0xC 13. "AEN13,ACTION [n] enable." "0,1" newline bitfld.long 0xC 12. "AEN12,ACTION [n] enable." "0,1" newline bitfld.long 0xC 11. "AEN11,ACTION [n] enable." "0,1" newline bitfld.long 0xC 10. "AEN10,ACTION [n] enable." "0,1" newline bitfld.long 0xC 9. "AEN9,ACTION [n] enable." "0,1" newline bitfld.long 0xC 8. "AEN8,ACTION [n] enable." "0,1" line.long 0x10 "DPLL_CTRL_4," bitfld.long 0x10 23. "WAD23,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x10 22. "WAD22,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x10 21. "WAD21,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x10 20. "WAD20,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x10 19. "WAD19,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x10 18. "WAD18,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x10 17. "WAD17,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x10 16. "WAD16,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x10 15. "AEN23,ACTION [n] enable." "0,1" newline bitfld.long 0x10 14. "AEN22,ACTION [n] enable." "0,1" newline bitfld.long 0x10 13. "AEN21,ACTION [n] enable." "0,1" newline bitfld.long 0x10 12. "AEN20,ACTION [n] enable." "0,1" newline bitfld.long 0x10 11. "AEN19,ACTION [n] enable." "0,1" newline bitfld.long 0x10 10. "AEN18,ACTION [n] enable." "0,1" newline bitfld.long 0x10 9. "AEN17,ACTION [n] enable." "0,1" newline bitfld.long 0x10 8. "AEN16,ACTION [n] enable." "0,1" line.long 0x14 "DPLL_CTRL_5," bitfld.long 0x14 23. "WAD31,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x14 22. "WAD30,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x14 21. "WAD29,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x14 20. "WAD28,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x14 19. "WAD27,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x14 18. "WAD26,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x14 17. "WAD25,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x14 16. "WAD24,Write control bit of ACTION [m]." "0,1" newline bitfld.long 0x14 15. "AEN31,ACTION [n] enable." "0,1" newline bitfld.long 0x14 14. "AEN30,ACTION [n] enable." "0,1" newline bitfld.long 0x14 13. "AEN29,ACTION [n] enable." "0,1" newline bitfld.long 0x14 12. "AEN28,ACTION [n] enable." "0,1" newline bitfld.long 0x14 11. "AEN27,ACTION [n] enable." "0,1" newline bitfld.long 0x14 10. "AEN26,ACTION [n] enable." "0,1" newline bitfld.long 0x14 9. "AEN25,ACTION [n] enable." "0,1" newline bitfld.long 0x14 8. "AEN24,ACTION [n] enable." "0,1" line.long 0x18 "DPLL_ACT_STA," bitfld.long 0x18 31. "ACT_N31,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 30. "ACT_N30,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 29. "ACT_N29,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 28. "ACT_N28,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 27. "ACT_N27,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 26. "ACT_N26,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 25. "ACT_N25,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 24. "ACT_N24,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 23. "ACT_N23,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 22. "ACT_N22,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 21. "ACT_N21,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 20. "ACT_N20,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 19. "ACT_N19,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 18. "ACT_N18,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 17. "ACT_N17,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 16. "ACT_N16,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 15. "ACT_N15,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 14. "ACT_N14,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 13. "ACT_N13,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 12. "ACT_N12,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 11. "ACT_N11,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 10. "ACT_N10,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 9. "ACT_N9,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 8. "ACT_N8,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 7. "ACT_N7,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 6. "ACT_N6,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 5. "ACT_N5,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 4. "ACT_N4,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 3. "ACT_N3,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 2. "ACT_N2,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 1. "ACT_N1,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" newline bitfld.long 0x18 0. "ACT_N0,New output data values concerning to action n provided. DPLL_ACT_STA.ACT_N[n] (n=0...NOAC-1):" "0,1" line.long 0x1C "DPLL_OSW," bitfld.long 0x1C 8.--9. "OSS,Offset size of RAM region 2" "0,1,2,3" newline bitfld.long 0x1C 1. "SWON_T,Switch of new TRIGGER; Switch bit for LSB address of TRIGGER." "0,1" newline bitfld.long 0x1C 0. "SWON_S,Switch of new STATE; Switch bit for LSB address of STATE." "0,1" line.long 0x20 "DPLL_AOSV_2," hexmask.long.byte 0x20 24.--31. 1. "AOSV_2D,Address offset value of the RAM 2D region." newline hexmask.long.byte 0x20 16.--23. 1. "AOSV_2C,Address offset value of the RAM 2C region." newline hexmask.long.byte 0x20 8.--15. 1. "AOSV_2B,Address offset value of the RAM 2B region." newline hexmask.long.byte 0x20 0.--7. 1. "AOSV_2A,Address offset value of the RAM 2A region." line.long 0x24 "DPLL_APT," hexmask.long.word 0x24 14.--23. 1. "APT_2B,Address pointer TRIGGER for RAM region 2b; Actual RAM pointer address value for TSF_T[p]" newline bitfld.long 0x24 13. "WAPT_2B,Write bit for address pointer DPLL_APT.APT_2B read as zero." "0,1" newline hexmask.long.word 0x24 2.--11. 1. "APT,Address pointer TRIGGER; Actual RAM pointer address value offset for DT_T[p] and RDT_T[p] in FULL_SCALE for 2*(TNU+1-SYN_NT) TRIGGER events." newline bitfld.long 0x24 1. "WAPT,Write bit for address pointer DPLL_APT.APT read as zero." "0,1" line.long 0x28 "DPLL_APS," hexmask.long.byte 0x28 14.--19. 1. "APS_1C2,Actual RAM pointer address value for TSF_S[p]." newline bitfld.long 0x28 13. "WAPS_1C2,Write bit for address pointer DPLL_APS.APS_1C2 read as zero." "0,1" newline hexmask.long.byte 0x28 2.--7. 1. "APS,Address pointer STATE; Actual RAM pointer address value for DT_S[p] and RDT_S[p]" newline bitfld.long 0x28 1. "WAPS,Write bit for address pointer DPLL__EXT_APS.APS read as zero." "0,1" line.long 0x2C "DPLL_APT_2C," hexmask.long.word 0x2C 2.--11. 1. "APT_2C,Address pointer TRIGGER for RAM region 2c; Actual RAM pointer address value for ADT_T[p]." line.long 0x30 "DPLL_APS_1C3," hexmask.long.byte 0x30 2.--7. 1. "APS_1C3,Address pointer STATE for RAM region 1c3; Actual RAM pointer address value for ADT_S[p]" line.long 0x34 "DPLL_NUTC," bitfld.long 0x34 31. "WVTN,Write control bit for DPLL_NUTC.VTN; read as zero." "0,1" newline bitfld.long 0x34 30. "WSYN,Write control bit for DPLL_NUTC.SYN_T and DPLL_NUTC.SYN_T_OLD; read as zero." "0,1" newline bitfld.long 0x34 29. "WNUT,Write control bit for DPLL_NUTC.NUTE and DPLL_NUTC.FST; read as zero." "0,1" newline hexmask.long.byte 0x34 19.--24. 1. "VTN,Virtual TRIGGER number; number of virtual increments in the current DPLL_NUTC.NUTE region" newline bitfld.long 0x34 16.--18. "SYN_T_OLD,Number of real and virtual events to be considered for the last increment." "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 13.--15. "SYN_T,Number of real and virtual events to be considered for the current increment." "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 10. "FST,FULL_SCALE of TRIGGER; this value is to be set when DPLL_NUTC.NUTE is set to FULL_SCALE" "0,1" newline hexmask.long.word 0x34 0.--9. 1. "NUTE,Number of recent TRIGGER events used for SUB_INC1 and action calculations modulo 2*(TNUmax+1)." line.long 0x38 "DPLL_NUSC," bitfld.long 0x38 31. "WVSN,Write control bit for DPLL_NUSC.VSN; read as zero." "0,1" newline bitfld.long 0x38 30. "WSYN,Write control bit for DPLL_NUSC.SYN_S and DPLL_NUSC.SYN_S_OLD; read as zero." "0,1" newline bitfld.long 0x38 29. "WNUS,Write control bit for DPLL_NUSC.NUSE; read as zero." "0,1" newline hexmask.long.byte 0x38 19.--24. 1. "VSN,Virtual STATE number; number of virtual state increments in the current DPLL_NUSC.NUSE region." newline hexmask.long.byte 0x38 13.--18. 1. "SYN_S_OLD,Number of real and virtual events to be considered for the last increment." newline hexmask.long.byte 0x38 7.--12. 1. "SYN_S,Number of real and virtual events to be considered for the current increment." newline bitfld.long 0x38 6. "FSS,FULL_SCALE of STATE; this value is to be set when DPLL_NUSC.NUSE is set to FULL_SCALE" "0,1" newline hexmask.long.byte 0x38 0.--5. 1. "NUSE,Number of recent STATE events used for SUB_INCx calculations modulo 2*(SNUmax+1)." line.long 0x3C "DPLL_NTI_CNT," hexmask.long.word 0x3C 0.--9. 1. "NTI_CNT,Number of TRIGGERs to interrupt; Number of active TRIGGER events to the next DPLL_CDTI interrupt." line.long 0x40 "DPLL_IRQ_NOTIFY," bitfld.long 0x40 27. "DCGI,Direction change interrupt" "0,1" newline bitfld.long 0x40 26. "SORI,STATE out of range" "0,1" newline bitfld.long 0x40 25. "TORI,TRIGGER out of range interrupt" "0,1" newline bitfld.long 0x40 24. "CDSI,Calculation of STATE duration done" "0,1" newline bitfld.long 0x40 23. "CDTI,Calculation of TRIGGER duration done only while DPLL_NTI_CNT.NTI_CNT is zero." "0,1" newline bitfld.long 0x40 22. "TE4I,TRIGGER event interrupt 4." "0,1" newline bitfld.long 0x40 21. "TE3I,TRIGGER event interrupt 3." "0,1" newline bitfld.long 0x40 20. "TE2I,TRIGGER event interrupt 2." "0,1" newline bitfld.long 0x40 19. "TE1I,TRIGGER event interrupt 1." "0,1" newline bitfld.long 0x40 18. "TE0I,TRIGGER event interrupt 0." "0,1" newline bitfld.long 0x40 17. "LL2I,Loss of lock interrupt for SUB_INC2." "0,1" newline bitfld.long 0x40 16. "GL2I,Get of lock interrupt for SUB_INC2." "0,1" newline bitfld.long 0x40 15. "EI,Error interrupt (see status register bit 31)." "0,1" newline bitfld.long 0x40 14. "LL1I,Loss of lock interrupt for SUB_INC1." "0,1" newline bitfld.long 0x40 13. "GL1I,Get of lock interrupt for SUB_INC1." "0,1" newline bitfld.long 0x40 12. "W1I,Write access to RAM region 1b or 1c interrupt." "0,1" newline bitfld.long 0x40 11. "W2I,RAM write access to RAM region 2 interrupt." "0,1" newline bitfld.long 0x40 10. "PWI,Plausibility window (PVT) violation interrupt of TRIGGER." "0,1" newline bitfld.long 0x40 9. "TASI,TRIGGER active slope interrupt." "0,1" newline bitfld.long 0x40 8. "SASI,STATE active slope interrupt." "0,1" newline bitfld.long 0x40 7. "MTI,Missing TRIGGER interrupt." "0,1" newline bitfld.long 0x40 6. "MSI,Missing STATE interrupt." "0,1" newline bitfld.long 0x40 5. "TISI,TRIGGER inactive slope interrupt." "0,1" newline bitfld.long 0x40 4. "SISI,STATE inactive slope interrupt." "0,1" newline bitfld.long 0x40 3. "TAXI,TRIGGER maximum hold time violation interrupt (dt > THMA > 0)." "0,1" newline bitfld.long 0x40 2. "TINI,TRIGGER minimum hold time violation interrupt (dt <= THMI > 0)." "0,1" newline bitfld.long 0x40 1. "PEI,DPLL enable interrupt; announces the switch on of the DPLL_CTRL_1.DEN bit." "0,1" newline bitfld.long 0x40 0. "PDI,DPLL disable interrupt; announces the switch off of the DPLL_CTRL_1.DEN bit." "0,1" line.long 0x44 "DPLL_IRQ_EN," bitfld.long 0x44 27. "DCGI_IRQ_EN,Direction change interrupt" "0,1" newline bitfld.long 0x44 26. "SORI_IRQ_EN,STATE out of range" "0,1" newline bitfld.long 0x44 25. "TORI_IRQ_EN,TRIGGER out of range interrupt" "0,1" newline bitfld.long 0x44 24. "CDSI_IRQ_EN,Enable interrupt when calculation of TRIGGER duration done" "0,1" newline bitfld.long 0x44 23. "CDTI_IRQ_EN,Enable interrupt when calculation of TRIGGER duration done" "0,1" newline bitfld.long 0x44 22. "TE4I_IRQ_EN,TRIGGER event interrupt 4 enable." "0,1" newline bitfld.long 0x44 21. "TE3I_IRQ_EN,TRIGGER event interrupt 3 enable." "0,1" newline bitfld.long 0x44 20. "TE2I_IRQ_EN,TRIGGER event interrupt 2 enable." "0,1" newline bitfld.long 0x44 19. "TE1I_IRQ_EN,TRIGGER event interrupt 1 enable." "0,1" newline bitfld.long 0x44 18. "TE0I_IRQ_EN,TRIGGER event interrupt 0 enable." "0,1" newline bitfld.long 0x44 17. "LL2I_IRQ_EN,Loss of lock interrupt enable for SUB_INC2." "0,1" newline bitfld.long 0x44 16. "GL2I_IRQ_EN,Get of lock interrupt enable for SUB_INC2." "0,1" newline bitfld.long 0x44 15. "EI_IRQ_EN,Error interrupt enable (see status register)." "0,1" newline bitfld.long 0x44 14. "LL1I_IRQ_EN,Loss of lock interrupt enable." "0,1" newline bitfld.long 0x44 13. "GL1I_IRQ_EN,Get of lock interrupt enable when lock arises." "0,1" newline bitfld.long 0x44 12. "W1I_IRQ_EN,Write access to RAM region 1b or 1c interrupt." "0,1" newline bitfld.long 0x44 11. "W2I_IRQ_EN,RAM write access to RAM region 2 interrupt enable." "0,1" newline bitfld.long 0x44 10. "PWI_IRQ_EN,Plausibility window (PVT) violation interrupt of TRIGGER enable." "0,1" newline bitfld.long 0x44 9. "TASI_IRQ_EN,TRIGGER active slope interrupt enable." "0,1" newline bitfld.long 0x44 8. "SASI_IRQ_EN,STATE active slope interrupt enable." "0,1" newline bitfld.long 0x44 7. "MTI_IRQ_EN,Missing TRIGGER interrupt enable." "0,1" newline bitfld.long 0x44 6. "MSI_IRQ_EN,Missing STATE interrupt enable." "0,1" newline bitfld.long 0x44 5. "TISI_IRQ_EN,TRIGGER inactive slope interrupt enable bit." "0,1" newline bitfld.long 0x44 4. "SISI_IRQ_EN,STATE inactive slope interrupt enable bit." "0,1" newline bitfld.long 0x44 3. "TAXI_IRQ_EN,TRIGGER maximum hold time violation interrupt enable bit." "0,1" newline bitfld.long 0x44 2. "TINI_IRQ_EN,TRIGGER minimum hold time violation interrupt enable bit." "0,1" newline bitfld.long 0x44 1. "PEI_IRQ_EN,DPLL enable interrupt enable when switch on of the DPLL_CTRL_1.DEN bit." "0,1" newline bitfld.long 0x44 0. "PDI_IRQ_EN,DPLL disable interrupt enable when switch off of the DPLL_CTRL_1.DEN bit." "0,1" line.long 0x48 "DPLL_IRQ_FORCINT," bitfld.long 0x48 27. "TRG_DCGI,Force interrupt DCGI" "0,1" newline bitfld.long 0x48 26. "TRG_SORI,Force Interrupt SORI" "0,1" newline bitfld.long 0x48 25. "TRG_TORI,Force Interrupt TORI" "0,1" newline bitfld.long 0x48 24. "TRG_CDSI,Force Interrupt CDSI" "0,1" newline bitfld.long 0x48 23. "TRG_CDTI,Force Interrupt CDTI" "0,1" newline bitfld.long 0x48 22. "TRG_TE4I,Force Interrupt TE4I" "0,1" newline bitfld.long 0x48 21. "TRG_TE3I,Force Interrupt TE3I" "0,1" newline bitfld.long 0x48 20. "TRG_TE2I,Force Interrupt TE2I" "0,1" newline bitfld.long 0x48 19. "TRG_TE1I,Force Interrupt TE1I" "0,1" newline bitfld.long 0x48 18. "TRG_TE0I,Force Interrupt TE0I" "0,1" newline bitfld.long 0x48 17. "TRG_LL2I,Force Interrupt LL2I" "0,1" newline bitfld.long 0x48 16. "TRG_GL2I,Force Interrupt GL2I" "0,1" newline bitfld.long 0x48 15. "TRG_EI,Force Interrupt EI" "0,1" newline bitfld.long 0x48 14. "TRG_LL1I,Force Interrupt LL1I" "0,1" newline bitfld.long 0x48 13. "TRG_GL1I,Force Interrupt GL1I" "0,1" newline bitfld.long 0x48 12. "TRG_W1I,Force Interrupt W1I" "0,1" newline bitfld.long 0x48 11. "TRG_W2I,Force Interrupt W2IF" "0,1" newline bitfld.long 0x48 10. "TRG_PWI,Force Interrupt PWI" "0,1" newline bitfld.long 0x48 9. "TRG_TASI,Force Interrupt TASI" "0,1" newline bitfld.long 0x48 8. "TRG_SASI,Force Interrupt SASI" "0,1" newline bitfld.long 0x48 7. "TRG_MTI,Force Interrupt MTI" "0,1" newline bitfld.long 0x48 6. "TRG_MSI,Force Interrupt MSI" "0,1" newline bitfld.long 0x48 5. "TRG_TISI,Force Interrupt TISI" "0,1" newline bitfld.long 0x48 4. "TRG_SISI,Force Interrupt SISI" "0,1" newline bitfld.long 0x48 3. "TRG_TAXI,Force Interrupt TAXI" "0,1" newline bitfld.long 0x48 2. "TRG_TINI,Force Interrupt TINI" "0,1" newline bitfld.long 0x48 1. "TRG_PEI,Force Interrupt PEI" "0,1" newline bitfld.long 0x48 0. "TRG_PDI,Force Interrupt PDI" "0,1" line.long 0x4C "DPLL_IRQ_MODE," bitfld.long 0x4C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x50 "DPLL_EIRQ_EN," bitfld.long 0x50 27. "DCGI_EIRQ_EN,Direction change interrupt" "0,1" newline bitfld.long 0x50 26. "SORI_EIRQ_EN,STATE out of range" "0,1" newline bitfld.long 0x50 25. "TORI_EIRQ_EN,TRIGGER out of range interrupt" "0,1" newline bitfld.long 0x50 24. "CDSI_EIRQ_EN,Enable interrupt when calculation of TRIGGER duration done" "0,1" newline bitfld.long 0x50 23. "CDTI_EIRQ_EN,Enable interrupt when calculation of TRIGGER duration done" "0,1" newline bitfld.long 0x50 22. "TE4I_EIRQ_EN,TRIGGER event interrupt 4 enable." "0,1" newline bitfld.long 0x50 21. "TE3I_EIRQ_EN,TRIGGER event interrupt 3 enable." "0,1" newline bitfld.long 0x50 20. "TE2I_EIRQ_EN,TRIGGER event interrupt 2 enable." "0,1" newline bitfld.long 0x50 19. "TE1I_EIRQ_EN,TRIGGER event interrupt 1 enable." "0,1" newline bitfld.long 0x50 18. "TE0I_EIRQ_EN,TRIGGER event interrupt 0 enable." "0,1" newline bitfld.long 0x50 17. "LL2I_EIRQ_EN,Loss of lock interrupt enable for SUB_INC2." "0,1" newline bitfld.long 0x50 16. "GL2I_EIRQ_EN,Get of lock interrupt enable for SUB_INC2." "0,1" newline bitfld.long 0x50 15. "EI_EIRQ_EN,Error interrupt enable (see status register)." "0,1" newline bitfld.long 0x50 14. "LL1I_EIRQ_EN,Loss of lock interrupt enable." "0,1" newline bitfld.long 0x50 13. "GL1I_EIRQ_EN,Get of lock interrupt enable when lock arises." "0,1" newline bitfld.long 0x50 12. "W1I_EIRQ_EN,Write access to RAM region 1b or 1c interrupt." "0,1" newline bitfld.long 0x50 11. "W2I_EIRQ_EN,RAM write access to RAM region 2 interrupt enable." "0,1" newline bitfld.long 0x50 10. "PWI_EIRQ_EN,Plausibility window (PVT) violation interrupt of TRIGGER enable." "0,1" newline bitfld.long 0x50 9. "TASI_EIRQ_EN,TRIGGER active slope interrupt enable." "0,1" newline bitfld.long 0x50 8. "SASI_EIRQ_EN,STATE active slope interrupt enable." "0,1" newline bitfld.long 0x50 7. "MTI_EIRQ_EN,Missing TRIGGER interrupt enable." "0,1" newline bitfld.long 0x50 6. "MSI_EIRQ_EN,Missing STATE interrupt enable." "0,1" newline bitfld.long 0x50 5. "TISI_EIRQ_EN,TRIGGER inactive slope interrupt enable bit." "0,1" newline bitfld.long 0x50 4. "SISI_EIRQ_EN,STATE inactive slope interrupt enable bit." "0,1" newline bitfld.long 0x50 3. "TAXI_EIRQ_EN,TRIGGER maximum hold time violation interrupt enable bit." "0,1" newline bitfld.long 0x50 2. "TINI_EIRQ_EN,TRIGGER minimum hold time violation interrupt enable bit." "0,1" newline bitfld.long 0x50 1. "PEI_EIRQ_EN,DPLL enable interrupt enable when switch on of the DPLL_CTRL_1.DEN bit." "0,1" newline bitfld.long 0x50 0. "PDI_EIRQ_EN,DPLL disable interrupt enable when switch off of the DPLL_CTRL_1.DEN bit." "0,1" group.long 0x80B0++0x1F line.long 0x0 "DPLL_INC_CNT1," hexmask.long.tbyte 0x0 0.--23. 1. "INC_CNT1,Actual number of pulses to be still sent out at the current increment until the next active input signal in automatic end mode;" line.long 0x4 "DPLL_INC_CNT2," hexmask.long.tbyte 0x4 0.--23. 1. "INC_CNT2,Actual number of pulses to be still sent out at the current increment until the next active input signal in automatic end mode;" line.long 0x8 "DPLL_APT_SYNC," hexmask.long.word 0x8 14.--23. 1. "APT_2B_OLD,Address pointer TRIGGER for RAM region 2b at synchronization time; this value is set by the current DPLL_APT.APT_2B value when the synchronization takes place for the first active TRIGGER event after writing DPLL_APT_2C.APT_2C but before.." newline bitfld.long 0x8 6. "APT_2B_STATUS,Address pointer 2b status; set by CPU before the synchronization is performed. The value is cleared when the DPLL_APT_SYNC.APT_2B_OLD value is written." "0,1" newline hexmask.long.byte 0x8 0.--5. 1. "APT_2B_EXT,Address pointer 2b extension; this offset value determines by which value the DPLL_APT.APT_2B is changed at the synchronization time; set by CPU before the synchronization is performed." line.long 0xC "DPLL_APS_SYNC," hexmask.long.byte 0xC 14.--19. 1. "APS_1C2_OLD,Address pointer STATE for RAM region 1c2 at synchronization time; this value is set by the current DPLL_APS_EXT.APS_1C2 value when the synchronization takes place for the first active STATE event after writing DPLL_APS_1C3_EXT.APS_1C3 but.." newline bitfld.long 0xC 6. "APS_1C2_STATUS,Address pointer 1c2 status; set by CPU before the synchronization is performed. The value is cleared automatically when the DPLL_APS_SYNC_EXT.APS_1C2_OLD value is written." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "APS_1C2_EXT,Address pointer 1c2 extension; this offset value determines by which value the DPLL_APS_EXT.APS_1C2 is changed at the synchronization time; set by CPU before the synchronization is performed." line.long 0x10 "DPLL_TBU_TS0_T," hexmask.long.tbyte 0x10 0.--23. 1. "TBU_TS0_T,Value of TBU_TS0 at the last TRIGGER event;" line.long 0x14 "DPLL_TBU_TS0_S," hexmask.long.tbyte 0x14 0.--23. 1. "TBU_TS0_S,Value of TBU_TS0 at the last STATE event;" line.long 0x18 "DPLL_ADD_IN_LD1," hexmask.long.tbyte 0x18 0.--23. 1. "ADD_IN_LD1,Input value for SUB_INC1 generation given by CPU. This value can be used in normal und emergency mode (DPLL_CTRL_1.SMC=0) as well as for DPLL_CTRL_1.SMC=1." line.long 0x1C "DPLL_ADD_IN_LD2," hexmask.long.tbyte 0x1C 0.--23. 1. "ADD_IN_LD2,ADD_IN_LD_2: Input value for SUB_INC2 generation given by CPU. This value can be used for DPLL_CTRL_1.SMC=1 while DPLL_CTRL_0.RMO=1." group.long 0x80FC++0x83 line.long 0x0 "DPLL_STATUS," bitfld.long 0x0 31. "ERR,Error during configuration or operation resulting in unexpected values." "0,1" newline bitfld.long 0x0 30. "LOCK1,DPLL Lock status concerning SUB_INC1." "0,1" newline bitfld.long 0x0 29. "FTD,First TRIGGER detected." "0,1" newline bitfld.long 0x0 28. "FSD,First STATE detected." "0,1" newline bitfld.long 0x0 27. "SYT,Synchronization condition of TRIGGER fixed." "0,1" newline bitfld.long 0x0 26. "SYS,Synchronization condition of STATE fixed." "0,1" newline bitfld.long 0x0 25. "LOCK2,DPLL Lock status concerning SUB_INC2" "0,1" newline bitfld.long 0x0 23. "BWD1,Backwards drive of SUB_INC1" "0,1" newline bitfld.long 0x0 22. "BWD2,Backwards drive of SUB_INC2" "0,1" newline bitfld.long 0x0 21. "ITN,Increment number of TRIGGER is not plausible; Bit is set when the number of TRIGGERS is different to profile" "0,1" newline bitfld.long 0x0 20. "ISN,Increment number of STATE is not plausible; Bit is set when the number of STATES is different to profile" "0,1" newline bitfld.long 0x0 19. "CAIP1,Calculation of lower half actions in progress" "0,1" newline bitfld.long 0x0 18. "CAIP2,Calculation of upper half actions in progress" "0,1" newline bitfld.long 0x0 17. "CSVT,Current signal value TRIGGER" "0,1" newline bitfld.long 0x0 16. "CSVS,Current signal value STATE" "0,1" newline bitfld.long 0x0 15. "LOW_RES,Low resolution of TBU_TS0 is used for DPLL input; this value reflects the input signal LOW_RES" "0,1" newline bitfld.long 0x0 12. "RAM2_ERR,DPLL internal access to not configured RAM2 memory space" "0,1" newline bitfld.long 0x0 11. "MT,Missing TRIGGER detected according to TOV" "0,1" newline bitfld.long 0x0 10. "TOR,TRIGGER out of range" "0,1" newline bitfld.long 0x0 9. "MS,Missing STATE detected according to SOV." "0,1" newline bitfld.long 0x0 8. "SOR,STATE out of range" "0,1" newline bitfld.long 0x0 7. "PSE,Prediction space configuration error" "0,1" newline bitfld.long 0x0 6. "RCT,Resolution conflict TRIGGER." "0,1" newline bitfld.long 0x0 5. "RCS,Resolution conflict STATE." "0,1" newline bitfld.long 0x0 4. "CRO,Calculated Reciprocal value overflow." "0,1" newline bitfld.long 0x0 3. "CTO,Calculated TRIGGER duration overflow." "0,1" newline bitfld.long 0x0 1. "CSO,Calculated STATE duration overflow." "0,1" newline bitfld.long 0x0 0. "FPCE,Fast pulse correction error" "0,1" line.long 0x4 "DPLL_ID_PMTR_0," hexmask.long.word 0x4 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x8 "DPLL_ID_PMTR_1," hexmask.long.word 0x8 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0xC "DPLL_ID_PMTR_2," hexmask.long.word 0xC 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x10 "DPLL_ID_PMTR_3," hexmask.long.word 0x10 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x14 "DPLL_ID_PMTR_4," hexmask.long.word 0x14 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x18 "DPLL_ID_PMTR_5," hexmask.long.word 0x18 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x1C "DPLL_ID_PMTR_6," hexmask.long.word 0x1C 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x20 "DPLL_ID_PMTR_7," hexmask.long.word 0x20 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x24 "DPLL_ID_PMTR_8," hexmask.long.word 0x24 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x28 "DPLL_ID_PMTR_9," hexmask.long.word 0x28 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x2C "DPLL_ID_PMTR_10," hexmask.long.word 0x2C 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x30 "DPLL_ID_PMTR_11," hexmask.long.word 0x30 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x34 "DPLL_ID_PMTR_12," hexmask.long.word 0x34 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x38 "DPLL_ID_PMTR_13," hexmask.long.word 0x38 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x3C "DPLL_ID_PMTR_14," hexmask.long.word 0x3C 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x40 "DPLL_ID_PMTR_15," hexmask.long.word 0x40 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x44 "DPLL_ID_PMTR_16," hexmask.long.word 0x44 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x48 "DPLL_ID_PMTR_17," hexmask.long.word 0x48 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x4C "DPLL_ID_PMTR_18," hexmask.long.word 0x4C 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x50 "DPLL_ID_PMTR_19," hexmask.long.word 0x50 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x54 "DPLL_ID_PMTR_20," hexmask.long.word 0x54 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x58 "DPLL_ID_PMTR_21," hexmask.long.word 0x58 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x5C "DPLL_ID_PMTR_22," hexmask.long.word 0x5C 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x60 "DPLL_ID_PMTR_23," hexmask.long.word 0x60 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x64 "DPLL_ID_PMTR_24," hexmask.long.word 0x64 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x68 "DPLL_ID_PMTR_25," hexmask.long.word 0x68 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x6C "DPLL_ID_PMTR_26," hexmask.long.word 0x6C 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x70 "DPLL_ID_PMTR_27," hexmask.long.word 0x70 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x74 "DPLL_ID_PMTR_28," hexmask.long.word 0x74 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x78 "DPLL_ID_PMTR_29," hexmask.long.word 0x78 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x7C "DPLL_ID_PMTR_30," hexmask.long.word 0x7C 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." line.long 0x80 "DPLL_ID_PMTR_31," hexmask.long.word 0x80 0.--8. 1. "ID_PMTR,ID information to the input signal PMTR[n] from the ARU." group.long 0x81E0++0xF line.long 0x0 "DPLL_CTRL_0_SHADOW_TRIGGER," bitfld.long 0x0 31. "RMO,Reference mode; selection of the relevant the input signal for generation of SUB_INC1." "0,1" newline bitfld.long 0x0 28. "IDT,Input delay TRIGGER; use of input delay information transmitted in FT part of the TRIGGER signal." "0,1" newline bitfld.long 0x0 26. "AMT,Use of adaptation information of Adapt mode TRIGGER;" "0,1" newline bitfld.long 0x0 10. "IFP,Input filter position; value contains position or time related information." "0,1" newline hexmask.long.word 0x0 0.--9. 1. "MLT,Multiplier for TRIGGER; MLT+1 is number of SUB_INC1 pulses between two TRIGGER events in normal mode (1...1024);" line.long 0x4 "DPLL_CTRL_0_SHADOW_STATE," bitfld.long 0x4 31. "RMO,Reference mode; selection of the relevant the input signal for generation of SUB_INC1." "0,1" newline bitfld.long 0x4 27. "IDS,Input delay STATE; Use of input delay information transmitted in FT part of the STATE signal." "0,1" newline bitfld.long 0x4 25. "AMS,Adapt mode STATE; Use of adaptation information of STATE." "0,1" newline bitfld.long 0x4 10. "IFP,Input filter position; value contains position or time related information." "0,1" line.long 0x8 "DPLL_CTRL_1_SHADOW_TRIGGER," bitfld.long 0x8 7. "PCM1,Pulse Correction Mode for SUB_INC1 generation." "0,1" newline bitfld.long 0x8 6. "DLM1,Direct Load Mode for SUB_INC1 generation" "0,1" newline bitfld.long 0x8 5. "SGE1,SUB_INC1 generator enable." "0,1" newline bitfld.long 0x8 4. "PIT,Plausibility value PVT to next active TRIGGER is time related" "0,1" newline bitfld.long 0x8 3. "COA,Correction strategy in automatic end mode (DPLL_CTRL_1.DMO=0)." "0,1" newline bitfld.long 0x8 0. "DMO,DPLL mode select." "0,1" line.long 0xC "DPLL_CTRL_1_SHADOW_STATE," bitfld.long 0xC 10. "PCM2,Pulse Correction Mode for SUB_INC2 generation." "0,1" newline bitfld.long 0xC 9. "DLM2,Direct Load Mode for SUB_INC2 generation" "0,1" newline bitfld.long 0xC 8. "SGE2,SUB_INC2 generator enable." "0,1" newline bitfld.long 0xC 7. "PCM1,Pulse Correction Mode for SUB_INC1 generation." "0,1" newline bitfld.long 0xC 6. "DLM1,Direct Load Mode for SUB_INC1 generation" "0,1" newline bitfld.long 0xC 5. "SGE1,SUB_INC1 generator enable." "0,1" newline bitfld.long 0xC 3. "COA,Correction strategy in automatic end mode (DPLL_CTRL_1.DMO=0)." "0,1" newline bitfld.long 0xC 0. "DMO,DPLL mode select." "0,1" group.long 0x81FC++0x803 line.long 0x0 "DPLL_RAM_INI," bitfld.long 0x0 4. "INIT_RAM,RAM regions 1a 1b and 2 are to be initialized." "0,1" newline bitfld.long 0x0 2. "INIT_2,RAM region 2 initialization in progress" "0,1" newline bitfld.long 0x0 1. "INIT_1BC,RAM region 1b and 1c initialization in progress" "0,1" newline bitfld.long 0x0 0. "INIT_1A,RAM region 1a initialization in progress" "0,1" line.long 0x4 "DPLL_PSA0," hexmask.long.tbyte 0x4 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x8 "DPLL_PSA1," hexmask.long.tbyte 0x8 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0xC "DPLL_PSA2," hexmask.long.tbyte 0xC 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x10 "DPLL_PSA3," hexmask.long.tbyte 0x10 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x14 "DPLL_PSA4," hexmask.long.tbyte 0x14 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x18 "DPLL_PSA5," hexmask.long.tbyte 0x18 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x1C "DPLL_PSA6," hexmask.long.tbyte 0x1C 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x20 "DPLL_PSA7," hexmask.long.tbyte 0x20 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x24 "DPLL_PSA8," hexmask.long.tbyte 0x24 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x28 "DPLL_PSA9," hexmask.long.tbyte 0x28 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x2C "DPLL_PSA10," hexmask.long.tbyte 0x2C 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x30 "DPLL_PSA11," hexmask.long.tbyte 0x30 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x34 "DPLL_PSA12," hexmask.long.tbyte 0x34 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x38 "DPLL_PSA13," hexmask.long.tbyte 0x38 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x3C "DPLL_PSA14," hexmask.long.tbyte 0x3C 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x40 "DPLL_PSA15," hexmask.long.tbyte 0x40 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x44 "DPLL_PSA16," hexmask.long.tbyte 0x44 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x48 "DPLL_PSA17," hexmask.long.tbyte 0x48 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x4C "DPLL_PSA18," hexmask.long.tbyte 0x4C 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x50 "DPLL_PSA19," hexmask.long.tbyte 0x50 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x54 "DPLL_PSA20," hexmask.long.tbyte 0x54 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x58 "DPLL_PSA21," hexmask.long.tbyte 0x58 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x5C "DPLL_PSA22," hexmask.long.tbyte 0x5C 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x60 "DPLL_PSA23," hexmask.long.tbyte 0x60 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x64 "DPLL_PSA24," hexmask.long.tbyte 0x64 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x68 "DPLL_PSA25," hexmask.long.tbyte 0x68 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x6C "DPLL_PSA26," hexmask.long.tbyte 0x6C 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x70 "DPLL_PSA27," hexmask.long.tbyte 0x70 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x74 "DPLL_PSA28," hexmask.long.tbyte 0x74 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x78 "DPLL_PSA29," hexmask.long.tbyte 0x78 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x7C "DPLL_PSA30," hexmask.long.tbyte 0x7C 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x80 "DPLL_PSA31," hexmask.long.tbyte 0x80 0.--23. 1. "PSA,Position information of a desired action (n=0...NOAC-1)." line.long 0x84 "DPLL_DLA0," hexmask.long.tbyte 0x84 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0x88 "DPLL_DLA1," hexmask.long.tbyte 0x88 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0x8C "DPLL_DLA2," hexmask.long.tbyte 0x8C 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0x90 "DPLL_DLA3," hexmask.long.tbyte 0x90 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0x94 "DPLL_DLA4," hexmask.long.tbyte 0x94 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0x98 "DPLL_DLA5," hexmask.long.tbyte 0x98 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0x9C "DPLL_DLA6," hexmask.long.tbyte 0x9C 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xA0 "DPLL_DLA7," hexmask.long.tbyte 0xA0 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xA4 "DPLL_DLA8," hexmask.long.tbyte 0xA4 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xA8 "DPLL_DLA9," hexmask.long.tbyte 0xA8 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xAC "DPLL_DLA10," hexmask.long.tbyte 0xAC 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xB0 "DPLL_DLA11," hexmask.long.tbyte 0xB0 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xB4 "DPLL_DLA12," hexmask.long.tbyte 0xB4 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xB8 "DPLL_DLA13," hexmask.long.tbyte 0xB8 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xBC "DPLL_DLA14," hexmask.long.tbyte 0xBC 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xC0 "DPLL_DLA15," hexmask.long.tbyte 0xC0 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xC4 "DPLL_DLA16," hexmask.long.tbyte 0xC4 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xC8 "DPLL_DLA17," hexmask.long.tbyte 0xC8 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xCC "DPLL_DLA18," hexmask.long.tbyte 0xCC 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xD0 "DPLL_DLA19," hexmask.long.tbyte 0xD0 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xD4 "DPLL_DLA20," hexmask.long.tbyte 0xD4 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xD8 "DPLL_DLA21," hexmask.long.tbyte 0xD8 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xDC "DPLL_DLA22," hexmask.long.tbyte 0xDC 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xE0 "DPLL_DLA23," hexmask.long.tbyte 0xE0 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xE4 "DPLL_DLA24," hexmask.long.tbyte 0xE4 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xE8 "DPLL_DLA25," hexmask.long.tbyte 0xE8 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xEC "DPLL_DLA26," hexmask.long.tbyte 0xEC 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xF0 "DPLL_DLA27," hexmask.long.tbyte 0xF0 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xF4 "DPLL_DLA28," hexmask.long.tbyte 0xF4 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xF8 "DPLL_DLA29," hexmask.long.tbyte 0xF8 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0xFC "DPLL_DLA30," hexmask.long.tbyte 0xFC 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0x100 "DPLL_DLA31," hexmask.long.tbyte 0x100 0.--23. 1. "DLA,Time to react before the corresponding position value of a desired action is reached (n=0...NOAC-1)." line.long 0x104 "DPLL_NA0," hexmask.long.byte 0x104 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x104 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x104 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x108 "DPLL_NA1," hexmask.long.byte 0x108 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x108 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x108 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x10C "DPLL_NA2," hexmask.long.byte 0x10C 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x10C 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x10C 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x110 "DPLL_NA3," hexmask.long.byte 0x110 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x110 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x110 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x114 "DPLL_NA4," hexmask.long.byte 0x114 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x114 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x114 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x118 "DPLL_NA5," hexmask.long.byte 0x118 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x118 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x118 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x11C "DPLL_NA6," hexmask.long.byte 0x11C 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x11C 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x11C 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x120 "DPLL_NA7," hexmask.long.byte 0x120 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x120 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x120 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x124 "DPLL_NA8," hexmask.long.byte 0x124 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x124 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x124 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x128 "DPLL_NA9," hexmask.long.byte 0x128 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x128 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x128 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x12C "DPLL_NA10," hexmask.long.byte 0x12C 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x12C 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x12C 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x130 "DPLL_NA11," hexmask.long.byte 0x130 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x130 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x130 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x134 "DPLL_NA12," hexmask.long.byte 0x134 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x134 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x134 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x138 "DPLL_NA13," hexmask.long.byte 0x138 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x138 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x138 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x13C "DPLL_NA14," hexmask.long.byte 0x13C 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x13C 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x13C 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x140 "DPLL_NA15," hexmask.long.byte 0x140 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x140 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x140 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x144 "DPLL_NA16," hexmask.long.byte 0x144 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x144 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x144 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x148 "DPLL_NA17," hexmask.long.byte 0x148 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x148 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x148 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x14C "DPLL_NA18," hexmask.long.byte 0x14C 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x14C 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x14C 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x150 "DPLL_NA19," hexmask.long.byte 0x150 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x150 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x150 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x154 "DPLL_NA20," hexmask.long.byte 0x154 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x154 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x154 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x158 "DPLL_NA21," hexmask.long.byte 0x158 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x158 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x158 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x15C "DPLL_NA22," hexmask.long.byte 0x15C 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x15C 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x15C 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x160 "DPLL_NA23," hexmask.long.byte 0x160 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x160 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x160 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x164 "DPLL_NA24," hexmask.long.byte 0x164 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x164 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x164 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x168 "DPLL_NA25," hexmask.long.byte 0x168 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x168 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x168 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x16C "DPLL_NA26," hexmask.long.byte 0x16C 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x16C 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x16C 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x170 "DPLL_NA27," hexmask.long.byte 0x170 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x170 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x170 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x174 "DPLL_NA28," hexmask.long.byte 0x174 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x174 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x174 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x178 "DPLL_NA29," hexmask.long.byte 0x178 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x178 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x178 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x17C "DPLL_NA30," hexmask.long.byte 0x17C 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x17C 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x17C 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x180 "DPLL_NA31," hexmask.long.byte 0x180 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x180 10.--19. 1. "DW,Number of events to Action_n (integer part n=0...NOAC-1)." newline hexmask.long.word 0x180 0.--9. 1. "DB,Number of events to Action_n (fractional part n=0...NOAC-1)." line.long 0x184 "DPLL_DTA0," hexmask.long.tbyte 0x184 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x188 "DPLL_DTA1," hexmask.long.tbyte 0x188 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x18C "DPLL_DTA2," hexmask.long.tbyte 0x18C 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x190 "DPLL_DTA3," hexmask.long.tbyte 0x190 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x194 "DPLL_DTA4," hexmask.long.tbyte 0x194 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x198 "DPLL_DTA5," hexmask.long.tbyte 0x198 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x19C "DPLL_DTA6," hexmask.long.tbyte 0x19C 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1A0 "DPLL_DTA7," hexmask.long.tbyte 0x1A0 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1A4 "DPLL_DTA8," hexmask.long.tbyte 0x1A4 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1A8 "DPLL_DTA9," hexmask.long.tbyte 0x1A8 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1AC "DPLL_DTA10," hexmask.long.tbyte 0x1AC 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1B0 "DPLL_DTA11," hexmask.long.tbyte 0x1B0 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1B4 "DPLL_DTA12," hexmask.long.tbyte 0x1B4 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1B8 "DPLL_DTA13," hexmask.long.tbyte 0x1B8 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1BC "DPLL_DTA14," hexmask.long.tbyte 0x1BC 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1C0 "DPLL_DTA15," hexmask.long.tbyte 0x1C0 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1C4 "DPLL_DTA16," hexmask.long.tbyte 0x1C4 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1C8 "DPLL_DTA17," hexmask.long.tbyte 0x1C8 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1CC "DPLL_DTA18," hexmask.long.tbyte 0x1CC 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1D0 "DPLL_DTA19," hexmask.long.tbyte 0x1D0 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1D4 "DPLL_DTA20," hexmask.long.tbyte 0x1D4 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1D8 "DPLL_DTA21," hexmask.long.tbyte 0x1D8 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1DC "DPLL_DTA22," hexmask.long.tbyte 0x1DC 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1E0 "DPLL_DTA23," hexmask.long.tbyte 0x1E0 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1E4 "DPLL_DTA24," hexmask.long.tbyte 0x1E4 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1E8 "DPLL_DTA25," hexmask.long.tbyte 0x1E8 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1EC "DPLL_DTA26," hexmask.long.tbyte 0x1EC 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1F0 "DPLL_DTA27," hexmask.long.tbyte 0x1F0 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1F4 "DPLL_DTA28," hexmask.long.tbyte 0x1F4 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1F8 "DPLL_DTA29," hexmask.long.tbyte 0x1F8 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x1FC "DPLL_DTA30," hexmask.long.tbyte 0x1FC 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x200 "DPLL_DTA31," hexmask.long.tbyte 0x200 0.--23. 1. "DTA,Calculated relative time to ACTION_n (n=0...NOAC-1)" line.long 0x204 "DPLL_TS_T," hexmask.long.tbyte 0x204 0.--23. 1. "TRIGGER_TS,Time stamp value of the last active TRIGGER input." line.long 0x208 "DPLL_TS_T_OLD," hexmask.long.tbyte 0x208 0.--23. 1. "TRIGGER_TS_OLD,Time stamp value of the last but one active TRIGGER input." line.long 0x20C "DPLL_FTV_T," hexmask.long.tbyte 0x20C 0.--23. 1. "TRIGGER_FT,Filter value of the last active TRIGGER input." line.long 0x210 "DPLL_RAM1B_RSVD_0," hexmask.long.tbyte 0x210 0.--23. 1. "RSVD,Reserved Data word no DPLL internal use." line.long 0x214 "DPLL_TS_S," hexmask.long.tbyte 0x214 0.--23. 1. "STATE_TS,Time stamp value of the last active STATE input." line.long 0x218 "DPLL_TS_S_OLD," hexmask.long.tbyte 0x218 0.--23. 1. "STATE_TS_OLD,Time stamp value of the last active STATE input." line.long 0x21C "DPLL_FTV_S," hexmask.long.tbyte 0x21C 0.--23. 1. "STATE_FT,Filter value of the last active STATE input." line.long 0x220 "DPLL_RAM1B_RSVD_1," hexmask.long.tbyte 0x220 0.--23. 1. "RSVD,Reserved Data word no DPLL internal use." line.long 0x224 "DPLL_THMI," hexmask.long.byte 0x224 16.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x224 0.--15. 1. "THMI,Minimal time between active and inactive TRIGGER slope (uint16); the time value corresponds to the time stamp clock counts: this does mean the clock selected for the TBU_CH0_BASE (see TBU_CH0_CTRL register)" line.long 0x228 "DPLL_THMA," hexmask.long.byte 0x228 16.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x228 0.--15. 1. "THMA,Maximal time between active and inactive TRIGGER slope (uint16); the time value corresponds to the time stamp clock counts: this does mean the clock selected for the TBU_CH0_BASE (see TBU_CH0_CTRL register)" line.long 0x22C "DPLL_THVAL," hexmask.long.tbyte 0x22C 0.--23. 1. "THVAL,Measured time from the last active slope to the next inactive TRIGGER slope in time stamp clock counts: this does mean the clock selected for the TBU_CH0_BASE (uint16);" line.long 0x230 "DPLL_RAM1B_RSVD_2," hexmask.long.tbyte 0x230 0.--23. 1. "RSVD,Reserved Data word no DPLL internal use." line.long 0x234 "DPLL_TOV," hexmask.long.byte 0x234 16.--23. 1. "NOT_USED,Not used" newline hexmask.long.byte 0x234 10.--15. 1. "TOV_DW,Decision value (integer part) for missing TRIGGER interrupt." newline hexmask.long.word 0x234 0.--9. 1. "TOV_DB,Decision value (fractional part) for missing TRIGGER interrupt." line.long 0x238 "DPLL_TOV_S," hexmask.long.byte 0x238 16.--23. 1. "NOT_USED,Not used" newline hexmask.long.byte 0x238 10.--15. 1. "DW,Decision value (integer part) for missing STATE interrupt." newline hexmask.long.word 0x238 0.--9. 1. "DB,Decision value (fractional part) for missing STATE interrupt." line.long 0x23C "DPLL_ADD_IN_CAL1," hexmask.long.tbyte 0x23C 0.--23. 1. "ADD_IN_CAL1,Calculated input value for SUB_INC1 generation calculated by the DPLL." line.long 0x240 "DPLL_ADD_IN_CAL2," hexmask.long.tbyte 0x240 0.--23. 1. "ADD_IN_CAL2,Input value for SUB_INC2 generation calculated by the DPLL for DPLL_CTRL_1.SMC=RMO=1." line.long 0x244 "DPLL_MPVAL1," hexmask.long.byte 0x244 16.--23. 1. "SIX1,Sign extension for MPVAL1" newline hexmask.long.word 0x244 0.--15. 1. "MPVAL1,Missing pulses for direct correction of SUB_INC1 pulses by the CPU (sint16);" line.long 0x248 "DPLL_MPVAL2," hexmask.long.byte 0x248 16.--23. 1. "SIX2,Sign extension for MPVAL2" newline hexmask.long.word 0x248 0.--15. 1. "MPVAL2,Missing pulses for direct correction of SUB_INC2 pulses by the CPU (sint16);" line.long 0x24C "DPLL_NMB_T_TAR," hexmask.long.byte 0x24C 16.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x24C 0.--15. 1. "NMB_T_TAR,Target number of pulses for TRIGGER; Calculated target number of pulses in normal mode for the current TRIGGER increment without missing pulses." line.long 0x250 "DPLL_NMB_T_TAR_OLD," hexmask.long.byte 0x250 16.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x250 0.--15. 1. "NMB_T_TAR_OLD,Target Number of pulses for TRIGGER; Calculated number of pulses in normal mode for the current TRIGGER increment without missing pulses." line.long 0x254 "DPLL_NMB_S_TAR," hexmask.long.byte 0x254 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.tbyte 0x254 0.--19. 1. "NMB_S_TAR,Target Number of pulses for STATE; Calculated number of pulses in emergency mode for the current STATE increment without missing pulses." line.long 0x258 "DPLL_NMB_S_TAR_OLD," hexmask.long.byte 0x258 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.tbyte 0x258 0.--19. 1. "NMB_S_TAR_OLD,Target Number of pulses for STATE; Calculated number of pulses in emergency mode for the current STATE increment without missing pulses." line.long 0x25C "DPLL_RAM1B_RSVD_3_0," hexmask.long.tbyte 0x25C 0.--23. 1. "RSVD,Reserved Data word no DPLL internal use." line.long 0x260 "DPLL_RAM1B_RSVD_3_1," hexmask.long.tbyte 0x260 0.--23. 1. "RSVD,Reserved Data word no DPLL internal use." line.long 0x264 "DPLL_RCDT_TX," hexmask.long.tbyte 0x264 0.--23. 1. "RCDT_TX,Reciprocal value of expected increment duration *232 while only the lower 24 bits are used." line.long 0x268 "DPLL_RCDT_SX," hexmask.long.tbyte 0x268 0.--23. 1. "RCDT_SX,Reciprocal value of expected increment duration *232 while only the lower 24 bits are used." line.long 0x26C "DPLL_RCDT_TX_NOM," hexmask.long.tbyte 0x26C 0.--23. 1. "RCDT_TX_NOM,Reciprocal value of nominal increment duration *232 while only the lower 24 bits are used." line.long 0x270 "DPLL_RCDT_SX_NOM," hexmask.long.tbyte 0x270 0.--23. 1. "RCDT_SX_NOM,Reciprocal value of nominal increment duration *232 while only the lower 24 bits are used." line.long 0x274 "DPLL_RDT_T_ACT," hexmask.long.tbyte 0x274 0.--23. 1. "RDT_T_ACT,Reciprocal value of last TRIGGER increment *232 only the lower 24 bits are used; the LSB is rounded up when the next truncated bit is 1." line.long 0x278 "DPLL_RDT_S_ACT," hexmask.long.tbyte 0x278 0.--23. 1. "RDT_S_ACT,Reciprocal value of last STATE increment *232 only the lower 24 bits are used; the LSB is rounded up when the next truncated bit is 1." line.long 0x27C "DPLL_DT_T_ACT," hexmask.long.tbyte 0x27C 0.--23. 1. "DT_T_ACT,Calculated duration of the last TRIGGER increment." line.long 0x280 "DPLL_DT_S_ACT," hexmask.long.tbyte 0x280 0.--23. 1. "DT_S_ACT,Calculated duration of the last STATE increment." line.long 0x284 "DPLL_EDT_T," hexmask.long.tbyte 0x284 0.--23. 1. "EDT_T,Signed difference between actual value and a simple prediction of the last TRIGGER increment: sint24" line.long 0x288 "DPLL_MEDT_T," hexmask.long.tbyte 0x288 0.--23. 1. "MEDT_T,Signed middle weighted difference between actual value and prediction of the last TRIGGER increments: sint24; only calculated for DPLL_STATUS.SYT=1" line.long 0x28C "DPLL_EDT_S," hexmask.long.tbyte 0x28C 0.--23. 1. "EDT_S,Signed difference between actual value and prediction of the last STATE increment: sint24" line.long 0x290 "DPLL_MEDT_S," hexmask.long.tbyte 0x290 0.--23. 1. "MEDT_S,Signed middle weighted difference between actual value and prediction of the last STATE increments: sint24; only calculated for SYS=1" line.long 0x294 "DPLL_CDT_TX," hexmask.long.tbyte 0x294 0.--23. 1. "CDT_TX,Calculated duration of the current TRIGGER increment." line.long 0x298 "DPLL_CDT_SX," hexmask.long.tbyte 0x298 0.--23. 1. "CDT_SX,Calculated duration of the current STATE increment." line.long 0x29C "DPLL_CDT_TX_NOM," hexmask.long.tbyte 0x29C 0.--23. 1. "CDT_TX_NOM,Calculated duration of the current nominal TRIGGER event." line.long 0x2A0 "DPLL_CDT_SX_NOM," hexmask.long.tbyte 0x2A0 0.--23. 1. "CDT_SX_NOM,Calculated duration of the current nominal STATE event." line.long 0x2A4 "DPLL_TLR," hexmask.long.word 0x2A4 8.--23. 1. "NOT_USED,Not used" newline hexmask.long.byte 0x2A4 0.--7. 1. "TLR,Value is to be multiplied with the last nominal TRIGGER duration in order to get the range for the next TRIGGER event without setting DPLL_STATUS.TOR in the DPLL_STATUS register" line.long 0x2A8 "DPLL_SLR," hexmask.long.word 0x2A8 8.--23. 1. "NOT_USED,Not used" newline hexmask.long.byte 0x2A8 0.--7. 1. "SLR,Value is to be multiplied with the last nominal STATE duration in order to get the range for the next STATE event without setting DPLL_STATUS.SOR in the DPLL_STATUS register" line.long 0x2AC "DPLL_RAM1B_RSVD_4_0," hexmask.long.tbyte 0x2AC 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x2B0 "DPLL_RAM1B_RSVD_4_1," hexmask.long.tbyte 0x2B0 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x2B4 "DPLL_RAM1B_RSVD_4_2," hexmask.long.tbyte 0x2B4 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x2B8 "DPLL_RAM1B_RSVD_4_3," hexmask.long.tbyte 0x2B8 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x2BC "DPLL_RAM1B_RSVD_4_4," hexmask.long.tbyte 0x2BC 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x2C0 "DPLL_RAM1B_RSVD_4_5," hexmask.long.tbyte 0x2C0 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x2C4 "DPLL_RAM1B_RSVD_4_6," hexmask.long.tbyte 0x2C4 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x2C8 "DPLL_RAM1B_RSVD_4_7," hexmask.long.tbyte 0x2C8 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x2CC "DPLL_RAM1B_RSVD_4_8," hexmask.long.tbyte 0x2CC 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x2D0 "DPLL_RAM1B_RSVD_4_9," hexmask.long.tbyte 0x2D0 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x2D4 "DPLL_RAM1B_RSVD_4_10," hexmask.long.tbyte 0x2D4 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x2D8 "DPLL_RAM1B_RSVD_4_11," hexmask.long.tbyte 0x2D8 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x2DC "DPLL_RAM1B_RSVD_4_12," hexmask.long.tbyte 0x2DC 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x2E0 "DPLL_RAM1B_RSVD_4_13," hexmask.long.tbyte 0x2E0 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x2E4 "DPLL_RAM1B_RSVD_4_14," hexmask.long.tbyte 0x2E4 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x2E8 "DPLL_RAM1B_RSVD_4_15," hexmask.long.tbyte 0x2E8 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x2EC "DPLL_RAM1B_RSVD_4_16," hexmask.long.tbyte 0x2EC 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x2F0 "DPLL_RAM1B_RSVD_4_17," hexmask.long.tbyte 0x2F0 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x2F4 "DPLL_RAM1B_RSVD_4_18," hexmask.long.tbyte 0x2F4 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x2F8 "DPLL_RAM1B_RSVD_4_19," hexmask.long.tbyte 0x2F8 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x2FC "DPLL_RAM1B_RSVD_4_20," hexmask.long.tbyte 0x2FC 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x300 "DPLL_RAM1B_RSVD_4_21," hexmask.long.tbyte 0x300 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x304 "DPLL_PDT_0," hexmask.long.word 0x304 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x304 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x308 "DPLL_PDT_1," hexmask.long.word 0x308 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x308 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x30C "DPLL_PDT_2," hexmask.long.word 0x30C 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x30C 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x310 "DPLL_PDT_3," hexmask.long.word 0x310 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x310 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x314 "DPLL_PDT_4," hexmask.long.word 0x314 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x314 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x318 "DPLL_PDT_5," hexmask.long.word 0x318 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x318 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x31C "DPLL_PDT_6," hexmask.long.word 0x31C 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x31C 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x320 "DPLL_PDT_7," hexmask.long.word 0x320 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x320 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x324 "DPLL_PDT_8," hexmask.long.word 0x324 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x324 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x328 "DPLL_PDT_9," hexmask.long.word 0x328 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x328 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x32C "DPLL_PDT_10," hexmask.long.word 0x32C 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x32C 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x330 "DPLL_PDT_11," hexmask.long.word 0x330 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x330 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x334 "DPLL_PDT_12," hexmask.long.word 0x334 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x334 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x338 "DPLL_PDT_13," hexmask.long.word 0x338 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x338 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x33C "DPLL_PDT_14," hexmask.long.word 0x33C 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x33C 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x340 "DPLL_PDT_15," hexmask.long.word 0x340 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x340 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x344 "DPLL_PDT_16," hexmask.long.word 0x344 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x344 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x348 "DPLL_PDT_17," hexmask.long.word 0x348 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x348 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x34C "DPLL_PDT_18," hexmask.long.word 0x34C 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x34C 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x350 "DPLL_PDT_19," hexmask.long.word 0x350 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x350 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x354 "DPLL_PDT_20," hexmask.long.word 0x354 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x354 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x358 "DPLL_PDT_21," hexmask.long.word 0x358 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x358 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x35C "DPLL_PDT_22," hexmask.long.word 0x35C 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x35C 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x360 "DPLL_PDT_23," hexmask.long.word 0x360 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x360 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x364 "DPLL_PDT_24," hexmask.long.word 0x364 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x364 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x368 "DPLL_PDT_25," hexmask.long.word 0x368 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x368 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x36C "DPLL_PDT_26," hexmask.long.word 0x36C 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x36C 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x370 "DPLL_PDT_27," hexmask.long.word 0x370 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x370 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x374 "DPLL_PDT_28," hexmask.long.word 0x374 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x374 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x378 "DPLL_PDT_29," hexmask.long.word 0x378 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x378 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x37C "DPLL_PDT_30," hexmask.long.word 0x37C 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x37C 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x380 "DPLL_PDT_31," hexmask.long.word 0x380 14.--23. 1. "DW,Integer part of relation between TRIGGER and STATE increments." newline hexmask.long.word 0x380 0.--13. 1. "DB,Fractional part of relation between TRIGGER and STATE increments." line.long 0x384 "DPLL_RAM1B_RSVD_5_0," hexmask.long.tbyte 0x384 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x388 "DPLL_RAM1B_RSVD_5_1," hexmask.long.tbyte 0x388 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x38C "DPLL_RAM1B_RSVD_5_2," hexmask.long.tbyte 0x38C 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x390 "DPLL_RAM1B_RSVD_5_3," hexmask.long.tbyte 0x390 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x394 "DPLL_RAM1B_RSVD_5_4," hexmask.long.tbyte 0x394 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x398 "DPLL_RAM1B_RSVD_5_5," hexmask.long.tbyte 0x398 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x39C "DPLL_RAM1B_RSVD_5_6," hexmask.long.tbyte 0x39C 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x3A0 "DPLL_RAM1B_RSVD_5_7," hexmask.long.tbyte 0x3A0 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x3A4 "DPLL_RAM1B_RSVD_5_8," hexmask.long.tbyte 0x3A4 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x3A8 "DPLL_RAM1B_RSVD_5_9," hexmask.long.tbyte 0x3A8 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x3AC "DPLL_RAM1B_RSVD_5_10," hexmask.long.tbyte 0x3AC 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x3B0 "DPLL_RAM1B_RSVD_5_11," hexmask.long.tbyte 0x3B0 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x3B4 "DPLL_RAM1B_RSVD_5_12," hexmask.long.tbyte 0x3B4 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x3B8 "DPLL_RAM1B_RSVD_5_13," hexmask.long.tbyte 0x3B8 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x3BC "DPLL_RAM1B_RSVD_5_14," hexmask.long.tbyte 0x3BC 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x3C0 "DPLL_RAM1B_RSVD_5_15," hexmask.long.tbyte 0x3C0 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x3C4 "DPLL_MLS1," hexmask.long.byte 0x3C4 18.--23. 1. "NOT_USED,Not used" newline hexmask.long.tbyte 0x3C4 0.--17. 1. "MLS1,Number of pulses between two STATE events (to be set and updated by the CPU)." line.long 0x3C8 "DPLL_MLS2," hexmask.long.byte 0x3C8 18.--23. 1. "NOT_USED,Not used" newline hexmask.long.tbyte 0x3C8 0.--17. 1. "MLS2,Number of pulses between two STATE events (to be set and updated by the CPU)." line.long 0x3CC "DPLL_CNT_NUM_1," hexmask.long.tbyte 0x3CC 0.--23. 1. "CNT_NUM_1,Counter for number of SUB_INC1 pulses; Number of pulses in continuous mode for a nominal increment in normal and emergency mode for SUB_INC1 given and updated by CPU only." line.long 0x3D0 "DPLL_CNT_NUM_2," hexmask.long.tbyte 0x3D0 0.--23. 1. "CNT_NUM_2,Counter for number of SUB_INC2 pulses; Number of pulses in continuous mode for a nominal increment in normal and emergency mode for SUB_INC2 given and updated by CPU only." line.long 0x3D4 "DPLL_PVT," hexmask.long.tbyte 0x3D4 0.--23. 1. "PVT,Plausibility value of next active TRIGGER slope." line.long 0x3D8 "DPLL_RAM1B_RSVD_6_0," hexmask.long.tbyte 0x3D8 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x3DC "DPLL_RAM1B_RSVD_6_1," hexmask.long.tbyte 0x3DC 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x3E0 "DPLL_RAM1B_RSVD_6_2," hexmask.long.tbyte 0x3E0 0.--23. 1. "RSVD,Reserved data word no DPLL internal use." line.long 0x3E4 "DPLL_PSTC," hexmask.long.tbyte 0x3E4 0.--23. 1. "PSTC,Calculated position stamp of last TRIGGER input;" line.long 0x3E8 "DPLL_PSSC," hexmask.long.tbyte 0x3E8 0.--23. 1. "PSSC,Calculated position stamp for the last STATE input;" line.long 0x3EC "DPLL_PSTM," hexmask.long.tbyte 0x3EC 0.--23. 1. "PSTM,Position stamp of TRIGGER measured; Measured position stamp of last active TRIGGER input." line.long 0x3F0 "DPLL_PSTM_OLD," hexmask.long.tbyte 0x3F0 0.--23. 1. "PSTM_OLD,Last but one position stamp of TRIGGER measured; Measured position stamp of last but one active TRIGGER input." line.long 0x3F4 "DPLL_PSSM," hexmask.long.tbyte 0x3F4 0.--23. 1. "PSSM,Position stamp of STATE measured; Measured position stamp of last active STATE input." line.long 0x3F8 "DPLL_PSSM_OLD," hexmask.long.tbyte 0x3F8 0.--23. 1. "PSSM_OLD,Last but one position stamp of STATE measured; Measured position stamp of last but one active STATE input." line.long 0x3FC "DPLL_NMB_T," hexmask.long.byte 0x3FC 16.--23. 1. "NOT_USED,Not used" newline hexmask.long.word 0x3FC 0.--15. 1. "NMB_T,Number of pulses for TRIGGER; Calculated number of pulses in normal mode for the current TRIGGER increment." line.long 0x400 "DPLL_NMB_S," hexmask.long.byte 0x400 20.--23. 1. "NOT_USED,Not used" newline hexmask.long.tbyte 0x400 0.--19. 1. "NMB_S,NMB_S: Number of pulses for STATE; Calculated number of pulses in emergency mode for the current STATE increment." line.long 0x404 "DPLL_RDT_S0," hexmask.long.tbyte 0x404 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x408 "DPLL_RDT_S1," hexmask.long.tbyte 0x408 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x40C "DPLL_RDT_S2," hexmask.long.tbyte 0x40C 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x410 "DPLL_RDT_S3," hexmask.long.tbyte 0x410 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x414 "DPLL_RDT_S4," hexmask.long.tbyte 0x414 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x418 "DPLL_RDT_S5," hexmask.long.tbyte 0x418 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x41C "DPLL_RDT_S6," hexmask.long.tbyte 0x41C 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x420 "DPLL_RDT_S7," hexmask.long.tbyte 0x420 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x424 "DPLL_RDT_S8," hexmask.long.tbyte 0x424 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x428 "DPLL_RDT_S9," hexmask.long.tbyte 0x428 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x42C "DPLL_RDT_S10," hexmask.long.tbyte 0x42C 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x430 "DPLL_RDT_S11," hexmask.long.tbyte 0x430 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x434 "DPLL_RDT_S12," hexmask.long.tbyte 0x434 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x438 "DPLL_RDT_S13," hexmask.long.tbyte 0x438 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x43C "DPLL_RDT_S14," hexmask.long.tbyte 0x43C 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x440 "DPLL_RDT_S15," hexmask.long.tbyte 0x440 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x444 "DPLL_RDT_S16," hexmask.long.tbyte 0x444 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x448 "DPLL_RDT_S17," hexmask.long.tbyte 0x448 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x44C "DPLL_RDT_S18," hexmask.long.tbyte 0x44C 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x450 "DPLL_RDT_S19," hexmask.long.tbyte 0x450 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x454 "DPLL_RDT_S20," hexmask.long.tbyte 0x454 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x458 "DPLL_RDT_S21," hexmask.long.tbyte 0x458 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x45C "DPLL_RDT_S22," hexmask.long.tbyte 0x45C 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x460 "DPLL_RDT_S23," hexmask.long.tbyte 0x460 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x464 "DPLL_RDT_S24," hexmask.long.tbyte 0x464 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x468 "DPLL_RDT_S25," hexmask.long.tbyte 0x468 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x46C "DPLL_RDT_S26," hexmask.long.tbyte 0x46C 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x470 "DPLL_RDT_S27," hexmask.long.tbyte 0x470 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x474 "DPLL_RDT_S28," hexmask.long.tbyte 0x474 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x478 "DPLL_RDT_S29," hexmask.long.tbyte 0x478 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x47C "DPLL_RDT_S30," hexmask.long.tbyte 0x47C 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x480 "DPLL_RDT_S31," hexmask.long.tbyte 0x480 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x484 "DPLL_RDT_S32," hexmask.long.tbyte 0x484 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x488 "DPLL_RDT_S33," hexmask.long.tbyte 0x488 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x48C "DPLL_RDT_S34," hexmask.long.tbyte 0x48C 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x490 "DPLL_RDT_S35," hexmask.long.tbyte 0x490 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x494 "DPLL_RDT_S36," hexmask.long.tbyte 0x494 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x498 "DPLL_RDT_S37," hexmask.long.tbyte 0x498 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x49C "DPLL_RDT_S38," hexmask.long.tbyte 0x49C 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4A0 "DPLL_RDT_S39," hexmask.long.tbyte 0x4A0 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4A4 "DPLL_RDT_S40," hexmask.long.tbyte 0x4A4 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4A8 "DPLL_RDT_S41," hexmask.long.tbyte 0x4A8 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4AC "DPLL_RDT_S42," hexmask.long.tbyte 0x4AC 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4B0 "DPLL_RDT_S43," hexmask.long.tbyte 0x4B0 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4B4 "DPLL_RDT_S44," hexmask.long.tbyte 0x4B4 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4B8 "DPLL_RDT_S45," hexmask.long.tbyte 0x4B8 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4BC "DPLL_RDT_S46," hexmask.long.tbyte 0x4BC 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4C0 "DPLL_RDT_S47," hexmask.long.tbyte 0x4C0 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4C4 "DPLL_RDT_S48," hexmask.long.tbyte 0x4C4 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4C8 "DPLL_RDT_S49," hexmask.long.tbyte 0x4C8 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4CC "DPLL_RDT_S50," hexmask.long.tbyte 0x4CC 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4D0 "DPLL_RDT_S51," hexmask.long.tbyte 0x4D0 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4D4 "DPLL_RDT_S52," hexmask.long.tbyte 0x4D4 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4D8 "DPLL_RDT_S53," hexmask.long.tbyte 0x4D8 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4DC "DPLL_RDT_S54," hexmask.long.tbyte 0x4DC 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4E0 "DPLL_RDT_S55," hexmask.long.tbyte 0x4E0 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4E4 "DPLL_RDT_S56," hexmask.long.tbyte 0x4E4 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4E8 "DPLL_RDT_S57," hexmask.long.tbyte 0x4E8 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4EC "DPLL_RDT_S58," hexmask.long.tbyte 0x4EC 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4F0 "DPLL_RDT_S59," hexmask.long.tbyte 0x4F0 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4F4 "DPLL_RDT_S60," hexmask.long.tbyte 0x4F4 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4F8 "DPLL_RDT_S61," hexmask.long.tbyte 0x4F8 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x4FC "DPLL_RDT_S62," hexmask.long.tbyte 0x4FC 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x500 "DPLL_RDT_S63," hexmask.long.tbyte 0x500 0.--23. 1. "RDT_S,Reciprocal difference time of STATE; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *232 while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated.." line.long 0x504 "DPLL_TSF_S0," hexmask.long.tbyte 0x504 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x508 "DPLL_TSF_S1," hexmask.long.tbyte 0x508 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x50C "DPLL_TSF_S2," hexmask.long.tbyte 0x50C 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x510 "DPLL_TSF_S3," hexmask.long.tbyte 0x510 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x514 "DPLL_TSF_S4," hexmask.long.tbyte 0x514 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x518 "DPLL_TSF_S5," hexmask.long.tbyte 0x518 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x51C "DPLL_TSF_S6," hexmask.long.tbyte 0x51C 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x520 "DPLL_TSF_S7," hexmask.long.tbyte 0x520 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x524 "DPLL_TSF_S8," hexmask.long.tbyte 0x524 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x528 "DPLL_TSF_S9," hexmask.long.tbyte 0x528 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x52C "DPLL_TSF_S10," hexmask.long.tbyte 0x52C 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x530 "DPLL_TSF_S11," hexmask.long.tbyte 0x530 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x534 "DPLL_TSF_S12," hexmask.long.tbyte 0x534 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x538 "DPLL_TSF_S13," hexmask.long.tbyte 0x538 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x53C "DPLL_TSF_S14," hexmask.long.tbyte 0x53C 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x540 "DPLL_TSF_S15," hexmask.long.tbyte 0x540 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x544 "DPLL_TSF_S16," hexmask.long.tbyte 0x544 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x548 "DPLL_TSF_S17," hexmask.long.tbyte 0x548 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x54C "DPLL_TSF_S18," hexmask.long.tbyte 0x54C 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x550 "DPLL_TSF_S19," hexmask.long.tbyte 0x550 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x554 "DPLL_TSF_S20," hexmask.long.tbyte 0x554 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x558 "DPLL_TSF_S21," hexmask.long.tbyte 0x558 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x55C "DPLL_TSF_S22," hexmask.long.tbyte 0x55C 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x560 "DPLL_TSF_S23," hexmask.long.tbyte 0x560 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x564 "DPLL_TSF_S24," hexmask.long.tbyte 0x564 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x568 "DPLL_TSF_S25," hexmask.long.tbyte 0x568 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x56C "DPLL_TSF_S26," hexmask.long.tbyte 0x56C 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x570 "DPLL_TSF_S27," hexmask.long.tbyte 0x570 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x574 "DPLL_TSF_S28," hexmask.long.tbyte 0x574 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x578 "DPLL_TSF_S29," hexmask.long.tbyte 0x578 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x57C "DPLL_TSF_S30," hexmask.long.tbyte 0x57C 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x580 "DPLL_TSF_S31," hexmask.long.tbyte 0x580 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x584 "DPLL_TSF_S32," hexmask.long.tbyte 0x584 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x588 "DPLL_TSF_S33," hexmask.long.tbyte 0x588 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x58C "DPLL_TSF_S34," hexmask.long.tbyte 0x58C 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x590 "DPLL_TSF_S35," hexmask.long.tbyte 0x590 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x594 "DPLL_TSF_S36," hexmask.long.tbyte 0x594 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x598 "DPLL_TSF_S37," hexmask.long.tbyte 0x598 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x59C "DPLL_TSF_S38," hexmask.long.tbyte 0x59C 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5A0 "DPLL_TSF_S39," hexmask.long.tbyte 0x5A0 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5A4 "DPLL_TSF_S40," hexmask.long.tbyte 0x5A4 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5A8 "DPLL_TSF_S41," hexmask.long.tbyte 0x5A8 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5AC "DPLL_TSF_S42," hexmask.long.tbyte 0x5AC 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5B0 "DPLL_TSF_S43," hexmask.long.tbyte 0x5B0 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5B4 "DPLL_TSF_S44," hexmask.long.tbyte 0x5B4 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5B8 "DPLL_TSF_S45," hexmask.long.tbyte 0x5B8 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5BC "DPLL_TSF_S46," hexmask.long.tbyte 0x5BC 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5C0 "DPLL_TSF_S47," hexmask.long.tbyte 0x5C0 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5C4 "DPLL_TSF_S48," hexmask.long.tbyte 0x5C4 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5C8 "DPLL_TSF_S49," hexmask.long.tbyte 0x5C8 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5CC "DPLL_TSF_S50," hexmask.long.tbyte 0x5CC 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5D0 "DPLL_TSF_S51," hexmask.long.tbyte 0x5D0 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5D4 "DPLL_TSF_S52," hexmask.long.tbyte 0x5D4 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5D8 "DPLL_TSF_S53," hexmask.long.tbyte 0x5D8 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5DC "DPLL_TSF_S54," hexmask.long.tbyte 0x5DC 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5E0 "DPLL_TSF_S55," hexmask.long.tbyte 0x5E0 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5E4 "DPLL_TSF_S56," hexmask.long.tbyte 0x5E4 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5E8 "DPLL_TSF_S57," hexmask.long.tbyte 0x5E8 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5EC "DPLL_TSF_S58," hexmask.long.tbyte 0x5EC 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5F0 "DPLL_TSF_S59," hexmask.long.tbyte 0x5F0 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5F4 "DPLL_TSF_S60," hexmask.long.tbyte 0x5F4 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5F8 "DPLL_TSF_S61," hexmask.long.tbyte 0x5F8 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x5FC "DPLL_TSF_S62," hexmask.long.tbyte 0x5FC 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x600 "DPLL_TSF_S63," hexmask.long.tbyte 0x600 0.--23. 1. "TSF_S,Time stamp field of STATE; Time stamp value of each active STATE event." line.long 0x604 "DPLL_ADT_S0," bitfld.long 0x604 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x604 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x604 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x608 "DPLL_ADT_S1," bitfld.long 0x608 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x608 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x608 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x60C "DPLL_ADT_S2," bitfld.long 0x60C 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x60C 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x60C 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x610 "DPLL_ADT_S3," bitfld.long 0x610 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x610 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x610 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x614 "DPLL_ADT_S4," bitfld.long 0x614 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x614 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x614 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x618 "DPLL_ADT_S5," bitfld.long 0x618 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x618 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x618 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x61C "DPLL_ADT_S6," bitfld.long 0x61C 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x61C 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x61C 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x620 "DPLL_ADT_S7," bitfld.long 0x620 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x620 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x620 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x624 "DPLL_ADT_S8," bitfld.long 0x624 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x624 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x624 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x628 "DPLL_ADT_S9," bitfld.long 0x628 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x628 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x628 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x62C "DPLL_ADT_S10," bitfld.long 0x62C 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x62C 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x62C 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x630 "DPLL_ADT_S11," bitfld.long 0x630 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x630 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x630 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x634 "DPLL_ADT_S12," bitfld.long 0x634 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x634 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x634 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x638 "DPLL_ADT_S13," bitfld.long 0x638 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x638 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x638 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x63C "DPLL_ADT_S14," bitfld.long 0x63C 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x63C 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x63C 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x640 "DPLL_ADT_S15," bitfld.long 0x640 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x640 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x640 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x644 "DPLL_ADT_S16," bitfld.long 0x644 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x644 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x644 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x648 "DPLL_ADT_S17," bitfld.long 0x648 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x648 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x648 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x64C "DPLL_ADT_S18," bitfld.long 0x64C 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x64C 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x64C 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x650 "DPLL_ADT_S19," bitfld.long 0x650 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x650 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x650 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x654 "DPLL_ADT_S20," bitfld.long 0x654 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x654 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x654 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x658 "DPLL_ADT_S21," bitfld.long 0x658 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x658 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x658 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x65C "DPLL_ADT_S22," bitfld.long 0x65C 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x65C 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x65C 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x660 "DPLL_ADT_S23," bitfld.long 0x660 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x660 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x660 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x664 "DPLL_ADT_S24," bitfld.long 0x664 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x664 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x664 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x668 "DPLL_ADT_S25," bitfld.long 0x668 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x668 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x668 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x66C "DPLL_ADT_S26," bitfld.long 0x66C 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x66C 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x66C 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x670 "DPLL_ADT_S27," bitfld.long 0x670 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x670 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x670 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x674 "DPLL_ADT_S28," bitfld.long 0x674 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x674 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x674 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x678 "DPLL_ADT_S29," bitfld.long 0x678 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x678 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x678 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x67C "DPLL_ADT_S30," bitfld.long 0x67C 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x67C 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x67C 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x680 "DPLL_ADT_S31," bitfld.long 0x680 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x680 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x680 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x684 "DPLL_ADT_S32," bitfld.long 0x684 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x684 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x684 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x688 "DPLL_ADT_S33," bitfld.long 0x688 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x688 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x688 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x68C "DPLL_ADT_S34," bitfld.long 0x68C 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x68C 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x68C 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x690 "DPLL_ADT_S35," bitfld.long 0x690 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x690 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x690 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x694 "DPLL_ADT_S36," bitfld.long 0x694 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x694 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x694 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x698 "DPLL_ADT_S37," bitfld.long 0x698 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x698 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x698 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x69C "DPLL_ADT_S38," bitfld.long 0x69C 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x69C 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x69C 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6A0 "DPLL_ADT_S39," bitfld.long 0x6A0 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6A0 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6A0 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6A4 "DPLL_ADT_S40," bitfld.long 0x6A4 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6A4 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6A4 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6A8 "DPLL_ADT_S41," bitfld.long 0x6A8 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6A8 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6A8 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6AC "DPLL_ADT_S42," bitfld.long 0x6AC 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6AC 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6AC 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6B0 "DPLL_ADT_S43," bitfld.long 0x6B0 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6B0 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6B0 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6B4 "DPLL_ADT_S44," bitfld.long 0x6B4 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6B4 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6B4 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6B8 "DPLL_ADT_S45," bitfld.long 0x6B8 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6B8 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6B8 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6BC "DPLL_ADT_S46," bitfld.long 0x6BC 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6BC 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6BC 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6C0 "DPLL_ADT_S47," bitfld.long 0x6C0 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6C0 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6C0 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6C4 "DPLL_ADT_S48," bitfld.long 0x6C4 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6C4 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6C4 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6C8 "DPLL_ADT_S49," bitfld.long 0x6C8 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6C8 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6C8 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6CC "DPLL_ADT_S50," bitfld.long 0x6CC 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6CC 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6CC 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6D0 "DPLL_ADT_S51," bitfld.long 0x6D0 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6D0 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6D0 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6D4 "DPLL_ADT_S52," bitfld.long 0x6D4 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6D4 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6D4 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6D8 "DPLL_ADT_S53," bitfld.long 0x6D8 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6D8 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6D8 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6DC "DPLL_ADT_S54," bitfld.long 0x6DC 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6DC 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6DC 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6E0 "DPLL_ADT_S55," bitfld.long 0x6E0 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6E0 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6E0 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6E4 "DPLL_ADT_S56," bitfld.long 0x6E4 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6E4 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6E4 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6E8 "DPLL_ADT_S57," bitfld.long 0x6E8 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6E8 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6E8 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6EC "DPLL_ADT_S58," bitfld.long 0x6EC 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6EC 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6EC 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6F0 "DPLL_ADT_S59," bitfld.long 0x6F0 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6F0 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6F0 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6F4 "DPLL_ADT_S60," bitfld.long 0x6F4 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6F4 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6F4 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6F8 "DPLL_ADT_S61," bitfld.long 0x6F8 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6F8 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6F8 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x6FC "DPLL_ADT_S62," bitfld.long 0x6FC 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x6FC 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x6FC 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x700 "DPLL_ADT_S63," bitfld.long 0x700 22.--23. "NOT_USED,Not used" "0,1,2,3" newline hexmask.long.byte 0x700 16.--21. 1. "NS,Number of STATEs; number of nominal STATE parts in the corresponding increment." newline hexmask.long.word 0x700 0.--15. 1. "PD_S,Physical deviation of STATE; Adapt values for each nominal STATE increment in FULL_SCALE (sint16);" line.long 0x704 "DPLL_DT_S0," hexmask.long.tbyte 0x704 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x708 "DPLL_DT_S1," hexmask.long.tbyte 0x708 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x70C "DPLL_DT_S2," hexmask.long.tbyte 0x70C 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x710 "DPLL_DT_S3," hexmask.long.tbyte 0x710 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x714 "DPLL_DT_S4," hexmask.long.tbyte 0x714 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x718 "DPLL_DT_S5," hexmask.long.tbyte 0x718 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x71C "DPLL_DT_S6," hexmask.long.tbyte 0x71C 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x720 "DPLL_DT_S7," hexmask.long.tbyte 0x720 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x724 "DPLL_DT_S8," hexmask.long.tbyte 0x724 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x728 "DPLL_DT_S9," hexmask.long.tbyte 0x728 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x72C "DPLL_DT_S10," hexmask.long.tbyte 0x72C 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x730 "DPLL_DT_S11," hexmask.long.tbyte 0x730 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x734 "DPLL_DT_S12," hexmask.long.tbyte 0x734 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x738 "DPLL_DT_S13," hexmask.long.tbyte 0x738 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x73C "DPLL_DT_S14," hexmask.long.tbyte 0x73C 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x740 "DPLL_DT_S15," hexmask.long.tbyte 0x740 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x744 "DPLL_DT_S16," hexmask.long.tbyte 0x744 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x748 "DPLL_DT_S17," hexmask.long.tbyte 0x748 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x74C "DPLL_DT_S18," hexmask.long.tbyte 0x74C 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x750 "DPLL_DT_S19," hexmask.long.tbyte 0x750 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x754 "DPLL_DT_S20," hexmask.long.tbyte 0x754 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x758 "DPLL_DT_S21," hexmask.long.tbyte 0x758 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x75C "DPLL_DT_S22," hexmask.long.tbyte 0x75C 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x760 "DPLL_DT_S23," hexmask.long.tbyte 0x760 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x764 "DPLL_DT_S24," hexmask.long.tbyte 0x764 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x768 "DPLL_DT_S25," hexmask.long.tbyte 0x768 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x76C "DPLL_DT_S26," hexmask.long.tbyte 0x76C 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x770 "DPLL_DT_S27," hexmask.long.tbyte 0x770 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x774 "DPLL_DT_S28," hexmask.long.tbyte 0x774 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x778 "DPLL_DT_S29," hexmask.long.tbyte 0x778 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x77C "DPLL_DT_S30," hexmask.long.tbyte 0x77C 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x780 "DPLL_DT_S31," hexmask.long.tbyte 0x780 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x784 "DPLL_DT_S32," hexmask.long.tbyte 0x784 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x788 "DPLL_DT_S33," hexmask.long.tbyte 0x788 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x78C "DPLL_DT_S34," hexmask.long.tbyte 0x78C 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x790 "DPLL_DT_S35," hexmask.long.tbyte 0x790 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x794 "DPLL_DT_S36," hexmask.long.tbyte 0x794 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x798 "DPLL_DT_S37," hexmask.long.tbyte 0x798 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x79C "DPLL_DT_S38," hexmask.long.tbyte 0x79C 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7A0 "DPLL_DT_S39," hexmask.long.tbyte 0x7A0 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7A4 "DPLL_DT_S40," hexmask.long.tbyte 0x7A4 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7A8 "DPLL_DT_S41," hexmask.long.tbyte 0x7A8 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7AC "DPLL_DT_S42," hexmask.long.tbyte 0x7AC 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7B0 "DPLL_DT_S43," hexmask.long.tbyte 0x7B0 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7B4 "DPLL_DT_S44," hexmask.long.tbyte 0x7B4 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7B8 "DPLL_DT_S45," hexmask.long.tbyte 0x7B8 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7BC "DPLL_DT_S46," hexmask.long.tbyte 0x7BC 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7C0 "DPLL_DT_S47," hexmask.long.tbyte 0x7C0 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7C4 "DPLL_DT_S48," hexmask.long.tbyte 0x7C4 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7C8 "DPLL_DT_S49," hexmask.long.tbyte 0x7C8 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7CC "DPLL_DT_S50," hexmask.long.tbyte 0x7CC 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7D0 "DPLL_DT_S51," hexmask.long.tbyte 0x7D0 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7D4 "DPLL_DT_S52," hexmask.long.tbyte 0x7D4 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7D8 "DPLL_DT_S53," hexmask.long.tbyte 0x7D8 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7DC "DPLL_DT_S54," hexmask.long.tbyte 0x7DC 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7E0 "DPLL_DT_S55," hexmask.long.tbyte 0x7E0 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7E4 "DPLL_DT_S56," hexmask.long.tbyte 0x7E4 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7E8 "DPLL_DT_S57," hexmask.long.tbyte 0x7E8 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7EC "DPLL_DT_S58," hexmask.long.tbyte 0x7EC 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7F0 "DPLL_DT_S59," hexmask.long.tbyte 0x7F0 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7F4 "DPLL_DT_S60," hexmask.long.tbyte 0x7F4 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7F8 "DPLL_DT_S61," hexmask.long.tbyte 0x7F8 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x7FC "DPLL_DT_S62," hexmask.long.tbyte 0x7FC 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." line.long 0x800 "DPLL_DT_S63," hexmask.long.tbyte 0x800 0.--23. 1. "DT_S,Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap)." group.long 0x8E00++0x18B line.long 0x0 "DPLL_TSAC0," hexmask.long.tbyte 0x0 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x4 "DPLL_TSAC1," hexmask.long.tbyte 0x4 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x8 "DPLL_TSAC2," hexmask.long.tbyte 0x8 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0xC "DPLL_TSAC3," hexmask.long.tbyte 0xC 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x10 "DPLL_TSAC4," hexmask.long.tbyte 0x10 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x14 "DPLL_TSAC5," hexmask.long.tbyte 0x14 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x18 "DPLL_TSAC6," hexmask.long.tbyte 0x18 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x1C "DPLL_TSAC7," hexmask.long.tbyte 0x1C 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x20 "DPLL_TSAC8," hexmask.long.tbyte 0x20 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x24 "DPLL_TSAC9," hexmask.long.tbyte 0x24 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x28 "DPLL_TSAC10," hexmask.long.tbyte 0x28 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x2C "DPLL_TSAC11," hexmask.long.tbyte 0x2C 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x30 "DPLL_TSAC12," hexmask.long.tbyte 0x30 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x34 "DPLL_TSAC13," hexmask.long.tbyte 0x34 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x38 "DPLL_TSAC14," hexmask.long.tbyte 0x38 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x3C "DPLL_TSAC15," hexmask.long.tbyte 0x3C 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x40 "DPLL_TSAC16," hexmask.long.tbyte 0x40 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x44 "DPLL_TSAC17," hexmask.long.tbyte 0x44 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x48 "DPLL_TSAC18," hexmask.long.tbyte 0x48 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x4C "DPLL_TSAC19," hexmask.long.tbyte 0x4C 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x50 "DPLL_TSAC20," hexmask.long.tbyte 0x50 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x54 "DPLL_TSAC21," hexmask.long.tbyte 0x54 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x58 "DPLL_TSAC22," hexmask.long.tbyte 0x58 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x5C "DPLL_TSAC23," hexmask.long.tbyte 0x5C 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x60 "DPLL_TSAC24," hexmask.long.tbyte 0x60 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x64 "DPLL_TSAC25," hexmask.long.tbyte 0x64 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x68 "DPLL_TSAC26," hexmask.long.tbyte 0x68 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x6C "DPLL_TSAC27," hexmask.long.tbyte 0x6C 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x70 "DPLL_TSAC28," hexmask.long.tbyte 0x70 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x74 "DPLL_TSAC29," hexmask.long.tbyte 0x74 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x78 "DPLL_TSAC30," hexmask.long.tbyte 0x78 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x7C "DPLL_TSAC31," hexmask.long.tbyte 0x7C 0.--23. 1. "TSAC,Calculated time stamp for ACTION n (n = 0...NOAC-1)" line.long 0x80 "DPLL_PSAC0," hexmask.long.tbyte 0x80 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0x84 "DPLL_PSAC1," hexmask.long.tbyte 0x84 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0x88 "DPLL_PSAC2," hexmask.long.tbyte 0x88 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0x8C "DPLL_PSAC3," hexmask.long.tbyte 0x8C 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0x90 "DPLL_PSAC4," hexmask.long.tbyte 0x90 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0x94 "DPLL_PSAC5," hexmask.long.tbyte 0x94 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0x98 "DPLL_PSAC6," hexmask.long.tbyte 0x98 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0x9C "DPLL_PSAC7," hexmask.long.tbyte 0x9C 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xA0 "DPLL_PSAC8," hexmask.long.tbyte 0xA0 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xA4 "DPLL_PSAC9," hexmask.long.tbyte 0xA4 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xA8 "DPLL_PSAC10," hexmask.long.tbyte 0xA8 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xAC "DPLL_PSAC11," hexmask.long.tbyte 0xAC 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xB0 "DPLL_PSAC12," hexmask.long.tbyte 0xB0 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xB4 "DPLL_PSAC13," hexmask.long.tbyte 0xB4 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xB8 "DPLL_PSAC14," hexmask.long.tbyte 0xB8 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xBC "DPLL_PSAC15," hexmask.long.tbyte 0xBC 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xC0 "DPLL_PSAC16," hexmask.long.tbyte 0xC0 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xC4 "DPLL_PSAC17," hexmask.long.tbyte 0xC4 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xC8 "DPLL_PSAC18," hexmask.long.tbyte 0xC8 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xCC "DPLL_PSAC19," hexmask.long.tbyte 0xCC 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xD0 "DPLL_PSAC20," hexmask.long.tbyte 0xD0 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xD4 "DPLL_PSAC21," hexmask.long.tbyte 0xD4 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xD8 "DPLL_PSAC22," hexmask.long.tbyte 0xD8 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xDC "DPLL_PSAC23," hexmask.long.tbyte 0xDC 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xE0 "DPLL_PSAC24," hexmask.long.tbyte 0xE0 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xE4 "DPLL_PSAC25," hexmask.long.tbyte 0xE4 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xE8 "DPLL_PSAC26," hexmask.long.tbyte 0xE8 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xEC "DPLL_PSAC27," hexmask.long.tbyte 0xEC 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xF0 "DPLL_PSAC28," hexmask.long.tbyte 0xF0 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xF4 "DPLL_PSAC29," hexmask.long.tbyte 0xF4 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xF8 "DPLL_PSAC30," hexmask.long.tbyte 0xF8 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0xFC "DPLL_PSAC31," hexmask.long.tbyte 0xFC 0.--23. 1. "PSAC,Calculated position value for the start of ACTION n." line.long 0x100 "DPLL_ACB_0," hexmask.long.byte 0x100 24.--28. 1. "ACB_3,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x100 16.--20. 1. "ACB_2,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x100 8.--12. 1. "ACB_1,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x100 0.--4. 1. "ACB_0,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" line.long 0x104 "DPLL_ACB_1," hexmask.long.byte 0x104 24.--28. 1. "ACB_3,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x104 16.--20. 1. "ACB_2,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x104 8.--12. 1. "ACB_1,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x104 0.--4. 1. "ACB_0,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" line.long 0x108 "DPLL_ACB_2," hexmask.long.byte 0x108 24.--28. 1. "ACB_3,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x108 16.--20. 1. "ACB_2,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x108 8.--12. 1. "ACB_1,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x108 0.--4. 1. "ACB_0,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" line.long 0x10C "DPLL_ACB_3," hexmask.long.byte 0x10C 24.--28. 1. "ACB_3,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x10C 16.--20. 1. "ACB_2,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x10C 8.--12. 1. "ACB_1,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x10C 0.--4. 1. "ACB_0,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" line.long 0x110 "DPLL_ACB_4," hexmask.long.byte 0x110 24.--28. 1. "ACB_3,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x110 16.--20. 1. "ACB_2,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x110 8.--12. 1. "ACB_1,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x110 0.--4. 1. "ACB_0,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" line.long 0x114 "DPLL_ACB_5," hexmask.long.byte 0x114 24.--28. 1. "ACB_3,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x114 16.--20. 1. "ACB_2,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x114 8.--12. 1. "ACB_1,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x114 0.--4. 1. "ACB_0,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" line.long 0x118 "DPLL_ACB_6," hexmask.long.byte 0x118 24.--28. 1. "ACB_3,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x118 16.--20. 1. "ACB_2,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x118 8.--12. 1. "ACB_1,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x118 0.--4. 1. "ACB_0,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" line.long 0x11C "DPLL_ACB_7," hexmask.long.byte 0x11C 24.--28. 1. "ACB_3,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x11C 16.--20. 1. "ACB_2,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x11C 8.--12. 1. "ACB_1,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" newline hexmask.long.byte 0x11C 0.--4. 1. "ACB_0,Action Control Bits of ACTION_m reflects ACT_D[m](52:48) m=4*n" line.long 0x120 "DPLL_CTRL_11," bitfld.long 0x120 31. "WACBU,Write enable for ACB use; the ACB values of PMTR are used to decide if an action is in the past" "0,1" newline bitfld.long 0x120 30. "WSTATE_EXT,Write enable of DPLL_CTRL_11.STATE_EXT" "0,1" newline bitfld.long 0x120 29. "WPCMF2_INCCNT_B,Write enable of DPLL_CTRL_11.PCMF2_INCCNT_B" "0,1" newline bitfld.long 0x120 28. "WINCF2,Write enable for DPLL_INC_CNT2.INC_CNT2 fast" "0,1" newline bitfld.long 0x120 27. "WFSYL2,Write enable for Force Synchronization Loss 2." "0,1" newline bitfld.long 0x120 26. "WPCMF2,Write enable for pulse correction mode fast 2" "0,1" newline bitfld.long 0x120 25. "WERZ2,Write enable for error zero 2." "0,1" newline bitfld.long 0x120 24. "WSIP2,Write enable for simplified increment prediction 2." "0,1" newline bitfld.long 0x120 23. "WADS,Write enable of DPLL_CTRL_11.ADS" "0,1" newline bitfld.long 0x120 22. "WADT,Write enable of DPLL_CTRL_11.ADT" "0,1" newline bitfld.long 0x120 21. "WPCMF1_INCCNT_B,Write enable of DPLL_CTRL_11.PCMF1_INCCNT_B" "0,1" newline bitfld.long 0x120 20. "WINCF1,Write enable for DPLL_INC_CNT1.INC_CNT1 fast" "0,1" newline bitfld.long 0x120 19. "WFSYL1,Write enable for Force Synchronization Loss 1." "0,1" newline bitfld.long 0x120 18. "WPCMF1,Write enable for pulse correction mode fast 1" "0,1" newline bitfld.long 0x120 17. "WERZ1,Write enable for error zero 1." "0,1" newline bitfld.long 0x120 16. "WSIP1,Write enable for simplified increment prediction 1." "0,1" newline bitfld.long 0x120 15. "ACBU,ACB use; the ACB values of PMTR are used to decide if an action is in the past" "0,1" newline bitfld.long 0x120 14. "STATE_EXT,Use of STATE engine extension" "0,1" newline bitfld.long 0x120 13. "PCMF2_INCCNT_B,No increment of DPLL_INC_CNT2.INC_CNT2 when DPLL_CTRL_11.PCMF2 active (automatic end mode)." "0,1" newline bitfld.long 0x120 12. "INCF2,DPLL_INC_CNT2.INC_CNT2 fast" "0,1" newline bitfld.long 0x120 11. "FSYL2,Force Synchronization Loss of DPLL_STATUS.LOCK2." "0,1" newline bitfld.long 0x120 10. "PCMF2,Pulse correction mode fast for DPLL_INC_CNT2.INC_CNT2" "0,1" newline bitfld.long 0x120 9. "ERZ2,Error is assumed as zero in emergency mode and for the second engine for DPLL_CTRL_1.SMC=1." "0,1" newline bitfld.long 0x120 8. "SIP2,Simplified increment prediction in emergency mode and for the second engine in the case DPLL_CTRL_0.RMO=1." "0,1" newline bitfld.long 0x120 7. "ADS,Correction of DT_S_ACTUAL CDT_SX_nom_corr by PD_S" "0,1" newline bitfld.long 0x120 6. "ADT,Correction of DT_T_ACTUAL CDT_TX_nom_corr by PD_T" "0,1" newline bitfld.long 0x120 5. "PCMF1_INCCNT_B,No increment of DPLL_INC_CNT1.INC_CNT1 when DPLL_CTRL_11.PCMF1 active (automatic end mode)." "0,1" newline bitfld.long 0x120 4. "INCF1,DPLL_INC_CNT1.INC_CNT1 fast correction" "0,1" newline bitfld.long 0x120 3. "FSYL1,Force Synchronization Loss of DPLL_STATUS.LOCK1." "0,1" newline bitfld.long 0x120 2. "PCMF1,Pulse correction mode fast for DPLL_INC_CNT1.INC_CNT1" "0,1" newline bitfld.long 0x120 1. "ERZ1,Error is assumed as zero in normal mode and for the first engine for DPLL_CTRL_1.SMC=1." "0,1" newline bitfld.long 0x120 0. "SIP1,Simplified increment prediction in normal mode and for the first engine in the case DPLL_CTRL_1.SMC=1." "0,1" line.long 0x124 "DPLL_THVAL2," hexmask.long.tbyte 0x124 0.--23. 1. "THVAL,Measured last pulse time from active to inactive slope of TRIGGER after correction of input slope filter delays" line.long 0x128 "DPLL_TIDEL," hexmask.long.tbyte 0x128 0.--23. 1. "TIDEL,TRIGGER input delay" line.long 0x12C "DPLL_SIDEL," hexmask.long.tbyte 0x12C 0.--23. 1. "SIDEL,STATE input delay" line.long 0x130 "DPLL_APS_SYNC_EXT," hexmask.long.byte 0x130 16.--22. 1. "APS_1C2_OLD,Address pointer STATE for RAM region 1c2 at synchronization time; this value is set by the current DPLL_APS_EXT.APS_1C2 value when the synchronization takes place for the first active STATE event after writing DPLL_APS_1C3_EXT.APS_1C3 but.." newline bitfld.long 0x130 15. "APS_1C2_STATUS,Address pointer 1c2 status; set by CPU before the synchronization is performed. The value is cleared automatically when the DPLL_APS_SYNC_EXT.APS_1C2_OLD value is written." "0,1" newline hexmask.long.byte 0x130 0.--6. 1. "APS_1C2_EXT,Address pointer 1c2 extension; this offset value determines by which value the DPLL_APS_EXT.APS_1C2 is changed at the synchronization time; set by CPU before the synchronization is performed." line.long 0x134 "DPLL_CTRL_EXT," hexmask.long.byte 0x134 16.--21. 1. "SYN_NS,Synchronization number of STATE; summarized number of virtual increments in HALF_SCALE" newline hexmask.long.byte 0x134 0.--5. 1. "SNU,STATE number; SNU+1 is number of nominal STATE events in HALF_SCALE (1...32)." line.long 0x138 "DPLL_APS_EXT," hexmask.long.byte 0x138 14.--20. 1. "APS_1C2,Address pointer STATE for RAM region 1c2; Actual RAM pointer address value for TSF_S[p]." newline bitfld.long 0x138 13. "WAPS_1C2,Write bit for address pointer DPLL_APS_EXT.APS_1C2 read as zero." "0,1" newline hexmask.long.byte 0x138 2.--8. 1. "APS,Address pointer STATE; Actual RAM pointer address value for DT_S[p] and RDT_S[p]" newline bitfld.long 0x138 1. "WAPS,Write bit for address pointer DPLL_APS_EXT.APS read as zero." "0,1" line.long 0x13C "DPLL_APS_1C3_EXT," hexmask.long.byte 0x13C 2.--8. 1. "APS_1C3,Address pointer STATE for RAM region 1c3; Actual RAM pointer address value for ADT_S[p]" line.long 0x140 "DPLL_STA," bitfld.long 0x140 21.--23. "CNT_S,Count STATE; this reflects the count of active STATE slopes (mod8)." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x140 12.--19. 1. "STA_S,Status of STATE state machine; state binary coded" newline bitfld.long 0x140 9.--11. "CNT_T,Count TRIGGER; this reflects the count of active TRIGGER slopes (mod8)." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x140 0.--7. 1. "STA_T,Status of TRIGGER state machine; state binary coded" line.long 0x144 "DPLL_INCF1_OFFSET," hexmask.long.tbyte 0x144 0.--23. 1. "DPLL_INCF1_OFFSET,Start value of the ADD_IN_ADDER1" line.long 0x148 "DPLL_INCF2_OFFSET," hexmask.long.tbyte 0x148 0.--23. 1. "DPLL_INCF2_OFFSET,Start value of the ADD_IN_ADDER2" line.long 0x14C "DPLL_DT_T_START," hexmask.long.tbyte 0x14C 0.--23. 1. "DPLL_DT_T_START,Start value of DPLL_DT_T_ACT for the first increment after DPLL_CTRL_11.SIP1 is set to 1" line.long 0x150 "DPLL_DT_S_START," hexmask.long.tbyte 0x150 0.--23. 1. "DPLL_DT_S_START,Start value of DPLL_DT_S_ACT for the first increment after DPLL_CTRL_11.SIP2 is set to 1" line.long 0x154 "DPLL_STA_MASK," hexmask.long.byte 0x154 8.--15. 1. "STA_NOTIFY_S,Notify value for STA_S of register DPLL_STA." newline hexmask.long.byte 0x154 0.--7. 1. "STA_NOTIFY_T,Notify value for DPLL_STA.STA_T." line.long 0x158 "DPLL_STA_FLAG," bitfld.long 0x158 10. "INC_CNT2_FLAG,Flag according to DPLL_INC_CNT2_MASK.INC_CNT2_NOTIFY" "0,1" newline bitfld.long 0x158 9. "INC_CNT1_FLAG,Flag according to DPLL_INC_CNT1_MASK.INC_CNT1_NOTIFY" "0,1" newline bitfld.long 0x158 8. "STA_FLAG_S,Flag according to DPLL_STA_MASK.STA_NOTIFY_S" "0,1" newline bitfld.long 0x158 0. "STA_FLAG_T,Flag according to DPLL_MASK.STA_NOTIFY_T" "0,1" line.long 0x15C "DPLL_INC_CNT1_MASK," hexmask.long.tbyte 0x15C 0.--23. 1. "INC_CNT1_NOTIFY,Notify value for DPLL_INC_CNT1.INC_CNT1 of register DPLL_INC_CNT1." line.long 0x160 "DPLL_INC_CNT2_MASK," hexmask.long.tbyte 0x160 0.--23. 1. "INC_CNT2_NOTIFY,Notify value for DPLL_INC_CNT2.INC_CNT2 of register DPLL_INC_CNT2." line.long 0x164 "DPLL_NUSC_EXT1," bitfld.long 0x164 30. "WSYN,Write control bit for DPLL_NUSC_EXT1.SYN_S and DPLL_NUSC_EXT1.SYN_S_OLD; read as zero." "0,1" newline hexmask.long.byte 0x164 16.--22. 1. "SYN_S_OLD,Number of real and virtual events to be considered for the last increment." newline hexmask.long.byte 0x164 0.--6. 1. "SYN_S,Number of real and virtual events to be considered for the current increment." line.long 0x168 "DPLL_NUSC_EXT2," bitfld.long 0x168 31. "WVSN,Write control bit for DPLL_NUSC_EXT2.VSN; read as zero." "0,1" newline bitfld.long 0x168 29. "WNUS,Write control bit for DPLL_NUSC_EXT2.NUSE; read as zero." "0,1" newline hexmask.long.byte 0x168 16.--22. 1. "VSN,Virtual STATE number; number of virtual state increments in the current DPLL_NUSC_EXT2.NUSE region." newline bitfld.long 0x168 15. "FSS,FULL_SCALE of STATE; this value is to be set when DPLL_NUSC_EXT2.NUSE is set to FULL_SCALE" "0,1" newline hexmask.long.byte 0x168 0.--6. 1. "NUSE,Number of recent STATE events used for SUB_INCx calculations modulo 2*(SNUmax+1)." line.long 0x16C "DPLL_CTN_MIN," hexmask.long.tbyte 0x16C 0.--23. 1. "CTN_MIN,CDT_T_NOM min value" line.long 0x170 "DPLL_CTN_MAX," hexmask.long.tbyte 0x170 0.--23. 1. "CTN_MAX,CDT_T_NOM max value" line.long 0x174 "DPLL_CSN_MIN," hexmask.long.tbyte 0x174 0.--23. 1. "CSN_MIN,CDT_S_NOM min value" line.long 0x178 "DPLL_CSN_MAX," hexmask.long.tbyte 0x178 0.--23. 1. "CSN_MAX,CDT_S_NOM max value" line.long 0x17C "DPLL_SW_TRIG," bitfld.long 0x17C 7. "WSTATE_LEVEL,Write enable for DPLL_SW_TRIG.STATE_LEVEL" "0,1" newline bitfld.long 0x17C 6. "STATE_LEVEL,Input signal level of software triggered input event for STATE" "0,1" newline bitfld.long 0x17C 5. "WSTATE_EVENT,Write enable for DPLL_SW_TRIG.STATE_EVENT" "0,1" newline bitfld.long 0x17C 4. "STATE_EVENT,Software triggered input event for STATE" "0,1" newline bitfld.long 0x17C 3. "WTRIG_LEVEL,Write enable for DPLL_SW_TRIG.TRIG_LEVEL" "0,1" newline bitfld.long 0x17C 2. "TRIG_LEVEL,Input signal level of software triggered input event for TRIGGER" "0,1" newline bitfld.long 0x17C 1. "WTRIG_EVENT,Write enable for DPLL_SW_TRIG.TRIG_EVENT" "0,1" newline bitfld.long 0x17C 0. "TRIG_EVENT,Software triggered input event for TRIGGER" "0,1" line.long 0x180 "DPLL_MP_T," hexmask.long.tbyte 0x180 0.--23. 1. "MP_T,Number of missing pulses of the SUB_INC1 pulses in automatic end mode (DPLL_CTRL_1.DMO=0)." line.long 0x184 "DPLL_MP_S," hexmask.long.tbyte 0x184 0.--23. 1. "MP_S,Number of missing pulses of the SUB_INC1/2 pulses in automatic end mode (DPLL_CTRL_1.DMO=0)." line.long 0x188 "DPLL_CTRL_12," bitfld.long 0x188 16. "WSUBINC_MUX_SEL,Write enable for DPLL_CTRL_12.SUBINC_MUX_SEL." "0,1" newline bitfld.long 0x188 0. "SUBINC_MUX_SEL,Selction of DPLL sub increment source for TBU_TS1 angle base." "0,1" repeat 4096. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC000)++0x3 line.long 0x0 "DPLL_RR2[$1]," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data" repeat.end repeat 16384. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10000)++0x3 line.long 0x0 "MCS0_MEM[$1]," hexmask.long 0x0 0.--31. 1. "DATA,MCS memory location." repeat.end tree.end tree "GTM_CLS1" base ad:0x74020000 group.long 0x680++0x33 line.long 0x0 "MON_STATUS," bitfld.long 0x0 29. "MCS9_ERR,Error detected at MCS[j]" "0,1" newline bitfld.long 0x0 28. "MCS8_ERR,Error detected at MCS[j]" "0,1" newline bitfld.long 0x0 27. "MCS7_ERR,Error detected at MCS[j]" "0,1" newline bitfld.long 0x0 26. "MCS6_ERR,Error detected at MCS[j]" "0,1" newline bitfld.long 0x0 25. "MCS5_ERR,Error detected at MCS[j]" "0,1" newline bitfld.long 0x0 24. "MCS4_ERR,Error detected at MCS[j]" "0,1" newline bitfld.long 0x0 23. "MCS3_ERR,Error detected at MCS[j]" "0,1" newline bitfld.long 0x0 22. "MCS2_ERR,Error detected at MCS[j]" "0,1" newline bitfld.long 0x0 21. "MCS1_ERR,Error detected at MCS[j]" "0,1" newline bitfld.long 0x0 20. "MCS0_ERR,Error detected at MCS[j]" "0,1" newline bitfld.long 0x0 16. "CMP_ERR,Error detected at CMP" "0,1" newline bitfld.long 0x0 14. "ACT_CMU8,CMU_CLK8 activity" "0,1" newline bitfld.long 0x0 12. "ACT_CMUFX4,CMU_CLKFX[y] activity" "0,1" newline bitfld.long 0x0 11. "ACT_CMUFX3,CMU_CLKFX[y] activity" "0,1" newline bitfld.long 0x0 10. "ACT_CMUFX2,CMU_CLKFX[y] activity" "0,1" newline bitfld.long 0x0 9. "ACT_CMUFX1,CMU_CLKFX[y] activity" "0,1" newline bitfld.long 0x0 8. "ACT_CMUFX0,CMU_CLKFX[y] activity" "0,1" newline bitfld.long 0x0 7. "ACT_CMU7,CMU_CLK[x] activity" "0,1" newline bitfld.long 0x0 6. "ACT_CMU6,CMU_CLK[x] activity" "0,1" newline bitfld.long 0x0 5. "ACT_CMU5,CMU_CLK[x] activity" "0,1" newline bitfld.long 0x0 4. "ACT_CMU4,CMU_CLK[x] activity" "0,1" newline bitfld.long 0x0 3. "ACT_CMU3,CMU_CLK[x] activity" "0,1" newline bitfld.long 0x0 2. "ACT_CMU2,CMU_CLK[x] activity" "0,1" newline bitfld.long 0x0 1. "ACT_CMU1,CMU_CLK[x] activity" "0,1" newline bitfld.long 0x0 0. "ACT_CMU0,CMU_CLK[x] activity" "0,1" line.long 0x4 "MON_ACTIVITY_0," bitfld.long 0x4 31. "MCA_3_7,Activity of check performed in module MCS3 at channel x" "0,1" newline bitfld.long 0x4 30. "MCA_3_6,Activity of check performed in module MCS3 at channel x" "0,1" newline bitfld.long 0x4 29. "MCA_3_5,Activity of check performed in module MCS3 at channel x" "0,1" newline bitfld.long 0x4 28. "MCA_3_4,Activity of check performed in module MCS3 at channel x" "0,1" newline bitfld.long 0x4 27. "MCA_3_3,Activity of check performed in module MCS3 at channel x" "0,1" newline bitfld.long 0x4 26. "MCA_3_2,Activity of check performed in module MCS3 at channel x" "0,1" newline bitfld.long 0x4 25. "MCA_3_1,Activity of check performed in module MCS3 at channel x" "0,1" newline bitfld.long 0x4 24. "MCA_3_0,Activity of check performed in module MCS3 at channel x" "0,1" newline bitfld.long 0x4 23. "MCA_2_7,Activity of check performed in module MCS2 at channel x" "0,1" newline bitfld.long 0x4 22. "MCA_2_6,Activity of check performed in module MCS2 at channel x" "0,1" newline bitfld.long 0x4 21. "MCA_2_5,Activity of check performed in module MCS2 at channel x" "0,1" newline bitfld.long 0x4 20. "MCA_2_4,Activity of check performed in module MCS2 at channel x" "0,1" newline bitfld.long 0x4 19. "MCA_2_3,Activity of check performed in module MCS2 at channel x" "0,1" newline bitfld.long 0x4 18. "MCA_2_2,Activity of check performed in module MCS2 at channel x" "0,1" newline bitfld.long 0x4 17. "MCA_2_1,Activity of check performed in module MCS2 at channel x" "0,1" newline bitfld.long 0x4 16. "MCA_2_0,Activity of check performed in module MCS2 at channel x" "0,1" newline bitfld.long 0x4 15. "MCA_1_7,Activity of check performed in module MCS1 at channel x" "0,1" newline bitfld.long 0x4 14. "MCA_1_6,Activity of check performed in module MCS1 at channel x" "0,1" newline bitfld.long 0x4 13. "MCA_1_5,Activity of check performed in module MCS1 at channel x" "0,1" newline bitfld.long 0x4 12. "MCA_1_4,Activity of check performed in module MCS1 at channel x" "0,1" newline bitfld.long 0x4 11. "MCA_1_3,Activity of check performed in module MCS1 at channel x" "0,1" newline bitfld.long 0x4 10. "MCA_1_2,Activity of check performed in module MCS1 at channel x" "0,1" newline bitfld.long 0x4 9. "MCA_1_1,Activity of check performed in module MCS1 at channel x" "0,1" newline bitfld.long 0x4 8. "MCA_1_0,Activity of check performed in module MCS1 at channel x" "0,1" newline bitfld.long 0x4 7. "MCA_0_7,Activity of check performed in module MCS0 at channel x" "0,1" newline bitfld.long 0x4 6. "MCA_0_6,Activity of check performed in module MCS0 at channel x" "0,1" newline bitfld.long 0x4 5. "MCA_0_5,Activity of check performed in module MCS0 at channel x" "0,1" newline bitfld.long 0x4 4. "MCA_0_4,Activity of check performed in module MCS0 at channel x" "0,1" newline bitfld.long 0x4 3. "MCA_0_3,Activity of check performed in module MCS0 at channel x" "0,1" newline bitfld.long 0x4 2. "MCA_0_2,Activity of check performed in module MCS0 at channel x" "0,1" newline bitfld.long 0x4 1. "MCA_0_1,Activity of check performed in module MCS0 at channel x" "0,1" newline bitfld.long 0x4 0. "MCA_0_0,Activity of check performed in module MCS0 at channel x" "0,1" line.long 0x8 "MON_ACTIVITY_1," bitfld.long 0x8 31. "MCA_7_7,Activity of check performed in module MCS7 at channel x" "0,1" newline bitfld.long 0x8 30. "MCA_7_6,Activity of check performed in module MCS7 at channel x" "0,1" newline bitfld.long 0x8 29. "MCA_7_5,Activity of check performed in module MCS7 at channel x" "0,1" newline bitfld.long 0x8 28. "MCA_7_4,Activity of check performed in module MCS7 at channel x" "0,1" newline bitfld.long 0x8 27. "MCA_7_3,Activity of check performed in module MCS7 at channel x" "0,1" newline bitfld.long 0x8 26. "MCA_7_2,Activity of check performed in module MCS7 at channel x" "0,1" newline bitfld.long 0x8 25. "MCA_7_1,Activity of check performed in module MCS7 at channel x" "0,1" newline bitfld.long 0x8 24. "MCA_7_0,Activity of check performed in module MCS7 at channel x" "0,1" newline bitfld.long 0x8 23. "MCA_6_7,Activity of check performed in module MCS6 at channel x" "0,1" newline bitfld.long 0x8 22. "MCA_6_6,Activity of check performed in module MCS6 at channel x" "0,1" newline bitfld.long 0x8 21. "MCA_6_5,Activity of check performed in module MCS6 at channel x" "0,1" newline bitfld.long 0x8 20. "MCA_6_4,Activity of check performed in module MCS6 at channel x" "0,1" newline bitfld.long 0x8 19. "MCA_6_3,Activity of check performed in module MCS6 at channel x" "0,1" newline bitfld.long 0x8 18. "MCA_6_2,Activity of check performed in module MCS6 at channel x" "0,1" newline bitfld.long 0x8 17. "MCA_6_1,Activity of check performed in module MCS6 at channel x" "0,1" newline bitfld.long 0x8 16. "MCA_6_0,Activity of check performed in module MCS6 at channel x" "0,1" newline bitfld.long 0x8 15. "MCA_5_7,Activity of check performed in module MCS5 at channel x" "0,1" newline bitfld.long 0x8 14. "MCA_5_6,Activity of check performed in module MCS5 at channel x" "0,1" newline bitfld.long 0x8 13. "MCA_5_5,Activity of check performed in module MCS5 at channel x" "0,1" newline bitfld.long 0x8 12. "MCA_5_4,Activity of check performed in module MCS5 at channel x" "0,1" newline bitfld.long 0x8 11. "MCA_5_3,Activity of check performed in module MCS5 at channel x" "0,1" newline bitfld.long 0x8 10. "MCA_5_2,Activity of check performed in module MCS5 at channel x" "0,1" newline bitfld.long 0x8 9. "MCA_5_1,Activity of check performed in module MCS5 at channel x" "0,1" newline bitfld.long 0x8 8. "MCA_5_0,Activity of check performed in module MCS5 at channel x" "0,1" newline bitfld.long 0x8 7. "MCA_4_7,Activity of check performed in module MCS4 at channel x" "0,1" newline bitfld.long 0x8 6. "MCA_4_6,Activity of check performed in module MCS4 at channel x" "0,1" newline bitfld.long 0x8 5. "MCA_4_5,Activity of check performed in module MCS4 at channel x" "0,1" newline bitfld.long 0x8 4. "MCA_4_4,Activity of check performed in module MCS4 at channel x" "0,1" newline bitfld.long 0x8 3. "MCA_4_3,Activity of check performed in module MCS4 at channel x" "0,1" newline bitfld.long 0x8 2. "MCA_4_2,Activity of check performed in module MCS4 at channel x" "0,1" newline bitfld.long 0x8 1. "MCA_4_1,Activity of check performed in module MCS4 at channel x" "0,1" newline bitfld.long 0x8 0. "MCA_4_0,Activity of check performed in module MCS4 at channel x" "0,1" line.long 0xC "MON_ACTIVITY_MCS0," bitfld.long 0xC 7. "MCA_7,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0xC 6. "MCA_6,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0xC 5. "MCA_5,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0xC 4. "MCA_4,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0xC 3. "MCA_3,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0xC 2. "MCA_2,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0xC 1. "MCA_1,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0xC 0. "MCA_0,Activity of check performed in module MCS j at channel x" "0,1" line.long 0x10 "MON_ACTIVITY_MCS1," bitfld.long 0x10 7. "MCA_7,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x10 6. "MCA_6,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x10 5. "MCA_5,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x10 4. "MCA_4,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x10 3. "MCA_3,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x10 2. "MCA_2,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x10 1. "MCA_1,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x10 0. "MCA_0,Activity of check performed in module MCS j at channel x" "0,1" line.long 0x14 "MON_ACTIVITY_MCS2," bitfld.long 0x14 7. "MCA_7,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x14 6. "MCA_6,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x14 5. "MCA_5,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x14 4. "MCA_4,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x14 3. "MCA_3,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x14 2. "MCA_2,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x14 1. "MCA_1,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x14 0. "MCA_0,Activity of check performed in module MCS j at channel x" "0,1" line.long 0x18 "MON_ACTIVITY_MCS3," bitfld.long 0x18 7. "MCA_7,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x18 6. "MCA_6,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x18 5. "MCA_5,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x18 4. "MCA_4,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x18 3. "MCA_3,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x18 2. "MCA_2,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x18 1. "MCA_1,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x18 0. "MCA_0,Activity of check performed in module MCS j at channel x" "0,1" line.long 0x1C "MON_ACTIVITY_MCS4," bitfld.long 0x1C 7. "MCA_7,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x1C 6. "MCA_6,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x1C 5. "MCA_5,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x1C 4. "MCA_4,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x1C 3. "MCA_3,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x1C 2. "MCA_2,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x1C 1. "MCA_1,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x1C 0. "MCA_0,Activity of check performed in module MCS j at channel x" "0,1" line.long 0x20 "MON_ACTIVITY_MCS5," bitfld.long 0x20 7. "MCA_7,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x20 6. "MCA_6,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x20 5. "MCA_5,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x20 4. "MCA_4,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x20 3. "MCA_3,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x20 2. "MCA_2,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x20 1. "MCA_1,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x20 0. "MCA_0,Activity of check performed in module MCS j at channel x" "0,1" line.long 0x24 "MON_ACTIVITY_MCS6," bitfld.long 0x24 7. "MCA_7,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x24 6. "MCA_6,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x24 5. "MCA_5,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x24 4. "MCA_4,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x24 3. "MCA_3,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x24 2. "MCA_2,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x24 1. "MCA_1,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x24 0. "MCA_0,Activity of check performed in module MCS j at channel x" "0,1" line.long 0x28 "MON_ACTIVITY_MCS7," bitfld.long 0x28 7. "MCA_7,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x28 6. "MCA_6,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x28 5. "MCA_5,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x28 4. "MCA_4,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x28 3. "MCA_3,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x28 2. "MCA_2,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x28 1. "MCA_1,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x28 0. "MCA_0,Activity of check performed in module MCS j at channel x" "0,1" line.long 0x2C "MON_ACTIVITY_MCS8," bitfld.long 0x2C 7. "MCA_7,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x2C 6. "MCA_6,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x2C 5. "MCA_5,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x2C 4. "MCA_4,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x2C 3. "MCA_3,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x2C 2. "MCA_2,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x2C 1. "MCA_1,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x2C 0. "MCA_0,Activity of check performed in module MCS j at channel x" "0,1" line.long 0x30 "MON_ACTIVITY_MCS9," bitfld.long 0x30 7. "MCA_7,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x30 6. "MCA_6,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x30 5. "MCA_5,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x30 4. "MCA_4,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x30 3. "MCA_3,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x30 2. "MCA_2,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x30 1. "MCA_1,Activity of check performed in module MCS j at channel x" "0,1" newline bitfld.long 0x30 0. "MCA_0,Activity of check performed in module MCS j at channel x" "0,1" group.long 0x6C0++0x17 line.long 0x0 "CMP_EN," bitfld.long 0x0 23. "TBWC11_EN,Enable comparator channel [c] in TBWC" "0,1" newline bitfld.long 0x0 22. "TBWC10_EN,Enable comparator channel [c] in TBWC" "0,1" newline bitfld.long 0x0 21. "TBWC9_EN,Enable comparator channel [c] in TBWC" "0,1" newline bitfld.long 0x0 20. "TBWC8_EN,Enable comparator channel [c] in TBWC" "0,1" newline bitfld.long 0x0 19. "TBWC7_EN,Enable comparator channel [c] in TBWC" "0,1" newline bitfld.long 0x0 18. "TBWC6_EN,Enable comparator channel [c] in TBWC" "0,1" newline bitfld.long 0x0 17. "TBWC5_EN,Enable comparator channel [c] in TBWC" "0,1" newline bitfld.long 0x0 16. "TBWC4_EN,Enable comparator channel [c] in TBWC" "0,1" newline bitfld.long 0x0 15. "TBWC3_EN,Enable comparator channel [c] in TBWC" "0,1" newline bitfld.long 0x0 14. "TBWC2_EN,Enable comparator channel [c] in TBWC" "0,1" newline bitfld.long 0x0 13. "TBWC1_EN,Enable comparator channel [c] in TBWC" "0,1" newline bitfld.long 0x0 12. "TBWC0_EN,Enable comparator channel [c] in TBWC" "0,1" newline bitfld.long 0x0 11. "ABWC11_EN,Enable comparator channel [c] in ABWC" "0,1" newline bitfld.long 0x0 10. "ABWC10_EN,Enable comparator channel [c] in ABWC" "0,1" newline bitfld.long 0x0 9. "ABWC9_EN,Enable comparator channel [c] in ABWC" "0,1" newline bitfld.long 0x0 8. "ABWC8_EN,Enable comparator channel [c] in ABWC" "0,1" newline bitfld.long 0x0 7. "ABWC7_EN,Enable comparator channel [c] in ABWC" "0,1" newline bitfld.long 0x0 6. "ABWC6_EN,Enable comparator channel [c] in ABWC" "0,1" newline bitfld.long 0x0 5. "ABWC5_EN,Enable comparator channel [c] in ABWC" "0,1" newline bitfld.long 0x0 4. "ABWC4_EN,Enable comparator channel [c] in ABWC" "0,1" newline bitfld.long 0x0 3. "ABWC3_EN,Enable comparator channel [c] in ABWC" "0,1" newline bitfld.long 0x0 2. "ABWC2_EN,Enable comparator channel [c] in ABWC" "0,1" newline bitfld.long 0x0 1. "ABWC1_EN,Enable comparator channel [c] in ABWC" "0,1" newline bitfld.long 0x0 0. "ABWC0_EN,Enable comparator channel [c] in ABWC" "0,1" line.long 0x4 "CMP_IRQ_NOTIFY," bitfld.long 0x4 23. "TBWC11,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 22. "TBWC10,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 21. "TBWC9,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 20. "TBWC8,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 19. "TBWC7,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 18. "TBWC6,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 17. "TBWC5,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 16. "TBWC4,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 15. "TBWC3,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 14. "TBWC2,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 13. "TBWC1,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 12. "TBWC0,TOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 11. "ABWC11,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 10. "ABWC10,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 9. "ABWC9,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 8. "ABWC8,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 7. "ABWC7,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 6. "ABWC6,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 5. "ABWC5,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 4. "ABWC4,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 3. "ABWC3,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 2. "ABWC2,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 1. "ABWC1,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" newline bitfld.long 0x4 0. "ABWC0,ATOM sub-modules outputs bitwise comparator [c] error indication" "0,1" line.long 0x8 "CMP_IRQ_EN," bitfld.long 0x8 23. "TBWC11_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 22. "TBWC10_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 21. "TBWC9_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 20. "TBWC8_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 19. "TBWC7_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 18. "TBWC6_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 17. "TBWC5_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 16. "TBWC4_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 15. "TBWC3_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 14. "TBWC2_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 13. "TBWC1_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 12. "TBWC0_EN_IRQ,Enable TBWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 11. "ABWC11_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 10. "ABWC10_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 9. "ABWC9_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 8. "ABWC8_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 7. "ABWC7_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 6. "ABWC6_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 5. "ABWC5_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 4. "ABWC4_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 3. "ABWC3_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 2. "ABWC2_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 1. "ABWC1_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" newline bitfld.long 0x8 0. "ABWC0_EN_IRQ,Enable ABWC[c] interrupt source for CMP_IRQ line" "0,1" line.long 0xC "CMP_IRQ_FORCINT," bitfld.long 0xC 23. "TRG_TBWC11,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 22. "TRG_TBWC10,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 21. "TRG_TBWC9,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 20. "TRG_TBWC8,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 19. "TRG_TBWC7,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 18. "TRG_TBWC6,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 17. "TRG_TBWC5,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 16. "TRG_TBWC4,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 15. "TRG_TBWC3,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 14. "TRG_TBWC2,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 13. "TRG_TBWC1,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 12. "TRG_TBWC0,Trigger TBWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 11. "TRG_ABWC11,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 10. "TRG_ABWC10,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 9. "TRG_ABWC9,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 8. "TRG_ABWC8,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 7. "TRG_ABWC7,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 6. "TRG_ABWC6,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 5. "TRG_ABWC5,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 4. "TRG_ABWC4,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 3. "TRG_ABWC3,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 2. "TRG_ABWC2,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 1. "TRG_ABWC1,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_ABWC0,Trigger ABWC[c] bit in CMP_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "CMP_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "CMP_EIRQ_EN," bitfld.long 0x14 23. "TBWC11_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 22. "TBWC10_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 21. "TBWC9_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 20. "TBWC8_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 19. "TBWC7_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 18. "TBWC6_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 17. "TBWC5_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 16. "TBWC4_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 15. "TBWC3_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 14. "TBWC2_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 13. "TBWC1_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 12. "TBWC0_EN_EIRQ,Enable TBWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 11. "ABWC11_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 10. "ABWC10_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 9. "ABWC9_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 8. "ABWC8_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 7. "ABWC7_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 6. "ABWC6_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 5. "ABWC5_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 4. "ABWC4_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 3. "ABWC3_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 2. "ABWC2_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 1. "ABWC1_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" newline bitfld.long 0x14 0. "ABWC0_EN_EIRQ,Enable ABWC comparator [c] interrupt source for CMP_EIRQ line" "0,1" group.long 0x800++0x3F line.long 0x0 "TIM1_CH0_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM1_CH0_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM1_CH0_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM1_CH0_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM1_CH0_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM1_CH0_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM1_CH0_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM1_CH0_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM1_CH0_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM1_CH0_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM1_CH0_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM1_CH0_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM1_CH0_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM1_CH0_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM1_CH0_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM1_CH0_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x880++0x3F line.long 0x0 "TIM1_CH1_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM1_CH1_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM1_CH1_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM1_CH1_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM1_CH1_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM1_CH1_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM1_CH1_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM1_CH1_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM1_CH1_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM1_CH1_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM1_CH1_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM1_CH1_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM1_CH1_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM1_CH1_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM1_CH1_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM1_CH1_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x900++0x3F line.long 0x0 "TIM1_CH2_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM1_CH2_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM1_CH2_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM1_CH2_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM1_CH2_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM1_CH2_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM1_CH2_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM1_CH2_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM1_CH2_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM1_CH2_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM1_CH2_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM1_CH2_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM1_CH2_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM1_CH2_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM1_CH2_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM1_CH2_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x980++0x3F line.long 0x0 "TIM1_CH3_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM1_CH3_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM1_CH3_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM1_CH3_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM1_CH3_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM1_CH3_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM1_CH3_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM1_CH3_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM1_CH3_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM1_CH3_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM1_CH3_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM1_CH3_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM1_CH3_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM1_CH3_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM1_CH3_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM1_CH3_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xA00++0x3F line.long 0x0 "TIM1_CH4_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM1_CH4_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM1_CH4_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM1_CH4_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM1_CH4_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM1_CH4_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM1_CH4_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM1_CH4_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM1_CH4_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM1_CH4_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM1_CH4_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM1_CH4_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM1_CH4_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM1_CH4_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM1_CH4_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM1_CH4_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xA80++0x3F line.long 0x0 "TIM1_CH5_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM1_CH5_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM1_CH5_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM1_CH5_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM1_CH5_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM1_CH5_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM1_CH5_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM1_CH5_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM1_CH5_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM1_CH5_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM1_CH5_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM1_CH5_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM1_CH5_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM1_CH5_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM1_CH5_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM1_CH5_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xB00++0x3F line.long 0x0 "TIM1_CH6_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM1_CH6_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM1_CH6_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM1_CH6_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM1_CH6_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM1_CH6_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM1_CH6_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM1_CH6_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM1_CH6_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM1_CH6_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM1_CH6_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM1_CH6_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM1_CH6_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM1_CH6_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM1_CH6_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM1_CH6_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xB80++0x3F line.long 0x0 "TIM1_CH7_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM1_CH7_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM1_CH7_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM1_CH7_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM1_CH7_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM1_CH7_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM1_CH7_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM1_CH7_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM1_CH7_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM1_CH7_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM1_CH7_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM1_CH7_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM1_CH7_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM1_CH7_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM1_CH7_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM1_CH7_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xC00++0xB line.long 0x0 "TIM1_INP_VAL," bitfld.long 0x0 23. "TIM_IN7,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 22. "TIM_IN6,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 21. "TIM_IN5,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 20. "TIM_IN4,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 19. "TIM_IN3,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 18. "TIM_IN2,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 17. "TIM_IN1,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 16. "TIM_IN0,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 15. "F_IN7,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 14. "F_IN6,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 13. "F_IN5,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 12. "F_IN4,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 11. "F_IN3,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 10. "F_IN2,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 9. "F_IN1,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 8. "F_IN0,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 7. "F_OUT7,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 6. "F_OUT6,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 5. "F_OUT5,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 4. "F_OUT4,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 3. "F_OUT3,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 2. "F_OUT2,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 1. "F_OUT1,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 0. "F_OUT0,Signal channel x after TIM FLT unit" "0,1" line.long 0x4 "TIM1_IN_SRC," bitfld.long 0x4 30.--31. "MODE_7,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 28.--29. "VAL_7,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 26.--27. "MODE_6,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 24.--25. "VAL_6,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 22.--23. "MODE_5,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 20.--21. "VAL_5,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 18.--19. "MODE_4,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 16.--17. "VAL_4,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 14.--15. "MODE_3,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 12.--13. "VAL_3,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 10.--11. "MODE_2,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 8.--9. "VAL_2,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 6.--7. "MODE_1,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 4.--5. "VAL_1,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 2.--3. "MODE_0,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 0.--1. "VAL_0,Value to be fed to channel [x]" "0,1,2,3" line.long 0x8 "TIM1_RST," bitfld.long 0x8 7. "RST_CH7,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 6. "RST_CH6,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 5. "RST_CH5,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 4. "RST_CH4,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 3. "RST_CH3,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 2. "RST_CH2,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 1. "RST_CH1,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 0. "RST_CH0,Software reset of channel [x]" "0,1" group.long 0x1000++0x2B line.long 0x0 "TOM1_CH0_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM1_CH0_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM1_CH0_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM1_CH0_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM1_CH0_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM1_CH0_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM1_CH0_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM1_CH0_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM1_CH0_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM1_CH0_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM1_CH0_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1030++0x3 line.long 0x0 "TOM1_CH0_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1040++0x2B line.long 0x0 "TOM1_CH1_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM1_CH1_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM1_CH1_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM1_CH1_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM1_CH1_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM1_CH1_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM1_CH1_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM1_CH1_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM1_CH1_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM1_CH1_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM1_CH1_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1070++0x3 line.long 0x0 "TOM1_CH1_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1080++0x2B line.long 0x0 "TOM1_CH2_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM1_CH2_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM1_CH2_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM1_CH2_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM1_CH2_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM1_CH2_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM1_CH2_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM1_CH2_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM1_CH2_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM1_CH2_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM1_CH2_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x10B0++0x3 line.long 0x0 "TOM1_CH2_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x10C0++0x2B line.long 0x0 "TOM1_CH3_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM1_CH3_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM1_CH3_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM1_CH3_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM1_CH3_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM1_CH3_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM1_CH3_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM1_CH3_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM1_CH3_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM1_CH3_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM1_CH3_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x10F0++0x3 line.long 0x0 "TOM1_CH3_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1100++0x2B line.long 0x0 "TOM1_CH4_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM1_CH4_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM1_CH4_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM1_CH4_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM1_CH4_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM1_CH4_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM1_CH4_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM1_CH4_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM1_CH4_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM1_CH4_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM1_CH4_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1130++0x3 line.long 0x0 "TOM1_CH4_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1140++0x2B line.long 0x0 "TOM1_CH5_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM1_CH5_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM1_CH5_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM1_CH5_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM1_CH5_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM1_CH5_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM1_CH5_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM1_CH5_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM1_CH5_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM1_CH5_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM1_CH5_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1170++0x3 line.long 0x0 "TOM1_CH5_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1180++0x2B line.long 0x0 "TOM1_CH6_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM1_CH6_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM1_CH6_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM1_CH6_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM1_CH6_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM1_CH6_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM1_CH6_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM1_CH6_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM1_CH6_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM1_CH6_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM1_CH6_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x11B0++0x3 line.long 0x0 "TOM1_CH6_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x11C0++0x2B line.long 0x0 "TOM1_CH7_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM1_CH7_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM1_CH7_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM1_CH7_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM1_CH7_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM1_CH7_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM1_CH7_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM1_CH7_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM1_CH7_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM1_CH7_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM1_CH7_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x11F0++0x3 line.long 0x0 "TOM1_CH7_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1200++0x2B line.long 0x0 "TOM1_CH8_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM1_CH8_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM1_CH8_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM1_CH8_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM1_CH8_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM1_CH8_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM1_CH8_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM1_CH8_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM1_CH8_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM1_CH8_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM1_CH8_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1230++0x3 line.long 0x0 "TOM1_CH8_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1240++0x2B line.long 0x0 "TOM1_CH9_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM1_CH9_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM1_CH9_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM1_CH9_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM1_CH9_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM1_CH9_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM1_CH9_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM1_CH9_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM1_CH9_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM1_CH9_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM1_CH9_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1270++0x3 line.long 0x0 "TOM1_CH9_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1280++0x2B line.long 0x0 "TOM1_CH10_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM1_CH10_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM1_CH10_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM1_CH10_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM1_CH10_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM1_CH10_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM1_CH10_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM1_CH10_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM1_CH10_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM1_CH10_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM1_CH10_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x12B0++0x3 line.long 0x0 "TOM1_CH10_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x12C0++0x2B line.long 0x0 "TOM1_CH11_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM1_CH11_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM1_CH11_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM1_CH11_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM1_CH11_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM1_CH11_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM1_CH11_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM1_CH11_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM1_CH11_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM1_CH11_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM1_CH11_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x12F0++0x3 line.long 0x0 "TOM1_CH11_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1300++0x2B line.long 0x0 "TOM1_CH12_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM1_CH12_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM1_CH12_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM1_CH12_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM1_CH12_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM1_CH12_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM1_CH12_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM1_CH12_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM1_CH12_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM1_CH12_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM1_CH12_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1330++0x3 line.long 0x0 "TOM1_CH12_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1340++0x2B line.long 0x0 "TOM1_CH13_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM1_CH13_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM1_CH13_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM1_CH13_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM1_CH13_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM1_CH13_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM1_CH13_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM1_CH13_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM1_CH13_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM1_CH13_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM1_CH13_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1370++0x3 line.long 0x0 "TOM1_CH13_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1380++0x2B line.long 0x0 "TOM1_CH14_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM1_CH14_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM1_CH14_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM1_CH14_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM1_CH14_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM1_CH14_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM1_CH14_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM1_CH14_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM1_CH14_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM1_CH14_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM1_CH14_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x13B0++0x3 line.long 0x0 "TOM1_CH14_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x13C0++0x2B line.long 0x0 "TOM1_CH15_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM1_CH15_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM1_CH15_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM1_CH15_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM1_CH15_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM1_CH15_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM1_CH15_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM1_CH15_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM1_CH15_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM1_CH15_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM1_CH15_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x13F0++0x3 line.long 0x0 "TOM1_CH15_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1430++0xF line.long 0x0 "TOM1_TGC0_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 28.--29. "UPEN_CTRL6,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 26.--27. "UPEN_CTRL5,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 24.--25. "UPEN_CTRL4,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 22.--23. "UPEN_CTRL3,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 20.--21. "UPEN_CTRL2,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 16.--17. "UPEN_CTRL0,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 15. "RST_CH7,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 14. "RST_CH6,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 13. "RST_CH5,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 12. "RST_CH4,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 10. "RST_CH2,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 9. "RST_CH1,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 8. "RST_CH0,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see TGC0 TGC1) to update the register TOM[i]_TGC[g]_ENDIS_STAT and TOM[i]_TGC[g]_OUTEN_STAT" "0,1" line.long 0x4 "TOM1_TGC0_ACT_TB," bitfld.long 0x4 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" newline bitfld.long 0x4 24. "TB_TRIG,Set trigger request" "0,1" newline hexmask.long.tbyte 0x4 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[y] y=0..2. If selected TBU_TS[y] value is in the interval [TOM[i]_TGC[g]_ACT_TB.ACT_TB-007FFFFFh TOM[i]_TGC[g]_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x8 "TOM1_TGC0_FUPD_CTRL," bitfld.long 0x8 30.--31. "RSTCN0_CH7,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 28.--29. "RSTCN0_CH6,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 26.--27. "RSTCN0_CH5,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 24.--25. "RSTCN0_CH4,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 22.--23. "RSTCN0_CH3,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 20.--21. "RSTCN0_CH2,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 18.--19. "RSTCN0_CH1,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 16.--17. "RSTCN0_CH0,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 14.--15. "FUPD_CTRL7,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 12.--13. "FUPD_CTRL6,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 10.--11. "FUPD_CTRL5,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 8.--9. "FUPD_CTRL4,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 6.--7. "FUPD_CTRL3,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 4.--5. "FUPD_CTRL2,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 2.--3. "FUPD_CTRL1,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 0.--1. "FUPD_CTRL0,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" line.long 0xC "TOM1_TGC0_INT_TRIG," bitfld.long 0xC 14.--15. "INT_TRIG7,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 12.--13. "INT_TRIG6,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 10.--11. "INT_TRIG5,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "INT_TRIG4,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 6.--7. "INT_TRIG3,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 4.--5. "INT_TRIG2,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "INT_TRIG1,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 0.--1. "INT_TRIG0,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" group.long 0x1470++0xF line.long 0x0 "TOM1_TGC0_ENDIS_CTRL," bitfld.long 0x0 14.--15. "ENDIS_CTRL7,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 12.--13. "ENDIS_CTRL6,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 10.--11. "ENDIS_CTRL5,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 8.--9. "ENDIS_CTRL4,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 6.--7. "ENDIS_CTRL3,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ENDIS_CTRL2,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 2.--3. "ENDIS_CTRL1,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 0.--1. "ENDIS_CTRL0,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" line.long 0x4 "TOM1_TGC0_ENDIS_STAT," bitfld.long 0x4 14.--15. "ENDIS_STAT7,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 12.--13. "ENDIS_STAT6,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 10.--11. "ENDIS_STAT5,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 8.--9. "ENDIS_STAT4,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 6.--7. "ENDIS_STAT3,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 4.--5. "ENDIS_STAT2,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_STAT1,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 0.--1. "ENDIS_STAT0,TOM channel x=c + g*8 enable/disable" "0,1,2,3" line.long 0x8 "TOM1_TGC0_OUTEN_CTRL," bitfld.long 0x8 14.--15. "OUTEN_CTRL7,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 12.--13. "OUTEN_CTRL6,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OUTEN_CTRL5,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 8.--9. "OUTEN_CTRL4,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OUTEN_CTRL3,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 4.--5. "OUTEN_CTRL2,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OUTEN_CTRL1,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 0.--1. "OUTEN_CTRL0,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" line.long 0xC "TOM1_TGC0_OUTEN_STAT," bitfld.long 0xC 14.--15. "OUTEN_STAT7,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 12.--13. "OUTEN_STAT6,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 10.--11. "OUTEN_STAT5,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "OUTEN_STAT4,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 6.--7. "OUTEN_STAT3,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 4.--5. "OUTEN_STAT2,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "OUTEN_STAT1,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 0.--1. "OUTEN_STAT0,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" group.long 0x14B0++0xF line.long 0x0 "TOM1_TGC1_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 28.--29. "UPEN_CTRL6,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 26.--27. "UPEN_CTRL5,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 24.--25. "UPEN_CTRL4,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 22.--23. "UPEN_CTRL3,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 20.--21. "UPEN_CTRL2,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 16.--17. "UPEN_CTRL0,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 15. "RST_CH7,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 14. "RST_CH6,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 13. "RST_CH5,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 12. "RST_CH4,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 10. "RST_CH2,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 9. "RST_CH1,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 8. "RST_CH0,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see TGC0 TGC1) to update the register TOM[i]_TGC[g]_ENDIS_STAT and TOM[i]_TGC[g]_OUTEN_STAT" "0,1" line.long 0x4 "TOM1_TGC1_ACT_TB," bitfld.long 0x4 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" newline bitfld.long 0x4 24. "TB_TRIG,Set trigger request" "0,1" newline hexmask.long.tbyte 0x4 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[y] y=0..2. If selected TBU_TS[y] value is in the interval [TOM[i]_TGC[g]_ACT_TB.ACT_TB-007FFFFFh TOM[i]_TGC[g]_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x8 "TOM1_TGC1_FUPD_CTRL," bitfld.long 0x8 30.--31. "RSTCN0_CH7,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 28.--29. "RSTCN0_CH6,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 26.--27. "RSTCN0_CH5,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 24.--25. "RSTCN0_CH4,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 22.--23. "RSTCN0_CH3,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 20.--21. "RSTCN0_CH2,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 18.--19. "RSTCN0_CH1,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 16.--17. "RSTCN0_CH0,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 14.--15. "FUPD_CTRL7,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 12.--13. "FUPD_CTRL6,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 10.--11. "FUPD_CTRL5,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 8.--9. "FUPD_CTRL4,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 6.--7. "FUPD_CTRL3,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 4.--5. "FUPD_CTRL2,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 2.--3. "FUPD_CTRL1,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 0.--1. "FUPD_CTRL0,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" line.long 0xC "TOM1_TGC1_INT_TRIG," bitfld.long 0xC 14.--15. "INT_TRIG7,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 12.--13. "INT_TRIG6,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 10.--11. "INT_TRIG5,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "INT_TRIG4,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 6.--7. "INT_TRIG3,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 4.--5. "INT_TRIG2,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "INT_TRIG1,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 0.--1. "INT_TRIG0,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" group.long 0x14F0++0xF line.long 0x0 "TOM1_TGC1_ENDIS_CTRL," bitfld.long 0x0 14.--15. "ENDIS_CTRL7,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 12.--13. "ENDIS_CTRL6,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 10.--11. "ENDIS_CTRL5,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 8.--9. "ENDIS_CTRL4,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 6.--7. "ENDIS_CTRL3,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ENDIS_CTRL2,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 2.--3. "ENDIS_CTRL1,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 0.--1. "ENDIS_CTRL0,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" line.long 0x4 "TOM1_TGC1_ENDIS_STAT," bitfld.long 0x4 14.--15. "ENDIS_STAT7,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 12.--13. "ENDIS_STAT6,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 10.--11. "ENDIS_STAT5,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 8.--9. "ENDIS_STAT4,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 6.--7. "ENDIS_STAT3,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 4.--5. "ENDIS_STAT2,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_STAT1,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 0.--1. "ENDIS_STAT0,TOM channel x=c + g*8 enable/disable" "0,1,2,3" line.long 0x8 "TOM1_TGC1_OUTEN_CTRL," bitfld.long 0x8 14.--15. "OUTEN_CTRL7,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 12.--13. "OUTEN_CTRL6,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OUTEN_CTRL5,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 8.--9. "OUTEN_CTRL4,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OUTEN_CTRL3,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 4.--5. "OUTEN_CTRL2,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OUTEN_CTRL1,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 0.--1. "OUTEN_CTRL0,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" line.long 0xC "TOM1_TGC1_OUTEN_STAT," bitfld.long 0xC 14.--15. "OUTEN_STAT7,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 12.--13. "OUTEN_STAT6,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 10.--11. "OUTEN_STAT5,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "OUTEN_STAT4,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 6.--7. "OUTEN_STAT3,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 4.--5. "OUTEN_STAT2,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "OUTEN_STAT1,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 0.--1. "OUTEN_STAT0,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" group.long 0x1800++0x37 line.long 0x0 "ATOM1_CH0_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM1_CH0_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM1_CH0_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM1_CH0_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM1_CH0_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM1_CH0_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM1_CH0_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM1_CH0_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM1_CH0_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM1_CH0_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM1_CH0_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM1_CH0_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x30 "ATOM1_CH0_CTRL2," bitfld.long 0x30 0. "HRES,HRES: TOM high resolution support" "0,1" line.long 0x34 "ATOM1_CH0_CTRL_SR," hexmask.long.byte 0x34 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x34 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1880++0x37 line.long 0x0 "ATOM1_CH1_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM1_CH1_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM1_CH1_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM1_CH1_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM1_CH1_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM1_CH1_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM1_CH1_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM1_CH1_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM1_CH1_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM1_CH1_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM1_CH1_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM1_CH1_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x30 "ATOM1_CH1_CTRL2," bitfld.long 0x30 0. "HRES,HRES: TOM high resolution support" "0,1" line.long 0x34 "ATOM1_CH1_CTRL_SR," hexmask.long.byte 0x34 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x34 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1900++0x37 line.long 0x0 "ATOM1_CH2_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM1_CH2_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM1_CH2_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM1_CH2_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM1_CH2_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM1_CH2_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM1_CH2_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM1_CH2_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM1_CH2_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM1_CH2_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM1_CH2_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM1_CH2_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x30 "ATOM1_CH2_CTRL2," bitfld.long 0x30 0. "HRES,HRES: TOM high resolution support" "0,1" line.long 0x34 "ATOM1_CH2_CTRL_SR," hexmask.long.byte 0x34 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x34 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1980++0x37 line.long 0x0 "ATOM1_CH3_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM1_CH3_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM1_CH3_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM1_CH3_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM1_CH3_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM1_CH3_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM1_CH3_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM1_CH3_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM1_CH3_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM1_CH3_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM1_CH3_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM1_CH3_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x30 "ATOM1_CH3_CTRL2," bitfld.long 0x30 0. "HRES,HRES: TOM high resolution support" "0,1" line.long 0x34 "ATOM1_CH3_CTRL_SR," hexmask.long.byte 0x34 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x34 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A00++0x2F line.long 0x0 "ATOM1_CH4_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM1_CH4_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM1_CH4_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM1_CH4_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM1_CH4_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM1_CH4_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM1_CH4_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM1_CH4_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM1_CH4_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM1_CH4_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM1_CH4_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM1_CH4_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1A34++0x3 line.long 0x0 "ATOM1_CH4_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A80++0x2F line.long 0x0 "ATOM1_CH5_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM1_CH5_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM1_CH5_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM1_CH5_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM1_CH5_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM1_CH5_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM1_CH5_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM1_CH5_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM1_CH5_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM1_CH5_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM1_CH5_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM1_CH5_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1AB4++0x3 line.long 0x0 "ATOM1_CH5_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B00++0x2F line.long 0x0 "ATOM1_CH6_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM1_CH6_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM1_CH6_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM1_CH6_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM1_CH6_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM1_CH6_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM1_CH6_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM1_CH6_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM1_CH6_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM1_CH6_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM1_CH6_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM1_CH6_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1B34++0x3 line.long 0x0 "ATOM1_CH6_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B80++0x2F line.long 0x0 "ATOM1_CH7_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM1_CH7_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM1_CH7_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM1_CH7_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM1_CH7_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM1_CH7_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM1_CH7_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM1_CH7_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM1_CH7_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM1_CH7_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM1_CH7_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM1_CH7_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1BB4++0x3 line.long 0x0 "ATOM1_CH7_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1C40++0x1F line.long 0x0 "ATOM1_AGC_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 28.--29. "UPEN_CTRL6,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 26.--27. "UPEN_CTRL5,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 24.--25. "UPEN_CTRL4,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 22.--23. "UPEN_CTRL3,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 20.--21. "UPEN_CTRL2,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 16.--17. "UPEN_CTRL0,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 15. "RST_CH7,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 14. "RST_CH6,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 13. "RST_CH5,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 12. "RST_CH4,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 10. "RST_CH2,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 9. "RST_CH1,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 8. "RST_CH0,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see AGC) to update the register ATOM[i]_AGC_ENDIS_STAT and ATOM[i]_AGC_OUTEN_STAT" "0,1" line.long 0x4 "ATOM1_AGC_ENDIS_CTRL," bitfld.long 0x4 14.--15. "ENDIS_CTRL7,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 12.--13. "ENDIS_CTRL6,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 10.--11. "ENDIS_CTRL5,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 8.--9. "ENDIS_CTRL4,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 6.--7. "ENDIS_CTRL3,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 4.--5. "ENDIS_CTRL2,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_CTRL1,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 0.--1. "ENDIS_CTRL0,ATOM channel [k] enable/disable update value." "0,1,2,3" line.long 0x8 "ATOM1_AGC_ENDIS_STAT," bitfld.long 0x8 14.--15. "ENDIS_STAT7,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 12.--13. "ENDIS_STAT6,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 10.--11. "ENDIS_STAT5,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 8.--9. "ENDIS_STAT4,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 6.--7. "ENDIS_STAT3,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 4.--5. "ENDIS_STAT2,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 2.--3. "ENDIS_STAT1,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 0.--1. "ENDIS_STAT0,ATOM channel [k] enable/disable" "0,1,2,3" line.long 0xC "ATOM1_AGC_ACT_TB," bitfld.long 0xC 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" newline bitfld.long 0xC 24. "TB_TRIG,Set trigger request" "0,1" newline hexmask.long.tbyte 0xC 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[x] x=0..2. If selected TBU_TS[x] value is in the interval [ATOM[i]_AGC_ACT_TB.ACT_TB-007FFFFFh ATOM[i]_AGC_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x10 "ATOM1_AGC_OUTEN_CTRL," bitfld.long 0x10 14.--15. "OUTEN_CTRL7,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 12.--13. "OUTEN_CTRL6,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 10.--11. "OUTEN_CTRL5,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 8.--9. "OUTEN_CTRL4,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 6.--7. "OUTEN_CTRL3,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 4.--5. "OUTEN_CTRL2,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 2.--3. "OUTEN_CTRL1,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 0.--1. "OUTEN_CTRL0,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" line.long 0x14 "ATOM1_AGC_OUTEN_STAT," bitfld.long 0x14 14.--15. "OUTEN_STAT7,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 12.--13. "OUTEN_STAT6,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 10.--11. "OUTEN_STAT5,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 8.--9. "OUTEN_STAT4,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 6.--7. "OUTEN_STAT3,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 4.--5. "OUTEN_STAT2,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 2.--3. "OUTEN_STAT1,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 0.--1. "OUTEN_STAT0,Control/status of output ATOM_OUT [k]" "0,1,2,3" line.long 0x18 "ATOM1_AGC_FUPD_CTRL," bitfld.long 0x18 30.--31. "RSTCN0_CH7,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 28.--29. "RSTCN0_CH6,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 26.--27. "RSTCN0_CH5,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 24.--25. "RSTCN0_CH4,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 22.--23. "RSTCN0_CH3,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 20.--21. "RSTCN0_CH2,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 18.--19. "RSTCN0_CH1,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 16.--17. "RSTCN0_CH0,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 14.--15. "FUPD_CTRL7,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 12.--13. "FUPD_CTRL6,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 10.--11. "FUPD_CTRL5,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 8.--9. "FUPD_CTRL4,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 6.--7. "FUPD_CTRL3,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 4.--5. "FUPD_CTRL2,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 2.--3. "FUPD_CTRL1,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 0.--1. "FUPD_CTRL0,Force update of ATOM channel [k] operation registers" "0,1,2,3" line.long 0x1C "ATOM1_AGC_INT_TRIG," bitfld.long 0x1C 14.--15. "INT_TRIG7,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 12.--13. "INT_TRIG6,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 10.--11. "INT_TRIG5,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 8.--9. "INT_TRIG4,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 6.--7. "INT_TRIG3,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 4.--5. "INT_TRIG2,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 2.--3. "INT_TRIG1,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "INT_TRIG0,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" group.long 0x2000++0x27 line.long 0x0 "MCS1_CH0_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS1_CH0_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS1_CH0_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS1_CH0_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS1_CH0_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS1_CH0_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS1_CH0_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS1_CH0_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS1_CH0_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS1_CH0_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x203C++0x3 line.long 0x0 "MCS1_CH0_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x20E0++0x17 line.long 0x0 "MCS1_CH0_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS1_CH0_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS1_CH0_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS1_CH0_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS1_CH0_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS1_CH0_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2100++0x27 line.long 0x0 "MCS1_CH1_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS1_CH1_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS1_CH1_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS1_CH1_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS1_CH1_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS1_CH1_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS1_CH1_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS1_CH1_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS1_CH1_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS1_CH1_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x213C++0x3 line.long 0x0 "MCS1_CH1_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x21E0++0x17 line.long 0x0 "MCS1_CH1_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS1_CH1_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS1_CH1_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS1_CH1_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS1_CH1_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS1_CH1_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2200++0x27 line.long 0x0 "MCS1_CH2_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS1_CH2_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS1_CH2_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS1_CH2_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS1_CH2_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS1_CH2_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS1_CH2_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS1_CH2_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS1_CH2_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS1_CH2_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x223C++0x3 line.long 0x0 "MCS1_CH2_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x22E0++0x17 line.long 0x0 "MCS1_CH2_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS1_CH2_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS1_CH2_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS1_CH2_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS1_CH2_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS1_CH2_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2300++0x27 line.long 0x0 "MCS1_CH3_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS1_CH3_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS1_CH3_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS1_CH3_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS1_CH3_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS1_CH3_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS1_CH3_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS1_CH3_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS1_CH3_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS1_CH3_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x233C++0x3 line.long 0x0 "MCS1_CH3_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x23E0++0x17 line.long 0x0 "MCS1_CH3_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS1_CH3_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS1_CH3_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS1_CH3_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS1_CH3_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS1_CH3_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2400++0x27 line.long 0x0 "MCS1_CH4_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS1_CH4_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS1_CH4_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS1_CH4_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS1_CH4_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS1_CH4_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS1_CH4_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS1_CH4_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS1_CH4_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS1_CH4_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x243C++0x3 line.long 0x0 "MCS1_CH4_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x24E0++0x17 line.long 0x0 "MCS1_CH4_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS1_CH4_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS1_CH4_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS1_CH4_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS1_CH4_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS1_CH4_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2500++0x27 line.long 0x0 "MCS1_CH5_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS1_CH5_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS1_CH5_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS1_CH5_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS1_CH5_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS1_CH5_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS1_CH5_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS1_CH5_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS1_CH5_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS1_CH5_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x253C++0x3 line.long 0x0 "MCS1_CH5_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x25E0++0x17 line.long 0x0 "MCS1_CH5_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS1_CH5_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS1_CH5_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS1_CH5_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS1_CH5_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS1_CH5_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2600++0x27 line.long 0x0 "MCS1_CH6_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS1_CH6_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS1_CH6_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS1_CH6_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS1_CH6_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS1_CH6_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS1_CH6_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS1_CH6_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS1_CH6_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS1_CH6_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x263C++0x3 line.long 0x0 "MCS1_CH6_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x26E0++0x17 line.long 0x0 "MCS1_CH6_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS1_CH6_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS1_CH6_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS1_CH6_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS1_CH6_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS1_CH6_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2700++0x27 line.long 0x0 "MCS1_CH7_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS1_CH7_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS1_CH7_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS1_CH7_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS1_CH7_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS1_CH7_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS1_CH7_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS1_CH7_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS1_CH7_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS1_CH7_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x273C++0x3 line.long 0x0 "MCS1_CH7_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x27E0++0x17 line.long 0x0 "MCS1_CH7_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS1_CH7_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS1_CH7_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS1_CH7_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS1_CH7_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS1_CH7_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2E28++0x7 line.long 0x0 "MCS1_CTRG," bitfld.long 0x0 23. "TRG23,Trigger bit o." "0,1" newline bitfld.long 0x0 22. "TRG22,Trigger bit o." "0,1" newline bitfld.long 0x0 21. "TRG21,Trigger bit o." "0,1" newline bitfld.long 0x0 20. "TRG20,Trigger bit o." "0,1" newline bitfld.long 0x0 19. "TRG19,Trigger bit o." "0,1" newline bitfld.long 0x0 18. "TRG18,Trigger bit o." "0,1" newline bitfld.long 0x0 17. "TRG17,Trigger bit o." "0,1" newline bitfld.long 0x0 16. "TRG16,Trigger bit o." "0,1" newline bitfld.long 0x0 15. "TRG15,Trigger bit n." "0,1" newline bitfld.long 0x0 14. "TRG14,Trigger bit n." "0,1" newline bitfld.long 0x0 13. "TRG13,Trigger bit n." "0,1" newline bitfld.long 0x0 12. "TRG12,Trigger bit n." "0,1" newline bitfld.long 0x0 11. "TRG11,Trigger bit n." "0,1" newline bitfld.long 0x0 10. "TRG10,Trigger bit n." "0,1" newline bitfld.long 0x0 9. "TRG9,Trigger bit n." "0,1" newline bitfld.long 0x0 8. "TRG8,Trigger bit n." "0,1" newline bitfld.long 0x0 7. "TRG7,Trigger bit m." "0,1" newline bitfld.long 0x0 6. "TRG6,Trigger bit m." "0,1" newline bitfld.long 0x0 5. "TRG5,Trigger bit m." "0,1" newline bitfld.long 0x0 4. "TRG4,Trigger bit m." "0,1" newline bitfld.long 0x0 3. "TRG3,Trigger bit m." "0,1" newline bitfld.long 0x0 2. "TRG2,Trigger bit m." "0,1" newline bitfld.long 0x0 1. "TRG1,Trigger bit m." "0,1" newline bitfld.long 0x0 0. "TRG0,Trigger bit m." "0,1" line.long 0x4 "MCS1_STRG," bitfld.long 0x4 23. "TRG23,Trigger bit k." "0,1" newline bitfld.long 0x4 22. "TRG22,Trigger bit k." "0,1" newline bitfld.long 0x4 21. "TRG21,Trigger bit k." "0,1" newline bitfld.long 0x4 20. "TRG20,Trigger bit k." "0,1" newline bitfld.long 0x4 19. "TRG19,Trigger bit k." "0,1" newline bitfld.long 0x4 18. "TRG18,Trigger bit k." "0,1" newline bitfld.long 0x4 17. "TRG17,Trigger bit k." "0,1" newline bitfld.long 0x4 16. "TRG16,Trigger bit k." "0,1" newline bitfld.long 0x4 15. "TRG15,Trigger bit k." "0,1" newline bitfld.long 0x4 14. "TRG14,Trigger bit k." "0,1" newline bitfld.long 0x4 13. "TRG13,Trigger bit k." "0,1" newline bitfld.long 0x4 12. "TRG12,Trigger bit k." "0,1" newline bitfld.long 0x4 11. "TRG11,Trigger bit k." "0,1" newline bitfld.long 0x4 10. "TRG10,Trigger bit k." "0,1" newline bitfld.long 0x4 9. "TRG9,Trigger bit k." "0,1" newline bitfld.long 0x4 8. "TRG8,Trigger bit k." "0,1" newline bitfld.long 0x4 7. "TRG7,Trigger bit k." "0,1" newline bitfld.long 0x4 6. "TRG6,Trigger bit k." "0,1" newline bitfld.long 0x4 5. "TRG5,Trigger bit k." "0,1" newline bitfld.long 0x4 4. "TRG4,Trigger bit k." "0,1" newline bitfld.long 0x4 3. "TRG3,Trigger bit k." "0,1" newline bitfld.long 0x4 2. "TRG2,Trigger bit k." "0,1" newline bitfld.long 0x4 1. "TRG1,Trigger bit k." "0,1" newline bitfld.long 0x4 0. "TRG0,Trigger bit k." "0,1" group.long 0x2F00++0x13 line.long 0x0 "MCS1_CTRL_STAT," bitfld.long 0x0 26. "HLT_AEIM_ERR,Halt on AEI bus master error." "0,1" newline bitfld.long 0x0 25. "EN_HVD,Enable Modified Harvard architecture." "0,1" newline bitfld.long 0x0 24. "EN_TIM_FOUT,Enable routing of TIM[i]_CH[x]_F_OUT signal." "0,1" newline bitfld.long 0x0 20.--22. "ERR_SRC_ID,Error source identifier." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "RAM_RST,RAM reset bit." "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "SCD_CH,Channel selection for scheduling algorithm." newline bitfld.long 0x0 0.--1. "SCD_MODE,Select MCS scheduling mode" "0,1,2,3" line.long 0x4 "MCS1_RESET," bitfld.long 0x4 7. "RST7,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 6. "RST6,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 5. "RST5,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 4. "RST4,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 3. "RST3,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 2. "RST2,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 1. "RST1,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 0. "RST0,Software reset of channel [k]" "0,1" line.long 0x8 "MCS1_CAT," bitfld.long 0x8 7. "CAT7,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 6. "CAT6,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 5. "CAT5,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 4. "CAT4,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 3. "CAT3,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 2. "CAT2,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 1. "CAT1,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 0. "CAT0,Cancel ARU transfer of channel [k]." "0,1" line.long 0xC "MCS1_CWT," bitfld.long 0xC 7. "CWT7,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 6. "CWT6,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 5. "CWT5,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 4. "CWT4,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 3. "CWT3,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 2. "CWT2,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 1. "CWT1,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 0. "CWT0,Cancel waiting instruction for channel [k]." "0,1" line.long 0x10 "MCS1_ERR," bitfld.long 0x10 7. "ERR7,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 6. "ERR6,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 5. "ERR5,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 4. "ERR4,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 3. "ERR3,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 2. "ERR2,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 1. "ERR1,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 0. "ERR0,Error State of MCS-channel [k]." "0,1" group.long 0x2F1C++0x13 line.long 0x0 "MCS1_REG_PROT," bitfld.long 0x0 14.--15. "WPROT7,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 12.--13. "WPROT6,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 10.--11. "WPROT5,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 8.--9. "WPROT4,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 6.--7. "WPROT3,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 4.--5. "WPROT2,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 2.--3. "WPROT1,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 0.--1. "WPROT0,Register Write Protection of MCS-channel k." "0,1,2,3" line.long 0x4 "MCS1_SINT_IRQ_NOTIFY," bitfld.long 0x4 7. "S_IRQ7,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 6. "S_IRQ6,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 5. "S_IRQ5,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 4. "S_IRQ4,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 3. "S_IRQ3,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 2. "S_IRQ2,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 1. "S_IRQ1,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 0. "S_IRQ0,Shared interrupt [k] notify flag." "0,1" line.long 0x8 "MCS1_SINT_IRQ_EN," bitfld.long 0x8 7. "S_IRQ7_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 6. "S_IRQ6_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 5. "S_IRQ5_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 4. "S_IRQ4_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 3. "S_IRQ3_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 2. "S_IRQ2_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 1. "S_IRQ1_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 0. "S_IRQ0_EN,Shared interrupt [k]" "0,1" line.long 0xC "MCS1_SINT_IRQ_FORCINT," bitfld.long 0xC 7. "TRG_S_IRQ7,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 6. "TRG_S_IRQ6,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 5. "TRG_S_IRQ5,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 4. "TRG_S_IRQ4,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 3. "TRG_S_IRQ3,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 2. "TRG_S_IRQ2,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 1. "TRG_S_IRQ1,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 0. "TRG_S_IRQ0,Trigger IRQ [k] in shared interrupt register" "0,1" line.long 0x10 "MCS1_SINT_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x2F40++0x1B line.long 0x0 "MCS1_HBP0_CTRL," bitfld.long 0x0 17. "NOT,Logical negation of h-th hardware break point." "0,1" newline bitfld.long 0x0 16. "AND,Logical AND conjunction of h-th hardware break point." "0,1" newline bitfld.long 0x0 12.--14. "TYPE,Define type of h-th hardware break point." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--9. "SCOPE,Define scope of h-th hardware break point." "0,1,2,3" newline bitfld.long 0x0 7. "EN_CH7,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 6. "EN_CH6,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 5. "EN_CH5,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 4. "EN_CH4,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 3. "EN_CH3,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 2. "EN_CH2,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 1. "EN_CH1,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 0. "EN_CH0,Enable h-th hardware break point for channel x." "0,1" line.long 0x4 "MCS1_HBP0_PATTERN," hexmask.long 0x4 0.--31. 1. "DATA,Define pattern or address of h-th hardware break point." line.long 0x8 "MCS1_HBP0_STATUS," bitfld.long 0x8 7. "HALT_CH7,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 6. "HALT_CH6,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 5. "HALT_CH5,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 4. "HALT_CH4,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 3. "HALT_CH3,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 2. "HALT_CH2,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 1. "HALT_CH1,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 0. "HALT_CH0,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" line.long 0xC "MCS1_HBP0_IRQ_NOTIFY," bitfld.long 0xC 0. "HBP_IRQ,Interrupt notify flag of the h-th hardware break point." "0,1" line.long 0x10 "MCS1_HBP0_IRQ_EN," bitfld.long 0x10 0. "HBP_IRQ_EN,Interrupt Enable bit of the h-th hardware break point." "0,1" line.long 0x14 "MCS1_HBP0_IRQ_FORCINT," bitfld.long 0x14 0. "TRG_HBP_IRQ,Trigger IRQ of the h-th hardware break point." "0,1" line.long 0x18 "MCS1_HBP0_IRQ_MODE," bitfld.long 0x18 0.--1. "IRQ_MODE,IRQ mode selection for all break point interrupts." "0,1,2,3" group.long 0x2F60++0x1B line.long 0x0 "MCS1_HBP1_CTRL," bitfld.long 0x0 17. "NOT,Logical negation of h-th hardware break point." "0,1" newline bitfld.long 0x0 16. "AND,Logical AND conjunction of h-th hardware break point." "0,1" newline bitfld.long 0x0 12.--14. "TYPE,Define type of h-th hardware break point." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--9. "SCOPE,Define scope of h-th hardware break point." "0,1,2,3" newline bitfld.long 0x0 7. "EN_CH7,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 6. "EN_CH6,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 5. "EN_CH5,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 4. "EN_CH4,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 3. "EN_CH3,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 2. "EN_CH2,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 1. "EN_CH1,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 0. "EN_CH0,Enable h-th hardware break point for channel x." "0,1" line.long 0x4 "MCS1_HBP1_PATTERN," hexmask.long 0x4 0.--31. 1. "DATA,Define pattern or address of h-th hardware break point." line.long 0x8 "MCS1_HBP1_STATUS," bitfld.long 0x8 7. "HALT_CH7,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 6. "HALT_CH6,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 5. "HALT_CH5,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 4. "HALT_CH4,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 3. "HALT_CH3,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 2. "HALT_CH2,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 1. "HALT_CH1,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 0. "HALT_CH0,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" line.long 0xC "MCS1_HBP1_IRQ_NOTIFY," bitfld.long 0xC 0. "HBP_IRQ,Interrupt notify flag of the h-th hardware break point." "0,1" line.long 0x10 "MCS1_HBP1_IRQ_EN," bitfld.long 0x10 0. "HBP_IRQ_EN,Interrupt Enable bit of the h-th hardware break point." "0,1" line.long 0x14 "MCS1_HBP1_IRQ_FORCINT," bitfld.long 0x14 0. "TRG_HBP_IRQ,Trigger IRQ of the h-th hardware break point." "0,1" line.long 0x18 "MCS1_HBP1_IRQ_MODE," bitfld.long 0x18 0.--1. "IRQ_MODE,IRQ mode selection for all break point interrupts." "0,1,2,3" group.long 0x3000++0x13 line.long 0x0 "TIO1_G0_CH0_CTRL," bitfld.long 0x0 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x0 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x0 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x0 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x0 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x0 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x0 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x0 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x0 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x0 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x0 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x0 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x0 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x0 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x0 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x0 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x0 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x0 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x0 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x0 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x0 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x4 "TIO1_G0_CH0_IRQ_NOTIFY," bitfld.long 0x4 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x4 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x4 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x4 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x4 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x4 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x8 "TIO1_G0_CH0_IRQ_EN," bitfld.long 0x8 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x8 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x8 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x8 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x8 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x8 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0xC "TIO1_G0_CH0_IRQ_FORCINT," bitfld.long 0xC 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0xC 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0xC 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0xC 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0xC 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0xC 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x10 "TIO1_G0_CH0_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3020++0xB line.long 0x0 "TIO1_G0_CH0_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO1_G0_CH0_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO1_G0_CH0_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3030++0x23 line.long 0x0 "TIO1_G0_CH0_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO1_G0_CH0_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO1_G0_CH0_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO1_G0_CH0_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO1_G0_CH1_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO1_G0_CH1_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO1_G0_CH1_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO1_G0_CH1_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO1_G0_CH1_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3060++0xB line.long 0x0 "TIO1_G0_CH1_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO1_G0_CH1_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO1_G0_CH1_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3070++0x23 line.long 0x0 "TIO1_G0_CH1_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO1_G0_CH1_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO1_G0_CH1_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO1_G0_CH1_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO1_G0_CH2_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO1_G0_CH2_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO1_G0_CH2_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO1_G0_CH2_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO1_G0_CH2_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x30A0++0xB line.long 0x0 "TIO1_G0_CH2_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO1_G0_CH2_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO1_G0_CH2_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x30B0++0x23 line.long 0x0 "TIO1_G0_CH2_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO1_G0_CH2_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO1_G0_CH2_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO1_G0_CH2_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO1_G0_CH3_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO1_G0_CH3_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO1_G0_CH3_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO1_G0_CH3_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO1_G0_CH3_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x30E0++0xB line.long 0x0 "TIO1_G0_CH3_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO1_G0_CH3_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO1_G0_CH3_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x30F0++0x23 line.long 0x0 "TIO1_G0_CH3_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO1_G0_CH3_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO1_G0_CH3_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO1_G0_CH3_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO1_G0_CH4_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO1_G0_CH4_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO1_G0_CH4_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO1_G0_CH4_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO1_G0_CH4_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3120++0xB line.long 0x0 "TIO1_G0_CH4_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO1_G0_CH4_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO1_G0_CH4_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3130++0x23 line.long 0x0 "TIO1_G0_CH4_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO1_G0_CH4_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO1_G0_CH4_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO1_G0_CH4_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO1_G0_CH5_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO1_G0_CH5_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO1_G0_CH5_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO1_G0_CH5_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO1_G0_CH5_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3160++0xB line.long 0x0 "TIO1_G0_CH5_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO1_G0_CH5_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO1_G0_CH5_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3170++0x23 line.long 0x0 "TIO1_G0_CH5_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO1_G0_CH5_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO1_G0_CH5_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO1_G0_CH5_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO1_G0_CH6_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO1_G0_CH6_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO1_G0_CH6_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO1_G0_CH6_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO1_G0_CH6_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x31A0++0xB line.long 0x0 "TIO1_G0_CH6_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO1_G0_CH6_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO1_G0_CH6_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x31B0++0x23 line.long 0x0 "TIO1_G0_CH6_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO1_G0_CH6_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO1_G0_CH6_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO1_G0_CH6_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO1_G0_CH7_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO1_G0_CH7_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO1_G0_CH7_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO1_G0_CH7_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO1_G0_CH7_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x31E0++0xB line.long 0x0 "TIO1_G0_CH7_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO1_G0_CH7_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO1_G0_CH7_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x31F0++0x17 line.long 0x0 "TIO1_G0_CH7_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO1_G0_CH7_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO1_G0_CH7_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO1_G0_CH7_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO1_G0_ISEL0_CTRL1," bitfld.long 0x10 27. "WRITE_EN3,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 26. "WRITE_EN2,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 25. "WRITE_EN1,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 24. "WRITE_EN0,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 19. "OUT_SEL3,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x10 18. "OUT_SEL2,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x10 17. "OUT_SEL1,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x10 16. "OUT_SEL0,select signal for ISEL_OUT[k]" "0,1" newline hexmask.long.byte 0x10 12.--15. 1. "LUT2_3,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x10 8.--11. 1. "LUT2_2,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x10 4.--7. 1. "LUT2_1,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x10 0.--3. 1. "LUT2_0,2 bit Lookup table function for channel c=q*4+k" line.long 0x14 "TIO1_G0_ISEL0_CTRL2," bitfld.long 0x14 22. "LUT3IN_SEL2,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x14 21. "LUT3IN_SEL1,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x14 20. "LUT3IN_SEL0,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x14 16.--17. "QOUT_SEL,select source for ISEL_QOUT signal in quad = q" "0,1,2,3" newline hexmask.long.byte 0x14 0.--7. 1. "LUT3,3 bit Lookup table function for quad=q; channels q*4+2 .. q*4" group.long 0x3220++0x7 line.long 0x0 "TIO1_G0_ISEL1_CTRL1," bitfld.long 0x0 27. "WRITE_EN3,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 26. "WRITE_EN2,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 25. "WRITE_EN1,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 24. "WRITE_EN0,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 19. "OUT_SEL3,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x0 18. "OUT_SEL2,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x0 17. "OUT_SEL1,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x0 16. "OUT_SEL0,select signal for ISEL_OUT[k]" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "LUT2_3,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x0 8.--11. 1. "LUT2_2,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x0 4.--7. 1. "LUT2_1,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x0 0.--3. 1. "LUT2_0,2 bit Lookup table function for channel c=q*4+k" line.long 0x4 "TIO1_G0_ISEL1_CTRL2," bitfld.long 0x4 22. "LUT3IN_SEL2,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x4 21. "LUT3IN_SEL1,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x4 20. "LUT3IN_SEL0,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x4 16.--17. "QOUT_SEL,select source for ISEL_QOUT signal in quad = q" "0,1,2,3" newline hexmask.long.byte 0x4 0.--7. 1. "LUT3,3 bit Lookup table function for quad=q; channels q*4+2 .. q*4" group.long 0x3240++0x3 line.long 0x0 "TIO1_G0_OP_USAGE," bitfld.long 0x0 31. "WRITE_EN7,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 30. "WRITE_EN6,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 29. "WRITE_EN5,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 28. "WRITE_EN4,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 27. "WRITE_EN3,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 26. "WRITE_EN2,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 25. "WRITE_EN1,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 24. "WRITE_EN0,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 21.--23. "MODE7,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "MODE6,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15.--17. "MODE5,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "MODE4,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9.--11. "MODE3,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "MODE2,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "MODE1,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "MODE0,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" group.long 0x3C00++0x1F line.long 0x0 "TIO1_S," bitfld.long 0x0 7. "CH7,Value of channel x." "0,1" newline bitfld.long 0x0 6. "CH6,Value of channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Value of channel x." "0,1" newline bitfld.long 0x0 4. "CH4,Value of channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Value of channel x." "0,1" newline bitfld.long 0x0 2. "CH2,Value of channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Value of channel x." "0,1" newline bitfld.long 0x0 0. "CH0,Value of channel x." "0,1" line.long 0x4 "TIO1_O," bitfld.long 0x4 7. "CH7,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 6. "CH6,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 4. "CH4,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 2. "CH2,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 0. "CH0,Value driven on output of channel x." "0,1" line.long 0x8 "TIO1_ENDIS," bitfld.long 0x8 7. "CH7,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 6. "CH6,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 4. "CH4,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 2. "CH2,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 0. "CH0,Enable/Disable request of channel x." "0,1" line.long 0xC "TIO1_INVERT," bitfld.long 0xC 7. "CH7,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 6. "CH6,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 4. "CH4,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 2. "CH2,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 0. "CH0,Enable/Disable signal inversion of channel x." "0,1" line.long 0x10 "TIO1_INPUT_MODE," bitfld.long 0x10 7. "CH7,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 6. "CH6,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 4. "CH4,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 2. "CH2,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 0. "CH0,Enable/Disable input mode of channel x." "0,1" line.long 0x14 "TIO1_CYCLIC_MODE," bitfld.long 0x14 7. "CH7,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 6. "CH6,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 4. "CH4,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 2. "CH2,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 0. "CH0,Enable/Disable cyclic mode of channel x." "0,1" line.long 0x18 "TIO1_TRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 6. "CH6,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 4. "CH4,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 2. "CH2,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 0. "CH0,enable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO1_PLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 6. "CH6,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 4. "CH4,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 2. "CH2,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 0. "CH0,enable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3C40++0x1F line.long 0x0 "TIO1_CS," bitfld.long 0x0 7. "CH7,Clear channel x." "0,1" newline bitfld.long 0x0 6. "CH6,Clear channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Clear channel x." "0,1" newline bitfld.long 0x0 4. "CH4,Clear channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Clear channel x." "0,1" newline bitfld.long 0x0 2. "CH2,Clear channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Clear channel x." "0,1" newline bitfld.long 0x0 0. "CH0,Clear channel x." "0,1" line.long 0x4 "TIO1_CO," bitfld.long 0x4 7. "CH7,Clear channel x." "0,1" newline bitfld.long 0x4 6. "CH6,Clear channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Clear channel x." "0,1" newline bitfld.long 0x4 4. "CH4,Clear channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Clear channel x." "0,1" newline bitfld.long 0x4 2. "CH2,Clear channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Clear channel x." "0,1" newline bitfld.long 0x4 0. "CH0,Clear channel x." "0,1" line.long 0x8 "TIO1_CENDIS," bitfld.long 0x8 7. "CH7,Disable request of channel x." "0,1" newline bitfld.long 0x8 6. "CH6,Disable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Disable request of channel x." "0,1" newline bitfld.long 0x8 4. "CH4,Disable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Disable request of channel x." "0,1" newline bitfld.long 0x8 2. "CH2,Disable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Disable request of channel x." "0,1" newline bitfld.long 0x8 0. "CH0,Disable request of channel x." "0,1" line.long 0xC "TIO1_CINVERT," bitfld.long 0xC 7. "CH7,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 6. "CH6,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 4. "CH4,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 2. "CH2,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 0. "CH0,Disable signal inversion of channel x." "0,1" line.long 0x10 "TIO1_CINPUT_MODE," bitfld.long 0x10 7. "CH7,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 6. "CH6,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 4. "CH4,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 2. "CH2,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 0. "CH0,Disable input mode of channel x." "0,1" line.long 0x14 "TIO1_CCYCLIC_MODE," bitfld.long 0x14 7. "CH7,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 6. "CH6,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 4. "CH4,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 2. "CH2,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 0. "CH0,Disable cyclic mode of channel x." "0,1" line.long 0x18 "TIO1_CTRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 6. "CH6,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 4. "CH4,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 2. "CH2,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 0. "CH0,disable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO1_CPLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 6. "CH6,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 4. "CH4,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 2. "CH2,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 0. "CH0,disable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3C80++0x1F line.long 0x0 "TIO1_SS," bitfld.long 0x0 7. "CH7,Set channel x." "0,1" newline bitfld.long 0x0 6. "CH6,Set channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Set channel x." "0,1" newline bitfld.long 0x0 4. "CH4,Set channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Set channel x." "0,1" newline bitfld.long 0x0 2. "CH2,Set channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Set channel x." "0,1" newline bitfld.long 0x0 0. "CH0,Set channel x." "0,1" line.long 0x4 "TIO1_SO," bitfld.long 0x4 7. "CH7,Set channel x." "0,1" newline bitfld.long 0x4 6. "CH6,Set channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Set channel x." "0,1" newline bitfld.long 0x4 4. "CH4,Set channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Set channel x." "0,1" newline bitfld.long 0x4 2. "CH2,Set channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Set channel x." "0,1" newline bitfld.long 0x4 0. "CH0,Set channel x." "0,1" line.long 0x8 "TIO1_SENDIS," bitfld.long 0x8 7. "CH7,Enable request of channel x." "0,1" newline bitfld.long 0x8 6. "CH6,Enable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Enable request of channel x." "0,1" newline bitfld.long 0x8 4. "CH4,Enable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Enable request of channel x." "0,1" newline bitfld.long 0x8 2. "CH2,Enable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Enable request of channel x." "0,1" newline bitfld.long 0x8 0. "CH0,Enable request of channel x." "0,1" line.long 0xC "TIO1_SINVERT," bitfld.long 0xC 7. "CH7,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 6. "CH6,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 4. "CH4,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 2. "CH2,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 0. "CH0,Enable signal inversion of channel x." "0,1" line.long 0x10 "TIO1_SINPUT_MODE," bitfld.long 0x10 7. "CH7,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 6. "CH6,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 4. "CH4,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 2. "CH2,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 0. "CH0,Enable input mode of channel x." "0,1" line.long 0x14 "TIO1_SCYCLIC_MODE," bitfld.long 0x14 7. "CH7,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 6. "CH6,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 4. "CH4,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 2. "CH2,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 0. "CH0,Enable cyclic mode of channel x." "0,1" line.long 0x18 "TIO1_STRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 6. "CH6,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 4. "CH4,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 2. "CH2,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 0. "CH0,enable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO1_SPLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 6. "CH6,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 4. "CH4,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 2. "CH2,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 0. "CH0,enable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3CC0++0x17 line.long 0x0 "TIO1_IS," bitfld.long 0x0 7. "CH7,Invert channel x." "0,1" newline bitfld.long 0x0 6. "CH6,Invert channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Invert channel x." "0,1" newline bitfld.long 0x0 4. "CH4,Invert channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Invert channel x." "0,1" newline bitfld.long 0x0 2. "CH2,Invert channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Invert channel x." "0,1" newline bitfld.long 0x0 0. "CH0,Invert channel x." "0,1" line.long 0x4 "TIO1_IO," bitfld.long 0x4 7. "CH7,Invert channel x." "0,1" newline bitfld.long 0x4 6. "CH6,Invert channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Invert channel x." "0,1" newline bitfld.long 0x4 4. "CH4,Invert channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Invert channel x." "0,1" newline bitfld.long 0x4 2. "CH2,Invert channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Invert channel x." "0,1" newline bitfld.long 0x4 0. "CH0,Invert channel x." "0,1" line.long 0x8 "TIO1_IENDIS," bitfld.long 0x8 7. "CH7,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 6. "CH6,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 4. "CH4,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 2. "CH2,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 0. "CH0,Toggle state request of channel x." "0,1" line.long 0xC "TIO1_IINVERT," bitfld.long 0xC 7. "CH7,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 6. "CH6,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 4. "CH4,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 2. "CH2,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 0. "CH0,Invert signal inversion of channel x." "0,1" line.long 0x10 "TIO1_IINPUT_MODE," bitfld.long 0x10 7. "CH7,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 6. "CH6,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 4. "CH4,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 2. "CH2,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 0. "CH0,Toggle input mode of channel x." "0,1" line.long 0x14 "TIO1_ICYCLIC_MODE," bitfld.long 0x14 7. "CH7,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 6. "CH6,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 4. "CH4,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 2. "CH2,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 0. "CH0,Toggle cyclic mode of channel x." "0,1" group.long 0x3D00++0x13 line.long 0x0 "TIO1_FUPD," bitfld.long 0x0 7. "CH7,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 6. "CH6,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 5. "CH5,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 4. "CH4,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 3. "CH3,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 2. "CH2,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 1. "CH1,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 0. "CH0,issue immediately a signal pulse on the update signal of channel x" "0,1" line.long 0x4 "TIO1_HW_CONF," bitfld.long 0x4 4. "TIO_PLUS,signals availablity of TIOplus functionality" "0,1" newline bitfld.long 0x4 0.--1. "NTIO_CH8,signals availablity of amount of channels" "0,1,2,3" line.long 0x8 "TIO1_RSEL_CTRL1," bitfld.long 0x8 28. "SEL_CLKEN7_0,select source of RS_CLKEN7[g][7] for channels g*8 .. g*8+7" "0,1" newline bitfld.long 0x8 24. "SEL_CLKEN6_0,select source of RS_CLKEN[g][6] for channels g*8 .. g*8+7" "0,1" line.long 0xC "TIO1_RSEL_CTRL2," bitfld.long 0xC 8. "SEL_TB2_0,select source of RS_TB2[g] for channels g*8 .. g*8+7" "0,1" newline bitfld.long 0xC 4. "SEL_TB1_0,select source of RS_TB1[g] for channels g*8 .. g*8+7" "0,1" line.long 0x10 "TIO1_PL_SWRST," bitfld.long 0x10 7. "CH7,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 6. "CH6,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 5. "CH5,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 4. "CH4,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 3. "CH3,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 2. "CH2,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 1. "CH1,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 0. "CH0,reset TIO_Plus resources of channel x" "0,1" group.long 0x4000++0x4F line.long 0x0 "CCM1_ARP0_CTRL," bitfld.long 0x0 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x0 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x0 0.--15. 1. "ADDR,ARP base address." line.long 0x4 "CCM1_ARP0_PROT," bitfld.long 0x4 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x8 "CCM1_ARP1_CTRL," bitfld.long 0x8 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x8 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x8 0.--15. 1. "ADDR,ARP base address." line.long 0xC "CCM1_ARP1_PROT," bitfld.long 0xC 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x10 "CCM1_ARP2_CTRL," bitfld.long 0x10 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x10 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x10 0.--15. 1. "ADDR,ARP base address." line.long 0x14 "CCM1_ARP2_PROT," bitfld.long 0x14 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x18 "CCM1_ARP3_CTRL," bitfld.long 0x18 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x18 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x18 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x18 0.--15. 1. "ADDR,ARP base address." line.long 0x1C "CCM1_ARP3_PROT," bitfld.long 0x1C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x20 "CCM1_ARP4_CTRL," bitfld.long 0x20 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x20 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x20 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x20 0.--15. 1. "ADDR,ARP base address." line.long 0x24 "CCM1_ARP4_PROT," bitfld.long 0x24 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x28 "CCM1_ARP5_CTRL," bitfld.long 0x28 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x28 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x28 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x28 0.--15. 1. "ADDR,ARP base address." line.long 0x2C "CCM1_ARP5_PROT," bitfld.long 0x2C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x30 "CCM1_ARP6_CTRL," bitfld.long 0x30 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x30 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x30 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x30 0.--15. 1. "ADDR,ARP base address." line.long 0x34 "CCM1_ARP6_PROT," bitfld.long 0x34 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x38 "CCM1_ARP7_CTRL," bitfld.long 0x38 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x38 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x38 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x38 0.--15. 1. "ADDR,ARP base address." line.long 0x3C "CCM1_ARP7_PROT," bitfld.long 0x3C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x40 "CCM1_ARP8_CTRL," bitfld.long 0x40 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x40 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x40 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x40 0.--15. 1. "ADDR,ARP base address." line.long 0x44 "CCM1_ARP8_PROT," bitfld.long 0x44 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x48 "CCM1_ARP9_CTRL," bitfld.long 0x48 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x48 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x48 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x48 0.--15. 1. "ADDR,ARP base address." line.long 0x4C "CCM1_ARP9_PROT," bitfld.long 0x4C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 0. "WPROT0,Write Protection MCS channel x." "0,1" group.long 0x41CC++0x3 line.long 0x0 "CCM1_TIO_G0_OUT," bitfld.long 0x0 31. "TIO_G1_OUT_N7,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 30. "TIO_G1_OUT_N6,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 29. "TIO_G1_OUT_N5,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 28. "TIO_G1_OUT_N4,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 27. "TIO_G1_OUT_N3,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 26. "TIO_G1_OUT_N2,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 25. "TIO_G1_OUT_N1,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 24. "TIO_G1_OUT_N0,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 23. "TIO_G0_OUT_N7,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 22. "TIO_G0_OUT_N6,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 21. "TIO_G0_OUT_N5,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 20. "TIO_G0_OUT_N4,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 19. "TIO_G0_OUT_N3,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 18. "TIO_G0_OUT_N2,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 17. "TIO_G0_OUT_N1,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 16. "TIO_G0_OUT_N0,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 15. "TIO_G1_OUT7,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 14. "TIO_G1_OUT6,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 13. "TIO_G1_OUT5,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 12. "TIO_G1_OUT4,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 11. "TIO_G1_OUT3,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 10. "TIO_G1_OUT2,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 9. "TIO_G1_OUT1,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 8. "TIO_G1_OUT0,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 7. "TIO_G0_OUT7,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 6. "TIO_G0_OUT6,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 5. "TIO_G0_OUT5,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 4. "TIO_G0_OUT4,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 3. "TIO_G0_OUT3,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 2. "TIO_G0_OUT2,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 1. "TIO_G0_OUT1,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 0. "TIO_G0_OUT0,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" group.long 0x41D4++0x2B line.long 0x0 "CCM1_HW_CONF2," bitfld.long 0x0 18. "AXIM_DATA_SIZE,Defines the data bus width of the AXI master interface" "0,1" newline bitfld.long 0x0 16. "AXIS_DATA_SIZE,Defines the data bus width of the AXI slave interface" "0,1" newline bitfld.long 0x0 9. "TIO_OUT_RST,TIO_OUT reset level" "0,1" newline bitfld.long 0x0 7. "AXIM_POSTED_WRITE,Write transaction without response" "0,1" newline bitfld.long 0x0 6. "AXIM_SEC_ACC,Secure AXI master access constant" "0,1" newline bitfld.long 0x0 5. "AXIM_PRIV_ACC,Privileged AXI master access constant" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "AXIM_ID_WIDTH,Defines which LSB of AXIM_ID are send to the bus" line.long 0x4 "CCM1_AEIM_STA," bitfld.long 0x4 24.--25. "AEIM_XPT_STA,AEIM Exception status." "0,1,2,3" newline hexmask.long.word 0x4 0.--15. 1. "AEIM_XPT_ADDR,Exception Address." line.long 0x8 "CCM1_HW_CONF," bitfld.long 0x8 31. "AEI_RDATA_PIPELINE_STAGE,Read data pipeline stage implemented" "0,1" newline bitfld.long 0x8 30. "AEI_ADDR_PIPELINE_STAGE,Address pipeline stage implemented" "0,1" newline bitfld.long 0x8 29. "INT_CLK_EN_GEN,Internal clock enable generation" "0,1" newline hexmask.long.byte 0x8 24.--28. 1. "TOM_TRIG_INTCHAIN,TOM internal trigger chain length without synchronization register" newline hexmask.long.byte 0x8 20.--23. 1. "ATOM_TRIG_INTCHAIN,ATOM internal trigger chain length without synchronization register" newline bitfld.long 0x8 19. "IRQ_MODE_SINGLE_PULSE,Signalize availability of Single Pulse IRQ mode" "0,1" newline bitfld.long 0x8 18. "IRQ_MODE_PULSE_NOTIFY,Signalize availability of Pulse Notoify IRQ mode" "0,1" newline bitfld.long 0x8 17. "IRQ_MODE_PULSE,Signalize availability of Pulse IRQ mode" "0,1" newline bitfld.long 0x8 16. "IRQ_MODE_LEVEL,Signalize availability of Level IRQ mode" "0,1" newline bitfld.long 0x8 15. "RESET_ACTIVE,Active level of asynchronous reset" "0,1" newline bitfld.long 0x8 13. "ERM,Enable RAM1 MSB for available MCS modules" "0,1" newline bitfld.long 0x8 12. "RAM_INIT_RST,RAM initialization from reset" "0,1" newline bitfld.long 0x8 9.--11. "TOM_TRIG_CHAIN,TOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "TOM_OUT_RST,TOM_OUT reset level" "0,1" newline bitfld.long 0x8 5.--7. "ATOM_TRIG_CHAIN,ATOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "ATOM_OUT_RST,ATOM_OUT reset level" "0,1" newline bitfld.long 0x8 3. "CFG_CLOCK_RATE,Clocks per ARU transfer" "0,1" newline bitfld.long 0x8 2. "SYNC_INPUT_REG,Additional pipelined stage in synchronous bridge mode" "0,1" newline bitfld.long 0x8 1. "BRIDGE_MODE_RST,Bridge mode after reset" "0,1" newline bitfld.long 0x8 0. "GRSTEN,Global Reset Enable" "0,1" line.long 0xC "CCM1_TIM_AUX_IN_SRC," bitfld.long 0xC 23. "SEL_OUT_N_CH7,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 22. "SEL_OUT_N_CH6,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 21. "SEL_OUT_N_CH5,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 20. "SEL_OUT_N_CH4,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 19. "SEL_OUT_N_CH3,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 18. "SEL_OUT_N_CH2,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 17. "SEL_OUT_N_CH1,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 16. "SEL_OUT_N_CH0,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 7. "SRC_CH7,Defines AUX_IN source of TIM[i] channel 7" "0,1" newline bitfld.long 0xC 6. "SRC_CH6,Defines AUX_IN source of TIM[i] channel 6" "0,1" newline bitfld.long 0xC 5. "SRC_CH5,Defines AUX_IN source of TIM[i] channel 5" "0,1" newline bitfld.long 0xC 4. "SRC_CH4,Defines AUX_IN source of TIM[i] channel 4" "0,1" newline bitfld.long 0xC 3. "SRC_CH3,Defines AUX_IN source of TIM[i] channel 3" "0,1" newline bitfld.long 0xC 2. "SRC_CH2,Defines AUX_IN source of TIM[i] channel 2" "0,1" newline bitfld.long 0xC 1. "SRC_CH1,Defines AUX_IN source of TIM[i] channel 1" "0,1" newline bitfld.long 0xC 0. "SRC_CH0,Defines AUX_IN source of TIM[i] channel 0" "0,1" line.long 0x10 "CCM1_EXT_CAP_EN," bitfld.long 0x10 15. "TIM_IP1_EXT_CAP_EN7,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 14. "TIM_IP1_EXT_CAP_EN6,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 13. "TIM_IP1_EXT_CAP_EN5,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 12. "TIM_IP1_EXT_CAP_EN4,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 11. "TIM_IP1_EXT_CAP_EN3,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 10. "TIM_IP1_EXT_CAP_EN2,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 9. "TIM_IP1_EXT_CAP_EN1,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 8. "TIM_IP1_EXT_CAP_EN0,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 7. "TIM_I_EXT_CAP_EN7,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 6. "TIM_I_EXT_CAP_EN6,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 5. "TIM_I_EXT_CAP_EN5,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 4. "TIM_I_EXT_CAP_EN4,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 3. "TIM_I_EXT_CAP_EN3,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 2. "TIM_I_EXT_CAP_EN2,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 1. "TIM_I_EXT_CAP_EN1,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 0. "TIM_I_EXT_CAP_EN0,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" line.long 0x14 "CCM1_TOM_OUT," bitfld.long 0x14 31. "TOM_OUT_N15,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 30. "TOM_OUT_N14,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 29. "TOM_OUT_N13,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 28. "TOM_OUT_N12,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 27. "TOM_OUT_N11,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 26. "TOM_OUT_N10,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 25. "TOM_OUT_N9,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 24. "TOM_OUT_N8,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 23. "TOM_OUT_N7,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 22. "TOM_OUT_N6,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 21. "TOM_OUT_N5,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 20. "TOM_OUT_N4,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 19. "TOM_OUT_N3,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 18. "TOM_OUT_N2,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 17. "TOM_OUT_N1,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 16. "TOM_OUT_N0,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 15. "TOM_OUT15,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 14. "TOM_OUT14,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 13. "TOM_OUT13,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 12. "TOM_OUT12,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 11. "TOM_OUT11,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 10. "TOM_OUT10,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 9. "TOM_OUT9,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 8. "TOM_OUT8,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 7. "TOM_OUT7,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 6. "TOM_OUT6,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 5. "TOM_OUT5,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 4. "TOM_OUT4,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 3. "TOM_OUT3,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 2. "TOM_OUT2,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 1. "TOM_OUT1,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 0. "TOM_OUT0,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" line.long 0x18 "CCM1_ATOM_OUT," bitfld.long 0x18 31. "ATOM_IP1_OUT_N7,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 30. "ATOM_IP1_OUT_N6,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 29. "ATOM_IP1_OUT_N5,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 28. "ATOM_IP1_OUT_N4,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 27. "ATOM_IP1_OUT_N3,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 26. "ATOM_IP1_OUT_N2,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 25. "ATOM_IP1_OUT_N1,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 24. "ATOM_IP1_OUT_N0,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 23. "ATOM_IP1_OUT7,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 22. "ATOM_IP1_OUT6,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 21. "ATOM_IP1_OUT5,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 20. "ATOM_IP1_OUT4,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 19. "ATOM_IP1_OUT3,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 18. "ATOM_IP1_OUT2,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 17. "ATOM_IP1_OUT1,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 16. "ATOM_IP1_OUT0,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 15. "ATOM_I_OUT_N7,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 14. "ATOM_I_OUT_N6,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 13. "ATOM_I_OUT_N5,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 12. "ATOM_I_OUT_N4,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 11. "ATOM_I_OUT_N3,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 10. "ATOM_I_OUT_N2,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 9. "ATOM_I_OUT_N1,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 8. "ATOM_I_OUT_N0,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 7. "ATOM_I_OUT7,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 6. "ATOM_I_OUT6,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 5. "ATOM_I_OUT5,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 4. "ATOM_I_OUT4,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 3. "ATOM_I_OUT3,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 2. "ATOM_I_OUT2,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 1. "ATOM_I_OUT1,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 0. "ATOM_I_OUT0,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" line.long 0x1C "CCM1_CMU_CLK_CFG," bitfld.long 0x1C 28.--29. "CLK7_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 24.--25. "CLK6_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 20.--21. "CLK5_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 16.--17. "CLK4_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 12.--13. "CLK3_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 8.--9. "CLK2_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 4.--5. "CLK1_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "CLK0_SRC,Clock y source signal selector" "0,1,2,3" line.long 0x20 "CCM1_CMU_FXCLK_CFG," hexmask.long.byte 0x20 0.--3. 1. "FXCLK0_SRC,Fixed clock 0 source signal selector" line.long 0x24 "CCM1_CFG," bitfld.long 0x24 31. "TBU_DIR2,DIR1 input signal of module TBU timebase [z]." "0,1" newline bitfld.long 0x24 30. "TBU_DIR1,DIR1 input signal of module TBU timebase [z]." "0,1" newline bitfld.long 0x24 16.--17. "CLS_CLK_DIV,Cluster Clock Divider." "0,1,2,3" newline bitfld.long 0x24 8. "EN_TIO_DTM,Enable TIO and connected DTM" "0,1" newline bitfld.long 0x24 7. "EN_CMP_MON,Enable CMP and MON" "0,1" newline bitfld.long 0x24 6. "EN_PSM,Enable PSM" "0,1" newline bitfld.long 0x24 5. "EN_BRC,Enable BRC" "0,1" newline bitfld.long 0x24 4. "EN_DPLL_MAP,Enable DPLL and MAP" "0,1" newline bitfld.long 0x24 3. "EN_MCS,Enable MCS" "0,1" newline bitfld.long 0x24 2. "EN_ATOM_ADTM,Enable ATOM and ADTM" "0,1" newline bitfld.long 0x24 1. "EN_TOM_SPE_TDTM,Enable TOM SPE and TDTM" "0,1" newline bitfld.long 0x24 0. "EN_TIM,Enable TIM" "0,1" line.long 0x28 "CCM1_PROT," bitfld.long 0x28 0. "CLS_PROT,Cluster Protection" "0,1" group.long 0x4400++0x7F line.long 0x0 "CDTM1_DTM0_CTRL," bitfld.long 0x0 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x0 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x0 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x0 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x0 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x4 "CDTM1_DTM0_CH_CTRL1," bitfld.long 0x4 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x4 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x4 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x4 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x4 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x4 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x4 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x4 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x4 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x4 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x4 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x4 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x4 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x4 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x4 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x4 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x4 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x8 "CDTM1_DTM0_CH_CTRL2," bitfld.long 0x8 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x8 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x8 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x8 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x8 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x8 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x8 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x8 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x8 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x8 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x8 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x8 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x8 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x8 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x8 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x8 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x8 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x8 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x8 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x8 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x8 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x8 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x8 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x8 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x8 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x8 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x8 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x8 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x8 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x8 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x8 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x8 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0xC "CDTM1_DTM0_CH_CTRL2_SR," bitfld.long 0xC 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x10 "CDTM1_DTM0_PS_CTRL," bitfld.long 0x10 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x10 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x10 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x10 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x10 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x14 "CDTM1_DTM0_CH0_DTV," bitfld.long 0x14 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x14 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x14 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x18 "CDTM1_DTM0_CH1_DTV," bitfld.long 0x18 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x18 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x18 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x1C "CDTM1_DTM0_CH2_DTV," bitfld.long 0x1C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x1C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x1C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x20 "CDTM1_DTM0_CH3_DTV," bitfld.long 0x20 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x20 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x20 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x24 "CDTM1_DTM0_CH_SR," bitfld.long 0x24 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x24 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x24 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x24 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x24 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x24 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x24 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x24 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x28 "CDTM1_DTM0_CH_CTRL3," bitfld.long 0x28 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x28 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x28 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x28 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x28 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x28 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x28 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x28 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x2C "CDTM1_DTM0_CTRL2," bitfld.long 0x2C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x2C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x2C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x2C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x2C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x2C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x2C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x2C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x2C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x2C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x2C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x2C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x2C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x2C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x2C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x2C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x2C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x2C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x2C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x2C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x30 "CDTM1_DTM0_CH0_DTV_SR," bitfld.long 0x30 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x30 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x30 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x30 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x30 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x30 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x34 "CDTM1_DTM0_CH1_DTV_SR," bitfld.long 0x34 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x34 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x34 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x34 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x34 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x34 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x38 "CDTM1_DTM0_CH2_DTV_SR," bitfld.long 0x38 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x38 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x38 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x38 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x38 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x38 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x3C "CDTM1_DTM0_CH3_DTV_SR," bitfld.long 0x3C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x3C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x3C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x3C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x3C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x3C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x40 "CDTM1_DTM1_CTRL," bitfld.long 0x40 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x40 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x40 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x40 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x40 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x44 "CDTM1_DTM1_CH_CTRL1," bitfld.long 0x44 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x44 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x44 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x44 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x44 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x44 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x44 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x44 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x44 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x44 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x44 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x44 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x44 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x44 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x44 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x44 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x44 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x48 "CDTM1_DTM1_CH_CTRL2," bitfld.long 0x48 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x48 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x48 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x48 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x48 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x48 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x48 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x48 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x48 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x48 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x48 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x48 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x48 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x48 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x48 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x48 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x48 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x48 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x48 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x48 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x48 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x48 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x48 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x48 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x48 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x48 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x48 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x48 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x48 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x48 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x48 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x48 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0x4C "CDTM1_DTM1_CH_CTRL2_SR," bitfld.long 0x4C 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x50 "CDTM1_DTM1_PS_CTRL," bitfld.long 0x50 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x50 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x50 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x50 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x50 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x54 "CDTM1_DTM1_CH0_DTV," bitfld.long 0x54 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x54 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x54 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x58 "CDTM1_DTM1_CH1_DTV," bitfld.long 0x58 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x58 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x58 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x5C "CDTM1_DTM1_CH2_DTV," bitfld.long 0x5C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x5C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x5C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x60 "CDTM1_DTM1_CH3_DTV," bitfld.long 0x60 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x60 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x60 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x64 "CDTM1_DTM1_CH_SR," bitfld.long 0x64 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x64 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x64 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x64 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x64 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x64 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x64 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x64 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x68 "CDTM1_DTM1_CH_CTRL3," bitfld.long 0x68 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x68 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x68 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x68 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x68 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x68 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x68 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x68 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x6C "CDTM1_DTM1_CTRL2," bitfld.long 0x6C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x6C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x6C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x6C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x6C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x6C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x6C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x6C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x6C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x6C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x6C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x6C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x6C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x6C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x6C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x6C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x6C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x6C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x6C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x6C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x70 "CDTM1_DTM1_CH0_DTV_SR," bitfld.long 0x70 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x70 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x70 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x70 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x70 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x70 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x74 "CDTM1_DTM1_CH1_DTV_SR," bitfld.long 0x74 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x74 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x74 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x74 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x74 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x74 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x78 "CDTM1_DTM1_CH2_DTV_SR," bitfld.long 0x78 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x78 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x78 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x78 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x78 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x78 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x7C "CDTM1_DTM1_CH3_DTV_SR," bitfld.long 0x7C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x7C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x7C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x7C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x7C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x7C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" group.long 0x4500++0x7F line.long 0x0 "CDTM1_DTM4_CTRL," bitfld.long 0x0 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x0 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x0 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x0 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x0 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x4 "CDTM1_DTM4_CH_CTRL1," bitfld.long 0x4 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x4 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x4 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x4 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x4 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x4 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x4 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x4 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x4 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x4 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x4 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x4 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x4 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x4 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x4 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x4 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x4 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x8 "CDTM1_DTM4_CH_CTRL2," bitfld.long 0x8 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x8 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x8 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x8 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x8 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x8 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x8 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x8 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x8 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x8 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x8 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x8 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x8 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x8 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x8 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x8 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x8 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x8 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x8 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x8 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x8 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x8 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x8 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x8 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x8 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x8 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x8 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x8 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x8 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x8 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x8 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x8 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0xC "CDTM1_DTM4_CH_CTRL2_SR," bitfld.long 0xC 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x10 "CDTM1_DTM4_PS_CTRL," bitfld.long 0x10 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x10 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x10 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x10 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x10 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x14 "CDTM1_DTM4_CH0_DTV," bitfld.long 0x14 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x14 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x14 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x18 "CDTM1_DTM4_CH1_DTV," bitfld.long 0x18 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x18 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x18 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x1C "CDTM1_DTM4_CH2_DTV," bitfld.long 0x1C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x1C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x1C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x20 "CDTM1_DTM4_CH3_DTV," bitfld.long 0x20 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x20 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x20 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x24 "CDTM1_DTM4_CH_SR," bitfld.long 0x24 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x24 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x24 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x24 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x24 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x24 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x24 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x24 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x28 "CDTM1_DTM4_CH_CTRL3," bitfld.long 0x28 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x28 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x28 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x28 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x28 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x28 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x28 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x28 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x2C "CDTM1_DTM4_CTRL2," bitfld.long 0x2C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x2C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x2C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x2C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x2C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x2C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x2C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x2C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x2C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x2C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x2C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x2C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x2C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x2C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x2C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x2C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x2C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x2C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x2C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x2C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x30 "CDTM1_DTM4_CH0_DTV_SR," bitfld.long 0x30 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x30 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x30 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x30 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x30 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x30 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x34 "CDTM1_DTM4_CH1_DTV_SR," bitfld.long 0x34 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x34 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x34 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x34 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x34 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x34 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x38 "CDTM1_DTM4_CH2_DTV_SR," bitfld.long 0x38 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x38 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x38 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x38 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x38 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x38 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x3C "CDTM1_DTM4_CH3_DTV_SR," bitfld.long 0x3C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x3C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x3C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x3C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x3C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x3C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x40 "CDTM1_DTM5_CTRL," bitfld.long 0x40 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x40 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x40 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x40 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x40 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x44 "CDTM1_DTM5_CH_CTRL1," bitfld.long 0x44 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x44 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x44 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x44 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x44 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x44 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x44 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x44 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x44 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x44 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x44 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x44 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x44 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x44 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x44 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x44 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x44 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x48 "CDTM1_DTM5_CH_CTRL2," bitfld.long 0x48 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x48 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x48 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x48 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x48 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x48 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x48 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x48 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x48 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x48 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x48 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x48 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x48 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x48 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x48 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x48 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x48 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x48 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x48 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x48 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x48 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x48 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x48 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x48 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x48 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x48 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x48 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x48 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x48 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x48 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x48 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x48 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0x4C "CDTM1_DTM5_CH_CTRL2_SR," bitfld.long 0x4C 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x50 "CDTM1_DTM5_PS_CTRL," bitfld.long 0x50 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x50 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x50 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x50 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x50 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x54 "CDTM1_DTM5_CH0_DTV," bitfld.long 0x54 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x54 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x54 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x58 "CDTM1_DTM5_CH1_DTV," bitfld.long 0x58 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x58 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x58 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x5C "CDTM1_DTM5_CH2_DTV," bitfld.long 0x5C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x5C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x5C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x60 "CDTM1_DTM5_CH3_DTV," bitfld.long 0x60 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x60 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x60 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x64 "CDTM1_DTM5_CH_SR," bitfld.long 0x64 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x64 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x64 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x64 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x64 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x64 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x64 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x64 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x68 "CDTM1_DTM5_CH_CTRL3," bitfld.long 0x68 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x68 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x68 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x68 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x68 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x68 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x68 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x68 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x6C "CDTM1_DTM5_CTRL2," bitfld.long 0x6C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x6C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x6C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x6C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x6C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x6C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x6C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x6C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x6C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x6C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x6C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x6C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x6C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x6C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x6C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x6C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x6C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x6C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x6C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x6C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x70 "CDTM1_DTM5_CH0_DTV_SR," bitfld.long 0x70 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x70 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x70 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x70 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x70 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x70 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x74 "CDTM1_DTM5_CH1_DTV_SR," bitfld.long 0x74 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x74 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x74 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x74 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x74 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x74 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x78 "CDTM1_DTM5_CH2_DTV_SR," bitfld.long 0x78 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x78 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x78 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x78 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x78 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x78 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x7C "CDTM1_DTM5_CH3_DTV_SR," bitfld.long 0x7C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x7C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x7C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x7C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x7C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x7C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" group.long 0x4800++0x47 line.long 0x0 "F2A1_CH0_ARU_RD_FIFO," hexmask.long.word 0x0 0.--8. 1. "ADDR,ARU Read address" line.long 0x4 "F2A1_CH1_ARU_RD_FIFO," hexmask.long.word 0x4 0.--8. 1. "ADDR,ARU Read address" line.long 0x8 "F2A1_CH2_ARU_RD_FIFO," hexmask.long.word 0x8 0.--8. 1. "ADDR,ARU Read address" line.long 0xC "F2A1_CH3_ARU_RD_FIFO," hexmask.long.word 0xC 0.--8. 1. "ADDR,ARU Read address" line.long 0x10 "F2A1_CH4_ARU_RD_FIFO," hexmask.long.word 0x10 0.--8. 1. "ADDR,ARU Read address" line.long 0x14 "F2A1_CH5_ARU_RD_FIFO," hexmask.long.word 0x14 0.--8. 1. "ADDR,ARU Read address" line.long 0x18 "F2A1_CH6_ARU_RD_FIFO," hexmask.long.word 0x18 0.--8. 1. "ADDR,ARU Read address" line.long 0x1C "F2A1_CH7_ARU_RD_FIFO," hexmask.long.word 0x1C 0.--8. 1. "ADDR,ARU Read address" line.long 0x20 "F2A1_CH0_STR_CFG," bitfld.long 0x20 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x20 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x24 "F2A1_CH1_STR_CFG," bitfld.long 0x24 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x24 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x28 "F2A1_CH2_STR_CFG," bitfld.long 0x28 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x28 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x2C "F2A1_CH3_STR_CFG," bitfld.long 0x2C 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x2C 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x30 "F2A1_CH4_STR_CFG," bitfld.long 0x30 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x30 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x34 "F2A1_CH5_STR_CFG," bitfld.long 0x34 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x34 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x38 "F2A1_CH6_STR_CFG," bitfld.long 0x38 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x38 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x3C "F2A1_CH7_STR_CFG," bitfld.long 0x3C 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x3C 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x40 "F2A1_ENABLE," bitfld.long 0x40 14.--15. "STR7_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 12.--13. "STR6_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 10.--11. "STR5_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 8.--9. "STR4_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 6.--7. "STR3_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 4.--5. "STR2_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 2.--3. "STR1_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 0.--1. "STR0_EN,Enable/disable stream y" "0,1,2,3" line.long 0x44 "F2A1_CTRL," bitfld.long 0x44 6.--7. "STR7_CONF,Reconfiguration of stream y to FIFO channel y-4" "0,1,2,3" newline bitfld.long 0x44 4.--5. "STR6_CONF,Reconfiguration of stream y to FIFO channel y-4" "0,1,2,3" newline bitfld.long 0x44 2.--3. "STR5_CONF,Reconfiguration of stream y to FIFO channel y-4" "0,1,2,3" newline bitfld.long 0x44 0.--1. "STR4_CONF,Reconfiguration of stream y to FIFO channel y-4" "0,1,2,3" group.long 0x4880++0x3 line.long 0x0 "AFD1_CH0_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x4890++0x3 line.long 0x0 "AFD1_CH1_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48A0++0x3 line.long 0x0 "AFD1_CH2_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48B0++0x3 line.long 0x0 "AFD1_CH3_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48C0++0x3 line.long 0x0 "AFD1_CH4_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48D0++0x3 line.long 0x0 "AFD1_CH5_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48E0++0x3 line.long 0x0 "AFD1_CH6_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48F0++0x3 line.long 0x0 "AFD1_CH7_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x4A00++0x37 line.long 0x0 "FIFO1_CH0_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO1_CH0_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO1_CH0_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO1_CH0_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO1_CH0_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO1_CH0_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO1_CH0_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO1_CH0_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO1_CH0_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO1_CH0_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO1_CH0_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO1_CH0_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO1_CH0_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO1_CH0_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4A40++0x37 line.long 0x0 "FIFO1_CH1_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO1_CH1_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO1_CH1_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO1_CH1_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO1_CH1_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO1_CH1_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO1_CH1_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO1_CH1_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO1_CH1_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO1_CH1_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO1_CH1_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO1_CH1_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO1_CH1_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO1_CH1_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4A80++0x37 line.long 0x0 "FIFO1_CH2_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO1_CH2_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO1_CH2_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO1_CH2_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO1_CH2_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO1_CH2_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO1_CH2_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO1_CH2_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO1_CH2_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO1_CH2_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO1_CH2_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO1_CH2_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO1_CH2_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO1_CH2_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4AC0++0x37 line.long 0x0 "FIFO1_CH3_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO1_CH3_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO1_CH3_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO1_CH3_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO1_CH3_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO1_CH3_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO1_CH3_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO1_CH3_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO1_CH3_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO1_CH3_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO1_CH3_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO1_CH3_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO1_CH3_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO1_CH3_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4B00++0x37 line.long 0x0 "FIFO1_CH4_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO1_CH4_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO1_CH4_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO1_CH4_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO1_CH4_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO1_CH4_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO1_CH4_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO1_CH4_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO1_CH4_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO1_CH4_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO1_CH4_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO1_CH4_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO1_CH4_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO1_CH4_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4B40++0x37 line.long 0x0 "FIFO1_CH5_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO1_CH5_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO1_CH5_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO1_CH5_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO1_CH5_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO1_CH5_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO1_CH5_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO1_CH5_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO1_CH5_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO1_CH5_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO1_CH5_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO1_CH5_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO1_CH5_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO1_CH5_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4B80++0x37 line.long 0x0 "FIFO1_CH6_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO1_CH6_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO1_CH6_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO1_CH6_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO1_CH6_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO1_CH6_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO1_CH6_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO1_CH6_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO1_CH6_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO1_CH6_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO1_CH6_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO1_CH6_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO1_CH6_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO1_CH6_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4BC0++0x37 line.long 0x0 "FIFO1_CH7_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO1_CH7_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO1_CH7_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO1_CH7_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO1_CH7_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO1_CH7_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO1_CH7_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO1_CH7_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO1_CH7_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO1_CH7_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO1_CH7_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO1_CH7_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO1_CH7_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO1_CH7_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4C00++0x4F line.long 0x0 "SPE1_CTRL_STAT," hexmask.long.byte 0x0 24.--31. 1. "FSOL,Fast Shutoff Level for TOM[i] channel 0 to 7" newline bitfld.long 0x0 23. "ETRIG_SEL,Extended trigger selection of signal SPE[i]_CTRL_STAT.TRIG_SEL" "0,1" newline bitfld.long 0x0 20.--22. "NIP,New input pattern that was detected." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "PDIR,Previous rotation direction." "0,1" newline bitfld.long 0x0 16.--18. "PIP,Previous input pattern that was detected by a regular input pattern change." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "ADIR,Rotation direction. Will be reflected in the signal SPE(i)_DIR." "0,1" newline bitfld.long 0x0 12.--14. "AIP,Input pattern that was detected by a regular input pattern change." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "SPE_PAT_PTR,Pattern selector for TOM output signals." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "FSOM,Fast Shutoff Mode" "0,1" newline bitfld.long 0x0 6. "TIM_SEL,Select TIM input signal" "0,1" newline bitfld.long 0x0 4.--5. "TRIG_SEL,Select trigger input signal." "0,1,2,3" newline bitfld.long 0x0 3. "SIE2,SPE Input enable for TIM_CHx(48)." "0,1" newline bitfld.long 0x0 2. "SIE1,SPE Input enable for TIM_CHx(48)." "0,1" newline bitfld.long 0x0 1. "SIE0,SPE Input enable for TIM_CHx(48)." "0,1" newline bitfld.long 0x0 0. "EN,SPE Submodule enable." "0,1" line.long 0x4 "SPE1_PAT," bitfld.long 0x4 29.--31. "IP7_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "IP7_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 25.--27. "IP6_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 24. "IP6_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 21.--23. "IP5_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "IP5_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 17.--19. "IP4_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "IP4_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 13.--15. "IP3_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12. "IP3_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 9.--11. "IP2_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "IP2_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 5.--7. "IP1_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4. "IP1_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 1.--3. "IP0_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "IP0_VAL,Input pattern t is a valid pattern." "0,1" line.long 0x8 "SPE1_OUT_PAT0," bitfld.long 0x8 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0xC "SPE1_OUT_PAT1," bitfld.long 0xC 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x10 "SPE1_OUT_PAT2," bitfld.long 0x10 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x14 "SPE1_OUT_PAT3," bitfld.long 0x14 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x18 "SPE1_OUT_PAT4," bitfld.long 0x18 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x1C "SPE1_OUT_PAT5," bitfld.long 0x1C 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x20 "SPE1_OUT_PAT6," bitfld.long 0x20 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x24 "SPE1_OUT_PAT7," bitfld.long 0x24 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x28 "SPE1_OUT_CTRL," bitfld.long 0x28 14.--15. "SPE_OUT_CTRL7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 12.--13. "SPE_OUT_CTRL6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 10.--11. "SPE_OUT_CTRL5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 8.--9. "SPE_OUT_CTRL4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 6.--7. "SPE_OUT_CTRL3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 4.--5. "SPE_OUT_CTRL2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 2.--3. "SPE_OUT_CTRL1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 0.--1. "SPE_OUT_CTRL0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x2C "SPE1_IRQ_NOTIFY," bitfld.long 0x2C 4. "SPE_RCMP,SPE revolution counter match event." "0,1" newline bitfld.long 0x2C 3. "SPE_BIS,Bouncing input signal detected." "0,1" newline bitfld.long 0x2C 2. "SPE_PERR,Wrong or invalid pattern detected at input." "0,1" newline bitfld.long 0x2C 1. "SPE_DCHG,SPE_DIR bit changed on behalf of new input pattern." "0,1" newline bitfld.long 0x2C 0. "SPE_NIPD,New input pattern interrupt occurred." "0,1" line.long 0x30 "SPE1_IRQ_EN," bitfld.long 0x30 4. "SPE_RCMP_IRQ_EN,SPE_RCMP_IRQ interrupt enable." "0,1" newline bitfld.long 0x30 3. "SPE_BIS_IRQ_EN,SPE_BIS_IRQ interrupt enable." "0,1" newline bitfld.long 0x30 2. "SPE_PERR_IRQ_EN,SPE_PERR_IRQ interrupt enable." "0,1" newline bitfld.long 0x30 1. "SPE_DCHG_IRQ_EN,SPE_DCHG_IRQ interrupt enable." "0,1" newline bitfld.long 0x30 0. "SPE_NIPD_IRQ_EN,SPE_NIPD_IRQ interrupt enable." "0,1" line.long 0x34 "SPE1_IRQ_FORCINT," bitfld.long 0x34 4. "TRG_SPE_RCMP,Force interrupt of SPE_RCMP." "0,1" newline bitfld.long 0x34 3. "TRG_SPE_BIS,Force interrupt of SPE_BIS." "0,1" newline bitfld.long 0x34 2. "TRG_SPE_PERR,Force interrupt of SPE_PERR." "0,1" newline bitfld.long 0x34 1. "TRG_SPE_DCHG,Force interrupt of SPE_DCHG." "0,1" newline bitfld.long 0x34 0. "TRG_SPE_NIPD,Force interrupt of SPE_NIPD." "0,1" line.long 0x38 "SPE1_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x3C "SPE1_EIRQ_EN," bitfld.long 0x3C 4. "SPE_RCMP_EIRQ_EN,SPE_RCMP_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x3C 3. "SPE_BIS_EIRQ_EN,SPE_BIS_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x3C 2. "SPE_PERR_EIRQ_EN,SPE_PERR_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x3C 1. "SPE_DCHG_EIRQ_EN,SPE_DCHG_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x3C 0. "SPE_NIPD_EIRQ_EN,SPE_NIPD_EIRQ interrupt enable." "0,1" line.long 0x40 "SPE1_REV_CNT," hexmask.long.tbyte 0x40 0.--23. 1. "REV_CNT,Input signal revolution counter" line.long 0x44 "SPE1_REV_CMP," hexmask.long.tbyte 0x44 0.--23. 1. "REV_CMP,Input signal revolution counter compare value" line.long 0x48 "SPE1_CTRL_STAT2," bitfld.long 0x48 8.--10. "SPE_PAT_PTR_BWD,Pattern selector for TOM output signals in case of SPE[i]_CMD.SPE_CTRL_CMD = 0b01 (e.g. backward direction)." "0,1,2,3,4,5,6,7" line.long 0x4C "SPE1_CMD," bitfld.long 0x4C 16. "SPE_UPD_TRIG,SPE updater trigger" "0,1" newline bitfld.long 0x4C 0.--1. "SPE_CTRL_CMD,SPE control command" "0,1,2,3" group.long 0x5000++0xB line.long 0x0 "AXIM1_FREE," bitfld.long 0x0 3. "FREE3,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 2. "FREE2,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 1. "FREE1,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 0. "FREE0,This bit represents the allocation status of the slot [t]" "0,1" line.long 0x4 "AXIM1_REQUEST," hexmask.long.byte 0x4 24.--31. 1. "REQID,This bit field shows the new allocated slot as binary encoded index. If no slot could be allocated this bit field is read as all 1 (0xff)." newline bitfld.long 0x4 3. "REQ1HOT3,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 2. "REQ1HOT2,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 1. "REQ1HOT1,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 0. "REQ1HOT0,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" line.long 0x8 "AXIM1_RELEASE," bitfld.long 0x8 3. "RELREQ3,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 2. "RELREQ2,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 1. "RELREQ1,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 0. "RELREQ0,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" group.long 0x5020++0x3 line.long 0x0 "AXIM1_SLOT0_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5028++0x3 line.long 0x0 "AXIM1_SLOT0_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5030++0xB line.long 0x0 "AXIM1_SLOT0_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM1_SLOT0_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM1_SLOT0_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5040++0x3 line.long 0x0 "AXIM1_SLOT1_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5048++0x3 line.long 0x0 "AXIM1_SLOT1_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5050++0xB line.long 0x0 "AXIM1_SLOT1_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM1_SLOT1_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM1_SLOT1_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5060++0x3 line.long 0x0 "AXIM1_SLOT2_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5068++0x3 line.long 0x0 "AXIM1_SLOT2_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5070++0xB line.long 0x0 "AXIM1_SLOT2_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM1_SLOT2_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM1_SLOT2_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5080++0x3 line.long 0x0 "AXIM1_SLOT3_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5088++0x3 line.long 0x0 "AXIM1_SLOT3_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5090++0xB line.long 0x0 "AXIM1_SLOT3_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM1_SLOT3_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM1_SLOT3_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" repeat 1024. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6000)++0x3 line.long 0x0 "FIFO1_MEMORY[$1]," hexmask.long 0x0 0.--28. 1. "DATA,FIFO memory location." repeat.end repeat 16384. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10000)++0x3 line.long 0x0 "MCS1_MEM[$1]," hexmask.long 0x0 0.--31. 1. "DATA,MCS memory location." repeat.end tree.end tree "GTM_CLS2" base ad:0x74040000 group.long 0x800++0x3F line.long 0x0 "TIM2_CH0_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM2_CH0_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM2_CH0_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM2_CH0_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM2_CH0_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM2_CH0_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM2_CH0_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM2_CH0_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM2_CH0_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM2_CH0_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM2_CH0_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM2_CH0_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM2_CH0_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM2_CH0_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM2_CH0_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM2_CH0_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x880++0x3F line.long 0x0 "TIM2_CH1_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM2_CH1_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM2_CH1_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM2_CH1_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM2_CH1_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM2_CH1_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM2_CH1_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM2_CH1_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM2_CH1_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM2_CH1_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM2_CH1_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM2_CH1_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM2_CH1_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM2_CH1_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM2_CH1_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM2_CH1_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x900++0x3F line.long 0x0 "TIM2_CH2_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM2_CH2_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM2_CH2_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM2_CH2_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM2_CH2_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM2_CH2_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM2_CH2_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM2_CH2_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM2_CH2_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM2_CH2_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM2_CH2_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM2_CH2_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM2_CH2_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM2_CH2_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM2_CH2_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM2_CH2_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x980++0x3F line.long 0x0 "TIM2_CH3_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM2_CH3_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM2_CH3_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM2_CH3_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM2_CH3_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM2_CH3_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM2_CH3_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM2_CH3_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM2_CH3_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM2_CH3_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM2_CH3_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM2_CH3_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM2_CH3_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM2_CH3_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM2_CH3_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM2_CH3_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xA00++0x3F line.long 0x0 "TIM2_CH4_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM2_CH4_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM2_CH4_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM2_CH4_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM2_CH4_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM2_CH4_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM2_CH4_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM2_CH4_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM2_CH4_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM2_CH4_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM2_CH4_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM2_CH4_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM2_CH4_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM2_CH4_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM2_CH4_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM2_CH4_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xA80++0x3F line.long 0x0 "TIM2_CH5_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM2_CH5_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM2_CH5_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM2_CH5_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM2_CH5_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM2_CH5_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM2_CH5_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM2_CH5_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM2_CH5_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM2_CH5_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM2_CH5_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM2_CH5_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM2_CH5_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM2_CH5_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM2_CH5_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM2_CH5_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xB00++0x3F line.long 0x0 "TIM2_CH6_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM2_CH6_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM2_CH6_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM2_CH6_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM2_CH6_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM2_CH6_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM2_CH6_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM2_CH6_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM2_CH6_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM2_CH6_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM2_CH6_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM2_CH6_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM2_CH6_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM2_CH6_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM2_CH6_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM2_CH6_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xB80++0x3F line.long 0x0 "TIM2_CH7_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM2_CH7_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM2_CH7_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM2_CH7_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM2_CH7_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM2_CH7_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM2_CH7_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM2_CH7_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM2_CH7_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM2_CH7_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM2_CH7_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM2_CH7_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM2_CH7_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM2_CH7_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM2_CH7_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM2_CH7_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xC00++0xB line.long 0x0 "TIM2_INP_VAL," bitfld.long 0x0 23. "TIM_IN7,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 22. "TIM_IN6,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 21. "TIM_IN5,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 20. "TIM_IN4,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 19. "TIM_IN3,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 18. "TIM_IN2,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 17. "TIM_IN1,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 16. "TIM_IN0,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 15. "F_IN7,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 14. "F_IN6,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 13. "F_IN5,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 12. "F_IN4,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 11. "F_IN3,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 10. "F_IN2,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 9. "F_IN1,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 8. "F_IN0,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 7. "F_OUT7,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 6. "F_OUT6,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 5. "F_OUT5,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 4. "F_OUT4,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 3. "F_OUT3,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 2. "F_OUT2,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 1. "F_OUT1,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 0. "F_OUT0,Signal channel x after TIM FLT unit" "0,1" line.long 0x4 "TIM2_IN_SRC," bitfld.long 0x4 30.--31. "MODE_7,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 28.--29. "VAL_7,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 26.--27. "MODE_6,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 24.--25. "VAL_6,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 22.--23. "MODE_5,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 20.--21. "VAL_5,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 18.--19. "MODE_4,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 16.--17. "VAL_4,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 14.--15. "MODE_3,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 12.--13. "VAL_3,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 10.--11. "MODE_2,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 8.--9. "VAL_2,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 6.--7. "MODE_1,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 4.--5. "VAL_1,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 2.--3. "MODE_0,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 0.--1. "VAL_0,Value to be fed to channel [x]" "0,1,2,3" line.long 0x8 "TIM2_RST," bitfld.long 0x8 7. "RST_CH7,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 6. "RST_CH6,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 5. "RST_CH5,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 4. "RST_CH4,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 3. "RST_CH3,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 2. "RST_CH2,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 1. "RST_CH1,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 0. "RST_CH0,Software reset of channel [x]" "0,1" group.long 0x1000++0x2B line.long 0x0 "TOM2_CH0_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM2_CH0_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM2_CH0_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM2_CH0_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM2_CH0_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM2_CH0_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM2_CH0_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM2_CH0_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM2_CH0_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM2_CH0_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM2_CH0_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1030++0x3 line.long 0x0 "TOM2_CH0_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1040++0x2B line.long 0x0 "TOM2_CH1_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM2_CH1_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM2_CH1_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM2_CH1_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM2_CH1_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM2_CH1_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM2_CH1_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM2_CH1_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM2_CH1_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM2_CH1_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM2_CH1_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1070++0x3 line.long 0x0 "TOM2_CH1_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1080++0x2B line.long 0x0 "TOM2_CH2_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM2_CH2_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM2_CH2_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM2_CH2_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM2_CH2_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM2_CH2_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM2_CH2_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM2_CH2_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM2_CH2_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM2_CH2_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM2_CH2_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x10B0++0x3 line.long 0x0 "TOM2_CH2_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x10C0++0x2B line.long 0x0 "TOM2_CH3_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM2_CH3_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM2_CH3_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM2_CH3_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM2_CH3_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM2_CH3_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM2_CH3_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM2_CH3_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM2_CH3_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM2_CH3_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM2_CH3_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x10F0++0x3 line.long 0x0 "TOM2_CH3_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1100++0x2B line.long 0x0 "TOM2_CH4_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM2_CH4_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM2_CH4_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM2_CH4_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM2_CH4_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM2_CH4_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM2_CH4_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM2_CH4_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM2_CH4_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM2_CH4_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM2_CH4_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1130++0x3 line.long 0x0 "TOM2_CH4_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1140++0x2B line.long 0x0 "TOM2_CH5_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM2_CH5_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM2_CH5_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM2_CH5_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM2_CH5_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM2_CH5_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM2_CH5_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM2_CH5_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM2_CH5_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM2_CH5_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM2_CH5_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1170++0x3 line.long 0x0 "TOM2_CH5_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1180++0x2B line.long 0x0 "TOM2_CH6_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM2_CH6_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM2_CH6_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM2_CH6_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM2_CH6_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM2_CH6_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM2_CH6_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM2_CH6_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM2_CH6_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM2_CH6_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM2_CH6_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x11B0++0x3 line.long 0x0 "TOM2_CH6_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x11C0++0x2B line.long 0x0 "TOM2_CH7_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM2_CH7_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM2_CH7_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM2_CH7_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM2_CH7_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM2_CH7_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM2_CH7_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM2_CH7_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM2_CH7_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM2_CH7_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM2_CH7_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x11F0++0x3 line.long 0x0 "TOM2_CH7_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1200++0x2B line.long 0x0 "TOM2_CH8_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM2_CH8_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM2_CH8_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM2_CH8_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM2_CH8_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM2_CH8_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM2_CH8_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM2_CH8_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM2_CH8_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM2_CH8_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM2_CH8_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1230++0x3 line.long 0x0 "TOM2_CH8_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1240++0x2B line.long 0x0 "TOM2_CH9_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM2_CH9_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM2_CH9_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM2_CH9_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM2_CH9_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM2_CH9_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM2_CH9_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM2_CH9_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM2_CH9_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM2_CH9_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM2_CH9_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1270++0x3 line.long 0x0 "TOM2_CH9_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1280++0x2B line.long 0x0 "TOM2_CH10_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM2_CH10_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM2_CH10_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM2_CH10_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM2_CH10_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM2_CH10_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM2_CH10_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM2_CH10_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM2_CH10_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM2_CH10_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM2_CH10_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x12B0++0x3 line.long 0x0 "TOM2_CH10_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x12C0++0x2B line.long 0x0 "TOM2_CH11_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM2_CH11_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM2_CH11_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM2_CH11_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM2_CH11_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM2_CH11_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM2_CH11_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM2_CH11_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM2_CH11_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM2_CH11_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM2_CH11_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x12F0++0x3 line.long 0x0 "TOM2_CH11_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1300++0x2B line.long 0x0 "TOM2_CH12_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM2_CH12_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM2_CH12_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM2_CH12_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM2_CH12_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM2_CH12_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM2_CH12_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM2_CH12_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM2_CH12_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM2_CH12_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM2_CH12_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1330++0x3 line.long 0x0 "TOM2_CH12_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1340++0x2B line.long 0x0 "TOM2_CH13_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM2_CH13_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM2_CH13_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM2_CH13_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM2_CH13_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM2_CH13_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM2_CH13_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM2_CH13_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM2_CH13_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM2_CH13_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM2_CH13_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1370++0x3 line.long 0x0 "TOM2_CH13_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1380++0x2B line.long 0x0 "TOM2_CH14_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM2_CH14_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM2_CH14_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM2_CH14_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM2_CH14_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM2_CH14_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM2_CH14_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM2_CH14_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM2_CH14_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM2_CH14_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM2_CH14_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x13B0++0x3 line.long 0x0 "TOM2_CH14_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x13C0++0x2B line.long 0x0 "TOM2_CH15_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM2_CH15_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM2_CH15_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM2_CH15_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM2_CH15_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM2_CH15_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM2_CH15_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM2_CH15_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM2_CH15_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM2_CH15_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM2_CH15_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x13F0++0x3 line.long 0x0 "TOM2_CH15_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1430++0xF line.long 0x0 "TOM2_TGC0_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 28.--29. "UPEN_CTRL6,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 26.--27. "UPEN_CTRL5,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 24.--25. "UPEN_CTRL4,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 22.--23. "UPEN_CTRL3,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 20.--21. "UPEN_CTRL2,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 16.--17. "UPEN_CTRL0,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 15. "RST_CH7,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 14. "RST_CH6,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 13. "RST_CH5,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 12. "RST_CH4,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 10. "RST_CH2,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 9. "RST_CH1,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 8. "RST_CH0,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see TGC0 TGC1) to update the register TOM[i]_TGC[g]_ENDIS_STAT and TOM[i]_TGC[g]_OUTEN_STAT" "0,1" line.long 0x4 "TOM2_TGC0_ACT_TB," bitfld.long 0x4 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" newline bitfld.long 0x4 24. "TB_TRIG,Set trigger request" "0,1" newline hexmask.long.tbyte 0x4 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[y] y=0..2. If selected TBU_TS[y] value is in the interval [TOM[i]_TGC[g]_ACT_TB.ACT_TB-007FFFFFh TOM[i]_TGC[g]_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x8 "TOM2_TGC0_FUPD_CTRL," bitfld.long 0x8 30.--31. "RSTCN0_CH7,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 28.--29. "RSTCN0_CH6,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 26.--27. "RSTCN0_CH5,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 24.--25. "RSTCN0_CH4,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 22.--23. "RSTCN0_CH3,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 20.--21. "RSTCN0_CH2,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 18.--19. "RSTCN0_CH1,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 16.--17. "RSTCN0_CH0,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 14.--15. "FUPD_CTRL7,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 12.--13. "FUPD_CTRL6,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 10.--11. "FUPD_CTRL5,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 8.--9. "FUPD_CTRL4,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 6.--7. "FUPD_CTRL3,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 4.--5. "FUPD_CTRL2,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 2.--3. "FUPD_CTRL1,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 0.--1. "FUPD_CTRL0,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" line.long 0xC "TOM2_TGC0_INT_TRIG," bitfld.long 0xC 14.--15. "INT_TRIG7,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 12.--13. "INT_TRIG6,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 10.--11. "INT_TRIG5,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "INT_TRIG4,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 6.--7. "INT_TRIG3,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 4.--5. "INT_TRIG2,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "INT_TRIG1,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 0.--1. "INT_TRIG0,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" group.long 0x1470++0xF line.long 0x0 "TOM2_TGC0_ENDIS_CTRL," bitfld.long 0x0 14.--15. "ENDIS_CTRL7,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 12.--13. "ENDIS_CTRL6,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 10.--11. "ENDIS_CTRL5,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 8.--9. "ENDIS_CTRL4,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 6.--7. "ENDIS_CTRL3,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ENDIS_CTRL2,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 2.--3. "ENDIS_CTRL1,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 0.--1. "ENDIS_CTRL0,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" line.long 0x4 "TOM2_TGC0_ENDIS_STAT," bitfld.long 0x4 14.--15. "ENDIS_STAT7,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 12.--13. "ENDIS_STAT6,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 10.--11. "ENDIS_STAT5,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 8.--9. "ENDIS_STAT4,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 6.--7. "ENDIS_STAT3,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 4.--5. "ENDIS_STAT2,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_STAT1,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 0.--1. "ENDIS_STAT0,TOM channel x=c + g*8 enable/disable" "0,1,2,3" line.long 0x8 "TOM2_TGC0_OUTEN_CTRL," bitfld.long 0x8 14.--15. "OUTEN_CTRL7,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 12.--13. "OUTEN_CTRL6,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OUTEN_CTRL5,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 8.--9. "OUTEN_CTRL4,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OUTEN_CTRL3,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 4.--5. "OUTEN_CTRL2,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OUTEN_CTRL1,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 0.--1. "OUTEN_CTRL0,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" line.long 0xC "TOM2_TGC0_OUTEN_STAT," bitfld.long 0xC 14.--15. "OUTEN_STAT7,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 12.--13. "OUTEN_STAT6,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 10.--11. "OUTEN_STAT5,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "OUTEN_STAT4,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 6.--7. "OUTEN_STAT3,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 4.--5. "OUTEN_STAT2,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "OUTEN_STAT1,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 0.--1. "OUTEN_STAT0,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" group.long 0x14B0++0xF line.long 0x0 "TOM2_TGC1_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 28.--29. "UPEN_CTRL6,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 26.--27. "UPEN_CTRL5,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 24.--25. "UPEN_CTRL4,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 22.--23. "UPEN_CTRL3,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 20.--21. "UPEN_CTRL2,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 16.--17. "UPEN_CTRL0,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 15. "RST_CH7,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 14. "RST_CH6,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 13. "RST_CH5,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 12. "RST_CH4,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 10. "RST_CH2,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 9. "RST_CH1,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 8. "RST_CH0,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see TGC0 TGC1) to update the register TOM[i]_TGC[g]_ENDIS_STAT and TOM[i]_TGC[g]_OUTEN_STAT" "0,1" line.long 0x4 "TOM2_TGC1_ACT_TB," bitfld.long 0x4 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" newline bitfld.long 0x4 24. "TB_TRIG,Set trigger request" "0,1" newline hexmask.long.tbyte 0x4 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[y] y=0..2. If selected TBU_TS[y] value is in the interval [TOM[i]_TGC[g]_ACT_TB.ACT_TB-007FFFFFh TOM[i]_TGC[g]_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x8 "TOM2_TGC1_FUPD_CTRL," bitfld.long 0x8 30.--31. "RSTCN0_CH7,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 28.--29. "RSTCN0_CH6,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 26.--27. "RSTCN0_CH5,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 24.--25. "RSTCN0_CH4,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 22.--23. "RSTCN0_CH3,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 20.--21. "RSTCN0_CH2,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 18.--19. "RSTCN0_CH1,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 16.--17. "RSTCN0_CH0,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 14.--15. "FUPD_CTRL7,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 12.--13. "FUPD_CTRL6,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 10.--11. "FUPD_CTRL5,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 8.--9. "FUPD_CTRL4,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 6.--7. "FUPD_CTRL3,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 4.--5. "FUPD_CTRL2,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 2.--3. "FUPD_CTRL1,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 0.--1. "FUPD_CTRL0,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" line.long 0xC "TOM2_TGC1_INT_TRIG," bitfld.long 0xC 14.--15. "INT_TRIG7,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 12.--13. "INT_TRIG6,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 10.--11. "INT_TRIG5,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "INT_TRIG4,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 6.--7. "INT_TRIG3,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 4.--5. "INT_TRIG2,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "INT_TRIG1,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 0.--1. "INT_TRIG0,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" group.long 0x14F0++0xF line.long 0x0 "TOM2_TGC1_ENDIS_CTRL," bitfld.long 0x0 14.--15. "ENDIS_CTRL7,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 12.--13. "ENDIS_CTRL6,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 10.--11. "ENDIS_CTRL5,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 8.--9. "ENDIS_CTRL4,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 6.--7. "ENDIS_CTRL3,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ENDIS_CTRL2,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 2.--3. "ENDIS_CTRL1,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 0.--1. "ENDIS_CTRL0,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" line.long 0x4 "TOM2_TGC1_ENDIS_STAT," bitfld.long 0x4 14.--15. "ENDIS_STAT7,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 12.--13. "ENDIS_STAT6,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 10.--11. "ENDIS_STAT5,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 8.--9. "ENDIS_STAT4,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 6.--7. "ENDIS_STAT3,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 4.--5. "ENDIS_STAT2,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_STAT1,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 0.--1. "ENDIS_STAT0,TOM channel x=c + g*8 enable/disable" "0,1,2,3" line.long 0x8 "TOM2_TGC1_OUTEN_CTRL," bitfld.long 0x8 14.--15. "OUTEN_CTRL7,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 12.--13. "OUTEN_CTRL6,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OUTEN_CTRL5,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 8.--9. "OUTEN_CTRL4,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OUTEN_CTRL3,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 4.--5. "OUTEN_CTRL2,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OUTEN_CTRL1,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 0.--1. "OUTEN_CTRL0,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" line.long 0xC "TOM2_TGC1_OUTEN_STAT," bitfld.long 0xC 14.--15. "OUTEN_STAT7,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 12.--13. "OUTEN_STAT6,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 10.--11. "OUTEN_STAT5,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "OUTEN_STAT4,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 6.--7. "OUTEN_STAT3,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 4.--5. "OUTEN_STAT2,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "OUTEN_STAT1,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 0.--1. "OUTEN_STAT0,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" group.long 0x1800++0x37 line.long 0x0 "ATOM2_CH0_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM2_CH0_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM2_CH0_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM2_CH0_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM2_CH0_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM2_CH0_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM2_CH0_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM2_CH0_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM2_CH0_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM2_CH0_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM2_CH0_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM2_CH0_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x30 "ATOM2_CH0_CTRL2," bitfld.long 0x30 0. "HRES,HRES: TOM high resolution support" "0,1" line.long 0x34 "ATOM2_CH0_CTRL_SR," hexmask.long.byte 0x34 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x34 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1880++0x37 line.long 0x0 "ATOM2_CH1_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM2_CH1_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM2_CH1_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM2_CH1_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM2_CH1_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM2_CH1_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM2_CH1_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM2_CH1_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM2_CH1_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM2_CH1_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM2_CH1_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM2_CH1_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x30 "ATOM2_CH1_CTRL2," bitfld.long 0x30 0. "HRES,HRES: TOM high resolution support" "0,1" line.long 0x34 "ATOM2_CH1_CTRL_SR," hexmask.long.byte 0x34 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x34 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1900++0x37 line.long 0x0 "ATOM2_CH2_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM2_CH2_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM2_CH2_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM2_CH2_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM2_CH2_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM2_CH2_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM2_CH2_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM2_CH2_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM2_CH2_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM2_CH2_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM2_CH2_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM2_CH2_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x30 "ATOM2_CH2_CTRL2," bitfld.long 0x30 0. "HRES,HRES: TOM high resolution support" "0,1" line.long 0x34 "ATOM2_CH2_CTRL_SR," hexmask.long.byte 0x34 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x34 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1980++0x37 line.long 0x0 "ATOM2_CH3_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM2_CH3_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM2_CH3_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM2_CH3_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM2_CH3_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM2_CH3_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM2_CH3_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM2_CH3_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM2_CH3_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM2_CH3_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM2_CH3_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM2_CH3_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x30 "ATOM2_CH3_CTRL2," bitfld.long 0x30 0. "HRES,HRES: TOM high resolution support" "0,1" line.long 0x34 "ATOM2_CH3_CTRL_SR," hexmask.long.byte 0x34 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x34 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A00++0x2F line.long 0x0 "ATOM2_CH4_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM2_CH4_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM2_CH4_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM2_CH4_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM2_CH4_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM2_CH4_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM2_CH4_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM2_CH4_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM2_CH4_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM2_CH4_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM2_CH4_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM2_CH4_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1A34++0x3 line.long 0x0 "ATOM2_CH4_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A80++0x2F line.long 0x0 "ATOM2_CH5_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM2_CH5_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM2_CH5_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM2_CH5_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM2_CH5_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM2_CH5_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM2_CH5_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM2_CH5_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM2_CH5_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM2_CH5_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM2_CH5_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM2_CH5_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1AB4++0x3 line.long 0x0 "ATOM2_CH5_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B00++0x2F line.long 0x0 "ATOM2_CH6_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM2_CH6_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM2_CH6_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM2_CH6_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM2_CH6_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM2_CH6_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM2_CH6_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM2_CH6_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM2_CH6_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM2_CH6_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM2_CH6_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM2_CH6_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1B34++0x3 line.long 0x0 "ATOM2_CH6_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B80++0x2F line.long 0x0 "ATOM2_CH7_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM2_CH7_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM2_CH7_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM2_CH7_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM2_CH7_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM2_CH7_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM2_CH7_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM2_CH7_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM2_CH7_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM2_CH7_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM2_CH7_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM2_CH7_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1BB4++0x3 line.long 0x0 "ATOM2_CH7_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1C40++0x1F line.long 0x0 "ATOM2_AGC_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 28.--29. "UPEN_CTRL6,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 26.--27. "UPEN_CTRL5,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 24.--25. "UPEN_CTRL4,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 22.--23. "UPEN_CTRL3,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 20.--21. "UPEN_CTRL2,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 16.--17. "UPEN_CTRL0,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 15. "RST_CH7,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 14. "RST_CH6,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 13. "RST_CH5,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 12. "RST_CH4,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 10. "RST_CH2,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 9. "RST_CH1,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 8. "RST_CH0,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see AGC) to update the register ATOM[i]_AGC_ENDIS_STAT and ATOM[i]_AGC_OUTEN_STAT" "0,1" line.long 0x4 "ATOM2_AGC_ENDIS_CTRL," bitfld.long 0x4 14.--15. "ENDIS_CTRL7,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 12.--13. "ENDIS_CTRL6,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 10.--11. "ENDIS_CTRL5,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 8.--9. "ENDIS_CTRL4,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 6.--7. "ENDIS_CTRL3,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 4.--5. "ENDIS_CTRL2,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_CTRL1,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 0.--1. "ENDIS_CTRL0,ATOM channel [k] enable/disable update value." "0,1,2,3" line.long 0x8 "ATOM2_AGC_ENDIS_STAT," bitfld.long 0x8 14.--15. "ENDIS_STAT7,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 12.--13. "ENDIS_STAT6,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 10.--11. "ENDIS_STAT5,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 8.--9. "ENDIS_STAT4,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 6.--7. "ENDIS_STAT3,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 4.--5. "ENDIS_STAT2,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 2.--3. "ENDIS_STAT1,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 0.--1. "ENDIS_STAT0,ATOM channel [k] enable/disable" "0,1,2,3" line.long 0xC "ATOM2_AGC_ACT_TB," bitfld.long 0xC 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" newline bitfld.long 0xC 24. "TB_TRIG,Set trigger request" "0,1" newline hexmask.long.tbyte 0xC 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[x] x=0..2. If selected TBU_TS[x] value is in the interval [ATOM[i]_AGC_ACT_TB.ACT_TB-007FFFFFh ATOM[i]_AGC_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x10 "ATOM2_AGC_OUTEN_CTRL," bitfld.long 0x10 14.--15. "OUTEN_CTRL7,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 12.--13. "OUTEN_CTRL6,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 10.--11. "OUTEN_CTRL5,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 8.--9. "OUTEN_CTRL4,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 6.--7. "OUTEN_CTRL3,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 4.--5. "OUTEN_CTRL2,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 2.--3. "OUTEN_CTRL1,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 0.--1. "OUTEN_CTRL0,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" line.long 0x14 "ATOM2_AGC_OUTEN_STAT," bitfld.long 0x14 14.--15. "OUTEN_STAT7,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 12.--13. "OUTEN_STAT6,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 10.--11. "OUTEN_STAT5,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 8.--9. "OUTEN_STAT4,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 6.--7. "OUTEN_STAT3,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 4.--5. "OUTEN_STAT2,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 2.--3. "OUTEN_STAT1,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 0.--1. "OUTEN_STAT0,Control/status of output ATOM_OUT [k]" "0,1,2,3" line.long 0x18 "ATOM2_AGC_FUPD_CTRL," bitfld.long 0x18 30.--31. "RSTCN0_CH7,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 28.--29. "RSTCN0_CH6,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 26.--27. "RSTCN0_CH5,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 24.--25. "RSTCN0_CH4,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 22.--23. "RSTCN0_CH3,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 20.--21. "RSTCN0_CH2,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 18.--19. "RSTCN0_CH1,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 16.--17. "RSTCN0_CH0,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 14.--15. "FUPD_CTRL7,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 12.--13. "FUPD_CTRL6,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 10.--11. "FUPD_CTRL5,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 8.--9. "FUPD_CTRL4,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 6.--7. "FUPD_CTRL3,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 4.--5. "FUPD_CTRL2,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 2.--3. "FUPD_CTRL1,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 0.--1. "FUPD_CTRL0,Force update of ATOM channel [k] operation registers" "0,1,2,3" line.long 0x1C "ATOM2_AGC_INT_TRIG," bitfld.long 0x1C 14.--15. "INT_TRIG7,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 12.--13. "INT_TRIG6,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 10.--11. "INT_TRIG5,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 8.--9. "INT_TRIG4,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 6.--7. "INT_TRIG3,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 4.--5. "INT_TRIG2,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 2.--3. "INT_TRIG1,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "INT_TRIG0,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" group.long 0x2000++0x27 line.long 0x0 "MCS2_CH0_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS2_CH0_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS2_CH0_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS2_CH0_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS2_CH0_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS2_CH0_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS2_CH0_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS2_CH0_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS2_CH0_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS2_CH0_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x203C++0x3 line.long 0x0 "MCS2_CH0_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x20E0++0x17 line.long 0x0 "MCS2_CH0_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS2_CH0_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS2_CH0_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS2_CH0_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS2_CH0_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS2_CH0_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2100++0x27 line.long 0x0 "MCS2_CH1_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS2_CH1_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS2_CH1_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS2_CH1_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS2_CH1_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS2_CH1_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS2_CH1_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS2_CH1_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS2_CH1_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS2_CH1_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x213C++0x3 line.long 0x0 "MCS2_CH1_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x21E0++0x17 line.long 0x0 "MCS2_CH1_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS2_CH1_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS2_CH1_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS2_CH1_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS2_CH1_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS2_CH1_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2200++0x27 line.long 0x0 "MCS2_CH2_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS2_CH2_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS2_CH2_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS2_CH2_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS2_CH2_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS2_CH2_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS2_CH2_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS2_CH2_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS2_CH2_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS2_CH2_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x223C++0x3 line.long 0x0 "MCS2_CH2_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x22E0++0x17 line.long 0x0 "MCS2_CH2_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS2_CH2_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS2_CH2_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS2_CH2_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS2_CH2_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS2_CH2_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2300++0x27 line.long 0x0 "MCS2_CH3_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS2_CH3_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS2_CH3_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS2_CH3_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS2_CH3_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS2_CH3_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS2_CH3_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS2_CH3_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS2_CH3_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS2_CH3_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x233C++0x3 line.long 0x0 "MCS2_CH3_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x23E0++0x17 line.long 0x0 "MCS2_CH3_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS2_CH3_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS2_CH3_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS2_CH3_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS2_CH3_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS2_CH3_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2400++0x27 line.long 0x0 "MCS2_CH4_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS2_CH4_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS2_CH4_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS2_CH4_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS2_CH4_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS2_CH4_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS2_CH4_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS2_CH4_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS2_CH4_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS2_CH4_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x243C++0x3 line.long 0x0 "MCS2_CH4_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x24E0++0x17 line.long 0x0 "MCS2_CH4_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS2_CH4_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS2_CH4_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS2_CH4_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS2_CH4_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS2_CH4_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2500++0x27 line.long 0x0 "MCS2_CH5_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS2_CH5_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS2_CH5_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS2_CH5_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS2_CH5_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS2_CH5_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS2_CH5_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS2_CH5_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS2_CH5_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS2_CH5_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x253C++0x3 line.long 0x0 "MCS2_CH5_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x25E0++0x17 line.long 0x0 "MCS2_CH5_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS2_CH5_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS2_CH5_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS2_CH5_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS2_CH5_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS2_CH5_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2600++0x27 line.long 0x0 "MCS2_CH6_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS2_CH6_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS2_CH6_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS2_CH6_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS2_CH6_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS2_CH6_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS2_CH6_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS2_CH6_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS2_CH6_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS2_CH6_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x263C++0x3 line.long 0x0 "MCS2_CH6_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x26E0++0x17 line.long 0x0 "MCS2_CH6_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS2_CH6_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS2_CH6_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS2_CH6_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS2_CH6_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS2_CH6_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2700++0x27 line.long 0x0 "MCS2_CH7_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS2_CH7_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS2_CH7_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS2_CH7_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS2_CH7_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS2_CH7_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS2_CH7_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS2_CH7_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS2_CH7_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS2_CH7_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x273C++0x3 line.long 0x0 "MCS2_CH7_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x27E0++0x17 line.long 0x0 "MCS2_CH7_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS2_CH7_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS2_CH7_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS2_CH7_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS2_CH7_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS2_CH7_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2E28++0x7 line.long 0x0 "MCS2_CTRG," bitfld.long 0x0 23. "TRG23,Trigger bit o." "0,1" newline bitfld.long 0x0 22. "TRG22,Trigger bit o." "0,1" newline bitfld.long 0x0 21. "TRG21,Trigger bit o." "0,1" newline bitfld.long 0x0 20. "TRG20,Trigger bit o." "0,1" newline bitfld.long 0x0 19. "TRG19,Trigger bit o." "0,1" newline bitfld.long 0x0 18. "TRG18,Trigger bit o." "0,1" newline bitfld.long 0x0 17. "TRG17,Trigger bit o." "0,1" newline bitfld.long 0x0 16. "TRG16,Trigger bit o." "0,1" newline bitfld.long 0x0 15. "TRG15,Trigger bit n." "0,1" newline bitfld.long 0x0 14. "TRG14,Trigger bit n." "0,1" newline bitfld.long 0x0 13. "TRG13,Trigger bit n." "0,1" newline bitfld.long 0x0 12. "TRG12,Trigger bit n." "0,1" newline bitfld.long 0x0 11. "TRG11,Trigger bit n." "0,1" newline bitfld.long 0x0 10. "TRG10,Trigger bit n." "0,1" newline bitfld.long 0x0 9. "TRG9,Trigger bit n." "0,1" newline bitfld.long 0x0 8. "TRG8,Trigger bit n." "0,1" newline bitfld.long 0x0 7. "TRG7,Trigger bit m." "0,1" newline bitfld.long 0x0 6. "TRG6,Trigger bit m." "0,1" newline bitfld.long 0x0 5. "TRG5,Trigger bit m." "0,1" newline bitfld.long 0x0 4. "TRG4,Trigger bit m." "0,1" newline bitfld.long 0x0 3. "TRG3,Trigger bit m." "0,1" newline bitfld.long 0x0 2. "TRG2,Trigger bit m." "0,1" newline bitfld.long 0x0 1. "TRG1,Trigger bit m." "0,1" newline bitfld.long 0x0 0. "TRG0,Trigger bit m." "0,1" line.long 0x4 "MCS2_STRG," bitfld.long 0x4 23. "TRG23,Trigger bit k." "0,1" newline bitfld.long 0x4 22. "TRG22,Trigger bit k." "0,1" newline bitfld.long 0x4 21. "TRG21,Trigger bit k." "0,1" newline bitfld.long 0x4 20. "TRG20,Trigger bit k." "0,1" newline bitfld.long 0x4 19. "TRG19,Trigger bit k." "0,1" newline bitfld.long 0x4 18. "TRG18,Trigger bit k." "0,1" newline bitfld.long 0x4 17. "TRG17,Trigger bit k." "0,1" newline bitfld.long 0x4 16. "TRG16,Trigger bit k." "0,1" newline bitfld.long 0x4 15. "TRG15,Trigger bit k." "0,1" newline bitfld.long 0x4 14. "TRG14,Trigger bit k." "0,1" newline bitfld.long 0x4 13. "TRG13,Trigger bit k." "0,1" newline bitfld.long 0x4 12. "TRG12,Trigger bit k." "0,1" newline bitfld.long 0x4 11. "TRG11,Trigger bit k." "0,1" newline bitfld.long 0x4 10. "TRG10,Trigger bit k." "0,1" newline bitfld.long 0x4 9. "TRG9,Trigger bit k." "0,1" newline bitfld.long 0x4 8. "TRG8,Trigger bit k." "0,1" newline bitfld.long 0x4 7. "TRG7,Trigger bit k." "0,1" newline bitfld.long 0x4 6. "TRG6,Trigger bit k." "0,1" newline bitfld.long 0x4 5. "TRG5,Trigger bit k." "0,1" newline bitfld.long 0x4 4. "TRG4,Trigger bit k." "0,1" newline bitfld.long 0x4 3. "TRG3,Trigger bit k." "0,1" newline bitfld.long 0x4 2. "TRG2,Trigger bit k." "0,1" newline bitfld.long 0x4 1. "TRG1,Trigger bit k." "0,1" newline bitfld.long 0x4 0. "TRG0,Trigger bit k." "0,1" group.long 0x2F00++0x13 line.long 0x0 "MCS2_CTRL_STAT," bitfld.long 0x0 26. "HLT_AEIM_ERR,Halt on AEI bus master error." "0,1" newline bitfld.long 0x0 25. "EN_HVD,Enable Modified Harvard architecture." "0,1" newline bitfld.long 0x0 24. "EN_TIM_FOUT,Enable routing of TIM[i]_CH[x]_F_OUT signal." "0,1" newline bitfld.long 0x0 20.--22. "ERR_SRC_ID,Error source identifier." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "RAM_RST,RAM reset bit." "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "SCD_CH,Channel selection for scheduling algorithm." newline bitfld.long 0x0 0.--1. "SCD_MODE,Select MCS scheduling mode" "0,1,2,3" line.long 0x4 "MCS2_RESET," bitfld.long 0x4 7. "RST7,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 6. "RST6,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 5. "RST5,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 4. "RST4,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 3. "RST3,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 2. "RST2,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 1. "RST1,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 0. "RST0,Software reset of channel [k]" "0,1" line.long 0x8 "MCS2_CAT," bitfld.long 0x8 7. "CAT7,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 6. "CAT6,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 5. "CAT5,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 4. "CAT4,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 3. "CAT3,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 2. "CAT2,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 1. "CAT1,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 0. "CAT0,Cancel ARU transfer of channel [k]." "0,1" line.long 0xC "MCS2_CWT," bitfld.long 0xC 7. "CWT7,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 6. "CWT6,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 5. "CWT5,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 4. "CWT4,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 3. "CWT3,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 2. "CWT2,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 1. "CWT1,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 0. "CWT0,Cancel waiting instruction for channel [k]." "0,1" line.long 0x10 "MCS2_ERR," bitfld.long 0x10 7. "ERR7,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 6. "ERR6,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 5. "ERR5,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 4. "ERR4,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 3. "ERR3,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 2. "ERR2,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 1. "ERR1,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 0. "ERR0,Error State of MCS-channel [k]." "0,1" group.long 0x2F1C++0x13 line.long 0x0 "MCS2_REG_PROT," bitfld.long 0x0 14.--15. "WPROT7,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 12.--13. "WPROT6,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 10.--11. "WPROT5,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 8.--9. "WPROT4,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 6.--7. "WPROT3,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 4.--5. "WPROT2,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 2.--3. "WPROT1,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 0.--1. "WPROT0,Register Write Protection of MCS-channel k." "0,1,2,3" line.long 0x4 "MCS2_SINT_IRQ_NOTIFY," bitfld.long 0x4 7. "S_IRQ7,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 6. "S_IRQ6,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 5. "S_IRQ5,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 4. "S_IRQ4,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 3. "S_IRQ3,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 2. "S_IRQ2,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 1. "S_IRQ1,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 0. "S_IRQ0,Shared interrupt [k] notify flag." "0,1" line.long 0x8 "MCS2_SINT_IRQ_EN," bitfld.long 0x8 7. "S_IRQ7_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 6. "S_IRQ6_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 5. "S_IRQ5_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 4. "S_IRQ4_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 3. "S_IRQ3_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 2. "S_IRQ2_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 1. "S_IRQ1_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 0. "S_IRQ0_EN,Shared interrupt [k]" "0,1" line.long 0xC "MCS2_SINT_IRQ_FORCINT," bitfld.long 0xC 7. "TRG_S_IRQ7,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 6. "TRG_S_IRQ6,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 5. "TRG_S_IRQ5,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 4. "TRG_S_IRQ4,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 3. "TRG_S_IRQ3,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 2. "TRG_S_IRQ2,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 1. "TRG_S_IRQ1,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 0. "TRG_S_IRQ0,Trigger IRQ [k] in shared interrupt register" "0,1" line.long 0x10 "MCS2_SINT_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x2F40++0x1B line.long 0x0 "MCS2_HBP0_CTRL," bitfld.long 0x0 17. "NOT,Logical negation of h-th hardware break point." "0,1" newline bitfld.long 0x0 16. "AND,Logical AND conjunction of h-th hardware break point." "0,1" newline bitfld.long 0x0 12.--14. "TYPE,Define type of h-th hardware break point." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--9. "SCOPE,Define scope of h-th hardware break point." "0,1,2,3" newline bitfld.long 0x0 7. "EN_CH7,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 6. "EN_CH6,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 5. "EN_CH5,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 4. "EN_CH4,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 3. "EN_CH3,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 2. "EN_CH2,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 1. "EN_CH1,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 0. "EN_CH0,Enable h-th hardware break point for channel x." "0,1" line.long 0x4 "MCS2_HBP0_PATTERN," hexmask.long 0x4 0.--31. 1. "DATA,Define pattern or address of h-th hardware break point." line.long 0x8 "MCS2_HBP0_STATUS," bitfld.long 0x8 7. "HALT_CH7,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 6. "HALT_CH6,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 5. "HALT_CH5,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 4. "HALT_CH4,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 3. "HALT_CH3,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 2. "HALT_CH2,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 1. "HALT_CH1,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 0. "HALT_CH0,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" line.long 0xC "MCS2_HBP0_IRQ_NOTIFY," bitfld.long 0xC 0. "HBP_IRQ,Interrupt notify flag of the h-th hardware break point." "0,1" line.long 0x10 "MCS2_HBP0_IRQ_EN," bitfld.long 0x10 0. "HBP_IRQ_EN,Interrupt Enable bit of the h-th hardware break point." "0,1" line.long 0x14 "MCS2_HBP0_IRQ_FORCINT," bitfld.long 0x14 0. "TRG_HBP_IRQ,Trigger IRQ of the h-th hardware break point." "0,1" line.long 0x18 "MCS2_HBP0_IRQ_MODE," bitfld.long 0x18 0.--1. "IRQ_MODE,IRQ mode selection for all break point interrupts." "0,1,2,3" group.long 0x2F60++0x1B line.long 0x0 "MCS2_HBP1_CTRL," bitfld.long 0x0 17. "NOT,Logical negation of h-th hardware break point." "0,1" newline bitfld.long 0x0 16. "AND,Logical AND conjunction of h-th hardware break point." "0,1" newline bitfld.long 0x0 12.--14. "TYPE,Define type of h-th hardware break point." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--9. "SCOPE,Define scope of h-th hardware break point." "0,1,2,3" newline bitfld.long 0x0 7. "EN_CH7,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 6. "EN_CH6,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 5. "EN_CH5,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 4. "EN_CH4,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 3. "EN_CH3,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 2. "EN_CH2,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 1. "EN_CH1,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 0. "EN_CH0,Enable h-th hardware break point for channel x." "0,1" line.long 0x4 "MCS2_HBP1_PATTERN," hexmask.long 0x4 0.--31. 1. "DATA,Define pattern or address of h-th hardware break point." line.long 0x8 "MCS2_HBP1_STATUS," bitfld.long 0x8 7. "HALT_CH7,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 6. "HALT_CH6,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 5. "HALT_CH5,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 4. "HALT_CH4,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 3. "HALT_CH3,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 2. "HALT_CH2,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 1. "HALT_CH1,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 0. "HALT_CH0,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" line.long 0xC "MCS2_HBP1_IRQ_NOTIFY," bitfld.long 0xC 0. "HBP_IRQ,Interrupt notify flag of the h-th hardware break point." "0,1" line.long 0x10 "MCS2_HBP1_IRQ_EN," bitfld.long 0x10 0. "HBP_IRQ_EN,Interrupt Enable bit of the h-th hardware break point." "0,1" line.long 0x14 "MCS2_HBP1_IRQ_FORCINT," bitfld.long 0x14 0. "TRG_HBP_IRQ,Trigger IRQ of the h-th hardware break point." "0,1" line.long 0x18 "MCS2_HBP1_IRQ_MODE," bitfld.long 0x18 0.--1. "IRQ_MODE,IRQ mode selection for all break point interrupts." "0,1,2,3" group.long 0x3000++0x13 line.long 0x0 "TIO2_G0_CH0_CTRL," bitfld.long 0x0 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x0 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x0 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x0 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x0 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x0 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x0 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x0 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x0 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x0 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x0 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x0 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x0 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x0 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x0 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x0 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x0 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x0 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x0 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x0 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x0 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x4 "TIO2_G0_CH0_IRQ_NOTIFY," bitfld.long 0x4 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x4 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x4 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x4 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x4 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x4 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x8 "TIO2_G0_CH0_IRQ_EN," bitfld.long 0x8 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x8 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x8 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x8 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x8 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x8 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0xC "TIO2_G0_CH0_IRQ_FORCINT," bitfld.long 0xC 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0xC 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0xC 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0xC 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0xC 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0xC 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x10 "TIO2_G0_CH0_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3020++0xB line.long 0x0 "TIO2_G0_CH0_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO2_G0_CH0_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO2_G0_CH0_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3030++0x23 line.long 0x0 "TIO2_G0_CH0_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO2_G0_CH0_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO2_G0_CH0_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO2_G0_CH0_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO2_G0_CH1_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO2_G0_CH1_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO2_G0_CH1_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO2_G0_CH1_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO2_G0_CH1_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3060++0xB line.long 0x0 "TIO2_G0_CH1_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO2_G0_CH1_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO2_G0_CH1_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3070++0x23 line.long 0x0 "TIO2_G0_CH1_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO2_G0_CH1_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO2_G0_CH1_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO2_G0_CH1_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO2_G0_CH2_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO2_G0_CH2_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO2_G0_CH2_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO2_G0_CH2_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO2_G0_CH2_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x30A0++0xB line.long 0x0 "TIO2_G0_CH2_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO2_G0_CH2_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO2_G0_CH2_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x30B0++0x23 line.long 0x0 "TIO2_G0_CH2_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO2_G0_CH2_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO2_G0_CH2_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO2_G0_CH2_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO2_G0_CH3_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO2_G0_CH3_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO2_G0_CH3_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO2_G0_CH3_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO2_G0_CH3_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x30E0++0xB line.long 0x0 "TIO2_G0_CH3_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO2_G0_CH3_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO2_G0_CH3_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x30F0++0x23 line.long 0x0 "TIO2_G0_CH3_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO2_G0_CH3_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO2_G0_CH3_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO2_G0_CH3_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO2_G0_CH4_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO2_G0_CH4_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO2_G0_CH4_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO2_G0_CH4_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO2_G0_CH4_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3120++0xB line.long 0x0 "TIO2_G0_CH4_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO2_G0_CH4_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO2_G0_CH4_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3130++0x23 line.long 0x0 "TIO2_G0_CH4_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO2_G0_CH4_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO2_G0_CH4_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO2_G0_CH4_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO2_G0_CH5_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO2_G0_CH5_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO2_G0_CH5_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO2_G0_CH5_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO2_G0_CH5_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3160++0xB line.long 0x0 "TIO2_G0_CH5_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO2_G0_CH5_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO2_G0_CH5_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3170++0x23 line.long 0x0 "TIO2_G0_CH5_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO2_G0_CH5_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO2_G0_CH5_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO2_G0_CH5_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO2_G0_CH6_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO2_G0_CH6_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO2_G0_CH6_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO2_G0_CH6_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO2_G0_CH6_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x31A0++0xB line.long 0x0 "TIO2_G0_CH6_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO2_G0_CH6_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO2_G0_CH6_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x31B0++0x23 line.long 0x0 "TIO2_G0_CH6_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO2_G0_CH6_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO2_G0_CH6_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO2_G0_CH6_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO2_G0_CH7_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO2_G0_CH7_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO2_G0_CH7_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO2_G0_CH7_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO2_G0_CH7_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x31E0++0xB line.long 0x0 "TIO2_G0_CH7_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO2_G0_CH7_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO2_G0_CH7_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x31F0++0x17 line.long 0x0 "TIO2_G0_CH7_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO2_G0_CH7_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO2_G0_CH7_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO2_G0_CH7_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO2_G0_ISEL0_CTRL1," bitfld.long 0x10 27. "WRITE_EN3,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 26. "WRITE_EN2,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 25. "WRITE_EN1,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 24. "WRITE_EN0,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 19. "OUT_SEL3,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x10 18. "OUT_SEL2,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x10 17. "OUT_SEL1,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x10 16. "OUT_SEL0,select signal for ISEL_OUT[k]" "0,1" newline hexmask.long.byte 0x10 12.--15. 1. "LUT2_3,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x10 8.--11. 1. "LUT2_2,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x10 4.--7. 1. "LUT2_1,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x10 0.--3. 1. "LUT2_0,2 bit Lookup table function for channel c=q*4+k" line.long 0x14 "TIO2_G0_ISEL0_CTRL2," bitfld.long 0x14 22. "LUT3IN_SEL2,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x14 21. "LUT3IN_SEL1,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x14 20. "LUT3IN_SEL0,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x14 16.--17. "QOUT_SEL,select source for ISEL_QOUT signal in quad = q" "0,1,2,3" newline hexmask.long.byte 0x14 0.--7. 1. "LUT3,3 bit Lookup table function for quad=q; channels q*4+2 .. q*4" group.long 0x3220++0x7 line.long 0x0 "TIO2_G0_ISEL1_CTRL1," bitfld.long 0x0 27. "WRITE_EN3,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 26. "WRITE_EN2,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 25. "WRITE_EN1,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 24. "WRITE_EN0,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 19. "OUT_SEL3,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x0 18. "OUT_SEL2,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x0 17. "OUT_SEL1,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x0 16. "OUT_SEL0,select signal for ISEL_OUT[k]" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "LUT2_3,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x0 8.--11. 1. "LUT2_2,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x0 4.--7. 1. "LUT2_1,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x0 0.--3. 1. "LUT2_0,2 bit Lookup table function for channel c=q*4+k" line.long 0x4 "TIO2_G0_ISEL1_CTRL2," bitfld.long 0x4 22. "LUT3IN_SEL2,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x4 21. "LUT3IN_SEL1,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x4 20. "LUT3IN_SEL0,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x4 16.--17. "QOUT_SEL,select source for ISEL_QOUT signal in quad = q" "0,1,2,3" newline hexmask.long.byte 0x4 0.--7. 1. "LUT3,3 bit Lookup table function for quad=q; channels q*4+2 .. q*4" group.long 0x3240++0x3 line.long 0x0 "TIO2_G0_OP_USAGE," bitfld.long 0x0 31. "WRITE_EN7,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 30. "WRITE_EN6,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 29. "WRITE_EN5,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 28. "WRITE_EN4,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 27. "WRITE_EN3,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 26. "WRITE_EN2,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 25. "WRITE_EN1,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 24. "WRITE_EN0,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 21.--23. "MODE7,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "MODE6,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15.--17. "MODE5,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "MODE4,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9.--11. "MODE3,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "MODE2,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "MODE1,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "MODE0,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" group.long 0x3C00++0x1F line.long 0x0 "TIO2_S," bitfld.long 0x0 7. "CH7,Value of channel x." "0,1" newline bitfld.long 0x0 6. "CH6,Value of channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Value of channel x." "0,1" newline bitfld.long 0x0 4. "CH4,Value of channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Value of channel x." "0,1" newline bitfld.long 0x0 2. "CH2,Value of channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Value of channel x." "0,1" newline bitfld.long 0x0 0. "CH0,Value of channel x." "0,1" line.long 0x4 "TIO2_O," bitfld.long 0x4 7. "CH7,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 6. "CH6,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 4. "CH4,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 2. "CH2,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 0. "CH0,Value driven on output of channel x." "0,1" line.long 0x8 "TIO2_ENDIS," bitfld.long 0x8 7. "CH7,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 6. "CH6,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 4. "CH4,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 2. "CH2,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 0. "CH0,Enable/Disable request of channel x." "0,1" line.long 0xC "TIO2_INVERT," bitfld.long 0xC 7. "CH7,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 6. "CH6,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 4. "CH4,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 2. "CH2,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 0. "CH0,Enable/Disable signal inversion of channel x." "0,1" line.long 0x10 "TIO2_INPUT_MODE," bitfld.long 0x10 7. "CH7,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 6. "CH6,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 4. "CH4,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 2. "CH2,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 0. "CH0,Enable/Disable input mode of channel x." "0,1" line.long 0x14 "TIO2_CYCLIC_MODE," bitfld.long 0x14 7. "CH7,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 6. "CH6,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 4. "CH4,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 2. "CH2,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 0. "CH0,Enable/Disable cyclic mode of channel x." "0,1" line.long 0x18 "TIO2_TRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 6. "CH6,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 4. "CH4,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 2. "CH2,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 0. "CH0,enable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO2_PLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 6. "CH6,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 4. "CH4,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 2. "CH2,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 0. "CH0,enable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3C40++0x1F line.long 0x0 "TIO2_CS," bitfld.long 0x0 7. "CH7,Clear channel x." "0,1" newline bitfld.long 0x0 6. "CH6,Clear channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Clear channel x." "0,1" newline bitfld.long 0x0 4. "CH4,Clear channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Clear channel x." "0,1" newline bitfld.long 0x0 2. "CH2,Clear channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Clear channel x." "0,1" newline bitfld.long 0x0 0. "CH0,Clear channel x." "0,1" line.long 0x4 "TIO2_CO," bitfld.long 0x4 7. "CH7,Clear channel x." "0,1" newline bitfld.long 0x4 6. "CH6,Clear channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Clear channel x." "0,1" newline bitfld.long 0x4 4. "CH4,Clear channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Clear channel x." "0,1" newline bitfld.long 0x4 2. "CH2,Clear channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Clear channel x." "0,1" newline bitfld.long 0x4 0. "CH0,Clear channel x." "0,1" line.long 0x8 "TIO2_CENDIS," bitfld.long 0x8 7. "CH7,Disable request of channel x." "0,1" newline bitfld.long 0x8 6. "CH6,Disable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Disable request of channel x." "0,1" newline bitfld.long 0x8 4. "CH4,Disable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Disable request of channel x." "0,1" newline bitfld.long 0x8 2. "CH2,Disable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Disable request of channel x." "0,1" newline bitfld.long 0x8 0. "CH0,Disable request of channel x." "0,1" line.long 0xC "TIO2_CINVERT," bitfld.long 0xC 7. "CH7,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 6. "CH6,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 4. "CH4,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 2. "CH2,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 0. "CH0,Disable signal inversion of channel x." "0,1" line.long 0x10 "TIO2_CINPUT_MODE," bitfld.long 0x10 7. "CH7,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 6. "CH6,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 4. "CH4,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 2. "CH2,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 0. "CH0,Disable input mode of channel x." "0,1" line.long 0x14 "TIO2_CCYCLIC_MODE," bitfld.long 0x14 7. "CH7,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 6. "CH6,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 4. "CH4,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 2. "CH2,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 0. "CH0,Disable cyclic mode of channel x." "0,1" line.long 0x18 "TIO2_CTRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 6. "CH6,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 4. "CH4,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 2. "CH2,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 0. "CH0,disable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO2_CPLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 6. "CH6,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 4. "CH4,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 2. "CH2,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 0. "CH0,disable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3C80++0x1F line.long 0x0 "TIO2_SS," bitfld.long 0x0 7. "CH7,Set channel x." "0,1" newline bitfld.long 0x0 6. "CH6,Set channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Set channel x." "0,1" newline bitfld.long 0x0 4. "CH4,Set channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Set channel x." "0,1" newline bitfld.long 0x0 2. "CH2,Set channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Set channel x." "0,1" newline bitfld.long 0x0 0. "CH0,Set channel x." "0,1" line.long 0x4 "TIO2_SO," bitfld.long 0x4 7. "CH7,Set channel x." "0,1" newline bitfld.long 0x4 6. "CH6,Set channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Set channel x." "0,1" newline bitfld.long 0x4 4. "CH4,Set channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Set channel x." "0,1" newline bitfld.long 0x4 2. "CH2,Set channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Set channel x." "0,1" newline bitfld.long 0x4 0. "CH0,Set channel x." "0,1" line.long 0x8 "TIO2_SENDIS," bitfld.long 0x8 7. "CH7,Enable request of channel x." "0,1" newline bitfld.long 0x8 6. "CH6,Enable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Enable request of channel x." "0,1" newline bitfld.long 0x8 4. "CH4,Enable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Enable request of channel x." "0,1" newline bitfld.long 0x8 2. "CH2,Enable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Enable request of channel x." "0,1" newline bitfld.long 0x8 0. "CH0,Enable request of channel x." "0,1" line.long 0xC "TIO2_SINVERT," bitfld.long 0xC 7. "CH7,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 6. "CH6,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 4. "CH4,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 2. "CH2,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 0. "CH0,Enable signal inversion of channel x." "0,1" line.long 0x10 "TIO2_SINPUT_MODE," bitfld.long 0x10 7. "CH7,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 6. "CH6,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 4. "CH4,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 2. "CH2,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 0. "CH0,Enable input mode of channel x." "0,1" line.long 0x14 "TIO2_SCYCLIC_MODE," bitfld.long 0x14 7. "CH7,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 6. "CH6,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 4. "CH4,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 2. "CH2,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 0. "CH0,Enable cyclic mode of channel x." "0,1" line.long 0x18 "TIO2_STRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 6. "CH6,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 4. "CH4,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 2. "CH2,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 0. "CH0,enable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO2_SPLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 6. "CH6,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 4. "CH4,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 2. "CH2,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 0. "CH0,enable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3CC0++0x17 line.long 0x0 "TIO2_IS," bitfld.long 0x0 7. "CH7,Invert channel x." "0,1" newline bitfld.long 0x0 6. "CH6,Invert channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Invert channel x." "0,1" newline bitfld.long 0x0 4. "CH4,Invert channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Invert channel x." "0,1" newline bitfld.long 0x0 2. "CH2,Invert channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Invert channel x." "0,1" newline bitfld.long 0x0 0. "CH0,Invert channel x." "0,1" line.long 0x4 "TIO2_IO," bitfld.long 0x4 7. "CH7,Invert channel x." "0,1" newline bitfld.long 0x4 6. "CH6,Invert channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Invert channel x." "0,1" newline bitfld.long 0x4 4. "CH4,Invert channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Invert channel x." "0,1" newline bitfld.long 0x4 2. "CH2,Invert channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Invert channel x." "0,1" newline bitfld.long 0x4 0. "CH0,Invert channel x." "0,1" line.long 0x8 "TIO2_IENDIS," bitfld.long 0x8 7. "CH7,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 6. "CH6,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 4. "CH4,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 2. "CH2,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 0. "CH0,Toggle state request of channel x." "0,1" line.long 0xC "TIO2_IINVERT," bitfld.long 0xC 7. "CH7,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 6. "CH6,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 4. "CH4,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 2. "CH2,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 0. "CH0,Invert signal inversion of channel x." "0,1" line.long 0x10 "TIO2_IINPUT_MODE," bitfld.long 0x10 7. "CH7,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 6. "CH6,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 4. "CH4,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 2. "CH2,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 0. "CH0,Toggle input mode of channel x." "0,1" line.long 0x14 "TIO2_ICYCLIC_MODE," bitfld.long 0x14 7. "CH7,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 6. "CH6,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 4. "CH4,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 2. "CH2,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 0. "CH0,Toggle cyclic mode of channel x." "0,1" group.long 0x3D00++0x13 line.long 0x0 "TIO2_FUPD," bitfld.long 0x0 7. "CH7,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 6. "CH6,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 5. "CH5,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 4. "CH4,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 3. "CH3,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 2. "CH2,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 1. "CH1,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 0. "CH0,issue immediately a signal pulse on the update signal of channel x" "0,1" line.long 0x4 "TIO2_HW_CONF," bitfld.long 0x4 4. "TIO_PLUS,signals availablity of TIOplus functionality" "0,1" newline bitfld.long 0x4 0.--1. "NTIO_CH8,signals availablity of amount of channels" "0,1,2,3" line.long 0x8 "TIO2_RSEL_CTRL1," bitfld.long 0x8 28. "SEL_CLKEN7_0,select source of RS_CLKEN7[g][7] for channels g*8 .. g*8+7" "0,1" newline bitfld.long 0x8 24. "SEL_CLKEN6_0,select source of RS_CLKEN[g][6] for channels g*8 .. g*8+7" "0,1" line.long 0xC "TIO2_RSEL_CTRL2," bitfld.long 0xC 8. "SEL_TB2_0,select source of RS_TB2[g] for channels g*8 .. g*8+7" "0,1" newline bitfld.long 0xC 4. "SEL_TB1_0,select source of RS_TB1[g] for channels g*8 .. g*8+7" "0,1" line.long 0x10 "TIO2_PL_SWRST," bitfld.long 0x10 7. "CH7,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 6. "CH6,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 5. "CH5,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 4. "CH4,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 3. "CH3,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 2. "CH2,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 1. "CH1,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 0. "CH0,reset TIO_Plus resources of channel x" "0,1" group.long 0x4000++0x4F line.long 0x0 "CCM2_ARP0_CTRL," bitfld.long 0x0 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x0 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x0 0.--15. 1. "ADDR,ARP base address." line.long 0x4 "CCM2_ARP0_PROT," bitfld.long 0x4 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x8 "CCM2_ARP1_CTRL," bitfld.long 0x8 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x8 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x8 0.--15. 1. "ADDR,ARP base address." line.long 0xC "CCM2_ARP1_PROT," bitfld.long 0xC 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x10 "CCM2_ARP2_CTRL," bitfld.long 0x10 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x10 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x10 0.--15. 1. "ADDR,ARP base address." line.long 0x14 "CCM2_ARP2_PROT," bitfld.long 0x14 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x18 "CCM2_ARP3_CTRL," bitfld.long 0x18 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x18 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x18 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x18 0.--15. 1. "ADDR,ARP base address." line.long 0x1C "CCM2_ARP3_PROT," bitfld.long 0x1C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x20 "CCM2_ARP4_CTRL," bitfld.long 0x20 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x20 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x20 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x20 0.--15. 1. "ADDR,ARP base address." line.long 0x24 "CCM2_ARP4_PROT," bitfld.long 0x24 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x28 "CCM2_ARP5_CTRL," bitfld.long 0x28 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x28 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x28 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x28 0.--15. 1. "ADDR,ARP base address." line.long 0x2C "CCM2_ARP5_PROT," bitfld.long 0x2C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x30 "CCM2_ARP6_CTRL," bitfld.long 0x30 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x30 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x30 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x30 0.--15. 1. "ADDR,ARP base address." line.long 0x34 "CCM2_ARP6_PROT," bitfld.long 0x34 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x38 "CCM2_ARP7_CTRL," bitfld.long 0x38 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x38 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x38 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x38 0.--15. 1. "ADDR,ARP base address." line.long 0x3C "CCM2_ARP7_PROT," bitfld.long 0x3C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x40 "CCM2_ARP8_CTRL," bitfld.long 0x40 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x40 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x40 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x40 0.--15. 1. "ADDR,ARP base address." line.long 0x44 "CCM2_ARP8_PROT," bitfld.long 0x44 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x48 "CCM2_ARP9_CTRL," bitfld.long 0x48 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x48 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x48 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x48 0.--15. 1. "ADDR,ARP base address." line.long 0x4C "CCM2_ARP9_PROT," bitfld.long 0x4C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 0. "WPROT0,Write Protection MCS channel x." "0,1" group.long 0x41CC++0x3 line.long 0x0 "CCM2_TIO_G0_OUT," bitfld.long 0x0 31. "TIO_G1_OUT_N7,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 30. "TIO_G1_OUT_N6,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 29. "TIO_G1_OUT_N5,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 28. "TIO_G1_OUT_N4,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 27. "TIO_G1_OUT_N3,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 26. "TIO_G1_OUT_N2,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 25. "TIO_G1_OUT_N1,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 24. "TIO_G1_OUT_N0,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 23. "TIO_G0_OUT_N7,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 22. "TIO_G0_OUT_N6,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 21. "TIO_G0_OUT_N5,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 20. "TIO_G0_OUT_N4,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 19. "TIO_G0_OUT_N3,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 18. "TIO_G0_OUT_N2,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 17. "TIO_G0_OUT_N1,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 16. "TIO_G0_OUT_N0,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 15. "TIO_G1_OUT7,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 14. "TIO_G1_OUT6,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 13. "TIO_G1_OUT5,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 12. "TIO_G1_OUT4,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 11. "TIO_G1_OUT3,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 10. "TIO_G1_OUT2,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 9. "TIO_G1_OUT1,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 8. "TIO_G1_OUT0,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 7. "TIO_G0_OUT7,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 6. "TIO_G0_OUT6,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 5. "TIO_G0_OUT5,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 4. "TIO_G0_OUT4,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 3. "TIO_G0_OUT3,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 2. "TIO_G0_OUT2,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 1. "TIO_G0_OUT1,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 0. "TIO_G0_OUT0,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" group.long 0x41D4++0x2B line.long 0x0 "CCM2_HW_CONF2," bitfld.long 0x0 18. "AXIM_DATA_SIZE,Defines the data bus width of the AXI master interface" "0,1" newline bitfld.long 0x0 16. "AXIS_DATA_SIZE,Defines the data bus width of the AXI slave interface" "0,1" newline bitfld.long 0x0 9. "TIO_OUT_RST,TIO_OUT reset level" "0,1" newline bitfld.long 0x0 7. "AXIM_POSTED_WRITE,Write transaction without response" "0,1" newline bitfld.long 0x0 6. "AXIM_SEC_ACC,Secure AXI master access constant" "0,1" newline bitfld.long 0x0 5. "AXIM_PRIV_ACC,Privileged AXI master access constant" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "AXIM_ID_WIDTH,Defines which LSB of AXIM_ID are send to the bus" line.long 0x4 "CCM2_AEIM_STA," bitfld.long 0x4 24.--25. "AEIM_XPT_STA,AEIM Exception status." "0,1,2,3" newline hexmask.long.word 0x4 0.--15. 1. "AEIM_XPT_ADDR,Exception Address." line.long 0x8 "CCM2_HW_CONF," bitfld.long 0x8 31. "AEI_RDATA_PIPELINE_STAGE,Read data pipeline stage implemented" "0,1" newline bitfld.long 0x8 30. "AEI_ADDR_PIPELINE_STAGE,Address pipeline stage implemented" "0,1" newline bitfld.long 0x8 29. "INT_CLK_EN_GEN,Internal clock enable generation" "0,1" newline hexmask.long.byte 0x8 24.--28. 1. "TOM_TRIG_INTCHAIN,TOM internal trigger chain length without synchronization register" newline hexmask.long.byte 0x8 20.--23. 1. "ATOM_TRIG_INTCHAIN,ATOM internal trigger chain length without synchronization register" newline bitfld.long 0x8 19. "IRQ_MODE_SINGLE_PULSE,Signalize availability of Single Pulse IRQ mode" "0,1" newline bitfld.long 0x8 18. "IRQ_MODE_PULSE_NOTIFY,Signalize availability of Pulse Notoify IRQ mode" "0,1" newline bitfld.long 0x8 17. "IRQ_MODE_PULSE,Signalize availability of Pulse IRQ mode" "0,1" newline bitfld.long 0x8 16. "IRQ_MODE_LEVEL,Signalize availability of Level IRQ mode" "0,1" newline bitfld.long 0x8 15. "RESET_ACTIVE,Active level of asynchronous reset" "0,1" newline bitfld.long 0x8 13. "ERM,Enable RAM1 MSB for available MCS modules" "0,1" newline bitfld.long 0x8 12. "RAM_INIT_RST,RAM initialization from reset" "0,1" newline bitfld.long 0x8 9.--11. "TOM_TRIG_CHAIN,TOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "TOM_OUT_RST,TOM_OUT reset level" "0,1" newline bitfld.long 0x8 5.--7. "ATOM_TRIG_CHAIN,ATOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "ATOM_OUT_RST,ATOM_OUT reset level" "0,1" newline bitfld.long 0x8 3. "CFG_CLOCK_RATE,Clocks per ARU transfer" "0,1" newline bitfld.long 0x8 2. "SYNC_INPUT_REG,Additional pipelined stage in synchronous bridge mode" "0,1" newline bitfld.long 0x8 1. "BRIDGE_MODE_RST,Bridge mode after reset" "0,1" newline bitfld.long 0x8 0. "GRSTEN,Global Reset Enable" "0,1" line.long 0xC "CCM2_TIM_AUX_IN_SRC," bitfld.long 0xC 23. "SEL_OUT_N_CH7,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 22. "SEL_OUT_N_CH6,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 21. "SEL_OUT_N_CH5,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 20. "SEL_OUT_N_CH4,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 19. "SEL_OUT_N_CH3,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 18. "SEL_OUT_N_CH2,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 17. "SEL_OUT_N_CH1,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 16. "SEL_OUT_N_CH0,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 7. "SRC_CH7,Defines AUX_IN source of TIM[i] channel 7" "0,1" newline bitfld.long 0xC 6. "SRC_CH6,Defines AUX_IN source of TIM[i] channel 6" "0,1" newline bitfld.long 0xC 5. "SRC_CH5,Defines AUX_IN source of TIM[i] channel 5" "0,1" newline bitfld.long 0xC 4. "SRC_CH4,Defines AUX_IN source of TIM[i] channel 4" "0,1" newline bitfld.long 0xC 3. "SRC_CH3,Defines AUX_IN source of TIM[i] channel 3" "0,1" newline bitfld.long 0xC 2. "SRC_CH2,Defines AUX_IN source of TIM[i] channel 2" "0,1" newline bitfld.long 0xC 1. "SRC_CH1,Defines AUX_IN source of TIM[i] channel 1" "0,1" newline bitfld.long 0xC 0. "SRC_CH0,Defines AUX_IN source of TIM[i] channel 0" "0,1" line.long 0x10 "CCM2_EXT_CAP_EN," bitfld.long 0x10 15. "TIM_IP1_EXT_CAP_EN7,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 14. "TIM_IP1_EXT_CAP_EN6,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 13. "TIM_IP1_EXT_CAP_EN5,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 12. "TIM_IP1_EXT_CAP_EN4,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 11. "TIM_IP1_EXT_CAP_EN3,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 10. "TIM_IP1_EXT_CAP_EN2,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 9. "TIM_IP1_EXT_CAP_EN1,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 8. "TIM_IP1_EXT_CAP_EN0,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 7. "TIM_I_EXT_CAP_EN7,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 6. "TIM_I_EXT_CAP_EN6,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 5. "TIM_I_EXT_CAP_EN5,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 4. "TIM_I_EXT_CAP_EN4,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 3. "TIM_I_EXT_CAP_EN3,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 2. "TIM_I_EXT_CAP_EN2,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 1. "TIM_I_EXT_CAP_EN1,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 0. "TIM_I_EXT_CAP_EN0,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" line.long 0x14 "CCM2_TOM_OUT," bitfld.long 0x14 31. "TOM_OUT_N15,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 30. "TOM_OUT_N14,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 29. "TOM_OUT_N13,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 28. "TOM_OUT_N12,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 27. "TOM_OUT_N11,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 26. "TOM_OUT_N10,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 25. "TOM_OUT_N9,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 24. "TOM_OUT_N8,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 23. "TOM_OUT_N7,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 22. "TOM_OUT_N6,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 21. "TOM_OUT_N5,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 20. "TOM_OUT_N4,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 19. "TOM_OUT_N3,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 18. "TOM_OUT_N2,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 17. "TOM_OUT_N1,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 16. "TOM_OUT_N0,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 15. "TOM_OUT15,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 14. "TOM_OUT14,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 13. "TOM_OUT13,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 12. "TOM_OUT12,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 11. "TOM_OUT11,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 10. "TOM_OUT10,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 9. "TOM_OUT9,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 8. "TOM_OUT8,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 7. "TOM_OUT7,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 6. "TOM_OUT6,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 5. "TOM_OUT5,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 4. "TOM_OUT4,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 3. "TOM_OUT3,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 2. "TOM_OUT2,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 1. "TOM_OUT1,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 0. "TOM_OUT0,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" line.long 0x18 "CCM2_ATOM_OUT," bitfld.long 0x18 31. "ATOM_IP1_OUT_N7,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 30. "ATOM_IP1_OUT_N6,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 29. "ATOM_IP1_OUT_N5,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 28. "ATOM_IP1_OUT_N4,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 27. "ATOM_IP1_OUT_N3,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 26. "ATOM_IP1_OUT_N2,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 25. "ATOM_IP1_OUT_N1,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 24. "ATOM_IP1_OUT_N0,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 23. "ATOM_IP1_OUT7,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 22. "ATOM_IP1_OUT6,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 21. "ATOM_IP1_OUT5,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 20. "ATOM_IP1_OUT4,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 19. "ATOM_IP1_OUT3,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 18. "ATOM_IP1_OUT2,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 17. "ATOM_IP1_OUT1,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 16. "ATOM_IP1_OUT0,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 15. "ATOM_I_OUT_N7,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 14. "ATOM_I_OUT_N6,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 13. "ATOM_I_OUT_N5,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 12. "ATOM_I_OUT_N4,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 11. "ATOM_I_OUT_N3,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 10. "ATOM_I_OUT_N2,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 9. "ATOM_I_OUT_N1,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 8. "ATOM_I_OUT_N0,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 7. "ATOM_I_OUT7,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 6. "ATOM_I_OUT6,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 5. "ATOM_I_OUT5,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 4. "ATOM_I_OUT4,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 3. "ATOM_I_OUT3,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 2. "ATOM_I_OUT2,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 1. "ATOM_I_OUT1,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 0. "ATOM_I_OUT0,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" line.long 0x1C "CCM2_CMU_CLK_CFG," bitfld.long 0x1C 28.--29. "CLK7_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 24.--25. "CLK6_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 20.--21. "CLK5_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 16.--17. "CLK4_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 12.--13. "CLK3_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 8.--9. "CLK2_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 4.--5. "CLK1_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "CLK0_SRC,Clock y source signal selector" "0,1,2,3" line.long 0x20 "CCM2_CMU_FXCLK_CFG," hexmask.long.byte 0x20 0.--3. 1. "FXCLK0_SRC,Fixed clock 0 source signal selector" line.long 0x24 "CCM2_CFG," bitfld.long 0x24 31. "TBU_DIR2,DIR1 input signal of module TBU timebase [z]." "0,1" newline bitfld.long 0x24 30. "TBU_DIR1,DIR1 input signal of module TBU timebase [z]." "0,1" newline bitfld.long 0x24 16.--17. "CLS_CLK_DIV,Cluster Clock Divider." "0,1,2,3" newline bitfld.long 0x24 8. "EN_TIO_DTM,Enable TIO and connected DTM" "0,1" newline bitfld.long 0x24 7. "EN_CMP_MON,Enable CMP and MON" "0,1" newline bitfld.long 0x24 6. "EN_PSM,Enable PSM" "0,1" newline bitfld.long 0x24 5. "EN_BRC,Enable BRC" "0,1" newline bitfld.long 0x24 4. "EN_DPLL_MAP,Enable DPLL and MAP" "0,1" newline bitfld.long 0x24 3. "EN_MCS,Enable MCS" "0,1" newline bitfld.long 0x24 2. "EN_ATOM_ADTM,Enable ATOM and ADTM" "0,1" newline bitfld.long 0x24 1. "EN_TOM_SPE_TDTM,Enable TOM SPE and TDTM" "0,1" newline bitfld.long 0x24 0. "EN_TIM,Enable TIM" "0,1" line.long 0x28 "CCM2_PROT," bitfld.long 0x28 0. "CLS_PROT,Cluster Protection" "0,1" group.long 0x4400++0x7F line.long 0x0 "CDTM2_DTM0_CTRL," bitfld.long 0x0 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x0 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x0 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x0 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x0 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x4 "CDTM2_DTM0_CH_CTRL1," bitfld.long 0x4 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x4 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x4 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x4 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x4 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x4 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x4 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x4 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x4 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x4 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x4 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x4 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x4 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x4 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x4 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x4 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x4 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x8 "CDTM2_DTM0_CH_CTRL2," bitfld.long 0x8 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x8 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x8 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x8 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x8 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x8 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x8 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x8 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x8 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x8 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x8 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x8 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x8 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x8 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x8 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x8 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x8 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x8 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x8 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x8 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x8 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x8 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x8 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x8 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x8 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x8 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x8 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x8 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x8 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x8 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x8 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x8 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0xC "CDTM2_DTM0_CH_CTRL2_SR," bitfld.long 0xC 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x10 "CDTM2_DTM0_PS_CTRL," bitfld.long 0x10 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x10 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x10 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x10 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x10 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x14 "CDTM2_DTM0_CH0_DTV," bitfld.long 0x14 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x14 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x14 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x18 "CDTM2_DTM0_CH1_DTV," bitfld.long 0x18 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x18 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x18 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x1C "CDTM2_DTM0_CH2_DTV," bitfld.long 0x1C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x1C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x1C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x20 "CDTM2_DTM0_CH3_DTV," bitfld.long 0x20 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x20 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x20 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x24 "CDTM2_DTM0_CH_SR," bitfld.long 0x24 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x24 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x24 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x24 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x24 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x24 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x24 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x24 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x28 "CDTM2_DTM0_CH_CTRL3," bitfld.long 0x28 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x28 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x28 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x28 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x28 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x28 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x28 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x28 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x2C "CDTM2_DTM0_CTRL2," bitfld.long 0x2C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x2C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x2C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x2C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x2C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x2C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x2C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x2C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x2C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x2C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x2C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x2C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x2C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x2C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x2C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x2C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x2C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x2C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x2C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x2C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x30 "CDTM2_DTM0_CH0_DTV_SR," bitfld.long 0x30 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x30 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x30 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x30 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x30 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x30 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x34 "CDTM2_DTM0_CH1_DTV_SR," bitfld.long 0x34 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x34 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x34 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x34 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x34 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x34 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x38 "CDTM2_DTM0_CH2_DTV_SR," bitfld.long 0x38 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x38 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x38 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x38 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x38 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x38 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x3C "CDTM2_DTM0_CH3_DTV_SR," bitfld.long 0x3C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x3C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x3C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x3C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x3C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x3C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x40 "CDTM2_DTM1_CTRL," bitfld.long 0x40 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x40 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x40 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x40 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x40 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x44 "CDTM2_DTM1_CH_CTRL1," bitfld.long 0x44 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x44 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x44 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x44 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x44 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x44 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x44 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x44 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x44 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x44 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x44 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x44 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x44 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x44 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x44 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x44 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x44 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x48 "CDTM2_DTM1_CH_CTRL2," bitfld.long 0x48 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x48 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x48 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x48 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x48 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x48 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x48 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x48 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x48 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x48 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x48 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x48 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x48 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x48 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x48 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x48 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x48 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x48 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x48 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x48 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x48 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x48 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x48 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x48 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x48 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x48 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x48 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x48 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x48 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x48 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x48 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x48 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0x4C "CDTM2_DTM1_CH_CTRL2_SR," bitfld.long 0x4C 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x50 "CDTM2_DTM1_PS_CTRL," bitfld.long 0x50 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x50 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x50 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x50 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x50 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x54 "CDTM2_DTM1_CH0_DTV," bitfld.long 0x54 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x54 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x54 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x58 "CDTM2_DTM1_CH1_DTV," bitfld.long 0x58 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x58 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x58 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x5C "CDTM2_DTM1_CH2_DTV," bitfld.long 0x5C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x5C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x5C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x60 "CDTM2_DTM1_CH3_DTV," bitfld.long 0x60 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x60 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x60 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x64 "CDTM2_DTM1_CH_SR," bitfld.long 0x64 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x64 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x64 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x64 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x64 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x64 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x64 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x64 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x68 "CDTM2_DTM1_CH_CTRL3," bitfld.long 0x68 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x68 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x68 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x68 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x68 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x68 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x68 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x68 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x6C "CDTM2_DTM1_CTRL2," bitfld.long 0x6C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x6C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x6C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x6C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x6C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x6C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x6C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x6C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x6C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x6C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x6C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x6C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x6C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x6C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x6C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x6C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x6C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x6C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x6C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x6C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x70 "CDTM2_DTM1_CH0_DTV_SR," bitfld.long 0x70 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x70 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x70 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x70 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x70 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x70 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x74 "CDTM2_DTM1_CH1_DTV_SR," bitfld.long 0x74 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x74 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x74 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x74 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x74 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x74 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x78 "CDTM2_DTM1_CH2_DTV_SR," bitfld.long 0x78 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x78 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x78 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x78 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x78 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x78 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x7C "CDTM2_DTM1_CH3_DTV_SR," bitfld.long 0x7C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x7C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x7C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x7C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x7C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x7C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" group.long 0x4500++0x7F line.long 0x0 "CDTM2_DTM4_CTRL," bitfld.long 0x0 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x0 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x0 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x0 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x0 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x4 "CDTM2_DTM4_CH_CTRL1," bitfld.long 0x4 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x4 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x4 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x4 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x4 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x4 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x4 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x4 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x4 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x4 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x4 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x4 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x4 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x4 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x4 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x4 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x4 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x8 "CDTM2_DTM4_CH_CTRL2," bitfld.long 0x8 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x8 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x8 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x8 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x8 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x8 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x8 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x8 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x8 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x8 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x8 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x8 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x8 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x8 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x8 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x8 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x8 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x8 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x8 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x8 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x8 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x8 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x8 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x8 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x8 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x8 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x8 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x8 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x8 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x8 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x8 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x8 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0xC "CDTM2_DTM4_CH_CTRL2_SR," bitfld.long 0xC 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x10 "CDTM2_DTM4_PS_CTRL," bitfld.long 0x10 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x10 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x10 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x10 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x10 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x14 "CDTM2_DTM4_CH0_DTV," bitfld.long 0x14 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x14 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x14 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x18 "CDTM2_DTM4_CH1_DTV," bitfld.long 0x18 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x18 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x18 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x1C "CDTM2_DTM4_CH2_DTV," bitfld.long 0x1C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x1C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x1C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x20 "CDTM2_DTM4_CH3_DTV," bitfld.long 0x20 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x20 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x20 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x24 "CDTM2_DTM4_CH_SR," bitfld.long 0x24 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x24 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x24 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x24 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x24 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x24 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x24 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x24 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x28 "CDTM2_DTM4_CH_CTRL3," bitfld.long 0x28 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x28 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x28 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x28 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x28 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x28 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x28 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x28 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x2C "CDTM2_DTM4_CTRL2," bitfld.long 0x2C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x2C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x2C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x2C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x2C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x2C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x2C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x2C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x2C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x2C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x2C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x2C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x2C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x2C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x2C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x2C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x2C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x2C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x2C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x2C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x30 "CDTM2_DTM4_CH0_DTV_SR," bitfld.long 0x30 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x30 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x30 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x30 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x30 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x30 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x34 "CDTM2_DTM4_CH1_DTV_SR," bitfld.long 0x34 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x34 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x34 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x34 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x34 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x34 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x38 "CDTM2_DTM4_CH2_DTV_SR," bitfld.long 0x38 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x38 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x38 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x38 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x38 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x38 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x3C "CDTM2_DTM4_CH3_DTV_SR," bitfld.long 0x3C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x3C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x3C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x3C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x3C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x3C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x40 "CDTM2_DTM5_CTRL," bitfld.long 0x40 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x40 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x40 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x40 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x40 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x44 "CDTM2_DTM5_CH_CTRL1," bitfld.long 0x44 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x44 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x44 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x44 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x44 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x44 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x44 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x44 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x44 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x44 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x44 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x44 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x44 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x44 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x44 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x44 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x44 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x48 "CDTM2_DTM5_CH_CTRL2," bitfld.long 0x48 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x48 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x48 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x48 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x48 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x48 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x48 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x48 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x48 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x48 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x48 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x48 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x48 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x48 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x48 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x48 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x48 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x48 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x48 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x48 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x48 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x48 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x48 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x48 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x48 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x48 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x48 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x48 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x48 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x48 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x48 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x48 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0x4C "CDTM2_DTM5_CH_CTRL2_SR," bitfld.long 0x4C 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x50 "CDTM2_DTM5_PS_CTRL," bitfld.long 0x50 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x50 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x50 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x50 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x50 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x54 "CDTM2_DTM5_CH0_DTV," bitfld.long 0x54 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x54 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x54 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x58 "CDTM2_DTM5_CH1_DTV," bitfld.long 0x58 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x58 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x58 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x5C "CDTM2_DTM5_CH2_DTV," bitfld.long 0x5C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x5C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x5C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x60 "CDTM2_DTM5_CH3_DTV," bitfld.long 0x60 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x60 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x60 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x64 "CDTM2_DTM5_CH_SR," bitfld.long 0x64 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x64 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x64 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x64 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x64 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x64 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x64 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x64 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x68 "CDTM2_DTM5_CH_CTRL3," bitfld.long 0x68 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x68 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x68 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x68 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x68 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x68 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x68 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x68 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x6C "CDTM2_DTM5_CTRL2," bitfld.long 0x6C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x6C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x6C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x6C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x6C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x6C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x6C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x6C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x6C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x6C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x6C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x6C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x6C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x6C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x6C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x6C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x6C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x6C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x6C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x6C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x70 "CDTM2_DTM5_CH0_DTV_SR," bitfld.long 0x70 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x70 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x70 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x70 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x70 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x70 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x74 "CDTM2_DTM5_CH1_DTV_SR," bitfld.long 0x74 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x74 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x74 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x74 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x74 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x74 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x78 "CDTM2_DTM5_CH2_DTV_SR," bitfld.long 0x78 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x78 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x78 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x78 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x78 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x78 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x7C "CDTM2_DTM5_CH3_DTV_SR," bitfld.long 0x7C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x7C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x7C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x7C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x7C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x7C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" group.long 0x4800++0x47 line.long 0x0 "F2A2_CH0_ARU_RD_FIFO," hexmask.long.word 0x0 0.--8. 1. "ADDR,ARU Read address" line.long 0x4 "F2A2_CH1_ARU_RD_FIFO," hexmask.long.word 0x4 0.--8. 1. "ADDR,ARU Read address" line.long 0x8 "F2A2_CH2_ARU_RD_FIFO," hexmask.long.word 0x8 0.--8. 1. "ADDR,ARU Read address" line.long 0xC "F2A2_CH3_ARU_RD_FIFO," hexmask.long.word 0xC 0.--8. 1. "ADDR,ARU Read address" line.long 0x10 "F2A2_CH4_ARU_RD_FIFO," hexmask.long.word 0x10 0.--8. 1. "ADDR,ARU Read address" line.long 0x14 "F2A2_CH5_ARU_RD_FIFO," hexmask.long.word 0x14 0.--8. 1. "ADDR,ARU Read address" line.long 0x18 "F2A2_CH6_ARU_RD_FIFO," hexmask.long.word 0x18 0.--8. 1. "ADDR,ARU Read address" line.long 0x1C "F2A2_CH7_ARU_RD_FIFO," hexmask.long.word 0x1C 0.--8. 1. "ADDR,ARU Read address" line.long 0x20 "F2A2_CH0_STR_CFG," bitfld.long 0x20 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x20 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x24 "F2A2_CH1_STR_CFG," bitfld.long 0x24 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x24 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x28 "F2A2_CH2_STR_CFG," bitfld.long 0x28 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x28 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x2C "F2A2_CH3_STR_CFG," bitfld.long 0x2C 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x2C 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x30 "F2A2_CH4_STR_CFG," bitfld.long 0x30 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x30 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x34 "F2A2_CH5_STR_CFG," bitfld.long 0x34 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x34 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x38 "F2A2_CH6_STR_CFG," bitfld.long 0x38 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x38 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x3C "F2A2_CH7_STR_CFG," bitfld.long 0x3C 18. "DIR,Data transfer direction" "0,1" newline bitfld.long 0x3C 16.--17. "TMODE,Transfer mode for 53 bit ARU data from/to FIFO" "0,1,2,3" line.long 0x40 "F2A2_ENABLE," bitfld.long 0x40 14.--15. "STR7_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 12.--13. "STR6_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 10.--11. "STR5_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 8.--9. "STR4_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 6.--7. "STR3_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 4.--5. "STR2_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 2.--3. "STR1_EN,Enable/disable stream y" "0,1,2,3" newline bitfld.long 0x40 0.--1. "STR0_EN,Enable/disable stream y" "0,1,2,3" line.long 0x44 "F2A2_CTRL," bitfld.long 0x44 6.--7. "STR7_CONF,Reconfiguration of stream y to FIFO channel y-4" "0,1,2,3" newline bitfld.long 0x44 4.--5. "STR6_CONF,Reconfiguration of stream y to FIFO channel y-4" "0,1,2,3" newline bitfld.long 0x44 2.--3. "STR5_CONF,Reconfiguration of stream y to FIFO channel y-4" "0,1,2,3" newline bitfld.long 0x44 0.--1. "STR4_CONF,Reconfiguration of stream y to FIFO channel y-4" "0,1,2,3" group.long 0x4880++0x3 line.long 0x0 "AFD2_CH0_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x4890++0x3 line.long 0x0 "AFD2_CH1_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48A0++0x3 line.long 0x0 "AFD2_CH2_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48B0++0x3 line.long 0x0 "AFD2_CH3_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48C0++0x3 line.long 0x0 "AFD2_CH4_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48D0++0x3 line.long 0x0 "AFD2_CH5_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48E0++0x3 line.long 0x0 "AFD2_CH6_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x48F0++0x3 line.long 0x0 "AFD2_CH7_BUF_ACC," hexmask.long 0x0 0.--28. 1. "DATA,Read/write data from/to FIFO" group.long 0x4A00++0x37 line.long 0x0 "FIFO2_CH0_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO2_CH0_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO2_CH0_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO2_CH0_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO2_CH0_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO2_CH0_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO2_CH0_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO2_CH0_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO2_CH0_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO2_CH0_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO2_CH0_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO2_CH0_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO2_CH0_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO2_CH0_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4A40++0x37 line.long 0x0 "FIFO2_CH1_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO2_CH1_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO2_CH1_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO2_CH1_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO2_CH1_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO2_CH1_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO2_CH1_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO2_CH1_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO2_CH1_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO2_CH1_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO2_CH1_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO2_CH1_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO2_CH1_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO2_CH1_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4A80++0x37 line.long 0x0 "FIFO2_CH2_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO2_CH2_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO2_CH2_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO2_CH2_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO2_CH2_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO2_CH2_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO2_CH2_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO2_CH2_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO2_CH2_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO2_CH2_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO2_CH2_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO2_CH2_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO2_CH2_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO2_CH2_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4AC0++0x37 line.long 0x0 "FIFO2_CH3_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO2_CH3_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO2_CH3_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO2_CH3_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO2_CH3_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO2_CH3_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO2_CH3_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO2_CH3_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO2_CH3_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO2_CH3_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO2_CH3_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO2_CH3_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO2_CH3_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO2_CH3_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4B00++0x37 line.long 0x0 "FIFO2_CH4_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO2_CH4_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO2_CH4_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO2_CH4_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO2_CH4_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO2_CH4_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO2_CH4_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO2_CH4_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO2_CH4_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO2_CH4_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO2_CH4_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO2_CH4_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO2_CH4_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO2_CH4_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4B40++0x37 line.long 0x0 "FIFO2_CH5_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO2_CH5_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO2_CH5_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO2_CH5_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO2_CH5_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO2_CH5_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO2_CH5_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO2_CH5_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO2_CH5_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO2_CH5_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO2_CH5_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO2_CH5_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO2_CH5_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO2_CH5_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4B80++0x37 line.long 0x0 "FIFO2_CH6_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO2_CH6_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO2_CH6_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO2_CH6_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO2_CH6_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO2_CH6_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO2_CH6_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO2_CH6_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO2_CH6_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO2_CH6_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO2_CH6_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO2_CH6_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO2_CH6_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO2_CH6_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4BC0++0x37 line.long 0x0 "FIFO2_CH7_CTRL," bitfld.long 0x0 3. "WULOCK,RAM write unlock. Enable/disable direct RAM write access to the memory mapped FIFO region." "0,1" newline bitfld.long 0x0 2. "FLUSH,FIFO Flush control" "0,1" newline bitfld.long 0x0 1. "RAP,RAM access priority" "0,1" newline bitfld.long 0x0 0. "RBM,Ring buffer mode enable" "0,1" line.long 0x4 "FIFO2_CH7_END_ADDR," hexmask.long.word 0x4 0.--9. 1. "ADDR,End address for FIFO channel x (x:0...7)" line.long 0x8 "FIFO2_CH7_START_ADDR," hexmask.long.word 0x8 0.--9. 1. "ADDR,Start address for FIFO channel x (x:0...7)" line.long 0xC "FIFO2_CH7_UPPER_WM," hexmask.long.word 0xC 0.--9. 1. "ADDR,Upper watermark address." line.long 0x10 "FIFO2_CH7_LOWER_WM," hexmask.long.word 0x10 0.--9. 1. "ADDR,Lower watermark address." line.long 0x14 "FIFO2_CH7_STATUS," bitfld.long 0x14 3. "UP_WM,Upper watermark reached" "0,1" newline bitfld.long 0x14 2. "LOW_WM,Lower watermark reached" "0,1" newline bitfld.long 0x14 1. "FULL,FIFO is full." "0,1" newline bitfld.long 0x14 0. "EMPTY,FIFO is empty." "0,1" line.long 0x18 "FIFO2_CH7_FILL_LEVEL," hexmask.long.word 0x18 0.--10. 1. "LEVEL,Fill level of the current FIFO" line.long 0x1C "FIFO2_CH7_WR_PTR," hexmask.long.word 0x1C 0.--9. 1. "ADDR,Position of the write pointer" line.long 0x20 "FIFO2_CH7_RD_PTR," hexmask.long.word 0x20 0.--9. 1. "ADDR,Position of the read pointer" line.long 0x24 "FIFO2_CH7_IRQ_NOTIFY," bitfld.long 0x24 3. "FIFO_UWM,FIFO Upper watermark was overrun." "0,1" newline bitfld.long 0x24 2. "FIFO_LWM,FIFO Lower watermark was under-run." "0,1" newline bitfld.long 0x24 1. "FIFO_FULL,FIFO is full." "0,1" newline bitfld.long 0x24 0. "FIFO_EMPTY,FIFO is empty" "0,1" line.long 0x28 "FIFO2_CH7_IRQ_EN," bitfld.long 0x28 3. "FIFO_UWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 2. "FIFO_LWM_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 1. "FIFO_FULL_IRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x28 0. "FIFO_EMPTY_IRQ_EN,Interrupt enable" "0,1" line.long 0x2C "FIFO2_CH7_IRQ_FORCINT," bitfld.long 0x2C 3. "TRG_FIFO_UWM,Force interrupt of upper watermark." "0,1" newline bitfld.long 0x2C 2. "TRG_FIFO_LWM,Force interrupt of lower watermark." "0,1" newline bitfld.long 0x2C 1. "TRG_FIFO_FULL,Force interrupt of FIFO full status." "0,1" newline bitfld.long 0x2C 0. "TRG_FIFO_EMPTY,Force interrupt of FIFO empty status." "0,1" line.long 0x30 "FIFO2_CH7_IRQ_MODE," bitfld.long 0x30 3. "DMA_HYST_DIR,DMA direction in hysteresis mode" "0,1" newline bitfld.long 0x30 2. "DMA_HYSTERESIS,Enable DMA hysteresis mode." "0,1" newline bitfld.long 0x30 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x34 "FIFO2_CH7_EIRQ_EN," bitfld.long 0x34 3. "FIFO_UWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 2. "FIFO_LWM_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 1. "FIFO_FULL_EIRQ_EN,Interrupt enable." "0,1" newline bitfld.long 0x34 0. "FIFO_EMPTY_EIRQ_EN,Error interrupt enable" "0,1" group.long 0x4C00++0x4F line.long 0x0 "SPE2_CTRL_STAT," hexmask.long.byte 0x0 24.--31. 1. "FSOL,Fast Shutoff Level for TOM[i] channel 0 to 7" newline bitfld.long 0x0 23. "ETRIG_SEL,Extended trigger selection of signal SPE[i]_CTRL_STAT.TRIG_SEL" "0,1" newline bitfld.long 0x0 20.--22. "NIP,New input pattern that was detected." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "PDIR,Previous rotation direction." "0,1" newline bitfld.long 0x0 16.--18. "PIP,Previous input pattern that was detected by a regular input pattern change." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "ADIR,Rotation direction. Will be reflected in the signal SPE(i)_DIR." "0,1" newline bitfld.long 0x0 12.--14. "AIP,Input pattern that was detected by a regular input pattern change." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "SPE_PAT_PTR,Pattern selector for TOM output signals." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "FSOM,Fast Shutoff Mode" "0,1" newline bitfld.long 0x0 6. "TIM_SEL,Select TIM input signal" "0,1" newline bitfld.long 0x0 4.--5. "TRIG_SEL,Select trigger input signal." "0,1,2,3" newline bitfld.long 0x0 3. "SIE2,SPE Input enable for TIM_CHx(48)." "0,1" newline bitfld.long 0x0 2. "SIE1,SPE Input enable for TIM_CHx(48)." "0,1" newline bitfld.long 0x0 1. "SIE0,SPE Input enable for TIM_CHx(48)." "0,1" newline bitfld.long 0x0 0. "EN,SPE Submodule enable." "0,1" line.long 0x4 "SPE2_PAT," bitfld.long 0x4 29.--31. "IP7_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "IP7_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 25.--27. "IP6_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 24. "IP6_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 21.--23. "IP5_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "IP5_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 17.--19. "IP4_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "IP4_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 13.--15. "IP3_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12. "IP3_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 9.--11. "IP2_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "IP2_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 5.--7. "IP1_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4. "IP1_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 1.--3. "IP0_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "IP0_VAL,Input pattern t is a valid pattern." "0,1" line.long 0x8 "SPE2_OUT_PAT0," bitfld.long 0x8 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0xC "SPE2_OUT_PAT1," bitfld.long 0xC 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x10 "SPE2_OUT_PAT2," bitfld.long 0x10 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x14 "SPE2_OUT_PAT3," bitfld.long 0x14 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x18 "SPE2_OUT_PAT4," bitfld.long 0x18 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x1C "SPE2_OUT_PAT5," bitfld.long 0x1C 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x20 "SPE2_OUT_PAT6," bitfld.long 0x20 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x24 "SPE2_OUT_PAT7," bitfld.long 0x24 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x28 "SPE2_OUT_CTRL," bitfld.long 0x28 14.--15. "SPE_OUT_CTRL7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 12.--13. "SPE_OUT_CTRL6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 10.--11. "SPE_OUT_CTRL5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 8.--9. "SPE_OUT_CTRL4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 6.--7. "SPE_OUT_CTRL3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 4.--5. "SPE_OUT_CTRL2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 2.--3. "SPE_OUT_CTRL1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 0.--1. "SPE_OUT_CTRL0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x2C "SPE2_IRQ_NOTIFY," bitfld.long 0x2C 4. "SPE_RCMP,SPE revolution counter match event." "0,1" newline bitfld.long 0x2C 3. "SPE_BIS,Bouncing input signal detected." "0,1" newline bitfld.long 0x2C 2. "SPE_PERR,Wrong or invalid pattern detected at input." "0,1" newline bitfld.long 0x2C 1. "SPE_DCHG,SPE_DIR bit changed on behalf of new input pattern." "0,1" newline bitfld.long 0x2C 0. "SPE_NIPD,New input pattern interrupt occurred." "0,1" line.long 0x30 "SPE2_IRQ_EN," bitfld.long 0x30 4. "SPE_RCMP_IRQ_EN,SPE_RCMP_IRQ interrupt enable." "0,1" newline bitfld.long 0x30 3. "SPE_BIS_IRQ_EN,SPE_BIS_IRQ interrupt enable." "0,1" newline bitfld.long 0x30 2. "SPE_PERR_IRQ_EN,SPE_PERR_IRQ interrupt enable." "0,1" newline bitfld.long 0x30 1. "SPE_DCHG_IRQ_EN,SPE_DCHG_IRQ interrupt enable." "0,1" newline bitfld.long 0x30 0. "SPE_NIPD_IRQ_EN,SPE_NIPD_IRQ interrupt enable." "0,1" line.long 0x34 "SPE2_IRQ_FORCINT," bitfld.long 0x34 4. "TRG_SPE_RCMP,Force interrupt of SPE_RCMP." "0,1" newline bitfld.long 0x34 3. "TRG_SPE_BIS,Force interrupt of SPE_BIS." "0,1" newline bitfld.long 0x34 2. "TRG_SPE_PERR,Force interrupt of SPE_PERR." "0,1" newline bitfld.long 0x34 1. "TRG_SPE_DCHG,Force interrupt of SPE_DCHG." "0,1" newline bitfld.long 0x34 0. "TRG_SPE_NIPD,Force interrupt of SPE_NIPD." "0,1" line.long 0x38 "SPE2_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x3C "SPE2_EIRQ_EN," bitfld.long 0x3C 4. "SPE_RCMP_EIRQ_EN,SPE_RCMP_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x3C 3. "SPE_BIS_EIRQ_EN,SPE_BIS_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x3C 2. "SPE_PERR_EIRQ_EN,SPE_PERR_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x3C 1. "SPE_DCHG_EIRQ_EN,SPE_DCHG_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x3C 0. "SPE_NIPD_EIRQ_EN,SPE_NIPD_EIRQ interrupt enable." "0,1" line.long 0x40 "SPE2_REV_CNT," hexmask.long.tbyte 0x40 0.--23. 1. "REV_CNT,Input signal revolution counter" line.long 0x44 "SPE2_REV_CMP," hexmask.long.tbyte 0x44 0.--23. 1. "REV_CMP,Input signal revolution counter compare value" line.long 0x48 "SPE2_CTRL_STAT2," bitfld.long 0x48 8.--10. "SPE_PAT_PTR_BWD,Pattern selector for TOM output signals in case of SPE[i]_CMD.SPE_CTRL_CMD = 0b01 (e.g. backward direction)." "0,1,2,3,4,5,6,7" line.long 0x4C "SPE2_CMD," bitfld.long 0x4C 16. "SPE_UPD_TRIG,SPE updater trigger" "0,1" newline bitfld.long 0x4C 0.--1. "SPE_CTRL_CMD,SPE control command" "0,1,2,3" group.long 0x5000++0xB line.long 0x0 "AXIM2_FREE," bitfld.long 0x0 3. "FREE3,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 2. "FREE2,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 1. "FREE1,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 0. "FREE0,This bit represents the allocation status of the slot [t]" "0,1" line.long 0x4 "AXIM2_REQUEST," hexmask.long.byte 0x4 24.--31. 1. "REQID,This bit field shows the new allocated slot as binary encoded index. If no slot could be allocated this bit field is read as all 1 (0xff)." newline bitfld.long 0x4 3. "REQ1HOT3,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 2. "REQ1HOT2,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 1. "REQ1HOT1,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 0. "REQ1HOT0,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" line.long 0x8 "AXIM2_RELEASE," bitfld.long 0x8 3. "RELREQ3,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 2. "RELREQ2,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 1. "RELREQ1,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 0. "RELREQ0,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" group.long 0x5020++0x3 line.long 0x0 "AXIM2_SLOT0_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5028++0x3 line.long 0x0 "AXIM2_SLOT0_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5030++0xB line.long 0x0 "AXIM2_SLOT0_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM2_SLOT0_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM2_SLOT0_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5040++0x3 line.long 0x0 "AXIM2_SLOT1_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5048++0x3 line.long 0x0 "AXIM2_SLOT1_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5050++0xB line.long 0x0 "AXIM2_SLOT1_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM2_SLOT1_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM2_SLOT1_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5060++0x3 line.long 0x0 "AXIM2_SLOT2_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5068++0x3 line.long 0x0 "AXIM2_SLOT2_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5070++0xB line.long 0x0 "AXIM2_SLOT2_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM2_SLOT2_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM2_SLOT2_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5080++0x3 line.long 0x0 "AXIM2_SLOT3_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5088++0x3 line.long 0x0 "AXIM2_SLOT3_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5090++0xB line.long 0x0 "AXIM2_SLOT3_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM2_SLOT3_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM2_SLOT3_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" repeat 1024. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6000)++0x3 line.long 0x0 "FIFO2_MEMORY[$1]," hexmask.long 0x0 0.--28. 1. "DATA,FIFO memory location." repeat.end repeat 16384. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10000)++0x3 line.long 0x0 "MCS2_MEM[$1]," hexmask.long 0x0 0.--31. 1. "DATA,MCS memory location." repeat.end tree.end tree "GTM_CLS3" base ad:0x74060000 group.long 0x800++0x3F line.long 0x0 "TIM3_CH0_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM3_CH0_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM3_CH0_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM3_CH0_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM3_CH0_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM3_CH0_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM3_CH0_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM3_CH0_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM3_CH0_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM3_CH0_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM3_CH0_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM3_CH0_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM3_CH0_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM3_CH0_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM3_CH0_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM3_CH0_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x880++0x3F line.long 0x0 "TIM3_CH1_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM3_CH1_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM3_CH1_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM3_CH1_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM3_CH1_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM3_CH1_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM3_CH1_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM3_CH1_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM3_CH1_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM3_CH1_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM3_CH1_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM3_CH1_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM3_CH1_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM3_CH1_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM3_CH1_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM3_CH1_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x900++0x3F line.long 0x0 "TIM3_CH2_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM3_CH2_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM3_CH2_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM3_CH2_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM3_CH2_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM3_CH2_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM3_CH2_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM3_CH2_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM3_CH2_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM3_CH2_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM3_CH2_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM3_CH2_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM3_CH2_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM3_CH2_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM3_CH2_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM3_CH2_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x980++0x3F line.long 0x0 "TIM3_CH3_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM3_CH3_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM3_CH3_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM3_CH3_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM3_CH3_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM3_CH3_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM3_CH3_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM3_CH3_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM3_CH3_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM3_CH3_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM3_CH3_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM3_CH3_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM3_CH3_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM3_CH3_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM3_CH3_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM3_CH3_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xA00++0x3F line.long 0x0 "TIM3_CH4_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM3_CH4_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM3_CH4_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM3_CH4_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM3_CH4_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM3_CH4_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM3_CH4_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM3_CH4_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM3_CH4_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM3_CH4_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM3_CH4_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM3_CH4_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM3_CH4_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM3_CH4_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM3_CH4_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM3_CH4_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xA80++0x3F line.long 0x0 "TIM3_CH5_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM3_CH5_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM3_CH5_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM3_CH5_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM3_CH5_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM3_CH5_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM3_CH5_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM3_CH5_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM3_CH5_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM3_CH5_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM3_CH5_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM3_CH5_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM3_CH5_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM3_CH5_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM3_CH5_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM3_CH5_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xB00++0x3F line.long 0x0 "TIM3_CH6_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM3_CH6_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM3_CH6_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM3_CH6_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM3_CH6_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM3_CH6_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM3_CH6_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM3_CH6_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM3_CH6_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM3_CH6_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM3_CH6_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM3_CH6_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM3_CH6_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM3_CH6_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM3_CH6_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM3_CH6_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xB80++0x3F line.long 0x0 "TIM3_CH7_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM3_CH7_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM3_CH7_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM3_CH7_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM3_CH7_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM3_CH7_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM3_CH7_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM3_CH7_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM3_CH7_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM3_CH7_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM3_CH7_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM3_CH7_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM3_CH7_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM3_CH7_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM3_CH7_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM3_CH7_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xC00++0xB line.long 0x0 "TIM3_INP_VAL," bitfld.long 0x0 23. "TIM_IN7,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 22. "TIM_IN6,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 21. "TIM_IN5,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 20. "TIM_IN4,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 19. "TIM_IN3,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 18. "TIM_IN2,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 17. "TIM_IN1,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 16. "TIM_IN0,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 15. "F_IN7,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 14. "F_IN6,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 13. "F_IN5,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 12. "F_IN4,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 11. "F_IN3,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 10. "F_IN2,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 9. "F_IN1,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 8. "F_IN0,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 7. "F_OUT7,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 6. "F_OUT6,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 5. "F_OUT5,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 4. "F_OUT4,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 3. "F_OUT3,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 2. "F_OUT2,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 1. "F_OUT1,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 0. "F_OUT0,Signal channel x after TIM FLT unit" "0,1" line.long 0x4 "TIM3_IN_SRC," bitfld.long 0x4 30.--31. "MODE_7,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 28.--29. "VAL_7,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 26.--27. "MODE_6,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 24.--25. "VAL_6,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 22.--23. "MODE_5,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 20.--21. "VAL_5,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 18.--19. "MODE_4,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 16.--17. "VAL_4,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 14.--15. "MODE_3,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 12.--13. "VAL_3,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 10.--11. "MODE_2,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 8.--9. "VAL_2,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 6.--7. "MODE_1,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 4.--5. "VAL_1,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 2.--3. "MODE_0,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 0.--1. "VAL_0,Value to be fed to channel [x]" "0,1,2,3" line.long 0x8 "TIM3_RST," bitfld.long 0x8 7. "RST_CH7,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 6. "RST_CH6,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 5. "RST_CH5,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 4. "RST_CH4,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 3. "RST_CH3,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 2. "RST_CH2,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 1. "RST_CH1,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 0. "RST_CH0,Software reset of channel [x]" "0,1" group.long 0x1000++0x2B line.long 0x0 "TOM3_CH0_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM3_CH0_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM3_CH0_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM3_CH0_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM3_CH0_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM3_CH0_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM3_CH0_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM3_CH0_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM3_CH0_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM3_CH0_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM3_CH0_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1030++0x3 line.long 0x0 "TOM3_CH0_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1040++0x2B line.long 0x0 "TOM3_CH1_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM3_CH1_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM3_CH1_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM3_CH1_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM3_CH1_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM3_CH1_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM3_CH1_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM3_CH1_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM3_CH1_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM3_CH1_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM3_CH1_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1070++0x3 line.long 0x0 "TOM3_CH1_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1080++0x2B line.long 0x0 "TOM3_CH2_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM3_CH2_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM3_CH2_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM3_CH2_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM3_CH2_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM3_CH2_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM3_CH2_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM3_CH2_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM3_CH2_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM3_CH2_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM3_CH2_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x10B0++0x3 line.long 0x0 "TOM3_CH2_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x10C0++0x2B line.long 0x0 "TOM3_CH3_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM3_CH3_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM3_CH3_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM3_CH3_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM3_CH3_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM3_CH3_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM3_CH3_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM3_CH3_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM3_CH3_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM3_CH3_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM3_CH3_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x10F0++0x3 line.long 0x0 "TOM3_CH3_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1100++0x2B line.long 0x0 "TOM3_CH4_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM3_CH4_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM3_CH4_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM3_CH4_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM3_CH4_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM3_CH4_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM3_CH4_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM3_CH4_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM3_CH4_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM3_CH4_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM3_CH4_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1130++0x3 line.long 0x0 "TOM3_CH4_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1140++0x2B line.long 0x0 "TOM3_CH5_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM3_CH5_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM3_CH5_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM3_CH5_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM3_CH5_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM3_CH5_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM3_CH5_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM3_CH5_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM3_CH5_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM3_CH5_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM3_CH5_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1170++0x3 line.long 0x0 "TOM3_CH5_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1180++0x2B line.long 0x0 "TOM3_CH6_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM3_CH6_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM3_CH6_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM3_CH6_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM3_CH6_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM3_CH6_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM3_CH6_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM3_CH6_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM3_CH6_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM3_CH6_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM3_CH6_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x11B0++0x3 line.long 0x0 "TOM3_CH6_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x11C0++0x2B line.long 0x0 "TOM3_CH7_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM3_CH7_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM3_CH7_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM3_CH7_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM3_CH7_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM3_CH7_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM3_CH7_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM3_CH7_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM3_CH7_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM3_CH7_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM3_CH7_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x11F0++0x3 line.long 0x0 "TOM3_CH7_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1200++0x2B line.long 0x0 "TOM3_CH8_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM3_CH8_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM3_CH8_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM3_CH8_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM3_CH8_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM3_CH8_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM3_CH8_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM3_CH8_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM3_CH8_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM3_CH8_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM3_CH8_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1230++0x3 line.long 0x0 "TOM3_CH8_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1240++0x2B line.long 0x0 "TOM3_CH9_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM3_CH9_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM3_CH9_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM3_CH9_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM3_CH9_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM3_CH9_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM3_CH9_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM3_CH9_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM3_CH9_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM3_CH9_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM3_CH9_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1270++0x3 line.long 0x0 "TOM3_CH9_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1280++0x2B line.long 0x0 "TOM3_CH10_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM3_CH10_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM3_CH10_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM3_CH10_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM3_CH10_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM3_CH10_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM3_CH10_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM3_CH10_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM3_CH10_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM3_CH10_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM3_CH10_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x12B0++0x3 line.long 0x0 "TOM3_CH10_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x12C0++0x2B line.long 0x0 "TOM3_CH11_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM3_CH11_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM3_CH11_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM3_CH11_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM3_CH11_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM3_CH11_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM3_CH11_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM3_CH11_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM3_CH11_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM3_CH11_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM3_CH11_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x12F0++0x3 line.long 0x0 "TOM3_CH11_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1300++0x2B line.long 0x0 "TOM3_CH12_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM3_CH12_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM3_CH12_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM3_CH12_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM3_CH12_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM3_CH12_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM3_CH12_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM3_CH12_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM3_CH12_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM3_CH12_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM3_CH12_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1330++0x3 line.long 0x0 "TOM3_CH12_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1340++0x2B line.long 0x0 "TOM3_CH13_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM3_CH13_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM3_CH13_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM3_CH13_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM3_CH13_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM3_CH13_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM3_CH13_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM3_CH13_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM3_CH13_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM3_CH13_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM3_CH13_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1370++0x3 line.long 0x0 "TOM3_CH13_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1380++0x2B line.long 0x0 "TOM3_CH14_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM3_CH14_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM3_CH14_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM3_CH14_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM3_CH14_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM3_CH14_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM3_CH14_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM3_CH14_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM3_CH14_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM3_CH14_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM3_CH14_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x13B0++0x3 line.long 0x0 "TOM3_CH14_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x13C0++0x2B line.long 0x0 "TOM3_CH15_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM3_CH15_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM3_CH15_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM3_CH15_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM3_CH15_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM3_CH15_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM3_CH15_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM3_CH15_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM3_CH15_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM3_CH15_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM3_CH15_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x13F0++0x3 line.long 0x0 "TOM3_CH15_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1430++0xF line.long 0x0 "TOM3_TGC0_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 28.--29. "UPEN_CTRL6,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 26.--27. "UPEN_CTRL5,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 24.--25. "UPEN_CTRL4,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 22.--23. "UPEN_CTRL3,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 20.--21. "UPEN_CTRL2,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 16.--17. "UPEN_CTRL0,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 15. "RST_CH7,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 14. "RST_CH6,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 13. "RST_CH5,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 12. "RST_CH4,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 10. "RST_CH2,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 9. "RST_CH1,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 8. "RST_CH0,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see TGC0 TGC1) to update the register TOM[i]_TGC[g]_ENDIS_STAT and TOM[i]_TGC[g]_OUTEN_STAT" "0,1" line.long 0x4 "TOM3_TGC0_ACT_TB," bitfld.long 0x4 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" newline bitfld.long 0x4 24. "TB_TRIG,Set trigger request" "0,1" newline hexmask.long.tbyte 0x4 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[y] y=0..2. If selected TBU_TS[y] value is in the interval [TOM[i]_TGC[g]_ACT_TB.ACT_TB-007FFFFFh TOM[i]_TGC[g]_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x8 "TOM3_TGC0_FUPD_CTRL," bitfld.long 0x8 30.--31. "RSTCN0_CH7,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 28.--29. "RSTCN0_CH6,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 26.--27. "RSTCN0_CH5,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 24.--25. "RSTCN0_CH4,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 22.--23. "RSTCN0_CH3,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 20.--21. "RSTCN0_CH2,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 18.--19. "RSTCN0_CH1,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 16.--17. "RSTCN0_CH0,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 14.--15. "FUPD_CTRL7,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 12.--13. "FUPD_CTRL6,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 10.--11. "FUPD_CTRL5,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 8.--9. "FUPD_CTRL4,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 6.--7. "FUPD_CTRL3,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 4.--5. "FUPD_CTRL2,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 2.--3. "FUPD_CTRL1,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 0.--1. "FUPD_CTRL0,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" line.long 0xC "TOM3_TGC0_INT_TRIG," bitfld.long 0xC 14.--15. "INT_TRIG7,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 12.--13. "INT_TRIG6,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 10.--11. "INT_TRIG5,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "INT_TRIG4,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 6.--7. "INT_TRIG3,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 4.--5. "INT_TRIG2,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "INT_TRIG1,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 0.--1. "INT_TRIG0,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" group.long 0x1470++0xF line.long 0x0 "TOM3_TGC0_ENDIS_CTRL," bitfld.long 0x0 14.--15. "ENDIS_CTRL7,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 12.--13. "ENDIS_CTRL6,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 10.--11. "ENDIS_CTRL5,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 8.--9. "ENDIS_CTRL4,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 6.--7. "ENDIS_CTRL3,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ENDIS_CTRL2,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 2.--3. "ENDIS_CTRL1,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 0.--1. "ENDIS_CTRL0,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" line.long 0x4 "TOM3_TGC0_ENDIS_STAT," bitfld.long 0x4 14.--15. "ENDIS_STAT7,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 12.--13. "ENDIS_STAT6,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 10.--11. "ENDIS_STAT5,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 8.--9. "ENDIS_STAT4,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 6.--7. "ENDIS_STAT3,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 4.--5. "ENDIS_STAT2,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_STAT1,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 0.--1. "ENDIS_STAT0,TOM channel x=c + g*8 enable/disable" "0,1,2,3" line.long 0x8 "TOM3_TGC0_OUTEN_CTRL," bitfld.long 0x8 14.--15. "OUTEN_CTRL7,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 12.--13. "OUTEN_CTRL6,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OUTEN_CTRL5,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 8.--9. "OUTEN_CTRL4,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OUTEN_CTRL3,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 4.--5. "OUTEN_CTRL2,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OUTEN_CTRL1,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 0.--1. "OUTEN_CTRL0,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" line.long 0xC "TOM3_TGC0_OUTEN_STAT," bitfld.long 0xC 14.--15. "OUTEN_STAT7,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 12.--13. "OUTEN_STAT6,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 10.--11. "OUTEN_STAT5,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "OUTEN_STAT4,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 6.--7. "OUTEN_STAT3,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 4.--5. "OUTEN_STAT2,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "OUTEN_STAT1,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 0.--1. "OUTEN_STAT0,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" group.long 0x14B0++0xF line.long 0x0 "TOM3_TGC1_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 28.--29. "UPEN_CTRL6,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 26.--27. "UPEN_CTRL5,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 24.--25. "UPEN_CTRL4,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 22.--23. "UPEN_CTRL3,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 20.--21. "UPEN_CTRL2,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 16.--17. "UPEN_CTRL0,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 15. "RST_CH7,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 14. "RST_CH6,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 13. "RST_CH5,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 12. "RST_CH4,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 10. "RST_CH2,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 9. "RST_CH1,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 8. "RST_CH0,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see TGC0 TGC1) to update the register TOM[i]_TGC[g]_ENDIS_STAT and TOM[i]_TGC[g]_OUTEN_STAT" "0,1" line.long 0x4 "TOM3_TGC1_ACT_TB," bitfld.long 0x4 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" newline bitfld.long 0x4 24. "TB_TRIG,Set trigger request" "0,1" newline hexmask.long.tbyte 0x4 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[y] y=0..2. If selected TBU_TS[y] value is in the interval [TOM[i]_TGC[g]_ACT_TB.ACT_TB-007FFFFFh TOM[i]_TGC[g]_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x8 "TOM3_TGC1_FUPD_CTRL," bitfld.long 0x8 30.--31. "RSTCN0_CH7,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 28.--29. "RSTCN0_CH6,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 26.--27. "RSTCN0_CH5,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 24.--25. "RSTCN0_CH4,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 22.--23. "RSTCN0_CH3,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 20.--21. "RSTCN0_CH2,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 18.--19. "RSTCN0_CH1,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 16.--17. "RSTCN0_CH0,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 14.--15. "FUPD_CTRL7,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 12.--13. "FUPD_CTRL6,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 10.--11. "FUPD_CTRL5,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 8.--9. "FUPD_CTRL4,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 6.--7. "FUPD_CTRL3,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 4.--5. "FUPD_CTRL2,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 2.--3. "FUPD_CTRL1,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 0.--1. "FUPD_CTRL0,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" line.long 0xC "TOM3_TGC1_INT_TRIG," bitfld.long 0xC 14.--15. "INT_TRIG7,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 12.--13. "INT_TRIG6,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 10.--11. "INT_TRIG5,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "INT_TRIG4,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 6.--7. "INT_TRIG3,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 4.--5. "INT_TRIG2,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "INT_TRIG1,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 0.--1. "INT_TRIG0,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" group.long 0x14F0++0xF line.long 0x0 "TOM3_TGC1_ENDIS_CTRL," bitfld.long 0x0 14.--15. "ENDIS_CTRL7,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 12.--13. "ENDIS_CTRL6,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 10.--11. "ENDIS_CTRL5,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 8.--9. "ENDIS_CTRL4,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 6.--7. "ENDIS_CTRL3,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ENDIS_CTRL2,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 2.--3. "ENDIS_CTRL1,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 0.--1. "ENDIS_CTRL0,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" line.long 0x4 "TOM3_TGC1_ENDIS_STAT," bitfld.long 0x4 14.--15. "ENDIS_STAT7,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 12.--13. "ENDIS_STAT6,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 10.--11. "ENDIS_STAT5,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 8.--9. "ENDIS_STAT4,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 6.--7. "ENDIS_STAT3,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 4.--5. "ENDIS_STAT2,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_STAT1,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 0.--1. "ENDIS_STAT0,TOM channel x=c + g*8 enable/disable" "0,1,2,3" line.long 0x8 "TOM3_TGC1_OUTEN_CTRL," bitfld.long 0x8 14.--15. "OUTEN_CTRL7,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 12.--13. "OUTEN_CTRL6,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OUTEN_CTRL5,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 8.--9. "OUTEN_CTRL4,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OUTEN_CTRL3,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 4.--5. "OUTEN_CTRL2,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OUTEN_CTRL1,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 0.--1. "OUTEN_CTRL0,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" line.long 0xC "TOM3_TGC1_OUTEN_STAT," bitfld.long 0xC 14.--15. "OUTEN_STAT7,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 12.--13. "OUTEN_STAT6,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 10.--11. "OUTEN_STAT5,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "OUTEN_STAT4,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 6.--7. "OUTEN_STAT3,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 4.--5. "OUTEN_STAT2,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "OUTEN_STAT1,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 0.--1. "OUTEN_STAT0,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" group.long 0x1800++0x2F line.long 0x0 "ATOM3_CH0_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM3_CH0_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM3_CH0_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM3_CH0_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM3_CH0_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM3_CH0_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM3_CH0_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM3_CH0_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM3_CH0_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM3_CH0_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM3_CH0_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM3_CH0_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1834++0x3 line.long 0x0 "ATOM3_CH0_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1880++0x2F line.long 0x0 "ATOM3_CH1_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM3_CH1_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM3_CH1_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM3_CH1_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM3_CH1_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM3_CH1_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM3_CH1_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM3_CH1_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM3_CH1_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM3_CH1_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM3_CH1_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM3_CH1_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x18B4++0x3 line.long 0x0 "ATOM3_CH1_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1900++0x2F line.long 0x0 "ATOM3_CH2_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM3_CH2_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM3_CH2_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM3_CH2_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM3_CH2_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM3_CH2_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM3_CH2_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM3_CH2_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM3_CH2_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM3_CH2_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM3_CH2_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM3_CH2_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1934++0x3 line.long 0x0 "ATOM3_CH2_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1980++0x2F line.long 0x0 "ATOM3_CH3_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM3_CH3_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM3_CH3_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM3_CH3_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM3_CH3_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM3_CH3_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM3_CH3_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM3_CH3_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM3_CH3_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM3_CH3_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM3_CH3_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM3_CH3_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x19B4++0x3 line.long 0x0 "ATOM3_CH3_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A00++0x2F line.long 0x0 "ATOM3_CH4_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM3_CH4_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM3_CH4_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM3_CH4_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM3_CH4_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM3_CH4_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM3_CH4_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM3_CH4_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM3_CH4_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM3_CH4_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM3_CH4_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM3_CH4_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1A34++0x3 line.long 0x0 "ATOM3_CH4_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A80++0x2F line.long 0x0 "ATOM3_CH5_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM3_CH5_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM3_CH5_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM3_CH5_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM3_CH5_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM3_CH5_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM3_CH5_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM3_CH5_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM3_CH5_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM3_CH5_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM3_CH5_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM3_CH5_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1AB4++0x3 line.long 0x0 "ATOM3_CH5_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B00++0x2F line.long 0x0 "ATOM3_CH6_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM3_CH6_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM3_CH6_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM3_CH6_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM3_CH6_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM3_CH6_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM3_CH6_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM3_CH6_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM3_CH6_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM3_CH6_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM3_CH6_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM3_CH6_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1B34++0x3 line.long 0x0 "ATOM3_CH6_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B80++0x2F line.long 0x0 "ATOM3_CH7_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM3_CH7_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM3_CH7_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM3_CH7_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM3_CH7_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM3_CH7_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM3_CH7_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM3_CH7_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM3_CH7_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM3_CH7_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM3_CH7_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM3_CH7_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1BB4++0x3 line.long 0x0 "ATOM3_CH7_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1C40++0x1F line.long 0x0 "ATOM3_AGC_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 28.--29. "UPEN_CTRL6,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 26.--27. "UPEN_CTRL5,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 24.--25. "UPEN_CTRL4,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 22.--23. "UPEN_CTRL3,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 20.--21. "UPEN_CTRL2,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 16.--17. "UPEN_CTRL0,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 15. "RST_CH7,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 14. "RST_CH6,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 13. "RST_CH5,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 12. "RST_CH4,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 10. "RST_CH2,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 9. "RST_CH1,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 8. "RST_CH0,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see AGC) to update the register ATOM[i]_AGC_ENDIS_STAT and ATOM[i]_AGC_OUTEN_STAT" "0,1" line.long 0x4 "ATOM3_AGC_ENDIS_CTRL," bitfld.long 0x4 14.--15. "ENDIS_CTRL7,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 12.--13. "ENDIS_CTRL6,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 10.--11. "ENDIS_CTRL5,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 8.--9. "ENDIS_CTRL4,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 6.--7. "ENDIS_CTRL3,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 4.--5. "ENDIS_CTRL2,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_CTRL1,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 0.--1. "ENDIS_CTRL0,ATOM channel [k] enable/disable update value." "0,1,2,3" line.long 0x8 "ATOM3_AGC_ENDIS_STAT," bitfld.long 0x8 14.--15. "ENDIS_STAT7,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 12.--13. "ENDIS_STAT6,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 10.--11. "ENDIS_STAT5,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 8.--9. "ENDIS_STAT4,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 6.--7. "ENDIS_STAT3,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 4.--5. "ENDIS_STAT2,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 2.--3. "ENDIS_STAT1,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 0.--1. "ENDIS_STAT0,ATOM channel [k] enable/disable" "0,1,2,3" line.long 0xC "ATOM3_AGC_ACT_TB," bitfld.long 0xC 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" newline bitfld.long 0xC 24. "TB_TRIG,Set trigger request" "0,1" newline hexmask.long.tbyte 0xC 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[x] x=0..2. If selected TBU_TS[x] value is in the interval [ATOM[i]_AGC_ACT_TB.ACT_TB-007FFFFFh ATOM[i]_AGC_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x10 "ATOM3_AGC_OUTEN_CTRL," bitfld.long 0x10 14.--15. "OUTEN_CTRL7,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 12.--13. "OUTEN_CTRL6,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 10.--11. "OUTEN_CTRL5,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 8.--9. "OUTEN_CTRL4,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 6.--7. "OUTEN_CTRL3,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 4.--5. "OUTEN_CTRL2,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 2.--3. "OUTEN_CTRL1,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 0.--1. "OUTEN_CTRL0,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" line.long 0x14 "ATOM3_AGC_OUTEN_STAT," bitfld.long 0x14 14.--15. "OUTEN_STAT7,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 12.--13. "OUTEN_STAT6,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 10.--11. "OUTEN_STAT5,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 8.--9. "OUTEN_STAT4,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 6.--7. "OUTEN_STAT3,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 4.--5. "OUTEN_STAT2,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 2.--3. "OUTEN_STAT1,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 0.--1. "OUTEN_STAT0,Control/status of output ATOM_OUT [k]" "0,1,2,3" line.long 0x18 "ATOM3_AGC_FUPD_CTRL," bitfld.long 0x18 30.--31. "RSTCN0_CH7,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 28.--29. "RSTCN0_CH6,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 26.--27. "RSTCN0_CH5,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 24.--25. "RSTCN0_CH4,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 22.--23. "RSTCN0_CH3,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 20.--21. "RSTCN0_CH2,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 18.--19. "RSTCN0_CH1,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 16.--17. "RSTCN0_CH0,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 14.--15. "FUPD_CTRL7,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 12.--13. "FUPD_CTRL6,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 10.--11. "FUPD_CTRL5,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 8.--9. "FUPD_CTRL4,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 6.--7. "FUPD_CTRL3,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 4.--5. "FUPD_CTRL2,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 2.--3. "FUPD_CTRL1,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 0.--1. "FUPD_CTRL0,Force update of ATOM channel [k] operation registers" "0,1,2,3" line.long 0x1C "ATOM3_AGC_INT_TRIG," bitfld.long 0x1C 14.--15. "INT_TRIG7,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 12.--13. "INT_TRIG6,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 10.--11. "INT_TRIG5,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 8.--9. "INT_TRIG4,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 6.--7. "INT_TRIG3,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 4.--5. "INT_TRIG2,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 2.--3. "INT_TRIG1,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "INT_TRIG0,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" group.long 0x2000++0x27 line.long 0x0 "MCS3_CH0_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS3_CH0_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS3_CH0_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS3_CH0_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS3_CH0_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS3_CH0_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS3_CH0_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS3_CH0_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS3_CH0_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS3_CH0_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x203C++0x3 line.long 0x0 "MCS3_CH0_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x20E0++0x17 line.long 0x0 "MCS3_CH0_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS3_CH0_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS3_CH0_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS3_CH0_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS3_CH0_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS3_CH0_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2100++0x27 line.long 0x0 "MCS3_CH1_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS3_CH1_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS3_CH1_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS3_CH1_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS3_CH1_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS3_CH1_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS3_CH1_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS3_CH1_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS3_CH1_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS3_CH1_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x213C++0x3 line.long 0x0 "MCS3_CH1_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x21E0++0x17 line.long 0x0 "MCS3_CH1_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS3_CH1_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS3_CH1_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS3_CH1_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS3_CH1_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS3_CH1_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2200++0x27 line.long 0x0 "MCS3_CH2_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS3_CH2_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS3_CH2_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS3_CH2_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS3_CH2_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS3_CH2_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS3_CH2_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS3_CH2_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS3_CH2_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS3_CH2_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x223C++0x3 line.long 0x0 "MCS3_CH2_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x22E0++0x17 line.long 0x0 "MCS3_CH2_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS3_CH2_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS3_CH2_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS3_CH2_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS3_CH2_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS3_CH2_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2300++0x27 line.long 0x0 "MCS3_CH3_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS3_CH3_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS3_CH3_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS3_CH3_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS3_CH3_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS3_CH3_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS3_CH3_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS3_CH3_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS3_CH3_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS3_CH3_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x233C++0x3 line.long 0x0 "MCS3_CH3_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x23E0++0x17 line.long 0x0 "MCS3_CH3_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS3_CH3_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS3_CH3_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS3_CH3_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS3_CH3_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS3_CH3_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2400++0x27 line.long 0x0 "MCS3_CH4_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS3_CH4_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS3_CH4_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS3_CH4_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS3_CH4_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS3_CH4_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS3_CH4_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS3_CH4_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS3_CH4_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS3_CH4_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x243C++0x3 line.long 0x0 "MCS3_CH4_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x24E0++0x17 line.long 0x0 "MCS3_CH4_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS3_CH4_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS3_CH4_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS3_CH4_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS3_CH4_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS3_CH4_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2500++0x27 line.long 0x0 "MCS3_CH5_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS3_CH5_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS3_CH5_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS3_CH5_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS3_CH5_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS3_CH5_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS3_CH5_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS3_CH5_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS3_CH5_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS3_CH5_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x253C++0x3 line.long 0x0 "MCS3_CH5_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x25E0++0x17 line.long 0x0 "MCS3_CH5_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS3_CH5_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS3_CH5_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS3_CH5_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS3_CH5_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS3_CH5_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2600++0x27 line.long 0x0 "MCS3_CH6_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS3_CH6_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS3_CH6_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS3_CH6_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS3_CH6_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS3_CH6_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS3_CH6_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS3_CH6_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS3_CH6_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS3_CH6_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x263C++0x3 line.long 0x0 "MCS3_CH6_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x26E0++0x17 line.long 0x0 "MCS3_CH6_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS3_CH6_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS3_CH6_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS3_CH6_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS3_CH6_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS3_CH6_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2700++0x27 line.long 0x0 "MCS3_CH7_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS3_CH7_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS3_CH7_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS3_CH7_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS3_CH7_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS3_CH7_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS3_CH7_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS3_CH7_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS3_CH7_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS3_CH7_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x273C++0x3 line.long 0x0 "MCS3_CH7_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x27E0++0x17 line.long 0x0 "MCS3_CH7_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS3_CH7_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS3_CH7_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS3_CH7_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS3_CH7_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS3_CH7_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2E28++0x7 line.long 0x0 "MCS3_CTRG," bitfld.long 0x0 23. "TRG23,Trigger bit o." "0,1" newline bitfld.long 0x0 22. "TRG22,Trigger bit o." "0,1" newline bitfld.long 0x0 21. "TRG21,Trigger bit o." "0,1" newline bitfld.long 0x0 20. "TRG20,Trigger bit o." "0,1" newline bitfld.long 0x0 19. "TRG19,Trigger bit o." "0,1" newline bitfld.long 0x0 18. "TRG18,Trigger bit o." "0,1" newline bitfld.long 0x0 17. "TRG17,Trigger bit o." "0,1" newline bitfld.long 0x0 16. "TRG16,Trigger bit o." "0,1" newline bitfld.long 0x0 15. "TRG15,Trigger bit n." "0,1" newline bitfld.long 0x0 14. "TRG14,Trigger bit n." "0,1" newline bitfld.long 0x0 13. "TRG13,Trigger bit n." "0,1" newline bitfld.long 0x0 12. "TRG12,Trigger bit n." "0,1" newline bitfld.long 0x0 11. "TRG11,Trigger bit n." "0,1" newline bitfld.long 0x0 10. "TRG10,Trigger bit n." "0,1" newline bitfld.long 0x0 9. "TRG9,Trigger bit n." "0,1" newline bitfld.long 0x0 8. "TRG8,Trigger bit n." "0,1" newline bitfld.long 0x0 7. "TRG7,Trigger bit m." "0,1" newline bitfld.long 0x0 6. "TRG6,Trigger bit m." "0,1" newline bitfld.long 0x0 5. "TRG5,Trigger bit m." "0,1" newline bitfld.long 0x0 4. "TRG4,Trigger bit m." "0,1" newline bitfld.long 0x0 3. "TRG3,Trigger bit m." "0,1" newline bitfld.long 0x0 2. "TRG2,Trigger bit m." "0,1" newline bitfld.long 0x0 1. "TRG1,Trigger bit m." "0,1" newline bitfld.long 0x0 0. "TRG0,Trigger bit m." "0,1" line.long 0x4 "MCS3_STRG," bitfld.long 0x4 23. "TRG23,Trigger bit k." "0,1" newline bitfld.long 0x4 22. "TRG22,Trigger bit k." "0,1" newline bitfld.long 0x4 21. "TRG21,Trigger bit k." "0,1" newline bitfld.long 0x4 20. "TRG20,Trigger bit k." "0,1" newline bitfld.long 0x4 19. "TRG19,Trigger bit k." "0,1" newline bitfld.long 0x4 18. "TRG18,Trigger bit k." "0,1" newline bitfld.long 0x4 17. "TRG17,Trigger bit k." "0,1" newline bitfld.long 0x4 16. "TRG16,Trigger bit k." "0,1" newline bitfld.long 0x4 15. "TRG15,Trigger bit k." "0,1" newline bitfld.long 0x4 14. "TRG14,Trigger bit k." "0,1" newline bitfld.long 0x4 13. "TRG13,Trigger bit k." "0,1" newline bitfld.long 0x4 12. "TRG12,Trigger bit k." "0,1" newline bitfld.long 0x4 11. "TRG11,Trigger bit k." "0,1" newline bitfld.long 0x4 10. "TRG10,Trigger bit k." "0,1" newline bitfld.long 0x4 9. "TRG9,Trigger bit k." "0,1" newline bitfld.long 0x4 8. "TRG8,Trigger bit k." "0,1" newline bitfld.long 0x4 7. "TRG7,Trigger bit k." "0,1" newline bitfld.long 0x4 6. "TRG6,Trigger bit k." "0,1" newline bitfld.long 0x4 5. "TRG5,Trigger bit k." "0,1" newline bitfld.long 0x4 4. "TRG4,Trigger bit k." "0,1" newline bitfld.long 0x4 3. "TRG3,Trigger bit k." "0,1" newline bitfld.long 0x4 2. "TRG2,Trigger bit k." "0,1" newline bitfld.long 0x4 1. "TRG1,Trigger bit k." "0,1" newline bitfld.long 0x4 0. "TRG0,Trigger bit k." "0,1" group.long 0x2F00++0x13 line.long 0x0 "MCS3_CTRL_STAT," bitfld.long 0x0 26. "HLT_AEIM_ERR,Halt on AEI bus master error." "0,1" newline bitfld.long 0x0 25. "EN_HVD,Enable Modified Harvard architecture." "0,1" newline bitfld.long 0x0 24. "EN_TIM_FOUT,Enable routing of TIM[i]_CH[x]_F_OUT signal." "0,1" newline bitfld.long 0x0 20.--22. "ERR_SRC_ID,Error source identifier." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "RAM_RST,RAM reset bit." "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "SCD_CH,Channel selection for scheduling algorithm." newline bitfld.long 0x0 0.--1. "SCD_MODE,Select MCS scheduling mode" "0,1,2,3" line.long 0x4 "MCS3_RESET," bitfld.long 0x4 7. "RST7,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 6. "RST6,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 5. "RST5,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 4. "RST4,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 3. "RST3,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 2. "RST2,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 1. "RST1,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 0. "RST0,Software reset of channel [k]" "0,1" line.long 0x8 "MCS3_CAT," bitfld.long 0x8 7. "CAT7,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 6. "CAT6,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 5. "CAT5,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 4. "CAT4,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 3. "CAT3,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 2. "CAT2,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 1. "CAT1,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 0. "CAT0,Cancel ARU transfer of channel [k]." "0,1" line.long 0xC "MCS3_CWT," bitfld.long 0xC 7. "CWT7,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 6. "CWT6,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 5. "CWT5,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 4. "CWT4,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 3. "CWT3,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 2. "CWT2,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 1. "CWT1,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 0. "CWT0,Cancel waiting instruction for channel [k]." "0,1" line.long 0x10 "MCS3_ERR," bitfld.long 0x10 7. "ERR7,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 6. "ERR6,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 5. "ERR5,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 4. "ERR4,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 3. "ERR3,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 2. "ERR2,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 1. "ERR1,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 0. "ERR0,Error State of MCS-channel [k]." "0,1" group.long 0x2F1C++0x13 line.long 0x0 "MCS3_REG_PROT," bitfld.long 0x0 14.--15. "WPROT7,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 12.--13. "WPROT6,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 10.--11. "WPROT5,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 8.--9. "WPROT4,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 6.--7. "WPROT3,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 4.--5. "WPROT2,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 2.--3. "WPROT1,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 0.--1. "WPROT0,Register Write Protection of MCS-channel k." "0,1,2,3" line.long 0x4 "MCS3_SINT_IRQ_NOTIFY," bitfld.long 0x4 7. "S_IRQ7,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 6. "S_IRQ6,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 5. "S_IRQ5,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 4. "S_IRQ4,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 3. "S_IRQ3,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 2. "S_IRQ2,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 1. "S_IRQ1,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 0. "S_IRQ0,Shared interrupt [k] notify flag." "0,1" line.long 0x8 "MCS3_SINT_IRQ_EN," bitfld.long 0x8 7. "S_IRQ7_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 6. "S_IRQ6_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 5. "S_IRQ5_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 4. "S_IRQ4_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 3. "S_IRQ3_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 2. "S_IRQ2_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 1. "S_IRQ1_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 0. "S_IRQ0_EN,Shared interrupt [k]" "0,1" line.long 0xC "MCS3_SINT_IRQ_FORCINT," bitfld.long 0xC 7. "TRG_S_IRQ7,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 6. "TRG_S_IRQ6,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 5. "TRG_S_IRQ5,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 4. "TRG_S_IRQ4,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 3. "TRG_S_IRQ3,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 2. "TRG_S_IRQ2,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 1. "TRG_S_IRQ1,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 0. "TRG_S_IRQ0,Trigger IRQ [k] in shared interrupt register" "0,1" line.long 0x10 "MCS3_SINT_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x2F40++0x1B line.long 0x0 "MCS3_HBP0_CTRL," bitfld.long 0x0 17. "NOT,Logical negation of h-th hardware break point." "0,1" newline bitfld.long 0x0 16. "AND,Logical AND conjunction of h-th hardware break point." "0,1" newline bitfld.long 0x0 12.--14. "TYPE,Define type of h-th hardware break point." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--9. "SCOPE,Define scope of h-th hardware break point." "0,1,2,3" newline bitfld.long 0x0 7. "EN_CH7,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 6. "EN_CH6,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 5. "EN_CH5,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 4. "EN_CH4,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 3. "EN_CH3,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 2. "EN_CH2,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 1. "EN_CH1,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 0. "EN_CH0,Enable h-th hardware break point for channel x." "0,1" line.long 0x4 "MCS3_HBP0_PATTERN," hexmask.long 0x4 0.--31. 1. "DATA,Define pattern or address of h-th hardware break point." line.long 0x8 "MCS3_HBP0_STATUS," bitfld.long 0x8 7. "HALT_CH7,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 6. "HALT_CH6,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 5. "HALT_CH5,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 4. "HALT_CH4,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 3. "HALT_CH3,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 2. "HALT_CH2,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 1. "HALT_CH1,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 0. "HALT_CH0,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" line.long 0xC "MCS3_HBP0_IRQ_NOTIFY," bitfld.long 0xC 0. "HBP_IRQ,Interrupt notify flag of the h-th hardware break point." "0,1" line.long 0x10 "MCS3_HBP0_IRQ_EN," bitfld.long 0x10 0. "HBP_IRQ_EN,Interrupt Enable bit of the h-th hardware break point." "0,1" line.long 0x14 "MCS3_HBP0_IRQ_FORCINT," bitfld.long 0x14 0. "TRG_HBP_IRQ,Trigger IRQ of the h-th hardware break point." "0,1" line.long 0x18 "MCS3_HBP0_IRQ_MODE," bitfld.long 0x18 0.--1. "IRQ_MODE,IRQ mode selection for all break point interrupts." "0,1,2,3" group.long 0x2F60++0x1B line.long 0x0 "MCS3_HBP1_CTRL," bitfld.long 0x0 17. "NOT,Logical negation of h-th hardware break point." "0,1" newline bitfld.long 0x0 16. "AND,Logical AND conjunction of h-th hardware break point." "0,1" newline bitfld.long 0x0 12.--14. "TYPE,Define type of h-th hardware break point." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--9. "SCOPE,Define scope of h-th hardware break point." "0,1,2,3" newline bitfld.long 0x0 7. "EN_CH7,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 6. "EN_CH6,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 5. "EN_CH5,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 4. "EN_CH4,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 3. "EN_CH3,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 2. "EN_CH2,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 1. "EN_CH1,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 0. "EN_CH0,Enable h-th hardware break point for channel x." "0,1" line.long 0x4 "MCS3_HBP1_PATTERN," hexmask.long 0x4 0.--31. 1. "DATA,Define pattern or address of h-th hardware break point." line.long 0x8 "MCS3_HBP1_STATUS," bitfld.long 0x8 7. "HALT_CH7,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 6. "HALT_CH6,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 5. "HALT_CH5,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 4. "HALT_CH4,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 3. "HALT_CH3,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 2. "HALT_CH2,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 1. "HALT_CH1,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 0. "HALT_CH0,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" line.long 0xC "MCS3_HBP1_IRQ_NOTIFY," bitfld.long 0xC 0. "HBP_IRQ,Interrupt notify flag of the h-th hardware break point." "0,1" line.long 0x10 "MCS3_HBP1_IRQ_EN," bitfld.long 0x10 0. "HBP_IRQ_EN,Interrupt Enable bit of the h-th hardware break point." "0,1" line.long 0x14 "MCS3_HBP1_IRQ_FORCINT," bitfld.long 0x14 0. "TRG_HBP_IRQ,Trigger IRQ of the h-th hardware break point." "0,1" line.long 0x18 "MCS3_HBP1_IRQ_MODE," bitfld.long 0x18 0.--1. "IRQ_MODE,IRQ mode selection for all break point interrupts." "0,1,2,3" group.long 0x3000++0x13 line.long 0x0 "TIO3_G0_CH0_CTRL," bitfld.long 0x0 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x0 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x0 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x0 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x0 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x0 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x0 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x0 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x0 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x0 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x0 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x0 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x0 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x0 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x0 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x0 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x0 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x0 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x0 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x0 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x0 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x4 "TIO3_G0_CH0_IRQ_NOTIFY," bitfld.long 0x4 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x4 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x4 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x4 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x4 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x4 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x8 "TIO3_G0_CH0_IRQ_EN," bitfld.long 0x8 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x8 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x8 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x8 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x8 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x8 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0xC "TIO3_G0_CH0_IRQ_FORCINT," bitfld.long 0xC 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0xC 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0xC 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0xC 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0xC 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0xC 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x10 "TIO3_G0_CH0_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3020++0xB line.long 0x0 "TIO3_G0_CH0_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO3_G0_CH0_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO3_G0_CH0_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3030++0x23 line.long 0x0 "TIO3_G0_CH0_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO3_G0_CH0_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO3_G0_CH0_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO3_G0_CH0_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO3_G0_CH1_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO3_G0_CH1_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO3_G0_CH1_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO3_G0_CH1_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO3_G0_CH1_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3060++0xB line.long 0x0 "TIO3_G0_CH1_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO3_G0_CH1_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO3_G0_CH1_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3070++0x23 line.long 0x0 "TIO3_G0_CH1_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO3_G0_CH1_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO3_G0_CH1_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO3_G0_CH1_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO3_G0_CH2_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO3_G0_CH2_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO3_G0_CH2_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO3_G0_CH2_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO3_G0_CH2_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x30A0++0xB line.long 0x0 "TIO3_G0_CH2_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO3_G0_CH2_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO3_G0_CH2_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x30B0++0x23 line.long 0x0 "TIO3_G0_CH2_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO3_G0_CH2_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO3_G0_CH2_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO3_G0_CH2_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO3_G0_CH3_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO3_G0_CH3_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO3_G0_CH3_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO3_G0_CH3_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO3_G0_CH3_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x30E0++0xB line.long 0x0 "TIO3_G0_CH3_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO3_G0_CH3_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO3_G0_CH3_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x30F0++0x23 line.long 0x0 "TIO3_G0_CH3_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO3_G0_CH3_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO3_G0_CH3_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO3_G0_CH3_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO3_G0_CH4_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO3_G0_CH4_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO3_G0_CH4_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO3_G0_CH4_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO3_G0_CH4_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3120++0xB line.long 0x0 "TIO3_G0_CH4_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO3_G0_CH4_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO3_G0_CH4_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3130++0x23 line.long 0x0 "TIO3_G0_CH4_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO3_G0_CH4_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO3_G0_CH4_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO3_G0_CH4_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO3_G0_CH5_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO3_G0_CH5_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO3_G0_CH5_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO3_G0_CH5_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO3_G0_CH5_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3160++0xB line.long 0x0 "TIO3_G0_CH5_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO3_G0_CH5_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO3_G0_CH5_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3170++0x23 line.long 0x0 "TIO3_G0_CH5_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO3_G0_CH5_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO3_G0_CH5_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO3_G0_CH5_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO3_G0_CH6_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO3_G0_CH6_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO3_G0_CH6_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO3_G0_CH6_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO3_G0_CH6_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x31A0++0xB line.long 0x0 "TIO3_G0_CH6_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO3_G0_CH6_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO3_G0_CH6_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x31B0++0x23 line.long 0x0 "TIO3_G0_CH6_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO3_G0_CH6_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO3_G0_CH6_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO3_G0_CH6_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO3_G0_CH7_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO3_G0_CH7_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO3_G0_CH7_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO3_G0_CH7_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO3_G0_CH7_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x31E0++0xB line.long 0x0 "TIO3_G0_CH7_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO3_G0_CH7_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO3_G0_CH7_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x31F0++0x17 line.long 0x0 "TIO3_G0_CH7_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO3_G0_CH7_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO3_G0_CH7_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO3_G0_CH7_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO3_G0_ISEL0_CTRL1," bitfld.long 0x10 27. "WRITE_EN3,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 26. "WRITE_EN2,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 25. "WRITE_EN1,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 24. "WRITE_EN0,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 19. "OUT_SEL3,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x10 18. "OUT_SEL2,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x10 17. "OUT_SEL1,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x10 16. "OUT_SEL0,select signal for ISEL_OUT[k]" "0,1" newline hexmask.long.byte 0x10 12.--15. 1. "LUT2_3,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x10 8.--11. 1. "LUT2_2,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x10 4.--7. 1. "LUT2_1,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x10 0.--3. 1. "LUT2_0,2 bit Lookup table function for channel c=q*4+k" line.long 0x14 "TIO3_G0_ISEL0_CTRL2," bitfld.long 0x14 22. "LUT3IN_SEL2,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x14 21. "LUT3IN_SEL1,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x14 20. "LUT3IN_SEL0,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x14 16.--17. "QOUT_SEL,select source for ISEL_QOUT signal in quad = q" "0,1,2,3" newline hexmask.long.byte 0x14 0.--7. 1. "LUT3,3 bit Lookup table function for quad=q; channels q*4+2 .. q*4" group.long 0x3220++0x7 line.long 0x0 "TIO3_G0_ISEL1_CTRL1," bitfld.long 0x0 27. "WRITE_EN3,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 26. "WRITE_EN2,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 25. "WRITE_EN1,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 24. "WRITE_EN0,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 19. "OUT_SEL3,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x0 18. "OUT_SEL2,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x0 17. "OUT_SEL1,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x0 16. "OUT_SEL0,select signal for ISEL_OUT[k]" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "LUT2_3,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x0 8.--11. 1. "LUT2_2,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x0 4.--7. 1. "LUT2_1,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x0 0.--3. 1. "LUT2_0,2 bit Lookup table function for channel c=q*4+k" line.long 0x4 "TIO3_G0_ISEL1_CTRL2," bitfld.long 0x4 22. "LUT3IN_SEL2,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x4 21. "LUT3IN_SEL1,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x4 20. "LUT3IN_SEL0,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x4 16.--17. "QOUT_SEL,select source for ISEL_QOUT signal in quad = q" "0,1,2,3" newline hexmask.long.byte 0x4 0.--7. 1. "LUT3,3 bit Lookup table function for quad=q; channels q*4+2 .. q*4" group.long 0x3240++0x3 line.long 0x0 "TIO3_G0_OP_USAGE," bitfld.long 0x0 31. "WRITE_EN7,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 30. "WRITE_EN6,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 29. "WRITE_EN5,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 28. "WRITE_EN4,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 27. "WRITE_EN3,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 26. "WRITE_EN2,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 25. "WRITE_EN1,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 24. "WRITE_EN0,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 21.--23. "MODE7,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "MODE6,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15.--17. "MODE5,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "MODE4,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9.--11. "MODE3,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "MODE2,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "MODE1,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "MODE0,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" group.long 0x3C00++0x1F line.long 0x0 "TIO3_S," bitfld.long 0x0 7. "CH7,Value of channel x." "0,1" newline bitfld.long 0x0 6. "CH6,Value of channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Value of channel x." "0,1" newline bitfld.long 0x0 4. "CH4,Value of channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Value of channel x." "0,1" newline bitfld.long 0x0 2. "CH2,Value of channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Value of channel x." "0,1" newline bitfld.long 0x0 0. "CH0,Value of channel x." "0,1" line.long 0x4 "TIO3_O," bitfld.long 0x4 7. "CH7,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 6. "CH6,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 4. "CH4,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 2. "CH2,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 0. "CH0,Value driven on output of channel x." "0,1" line.long 0x8 "TIO3_ENDIS," bitfld.long 0x8 7. "CH7,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 6. "CH6,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 4. "CH4,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 2. "CH2,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 0. "CH0,Enable/Disable request of channel x." "0,1" line.long 0xC "TIO3_INVERT," bitfld.long 0xC 7. "CH7,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 6. "CH6,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 4. "CH4,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 2. "CH2,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 0. "CH0,Enable/Disable signal inversion of channel x." "0,1" line.long 0x10 "TIO3_INPUT_MODE," bitfld.long 0x10 7. "CH7,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 6. "CH6,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 4. "CH4,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 2. "CH2,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 0. "CH0,Enable/Disable input mode of channel x." "0,1" line.long 0x14 "TIO3_CYCLIC_MODE," bitfld.long 0x14 7. "CH7,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 6. "CH6,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 4. "CH4,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 2. "CH2,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 0. "CH0,Enable/Disable cyclic mode of channel x." "0,1" line.long 0x18 "TIO3_TRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 6. "CH6,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 4. "CH4,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 2. "CH2,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 0. "CH0,enable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO3_PLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 6. "CH6,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 4. "CH4,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 2. "CH2,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 0. "CH0,enable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3C40++0x1F line.long 0x0 "TIO3_CS," bitfld.long 0x0 7. "CH7,Clear channel x." "0,1" newline bitfld.long 0x0 6. "CH6,Clear channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Clear channel x." "0,1" newline bitfld.long 0x0 4. "CH4,Clear channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Clear channel x." "0,1" newline bitfld.long 0x0 2. "CH2,Clear channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Clear channel x." "0,1" newline bitfld.long 0x0 0. "CH0,Clear channel x." "0,1" line.long 0x4 "TIO3_CO," bitfld.long 0x4 7. "CH7,Clear channel x." "0,1" newline bitfld.long 0x4 6. "CH6,Clear channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Clear channel x." "0,1" newline bitfld.long 0x4 4. "CH4,Clear channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Clear channel x." "0,1" newline bitfld.long 0x4 2. "CH2,Clear channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Clear channel x." "0,1" newline bitfld.long 0x4 0. "CH0,Clear channel x." "0,1" line.long 0x8 "TIO3_CENDIS," bitfld.long 0x8 7. "CH7,Disable request of channel x." "0,1" newline bitfld.long 0x8 6. "CH6,Disable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Disable request of channel x." "0,1" newline bitfld.long 0x8 4. "CH4,Disable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Disable request of channel x." "0,1" newline bitfld.long 0x8 2. "CH2,Disable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Disable request of channel x." "0,1" newline bitfld.long 0x8 0. "CH0,Disable request of channel x." "0,1" line.long 0xC "TIO3_CINVERT," bitfld.long 0xC 7. "CH7,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 6. "CH6,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 4. "CH4,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 2. "CH2,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 0. "CH0,Disable signal inversion of channel x." "0,1" line.long 0x10 "TIO3_CINPUT_MODE," bitfld.long 0x10 7. "CH7,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 6. "CH6,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 4. "CH4,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 2. "CH2,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 0. "CH0,Disable input mode of channel x." "0,1" line.long 0x14 "TIO3_CCYCLIC_MODE," bitfld.long 0x14 7. "CH7,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 6. "CH6,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 4. "CH4,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 2. "CH2,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 0. "CH0,Disable cyclic mode of channel x." "0,1" line.long 0x18 "TIO3_CTRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 6. "CH6,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 4. "CH4,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 2. "CH2,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 0. "CH0,disable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO3_CPLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 6. "CH6,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 4. "CH4,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 2. "CH2,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 0. "CH0,disable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3C80++0x1F line.long 0x0 "TIO3_SS," bitfld.long 0x0 7. "CH7,Set channel x." "0,1" newline bitfld.long 0x0 6. "CH6,Set channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Set channel x." "0,1" newline bitfld.long 0x0 4. "CH4,Set channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Set channel x." "0,1" newline bitfld.long 0x0 2. "CH2,Set channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Set channel x." "0,1" newline bitfld.long 0x0 0. "CH0,Set channel x." "0,1" line.long 0x4 "TIO3_SO," bitfld.long 0x4 7. "CH7,Set channel x." "0,1" newline bitfld.long 0x4 6. "CH6,Set channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Set channel x." "0,1" newline bitfld.long 0x4 4. "CH4,Set channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Set channel x." "0,1" newline bitfld.long 0x4 2. "CH2,Set channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Set channel x." "0,1" newline bitfld.long 0x4 0. "CH0,Set channel x." "0,1" line.long 0x8 "TIO3_SENDIS," bitfld.long 0x8 7. "CH7,Enable request of channel x." "0,1" newline bitfld.long 0x8 6. "CH6,Enable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Enable request of channel x." "0,1" newline bitfld.long 0x8 4. "CH4,Enable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Enable request of channel x." "0,1" newline bitfld.long 0x8 2. "CH2,Enable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Enable request of channel x." "0,1" newline bitfld.long 0x8 0. "CH0,Enable request of channel x." "0,1" line.long 0xC "TIO3_SINVERT," bitfld.long 0xC 7. "CH7,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 6. "CH6,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 4. "CH4,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 2. "CH2,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 0. "CH0,Enable signal inversion of channel x." "0,1" line.long 0x10 "TIO3_SINPUT_MODE," bitfld.long 0x10 7. "CH7,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 6. "CH6,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 4. "CH4,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 2. "CH2,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 0. "CH0,Enable input mode of channel x." "0,1" line.long 0x14 "TIO3_SCYCLIC_MODE," bitfld.long 0x14 7. "CH7,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 6. "CH6,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 4. "CH4,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 2. "CH2,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 0. "CH0,Enable cyclic mode of channel x." "0,1" line.long 0x18 "TIO3_STRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 6. "CH6,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 4. "CH4,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 2. "CH2,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 0. "CH0,enable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO3_SPLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 6. "CH6,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 4. "CH4,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 2. "CH2,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 0. "CH0,enable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3CC0++0x17 line.long 0x0 "TIO3_IS," bitfld.long 0x0 7. "CH7,Invert channel x." "0,1" newline bitfld.long 0x0 6. "CH6,Invert channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Invert channel x." "0,1" newline bitfld.long 0x0 4. "CH4,Invert channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Invert channel x." "0,1" newline bitfld.long 0x0 2. "CH2,Invert channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Invert channel x." "0,1" newline bitfld.long 0x0 0. "CH0,Invert channel x." "0,1" line.long 0x4 "TIO3_IO," bitfld.long 0x4 7. "CH7,Invert channel x." "0,1" newline bitfld.long 0x4 6. "CH6,Invert channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Invert channel x." "0,1" newline bitfld.long 0x4 4. "CH4,Invert channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Invert channel x." "0,1" newline bitfld.long 0x4 2. "CH2,Invert channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Invert channel x." "0,1" newline bitfld.long 0x4 0. "CH0,Invert channel x." "0,1" line.long 0x8 "TIO3_IENDIS," bitfld.long 0x8 7. "CH7,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 6. "CH6,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 4. "CH4,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 2. "CH2,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 0. "CH0,Toggle state request of channel x." "0,1" line.long 0xC "TIO3_IINVERT," bitfld.long 0xC 7. "CH7,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 6. "CH6,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 4. "CH4,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 2. "CH2,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 0. "CH0,Invert signal inversion of channel x." "0,1" line.long 0x10 "TIO3_IINPUT_MODE," bitfld.long 0x10 7. "CH7,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 6. "CH6,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 4. "CH4,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 2. "CH2,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 0. "CH0,Toggle input mode of channel x." "0,1" line.long 0x14 "TIO3_ICYCLIC_MODE," bitfld.long 0x14 7. "CH7,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 6. "CH6,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 4. "CH4,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 2. "CH2,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 0. "CH0,Toggle cyclic mode of channel x." "0,1" group.long 0x3D00++0x13 line.long 0x0 "TIO3_FUPD," bitfld.long 0x0 7. "CH7,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 6. "CH6,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 5. "CH5,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 4. "CH4,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 3. "CH3,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 2. "CH2,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 1. "CH1,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 0. "CH0,issue immediately a signal pulse on the update signal of channel x" "0,1" line.long 0x4 "TIO3_HW_CONF," bitfld.long 0x4 4. "TIO_PLUS,signals availablity of TIOplus functionality" "0,1" newline bitfld.long 0x4 0.--1. "NTIO_CH8,signals availablity of amount of channels" "0,1,2,3" line.long 0x8 "TIO3_RSEL_CTRL1," bitfld.long 0x8 28. "SEL_CLKEN7_0,select source of RS_CLKEN7[g][7] for channels g*8 .. g*8+7" "0,1" newline bitfld.long 0x8 24. "SEL_CLKEN6_0,select source of RS_CLKEN[g][6] for channels g*8 .. g*8+7" "0,1" line.long 0xC "TIO3_RSEL_CTRL2," bitfld.long 0xC 8. "SEL_TB2_0,select source of RS_TB2[g] for channels g*8 .. g*8+7" "0,1" newline bitfld.long 0xC 4. "SEL_TB1_0,select source of RS_TB1[g] for channels g*8 .. g*8+7" "0,1" line.long 0x10 "TIO3_PL_SWRST," bitfld.long 0x10 7. "CH7,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 6. "CH6,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 5. "CH5,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 4. "CH4,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 3. "CH3,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 2. "CH2,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 1. "CH1,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 0. "CH0,reset TIO_Plus resources of channel x" "0,1" group.long 0x4000++0x4F line.long 0x0 "CCM3_ARP0_CTRL," bitfld.long 0x0 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x0 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x0 0.--15. 1. "ADDR,ARP base address." line.long 0x4 "CCM3_ARP0_PROT," bitfld.long 0x4 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x8 "CCM3_ARP1_CTRL," bitfld.long 0x8 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x8 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x8 0.--15. 1. "ADDR,ARP base address." line.long 0xC "CCM3_ARP1_PROT," bitfld.long 0xC 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x10 "CCM3_ARP2_CTRL," bitfld.long 0x10 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x10 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x10 0.--15. 1. "ADDR,ARP base address." line.long 0x14 "CCM3_ARP2_PROT," bitfld.long 0x14 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x18 "CCM3_ARP3_CTRL," bitfld.long 0x18 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x18 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x18 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x18 0.--15. 1. "ADDR,ARP base address." line.long 0x1C "CCM3_ARP3_PROT," bitfld.long 0x1C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x20 "CCM3_ARP4_CTRL," bitfld.long 0x20 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x20 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x20 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x20 0.--15. 1. "ADDR,ARP base address." line.long 0x24 "CCM3_ARP4_PROT," bitfld.long 0x24 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x28 "CCM3_ARP5_CTRL," bitfld.long 0x28 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x28 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x28 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x28 0.--15. 1. "ADDR,ARP base address." line.long 0x2C "CCM3_ARP5_PROT," bitfld.long 0x2C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x30 "CCM3_ARP6_CTRL," bitfld.long 0x30 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x30 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x30 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x30 0.--15. 1. "ADDR,ARP base address." line.long 0x34 "CCM3_ARP6_PROT," bitfld.long 0x34 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x38 "CCM3_ARP7_CTRL," bitfld.long 0x38 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x38 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x38 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x38 0.--15. 1. "ADDR,ARP base address." line.long 0x3C "CCM3_ARP7_PROT," bitfld.long 0x3C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x40 "CCM3_ARP8_CTRL," bitfld.long 0x40 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x40 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x40 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x40 0.--15. 1. "ADDR,ARP base address." line.long 0x44 "CCM3_ARP8_PROT," bitfld.long 0x44 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x48 "CCM3_ARP9_CTRL," bitfld.long 0x48 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x48 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x48 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x48 0.--15. 1. "ADDR,ARP base address." line.long 0x4C "CCM3_ARP9_PROT," bitfld.long 0x4C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 0. "WPROT0,Write Protection MCS channel x." "0,1" group.long 0x41CC++0x3 line.long 0x0 "CCM3_TIO_G0_OUT," bitfld.long 0x0 31. "TIO_G1_OUT_N7,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 30. "TIO_G1_OUT_N6,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 29. "TIO_G1_OUT_N5,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 28. "TIO_G1_OUT_N4,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 27. "TIO_G1_OUT_N3,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 26. "TIO_G1_OUT_N2,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 25. "TIO_G1_OUT_N1,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 24. "TIO_G1_OUT_N0,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 23. "TIO_G0_OUT_N7,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 22. "TIO_G0_OUT_N6,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 21. "TIO_G0_OUT_N5,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 20. "TIO_G0_OUT_N4,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 19. "TIO_G0_OUT_N3,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 18. "TIO_G0_OUT_N2,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 17. "TIO_G0_OUT_N1,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 16. "TIO_G0_OUT_N0,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 15. "TIO_G1_OUT7,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 14. "TIO_G1_OUT6,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 13. "TIO_G1_OUT5,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 12. "TIO_G1_OUT4,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 11. "TIO_G1_OUT3,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 10. "TIO_G1_OUT2,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 9. "TIO_G1_OUT1,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 8. "TIO_G1_OUT0,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 7. "TIO_G0_OUT7,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 6. "TIO_G0_OUT6,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 5. "TIO_G0_OUT5,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 4. "TIO_G0_OUT4,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 3. "TIO_G0_OUT3,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 2. "TIO_G0_OUT2,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 1. "TIO_G0_OUT1,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 0. "TIO_G0_OUT0,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" group.long 0x41D4++0x2B line.long 0x0 "CCM3_HW_CONF2," bitfld.long 0x0 18. "AXIM_DATA_SIZE,Defines the data bus width of the AXI master interface" "0,1" newline bitfld.long 0x0 16. "AXIS_DATA_SIZE,Defines the data bus width of the AXI slave interface" "0,1" newline bitfld.long 0x0 9. "TIO_OUT_RST,TIO_OUT reset level" "0,1" newline bitfld.long 0x0 7. "AXIM_POSTED_WRITE,Write transaction without response" "0,1" newline bitfld.long 0x0 6. "AXIM_SEC_ACC,Secure AXI master access constant" "0,1" newline bitfld.long 0x0 5. "AXIM_PRIV_ACC,Privileged AXI master access constant" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "AXIM_ID_WIDTH,Defines which LSB of AXIM_ID are send to the bus" line.long 0x4 "CCM3_AEIM_STA," bitfld.long 0x4 24.--25. "AEIM_XPT_STA,AEIM Exception status." "0,1,2,3" newline hexmask.long.word 0x4 0.--15. 1. "AEIM_XPT_ADDR,Exception Address." line.long 0x8 "CCM3_HW_CONF," bitfld.long 0x8 31. "AEI_RDATA_PIPELINE_STAGE,Read data pipeline stage implemented" "0,1" newline bitfld.long 0x8 30. "AEI_ADDR_PIPELINE_STAGE,Address pipeline stage implemented" "0,1" newline bitfld.long 0x8 29. "INT_CLK_EN_GEN,Internal clock enable generation" "0,1" newline hexmask.long.byte 0x8 24.--28. 1. "TOM_TRIG_INTCHAIN,TOM internal trigger chain length without synchronization register" newline hexmask.long.byte 0x8 20.--23. 1. "ATOM_TRIG_INTCHAIN,ATOM internal trigger chain length without synchronization register" newline bitfld.long 0x8 19. "IRQ_MODE_SINGLE_PULSE,Signalize availability of Single Pulse IRQ mode" "0,1" newline bitfld.long 0x8 18. "IRQ_MODE_PULSE_NOTIFY,Signalize availability of Pulse Notoify IRQ mode" "0,1" newline bitfld.long 0x8 17. "IRQ_MODE_PULSE,Signalize availability of Pulse IRQ mode" "0,1" newline bitfld.long 0x8 16. "IRQ_MODE_LEVEL,Signalize availability of Level IRQ mode" "0,1" newline bitfld.long 0x8 15. "RESET_ACTIVE,Active level of asynchronous reset" "0,1" newline bitfld.long 0x8 13. "ERM,Enable RAM1 MSB for available MCS modules" "0,1" newline bitfld.long 0x8 12. "RAM_INIT_RST,RAM initialization from reset" "0,1" newline bitfld.long 0x8 9.--11. "TOM_TRIG_CHAIN,TOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "TOM_OUT_RST,TOM_OUT reset level" "0,1" newline bitfld.long 0x8 5.--7. "ATOM_TRIG_CHAIN,ATOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "ATOM_OUT_RST,ATOM_OUT reset level" "0,1" newline bitfld.long 0x8 3. "CFG_CLOCK_RATE,Clocks per ARU transfer" "0,1" newline bitfld.long 0x8 2. "SYNC_INPUT_REG,Additional pipelined stage in synchronous bridge mode" "0,1" newline bitfld.long 0x8 1. "BRIDGE_MODE_RST,Bridge mode after reset" "0,1" newline bitfld.long 0x8 0. "GRSTEN,Global Reset Enable" "0,1" line.long 0xC "CCM3_TIM_AUX_IN_SRC," bitfld.long 0xC 23. "SEL_OUT_N_CH7,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 22. "SEL_OUT_N_CH6,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 21. "SEL_OUT_N_CH5,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 20. "SEL_OUT_N_CH4,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 19. "SEL_OUT_N_CH3,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 18. "SEL_OUT_N_CH2,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 17. "SEL_OUT_N_CH1,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 16. "SEL_OUT_N_CH0,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 7. "SRC_CH7,Defines AUX_IN source of TIM[i] channel 7" "0,1" newline bitfld.long 0xC 6. "SRC_CH6,Defines AUX_IN source of TIM[i] channel 6" "0,1" newline bitfld.long 0xC 5. "SRC_CH5,Defines AUX_IN source of TIM[i] channel 5" "0,1" newline bitfld.long 0xC 4. "SRC_CH4,Defines AUX_IN source of TIM[i] channel 4" "0,1" newline bitfld.long 0xC 3. "SRC_CH3,Defines AUX_IN source of TIM[i] channel 3" "0,1" newline bitfld.long 0xC 2. "SRC_CH2,Defines AUX_IN source of TIM[i] channel 2" "0,1" newline bitfld.long 0xC 1. "SRC_CH1,Defines AUX_IN source of TIM[i] channel 1" "0,1" newline bitfld.long 0xC 0. "SRC_CH0,Defines AUX_IN source of TIM[i] channel 0" "0,1" line.long 0x10 "CCM3_EXT_CAP_EN," bitfld.long 0x10 15. "TIM_IP1_EXT_CAP_EN7,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 14. "TIM_IP1_EXT_CAP_EN6,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 13. "TIM_IP1_EXT_CAP_EN5,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 12. "TIM_IP1_EXT_CAP_EN4,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 11. "TIM_IP1_EXT_CAP_EN3,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 10. "TIM_IP1_EXT_CAP_EN2,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 9. "TIM_IP1_EXT_CAP_EN1,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 8. "TIM_IP1_EXT_CAP_EN0,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 7. "TIM_I_EXT_CAP_EN7,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 6. "TIM_I_EXT_CAP_EN6,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 5. "TIM_I_EXT_CAP_EN5,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 4. "TIM_I_EXT_CAP_EN4,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 3. "TIM_I_EXT_CAP_EN3,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 2. "TIM_I_EXT_CAP_EN2,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 1. "TIM_I_EXT_CAP_EN1,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 0. "TIM_I_EXT_CAP_EN0,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" line.long 0x14 "CCM3_TOM_OUT," bitfld.long 0x14 31. "TOM_OUT_N15,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 30. "TOM_OUT_N14,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 29. "TOM_OUT_N13,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 28. "TOM_OUT_N12,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 27. "TOM_OUT_N11,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 26. "TOM_OUT_N10,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 25. "TOM_OUT_N9,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 24. "TOM_OUT_N8,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 23. "TOM_OUT_N7,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 22. "TOM_OUT_N6,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 21. "TOM_OUT_N5,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 20. "TOM_OUT_N4,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 19. "TOM_OUT_N3,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 18. "TOM_OUT_N2,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 17. "TOM_OUT_N1,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 16. "TOM_OUT_N0,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 15. "TOM_OUT15,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 14. "TOM_OUT14,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 13. "TOM_OUT13,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 12. "TOM_OUT12,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 11. "TOM_OUT11,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 10. "TOM_OUT10,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 9. "TOM_OUT9,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 8. "TOM_OUT8,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 7. "TOM_OUT7,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 6. "TOM_OUT6,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 5. "TOM_OUT5,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 4. "TOM_OUT4,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 3. "TOM_OUT3,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 2. "TOM_OUT2,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 1. "TOM_OUT1,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 0. "TOM_OUT0,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" line.long 0x18 "CCM3_ATOM_OUT," bitfld.long 0x18 31. "ATOM_IP1_OUT_N7,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 30. "ATOM_IP1_OUT_N6,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 29. "ATOM_IP1_OUT_N5,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 28. "ATOM_IP1_OUT_N4,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 27. "ATOM_IP1_OUT_N3,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 26. "ATOM_IP1_OUT_N2,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 25. "ATOM_IP1_OUT_N1,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 24. "ATOM_IP1_OUT_N0,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 23. "ATOM_IP1_OUT7,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 22. "ATOM_IP1_OUT6,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 21. "ATOM_IP1_OUT5,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 20. "ATOM_IP1_OUT4,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 19. "ATOM_IP1_OUT3,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 18. "ATOM_IP1_OUT2,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 17. "ATOM_IP1_OUT1,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 16. "ATOM_IP1_OUT0,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 15. "ATOM_I_OUT_N7,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 14. "ATOM_I_OUT_N6,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 13. "ATOM_I_OUT_N5,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 12. "ATOM_I_OUT_N4,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 11. "ATOM_I_OUT_N3,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 10. "ATOM_I_OUT_N2,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 9. "ATOM_I_OUT_N1,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 8. "ATOM_I_OUT_N0,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 7. "ATOM_I_OUT7,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 6. "ATOM_I_OUT6,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 5. "ATOM_I_OUT5,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 4. "ATOM_I_OUT4,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 3. "ATOM_I_OUT3,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 2. "ATOM_I_OUT2,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 1. "ATOM_I_OUT1,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 0. "ATOM_I_OUT0,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" line.long 0x1C "CCM3_CMU_CLK_CFG," bitfld.long 0x1C 28.--29. "CLK7_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 24.--25. "CLK6_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 20.--21. "CLK5_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 16.--17. "CLK4_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 12.--13. "CLK3_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 8.--9. "CLK2_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 4.--5. "CLK1_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "CLK0_SRC,Clock y source signal selector" "0,1,2,3" line.long 0x20 "CCM3_CMU_FXCLK_CFG," hexmask.long.byte 0x20 0.--3. 1. "FXCLK0_SRC,Fixed clock 0 source signal selector" line.long 0x24 "CCM3_CFG," bitfld.long 0x24 31. "TBU_DIR2,DIR1 input signal of module TBU timebase [z]." "0,1" newline bitfld.long 0x24 30. "TBU_DIR1,DIR1 input signal of module TBU timebase [z]." "0,1" newline bitfld.long 0x24 16.--17. "CLS_CLK_DIV,Cluster Clock Divider." "0,1,2,3" newline bitfld.long 0x24 8. "EN_TIO_DTM,Enable TIO and connected DTM" "0,1" newline bitfld.long 0x24 7. "EN_CMP_MON,Enable CMP and MON" "0,1" newline bitfld.long 0x24 6. "EN_PSM,Enable PSM" "0,1" newline bitfld.long 0x24 5. "EN_BRC,Enable BRC" "0,1" newline bitfld.long 0x24 4. "EN_DPLL_MAP,Enable DPLL and MAP" "0,1" newline bitfld.long 0x24 3. "EN_MCS,Enable MCS" "0,1" newline bitfld.long 0x24 2. "EN_ATOM_ADTM,Enable ATOM and ADTM" "0,1" newline bitfld.long 0x24 1. "EN_TOM_SPE_TDTM,Enable TOM SPE and TDTM" "0,1" newline bitfld.long 0x24 0. "EN_TIM,Enable TIM" "0,1" line.long 0x28 "CCM3_PROT," bitfld.long 0x28 0. "CLS_PROT,Cluster Protection" "0,1" group.long 0x4400++0x7F line.long 0x0 "CDTM3_DTM0_CTRL," bitfld.long 0x0 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x0 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x0 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x0 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x0 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x4 "CDTM3_DTM0_CH_CTRL1," bitfld.long 0x4 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x4 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x4 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x4 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x4 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x4 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x4 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x4 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x4 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x4 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x4 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x4 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x4 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x4 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x4 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x4 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x4 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x8 "CDTM3_DTM0_CH_CTRL2," bitfld.long 0x8 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x8 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x8 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x8 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x8 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x8 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x8 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x8 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x8 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x8 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x8 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x8 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x8 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x8 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x8 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x8 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x8 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x8 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x8 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x8 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x8 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x8 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x8 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x8 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x8 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x8 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x8 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x8 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x8 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x8 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x8 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x8 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0xC "CDTM3_DTM0_CH_CTRL2_SR," bitfld.long 0xC 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x10 "CDTM3_DTM0_PS_CTRL," bitfld.long 0x10 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x10 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x10 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x10 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x10 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x14 "CDTM3_DTM0_CH0_DTV," bitfld.long 0x14 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x14 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x14 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x18 "CDTM3_DTM0_CH1_DTV," bitfld.long 0x18 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x18 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x18 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x1C "CDTM3_DTM0_CH2_DTV," bitfld.long 0x1C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x1C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x1C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x20 "CDTM3_DTM0_CH3_DTV," bitfld.long 0x20 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x20 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x20 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x24 "CDTM3_DTM0_CH_SR," bitfld.long 0x24 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x24 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x24 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x24 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x24 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x24 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x24 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x24 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x28 "CDTM3_DTM0_CH_CTRL3," bitfld.long 0x28 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x28 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x28 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x28 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x28 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x28 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x28 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x28 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x2C "CDTM3_DTM0_CTRL2," bitfld.long 0x2C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x2C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x2C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x2C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x2C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x2C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x2C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x2C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x2C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x2C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x2C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x2C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x2C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x2C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x2C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x2C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x2C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x2C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x2C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x2C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x30 "CDTM3_DTM0_CH0_DTV_SR," bitfld.long 0x30 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x30 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x30 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x30 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x30 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x30 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x34 "CDTM3_DTM0_CH1_DTV_SR," bitfld.long 0x34 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x34 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x34 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x34 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x34 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x34 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x38 "CDTM3_DTM0_CH2_DTV_SR," bitfld.long 0x38 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x38 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x38 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x38 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x38 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x38 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x3C "CDTM3_DTM0_CH3_DTV_SR," bitfld.long 0x3C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x3C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x3C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x3C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x3C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x3C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x40 "CDTM3_DTM1_CTRL," bitfld.long 0x40 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x40 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x40 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x40 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x40 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x44 "CDTM3_DTM1_CH_CTRL1," bitfld.long 0x44 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x44 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x44 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x44 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x44 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x44 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x44 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x44 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x44 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x44 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x44 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x44 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x44 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x44 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x44 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x44 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x44 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x48 "CDTM3_DTM1_CH_CTRL2," bitfld.long 0x48 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x48 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x48 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x48 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x48 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x48 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x48 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x48 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x48 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x48 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x48 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x48 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x48 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x48 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x48 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x48 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x48 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x48 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x48 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x48 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x48 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x48 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x48 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x48 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x48 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x48 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x48 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x48 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x48 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x48 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x48 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x48 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0x4C "CDTM3_DTM1_CH_CTRL2_SR," bitfld.long 0x4C 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x50 "CDTM3_DTM1_PS_CTRL," bitfld.long 0x50 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x50 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x50 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x50 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x50 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x54 "CDTM3_DTM1_CH0_DTV," bitfld.long 0x54 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x54 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x54 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x58 "CDTM3_DTM1_CH1_DTV," bitfld.long 0x58 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x58 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x58 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x5C "CDTM3_DTM1_CH2_DTV," bitfld.long 0x5C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x5C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x5C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x60 "CDTM3_DTM1_CH3_DTV," bitfld.long 0x60 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x60 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x60 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x64 "CDTM3_DTM1_CH_SR," bitfld.long 0x64 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x64 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x64 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x64 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x64 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x64 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x64 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x64 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x68 "CDTM3_DTM1_CH_CTRL3," bitfld.long 0x68 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x68 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x68 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x68 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x68 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x68 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x68 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x68 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x6C "CDTM3_DTM1_CTRL2," bitfld.long 0x6C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x6C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x6C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x6C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x6C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x6C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x6C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x6C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x6C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x6C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x6C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x6C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x6C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x6C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x6C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x6C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x6C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x6C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x6C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x6C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x70 "CDTM3_DTM1_CH0_DTV_SR," bitfld.long 0x70 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x70 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x70 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x70 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x70 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x70 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x74 "CDTM3_DTM1_CH1_DTV_SR," bitfld.long 0x74 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x74 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x74 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x74 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x74 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x74 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x78 "CDTM3_DTM1_CH2_DTV_SR," bitfld.long 0x78 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x78 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x78 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x78 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x78 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x78 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x7C "CDTM3_DTM1_CH3_DTV_SR," bitfld.long 0x7C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x7C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x7C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x7C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x7C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x7C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" group.long 0x4500++0x7F line.long 0x0 "CDTM3_DTM4_CTRL," bitfld.long 0x0 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x0 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x0 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x0 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x0 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x4 "CDTM3_DTM4_CH_CTRL1," bitfld.long 0x4 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x4 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x4 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x4 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x4 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x4 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x4 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x4 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x4 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x4 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x4 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x4 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x4 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x4 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x4 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x4 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x4 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x8 "CDTM3_DTM4_CH_CTRL2," bitfld.long 0x8 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x8 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x8 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x8 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x8 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x8 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x8 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x8 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x8 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x8 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x8 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x8 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x8 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x8 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x8 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x8 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x8 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x8 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x8 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x8 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x8 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x8 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x8 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x8 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x8 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x8 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x8 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x8 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x8 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x8 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x8 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x8 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0xC "CDTM3_DTM4_CH_CTRL2_SR," bitfld.long 0xC 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x10 "CDTM3_DTM4_PS_CTRL," bitfld.long 0x10 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x10 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x10 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x10 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x10 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x14 "CDTM3_DTM4_CH0_DTV," bitfld.long 0x14 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x14 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x14 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x18 "CDTM3_DTM4_CH1_DTV," bitfld.long 0x18 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x18 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x18 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x1C "CDTM3_DTM4_CH2_DTV," bitfld.long 0x1C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x1C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x1C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x20 "CDTM3_DTM4_CH3_DTV," bitfld.long 0x20 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x20 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x20 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x24 "CDTM3_DTM4_CH_SR," bitfld.long 0x24 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x24 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x24 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x24 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x24 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x24 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x24 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x24 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x28 "CDTM3_DTM4_CH_CTRL3," bitfld.long 0x28 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x28 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x28 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x28 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x28 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x28 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x28 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x28 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x2C "CDTM3_DTM4_CTRL2," bitfld.long 0x2C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x2C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x2C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x2C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x2C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x2C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x2C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x2C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x2C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x2C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x2C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x2C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x2C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x2C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x2C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x2C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x2C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x2C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x2C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x2C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x30 "CDTM3_DTM4_CH0_DTV_SR," bitfld.long 0x30 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x30 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x30 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x30 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x30 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x30 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x34 "CDTM3_DTM4_CH1_DTV_SR," bitfld.long 0x34 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x34 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x34 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x34 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x34 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x34 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x38 "CDTM3_DTM4_CH2_DTV_SR," bitfld.long 0x38 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x38 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x38 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x38 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x38 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x38 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x3C "CDTM3_DTM4_CH3_DTV_SR," bitfld.long 0x3C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x3C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x3C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x3C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x3C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x3C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x40 "CDTM3_DTM5_CTRL," bitfld.long 0x40 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x40 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x40 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x40 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x40 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x44 "CDTM3_DTM5_CH_CTRL1," bitfld.long 0x44 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x44 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x44 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x44 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x44 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x44 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x44 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x44 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x44 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x44 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x44 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x44 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x44 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x44 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x44 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x44 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x44 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x48 "CDTM3_DTM5_CH_CTRL2," bitfld.long 0x48 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x48 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x48 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x48 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x48 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x48 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x48 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x48 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x48 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x48 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x48 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x48 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x48 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x48 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x48 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x48 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x48 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x48 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x48 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x48 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x48 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x48 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x48 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x48 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x48 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x48 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x48 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x48 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x48 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x48 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x48 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x48 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0x4C "CDTM3_DTM5_CH_CTRL2_SR," bitfld.long 0x4C 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x50 "CDTM3_DTM5_PS_CTRL," bitfld.long 0x50 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x50 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x50 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x50 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x50 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x54 "CDTM3_DTM5_CH0_DTV," bitfld.long 0x54 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x54 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x54 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x58 "CDTM3_DTM5_CH1_DTV," bitfld.long 0x58 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x58 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x58 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x5C "CDTM3_DTM5_CH2_DTV," bitfld.long 0x5C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x5C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x5C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x60 "CDTM3_DTM5_CH3_DTV," bitfld.long 0x60 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x60 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x60 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x64 "CDTM3_DTM5_CH_SR," bitfld.long 0x64 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x64 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x64 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x64 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x64 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x64 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x64 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x64 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x68 "CDTM3_DTM5_CH_CTRL3," bitfld.long 0x68 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x68 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x68 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x68 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x68 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x68 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x68 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x68 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x6C "CDTM3_DTM5_CTRL2," bitfld.long 0x6C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x6C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x6C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x6C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x6C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x6C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x6C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x6C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x6C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x6C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x6C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x6C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x6C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x6C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x6C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x6C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x6C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x6C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x6C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x6C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x70 "CDTM3_DTM5_CH0_DTV_SR," bitfld.long 0x70 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x70 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x70 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x70 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x70 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x70 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x74 "CDTM3_DTM5_CH1_DTV_SR," bitfld.long 0x74 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x74 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x74 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x74 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x74 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x74 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x78 "CDTM3_DTM5_CH2_DTV_SR," bitfld.long 0x78 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x78 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x78 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x78 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x78 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x78 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x7C "CDTM3_DTM5_CH3_DTV_SR," bitfld.long 0x7C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x7C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x7C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x7C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x7C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x7C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" group.long 0x4C00++0x4F line.long 0x0 "SPE3_CTRL_STAT," hexmask.long.byte 0x0 24.--31. 1. "FSOL,Fast Shutoff Level for TOM[i] channel 0 to 7" newline bitfld.long 0x0 23. "ETRIG_SEL,Extended trigger selection of signal SPE[i]_CTRL_STAT.TRIG_SEL" "0,1" newline bitfld.long 0x0 20.--22. "NIP,New input pattern that was detected." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "PDIR,Previous rotation direction." "0,1" newline bitfld.long 0x0 16.--18. "PIP,Previous input pattern that was detected by a regular input pattern change." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "ADIR,Rotation direction. Will be reflected in the signal SPE(i)_DIR." "0,1" newline bitfld.long 0x0 12.--14. "AIP,Input pattern that was detected by a regular input pattern change." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "SPE_PAT_PTR,Pattern selector for TOM output signals." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "FSOM,Fast Shutoff Mode" "0,1" newline bitfld.long 0x0 6. "TIM_SEL,Select TIM input signal" "0,1" newline bitfld.long 0x0 4.--5. "TRIG_SEL,Select trigger input signal." "0,1,2,3" newline bitfld.long 0x0 3. "SIE2,SPE Input enable for TIM_CHx(48)." "0,1" newline bitfld.long 0x0 2. "SIE1,SPE Input enable for TIM_CHx(48)." "0,1" newline bitfld.long 0x0 1. "SIE0,SPE Input enable for TIM_CHx(48)." "0,1" newline bitfld.long 0x0 0. "EN,SPE Submodule enable." "0,1" line.long 0x4 "SPE3_PAT," bitfld.long 0x4 29.--31. "IP7_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "IP7_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 25.--27. "IP6_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 24. "IP6_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 21.--23. "IP5_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "IP5_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 17.--19. "IP4_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "IP4_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 13.--15. "IP3_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12. "IP3_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 9.--11. "IP2_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "IP2_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 5.--7. "IP1_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4. "IP1_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 1.--3. "IP0_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "IP0_VAL,Input pattern t is a valid pattern." "0,1" line.long 0x8 "SPE3_OUT_PAT0," bitfld.long 0x8 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0xC "SPE3_OUT_PAT1," bitfld.long 0xC 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x10 "SPE3_OUT_PAT2," bitfld.long 0x10 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x14 "SPE3_OUT_PAT3," bitfld.long 0x14 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x18 "SPE3_OUT_PAT4," bitfld.long 0x18 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x1C "SPE3_OUT_PAT5," bitfld.long 0x1C 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x20 "SPE3_OUT_PAT6," bitfld.long 0x20 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x24 "SPE3_OUT_PAT7," bitfld.long 0x24 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x28 "SPE3_OUT_CTRL," bitfld.long 0x28 14.--15. "SPE_OUT_CTRL7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 12.--13. "SPE_OUT_CTRL6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 10.--11. "SPE_OUT_CTRL5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 8.--9. "SPE_OUT_CTRL4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 6.--7. "SPE_OUT_CTRL3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 4.--5. "SPE_OUT_CTRL2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 2.--3. "SPE_OUT_CTRL1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 0.--1. "SPE_OUT_CTRL0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x2C "SPE3_IRQ_NOTIFY," bitfld.long 0x2C 4. "SPE_RCMP,SPE revolution counter match event." "0,1" newline bitfld.long 0x2C 3. "SPE_BIS,Bouncing input signal detected." "0,1" newline bitfld.long 0x2C 2. "SPE_PERR,Wrong or invalid pattern detected at input." "0,1" newline bitfld.long 0x2C 1. "SPE_DCHG,SPE_DIR bit changed on behalf of new input pattern." "0,1" newline bitfld.long 0x2C 0. "SPE_NIPD,New input pattern interrupt occurred." "0,1" line.long 0x30 "SPE3_IRQ_EN," bitfld.long 0x30 4. "SPE_RCMP_IRQ_EN,SPE_RCMP_IRQ interrupt enable." "0,1" newline bitfld.long 0x30 3. "SPE_BIS_IRQ_EN,SPE_BIS_IRQ interrupt enable." "0,1" newline bitfld.long 0x30 2. "SPE_PERR_IRQ_EN,SPE_PERR_IRQ interrupt enable." "0,1" newline bitfld.long 0x30 1. "SPE_DCHG_IRQ_EN,SPE_DCHG_IRQ interrupt enable." "0,1" newline bitfld.long 0x30 0. "SPE_NIPD_IRQ_EN,SPE_NIPD_IRQ interrupt enable." "0,1" line.long 0x34 "SPE3_IRQ_FORCINT," bitfld.long 0x34 4. "TRG_SPE_RCMP,Force interrupt of SPE_RCMP." "0,1" newline bitfld.long 0x34 3. "TRG_SPE_BIS,Force interrupt of SPE_BIS." "0,1" newline bitfld.long 0x34 2. "TRG_SPE_PERR,Force interrupt of SPE_PERR." "0,1" newline bitfld.long 0x34 1. "TRG_SPE_DCHG,Force interrupt of SPE_DCHG." "0,1" newline bitfld.long 0x34 0. "TRG_SPE_NIPD,Force interrupt of SPE_NIPD." "0,1" line.long 0x38 "SPE3_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x3C "SPE3_EIRQ_EN," bitfld.long 0x3C 4. "SPE_RCMP_EIRQ_EN,SPE_RCMP_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x3C 3. "SPE_BIS_EIRQ_EN,SPE_BIS_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x3C 2. "SPE_PERR_EIRQ_EN,SPE_PERR_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x3C 1. "SPE_DCHG_EIRQ_EN,SPE_DCHG_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x3C 0. "SPE_NIPD_EIRQ_EN,SPE_NIPD_EIRQ interrupt enable." "0,1" line.long 0x40 "SPE3_REV_CNT," hexmask.long.tbyte 0x40 0.--23. 1. "REV_CNT,Input signal revolution counter" line.long 0x44 "SPE3_REV_CMP," hexmask.long.tbyte 0x44 0.--23. 1. "REV_CMP,Input signal revolution counter compare value" line.long 0x48 "SPE3_CTRL_STAT2," bitfld.long 0x48 8.--10. "SPE_PAT_PTR_BWD,Pattern selector for TOM output signals in case of SPE[i]_CMD.SPE_CTRL_CMD = 0b01 (e.g. backward direction)." "0,1,2,3,4,5,6,7" line.long 0x4C "SPE3_CMD," bitfld.long 0x4C 16. "SPE_UPD_TRIG,SPE updater trigger" "0,1" newline bitfld.long 0x4C 0.--1. "SPE_CTRL_CMD,SPE control command" "0,1,2,3" group.long 0x5000++0xB line.long 0x0 "AXIM3_FREE," bitfld.long 0x0 3. "FREE3,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 2. "FREE2,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 1. "FREE1,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 0. "FREE0,This bit represents the allocation status of the slot [t]" "0,1" line.long 0x4 "AXIM3_REQUEST," hexmask.long.byte 0x4 24.--31. 1. "REQID,This bit field shows the new allocated slot as binary encoded index. If no slot could be allocated this bit field is read as all 1 (0xff)." newline bitfld.long 0x4 3. "REQ1HOT3,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 2. "REQ1HOT2,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 1. "REQ1HOT1,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 0. "REQ1HOT0,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" line.long 0x8 "AXIM3_RELEASE," bitfld.long 0x8 3. "RELREQ3,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 2. "RELREQ2,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 1. "RELREQ1,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 0. "RELREQ0,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" group.long 0x5020++0x3 line.long 0x0 "AXIM3_SLOT0_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5028++0x3 line.long 0x0 "AXIM3_SLOT0_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5030++0xB line.long 0x0 "AXIM3_SLOT0_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM3_SLOT0_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM3_SLOT0_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5040++0x3 line.long 0x0 "AXIM3_SLOT1_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5048++0x3 line.long 0x0 "AXIM3_SLOT1_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5050++0xB line.long 0x0 "AXIM3_SLOT1_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM3_SLOT1_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM3_SLOT1_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5060++0x3 line.long 0x0 "AXIM3_SLOT2_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5068++0x3 line.long 0x0 "AXIM3_SLOT2_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5070++0xB line.long 0x0 "AXIM3_SLOT2_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM3_SLOT2_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM3_SLOT2_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5080++0x3 line.long 0x0 "AXIM3_SLOT3_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5088++0x3 line.long 0x0 "AXIM3_SLOT3_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5090++0xB line.long 0x0 "AXIM3_SLOT3_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM3_SLOT3_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM3_SLOT3_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" repeat 16384. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10000)++0x3 line.long 0x0 "MCS3_MEM[$1]," hexmask.long 0x0 0.--31. 1. "DATA,MCS memory location." repeat.end tree.end tree "GTM_CLS4" base ad:0x74080000 group.long 0x800++0x3F line.long 0x0 "TIM4_CH0_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM4_CH0_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM4_CH0_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM4_CH0_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM4_CH0_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM4_CH0_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM4_CH0_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM4_CH0_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM4_CH0_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM4_CH0_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM4_CH0_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM4_CH0_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM4_CH0_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM4_CH0_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM4_CH0_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM4_CH0_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x880++0x3F line.long 0x0 "TIM4_CH1_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM4_CH1_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM4_CH1_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM4_CH1_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM4_CH1_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM4_CH1_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM4_CH1_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM4_CH1_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM4_CH1_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM4_CH1_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM4_CH1_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM4_CH1_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM4_CH1_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM4_CH1_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM4_CH1_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM4_CH1_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x900++0x3F line.long 0x0 "TIM4_CH2_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM4_CH2_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM4_CH2_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM4_CH2_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM4_CH2_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM4_CH2_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM4_CH2_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM4_CH2_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM4_CH2_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM4_CH2_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM4_CH2_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM4_CH2_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM4_CH2_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM4_CH2_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM4_CH2_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM4_CH2_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x980++0x3F line.long 0x0 "TIM4_CH3_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM4_CH3_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM4_CH3_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM4_CH3_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM4_CH3_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM4_CH3_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM4_CH3_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM4_CH3_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM4_CH3_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM4_CH3_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM4_CH3_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM4_CH3_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM4_CH3_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM4_CH3_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM4_CH3_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM4_CH3_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xA00++0x3F line.long 0x0 "TIM4_CH4_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM4_CH4_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM4_CH4_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM4_CH4_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM4_CH4_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM4_CH4_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM4_CH4_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM4_CH4_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM4_CH4_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM4_CH4_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM4_CH4_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM4_CH4_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM4_CH4_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM4_CH4_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM4_CH4_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM4_CH4_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xA80++0x3F line.long 0x0 "TIM4_CH5_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM4_CH5_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM4_CH5_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM4_CH5_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM4_CH5_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM4_CH5_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM4_CH5_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM4_CH5_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM4_CH5_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM4_CH5_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM4_CH5_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM4_CH5_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM4_CH5_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM4_CH5_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM4_CH5_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM4_CH5_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xB00++0x3F line.long 0x0 "TIM4_CH6_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM4_CH6_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM4_CH6_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM4_CH6_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM4_CH6_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM4_CH6_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM4_CH6_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM4_CH6_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM4_CH6_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM4_CH6_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM4_CH6_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM4_CH6_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM4_CH6_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM4_CH6_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM4_CH6_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM4_CH6_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xB80++0x3F line.long 0x0 "TIM4_CH7_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM4_CH7_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM4_CH7_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM4_CH7_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM4_CH7_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM4_CH7_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM4_CH7_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM4_CH7_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM4_CH7_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM4_CH7_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM4_CH7_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM4_CH7_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM4_CH7_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM4_CH7_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM4_CH7_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM4_CH7_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xC00++0xB line.long 0x0 "TIM4_INP_VAL," bitfld.long 0x0 23. "TIM_IN7,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 22. "TIM_IN6,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 21. "TIM_IN5,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 20. "TIM_IN4,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 19. "TIM_IN3,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 18. "TIM_IN2,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 17. "TIM_IN1,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 16. "TIM_IN0,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 15. "F_IN7,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 14. "F_IN6,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 13. "F_IN5,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 12. "F_IN4,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 11. "F_IN3,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 10. "F_IN2,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 9. "F_IN1,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 8. "F_IN0,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 7. "F_OUT7,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 6. "F_OUT6,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 5. "F_OUT5,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 4. "F_OUT4,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 3. "F_OUT3,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 2. "F_OUT2,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 1. "F_OUT1,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 0. "F_OUT0,Signal channel x after TIM FLT unit" "0,1" line.long 0x4 "TIM4_IN_SRC," bitfld.long 0x4 30.--31. "MODE_7,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 28.--29. "VAL_7,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 26.--27. "MODE_6,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 24.--25. "VAL_6,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 22.--23. "MODE_5,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 20.--21. "VAL_5,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 18.--19. "MODE_4,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 16.--17. "VAL_4,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 14.--15. "MODE_3,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 12.--13. "VAL_3,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 10.--11. "MODE_2,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 8.--9. "VAL_2,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 6.--7. "MODE_1,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 4.--5. "VAL_1,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 2.--3. "MODE_0,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 0.--1. "VAL_0,Value to be fed to channel [x]" "0,1,2,3" line.long 0x8 "TIM4_RST," bitfld.long 0x8 7. "RST_CH7,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 6. "RST_CH6,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 5. "RST_CH5,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 4. "RST_CH4,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 3. "RST_CH3,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 2. "RST_CH2,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 1. "RST_CH1,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 0. "RST_CH0,Software reset of channel [x]" "0,1" group.long 0x1000++0x2B line.long 0x0 "TOM4_CH0_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM4_CH0_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM4_CH0_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM4_CH0_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM4_CH0_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM4_CH0_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM4_CH0_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM4_CH0_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM4_CH0_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM4_CH0_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM4_CH0_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1030++0x3 line.long 0x0 "TOM4_CH0_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1040++0x2B line.long 0x0 "TOM4_CH1_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM4_CH1_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM4_CH1_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM4_CH1_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM4_CH1_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM4_CH1_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM4_CH1_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM4_CH1_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM4_CH1_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM4_CH1_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM4_CH1_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1070++0x3 line.long 0x0 "TOM4_CH1_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1080++0x2B line.long 0x0 "TOM4_CH2_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM4_CH2_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM4_CH2_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM4_CH2_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM4_CH2_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM4_CH2_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM4_CH2_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM4_CH2_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM4_CH2_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM4_CH2_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM4_CH2_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x10B0++0x3 line.long 0x0 "TOM4_CH2_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x10C0++0x2B line.long 0x0 "TOM4_CH3_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM4_CH3_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM4_CH3_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM4_CH3_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM4_CH3_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM4_CH3_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM4_CH3_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM4_CH3_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM4_CH3_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM4_CH3_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM4_CH3_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x10F0++0x3 line.long 0x0 "TOM4_CH3_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1100++0x2B line.long 0x0 "TOM4_CH4_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM4_CH4_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM4_CH4_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM4_CH4_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM4_CH4_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM4_CH4_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM4_CH4_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM4_CH4_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM4_CH4_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM4_CH4_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM4_CH4_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1130++0x3 line.long 0x0 "TOM4_CH4_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1140++0x2B line.long 0x0 "TOM4_CH5_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM4_CH5_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM4_CH5_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM4_CH5_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM4_CH5_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM4_CH5_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM4_CH5_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM4_CH5_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM4_CH5_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM4_CH5_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM4_CH5_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1170++0x3 line.long 0x0 "TOM4_CH5_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1180++0x2B line.long 0x0 "TOM4_CH6_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM4_CH6_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM4_CH6_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM4_CH6_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM4_CH6_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM4_CH6_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM4_CH6_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM4_CH6_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM4_CH6_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM4_CH6_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM4_CH6_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x11B0++0x3 line.long 0x0 "TOM4_CH6_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x11C0++0x2B line.long 0x0 "TOM4_CH7_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM4_CH7_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM4_CH7_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM4_CH7_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM4_CH7_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM4_CH7_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM4_CH7_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM4_CH7_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM4_CH7_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM4_CH7_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM4_CH7_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x11F0++0x3 line.long 0x0 "TOM4_CH7_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1200++0x2B line.long 0x0 "TOM4_CH8_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM4_CH8_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM4_CH8_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM4_CH8_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM4_CH8_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM4_CH8_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM4_CH8_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM4_CH8_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM4_CH8_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM4_CH8_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM4_CH8_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1230++0x3 line.long 0x0 "TOM4_CH8_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1240++0x2B line.long 0x0 "TOM4_CH9_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM4_CH9_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM4_CH9_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM4_CH9_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM4_CH9_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM4_CH9_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM4_CH9_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM4_CH9_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM4_CH9_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM4_CH9_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM4_CH9_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1270++0x3 line.long 0x0 "TOM4_CH9_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1280++0x2B line.long 0x0 "TOM4_CH10_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM4_CH10_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM4_CH10_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM4_CH10_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM4_CH10_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM4_CH10_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM4_CH10_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM4_CH10_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM4_CH10_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM4_CH10_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM4_CH10_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x12B0++0x3 line.long 0x0 "TOM4_CH10_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x12C0++0x2B line.long 0x0 "TOM4_CH11_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM4_CH11_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM4_CH11_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM4_CH11_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM4_CH11_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM4_CH11_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM4_CH11_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM4_CH11_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM4_CH11_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM4_CH11_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM4_CH11_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x12F0++0x3 line.long 0x0 "TOM4_CH11_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1300++0x2B line.long 0x0 "TOM4_CH12_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM4_CH12_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM4_CH12_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM4_CH12_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM4_CH12_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM4_CH12_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM4_CH12_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM4_CH12_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM4_CH12_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM4_CH12_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM4_CH12_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1330++0x3 line.long 0x0 "TOM4_CH12_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1340++0x2B line.long 0x0 "TOM4_CH13_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM4_CH13_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM4_CH13_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM4_CH13_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM4_CH13_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM4_CH13_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM4_CH13_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM4_CH13_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM4_CH13_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM4_CH13_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM4_CH13_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1370++0x3 line.long 0x0 "TOM4_CH13_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1380++0x2B line.long 0x0 "TOM4_CH14_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM4_CH14_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM4_CH14_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM4_CH14_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM4_CH14_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM4_CH14_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM4_CH14_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM4_CH14_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM4_CH14_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM4_CH14_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM4_CH14_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x13B0++0x3 line.long 0x0 "TOM4_CH14_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x13C0++0x2B line.long 0x0 "TOM4_CH15_CTRL," bitfld.long 0x0 31. "FREEZE,TOM Freeze Mode enable" "0,1" newline bitfld.long 0x0 29. "GCM,Gated Counter Mode enable" "0,1" newline bitfld.long 0x0 28. "SPEM,SPE output mode enable for channel." "0,1" newline bitfld.long 0x0 27. "BITREV,Bit-reversing of output of counter TOM[i]_CH[x]_CN0." "0,1" newline bitfld.long 0x0 26. "OSM,One-shot mode. In this mode the counter TOM[i]_CH[x]_CN0 counts for only one period. The length of period is defined by TOM[i]_CH[x]_CM0. A write access to the register TOM[i]_CH[x]_CN0 triggers the start of counting." "0,1" newline bitfld.long 0x0 25. "SPE_TRIG,SPE trigger to reset TOM[i]_CH[x]_CN0" "0,1" newline bitfld.long 0x0 24. "TRIGOUT,Trigger output selection (output signal TRIGOUT[x]) of module TOM_CH[x]" "0,1" newline bitfld.long 0x0 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIGOUT[x]" "0,1" newline bitfld.long 0x0 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x0 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x0 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x0 18.--19. "UDMODE,Up-down counter mode" "0,1,2,3" newline bitfld.long 0x0 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC,Clock source select for channel" newline bitfld.long 0x0 11. "SL,Signal level for duty cycle" "0,1" newline bitfld.long 0x0 7. "SR0_TRIG,TOM[i]_CH[x]_SR0 is used to generate a trigger on output TOM[i]_CH[x]_OUT_T if equal to TOM[i]_CH[x]_CN0." "0,1" line.long 0x4 "TOM4_CH15_SR0," hexmask.long.word 0x4 0.--15. 1. "SR0,TOM channel x shadow register TOM[i]_CH[x]_SR0 for update of compare register TOM[i]_CH[x]_CM0" line.long 0x8 "TOM4_CH15_SR1," hexmask.long.word 0x8 0.--15. 1. "SR1,TOM channel x shadow register TOM[i]_CH[x]_SR1 for update of compare register TOM[i]_CH[x]_CM1" line.long 0xC "TOM4_CH15_CM0," hexmask.long.word 0xC 0.--15. 1. "CM0,TOM CCU0 compare register" line.long 0x10 "TOM4_CH15_CM1," hexmask.long.word 0x10 0.--15. 1. "CM1,TOM CCU1 compare register" line.long 0x14 "TOM4_CH15_CN0," hexmask.long.word 0x14 0.--15. 1. "CN0,TOM CCU0 counter" line.long 0x18 "TOM4_CH15_STAT," bitfld.long 0x18 29. "OSM_RTF,Oneshot mode retrigger failed flag" "0,1" newline bitfld.long 0x18 0. "OL,Output level of output TOM_OUT(x)" "0,1" line.long 0x1C "TOM4_CH15_IRQ_NOTIFY," bitfld.long 0x1C 1. "CCU1TC,CCU1 Trigger condition interrupt for channel x" "0,1" newline bitfld.long 0x1C 0. "CCU0TC,CCU0 Trigger condition interrupt for channel x" "0,1" line.long 0x20 "TOM4_CH15_IRQ_EN," bitfld.long 0x20 1. "CCU1TC_IRQ_EN,TOM_CCU1TC_IRQ interrupt enable" "0,1" newline bitfld.long 0x20 0. "CCU0TC_IRQ_EN,TOM_CCU0TC_IRQ interrupt enable" "0,1" line.long 0x24 "TOM4_CH15_IRQ_FORCINT," bitfld.long 0x24 1. "TRG_CCU1TC0,Trigger TOM_CCU1TC0_IRQ interrupt by software" "0,1" newline bitfld.long 0x24 0. "TRG_CCU0TC0,Trigger TOM_CCU0TC0_IRQ interrupt by software" "0,1" line.long 0x28 "TOM4_CH15_IRQ_MODE," bitfld.long 0x28 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x13F0++0x3 line.long 0x0 "TOM4_CH15_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for TOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for TOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1430++0xF line.long 0x0 "TOM4_TGC0_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 28.--29. "UPEN_CTRL6,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 26.--27. "UPEN_CTRL5,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 24.--25. "UPEN_CTRL4,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 22.--23. "UPEN_CTRL3,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 20.--21. "UPEN_CTRL2,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 16.--17. "UPEN_CTRL0,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 15. "RST_CH7,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 14. "RST_CH6,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 13. "RST_CH5,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 12. "RST_CH4,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 10. "RST_CH2,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 9. "RST_CH1,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 8. "RST_CH0,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see TGC0 TGC1) to update the register TOM[i]_TGC[g]_ENDIS_STAT and TOM[i]_TGC[g]_OUTEN_STAT" "0,1" line.long 0x4 "TOM4_TGC0_ACT_TB," bitfld.long 0x4 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" newline bitfld.long 0x4 24. "TB_TRIG,Set trigger request" "0,1" newline hexmask.long.tbyte 0x4 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[y] y=0..2. If selected TBU_TS[y] value is in the interval [TOM[i]_TGC[g]_ACT_TB.ACT_TB-007FFFFFh TOM[i]_TGC[g]_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x8 "TOM4_TGC0_FUPD_CTRL," bitfld.long 0x8 30.--31. "RSTCN0_CH7,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 28.--29. "RSTCN0_CH6,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 26.--27. "RSTCN0_CH5,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 24.--25. "RSTCN0_CH4,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 22.--23. "RSTCN0_CH3,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 20.--21. "RSTCN0_CH2,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 18.--19. "RSTCN0_CH1,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 16.--17. "RSTCN0_CH0,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 14.--15. "FUPD_CTRL7,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 12.--13. "FUPD_CTRL6,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 10.--11. "FUPD_CTRL5,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 8.--9. "FUPD_CTRL4,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 6.--7. "FUPD_CTRL3,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 4.--5. "FUPD_CTRL2,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 2.--3. "FUPD_CTRL1,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 0.--1. "FUPD_CTRL0,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" line.long 0xC "TOM4_TGC0_INT_TRIG," bitfld.long 0xC 14.--15. "INT_TRIG7,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 12.--13. "INT_TRIG6,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 10.--11. "INT_TRIG5,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "INT_TRIG4,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 6.--7. "INT_TRIG3,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 4.--5. "INT_TRIG2,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "INT_TRIG1,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 0.--1. "INT_TRIG0,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" group.long 0x1470++0xF line.long 0x0 "TOM4_TGC0_ENDIS_CTRL," bitfld.long 0x0 14.--15. "ENDIS_CTRL7,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 12.--13. "ENDIS_CTRL6,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 10.--11. "ENDIS_CTRL5,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 8.--9. "ENDIS_CTRL4,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 6.--7. "ENDIS_CTRL3,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ENDIS_CTRL2,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 2.--3. "ENDIS_CTRL1,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 0.--1. "ENDIS_CTRL0,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" line.long 0x4 "TOM4_TGC0_ENDIS_STAT," bitfld.long 0x4 14.--15. "ENDIS_STAT7,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 12.--13. "ENDIS_STAT6,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 10.--11. "ENDIS_STAT5,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 8.--9. "ENDIS_STAT4,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 6.--7. "ENDIS_STAT3,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 4.--5. "ENDIS_STAT2,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_STAT1,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 0.--1. "ENDIS_STAT0,TOM channel x=c + g*8 enable/disable" "0,1,2,3" line.long 0x8 "TOM4_TGC0_OUTEN_CTRL," bitfld.long 0x8 14.--15. "OUTEN_CTRL7,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 12.--13. "OUTEN_CTRL6,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OUTEN_CTRL5,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 8.--9. "OUTEN_CTRL4,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OUTEN_CTRL3,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 4.--5. "OUTEN_CTRL2,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OUTEN_CTRL1,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 0.--1. "OUTEN_CTRL0,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" line.long 0xC "TOM4_TGC0_OUTEN_STAT," bitfld.long 0xC 14.--15. "OUTEN_STAT7,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 12.--13. "OUTEN_STAT6,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 10.--11. "OUTEN_STAT5,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "OUTEN_STAT4,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 6.--7. "OUTEN_STAT3,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 4.--5. "OUTEN_STAT2,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "OUTEN_STAT1,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 0.--1. "OUTEN_STAT0,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" group.long 0x14B0++0xF line.long 0x0 "TOM4_TGC1_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 28.--29. "UPEN_CTRL6,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 26.--27. "UPEN_CTRL5,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 24.--25. "UPEN_CTRL4,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 22.--23. "UPEN_CTRL3,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 20.--21. "UPEN_CTRL2,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 16.--17. "UPEN_CTRL0,TOM channel x=c + g*8 enable update of register TOM[i]_CH[x]_CM0 TOM[i]_CH[x]_CM1 TOM[i]_CH[x]_CTRL.SL and TOM[i]_CH[x]_CTRL.CLK_SRC from TOM[i]_CH[x]_SR0 TOM[i]_CH[x]_SR1 TOM[i]_CH[x]_CTRL_SL.SL_SR and TOM[i]_CH[x]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 15. "RST_CH7,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 14. "RST_CH6,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 13. "RST_CH5,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 12. "RST_CH4,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 10. "RST_CH2,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 9. "RST_CH1,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 8. "RST_CH0,Software reset of channel x = c + g*8" "0,1" newline bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see TGC0 TGC1) to update the register TOM[i]_TGC[g]_ENDIS_STAT and TOM[i]_TGC[g]_OUTEN_STAT" "0,1" line.long 0x4 "TOM4_TGC1_ACT_TB," bitfld.long 0x4 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" newline bitfld.long 0x4 24. "TB_TRIG,Set trigger request" "0,1" newline hexmask.long.tbyte 0x4 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[y] y=0..2. If selected TBU_TS[y] value is in the interval [TOM[i]_TGC[g]_ACT_TB.ACT_TB-007FFFFFh TOM[i]_TGC[g]_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x8 "TOM4_TGC1_FUPD_CTRL," bitfld.long 0x8 30.--31. "RSTCN0_CH7,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 28.--29. "RSTCN0_CH6,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 26.--27. "RSTCN0_CH5,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 24.--25. "RSTCN0_CH4,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 22.--23. "RSTCN0_CH3,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 20.--21. "RSTCN0_CH2,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 18.--19. "RSTCN0_CH1,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 16.--17. "RSTCN0_CH0,Reset TOM[i]_CH[x]_CN0 of channel x=c + g*8 on force update event" "0,1,2,3" newline bitfld.long 0x8 14.--15. "FUPD_CTRL7,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 12.--13. "FUPD_CTRL6,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 10.--11. "FUPD_CTRL5,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 8.--9. "FUPD_CTRL4,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 6.--7. "FUPD_CTRL3,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 4.--5. "FUPD_CTRL2,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 2.--3. "FUPD_CTRL1,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" newline bitfld.long 0x8 0.--1. "FUPD_CTRL0,Force update of TOM channel x=c + g*8 operation register" "0,1,2,3" line.long 0xC "TOM4_TGC1_INT_TRIG," bitfld.long 0xC 14.--15. "INT_TRIG7,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 12.--13. "INT_TRIG6,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 10.--11. "INT_TRIG5,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "INT_TRIG4,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 6.--7. "INT_TRIG3,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 4.--5. "INT_TRIG2,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "INT_TRIG1,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 0.--1. "INT_TRIG0,Select input signal TRIG_[x] as a trigger source x=c + g*8" "0,1,2,3" group.long 0x14F0++0xF line.long 0x0 "TOM4_TGC1_ENDIS_CTRL," bitfld.long 0x0 14.--15. "ENDIS_CTRL7,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 12.--13. "ENDIS_CTRL6,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 10.--11. "ENDIS_CTRL5,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 8.--9. "ENDIS_CTRL4,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 6.--7. "ENDIS_CTRL3,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ENDIS_CTRL2,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 2.--3. "ENDIS_CTRL1,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" newline bitfld.long 0x0 0.--1. "ENDIS_CTRL0,TOM channel x=c + g*8 enable/disable update value." "0,1,2,3" line.long 0x4 "TOM4_TGC1_ENDIS_STAT," bitfld.long 0x4 14.--15. "ENDIS_STAT7,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 12.--13. "ENDIS_STAT6,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 10.--11. "ENDIS_STAT5,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 8.--9. "ENDIS_STAT4,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 6.--7. "ENDIS_STAT3,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 4.--5. "ENDIS_STAT2,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_STAT1,TOM channel x=c + g*8 enable/disable" "0,1,2,3" newline bitfld.long 0x4 0.--1. "ENDIS_STAT0,TOM channel x=c + g*8 enable/disable" "0,1,2,3" line.long 0x8 "TOM4_TGC1_OUTEN_CTRL," bitfld.long 0x8 14.--15. "OUTEN_CTRL7,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 12.--13. "OUTEN_CTRL6,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OUTEN_CTRL5,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 8.--9. "OUTEN_CTRL4,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OUTEN_CTRL3,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 4.--5. "OUTEN_CTRL2,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OUTEN_CTRL1,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" newline bitfld.long 0x8 0.--1. "OUTEN_CTRL0,Output TOM[i]_CH[x]_OUT enable/disable update value x=c + g*8" "0,1,2,3" line.long 0xC "TOM4_TGC1_OUTEN_STAT," bitfld.long 0xC 14.--15. "OUTEN_STAT7,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 12.--13. "OUTEN_STAT6,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 10.--11. "OUTEN_STAT5,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 8.--9. "OUTEN_STAT4,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 6.--7. "OUTEN_STAT3,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 4.--5. "OUTEN_STAT2,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 2.--3. "OUTEN_STAT1,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" newline bitfld.long 0xC 0.--1. "OUTEN_STAT0,Control/status of output TOM[i]_CH[x]_OUT x=c + g*8" "0,1,2,3" group.long 0x1800++0x2F line.long 0x0 "ATOM4_CH0_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM4_CH0_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM4_CH0_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM4_CH0_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM4_CH0_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM4_CH0_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM4_CH0_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM4_CH0_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM4_CH0_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM4_CH0_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM4_CH0_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM4_CH0_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1834++0x3 line.long 0x0 "ATOM4_CH0_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1880++0x2F line.long 0x0 "ATOM4_CH1_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM4_CH1_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM4_CH1_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM4_CH1_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM4_CH1_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM4_CH1_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM4_CH1_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM4_CH1_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM4_CH1_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM4_CH1_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM4_CH1_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM4_CH1_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x18B4++0x3 line.long 0x0 "ATOM4_CH1_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1900++0x2F line.long 0x0 "ATOM4_CH2_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM4_CH2_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM4_CH2_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM4_CH2_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM4_CH2_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM4_CH2_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM4_CH2_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM4_CH2_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM4_CH2_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM4_CH2_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM4_CH2_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM4_CH2_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1934++0x3 line.long 0x0 "ATOM4_CH2_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1980++0x2F line.long 0x0 "ATOM4_CH3_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM4_CH3_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM4_CH3_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM4_CH3_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM4_CH3_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM4_CH3_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM4_CH3_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM4_CH3_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM4_CH3_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM4_CH3_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM4_CH3_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM4_CH3_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x19B4++0x3 line.long 0x0 "ATOM4_CH3_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A00++0x2F line.long 0x0 "ATOM4_CH4_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM4_CH4_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM4_CH4_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM4_CH4_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM4_CH4_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM4_CH4_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM4_CH4_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM4_CH4_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM4_CH4_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM4_CH4_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM4_CH4_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM4_CH4_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1A34++0x3 line.long 0x0 "ATOM4_CH4_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A80++0x2F line.long 0x0 "ATOM4_CH5_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM4_CH5_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM4_CH5_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM4_CH5_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM4_CH5_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM4_CH5_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM4_CH5_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM4_CH5_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM4_CH5_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM4_CH5_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM4_CH5_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM4_CH5_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1AB4++0x3 line.long 0x0 "ATOM4_CH5_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B00++0x2F line.long 0x0 "ATOM4_CH6_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM4_CH6_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM4_CH6_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM4_CH6_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM4_CH6_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM4_CH6_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM4_CH6_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM4_CH6_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM4_CH6_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM4_CH6_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM4_CH6_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM4_CH6_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1B34++0x3 line.long 0x0 "ATOM4_CH6_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B80++0x2F line.long 0x0 "ATOM4_CH7_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM4_CH7_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM4_CH7_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM4_CH7_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM4_CH7_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM4_CH7_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM4_CH7_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM4_CH7_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM4_CH7_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM4_CH7_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM4_CH7_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM4_CH7_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1BB4++0x3 line.long 0x0 "ATOM4_CH7_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1C40++0x1F line.long 0x0 "ATOM4_AGC_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 28.--29. "UPEN_CTRL6,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 26.--27. "UPEN_CTRL5,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 24.--25. "UPEN_CTRL4,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 22.--23. "UPEN_CTRL3,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 20.--21. "UPEN_CTRL2,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 16.--17. "UPEN_CTRL0,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 15. "RST_CH7,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 14. "RST_CH6,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 13. "RST_CH5,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 12. "RST_CH4,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 10. "RST_CH2,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 9. "RST_CH1,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 8. "RST_CH0,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see AGC) to update the register ATOM[i]_AGC_ENDIS_STAT and ATOM[i]_AGC_OUTEN_STAT" "0,1" line.long 0x4 "ATOM4_AGC_ENDIS_CTRL," bitfld.long 0x4 14.--15. "ENDIS_CTRL7,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 12.--13. "ENDIS_CTRL6,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 10.--11. "ENDIS_CTRL5,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 8.--9. "ENDIS_CTRL4,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 6.--7. "ENDIS_CTRL3,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 4.--5. "ENDIS_CTRL2,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_CTRL1,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 0.--1. "ENDIS_CTRL0,ATOM channel [k] enable/disable update value." "0,1,2,3" line.long 0x8 "ATOM4_AGC_ENDIS_STAT," bitfld.long 0x8 14.--15. "ENDIS_STAT7,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 12.--13. "ENDIS_STAT6,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 10.--11. "ENDIS_STAT5,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 8.--9. "ENDIS_STAT4,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 6.--7. "ENDIS_STAT3,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 4.--5. "ENDIS_STAT2,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 2.--3. "ENDIS_STAT1,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 0.--1. "ENDIS_STAT0,ATOM channel [k] enable/disable" "0,1,2,3" line.long 0xC "ATOM4_AGC_ACT_TB," bitfld.long 0xC 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" newline bitfld.long 0xC 24. "TB_TRIG,Set trigger request" "0,1" newline hexmask.long.tbyte 0xC 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[x] x=0..2. If selected TBU_TS[x] value is in the interval [ATOM[i]_AGC_ACT_TB.ACT_TB-007FFFFFh ATOM[i]_AGC_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x10 "ATOM4_AGC_OUTEN_CTRL," bitfld.long 0x10 14.--15. "OUTEN_CTRL7,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 12.--13. "OUTEN_CTRL6,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 10.--11. "OUTEN_CTRL5,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 8.--9. "OUTEN_CTRL4,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 6.--7. "OUTEN_CTRL3,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 4.--5. "OUTEN_CTRL2,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 2.--3. "OUTEN_CTRL1,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 0.--1. "OUTEN_CTRL0,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" line.long 0x14 "ATOM4_AGC_OUTEN_STAT," bitfld.long 0x14 14.--15. "OUTEN_STAT7,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 12.--13. "OUTEN_STAT6,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 10.--11. "OUTEN_STAT5,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 8.--9. "OUTEN_STAT4,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 6.--7. "OUTEN_STAT3,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 4.--5. "OUTEN_STAT2,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 2.--3. "OUTEN_STAT1,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 0.--1. "OUTEN_STAT0,Control/status of output ATOM_OUT [k]" "0,1,2,3" line.long 0x18 "ATOM4_AGC_FUPD_CTRL," bitfld.long 0x18 30.--31. "RSTCN0_CH7,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 28.--29. "RSTCN0_CH6,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 26.--27. "RSTCN0_CH5,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 24.--25. "RSTCN0_CH4,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 22.--23. "RSTCN0_CH3,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 20.--21. "RSTCN0_CH2,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 18.--19. "RSTCN0_CH1,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 16.--17. "RSTCN0_CH0,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 14.--15. "FUPD_CTRL7,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 12.--13. "FUPD_CTRL6,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 10.--11. "FUPD_CTRL5,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 8.--9. "FUPD_CTRL4,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 6.--7. "FUPD_CTRL3,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 4.--5. "FUPD_CTRL2,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 2.--3. "FUPD_CTRL1,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 0.--1. "FUPD_CTRL0,Force update of ATOM channel [k] operation registers" "0,1,2,3" line.long 0x1C "ATOM4_AGC_INT_TRIG," bitfld.long 0x1C 14.--15. "INT_TRIG7,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 12.--13. "INT_TRIG6,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 10.--11. "INT_TRIG5,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 8.--9. "INT_TRIG4,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 6.--7. "INT_TRIG3,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 4.--5. "INT_TRIG2,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 2.--3. "INT_TRIG1,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "INT_TRIG0,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" group.long 0x2000++0x27 line.long 0x0 "MCS4_CH0_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS4_CH0_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS4_CH0_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS4_CH0_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS4_CH0_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS4_CH0_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS4_CH0_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS4_CH0_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS4_CH0_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS4_CH0_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x203C++0x3 line.long 0x0 "MCS4_CH0_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x20E0++0x17 line.long 0x0 "MCS4_CH0_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS4_CH0_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS4_CH0_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS4_CH0_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS4_CH0_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS4_CH0_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2100++0x27 line.long 0x0 "MCS4_CH1_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS4_CH1_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS4_CH1_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS4_CH1_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS4_CH1_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS4_CH1_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS4_CH1_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS4_CH1_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS4_CH1_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS4_CH1_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x213C++0x3 line.long 0x0 "MCS4_CH1_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x21E0++0x17 line.long 0x0 "MCS4_CH1_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS4_CH1_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS4_CH1_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS4_CH1_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS4_CH1_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS4_CH1_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2200++0x27 line.long 0x0 "MCS4_CH2_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS4_CH2_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS4_CH2_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS4_CH2_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS4_CH2_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS4_CH2_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS4_CH2_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS4_CH2_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS4_CH2_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS4_CH2_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x223C++0x3 line.long 0x0 "MCS4_CH2_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x22E0++0x17 line.long 0x0 "MCS4_CH2_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS4_CH2_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS4_CH2_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS4_CH2_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS4_CH2_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS4_CH2_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2300++0x27 line.long 0x0 "MCS4_CH3_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS4_CH3_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS4_CH3_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS4_CH3_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS4_CH3_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS4_CH3_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS4_CH3_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS4_CH3_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS4_CH3_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS4_CH3_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x233C++0x3 line.long 0x0 "MCS4_CH3_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x23E0++0x17 line.long 0x0 "MCS4_CH3_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS4_CH3_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS4_CH3_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS4_CH3_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS4_CH3_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS4_CH3_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2400++0x27 line.long 0x0 "MCS4_CH4_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS4_CH4_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS4_CH4_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS4_CH4_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS4_CH4_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS4_CH4_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS4_CH4_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS4_CH4_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS4_CH4_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS4_CH4_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x243C++0x3 line.long 0x0 "MCS4_CH4_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x24E0++0x17 line.long 0x0 "MCS4_CH4_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS4_CH4_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS4_CH4_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS4_CH4_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS4_CH4_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS4_CH4_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2500++0x27 line.long 0x0 "MCS4_CH5_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS4_CH5_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS4_CH5_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS4_CH5_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS4_CH5_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS4_CH5_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS4_CH5_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS4_CH5_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS4_CH5_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS4_CH5_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x253C++0x3 line.long 0x0 "MCS4_CH5_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x25E0++0x17 line.long 0x0 "MCS4_CH5_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS4_CH5_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS4_CH5_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS4_CH5_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS4_CH5_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS4_CH5_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2600++0x27 line.long 0x0 "MCS4_CH6_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS4_CH6_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS4_CH6_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS4_CH6_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS4_CH6_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS4_CH6_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS4_CH6_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS4_CH6_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS4_CH6_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS4_CH6_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x263C++0x3 line.long 0x0 "MCS4_CH6_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x26E0++0x17 line.long 0x0 "MCS4_CH6_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS4_CH6_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS4_CH6_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS4_CH6_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS4_CH6_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS4_CH6_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2700++0x27 line.long 0x0 "MCS4_CH7_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS4_CH7_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS4_CH7_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS4_CH7_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS4_CH7_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS4_CH7_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS4_CH7_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS4_CH7_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS4_CH7_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS4_CH7_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x273C++0x3 line.long 0x0 "MCS4_CH7_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x27E0++0x17 line.long 0x0 "MCS4_CH7_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS4_CH7_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS4_CH7_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS4_CH7_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS4_CH7_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS4_CH7_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2E28++0x7 line.long 0x0 "MCS4_CTRG," bitfld.long 0x0 23. "TRG23,Trigger bit o." "0,1" newline bitfld.long 0x0 22. "TRG22,Trigger bit o." "0,1" newline bitfld.long 0x0 21. "TRG21,Trigger bit o." "0,1" newline bitfld.long 0x0 20. "TRG20,Trigger bit o." "0,1" newline bitfld.long 0x0 19. "TRG19,Trigger bit o." "0,1" newline bitfld.long 0x0 18. "TRG18,Trigger bit o." "0,1" newline bitfld.long 0x0 17. "TRG17,Trigger bit o." "0,1" newline bitfld.long 0x0 16. "TRG16,Trigger bit o." "0,1" newline bitfld.long 0x0 15. "TRG15,Trigger bit n." "0,1" newline bitfld.long 0x0 14. "TRG14,Trigger bit n." "0,1" newline bitfld.long 0x0 13. "TRG13,Trigger bit n." "0,1" newline bitfld.long 0x0 12. "TRG12,Trigger bit n." "0,1" newline bitfld.long 0x0 11. "TRG11,Trigger bit n." "0,1" newline bitfld.long 0x0 10. "TRG10,Trigger bit n." "0,1" newline bitfld.long 0x0 9. "TRG9,Trigger bit n." "0,1" newline bitfld.long 0x0 8. "TRG8,Trigger bit n." "0,1" newline bitfld.long 0x0 7. "TRG7,Trigger bit m." "0,1" newline bitfld.long 0x0 6. "TRG6,Trigger bit m." "0,1" newline bitfld.long 0x0 5. "TRG5,Trigger bit m." "0,1" newline bitfld.long 0x0 4. "TRG4,Trigger bit m." "0,1" newline bitfld.long 0x0 3. "TRG3,Trigger bit m." "0,1" newline bitfld.long 0x0 2. "TRG2,Trigger bit m." "0,1" newline bitfld.long 0x0 1. "TRG1,Trigger bit m." "0,1" newline bitfld.long 0x0 0. "TRG0,Trigger bit m." "0,1" line.long 0x4 "MCS4_STRG," bitfld.long 0x4 23. "TRG23,Trigger bit k." "0,1" newline bitfld.long 0x4 22. "TRG22,Trigger bit k." "0,1" newline bitfld.long 0x4 21. "TRG21,Trigger bit k." "0,1" newline bitfld.long 0x4 20. "TRG20,Trigger bit k." "0,1" newline bitfld.long 0x4 19. "TRG19,Trigger bit k." "0,1" newline bitfld.long 0x4 18. "TRG18,Trigger bit k." "0,1" newline bitfld.long 0x4 17. "TRG17,Trigger bit k." "0,1" newline bitfld.long 0x4 16. "TRG16,Trigger bit k." "0,1" newline bitfld.long 0x4 15. "TRG15,Trigger bit k." "0,1" newline bitfld.long 0x4 14. "TRG14,Trigger bit k." "0,1" newline bitfld.long 0x4 13. "TRG13,Trigger bit k." "0,1" newline bitfld.long 0x4 12. "TRG12,Trigger bit k." "0,1" newline bitfld.long 0x4 11. "TRG11,Trigger bit k." "0,1" newline bitfld.long 0x4 10. "TRG10,Trigger bit k." "0,1" newline bitfld.long 0x4 9. "TRG9,Trigger bit k." "0,1" newline bitfld.long 0x4 8. "TRG8,Trigger bit k." "0,1" newline bitfld.long 0x4 7. "TRG7,Trigger bit k." "0,1" newline bitfld.long 0x4 6. "TRG6,Trigger bit k." "0,1" newline bitfld.long 0x4 5. "TRG5,Trigger bit k." "0,1" newline bitfld.long 0x4 4. "TRG4,Trigger bit k." "0,1" newline bitfld.long 0x4 3. "TRG3,Trigger bit k." "0,1" newline bitfld.long 0x4 2. "TRG2,Trigger bit k." "0,1" newline bitfld.long 0x4 1. "TRG1,Trigger bit k." "0,1" newline bitfld.long 0x4 0. "TRG0,Trigger bit k." "0,1" group.long 0x2F00++0x13 line.long 0x0 "MCS4_CTRL_STAT," bitfld.long 0x0 26. "HLT_AEIM_ERR,Halt on AEI bus master error." "0,1" newline bitfld.long 0x0 25. "EN_HVD,Enable Modified Harvard architecture." "0,1" newline bitfld.long 0x0 24. "EN_TIM_FOUT,Enable routing of TIM[i]_CH[x]_F_OUT signal." "0,1" newline bitfld.long 0x0 20.--22. "ERR_SRC_ID,Error source identifier." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "RAM_RST,RAM reset bit." "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "SCD_CH,Channel selection for scheduling algorithm." newline bitfld.long 0x0 0.--1. "SCD_MODE,Select MCS scheduling mode" "0,1,2,3" line.long 0x4 "MCS4_RESET," bitfld.long 0x4 7. "RST7,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 6. "RST6,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 5. "RST5,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 4. "RST4,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 3. "RST3,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 2. "RST2,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 1. "RST1,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 0. "RST0,Software reset of channel [k]" "0,1" line.long 0x8 "MCS4_CAT," bitfld.long 0x8 7. "CAT7,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 6. "CAT6,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 5. "CAT5,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 4. "CAT4,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 3. "CAT3,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 2. "CAT2,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 1. "CAT1,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 0. "CAT0,Cancel ARU transfer of channel [k]." "0,1" line.long 0xC "MCS4_CWT," bitfld.long 0xC 7. "CWT7,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 6. "CWT6,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 5. "CWT5,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 4. "CWT4,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 3. "CWT3,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 2. "CWT2,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 1. "CWT1,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 0. "CWT0,Cancel waiting instruction for channel [k]." "0,1" line.long 0x10 "MCS4_ERR," bitfld.long 0x10 7. "ERR7,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 6. "ERR6,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 5. "ERR5,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 4. "ERR4,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 3. "ERR3,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 2. "ERR2,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 1. "ERR1,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 0. "ERR0,Error State of MCS-channel [k]." "0,1" group.long 0x2F1C++0x13 line.long 0x0 "MCS4_REG_PROT," bitfld.long 0x0 14.--15. "WPROT7,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 12.--13. "WPROT6,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 10.--11. "WPROT5,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 8.--9. "WPROT4,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 6.--7. "WPROT3,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 4.--5. "WPROT2,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 2.--3. "WPROT1,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 0.--1. "WPROT0,Register Write Protection of MCS-channel k." "0,1,2,3" line.long 0x4 "MCS4_SINT_IRQ_NOTIFY," bitfld.long 0x4 7. "S_IRQ7,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 6. "S_IRQ6,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 5. "S_IRQ5,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 4. "S_IRQ4,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 3. "S_IRQ3,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 2. "S_IRQ2,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 1. "S_IRQ1,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 0. "S_IRQ0,Shared interrupt [k] notify flag." "0,1" line.long 0x8 "MCS4_SINT_IRQ_EN," bitfld.long 0x8 7. "S_IRQ7_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 6. "S_IRQ6_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 5. "S_IRQ5_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 4. "S_IRQ4_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 3. "S_IRQ3_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 2. "S_IRQ2_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 1. "S_IRQ1_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 0. "S_IRQ0_EN,Shared interrupt [k]" "0,1" line.long 0xC "MCS4_SINT_IRQ_FORCINT," bitfld.long 0xC 7. "TRG_S_IRQ7,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 6. "TRG_S_IRQ6,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 5. "TRG_S_IRQ5,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 4. "TRG_S_IRQ4,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 3. "TRG_S_IRQ3,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 2. "TRG_S_IRQ2,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 1. "TRG_S_IRQ1,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 0. "TRG_S_IRQ0,Trigger IRQ [k] in shared interrupt register" "0,1" line.long 0x10 "MCS4_SINT_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x2F40++0x1B line.long 0x0 "MCS4_HBP0_CTRL," bitfld.long 0x0 17. "NOT,Logical negation of h-th hardware break point." "0,1" newline bitfld.long 0x0 16. "AND,Logical AND conjunction of h-th hardware break point." "0,1" newline bitfld.long 0x0 12.--14. "TYPE,Define type of h-th hardware break point." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--9. "SCOPE,Define scope of h-th hardware break point." "0,1,2,3" newline bitfld.long 0x0 7. "EN_CH7,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 6. "EN_CH6,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 5. "EN_CH5,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 4. "EN_CH4,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 3. "EN_CH3,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 2. "EN_CH2,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 1. "EN_CH1,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 0. "EN_CH0,Enable h-th hardware break point for channel x." "0,1" line.long 0x4 "MCS4_HBP0_PATTERN," hexmask.long 0x4 0.--31. 1. "DATA,Define pattern or address of h-th hardware break point." line.long 0x8 "MCS4_HBP0_STATUS," bitfld.long 0x8 7. "HALT_CH7,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 6. "HALT_CH6,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 5. "HALT_CH5,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 4. "HALT_CH4,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 3. "HALT_CH3,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 2. "HALT_CH2,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 1. "HALT_CH1,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 0. "HALT_CH0,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" line.long 0xC "MCS4_HBP0_IRQ_NOTIFY," bitfld.long 0xC 0. "HBP_IRQ,Interrupt notify flag of the h-th hardware break point." "0,1" line.long 0x10 "MCS4_HBP0_IRQ_EN," bitfld.long 0x10 0. "HBP_IRQ_EN,Interrupt Enable bit of the h-th hardware break point." "0,1" line.long 0x14 "MCS4_HBP0_IRQ_FORCINT," bitfld.long 0x14 0. "TRG_HBP_IRQ,Trigger IRQ of the h-th hardware break point." "0,1" line.long 0x18 "MCS4_HBP0_IRQ_MODE," bitfld.long 0x18 0.--1. "IRQ_MODE,IRQ mode selection for all break point interrupts." "0,1,2,3" group.long 0x2F60++0x1B line.long 0x0 "MCS4_HBP1_CTRL," bitfld.long 0x0 17. "NOT,Logical negation of h-th hardware break point." "0,1" newline bitfld.long 0x0 16. "AND,Logical AND conjunction of h-th hardware break point." "0,1" newline bitfld.long 0x0 12.--14. "TYPE,Define type of h-th hardware break point." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--9. "SCOPE,Define scope of h-th hardware break point." "0,1,2,3" newline bitfld.long 0x0 7. "EN_CH7,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 6. "EN_CH6,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 5. "EN_CH5,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 4. "EN_CH4,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 3. "EN_CH3,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 2. "EN_CH2,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 1. "EN_CH1,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 0. "EN_CH0,Enable h-th hardware break point for channel x." "0,1" line.long 0x4 "MCS4_HBP1_PATTERN," hexmask.long 0x4 0.--31. 1. "DATA,Define pattern or address of h-th hardware break point." line.long 0x8 "MCS4_HBP1_STATUS," bitfld.long 0x8 7. "HALT_CH7,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 6. "HALT_CH6,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 5. "HALT_CH5,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 4. "HALT_CH4,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 3. "HALT_CH3,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 2. "HALT_CH2,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 1. "HALT_CH1,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 0. "HALT_CH0,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" line.long 0xC "MCS4_HBP1_IRQ_NOTIFY," bitfld.long 0xC 0. "HBP_IRQ,Interrupt notify flag of the h-th hardware break point." "0,1" line.long 0x10 "MCS4_HBP1_IRQ_EN," bitfld.long 0x10 0. "HBP_IRQ_EN,Interrupt Enable bit of the h-th hardware break point." "0,1" line.long 0x14 "MCS4_HBP1_IRQ_FORCINT," bitfld.long 0x14 0. "TRG_HBP_IRQ,Trigger IRQ of the h-th hardware break point." "0,1" line.long 0x18 "MCS4_HBP1_IRQ_MODE," bitfld.long 0x18 0.--1. "IRQ_MODE,IRQ mode selection for all break point interrupts." "0,1,2,3" group.long 0x3000++0x13 line.long 0x0 "TIO4_G0_CH0_CTRL," bitfld.long 0x0 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x0 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x0 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x0 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x0 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x0 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x0 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x0 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x0 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x0 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x0 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x0 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x0 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x0 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x0 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x0 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x0 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x0 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x0 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x0 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x0 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x4 "TIO4_G0_CH0_IRQ_NOTIFY," bitfld.long 0x4 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x4 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x4 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x4 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x4 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x4 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x8 "TIO4_G0_CH0_IRQ_EN," bitfld.long 0x8 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x8 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x8 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x8 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x8 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x8 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0xC "TIO4_G0_CH0_IRQ_FORCINT," bitfld.long 0xC 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0xC 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0xC 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0xC 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0xC 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0xC 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x10 "TIO4_G0_CH0_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3020++0xB line.long 0x0 "TIO4_G0_CH0_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO4_G0_CH0_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO4_G0_CH0_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3030++0x23 line.long 0x0 "TIO4_G0_CH0_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO4_G0_CH0_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO4_G0_CH0_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO4_G0_CH0_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO4_G0_CH1_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO4_G0_CH1_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO4_G0_CH1_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO4_G0_CH1_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO4_G0_CH1_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3060++0xB line.long 0x0 "TIO4_G0_CH1_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO4_G0_CH1_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO4_G0_CH1_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3070++0x23 line.long 0x0 "TIO4_G0_CH1_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO4_G0_CH1_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO4_G0_CH1_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO4_G0_CH1_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO4_G0_CH2_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO4_G0_CH2_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO4_G0_CH2_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO4_G0_CH2_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO4_G0_CH2_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x30A0++0xB line.long 0x0 "TIO4_G0_CH2_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO4_G0_CH2_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO4_G0_CH2_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x30B0++0x23 line.long 0x0 "TIO4_G0_CH2_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO4_G0_CH2_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO4_G0_CH2_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO4_G0_CH2_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO4_G0_CH3_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO4_G0_CH3_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO4_G0_CH3_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO4_G0_CH3_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO4_G0_CH3_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x30E0++0xB line.long 0x0 "TIO4_G0_CH3_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO4_G0_CH3_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO4_G0_CH3_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x30F0++0x23 line.long 0x0 "TIO4_G0_CH3_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO4_G0_CH3_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO4_G0_CH3_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO4_G0_CH3_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO4_G0_CH4_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO4_G0_CH4_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO4_G0_CH4_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO4_G0_CH4_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO4_G0_CH4_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3120++0xB line.long 0x0 "TIO4_G0_CH4_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO4_G0_CH4_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO4_G0_CH4_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3130++0x23 line.long 0x0 "TIO4_G0_CH4_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO4_G0_CH4_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO4_G0_CH4_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO4_G0_CH4_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO4_G0_CH5_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO4_G0_CH5_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO4_G0_CH5_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO4_G0_CH5_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO4_G0_CH5_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3160++0xB line.long 0x0 "TIO4_G0_CH5_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO4_G0_CH5_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO4_G0_CH5_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3170++0x23 line.long 0x0 "TIO4_G0_CH5_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO4_G0_CH5_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO4_G0_CH5_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO4_G0_CH5_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO4_G0_CH6_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO4_G0_CH6_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO4_G0_CH6_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO4_G0_CH6_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO4_G0_CH6_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x31A0++0xB line.long 0x0 "TIO4_G0_CH6_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO4_G0_CH6_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO4_G0_CH6_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x31B0++0x23 line.long 0x0 "TIO4_G0_CH6_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO4_G0_CH6_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO4_G0_CH6_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO4_G0_CH6_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO4_G0_CH7_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO4_G0_CH7_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO4_G0_CH7_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO4_G0_CH7_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO4_G0_CH7_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x31E0++0xB line.long 0x0 "TIO4_G0_CH7_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO4_G0_CH7_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO4_G0_CH7_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x31F0++0x17 line.long 0x0 "TIO4_G0_CH7_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO4_G0_CH7_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO4_G0_CH7_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO4_G0_CH7_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO4_G0_ISEL0_CTRL1," bitfld.long 0x10 27. "WRITE_EN3,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 26. "WRITE_EN2,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 25. "WRITE_EN1,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 24. "WRITE_EN0,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 19. "OUT_SEL3,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x10 18. "OUT_SEL2,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x10 17. "OUT_SEL1,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x10 16. "OUT_SEL0,select signal for ISEL_OUT[k]" "0,1" newline hexmask.long.byte 0x10 12.--15. 1. "LUT2_3,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x10 8.--11. 1. "LUT2_2,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x10 4.--7. 1. "LUT2_1,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x10 0.--3. 1. "LUT2_0,2 bit Lookup table function for channel c=q*4+k" line.long 0x14 "TIO4_G0_ISEL0_CTRL2," bitfld.long 0x14 22. "LUT3IN_SEL2,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x14 21. "LUT3IN_SEL1,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x14 20. "LUT3IN_SEL0,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x14 16.--17. "QOUT_SEL,select source for ISEL_QOUT signal in quad = q" "0,1,2,3" newline hexmask.long.byte 0x14 0.--7. 1. "LUT3,3 bit Lookup table function for quad=q; channels q*4+2 .. q*4" group.long 0x3220++0x7 line.long 0x0 "TIO4_G0_ISEL1_CTRL1," bitfld.long 0x0 27. "WRITE_EN3,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 26. "WRITE_EN2,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 25. "WRITE_EN1,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 24. "WRITE_EN0,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 19. "OUT_SEL3,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x0 18. "OUT_SEL2,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x0 17. "OUT_SEL1,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x0 16. "OUT_SEL0,select signal for ISEL_OUT[k]" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "LUT2_3,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x0 8.--11. 1. "LUT2_2,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x0 4.--7. 1. "LUT2_1,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x0 0.--3. 1. "LUT2_0,2 bit Lookup table function for channel c=q*4+k" line.long 0x4 "TIO4_G0_ISEL1_CTRL2," bitfld.long 0x4 22. "LUT3IN_SEL2,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x4 21. "LUT3IN_SEL1,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x4 20. "LUT3IN_SEL0,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x4 16.--17. "QOUT_SEL,select source for ISEL_QOUT signal in quad = q" "0,1,2,3" newline hexmask.long.byte 0x4 0.--7. 1. "LUT3,3 bit Lookup table function for quad=q; channels q*4+2 .. q*4" group.long 0x3240++0x3 line.long 0x0 "TIO4_G0_OP_USAGE," bitfld.long 0x0 31. "WRITE_EN7,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 30. "WRITE_EN6,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 29. "WRITE_EN5,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 28. "WRITE_EN4,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 27. "WRITE_EN3,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 26. "WRITE_EN2,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 25. "WRITE_EN1,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 24. "WRITE_EN0,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 21.--23. "MODE7,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "MODE6,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15.--17. "MODE5,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "MODE4,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9.--11. "MODE3,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "MODE2,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "MODE1,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "MODE0,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" group.long 0x3C00++0x1F line.long 0x0 "TIO4_S," bitfld.long 0x0 7. "CH7,Value of channel x." "0,1" newline bitfld.long 0x0 6. "CH6,Value of channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Value of channel x." "0,1" newline bitfld.long 0x0 4. "CH4,Value of channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Value of channel x." "0,1" newline bitfld.long 0x0 2. "CH2,Value of channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Value of channel x." "0,1" newline bitfld.long 0x0 0. "CH0,Value of channel x." "0,1" line.long 0x4 "TIO4_O," bitfld.long 0x4 7. "CH7,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 6. "CH6,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 4. "CH4,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 2. "CH2,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 0. "CH0,Value driven on output of channel x." "0,1" line.long 0x8 "TIO4_ENDIS," bitfld.long 0x8 7. "CH7,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 6. "CH6,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 4. "CH4,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 2. "CH2,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 0. "CH0,Enable/Disable request of channel x." "0,1" line.long 0xC "TIO4_INVERT," bitfld.long 0xC 7. "CH7,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 6. "CH6,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 4. "CH4,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 2. "CH2,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 0. "CH0,Enable/Disable signal inversion of channel x." "0,1" line.long 0x10 "TIO4_INPUT_MODE," bitfld.long 0x10 7. "CH7,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 6. "CH6,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 4. "CH4,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 2. "CH2,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 0. "CH0,Enable/Disable input mode of channel x." "0,1" line.long 0x14 "TIO4_CYCLIC_MODE," bitfld.long 0x14 7. "CH7,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 6. "CH6,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 4. "CH4,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 2. "CH2,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 0. "CH0,Enable/Disable cyclic mode of channel x." "0,1" line.long 0x18 "TIO4_TRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 6. "CH6,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 4. "CH4,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 2. "CH2,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 0. "CH0,enable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO4_PLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 6. "CH6,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 4. "CH4,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 2. "CH2,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 0. "CH0,enable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3C40++0x1F line.long 0x0 "TIO4_CS," bitfld.long 0x0 7. "CH7,Clear channel x." "0,1" newline bitfld.long 0x0 6. "CH6,Clear channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Clear channel x." "0,1" newline bitfld.long 0x0 4. "CH4,Clear channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Clear channel x." "0,1" newline bitfld.long 0x0 2. "CH2,Clear channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Clear channel x." "0,1" newline bitfld.long 0x0 0. "CH0,Clear channel x." "0,1" line.long 0x4 "TIO4_CO," bitfld.long 0x4 7. "CH7,Clear channel x." "0,1" newline bitfld.long 0x4 6. "CH6,Clear channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Clear channel x." "0,1" newline bitfld.long 0x4 4. "CH4,Clear channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Clear channel x." "0,1" newline bitfld.long 0x4 2. "CH2,Clear channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Clear channel x." "0,1" newline bitfld.long 0x4 0. "CH0,Clear channel x." "0,1" line.long 0x8 "TIO4_CENDIS," bitfld.long 0x8 7. "CH7,Disable request of channel x." "0,1" newline bitfld.long 0x8 6. "CH6,Disable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Disable request of channel x." "0,1" newline bitfld.long 0x8 4. "CH4,Disable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Disable request of channel x." "0,1" newline bitfld.long 0x8 2. "CH2,Disable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Disable request of channel x." "0,1" newline bitfld.long 0x8 0. "CH0,Disable request of channel x." "0,1" line.long 0xC "TIO4_CINVERT," bitfld.long 0xC 7. "CH7,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 6. "CH6,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 4. "CH4,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 2. "CH2,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 0. "CH0,Disable signal inversion of channel x." "0,1" line.long 0x10 "TIO4_CINPUT_MODE," bitfld.long 0x10 7. "CH7,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 6. "CH6,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 4. "CH4,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 2. "CH2,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 0. "CH0,Disable input mode of channel x." "0,1" line.long 0x14 "TIO4_CCYCLIC_MODE," bitfld.long 0x14 7. "CH7,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 6. "CH6,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 4. "CH4,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 2. "CH2,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 0. "CH0,Disable cyclic mode of channel x." "0,1" line.long 0x18 "TIO4_CTRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 6. "CH6,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 4. "CH4,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 2. "CH2,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 0. "CH0,disable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO4_CPLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 6. "CH6,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 4. "CH4,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 2. "CH2,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 0. "CH0,disable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3C80++0x1F line.long 0x0 "TIO4_SS," bitfld.long 0x0 7. "CH7,Set channel x." "0,1" newline bitfld.long 0x0 6. "CH6,Set channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Set channel x." "0,1" newline bitfld.long 0x0 4. "CH4,Set channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Set channel x." "0,1" newline bitfld.long 0x0 2. "CH2,Set channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Set channel x." "0,1" newline bitfld.long 0x0 0. "CH0,Set channel x." "0,1" line.long 0x4 "TIO4_SO," bitfld.long 0x4 7. "CH7,Set channel x." "0,1" newline bitfld.long 0x4 6. "CH6,Set channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Set channel x." "0,1" newline bitfld.long 0x4 4. "CH4,Set channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Set channel x." "0,1" newline bitfld.long 0x4 2. "CH2,Set channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Set channel x." "0,1" newline bitfld.long 0x4 0. "CH0,Set channel x." "0,1" line.long 0x8 "TIO4_SENDIS," bitfld.long 0x8 7. "CH7,Enable request of channel x." "0,1" newline bitfld.long 0x8 6. "CH6,Enable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Enable request of channel x." "0,1" newline bitfld.long 0x8 4. "CH4,Enable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Enable request of channel x." "0,1" newline bitfld.long 0x8 2. "CH2,Enable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Enable request of channel x." "0,1" newline bitfld.long 0x8 0. "CH0,Enable request of channel x." "0,1" line.long 0xC "TIO4_SINVERT," bitfld.long 0xC 7. "CH7,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 6. "CH6,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 4. "CH4,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 2. "CH2,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 0. "CH0,Enable signal inversion of channel x." "0,1" line.long 0x10 "TIO4_SINPUT_MODE," bitfld.long 0x10 7. "CH7,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 6. "CH6,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 4. "CH4,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 2. "CH2,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 0. "CH0,Enable input mode of channel x." "0,1" line.long 0x14 "TIO4_SCYCLIC_MODE," bitfld.long 0x14 7. "CH7,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 6. "CH6,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 4. "CH4,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 2. "CH2,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 0. "CH0,Enable cyclic mode of channel x." "0,1" line.long 0x18 "TIO4_STRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 6. "CH6,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 4. "CH4,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 2. "CH2,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 0. "CH0,enable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO4_SPLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 6. "CH6,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 4. "CH4,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 2. "CH2,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 0. "CH0,enable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3CC0++0x17 line.long 0x0 "TIO4_IS," bitfld.long 0x0 7. "CH7,Invert channel x." "0,1" newline bitfld.long 0x0 6. "CH6,Invert channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Invert channel x." "0,1" newline bitfld.long 0x0 4. "CH4,Invert channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Invert channel x." "0,1" newline bitfld.long 0x0 2. "CH2,Invert channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Invert channel x." "0,1" newline bitfld.long 0x0 0. "CH0,Invert channel x." "0,1" line.long 0x4 "TIO4_IO," bitfld.long 0x4 7. "CH7,Invert channel x." "0,1" newline bitfld.long 0x4 6. "CH6,Invert channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Invert channel x." "0,1" newline bitfld.long 0x4 4. "CH4,Invert channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Invert channel x." "0,1" newline bitfld.long 0x4 2. "CH2,Invert channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Invert channel x." "0,1" newline bitfld.long 0x4 0. "CH0,Invert channel x." "0,1" line.long 0x8 "TIO4_IENDIS," bitfld.long 0x8 7. "CH7,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 6. "CH6,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 4. "CH4,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 2. "CH2,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 0. "CH0,Toggle state request of channel x." "0,1" line.long 0xC "TIO4_IINVERT," bitfld.long 0xC 7. "CH7,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 6. "CH6,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 4. "CH4,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 2. "CH2,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 0. "CH0,Invert signal inversion of channel x." "0,1" line.long 0x10 "TIO4_IINPUT_MODE," bitfld.long 0x10 7. "CH7,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 6. "CH6,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 4. "CH4,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 2. "CH2,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 0. "CH0,Toggle input mode of channel x." "0,1" line.long 0x14 "TIO4_ICYCLIC_MODE," bitfld.long 0x14 7. "CH7,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 6. "CH6,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 4. "CH4,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 2. "CH2,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 0. "CH0,Toggle cyclic mode of channel x." "0,1" group.long 0x3D00++0x13 line.long 0x0 "TIO4_FUPD," bitfld.long 0x0 7. "CH7,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 6. "CH6,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 5. "CH5,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 4. "CH4,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 3. "CH3,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 2. "CH2,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 1. "CH1,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 0. "CH0,issue immediately a signal pulse on the update signal of channel x" "0,1" line.long 0x4 "TIO4_HW_CONF," bitfld.long 0x4 4. "TIO_PLUS,signals availablity of TIOplus functionality" "0,1" newline bitfld.long 0x4 0.--1. "NTIO_CH8,signals availablity of amount of channels" "0,1,2,3" line.long 0x8 "TIO4_RSEL_CTRL1," bitfld.long 0x8 28. "SEL_CLKEN7_0,select source of RS_CLKEN7[g][7] for channels g*8 .. g*8+7" "0,1" newline bitfld.long 0x8 24. "SEL_CLKEN6_0,select source of RS_CLKEN[g][6] for channels g*8 .. g*8+7" "0,1" line.long 0xC "TIO4_RSEL_CTRL2," bitfld.long 0xC 8. "SEL_TB2_0,select source of RS_TB2[g] for channels g*8 .. g*8+7" "0,1" newline bitfld.long 0xC 4. "SEL_TB1_0,select source of RS_TB1[g] for channels g*8 .. g*8+7" "0,1" line.long 0x10 "TIO4_PL_SWRST," bitfld.long 0x10 7. "CH7,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 6. "CH6,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 5. "CH5,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 4. "CH4,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 3. "CH3,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 2. "CH2,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 1. "CH1,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 0. "CH0,reset TIO_Plus resources of channel x" "0,1" group.long 0x4000++0x4F line.long 0x0 "CCM4_ARP0_CTRL," bitfld.long 0x0 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x0 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x0 0.--15. 1. "ADDR,ARP base address." line.long 0x4 "CCM4_ARP0_PROT," bitfld.long 0x4 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x8 "CCM4_ARP1_CTRL," bitfld.long 0x8 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x8 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x8 0.--15. 1. "ADDR,ARP base address." line.long 0xC "CCM4_ARP1_PROT," bitfld.long 0xC 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x10 "CCM4_ARP2_CTRL," bitfld.long 0x10 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x10 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x10 0.--15. 1. "ADDR,ARP base address." line.long 0x14 "CCM4_ARP2_PROT," bitfld.long 0x14 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x18 "CCM4_ARP3_CTRL," bitfld.long 0x18 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x18 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x18 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x18 0.--15. 1. "ADDR,ARP base address." line.long 0x1C "CCM4_ARP3_PROT," bitfld.long 0x1C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x20 "CCM4_ARP4_CTRL," bitfld.long 0x20 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x20 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x20 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x20 0.--15. 1. "ADDR,ARP base address." line.long 0x24 "CCM4_ARP4_PROT," bitfld.long 0x24 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x28 "CCM4_ARP5_CTRL," bitfld.long 0x28 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x28 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x28 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x28 0.--15. 1. "ADDR,ARP base address." line.long 0x2C "CCM4_ARP5_PROT," bitfld.long 0x2C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x30 "CCM4_ARP6_CTRL," bitfld.long 0x30 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x30 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x30 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x30 0.--15. 1. "ADDR,ARP base address." line.long 0x34 "CCM4_ARP6_PROT," bitfld.long 0x34 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x38 "CCM4_ARP7_CTRL," bitfld.long 0x38 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x38 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x38 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x38 0.--15. 1. "ADDR,ARP base address." line.long 0x3C "CCM4_ARP7_PROT," bitfld.long 0x3C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x40 "CCM4_ARP8_CTRL," bitfld.long 0x40 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x40 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x40 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x40 0.--15. 1. "ADDR,ARP base address." line.long 0x44 "CCM4_ARP8_PROT," bitfld.long 0x44 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x48 "CCM4_ARP9_CTRL," bitfld.long 0x48 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x48 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x48 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x48 0.--15. 1. "ADDR,ARP base address." line.long 0x4C "CCM4_ARP9_PROT," bitfld.long 0x4C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 0. "WPROT0,Write Protection MCS channel x." "0,1" group.long 0x41CC++0x3 line.long 0x0 "CCM4_TIO_G0_OUT," bitfld.long 0x0 31. "TIO_G1_OUT_N7,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 30. "TIO_G1_OUT_N6,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 29. "TIO_G1_OUT_N5,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 28. "TIO_G1_OUT_N4,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 27. "TIO_G1_OUT_N3,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 26. "TIO_G1_OUT_N2,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 25. "TIO_G1_OUT_N1,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 24. "TIO_G1_OUT_N0,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 23. "TIO_G0_OUT_N7,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 22. "TIO_G0_OUT_N6,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 21. "TIO_G0_OUT_N5,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 20. "TIO_G0_OUT_N4,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 19. "TIO_G0_OUT_N3,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 18. "TIO_G0_OUT_N2,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 17. "TIO_G0_OUT_N1,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 16. "TIO_G0_OUT_N0,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 15. "TIO_G1_OUT7,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 14. "TIO_G1_OUT6,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 13. "TIO_G1_OUT5,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 12. "TIO_G1_OUT4,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 11. "TIO_G1_OUT3,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 10. "TIO_G1_OUT2,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 9. "TIO_G1_OUT1,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 8. "TIO_G1_OUT0,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 7. "TIO_G0_OUT7,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 6. "TIO_G0_OUT6,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 5. "TIO_G0_OUT5,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 4. "TIO_G0_OUT4,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 3. "TIO_G0_OUT3,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 2. "TIO_G0_OUT2,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 1. "TIO_G0_OUT1,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 0. "TIO_G0_OUT0,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" group.long 0x41D4++0x2B line.long 0x0 "CCM4_HW_CONF2," bitfld.long 0x0 18. "AXIM_DATA_SIZE,Defines the data bus width of the AXI master interface" "0,1" newline bitfld.long 0x0 16. "AXIS_DATA_SIZE,Defines the data bus width of the AXI slave interface" "0,1" newline bitfld.long 0x0 9. "TIO_OUT_RST,TIO_OUT reset level" "0,1" newline bitfld.long 0x0 7. "AXIM_POSTED_WRITE,Write transaction without response" "0,1" newline bitfld.long 0x0 6. "AXIM_SEC_ACC,Secure AXI master access constant" "0,1" newline bitfld.long 0x0 5. "AXIM_PRIV_ACC,Privileged AXI master access constant" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "AXIM_ID_WIDTH,Defines which LSB of AXIM_ID are send to the bus" line.long 0x4 "CCM4_AEIM_STA," bitfld.long 0x4 24.--25. "AEIM_XPT_STA,AEIM Exception status." "0,1,2,3" newline hexmask.long.word 0x4 0.--15. 1. "AEIM_XPT_ADDR,Exception Address." line.long 0x8 "CCM4_HW_CONF," bitfld.long 0x8 31. "AEI_RDATA_PIPELINE_STAGE,Read data pipeline stage implemented" "0,1" newline bitfld.long 0x8 30. "AEI_ADDR_PIPELINE_STAGE,Address pipeline stage implemented" "0,1" newline bitfld.long 0x8 29. "INT_CLK_EN_GEN,Internal clock enable generation" "0,1" newline hexmask.long.byte 0x8 24.--28. 1. "TOM_TRIG_INTCHAIN,TOM internal trigger chain length without synchronization register" newline hexmask.long.byte 0x8 20.--23. 1. "ATOM_TRIG_INTCHAIN,ATOM internal trigger chain length without synchronization register" newline bitfld.long 0x8 19. "IRQ_MODE_SINGLE_PULSE,Signalize availability of Single Pulse IRQ mode" "0,1" newline bitfld.long 0x8 18. "IRQ_MODE_PULSE_NOTIFY,Signalize availability of Pulse Notoify IRQ mode" "0,1" newline bitfld.long 0x8 17. "IRQ_MODE_PULSE,Signalize availability of Pulse IRQ mode" "0,1" newline bitfld.long 0x8 16. "IRQ_MODE_LEVEL,Signalize availability of Level IRQ mode" "0,1" newline bitfld.long 0x8 15. "RESET_ACTIVE,Active level of asynchronous reset" "0,1" newline bitfld.long 0x8 13. "ERM,Enable RAM1 MSB for available MCS modules" "0,1" newline bitfld.long 0x8 12. "RAM_INIT_RST,RAM initialization from reset" "0,1" newline bitfld.long 0x8 9.--11. "TOM_TRIG_CHAIN,TOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "TOM_OUT_RST,TOM_OUT reset level" "0,1" newline bitfld.long 0x8 5.--7. "ATOM_TRIG_CHAIN,ATOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "ATOM_OUT_RST,ATOM_OUT reset level" "0,1" newline bitfld.long 0x8 3. "CFG_CLOCK_RATE,Clocks per ARU transfer" "0,1" newline bitfld.long 0x8 2. "SYNC_INPUT_REG,Additional pipelined stage in synchronous bridge mode" "0,1" newline bitfld.long 0x8 1. "BRIDGE_MODE_RST,Bridge mode after reset" "0,1" newline bitfld.long 0x8 0. "GRSTEN,Global Reset Enable" "0,1" line.long 0xC "CCM4_TIM_AUX_IN_SRC," bitfld.long 0xC 23. "SEL_OUT_N_CH7,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 22. "SEL_OUT_N_CH6,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 21. "SEL_OUT_N_CH5,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 20. "SEL_OUT_N_CH4,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 19. "SEL_OUT_N_CH3,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 18. "SEL_OUT_N_CH2,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 17. "SEL_OUT_N_CH1,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 16. "SEL_OUT_N_CH0,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 7. "SRC_CH7,Defines AUX_IN source of TIM[i] channel 7" "0,1" newline bitfld.long 0xC 6. "SRC_CH6,Defines AUX_IN source of TIM[i] channel 6" "0,1" newline bitfld.long 0xC 5. "SRC_CH5,Defines AUX_IN source of TIM[i] channel 5" "0,1" newline bitfld.long 0xC 4. "SRC_CH4,Defines AUX_IN source of TIM[i] channel 4" "0,1" newline bitfld.long 0xC 3. "SRC_CH3,Defines AUX_IN source of TIM[i] channel 3" "0,1" newline bitfld.long 0xC 2. "SRC_CH2,Defines AUX_IN source of TIM[i] channel 2" "0,1" newline bitfld.long 0xC 1. "SRC_CH1,Defines AUX_IN source of TIM[i] channel 1" "0,1" newline bitfld.long 0xC 0. "SRC_CH0,Defines AUX_IN source of TIM[i] channel 0" "0,1" line.long 0x10 "CCM4_EXT_CAP_EN," bitfld.long 0x10 15. "TIM_IP1_EXT_CAP_EN7,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 14. "TIM_IP1_EXT_CAP_EN6,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 13. "TIM_IP1_EXT_CAP_EN5,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 12. "TIM_IP1_EXT_CAP_EN4,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 11. "TIM_IP1_EXT_CAP_EN3,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 10. "TIM_IP1_EXT_CAP_EN2,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 9. "TIM_IP1_EXT_CAP_EN1,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 8. "TIM_IP1_EXT_CAP_EN0,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 7. "TIM_I_EXT_CAP_EN7,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 6. "TIM_I_EXT_CAP_EN6,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 5. "TIM_I_EXT_CAP_EN5,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 4. "TIM_I_EXT_CAP_EN4,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 3. "TIM_I_EXT_CAP_EN3,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 2. "TIM_I_EXT_CAP_EN2,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 1. "TIM_I_EXT_CAP_EN1,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 0. "TIM_I_EXT_CAP_EN0,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" line.long 0x14 "CCM4_TOM_OUT," bitfld.long 0x14 31. "TOM_OUT_N15,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 30. "TOM_OUT_N14,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 29. "TOM_OUT_N13,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 28. "TOM_OUT_N12,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 27. "TOM_OUT_N11,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 26. "TOM_OUT_N10,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 25. "TOM_OUT_N9,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 24. "TOM_OUT_N8,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 23. "TOM_OUT_N7,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 22. "TOM_OUT_N6,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 21. "TOM_OUT_N5,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 20. "TOM_OUT_N4,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 19. "TOM_OUT_N3,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 18. "TOM_OUT_N2,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 17. "TOM_OUT_N1,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 16. "TOM_OUT_N0,Output level snapshot of TOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x14 15. "TOM_OUT15,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 14. "TOM_OUT14,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 13. "TOM_OUT13,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 12. "TOM_OUT12,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 11. "TOM_OUT11,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 10. "TOM_OUT10,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 9. "TOM_OUT9,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 8. "TOM_OUT8,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 7. "TOM_OUT7,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 6. "TOM_OUT6,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 5. "TOM_OUT5,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 4. "TOM_OUT4,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 3. "TOM_OUT3,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 2. "TOM_OUT2,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 1. "TOM_OUT1,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x14 0. "TOM_OUT0,Output level snapshot of TOM[i]_OUT channel [x]" "0,1" line.long 0x18 "CCM4_ATOM_OUT," bitfld.long 0x18 31. "ATOM_IP1_OUT_N7,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 30. "ATOM_IP1_OUT_N6,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 29. "ATOM_IP1_OUT_N5,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 28. "ATOM_IP1_OUT_N4,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 27. "ATOM_IP1_OUT_N3,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 26. "ATOM_IP1_OUT_N2,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 25. "ATOM_IP1_OUT_N1,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 24. "ATOM_IP1_OUT_N0,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 23. "ATOM_IP1_OUT7,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 22. "ATOM_IP1_OUT6,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 21. "ATOM_IP1_OUT5,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 20. "ATOM_IP1_OUT4,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 19. "ATOM_IP1_OUT3,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 18. "ATOM_IP1_OUT2,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 17. "ATOM_IP1_OUT1,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 16. "ATOM_IP1_OUT0,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x18 15. "ATOM_I_OUT_N7,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 14. "ATOM_I_OUT_N6,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 13. "ATOM_I_OUT_N5,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 12. "ATOM_I_OUT_N4,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 11. "ATOM_I_OUT_N3,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 10. "ATOM_I_OUT_N2,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 9. "ATOM_I_OUT_N1,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 8. "ATOM_I_OUT_N0,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x18 7. "ATOM_I_OUT7,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 6. "ATOM_I_OUT6,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 5. "ATOM_I_OUT5,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 4. "ATOM_I_OUT4,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 3. "ATOM_I_OUT3,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 2. "ATOM_I_OUT2,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 1. "ATOM_I_OUT1,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x18 0. "ATOM_I_OUT0,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" line.long 0x1C "CCM4_CMU_CLK_CFG," bitfld.long 0x1C 28.--29. "CLK7_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 24.--25. "CLK6_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 20.--21. "CLK5_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 16.--17. "CLK4_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 12.--13. "CLK3_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 8.--9. "CLK2_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 4.--5. "CLK1_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "CLK0_SRC,Clock y source signal selector" "0,1,2,3" line.long 0x20 "CCM4_CMU_FXCLK_CFG," hexmask.long.byte 0x20 0.--3. 1. "FXCLK0_SRC,Fixed clock 0 source signal selector" line.long 0x24 "CCM4_CFG," bitfld.long 0x24 31. "TBU_DIR2,DIR1 input signal of module TBU timebase [z]." "0,1" newline bitfld.long 0x24 30. "TBU_DIR1,DIR1 input signal of module TBU timebase [z]." "0,1" newline bitfld.long 0x24 16.--17. "CLS_CLK_DIV,Cluster Clock Divider." "0,1,2,3" newline bitfld.long 0x24 8. "EN_TIO_DTM,Enable TIO and connected DTM" "0,1" newline bitfld.long 0x24 7. "EN_CMP_MON,Enable CMP and MON" "0,1" newline bitfld.long 0x24 6. "EN_PSM,Enable PSM" "0,1" newline bitfld.long 0x24 5. "EN_BRC,Enable BRC" "0,1" newline bitfld.long 0x24 4. "EN_DPLL_MAP,Enable DPLL and MAP" "0,1" newline bitfld.long 0x24 3. "EN_MCS,Enable MCS" "0,1" newline bitfld.long 0x24 2. "EN_ATOM_ADTM,Enable ATOM and ADTM" "0,1" newline bitfld.long 0x24 1. "EN_TOM_SPE_TDTM,Enable TOM SPE and TDTM" "0,1" newline bitfld.long 0x24 0. "EN_TIM,Enable TIM" "0,1" line.long 0x28 "CCM4_PROT," bitfld.long 0x28 0. "CLS_PROT,Cluster Protection" "0,1" group.long 0x4500++0x7F line.long 0x0 "CDTM4_DTM4_CTRL," bitfld.long 0x0 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x0 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x0 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x0 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x0 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x4 "CDTM4_DTM4_CH_CTRL1," bitfld.long 0x4 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x4 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x4 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x4 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x4 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x4 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x4 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x4 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x4 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x4 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x4 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x4 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x4 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x4 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x4 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x4 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x4 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x8 "CDTM4_DTM4_CH_CTRL2," bitfld.long 0x8 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x8 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x8 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x8 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x8 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x8 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x8 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x8 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x8 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x8 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x8 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x8 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x8 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x8 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x8 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x8 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x8 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x8 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x8 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x8 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x8 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x8 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x8 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x8 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x8 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x8 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x8 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x8 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x8 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x8 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x8 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x8 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0xC "CDTM4_DTM4_CH_CTRL2_SR," bitfld.long 0xC 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x10 "CDTM4_DTM4_PS_CTRL," bitfld.long 0x10 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x10 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x10 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x10 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x10 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x14 "CDTM4_DTM4_CH0_DTV," bitfld.long 0x14 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x14 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x14 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x18 "CDTM4_DTM4_CH1_DTV," bitfld.long 0x18 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x18 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x18 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x1C "CDTM4_DTM4_CH2_DTV," bitfld.long 0x1C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x1C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x1C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x20 "CDTM4_DTM4_CH3_DTV," bitfld.long 0x20 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x20 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x20 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x24 "CDTM4_DTM4_CH_SR," bitfld.long 0x24 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x24 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x24 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x24 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x24 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x24 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x24 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x24 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x28 "CDTM4_DTM4_CH_CTRL3," bitfld.long 0x28 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x28 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x28 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x28 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x28 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x28 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x28 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x28 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x2C "CDTM4_DTM4_CTRL2," bitfld.long 0x2C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x2C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x2C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x2C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x2C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x2C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x2C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x2C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x2C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x2C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x2C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x2C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x2C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x2C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x2C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x2C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x2C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x2C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x2C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x2C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x30 "CDTM4_DTM4_CH0_DTV_SR," bitfld.long 0x30 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x30 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x30 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x30 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x30 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x30 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x34 "CDTM4_DTM4_CH1_DTV_SR," bitfld.long 0x34 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x34 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x34 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x34 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x34 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x34 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x38 "CDTM4_DTM4_CH2_DTV_SR," bitfld.long 0x38 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x38 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x38 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x38 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x38 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x38 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x3C "CDTM4_DTM4_CH3_DTV_SR," bitfld.long 0x3C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x3C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x3C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x3C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x3C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x3C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x40 "CDTM4_DTM5_CTRL," bitfld.long 0x40 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x40 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x40 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x40 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x40 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x44 "CDTM4_DTM5_CH_CTRL1," bitfld.long 0x44 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x44 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x44 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x44 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x44 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x44 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x44 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x44 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x44 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x44 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x44 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x44 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x44 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x44 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x44 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x44 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x44 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x48 "CDTM4_DTM5_CH_CTRL2," bitfld.long 0x48 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x48 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x48 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x48 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x48 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x48 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x48 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x48 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x48 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x48 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x48 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x48 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x48 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x48 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x48 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x48 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x48 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x48 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x48 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x48 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x48 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x48 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x48 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x48 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x48 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x48 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x48 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x48 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x48 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x48 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x48 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x48 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0x4C "CDTM4_DTM5_CH_CTRL2_SR," bitfld.long 0x4C 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x50 "CDTM4_DTM5_PS_CTRL," bitfld.long 0x50 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x50 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x50 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x50 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x50 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x54 "CDTM4_DTM5_CH0_DTV," bitfld.long 0x54 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x54 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x54 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x58 "CDTM4_DTM5_CH1_DTV," bitfld.long 0x58 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x58 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x58 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x5C "CDTM4_DTM5_CH2_DTV," bitfld.long 0x5C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x5C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x5C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x60 "CDTM4_DTM5_CH3_DTV," bitfld.long 0x60 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x60 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x60 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x64 "CDTM4_DTM5_CH_SR," bitfld.long 0x64 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x64 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x64 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x64 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x64 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x64 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x64 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x64 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x68 "CDTM4_DTM5_CH_CTRL3," bitfld.long 0x68 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x68 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x68 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x68 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x68 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x68 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x68 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x68 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x6C "CDTM4_DTM5_CTRL2," bitfld.long 0x6C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x6C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x6C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x6C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x6C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x6C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x6C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x6C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x6C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x6C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x6C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x6C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x6C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x6C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x6C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x6C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x6C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x6C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x6C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x6C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x70 "CDTM4_DTM5_CH0_DTV_SR," bitfld.long 0x70 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x70 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x70 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x70 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x70 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x70 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x74 "CDTM4_DTM5_CH1_DTV_SR," bitfld.long 0x74 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x74 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x74 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x74 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x74 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x74 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x78 "CDTM4_DTM5_CH2_DTV_SR," bitfld.long 0x78 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x78 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x78 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x78 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x78 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x78 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x7C "CDTM4_DTM5_CH3_DTV_SR," bitfld.long 0x7C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x7C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x7C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x7C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x7C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x7C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" group.long 0x4C00++0x4F line.long 0x0 "SPE4_CTRL_STAT," hexmask.long.byte 0x0 24.--31. 1. "FSOL,Fast Shutoff Level for TOM[i] channel 0 to 7" newline bitfld.long 0x0 23. "ETRIG_SEL,Extended trigger selection of signal SPE[i]_CTRL_STAT.TRIG_SEL" "0,1" newline bitfld.long 0x0 20.--22. "NIP,New input pattern that was detected." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "PDIR,Previous rotation direction." "0,1" newline bitfld.long 0x0 16.--18. "PIP,Previous input pattern that was detected by a regular input pattern change." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "ADIR,Rotation direction. Will be reflected in the signal SPE(i)_DIR." "0,1" newline bitfld.long 0x0 12.--14. "AIP,Input pattern that was detected by a regular input pattern change." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "SPE_PAT_PTR,Pattern selector for TOM output signals." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "FSOM,Fast Shutoff Mode" "0,1" newline bitfld.long 0x0 6. "TIM_SEL,Select TIM input signal" "0,1" newline bitfld.long 0x0 4.--5. "TRIG_SEL,Select trigger input signal." "0,1,2,3" newline bitfld.long 0x0 3. "SIE2,SPE Input enable for TIM_CHx(48)." "0,1" newline bitfld.long 0x0 2. "SIE1,SPE Input enable for TIM_CHx(48)." "0,1" newline bitfld.long 0x0 1. "SIE0,SPE Input enable for TIM_CHx(48)." "0,1" newline bitfld.long 0x0 0. "EN,SPE Submodule enable." "0,1" line.long 0x4 "SPE4_PAT," bitfld.long 0x4 29.--31. "IP7_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "IP7_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 25.--27. "IP6_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 24. "IP6_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 21.--23. "IP5_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "IP5_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 17.--19. "IP4_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "IP4_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 13.--15. "IP3_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12. "IP3_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 9.--11. "IP2_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "IP2_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 5.--7. "IP1_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4. "IP1_VAL,Input pattern t is a valid pattern." "0,1" newline bitfld.long 0x4 1.--3. "IP0_PAT,Input pattern t." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "IP0_VAL,Input pattern t is a valid pattern." "0,1" line.long 0x8 "SPE4_OUT_PAT0," bitfld.long 0x8 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x8 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0xC "SPE4_OUT_PAT1," bitfld.long 0xC 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0xC 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x10 "SPE4_OUT_PAT2," bitfld.long 0x10 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x10 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x14 "SPE4_OUT_PAT3," bitfld.long 0x14 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x14 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x18 "SPE4_OUT_PAT4," bitfld.long 0x18 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x18 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x1C "SPE4_OUT_PAT5," bitfld.long 0x1C 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x20 "SPE4_OUT_PAT6," bitfld.long 0x20 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x20 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x24 "SPE4_OUT_PAT7," bitfld.long 0x24 14.--15. "SPE_OUT_PAT7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 12.--13. "SPE_OUT_PAT6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 10.--11. "SPE_OUT_PAT5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 8.--9. "SPE_OUT_PAT4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 6.--7. "SPE_OUT_PAT3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 4.--5. "SPE_OUT_PAT2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 2.--3. "SPE_OUT_PAT1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x24 0.--1. "SPE_OUT_PAT0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x28 "SPE4_OUT_CTRL," bitfld.long 0x28 14.--15. "SPE_OUT_CTRL7,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 12.--13. "SPE_OUT_CTRL6,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 10.--11. "SPE_OUT_CTRL5,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 8.--9. "SPE_OUT_CTRL4,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 6.--7. "SPE_OUT_CTRL3,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 4.--5. "SPE_OUT_CTRL2,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 2.--3. "SPE_OUT_CTRL1,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" newline bitfld.long 0x28 0.--1. "SPE_OUT_CTRL0,SPE output control value for TOM_CH0 to TOM_CH7" "0,1,2,3" line.long 0x2C "SPE4_IRQ_NOTIFY," bitfld.long 0x2C 4. "SPE_RCMP,SPE revolution counter match event." "0,1" newline bitfld.long 0x2C 3. "SPE_BIS,Bouncing input signal detected." "0,1" newline bitfld.long 0x2C 2. "SPE_PERR,Wrong or invalid pattern detected at input." "0,1" newline bitfld.long 0x2C 1. "SPE_DCHG,SPE_DIR bit changed on behalf of new input pattern." "0,1" newline bitfld.long 0x2C 0. "SPE_NIPD,New input pattern interrupt occurred." "0,1" line.long 0x30 "SPE4_IRQ_EN," bitfld.long 0x30 4. "SPE_RCMP_IRQ_EN,SPE_RCMP_IRQ interrupt enable." "0,1" newline bitfld.long 0x30 3. "SPE_BIS_IRQ_EN,SPE_BIS_IRQ interrupt enable." "0,1" newline bitfld.long 0x30 2. "SPE_PERR_IRQ_EN,SPE_PERR_IRQ interrupt enable." "0,1" newline bitfld.long 0x30 1. "SPE_DCHG_IRQ_EN,SPE_DCHG_IRQ interrupt enable." "0,1" newline bitfld.long 0x30 0. "SPE_NIPD_IRQ_EN,SPE_NIPD_IRQ interrupt enable." "0,1" line.long 0x34 "SPE4_IRQ_FORCINT," bitfld.long 0x34 4. "TRG_SPE_RCMP,Force interrupt of SPE_RCMP." "0,1" newline bitfld.long 0x34 3. "TRG_SPE_BIS,Force interrupt of SPE_BIS." "0,1" newline bitfld.long 0x34 2. "TRG_SPE_PERR,Force interrupt of SPE_PERR." "0,1" newline bitfld.long 0x34 1. "TRG_SPE_DCHG,Force interrupt of SPE_DCHG." "0,1" newline bitfld.long 0x34 0. "TRG_SPE_NIPD,Force interrupt of SPE_NIPD." "0,1" line.long 0x38 "SPE4_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x3C "SPE4_EIRQ_EN," bitfld.long 0x3C 4. "SPE_RCMP_EIRQ_EN,SPE_RCMP_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x3C 3. "SPE_BIS_EIRQ_EN,SPE_BIS_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x3C 2. "SPE_PERR_EIRQ_EN,SPE_PERR_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x3C 1. "SPE_DCHG_EIRQ_EN,SPE_DCHG_EIRQ error interrupt enable." "0,1" newline bitfld.long 0x3C 0. "SPE_NIPD_EIRQ_EN,SPE_NIPD_EIRQ interrupt enable." "0,1" line.long 0x40 "SPE4_REV_CNT," hexmask.long.tbyte 0x40 0.--23. 1. "REV_CNT,Input signal revolution counter" line.long 0x44 "SPE4_REV_CMP," hexmask.long.tbyte 0x44 0.--23. 1. "REV_CMP,Input signal revolution counter compare value" line.long 0x48 "SPE4_CTRL_STAT2," bitfld.long 0x48 8.--10. "SPE_PAT_PTR_BWD,Pattern selector for TOM output signals in case of SPE[i]_CMD.SPE_CTRL_CMD = 0b01 (e.g. backward direction)." "0,1,2,3,4,5,6,7" line.long 0x4C "SPE4_CMD," bitfld.long 0x4C 16. "SPE_UPD_TRIG,SPE updater trigger" "0,1" newline bitfld.long 0x4C 0.--1. "SPE_CTRL_CMD,SPE control command" "0,1,2,3" group.long 0x5000++0xB line.long 0x0 "AXIM4_FREE," bitfld.long 0x0 3. "FREE3,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 2. "FREE2,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 1. "FREE1,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 0. "FREE0,This bit represents the allocation status of the slot [t]" "0,1" line.long 0x4 "AXIM4_REQUEST," hexmask.long.byte 0x4 24.--31. 1. "REQID,This bit field shows the new allocated slot as binary encoded index. If no slot could be allocated this bit field is read as all 1 (0xff)." newline bitfld.long 0x4 3. "REQ1HOT3,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 2. "REQ1HOT2,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 1. "REQ1HOT1,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 0. "REQ1HOT0,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" line.long 0x8 "AXIM4_RELEASE," bitfld.long 0x8 3. "RELREQ3,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 2. "RELREQ2,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 1. "RELREQ1,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 0. "RELREQ0,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" group.long 0x5020++0x3 line.long 0x0 "AXIM4_SLOT0_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5028++0x3 line.long 0x0 "AXIM4_SLOT0_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5030++0xB line.long 0x0 "AXIM4_SLOT0_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM4_SLOT0_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM4_SLOT0_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5040++0x3 line.long 0x0 "AXIM4_SLOT1_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5048++0x3 line.long 0x0 "AXIM4_SLOT1_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5050++0xB line.long 0x0 "AXIM4_SLOT1_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM4_SLOT1_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM4_SLOT1_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5060++0x3 line.long 0x0 "AXIM4_SLOT2_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5068++0x3 line.long 0x0 "AXIM4_SLOT2_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5070++0xB line.long 0x0 "AXIM4_SLOT2_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM4_SLOT2_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM4_SLOT2_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5080++0x3 line.long 0x0 "AXIM4_SLOT3_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5088++0x3 line.long 0x0 "AXIM4_SLOT3_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5090++0xB line.long 0x0 "AXIM4_SLOT3_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM4_SLOT3_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM4_SLOT3_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" repeat 16384. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10000)++0x3 line.long 0x0 "MCS4_MEM[$1]," hexmask.long 0x0 0.--31. 1. "DATA,MCS memory location." repeat.end tree.end tree "GTM_CLS5" base ad:0x740A0000 group.long 0x800++0x3F line.long 0x0 "TIM5_CH0_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM5_CH0_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM5_CH0_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM5_CH0_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM5_CH0_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM5_CH0_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM5_CH0_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM5_CH0_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM5_CH0_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM5_CH0_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM5_CH0_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM5_CH0_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM5_CH0_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM5_CH0_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM5_CH0_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM5_CH0_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x880++0x3F line.long 0x0 "TIM5_CH1_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM5_CH1_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM5_CH1_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM5_CH1_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM5_CH1_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM5_CH1_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM5_CH1_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM5_CH1_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM5_CH1_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM5_CH1_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM5_CH1_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM5_CH1_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM5_CH1_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM5_CH1_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM5_CH1_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM5_CH1_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x900++0x3F line.long 0x0 "TIM5_CH2_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM5_CH2_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM5_CH2_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM5_CH2_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM5_CH2_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM5_CH2_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM5_CH2_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM5_CH2_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM5_CH2_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM5_CH2_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM5_CH2_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM5_CH2_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM5_CH2_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM5_CH2_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM5_CH2_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM5_CH2_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x980++0x3F line.long 0x0 "TIM5_CH3_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM5_CH3_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM5_CH3_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM5_CH3_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM5_CH3_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM5_CH3_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM5_CH3_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM5_CH3_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM5_CH3_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM5_CH3_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM5_CH3_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM5_CH3_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM5_CH3_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM5_CH3_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM5_CH3_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM5_CH3_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xA00++0x3F line.long 0x0 "TIM5_CH4_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM5_CH4_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM5_CH4_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM5_CH4_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM5_CH4_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM5_CH4_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM5_CH4_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM5_CH4_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM5_CH4_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM5_CH4_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM5_CH4_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM5_CH4_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM5_CH4_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM5_CH4_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM5_CH4_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM5_CH4_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xA80++0x3F line.long 0x0 "TIM5_CH5_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM5_CH5_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM5_CH5_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM5_CH5_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM5_CH5_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM5_CH5_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM5_CH5_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM5_CH5_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM5_CH5_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM5_CH5_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM5_CH5_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM5_CH5_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM5_CH5_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM5_CH5_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM5_CH5_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM5_CH5_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xB00++0x3F line.long 0x0 "TIM5_CH6_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM5_CH6_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM5_CH6_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM5_CH6_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM5_CH6_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM5_CH6_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM5_CH6_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM5_CH6_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM5_CH6_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM5_CH6_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM5_CH6_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM5_CH6_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM5_CH6_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM5_CH6_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM5_CH6_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM5_CH6_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xB80++0x3F line.long 0x0 "TIM5_CH7_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM5_CH7_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM5_CH7_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM5_CH7_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM5_CH7_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM5_CH7_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM5_CH7_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM5_CH7_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM5_CH7_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM5_CH7_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM5_CH7_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM5_CH7_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM5_CH7_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM5_CH7_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM5_CH7_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM5_CH7_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xC00++0xB line.long 0x0 "TIM5_INP_VAL," bitfld.long 0x0 23. "TIM_IN7,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 22. "TIM_IN6,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 21. "TIM_IN5,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 20. "TIM_IN4,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 19. "TIM_IN3,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 18. "TIM_IN2,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 17. "TIM_IN1,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 16. "TIM_IN0,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 15. "F_IN7,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 14. "F_IN6,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 13. "F_IN5,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 12. "F_IN4,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 11. "F_IN3,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 10. "F_IN2,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 9. "F_IN1,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 8. "F_IN0,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 7. "F_OUT7,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 6. "F_OUT6,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 5. "F_OUT5,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 4. "F_OUT4,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 3. "F_OUT3,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 2. "F_OUT2,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 1. "F_OUT1,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 0. "F_OUT0,Signal channel x after TIM FLT unit" "0,1" line.long 0x4 "TIM5_IN_SRC," bitfld.long 0x4 30.--31. "MODE_7,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 28.--29. "VAL_7,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 26.--27. "MODE_6,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 24.--25. "VAL_6,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 22.--23. "MODE_5,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 20.--21. "VAL_5,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 18.--19. "MODE_4,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 16.--17. "VAL_4,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 14.--15. "MODE_3,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 12.--13. "VAL_3,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 10.--11. "MODE_2,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 8.--9. "VAL_2,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 6.--7. "MODE_1,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 4.--5. "VAL_1,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 2.--3. "MODE_0,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 0.--1. "VAL_0,Value to be fed to channel [x]" "0,1,2,3" line.long 0x8 "TIM5_RST," bitfld.long 0x8 7. "RST_CH7,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 6. "RST_CH6,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 5. "RST_CH5,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 4. "RST_CH4,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 3. "RST_CH3,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 2. "RST_CH2,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 1. "RST_CH1,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 0. "RST_CH0,Software reset of channel [x]" "0,1" group.long 0x1800++0x2F line.long 0x0 "ATOM5_CH0_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM5_CH0_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM5_CH0_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM5_CH0_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM5_CH0_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM5_CH0_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM5_CH0_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM5_CH0_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM5_CH0_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM5_CH0_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM5_CH0_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM5_CH0_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1834++0x3 line.long 0x0 "ATOM5_CH0_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1880++0x2F line.long 0x0 "ATOM5_CH1_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM5_CH1_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM5_CH1_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM5_CH1_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM5_CH1_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM5_CH1_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM5_CH1_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM5_CH1_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM5_CH1_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM5_CH1_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM5_CH1_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM5_CH1_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x18B4++0x3 line.long 0x0 "ATOM5_CH1_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1900++0x2F line.long 0x0 "ATOM5_CH2_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM5_CH2_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM5_CH2_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM5_CH2_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM5_CH2_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM5_CH2_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM5_CH2_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM5_CH2_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM5_CH2_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM5_CH2_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM5_CH2_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM5_CH2_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1934++0x3 line.long 0x0 "ATOM5_CH2_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1980++0x2F line.long 0x0 "ATOM5_CH3_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM5_CH3_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM5_CH3_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM5_CH3_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM5_CH3_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM5_CH3_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM5_CH3_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM5_CH3_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM5_CH3_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM5_CH3_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM5_CH3_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM5_CH3_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x19B4++0x3 line.long 0x0 "ATOM5_CH3_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A00++0x2F line.long 0x0 "ATOM5_CH4_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM5_CH4_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM5_CH4_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM5_CH4_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM5_CH4_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM5_CH4_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM5_CH4_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM5_CH4_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM5_CH4_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM5_CH4_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM5_CH4_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM5_CH4_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1A34++0x3 line.long 0x0 "ATOM5_CH4_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A80++0x2F line.long 0x0 "ATOM5_CH5_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM5_CH5_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM5_CH5_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM5_CH5_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM5_CH5_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM5_CH5_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM5_CH5_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM5_CH5_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM5_CH5_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM5_CH5_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM5_CH5_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM5_CH5_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1AB4++0x3 line.long 0x0 "ATOM5_CH5_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B00++0x2F line.long 0x0 "ATOM5_CH6_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM5_CH6_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM5_CH6_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM5_CH6_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM5_CH6_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM5_CH6_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM5_CH6_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM5_CH6_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM5_CH6_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM5_CH6_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM5_CH6_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM5_CH6_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1B34++0x3 line.long 0x0 "ATOM5_CH6_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B80++0x2F line.long 0x0 "ATOM5_CH7_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM5_CH7_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM5_CH7_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM5_CH7_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM5_CH7_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM5_CH7_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM5_CH7_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM5_CH7_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM5_CH7_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM5_CH7_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM5_CH7_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM5_CH7_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1BB4++0x3 line.long 0x0 "ATOM5_CH7_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1C40++0x1F line.long 0x0 "ATOM5_AGC_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 28.--29. "UPEN_CTRL6,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 26.--27. "UPEN_CTRL5,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 24.--25. "UPEN_CTRL4,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 22.--23. "UPEN_CTRL3,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 20.--21. "UPEN_CTRL2,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 16.--17. "UPEN_CTRL0,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 15. "RST_CH7,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 14. "RST_CH6,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 13. "RST_CH5,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 12. "RST_CH4,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 10. "RST_CH2,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 9. "RST_CH1,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 8. "RST_CH0,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see AGC) to update the register ATOM[i]_AGC_ENDIS_STAT and ATOM[i]_AGC_OUTEN_STAT" "0,1" line.long 0x4 "ATOM5_AGC_ENDIS_CTRL," bitfld.long 0x4 14.--15. "ENDIS_CTRL7,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 12.--13. "ENDIS_CTRL6,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 10.--11. "ENDIS_CTRL5,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 8.--9. "ENDIS_CTRL4,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 6.--7. "ENDIS_CTRL3,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 4.--5. "ENDIS_CTRL2,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_CTRL1,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 0.--1. "ENDIS_CTRL0,ATOM channel [k] enable/disable update value." "0,1,2,3" line.long 0x8 "ATOM5_AGC_ENDIS_STAT," bitfld.long 0x8 14.--15. "ENDIS_STAT7,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 12.--13. "ENDIS_STAT6,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 10.--11. "ENDIS_STAT5,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 8.--9. "ENDIS_STAT4,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 6.--7. "ENDIS_STAT3,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 4.--5. "ENDIS_STAT2,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 2.--3. "ENDIS_STAT1,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 0.--1. "ENDIS_STAT0,ATOM channel [k] enable/disable" "0,1,2,3" line.long 0xC "ATOM5_AGC_ACT_TB," bitfld.long 0xC 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" newline bitfld.long 0xC 24. "TB_TRIG,Set trigger request" "0,1" newline hexmask.long.tbyte 0xC 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[x] x=0..2. If selected TBU_TS[x] value is in the interval [ATOM[i]_AGC_ACT_TB.ACT_TB-007FFFFFh ATOM[i]_AGC_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x10 "ATOM5_AGC_OUTEN_CTRL," bitfld.long 0x10 14.--15. "OUTEN_CTRL7,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 12.--13. "OUTEN_CTRL6,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 10.--11. "OUTEN_CTRL5,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 8.--9. "OUTEN_CTRL4,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 6.--7. "OUTEN_CTRL3,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 4.--5. "OUTEN_CTRL2,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 2.--3. "OUTEN_CTRL1,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 0.--1. "OUTEN_CTRL0,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" line.long 0x14 "ATOM5_AGC_OUTEN_STAT," bitfld.long 0x14 14.--15. "OUTEN_STAT7,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 12.--13. "OUTEN_STAT6,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 10.--11. "OUTEN_STAT5,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 8.--9. "OUTEN_STAT4,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 6.--7. "OUTEN_STAT3,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 4.--5. "OUTEN_STAT2,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 2.--3. "OUTEN_STAT1,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 0.--1. "OUTEN_STAT0,Control/status of output ATOM_OUT [k]" "0,1,2,3" line.long 0x18 "ATOM5_AGC_FUPD_CTRL," bitfld.long 0x18 30.--31. "RSTCN0_CH7,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 28.--29. "RSTCN0_CH6,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 26.--27. "RSTCN0_CH5,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 24.--25. "RSTCN0_CH4,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 22.--23. "RSTCN0_CH3,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 20.--21. "RSTCN0_CH2,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 18.--19. "RSTCN0_CH1,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 16.--17. "RSTCN0_CH0,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 14.--15. "FUPD_CTRL7,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 12.--13. "FUPD_CTRL6,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 10.--11. "FUPD_CTRL5,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 8.--9. "FUPD_CTRL4,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 6.--7. "FUPD_CTRL3,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 4.--5. "FUPD_CTRL2,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 2.--3. "FUPD_CTRL1,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 0.--1. "FUPD_CTRL0,Force update of ATOM channel [k] operation registers" "0,1,2,3" line.long 0x1C "ATOM5_AGC_INT_TRIG," bitfld.long 0x1C 14.--15. "INT_TRIG7,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 12.--13. "INT_TRIG6,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 10.--11. "INT_TRIG5,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 8.--9. "INT_TRIG4,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 6.--7. "INT_TRIG3,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 4.--5. "INT_TRIG2,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 2.--3. "INT_TRIG1,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "INT_TRIG0,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" group.long 0x2000++0x27 line.long 0x0 "MCS5_CH0_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS5_CH0_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS5_CH0_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS5_CH0_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS5_CH0_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS5_CH0_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS5_CH0_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS5_CH0_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS5_CH0_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS5_CH0_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x203C++0x3 line.long 0x0 "MCS5_CH0_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x20E0++0x17 line.long 0x0 "MCS5_CH0_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS5_CH0_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS5_CH0_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS5_CH0_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS5_CH0_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS5_CH0_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2100++0x27 line.long 0x0 "MCS5_CH1_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS5_CH1_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS5_CH1_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS5_CH1_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS5_CH1_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS5_CH1_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS5_CH1_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS5_CH1_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS5_CH1_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS5_CH1_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x213C++0x3 line.long 0x0 "MCS5_CH1_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x21E0++0x17 line.long 0x0 "MCS5_CH1_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS5_CH1_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS5_CH1_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS5_CH1_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS5_CH1_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS5_CH1_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2200++0x27 line.long 0x0 "MCS5_CH2_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS5_CH2_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS5_CH2_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS5_CH2_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS5_CH2_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS5_CH2_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS5_CH2_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS5_CH2_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS5_CH2_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS5_CH2_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x223C++0x3 line.long 0x0 "MCS5_CH2_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x22E0++0x17 line.long 0x0 "MCS5_CH2_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS5_CH2_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS5_CH2_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS5_CH2_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS5_CH2_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS5_CH2_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2300++0x27 line.long 0x0 "MCS5_CH3_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS5_CH3_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS5_CH3_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS5_CH3_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS5_CH3_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS5_CH3_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS5_CH3_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS5_CH3_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS5_CH3_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS5_CH3_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x233C++0x3 line.long 0x0 "MCS5_CH3_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x23E0++0x17 line.long 0x0 "MCS5_CH3_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS5_CH3_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS5_CH3_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS5_CH3_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS5_CH3_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS5_CH3_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2400++0x27 line.long 0x0 "MCS5_CH4_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS5_CH4_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS5_CH4_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS5_CH4_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS5_CH4_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS5_CH4_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS5_CH4_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS5_CH4_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS5_CH4_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS5_CH4_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x243C++0x3 line.long 0x0 "MCS5_CH4_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x24E0++0x17 line.long 0x0 "MCS5_CH4_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS5_CH4_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS5_CH4_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS5_CH4_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS5_CH4_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS5_CH4_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2500++0x27 line.long 0x0 "MCS5_CH5_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS5_CH5_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS5_CH5_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS5_CH5_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS5_CH5_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS5_CH5_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS5_CH5_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS5_CH5_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS5_CH5_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS5_CH5_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x253C++0x3 line.long 0x0 "MCS5_CH5_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x25E0++0x17 line.long 0x0 "MCS5_CH5_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS5_CH5_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS5_CH5_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS5_CH5_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS5_CH5_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS5_CH5_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2600++0x27 line.long 0x0 "MCS5_CH6_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS5_CH6_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS5_CH6_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS5_CH6_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS5_CH6_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS5_CH6_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS5_CH6_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS5_CH6_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS5_CH6_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS5_CH6_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x263C++0x3 line.long 0x0 "MCS5_CH6_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x26E0++0x17 line.long 0x0 "MCS5_CH6_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS5_CH6_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS5_CH6_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS5_CH6_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS5_CH6_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS5_CH6_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2700++0x27 line.long 0x0 "MCS5_CH7_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS5_CH7_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS5_CH7_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS5_CH7_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS5_CH7_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS5_CH7_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS5_CH7_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS5_CH7_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS5_CH7_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS5_CH7_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x273C++0x3 line.long 0x0 "MCS5_CH7_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x27E0++0x17 line.long 0x0 "MCS5_CH7_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS5_CH7_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS5_CH7_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS5_CH7_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS5_CH7_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS5_CH7_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2E28++0x7 line.long 0x0 "MCS5_CTRG," bitfld.long 0x0 23. "TRG23,Trigger bit o." "0,1" newline bitfld.long 0x0 22. "TRG22,Trigger bit o." "0,1" newline bitfld.long 0x0 21. "TRG21,Trigger bit o." "0,1" newline bitfld.long 0x0 20. "TRG20,Trigger bit o." "0,1" newline bitfld.long 0x0 19. "TRG19,Trigger bit o." "0,1" newline bitfld.long 0x0 18. "TRG18,Trigger bit o." "0,1" newline bitfld.long 0x0 17. "TRG17,Trigger bit o." "0,1" newline bitfld.long 0x0 16. "TRG16,Trigger bit o." "0,1" newline bitfld.long 0x0 15. "TRG15,Trigger bit n." "0,1" newline bitfld.long 0x0 14. "TRG14,Trigger bit n." "0,1" newline bitfld.long 0x0 13. "TRG13,Trigger bit n." "0,1" newline bitfld.long 0x0 12. "TRG12,Trigger bit n." "0,1" newline bitfld.long 0x0 11. "TRG11,Trigger bit n." "0,1" newline bitfld.long 0x0 10. "TRG10,Trigger bit n." "0,1" newline bitfld.long 0x0 9. "TRG9,Trigger bit n." "0,1" newline bitfld.long 0x0 8. "TRG8,Trigger bit n." "0,1" newline bitfld.long 0x0 7. "TRG7,Trigger bit m." "0,1" newline bitfld.long 0x0 6. "TRG6,Trigger bit m." "0,1" newline bitfld.long 0x0 5. "TRG5,Trigger bit m." "0,1" newline bitfld.long 0x0 4. "TRG4,Trigger bit m." "0,1" newline bitfld.long 0x0 3. "TRG3,Trigger bit m." "0,1" newline bitfld.long 0x0 2. "TRG2,Trigger bit m." "0,1" newline bitfld.long 0x0 1. "TRG1,Trigger bit m." "0,1" newline bitfld.long 0x0 0. "TRG0,Trigger bit m." "0,1" line.long 0x4 "MCS5_STRG," bitfld.long 0x4 23. "TRG23,Trigger bit k." "0,1" newline bitfld.long 0x4 22. "TRG22,Trigger bit k." "0,1" newline bitfld.long 0x4 21. "TRG21,Trigger bit k." "0,1" newline bitfld.long 0x4 20. "TRG20,Trigger bit k." "0,1" newline bitfld.long 0x4 19. "TRG19,Trigger bit k." "0,1" newline bitfld.long 0x4 18. "TRG18,Trigger bit k." "0,1" newline bitfld.long 0x4 17. "TRG17,Trigger bit k." "0,1" newline bitfld.long 0x4 16. "TRG16,Trigger bit k." "0,1" newline bitfld.long 0x4 15. "TRG15,Trigger bit k." "0,1" newline bitfld.long 0x4 14. "TRG14,Trigger bit k." "0,1" newline bitfld.long 0x4 13. "TRG13,Trigger bit k." "0,1" newline bitfld.long 0x4 12. "TRG12,Trigger bit k." "0,1" newline bitfld.long 0x4 11. "TRG11,Trigger bit k." "0,1" newline bitfld.long 0x4 10. "TRG10,Trigger bit k." "0,1" newline bitfld.long 0x4 9. "TRG9,Trigger bit k." "0,1" newline bitfld.long 0x4 8. "TRG8,Trigger bit k." "0,1" newline bitfld.long 0x4 7. "TRG7,Trigger bit k." "0,1" newline bitfld.long 0x4 6. "TRG6,Trigger bit k." "0,1" newline bitfld.long 0x4 5. "TRG5,Trigger bit k." "0,1" newline bitfld.long 0x4 4. "TRG4,Trigger bit k." "0,1" newline bitfld.long 0x4 3. "TRG3,Trigger bit k." "0,1" newline bitfld.long 0x4 2. "TRG2,Trigger bit k." "0,1" newline bitfld.long 0x4 1. "TRG1,Trigger bit k." "0,1" newline bitfld.long 0x4 0. "TRG0,Trigger bit k." "0,1" group.long 0x2F00++0x13 line.long 0x0 "MCS5_CTRL_STAT," bitfld.long 0x0 26. "HLT_AEIM_ERR,Halt on AEI bus master error." "0,1" newline bitfld.long 0x0 25. "EN_HVD,Enable Modified Harvard architecture." "0,1" newline bitfld.long 0x0 24. "EN_TIM_FOUT,Enable routing of TIM[i]_CH[x]_F_OUT signal." "0,1" newline bitfld.long 0x0 20.--22. "ERR_SRC_ID,Error source identifier." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "RAM_RST,RAM reset bit." "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "SCD_CH,Channel selection for scheduling algorithm." newline bitfld.long 0x0 0.--1. "SCD_MODE,Select MCS scheduling mode" "0,1,2,3" line.long 0x4 "MCS5_RESET," bitfld.long 0x4 7. "RST7,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 6. "RST6,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 5. "RST5,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 4. "RST4,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 3. "RST3,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 2. "RST2,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 1. "RST1,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 0. "RST0,Software reset of channel [k]" "0,1" line.long 0x8 "MCS5_CAT," bitfld.long 0x8 7. "CAT7,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 6. "CAT6,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 5. "CAT5,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 4. "CAT4,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 3. "CAT3,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 2. "CAT2,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 1. "CAT1,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 0. "CAT0,Cancel ARU transfer of channel [k]." "0,1" line.long 0xC "MCS5_CWT," bitfld.long 0xC 7. "CWT7,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 6. "CWT6,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 5. "CWT5,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 4. "CWT4,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 3. "CWT3,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 2. "CWT2,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 1. "CWT1,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 0. "CWT0,Cancel waiting instruction for channel [k]." "0,1" line.long 0x10 "MCS5_ERR," bitfld.long 0x10 7. "ERR7,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 6. "ERR6,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 5. "ERR5,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 4. "ERR4,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 3. "ERR3,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 2. "ERR2,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 1. "ERR1,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 0. "ERR0,Error State of MCS-channel [k]." "0,1" group.long 0x2F1C++0x13 line.long 0x0 "MCS5_REG_PROT," bitfld.long 0x0 14.--15. "WPROT7,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 12.--13. "WPROT6,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 10.--11. "WPROT5,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 8.--9. "WPROT4,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 6.--7. "WPROT3,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 4.--5. "WPROT2,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 2.--3. "WPROT1,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 0.--1. "WPROT0,Register Write Protection of MCS-channel k." "0,1,2,3" line.long 0x4 "MCS5_SINT_IRQ_NOTIFY," bitfld.long 0x4 7. "S_IRQ7,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 6. "S_IRQ6,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 5. "S_IRQ5,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 4. "S_IRQ4,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 3. "S_IRQ3,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 2. "S_IRQ2,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 1. "S_IRQ1,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 0. "S_IRQ0,Shared interrupt [k] notify flag." "0,1" line.long 0x8 "MCS5_SINT_IRQ_EN," bitfld.long 0x8 7. "S_IRQ7_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 6. "S_IRQ6_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 5. "S_IRQ5_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 4. "S_IRQ4_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 3. "S_IRQ3_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 2. "S_IRQ2_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 1. "S_IRQ1_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 0. "S_IRQ0_EN,Shared interrupt [k]" "0,1" line.long 0xC "MCS5_SINT_IRQ_FORCINT," bitfld.long 0xC 7. "TRG_S_IRQ7,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 6. "TRG_S_IRQ6,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 5. "TRG_S_IRQ5,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 4. "TRG_S_IRQ4,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 3. "TRG_S_IRQ3,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 2. "TRG_S_IRQ2,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 1. "TRG_S_IRQ1,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 0. "TRG_S_IRQ0,Trigger IRQ [k] in shared interrupt register" "0,1" line.long 0x10 "MCS5_SINT_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x2F40++0x1B line.long 0x0 "MCS5_HBP0_CTRL," bitfld.long 0x0 17. "NOT,Logical negation of h-th hardware break point." "0,1" newline bitfld.long 0x0 16. "AND,Logical AND conjunction of h-th hardware break point." "0,1" newline bitfld.long 0x0 12.--14. "TYPE,Define type of h-th hardware break point." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--9. "SCOPE,Define scope of h-th hardware break point." "0,1,2,3" newline bitfld.long 0x0 7. "EN_CH7,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 6. "EN_CH6,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 5. "EN_CH5,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 4. "EN_CH4,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 3. "EN_CH3,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 2. "EN_CH2,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 1. "EN_CH1,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 0. "EN_CH0,Enable h-th hardware break point for channel x." "0,1" line.long 0x4 "MCS5_HBP0_PATTERN," hexmask.long 0x4 0.--31. 1. "DATA,Define pattern or address of h-th hardware break point." line.long 0x8 "MCS5_HBP0_STATUS," bitfld.long 0x8 7. "HALT_CH7,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 6. "HALT_CH6,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 5. "HALT_CH5,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 4. "HALT_CH4,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 3. "HALT_CH3,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 2. "HALT_CH2,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 1. "HALT_CH1,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 0. "HALT_CH0,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" line.long 0xC "MCS5_HBP0_IRQ_NOTIFY," bitfld.long 0xC 0. "HBP_IRQ,Interrupt notify flag of the h-th hardware break point." "0,1" line.long 0x10 "MCS5_HBP0_IRQ_EN," bitfld.long 0x10 0. "HBP_IRQ_EN,Interrupt Enable bit of the h-th hardware break point." "0,1" line.long 0x14 "MCS5_HBP0_IRQ_FORCINT," bitfld.long 0x14 0. "TRG_HBP_IRQ,Trigger IRQ of the h-th hardware break point." "0,1" line.long 0x18 "MCS5_HBP0_IRQ_MODE," bitfld.long 0x18 0.--1. "IRQ_MODE,IRQ mode selection for all break point interrupts." "0,1,2,3" group.long 0x2F60++0x1B line.long 0x0 "MCS5_HBP1_CTRL," bitfld.long 0x0 17. "NOT,Logical negation of h-th hardware break point." "0,1" newline bitfld.long 0x0 16. "AND,Logical AND conjunction of h-th hardware break point." "0,1" newline bitfld.long 0x0 12.--14. "TYPE,Define type of h-th hardware break point." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--9. "SCOPE,Define scope of h-th hardware break point." "0,1,2,3" newline bitfld.long 0x0 7. "EN_CH7,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 6. "EN_CH6,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 5. "EN_CH5,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 4. "EN_CH4,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 3. "EN_CH3,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 2. "EN_CH2,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 1. "EN_CH1,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 0. "EN_CH0,Enable h-th hardware break point for channel x." "0,1" line.long 0x4 "MCS5_HBP1_PATTERN," hexmask.long 0x4 0.--31. 1. "DATA,Define pattern or address of h-th hardware break point." line.long 0x8 "MCS5_HBP1_STATUS," bitfld.long 0x8 7. "HALT_CH7,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 6. "HALT_CH6,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 5. "HALT_CH5,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 4. "HALT_CH4,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 3. "HALT_CH3,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 2. "HALT_CH2,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 1. "HALT_CH1,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 0. "HALT_CH0,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" line.long 0xC "MCS5_HBP1_IRQ_NOTIFY," bitfld.long 0xC 0. "HBP_IRQ,Interrupt notify flag of the h-th hardware break point." "0,1" line.long 0x10 "MCS5_HBP1_IRQ_EN," bitfld.long 0x10 0. "HBP_IRQ_EN,Interrupt Enable bit of the h-th hardware break point." "0,1" line.long 0x14 "MCS5_HBP1_IRQ_FORCINT," bitfld.long 0x14 0. "TRG_HBP_IRQ,Trigger IRQ of the h-th hardware break point." "0,1" line.long 0x18 "MCS5_HBP1_IRQ_MODE," bitfld.long 0x18 0.--1. "IRQ_MODE,IRQ mode selection for all break point interrupts." "0,1,2,3" group.long 0x4000++0x4F line.long 0x0 "CCM5_ARP0_CTRL," bitfld.long 0x0 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x0 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x0 0.--15. 1. "ADDR,ARP base address." line.long 0x4 "CCM5_ARP0_PROT," bitfld.long 0x4 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x8 "CCM5_ARP1_CTRL," bitfld.long 0x8 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x8 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x8 0.--15. 1. "ADDR,ARP base address." line.long 0xC "CCM5_ARP1_PROT," bitfld.long 0xC 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x10 "CCM5_ARP2_CTRL," bitfld.long 0x10 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x10 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x10 0.--15. 1. "ADDR,ARP base address." line.long 0x14 "CCM5_ARP2_PROT," bitfld.long 0x14 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x18 "CCM5_ARP3_CTRL," bitfld.long 0x18 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x18 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x18 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x18 0.--15. 1. "ADDR,ARP base address." line.long 0x1C "CCM5_ARP3_PROT," bitfld.long 0x1C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x20 "CCM5_ARP4_CTRL," bitfld.long 0x20 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x20 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x20 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x20 0.--15. 1. "ADDR,ARP base address." line.long 0x24 "CCM5_ARP4_PROT," bitfld.long 0x24 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x28 "CCM5_ARP5_CTRL," bitfld.long 0x28 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x28 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x28 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x28 0.--15. 1. "ADDR,ARP base address." line.long 0x2C "CCM5_ARP5_PROT," bitfld.long 0x2C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x30 "CCM5_ARP6_CTRL," bitfld.long 0x30 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x30 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x30 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x30 0.--15. 1. "ADDR,ARP base address." line.long 0x34 "CCM5_ARP6_PROT," bitfld.long 0x34 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x38 "CCM5_ARP7_CTRL," bitfld.long 0x38 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x38 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x38 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x38 0.--15. 1. "ADDR,ARP base address." line.long 0x3C "CCM5_ARP7_PROT," bitfld.long 0x3C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x40 "CCM5_ARP8_CTRL," bitfld.long 0x40 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x40 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x40 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x40 0.--15. 1. "ADDR,ARP base address." line.long 0x44 "CCM5_ARP8_PROT," bitfld.long 0x44 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x48 "CCM5_ARP9_CTRL," bitfld.long 0x48 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x48 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x48 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x48 0.--15. 1. "ADDR,ARP base address." line.long 0x4C "CCM5_ARP9_PROT," bitfld.long 0x4C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 0. "WPROT0,Write Protection MCS channel x." "0,1" group.long 0x41D4++0x13 line.long 0x0 "CCM5_HW_CONF2," bitfld.long 0x0 18. "AXIM_DATA_SIZE,Defines the data bus width of the AXI master interface" "0,1" newline bitfld.long 0x0 16. "AXIS_DATA_SIZE,Defines the data bus width of the AXI slave interface" "0,1" newline bitfld.long 0x0 9. "TIO_OUT_RST,TIO_OUT reset level" "0,1" newline bitfld.long 0x0 7. "AXIM_POSTED_WRITE,Write transaction without response" "0,1" newline bitfld.long 0x0 6. "AXIM_SEC_ACC,Secure AXI master access constant" "0,1" newline bitfld.long 0x0 5. "AXIM_PRIV_ACC,Privileged AXI master access constant" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "AXIM_ID_WIDTH,Defines which LSB of AXIM_ID are send to the bus" line.long 0x4 "CCM5_AEIM_STA," bitfld.long 0x4 24.--25. "AEIM_XPT_STA,AEIM Exception status." "0,1,2,3" newline hexmask.long.word 0x4 0.--15. 1. "AEIM_XPT_ADDR,Exception Address." line.long 0x8 "CCM5_HW_CONF," bitfld.long 0x8 31. "AEI_RDATA_PIPELINE_STAGE,Read data pipeline stage implemented" "0,1" newline bitfld.long 0x8 30. "AEI_ADDR_PIPELINE_STAGE,Address pipeline stage implemented" "0,1" newline bitfld.long 0x8 29. "INT_CLK_EN_GEN,Internal clock enable generation" "0,1" newline hexmask.long.byte 0x8 24.--28. 1. "TOM_TRIG_INTCHAIN,TOM internal trigger chain length without synchronization register" newline hexmask.long.byte 0x8 20.--23. 1. "ATOM_TRIG_INTCHAIN,ATOM internal trigger chain length without synchronization register" newline bitfld.long 0x8 19. "IRQ_MODE_SINGLE_PULSE,Signalize availability of Single Pulse IRQ mode" "0,1" newline bitfld.long 0x8 18. "IRQ_MODE_PULSE_NOTIFY,Signalize availability of Pulse Notoify IRQ mode" "0,1" newline bitfld.long 0x8 17. "IRQ_MODE_PULSE,Signalize availability of Pulse IRQ mode" "0,1" newline bitfld.long 0x8 16. "IRQ_MODE_LEVEL,Signalize availability of Level IRQ mode" "0,1" newline bitfld.long 0x8 15. "RESET_ACTIVE,Active level of asynchronous reset" "0,1" newline bitfld.long 0x8 13. "ERM,Enable RAM1 MSB for available MCS modules" "0,1" newline bitfld.long 0x8 12. "RAM_INIT_RST,RAM initialization from reset" "0,1" newline bitfld.long 0x8 9.--11. "TOM_TRIG_CHAIN,TOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "TOM_OUT_RST,TOM_OUT reset level" "0,1" newline bitfld.long 0x8 5.--7. "ATOM_TRIG_CHAIN,ATOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "ATOM_OUT_RST,ATOM_OUT reset level" "0,1" newline bitfld.long 0x8 3. "CFG_CLOCK_RATE,Clocks per ARU transfer" "0,1" newline bitfld.long 0x8 2. "SYNC_INPUT_REG,Additional pipelined stage in synchronous bridge mode" "0,1" newline bitfld.long 0x8 1. "BRIDGE_MODE_RST,Bridge mode after reset" "0,1" newline bitfld.long 0x8 0. "GRSTEN,Global Reset Enable" "0,1" line.long 0xC "CCM5_TIM_AUX_IN_SRC," bitfld.long 0xC 23. "SEL_OUT_N_CH7,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 22. "SEL_OUT_N_CH6,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 21. "SEL_OUT_N_CH5,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 20. "SEL_OUT_N_CH4,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 19. "SEL_OUT_N_CH3,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 18. "SEL_OUT_N_CH2,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 17. "SEL_OUT_N_CH1,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 16. "SEL_OUT_N_CH0,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 7. "SRC_CH7,Defines AUX_IN source of TIM[i] channel 7" "0,1" newline bitfld.long 0xC 6. "SRC_CH6,Defines AUX_IN source of TIM[i] channel 6" "0,1" newline bitfld.long 0xC 5. "SRC_CH5,Defines AUX_IN source of TIM[i] channel 5" "0,1" newline bitfld.long 0xC 4. "SRC_CH4,Defines AUX_IN source of TIM[i] channel 4" "0,1" newline bitfld.long 0xC 3. "SRC_CH3,Defines AUX_IN source of TIM[i] channel 3" "0,1" newline bitfld.long 0xC 2. "SRC_CH2,Defines AUX_IN source of TIM[i] channel 2" "0,1" newline bitfld.long 0xC 1. "SRC_CH1,Defines AUX_IN source of TIM[i] channel 1" "0,1" newline bitfld.long 0xC 0. "SRC_CH0,Defines AUX_IN source of TIM[i] channel 0" "0,1" line.long 0x10 "CCM5_EXT_CAP_EN," bitfld.long 0x10 15. "TIM_IP1_EXT_CAP_EN7,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 14. "TIM_IP1_EXT_CAP_EN6,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 13. "TIM_IP1_EXT_CAP_EN5,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 12. "TIM_IP1_EXT_CAP_EN4,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 11. "TIM_IP1_EXT_CAP_EN3,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 10. "TIM_IP1_EXT_CAP_EN2,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 9. "TIM_IP1_EXT_CAP_EN1,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 8. "TIM_IP1_EXT_CAP_EN0,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 7. "TIM_I_EXT_CAP_EN7,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 6. "TIM_I_EXT_CAP_EN6,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 5. "TIM_I_EXT_CAP_EN5,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 4. "TIM_I_EXT_CAP_EN4,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 3. "TIM_I_EXT_CAP_EN3,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 2. "TIM_I_EXT_CAP_EN2,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 1. "TIM_I_EXT_CAP_EN1,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 0. "TIM_I_EXT_CAP_EN0,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" group.long 0x41EC++0x7 line.long 0x0 "CCM5_ATOM_OUT," bitfld.long 0x0 31. "ATOM_IP1_OUT_N7,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 30. "ATOM_IP1_OUT_N6,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 29. "ATOM_IP1_OUT_N5,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 28. "ATOM_IP1_OUT_N4,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 27. "ATOM_IP1_OUT_N3,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 26. "ATOM_IP1_OUT_N2,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 25. "ATOM_IP1_OUT_N1,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 24. "ATOM_IP1_OUT_N0,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 23. "ATOM_IP1_OUT7,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 22. "ATOM_IP1_OUT6,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 21. "ATOM_IP1_OUT5,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 20. "ATOM_IP1_OUT4,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 19. "ATOM_IP1_OUT3,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 18. "ATOM_IP1_OUT2,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 17. "ATOM_IP1_OUT1,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 16. "ATOM_IP1_OUT0,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 15. "ATOM_I_OUT_N7,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 14. "ATOM_I_OUT_N6,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 13. "ATOM_I_OUT_N5,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 12. "ATOM_I_OUT_N4,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 11. "ATOM_I_OUT_N3,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 10. "ATOM_I_OUT_N2,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 9. "ATOM_I_OUT_N1,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 8. "ATOM_I_OUT_N0,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 7. "ATOM_I_OUT7,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 6. "ATOM_I_OUT6,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 5. "ATOM_I_OUT5,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 4. "ATOM_I_OUT4,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 3. "ATOM_I_OUT3,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 2. "ATOM_I_OUT2,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 1. "ATOM_I_OUT1,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 0. "ATOM_I_OUT0,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" line.long 0x4 "CCM5_CMU_CLK_CFG," bitfld.long 0x4 28.--29. "CLK7_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 24.--25. "CLK6_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 20.--21. "CLK5_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 16.--17. "CLK4_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 12.--13. "CLK3_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 8.--9. "CLK2_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 4.--5. "CLK1_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 0.--1. "CLK0_SRC,Clock y source signal selector" "0,1,2,3" group.long 0x41F8++0x7 line.long 0x0 "CCM5_CFG," bitfld.long 0x0 31. "TBU_DIR2,DIR1 input signal of module TBU timebase [z]." "0,1" newline bitfld.long 0x0 30. "TBU_DIR1,DIR1 input signal of module TBU timebase [z]." "0,1" newline bitfld.long 0x0 16.--17. "CLS_CLK_DIV,Cluster Clock Divider." "0,1,2,3" newline bitfld.long 0x0 8. "EN_TIO_DTM,Enable TIO and connected DTM" "0,1" newline bitfld.long 0x0 7. "EN_CMP_MON,Enable CMP and MON" "0,1" newline bitfld.long 0x0 6. "EN_PSM,Enable PSM" "0,1" newline bitfld.long 0x0 5. "EN_BRC,Enable BRC" "0,1" newline bitfld.long 0x0 4. "EN_DPLL_MAP,Enable DPLL and MAP" "0,1" newline bitfld.long 0x0 3. "EN_MCS,Enable MCS" "0,1" newline bitfld.long 0x0 2. "EN_ATOM_ADTM,Enable ATOM and ADTM" "0,1" newline bitfld.long 0x0 1. "EN_TOM_SPE_TDTM,Enable TOM SPE and TDTM" "0,1" newline bitfld.long 0x0 0. "EN_TIM,Enable TIM" "0,1" line.long 0x4 "CCM5_PROT," bitfld.long 0x4 0. "CLS_PROT,Cluster Protection" "0,1" group.long 0x4500++0x7F line.long 0x0 "CDTM5_DTM4_CTRL," bitfld.long 0x0 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x0 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x0 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x0 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x0 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x4 "CDTM5_DTM4_CH_CTRL1," bitfld.long 0x4 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x4 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x4 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x4 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x4 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x4 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x4 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x4 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x4 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x4 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x4 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x4 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x4 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x4 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x4 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x4 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x4 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x8 "CDTM5_DTM4_CH_CTRL2," bitfld.long 0x8 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x8 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x8 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x8 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x8 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x8 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x8 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x8 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x8 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x8 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x8 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x8 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x8 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x8 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x8 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x8 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x8 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x8 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x8 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x8 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x8 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x8 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x8 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x8 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x8 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x8 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x8 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x8 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x8 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x8 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x8 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x8 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0xC "CDTM5_DTM4_CH_CTRL2_SR," bitfld.long 0xC 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x10 "CDTM5_DTM4_PS_CTRL," bitfld.long 0x10 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x10 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x10 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x10 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x10 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x14 "CDTM5_DTM4_CH0_DTV," bitfld.long 0x14 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x14 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x14 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x18 "CDTM5_DTM4_CH1_DTV," bitfld.long 0x18 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x18 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x18 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x1C "CDTM5_DTM4_CH2_DTV," bitfld.long 0x1C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x1C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x1C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x20 "CDTM5_DTM4_CH3_DTV," bitfld.long 0x20 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x20 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x20 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x24 "CDTM5_DTM4_CH_SR," bitfld.long 0x24 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x24 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x24 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x24 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x24 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x24 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x24 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x24 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x28 "CDTM5_DTM4_CH_CTRL3," bitfld.long 0x28 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x28 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x28 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x28 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x28 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x28 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x28 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x28 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x2C "CDTM5_DTM4_CTRL2," bitfld.long 0x2C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x2C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x2C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x2C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x2C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x2C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x2C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x2C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x2C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x2C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x2C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x2C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x2C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x2C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x2C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x2C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x2C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x2C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x2C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x2C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x30 "CDTM5_DTM4_CH0_DTV_SR," bitfld.long 0x30 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x30 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x30 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x30 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x30 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x30 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x34 "CDTM5_DTM4_CH1_DTV_SR," bitfld.long 0x34 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x34 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x34 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x34 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x34 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x34 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x38 "CDTM5_DTM4_CH2_DTV_SR," bitfld.long 0x38 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x38 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x38 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x38 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x38 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x38 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x3C "CDTM5_DTM4_CH3_DTV_SR," bitfld.long 0x3C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x3C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x3C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x3C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x3C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x3C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x40 "CDTM5_DTM5_CTRL," bitfld.long 0x40 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x40 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x40 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x40 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x40 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x44 "CDTM5_DTM5_CH_CTRL1," bitfld.long 0x44 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x44 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x44 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x44 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x44 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x44 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x44 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x44 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x44 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x44 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x44 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x44 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x44 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x44 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x44 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x44 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x44 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x48 "CDTM5_DTM5_CH_CTRL2," bitfld.long 0x48 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x48 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x48 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x48 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x48 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x48 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x48 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x48 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x48 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x48 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x48 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x48 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x48 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x48 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x48 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x48 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x48 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x48 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x48 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x48 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x48 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x48 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x48 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x48 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x48 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x48 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x48 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x48 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x48 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x48 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x48 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x48 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0x4C "CDTM5_DTM5_CH_CTRL2_SR," bitfld.long 0x4C 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x50 "CDTM5_DTM5_PS_CTRL," bitfld.long 0x50 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x50 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x50 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x50 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x50 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x54 "CDTM5_DTM5_CH0_DTV," bitfld.long 0x54 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x54 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x54 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x58 "CDTM5_DTM5_CH1_DTV," bitfld.long 0x58 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x58 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x58 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x5C "CDTM5_DTM5_CH2_DTV," bitfld.long 0x5C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x5C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x5C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x60 "CDTM5_DTM5_CH3_DTV," bitfld.long 0x60 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x60 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x60 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x64 "CDTM5_DTM5_CH_SR," bitfld.long 0x64 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x64 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x64 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x64 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x64 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x64 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x64 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x64 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x68 "CDTM5_DTM5_CH_CTRL3," bitfld.long 0x68 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x68 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x68 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x68 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x68 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x68 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x68 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x68 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x6C "CDTM5_DTM5_CTRL2," bitfld.long 0x6C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x6C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x6C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x6C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x6C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x6C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x6C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x6C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x6C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x6C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x6C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x6C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x6C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x6C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x6C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x6C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x6C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x6C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x6C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x6C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x70 "CDTM5_DTM5_CH0_DTV_SR," bitfld.long 0x70 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x70 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x70 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x70 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x70 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x70 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x74 "CDTM5_DTM5_CH1_DTV_SR," bitfld.long 0x74 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x74 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x74 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x74 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x74 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x74 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x78 "CDTM5_DTM5_CH2_DTV_SR," bitfld.long 0x78 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x78 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x78 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x78 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x78 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x78 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x7C "CDTM5_DTM5_CH3_DTV_SR," bitfld.long 0x7C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x7C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x7C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x7C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x7C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x7C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" group.long 0x5000++0xB line.long 0x0 "AXIM5_FREE," bitfld.long 0x0 3. "FREE3,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 2. "FREE2,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 1. "FREE1,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 0. "FREE0,This bit represents the allocation status of the slot [t]" "0,1" line.long 0x4 "AXIM5_REQUEST," hexmask.long.byte 0x4 24.--31. 1. "REQID,This bit field shows the new allocated slot as binary encoded index. If no slot could be allocated this bit field is read as all 1 (0xff)." newline bitfld.long 0x4 3. "REQ1HOT3,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 2. "REQ1HOT2,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 1. "REQ1HOT1,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 0. "REQ1HOT0,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" line.long 0x8 "AXIM5_RELEASE," bitfld.long 0x8 3. "RELREQ3,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 2. "RELREQ2,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 1. "RELREQ1,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 0. "RELREQ0,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" group.long 0x5020++0x3 line.long 0x0 "AXIM5_SLOT0_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5028++0x3 line.long 0x0 "AXIM5_SLOT0_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5030++0xB line.long 0x0 "AXIM5_SLOT0_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM5_SLOT0_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM5_SLOT0_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5040++0x3 line.long 0x0 "AXIM5_SLOT1_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5048++0x3 line.long 0x0 "AXIM5_SLOT1_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5050++0xB line.long 0x0 "AXIM5_SLOT1_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM5_SLOT1_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM5_SLOT1_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5060++0x3 line.long 0x0 "AXIM5_SLOT2_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5068++0x3 line.long 0x0 "AXIM5_SLOT2_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5070++0xB line.long 0x0 "AXIM5_SLOT2_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM5_SLOT2_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM5_SLOT2_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5080++0x3 line.long 0x0 "AXIM5_SLOT3_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5088++0x3 line.long 0x0 "AXIM5_SLOT3_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5090++0xB line.long 0x0 "AXIM5_SLOT3_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM5_SLOT3_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM5_SLOT3_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" repeat 16384. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10000)++0x3 line.long 0x0 "MCS5_MEM[$1]," hexmask.long 0x0 0.--31. 1. "DATA,MCS memory location." repeat.end tree.end tree "GTM_CLS6" base ad:0x740C0000 group.long 0x800++0x3F line.long 0x0 "TIM6_CH0_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM6_CH0_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM6_CH0_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM6_CH0_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM6_CH0_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM6_CH0_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM6_CH0_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM6_CH0_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM6_CH0_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM6_CH0_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM6_CH0_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM6_CH0_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM6_CH0_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM6_CH0_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM6_CH0_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM6_CH0_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x880++0x3F line.long 0x0 "TIM6_CH1_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM6_CH1_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM6_CH1_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM6_CH1_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM6_CH1_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM6_CH1_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM6_CH1_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM6_CH1_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM6_CH1_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM6_CH1_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM6_CH1_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM6_CH1_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM6_CH1_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM6_CH1_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM6_CH1_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM6_CH1_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x900++0x3F line.long 0x0 "TIM6_CH2_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM6_CH2_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM6_CH2_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM6_CH2_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM6_CH2_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM6_CH2_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM6_CH2_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM6_CH2_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM6_CH2_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM6_CH2_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM6_CH2_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM6_CH2_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM6_CH2_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM6_CH2_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM6_CH2_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM6_CH2_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x980++0x3F line.long 0x0 "TIM6_CH3_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM6_CH3_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM6_CH3_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM6_CH3_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM6_CH3_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM6_CH3_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM6_CH3_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM6_CH3_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM6_CH3_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM6_CH3_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM6_CH3_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM6_CH3_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM6_CH3_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM6_CH3_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM6_CH3_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM6_CH3_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xA00++0x3F line.long 0x0 "TIM6_CH4_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM6_CH4_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM6_CH4_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM6_CH4_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM6_CH4_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM6_CH4_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM6_CH4_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM6_CH4_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM6_CH4_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM6_CH4_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM6_CH4_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM6_CH4_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM6_CH4_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM6_CH4_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM6_CH4_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM6_CH4_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xA80++0x3F line.long 0x0 "TIM6_CH5_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM6_CH5_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM6_CH5_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM6_CH5_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM6_CH5_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM6_CH5_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM6_CH5_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM6_CH5_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM6_CH5_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM6_CH5_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM6_CH5_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM6_CH5_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM6_CH5_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM6_CH5_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM6_CH5_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM6_CH5_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xB00++0x3F line.long 0x0 "TIM6_CH6_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM6_CH6_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM6_CH6_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM6_CH6_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM6_CH6_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM6_CH6_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM6_CH6_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM6_CH6_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM6_CH6_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM6_CH6_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM6_CH6_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM6_CH6_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM6_CH6_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM6_CH6_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM6_CH6_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM6_CH6_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xB80++0x3F line.long 0x0 "TIM6_CH7_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM6_CH7_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM6_CH7_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM6_CH7_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM6_CH7_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." newline hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM6_CH7_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM6_CH7_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" newline bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM6_CH7_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM6_CH7_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM6_CH7_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" newline bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" newline bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" newline bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" newline bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" newline bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" newline bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" newline bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" newline bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" newline bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" newline bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM6_CH7_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" newline bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" newline bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" newline bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" newline bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM6_CH7_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" newline bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM6_CH7_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM6_CH7_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM6_CH7_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM6_CH7_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xC00++0xB line.long 0x0 "TIM6_INP_VAL," bitfld.long 0x0 23. "TIM_IN7,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 22. "TIM_IN6,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 21. "TIM_IN5,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 20. "TIM_IN4,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 19. "TIM_IN3,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 18. "TIM_IN2,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 17. "TIM_IN1,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 16. "TIM_IN0,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 15. "F_IN7,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 14. "F_IN6,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 13. "F_IN5,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 12. "F_IN4,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 11. "F_IN3,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 10. "F_IN2,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 9. "F_IN1,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 8. "F_IN0,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 7. "F_OUT7,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 6. "F_OUT6,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 5. "F_OUT5,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 4. "F_OUT4,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 3. "F_OUT3,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 2. "F_OUT2,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 1. "F_OUT1,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 0. "F_OUT0,Signal channel x after TIM FLT unit" "0,1" line.long 0x4 "TIM6_IN_SRC," bitfld.long 0x4 30.--31. "MODE_7,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 28.--29. "VAL_7,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 26.--27. "MODE_6,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 24.--25. "VAL_6,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 22.--23. "MODE_5,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 20.--21. "VAL_5,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 18.--19. "MODE_4,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 16.--17. "VAL_4,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 14.--15. "MODE_3,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 12.--13. "VAL_3,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 10.--11. "MODE_2,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 8.--9. "VAL_2,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 6.--7. "MODE_1,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 4.--5. "VAL_1,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 2.--3. "MODE_0,Input source to Channel x" "0,1,2,3" newline bitfld.long 0x4 0.--1. "VAL_0,Value to be fed to channel [x]" "0,1,2,3" line.long 0x8 "TIM6_RST," bitfld.long 0x8 7. "RST_CH7,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 6. "RST_CH6,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 5. "RST_CH5,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 4. "RST_CH4,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 3. "RST_CH3,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 2. "RST_CH2,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 1. "RST_CH1,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 0. "RST_CH0,Software reset of channel [x]" "0,1" group.long 0x1800++0x2F line.long 0x0 "ATOM6_CH0_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM6_CH0_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM6_CH0_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM6_CH0_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM6_CH0_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM6_CH0_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM6_CH0_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM6_CH0_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM6_CH0_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM6_CH0_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM6_CH0_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM6_CH0_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1834++0x3 line.long 0x0 "ATOM6_CH0_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1880++0x2F line.long 0x0 "ATOM6_CH1_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM6_CH1_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM6_CH1_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM6_CH1_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM6_CH1_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM6_CH1_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM6_CH1_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM6_CH1_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM6_CH1_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM6_CH1_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM6_CH1_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM6_CH1_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x18B4++0x3 line.long 0x0 "ATOM6_CH1_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1900++0x2F line.long 0x0 "ATOM6_CH2_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM6_CH2_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM6_CH2_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM6_CH2_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM6_CH2_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM6_CH2_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM6_CH2_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM6_CH2_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM6_CH2_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM6_CH2_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM6_CH2_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM6_CH2_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1934++0x3 line.long 0x0 "ATOM6_CH2_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1980++0x2F line.long 0x0 "ATOM6_CH3_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM6_CH3_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM6_CH3_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM6_CH3_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM6_CH3_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM6_CH3_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM6_CH3_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM6_CH3_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM6_CH3_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM6_CH3_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM6_CH3_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM6_CH3_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x19B4++0x3 line.long 0x0 "ATOM6_CH3_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A00++0x2F line.long 0x0 "ATOM6_CH4_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM6_CH4_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM6_CH4_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM6_CH4_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM6_CH4_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM6_CH4_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM6_CH4_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM6_CH4_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM6_CH4_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM6_CH4_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM6_CH4_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM6_CH4_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1A34++0x3 line.long 0x0 "ATOM6_CH4_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A80++0x2F line.long 0x0 "ATOM6_CH5_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM6_CH5_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM6_CH5_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM6_CH5_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM6_CH5_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM6_CH5_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM6_CH5_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM6_CH5_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM6_CH5_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM6_CH5_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM6_CH5_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM6_CH5_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1AB4++0x3 line.long 0x0 "ATOM6_CH5_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B00++0x2F line.long 0x0 "ATOM6_CH6_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM6_CH6_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM6_CH6_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM6_CH6_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM6_CH6_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM6_CH6_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM6_CH6_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM6_CH6_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM6_CH6_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM6_CH6_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM6_CH6_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM6_CH6_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1B34++0x3 line.long 0x0 "ATOM6_CH6_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B80++0x2F line.long 0x0 "ATOM6_CH7_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." newline hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM6_CH7_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" newline bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" newline bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" newline bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" newline bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" newline bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" newline bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" newline bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." newline bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" newline bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." newline bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" newline bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM6_CH7_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM6_CH7_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM6_CH7_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM6_CH7_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM6_CH7_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM6_CH7_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" newline hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" newline bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" newline hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM6_CH7_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" newline bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM6_CH7_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" newline bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM6_CH7_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" newline bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM6_CH7_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1BB4++0x3 line.long 0x0 "ATOM6_CH7_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" newline bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1C40++0x1F line.long 0x0 "ATOM6_AGC_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 28.--29. "UPEN_CTRL6,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 26.--27. "UPEN_CTRL5,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 24.--25. "UPEN_CTRL4,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 22.--23. "UPEN_CTRL3,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 20.--21. "UPEN_CTRL2,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 16.--17. "UPEN_CTRL0,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 15. "RST_CH7,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 14. "RST_CH6,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 13. "RST_CH5,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 12. "RST_CH4,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 10. "RST_CH2,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 9. "RST_CH1,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 8. "RST_CH0,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see AGC) to update the register ATOM[i]_AGC_ENDIS_STAT and ATOM[i]_AGC_OUTEN_STAT" "0,1" line.long 0x4 "ATOM6_AGC_ENDIS_CTRL," bitfld.long 0x4 14.--15. "ENDIS_CTRL7,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 12.--13. "ENDIS_CTRL6,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 10.--11. "ENDIS_CTRL5,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 8.--9. "ENDIS_CTRL4,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 6.--7. "ENDIS_CTRL3,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 4.--5. "ENDIS_CTRL2,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_CTRL1,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 0.--1. "ENDIS_CTRL0,ATOM channel [k] enable/disable update value." "0,1,2,3" line.long 0x8 "ATOM6_AGC_ENDIS_STAT," bitfld.long 0x8 14.--15. "ENDIS_STAT7,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 12.--13. "ENDIS_STAT6,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 10.--11. "ENDIS_STAT5,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 8.--9. "ENDIS_STAT4,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 6.--7. "ENDIS_STAT3,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 4.--5. "ENDIS_STAT2,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 2.--3. "ENDIS_STAT1,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 0.--1. "ENDIS_STAT0,ATOM channel [k] enable/disable" "0,1,2,3" line.long 0xC "ATOM6_AGC_ACT_TB," bitfld.long 0xC 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" newline bitfld.long 0xC 24. "TB_TRIG,Set trigger request" "0,1" newline hexmask.long.tbyte 0xC 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[x] x=0..2. If selected TBU_TS[x] value is in the interval [ATOM[i]_AGC_ACT_TB.ACT_TB-007FFFFFh ATOM[i]_AGC_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x10 "ATOM6_AGC_OUTEN_CTRL," bitfld.long 0x10 14.--15. "OUTEN_CTRL7,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 12.--13. "OUTEN_CTRL6,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 10.--11. "OUTEN_CTRL5,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 8.--9. "OUTEN_CTRL4,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 6.--7. "OUTEN_CTRL3,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 4.--5. "OUTEN_CTRL2,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 2.--3. "OUTEN_CTRL1,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 0.--1. "OUTEN_CTRL0,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" line.long 0x14 "ATOM6_AGC_OUTEN_STAT," bitfld.long 0x14 14.--15. "OUTEN_STAT7,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 12.--13. "OUTEN_STAT6,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 10.--11. "OUTEN_STAT5,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 8.--9. "OUTEN_STAT4,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 6.--7. "OUTEN_STAT3,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 4.--5. "OUTEN_STAT2,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 2.--3. "OUTEN_STAT1,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 0.--1. "OUTEN_STAT0,Control/status of output ATOM_OUT [k]" "0,1,2,3" line.long 0x18 "ATOM6_AGC_FUPD_CTRL," bitfld.long 0x18 30.--31. "RSTCN0_CH7,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 28.--29. "RSTCN0_CH6,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 26.--27. "RSTCN0_CH5,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 24.--25. "RSTCN0_CH4,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 22.--23. "RSTCN0_CH3,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 20.--21. "RSTCN0_CH2,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 18.--19. "RSTCN0_CH1,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 16.--17. "RSTCN0_CH0,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 14.--15. "FUPD_CTRL7,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 12.--13. "FUPD_CTRL6,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 10.--11. "FUPD_CTRL5,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 8.--9. "FUPD_CTRL4,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 6.--7. "FUPD_CTRL3,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 4.--5. "FUPD_CTRL2,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 2.--3. "FUPD_CTRL1,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 0.--1. "FUPD_CTRL0,Force update of ATOM channel [k] operation registers" "0,1,2,3" line.long 0x1C "ATOM6_AGC_INT_TRIG," bitfld.long 0x1C 14.--15. "INT_TRIG7,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 12.--13. "INT_TRIG6,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 10.--11. "INT_TRIG5,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 8.--9. "INT_TRIG4,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 6.--7. "INT_TRIG3,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 4.--5. "INT_TRIG2,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 2.--3. "INT_TRIG1,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "INT_TRIG0,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" group.long 0x2000++0x27 line.long 0x0 "MCS6_CH0_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS6_CH0_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS6_CH0_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS6_CH0_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS6_CH0_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS6_CH0_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS6_CH0_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS6_CH0_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS6_CH0_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS6_CH0_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x203C++0x3 line.long 0x0 "MCS6_CH0_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x20E0++0x17 line.long 0x0 "MCS6_CH0_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS6_CH0_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS6_CH0_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS6_CH0_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS6_CH0_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS6_CH0_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2100++0x27 line.long 0x0 "MCS6_CH1_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS6_CH1_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS6_CH1_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS6_CH1_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS6_CH1_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS6_CH1_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS6_CH1_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS6_CH1_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS6_CH1_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS6_CH1_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x213C++0x3 line.long 0x0 "MCS6_CH1_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x21E0++0x17 line.long 0x0 "MCS6_CH1_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS6_CH1_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS6_CH1_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS6_CH1_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS6_CH1_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS6_CH1_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2200++0x27 line.long 0x0 "MCS6_CH2_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS6_CH2_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS6_CH2_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS6_CH2_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS6_CH2_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS6_CH2_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS6_CH2_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS6_CH2_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS6_CH2_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS6_CH2_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x223C++0x3 line.long 0x0 "MCS6_CH2_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x22E0++0x17 line.long 0x0 "MCS6_CH2_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS6_CH2_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS6_CH2_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS6_CH2_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS6_CH2_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS6_CH2_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2300++0x27 line.long 0x0 "MCS6_CH3_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS6_CH3_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS6_CH3_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS6_CH3_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS6_CH3_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS6_CH3_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS6_CH3_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS6_CH3_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS6_CH3_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS6_CH3_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x233C++0x3 line.long 0x0 "MCS6_CH3_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x23E0++0x17 line.long 0x0 "MCS6_CH3_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS6_CH3_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS6_CH3_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS6_CH3_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS6_CH3_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS6_CH3_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2400++0x27 line.long 0x0 "MCS6_CH4_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS6_CH4_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS6_CH4_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS6_CH4_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS6_CH4_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS6_CH4_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS6_CH4_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS6_CH4_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS6_CH4_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS6_CH4_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x243C++0x3 line.long 0x0 "MCS6_CH4_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x24E0++0x17 line.long 0x0 "MCS6_CH4_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS6_CH4_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS6_CH4_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS6_CH4_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS6_CH4_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS6_CH4_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2500++0x27 line.long 0x0 "MCS6_CH5_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS6_CH5_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS6_CH5_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS6_CH5_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS6_CH5_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS6_CH5_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS6_CH5_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS6_CH5_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS6_CH5_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS6_CH5_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x253C++0x3 line.long 0x0 "MCS6_CH5_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x25E0++0x17 line.long 0x0 "MCS6_CH5_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS6_CH5_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS6_CH5_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS6_CH5_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS6_CH5_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS6_CH5_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2600++0x27 line.long 0x0 "MCS6_CH6_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS6_CH6_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS6_CH6_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS6_CH6_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS6_CH6_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS6_CH6_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS6_CH6_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS6_CH6_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS6_CH6_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS6_CH6_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x263C++0x3 line.long 0x0 "MCS6_CH6_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x26E0++0x17 line.long 0x0 "MCS6_CH6_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS6_CH6_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS6_CH6_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS6_CH6_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS6_CH6_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS6_CH6_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2700++0x27 line.long 0x0 "MCS6_CH7_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS6_CH7_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS6_CH7_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS6_CH7_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS6_CH7_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS6_CH7_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS6_CH7_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS6_CH7_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS6_CH7_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" newline bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" newline bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" newline bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" newline bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" newline bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS6_CH7_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" newline bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" newline bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x273C++0x3 line.long 0x0 "MCS6_CH7_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x27E0++0x17 line.long 0x0 "MCS6_CH7_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS6_CH7_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" newline bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS6_CH7_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" newline bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS6_CH7_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS6_CH7_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS6_CH7_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" newline bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2E28++0x7 line.long 0x0 "MCS6_CTRG," bitfld.long 0x0 23. "TRG23,Trigger bit o." "0,1" newline bitfld.long 0x0 22. "TRG22,Trigger bit o." "0,1" newline bitfld.long 0x0 21. "TRG21,Trigger bit o." "0,1" newline bitfld.long 0x0 20. "TRG20,Trigger bit o." "0,1" newline bitfld.long 0x0 19. "TRG19,Trigger bit o." "0,1" newline bitfld.long 0x0 18. "TRG18,Trigger bit o." "0,1" newline bitfld.long 0x0 17. "TRG17,Trigger bit o." "0,1" newline bitfld.long 0x0 16. "TRG16,Trigger bit o." "0,1" newline bitfld.long 0x0 15. "TRG15,Trigger bit n." "0,1" newline bitfld.long 0x0 14. "TRG14,Trigger bit n." "0,1" newline bitfld.long 0x0 13. "TRG13,Trigger bit n." "0,1" newline bitfld.long 0x0 12. "TRG12,Trigger bit n." "0,1" newline bitfld.long 0x0 11. "TRG11,Trigger bit n." "0,1" newline bitfld.long 0x0 10. "TRG10,Trigger bit n." "0,1" newline bitfld.long 0x0 9. "TRG9,Trigger bit n." "0,1" newline bitfld.long 0x0 8. "TRG8,Trigger bit n." "0,1" newline bitfld.long 0x0 7. "TRG7,Trigger bit m." "0,1" newline bitfld.long 0x0 6. "TRG6,Trigger bit m." "0,1" newline bitfld.long 0x0 5. "TRG5,Trigger bit m." "0,1" newline bitfld.long 0x0 4. "TRG4,Trigger bit m." "0,1" newline bitfld.long 0x0 3. "TRG3,Trigger bit m." "0,1" newline bitfld.long 0x0 2. "TRG2,Trigger bit m." "0,1" newline bitfld.long 0x0 1. "TRG1,Trigger bit m." "0,1" newline bitfld.long 0x0 0. "TRG0,Trigger bit m." "0,1" line.long 0x4 "MCS6_STRG," bitfld.long 0x4 23. "TRG23,Trigger bit k." "0,1" newline bitfld.long 0x4 22. "TRG22,Trigger bit k." "0,1" newline bitfld.long 0x4 21. "TRG21,Trigger bit k." "0,1" newline bitfld.long 0x4 20. "TRG20,Trigger bit k." "0,1" newline bitfld.long 0x4 19. "TRG19,Trigger bit k." "0,1" newline bitfld.long 0x4 18. "TRG18,Trigger bit k." "0,1" newline bitfld.long 0x4 17. "TRG17,Trigger bit k." "0,1" newline bitfld.long 0x4 16. "TRG16,Trigger bit k." "0,1" newline bitfld.long 0x4 15. "TRG15,Trigger bit k." "0,1" newline bitfld.long 0x4 14. "TRG14,Trigger bit k." "0,1" newline bitfld.long 0x4 13. "TRG13,Trigger bit k." "0,1" newline bitfld.long 0x4 12. "TRG12,Trigger bit k." "0,1" newline bitfld.long 0x4 11. "TRG11,Trigger bit k." "0,1" newline bitfld.long 0x4 10. "TRG10,Trigger bit k." "0,1" newline bitfld.long 0x4 9. "TRG9,Trigger bit k." "0,1" newline bitfld.long 0x4 8. "TRG8,Trigger bit k." "0,1" newline bitfld.long 0x4 7. "TRG7,Trigger bit k." "0,1" newline bitfld.long 0x4 6. "TRG6,Trigger bit k." "0,1" newline bitfld.long 0x4 5. "TRG5,Trigger bit k." "0,1" newline bitfld.long 0x4 4. "TRG4,Trigger bit k." "0,1" newline bitfld.long 0x4 3. "TRG3,Trigger bit k." "0,1" newline bitfld.long 0x4 2. "TRG2,Trigger bit k." "0,1" newline bitfld.long 0x4 1. "TRG1,Trigger bit k." "0,1" newline bitfld.long 0x4 0. "TRG0,Trigger bit k." "0,1" group.long 0x2F00++0x13 line.long 0x0 "MCS6_CTRL_STAT," bitfld.long 0x0 26. "HLT_AEIM_ERR,Halt on AEI bus master error." "0,1" newline bitfld.long 0x0 25. "EN_HVD,Enable Modified Harvard architecture." "0,1" newline bitfld.long 0x0 24. "EN_TIM_FOUT,Enable routing of TIM[i]_CH[x]_F_OUT signal." "0,1" newline bitfld.long 0x0 20.--22. "ERR_SRC_ID,Error source identifier." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "RAM_RST,RAM reset bit." "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "SCD_CH,Channel selection for scheduling algorithm." newline bitfld.long 0x0 0.--1. "SCD_MODE,Select MCS scheduling mode" "0,1,2,3" line.long 0x4 "MCS6_RESET," bitfld.long 0x4 7. "RST7,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 6. "RST6,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 5. "RST5,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 4. "RST4,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 3. "RST3,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 2. "RST2,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 1. "RST1,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 0. "RST0,Software reset of channel [k]" "0,1" line.long 0x8 "MCS6_CAT," bitfld.long 0x8 7. "CAT7,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 6. "CAT6,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 5. "CAT5,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 4. "CAT4,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 3. "CAT3,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 2. "CAT2,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 1. "CAT1,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 0. "CAT0,Cancel ARU transfer of channel [k]." "0,1" line.long 0xC "MCS6_CWT," bitfld.long 0xC 7. "CWT7,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 6. "CWT6,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 5. "CWT5,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 4. "CWT4,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 3. "CWT3,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 2. "CWT2,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 1. "CWT1,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 0. "CWT0,Cancel waiting instruction for channel [k]." "0,1" line.long 0x10 "MCS6_ERR," bitfld.long 0x10 7. "ERR7,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 6. "ERR6,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 5. "ERR5,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 4. "ERR4,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 3. "ERR3,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 2. "ERR2,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 1. "ERR1,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 0. "ERR0,Error State of MCS-channel [k]." "0,1" group.long 0x2F1C++0x13 line.long 0x0 "MCS6_REG_PROT," bitfld.long 0x0 14.--15. "WPROT7,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 12.--13. "WPROT6,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 10.--11. "WPROT5,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 8.--9. "WPROT4,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 6.--7. "WPROT3,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 4.--5. "WPROT2,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 2.--3. "WPROT1,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 0.--1. "WPROT0,Register Write Protection of MCS-channel k." "0,1,2,3" line.long 0x4 "MCS6_SINT_IRQ_NOTIFY," bitfld.long 0x4 7. "S_IRQ7,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 6. "S_IRQ6,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 5. "S_IRQ5,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 4. "S_IRQ4,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 3. "S_IRQ3,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 2. "S_IRQ2,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 1. "S_IRQ1,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 0. "S_IRQ0,Shared interrupt [k] notify flag." "0,1" line.long 0x8 "MCS6_SINT_IRQ_EN," bitfld.long 0x8 7. "S_IRQ7_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 6. "S_IRQ6_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 5. "S_IRQ5_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 4. "S_IRQ4_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 3. "S_IRQ3_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 2. "S_IRQ2_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 1. "S_IRQ1_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 0. "S_IRQ0_EN,Shared interrupt [k]" "0,1" line.long 0xC "MCS6_SINT_IRQ_FORCINT," bitfld.long 0xC 7. "TRG_S_IRQ7,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 6. "TRG_S_IRQ6,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 5. "TRG_S_IRQ5,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 4. "TRG_S_IRQ4,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 3. "TRG_S_IRQ3,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 2. "TRG_S_IRQ2,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 1. "TRG_S_IRQ1,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 0. "TRG_S_IRQ0,Trigger IRQ [k] in shared interrupt register" "0,1" line.long 0x10 "MCS6_SINT_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x2F40++0x1B line.long 0x0 "MCS6_HBP0_CTRL," bitfld.long 0x0 17. "NOT,Logical negation of h-th hardware break point." "0,1" newline bitfld.long 0x0 16. "AND,Logical AND conjunction of h-th hardware break point." "0,1" newline bitfld.long 0x0 12.--14. "TYPE,Define type of h-th hardware break point." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--9. "SCOPE,Define scope of h-th hardware break point." "0,1,2,3" newline bitfld.long 0x0 7. "EN_CH7,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 6. "EN_CH6,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 5. "EN_CH5,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 4. "EN_CH4,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 3. "EN_CH3,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 2. "EN_CH2,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 1. "EN_CH1,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 0. "EN_CH0,Enable h-th hardware break point for channel x." "0,1" line.long 0x4 "MCS6_HBP0_PATTERN," hexmask.long 0x4 0.--31. 1. "DATA,Define pattern or address of h-th hardware break point." line.long 0x8 "MCS6_HBP0_STATUS," bitfld.long 0x8 7. "HALT_CH7,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 6. "HALT_CH6,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 5. "HALT_CH5,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 4. "HALT_CH4,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 3. "HALT_CH3,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 2. "HALT_CH2,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 1. "HALT_CH1,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 0. "HALT_CH0,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" line.long 0xC "MCS6_HBP0_IRQ_NOTIFY," bitfld.long 0xC 0. "HBP_IRQ,Interrupt notify flag of the h-th hardware break point." "0,1" line.long 0x10 "MCS6_HBP0_IRQ_EN," bitfld.long 0x10 0. "HBP_IRQ_EN,Interrupt Enable bit of the h-th hardware break point." "0,1" line.long 0x14 "MCS6_HBP0_IRQ_FORCINT," bitfld.long 0x14 0. "TRG_HBP_IRQ,Trigger IRQ of the h-th hardware break point." "0,1" line.long 0x18 "MCS6_HBP0_IRQ_MODE," bitfld.long 0x18 0.--1. "IRQ_MODE,IRQ mode selection for all break point interrupts." "0,1,2,3" group.long 0x2F60++0x1B line.long 0x0 "MCS6_HBP1_CTRL," bitfld.long 0x0 17. "NOT,Logical negation of h-th hardware break point." "0,1" newline bitfld.long 0x0 16. "AND,Logical AND conjunction of h-th hardware break point." "0,1" newline bitfld.long 0x0 12.--14. "TYPE,Define type of h-th hardware break point." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--9. "SCOPE,Define scope of h-th hardware break point." "0,1,2,3" newline bitfld.long 0x0 7. "EN_CH7,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 6. "EN_CH6,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 5. "EN_CH5,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 4. "EN_CH4,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 3. "EN_CH3,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 2. "EN_CH2,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 1. "EN_CH1,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 0. "EN_CH0,Enable h-th hardware break point for channel x." "0,1" line.long 0x4 "MCS6_HBP1_PATTERN," hexmask.long 0x4 0.--31. 1. "DATA,Define pattern or address of h-th hardware break point." line.long 0x8 "MCS6_HBP1_STATUS," bitfld.long 0x8 7. "HALT_CH7,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 6. "HALT_CH6,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 5. "HALT_CH5,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 4. "HALT_CH4,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 3. "HALT_CH3,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 2. "HALT_CH2,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 1. "HALT_CH1,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 0. "HALT_CH0,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" line.long 0xC "MCS6_HBP1_IRQ_NOTIFY," bitfld.long 0xC 0. "HBP_IRQ,Interrupt notify flag of the h-th hardware break point." "0,1" line.long 0x10 "MCS6_HBP1_IRQ_EN," bitfld.long 0x10 0. "HBP_IRQ_EN,Interrupt Enable bit of the h-th hardware break point." "0,1" line.long 0x14 "MCS6_HBP1_IRQ_FORCINT," bitfld.long 0x14 0. "TRG_HBP_IRQ,Trigger IRQ of the h-th hardware break point." "0,1" line.long 0x18 "MCS6_HBP1_IRQ_MODE," bitfld.long 0x18 0.--1. "IRQ_MODE,IRQ mode selection for all break point interrupts." "0,1,2,3" group.long 0x3000++0x13 line.long 0x0 "TIO6_G0_CH0_CTRL," bitfld.long 0x0 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x0 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x0 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x0 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x0 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x0 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x0 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x0 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x0 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x0 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x0 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x0 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x0 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x0 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x0 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x0 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x0 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x0 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x0 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x0 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x0 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x4 "TIO6_G0_CH0_IRQ_NOTIFY," bitfld.long 0x4 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x4 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x4 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x4 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x4 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x4 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x8 "TIO6_G0_CH0_IRQ_EN," bitfld.long 0x8 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x8 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x8 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x8 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x8 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x8 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0xC "TIO6_G0_CH0_IRQ_FORCINT," bitfld.long 0xC 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0xC 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0xC 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0xC 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0xC 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0xC 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x10 "TIO6_G0_CH0_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3020++0xB line.long 0x0 "TIO6_G0_CH0_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO6_G0_CH0_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO6_G0_CH0_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3030++0x23 line.long 0x0 "TIO6_G0_CH0_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO6_G0_CH0_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO6_G0_CH0_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO6_G0_CH0_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO6_G0_CH1_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO6_G0_CH1_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO6_G0_CH1_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO6_G0_CH1_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO6_G0_CH1_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3060++0xB line.long 0x0 "TIO6_G0_CH1_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO6_G0_CH1_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO6_G0_CH1_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3070++0x23 line.long 0x0 "TIO6_G0_CH1_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO6_G0_CH1_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO6_G0_CH1_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO6_G0_CH1_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO6_G0_CH2_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO6_G0_CH2_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO6_G0_CH2_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO6_G0_CH2_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO6_G0_CH2_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x30A0++0xB line.long 0x0 "TIO6_G0_CH2_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO6_G0_CH2_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO6_G0_CH2_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x30B0++0x23 line.long 0x0 "TIO6_G0_CH2_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO6_G0_CH2_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO6_G0_CH2_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO6_G0_CH2_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO6_G0_CH3_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO6_G0_CH3_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO6_G0_CH3_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO6_G0_CH3_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO6_G0_CH3_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x30E0++0xB line.long 0x0 "TIO6_G0_CH3_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO6_G0_CH3_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO6_G0_CH3_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x30F0++0x23 line.long 0x0 "TIO6_G0_CH3_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO6_G0_CH3_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO6_G0_CH3_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO6_G0_CH3_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO6_G0_CH4_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO6_G0_CH4_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO6_G0_CH4_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO6_G0_CH4_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO6_G0_CH4_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3120++0xB line.long 0x0 "TIO6_G0_CH4_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO6_G0_CH4_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO6_G0_CH4_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3130++0x23 line.long 0x0 "TIO6_G0_CH4_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO6_G0_CH4_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO6_G0_CH4_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO6_G0_CH4_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO6_G0_CH5_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO6_G0_CH5_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO6_G0_CH5_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO6_G0_CH5_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO6_G0_CH5_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3160++0xB line.long 0x0 "TIO6_G0_CH5_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO6_G0_CH5_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO6_G0_CH5_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3170++0x23 line.long 0x0 "TIO6_G0_CH5_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO6_G0_CH5_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO6_G0_CH5_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO6_G0_CH5_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO6_G0_CH6_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO6_G0_CH6_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO6_G0_CH6_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO6_G0_CH6_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO6_G0_CH6_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x31A0++0xB line.long 0x0 "TIO6_G0_CH6_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO6_G0_CH6_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO6_G0_CH6_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x31B0++0x23 line.long 0x0 "TIO6_G0_CH6_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO6_G0_CH6_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO6_G0_CH6_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO6_G0_CH6_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO6_G0_CH7_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" newline bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" newline bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" newline bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" newline bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" newline bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" newline bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" newline bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" newline bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" newline bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO6_G0_CH7_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" newline bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" newline bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" newline bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO6_G0_CH7_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO6_G0_CH7_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" newline bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" newline bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" newline bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO6_G0_CH7_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x31E0++0xB line.long 0x0 "TIO6_G0_CH7_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO6_G0_CH7_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO6_G0_CH7_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x31F0++0x17 line.long 0x0 "TIO6_G0_CH7_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" newline hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO6_G0_CH7_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" newline bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO6_G0_CH7_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO6_G0_CH7_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO6_G0_ISEL0_CTRL1," bitfld.long 0x10 27. "WRITE_EN3,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 26. "WRITE_EN2,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 25. "WRITE_EN1,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 24. "WRITE_EN0,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 19. "OUT_SEL3,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x10 18. "OUT_SEL2,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x10 17. "OUT_SEL1,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x10 16. "OUT_SEL0,select signal for ISEL_OUT[k]" "0,1" newline hexmask.long.byte 0x10 12.--15. 1. "LUT2_3,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x10 8.--11. 1. "LUT2_2,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x10 4.--7. 1. "LUT2_1,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x10 0.--3. 1. "LUT2_0,2 bit Lookup table function for channel c=q*4+k" line.long 0x14 "TIO6_G0_ISEL0_CTRL2," bitfld.long 0x14 22. "LUT3IN_SEL2,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x14 21. "LUT3IN_SEL1,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x14 20. "LUT3IN_SEL0,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x14 16.--17. "QOUT_SEL,select source for ISEL_QOUT signal in quad = q" "0,1,2,3" newline hexmask.long.byte 0x14 0.--7. 1. "LUT3,3 bit Lookup table function for quad=q; channels q*4+2 .. q*4" group.long 0x3220++0x7 line.long 0x0 "TIO6_G0_ISEL1_CTRL1," bitfld.long 0x0 27. "WRITE_EN3,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 26. "WRITE_EN2,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 25. "WRITE_EN1,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 24. "WRITE_EN0,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 19. "OUT_SEL3,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x0 18. "OUT_SEL2,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x0 17. "OUT_SEL1,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x0 16. "OUT_SEL0,select signal for ISEL_OUT[k]" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "LUT2_3,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x0 8.--11. 1. "LUT2_2,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x0 4.--7. 1. "LUT2_1,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x0 0.--3. 1. "LUT2_0,2 bit Lookup table function for channel c=q*4+k" line.long 0x4 "TIO6_G0_ISEL1_CTRL2," bitfld.long 0x4 22. "LUT3IN_SEL2,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x4 21. "LUT3IN_SEL1,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x4 20. "LUT3IN_SEL0,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x4 16.--17. "QOUT_SEL,select source for ISEL_QOUT signal in quad = q" "0,1,2,3" newline hexmask.long.byte 0x4 0.--7. 1. "LUT3,3 bit Lookup table function for quad=q; channels q*4+2 .. q*4" group.long 0x3240++0x3 line.long 0x0 "TIO6_G0_OP_USAGE," bitfld.long 0x0 31. "WRITE_EN7,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 30. "WRITE_EN6,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 29. "WRITE_EN5,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 28. "WRITE_EN4,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 27. "WRITE_EN3,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 26. "WRITE_EN2,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 25. "WRITE_EN1,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 24. "WRITE_EN0,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 21.--23. "MODE7,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "MODE6,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15.--17. "MODE5,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "MODE4,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9.--11. "MODE3,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "MODE2,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "MODE1,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "MODE0,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" group.long 0x3C00++0x1F line.long 0x0 "TIO6_S," bitfld.long 0x0 7. "CH7,Value of channel x." "0,1" newline bitfld.long 0x0 6. "CH6,Value of channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Value of channel x." "0,1" newline bitfld.long 0x0 4. "CH4,Value of channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Value of channel x." "0,1" newline bitfld.long 0x0 2. "CH2,Value of channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Value of channel x." "0,1" newline bitfld.long 0x0 0. "CH0,Value of channel x." "0,1" line.long 0x4 "TIO6_O," bitfld.long 0x4 7. "CH7,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 6. "CH6,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 4. "CH4,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 2. "CH2,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 0. "CH0,Value driven on output of channel x." "0,1" line.long 0x8 "TIO6_ENDIS," bitfld.long 0x8 7. "CH7,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 6. "CH6,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 4. "CH4,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 2. "CH2,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 0. "CH0,Enable/Disable request of channel x." "0,1" line.long 0xC "TIO6_INVERT," bitfld.long 0xC 7. "CH7,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 6. "CH6,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 4. "CH4,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 2. "CH2,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 0. "CH0,Enable/Disable signal inversion of channel x." "0,1" line.long 0x10 "TIO6_INPUT_MODE," bitfld.long 0x10 7. "CH7,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 6. "CH6,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 4. "CH4,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 2. "CH2,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 0. "CH0,Enable/Disable input mode of channel x." "0,1" line.long 0x14 "TIO6_CYCLIC_MODE," bitfld.long 0x14 7. "CH7,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 6. "CH6,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 4. "CH4,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 2. "CH2,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 0. "CH0,Enable/Disable cyclic mode of channel x." "0,1" line.long 0x18 "TIO6_TRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 6. "CH6,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 4. "CH4,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 2. "CH2,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 0. "CH0,enable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO6_PLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 6. "CH6,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 4. "CH4,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 2. "CH2,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 0. "CH0,enable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3C40++0x1F line.long 0x0 "TIO6_CS," bitfld.long 0x0 7. "CH7,Clear channel x." "0,1" newline bitfld.long 0x0 6. "CH6,Clear channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Clear channel x." "0,1" newline bitfld.long 0x0 4. "CH4,Clear channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Clear channel x." "0,1" newline bitfld.long 0x0 2. "CH2,Clear channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Clear channel x." "0,1" newline bitfld.long 0x0 0. "CH0,Clear channel x." "0,1" line.long 0x4 "TIO6_CO," bitfld.long 0x4 7. "CH7,Clear channel x." "0,1" newline bitfld.long 0x4 6. "CH6,Clear channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Clear channel x." "0,1" newline bitfld.long 0x4 4. "CH4,Clear channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Clear channel x." "0,1" newline bitfld.long 0x4 2. "CH2,Clear channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Clear channel x." "0,1" newline bitfld.long 0x4 0. "CH0,Clear channel x." "0,1" line.long 0x8 "TIO6_CENDIS," bitfld.long 0x8 7. "CH7,Disable request of channel x." "0,1" newline bitfld.long 0x8 6. "CH6,Disable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Disable request of channel x." "0,1" newline bitfld.long 0x8 4. "CH4,Disable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Disable request of channel x." "0,1" newline bitfld.long 0x8 2. "CH2,Disable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Disable request of channel x." "0,1" newline bitfld.long 0x8 0. "CH0,Disable request of channel x." "0,1" line.long 0xC "TIO6_CINVERT," bitfld.long 0xC 7. "CH7,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 6. "CH6,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 4. "CH4,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 2. "CH2,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 0. "CH0,Disable signal inversion of channel x." "0,1" line.long 0x10 "TIO6_CINPUT_MODE," bitfld.long 0x10 7. "CH7,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 6. "CH6,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 4. "CH4,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 2. "CH2,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 0. "CH0,Disable input mode of channel x." "0,1" line.long 0x14 "TIO6_CCYCLIC_MODE," bitfld.long 0x14 7. "CH7,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 6. "CH6,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 4. "CH4,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 2. "CH2,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 0. "CH0,Disable cyclic mode of channel x." "0,1" line.long 0x18 "TIO6_CTRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 6. "CH6,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 4. "CH4,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 2. "CH2,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 0. "CH0,disable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO6_CPLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 6. "CH6,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 4. "CH4,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 2. "CH2,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 0. "CH0,disable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3C80++0x1F line.long 0x0 "TIO6_SS," bitfld.long 0x0 7. "CH7,Set channel x." "0,1" newline bitfld.long 0x0 6. "CH6,Set channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Set channel x." "0,1" newline bitfld.long 0x0 4. "CH4,Set channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Set channel x." "0,1" newline bitfld.long 0x0 2. "CH2,Set channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Set channel x." "0,1" newline bitfld.long 0x0 0. "CH0,Set channel x." "0,1" line.long 0x4 "TIO6_SO," bitfld.long 0x4 7. "CH7,Set channel x." "0,1" newline bitfld.long 0x4 6. "CH6,Set channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Set channel x." "0,1" newline bitfld.long 0x4 4. "CH4,Set channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Set channel x." "0,1" newline bitfld.long 0x4 2. "CH2,Set channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Set channel x." "0,1" newline bitfld.long 0x4 0. "CH0,Set channel x." "0,1" line.long 0x8 "TIO6_SENDIS," bitfld.long 0x8 7. "CH7,Enable request of channel x." "0,1" newline bitfld.long 0x8 6. "CH6,Enable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Enable request of channel x." "0,1" newline bitfld.long 0x8 4. "CH4,Enable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Enable request of channel x." "0,1" newline bitfld.long 0x8 2. "CH2,Enable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Enable request of channel x." "0,1" newline bitfld.long 0x8 0. "CH0,Enable request of channel x." "0,1" line.long 0xC "TIO6_SINVERT," bitfld.long 0xC 7. "CH7,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 6. "CH6,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 4. "CH4,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 2. "CH2,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 0. "CH0,Enable signal inversion of channel x." "0,1" line.long 0x10 "TIO6_SINPUT_MODE," bitfld.long 0x10 7. "CH7,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 6. "CH6,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 4. "CH4,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 2. "CH2,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 0. "CH0,Enable input mode of channel x." "0,1" line.long 0x14 "TIO6_SCYCLIC_MODE," bitfld.long 0x14 7. "CH7,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 6. "CH6,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 4. "CH4,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 2. "CH2,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 0. "CH0,Enable cyclic mode of channel x." "0,1" line.long 0x18 "TIO6_STRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 6. "CH6,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 4. "CH4,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 2. "CH2,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 0. "CH0,enable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO6_SPLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 6. "CH6,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 4. "CH4,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 2. "CH2,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 0. "CH0,enable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3CC0++0x17 line.long 0x0 "TIO6_IS," bitfld.long 0x0 7. "CH7,Invert channel x." "0,1" newline bitfld.long 0x0 6. "CH6,Invert channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Invert channel x." "0,1" newline bitfld.long 0x0 4. "CH4,Invert channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Invert channel x." "0,1" newline bitfld.long 0x0 2. "CH2,Invert channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Invert channel x." "0,1" newline bitfld.long 0x0 0. "CH0,Invert channel x." "0,1" line.long 0x4 "TIO6_IO," bitfld.long 0x4 7. "CH7,Invert channel x." "0,1" newline bitfld.long 0x4 6. "CH6,Invert channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Invert channel x." "0,1" newline bitfld.long 0x4 4. "CH4,Invert channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Invert channel x." "0,1" newline bitfld.long 0x4 2. "CH2,Invert channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Invert channel x." "0,1" newline bitfld.long 0x4 0. "CH0,Invert channel x." "0,1" line.long 0x8 "TIO6_IENDIS," bitfld.long 0x8 7. "CH7,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 6. "CH6,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 4. "CH4,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 2. "CH2,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 0. "CH0,Toggle state request of channel x." "0,1" line.long 0xC "TIO6_IINVERT," bitfld.long 0xC 7. "CH7,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 6. "CH6,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 4. "CH4,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 2. "CH2,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 0. "CH0,Invert signal inversion of channel x." "0,1" line.long 0x10 "TIO6_IINPUT_MODE," bitfld.long 0x10 7. "CH7,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 6. "CH6,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 4. "CH4,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 2. "CH2,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 0. "CH0,Toggle input mode of channel x." "0,1" line.long 0x14 "TIO6_ICYCLIC_MODE," bitfld.long 0x14 7. "CH7,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 6. "CH6,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 4. "CH4,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 2. "CH2,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 0. "CH0,Toggle cyclic mode of channel x." "0,1" group.long 0x3D00++0x13 line.long 0x0 "TIO6_FUPD," bitfld.long 0x0 7. "CH7,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 6. "CH6,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 5. "CH5,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 4. "CH4,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 3. "CH3,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 2. "CH2,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 1. "CH1,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 0. "CH0,issue immediately a signal pulse on the update signal of channel x" "0,1" line.long 0x4 "TIO6_HW_CONF," bitfld.long 0x4 4. "TIO_PLUS,signals availablity of TIOplus functionality" "0,1" newline bitfld.long 0x4 0.--1. "NTIO_CH8,signals availablity of amount of channels" "0,1,2,3" line.long 0x8 "TIO6_RSEL_CTRL1," bitfld.long 0x8 28. "SEL_CLKEN7_0,select source of RS_CLKEN7[g][7] for channels g*8 .. g*8+7" "0,1" newline bitfld.long 0x8 24. "SEL_CLKEN6_0,select source of RS_CLKEN[g][6] for channels g*8 .. g*8+7" "0,1" line.long 0xC "TIO6_RSEL_CTRL2," bitfld.long 0xC 8. "SEL_TB2_0,select source of RS_TB2[g] for channels g*8 .. g*8+7" "0,1" newline bitfld.long 0xC 4. "SEL_TB1_0,select source of RS_TB1[g] for channels g*8 .. g*8+7" "0,1" line.long 0x10 "TIO6_PL_SWRST," bitfld.long 0x10 7. "CH7,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 6. "CH6,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 5. "CH5,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 4. "CH4,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 3. "CH3,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 2. "CH2,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 1. "CH1,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 0. "CH0,reset TIO_Plus resources of channel x" "0,1" group.long 0x4000++0x4F line.long 0x0 "CCM6_ARP0_CTRL," bitfld.long 0x0 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x0 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x0 0.--15. 1. "ADDR,ARP base address." line.long 0x4 "CCM6_ARP0_PROT," bitfld.long 0x4 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x8 "CCM6_ARP1_CTRL," bitfld.long 0x8 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x8 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x8 0.--15. 1. "ADDR,ARP base address." line.long 0xC "CCM6_ARP1_PROT," bitfld.long 0xC 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x10 "CCM6_ARP2_CTRL," bitfld.long 0x10 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x10 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x10 0.--15. 1. "ADDR,ARP base address." line.long 0x14 "CCM6_ARP2_PROT," bitfld.long 0x14 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x18 "CCM6_ARP3_CTRL," bitfld.long 0x18 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x18 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x18 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x18 0.--15. 1. "ADDR,ARP base address." line.long 0x1C "CCM6_ARP3_PROT," bitfld.long 0x1C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x20 "CCM6_ARP4_CTRL," bitfld.long 0x20 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x20 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x20 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x20 0.--15. 1. "ADDR,ARP base address." line.long 0x24 "CCM6_ARP4_PROT," bitfld.long 0x24 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x28 "CCM6_ARP5_CTRL," bitfld.long 0x28 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x28 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x28 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x28 0.--15. 1. "ADDR,ARP base address." line.long 0x2C "CCM6_ARP5_PROT," bitfld.long 0x2C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x30 "CCM6_ARP6_CTRL," bitfld.long 0x30 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x30 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x30 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x30 0.--15. 1. "ADDR,ARP base address." line.long 0x34 "CCM6_ARP6_PROT," bitfld.long 0x34 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x38 "CCM6_ARP7_CTRL," bitfld.long 0x38 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x38 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x38 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x38 0.--15. 1. "ADDR,ARP base address." line.long 0x3C "CCM6_ARP7_PROT," bitfld.long 0x3C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x40 "CCM6_ARP8_CTRL," bitfld.long 0x40 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x40 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x40 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x40 0.--15. 1. "ADDR,ARP base address." line.long 0x44 "CCM6_ARP8_PROT," bitfld.long 0x44 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x48 "CCM6_ARP9_CTRL," bitfld.long 0x48 31. "WPROT_AEI,AEI slave write protection." "0,1" newline bitfld.long 0x48 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x48 16.--19. 1. "SIZE,Size of ARP" newline hexmask.long.word 0x48 0.--15. 1. "ADDR,ARP base address." line.long 0x4C "CCM6_ARP9_PROT," bitfld.long 0x4C 7. "WPROT7,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 5. "WPROT5,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 3. "WPROT3,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 1. "WPROT1,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 0. "WPROT0,Write Protection MCS channel x." "0,1" group.long 0x41CC++0x3 line.long 0x0 "CCM6_TIO_G0_OUT," bitfld.long 0x0 31. "TIO_G1_OUT_N7,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 30. "TIO_G1_OUT_N6,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 29. "TIO_G1_OUT_N5,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 28. "TIO_G1_OUT_N4,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 27. "TIO_G1_OUT_N3,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 26. "TIO_G1_OUT_N2,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 25. "TIO_G1_OUT_N1,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 24. "TIO_G1_OUT_N0,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 23. "TIO_G0_OUT_N7,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 22. "TIO_G0_OUT_N6,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 21. "TIO_G0_OUT_N5,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 20. "TIO_G0_OUT_N4,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 19. "TIO_G0_OUT_N3,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 18. "TIO_G0_OUT_N2,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 17. "TIO_G0_OUT_N1,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 16. "TIO_G0_OUT_N0,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 15. "TIO_G1_OUT7,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 14. "TIO_G1_OUT6,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 13. "TIO_G1_OUT5,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 12. "TIO_G1_OUT4,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 11. "TIO_G1_OUT3,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 10. "TIO_G1_OUT2,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 9. "TIO_G1_OUT1,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 8. "TIO_G1_OUT0,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 7. "TIO_G0_OUT7,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 6. "TIO_G0_OUT6,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 5. "TIO_G0_OUT5,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 4. "TIO_G0_OUT4,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 3. "TIO_G0_OUT3,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 2. "TIO_G0_OUT2,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 1. "TIO_G0_OUT1,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 0. "TIO_G0_OUT0,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" group.long 0x41D4++0x13 line.long 0x0 "CCM6_HW_CONF2," bitfld.long 0x0 18. "AXIM_DATA_SIZE,Defines the data bus width of the AXI master interface" "0,1" newline bitfld.long 0x0 16. "AXIS_DATA_SIZE,Defines the data bus width of the AXI slave interface" "0,1" newline bitfld.long 0x0 9. "TIO_OUT_RST,TIO_OUT reset level" "0,1" newline bitfld.long 0x0 7. "AXIM_POSTED_WRITE,Write transaction without response" "0,1" newline bitfld.long 0x0 6. "AXIM_SEC_ACC,Secure AXI master access constant" "0,1" newline bitfld.long 0x0 5. "AXIM_PRIV_ACC,Privileged AXI master access constant" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "AXIM_ID_WIDTH,Defines which LSB of AXIM_ID are send to the bus" line.long 0x4 "CCM6_AEIM_STA," bitfld.long 0x4 24.--25. "AEIM_XPT_STA,AEIM Exception status." "0,1,2,3" newline hexmask.long.word 0x4 0.--15. 1. "AEIM_XPT_ADDR,Exception Address." line.long 0x8 "CCM6_HW_CONF," bitfld.long 0x8 31. "AEI_RDATA_PIPELINE_STAGE,Read data pipeline stage implemented" "0,1" newline bitfld.long 0x8 30. "AEI_ADDR_PIPELINE_STAGE,Address pipeline stage implemented" "0,1" newline bitfld.long 0x8 29. "INT_CLK_EN_GEN,Internal clock enable generation" "0,1" newline hexmask.long.byte 0x8 24.--28. 1. "TOM_TRIG_INTCHAIN,TOM internal trigger chain length without synchronization register" newline hexmask.long.byte 0x8 20.--23. 1. "ATOM_TRIG_INTCHAIN,ATOM internal trigger chain length without synchronization register" newline bitfld.long 0x8 19. "IRQ_MODE_SINGLE_PULSE,Signalize availability of Single Pulse IRQ mode" "0,1" newline bitfld.long 0x8 18. "IRQ_MODE_PULSE_NOTIFY,Signalize availability of Pulse Notoify IRQ mode" "0,1" newline bitfld.long 0x8 17. "IRQ_MODE_PULSE,Signalize availability of Pulse IRQ mode" "0,1" newline bitfld.long 0x8 16. "IRQ_MODE_LEVEL,Signalize availability of Level IRQ mode" "0,1" newline bitfld.long 0x8 15. "RESET_ACTIVE,Active level of asynchronous reset" "0,1" newline bitfld.long 0x8 13. "ERM,Enable RAM1 MSB for available MCS modules" "0,1" newline bitfld.long 0x8 12. "RAM_INIT_RST,RAM initialization from reset" "0,1" newline bitfld.long 0x8 9.--11. "TOM_TRIG_CHAIN,TOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "TOM_OUT_RST,TOM_OUT reset level" "0,1" newline bitfld.long 0x8 5.--7. "ATOM_TRIG_CHAIN,ATOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "ATOM_OUT_RST,ATOM_OUT reset level" "0,1" newline bitfld.long 0x8 3. "CFG_CLOCK_RATE,Clocks per ARU transfer" "0,1" newline bitfld.long 0x8 2. "SYNC_INPUT_REG,Additional pipelined stage in synchronous bridge mode" "0,1" newline bitfld.long 0x8 1. "BRIDGE_MODE_RST,Bridge mode after reset" "0,1" newline bitfld.long 0x8 0. "GRSTEN,Global Reset Enable" "0,1" line.long 0xC "CCM6_TIM_AUX_IN_SRC," bitfld.long 0xC 23. "SEL_OUT_N_CH7,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 22. "SEL_OUT_N_CH6,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 21. "SEL_OUT_N_CH5,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 20. "SEL_OUT_N_CH4,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 19. "SEL_OUT_N_CH3,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 18. "SEL_OUT_N_CH2,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 17. "SEL_OUT_N_CH1,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 16. "SEL_OUT_N_CH0,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 7. "SRC_CH7,Defines AUX_IN source of TIM[i] channel 7" "0,1" newline bitfld.long 0xC 6. "SRC_CH6,Defines AUX_IN source of TIM[i] channel 6" "0,1" newline bitfld.long 0xC 5. "SRC_CH5,Defines AUX_IN source of TIM[i] channel 5" "0,1" newline bitfld.long 0xC 4. "SRC_CH4,Defines AUX_IN source of TIM[i] channel 4" "0,1" newline bitfld.long 0xC 3. "SRC_CH3,Defines AUX_IN source of TIM[i] channel 3" "0,1" newline bitfld.long 0xC 2. "SRC_CH2,Defines AUX_IN source of TIM[i] channel 2" "0,1" newline bitfld.long 0xC 1. "SRC_CH1,Defines AUX_IN source of TIM[i] channel 1" "0,1" newline bitfld.long 0xC 0. "SRC_CH0,Defines AUX_IN source of TIM[i] channel 0" "0,1" line.long 0x10 "CCM6_EXT_CAP_EN," bitfld.long 0x10 15. "TIM_IP1_EXT_CAP_EN7,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 14. "TIM_IP1_EXT_CAP_EN6,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 13. "TIM_IP1_EXT_CAP_EN5,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 12. "TIM_IP1_EXT_CAP_EN4,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 11. "TIM_IP1_EXT_CAP_EN3,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 10. "TIM_IP1_EXT_CAP_EN2,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 9. "TIM_IP1_EXT_CAP_EN1,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 8. "TIM_IP1_EXT_CAP_EN0,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 7. "TIM_I_EXT_CAP_EN7,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 6. "TIM_I_EXT_CAP_EN6,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 5. "TIM_I_EXT_CAP_EN5,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 4. "TIM_I_EXT_CAP_EN4,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 3. "TIM_I_EXT_CAP_EN3,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 2. "TIM_I_EXT_CAP_EN2,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 1. "TIM_I_EXT_CAP_EN1,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 0. "TIM_I_EXT_CAP_EN0,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" group.long 0x41EC++0x7 line.long 0x0 "CCM6_ATOM_OUT," bitfld.long 0x0 31. "ATOM_IP1_OUT_N7,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 30. "ATOM_IP1_OUT_N6,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 29. "ATOM_IP1_OUT_N5,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 28. "ATOM_IP1_OUT_N4,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 27. "ATOM_IP1_OUT_N3,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 26. "ATOM_IP1_OUT_N2,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 25. "ATOM_IP1_OUT_N1,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 24. "ATOM_IP1_OUT_N0,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 23. "ATOM_IP1_OUT7,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 22. "ATOM_IP1_OUT6,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 21. "ATOM_IP1_OUT5,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 20. "ATOM_IP1_OUT4,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 19. "ATOM_IP1_OUT3,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 18. "ATOM_IP1_OUT2,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 17. "ATOM_IP1_OUT1,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 16. "ATOM_IP1_OUT0,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 15. "ATOM_I_OUT_N7,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 14. "ATOM_I_OUT_N6,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 13. "ATOM_I_OUT_N5,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 12. "ATOM_I_OUT_N4,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 11. "ATOM_I_OUT_N3,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 10. "ATOM_I_OUT_N2,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 9. "ATOM_I_OUT_N1,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 8. "ATOM_I_OUT_N0,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 7. "ATOM_I_OUT7,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 6. "ATOM_I_OUT6,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 5. "ATOM_I_OUT5,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 4. "ATOM_I_OUT4,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 3. "ATOM_I_OUT3,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 2. "ATOM_I_OUT2,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 1. "ATOM_I_OUT1,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 0. "ATOM_I_OUT0,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" line.long 0x4 "CCM6_CMU_CLK_CFG," bitfld.long 0x4 28.--29. "CLK7_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 24.--25. "CLK6_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 20.--21. "CLK5_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 16.--17. "CLK4_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 12.--13. "CLK3_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 8.--9. "CLK2_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 4.--5. "CLK1_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 0.--1. "CLK0_SRC,Clock y source signal selector" "0,1,2,3" group.long 0x41F8++0x7 line.long 0x0 "CCM6_CFG," bitfld.long 0x0 31. "TBU_DIR2,DIR1 input signal of module TBU timebase [z]." "0,1" newline bitfld.long 0x0 30. "TBU_DIR1,DIR1 input signal of module TBU timebase [z]." "0,1" newline bitfld.long 0x0 16.--17. "CLS_CLK_DIV,Cluster Clock Divider." "0,1,2,3" newline bitfld.long 0x0 8. "EN_TIO_DTM,Enable TIO and connected DTM" "0,1" newline bitfld.long 0x0 7. "EN_CMP_MON,Enable CMP and MON" "0,1" newline bitfld.long 0x0 6. "EN_PSM,Enable PSM" "0,1" newline bitfld.long 0x0 5. "EN_BRC,Enable BRC" "0,1" newline bitfld.long 0x0 4. "EN_DPLL_MAP,Enable DPLL and MAP" "0,1" newline bitfld.long 0x0 3. "EN_MCS,Enable MCS" "0,1" newline bitfld.long 0x0 2. "EN_ATOM_ADTM,Enable ATOM and ADTM" "0,1" newline bitfld.long 0x0 1. "EN_TOM_SPE_TDTM,Enable TOM SPE and TDTM" "0,1" newline bitfld.long 0x0 0. "EN_TIM,Enable TIM" "0,1" line.long 0x4 "CCM6_PROT," bitfld.long 0x4 0. "CLS_PROT,Cluster Protection" "0,1" group.long 0x4500++0x7F line.long 0x0 "CDTM6_DTM4_CTRL," bitfld.long 0x0 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x0 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x0 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x0 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x0 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x4 "CDTM6_DTM4_CH_CTRL1," bitfld.long 0x4 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x4 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x4 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x4 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x4 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x4 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x4 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x4 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x4 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x4 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x4 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x4 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x4 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x4 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x4 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x4 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x4 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x4 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x8 "CDTM6_DTM4_CH_CTRL2," bitfld.long 0x8 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x8 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x8 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x8 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x8 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x8 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x8 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x8 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x8 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x8 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x8 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x8 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x8 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x8 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x8 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x8 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x8 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x8 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x8 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x8 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x8 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x8 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x8 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x8 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x8 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x8 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x8 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x8 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x8 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x8 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x8 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x8 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0xC "CDTM6_DTM4_CH_CTRL2_SR," bitfld.long 0xC 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0xC 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0xC 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0xC 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0xC 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0xC 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0xC 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0xC 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0xC 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0xC 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0xC 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0xC 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0xC 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x10 "CDTM6_DTM4_PS_CTRL," bitfld.long 0x10 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x10 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x10 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x10 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x10 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x14 "CDTM6_DTM4_CH0_DTV," bitfld.long 0x14 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x14 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x14 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x18 "CDTM6_DTM4_CH1_DTV," bitfld.long 0x18 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x18 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x18 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x1C "CDTM6_DTM4_CH2_DTV," bitfld.long 0x1C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x1C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x1C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x20 "CDTM6_DTM4_CH3_DTV," bitfld.long 0x20 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x20 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x20 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x24 "CDTM6_DTM4_CH_SR," bitfld.long 0x24 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x24 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x24 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x24 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x24 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x24 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x24 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x24 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x28 "CDTM6_DTM4_CH_CTRL3," bitfld.long 0x28 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x28 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x28 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x28 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x28 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x28 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x28 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x28 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x28 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x28 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x2C "CDTM6_DTM4_CTRL2," bitfld.long 0x2C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x2C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x2C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x2C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x2C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x2C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x2C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x2C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x2C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x2C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x2C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x2C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x2C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x2C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x2C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x2C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x2C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x2C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x2C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x2C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x30 "CDTM6_DTM4_CH0_DTV_SR," bitfld.long 0x30 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x30 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x30 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x30 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x30 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x30 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x34 "CDTM6_DTM4_CH1_DTV_SR," bitfld.long 0x34 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x34 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x34 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x34 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x34 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x34 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x38 "CDTM6_DTM4_CH2_DTV_SR," bitfld.long 0x38 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x38 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x38 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x38 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x38 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x38 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x3C "CDTM6_DTM4_CH3_DTV_SR," bitfld.long 0x3C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x3C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x3C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x3C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x3C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x3C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x40 "CDTM6_DTM5_CTRL," bitfld.long 0x40 16. "SHUT_OFF_RST,Shut off reset" "0,1" newline bitfld.long 0x40 8. "SR_UPD_EN,Shadow register update enable" "0,1" newline bitfld.long 0x40 7. "CH_SHUTOFF_EN,Individual shuftoff feature enable" "0,1" newline bitfld.long 0x40 4.--6. "UPD_MODE,Update mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 2.--3. "DTM_SEL,Select DTM update and SHUT_OFF reset signal" "0,1,2,3" newline bitfld.long 0x40 0.--1. "CLK_SEL,Clock source select" "0,1,2,3" line.long 0x44 "CDTM6_DTM5_CH_CTRL1," bitfld.long 0x44 28.--29. "O1F_3,Output 1 function channel 3" "0,1,2,3" newline bitfld.long 0x44 27. "SWAP_3,Swap outputs DTM[d]_CH[3]_OUT0 and DTM[d]_CH[3]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 26. "SH_EN_3,Shift enable channel 3" "0,1" newline bitfld.long 0x44 25. "I1SEL_3,Input 1 select channel 3" "0,1" newline bitfld.long 0x44 24. "O1SEL_3,Output 1 select channel 3" "0,1" newline bitfld.long 0x44 22. "XDT_EN_2_3,Cross dead time enable on channel 2 and 3" "0,1" newline bitfld.long 0x44 20.--21. "O1F_2,Output 1 function channel 2" "0,1,2,3" newline bitfld.long 0x44 19. "SWAP_2,Swap outputs DTM[d]_CH[2]_OUT0 and DTM[d]_CH[2]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 18. "SH_EN_2,Shift enable channel 2" "0,1" newline bitfld.long 0x44 17. "I1SEL_2,Input 1 select channel 2" "0,1" newline bitfld.long 0x44 16. "O1SEL_2,Output 1 select channel 2" "0,1" newline bitfld.long 0x44 12.--13. "O1F_1,Output 1 function channel 1" "0,1,2,3" newline bitfld.long 0x44 11. "SWAP_1,Swap outputs DTM[d]_CH[1]_OUT0 and DTM[d]_CH[1]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 10. "SH_EN_1,Shift enable channel 1" "0,1" newline bitfld.long 0x44 9. "I1SEL_1,Input 1 select channel 1" "0,1" newline bitfld.long 0x44 8. "O1SEL_1,Output 1 select channel 1" "0,1" newline bitfld.long 0x44 6. "XDT_EN_0_1,Cross dead time enable on channel 0 and 1" "0,1" newline bitfld.long 0x44 4.--5. "O1F_0,Output 1 function channel 0" "0,1,2,3" newline bitfld.long 0x44 3. "SWAP_0,Swap outputs DTM[d]_CH[0]_OUT0 and DTM[d]_CH[0]_OUT1 (before final output register)" "0,1" newline bitfld.long 0x44 1. "I1SEL_0,Input 1 select channel 0" "0,1" newline bitfld.long 0x44 0. "O1SEL_0,Output 1 select channel 0" "0,1" line.long 0x48 "CDTM6_DTM5_CH_CTRL2," bitfld.long 0x48 31. "DT1_3,Dead time path enable on output 1 channel 3" "0,1" newline bitfld.long 0x48 30. "SL1_3,Signal level on output 1 channel 3" "0,1" newline bitfld.long 0x48 29. "OC1_3,Output 1 control channel 3" "0,1" newline bitfld.long 0x48 28. "POL1_3,Polarity on output 1 channel 3" "0,1" newline bitfld.long 0x48 27. "DT0_3,Dead time path enable on output 0 channel 3" "0,1" newline bitfld.long 0x48 26. "SL0_3,Signal level on output 0 channel 3" "0,1" newline bitfld.long 0x48 25. "OC0_3,Output 0 control channel 3" "0,1" newline bitfld.long 0x48 24. "POL0_3,Polarity on output 0 channel 3" "0,1" newline bitfld.long 0x48 23. "DT1_2,Dead time path enable on output 1 channel 2" "0,1" newline bitfld.long 0x48 22. "SL1_2,Signal level on output 1 channel 2" "0,1" newline bitfld.long 0x48 21. "OC1_2,Output 1 control channel 2" "0,1" newline bitfld.long 0x48 20. "POL1_2,Polarity on output 1 channel 2" "0,1" newline bitfld.long 0x48 19. "DT0_2,Dead time path enable on output 0 channel 2" "0,1" newline bitfld.long 0x48 18. "SL0_2,Signal level on output 0 channel 2" "0,1" newline bitfld.long 0x48 17. "OC0_2,Output 0 control channel 2" "0,1" newline bitfld.long 0x48 16. "POL0_2,Polarity on output 0 channel 2" "0,1" newline bitfld.long 0x48 15. "DT1_1,Dead time path enable on output 1 channel 1" "0,1" newline bitfld.long 0x48 14. "SL1_1,Signal level on output 1 channel 1" "0,1" newline bitfld.long 0x48 13. "OC1_1,Output 1 control channel 1" "0,1" newline bitfld.long 0x48 12. "POL1_1,Polarity on output 1 channel 1" "0,1" newline bitfld.long 0x48 11. "DT0_1,Dead time path enable on output 0 channel 1" "0,1" newline bitfld.long 0x48 10. "SL0_1,Signal level on output 0 channel 1" "0,1" newline bitfld.long 0x48 9. "OC0_1,Output 0 control channel 1" "0,1" newline bitfld.long 0x48 8. "POL0_1,Polarity on output 0 channel 1" "0,1" newline bitfld.long 0x48 7. "DT1_0,Dead time path enable on output 1 channel 0" "0,1" newline bitfld.long 0x48 6. "SL1_0,Signal level on output 1 channel 0" "0,1" newline bitfld.long 0x48 5. "OC1_0,Output 1 control channel 0" "0,1" newline bitfld.long 0x48 4. "POL1_0,Polarity on output 1 channel 0" "0,1" newline bitfld.long 0x48 3. "DT0_0,Dead time path enable on output 0 channel 0" "0,1" newline bitfld.long 0x48 2. "SL0_0,Signal level on output 0 channel 0" "0,1" newline bitfld.long 0x48 1. "OC0_0,Output 0 control channel 0" "0,1" newline bitfld.long 0x48 0. "POL0_0,Polarity on output 0 channel 0" "0,1" line.long 0x4C "CDTM6_DTM5_CH_CTRL2_SR," bitfld.long 0x4C 31. "DT1_3_SR,Dead time path enable on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 30. "SL1_3_SR,Signal level on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 29. "OC1_3_SR,Output 1 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 28. "POL1_3_SR,Polarity on output 1 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 27. "DT0_3_SR,Dead time path enable on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 26. "SL0_3_SR,Signal level on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 25. "OC0_3_SR,Output 0 control channel 3 shadow register" "0,1" newline bitfld.long 0x4C 24. "POL0_3_SR,Polarity on output 0 channel 3 shadow register" "0,1" newline bitfld.long 0x4C 23. "DT1_2_SR,Dead time path enable on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 22. "SL1_2_SR,Signal level on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 21. "OC1_2_SR,Output 1 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 20. "POL1_2_SR,Polarity on output 1 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 19. "DT0_2_SR,Dead time path enable on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 18. "SL0_2_SR,Signal level on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 17. "OC0_2_SR,Output 0 control channel 2 shadow register" "0,1" newline bitfld.long 0x4C 16. "POL0_2_SR,Polarity on output 0 channel 2 shadow register" "0,1" newline bitfld.long 0x4C 15. "DT1_1_SR,Dead time path enable on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 14. "SL1_1_SR,Signal level on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 13. "OC1_1_SR,Output 1 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 12. "POL1_1_SR,Polarity on output 1 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 11. "DT0_1_SR,Dead time path enable on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 10. "SL0_1_SR,Signal level on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 9. "OC0_1_SR,Output 0 control channel 1 shadow register" "0,1" newline bitfld.long 0x4C 8. "POL0_1_SR,Polarity on output 0 channel 1 shadow register" "0,1" newline bitfld.long 0x4C 7. "DT1_0_SR,Dead time path enable on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 6. "SL1_0_SR,Signal level on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 5. "OC1_0_SR,Output 1 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 4. "POL1_0_SR,Polarity on output 1 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 3. "DT0_0_SR,Dead time path enable on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 2. "SL0_0_SR,Signal level on output 0 channel 0 shadow register" "0,1" newline bitfld.long 0x4C 1. "OC0_0_SR,Output 0 control channel 0 shadow register" "0,1" newline bitfld.long 0x4C 0. "POL0_0_SR,Polarity on output 0 channel 0 shadow register" "0,1" line.long 0x50 "CDTM6_DTM5_PS_CTRL," bitfld.long 0x50 20.--21. "SHIFT_SEL,Shift select" "0,1,2,3" newline bitfld.long 0x50 18. "TIM_SEL,TIM input select" "0,1" newline bitfld.long 0x50 17. "IN_POL,Input polarity" "0,1" newline bitfld.long 0x50 16. "PSU_IN_SEL,PSU input select" "0,1" newline hexmask.long.word 0x50 0.--9. 1. "RELBLK,Reload value blanking window" line.long 0x54 "CDTM6_DTM5_CH0_DTV," bitfld.long 0x54 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x54 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x54 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x58 "CDTM6_DTM5_CH1_DTV," bitfld.long 0x58 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x58 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x58 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x5C "CDTM6_DTM5_CH2_DTV," bitfld.long 0x5C 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x5C 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x5C 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x60 "CDTM6_DTM5_CH3_DTV," bitfld.long 0x60 31. "HRES,HRES: high resolution PWM support" "0,1" newline hexmask.long.word 0x60 16.--28. 1. "RELFALL,Reload value for falling edge dead time" newline hexmask.long.word 0x60 0.--12. 1. "RELRISE,Reload value for rising edge dead time" line.long 0x64 "CDTM6_DTM5_CH_SR," bitfld.long 0x64 7. "SL1_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_3_SR" "0,1" newline bitfld.long 0x64 6. "SL0_3_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_3_SR" "0,1" newline bitfld.long 0x64 5. "SL1_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_2_SR" "0,1" newline bitfld.long 0x64 4. "SL0_2_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_2_SR" "0,1" newline bitfld.long 0x64 3. "SL1_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_1_SR" "0,1" newline bitfld.long 0x64 2. "SL0_1_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_1_SR" "0,1" newline bitfld.long 0x64 1. "SL1_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL1_0_SR" "0,1" newline bitfld.long 0x64 0. "SL0_0_SR_SR,Shadow register for bit DTM[d]_CH_CTRL2_SR.SL0_0_SR" "0,1" line.long 0x68 "CDTM6_DTM5_CH_CTRL3," bitfld.long 0x68 27. "TSEL1_3,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 26. "TSEL0_3,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 25. "CIS3,Combinational input select channel 3" "0,1" newline bitfld.long 0x68 24. "CII3,Combinational input invert channel 3" "0,1" newline bitfld.long 0x68 19. "TSEL1_2,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 18. "TSEL0_2,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 17. "CIS2,Combinational input select channel 2" "0,1" newline bitfld.long 0x68 16. "CII2,Combinational input invert channel 2" "0,1" newline bitfld.long 0x68 11. "TSEL1_1,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 10. "TSEL0_1,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 9. "CIS1,Combinational input select channel 1" "0,1" newline bitfld.long 0x68 8. "CII1,Combinational input invert channel 1" "0,1" newline bitfld.long 0x68 3. "TSEL1_0,Input selection combinational logic path" "0,1" newline bitfld.long 0x68 2. "TSEL0_0,Input selection for dead time / edge trigger generation" "0,1" newline bitfld.long 0x68 1. "CIS0,Combinational input select channel 0" "0,1" newline bitfld.long 0x68 0. "CII0,Combinational input invert channel 0" "0,1" line.long 0x6C "CDTM6_DTM5_CTRL2," bitfld.long 0x6C 31. "WR_EN_3,Channel 3: Write enable of Bitfields" "0,1" newline bitfld.long 0x6C 30. "SHUT_OFF_RST_3,Channel 3: Clear of internal signal SHUTOFF_SYNC_3 if selected as control source." "0,1" newline bitfld.long 0x6C 28.--29. "UPD_MODE_3,Channel 3: Control the update mode of the internal SHUTOFF_SYNC_3 signal." "?,?,?,3: Control the update mode of the internal.." newline bitfld.long 0x6C 27. "SHUTOFF_POL_3,Channel 3: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0,1" newline bitfld.long 0x6C 24.--26. "SHUTOFF_SEL_3,Channel 3: Select input signal to be used as shut off signal." "?,?,?,3: Select input signal to be used as shut off signal,?,?,?,?" newline bitfld.long 0x6C 23. "WR_EN_2,Channel 2: Write enable of Bitfields" "?,?" newline bitfld.long 0x6C 22. "SHUT_OFF_RST_2,Channel 2: Clear of internal signal SHUTOFF_SYNC_2 if selected as control source." "?,?" newline bitfld.long 0x6C 20.--21. "UPD_MODE_2,Channel 2: Control the update mode of the internal SHUTOFF_SYNC_2 signal." "?,?,2: Control the update mode of the internal..,?" newline bitfld.long 0x6C 19. "SHUTOFF_POL_2,Channel 2: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,?" newline bitfld.long 0x6C 16.--18. "SHUTOFF_SEL_2,Channel 2: Select input signal to be used as shut off signal." "?,?,2: Select input signal to be used as shut off signal,?,?,?,?,?" newline bitfld.long 0x6C 15. "WR_EN_1,Channel 1: Write enable of Bitfields" "?,1: Write enable of Bitfields" newline bitfld.long 0x6C 14. "SHUT_OFF_RST_1,Channel 1: Clear of internal signal SHUTOFF_SYNC_1 if selected as control source." "?,1: Clear of internal signal SHUTOFF_SYNC_1 if.." newline bitfld.long 0x6C 12.--13. "UPD_MODE_1,Channel 1: Control the update mode of the internal SHUTOFF_SYNC_1 signal." "?,1: Control the update mode of the internal..,?,?" newline bitfld.long 0x6C 11. "SHUTOFF_POL_1,Channel 1: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "?,1: Configure if the selected shut off input signal.." newline bitfld.long 0x6C 8.--10. "SHUTOFF_SEL_1,Channel 1: Select input signal to be used as shut off signal." "?,1: Select input signal to be used as shut off signal,?,?,?,?,?,?" newline bitfld.long 0x6C 7. "WR_EN_0,Channel 0: Write enable of Bitfields" "0: Write enable of Bitfields,?" newline bitfld.long 0x6C 6. "SHUT_OFF_RST_0,Channel 0: Clear of internal signal SHUTOFF_SYNC_0 if selected as control source." "0: Clear of internal signal SHUTOFF_SYNC_0 if..,?" newline bitfld.long 0x6C 4.--5. "UPD_MODE_0,Channel 0: Control the update mode of the internal SHUTOFF_SYNC_0 signal." "0: Control the update mode of the internal..,?,?,?" newline bitfld.long 0x6C 3. "SHUTOFF_POL_0,Channel 0: Configure if the selected shut off input signal used as shut off output signal is inverted or not." "0: Configure if the selected shut off input signal..,?" newline bitfld.long 0x6C 0.--2. "SHUTOFF_SEL_0,Channel 0: Select input signal to be used as shut off signal." "0: Select input signal to be used as shut off signal,?,?,?,?,?,?,?" line.long 0x70 "CDTM6_DTM5_CH0_DTV_SR," bitfld.long 0x70 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x70 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x70 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x70 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x70 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x70 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x74 "CDTM6_DTM5_CH1_DTV_SR," bitfld.long 0x74 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x74 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x74 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x74 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x74 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x74 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x78 "CDTM6_DTM5_CH2_DTV_SR," bitfld.long 0x78 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x78 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x78 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x78 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x78 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x78 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" line.long 0x7C "CDTM6_DTM5_CH3_DTV_SR," bitfld.long 0x7C 31. "RELFALL_UPD_EN,Control bit to enable update of RELFALL" "0,1" newline bitfld.long 0x7C 30. "RELFALL_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELFALL" "0,1" newline hexmask.long.word 0x7C 16.--28. 1. "RELFALL_SR,Shadow value for falling edge dead time" newline bitfld.long 0x7C 15. "RELRISE_UPD_EN,Control bit to enable update of RELRISE" "0,1" newline bitfld.long 0x7C 14. "RELRISE_UPD_FE0RE1,Control if falling edge or rising edge triggers update of RELRISE" "0,1" newline hexmask.long.word 0x7C 0.--12. 1. "RELRISE_SR,Shadow value for rising edge dead time" group.long 0x5000++0xB line.long 0x0 "AXIM6_FREE," bitfld.long 0x0 3. "FREE3,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 2. "FREE2,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 1. "FREE1,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 0. "FREE0,This bit represents the allocation status of the slot [t]" "0,1" line.long 0x4 "AXIM6_REQUEST," hexmask.long.byte 0x4 24.--31. 1. "REQID,This bit field shows the new allocated slot as binary encoded index. If no slot could be allocated this bit field is read as all 1 (0xff)." newline bitfld.long 0x4 3. "REQ1HOT3,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 2. "REQ1HOT2,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 1. "REQ1HOT1,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 0. "REQ1HOT0,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" line.long 0x8 "AXIM6_RELEASE," bitfld.long 0x8 3. "RELREQ3,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 2. "RELREQ2,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 1. "RELREQ1,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 0. "RELREQ0,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" group.long 0x5020++0x3 line.long 0x0 "AXIM6_SLOT0_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5028++0x3 line.long 0x0 "AXIM6_SLOT0_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5030++0xB line.long 0x0 "AXIM6_SLOT0_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM6_SLOT0_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM6_SLOT0_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5040++0x3 line.long 0x0 "AXIM6_SLOT1_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5048++0x3 line.long 0x0 "AXIM6_SLOT1_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5050++0xB line.long 0x0 "AXIM6_SLOT1_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM6_SLOT1_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM6_SLOT1_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5060++0x3 line.long 0x0 "AXIM6_SLOT2_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5068++0x3 line.long 0x0 "AXIM6_SLOT2_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5070++0xB line.long 0x0 "AXIM6_SLOT2_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM6_SLOT2_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM6_SLOT2_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5080++0x3 line.long 0x0 "AXIM6_SLOT3_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5088++0x3 line.long 0x0 "AXIM6_SLOT3_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5090++0xB line.long 0x0 "AXIM6_SLOT3_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" newline bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" newline hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" newline bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM6_SLOT3_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM6_SLOT3_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" newline bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" newline bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" repeat 16384. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10000)++0x3 line.long 0x0 "MCS6_MEM[$1]," hexmask.long 0x0 0.--31. 1. "DATA,MCS memory location." repeat.end tree.end tree "GTM_CLS7" base ad:0x740E0000 group.long 0x800++0x3F line.long 0x0 "TIM7_CH0_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM7_CH0_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM7_CH0_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM7_CH0_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM7_CH0_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM7_CH0_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM7_CH0_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM7_CH0_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM7_CH0_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM7_CH0_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM7_CH0_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM7_CH0_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM7_CH0_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM7_CH0_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM7_CH0_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM7_CH0_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x880++0x3F line.long 0x0 "TIM7_CH1_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM7_CH1_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM7_CH1_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM7_CH1_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM7_CH1_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM7_CH1_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM7_CH1_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM7_CH1_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM7_CH1_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM7_CH1_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM7_CH1_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM7_CH1_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM7_CH1_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM7_CH1_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM7_CH1_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM7_CH1_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x900++0x3F line.long 0x0 "TIM7_CH2_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM7_CH2_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM7_CH2_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM7_CH2_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM7_CH2_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM7_CH2_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM7_CH2_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM7_CH2_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM7_CH2_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM7_CH2_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM7_CH2_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM7_CH2_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM7_CH2_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM7_CH2_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM7_CH2_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM7_CH2_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0x980++0x3F line.long 0x0 "TIM7_CH3_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM7_CH3_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM7_CH3_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM7_CH3_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM7_CH3_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM7_CH3_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM7_CH3_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM7_CH3_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM7_CH3_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM7_CH3_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM7_CH3_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM7_CH3_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM7_CH3_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM7_CH3_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM7_CH3_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM7_CH3_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xA00++0x3F line.long 0x0 "TIM7_CH4_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM7_CH4_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM7_CH4_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM7_CH4_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM7_CH4_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM7_CH4_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM7_CH4_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM7_CH4_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM7_CH4_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM7_CH4_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM7_CH4_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM7_CH4_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM7_CH4_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM7_CH4_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM7_CH4_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM7_CH4_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xA80++0x3F line.long 0x0 "TIM7_CH5_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM7_CH5_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM7_CH5_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM7_CH5_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM7_CH5_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM7_CH5_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM7_CH5_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM7_CH5_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM7_CH5_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM7_CH5_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM7_CH5_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM7_CH5_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM7_CH5_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM7_CH5_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM7_CH5_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM7_CH5_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xB00++0x3F line.long 0x0 "TIM7_CH6_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM7_CH6_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM7_CH6_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM7_CH6_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM7_CH6_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM7_CH6_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM7_CH6_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM7_CH6_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM7_CH6_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM7_CH6_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM7_CH6_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM7_CH6_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM7_CH6_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM7_CH6_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM7_CH6_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM7_CH6_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xB80++0x3F line.long 0x0 "TIM7_CH7_GPR0," hexmask.long.byte 0x0 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x0 0.--23. 1. "GPR0,Input signal characteristic parameter 0." line.long 0x4 "TIM7_CH7_GPR1," hexmask.long.byte 0x4 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x4 0.--23. 1. "GPR1,Input signal characteristic parameter 1." line.long 0x8 "TIM7_CH7_CNT," hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Actual SMU counter value" line.long 0xC "TIM7_CH7_ECNT," hexmask.long.word 0xC 0.--15. 1. "ECNT,Edge counter" line.long 0x10 "TIM7_CH7_CNTS," hexmask.long.byte 0x10 24.--31. 1. "ECNT,Edge counter." hexmask.long.tbyte 0x10 0.--23. 1. "CNTS,Counter shadow register." line.long 0x14 "TIM7_CH7_TDUC," hexmask.long.byte 0x14 16.--23. 1. "TO_CNT2,Current Timeout value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x14 8.--15. 1. "TO_CNT1,Current Timeout value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x14 0.--7. 1. "TO_CNT,Current Timeout value slice0 for channel x (x:0...m-1)." line.long 0x18 "TIM7_CH7_TDUV," bitfld.long 0x18 28.--30. "TCS,Timeout Clock selection" "0,1,2,3,4,5,6,7" bitfld.long 0x18 27. "TDU_SAME_CNT_CLK,Define clocking of TO_CNT TO_CNT1." "0,1" newline bitfld.long 0x18 26. "TCS_USE_SAMPLE_EVT,Use tdu_sample_evt as Timeout Clock" "0,1" bitfld.long 0x18 24.--25. "SLICING,Cascading of counter slices" "0,1,2,3" newline hexmask.long.byte 0x18 16.--23. 1. "TOV2,Time out compare value slice2 for channel x (x:0...m-1)." hexmask.long.byte 0x18 8.--15. 1. "TOV1,Time out compare value slice1 for channel x (x:0...m-1)." newline hexmask.long.byte 0x18 0.--7. 1. "TOV,Time out compare value slice0 for channel x (x:0...m-1)." line.long 0x1C "TIM7_CH7_FLT_RE," hexmask.long.tbyte 0x1C 0.--23. 1. "FLT_RE,Filter parameter for rising edge." line.long 0x20 "TIM7_CH7_FLT_FE," hexmask.long.tbyte 0x20 0.--23. 1. "FLT_FE,Filter parameter for falling edge." line.long 0x24 "TIM7_CH7_CTRL," bitfld.long 0x24 30.--31. "TOCTRL,Timeout control" "0,1,2,3" bitfld.long 0x24 29. "EGPR1_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR1_SEL bit field." "0,1" newline bitfld.long 0x24 28. "EGPR0_SEL,Extension of TIM[i]_CH[x]_CTRL.GPR0_SEL bit field." "0,1" bitfld.long 0x24 27. "FR_ECNT_OFL,Extended Edge counter overflow behavior" "0,1" newline bitfld.long 0x24 24.--26. "CLK_SEL,CMU clock source select for channel." "0,1,2,3,4,5,6,7" bitfld.long 0x24 23. "FLT_CTR_FE,Filter counter mode for falling edge." "0,1" newline bitfld.long 0x24 22. "FLT_MODE_FE,Filter mode for falling edge." "0,1" bitfld.long 0x24 21. "FLT_CTR_RE,Filter counter mode for rising edge." "0,1" newline bitfld.long 0x24 20. "FLT_MODE_RE,Filter mode for rising edge." "0,1" bitfld.long 0x24 19. "EXT_CAP_EN,Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored." "0,1" newline bitfld.long 0x24 17.--18. "FLT_CNT_FRQ,Filter counter frequency select" "0,1,2,3" bitfld.long 0x24 16. "FLT_EN,Filter enable for channel x (x:0...7)" "0,1" newline bitfld.long 0x24 15. "ECNT_RESET,Enables resetting of counter in certain modes" "0,1" bitfld.long 0x24 14. "ISL,Ignore signal level" "0,1" newline bitfld.long 0x24 13. "DSL,Signal level control" "0,1" bitfld.long 0x24 12. "CNTS_SEL,Selection for TIM[i]_CH[x]_CNTS register" "0,1" newline bitfld.long 0x24 10.--11. "GPR1_SEL,Selection for TIM[i]_CH[x]_GPR1 register" "0,1,2,3" bitfld.long 0x24 8.--9. "GPR0_SEL,Selection for TIM[i]_CH[x]_GPR0 register" "0,1,2,3" newline bitfld.long 0x24 7. "TBU0_SEL,TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0 1)" "0,1" bitfld.long 0x24 6. "CICTRL,Channel Input Control." "0,1" newline bitfld.long 0x24 5. "ARU_EN,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 register values routed to ARU" "0,1" bitfld.long 0x24 4. "OSM,One-shot mode" "0,1" newline bitfld.long 0x24 1.--3. "TIM_MODE,TIM channel x (x:0...7) mode" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "TIM_EN,TIM channel x (x:0...7) enable" "0,1" line.long 0x28 "TIM7_CH7_ECTRL," bitfld.long 0x28 31. "USE_PREV_CH_IN,Select input data source for TIM channel." "0,1" bitfld.long 0x28 30. "ECLK_SEL,Extension of bit field TIM[i]_CH[x]_CTRL.CLK_SEL." "0,1" newline bitfld.long 0x28 29. "IMM_START,Start immediately the measurement" "0,1" bitfld.long 0x28 28. "SWAP_CAPTURE,Swap point of time of capturing TIM[i]_CH[x]_CNTS and TIM[i]_CH[x]_GPR1" "0,1" newline bitfld.long 0x28 25. "EFLT_CTR_FE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_FE." "0,1" bitfld.long 0x28 24. "EFLT_CTR_RE,Extension of bit field TIM[i]_CH[x]_CTRL.FLT_CTR_RE." "0,1" newline bitfld.long 0x28 22.--23. "USE_LUT,Generate Filter input by lookup table" "0,1,2,3" hexmask.long.byte 0x28 16.--19. 1. "TDU_RESYNC,Defines condition which will resynchronize the TDU unit." newline bitfld.long 0x28 12.--14. "TDU_STOP,Defines condition which will stop the TDU unit." "0,1,2,3,4,5,6,7" bitfld.long 0x28 8.--10. "TDU_START,Defines condition which will start the TDU unit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--7. "TODET_IRQ_SRC,Selection of source for TODET_IRQ" "0,1,2,3" bitfld.long 0x28 5. "USE_PREV_TDU_IN,Select input data source for TDU." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "EXT_CAP_SRC,Defines selected source for triggering the EXT_CAPTURE functionality." line.long 0x2C "TIM7_CH7_IRQ_NOTIFY," bitfld.long 0x2C 5. "GLITCHDET,Glitch detected on channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 4. "TODET,Timeout reached for input signal of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 3. "GPROFL,TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 data overflow old data not read out before new data has arrived at input pin (x:0...m-1)" "0,1" bitfld.long 0x2C 2. "CNTOFL,SMU TIM[i]_CH[x]_CNT counter overflow of channel x (x:0...m-1)" "0,1" newline bitfld.long 0x2C 1. "ECNTOFL,ECNT counter overflow of channel x (x:0...m-1)" "0,1" bitfld.long 0x2C 0. "NEWVAL,New measurement value detected by in channel x (x:0...m-1)" "0,1" line.long 0x30 "TIM7_CH7_IRQ_EN," bitfld.long 0x30 5. "GLITCHDET_IRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x30 4. "TODET_IRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 3. "GPROFL_IRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" bitfld.long 0x30 2. "CNTOFL_IRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x30 1. "ECNTOFL_IRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x30 0. "NEWVAL_IRQ_EN,TIM_NEWVALx_IRQ interrupt enable" "0,1" line.long 0x34 "TIM7_CH7_IRQ_FORCINT," bitfld.long 0x34 5. "TRG_GLITCHDET,Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 4. "TRG_TODET,Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 3. "TRG_GPROFL,Trigger GPROFL bit in TIM_CH[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 2. "TRG_CNTOFL,Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" newline bitfld.long 0x34 1. "TRG_ECNTOFL,Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" bitfld.long 0x34 0. "TRG_NEWVAL,Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software" "0,1" line.long 0x38 "TIM7_CH7_IRQ_MODE," bitfld.long 0x38 0.--1. "IRQ_MODE,IRQ mode selection of channel [x]" "0,1,2,3" line.long 0x3C "TIM7_CH7_EIRQ_EN," bitfld.long 0x3C 5. "GLITCHDET_EIRQ_EN,TIM_GLITCHDETx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 4. "TODET_EIRQ_EN,TIM_TODETx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 3. "GPROFL_EIRQ_EN,TIM_GPROFL_IRQ interrupt enable" "0,1" bitfld.long 0x3C 2. "CNTOFL_EIRQ_EN,TIM_CNTOFLx_IRQ interrupt enable" "0,1" newline bitfld.long 0x3C 1. "ECNTOFL_EIRQ_EN,TIM_ECNTOFLx_IRQ interrupt enable" "0,1" bitfld.long 0x3C 0. "NEWVAL_EIRQ_EN,TIM_NEWVALx_EIRQ error interrupt enable" "0,1" group.long 0xC00++0xB line.long 0x0 "TIM7_INP_VAL," bitfld.long 0x0 23. "TIM_IN7,Signal channel x after TIM input signal synchronization" "0,1" bitfld.long 0x0 22. "TIM_IN6,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 21. "TIM_IN5,Signal channel x after TIM input signal synchronization" "0,1" bitfld.long 0x0 20. "TIM_IN4,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 19. "TIM_IN3,Signal channel x after TIM input signal synchronization" "0,1" bitfld.long 0x0 18. "TIM_IN2,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 17. "TIM_IN1,Signal channel x after TIM input signal synchronization" "0,1" bitfld.long 0x0 16. "TIM_IN0,Signal channel x after TIM input signal synchronization" "0,1" newline bitfld.long 0x0 15. "F_IN7,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" bitfld.long 0x0 14. "F_IN6,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 13. "F_IN5,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" bitfld.long 0x0 12. "F_IN4,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 11. "F_IN3,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" bitfld.long 0x0 10. "F_IN2,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 9. "F_IN1,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" bitfld.long 0x0 8. "F_IN0,Signal channel x after INPSRC selection before TIM FLT unit" "0,1" newline bitfld.long 0x0 7. "F_OUT7,Signal channel x after TIM FLT unit" "0,1" bitfld.long 0x0 6. "F_OUT6,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 5. "F_OUT5,Signal channel x after TIM FLT unit" "0,1" bitfld.long 0x0 4. "F_OUT4,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 3. "F_OUT3,Signal channel x after TIM FLT unit" "0,1" bitfld.long 0x0 2. "F_OUT2,Signal channel x after TIM FLT unit" "0,1" newline bitfld.long 0x0 1. "F_OUT1,Signal channel x after TIM FLT unit" "0,1" bitfld.long 0x0 0. "F_OUT0,Signal channel x after TIM FLT unit" "0,1" line.long 0x4 "TIM7_IN_SRC," bitfld.long 0x4 30.--31. "MODE_7,Input source to Channel x" "0,1,2,3" bitfld.long 0x4 28.--29. "VAL_7,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 26.--27. "MODE_6,Input source to Channel x" "0,1,2,3" bitfld.long 0x4 24.--25. "VAL_6,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 22.--23. "MODE_5,Input source to Channel x" "0,1,2,3" bitfld.long 0x4 20.--21. "VAL_5,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 18.--19. "MODE_4,Input source to Channel x" "0,1,2,3" bitfld.long 0x4 16.--17. "VAL_4,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 14.--15. "MODE_3,Input source to Channel x" "0,1,2,3" bitfld.long 0x4 12.--13. "VAL_3,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 10.--11. "MODE_2,Input source to Channel x" "0,1,2,3" bitfld.long 0x4 8.--9. "VAL_2,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 6.--7. "MODE_1,Input source to Channel x" "0,1,2,3" bitfld.long 0x4 4.--5. "VAL_1,Value to be fed to channel [x]" "0,1,2,3" newline bitfld.long 0x4 2.--3. "MODE_0,Input source to Channel x" "0,1,2,3" bitfld.long 0x4 0.--1. "VAL_0,Value to be fed to channel [x]" "0,1,2,3" line.long 0x8 "TIM7_RST," bitfld.long 0x8 7. "RST_CH7,Software reset of channel [x]" "0,1" bitfld.long 0x8 6. "RST_CH6,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 5. "RST_CH5,Software reset of channel [x]" "0,1" bitfld.long 0x8 4. "RST_CH4,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 3. "RST_CH3,Software reset of channel [x]" "0,1" bitfld.long 0x8 2. "RST_CH2,Software reset of channel [x]" "0,1" newline bitfld.long 0x8 1. "RST_CH1,Software reset of channel [x]" "0,1" bitfld.long 0x8 0. "RST_CH0,Software reset of channel [x]" "0,1" group.long 0x1800++0x2F line.long 0x0 "ATOM7_CH0_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM7_CH0_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM7_CH0_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM7_CH0_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM7_CH0_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM7_CH0_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM7_CH0_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM7_CH0_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM7_CH0_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM7_CH0_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM7_CH0_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM7_CH0_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1834++0x3 line.long 0x0 "ATOM7_CH0_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1880++0x2F line.long 0x0 "ATOM7_CH1_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM7_CH1_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM7_CH1_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM7_CH1_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM7_CH1_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM7_CH1_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM7_CH1_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM7_CH1_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM7_CH1_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM7_CH1_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM7_CH1_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM7_CH1_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x18B4++0x3 line.long 0x0 "ATOM7_CH1_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1900++0x2F line.long 0x0 "ATOM7_CH2_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM7_CH2_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM7_CH2_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM7_CH2_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM7_CH2_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM7_CH2_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM7_CH2_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM7_CH2_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM7_CH2_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM7_CH2_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM7_CH2_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM7_CH2_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1934++0x3 line.long 0x0 "ATOM7_CH2_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1980++0x2F line.long 0x0 "ATOM7_CH3_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM7_CH3_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM7_CH3_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM7_CH3_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM7_CH3_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM7_CH3_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM7_CH3_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM7_CH3_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM7_CH3_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM7_CH3_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM7_CH3_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM7_CH3_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x19B4++0x3 line.long 0x0 "ATOM7_CH3_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A00++0x2F line.long 0x0 "ATOM7_CH4_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM7_CH4_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM7_CH4_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM7_CH4_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM7_CH4_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM7_CH4_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM7_CH4_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM7_CH4_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM7_CH4_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM7_CH4_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM7_CH4_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM7_CH4_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1A34++0x3 line.long 0x0 "ATOM7_CH4_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A80++0x2F line.long 0x0 "ATOM7_CH5_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM7_CH5_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM7_CH5_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM7_CH5_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM7_CH5_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM7_CH5_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM7_CH5_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM7_CH5_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM7_CH5_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM7_CH5_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM7_CH5_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM7_CH5_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1AB4++0x3 line.long 0x0 "ATOM7_CH5_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B00++0x2F line.long 0x0 "ATOM7_CH6_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM7_CH6_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM7_CH6_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM7_CH6_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM7_CH6_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM7_CH6_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM7_CH6_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM7_CH6_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM7_CH6_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM7_CH6_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM7_CH6_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM7_CH6_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1B34++0x3 line.long 0x0 "ATOM7_CH6_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B80++0x2F line.long 0x0 "ATOM7_CH7_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM7_CH7_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM7_CH7_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM7_CH7_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM7_CH7_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM7_CH7_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM7_CH7_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM7_CH7_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM7_CH7_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM7_CH7_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM7_CH7_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM7_CH7_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1BB4++0x3 line.long 0x0 "ATOM7_CH7_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1C40++0x1F line.long 0x0 "ATOM7_AGC_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 28.--29. "UPEN_CTRL6,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 26.--27. "UPEN_CTRL5,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 24.--25. "UPEN_CTRL4,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 22.--23. "UPEN_CTRL3,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 20.--21. "UPEN_CTRL2,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 16.--17. "UPEN_CTRL0,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 15. "RST_CH7,Software reset of channel [k]" "0,1" bitfld.long 0x0 14. "RST_CH6,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 13. "RST_CH5,Software reset of channel [k]" "0,1" bitfld.long 0x0 12. "RST_CH4,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel [k]" "0,1" bitfld.long 0x0 10. "RST_CH2,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 9. "RST_CH1,Software reset of channel [k]" "0,1" bitfld.long 0x0 8. "RST_CH0,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see AGC) to update the register ATOM[i]_AGC_ENDIS_STAT and ATOM[i]_AGC_OUTEN_STAT" "0,1" line.long 0x4 "ATOM7_AGC_ENDIS_CTRL," bitfld.long 0x4 14.--15. "ENDIS_CTRL7,ATOM channel [k] enable/disable update value." "0,1,2,3" bitfld.long 0x4 12.--13. "ENDIS_CTRL6,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 10.--11. "ENDIS_CTRL5,ATOM channel [k] enable/disable update value." "0,1,2,3" bitfld.long 0x4 8.--9. "ENDIS_CTRL4,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 6.--7. "ENDIS_CTRL3,ATOM channel [k] enable/disable update value." "0,1,2,3" bitfld.long 0x4 4.--5. "ENDIS_CTRL2,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_CTRL1,ATOM channel [k] enable/disable update value." "0,1,2,3" bitfld.long 0x4 0.--1. "ENDIS_CTRL0,ATOM channel [k] enable/disable update value." "0,1,2,3" line.long 0x8 "ATOM7_AGC_ENDIS_STAT," bitfld.long 0x8 14.--15. "ENDIS_STAT7,ATOM channel [k] enable/disable" "0,1,2,3" bitfld.long 0x8 12.--13. "ENDIS_STAT6,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 10.--11. "ENDIS_STAT5,ATOM channel [k] enable/disable" "0,1,2,3" bitfld.long 0x8 8.--9. "ENDIS_STAT4,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 6.--7. "ENDIS_STAT3,ATOM channel [k] enable/disable" "0,1,2,3" bitfld.long 0x8 4.--5. "ENDIS_STAT2,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 2.--3. "ENDIS_STAT1,ATOM channel [k] enable/disable" "0,1,2,3" bitfld.long 0x8 0.--1. "ENDIS_STAT0,ATOM channel [k] enable/disable" "0,1,2,3" line.long 0xC "ATOM7_AGC_ACT_TB," bitfld.long 0xC 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" bitfld.long 0xC 24. "TB_TRIG,Set trigger request" "0,1" newline hexmask.long.tbyte 0xC 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[x] x=0..2. If selected TBU_TS[x] value is in the interval [ATOM[i]_AGC_ACT_TB.ACT_TB-007FFFFFh ATOM[i]_AGC_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x10 "ATOM7_AGC_OUTEN_CTRL," bitfld.long 0x10 14.--15. "OUTEN_CTRL7,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" bitfld.long 0x10 12.--13. "OUTEN_CTRL6,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 10.--11. "OUTEN_CTRL5,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" bitfld.long 0x10 8.--9. "OUTEN_CTRL4,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 6.--7. "OUTEN_CTRL3,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" bitfld.long 0x10 4.--5. "OUTEN_CTRL2,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 2.--3. "OUTEN_CTRL1,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" bitfld.long 0x10 0.--1. "OUTEN_CTRL0,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" line.long 0x14 "ATOM7_AGC_OUTEN_STAT," bitfld.long 0x14 14.--15. "OUTEN_STAT7,Control/status of output ATOM_OUT [k]" "0,1,2,3" bitfld.long 0x14 12.--13. "OUTEN_STAT6,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 10.--11. "OUTEN_STAT5,Control/status of output ATOM_OUT [k]" "0,1,2,3" bitfld.long 0x14 8.--9. "OUTEN_STAT4,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 6.--7. "OUTEN_STAT3,Control/status of output ATOM_OUT [k]" "0,1,2,3" bitfld.long 0x14 4.--5. "OUTEN_STAT2,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 2.--3. "OUTEN_STAT1,Control/status of output ATOM_OUT [k]" "0,1,2,3" bitfld.long 0x14 0.--1. "OUTEN_STAT0,Control/status of output ATOM_OUT [k]" "0,1,2,3" line.long 0x18 "ATOM7_AGC_FUPD_CTRL," bitfld.long 0x18 30.--31. "RSTCN0_CH7,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" bitfld.long 0x18 28.--29. "RSTCN0_CH6,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 26.--27. "RSTCN0_CH5,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" bitfld.long 0x18 24.--25. "RSTCN0_CH4,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 22.--23. "RSTCN0_CH3,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" bitfld.long 0x18 20.--21. "RSTCN0_CH2,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 18.--19. "RSTCN0_CH1,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" bitfld.long 0x18 16.--17. "RSTCN0_CH0,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 14.--15. "FUPD_CTRL7,Force update of ATOM channel [k] operation registers" "0,1,2,3" bitfld.long 0x18 12.--13. "FUPD_CTRL6,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 10.--11. "FUPD_CTRL5,Force update of ATOM channel [k] operation registers" "0,1,2,3" bitfld.long 0x18 8.--9. "FUPD_CTRL4,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 6.--7. "FUPD_CTRL3,Force update of ATOM channel [k] operation registers" "0,1,2,3" bitfld.long 0x18 4.--5. "FUPD_CTRL2,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 2.--3. "FUPD_CTRL1,Force update of ATOM channel [k] operation registers" "0,1,2,3" bitfld.long 0x18 0.--1. "FUPD_CTRL0,Force update of ATOM channel [k] operation registers" "0,1,2,3" line.long 0x1C "ATOM7_AGC_INT_TRIG," bitfld.long 0x1C 14.--15. "INT_TRIG7,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" bitfld.long 0x1C 12.--13. "INT_TRIG6,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 10.--11. "INT_TRIG5,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" bitfld.long 0x1C 8.--9. "INT_TRIG4,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 6.--7. "INT_TRIG3,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" bitfld.long 0x1C 4.--5. "INT_TRIG2,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 2.--3. "INT_TRIG1,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" bitfld.long 0x1C 0.--1. "INT_TRIG0,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" group.long 0x2000++0x27 line.long 0x0 "MCS7_CH0_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS7_CH0_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS7_CH0_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS7_CH0_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS7_CH0_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS7_CH0_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS7_CH0_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS7_CH0_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS7_CH0_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS7_CH0_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x203C++0x3 line.long 0x0 "MCS7_CH0_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x20E0++0x17 line.long 0x0 "MCS7_CH0_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS7_CH0_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS7_CH0_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS7_CH0_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS7_CH0_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS7_CH0_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2100++0x27 line.long 0x0 "MCS7_CH1_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS7_CH1_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS7_CH1_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS7_CH1_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS7_CH1_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS7_CH1_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS7_CH1_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS7_CH1_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS7_CH1_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS7_CH1_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x213C++0x3 line.long 0x0 "MCS7_CH1_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x21E0++0x17 line.long 0x0 "MCS7_CH1_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS7_CH1_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS7_CH1_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS7_CH1_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS7_CH1_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS7_CH1_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2200++0x27 line.long 0x0 "MCS7_CH2_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS7_CH2_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS7_CH2_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS7_CH2_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS7_CH2_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS7_CH2_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS7_CH2_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS7_CH2_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS7_CH2_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS7_CH2_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x223C++0x3 line.long 0x0 "MCS7_CH2_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x22E0++0x17 line.long 0x0 "MCS7_CH2_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS7_CH2_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS7_CH2_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS7_CH2_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS7_CH2_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS7_CH2_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2300++0x27 line.long 0x0 "MCS7_CH3_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS7_CH3_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS7_CH3_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS7_CH3_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS7_CH3_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS7_CH3_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS7_CH3_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS7_CH3_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS7_CH3_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS7_CH3_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x233C++0x3 line.long 0x0 "MCS7_CH3_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x23E0++0x17 line.long 0x0 "MCS7_CH3_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS7_CH3_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS7_CH3_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS7_CH3_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS7_CH3_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS7_CH3_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2400++0x27 line.long 0x0 "MCS7_CH4_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS7_CH4_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS7_CH4_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS7_CH4_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS7_CH4_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS7_CH4_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS7_CH4_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS7_CH4_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS7_CH4_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS7_CH4_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x243C++0x3 line.long 0x0 "MCS7_CH4_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x24E0++0x17 line.long 0x0 "MCS7_CH4_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS7_CH4_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS7_CH4_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS7_CH4_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS7_CH4_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS7_CH4_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2500++0x27 line.long 0x0 "MCS7_CH5_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS7_CH5_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS7_CH5_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS7_CH5_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS7_CH5_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS7_CH5_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS7_CH5_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS7_CH5_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS7_CH5_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS7_CH5_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x253C++0x3 line.long 0x0 "MCS7_CH5_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x25E0++0x17 line.long 0x0 "MCS7_CH5_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS7_CH5_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS7_CH5_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS7_CH5_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS7_CH5_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS7_CH5_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2600++0x27 line.long 0x0 "MCS7_CH6_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS7_CH6_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS7_CH6_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS7_CH6_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS7_CH6_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS7_CH6_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS7_CH6_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS7_CH6_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS7_CH6_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS7_CH6_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x263C++0x3 line.long 0x0 "MCS7_CH6_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x26E0++0x17 line.long 0x0 "MCS7_CH6_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS7_CH6_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS7_CH6_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS7_CH6_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS7_CH6_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS7_CH6_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2700++0x27 line.long 0x0 "MCS7_CH7_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS7_CH7_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS7_CH7_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS7_CH7_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS7_CH7_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS7_CH7_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS7_CH7_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS7_CH7_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS7_CH7_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS7_CH7_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x273C++0x3 line.long 0x0 "MCS7_CH7_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x27E0++0x17 line.long 0x0 "MCS7_CH7_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS7_CH7_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS7_CH7_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS7_CH7_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS7_CH7_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS7_CH7_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2E28++0x7 line.long 0x0 "MCS7_CTRG," bitfld.long 0x0 23. "TRG23,Trigger bit o." "0,1" bitfld.long 0x0 22. "TRG22,Trigger bit o." "0,1" newline bitfld.long 0x0 21. "TRG21,Trigger bit o." "0,1" bitfld.long 0x0 20. "TRG20,Trigger bit o." "0,1" newline bitfld.long 0x0 19. "TRG19,Trigger bit o." "0,1" bitfld.long 0x0 18. "TRG18,Trigger bit o." "0,1" newline bitfld.long 0x0 17. "TRG17,Trigger bit o." "0,1" bitfld.long 0x0 16. "TRG16,Trigger bit o." "0,1" newline bitfld.long 0x0 15. "TRG15,Trigger bit n." "0,1" bitfld.long 0x0 14. "TRG14,Trigger bit n." "0,1" newline bitfld.long 0x0 13. "TRG13,Trigger bit n." "0,1" bitfld.long 0x0 12. "TRG12,Trigger bit n." "0,1" newline bitfld.long 0x0 11. "TRG11,Trigger bit n." "0,1" bitfld.long 0x0 10. "TRG10,Trigger bit n." "0,1" newline bitfld.long 0x0 9. "TRG9,Trigger bit n." "0,1" bitfld.long 0x0 8. "TRG8,Trigger bit n." "0,1" newline bitfld.long 0x0 7. "TRG7,Trigger bit m." "0,1" bitfld.long 0x0 6. "TRG6,Trigger bit m." "0,1" newline bitfld.long 0x0 5. "TRG5,Trigger bit m." "0,1" bitfld.long 0x0 4. "TRG4,Trigger bit m." "0,1" newline bitfld.long 0x0 3. "TRG3,Trigger bit m." "0,1" bitfld.long 0x0 2. "TRG2,Trigger bit m." "0,1" newline bitfld.long 0x0 1. "TRG1,Trigger bit m." "0,1" bitfld.long 0x0 0. "TRG0,Trigger bit m." "0,1" line.long 0x4 "MCS7_STRG," bitfld.long 0x4 23. "TRG23,Trigger bit k." "0,1" bitfld.long 0x4 22. "TRG22,Trigger bit k." "0,1" newline bitfld.long 0x4 21. "TRG21,Trigger bit k." "0,1" bitfld.long 0x4 20. "TRG20,Trigger bit k." "0,1" newline bitfld.long 0x4 19. "TRG19,Trigger bit k." "0,1" bitfld.long 0x4 18. "TRG18,Trigger bit k." "0,1" newline bitfld.long 0x4 17. "TRG17,Trigger bit k." "0,1" bitfld.long 0x4 16. "TRG16,Trigger bit k." "0,1" newline bitfld.long 0x4 15. "TRG15,Trigger bit k." "0,1" bitfld.long 0x4 14. "TRG14,Trigger bit k." "0,1" newline bitfld.long 0x4 13. "TRG13,Trigger bit k." "0,1" bitfld.long 0x4 12. "TRG12,Trigger bit k." "0,1" newline bitfld.long 0x4 11. "TRG11,Trigger bit k." "0,1" bitfld.long 0x4 10. "TRG10,Trigger bit k." "0,1" newline bitfld.long 0x4 9. "TRG9,Trigger bit k." "0,1" bitfld.long 0x4 8. "TRG8,Trigger bit k." "0,1" newline bitfld.long 0x4 7. "TRG7,Trigger bit k." "0,1" bitfld.long 0x4 6. "TRG6,Trigger bit k." "0,1" newline bitfld.long 0x4 5. "TRG5,Trigger bit k." "0,1" bitfld.long 0x4 4. "TRG4,Trigger bit k." "0,1" newline bitfld.long 0x4 3. "TRG3,Trigger bit k." "0,1" bitfld.long 0x4 2. "TRG2,Trigger bit k." "0,1" newline bitfld.long 0x4 1. "TRG1,Trigger bit k." "0,1" bitfld.long 0x4 0. "TRG0,Trigger bit k." "0,1" group.long 0x2F00++0x13 line.long 0x0 "MCS7_CTRL_STAT," bitfld.long 0x0 26. "HLT_AEIM_ERR,Halt on AEI bus master error." "0,1" bitfld.long 0x0 25. "EN_HVD,Enable Modified Harvard architecture." "0,1" newline bitfld.long 0x0 24. "EN_TIM_FOUT,Enable routing of TIM[i]_CH[x]_F_OUT signal." "0,1" bitfld.long 0x0 20.--22. "ERR_SRC_ID,Error source identifier." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "RAM_RST,RAM reset bit." "0,1" hexmask.long.byte 0x0 8.--11. 1. "SCD_CH,Channel selection for scheduling algorithm." newline bitfld.long 0x0 0.--1. "SCD_MODE,Select MCS scheduling mode" "0,1,2,3" line.long 0x4 "MCS7_RESET," bitfld.long 0x4 7. "RST7,Software reset of channel [k]" "0,1" bitfld.long 0x4 6. "RST6,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 5. "RST5,Software reset of channel [k]" "0,1" bitfld.long 0x4 4. "RST4,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 3. "RST3,Software reset of channel [k]" "0,1" bitfld.long 0x4 2. "RST2,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 1. "RST1,Software reset of channel [k]" "0,1" bitfld.long 0x4 0. "RST0,Software reset of channel [k]" "0,1" line.long 0x8 "MCS7_CAT," bitfld.long 0x8 7. "CAT7,Cancel ARU transfer of channel [k]." "0,1" bitfld.long 0x8 6. "CAT6,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 5. "CAT5,Cancel ARU transfer of channel [k]." "0,1" bitfld.long 0x8 4. "CAT4,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 3. "CAT3,Cancel ARU transfer of channel [k]." "0,1" bitfld.long 0x8 2. "CAT2,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 1. "CAT1,Cancel ARU transfer of channel [k]." "0,1" bitfld.long 0x8 0. "CAT0,Cancel ARU transfer of channel [k]." "0,1" line.long 0xC "MCS7_CWT," bitfld.long 0xC 7. "CWT7,Cancel waiting instruction for channel [k]." "0,1" bitfld.long 0xC 6. "CWT6,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 5. "CWT5,Cancel waiting instruction for channel [k]." "0,1" bitfld.long 0xC 4. "CWT4,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 3. "CWT3,Cancel waiting instruction for channel [k]." "0,1" bitfld.long 0xC 2. "CWT2,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 1. "CWT1,Cancel waiting instruction for channel [k]." "0,1" bitfld.long 0xC 0. "CWT0,Cancel waiting instruction for channel [k]." "0,1" line.long 0x10 "MCS7_ERR," bitfld.long 0x10 7. "ERR7,Error State of MCS-channel [k]." "0,1" bitfld.long 0x10 6. "ERR6,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 5. "ERR5,Error State of MCS-channel [k]." "0,1" bitfld.long 0x10 4. "ERR4,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 3. "ERR3,Error State of MCS-channel [k]." "0,1" bitfld.long 0x10 2. "ERR2,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 1. "ERR1,Error State of MCS-channel [k]." "0,1" bitfld.long 0x10 0. "ERR0,Error State of MCS-channel [k]." "0,1" group.long 0x2F1C++0x13 line.long 0x0 "MCS7_REG_PROT," bitfld.long 0x0 14.--15. "WPROT7,Register Write Protection of MCS-channel k." "0,1,2,3" bitfld.long 0x0 12.--13. "WPROT6,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 10.--11. "WPROT5,Register Write Protection of MCS-channel k." "0,1,2,3" bitfld.long 0x0 8.--9. "WPROT4,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 6.--7. "WPROT3,Register Write Protection of MCS-channel k." "0,1,2,3" bitfld.long 0x0 4.--5. "WPROT2,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 2.--3. "WPROT1,Register Write Protection of MCS-channel k." "0,1,2,3" bitfld.long 0x0 0.--1. "WPROT0,Register Write Protection of MCS-channel k." "0,1,2,3" line.long 0x4 "MCS7_SINT_IRQ_NOTIFY," bitfld.long 0x4 7. "S_IRQ7,Shared interrupt [k] notify flag." "0,1" bitfld.long 0x4 6. "S_IRQ6,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 5. "S_IRQ5,Shared interrupt [k] notify flag." "0,1" bitfld.long 0x4 4. "S_IRQ4,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 3. "S_IRQ3,Shared interrupt [k] notify flag." "0,1" bitfld.long 0x4 2. "S_IRQ2,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 1. "S_IRQ1,Shared interrupt [k] notify flag." "0,1" bitfld.long 0x4 0. "S_IRQ0,Shared interrupt [k] notify flag." "0,1" line.long 0x8 "MCS7_SINT_IRQ_EN," bitfld.long 0x8 7. "S_IRQ7_EN,Shared interrupt [k]" "0,1" bitfld.long 0x8 6. "S_IRQ6_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 5. "S_IRQ5_EN,Shared interrupt [k]" "0,1" bitfld.long 0x8 4. "S_IRQ4_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 3. "S_IRQ3_EN,Shared interrupt [k]" "0,1" bitfld.long 0x8 2. "S_IRQ2_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 1. "S_IRQ1_EN,Shared interrupt [k]" "0,1" bitfld.long 0x8 0. "S_IRQ0_EN,Shared interrupt [k]" "0,1" line.long 0xC "MCS7_SINT_IRQ_FORCINT," bitfld.long 0xC 7. "TRG_S_IRQ7,Trigger IRQ [k] in shared interrupt register" "0,1" bitfld.long 0xC 6. "TRG_S_IRQ6,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 5. "TRG_S_IRQ5,Trigger IRQ [k] in shared interrupt register" "0,1" bitfld.long 0xC 4. "TRG_S_IRQ4,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 3. "TRG_S_IRQ3,Trigger IRQ [k] in shared interrupt register" "0,1" bitfld.long 0xC 2. "TRG_S_IRQ2,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 1. "TRG_S_IRQ1,Trigger IRQ [k] in shared interrupt register" "0,1" bitfld.long 0xC 0. "TRG_S_IRQ0,Trigger IRQ [k] in shared interrupt register" "0,1" line.long 0x10 "MCS7_SINT_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x2F40++0x1B line.long 0x0 "MCS7_HBP0_CTRL," bitfld.long 0x0 17. "NOT,Logical negation of h-th hardware break point." "0,1" bitfld.long 0x0 16. "AND,Logical AND conjunction of h-th hardware break point." "0,1" newline bitfld.long 0x0 12.--14. "TYPE,Define type of h-th hardware break point." "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. "SCOPE,Define scope of h-th hardware break point." "0,1,2,3" newline bitfld.long 0x0 7. "EN_CH7,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 6. "EN_CH6,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 5. "EN_CH5,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 4. "EN_CH4,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 3. "EN_CH3,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 2. "EN_CH2,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 1. "EN_CH1,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 0. "EN_CH0,Enable h-th hardware break point for channel x." "0,1" line.long 0x4 "MCS7_HBP0_PATTERN," hexmask.long 0x4 0.--31. 1. "DATA,Define pattern or address of h-th hardware break point." line.long 0x8 "MCS7_HBP0_STATUS," bitfld.long 0x8 7. "HALT_CH7,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 6. "HALT_CH6,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 5. "HALT_CH5,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 4. "HALT_CH4,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 3. "HALT_CH3,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 2. "HALT_CH2,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 1. "HALT_CH1,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 0. "HALT_CH0,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" line.long 0xC "MCS7_HBP0_IRQ_NOTIFY," bitfld.long 0xC 0. "HBP_IRQ,Interrupt notify flag of the h-th hardware break point." "0,1" line.long 0x10 "MCS7_HBP0_IRQ_EN," bitfld.long 0x10 0. "HBP_IRQ_EN,Interrupt Enable bit of the h-th hardware break point." "0,1" line.long 0x14 "MCS7_HBP0_IRQ_FORCINT," bitfld.long 0x14 0. "TRG_HBP_IRQ,Trigger IRQ of the h-th hardware break point." "0,1" line.long 0x18 "MCS7_HBP0_IRQ_MODE," bitfld.long 0x18 0.--1. "IRQ_MODE,IRQ mode selection for all break point interrupts." "0,1,2,3" group.long 0x2F60++0x1B line.long 0x0 "MCS7_HBP1_CTRL," bitfld.long 0x0 17. "NOT,Logical negation of h-th hardware break point." "0,1" bitfld.long 0x0 16. "AND,Logical AND conjunction of h-th hardware break point." "0,1" newline bitfld.long 0x0 12.--14. "TYPE,Define type of h-th hardware break point." "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. "SCOPE,Define scope of h-th hardware break point." "0,1,2,3" newline bitfld.long 0x0 7. "EN_CH7,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 6. "EN_CH6,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 5. "EN_CH5,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 4. "EN_CH4,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 3. "EN_CH3,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 2. "EN_CH2,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 1. "EN_CH1,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 0. "EN_CH0,Enable h-th hardware break point for channel x." "0,1" line.long 0x4 "MCS7_HBP1_PATTERN," hexmask.long 0x4 0.--31. 1. "DATA,Define pattern or address of h-th hardware break point." line.long 0x8 "MCS7_HBP1_STATUS," bitfld.long 0x8 7. "HALT_CH7,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 6. "HALT_CH6,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 5. "HALT_CH5,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 4. "HALT_CH4,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 3. "HALT_CH3,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 2. "HALT_CH2,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 1. "HALT_CH1,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 0. "HALT_CH0,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" line.long 0xC "MCS7_HBP1_IRQ_NOTIFY," bitfld.long 0xC 0. "HBP_IRQ,Interrupt notify flag of the h-th hardware break point." "0,1" line.long 0x10 "MCS7_HBP1_IRQ_EN," bitfld.long 0x10 0. "HBP_IRQ_EN,Interrupt Enable bit of the h-th hardware break point." "0,1" line.long 0x14 "MCS7_HBP1_IRQ_FORCINT," bitfld.long 0x14 0. "TRG_HBP_IRQ,Trigger IRQ of the h-th hardware break point." "0,1" line.long 0x18 "MCS7_HBP1_IRQ_MODE," bitfld.long 0x18 0.--1. "IRQ_MODE,IRQ mode selection for all break point interrupts." "0,1,2,3" group.long 0x3000++0x13 line.long 0x0 "TIO7_G0_CH0_CTRL," bitfld.long 0x0 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x0 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x0 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x0 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x0 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x0 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x0 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x0 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x0 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x0 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x0 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x0 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x0 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x0 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x0 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x0 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x0 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x0 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x0 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x0 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x4 "TIO7_G0_CH0_IRQ_NOTIFY," bitfld.long 0x4 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x4 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x4 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x4 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x4 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x4 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x8 "TIO7_G0_CH0_IRQ_EN," bitfld.long 0x8 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x8 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x8 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x8 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x8 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x8 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0xC "TIO7_G0_CH0_IRQ_FORCINT," bitfld.long 0xC 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0xC 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0xC 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0xC 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0xC 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0xC 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x10 "TIO7_G0_CH0_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3020++0xB line.long 0x0 "TIO7_G0_CH0_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO7_G0_CH0_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO7_G0_CH0_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3030++0x23 line.long 0x0 "TIO7_G0_CH0_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO7_G0_CH0_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO7_G0_CH0_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO7_G0_CH0_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO7_G0_CH1_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO7_G0_CH1_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO7_G0_CH1_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO7_G0_CH1_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO7_G0_CH1_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3060++0xB line.long 0x0 "TIO7_G0_CH1_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO7_G0_CH1_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO7_G0_CH1_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3070++0x23 line.long 0x0 "TIO7_G0_CH1_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO7_G0_CH1_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO7_G0_CH1_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO7_G0_CH1_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO7_G0_CH2_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO7_G0_CH2_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO7_G0_CH2_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO7_G0_CH2_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO7_G0_CH2_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x30A0++0xB line.long 0x0 "TIO7_G0_CH2_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO7_G0_CH2_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO7_G0_CH2_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x30B0++0x23 line.long 0x0 "TIO7_G0_CH2_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO7_G0_CH2_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO7_G0_CH2_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO7_G0_CH2_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO7_G0_CH3_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO7_G0_CH3_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO7_G0_CH3_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO7_G0_CH3_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO7_G0_CH3_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x30E0++0xB line.long 0x0 "TIO7_G0_CH3_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO7_G0_CH3_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO7_G0_CH3_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x30F0++0x23 line.long 0x0 "TIO7_G0_CH3_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO7_G0_CH3_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO7_G0_CH3_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO7_G0_CH3_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO7_G0_CH4_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO7_G0_CH4_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO7_G0_CH4_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO7_G0_CH4_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO7_G0_CH4_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3120++0xB line.long 0x0 "TIO7_G0_CH4_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO7_G0_CH4_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO7_G0_CH4_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3130++0x23 line.long 0x0 "TIO7_G0_CH4_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO7_G0_CH4_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO7_G0_CH4_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO7_G0_CH4_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO7_G0_CH5_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO7_G0_CH5_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO7_G0_CH5_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO7_G0_CH5_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO7_G0_CH5_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3160++0xB line.long 0x0 "TIO7_G0_CH5_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO7_G0_CH5_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO7_G0_CH5_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3170++0x23 line.long 0x0 "TIO7_G0_CH5_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO7_G0_CH5_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO7_G0_CH5_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO7_G0_CH5_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO7_G0_CH6_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO7_G0_CH6_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO7_G0_CH6_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO7_G0_CH6_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO7_G0_CH6_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x31A0++0xB line.long 0x0 "TIO7_G0_CH6_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO7_G0_CH6_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO7_G0_CH6_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x31B0++0x23 line.long 0x0 "TIO7_G0_CH6_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO7_G0_CH6_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO7_G0_CH6_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO7_G0_CH6_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO7_G0_CH7_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO7_G0_CH7_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO7_G0_CH7_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO7_G0_CH7_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO7_G0_CH7_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x31E0++0xB line.long 0x0 "TIO7_G0_CH7_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO7_G0_CH7_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO7_G0_CH7_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x31F0++0x17 line.long 0x0 "TIO7_G0_CH7_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO7_G0_CH7_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO7_G0_CH7_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO7_G0_CH7_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO7_G0_ISEL0_CTRL1," bitfld.long 0x10 27. "WRITE_EN3,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" bitfld.long 0x10 26. "WRITE_EN2,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 25. "WRITE_EN1,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" bitfld.long 0x10 24. "WRITE_EN0,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 19. "OUT_SEL3,select signal for ISEL_OUT[k]" "0,1" bitfld.long 0x10 18. "OUT_SEL2,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x10 17. "OUT_SEL1,select signal for ISEL_OUT[k]" "0,1" bitfld.long 0x10 16. "OUT_SEL0,select signal for ISEL_OUT[k]" "0,1" newline hexmask.long.byte 0x10 12.--15. 1. "LUT2_3,2 bit Lookup table function for channel c=q*4+k" hexmask.long.byte 0x10 8.--11. 1. "LUT2_2,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x10 4.--7. 1. "LUT2_1,2 bit Lookup table function for channel c=q*4+k" hexmask.long.byte 0x10 0.--3. 1. "LUT2_0,2 bit Lookup table function for channel c=q*4+k" line.long 0x14 "TIO7_G0_ISEL0_CTRL2," bitfld.long 0x14 22. "LUT3IN_SEL2,select source for LUT3_IN[k] signal in quad = q" "0,1" bitfld.long 0x14 21. "LUT3IN_SEL1,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x14 20. "LUT3IN_SEL0,select source for LUT3_IN[k] signal in quad = q" "0,1" bitfld.long 0x14 16.--17. "QOUT_SEL,select source for ISEL_QOUT signal in quad = q" "0,1,2,3" newline hexmask.long.byte 0x14 0.--7. 1. "LUT3,3 bit Lookup table function for quad=q; channels q*4+2 .. q*4" group.long 0x3220++0x7 line.long 0x0 "TIO7_G0_ISEL1_CTRL1," bitfld.long 0x0 27. "WRITE_EN3,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" bitfld.long 0x0 26. "WRITE_EN2,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 25. "WRITE_EN1,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" bitfld.long 0x0 24. "WRITE_EN0,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 19. "OUT_SEL3,select signal for ISEL_OUT[k]" "0,1" bitfld.long 0x0 18. "OUT_SEL2,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x0 17. "OUT_SEL1,select signal for ISEL_OUT[k]" "0,1" bitfld.long 0x0 16. "OUT_SEL0,select signal for ISEL_OUT[k]" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "LUT2_3,2 bit Lookup table function for channel c=q*4+k" hexmask.long.byte 0x0 8.--11. 1. "LUT2_2,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x0 4.--7. 1. "LUT2_1,2 bit Lookup table function for channel c=q*4+k" hexmask.long.byte 0x0 0.--3. 1. "LUT2_0,2 bit Lookup table function for channel c=q*4+k" line.long 0x4 "TIO7_G0_ISEL1_CTRL2," bitfld.long 0x4 22. "LUT3IN_SEL2,select source for LUT3_IN[k] signal in quad = q" "0,1" bitfld.long 0x4 21. "LUT3IN_SEL1,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x4 20. "LUT3IN_SEL0,select source for LUT3_IN[k] signal in quad = q" "0,1" bitfld.long 0x4 16.--17. "QOUT_SEL,select source for ISEL_QOUT signal in quad = q" "0,1,2,3" newline hexmask.long.byte 0x4 0.--7. 1. "LUT3,3 bit Lookup table function for quad=q; channels q*4+2 .. q*4" group.long 0x3240++0x3 line.long 0x0 "TIO7_G0_OP_USAGE," bitfld.long 0x0 31. "WRITE_EN7,enable writing of configuration bit fields MODE[c]" "0,1" bitfld.long 0x0 30. "WRITE_EN6,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 29. "WRITE_EN5,enable writing of configuration bit fields MODE[c]" "0,1" bitfld.long 0x0 28. "WRITE_EN4,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 27. "WRITE_EN3,enable writing of configuration bit fields MODE[c]" "0,1" bitfld.long 0x0 26. "WRITE_EN2,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 25. "WRITE_EN1,enable writing of configuration bit fields MODE[c]" "0,1" bitfld.long 0x0 24. "WRITE_EN0,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 21.--23. "MODE7,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18.--20. "MODE6,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15.--17. "MODE5,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "MODE4,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9.--11. "MODE3,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--8. "MODE2,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "MODE1,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "MODE0,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" group.long 0x3C00++0x1F line.long 0x0 "TIO7_S," bitfld.long 0x0 7. "CH7,Value of channel x." "0,1" bitfld.long 0x0 6. "CH6,Value of channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Value of channel x." "0,1" bitfld.long 0x0 4. "CH4,Value of channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Value of channel x." "0,1" bitfld.long 0x0 2. "CH2,Value of channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Value of channel x." "0,1" bitfld.long 0x0 0. "CH0,Value of channel x." "0,1" line.long 0x4 "TIO7_O," bitfld.long 0x4 7. "CH7,Value driven on output of channel x." "0,1" bitfld.long 0x4 6. "CH6,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Value driven on output of channel x." "0,1" bitfld.long 0x4 4. "CH4,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Value driven on output of channel x." "0,1" bitfld.long 0x4 2. "CH2,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Value driven on output of channel x." "0,1" bitfld.long 0x4 0. "CH0,Value driven on output of channel x." "0,1" line.long 0x8 "TIO7_ENDIS," bitfld.long 0x8 7. "CH7,Enable/Disable request of channel x." "0,1" bitfld.long 0x8 6. "CH6,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Enable/Disable request of channel x." "0,1" bitfld.long 0x8 4. "CH4,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Enable/Disable request of channel x." "0,1" bitfld.long 0x8 2. "CH2,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Enable/Disable request of channel x." "0,1" bitfld.long 0x8 0. "CH0,Enable/Disable request of channel x." "0,1" line.long 0xC "TIO7_INVERT," bitfld.long 0xC 7. "CH7,Enable/Disable signal inversion of channel x." "0,1" bitfld.long 0xC 6. "CH6,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Enable/Disable signal inversion of channel x." "0,1" bitfld.long 0xC 4. "CH4,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Enable/Disable signal inversion of channel x." "0,1" bitfld.long 0xC 2. "CH2,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Enable/Disable signal inversion of channel x." "0,1" bitfld.long 0xC 0. "CH0,Enable/Disable signal inversion of channel x." "0,1" line.long 0x10 "TIO7_INPUT_MODE," bitfld.long 0x10 7. "CH7,Enable/Disable input mode of channel x." "0,1" bitfld.long 0x10 6. "CH6,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Enable/Disable input mode of channel x." "0,1" bitfld.long 0x10 4. "CH4,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Enable/Disable input mode of channel x." "0,1" bitfld.long 0x10 2. "CH2,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Enable/Disable input mode of channel x." "0,1" bitfld.long 0x10 0. "CH0,Enable/Disable input mode of channel x." "0,1" line.long 0x14 "TIO7_CYCLIC_MODE," bitfld.long 0x14 7. "CH7,Enable/Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 6. "CH6,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Enable/Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 4. "CH4,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Enable/Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 2. "CH2,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Enable/Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 0. "CH0,Enable/Disable cyclic mode of channel x." "0,1" line.long 0x18 "TIO7_TRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 6. "CH6,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 4. "CH4,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 2. "CH2,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 0. "CH0,enable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO7_PLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 6. "CH6,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 4. "CH4,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 2. "CH2,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 0. "CH0,enable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3C40++0x1F line.long 0x0 "TIO7_CS," bitfld.long 0x0 7. "CH7,Clear channel x." "0,1" bitfld.long 0x0 6. "CH6,Clear channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Clear channel x." "0,1" bitfld.long 0x0 4. "CH4,Clear channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Clear channel x." "0,1" bitfld.long 0x0 2. "CH2,Clear channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Clear channel x." "0,1" bitfld.long 0x0 0. "CH0,Clear channel x." "0,1" line.long 0x4 "TIO7_CO," bitfld.long 0x4 7. "CH7,Clear channel x." "0,1" bitfld.long 0x4 6. "CH6,Clear channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Clear channel x." "0,1" bitfld.long 0x4 4. "CH4,Clear channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Clear channel x." "0,1" bitfld.long 0x4 2. "CH2,Clear channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Clear channel x." "0,1" bitfld.long 0x4 0. "CH0,Clear channel x." "0,1" line.long 0x8 "TIO7_CENDIS," bitfld.long 0x8 7. "CH7,Disable request of channel x." "0,1" bitfld.long 0x8 6. "CH6,Disable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Disable request of channel x." "0,1" bitfld.long 0x8 4. "CH4,Disable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Disable request of channel x." "0,1" bitfld.long 0x8 2. "CH2,Disable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Disable request of channel x." "0,1" bitfld.long 0x8 0. "CH0,Disable request of channel x." "0,1" line.long 0xC "TIO7_CINVERT," bitfld.long 0xC 7. "CH7,Disable signal inversion of channel x." "0,1" bitfld.long 0xC 6. "CH6,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Disable signal inversion of channel x." "0,1" bitfld.long 0xC 4. "CH4,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Disable signal inversion of channel x." "0,1" bitfld.long 0xC 2. "CH2,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Disable signal inversion of channel x." "0,1" bitfld.long 0xC 0. "CH0,Disable signal inversion of channel x." "0,1" line.long 0x10 "TIO7_CINPUT_MODE," bitfld.long 0x10 7. "CH7,Disable input mode of channel x." "0,1" bitfld.long 0x10 6. "CH6,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Disable input mode of channel x." "0,1" bitfld.long 0x10 4. "CH4,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Disable input mode of channel x." "0,1" bitfld.long 0x10 2. "CH2,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Disable input mode of channel x." "0,1" bitfld.long 0x10 0. "CH0,Disable input mode of channel x." "0,1" line.long 0x14 "TIO7_CCYCLIC_MODE," bitfld.long 0x14 7. "CH7,Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 6. "CH6,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 4. "CH4,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 2. "CH2,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 0. "CH0,Disable cyclic mode of channel x." "0,1" line.long 0x18 "TIO7_CTRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,disable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 6. "CH6,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,disable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 4. "CH4,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,disable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 2. "CH2,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,disable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 0. "CH0,disable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO7_CPLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,disable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 6. "CH6,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,disable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 4. "CH4,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,disable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 2. "CH2,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,disable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 0. "CH0,disable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3C80++0x1F line.long 0x0 "TIO7_SS," bitfld.long 0x0 7. "CH7,Set channel x." "0,1" bitfld.long 0x0 6. "CH6,Set channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Set channel x." "0,1" bitfld.long 0x0 4. "CH4,Set channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Set channel x." "0,1" bitfld.long 0x0 2. "CH2,Set channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Set channel x." "0,1" bitfld.long 0x0 0. "CH0,Set channel x." "0,1" line.long 0x4 "TIO7_SO," bitfld.long 0x4 7. "CH7,Set channel x." "0,1" bitfld.long 0x4 6. "CH6,Set channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Set channel x." "0,1" bitfld.long 0x4 4. "CH4,Set channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Set channel x." "0,1" bitfld.long 0x4 2. "CH2,Set channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Set channel x." "0,1" bitfld.long 0x4 0. "CH0,Set channel x." "0,1" line.long 0x8 "TIO7_SENDIS," bitfld.long 0x8 7. "CH7,Enable request of channel x." "0,1" bitfld.long 0x8 6. "CH6,Enable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Enable request of channel x." "0,1" bitfld.long 0x8 4. "CH4,Enable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Enable request of channel x." "0,1" bitfld.long 0x8 2. "CH2,Enable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Enable request of channel x." "0,1" bitfld.long 0x8 0. "CH0,Enable request of channel x." "0,1" line.long 0xC "TIO7_SINVERT," bitfld.long 0xC 7. "CH7,Enable signal inversion of channel x." "0,1" bitfld.long 0xC 6. "CH6,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Enable signal inversion of channel x." "0,1" bitfld.long 0xC 4. "CH4,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Enable signal inversion of channel x." "0,1" bitfld.long 0xC 2. "CH2,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Enable signal inversion of channel x." "0,1" bitfld.long 0xC 0. "CH0,Enable signal inversion of channel x." "0,1" line.long 0x10 "TIO7_SINPUT_MODE," bitfld.long 0x10 7. "CH7,Enable input mode of channel x." "0,1" bitfld.long 0x10 6. "CH6,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Enable input mode of channel x." "0,1" bitfld.long 0x10 4. "CH4,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Enable input mode of channel x." "0,1" bitfld.long 0x10 2. "CH2,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Enable input mode of channel x." "0,1" bitfld.long 0x10 0. "CH0,Enable input mode of channel x." "0,1" line.long 0x14 "TIO7_SCYCLIC_MODE," bitfld.long 0x14 7. "CH7,Enable cyclic mode of channel x." "0,1" bitfld.long 0x14 6. "CH6,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Enable cyclic mode of channel x." "0,1" bitfld.long 0x14 4. "CH4,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Enable cyclic mode of channel x." "0,1" bitfld.long 0x14 2. "CH2,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Enable cyclic mode of channel x." "0,1" bitfld.long 0x14 0. "CH0,Enable cyclic mode of channel x." "0,1" line.long 0x18 "TIO7_STRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 6. "CH6,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 4. "CH4,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 2. "CH2,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 0. "CH0,enable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO7_SPLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 6. "CH6,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 4. "CH4,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 2. "CH2,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 0. "CH0,enable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3CC0++0x17 line.long 0x0 "TIO7_IS," bitfld.long 0x0 7. "CH7,Invert channel x." "0,1" bitfld.long 0x0 6. "CH6,Invert channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Invert channel x." "0,1" bitfld.long 0x0 4. "CH4,Invert channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Invert channel x." "0,1" bitfld.long 0x0 2. "CH2,Invert channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Invert channel x." "0,1" bitfld.long 0x0 0. "CH0,Invert channel x." "0,1" line.long 0x4 "TIO7_IO," bitfld.long 0x4 7. "CH7,Invert channel x." "0,1" bitfld.long 0x4 6. "CH6,Invert channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Invert channel x." "0,1" bitfld.long 0x4 4. "CH4,Invert channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Invert channel x." "0,1" bitfld.long 0x4 2. "CH2,Invert channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Invert channel x." "0,1" bitfld.long 0x4 0. "CH0,Invert channel x." "0,1" line.long 0x8 "TIO7_IENDIS," bitfld.long 0x8 7. "CH7,Toggle state request of channel x." "0,1" bitfld.long 0x8 6. "CH6,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Toggle state request of channel x." "0,1" bitfld.long 0x8 4. "CH4,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Toggle state request of channel x." "0,1" bitfld.long 0x8 2. "CH2,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Toggle state request of channel x." "0,1" bitfld.long 0x8 0. "CH0,Toggle state request of channel x." "0,1" line.long 0xC "TIO7_IINVERT," bitfld.long 0xC 7. "CH7,Invert signal inversion of channel x." "0,1" bitfld.long 0xC 6. "CH6,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Invert signal inversion of channel x." "0,1" bitfld.long 0xC 4. "CH4,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Invert signal inversion of channel x." "0,1" bitfld.long 0xC 2. "CH2,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Invert signal inversion of channel x." "0,1" bitfld.long 0xC 0. "CH0,Invert signal inversion of channel x." "0,1" line.long 0x10 "TIO7_IINPUT_MODE," bitfld.long 0x10 7. "CH7,Toggle input mode of channel x." "0,1" bitfld.long 0x10 6. "CH6,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Toggle input mode of channel x." "0,1" bitfld.long 0x10 4. "CH4,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Toggle input mode of channel x." "0,1" bitfld.long 0x10 2. "CH2,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Toggle input mode of channel x." "0,1" bitfld.long 0x10 0. "CH0,Toggle input mode of channel x." "0,1" line.long 0x14 "TIO7_ICYCLIC_MODE," bitfld.long 0x14 7. "CH7,Toggle cyclic mode of channel x." "0,1" bitfld.long 0x14 6. "CH6,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Toggle cyclic mode of channel x." "0,1" bitfld.long 0x14 4. "CH4,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Toggle cyclic mode of channel x." "0,1" bitfld.long 0x14 2. "CH2,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Toggle cyclic mode of channel x." "0,1" bitfld.long 0x14 0. "CH0,Toggle cyclic mode of channel x." "0,1" group.long 0x3D00++0x13 line.long 0x0 "TIO7_FUPD," bitfld.long 0x0 7. "CH7,issue immediately a signal pulse on the update signal of channel x" "0,1" bitfld.long 0x0 6. "CH6,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 5. "CH5,issue immediately a signal pulse on the update signal of channel x" "0,1" bitfld.long 0x0 4. "CH4,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 3. "CH3,issue immediately a signal pulse on the update signal of channel x" "0,1" bitfld.long 0x0 2. "CH2,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 1. "CH1,issue immediately a signal pulse on the update signal of channel x" "0,1" bitfld.long 0x0 0. "CH0,issue immediately a signal pulse on the update signal of channel x" "0,1" line.long 0x4 "TIO7_HW_CONF," bitfld.long 0x4 4. "TIO_PLUS,signals availablity of TIOplus functionality" "0,1" bitfld.long 0x4 0.--1. "NTIO_CH8,signals availablity of amount of channels" "0,1,2,3" line.long 0x8 "TIO7_RSEL_CTRL1," bitfld.long 0x8 28. "SEL_CLKEN7_0,select source of RS_CLKEN7[g][7] for channels g*8 .. g*8+7" "0,1" bitfld.long 0x8 24. "SEL_CLKEN6_0,select source of RS_CLKEN[g][6] for channels g*8 .. g*8+7" "0,1" line.long 0xC "TIO7_RSEL_CTRL2," bitfld.long 0xC 8. "SEL_TB2_0,select source of RS_TB2[g] for channels g*8 .. g*8+7" "0,1" bitfld.long 0xC 4. "SEL_TB1_0,select source of RS_TB1[g] for channels g*8 .. g*8+7" "0,1" line.long 0x10 "TIO7_PL_SWRST," bitfld.long 0x10 7. "CH7,reset TIO_Plus resources of channel x" "0,1" bitfld.long 0x10 6. "CH6,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 5. "CH5,reset TIO_Plus resources of channel x" "0,1" bitfld.long 0x10 4. "CH4,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 3. "CH3,reset TIO_Plus resources of channel x" "0,1" bitfld.long 0x10 2. "CH2,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 1. "CH1,reset TIO_Plus resources of channel x" "0,1" bitfld.long 0x10 0. "CH0,reset TIO_Plus resources of channel x" "0,1" group.long 0x4000++0x4F line.long 0x0 "CCM7_ARP0_CTRL," bitfld.long 0x0 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x0 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x0 0.--15. 1. "ADDR,ARP base address." line.long 0x4 "CCM7_ARP0_PROT," bitfld.long 0x4 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x4 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x4 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x4 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x4 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x8 "CCM7_ARP1_CTRL," bitfld.long 0x8 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x8 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x8 0.--15. 1. "ADDR,ARP base address." line.long 0xC "CCM7_ARP1_PROT," bitfld.long 0xC 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0xC 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0xC 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0xC 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0xC 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x10 "CCM7_ARP2_CTRL," bitfld.long 0x10 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x10 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x10 0.--15. 1. "ADDR,ARP base address." line.long 0x14 "CCM7_ARP2_PROT," bitfld.long 0x14 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x14 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x14 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x14 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x14 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x18 "CCM7_ARP3_CTRL," bitfld.long 0x18 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x18 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x18 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x18 0.--15. 1. "ADDR,ARP base address." line.long 0x1C "CCM7_ARP3_PROT," bitfld.long 0x1C 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x1C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x1C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x1C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x1C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x20 "CCM7_ARP4_CTRL," bitfld.long 0x20 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x20 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x20 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x20 0.--15. 1. "ADDR,ARP base address." line.long 0x24 "CCM7_ARP4_PROT," bitfld.long 0x24 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x24 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x24 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x24 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x24 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x28 "CCM7_ARP5_CTRL," bitfld.long 0x28 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x28 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x28 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x28 0.--15. 1. "ADDR,ARP base address." line.long 0x2C "CCM7_ARP5_PROT," bitfld.long 0x2C 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x2C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x2C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x2C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x2C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x30 "CCM7_ARP6_CTRL," bitfld.long 0x30 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x30 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x30 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x30 0.--15. 1. "ADDR,ARP base address." line.long 0x34 "CCM7_ARP6_PROT," bitfld.long 0x34 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x34 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x34 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x34 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x34 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x38 "CCM7_ARP7_CTRL," bitfld.long 0x38 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x38 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x38 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x38 0.--15. 1. "ADDR,ARP base address." line.long 0x3C "CCM7_ARP7_PROT," bitfld.long 0x3C 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x3C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x3C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x3C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x3C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x40 "CCM7_ARP8_CTRL," bitfld.long 0x40 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x40 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x40 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x40 0.--15. 1. "ADDR,ARP base address." line.long 0x44 "CCM7_ARP8_PROT," bitfld.long 0x44 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x44 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x44 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x44 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x44 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x48 "CCM7_ARP9_CTRL," bitfld.long 0x48 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x48 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x48 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x48 0.--15. 1. "ADDR,ARP base address." line.long 0x4C "CCM7_ARP9_PROT," bitfld.long 0x4C 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x4C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x4C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x4C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x4C 0. "WPROT0,Write Protection MCS channel x." "0,1" group.long 0x41CC++0x3 line.long 0x0 "CCM7_TIO_G0_OUT," bitfld.long 0x0 31. "TIO_G1_OUT_N7,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" bitfld.long 0x0 30. "TIO_G1_OUT_N6,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 29. "TIO_G1_OUT_N5,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" bitfld.long 0x0 28. "TIO_G1_OUT_N4,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 27. "TIO_G1_OUT_N3,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" bitfld.long 0x0 26. "TIO_G1_OUT_N2,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 25. "TIO_G1_OUT_N1,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" bitfld.long 0x0 24. "TIO_G1_OUT_N0,Output level snapshot of TIO[i]_G1_OUT_N channel [c]" "0,1" newline bitfld.long 0x0 23. "TIO_G0_OUT_N7,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" bitfld.long 0x0 22. "TIO_G0_OUT_N6,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 21. "TIO_G0_OUT_N5,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" bitfld.long 0x0 20. "TIO_G0_OUT_N4,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 19. "TIO_G0_OUT_N3,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" bitfld.long 0x0 18. "TIO_G0_OUT_N2,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 17. "TIO_G0_OUT_N1,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" bitfld.long 0x0 16. "TIO_G0_OUT_N0,Output level snapshot of TIO[i]_G0_OUT_N channel" "0,1" newline bitfld.long 0x0 15. "TIO_G1_OUT7,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" bitfld.long 0x0 14. "TIO_G1_OUT6,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 13. "TIO_G1_OUT5,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" bitfld.long 0x0 12. "TIO_G1_OUT4,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 11. "TIO_G1_OUT3,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" bitfld.long 0x0 10. "TIO_G1_OUT2,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 9. "TIO_G1_OUT1,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" bitfld.long 0x0 8. "TIO_G1_OUT0,Output level snapshot of TIO[i]_G1_OUT channel [c]" "0,1" newline bitfld.long 0x0 7. "TIO_G0_OUT7,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" bitfld.long 0x0 6. "TIO_G0_OUT6,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 5. "TIO_G0_OUT5,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" bitfld.long 0x0 4. "TIO_G0_OUT4,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 3. "TIO_G0_OUT3,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" bitfld.long 0x0 2. "TIO_G0_OUT2,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" newline bitfld.long 0x0 1. "TIO_G0_OUT1,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" bitfld.long 0x0 0. "TIO_G0_OUT0,Output level snapshot of TIO[i]_G0_OUT channel [c]" "0,1" group.long 0x41D4++0x13 line.long 0x0 "CCM7_HW_CONF2," bitfld.long 0x0 18. "AXIM_DATA_SIZE,Defines the data bus width of the AXI master interface" "0,1" bitfld.long 0x0 16. "AXIS_DATA_SIZE,Defines the data bus width of the AXI slave interface" "0,1" newline bitfld.long 0x0 9. "TIO_OUT_RST,TIO_OUT reset level" "0,1" bitfld.long 0x0 7. "AXIM_POSTED_WRITE,Write transaction without response" "0,1" newline bitfld.long 0x0 6. "AXIM_SEC_ACC,Secure AXI master access constant" "0,1" bitfld.long 0x0 5. "AXIM_PRIV_ACC,Privileged AXI master access constant" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "AXIM_ID_WIDTH,Defines which LSB of AXIM_ID are send to the bus" line.long 0x4 "CCM7_AEIM_STA," bitfld.long 0x4 24.--25. "AEIM_XPT_STA,AEIM Exception status." "0,1,2,3" hexmask.long.word 0x4 0.--15. 1. "AEIM_XPT_ADDR,Exception Address." line.long 0x8 "CCM7_HW_CONF," bitfld.long 0x8 31. "AEI_RDATA_PIPELINE_STAGE,Read data pipeline stage implemented" "0,1" bitfld.long 0x8 30. "AEI_ADDR_PIPELINE_STAGE,Address pipeline stage implemented" "0,1" newline bitfld.long 0x8 29. "INT_CLK_EN_GEN,Internal clock enable generation" "0,1" hexmask.long.byte 0x8 24.--28. 1. "TOM_TRIG_INTCHAIN,TOM internal trigger chain length without synchronization register" newline hexmask.long.byte 0x8 20.--23. 1. "ATOM_TRIG_INTCHAIN,ATOM internal trigger chain length without synchronization register" bitfld.long 0x8 19. "IRQ_MODE_SINGLE_PULSE,Signalize availability of Single Pulse IRQ mode" "0,1" newline bitfld.long 0x8 18. "IRQ_MODE_PULSE_NOTIFY,Signalize availability of Pulse Notoify IRQ mode" "0,1" bitfld.long 0x8 17. "IRQ_MODE_PULSE,Signalize availability of Pulse IRQ mode" "0,1" newline bitfld.long 0x8 16. "IRQ_MODE_LEVEL,Signalize availability of Level IRQ mode" "0,1" bitfld.long 0x8 15. "RESET_ACTIVE,Active level of asynchronous reset" "0,1" newline bitfld.long 0x8 13. "ERM,Enable RAM1 MSB for available MCS modules" "0,1" bitfld.long 0x8 12. "RAM_INIT_RST,RAM initialization from reset" "0,1" newline bitfld.long 0x8 9.--11. "TOM_TRIG_CHAIN,TOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8. "TOM_OUT_RST,TOM_OUT reset level" "0,1" newline bitfld.long 0x8 5.--7. "ATOM_TRIG_CHAIN,ATOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "ATOM_OUT_RST,ATOM_OUT reset level" "0,1" newline bitfld.long 0x8 3. "CFG_CLOCK_RATE,Clocks per ARU transfer" "0,1" bitfld.long 0x8 2. "SYNC_INPUT_REG,Additional pipelined stage in synchronous bridge mode" "0,1" newline bitfld.long 0x8 1. "BRIDGE_MODE_RST,Bridge mode after reset" "0,1" bitfld.long 0x8 0. "GRSTEN,Global Reset Enable" "0,1" line.long 0xC "CCM7_TIM_AUX_IN_SRC," bitfld.long 0xC 23. "SEL_OUT_N_CH7,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" bitfld.long 0xC 22. "SEL_OUT_N_CH6,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 21. "SEL_OUT_N_CH5,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" bitfld.long 0xC 20. "SEL_OUT_N_CH4,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 19. "SEL_OUT_N_CH3,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" bitfld.long 0xC 18. "SEL_OUT_N_CH2,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 17. "SEL_OUT_N_CH1,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" bitfld.long 0xC 16. "SEL_OUT_N_CH0,Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i] channel [x]" "0,1" newline bitfld.long 0xC 7. "SRC_CH7,Defines AUX_IN source of TIM[i] channel 7" "0,1" bitfld.long 0xC 6. "SRC_CH6,Defines AUX_IN source of TIM[i] channel 6" "0,1" newline bitfld.long 0xC 5. "SRC_CH5,Defines AUX_IN source of TIM[i] channel 5" "0,1" bitfld.long 0xC 4. "SRC_CH4,Defines AUX_IN source of TIM[i] channel 4" "0,1" newline bitfld.long 0xC 3. "SRC_CH3,Defines AUX_IN source of TIM[i] channel 3" "0,1" bitfld.long 0xC 2. "SRC_CH2,Defines AUX_IN source of TIM[i] channel 2" "0,1" newline bitfld.long 0xC 1. "SRC_CH1,Defines AUX_IN source of TIM[i] channel 1" "0,1" bitfld.long 0xC 0. "SRC_CH0,Defines AUX_IN source of TIM[i] channel 0" "0,1" line.long 0x10 "CCM7_EXT_CAP_EN," bitfld.long 0x10 15. "TIM_IP1_EXT_CAP_EN7,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" bitfld.long 0x10 14. "TIM_IP1_EXT_CAP_EN6,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 13. "TIM_IP1_EXT_CAP_EN5,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" bitfld.long 0x10 12. "TIM_IP1_EXT_CAP_EN4,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 11. "TIM_IP1_EXT_CAP_EN3,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" bitfld.long 0x10 10. "TIM_IP1_EXT_CAP_EN2,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 9. "TIM_IP1_EXT_CAP_EN1,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" bitfld.long 0x10 8. "TIM_IP1_EXT_CAP_EN0,TIM[i+1]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 7. "TIM_I_EXT_CAP_EN7,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" bitfld.long 0x10 6. "TIM_I_EXT_CAP_EN6,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 5. "TIM_I_EXT_CAP_EN5,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" bitfld.long 0x10 4. "TIM_I_EXT_CAP_EN4,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 3. "TIM_I_EXT_CAP_EN3,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" bitfld.long 0x10 2. "TIM_I_EXT_CAP_EN2,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" newline bitfld.long 0x10 1. "TIM_I_EXT_CAP_EN1,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" bitfld.long 0x10 0. "TIM_I_EXT_CAP_EN0,TIM[i]_EXT_CAPTURE signal [x] forwarding enable" "0,1" group.long 0x41EC++0x7 line.long 0x0 "CCM7_ATOM_OUT," bitfld.long 0x0 31. "ATOM_IP1_OUT_N7,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" bitfld.long 0x0 30. "ATOM_IP1_OUT_N6,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 29. "ATOM_IP1_OUT_N5,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" bitfld.long 0x0 28. "ATOM_IP1_OUT_N4,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 27. "ATOM_IP1_OUT_N3,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" bitfld.long 0x0 26. "ATOM_IP1_OUT_N2,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 25. "ATOM_IP1_OUT_N1,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" bitfld.long 0x0 24. "ATOM_IP1_OUT_N0,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 23. "ATOM_IP1_OUT7,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" bitfld.long 0x0 22. "ATOM_IP1_OUT6,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 21. "ATOM_IP1_OUT5,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" bitfld.long 0x0 20. "ATOM_IP1_OUT4,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 19. "ATOM_IP1_OUT3,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" bitfld.long 0x0 18. "ATOM_IP1_OUT2,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 17. "ATOM_IP1_OUT1,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" bitfld.long 0x0 16. "ATOM_IP1_OUT0,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 15. "ATOM_I_OUT_N7,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 14. "ATOM_I_OUT_N6,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 13. "ATOM_I_OUT_N5,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 12. "ATOM_I_OUT_N4,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 11. "ATOM_I_OUT_N3,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 10. "ATOM_I_OUT_N2,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 9. "ATOM_I_OUT_N1,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 8. "ATOM_I_OUT_N0,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 7. "ATOM_I_OUT7,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 6. "ATOM_I_OUT6,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 5. "ATOM_I_OUT5,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 4. "ATOM_I_OUT4,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 3. "ATOM_I_OUT3,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 2. "ATOM_I_OUT2,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 1. "ATOM_I_OUT1,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 0. "ATOM_I_OUT0,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" line.long 0x4 "CCM7_CMU_CLK_CFG," bitfld.long 0x4 28.--29. "CLK7_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x4 24.--25. "CLK6_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 20.--21. "CLK5_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x4 16.--17. "CLK4_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 12.--13. "CLK3_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x4 8.--9. "CLK2_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 4.--5. "CLK1_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x4 0.--1. "CLK0_SRC,Clock y source signal selector" "0,1,2,3" group.long 0x41F8++0x7 line.long 0x0 "CCM7_CFG," bitfld.long 0x0 31. "TBU_DIR2,DIR1 input signal of module TBU timebase [z]." "0,1" bitfld.long 0x0 30. "TBU_DIR1,DIR1 input signal of module TBU timebase [z]." "0,1" newline bitfld.long 0x0 16.--17. "CLS_CLK_DIV,Cluster Clock Divider." "0,1,2,3" bitfld.long 0x0 8. "EN_TIO_DTM,Enable TIO and connected DTM" "0,1" newline bitfld.long 0x0 7. "EN_CMP_MON,Enable CMP and MON" "0,1" bitfld.long 0x0 6. "EN_PSM,Enable PSM" "0,1" newline bitfld.long 0x0 5. "EN_BRC,Enable BRC" "0,1" bitfld.long 0x0 4. "EN_DPLL_MAP,Enable DPLL and MAP" "0,1" newline bitfld.long 0x0 3. "EN_MCS,Enable MCS" "0,1" bitfld.long 0x0 2. "EN_ATOM_ADTM,Enable ATOM and ADTM" "0,1" newline bitfld.long 0x0 1. "EN_TOM_SPE_TDTM,Enable TOM SPE and TDTM" "0,1" bitfld.long 0x0 0. "EN_TIM,Enable TIM" "0,1" line.long 0x4 "CCM7_PROT," bitfld.long 0x4 0. "CLS_PROT,Cluster Protection" "0,1" group.long 0x5000++0xB line.long 0x0 "AXIM7_FREE," bitfld.long 0x0 3. "FREE3,This bit represents the allocation status of the slot [t]" "0,1" bitfld.long 0x0 2. "FREE2,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 1. "FREE1,This bit represents the allocation status of the slot [t]" "0,1" bitfld.long 0x0 0. "FREE0,This bit represents the allocation status of the slot [t]" "0,1" line.long 0x4 "AXIM7_REQUEST," hexmask.long.byte 0x4 24.--31. 1. "REQID,This bit field shows the new allocated slot as binary encoded index. If no slot could be allocated this bit field is read as all 1 (0xff)." bitfld.long 0x4 3. "REQ1HOT3,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 2. "REQ1HOT2,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" bitfld.long 0x4 1. "REQ1HOT1,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 0. "REQ1HOT0,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" line.long 0x8 "AXIM7_RELEASE," bitfld.long 0x8 3. "RELREQ3,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" bitfld.long 0x8 2. "RELREQ2,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 1. "RELREQ1,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" bitfld.long 0x8 0. "RELREQ0,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" group.long 0x5020++0x3 line.long 0x0 "AXIM7_SLOT0_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5028++0x3 line.long 0x0 "AXIM7_SLOT0_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5030++0xB line.long 0x0 "AXIM7_SLOT0_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM7_SLOT0_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM7_SLOT0_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5040++0x3 line.long 0x0 "AXIM7_SLOT1_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5048++0x3 line.long 0x0 "AXIM7_SLOT1_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5050++0xB line.long 0x0 "AXIM7_SLOT1_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM7_SLOT1_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM7_SLOT1_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5060++0x3 line.long 0x0 "AXIM7_SLOT2_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5068++0x3 line.long 0x0 "AXIM7_SLOT2_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5070++0xB line.long 0x0 "AXIM7_SLOT2_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM7_SLOT2_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM7_SLOT2_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5080++0x3 line.long 0x0 "AXIM7_SLOT3_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5088++0x3 line.long 0x0 "AXIM7_SLOT3_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5090++0xB line.long 0x0 "AXIM7_SLOT3_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM7_SLOT3_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM7_SLOT3_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" repeat 16384. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10000)++0x3 line.long 0x0 "MCS7_MEM[$1]," hexmask.long 0x0 0.--31. 1. "DATA,MCS memory location." repeat.end tree.end tree "GTM_CLS8" base ad:0x74100000 group.long 0x1800++0x2F line.long 0x0 "ATOM8_CH0_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM8_CH0_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM8_CH0_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM8_CH0_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM8_CH0_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM8_CH0_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM8_CH0_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM8_CH0_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM8_CH0_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM8_CH0_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM8_CH0_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM8_CH0_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1834++0x3 line.long 0x0 "ATOM8_CH0_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1880++0x2F line.long 0x0 "ATOM8_CH1_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM8_CH1_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM8_CH1_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM8_CH1_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM8_CH1_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM8_CH1_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM8_CH1_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM8_CH1_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM8_CH1_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM8_CH1_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM8_CH1_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM8_CH1_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x18B4++0x3 line.long 0x0 "ATOM8_CH1_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1900++0x2F line.long 0x0 "ATOM8_CH2_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM8_CH2_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM8_CH2_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM8_CH2_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM8_CH2_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM8_CH2_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM8_CH2_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM8_CH2_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM8_CH2_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM8_CH2_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM8_CH2_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM8_CH2_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1934++0x3 line.long 0x0 "ATOM8_CH2_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1980++0x2F line.long 0x0 "ATOM8_CH3_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM8_CH3_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM8_CH3_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM8_CH3_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM8_CH3_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM8_CH3_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM8_CH3_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM8_CH3_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM8_CH3_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM8_CH3_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM8_CH3_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM8_CH3_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x19B4++0x3 line.long 0x0 "ATOM8_CH3_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A00++0x2F line.long 0x0 "ATOM8_CH4_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM8_CH4_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM8_CH4_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM8_CH4_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM8_CH4_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM8_CH4_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM8_CH4_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM8_CH4_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM8_CH4_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM8_CH4_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM8_CH4_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM8_CH4_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1A34++0x3 line.long 0x0 "ATOM8_CH4_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A80++0x2F line.long 0x0 "ATOM8_CH5_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM8_CH5_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM8_CH5_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM8_CH5_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM8_CH5_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM8_CH5_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM8_CH5_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM8_CH5_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM8_CH5_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM8_CH5_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM8_CH5_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM8_CH5_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1AB4++0x3 line.long 0x0 "ATOM8_CH5_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B00++0x2F line.long 0x0 "ATOM8_CH6_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM8_CH6_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM8_CH6_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM8_CH6_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM8_CH6_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM8_CH6_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM8_CH6_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM8_CH6_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM8_CH6_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM8_CH6_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM8_CH6_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM8_CH6_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1B34++0x3 line.long 0x0 "ATOM8_CH6_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B80++0x2F line.long 0x0 "ATOM8_CH7_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM8_CH7_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM8_CH7_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM8_CH7_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM8_CH7_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM8_CH7_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM8_CH7_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM8_CH7_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM8_CH7_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM8_CH7_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM8_CH7_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM8_CH7_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1BB4++0x3 line.long 0x0 "ATOM8_CH7_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1C40++0x1F line.long 0x0 "ATOM8_AGC_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 28.--29. "UPEN_CTRL6,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 26.--27. "UPEN_CTRL5,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 24.--25. "UPEN_CTRL4,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 22.--23. "UPEN_CTRL3,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 20.--21. "UPEN_CTRL2,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 16.--17. "UPEN_CTRL0,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 15. "RST_CH7,Software reset of channel [k]" "0,1" bitfld.long 0x0 14. "RST_CH6,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 13. "RST_CH5,Software reset of channel [k]" "0,1" bitfld.long 0x0 12. "RST_CH4,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel [k]" "0,1" bitfld.long 0x0 10. "RST_CH2,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 9. "RST_CH1,Software reset of channel [k]" "0,1" bitfld.long 0x0 8. "RST_CH0,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see AGC) to update the register ATOM[i]_AGC_ENDIS_STAT and ATOM[i]_AGC_OUTEN_STAT" "0,1" line.long 0x4 "ATOM8_AGC_ENDIS_CTRL," bitfld.long 0x4 14.--15. "ENDIS_CTRL7,ATOM channel [k] enable/disable update value." "0,1,2,3" bitfld.long 0x4 12.--13. "ENDIS_CTRL6,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 10.--11. "ENDIS_CTRL5,ATOM channel [k] enable/disable update value." "0,1,2,3" bitfld.long 0x4 8.--9. "ENDIS_CTRL4,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 6.--7. "ENDIS_CTRL3,ATOM channel [k] enable/disable update value." "0,1,2,3" bitfld.long 0x4 4.--5. "ENDIS_CTRL2,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_CTRL1,ATOM channel [k] enable/disable update value." "0,1,2,3" bitfld.long 0x4 0.--1. "ENDIS_CTRL0,ATOM channel [k] enable/disable update value." "0,1,2,3" line.long 0x8 "ATOM8_AGC_ENDIS_STAT," bitfld.long 0x8 14.--15. "ENDIS_STAT7,ATOM channel [k] enable/disable" "0,1,2,3" bitfld.long 0x8 12.--13. "ENDIS_STAT6,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 10.--11. "ENDIS_STAT5,ATOM channel [k] enable/disable" "0,1,2,3" bitfld.long 0x8 8.--9. "ENDIS_STAT4,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 6.--7. "ENDIS_STAT3,ATOM channel [k] enable/disable" "0,1,2,3" bitfld.long 0x8 4.--5. "ENDIS_STAT2,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 2.--3. "ENDIS_STAT1,ATOM channel [k] enable/disable" "0,1,2,3" bitfld.long 0x8 0.--1. "ENDIS_STAT0,ATOM channel [k] enable/disable" "0,1,2,3" line.long 0xC "ATOM8_AGC_ACT_TB," bitfld.long 0xC 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" bitfld.long 0xC 24. "TB_TRIG,Set trigger request" "0,1" newline hexmask.long.tbyte 0xC 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[x] x=0..2. If selected TBU_TS[x] value is in the interval [ATOM[i]_AGC_ACT_TB.ACT_TB-007FFFFFh ATOM[i]_AGC_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x10 "ATOM8_AGC_OUTEN_CTRL," bitfld.long 0x10 14.--15. "OUTEN_CTRL7,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" bitfld.long 0x10 12.--13. "OUTEN_CTRL6,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 10.--11. "OUTEN_CTRL5,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" bitfld.long 0x10 8.--9. "OUTEN_CTRL4,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 6.--7. "OUTEN_CTRL3,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" bitfld.long 0x10 4.--5. "OUTEN_CTRL2,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 2.--3. "OUTEN_CTRL1,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" bitfld.long 0x10 0.--1. "OUTEN_CTRL0,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" line.long 0x14 "ATOM8_AGC_OUTEN_STAT," bitfld.long 0x14 14.--15. "OUTEN_STAT7,Control/status of output ATOM_OUT [k]" "0,1,2,3" bitfld.long 0x14 12.--13. "OUTEN_STAT6,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 10.--11. "OUTEN_STAT5,Control/status of output ATOM_OUT [k]" "0,1,2,3" bitfld.long 0x14 8.--9. "OUTEN_STAT4,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 6.--7. "OUTEN_STAT3,Control/status of output ATOM_OUT [k]" "0,1,2,3" bitfld.long 0x14 4.--5. "OUTEN_STAT2,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 2.--3. "OUTEN_STAT1,Control/status of output ATOM_OUT [k]" "0,1,2,3" bitfld.long 0x14 0.--1. "OUTEN_STAT0,Control/status of output ATOM_OUT [k]" "0,1,2,3" line.long 0x18 "ATOM8_AGC_FUPD_CTRL," bitfld.long 0x18 30.--31. "RSTCN0_CH7,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" bitfld.long 0x18 28.--29. "RSTCN0_CH6,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 26.--27. "RSTCN0_CH5,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" bitfld.long 0x18 24.--25. "RSTCN0_CH4,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 22.--23. "RSTCN0_CH3,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" bitfld.long 0x18 20.--21. "RSTCN0_CH2,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 18.--19. "RSTCN0_CH1,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" bitfld.long 0x18 16.--17. "RSTCN0_CH0,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 14.--15. "FUPD_CTRL7,Force update of ATOM channel [k] operation registers" "0,1,2,3" bitfld.long 0x18 12.--13. "FUPD_CTRL6,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 10.--11. "FUPD_CTRL5,Force update of ATOM channel [k] operation registers" "0,1,2,3" bitfld.long 0x18 8.--9. "FUPD_CTRL4,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 6.--7. "FUPD_CTRL3,Force update of ATOM channel [k] operation registers" "0,1,2,3" bitfld.long 0x18 4.--5. "FUPD_CTRL2,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 2.--3. "FUPD_CTRL1,Force update of ATOM channel [k] operation registers" "0,1,2,3" bitfld.long 0x18 0.--1. "FUPD_CTRL0,Force update of ATOM channel [k] operation registers" "0,1,2,3" line.long 0x1C "ATOM8_AGC_INT_TRIG," bitfld.long 0x1C 14.--15. "INT_TRIG7,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" bitfld.long 0x1C 12.--13. "INT_TRIG6,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 10.--11. "INT_TRIG5,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" bitfld.long 0x1C 8.--9. "INT_TRIG4,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 6.--7. "INT_TRIG3,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" bitfld.long 0x1C 4.--5. "INT_TRIG2,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 2.--3. "INT_TRIG1,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" bitfld.long 0x1C 0.--1. "INT_TRIG0,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" group.long 0x2000++0x27 line.long 0x0 "MCS8_CH0_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS8_CH0_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS8_CH0_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS8_CH0_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS8_CH0_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS8_CH0_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS8_CH0_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS8_CH0_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS8_CH0_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS8_CH0_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x203C++0x3 line.long 0x0 "MCS8_CH0_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x20E0++0x17 line.long 0x0 "MCS8_CH0_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS8_CH0_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS8_CH0_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS8_CH0_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS8_CH0_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS8_CH0_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2100++0x27 line.long 0x0 "MCS8_CH1_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS8_CH1_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS8_CH1_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS8_CH1_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS8_CH1_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS8_CH1_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS8_CH1_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS8_CH1_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS8_CH1_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS8_CH1_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x213C++0x3 line.long 0x0 "MCS8_CH1_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x21E0++0x17 line.long 0x0 "MCS8_CH1_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS8_CH1_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS8_CH1_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS8_CH1_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS8_CH1_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS8_CH1_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2200++0x27 line.long 0x0 "MCS8_CH2_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS8_CH2_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS8_CH2_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS8_CH2_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS8_CH2_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS8_CH2_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS8_CH2_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS8_CH2_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS8_CH2_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS8_CH2_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x223C++0x3 line.long 0x0 "MCS8_CH2_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x22E0++0x17 line.long 0x0 "MCS8_CH2_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS8_CH2_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS8_CH2_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS8_CH2_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS8_CH2_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS8_CH2_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2300++0x27 line.long 0x0 "MCS8_CH3_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS8_CH3_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS8_CH3_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS8_CH3_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS8_CH3_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS8_CH3_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS8_CH3_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS8_CH3_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS8_CH3_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS8_CH3_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x233C++0x3 line.long 0x0 "MCS8_CH3_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x23E0++0x17 line.long 0x0 "MCS8_CH3_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS8_CH3_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS8_CH3_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS8_CH3_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS8_CH3_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS8_CH3_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2400++0x27 line.long 0x0 "MCS8_CH4_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS8_CH4_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS8_CH4_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS8_CH4_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS8_CH4_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS8_CH4_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS8_CH4_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS8_CH4_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS8_CH4_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS8_CH4_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x243C++0x3 line.long 0x0 "MCS8_CH4_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x24E0++0x17 line.long 0x0 "MCS8_CH4_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS8_CH4_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS8_CH4_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS8_CH4_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS8_CH4_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS8_CH4_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2500++0x27 line.long 0x0 "MCS8_CH5_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS8_CH5_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS8_CH5_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS8_CH5_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS8_CH5_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS8_CH5_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS8_CH5_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS8_CH5_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS8_CH5_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS8_CH5_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x253C++0x3 line.long 0x0 "MCS8_CH5_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x25E0++0x17 line.long 0x0 "MCS8_CH5_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS8_CH5_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS8_CH5_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS8_CH5_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS8_CH5_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS8_CH5_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2600++0x27 line.long 0x0 "MCS8_CH6_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS8_CH6_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS8_CH6_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS8_CH6_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS8_CH6_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS8_CH6_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS8_CH6_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS8_CH6_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS8_CH6_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS8_CH6_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x263C++0x3 line.long 0x0 "MCS8_CH6_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x26E0++0x17 line.long 0x0 "MCS8_CH6_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS8_CH6_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS8_CH6_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS8_CH6_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS8_CH6_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS8_CH6_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2700++0x27 line.long 0x0 "MCS8_CH7_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS8_CH7_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS8_CH7_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS8_CH7_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS8_CH7_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS8_CH7_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS8_CH7_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS8_CH7_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS8_CH7_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS8_CH7_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x273C++0x3 line.long 0x0 "MCS8_CH7_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x27E0++0x17 line.long 0x0 "MCS8_CH7_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS8_CH7_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS8_CH7_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS8_CH7_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS8_CH7_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS8_CH7_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2E28++0x7 line.long 0x0 "MCS8_CTRG," bitfld.long 0x0 23. "TRG23,Trigger bit o." "0,1" bitfld.long 0x0 22. "TRG22,Trigger bit o." "0,1" newline bitfld.long 0x0 21. "TRG21,Trigger bit o." "0,1" bitfld.long 0x0 20. "TRG20,Trigger bit o." "0,1" newline bitfld.long 0x0 19. "TRG19,Trigger bit o." "0,1" bitfld.long 0x0 18. "TRG18,Trigger bit o." "0,1" newline bitfld.long 0x0 17. "TRG17,Trigger bit o." "0,1" bitfld.long 0x0 16. "TRG16,Trigger bit o." "0,1" newline bitfld.long 0x0 15. "TRG15,Trigger bit n." "0,1" bitfld.long 0x0 14. "TRG14,Trigger bit n." "0,1" newline bitfld.long 0x0 13. "TRG13,Trigger bit n." "0,1" bitfld.long 0x0 12. "TRG12,Trigger bit n." "0,1" newline bitfld.long 0x0 11. "TRG11,Trigger bit n." "0,1" bitfld.long 0x0 10. "TRG10,Trigger bit n." "0,1" newline bitfld.long 0x0 9. "TRG9,Trigger bit n." "0,1" bitfld.long 0x0 8. "TRG8,Trigger bit n." "0,1" newline bitfld.long 0x0 7. "TRG7,Trigger bit m." "0,1" bitfld.long 0x0 6. "TRG6,Trigger bit m." "0,1" newline bitfld.long 0x0 5. "TRG5,Trigger bit m." "0,1" bitfld.long 0x0 4. "TRG4,Trigger bit m." "0,1" newline bitfld.long 0x0 3. "TRG3,Trigger bit m." "0,1" bitfld.long 0x0 2. "TRG2,Trigger bit m." "0,1" newline bitfld.long 0x0 1. "TRG1,Trigger bit m." "0,1" bitfld.long 0x0 0. "TRG0,Trigger bit m." "0,1" line.long 0x4 "MCS8_STRG," bitfld.long 0x4 23. "TRG23,Trigger bit k." "0,1" bitfld.long 0x4 22. "TRG22,Trigger bit k." "0,1" newline bitfld.long 0x4 21. "TRG21,Trigger bit k." "0,1" bitfld.long 0x4 20. "TRG20,Trigger bit k." "0,1" newline bitfld.long 0x4 19. "TRG19,Trigger bit k." "0,1" bitfld.long 0x4 18. "TRG18,Trigger bit k." "0,1" newline bitfld.long 0x4 17. "TRG17,Trigger bit k." "0,1" bitfld.long 0x4 16. "TRG16,Trigger bit k." "0,1" newline bitfld.long 0x4 15. "TRG15,Trigger bit k." "0,1" bitfld.long 0x4 14. "TRG14,Trigger bit k." "0,1" newline bitfld.long 0x4 13. "TRG13,Trigger bit k." "0,1" bitfld.long 0x4 12. "TRG12,Trigger bit k." "0,1" newline bitfld.long 0x4 11. "TRG11,Trigger bit k." "0,1" bitfld.long 0x4 10. "TRG10,Trigger bit k." "0,1" newline bitfld.long 0x4 9. "TRG9,Trigger bit k." "0,1" bitfld.long 0x4 8. "TRG8,Trigger bit k." "0,1" newline bitfld.long 0x4 7. "TRG7,Trigger bit k." "0,1" bitfld.long 0x4 6. "TRG6,Trigger bit k." "0,1" newline bitfld.long 0x4 5. "TRG5,Trigger bit k." "0,1" bitfld.long 0x4 4. "TRG4,Trigger bit k." "0,1" newline bitfld.long 0x4 3. "TRG3,Trigger bit k." "0,1" bitfld.long 0x4 2. "TRG2,Trigger bit k." "0,1" newline bitfld.long 0x4 1. "TRG1,Trigger bit k." "0,1" bitfld.long 0x4 0. "TRG0,Trigger bit k." "0,1" group.long 0x2F00++0x13 line.long 0x0 "MCS8_CTRL_STAT," bitfld.long 0x0 26. "HLT_AEIM_ERR,Halt on AEI bus master error." "0,1" bitfld.long 0x0 25. "EN_HVD,Enable Modified Harvard architecture." "0,1" newline bitfld.long 0x0 24. "EN_TIM_FOUT,Enable routing of TIM[i]_CH[x]_F_OUT signal." "0,1" bitfld.long 0x0 20.--22. "ERR_SRC_ID,Error source identifier." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "RAM_RST,RAM reset bit." "0,1" hexmask.long.byte 0x0 8.--11. 1. "SCD_CH,Channel selection for scheduling algorithm." newline bitfld.long 0x0 0.--1. "SCD_MODE,Select MCS scheduling mode" "0,1,2,3" line.long 0x4 "MCS8_RESET," bitfld.long 0x4 7. "RST7,Software reset of channel [k]" "0,1" bitfld.long 0x4 6. "RST6,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 5. "RST5,Software reset of channel [k]" "0,1" bitfld.long 0x4 4. "RST4,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 3. "RST3,Software reset of channel [k]" "0,1" bitfld.long 0x4 2. "RST2,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 1. "RST1,Software reset of channel [k]" "0,1" bitfld.long 0x4 0. "RST0,Software reset of channel [k]" "0,1" line.long 0x8 "MCS8_CAT," bitfld.long 0x8 7. "CAT7,Cancel ARU transfer of channel [k]." "0,1" bitfld.long 0x8 6. "CAT6,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 5. "CAT5,Cancel ARU transfer of channel [k]." "0,1" bitfld.long 0x8 4. "CAT4,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 3. "CAT3,Cancel ARU transfer of channel [k]." "0,1" bitfld.long 0x8 2. "CAT2,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 1. "CAT1,Cancel ARU transfer of channel [k]." "0,1" bitfld.long 0x8 0. "CAT0,Cancel ARU transfer of channel [k]." "0,1" line.long 0xC "MCS8_CWT," bitfld.long 0xC 7. "CWT7,Cancel waiting instruction for channel [k]." "0,1" bitfld.long 0xC 6. "CWT6,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 5. "CWT5,Cancel waiting instruction for channel [k]." "0,1" bitfld.long 0xC 4. "CWT4,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 3. "CWT3,Cancel waiting instruction for channel [k]." "0,1" bitfld.long 0xC 2. "CWT2,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 1. "CWT1,Cancel waiting instruction for channel [k]." "0,1" bitfld.long 0xC 0. "CWT0,Cancel waiting instruction for channel [k]." "0,1" line.long 0x10 "MCS8_ERR," bitfld.long 0x10 7. "ERR7,Error State of MCS-channel [k]." "0,1" bitfld.long 0x10 6. "ERR6,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 5. "ERR5,Error State of MCS-channel [k]." "0,1" bitfld.long 0x10 4. "ERR4,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 3. "ERR3,Error State of MCS-channel [k]." "0,1" bitfld.long 0x10 2. "ERR2,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 1. "ERR1,Error State of MCS-channel [k]." "0,1" bitfld.long 0x10 0. "ERR0,Error State of MCS-channel [k]." "0,1" group.long 0x2F1C++0x13 line.long 0x0 "MCS8_REG_PROT," bitfld.long 0x0 14.--15. "WPROT7,Register Write Protection of MCS-channel k." "0,1,2,3" bitfld.long 0x0 12.--13. "WPROT6,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 10.--11. "WPROT5,Register Write Protection of MCS-channel k." "0,1,2,3" bitfld.long 0x0 8.--9. "WPROT4,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 6.--7. "WPROT3,Register Write Protection of MCS-channel k." "0,1,2,3" bitfld.long 0x0 4.--5. "WPROT2,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 2.--3. "WPROT1,Register Write Protection of MCS-channel k." "0,1,2,3" bitfld.long 0x0 0.--1. "WPROT0,Register Write Protection of MCS-channel k." "0,1,2,3" line.long 0x4 "MCS8_SINT_IRQ_NOTIFY," bitfld.long 0x4 7. "S_IRQ7,Shared interrupt [k] notify flag." "0,1" bitfld.long 0x4 6. "S_IRQ6,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 5. "S_IRQ5,Shared interrupt [k] notify flag." "0,1" bitfld.long 0x4 4. "S_IRQ4,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 3. "S_IRQ3,Shared interrupt [k] notify flag." "0,1" bitfld.long 0x4 2. "S_IRQ2,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 1. "S_IRQ1,Shared interrupt [k] notify flag." "0,1" bitfld.long 0x4 0. "S_IRQ0,Shared interrupt [k] notify flag." "0,1" line.long 0x8 "MCS8_SINT_IRQ_EN," bitfld.long 0x8 7. "S_IRQ7_EN,Shared interrupt [k]" "0,1" bitfld.long 0x8 6. "S_IRQ6_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 5. "S_IRQ5_EN,Shared interrupt [k]" "0,1" bitfld.long 0x8 4. "S_IRQ4_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 3. "S_IRQ3_EN,Shared interrupt [k]" "0,1" bitfld.long 0x8 2. "S_IRQ2_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 1. "S_IRQ1_EN,Shared interrupt [k]" "0,1" bitfld.long 0x8 0. "S_IRQ0_EN,Shared interrupt [k]" "0,1" line.long 0xC "MCS8_SINT_IRQ_FORCINT," bitfld.long 0xC 7. "TRG_S_IRQ7,Trigger IRQ [k] in shared interrupt register" "0,1" bitfld.long 0xC 6. "TRG_S_IRQ6,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 5. "TRG_S_IRQ5,Trigger IRQ [k] in shared interrupt register" "0,1" bitfld.long 0xC 4. "TRG_S_IRQ4,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 3. "TRG_S_IRQ3,Trigger IRQ [k] in shared interrupt register" "0,1" bitfld.long 0xC 2. "TRG_S_IRQ2,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 1. "TRG_S_IRQ1,Trigger IRQ [k] in shared interrupt register" "0,1" bitfld.long 0xC 0. "TRG_S_IRQ0,Trigger IRQ [k] in shared interrupt register" "0,1" line.long 0x10 "MCS8_SINT_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x2F40++0x1B line.long 0x0 "MCS8_HBP0_CTRL," bitfld.long 0x0 17. "NOT,Logical negation of h-th hardware break point." "0,1" bitfld.long 0x0 16. "AND,Logical AND conjunction of h-th hardware break point." "0,1" newline bitfld.long 0x0 12.--14. "TYPE,Define type of h-th hardware break point." "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. "SCOPE,Define scope of h-th hardware break point." "0,1,2,3" newline bitfld.long 0x0 7. "EN_CH7,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 6. "EN_CH6,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 5. "EN_CH5,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 4. "EN_CH4,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 3. "EN_CH3,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 2. "EN_CH2,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 1. "EN_CH1,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 0. "EN_CH0,Enable h-th hardware break point for channel x." "0,1" line.long 0x4 "MCS8_HBP0_PATTERN," hexmask.long 0x4 0.--31. 1. "DATA,Define pattern or address of h-th hardware break point." line.long 0x8 "MCS8_HBP0_STATUS," bitfld.long 0x8 7. "HALT_CH7,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 6. "HALT_CH6,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 5. "HALT_CH5,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 4. "HALT_CH4,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 3. "HALT_CH3,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 2. "HALT_CH2,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 1. "HALT_CH1,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 0. "HALT_CH0,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" line.long 0xC "MCS8_HBP0_IRQ_NOTIFY," bitfld.long 0xC 0. "HBP_IRQ,Interrupt notify flag of the h-th hardware break point." "0,1" line.long 0x10 "MCS8_HBP0_IRQ_EN," bitfld.long 0x10 0. "HBP_IRQ_EN,Interrupt Enable bit of the h-th hardware break point." "0,1" line.long 0x14 "MCS8_HBP0_IRQ_FORCINT," bitfld.long 0x14 0. "TRG_HBP_IRQ,Trigger IRQ of the h-th hardware break point." "0,1" line.long 0x18 "MCS8_HBP0_IRQ_MODE," bitfld.long 0x18 0.--1. "IRQ_MODE,IRQ mode selection for all break point interrupts." "0,1,2,3" group.long 0x2F60++0x1B line.long 0x0 "MCS8_HBP1_CTRL," bitfld.long 0x0 17. "NOT,Logical negation of h-th hardware break point." "0,1" bitfld.long 0x0 16. "AND,Logical AND conjunction of h-th hardware break point." "0,1" newline bitfld.long 0x0 12.--14. "TYPE,Define type of h-th hardware break point." "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. "SCOPE,Define scope of h-th hardware break point." "0,1,2,3" newline bitfld.long 0x0 7. "EN_CH7,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 6. "EN_CH6,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 5. "EN_CH5,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 4. "EN_CH4,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 3. "EN_CH3,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 2. "EN_CH2,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 1. "EN_CH1,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 0. "EN_CH0,Enable h-th hardware break point for channel x." "0,1" line.long 0x4 "MCS8_HBP1_PATTERN," hexmask.long 0x4 0.--31. 1. "DATA,Define pattern or address of h-th hardware break point." line.long 0x8 "MCS8_HBP1_STATUS," bitfld.long 0x8 7. "HALT_CH7,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 6. "HALT_CH6,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 5. "HALT_CH5,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 4. "HALT_CH4,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 3. "HALT_CH3,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 2. "HALT_CH2,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 1. "HALT_CH1,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 0. "HALT_CH0,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" line.long 0xC "MCS8_HBP1_IRQ_NOTIFY," bitfld.long 0xC 0. "HBP_IRQ,Interrupt notify flag of the h-th hardware break point." "0,1" line.long 0x10 "MCS8_HBP1_IRQ_EN," bitfld.long 0x10 0. "HBP_IRQ_EN,Interrupt Enable bit of the h-th hardware break point." "0,1" line.long 0x14 "MCS8_HBP1_IRQ_FORCINT," bitfld.long 0x14 0. "TRG_HBP_IRQ,Trigger IRQ of the h-th hardware break point." "0,1" line.long 0x18 "MCS8_HBP1_IRQ_MODE," bitfld.long 0x18 0.--1. "IRQ_MODE,IRQ mode selection for all break point interrupts." "0,1,2,3" group.long 0x3000++0x13 line.long 0x0 "TIO8_G0_CH0_CTRL," bitfld.long 0x0 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x0 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x0 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x0 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x0 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x0 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x0 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x0 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x0 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x0 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x0 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x0 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x0 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x0 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x0 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x0 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x0 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x0 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x0 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x0 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x4 "TIO8_G0_CH0_IRQ_NOTIFY," bitfld.long 0x4 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x4 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x4 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x4 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x4 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x4 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x8 "TIO8_G0_CH0_IRQ_EN," bitfld.long 0x8 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x8 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x8 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x8 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x8 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x8 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0xC "TIO8_G0_CH0_IRQ_FORCINT," bitfld.long 0xC 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0xC 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0xC 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0xC 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0xC 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0xC 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x10 "TIO8_G0_CH0_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3020++0xB line.long 0x0 "TIO8_G0_CH0_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO8_G0_CH0_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO8_G0_CH0_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3030++0x23 line.long 0x0 "TIO8_G0_CH0_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO8_G0_CH0_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO8_G0_CH0_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO8_G0_CH0_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO8_G0_CH1_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO8_G0_CH1_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO8_G0_CH1_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO8_G0_CH1_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO8_G0_CH1_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3060++0xB line.long 0x0 "TIO8_G0_CH1_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO8_G0_CH1_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO8_G0_CH1_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3070++0x23 line.long 0x0 "TIO8_G0_CH1_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO8_G0_CH1_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO8_G0_CH1_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO8_G0_CH1_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO8_G0_CH2_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO8_G0_CH2_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO8_G0_CH2_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO8_G0_CH2_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO8_G0_CH2_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x30A0++0xB line.long 0x0 "TIO8_G0_CH2_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO8_G0_CH2_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO8_G0_CH2_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x30B0++0x23 line.long 0x0 "TIO8_G0_CH2_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO8_G0_CH2_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO8_G0_CH2_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO8_G0_CH2_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO8_G0_CH3_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO8_G0_CH3_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO8_G0_CH3_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO8_G0_CH3_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO8_G0_CH3_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x30E0++0xB line.long 0x0 "TIO8_G0_CH3_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO8_G0_CH3_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO8_G0_CH3_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x30F0++0x23 line.long 0x0 "TIO8_G0_CH3_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO8_G0_CH3_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO8_G0_CH3_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO8_G0_CH3_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO8_G0_CH4_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO8_G0_CH4_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO8_G0_CH4_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO8_G0_CH4_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO8_G0_CH4_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3120++0xB line.long 0x0 "TIO8_G0_CH4_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO8_G0_CH4_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO8_G0_CH4_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3130++0x23 line.long 0x0 "TIO8_G0_CH4_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO8_G0_CH4_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO8_G0_CH4_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO8_G0_CH4_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO8_G0_CH5_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO8_G0_CH5_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO8_G0_CH5_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO8_G0_CH5_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO8_G0_CH5_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3160++0xB line.long 0x0 "TIO8_G0_CH5_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO8_G0_CH5_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO8_G0_CH5_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3170++0x23 line.long 0x0 "TIO8_G0_CH5_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO8_G0_CH5_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO8_G0_CH5_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO8_G0_CH5_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO8_G0_CH6_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO8_G0_CH6_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO8_G0_CH6_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO8_G0_CH6_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO8_G0_CH6_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x31A0++0xB line.long 0x0 "TIO8_G0_CH6_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO8_G0_CH6_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO8_G0_CH6_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x31B0++0x23 line.long 0x0 "TIO8_G0_CH6_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO8_G0_CH6_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO8_G0_CH6_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO8_G0_CH6_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO8_G0_CH7_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO8_G0_CH7_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO8_G0_CH7_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO8_G0_CH7_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO8_G0_CH7_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x31E0++0xB line.long 0x0 "TIO8_G0_CH7_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO8_G0_CH7_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO8_G0_CH7_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x31F0++0x17 line.long 0x0 "TIO8_G0_CH7_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO8_G0_CH7_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO8_G0_CH7_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO8_G0_CH7_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO8_G0_ISEL0_CTRL1," bitfld.long 0x10 27. "WRITE_EN3,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" bitfld.long 0x10 26. "WRITE_EN2,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 25. "WRITE_EN1,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" bitfld.long 0x10 24. "WRITE_EN0,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 19. "OUT_SEL3,select signal for ISEL_OUT[k]" "0,1" bitfld.long 0x10 18. "OUT_SEL2,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x10 17. "OUT_SEL1,select signal for ISEL_OUT[k]" "0,1" bitfld.long 0x10 16. "OUT_SEL0,select signal for ISEL_OUT[k]" "0,1" newline hexmask.long.byte 0x10 12.--15. 1. "LUT2_3,2 bit Lookup table function for channel c=q*4+k" hexmask.long.byte 0x10 8.--11. 1. "LUT2_2,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x10 4.--7. 1. "LUT2_1,2 bit Lookup table function for channel c=q*4+k" hexmask.long.byte 0x10 0.--3. 1. "LUT2_0,2 bit Lookup table function for channel c=q*4+k" line.long 0x14 "TIO8_G0_ISEL0_CTRL2," bitfld.long 0x14 22. "LUT3IN_SEL2,select source for LUT3_IN[k] signal in quad = q" "0,1" bitfld.long 0x14 21. "LUT3IN_SEL1,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x14 20. "LUT3IN_SEL0,select source for LUT3_IN[k] signal in quad = q" "0,1" bitfld.long 0x14 16.--17. "QOUT_SEL,select source for ISEL_QOUT signal in quad = q" "0,1,2,3" newline hexmask.long.byte 0x14 0.--7. 1. "LUT3,3 bit Lookup table function for quad=q; channels q*4+2 .. q*4" group.long 0x3220++0x7 line.long 0x0 "TIO8_G0_ISEL1_CTRL1," bitfld.long 0x0 27. "WRITE_EN3,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" bitfld.long 0x0 26. "WRITE_EN2,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 25. "WRITE_EN1,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" bitfld.long 0x0 24. "WRITE_EN0,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 19. "OUT_SEL3,select signal for ISEL_OUT[k]" "0,1" bitfld.long 0x0 18. "OUT_SEL2,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x0 17. "OUT_SEL1,select signal for ISEL_OUT[k]" "0,1" bitfld.long 0x0 16. "OUT_SEL0,select signal for ISEL_OUT[k]" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "LUT2_3,2 bit Lookup table function for channel c=q*4+k" hexmask.long.byte 0x0 8.--11. 1. "LUT2_2,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x0 4.--7. 1. "LUT2_1,2 bit Lookup table function for channel c=q*4+k" hexmask.long.byte 0x0 0.--3. 1. "LUT2_0,2 bit Lookup table function for channel c=q*4+k" line.long 0x4 "TIO8_G0_ISEL1_CTRL2," bitfld.long 0x4 22. "LUT3IN_SEL2,select source for LUT3_IN[k] signal in quad = q" "0,1" bitfld.long 0x4 21. "LUT3IN_SEL1,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x4 20. "LUT3IN_SEL0,select source for LUT3_IN[k] signal in quad = q" "0,1" bitfld.long 0x4 16.--17. "QOUT_SEL,select source for ISEL_QOUT signal in quad = q" "0,1,2,3" newline hexmask.long.byte 0x4 0.--7. 1. "LUT3,3 bit Lookup table function for quad=q; channels q*4+2 .. q*4" group.long 0x3240++0x3 line.long 0x0 "TIO8_G0_OP_USAGE," bitfld.long 0x0 31. "WRITE_EN7,enable writing of configuration bit fields MODE[c]" "0,1" bitfld.long 0x0 30. "WRITE_EN6,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 29. "WRITE_EN5,enable writing of configuration bit fields MODE[c]" "0,1" bitfld.long 0x0 28. "WRITE_EN4,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 27. "WRITE_EN3,enable writing of configuration bit fields MODE[c]" "0,1" bitfld.long 0x0 26. "WRITE_EN2,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 25. "WRITE_EN1,enable writing of configuration bit fields MODE[c]" "0,1" bitfld.long 0x0 24. "WRITE_EN0,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 21.--23. "MODE7,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18.--20. "MODE6,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15.--17. "MODE5,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "MODE4,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9.--11. "MODE3,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--8. "MODE2,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "MODE1,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "MODE0,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" group.long 0x3C00++0x1F line.long 0x0 "TIO8_S," bitfld.long 0x0 7. "CH7,Value of channel x." "0,1" bitfld.long 0x0 6. "CH6,Value of channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Value of channel x." "0,1" bitfld.long 0x0 4. "CH4,Value of channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Value of channel x." "0,1" bitfld.long 0x0 2. "CH2,Value of channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Value of channel x." "0,1" bitfld.long 0x0 0. "CH0,Value of channel x." "0,1" line.long 0x4 "TIO8_O," bitfld.long 0x4 7. "CH7,Value driven on output of channel x." "0,1" bitfld.long 0x4 6. "CH6,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Value driven on output of channel x." "0,1" bitfld.long 0x4 4. "CH4,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Value driven on output of channel x." "0,1" bitfld.long 0x4 2. "CH2,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Value driven on output of channel x." "0,1" bitfld.long 0x4 0. "CH0,Value driven on output of channel x." "0,1" line.long 0x8 "TIO8_ENDIS," bitfld.long 0x8 7. "CH7,Enable/Disable request of channel x." "0,1" bitfld.long 0x8 6. "CH6,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Enable/Disable request of channel x." "0,1" bitfld.long 0x8 4. "CH4,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Enable/Disable request of channel x." "0,1" bitfld.long 0x8 2. "CH2,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Enable/Disable request of channel x." "0,1" bitfld.long 0x8 0. "CH0,Enable/Disable request of channel x." "0,1" line.long 0xC "TIO8_INVERT," bitfld.long 0xC 7. "CH7,Enable/Disable signal inversion of channel x." "0,1" bitfld.long 0xC 6. "CH6,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Enable/Disable signal inversion of channel x." "0,1" bitfld.long 0xC 4. "CH4,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Enable/Disable signal inversion of channel x." "0,1" bitfld.long 0xC 2. "CH2,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Enable/Disable signal inversion of channel x." "0,1" bitfld.long 0xC 0. "CH0,Enable/Disable signal inversion of channel x." "0,1" line.long 0x10 "TIO8_INPUT_MODE," bitfld.long 0x10 7. "CH7,Enable/Disable input mode of channel x." "0,1" bitfld.long 0x10 6. "CH6,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Enable/Disable input mode of channel x." "0,1" bitfld.long 0x10 4. "CH4,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Enable/Disable input mode of channel x." "0,1" bitfld.long 0x10 2. "CH2,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Enable/Disable input mode of channel x." "0,1" bitfld.long 0x10 0. "CH0,Enable/Disable input mode of channel x." "0,1" line.long 0x14 "TIO8_CYCLIC_MODE," bitfld.long 0x14 7. "CH7,Enable/Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 6. "CH6,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Enable/Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 4. "CH4,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Enable/Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 2. "CH2,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Enable/Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 0. "CH0,Enable/Disable cyclic mode of channel x." "0,1" line.long 0x18 "TIO8_TRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 6. "CH6,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 4. "CH4,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 2. "CH2,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 0. "CH0,enable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO8_PLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 6. "CH6,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 4. "CH4,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 2. "CH2,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 0. "CH0,enable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3C40++0x1F line.long 0x0 "TIO8_CS," bitfld.long 0x0 7. "CH7,Clear channel x." "0,1" bitfld.long 0x0 6. "CH6,Clear channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Clear channel x." "0,1" bitfld.long 0x0 4. "CH4,Clear channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Clear channel x." "0,1" bitfld.long 0x0 2. "CH2,Clear channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Clear channel x." "0,1" bitfld.long 0x0 0. "CH0,Clear channel x." "0,1" line.long 0x4 "TIO8_CO," bitfld.long 0x4 7. "CH7,Clear channel x." "0,1" bitfld.long 0x4 6. "CH6,Clear channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Clear channel x." "0,1" bitfld.long 0x4 4. "CH4,Clear channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Clear channel x." "0,1" bitfld.long 0x4 2. "CH2,Clear channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Clear channel x." "0,1" bitfld.long 0x4 0. "CH0,Clear channel x." "0,1" line.long 0x8 "TIO8_CENDIS," bitfld.long 0x8 7. "CH7,Disable request of channel x." "0,1" bitfld.long 0x8 6. "CH6,Disable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Disable request of channel x." "0,1" bitfld.long 0x8 4. "CH4,Disable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Disable request of channel x." "0,1" bitfld.long 0x8 2. "CH2,Disable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Disable request of channel x." "0,1" bitfld.long 0x8 0. "CH0,Disable request of channel x." "0,1" line.long 0xC "TIO8_CINVERT," bitfld.long 0xC 7. "CH7,Disable signal inversion of channel x." "0,1" bitfld.long 0xC 6. "CH6,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Disable signal inversion of channel x." "0,1" bitfld.long 0xC 4. "CH4,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Disable signal inversion of channel x." "0,1" bitfld.long 0xC 2. "CH2,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Disable signal inversion of channel x." "0,1" bitfld.long 0xC 0. "CH0,Disable signal inversion of channel x." "0,1" line.long 0x10 "TIO8_CINPUT_MODE," bitfld.long 0x10 7. "CH7,Disable input mode of channel x." "0,1" bitfld.long 0x10 6. "CH6,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Disable input mode of channel x." "0,1" bitfld.long 0x10 4. "CH4,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Disable input mode of channel x." "0,1" bitfld.long 0x10 2. "CH2,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Disable input mode of channel x." "0,1" bitfld.long 0x10 0. "CH0,Disable input mode of channel x." "0,1" line.long 0x14 "TIO8_CCYCLIC_MODE," bitfld.long 0x14 7. "CH7,Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 6. "CH6,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 4. "CH4,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 2. "CH2,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 0. "CH0,Disable cyclic mode of channel x." "0,1" line.long 0x18 "TIO8_CTRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,disable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 6. "CH6,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,disable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 4. "CH4,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,disable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 2. "CH2,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,disable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 0. "CH0,disable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO8_CPLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,disable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 6. "CH6,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,disable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 4. "CH4,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,disable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 2. "CH2,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,disable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 0. "CH0,disable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3C80++0x1F line.long 0x0 "TIO8_SS," bitfld.long 0x0 7. "CH7,Set channel x." "0,1" bitfld.long 0x0 6. "CH6,Set channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Set channel x." "0,1" bitfld.long 0x0 4. "CH4,Set channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Set channel x." "0,1" bitfld.long 0x0 2. "CH2,Set channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Set channel x." "0,1" bitfld.long 0x0 0. "CH0,Set channel x." "0,1" line.long 0x4 "TIO8_SO," bitfld.long 0x4 7. "CH7,Set channel x." "0,1" bitfld.long 0x4 6. "CH6,Set channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Set channel x." "0,1" bitfld.long 0x4 4. "CH4,Set channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Set channel x." "0,1" bitfld.long 0x4 2. "CH2,Set channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Set channel x." "0,1" bitfld.long 0x4 0. "CH0,Set channel x." "0,1" line.long 0x8 "TIO8_SENDIS," bitfld.long 0x8 7. "CH7,Enable request of channel x." "0,1" bitfld.long 0x8 6. "CH6,Enable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Enable request of channel x." "0,1" bitfld.long 0x8 4. "CH4,Enable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Enable request of channel x." "0,1" bitfld.long 0x8 2. "CH2,Enable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Enable request of channel x." "0,1" bitfld.long 0x8 0. "CH0,Enable request of channel x." "0,1" line.long 0xC "TIO8_SINVERT," bitfld.long 0xC 7. "CH7,Enable signal inversion of channel x." "0,1" bitfld.long 0xC 6. "CH6,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Enable signal inversion of channel x." "0,1" bitfld.long 0xC 4. "CH4,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Enable signal inversion of channel x." "0,1" bitfld.long 0xC 2. "CH2,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Enable signal inversion of channel x." "0,1" bitfld.long 0xC 0. "CH0,Enable signal inversion of channel x." "0,1" line.long 0x10 "TIO8_SINPUT_MODE," bitfld.long 0x10 7. "CH7,Enable input mode of channel x." "0,1" bitfld.long 0x10 6. "CH6,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Enable input mode of channel x." "0,1" bitfld.long 0x10 4. "CH4,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Enable input mode of channel x." "0,1" bitfld.long 0x10 2. "CH2,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Enable input mode of channel x." "0,1" bitfld.long 0x10 0. "CH0,Enable input mode of channel x." "0,1" line.long 0x14 "TIO8_SCYCLIC_MODE," bitfld.long 0x14 7. "CH7,Enable cyclic mode of channel x." "0,1" bitfld.long 0x14 6. "CH6,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Enable cyclic mode of channel x." "0,1" bitfld.long 0x14 4. "CH4,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Enable cyclic mode of channel x." "0,1" bitfld.long 0x14 2. "CH2,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Enable cyclic mode of channel x." "0,1" bitfld.long 0x14 0. "CH0,Enable cyclic mode of channel x." "0,1" line.long 0x18 "TIO8_STRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 6. "CH6,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 4. "CH4,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 2. "CH2,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 0. "CH0,enable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO8_SPLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 6. "CH6,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 4. "CH4,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 2. "CH2,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 0. "CH0,enable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3CC0++0x17 line.long 0x0 "TIO8_IS," bitfld.long 0x0 7. "CH7,Invert channel x." "0,1" bitfld.long 0x0 6. "CH6,Invert channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Invert channel x." "0,1" bitfld.long 0x0 4. "CH4,Invert channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Invert channel x." "0,1" bitfld.long 0x0 2. "CH2,Invert channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Invert channel x." "0,1" bitfld.long 0x0 0. "CH0,Invert channel x." "0,1" line.long 0x4 "TIO8_IO," bitfld.long 0x4 7. "CH7,Invert channel x." "0,1" bitfld.long 0x4 6. "CH6,Invert channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Invert channel x." "0,1" bitfld.long 0x4 4. "CH4,Invert channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Invert channel x." "0,1" bitfld.long 0x4 2. "CH2,Invert channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Invert channel x." "0,1" bitfld.long 0x4 0. "CH0,Invert channel x." "0,1" line.long 0x8 "TIO8_IENDIS," bitfld.long 0x8 7. "CH7,Toggle state request of channel x." "0,1" bitfld.long 0x8 6. "CH6,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Toggle state request of channel x." "0,1" bitfld.long 0x8 4. "CH4,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Toggle state request of channel x." "0,1" bitfld.long 0x8 2. "CH2,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Toggle state request of channel x." "0,1" bitfld.long 0x8 0. "CH0,Toggle state request of channel x." "0,1" line.long 0xC "TIO8_IINVERT," bitfld.long 0xC 7. "CH7,Invert signal inversion of channel x." "0,1" bitfld.long 0xC 6. "CH6,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Invert signal inversion of channel x." "0,1" bitfld.long 0xC 4. "CH4,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Invert signal inversion of channel x." "0,1" bitfld.long 0xC 2. "CH2,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Invert signal inversion of channel x." "0,1" bitfld.long 0xC 0. "CH0,Invert signal inversion of channel x." "0,1" line.long 0x10 "TIO8_IINPUT_MODE," bitfld.long 0x10 7. "CH7,Toggle input mode of channel x." "0,1" bitfld.long 0x10 6. "CH6,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Toggle input mode of channel x." "0,1" bitfld.long 0x10 4. "CH4,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Toggle input mode of channel x." "0,1" bitfld.long 0x10 2. "CH2,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Toggle input mode of channel x." "0,1" bitfld.long 0x10 0. "CH0,Toggle input mode of channel x." "0,1" line.long 0x14 "TIO8_ICYCLIC_MODE," bitfld.long 0x14 7. "CH7,Toggle cyclic mode of channel x." "0,1" bitfld.long 0x14 6. "CH6,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Toggle cyclic mode of channel x." "0,1" bitfld.long 0x14 4. "CH4,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Toggle cyclic mode of channel x." "0,1" bitfld.long 0x14 2. "CH2,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Toggle cyclic mode of channel x." "0,1" bitfld.long 0x14 0. "CH0,Toggle cyclic mode of channel x." "0,1" group.long 0x3D00++0x13 line.long 0x0 "TIO8_FUPD," bitfld.long 0x0 7. "CH7,issue immediately a signal pulse on the update signal of channel x" "0,1" bitfld.long 0x0 6. "CH6,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 5. "CH5,issue immediately a signal pulse on the update signal of channel x" "0,1" bitfld.long 0x0 4. "CH4,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 3. "CH3,issue immediately a signal pulse on the update signal of channel x" "0,1" bitfld.long 0x0 2. "CH2,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 1. "CH1,issue immediately a signal pulse on the update signal of channel x" "0,1" bitfld.long 0x0 0. "CH0,issue immediately a signal pulse on the update signal of channel x" "0,1" line.long 0x4 "TIO8_HW_CONF," bitfld.long 0x4 4. "TIO_PLUS,signals availablity of TIOplus functionality" "0,1" bitfld.long 0x4 0.--1. "NTIO_CH8,signals availablity of amount of channels" "0,1,2,3" line.long 0x8 "TIO8_RSEL_CTRL1," bitfld.long 0x8 28. "SEL_CLKEN7_0,select source of RS_CLKEN7[g][7] for channels g*8 .. g*8+7" "0,1" bitfld.long 0x8 24. "SEL_CLKEN6_0,select source of RS_CLKEN[g][6] for channels g*8 .. g*8+7" "0,1" line.long 0xC "TIO8_RSEL_CTRL2," bitfld.long 0xC 8. "SEL_TB2_0,select source of RS_TB2[g] for channels g*8 .. g*8+7" "0,1" bitfld.long 0xC 4. "SEL_TB1_0,select source of RS_TB1[g] for channels g*8 .. g*8+7" "0,1" line.long 0x10 "TIO8_PL_SWRST," bitfld.long 0x10 7. "CH7,reset TIO_Plus resources of channel x" "0,1" bitfld.long 0x10 6. "CH6,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 5. "CH5,reset TIO_Plus resources of channel x" "0,1" bitfld.long 0x10 4. "CH4,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 3. "CH3,reset TIO_Plus resources of channel x" "0,1" bitfld.long 0x10 2. "CH2,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 1. "CH1,reset TIO_Plus resources of channel x" "0,1" bitfld.long 0x10 0. "CH0,reset TIO_Plus resources of channel x" "0,1" group.long 0x4000++0x4F line.long 0x0 "CCM8_ARP0_CTRL," bitfld.long 0x0 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x0 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x0 0.--15. 1. "ADDR,ARP base address." line.long 0x4 "CCM8_ARP0_PROT," bitfld.long 0x4 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x4 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x4 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x4 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x4 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x8 "CCM8_ARP1_CTRL," bitfld.long 0x8 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x8 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x8 0.--15. 1. "ADDR,ARP base address." line.long 0xC "CCM8_ARP1_PROT," bitfld.long 0xC 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0xC 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0xC 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0xC 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0xC 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x10 "CCM8_ARP2_CTRL," bitfld.long 0x10 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x10 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x10 0.--15. 1. "ADDR,ARP base address." line.long 0x14 "CCM8_ARP2_PROT," bitfld.long 0x14 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x14 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x14 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x14 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x14 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x18 "CCM8_ARP3_CTRL," bitfld.long 0x18 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x18 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x18 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x18 0.--15. 1. "ADDR,ARP base address." line.long 0x1C "CCM8_ARP3_PROT," bitfld.long 0x1C 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x1C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x1C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x1C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x1C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x20 "CCM8_ARP4_CTRL," bitfld.long 0x20 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x20 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x20 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x20 0.--15. 1. "ADDR,ARP base address." line.long 0x24 "CCM8_ARP4_PROT," bitfld.long 0x24 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x24 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x24 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x24 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x24 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x28 "CCM8_ARP5_CTRL," bitfld.long 0x28 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x28 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x28 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x28 0.--15. 1. "ADDR,ARP base address." line.long 0x2C "CCM8_ARP5_PROT," bitfld.long 0x2C 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x2C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x2C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x2C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x2C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x30 "CCM8_ARP6_CTRL," bitfld.long 0x30 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x30 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x30 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x30 0.--15. 1. "ADDR,ARP base address." line.long 0x34 "CCM8_ARP6_PROT," bitfld.long 0x34 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x34 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x34 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x34 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x34 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x38 "CCM8_ARP7_CTRL," bitfld.long 0x38 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x38 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x38 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x38 0.--15. 1. "ADDR,ARP base address." line.long 0x3C "CCM8_ARP7_PROT," bitfld.long 0x3C 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x3C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x3C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x3C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x3C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x40 "CCM8_ARP8_CTRL," bitfld.long 0x40 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x40 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x40 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x40 0.--15. 1. "ADDR,ARP base address." line.long 0x44 "CCM8_ARP8_PROT," bitfld.long 0x44 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x44 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x44 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x44 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x44 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x48 "CCM8_ARP9_CTRL," bitfld.long 0x48 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x48 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x48 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x48 0.--15. 1. "ADDR,ARP base address." line.long 0x4C "CCM8_ARP9_PROT," bitfld.long 0x4C 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x4C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x4C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x4C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x4C 0. "WPROT0,Write Protection MCS channel x." "0,1" group.long 0x41D4++0xB line.long 0x0 "CCM8_HW_CONF2," bitfld.long 0x0 18. "AXIM_DATA_SIZE,Defines the data bus width of the AXI master interface" "0,1" bitfld.long 0x0 16. "AXIS_DATA_SIZE,Defines the data bus width of the AXI slave interface" "0,1" newline bitfld.long 0x0 9. "TIO_OUT_RST,TIO_OUT reset level" "0,1" bitfld.long 0x0 7. "AXIM_POSTED_WRITE,Write transaction without response" "0,1" newline bitfld.long 0x0 6. "AXIM_SEC_ACC,Secure AXI master access constant" "0,1" bitfld.long 0x0 5. "AXIM_PRIV_ACC,Privileged AXI master access constant" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "AXIM_ID_WIDTH,Defines which LSB of AXIM_ID are send to the bus" line.long 0x4 "CCM8_AEIM_STA," bitfld.long 0x4 24.--25. "AEIM_XPT_STA,AEIM Exception status." "0,1,2,3" hexmask.long.word 0x4 0.--15. 1. "AEIM_XPT_ADDR,Exception Address." line.long 0x8 "CCM8_HW_CONF," bitfld.long 0x8 31. "AEI_RDATA_PIPELINE_STAGE,Read data pipeline stage implemented" "0,1" bitfld.long 0x8 30. "AEI_ADDR_PIPELINE_STAGE,Address pipeline stage implemented" "0,1" newline bitfld.long 0x8 29. "INT_CLK_EN_GEN,Internal clock enable generation" "0,1" hexmask.long.byte 0x8 24.--28. 1. "TOM_TRIG_INTCHAIN,TOM internal trigger chain length without synchronization register" newline hexmask.long.byte 0x8 20.--23. 1. "ATOM_TRIG_INTCHAIN,ATOM internal trigger chain length without synchronization register" bitfld.long 0x8 19. "IRQ_MODE_SINGLE_PULSE,Signalize availability of Single Pulse IRQ mode" "0,1" newline bitfld.long 0x8 18. "IRQ_MODE_PULSE_NOTIFY,Signalize availability of Pulse Notoify IRQ mode" "0,1" bitfld.long 0x8 17. "IRQ_MODE_PULSE,Signalize availability of Pulse IRQ mode" "0,1" newline bitfld.long 0x8 16. "IRQ_MODE_LEVEL,Signalize availability of Level IRQ mode" "0,1" bitfld.long 0x8 15. "RESET_ACTIVE,Active level of asynchronous reset" "0,1" newline bitfld.long 0x8 13. "ERM,Enable RAM1 MSB for available MCS modules" "0,1" bitfld.long 0x8 12. "RAM_INIT_RST,RAM initialization from reset" "0,1" newline bitfld.long 0x8 9.--11. "TOM_TRIG_CHAIN,TOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8. "TOM_OUT_RST,TOM_OUT reset level" "0,1" newline bitfld.long 0x8 5.--7. "ATOM_TRIG_CHAIN,ATOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "ATOM_OUT_RST,ATOM_OUT reset level" "0,1" newline bitfld.long 0x8 3. "CFG_CLOCK_RATE,Clocks per ARU transfer" "0,1" bitfld.long 0x8 2. "SYNC_INPUT_REG,Additional pipelined stage in synchronous bridge mode" "0,1" newline bitfld.long 0x8 1. "BRIDGE_MODE_RST,Bridge mode after reset" "0,1" bitfld.long 0x8 0. "GRSTEN,Global Reset Enable" "0,1" group.long 0x41EC++0x7 line.long 0x0 "CCM8_ATOM_OUT," bitfld.long 0x0 31. "ATOM_IP1_OUT_N7,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" bitfld.long 0x0 30. "ATOM_IP1_OUT_N6,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 29. "ATOM_IP1_OUT_N5,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" bitfld.long 0x0 28. "ATOM_IP1_OUT_N4,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 27. "ATOM_IP1_OUT_N3,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" bitfld.long 0x0 26. "ATOM_IP1_OUT_N2,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 25. "ATOM_IP1_OUT_N1,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" bitfld.long 0x0 24. "ATOM_IP1_OUT_N0,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 23. "ATOM_IP1_OUT7,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" bitfld.long 0x0 22. "ATOM_IP1_OUT6,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 21. "ATOM_IP1_OUT5,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" bitfld.long 0x0 20. "ATOM_IP1_OUT4,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 19. "ATOM_IP1_OUT3,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" bitfld.long 0x0 18. "ATOM_IP1_OUT2,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 17. "ATOM_IP1_OUT1,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" bitfld.long 0x0 16. "ATOM_IP1_OUT0,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 15. "ATOM_I_OUT_N7,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 14. "ATOM_I_OUT_N6,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 13. "ATOM_I_OUT_N5,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 12. "ATOM_I_OUT_N4,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 11. "ATOM_I_OUT_N3,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 10. "ATOM_I_OUT_N2,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 9. "ATOM_I_OUT_N1,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 8. "ATOM_I_OUT_N0,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 7. "ATOM_I_OUT7,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 6. "ATOM_I_OUT6,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 5. "ATOM_I_OUT5,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 4. "ATOM_I_OUT4,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 3. "ATOM_I_OUT3,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 2. "ATOM_I_OUT2,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 1. "ATOM_I_OUT1,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 0. "ATOM_I_OUT0,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" line.long 0x4 "CCM8_CMU_CLK_CFG," bitfld.long 0x4 28.--29. "CLK7_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x4 24.--25. "CLK6_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 20.--21. "CLK5_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x4 16.--17. "CLK4_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 12.--13. "CLK3_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x4 8.--9. "CLK2_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 4.--5. "CLK1_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x4 0.--1. "CLK0_SRC,Clock y source signal selector" "0,1,2,3" group.long 0x41F8++0x7 line.long 0x0 "CCM8_CFG," bitfld.long 0x0 31. "TBU_DIR2,DIR1 input signal of module TBU timebase [z]." "0,1" bitfld.long 0x0 30. "TBU_DIR1,DIR1 input signal of module TBU timebase [z]." "0,1" newline bitfld.long 0x0 16.--17. "CLS_CLK_DIV,Cluster Clock Divider." "0,1,2,3" bitfld.long 0x0 8. "EN_TIO_DTM,Enable TIO and connected DTM" "0,1" newline bitfld.long 0x0 7. "EN_CMP_MON,Enable CMP and MON" "0,1" bitfld.long 0x0 6. "EN_PSM,Enable PSM" "0,1" newline bitfld.long 0x0 5. "EN_BRC,Enable BRC" "0,1" bitfld.long 0x0 4. "EN_DPLL_MAP,Enable DPLL and MAP" "0,1" newline bitfld.long 0x0 3. "EN_MCS,Enable MCS" "0,1" bitfld.long 0x0 2. "EN_ATOM_ADTM,Enable ATOM and ADTM" "0,1" newline bitfld.long 0x0 1. "EN_TOM_SPE_TDTM,Enable TOM SPE and TDTM" "0,1" bitfld.long 0x0 0. "EN_TIM,Enable TIM" "0,1" line.long 0x4 "CCM8_PROT," bitfld.long 0x4 0. "CLS_PROT,Cluster Protection" "0,1" group.long 0x5000++0xB line.long 0x0 "AXIM8_FREE," bitfld.long 0x0 3. "FREE3,This bit represents the allocation status of the slot [t]" "0,1" bitfld.long 0x0 2. "FREE2,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 1. "FREE1,This bit represents the allocation status of the slot [t]" "0,1" bitfld.long 0x0 0. "FREE0,This bit represents the allocation status of the slot [t]" "0,1" line.long 0x4 "AXIM8_REQUEST," hexmask.long.byte 0x4 24.--31. 1. "REQID,This bit field shows the new allocated slot as binary encoded index. If no slot could be allocated this bit field is read as all 1 (0xff)." bitfld.long 0x4 3. "REQ1HOT3,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 2. "REQ1HOT2,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" bitfld.long 0x4 1. "REQ1HOT1,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 0. "REQ1HOT0,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" line.long 0x8 "AXIM8_RELEASE," bitfld.long 0x8 3. "RELREQ3,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" bitfld.long 0x8 2. "RELREQ2,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 1. "RELREQ1,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" bitfld.long 0x8 0. "RELREQ0,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" group.long 0x5020++0x3 line.long 0x0 "AXIM8_SLOT0_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5028++0x3 line.long 0x0 "AXIM8_SLOT0_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5030++0xB line.long 0x0 "AXIM8_SLOT0_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM8_SLOT0_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM8_SLOT0_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5040++0x3 line.long 0x0 "AXIM8_SLOT1_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5048++0x3 line.long 0x0 "AXIM8_SLOT1_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5050++0xB line.long 0x0 "AXIM8_SLOT1_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM8_SLOT1_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM8_SLOT1_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5060++0x3 line.long 0x0 "AXIM8_SLOT2_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5068++0x3 line.long 0x0 "AXIM8_SLOT2_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5070++0xB line.long 0x0 "AXIM8_SLOT2_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM8_SLOT2_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM8_SLOT2_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5080++0x3 line.long 0x0 "AXIM8_SLOT3_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5088++0x3 line.long 0x0 "AXIM8_SLOT3_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5090++0xB line.long 0x0 "AXIM8_SLOT3_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM8_SLOT3_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM8_SLOT3_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" repeat 16384. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10000)++0x3 line.long 0x0 "MCS8_MEM[$1]," hexmask.long 0x0 0.--31. 1. "DATA,MCS memory location." repeat.end tree.end tree "GTM_CLS9" base ad:0x74120000 group.long 0x1800++0x2F line.long 0x0 "ATOM9_CH0_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM9_CH0_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM9_CH0_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM9_CH0_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM9_CH0_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM9_CH0_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM9_CH0_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM9_CH0_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM9_CH0_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM9_CH0_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM9_CH0_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM9_CH0_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1834++0x3 line.long 0x0 "ATOM9_CH0_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1880++0x2F line.long 0x0 "ATOM9_CH1_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM9_CH1_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM9_CH1_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM9_CH1_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM9_CH1_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM9_CH1_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM9_CH1_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM9_CH1_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM9_CH1_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM9_CH1_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM9_CH1_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM9_CH1_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x18B4++0x3 line.long 0x0 "ATOM9_CH1_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1900++0x2F line.long 0x0 "ATOM9_CH2_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM9_CH2_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM9_CH2_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM9_CH2_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM9_CH2_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM9_CH2_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM9_CH2_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM9_CH2_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM9_CH2_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM9_CH2_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM9_CH2_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM9_CH2_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1934++0x3 line.long 0x0 "ATOM9_CH2_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1980++0x2F line.long 0x0 "ATOM9_CH3_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM9_CH3_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM9_CH3_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM9_CH3_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM9_CH3_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM9_CH3_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM9_CH3_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM9_CH3_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM9_CH3_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM9_CH3_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM9_CH3_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM9_CH3_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x19B4++0x3 line.long 0x0 "ATOM9_CH3_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A00++0x2F line.long 0x0 "ATOM9_CH4_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM9_CH4_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM9_CH4_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM9_CH4_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM9_CH4_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM9_CH4_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM9_CH4_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM9_CH4_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM9_CH4_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM9_CH4_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM9_CH4_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM9_CH4_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1A34++0x3 line.long 0x0 "ATOM9_CH4_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1A80++0x2F line.long 0x0 "ATOM9_CH5_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM9_CH5_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM9_CH5_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM9_CH5_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM9_CH5_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM9_CH5_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM9_CH5_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM9_CH5_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM9_CH5_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM9_CH5_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM9_CH5_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM9_CH5_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1AB4++0x3 line.long 0x0 "ATOM9_CH5_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B00++0x2F line.long 0x0 "ATOM9_CH6_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM9_CH6_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM9_CH6_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM9_CH6_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM9_CH6_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM9_CH6_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM9_CH6_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM9_CH6_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM9_CH6_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM9_CH6_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM9_CH6_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM9_CH6_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1B34++0x3 line.long 0x0 "ATOM9_CH6_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1B80++0x2F line.long 0x0 "ATOM9_CH7_RDADDR," hexmask.long.word 0x0 16.--24. 1. "RDADDR1,ARU Read address 1." hexmask.long.word 0x0 0.--8. 1. "RDADDR0,ARU Read address 0." line.long 0x4 "ATOM9_CH7_CTRL," bitfld.long 0x4 31. "FREEZE,ATOM Freeze Mode enable" "0,1" bitfld.long 0x4 30. "SOMB,SOMB mode" "0,1" newline bitfld.long 0x4 29. "EXT_FUPD,External forced update" "0,1" bitfld.long 0x4 27. "ABM,ARU blocking mode" "0,1" newline bitfld.long 0x4 26. "OSM,One-shot mode" "0,1" bitfld.long 0x4 25. "SLA,'Serve last' ARU communication strategy" "0,1" newline bitfld.long 0x4 24. "TRIGOUT,Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx." "0,1" bitfld.long 0x4 23. "EXTTRIGOUT,Select TIM_EXT_CAPTURE(x) as potential output signal TRIG_[x]" "0,1" newline bitfld.long 0x4 22. "EXT_TRIG,Select TIM_EXT_CAPTURE(x) as trigger signal" "0,1" bitfld.long 0x4 21. "OSM_TRIG,Enable trigger of one-shot pulse by trigger signal OSM_TRIG" "0,1" newline bitfld.long 0x4 20. "RST_CCU0,Reset source of CCU0" "0,1" bitfld.long 0x4 18.--19. "UDMODE,Up/down counter mode" "0,1,2,3" newline bitfld.long 0x4 17. "TRIG_PULSE,Trigger output pulse length of one SYS_CLK period" "0,1" bitfld.long 0x4 16. "WR_REQ,CPU Write request bit for late compare register update." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "CLK_SRC,CMU clock source (SOMS)/ register for CMU clock source (SOMP)." bitfld.long 0x4 11. "SL,Initial signal level." "0,1" newline bitfld.long 0x4 10. "EUPM,Extended update mode" "0,1" bitfld.long 0x4 9. "CMP_CTRL,CCUx compare strategy select." "0,1" newline hexmask.long.byte 0x4 4.--8. 1. "ACB,ATOM Mode control bits." bitfld.long 0x4 3. "ARU_EN,ARU Input stream enable." "0,1" newline bitfld.long 0x4 2. "TB12_SEL,Select time base value TBU_TS1 or TBU_TS2." "0,1" bitfld.long 0x4 0.--1. "MODE,ATOM channel mode select." "0,1,2,3" line.long 0x8 "ATOM9_CH7_SR0," hexmask.long.tbyte 0x8 0.--23. 1. "SR0,ATOM channel x shadow register SR0." line.long 0xC "ATOM9_CH7_SR1," hexmask.long.tbyte 0xC 0.--23. 1. "SR1,ATOM channel x shadow register SR1." line.long 0x10 "ATOM9_CH7_CM0," hexmask.long.tbyte 0x10 0.--23. 1. "CM0,ATOM CCU0 compare register." line.long 0x14 "ATOM9_CH7_CM1," hexmask.long.tbyte 0x14 0.--23. 1. "CM1,ATOM CCU1 compare register." line.long 0x18 "ATOM9_CH7_CN0," hexmask.long.tbyte 0x18 0.--23. 1. "CN0,ATOM CCU0 counter register." line.long 0x1C "ATOM9_CH7_STAT," bitfld.long 0x1C 29. "OSM_RTF,Oneshot mode retrigger failed flag." "0,1" hexmask.long.byte 0x1C 24.--28. 1. "ACBO,ATOM Internal status bits." newline bitfld.long 0x1C 23. "DR,ARU data rejected flag" "0,1" bitfld.long 0x1C 22. "WRF,Write request of CPU failed for late update." "0,1" newline bitfld.long 0x1C 21. "DV,Valid ARU Data stored in compare registers." "0,1" hexmask.long.byte 0x1C 16.--20. 1. "ACBI,ATOM Mode control bits." newline bitfld.long 0x1C 0. "OL,Output signal level of ATOM_CHx_OUT." "0,1" line.long 0x20 "ATOM9_CH7_IRQ_NOTIFY," bitfld.long 0x20 1. "CCU1TC,CCU[k] Trigger condition interrupt for channel x." "0,1" bitfld.long 0x20 0. "CCU0TC,CCU[k] Trigger condition interrupt for channel x." "0,1" line.long 0x24 "ATOM9_CH7_IRQ_EN," bitfld.long 0x24 1. "CCU1TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" bitfld.long 0x24 0. "CCU0TC_IRQ_EN,ATOM_CCU[k]TC_IRQ interrupt enable." "0,1" line.long 0x28 "ATOM9_CH7_IRQ_FORCINT," bitfld.long 0x28 1. "TRG_CCU1TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" bitfld.long 0x28 0. "TRG_CCU0TC,Trigger ATOM_CCU[k]TC_IRQ interrupt by software." "0,1" line.long 0x2C "ATOM9_CH7_IRQ_MODE," bitfld.long 0x2C 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x1BB4++0x3 line.long 0x0 "ATOM9_CH7_CTRL_SR," hexmask.long.byte 0x0 12.--15. 1. "CLK_SRC_SR,Shadow register for ATOM[i]_CH[x]_CTRL.CLK_SRC" bitfld.long 0x0 11. "SL_SR,Shadow register for ATOM[i]_CH[x]_CTRL.SL" "0,1" group.long 0x1C40++0x1F line.long 0x0 "ATOM9_AGC_GLB_CTRL," bitfld.long 0x0 30.--31. "UPEN_CTRL7,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 28.--29. "UPEN_CTRL6,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 26.--27. "UPEN_CTRL5,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 24.--25. "UPEN_CTRL4,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 22.--23. "UPEN_CTRL3,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 20.--21. "UPEN_CTRL2,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 18.--19. "UPEN_CTRL1,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" bitfld.long 0x0 16.--17. "UPEN_CTRL0,ATOM channel [k] enable update of register ATOM[i]_CH[k]_CM0 ATOM[i]_CH[k]_CM1 ATOM[i]_CH[k]_CTRL.SL and ATOM[i]_CH[k]_CTRL.CLK_SRC from ATOM[i]_CH[k]_SR0 ATOM[i]_CH[k]_SR1 ATOM[i]_CH[k]_CTRL_SR.SL_SR and ATOM[i]_CH[k]_CTRL_SR.CLK_SRC_SR." "0,1,2,3" newline bitfld.long 0x0 15. "RST_CH7,Software reset of channel [k]" "0,1" bitfld.long 0x0 14. "RST_CH6,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 13. "RST_CH5,Software reset of channel [k]" "0,1" bitfld.long 0x0 12. "RST_CH4,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 11. "RST_CH3,Software reset of channel [k]" "0,1" bitfld.long 0x0 10. "RST_CH2,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 9. "RST_CH1,Software reset of channel [k]" "0,1" bitfld.long 0x0 8. "RST_CH0,Software reset of channel [k]" "0,1" newline bitfld.long 0x0 0. "HOST_TRIG,Trigger request signal (see AGC) to update the register ATOM[i]_AGC_ENDIS_STAT and ATOM[i]_AGC_OUTEN_STAT" "0,1" line.long 0x4 "ATOM9_AGC_ENDIS_CTRL," bitfld.long 0x4 14.--15. "ENDIS_CTRL7,ATOM channel [k] enable/disable update value." "0,1,2,3" bitfld.long 0x4 12.--13. "ENDIS_CTRL6,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 10.--11. "ENDIS_CTRL5,ATOM channel [k] enable/disable update value." "0,1,2,3" bitfld.long 0x4 8.--9. "ENDIS_CTRL4,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 6.--7. "ENDIS_CTRL3,ATOM channel [k] enable/disable update value." "0,1,2,3" bitfld.long 0x4 4.--5. "ENDIS_CTRL2,ATOM channel [k] enable/disable update value." "0,1,2,3" newline bitfld.long 0x4 2.--3. "ENDIS_CTRL1,ATOM channel [k] enable/disable update value." "0,1,2,3" bitfld.long 0x4 0.--1. "ENDIS_CTRL0,ATOM channel [k] enable/disable update value." "0,1,2,3" line.long 0x8 "ATOM9_AGC_ENDIS_STAT," bitfld.long 0x8 14.--15. "ENDIS_STAT7,ATOM channel [k] enable/disable" "0,1,2,3" bitfld.long 0x8 12.--13. "ENDIS_STAT6,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 10.--11. "ENDIS_STAT5,ATOM channel [k] enable/disable" "0,1,2,3" bitfld.long 0x8 8.--9. "ENDIS_STAT4,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 6.--7. "ENDIS_STAT3,ATOM channel [k] enable/disable" "0,1,2,3" bitfld.long 0x8 4.--5. "ENDIS_STAT2,ATOM channel [k] enable/disable" "0,1,2,3" newline bitfld.long 0x8 2.--3. "ENDIS_STAT1,ATOM channel [k] enable/disable" "0,1,2,3" bitfld.long 0x8 0.--1. "ENDIS_STAT0,ATOM channel [k] enable/disable" "0,1,2,3" line.long 0xC "ATOM9_AGC_ACT_TB," bitfld.long 0xC 25.--26. "TBU_SEL,Selection of time base used for comparison" "0,1,2,3" bitfld.long 0xC 24. "TB_TRIG,Set trigger request" "0,1" newline hexmask.long.tbyte 0xC 0.--23. 1. "ACT_TB,Specifies the signed compare value with selected signal TBU_TS[x] x=0..2. If selected TBU_TS[x] value is in the interval [ATOM[i]_AGC_ACT_TB.ACT_TB-007FFFFFh ATOM[i]_AGC_ACT_TB.ACT_TB] the event is in the past and the trigger is generated.." line.long 0x10 "ATOM9_AGC_OUTEN_CTRL," bitfld.long 0x10 14.--15. "OUTEN_CTRL7,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" bitfld.long 0x10 12.--13. "OUTEN_CTRL6,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 10.--11. "OUTEN_CTRL5,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" bitfld.long 0x10 8.--9. "OUTEN_CTRL4,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 6.--7. "OUTEN_CTRL3,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" bitfld.long 0x10 4.--5. "OUTEN_CTRL2,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" newline bitfld.long 0x10 2.--3. "OUTEN_CTRL1,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" bitfld.long 0x10 0.--1. "OUTEN_CTRL0,Output ATOM_OUT [k] enable/disable update value" "0,1,2,3" line.long 0x14 "ATOM9_AGC_OUTEN_STAT," bitfld.long 0x14 14.--15. "OUTEN_STAT7,Control/status of output ATOM_OUT [k]" "0,1,2,3" bitfld.long 0x14 12.--13. "OUTEN_STAT6,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 10.--11. "OUTEN_STAT5,Control/status of output ATOM_OUT [k]" "0,1,2,3" bitfld.long 0x14 8.--9. "OUTEN_STAT4,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 6.--7. "OUTEN_STAT3,Control/status of output ATOM_OUT [k]" "0,1,2,3" bitfld.long 0x14 4.--5. "OUTEN_STAT2,Control/status of output ATOM_OUT [k]" "0,1,2,3" newline bitfld.long 0x14 2.--3. "OUTEN_STAT1,Control/status of output ATOM_OUT [k]" "0,1,2,3" bitfld.long 0x14 0.--1. "OUTEN_STAT0,Control/status of output ATOM_OUT [k]" "0,1,2,3" line.long 0x18 "ATOM9_AGC_FUPD_CTRL," bitfld.long 0x18 30.--31. "RSTCN0_CH7,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" bitfld.long 0x18 28.--29. "RSTCN0_CH6,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 26.--27. "RSTCN0_CH5,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" bitfld.long 0x18 24.--25. "RSTCN0_CH4,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 22.--23. "RSTCN0_CH3,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" bitfld.long 0x18 20.--21. "RSTCN0_CH2,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 18.--19. "RSTCN0_CH1,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" bitfld.long 0x18 16.--17. "RSTCN0_CH0,Reset ATOM[i]_CH[k]_CN0 of channel [k] on force update event" "0,1,2,3" newline bitfld.long 0x18 14.--15. "FUPD_CTRL7,Force update of ATOM channel [k] operation registers" "0,1,2,3" bitfld.long 0x18 12.--13. "FUPD_CTRL6,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 10.--11. "FUPD_CTRL5,Force update of ATOM channel [k] operation registers" "0,1,2,3" bitfld.long 0x18 8.--9. "FUPD_CTRL4,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 6.--7. "FUPD_CTRL3,Force update of ATOM channel [k] operation registers" "0,1,2,3" bitfld.long 0x18 4.--5. "FUPD_CTRL2,Force update of ATOM channel [k] operation registers" "0,1,2,3" newline bitfld.long 0x18 2.--3. "FUPD_CTRL1,Force update of ATOM channel [k] operation registers" "0,1,2,3" bitfld.long 0x18 0.--1. "FUPD_CTRL0,Force update of ATOM channel [k] operation registers" "0,1,2,3" line.long 0x1C "ATOM9_AGC_INT_TRIG," bitfld.long 0x1C 14.--15. "INT_TRIG7,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" bitfld.long 0x1C 12.--13. "INT_TRIG6,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 10.--11. "INT_TRIG5,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" bitfld.long 0x1C 8.--9. "INT_TRIG4,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 6.--7. "INT_TRIG3,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" bitfld.long 0x1C 4.--5. "INT_TRIG2,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" newline bitfld.long 0x1C 2.--3. "INT_TRIG1,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" bitfld.long 0x1C 0.--1. "INT_TRIG0,Select input signal TRIG_[k] as a trigger source" "0,1,2,3" group.long 0x2000++0x27 line.long 0x0 "MCS9_CH0_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS9_CH0_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS9_CH0_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS9_CH0_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS9_CH0_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS9_CH0_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS9_CH0_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS9_CH0_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS9_CH0_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS9_CH0_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x203C++0x3 line.long 0x0 "MCS9_CH0_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x20E0++0x17 line.long 0x0 "MCS9_CH0_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS9_CH0_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS9_CH0_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS9_CH0_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS9_CH0_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS9_CH0_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2100++0x27 line.long 0x0 "MCS9_CH1_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS9_CH1_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS9_CH1_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS9_CH1_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS9_CH1_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS9_CH1_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS9_CH1_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS9_CH1_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS9_CH1_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS9_CH1_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x213C++0x3 line.long 0x0 "MCS9_CH1_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x21E0++0x17 line.long 0x0 "MCS9_CH1_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS9_CH1_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS9_CH1_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS9_CH1_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS9_CH1_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS9_CH1_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2200++0x27 line.long 0x0 "MCS9_CH2_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS9_CH2_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS9_CH2_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS9_CH2_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS9_CH2_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS9_CH2_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS9_CH2_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS9_CH2_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS9_CH2_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS9_CH2_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x223C++0x3 line.long 0x0 "MCS9_CH2_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x22E0++0x17 line.long 0x0 "MCS9_CH2_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS9_CH2_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS9_CH2_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS9_CH2_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS9_CH2_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS9_CH2_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2300++0x27 line.long 0x0 "MCS9_CH3_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS9_CH3_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS9_CH3_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS9_CH3_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS9_CH3_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS9_CH3_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS9_CH3_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS9_CH3_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS9_CH3_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS9_CH3_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x233C++0x3 line.long 0x0 "MCS9_CH3_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x23E0++0x17 line.long 0x0 "MCS9_CH3_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS9_CH3_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS9_CH3_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS9_CH3_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS9_CH3_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS9_CH3_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2400++0x27 line.long 0x0 "MCS9_CH4_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS9_CH4_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS9_CH4_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS9_CH4_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS9_CH4_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS9_CH4_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS9_CH4_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS9_CH4_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS9_CH4_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS9_CH4_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x243C++0x3 line.long 0x0 "MCS9_CH4_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x24E0++0x17 line.long 0x0 "MCS9_CH4_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS9_CH4_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS9_CH4_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS9_CH4_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS9_CH4_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS9_CH4_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2500++0x27 line.long 0x0 "MCS9_CH5_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS9_CH5_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS9_CH5_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS9_CH5_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS9_CH5_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS9_CH5_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS9_CH5_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS9_CH5_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS9_CH5_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS9_CH5_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x253C++0x3 line.long 0x0 "MCS9_CH5_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x25E0++0x17 line.long 0x0 "MCS9_CH5_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS9_CH5_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS9_CH5_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS9_CH5_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS9_CH5_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS9_CH5_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2600++0x27 line.long 0x0 "MCS9_CH6_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS9_CH6_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS9_CH6_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS9_CH6_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS9_CH6_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS9_CH6_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS9_CH6_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS9_CH6_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS9_CH6_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS9_CH6_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x263C++0x3 line.long 0x0 "MCS9_CH6_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x26E0++0x17 line.long 0x0 "MCS9_CH6_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS9_CH6_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS9_CH6_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS9_CH6_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS9_CH6_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS9_CH6_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2700++0x27 line.long 0x0 "MCS9_CH7_R0," hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x4 "MCS9_CH7_R1," hexmask.long.tbyte 0x4 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x8 "MCS9_CH7_R2," hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0xC "MCS9_CH7_R3," hexmask.long.tbyte 0xC 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x10 "MCS9_CH7_R4," hexmask.long.tbyte 0x10 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x14 "MCS9_CH7_R5," hexmask.long.tbyte 0x14 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x18 "MCS9_CH7_R6," hexmask.long.tbyte 0x18 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x1C "MCS9_CH7_R7," hexmask.long.tbyte 0x1C 0.--23. 1. "DATA,Data of general purpose register R[y]." line.long 0x20 "MCS9_CH7_CTRL," bitfld.long 0x20 10. "SAT,Successful ARU transfer bit." "0,1" bitfld.long 0x20 9. "CWT,Cancel WURM instruction state." "0,1" newline bitfld.long 0x20 8. "CAT,Cancel ARU transfer state." "0,1" bitfld.long 0x20 7. "N,Negative bit state." "0,1" newline bitfld.long 0x20 6. "V,Overflow bit state." "0,1" bitfld.long 0x20 5. "Z,Zero bit state." "0,1" newline bitfld.long 0x20 4. "CY,Carry bit state." "0,1" bitfld.long 0x20 2. "ERR,Error state." "0,1" newline bitfld.long 0x20 1. "IRQ,Interrupt state." "0,1" bitfld.long 0x20 0. "EN,Enable/Disable Request of MCS-channel x." "0,1" line.long 0x24 "MCS9_CH7_ACB," bitfld.long 0x24 4. "ACB4,ARU Control bit k." "0,1" bitfld.long 0x24 3. "ACB3,ARU Control bit k." "0,1" newline bitfld.long 0x24 2. "ACB2,ARU Control bit k." "0,1" bitfld.long 0x24 1. "ACB1,ARU Control bit k." "0,1" newline bitfld.long 0x24 0. "ACB0,ARU Control bit k." "0,1" group.long 0x273C++0x3 line.long 0x0 "MCS9_CH7_MHB," hexmask.long.byte 0x0 0.--7. 1. "DATA,Data of memory high bit register MHB." group.long 0x27E0++0x17 line.long 0x0 "MCS9_CH7_PC," hexmask.long.word 0x0 0.--15. 1. "PC,Current Program Counter." line.long 0x4 "MCS9_CH7_IRQ_NOTIFY," bitfld.long 0x4 2. "ERR_IRQ,MCS channel x ERR interrupt." "0,1" bitfld.long 0x4 0. "MCS_IRQ,Interrupt request by MCS-channel x." "0,1" line.long 0x8 "MCS9_CH7_IRQ_EN," bitfld.long 0x8 2. "ERR_IRQ_EN,MCS channel x ERR_IRQ interrupt enable" "0,1" bitfld.long 0x8 0. "MCS_IRQ_EN,MCS channel x MCS_IRQ interrupt enable" "0,1" line.long 0xC "MCS9_CH7_IRQ_FORCINT," bitfld.long 0xC 2. "TRG_ERR_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" bitfld.long 0xC 0. "TRG_MCS_IRQ,Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software" "0,1" line.long 0x10 "MCS9_CH7_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" line.long 0x14 "MCS9_CH7_EIRQ_EN," bitfld.long 0x14 2. "ERR_EIRQ_EN,MCS channel x ERR_EIRQ error interrupt enable" "0,1" bitfld.long 0x14 0. "MCS_EIRQ_EN,MCS_EIRQ_EN: MCS channel x MCS_EIRQ error interrupt enable" "0,1" group.long 0x2E28++0x7 line.long 0x0 "MCS9_CTRG," bitfld.long 0x0 23. "TRG23,Trigger bit o." "0,1" bitfld.long 0x0 22. "TRG22,Trigger bit o." "0,1" newline bitfld.long 0x0 21. "TRG21,Trigger bit o." "0,1" bitfld.long 0x0 20. "TRG20,Trigger bit o." "0,1" newline bitfld.long 0x0 19. "TRG19,Trigger bit o." "0,1" bitfld.long 0x0 18. "TRG18,Trigger bit o." "0,1" newline bitfld.long 0x0 17. "TRG17,Trigger bit o." "0,1" bitfld.long 0x0 16. "TRG16,Trigger bit o." "0,1" newline bitfld.long 0x0 15. "TRG15,Trigger bit n." "0,1" bitfld.long 0x0 14. "TRG14,Trigger bit n." "0,1" newline bitfld.long 0x0 13. "TRG13,Trigger bit n." "0,1" bitfld.long 0x0 12. "TRG12,Trigger bit n." "0,1" newline bitfld.long 0x0 11. "TRG11,Trigger bit n." "0,1" bitfld.long 0x0 10. "TRG10,Trigger bit n." "0,1" newline bitfld.long 0x0 9. "TRG9,Trigger bit n." "0,1" bitfld.long 0x0 8. "TRG8,Trigger bit n." "0,1" newline bitfld.long 0x0 7. "TRG7,Trigger bit m." "0,1" bitfld.long 0x0 6. "TRG6,Trigger bit m." "0,1" newline bitfld.long 0x0 5. "TRG5,Trigger bit m." "0,1" bitfld.long 0x0 4. "TRG4,Trigger bit m." "0,1" newline bitfld.long 0x0 3. "TRG3,Trigger bit m." "0,1" bitfld.long 0x0 2. "TRG2,Trigger bit m." "0,1" newline bitfld.long 0x0 1. "TRG1,Trigger bit m." "0,1" bitfld.long 0x0 0. "TRG0,Trigger bit m." "0,1" line.long 0x4 "MCS9_STRG," bitfld.long 0x4 23. "TRG23,Trigger bit k." "0,1" bitfld.long 0x4 22. "TRG22,Trigger bit k." "0,1" newline bitfld.long 0x4 21. "TRG21,Trigger bit k." "0,1" bitfld.long 0x4 20. "TRG20,Trigger bit k." "0,1" newline bitfld.long 0x4 19. "TRG19,Trigger bit k." "0,1" bitfld.long 0x4 18. "TRG18,Trigger bit k." "0,1" newline bitfld.long 0x4 17. "TRG17,Trigger bit k." "0,1" bitfld.long 0x4 16. "TRG16,Trigger bit k." "0,1" newline bitfld.long 0x4 15. "TRG15,Trigger bit k." "0,1" bitfld.long 0x4 14. "TRG14,Trigger bit k." "0,1" newline bitfld.long 0x4 13. "TRG13,Trigger bit k." "0,1" bitfld.long 0x4 12. "TRG12,Trigger bit k." "0,1" newline bitfld.long 0x4 11. "TRG11,Trigger bit k." "0,1" bitfld.long 0x4 10. "TRG10,Trigger bit k." "0,1" newline bitfld.long 0x4 9. "TRG9,Trigger bit k." "0,1" bitfld.long 0x4 8. "TRG8,Trigger bit k." "0,1" newline bitfld.long 0x4 7. "TRG7,Trigger bit k." "0,1" bitfld.long 0x4 6. "TRG6,Trigger bit k." "0,1" newline bitfld.long 0x4 5. "TRG5,Trigger bit k." "0,1" bitfld.long 0x4 4. "TRG4,Trigger bit k." "0,1" newline bitfld.long 0x4 3. "TRG3,Trigger bit k." "0,1" bitfld.long 0x4 2. "TRG2,Trigger bit k." "0,1" newline bitfld.long 0x4 1. "TRG1,Trigger bit k." "0,1" bitfld.long 0x4 0. "TRG0,Trigger bit k." "0,1" group.long 0x2F00++0x13 line.long 0x0 "MCS9_CTRL_STAT," bitfld.long 0x0 26. "HLT_AEIM_ERR,Halt on AEI bus master error." "0,1" bitfld.long 0x0 25. "EN_HVD,Enable Modified Harvard architecture." "0,1" newline bitfld.long 0x0 24. "EN_TIM_FOUT,Enable routing of TIM[i]_CH[x]_F_OUT signal." "0,1" bitfld.long 0x0 20.--22. "ERR_SRC_ID,Error source identifier." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "RAM_RST,RAM reset bit." "0,1" hexmask.long.byte 0x0 8.--11. 1. "SCD_CH,Channel selection for scheduling algorithm." newline bitfld.long 0x0 0.--1. "SCD_MODE,Select MCS scheduling mode" "0,1,2,3" line.long 0x4 "MCS9_RESET," bitfld.long 0x4 7. "RST7,Software reset of channel [k]" "0,1" bitfld.long 0x4 6. "RST6,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 5. "RST5,Software reset of channel [k]" "0,1" bitfld.long 0x4 4. "RST4,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 3. "RST3,Software reset of channel [k]" "0,1" bitfld.long 0x4 2. "RST2,Software reset of channel [k]" "0,1" newline bitfld.long 0x4 1. "RST1,Software reset of channel [k]" "0,1" bitfld.long 0x4 0. "RST0,Software reset of channel [k]" "0,1" line.long 0x8 "MCS9_CAT," bitfld.long 0x8 7. "CAT7,Cancel ARU transfer of channel [k]." "0,1" bitfld.long 0x8 6. "CAT6,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 5. "CAT5,Cancel ARU transfer of channel [k]." "0,1" bitfld.long 0x8 4. "CAT4,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 3. "CAT3,Cancel ARU transfer of channel [k]." "0,1" bitfld.long 0x8 2. "CAT2,Cancel ARU transfer of channel [k]." "0,1" newline bitfld.long 0x8 1. "CAT1,Cancel ARU transfer of channel [k]." "0,1" bitfld.long 0x8 0. "CAT0,Cancel ARU transfer of channel [k]." "0,1" line.long 0xC "MCS9_CWT," bitfld.long 0xC 7. "CWT7,Cancel waiting instruction for channel [k]." "0,1" bitfld.long 0xC 6. "CWT6,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 5. "CWT5,Cancel waiting instruction for channel [k]." "0,1" bitfld.long 0xC 4. "CWT4,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 3. "CWT3,Cancel waiting instruction for channel [k]." "0,1" bitfld.long 0xC 2. "CWT2,Cancel waiting instruction for channel [k]." "0,1" newline bitfld.long 0xC 1. "CWT1,Cancel waiting instruction for channel [k]." "0,1" bitfld.long 0xC 0. "CWT0,Cancel waiting instruction for channel [k]." "0,1" line.long 0x10 "MCS9_ERR," bitfld.long 0x10 7. "ERR7,Error State of MCS-channel [k]." "0,1" bitfld.long 0x10 6. "ERR6,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 5. "ERR5,Error State of MCS-channel [k]." "0,1" bitfld.long 0x10 4. "ERR4,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 3. "ERR3,Error State of MCS-channel [k]." "0,1" bitfld.long 0x10 2. "ERR2,Error State of MCS-channel [k]." "0,1" newline bitfld.long 0x10 1. "ERR1,Error State of MCS-channel [k]." "0,1" bitfld.long 0x10 0. "ERR0,Error State of MCS-channel [k]." "0,1" group.long 0x2F1C++0x13 line.long 0x0 "MCS9_REG_PROT," bitfld.long 0x0 14.--15. "WPROT7,Register Write Protection of MCS-channel k." "0,1,2,3" bitfld.long 0x0 12.--13. "WPROT6,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 10.--11. "WPROT5,Register Write Protection of MCS-channel k." "0,1,2,3" bitfld.long 0x0 8.--9. "WPROT4,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 6.--7. "WPROT3,Register Write Protection of MCS-channel k." "0,1,2,3" bitfld.long 0x0 4.--5. "WPROT2,Register Write Protection of MCS-channel k." "0,1,2,3" newline bitfld.long 0x0 2.--3. "WPROT1,Register Write Protection of MCS-channel k." "0,1,2,3" bitfld.long 0x0 0.--1. "WPROT0,Register Write Protection of MCS-channel k." "0,1,2,3" line.long 0x4 "MCS9_SINT_IRQ_NOTIFY," bitfld.long 0x4 7. "S_IRQ7,Shared interrupt [k] notify flag." "0,1" bitfld.long 0x4 6. "S_IRQ6,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 5. "S_IRQ5,Shared interrupt [k] notify flag." "0,1" bitfld.long 0x4 4. "S_IRQ4,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 3. "S_IRQ3,Shared interrupt [k] notify flag." "0,1" bitfld.long 0x4 2. "S_IRQ2,Shared interrupt [k] notify flag." "0,1" newline bitfld.long 0x4 1. "S_IRQ1,Shared interrupt [k] notify flag." "0,1" bitfld.long 0x4 0. "S_IRQ0,Shared interrupt [k] notify flag." "0,1" line.long 0x8 "MCS9_SINT_IRQ_EN," bitfld.long 0x8 7. "S_IRQ7_EN,Shared interrupt [k]" "0,1" bitfld.long 0x8 6. "S_IRQ6_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 5. "S_IRQ5_EN,Shared interrupt [k]" "0,1" bitfld.long 0x8 4. "S_IRQ4_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 3. "S_IRQ3_EN,Shared interrupt [k]" "0,1" bitfld.long 0x8 2. "S_IRQ2_EN,Shared interrupt [k]" "0,1" newline bitfld.long 0x8 1. "S_IRQ1_EN,Shared interrupt [k]" "0,1" bitfld.long 0x8 0. "S_IRQ0_EN,Shared interrupt [k]" "0,1" line.long 0xC "MCS9_SINT_IRQ_FORCINT," bitfld.long 0xC 7. "TRG_S_IRQ7,Trigger IRQ [k] in shared interrupt register" "0,1" bitfld.long 0xC 6. "TRG_S_IRQ6,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 5. "TRG_S_IRQ5,Trigger IRQ [k] in shared interrupt register" "0,1" bitfld.long 0xC 4. "TRG_S_IRQ4,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 3. "TRG_S_IRQ3,Trigger IRQ [k] in shared interrupt register" "0,1" bitfld.long 0xC 2. "TRG_S_IRQ2,Trigger IRQ [k] in shared interrupt register" "0,1" newline bitfld.long 0xC 1. "TRG_S_IRQ1,Trigger IRQ [k] in shared interrupt register" "0,1" bitfld.long 0xC 0. "TRG_S_IRQ0,Trigger IRQ [k] in shared interrupt register" "0,1" line.long 0x10 "MCS9_SINT_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x2F40++0x1B line.long 0x0 "MCS9_HBP0_CTRL," bitfld.long 0x0 17. "NOT,Logical negation of h-th hardware break point." "0,1" bitfld.long 0x0 16. "AND,Logical AND conjunction of h-th hardware break point." "0,1" newline bitfld.long 0x0 12.--14. "TYPE,Define type of h-th hardware break point." "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. "SCOPE,Define scope of h-th hardware break point." "0,1,2,3" newline bitfld.long 0x0 7. "EN_CH7,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 6. "EN_CH6,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 5. "EN_CH5,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 4. "EN_CH4,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 3. "EN_CH3,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 2. "EN_CH2,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 1. "EN_CH1,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 0. "EN_CH0,Enable h-th hardware break point for channel x." "0,1" line.long 0x4 "MCS9_HBP0_PATTERN," hexmask.long 0x4 0.--31. 1. "DATA,Define pattern or address of h-th hardware break point." line.long 0x8 "MCS9_HBP0_STATUS," bitfld.long 0x8 7. "HALT_CH7,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 6. "HALT_CH6,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 5. "HALT_CH5,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 4. "HALT_CH4,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 3. "HALT_CH3,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 2. "HALT_CH2,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 1. "HALT_CH1,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 0. "HALT_CH0,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" line.long 0xC "MCS9_HBP0_IRQ_NOTIFY," bitfld.long 0xC 0. "HBP_IRQ,Interrupt notify flag of the h-th hardware break point." "0,1" line.long 0x10 "MCS9_HBP0_IRQ_EN," bitfld.long 0x10 0. "HBP_IRQ_EN,Interrupt Enable bit of the h-th hardware break point." "0,1" line.long 0x14 "MCS9_HBP0_IRQ_FORCINT," bitfld.long 0x14 0. "TRG_HBP_IRQ,Trigger IRQ of the h-th hardware break point." "0,1" line.long 0x18 "MCS9_HBP0_IRQ_MODE," bitfld.long 0x18 0.--1. "IRQ_MODE,IRQ mode selection for all break point interrupts." "0,1,2,3" group.long 0x2F60++0x1B line.long 0x0 "MCS9_HBP1_CTRL," bitfld.long 0x0 17. "NOT,Logical negation of h-th hardware break point." "0,1" bitfld.long 0x0 16. "AND,Logical AND conjunction of h-th hardware break point." "0,1" newline bitfld.long 0x0 12.--14. "TYPE,Define type of h-th hardware break point." "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. "SCOPE,Define scope of h-th hardware break point." "0,1,2,3" newline bitfld.long 0x0 7. "EN_CH7,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 6. "EN_CH6,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 5. "EN_CH5,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 4. "EN_CH4,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 3. "EN_CH3,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 2. "EN_CH2,Enable h-th hardware break point for channel x." "0,1" newline bitfld.long 0x0 1. "EN_CH1,Enable h-th hardware break point for channel x." "0,1" bitfld.long 0x0 0. "EN_CH0,Enable h-th hardware break point for channel x." "0,1" line.long 0x4 "MCS9_HBP1_PATTERN," hexmask.long 0x4 0.--31. 1. "DATA,Define pattern or address of h-th hardware break point." line.long 0x8 "MCS9_HBP1_STATUS," bitfld.long 0x8 7. "HALT_CH7,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 6. "HALT_CH6,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 5. "HALT_CH5,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 4. "HALT_CH4,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 3. "HALT_CH3,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 2. "HALT_CH2,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" newline bitfld.long 0x8 1. "HALT_CH1,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" bitfld.long 0x8 0. "HALT_CH0,Indicate that MCS channel x has fired the h-th hardware break point and either MCS channel x or the entire GTM was halted due to that break point depending on the state of bit field MCS[i]_HBP[h]_CTRL.SCOPE." "0,1" line.long 0xC "MCS9_HBP1_IRQ_NOTIFY," bitfld.long 0xC 0. "HBP_IRQ,Interrupt notify flag of the h-th hardware break point." "0,1" line.long 0x10 "MCS9_HBP1_IRQ_EN," bitfld.long 0x10 0. "HBP_IRQ_EN,Interrupt Enable bit of the h-th hardware break point." "0,1" line.long 0x14 "MCS9_HBP1_IRQ_FORCINT," bitfld.long 0x14 0. "TRG_HBP_IRQ,Trigger IRQ of the h-th hardware break point." "0,1" line.long 0x18 "MCS9_HBP1_IRQ_MODE," bitfld.long 0x18 0.--1. "IRQ_MODE,IRQ mode selection for all break point interrupts." "0,1,2,3" group.long 0x3000++0x13 line.long 0x0 "TIO9_G0_CH0_CTRL," bitfld.long 0x0 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x0 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x0 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x0 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x0 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x0 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x0 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x0 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x0 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x0 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x0 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x0 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x0 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x0 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x0 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x0 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x0 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x0 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x0 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x0 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x0 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x4 "TIO9_G0_CH0_IRQ_NOTIFY," bitfld.long 0x4 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x4 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x4 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x4 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x4 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x4 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x8 "TIO9_G0_CH0_IRQ_EN," bitfld.long 0x8 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x8 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x8 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x8 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x8 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x8 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0xC "TIO9_G0_CH0_IRQ_FORCINT," bitfld.long 0xC 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0xC 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0xC 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0xC 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0xC 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0xC 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x10 "TIO9_G0_CH0_IRQ_MODE," bitfld.long 0x10 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3020++0xB line.long 0x0 "TIO9_G0_CH0_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO9_G0_CH0_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO9_G0_CH0_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3030++0x23 line.long 0x0 "TIO9_G0_CH0_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO9_G0_CH0_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO9_G0_CH0_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO9_G0_CH0_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO9_G0_CH1_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO9_G0_CH1_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO9_G0_CH1_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO9_G0_CH1_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO9_G0_CH1_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3060++0xB line.long 0x0 "TIO9_G0_CH1_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO9_G0_CH1_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO9_G0_CH1_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3070++0x23 line.long 0x0 "TIO9_G0_CH1_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO9_G0_CH1_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO9_G0_CH1_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO9_G0_CH1_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO9_G0_CH2_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO9_G0_CH2_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO9_G0_CH2_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO9_G0_CH2_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO9_G0_CH2_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x30A0++0xB line.long 0x0 "TIO9_G0_CH2_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO9_G0_CH2_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO9_G0_CH2_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x30B0++0x23 line.long 0x0 "TIO9_G0_CH2_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO9_G0_CH2_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO9_G0_CH2_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO9_G0_CH2_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO9_G0_CH3_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO9_G0_CH3_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO9_G0_CH3_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO9_G0_CH3_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO9_G0_CH3_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x30E0++0xB line.long 0x0 "TIO9_G0_CH3_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO9_G0_CH3_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO9_G0_CH3_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x30F0++0x23 line.long 0x0 "TIO9_G0_CH3_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO9_G0_CH3_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO9_G0_CH3_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO9_G0_CH3_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO9_G0_CH4_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO9_G0_CH4_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO9_G0_CH4_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO9_G0_CH4_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO9_G0_CH4_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3120++0xB line.long 0x0 "TIO9_G0_CH4_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO9_G0_CH4_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO9_G0_CH4_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3130++0x23 line.long 0x0 "TIO9_G0_CH4_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO9_G0_CH4_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO9_G0_CH4_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO9_G0_CH4_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO9_G0_CH5_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO9_G0_CH5_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO9_G0_CH5_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO9_G0_CH5_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO9_G0_CH5_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x3160++0xB line.long 0x0 "TIO9_G0_CH5_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO9_G0_CH5_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO9_G0_CH5_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x3170++0x23 line.long 0x0 "TIO9_G0_CH5_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO9_G0_CH5_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO9_G0_CH5_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO9_G0_CH5_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO9_G0_CH6_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO9_G0_CH6_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO9_G0_CH6_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO9_G0_CH6_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO9_G0_CH6_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x31A0++0xB line.long 0x0 "TIO9_G0_CH6_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO9_G0_CH6_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO9_G0_CH6_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x31B0++0x23 line.long 0x0 "TIO9_G0_CH6_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO9_G0_CH6_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO9_G0_CH6_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO9_G0_CH6_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO9_G0_CH7_CTRL," bitfld.long 0x10 31. "PL_TRIG_OUT_UPD_EN,Select TIO basic update source of channel c." "0,1" bitfld.long 0x10 30. "PL_TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c PL_TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 29. "PL_TRIG_OUT_EN_PL_EVT,TIO channel c PL_TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 28. "PL_TRIG_OUT_EN_PREV_TRIG,TIO channel c PL_TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 27. "PL_TRIG_OUT_EN_O_FE,TIO channel c PL_TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 26. "PL_TRIG_OUT_EN_O_RE,TIO channel c PL_TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 25. "PL_TRIG_OUT_EN_S_FE,TIO channel c PL_TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 24. "PL_TRIG_OUT_EN_S_RE,TIO channel c PL_TRIG_OUT source: Rising edge S(c) enable" "0,1" newline bitfld.long 0x10 23. "PL_S_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of S resource channel c." "0,1" bitfld.long 0x10 22. "PL_O_TRIG_OUT_EN,Enable usage of TRIG_OUT[c] in instruction of O resource channel c." "0,1" newline bitfld.long 0x10 21. "PL_SEL_IN,Select input source for O resource channel c." "0,1" bitfld.long 0x10 20. "PL_ODIS,Disable change of TIO[i]_O[g*8+c] register" "0,1" newline bitfld.long 0x10 19. "PL_FREEZE_O_EN,Enable O buffer freeze in channel c." "0,1" bitfld.long 0x10 16.--18. "PL_O_MODE,Select mode of operation for O resource channel c." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "PL_CYCLIC_BUFF,Enable circular buffer functionality in channel c." "0,1" bitfld.long 0x10 14. "PL_FREEZE_S_EN,Enable S buffer freeze in channel c." "0,1" newline bitfld.long 0x10 12.--13. "PL_S_MODE,Select mode of operation for S resource channel c." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "UPDATE_SRC,Select update source of channel c." newline bitfld.long 0x10 7. "PL_CYCLIC_INIT_TRIG_EN,Enable usage of TRIG_OUT[c] as init trigger of cyclic buffer functionality in channel c." "0,1" bitfld.long 0x10 6. "TRIG_OUT_EN_PREV_PL_TRIG,TIO channel c TRIG_OUT source: PL_TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 5. "TRIG_OUT_EN_PL_EVT,TIO channel c TRIG_OUT source: PL_EVT(c)enable" "0,1" bitfld.long 0x10 4. "TRIG_OUT_EN_PREV_TRIG,TIO channel c TRIG_OUT source: TRIG_OUT(c-1)enable" "0,1" newline bitfld.long 0x10 3. "TRIG_OUT_EN_O_FE,TIO channel c TRIG_OUT source: Falling edge O(c) enable" "0,1" bitfld.long 0x10 2. "TRIG_OUT_EN_O_RE,TIO channel c TRIG_OUT source: Rising edge O(c) enable" "0,1" newline bitfld.long 0x10 1. "TRIG_OUT_EN_S_FE,TIO channel c TRIG_OUT source: Falling edge S(c) enable" "0,1" bitfld.long 0x10 0. "TRIG_OUT_EN_S_RE,TIO channel c TRIG_OUT source: Rising edge S(c) enable" "0,1" line.long 0x14 "TIO9_G0_CH7_IRQ_NOTIFY," bitfld.long 0x14 5. "PL_EVT_IRQ,Interrupt request PL_EVT of channel c" "0,1" bitfld.long 0x14 4. "UPDATE_IRQ,Interrupt request for update of channel c" "0,1" newline bitfld.long 0x14 3. "O_FE_IRQ,Interrupt request Falling edge O(c)" "0,1" bitfld.long 0x14 2. "O_RE_IRQ,Interrupt request Rising edge O(c)" "0,1" newline bitfld.long 0x14 1. "S_FE_IRQ,Interrupt request Falling edge S(c)" "0,1" bitfld.long 0x14 0. "S_RE_IRQ,Interrupt request Rising edge S(c)" "0,1" line.long 0x18 "TIO9_G0_CH7_IRQ_EN," bitfld.long 0x18 5. "PL_EVT_IRQ_EN,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x18 4. "UPDATE_IRQ_EN,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x18 3. "O_FE_IRQ_EN,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x18 2. "O_RE_IRQ_EN,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x18 1. "S_FE_IRQ_EN,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x18 0. "S_RE_IRQ_EN,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x1C "TIO9_G0_CH7_IRQ_FORCINT," bitfld.long 0x1C 5. "TRG_PL_EVT_IRQ,Interrupt enable request PL_EVT of channel c" "0,1" bitfld.long 0x1C 4. "TRG_UPDATE_IRQ,Interrupt enable request for update of channel c" "0,1" newline bitfld.long 0x1C 3. "TRG_O_FE_IRQ,Interrupt enable request Falling edge O(c)" "0,1" bitfld.long 0x1C 2. "TRG_O_RE_IRQ,Interrupt enable request Rising edge O(c)" "0,1" newline bitfld.long 0x1C 1. "TRG_S_FE_IRQ,Interrupt enable request Falling edge S(c)" "0,1" bitfld.long 0x1C 0. "TRG_S_RE_IRQ,Interrupt enable request Rising edge S(c)" "0,1" line.long 0x20 "TIO9_G0_CH7_IRQ_MODE," bitfld.long 0x20 0.--1. "IRQ_MODE,IRQ mode selection" "0,1,2,3" group.long 0x31E0++0xB line.long 0x0 "TIO9_G0_CH7_SINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO9_G0_CH7_SCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO9_G0_CH7_SOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" group.long 0x31F0++0x17 line.long 0x0 "TIO9_G0_CH7_OINST," bitfld.long 0x0 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x0 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "CMD,Command" hexmask.long.tbyte 0x0 0.--23. 1. "OP,Operand" line.long 0x4 "TIO9_G0_CH7_OCMD," bitfld.long 0x4 31. "INSTR_PULL_EN,Enable instruction fetch" "0,1" bitfld.long 0x4 30. "DATA_PUSH_EN,Enable data capture" "0,1" newline hexmask.long.byte 0x4 24.--29. 1. "CMD,Command" line.long 0x8 "TIO9_G0_CH7_OOP," hexmask.long.tbyte 0x8 0.--23. 1. "OP,Operand" line.long 0xC "TIO9_G0_CH7_SHIFTCNT," hexmask.long.byte 0xC 0.--4. 1. "CNT,Shift counter value" line.long 0x10 "TIO9_G0_ISEL0_CTRL1," bitfld.long 0x10 27. "WRITE_EN3,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" bitfld.long 0x10 26. "WRITE_EN2,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 25. "WRITE_EN1,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" bitfld.long 0x10 24. "WRITE_EN0,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x10 19. "OUT_SEL3,select signal for ISEL_OUT[k]" "0,1" bitfld.long 0x10 18. "OUT_SEL2,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x10 17. "OUT_SEL1,select signal for ISEL_OUT[k]" "0,1" bitfld.long 0x10 16. "OUT_SEL0,select signal for ISEL_OUT[k]" "0,1" newline hexmask.long.byte 0x10 12.--15. 1. "LUT2_3,2 bit Lookup table function for channel c=q*4+k" hexmask.long.byte 0x10 8.--11. 1. "LUT2_2,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x10 4.--7. 1. "LUT2_1,2 bit Lookup table function for channel c=q*4+k" hexmask.long.byte 0x10 0.--3. 1. "LUT2_0,2 bit Lookup table function for channel c=q*4+k" line.long 0x14 "TIO9_G0_ISEL0_CTRL2," bitfld.long 0x14 22. "LUT3IN_SEL2,select source for LUT3_IN[k] signal in quad = q" "0,1" bitfld.long 0x14 21. "LUT3IN_SEL1,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x14 20. "LUT3IN_SEL0,select source for LUT3_IN[k] signal in quad = q" "0,1" bitfld.long 0x14 16.--17. "QOUT_SEL,select source for ISEL_QOUT signal in quad = q" "0,1,2,3" newline hexmask.long.byte 0x14 0.--7. 1. "LUT3,3 bit Lookup table function for quad=q; channels q*4+2 .. q*4" group.long 0x3220++0x7 line.long 0x0 "TIO9_G0_ISEL1_CTRL1," bitfld.long 0x0 27. "WRITE_EN3,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" bitfld.long 0x0 26. "WRITE_EN2,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 25. "WRITE_EN1,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" bitfld.long 0x0 24. "WRITE_EN0,enable writing of configuration bit fields LUT2_[k] OUT_SEL[k]" "0,1" newline bitfld.long 0x0 19. "OUT_SEL3,select signal for ISEL_OUT[k]" "0,1" bitfld.long 0x0 18. "OUT_SEL2,select signal for ISEL_OUT[k]" "0,1" newline bitfld.long 0x0 17. "OUT_SEL1,select signal for ISEL_OUT[k]" "0,1" bitfld.long 0x0 16. "OUT_SEL0,select signal for ISEL_OUT[k]" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "LUT2_3,2 bit Lookup table function for channel c=q*4+k" hexmask.long.byte 0x0 8.--11. 1. "LUT2_2,2 bit Lookup table function for channel c=q*4+k" newline hexmask.long.byte 0x0 4.--7. 1. "LUT2_1,2 bit Lookup table function for channel c=q*4+k" hexmask.long.byte 0x0 0.--3. 1. "LUT2_0,2 bit Lookup table function for channel c=q*4+k" line.long 0x4 "TIO9_G0_ISEL1_CTRL2," bitfld.long 0x4 22. "LUT3IN_SEL2,select source for LUT3_IN[k] signal in quad = q" "0,1" bitfld.long 0x4 21. "LUT3IN_SEL1,select source for LUT3_IN[k] signal in quad = q" "0,1" newline bitfld.long 0x4 20. "LUT3IN_SEL0,select source for LUT3_IN[k] signal in quad = q" "0,1" bitfld.long 0x4 16.--17. "QOUT_SEL,select source for ISEL_QOUT signal in quad = q" "0,1,2,3" newline hexmask.long.byte 0x4 0.--7. 1. "LUT3,3 bit Lookup table function for quad=q; channels q*4+2 .. q*4" group.long 0x3240++0x3 line.long 0x0 "TIO9_G0_OP_USAGE," bitfld.long 0x0 31. "WRITE_EN7,enable writing of configuration bit fields MODE[c]" "0,1" bitfld.long 0x0 30. "WRITE_EN6,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 29. "WRITE_EN5,enable writing of configuration bit fields MODE[c]" "0,1" bitfld.long 0x0 28. "WRITE_EN4,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 27. "WRITE_EN3,enable writing of configuration bit fields MODE[c]" "0,1" bitfld.long 0x0 26. "WRITE_EN2,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 25. "WRITE_EN1,enable writing of configuration bit fields MODE[c]" "0,1" bitfld.long 0x0 24. "WRITE_EN0,enable writing of configuration bit fields MODE[c]" "0,1" newline bitfld.long 0x0 21.--23. "MODE7,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18.--20. "MODE6,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15.--17. "MODE5,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "MODE4,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9.--11. "MODE3,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--8. "MODE2,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "MODE1,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "MODE0,operand usage of S/ O resource" "0,1,2,3,4,5,6,7" group.long 0x3C00++0x1F line.long 0x0 "TIO9_S," bitfld.long 0x0 7. "CH7,Value of channel x." "0,1" bitfld.long 0x0 6. "CH6,Value of channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Value of channel x." "0,1" bitfld.long 0x0 4. "CH4,Value of channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Value of channel x." "0,1" bitfld.long 0x0 2. "CH2,Value of channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Value of channel x." "0,1" bitfld.long 0x0 0. "CH0,Value of channel x." "0,1" line.long 0x4 "TIO9_O," bitfld.long 0x4 7. "CH7,Value driven on output of channel x." "0,1" bitfld.long 0x4 6. "CH6,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Value driven on output of channel x." "0,1" bitfld.long 0x4 4. "CH4,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Value driven on output of channel x." "0,1" bitfld.long 0x4 2. "CH2,Value driven on output of channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Value driven on output of channel x." "0,1" bitfld.long 0x4 0. "CH0,Value driven on output of channel x." "0,1" line.long 0x8 "TIO9_ENDIS," bitfld.long 0x8 7. "CH7,Enable/Disable request of channel x." "0,1" bitfld.long 0x8 6. "CH6,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Enable/Disable request of channel x." "0,1" bitfld.long 0x8 4. "CH4,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Enable/Disable request of channel x." "0,1" bitfld.long 0x8 2. "CH2,Enable/Disable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Enable/Disable request of channel x." "0,1" bitfld.long 0x8 0. "CH0,Enable/Disable request of channel x." "0,1" line.long 0xC "TIO9_INVERT," bitfld.long 0xC 7. "CH7,Enable/Disable signal inversion of channel x." "0,1" bitfld.long 0xC 6. "CH6,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Enable/Disable signal inversion of channel x." "0,1" bitfld.long 0xC 4. "CH4,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Enable/Disable signal inversion of channel x." "0,1" bitfld.long 0xC 2. "CH2,Enable/Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Enable/Disable signal inversion of channel x." "0,1" bitfld.long 0xC 0. "CH0,Enable/Disable signal inversion of channel x." "0,1" line.long 0x10 "TIO9_INPUT_MODE," bitfld.long 0x10 7. "CH7,Enable/Disable input mode of channel x." "0,1" bitfld.long 0x10 6. "CH6,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Enable/Disable input mode of channel x." "0,1" bitfld.long 0x10 4. "CH4,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Enable/Disable input mode of channel x." "0,1" bitfld.long 0x10 2. "CH2,Enable/Disable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Enable/Disable input mode of channel x." "0,1" bitfld.long 0x10 0. "CH0,Enable/Disable input mode of channel x." "0,1" line.long 0x14 "TIO9_CYCLIC_MODE," bitfld.long 0x14 7. "CH7,Enable/Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 6. "CH6,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Enable/Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 4. "CH4,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Enable/Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 2. "CH2,Enable/Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Enable/Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 0. "CH0,Enable/Disable cyclic mode of channel x." "0,1" line.long 0x18 "TIO9_TRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 6. "CH6,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 4. "CH4,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 2. "CH2,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 0. "CH0,enable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO9_PLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 6. "CH6,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 4. "CH4,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 2. "CH2,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 0. "CH0,enable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3C40++0x1F line.long 0x0 "TIO9_CS," bitfld.long 0x0 7. "CH7,Clear channel x." "0,1" bitfld.long 0x0 6. "CH6,Clear channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Clear channel x." "0,1" bitfld.long 0x0 4. "CH4,Clear channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Clear channel x." "0,1" bitfld.long 0x0 2. "CH2,Clear channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Clear channel x." "0,1" bitfld.long 0x0 0. "CH0,Clear channel x." "0,1" line.long 0x4 "TIO9_CO," bitfld.long 0x4 7. "CH7,Clear channel x." "0,1" bitfld.long 0x4 6. "CH6,Clear channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Clear channel x." "0,1" bitfld.long 0x4 4. "CH4,Clear channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Clear channel x." "0,1" bitfld.long 0x4 2. "CH2,Clear channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Clear channel x." "0,1" bitfld.long 0x4 0. "CH0,Clear channel x." "0,1" line.long 0x8 "TIO9_CENDIS," bitfld.long 0x8 7. "CH7,Disable request of channel x." "0,1" bitfld.long 0x8 6. "CH6,Disable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Disable request of channel x." "0,1" bitfld.long 0x8 4. "CH4,Disable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Disable request of channel x." "0,1" bitfld.long 0x8 2. "CH2,Disable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Disable request of channel x." "0,1" bitfld.long 0x8 0. "CH0,Disable request of channel x." "0,1" line.long 0xC "TIO9_CINVERT," bitfld.long 0xC 7. "CH7,Disable signal inversion of channel x." "0,1" bitfld.long 0xC 6. "CH6,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Disable signal inversion of channel x." "0,1" bitfld.long 0xC 4. "CH4,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Disable signal inversion of channel x." "0,1" bitfld.long 0xC 2. "CH2,Disable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Disable signal inversion of channel x." "0,1" bitfld.long 0xC 0. "CH0,Disable signal inversion of channel x." "0,1" line.long 0x10 "TIO9_CINPUT_MODE," bitfld.long 0x10 7. "CH7,Disable input mode of channel x." "0,1" bitfld.long 0x10 6. "CH6,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Disable input mode of channel x." "0,1" bitfld.long 0x10 4. "CH4,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Disable input mode of channel x." "0,1" bitfld.long 0x10 2. "CH2,Disable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Disable input mode of channel x." "0,1" bitfld.long 0x10 0. "CH0,Disable input mode of channel x." "0,1" line.long 0x14 "TIO9_CCYCLIC_MODE," bitfld.long 0x14 7. "CH7,Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 6. "CH6,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 4. "CH4,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 2. "CH2,Disable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Disable cyclic mode of channel x." "0,1" bitfld.long 0x14 0. "CH0,Disable cyclic mode of channel x." "0,1" line.long 0x18 "TIO9_CTRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,disable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 6. "CH6,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,disable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 4. "CH4,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,disable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 2. "CH2,disable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,disable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 0. "CH0,disable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO9_CPLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,disable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 6. "CH6,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,disable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 4. "CH4,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,disable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 2. "CH2,disable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,disable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 0. "CH0,disable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3C80++0x1F line.long 0x0 "TIO9_SS," bitfld.long 0x0 7. "CH7,Set channel x." "0,1" bitfld.long 0x0 6. "CH6,Set channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Set channel x." "0,1" bitfld.long 0x0 4. "CH4,Set channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Set channel x." "0,1" bitfld.long 0x0 2. "CH2,Set channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Set channel x." "0,1" bitfld.long 0x0 0. "CH0,Set channel x." "0,1" line.long 0x4 "TIO9_SO," bitfld.long 0x4 7. "CH7,Set channel x." "0,1" bitfld.long 0x4 6. "CH6,Set channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Set channel x." "0,1" bitfld.long 0x4 4. "CH4,Set channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Set channel x." "0,1" bitfld.long 0x4 2. "CH2,Set channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Set channel x." "0,1" bitfld.long 0x4 0. "CH0,Set channel x." "0,1" line.long 0x8 "TIO9_SENDIS," bitfld.long 0x8 7. "CH7,Enable request of channel x." "0,1" bitfld.long 0x8 6. "CH6,Enable request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Enable request of channel x." "0,1" bitfld.long 0x8 4. "CH4,Enable request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Enable request of channel x." "0,1" bitfld.long 0x8 2. "CH2,Enable request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Enable request of channel x." "0,1" bitfld.long 0x8 0. "CH0,Enable request of channel x." "0,1" line.long 0xC "TIO9_SINVERT," bitfld.long 0xC 7. "CH7,Enable signal inversion of channel x." "0,1" bitfld.long 0xC 6. "CH6,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Enable signal inversion of channel x." "0,1" bitfld.long 0xC 4. "CH4,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Enable signal inversion of channel x." "0,1" bitfld.long 0xC 2. "CH2,Enable signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Enable signal inversion of channel x." "0,1" bitfld.long 0xC 0. "CH0,Enable signal inversion of channel x." "0,1" line.long 0x10 "TIO9_SINPUT_MODE," bitfld.long 0x10 7. "CH7,Enable input mode of channel x." "0,1" bitfld.long 0x10 6. "CH6,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Enable input mode of channel x." "0,1" bitfld.long 0x10 4. "CH4,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Enable input mode of channel x." "0,1" bitfld.long 0x10 2. "CH2,Enable input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Enable input mode of channel x." "0,1" bitfld.long 0x10 0. "CH0,Enable input mode of channel x." "0,1" line.long 0x14 "TIO9_SCYCLIC_MODE," bitfld.long 0x14 7. "CH7,Enable cyclic mode of channel x." "0,1" bitfld.long 0x14 6. "CH6,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Enable cyclic mode of channel x." "0,1" bitfld.long 0x14 4. "CH4,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Enable cyclic mode of channel x." "0,1" bitfld.long 0x14 2. "CH2,Enable cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Enable cyclic mode of channel x." "0,1" bitfld.long 0x14 0. "CH0,Enable cyclic mode of channel x." "0,1" line.long 0x18 "TIO9_STRIG_OUT_GATE_EN," bitfld.long 0x18 7. "CH7,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 6. "CH6,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 5. "CH5,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 4. "CH4,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 3. "CH3,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 2. "CH2,enable gating of TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x18 1. "CH1,enable gating of TRIG_OUT events of channel x" "0,1" bitfld.long 0x18 0. "CH0,enable gating of TRIG_OUT events of channel x" "0,1" line.long 0x1C "TIO9_SPLTRIG_OUT_GATE_EN," bitfld.long 0x1C 7. "CH7,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 6. "CH6,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 5. "CH5,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 4. "CH4,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 3. "CH3,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 2. "CH2,enable gating of PL_TRIG_OUT events of channel x" "0,1" newline bitfld.long 0x1C 1. "CH1,enable gating of PL_TRIG_OUT events of channel x" "0,1" bitfld.long 0x1C 0. "CH0,enable gating of PL_TRIG_OUT events of channel x" "0,1" group.long 0x3CC0++0x17 line.long 0x0 "TIO9_IS," bitfld.long 0x0 7. "CH7,Invert channel x." "0,1" bitfld.long 0x0 6. "CH6,Invert channel x." "0,1" newline bitfld.long 0x0 5. "CH5,Invert channel x." "0,1" bitfld.long 0x0 4. "CH4,Invert channel x." "0,1" newline bitfld.long 0x0 3. "CH3,Invert channel x." "0,1" bitfld.long 0x0 2. "CH2,Invert channel x." "0,1" newline bitfld.long 0x0 1. "CH1,Invert channel x." "0,1" bitfld.long 0x0 0. "CH0,Invert channel x." "0,1" line.long 0x4 "TIO9_IO," bitfld.long 0x4 7. "CH7,Invert channel x." "0,1" bitfld.long 0x4 6. "CH6,Invert channel x." "0,1" newline bitfld.long 0x4 5. "CH5,Invert channel x." "0,1" bitfld.long 0x4 4. "CH4,Invert channel x." "0,1" newline bitfld.long 0x4 3. "CH3,Invert channel x." "0,1" bitfld.long 0x4 2. "CH2,Invert channel x." "0,1" newline bitfld.long 0x4 1. "CH1,Invert channel x." "0,1" bitfld.long 0x4 0. "CH0,Invert channel x." "0,1" line.long 0x8 "TIO9_IENDIS," bitfld.long 0x8 7. "CH7,Toggle state request of channel x." "0,1" bitfld.long 0x8 6. "CH6,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 5. "CH5,Toggle state request of channel x." "0,1" bitfld.long 0x8 4. "CH4,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 3. "CH3,Toggle state request of channel x." "0,1" bitfld.long 0x8 2. "CH2,Toggle state request of channel x." "0,1" newline bitfld.long 0x8 1. "CH1,Toggle state request of channel x." "0,1" bitfld.long 0x8 0. "CH0,Toggle state request of channel x." "0,1" line.long 0xC "TIO9_IINVERT," bitfld.long 0xC 7. "CH7,Invert signal inversion of channel x." "0,1" bitfld.long 0xC 6. "CH6,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 5. "CH5,Invert signal inversion of channel x." "0,1" bitfld.long 0xC 4. "CH4,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 3. "CH3,Invert signal inversion of channel x." "0,1" bitfld.long 0xC 2. "CH2,Invert signal inversion of channel x." "0,1" newline bitfld.long 0xC 1. "CH1,Invert signal inversion of channel x." "0,1" bitfld.long 0xC 0. "CH0,Invert signal inversion of channel x." "0,1" line.long 0x10 "TIO9_IINPUT_MODE," bitfld.long 0x10 7. "CH7,Toggle input mode of channel x." "0,1" bitfld.long 0x10 6. "CH6,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 5. "CH5,Toggle input mode of channel x." "0,1" bitfld.long 0x10 4. "CH4,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 3. "CH3,Toggle input mode of channel x." "0,1" bitfld.long 0x10 2. "CH2,Toggle input mode of channel x." "0,1" newline bitfld.long 0x10 1. "CH1,Toggle input mode of channel x." "0,1" bitfld.long 0x10 0. "CH0,Toggle input mode of channel x." "0,1" line.long 0x14 "TIO9_ICYCLIC_MODE," bitfld.long 0x14 7. "CH7,Toggle cyclic mode of channel x." "0,1" bitfld.long 0x14 6. "CH6,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 5. "CH5,Toggle cyclic mode of channel x." "0,1" bitfld.long 0x14 4. "CH4,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 3. "CH3,Toggle cyclic mode of channel x." "0,1" bitfld.long 0x14 2. "CH2,Toggle cyclic mode of channel x." "0,1" newline bitfld.long 0x14 1. "CH1,Toggle cyclic mode of channel x." "0,1" bitfld.long 0x14 0. "CH0,Toggle cyclic mode of channel x." "0,1" group.long 0x3D00++0x13 line.long 0x0 "TIO9_FUPD," bitfld.long 0x0 7. "CH7,issue immediately a signal pulse on the update signal of channel x" "0,1" bitfld.long 0x0 6. "CH6,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 5. "CH5,issue immediately a signal pulse on the update signal of channel x" "0,1" bitfld.long 0x0 4. "CH4,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 3. "CH3,issue immediately a signal pulse on the update signal of channel x" "0,1" bitfld.long 0x0 2. "CH2,issue immediately a signal pulse on the update signal of channel x" "0,1" newline bitfld.long 0x0 1. "CH1,issue immediately a signal pulse on the update signal of channel x" "0,1" bitfld.long 0x0 0. "CH0,issue immediately a signal pulse on the update signal of channel x" "0,1" line.long 0x4 "TIO9_HW_CONF," bitfld.long 0x4 4. "TIO_PLUS,signals availablity of TIOplus functionality" "0,1" bitfld.long 0x4 0.--1. "NTIO_CH8,signals availablity of amount of channels" "0,1,2,3" line.long 0x8 "TIO9_RSEL_CTRL1," bitfld.long 0x8 28. "SEL_CLKEN7_0,select source of RS_CLKEN7[g][7] for channels g*8 .. g*8+7" "0,1" bitfld.long 0x8 24. "SEL_CLKEN6_0,select source of RS_CLKEN[g][6] for channels g*8 .. g*8+7" "0,1" line.long 0xC "TIO9_RSEL_CTRL2," bitfld.long 0xC 8. "SEL_TB2_0,select source of RS_TB2[g] for channels g*8 .. g*8+7" "0,1" bitfld.long 0xC 4. "SEL_TB1_0,select source of RS_TB1[g] for channels g*8 .. g*8+7" "0,1" line.long 0x10 "TIO9_PL_SWRST," bitfld.long 0x10 7. "CH7,reset TIO_Plus resources of channel x" "0,1" bitfld.long 0x10 6. "CH6,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 5. "CH5,reset TIO_Plus resources of channel x" "0,1" bitfld.long 0x10 4. "CH4,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 3. "CH3,reset TIO_Plus resources of channel x" "0,1" bitfld.long 0x10 2. "CH2,reset TIO_Plus resources of channel x" "0,1" newline bitfld.long 0x10 1. "CH1,reset TIO_Plus resources of channel x" "0,1" bitfld.long 0x10 0. "CH0,reset TIO_Plus resources of channel x" "0,1" group.long 0x4000++0x4F line.long 0x0 "CCM9_ARP0_CTRL," bitfld.long 0x0 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x0 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x0 0.--15. 1. "ADDR,ARP base address." line.long 0x4 "CCM9_ARP0_PROT," bitfld.long 0x4 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x4 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x4 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x4 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x4 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x8 "CCM9_ARP1_CTRL," bitfld.long 0x8 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x8 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x8 0.--15. 1. "ADDR,ARP base address." line.long 0xC "CCM9_ARP1_PROT," bitfld.long 0xC 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0xC 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0xC 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0xC 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0xC 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0xC 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x10 "CCM9_ARP2_CTRL," bitfld.long 0x10 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x10 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x10 0.--15. 1. "ADDR,ARP base address." line.long 0x14 "CCM9_ARP2_PROT," bitfld.long 0x14 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x14 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x14 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x14 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x14 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x14 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x18 "CCM9_ARP3_CTRL," bitfld.long 0x18 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x18 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x18 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x18 0.--15. 1. "ADDR,ARP base address." line.long 0x1C "CCM9_ARP3_PROT," bitfld.long 0x1C 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x1C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x1C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x1C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x1C 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x1C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x20 "CCM9_ARP4_CTRL," bitfld.long 0x20 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x20 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x20 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x20 0.--15. 1. "ADDR,ARP base address." line.long 0x24 "CCM9_ARP4_PROT," bitfld.long 0x24 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x24 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x24 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x24 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x24 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x24 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x28 "CCM9_ARP5_CTRL," bitfld.long 0x28 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x28 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x28 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x28 0.--15. 1. "ADDR,ARP base address." line.long 0x2C "CCM9_ARP5_PROT," bitfld.long 0x2C 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x2C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x2C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x2C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x2C 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x2C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x30 "CCM9_ARP6_CTRL," bitfld.long 0x30 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x30 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x30 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x30 0.--15. 1. "ADDR,ARP base address." line.long 0x34 "CCM9_ARP6_PROT," bitfld.long 0x34 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x34 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x34 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x34 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x34 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x34 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x38 "CCM9_ARP7_CTRL," bitfld.long 0x38 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x38 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x38 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x38 0.--15. 1. "ADDR,ARP base address." line.long 0x3C "CCM9_ARP7_PROT," bitfld.long 0x3C 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x3C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x3C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x3C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x3C 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x3C 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x40 "CCM9_ARP8_CTRL," bitfld.long 0x40 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x40 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x40 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x40 0.--15. 1. "ADDR,ARP base address." line.long 0x44 "CCM9_ARP8_PROT," bitfld.long 0x44 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x44 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x44 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x44 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x44 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x44 0. "WPROT0,Write Protection MCS channel x." "0,1" line.long 0x48 "CCM9_ARP9_CTRL," bitfld.long 0x48 31. "WPROT_AEI,AEI slave write protection." "0,1" bitfld.long 0x48 24. "DIS_PROT,Disable ARP protection." "0,1" newline hexmask.long.byte 0x48 16.--19. 1. "SIZE,Size of ARP" hexmask.long.word 0x48 0.--15. 1. "ADDR,ARP base address." line.long 0x4C "CCM9_ARP9_PROT," bitfld.long 0x4C 7. "WPROT7,Write Protection MCS channel x." "0,1" bitfld.long 0x4C 6. "WPROT6,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 5. "WPROT5,Write Protection MCS channel x." "0,1" bitfld.long 0x4C 4. "WPROT4,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 3. "WPROT3,Write Protection MCS channel x." "0,1" bitfld.long 0x4C 2. "WPROT2,Write Protection MCS channel x." "0,1" newline bitfld.long 0x4C 1. "WPROT1,Write Protection MCS channel x." "0,1" bitfld.long 0x4C 0. "WPROT0,Write Protection MCS channel x." "0,1" group.long 0x41D4++0xB line.long 0x0 "CCM9_HW_CONF2," bitfld.long 0x0 18. "AXIM_DATA_SIZE,Defines the data bus width of the AXI master interface" "0,1" bitfld.long 0x0 16. "AXIS_DATA_SIZE,Defines the data bus width of the AXI slave interface" "0,1" newline bitfld.long 0x0 9. "TIO_OUT_RST,TIO_OUT reset level" "0,1" bitfld.long 0x0 7. "AXIM_POSTED_WRITE,Write transaction without response" "0,1" newline bitfld.long 0x0 6. "AXIM_SEC_ACC,Secure AXI master access constant" "0,1" bitfld.long 0x0 5. "AXIM_PRIV_ACC,Privileged AXI master access constant" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "AXIM_ID_WIDTH,Defines which LSB of AXIM_ID are send to the bus" line.long 0x4 "CCM9_AEIM_STA," bitfld.long 0x4 24.--25. "AEIM_XPT_STA,AEIM Exception status." "0,1,2,3" hexmask.long.word 0x4 0.--15. 1. "AEIM_XPT_ADDR,Exception Address." line.long 0x8 "CCM9_HW_CONF," bitfld.long 0x8 31. "AEI_RDATA_PIPELINE_STAGE,Read data pipeline stage implemented" "0,1" bitfld.long 0x8 30. "AEI_ADDR_PIPELINE_STAGE,Address pipeline stage implemented" "0,1" newline bitfld.long 0x8 29. "INT_CLK_EN_GEN,Internal clock enable generation" "0,1" hexmask.long.byte 0x8 24.--28. 1. "TOM_TRIG_INTCHAIN,TOM internal trigger chain length without synchronization register" newline hexmask.long.byte 0x8 20.--23. 1. "ATOM_TRIG_INTCHAIN,ATOM internal trigger chain length without synchronization register" bitfld.long 0x8 19. "IRQ_MODE_SINGLE_PULSE,Signalize availability of Single Pulse IRQ mode" "0,1" newline bitfld.long 0x8 18. "IRQ_MODE_PULSE_NOTIFY,Signalize availability of Pulse Notoify IRQ mode" "0,1" bitfld.long 0x8 17. "IRQ_MODE_PULSE,Signalize availability of Pulse IRQ mode" "0,1" newline bitfld.long 0x8 16. "IRQ_MODE_LEVEL,Signalize availability of Level IRQ mode" "0,1" bitfld.long 0x8 15. "RESET_ACTIVE,Active level of asynchronous reset" "0,1" newline bitfld.long 0x8 13. "ERM,Enable RAM1 MSB for available MCS modules" "0,1" bitfld.long 0x8 12. "RAM_INIT_RST,RAM initialization from reset" "0,1" newline bitfld.long 0x8 9.--11. "TOM_TRIG_CHAIN,TOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8. "TOM_OUT_RST,TOM_OUT reset level" "0,1" newline bitfld.long 0x8 5.--7. "ATOM_TRIG_CHAIN,ATOM trigger chain length without synchronization register" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "ATOM_OUT_RST,ATOM_OUT reset level" "0,1" newline bitfld.long 0x8 3. "CFG_CLOCK_RATE,Clocks per ARU transfer" "0,1" bitfld.long 0x8 2. "SYNC_INPUT_REG,Additional pipelined stage in synchronous bridge mode" "0,1" newline bitfld.long 0x8 1. "BRIDGE_MODE_RST,Bridge mode after reset" "0,1" bitfld.long 0x8 0. "GRSTEN,Global Reset Enable" "0,1" group.long 0x41EC++0x7 line.long 0x0 "CCM9_ATOM_OUT," bitfld.long 0x0 31. "ATOM_IP1_OUT_N7,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" bitfld.long 0x0 30. "ATOM_IP1_OUT_N6,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 29. "ATOM_IP1_OUT_N5,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" bitfld.long 0x0 28. "ATOM_IP1_OUT_N4,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 27. "ATOM_IP1_OUT_N3,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" bitfld.long 0x0 26. "ATOM_IP1_OUT_N2,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 25. "ATOM_IP1_OUT_N1,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" bitfld.long 0x0 24. "ATOM_IP1_OUT_N0,Output level snapshot of ATOM[i+1]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 23. "ATOM_IP1_OUT7,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" bitfld.long 0x0 22. "ATOM_IP1_OUT6,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 21. "ATOM_IP1_OUT5,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" bitfld.long 0x0 20. "ATOM_IP1_OUT4,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 19. "ATOM_IP1_OUT3,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" bitfld.long 0x0 18. "ATOM_IP1_OUT2,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 17. "ATOM_IP1_OUT1,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" bitfld.long 0x0 16. "ATOM_IP1_OUT0,Output level snapshot of ATOM[i+1]_OUT channel [x]" "0,1" newline bitfld.long 0x0 15. "ATOM_I_OUT_N7,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 14. "ATOM_I_OUT_N6,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 13. "ATOM_I_OUT_N5,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 12. "ATOM_I_OUT_N4,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 11. "ATOM_I_OUT_N3,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 10. "ATOM_I_OUT_N2,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 9. "ATOM_I_OUT_N1,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" bitfld.long 0x0 8. "ATOM_I_OUT_N0,Output level snapshot of ATOM[i]_OUT_N channel [x]" "0,1" newline bitfld.long 0x0 7. "ATOM_I_OUT7,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 6. "ATOM_I_OUT6,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 5. "ATOM_I_OUT5,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 4. "ATOM_I_OUT4,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 3. "ATOM_I_OUT3,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 2. "ATOM_I_OUT2,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" newline bitfld.long 0x0 1. "ATOM_I_OUT1,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" bitfld.long 0x0 0. "ATOM_I_OUT0,Output level snapshot of ATOM[i]_OUT channel [x]" "0,1" line.long 0x4 "CCM9_CMU_CLK_CFG," bitfld.long 0x4 28.--29. "CLK7_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x4 24.--25. "CLK6_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 20.--21. "CLK5_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x4 16.--17. "CLK4_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 12.--13. "CLK3_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x4 8.--9. "CLK2_SRC,Clock y source signal selector" "0,1,2,3" newline bitfld.long 0x4 4.--5. "CLK1_SRC,Clock y source signal selector" "0,1,2,3" bitfld.long 0x4 0.--1. "CLK0_SRC,Clock y source signal selector" "0,1,2,3" group.long 0x41F8++0x7 line.long 0x0 "CCM9_CFG," bitfld.long 0x0 31. "TBU_DIR2,DIR1 input signal of module TBU timebase [z]." "0,1" bitfld.long 0x0 30. "TBU_DIR1,DIR1 input signal of module TBU timebase [z]." "0,1" newline bitfld.long 0x0 16.--17. "CLS_CLK_DIV,Cluster Clock Divider." "0,1,2,3" bitfld.long 0x0 8. "EN_TIO_DTM,Enable TIO and connected DTM" "0,1" newline bitfld.long 0x0 7. "EN_CMP_MON,Enable CMP and MON" "0,1" bitfld.long 0x0 6. "EN_PSM,Enable PSM" "0,1" newline bitfld.long 0x0 5. "EN_BRC,Enable BRC" "0,1" bitfld.long 0x0 4. "EN_DPLL_MAP,Enable DPLL and MAP" "0,1" newline bitfld.long 0x0 3. "EN_MCS,Enable MCS" "0,1" bitfld.long 0x0 2. "EN_ATOM_ADTM,Enable ATOM and ADTM" "0,1" newline bitfld.long 0x0 1. "EN_TOM_SPE_TDTM,Enable TOM SPE and TDTM" "0,1" bitfld.long 0x0 0. "EN_TIM,Enable TIM" "0,1" line.long 0x4 "CCM9_PROT," bitfld.long 0x4 0. "CLS_PROT,Cluster Protection" "0,1" group.long 0x5000++0xB line.long 0x0 "AXIM9_FREE," bitfld.long 0x0 3. "FREE3,This bit represents the allocation status of the slot [t]" "0,1" bitfld.long 0x0 2. "FREE2,This bit represents the allocation status of the slot [t]" "0,1" newline bitfld.long 0x0 1. "FREE1,This bit represents the allocation status of the slot [t]" "0,1" bitfld.long 0x0 0. "FREE0,This bit represents the allocation status of the slot [t]" "0,1" line.long 0x4 "AXIM9_REQUEST," hexmask.long.byte 0x4 24.--31. 1. "REQID,This bit field shows the new allocated slot as binary encoded index. If no slot could be allocated this bit field is read as all 1 (0xff)." bitfld.long 0x4 3. "REQ1HOT3,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 2. "REQ1HOT2,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" bitfld.long 0x4 1. "REQ1HOT1,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" newline bitfld.long 0x4 0. "REQ1HOT0,A read to the AXIM[i]_REQUEST register will allocate a new slot if any slot is available. This bit field shows the new allocated slot as 1-hot encoded vector. If no slot could be allocated this bit field is read as all 0." "0,1" line.long 0x8 "AXIM9_RELEASE," bitfld.long 0x8 3. "RELREQ3,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" bitfld.long 0x8 2. "RELREQ2,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" newline bitfld.long 0x8 1. "RELREQ1,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" bitfld.long 0x8 0. "RELREQ0,Slot [t] release request: A write to RELREQ will de-allocate one or more slots. Each bit in RELREQ represents one slot." "0,1" group.long 0x5020++0x3 line.long 0x0 "AXIM9_SLOT0_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5028++0x3 line.long 0x0 "AXIM9_SLOT0_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5030++0xB line.long 0x0 "AXIM9_SLOT0_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM9_SLOT0_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM9_SLOT0_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5040++0x3 line.long 0x0 "AXIM9_SLOT1_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5048++0x3 line.long 0x0 "AXIM9_SLOT1_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5050++0xB line.long 0x0 "AXIM9_SLOT1_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM9_SLOT1_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM9_SLOT1_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5060++0x3 line.long 0x0 "AXIM9_SLOT2_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5068++0x3 line.long 0x0 "AXIM9_SLOT2_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5070++0xB line.long 0x0 "AXIM9_SLOT2_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM9_SLOT2_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM9_SLOT2_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" group.long 0x5080++0x3 line.long 0x0 "AXIM9_SLOT3_ADDR_LOW," hexmask.long 0x0 0.--31. 1. "AXI_ADDR,Address for the AXI transaction." group.long 0x5088++0x3 line.long 0x0 "AXIM9_SLOT3_DATA_LOW," hexmask.long 0x0 0.--31. 1. "AXI_DATA_LOW,AXI write operation (AXIM[i]_SLOT[s]_CFG1.AXI_RW=0):" group.long 0x5090++0xB line.long 0x0 "AXIM9_SLOT3_CFG1," bitfld.long 0x0 25. "AXI_RW,AXI Read Write indication" "0,1" bitfld.long 0x0 22.--24. "AXI_SIZE,AXI data size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--19. "AXI_LOCK,AXI Lock indication" "0,1,2,3" hexmask.long.byte 0x0 14.--17. 1. "AXI_CACHE,AxCACHE bit field (see ARM AXI-3 spec)" newline bitfld.long 0x0 11.--13. "AXI_PROT,AxPROT bit field:" "0: Data mode access,1: instruction mode access,?,?,?,?,?,?" bitfld.long 0x0 5.--6. "PRIO,Slot priority. Priority used for slot arbitration. Lowest priority is 0 highest priority is 3" "0,1,2,3" newline bitfld.long 0x0 4. "AUTO_INCR,Enable or disable auto-increment mode" "0,1" hexmask.long.byte 0x0 0.--3. 1. "INCR,Address increment for auto-increment mode" line.long 0x4 "AXIM9_SLOT3_CFG2," hexmask.long.word 0x4 0.--15. 1. "AXI_ID,AXI ID for transaction. If posted writes are enabled (generic) the lower bit of the AXI_ID selects between posted and none-posted writes." line.long 0x8 "AXIM9_SLOT3_STATUS," bitfld.long 0x8 4.--5. "RESP,AXI response from last AXI transaction" "0,1,2,3" bitfld.long 0x8 3. "READY,This bit represents the slot READY state." "0,1" newline bitfld.long 0x8 2. "STARTED,This bit represents the slot STARTED state." "0,1" bitfld.long 0x8 1. "QUEUED,This bit represents the slot QUEUED state." "0,1" newline bitfld.long 0x8 0. "ALLOC,AXI Slot ccupation indication" "0,1" repeat 16384. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10000)++0x3 line.long 0x0 "MCS9_MEM[$1]," hexmask.long 0x0 0.--31. 1. "DATA,MCS memory location." repeat.end tree.end tree "GTMINT_1" base ad:0x70B00000 group.long 0xD0++0x3 line.long 0x0 "MCR,GTM Module Configuration Register" bitfld.long 0x0 30. "MDIS,MDIS" "0: Normal Mode.,1: Module disable request" bitfld.long 0x0 16. "AEISREN,AEISREN" "0: AEI soft-reset control is disabled.,1: AEI soft-reset control is enabled." bitfld.long 0x0 14. "STPS,STPS" "0: Normal Mode.,1: GTM is in Stop Mode." newline bitfld.long 0x0 0. "DEBUG_ACCESS_EN,Debug Access enable" "0: Debug access is disabled.,1: Debug access is enabled." group.long 0xD8++0x7 line.long 0x0 "INTCLR,GTM Interrupts Clear Register" hexmask.long.word 0x0 0.--9. 1. "INTCLR_PTR,INTCLR_PTR" line.long 0x4 "MAEICR,GTM AEI Control Register" bitfld.long 0x4 0. "AEISRST,AEISRST" "0,1" tree.end tree.end tree "HSM (Hardware Security Module)" base ad:0x0 tree "HSM2HT_0" base ad:0x7109C000 group.long 0x0++0x17 line.long 0x0 "HSM2HTF,HSM to Host Flags register" bitfld.long 0x0 31. "FLAG31,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 30. "FLAG30,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 29. "FLAG29,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 28. "FLAG28,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 27. "FLAG27,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 26. "FLAG26,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 25. "FLAG25,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 24. "FLAG24,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 23. "FLAG23,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 22. "FLAG22,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 21. "FLAG21,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 20. "FLAG20,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 19. "FLAG19,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 18. "FLAG18,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 17. "FLAG17,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 16. "FLAG16,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 15. "FLAG15,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 14. "FLAG14,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 13. "FLAG13,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 12. "FLAG12,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 11. "FLAG11,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 10. "FLAG10,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 9. "FLAG9,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 8. "FLAG8,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 7. "FLAG7,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 6. "FLAG6,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 5. "FLAG5,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 4. "FLAG4,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 3. "FLAG3,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 2. "FLAG2,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 1. "FLAG1,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 0. "FLAG0,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" line.long 0x4 "HSM2HTIE,HSM to Host Interrupt Enable register" bitfld.long 0x4 31. "IE31,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 30. "IE30,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 29. "IE29,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 28. "IE28,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 27. "IE27,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 26. "IE26,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 25. "IE25,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 24. "IE24,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 23. "IE23,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 22. "IE22,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 21. "IE21,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 20. "IE20,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 19. "IE19,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 18. "IE18,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 17. "IE17,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 16. "IE16,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 15. "IE15,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 14. "IE14,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 13. "IE13,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 12. "IE12,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 11. "IE11,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 10. "IE10,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 9. "IE9,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 8. "IE8,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 7. "IE7,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 6. "IE6,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 5. "IE5,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 4. "IE4,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 3. "IE3,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 2. "IE2,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 1. "IE1,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 0. "IE0,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" line.long 0x8 "HT2HSMF,Host to HSM Flags register" bitfld.long 0x8 31. "FLAG31,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 30. "FLAG30,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 29. "FLAG29,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 28. "FLAG28,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 27. "FLAG27,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 26. "FLAG26,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 25. "FLAG25,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 24. "FLAG24,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 23. "FLAG23,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 22. "FLAG22,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 21. "FLAG21,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 20. "FLAG20,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 19. "FLAG19,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 18. "FLAG18,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 17. "FLAG17,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 16. "FLAG16,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 15. "FLAG15,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 14. "FLAG14,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 13. "FLAG13,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 12. "FLAG12,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 11. "FLAG11,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 10. "FLAG10,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 9. "FLAG9,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 8. "FLAG8,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 7. "FLAG7,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 6. "FLAG6,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 5. "FLAG5,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 4. "FLAG4,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 3. "FLAG3,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 2. "FLAG2,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 1. "FLAG1,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 0. "FLAG0,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" line.long 0xC "HT2HSMIE,Host to HSM Interrupt Enable register" bitfld.long 0xC 31. "IE31,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 30. "IE30,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 29. "IE29,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 28. "IE28,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 27. "IE27,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 26. "IE26,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 25. "IE25,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 24. "IE24,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 23. "IE23,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 22. "IE22,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 21. "IE21,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 20. "IE20,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 19. "IE19,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 18. "IE18,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 17. "IE17,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 16. "IE16,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 15. "IE15,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 14. "IE14,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 13. "IE13,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 12. "IE12,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 11. "IE11,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 10. "IE10,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 9. "IE9,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 8. "IE8,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 7. "IE7,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 6. "IE6,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 5. "IE5,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 4. "IE4,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 3. "IE3,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 2. "IE2,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 1. "IE1,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 0. "IE0,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" line.long 0x10 "HSM2HTS,HSM to Host Status register" bitfld.long 0x10 31. "STATUS31,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 30. "STATUS30,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 29. "STATUS29,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 28. "STATUS28,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 27. "STATUS27,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 26. "STATUS26,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 25. "STATUS25,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 24. "STATUS24,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 23. "STATUS23,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 22. "STATUS22,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 21. "STATUS21,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 20. "STATUS20,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 19. "STATUS19,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 18. "STATUS18,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 17. "STATUS17,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 16. "STATUS16,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 15. "STATUS15,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 14. "STATUS14,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 13. "STATUS13,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 12. "STATUS12,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 11. "STATUS11,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 10. "STATUS10,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 9. "STATUS9,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 8. "STATUS8,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 7. "STATUS7,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 6. "STATUS6,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 5. "STATUS5,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 4. "STATUS4,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 3. "STATUS3,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 2. "STATUS2,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 1. "STATUS1,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 0. "STATUS0,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" line.long 0x14 "HT2HSMS,Host to HSM Status register" bitfld.long 0x14 31. "STATUS31,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 30. "STATUS30,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 29. "STATUS29,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 28. "STATUS28,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 27. "STATUS27,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 26. "STATUS26,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 25. "STATUS25,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 24. "STATUS24,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 23. "STATUS23,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 22. "STATUS22,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 21. "STATUS21,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 20. "STATUS20,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 19. "STATUS19,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 18. "STATUS18,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 17. "STATUS17,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 16. "STATUS16,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 15. "STATUS15,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 14. "STATUS14,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 13. "STATUS13,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 12. "STATUS12,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 11. "STATUS11,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 10. "STATUS10,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 9. "STATUS9,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 8. "STATUS8,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 7. "STATUS7,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 6. "STATUS6,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 5. "STATUS5,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 4. "STATUS4,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 3. "STATUS3,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 2. "STATUS2,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 1. "STATUS1,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 0. "STATUS0,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" tree.end tree "HSM2HT_1" base ad:0x7169C000 group.long 0x0++0x17 line.long 0x0 "HSM2HTF,HSM to Host Flags register" bitfld.long 0x0 31. "FLAG31,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 30. "FLAG30,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 29. "FLAG29,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 28. "FLAG28,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 27. "FLAG27,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 26. "FLAG26,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 25. "FLAG25,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 24. "FLAG24,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 23. "FLAG23,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 22. "FLAG22,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 21. "FLAG21,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 20. "FLAG20,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 19. "FLAG19,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 18. "FLAG18,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 17. "FLAG17,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 16. "FLAG16,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 15. "FLAG15,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 14. "FLAG14,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 13. "FLAG13,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 12. "FLAG12,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 11. "FLAG11,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 10. "FLAG10,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 9. "FLAG9,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 8. "FLAG8,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 7. "FLAG7,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 6. "FLAG6,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 5. "FLAG5,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 4. "FLAG4,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 3. "FLAG3,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 2. "FLAG2,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 1. "FLAG1,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 0. "FLAG0,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" line.long 0x4 "HSM2HTIE,HSM to Host Interrupt Enable register" bitfld.long 0x4 31. "IE31,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 30. "IE30,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 29. "IE29,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 28. "IE28,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 27. "IE27,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 26. "IE26,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 25. "IE25,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 24. "IE24,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 23. "IE23,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 22. "IE22,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 21. "IE21,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 20. "IE20,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 19. "IE19,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 18. "IE18,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 17. "IE17,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 16. "IE16,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 15. "IE15,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 14. "IE14,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 13. "IE13,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 12. "IE12,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 11. "IE11,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 10. "IE10,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 9. "IE9,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 8. "IE8,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 7. "IE7,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 6. "IE6,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 5. "IE5,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 4. "IE4,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 3. "IE3,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 2. "IE2,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 1. "IE1,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 0. "IE0,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" line.long 0x8 "HT2HSMF,Host to HSM Flags register" bitfld.long 0x8 31. "FLAG31,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 30. "FLAG30,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 29. "FLAG29,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 28. "FLAG28,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 27. "FLAG27,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 26. "FLAG26,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 25. "FLAG25,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 24. "FLAG24,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 23. "FLAG23,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 22. "FLAG22,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 21. "FLAG21,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 20. "FLAG20,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 19. "FLAG19,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 18. "FLAG18,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 17. "FLAG17,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 16. "FLAG16,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 15. "FLAG15,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 14. "FLAG14,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 13. "FLAG13,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 12. "FLAG12,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 11. "FLAG11,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 10. "FLAG10,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 9. "FLAG9,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 8. "FLAG8,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 7. "FLAG7,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 6. "FLAG6,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 5. "FLAG5,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 4. "FLAG4,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 3. "FLAG3,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 2. "FLAG2,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 1. "FLAG1,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 0. "FLAG0,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" line.long 0xC "HT2HSMIE,Host to HSM Interrupt Enable register" bitfld.long 0xC 31. "IE31,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 30. "IE30,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 29. "IE29,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 28. "IE28,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 27. "IE27,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 26. "IE26,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 25. "IE25,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 24. "IE24,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 23. "IE23,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 22. "IE22,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 21. "IE21,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 20. "IE20,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 19. "IE19,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 18. "IE18,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 17. "IE17,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 16. "IE16,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 15. "IE15,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 14. "IE14,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 13. "IE13,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 12. "IE12,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 11. "IE11,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 10. "IE10,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 9. "IE9,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 8. "IE8,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 7. "IE7,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 6. "IE6,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 5. "IE5,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 4. "IE4,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 3. "IE3,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 2. "IE2,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 1. "IE1,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 0. "IE0,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" line.long 0x10 "HSM2HTS,HSM to Host Status register" bitfld.long 0x10 31. "STATUS31,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 30. "STATUS30,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 29. "STATUS29,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 28. "STATUS28,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 27. "STATUS27,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 26. "STATUS26,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 25. "STATUS25,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 24. "STATUS24,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 23. "STATUS23,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 22. "STATUS22,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 21. "STATUS21,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 20. "STATUS20,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 19. "STATUS19,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 18. "STATUS18,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 17. "STATUS17,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 16. "STATUS16,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 15. "STATUS15,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 14. "STATUS14,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 13. "STATUS13,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 12. "STATUS12,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 11. "STATUS11,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 10. "STATUS10,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 9. "STATUS9,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 8. "STATUS8,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 7. "STATUS7,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 6. "STATUS6,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 5. "STATUS5,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 4. "STATUS4,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 3. "STATUS3,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 2. "STATUS2,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 1. "STATUS1,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 0. "STATUS0,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" line.long 0x14 "HT2HSMS,Host to HSM Status register" bitfld.long 0x14 31. "STATUS31,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 30. "STATUS30,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 29. "STATUS29,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 28. "STATUS28,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 27. "STATUS27,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 26. "STATUS26,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 25. "STATUS25,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 24. "STATUS24,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 23. "STATUS23,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 22. "STATUS22,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 21. "STATUS21,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 20. "STATUS20,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 19. "STATUS19,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 18. "STATUS18,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 17. "STATUS17,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 16. "STATUS16,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 15. "STATUS15,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 14. "STATUS14,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 13. "STATUS13,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 12. "STATUS12,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 11. "STATUS11,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 10. "STATUS10,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 9. "STATUS9,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 8. "STATUS8,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 7. "STATUS7,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 6. "STATUS6,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 5. "STATUS5,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 4. "STATUS4,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 3. "STATUS3,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 2. "STATUS2,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 1. "STATUS1,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 0. "STATUS0,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" tree.end tree "HSM2HT_2" base ad:0x710A0000 group.long 0x0++0x17 line.long 0x0 "HSM2HTF,HSM to Host Flags register" bitfld.long 0x0 31. "FLAG31,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 30. "FLAG30,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 29. "FLAG29,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 28. "FLAG28,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 27. "FLAG27,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 26. "FLAG26,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 25. "FLAG25,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 24. "FLAG24,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 23. "FLAG23,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 22. "FLAG22,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 21. "FLAG21,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 20. "FLAG20,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 19. "FLAG19,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 18. "FLAG18,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 17. "FLAG17,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 16. "FLAG16,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 15. "FLAG15,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 14. "FLAG14,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 13. "FLAG13,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 12. "FLAG12,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 11. "FLAG11,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 10. "FLAG10,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 9. "FLAG9,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 8. "FLAG8,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 7. "FLAG7,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 6. "FLAG6,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 5. "FLAG5,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 4. "FLAG4,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 3. "FLAG3,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 2. "FLAG2,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 1. "FLAG1,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 0. "FLAG0,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" line.long 0x4 "HSM2HTIE,HSM to Host Interrupt Enable register" bitfld.long 0x4 31. "IE31,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 30. "IE30,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 29. "IE29,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 28. "IE28,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 27. "IE27,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 26. "IE26,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 25. "IE25,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 24. "IE24,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 23. "IE23,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 22. "IE22,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 21. "IE21,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 20. "IE20,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 19. "IE19,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 18. "IE18,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 17. "IE17,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 16. "IE16,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 15. "IE15,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 14. "IE14,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 13. "IE13,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 12. "IE12,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 11. "IE11,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 10. "IE10,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 9. "IE9,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 8. "IE8,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 7. "IE7,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 6. "IE6,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 5. "IE5,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 4. "IE4,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 3. "IE3,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 2. "IE2,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 1. "IE1,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 0. "IE0,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" line.long 0x8 "HT2HSMF,Host to HSM Flags register" bitfld.long 0x8 31. "FLAG31,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 30. "FLAG30,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 29. "FLAG29,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 28. "FLAG28,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 27. "FLAG27,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 26. "FLAG26,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 25. "FLAG25,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 24. "FLAG24,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 23. "FLAG23,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 22. "FLAG22,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 21. "FLAG21,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 20. "FLAG20,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 19. "FLAG19,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 18. "FLAG18,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 17. "FLAG17,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 16. "FLAG16,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 15. "FLAG15,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 14. "FLAG14,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 13. "FLAG13,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 12. "FLAG12,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 11. "FLAG11,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 10. "FLAG10,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 9. "FLAG9,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 8. "FLAG8,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 7. "FLAG7,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 6. "FLAG6,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 5. "FLAG5,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 4. "FLAG4,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 3. "FLAG3,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 2. "FLAG2,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 1. "FLAG1,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 0. "FLAG0,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" line.long 0xC "HT2HSMIE,Host to HSM Interrupt Enable register" bitfld.long 0xC 31. "IE31,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 30. "IE30,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 29. "IE29,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 28. "IE28,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 27. "IE27,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 26. "IE26,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 25. "IE25,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 24. "IE24,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 23. "IE23,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 22. "IE22,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 21. "IE21,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 20. "IE20,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 19. "IE19,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 18. "IE18,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 17. "IE17,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 16. "IE16,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 15. "IE15,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 14. "IE14,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 13. "IE13,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 12. "IE12,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 11. "IE11,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 10. "IE10,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 9. "IE9,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 8. "IE8,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 7. "IE7,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 6. "IE6,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 5. "IE5,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 4. "IE4,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 3. "IE3,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 2. "IE2,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 1. "IE1,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 0. "IE0,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" line.long 0x10 "HSM2HTS,HSM to Host Status register" bitfld.long 0x10 31. "STATUS31,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 30. "STATUS30,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 29. "STATUS29,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 28. "STATUS28,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 27. "STATUS27,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 26. "STATUS26,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 25. "STATUS25,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 24. "STATUS24,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 23. "STATUS23,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 22. "STATUS22,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 21. "STATUS21,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 20. "STATUS20,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 19. "STATUS19,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 18. "STATUS18,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 17. "STATUS17,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 16. "STATUS16,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 15. "STATUS15,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 14. "STATUS14,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 13. "STATUS13,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 12. "STATUS12,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 11. "STATUS11,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 10. "STATUS10,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 9. "STATUS9,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 8. "STATUS8,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 7. "STATUS7,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 6. "STATUS6,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 5. "STATUS5,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 4. "STATUS4,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 3. "STATUS3,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 2. "STATUS2,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 1. "STATUS1,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 0. "STATUS0,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" line.long 0x14 "HT2HSMS,Host to HSM Status register" bitfld.long 0x14 31. "STATUS31,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 30. "STATUS30,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 29. "STATUS29,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 28. "STATUS28,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 27. "STATUS27,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 26. "STATUS26,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 25. "STATUS25,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 24. "STATUS24,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 23. "STATUS23,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 22. "STATUS22,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 21. "STATUS21,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 20. "STATUS20,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 19. "STATUS19,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 18. "STATUS18,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 17. "STATUS17,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 16. "STATUS16,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 15. "STATUS15,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 14. "STATUS14,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 13. "STATUS13,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 12. "STATUS12,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 11. "STATUS11,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 10. "STATUS10,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 9. "STATUS9,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 8. "STATUS8,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 7. "STATUS7,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 6. "STATUS6,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 5. "STATUS5,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 4. "STATUS4,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 3. "STATUS3,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 2. "STATUS2,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 1. "STATUS1,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 0. "STATUS0,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" tree.end tree "HSM2HT_3" base ad:0x716A0000 group.long 0x0++0x17 line.long 0x0 "HSM2HTF,HSM to Host Flags register" bitfld.long 0x0 31. "FLAG31,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 30. "FLAG30,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 29. "FLAG29,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 28. "FLAG28,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 27. "FLAG27,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 26. "FLAG26,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 25. "FLAG25,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 24. "FLAG24,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 23. "FLAG23,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 22. "FLAG22,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 21. "FLAG21,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 20. "FLAG20,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 19. "FLAG19,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 18. "FLAG18,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 17. "FLAG17,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 16. "FLAG16,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 15. "FLAG15,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 14. "FLAG14,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 13. "FLAG13,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 12. "FLAG12,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 11. "FLAG11,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 10. "FLAG10,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 9. "FLAG9,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 8. "FLAG8,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 7. "FLAG7,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 6. "FLAG6,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 5. "FLAG5,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 4. "FLAG4,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 3. "FLAG3,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 2. "FLAG2,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" newline bitfld.long 0x0 1. "FLAG1,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" bitfld.long 0x0 0. "FLAG0,FLAG[n]" "0: HSM2HOST flag[n] cleared (by Host),?" line.long 0x4 "HSM2HTIE,HSM to Host Interrupt Enable register" bitfld.long 0x4 31. "IE31,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 30. "IE30,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 29. "IE29,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 28. "IE28,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 27. "IE27,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 26. "IE26,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 25. "IE25,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 24. "IE24,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 23. "IE23,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 22. "IE22,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 21. "IE21,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 20. "IE20,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 19. "IE19,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 18. "IE18,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 17. "IE17,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 16. "IE16,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 15. "IE15,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 14. "IE14,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 13. "IE13,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 12. "IE12,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 11. "IE11,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 10. "IE10,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 9. "IE9,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 8. "IE8,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 7. "IE7,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 6. "IE6,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 5. "IE5,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 4. "IE4,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 3. "IE3,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 2. "IE2,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" newline bitfld.long 0x4 1. "IE1,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" bitfld.long 0x4 0. "IE0,IE[n]" "0: HSM2HT Interrupt Enable [n] cleared,1: HSM2HT Interrupt Enable [n] set" line.long 0x8 "HT2HSMF,Host to HSM Flags register" bitfld.long 0x8 31. "FLAG31,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 30. "FLAG30,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 29. "FLAG29,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 28. "FLAG28,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 27. "FLAG27,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 26. "FLAG26,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 25. "FLAG25,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 24. "FLAG24,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 23. "FLAG23,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 22. "FLAG22,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 21. "FLAG21,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 20. "FLAG20,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 19. "FLAG19,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 18. "FLAG18,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 17. "FLAG17,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 16. "FLAG16,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 15. "FLAG15,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 14. "FLAG14,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 13. "FLAG13,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 12. "FLAG12,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 11. "FLAG11,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 10. "FLAG10,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 9. "FLAG9,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 8. "FLAG8,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 7. "FLAG7,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 6. "FLAG6,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 5. "FLAG5,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 4. "FLAG4,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 3. "FLAG3,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 2. "FLAG2,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" newline bitfld.long 0x8 1. "FLAG1,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" bitfld.long 0x8 0. "FLAG0,FLAG[n]" "0: HSM2HOST flag[n] cleared (by HSM),1: HSM2HOST flag[n] set (by Host)" line.long 0xC "HT2HSMIE,Host to HSM Interrupt Enable register" bitfld.long 0xC 31. "IE31,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 30. "IE30,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 29. "IE29,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 28. "IE28,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 27. "IE27,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 26. "IE26,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 25. "IE25,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 24. "IE24,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 23. "IE23,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 22. "IE22,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 21. "IE21,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 20. "IE20,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 19. "IE19,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 18. "IE18,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 17. "IE17,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 16. "IE16,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 15. "IE15,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 14. "IE14,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 13. "IE13,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 12. "IE12,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 11. "IE11,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 10. "IE10,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 9. "IE9,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 8. "IE8,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 7. "IE7,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 6. "IE6,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 5. "IE5,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 4. "IE4,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 3. "IE3,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 2. "IE2,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" newline bitfld.long 0xC 1. "IE1,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" bitfld.long 0xC 0. "IE0,IE[n]" "0: HT2HSM Interrupt Enable [n] cleared,1: HT2HSM Interrupt Enable [n] set" line.long 0x10 "HSM2HTS,HSM to Host Status register" bitfld.long 0x10 31. "STATUS31,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 30. "STATUS30,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 29. "STATUS29,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 28. "STATUS28,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 27. "STATUS27,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 26. "STATUS26,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 25. "STATUS25,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 24. "STATUS24,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 23. "STATUS23,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 22. "STATUS22,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 21. "STATUS21,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 20. "STATUS20,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 19. "STATUS19,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 18. "STATUS18,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 17. "STATUS17,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 16. "STATUS16,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 15. "STATUS15,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 14. "STATUS14,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 13. "STATUS13,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 12. "STATUS12,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 11. "STATUS11,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 10. "STATUS10,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 9. "STATUS9,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 8. "STATUS8,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 7. "STATUS7,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 6. "STATUS6,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 5. "STATUS5,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 4. "STATUS4,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 3. "STATUS3,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 2. "STATUS2,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" newline bitfld.long 0x10 1. "STATUS1,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" bitfld.long 0x10 0. "STATUS0,STATUS[n]" "0: HSM2HT STATUS bit [n] cleared,1: HSM2HT STATUS bit [n] set" line.long 0x14 "HT2HSMS,Host to HSM Status register" bitfld.long 0x14 31. "STATUS31,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 30. "STATUS30,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 29. "STATUS29,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 28. "STATUS28,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 27. "STATUS27,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 26. "STATUS26,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 25. "STATUS25,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 24. "STATUS24,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 23. "STATUS23,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 22. "STATUS22,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 21. "STATUS21,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 20. "STATUS20,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 19. "STATUS19,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 18. "STATUS18,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 17. "STATUS17,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 16. "STATUS16,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 15. "STATUS15,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 14. "STATUS14,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 13. "STATUS13,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 12. "STATUS12,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 11. "STATUS11,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 10. "STATUS10,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 9. "STATUS9,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 8. "STATUS8,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 7. "STATUS7,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 6. "STATUS6,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 5. "STATUS5,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 4. "STATUS4,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 3. "STATUS3,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 2. "STATUS2,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" newline bitfld.long 0x14 1. "STATUS1,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" bitfld.long 0x14 0. "STATUS0,STATUS[n]" "0: HT2HSM STATUS bit [n] cleared,1: HT2HSM STATUS bit [n] set" tree.end tree "HSM_MAILBOX_0" base ad:0x704E0000 rgroup.long 0x4++0x7 line.long 0x0 "TS,Transmitter Status register" bitfld.long 0x0 31. "BSY,This bit indicates the Transmitter SW whether the transmission channel is busy or ready to accept a new message." "0: Channel is available,1: Channel is busy" bitfld.long 0x0 16. "CKG,This bit indicates the Transmitter SW whether the receiver HW clock is frozen or not." "0: Receiver HW clock is working,1: Receiver HW clock is frozen" newline bitfld.long 0x0 0. "ERR,This bit indicates the Transmitter SW whether any error happened during the message transmission." "0: No error happened during the transmission,1: An error happened during the transmission" line.long 0x4 "TMBS,Transmitter Message Box Status Register" bitfld.long 0x4 3. "MB3,This field indicates if the corresponding Message Box at the receiver side is available or not." "0: Message Box is available,1: Message Box is busy" bitfld.long 0x4 2. "MB2,This field indicates if the corresponding Message Box at the receiver side is available or not." "0: Message Box is available,1: Message Box is busy" newline bitfld.long 0x4 1. "MB1,This field indicates if the corresponding Message Box at the receiver side is available or not." "0: Message Box is available,1: Message Box is busy" bitfld.long 0x4 0. "MB0,This field indicates if the corresponding Message Box at the receiver side is available or not." "0: Message Box is available,1: Message Box is busy" group.long 0x10++0xB line.long 0x0 "TI,Transmitter Interrupt register" bitfld.long 0x0 22. "SNT,Size Not Transmitted interrupt pending bit" "0: The size has been correctly transmitted,1: The size has not been transmitted" bitfld.long 0x0 21. "PCF,Parameter Check Failure interrupt pending bit" "0: A parameter check failure has not been detected,1: A parameter check failure has been detected" newline bitfld.long 0x0 20. "DTE,Data Transmit Error interrupt pending bit" "0: No error,1: A data corruption has been detected" bitfld.long 0x0 19. "RWO,Register write overflow interrupt pending bit" "0: No overflow,1: Overflow" newline bitfld.long 0x0 18. "MBO,Message Box overflow interrupt pending bit" "0: No overflow,1: Overflow" bitfld.long 0x0 17. "TXO,Transmission overflow interrupt pending bit" "0: No overflow,1: Overflow" newline bitfld.long 0x0 16. "OOO,Out of Order interrupt pending bit" "0: Register writing order is correct,1: Register writing order is wrong" bitfld.long 0x0 1. "MBA,Message Box availability interrupt pending bit" "0: No Message Box has become available,1: A Message Box has become available" newline bitfld.long 0x0 0. "TMC,End of message transmission interrupt pending bit" "0: End of message transmission has not occurred,1: End of message transmission has occurred" line.long 0x4 "TIM,Transmitter Interrupt Mask register" bitfld.long 0x4 22. "SNT,Mask for the Size Not transmitted interrupt" "0: Interrupt is enabled,1: Interrupt is masked" bitfld.long 0x4 21. "PCF,Mask for the Parameter Check Failure interrupt" "0: Interrupt is enabled,1: Interrupt is masked" newline bitfld.long 0x4 20. "DTE,Mask for the Data Transmit Error interrupt" "0: Interrupt is enabled,1: Interrupt is masked" bitfld.long 0x4 19. "RWO,Mask for the Register Write Overflow interrupt" "0: Interrupt is enabled,1: Interrupt is masked" newline bitfld.long 0x4 18. "MBO,Mask for the Message Box Overflow interrupt" "0: Interrupt is enabled,1: Interrupt is masked" bitfld.long 0x4 17. "TXO,Mask for the Transmission Overflow interrupt" "0: Interrupt is enabled,1: Interrupt is masked" newline bitfld.long 0x4 16. "OOO,Mask for the Out of Order interrupt" "0: Interrupt is enabled,1: Interrupt is masked" bitfld.long 0x4 1. "MBA,Mask for the Message Box Available interrupt" "0: Interrupt is enabled,1: Interrupt is masked" newline bitfld.long 0x4 0. "TMC,Mask for the Transmission Message Completed interrupt" "0: Interrupt is enabled,1: Interrupt is masked" line.long 0x8 "TEOM,Transmitter End of Message register" hexmask.long 0x8 0.--31. 1. "EOM,The field is used to indicate if a whole message has been written by the transmitter SW into the message registers." group.long 0x1000++0x47 line.long 0x0 "TC,Transmitter Control register" hexmask.long.word 0x0 16.--31. 1. "USER,This field is used by the SW to add additional information." hexmask.long.byte 0x0 8.--15. 1. "PRIO,This field specifies the priority of the service request and accordingly the destination message box (MB) following the scheme:" newline hexmask.long.byte 0x0 0.--7. 1. "CMD,This field specifies the ID of the service request." line.long 0x4 "TX,Transmitter Context Register" hexmask.long 0x4 0.--31. 1. "CONTEXT,The field contains SW-specific data" line.long 0x8 "TP0,Transmitter Parameter Register 0" hexmask.long 0x8 0.--31. 1. "PARAM,The field contains the parameter associated to the transmitted message" line.long 0xC "TP1,Transmitter Parameter Register 1" hexmask.long 0xC 0.--31. 1. "PARAM,The field contains the parameter associated to the transmitted message" line.long 0x10 "TP2,Transmitter Parameter Register 2" hexmask.long 0x10 0.--31. 1. "PARAM,The field contains the parameter associated to the transmitted message" line.long 0x14 "TP3,Transmitter Parameter Register 3" hexmask.long 0x14 0.--31. 1. "PARAM,The field contains the parameter associated to the transmitted message" line.long 0x18 "TP4,Transmitter Parameter Register 4" hexmask.long 0x18 0.--31. 1. "PARAM,The field contains the parameter associated to the transmitted message" line.long 0x1C "TP5,Transmitter Parameter Register 5" hexmask.long 0x1C 0.--31. 1. "PARAM,The field contains the parameter associated to the transmitted message" line.long 0x20 "TP6,Transmitter Parameter Register 6" hexmask.long 0x20 0.--31. 1. "PARAM,The field contains the parameter associated to the transmitted message" line.long 0x24 "TP7,Transmitter Parameter Register 7" hexmask.long 0x24 0.--31. 1. "PARAM,The field contains the parameter associated to the transmitted message" line.long 0x28 "TP8,Transmitter Parameter Register 8" hexmask.long 0x28 0.--31. 1. "PARAM,The field contains the parameter associated to the transmitted message" line.long 0x2C "TP9,Transmitter Parameter Register 9" hexmask.long 0x2C 0.--31. 1. "PARAM,The field contains the parameter associated to the transmitted message" line.long 0x30 "TP10,Transmitter Parameter Register 10" hexmask.long 0x30 0.--31. 1. "PARAM,The field contains the parameter associated to the transmitted message" line.long 0x34 "TP11,Transmitter Parameter Register 11" hexmask.long 0x34 0.--31. 1. "PARAM,The field contains the parameter associated to the transmitted message" line.long 0x38 "TP12,Transmitter Parameter Register 12" hexmask.long 0x38 0.--31. 1. "PARAM,The field contains the parameter associated to the transmitted message" line.long 0x3C "TP13,Transmitter Parameter Register 13" hexmask.long 0x3C 0.--31. 1. "PARAM,The field contains the parameter associated to the transmitted message" line.long 0x40 "TP14,Transmitter Parameter Register 14" hexmask.long 0x40 0.--31. 1. "PARAM,The field contains the parameter associated to the transmitted message" line.long 0x44 "TP15,Transmitter Parameter Register 15" hexmask.long 0x44 0.--31. 1. "PARAM,The field contains the parameter associated to the transmitted message" group.long 0x2000++0x7 line.long 0x0 "RCHBA,Receiver Command Handler Base Address register" hexmask.long 0x0 2.--31. 1. "ADDRESS,This field contains the starting address of the look-up table" line.long 0x4 "RCHC,Receiver Command Handler Configuration register" hexmask.long.byte 0x4 0.--7. 1. "CCI,This field contains the starting index of the common command set" group.long 0x2C00++0x7 line.long 0x0 "RMBI,Receiver Message Box Interrupt register" bitfld.long 0x0 3. "MB3,The field indicates when a new message has been received by the corresponding Message Box." "0: No message has been received,1: A new message has been received" bitfld.long 0x0 2. "MB2,The field indicates when a new message has been received by the corresponding Message Box." "0: No message has been received,1: A new message has been received" newline bitfld.long 0x0 1. "MB1,The field indicates when a new message has been received by the corresponding Message Box." "0: No message has been received,1: A new message has been received" bitfld.long 0x0 0. "MB0,The field indicates when a new message has been received by the corresponding Message Box." "0: No message has been received,1: A new message has been received" line.long 0x4 "RMBIM,Receiver Message Box Interrupt Mask" bitfld.long 0x4 3. "MB3,Mask bit for the associated interrupt inside the RMBI register" "0: interrupt is enabled.,1: interrupt is masked." bitfld.long 0x4 2. "MB2,Mask bit for the associated interrupt inside the RMBI register" "0: interrupt is enabled.,1: interrupt is masked." newline bitfld.long 0x4 1. "MB1,Mask bit for the associated interrupt inside the RMBI register" "0: interrupt is enabled.,1: interrupt is masked." bitfld.long 0x4 0. "MB0,Mask bit for the associated interrupt inside the RMBI register" "0: interrupt is enabled.,1: interrupt is masked." rgroup.long 0x3000++0x13 line.long 0x0 "MB0_RC,MBn Receiver Control register" hexmask.long.word 0x0 16.--31. 1. "USER,The field stores additional information optionally written by the SW" hexmask.long.byte 0x0 8.--15. 1. "PRIO,The field stores the priority of the received command" newline hexmask.long.byte 0x0 0.--7. 1. "CMD,The field stores the ID of the received command" line.long 0x4 "MB0_RX,MBn Receiver Context register" hexmask.long 0x4 0.--31. 1. "CONTEXT,The field contains the Context token of the received message" line.long 0x8 "MB0_RP0,MBn Receiver Parameter register m" hexmask.long 0x8 0.--31. 1. "PARAM,The field contains a parameter token" line.long 0xC "MB0_RP1,MBn Receiver Parameter register m" hexmask.long 0xC 0.--31. 1. "PARAM,The field contains a parameter token" line.long 0x10 "MB0_RA,MBn Receiver Address register" hexmask.long 0x10 0.--31. 1. "ADDRESS,The field stores the address of the look-up table entry which stores the address of the command handling routine for the received command" group.long 0x3014++0x3 line.long 0x0 "MB0_RS,MBn Receiver Status register" bitfld.long 0x0 31. "HOLD,Hold bit" "0,1" bitfld.long 0x0 1. "RP1,Received Parameter flag bit" "0: The corresponding parameter is not received.,1: The corresponding parameter is received." newline bitfld.long 0x0 0. "RP0,Received Parameter flag bit" "0: The corresponding parameter is not received.,1: The corresponding parameter is received." rgroup.long 0x3080++0x13 line.long 0x0 "MB1_RC,MBn Receiver Control register" hexmask.long.word 0x0 16.--31. 1. "USER,The field stores additional information optionally written by the SW" hexmask.long.byte 0x0 8.--15. 1. "PRIO,The field stores the priority of the received command" newline hexmask.long.byte 0x0 0.--7. 1. "CMD,The field stores the ID of the received command" line.long 0x4 "MB1_RX,MBn Receiver Context register" hexmask.long 0x4 0.--31. 1. "CONTEXT,The field contains the Context token of the received message" line.long 0x8 "MB1_RP0,MBn Receiver Parameter register m" hexmask.long 0x8 0.--31. 1. "PARAM,The field contains a parameter token" line.long 0xC "MB1_RP1,MBn Receiver Parameter register m" hexmask.long 0xC 0.--31. 1. "PARAM,The field contains a parameter token" line.long 0x10 "MB1_RA,MBn Receiver Address register" hexmask.long 0x10 0.--31. 1. "ADDRESS,The field stores the address of the look-up table entry which stores the address of the command handling routine for the received command" group.long 0x3094++0x3 line.long 0x0 "MB1_RS,MBn Receiver Status register" bitfld.long 0x0 31. "HOLD,Hold bit" "0,1" bitfld.long 0x0 1. "RP1,Received Parameter flag bit" "0: The corresponding parameter is not received.,1: The corresponding parameter is received." newline bitfld.long 0x0 0. "RP0,Received Parameter flag bit" "0: The corresponding parameter is not received.,1: The corresponding parameter is received." rgroup.long 0x3100++0x13 line.long 0x0 "MB2_RC,MBn Receiver Control register" hexmask.long.word 0x0 16.--31. 1. "USER,The field stores additional information optionally written by the SW" hexmask.long.byte 0x0 8.--15. 1. "PRIO,The field stores the priority of the received command" newline hexmask.long.byte 0x0 0.--7. 1. "CMD,The field stores the ID of the received command" line.long 0x4 "MB2_RX,MBn Receiver Context register" hexmask.long 0x4 0.--31. 1. "CONTEXT,The field contains the Context token of the received message" line.long 0x8 "MB2_RP0,MBn Receiver Parameter register m" hexmask.long 0x8 0.--31. 1. "PARAM,The field contains a parameter token" line.long 0xC "MB2_RP1,MBn Receiver Parameter register m" hexmask.long 0xC 0.--31. 1. "PARAM,The field contains a parameter token" line.long 0x10 "MB2_RA,MBn Receiver Address register" hexmask.long 0x10 0.--31. 1. "ADDRESS,The field stores the address of the look-up table entry which stores the address of the command handling routine for the received command" group.long 0x3114++0x3 line.long 0x0 "MB2_RS,MBn Receiver Status register" bitfld.long 0x0 31. "HOLD,Hold bit" "0,1" bitfld.long 0x0 1. "RP1,Received Parameter flag bit" "0: The corresponding parameter is not received.,1: The corresponding parameter is received." newline bitfld.long 0x0 0. "RP0,Received Parameter flag bit" "0: The corresponding parameter is not received.,1: The corresponding parameter is received." rgroup.long 0x3180++0x13 line.long 0x0 "MB3_RC,MBn Receiver Control register" hexmask.long.word 0x0 16.--31. 1. "USER,The field stores additional information optionally written by the SW" hexmask.long.byte 0x0 8.--15. 1. "PRIO,The field stores the priority of the received command" newline hexmask.long.byte 0x0 0.--7. 1. "CMD,The field stores the ID of the received command" line.long 0x4 "MB3_RX,MBn Receiver Context register" hexmask.long 0x4 0.--31. 1. "CONTEXT,The field contains the Context token of the received message" line.long 0x8 "MB3_RP0,MBn Receiver Parameter register m" hexmask.long 0x8 0.--31. 1. "PARAM,The field contains a parameter token" line.long 0xC "MB3_RP1,MBn Receiver Parameter register m" hexmask.long 0xC 0.--31. 1. "PARAM,The field contains a parameter token" line.long 0x10 "MB3_RA,MBn Receiver Address register" hexmask.long 0x10 0.--31. 1. "ADDRESS,The field stores the address of the look-up table entry which stores the address of the command handling routine for the received command" group.long 0x3194++0x3 line.long 0x0 "MB3_RS,MBn Receiver Status register" bitfld.long 0x0 31. "HOLD,Hold bit" "0,1" bitfld.long 0x0 1. "RP1,Received Parameter flag bit" "0: The corresponding parameter is not received.,1: The corresponding parameter is received." newline bitfld.long 0x0 0. "RP0,Received Parameter flag bit" "0: The corresponding parameter is not received.,1: The corresponding parameter is received." tree.end tree.end tree "IBCM (Interrupt Broadcaster)" base ad:0x0 tree "CORE_0_SIG" base ad:0x6C200000 group.long 0x0++0xF7 line.long 0x0 "SGPPIREQ31_0_CL0C0," bitfld.long 0x0 31. "SGPPIREQ31,Cluster 0 Core 0 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 30. "SGPPIREQ30,Cluster 0 Core 0 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 29. "SGPPIREQ29,Cluster 0 Core 0 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 28. "SGPPIREQ28,Cluster 0 Core 0 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 27. "SGPPIREQ27,Cluster 0 Core 0 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 26. "SGPPIREQ26,Cluster 0 Core 0 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 25. "SGPPIREQ25,Cluster 0 Core 0 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 24. "SGPPIREQ24,Cluster 0 Core 0 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 23. "SGPPIREQ23,Cluster 0 Core 0 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 22. "SGPPIREQ22,Cluster 0 Core 0 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 21. "SGPPIREQ21,Cluster 0 Core 0 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 20. "SGPPIREQ20,Cluster 0 Core 0 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 19. "SGPPIREQ19,Cluster 0 Core 0 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 18. "SGPPIREQ18,Cluster 0 Core 0 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 17. "SGPPIREQ17,Cluster 0 Core 0 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 16. "SGPPIREQ16,Cluster 0 Core 0 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" line.long 0x4 "SGPPIREQ63_32_CL0C0," bitfld.long 0x4 27. "SGPPIREQ59,Cluster 0 Core 0 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" bitfld.long 0x4 26. "SGPPIREQ58,Cluster 0 Core 0 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 25. "SGPPIREQ57,Cluster 0 Core 0 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" bitfld.long 0x4 24. "SGPPIREQ56,Cluster 0 Core 0 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 19. "SGPPIREQ51,Cluster 0 Core 0 triggers interrupt to DME Core (cleared by hardware)" "0,1" bitfld.long 0x4 18. "SGPPIREQ50,Cluster 0 Core 0 triggers interrupt to DME Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 17. "SGPPIREQ49,Cluster 0 Core 0 triggers interrupt to DME Core (cleared by hardware)" "0,1" bitfld.long 0x4 16. "SGPPIREQ48,Cluster 0 Core 0 triggers interrupt to DME Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 15. "SGPPIREQ47,Cluster 0 Core 0 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 14. "SGPPIREQ46,Cluster 0 Core 0 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 13. "SGPPIREQ45,Cluster 0 Core 0 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 12. "SGPPIREQ44,Cluster 0 Core 0 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 11. "SGPPIREQ43,Cluster 0 Core 0 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 10. "SGPPIREQ42,Cluster 0 Core 0 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 9. "SGPPIREQ41,Cluster 0 Core 0 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 8. "SGPPIREQ40,Cluster 0 Core 0 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 7. "SGPPIREQ39,Cluster 0 Core 0 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 6. "SGPPIREQ38,Cluster 0 Core 0 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x4 5. "SGPPIREQ37,Cluster 0 Core 0 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 4. "SGPPIREQ36,Cluster 0 Core 0 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x4 3. "SGPPIREQ35,Cluster 0 Core 0 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 2. "SGPPIREQ34,Cluster 0 Core 0 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x4 1. "SGPPIREQ33,Cluster 0 Core 0 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 0. "SGPPIREQ32,Cluster 0 Core 0 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" line.long 0x8 "SGPPISETPEND31_0_CL0C0," bitfld.long 0x8 31. "SGPPISETPEND31,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 30. "SGPPISETPEND30,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 29. "SGPPISETPEND29,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 28. "SGPPISETPEND28,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 27. "SGPPISETPEND27,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 26. "SGPPISETPEND26,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 25. "SGPPISETPEND25,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 24. "SGPPISETPEND24,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 23. "SGPPISETPEND23,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 22. "SGPPISETPEND22,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 21. "SGPPISETPEND21,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 20. "SGPPISETPEND20,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 19. "SGPPISETPEND19,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 18. "SGPPISETPEND18,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 17. "SGPPISETPEND17,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 16. "SGPPISETPEND16,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" line.long 0xC "SGPPISETPEND63_32_CL0C0," bitfld.long 0xC 31. "SGPPISETPEND63,Set pending software interrupt on Cluster 0 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 30. "SGPPISETPEND62,Set pending software interrupt on Cluster 0 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 29. "SGPPISETPEND61,Set pending software interrupt on Cluster 0 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 28. "SGPPISETPEND60,Set pending software interrupt on Cluster 0 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 27. "SGPPISETPEND59,Set pending software interrupt on Cluster 0 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 26. "SGPPISETPEND58,Set pending software interrupt on Cluster 0 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 25. "SGPPISETPEND57,Set pending software interrupt on Cluster 0 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 24. "SGPPISETPEND56,Set pending software interrupt on Cluster 0 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 23. "SGPPISETPEND55,Set pending software interrupt on Cluster 0 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 22. "SGPPISETPEND54,Set pending software interrupt on Cluster 0 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 21. "SGPPISETPEND53,Set pending software interrupt on Cluster 0 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 20. "SGPPISETPEND52,Set pending software interrupt on Cluster 0 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 19. "SGPPISETPEND51,Set pending software interrupt on Cluster 0 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 18. "SGPPISETPEND50,Set pending software interrupt on Cluster 0 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 17. "SGPPISETPEND49,Set pending software interrupt on Cluster 0 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 16. "SGPPISETPEND48,Set pending software interrupt on Cluster 0 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 15. "SGPPISETPEND47,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 14. "SGPPISETPEND46,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 13. "SGPPISETPEND45,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 12. "SGPPISETPEND44,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 11. "SGPPISETPEND43,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 10. "SGPPISETPEND42,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 9. "SGPPISETPEND41,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 8. "SGPPISETPEND40,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 7. "SGPPISETPEND39,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 6. "SGPPISETPEND38,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 5. "SGPPISETPEND37,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 4. "SGPPISETPEND36,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 3. "SGPPISETPEND35,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 2. "SGPPISETPEND34,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 1. "SGPPISETPEND33,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 0. "SGPPISETPEND32,Set pending software interrupt on Cluster 0 Core 0 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" line.long 0x10 "SGPPICLRPEND31_0_CL0C0," bitfld.long 0x10 31. "SGPPICLRPEND31,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 30. "SGPPICLRPEND30,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 29. "SGPPICLRPEND29,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 28. "SGPPICLRPEND28,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 27. "SGPPICLRPEND27,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 26. "SGPPICLRPEND26,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 25. "SGPPICLRPEND25,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 24. "SGPPICLRPEND24,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 23. "SGPPICLRPEND23,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 22. "SGPPICLRPEND22,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 21. "SGPPICLRPEND21,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 20. "SGPPICLRPEND20,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 19. "SGPPICLRPEND19,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 18. "SGPPICLRPEND18,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 17. "SGPPICLRPEND17,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 16. "SGPPICLRPEND16,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" line.long 0x14 "SGPPICLRPEND63_32_CL0C0," bitfld.long 0x14 31. "SGPPICLRPEND63,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 30. "SGPPICLRPEND62,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 29. "SGPPICLRPEND61,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 28. "SGPPICLRPEND60,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 27. "SGPPICLRPEND59,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 26. "SGPPICLRPEND58,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 25. "SGPPICLRPEND57,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 24. "SGPPICLRPEND56,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 23. "SGPPICLRPEND55,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 22. "SGPPICLRPEND54,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 21. "SGPPICLRPEND53,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 20. "SGPPICLRPEND52,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 19. "SGPPICLRPEND51,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 18. "SGPPICLRPEND50,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 17. "SGPPICLRPEND49,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 16. "SGPPICLRPEND48,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 15. "SGPPICLRPEND47,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 14. "SGPPICLRPEND46,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 13. "SGPPICLRPEND45,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 12. "SGPPICLRPEND44,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 11. "SGPPICLRPEND43,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 10. "SGPPICLRPEND42,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 9. "SGPPICLRPEND41,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 8. "SGPPICLRPEND40,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 7. "SGPPICLRPEND39,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 6. "SGPPICLRPEND38,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 5. "SGPPICLRPEND37,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 4. "SGPPICLRPEND36,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 3. "SGPPICLRPEND35,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 2. "SGPPICLRPEND34,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 1. "SGPPICLRPEND33,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 0. "SGPPICLRPEND32,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" line.long 0x18 "SGPPIENABLE31_0_CL0C0," bitfld.long 0x18 31. "SGPPIEN31,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x18 30. "SGPPIEN30,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x18 29. "SGPPIEN29,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x18 28. "SGPPIEN28,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x18 27. "SGPPIEN27,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x18 26. "SGPPIEN26,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x18 25. "SGPPIEN25,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x18 24. "SGPPIEN24,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x18 23. "SGPPIEN23,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x18 22. "SGPPIEN22,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x18 21. "SGPPIEN21,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x18 20. "SGPPIEN20,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x18 19. "SGPPIEN19,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x18 18. "SGPPIEN18,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x18 17. "SGPPIEN17,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x18 16. "SGPPIEN16,Enable SW PPI on Cluster0 Core0." "0,1" line.long 0x1C "SGPPIENABLE63_32_CL0C0," bitfld.long 0x1C 31. "SGPPIEN63,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x1C 30. "SGPPIEN62,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x1C 29. "SGPPIEN61,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x1C 28. "SGPPIEN60,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x1C 27. "SGPPIEN59,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x1C 26. "SGPPIEN58,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x1C 25. "SGPPIEN57,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x1C 24. "SGPPIEN56,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x1C 23. "SGPPIEN55,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x1C 22. "SGPPIEN54,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x1C 21. "SGPPIEN53,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x1C 20. "SGPPIEN52,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x1C 19. "SGPPIEN51,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x1C 18. "SGPPIEN50,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x1C 17. "SGPPIEN49,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x1C 16. "SGPPIEN48,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x1C 15. "SGPPIEN47,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x1C 14. "SGPPIEN46,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x1C 13. "SGPPIEN45,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x1C 12. "SGPPIEN44,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x1C 11. "SGPPIEN43,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x1C 10. "SGPPIEN42,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x1C 9. "SGPPIEN41,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x1C 8. "SGPPIEN40,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x1C 7. "SGPPIEN39,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x1C 6. "SGPPIEN38,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x1C 5. "SGPPIEN37,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x1C 4. "SGPPIEN36,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x1C 3. "SGPPIEN35,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x1C 2. "SGPPIEN34,Enable SW PPI on Cluster0 Core0." "0,1" newline bitfld.long 0x1C 1. "SGPPIEN33,Enable SW PPI on Cluster0 Core0." "0,1" bitfld.long 0x1C 0. "SGPPIEN32,Enable SW PPI on Cluster0 Core0." "0,1" line.long 0x20 "SGPPISEL0_CL0C0," hexmask.long.byte 0x20 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x24 "SGPPISEL1_CL0C0," hexmask.long.byte 0x24 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x28 "SGPPISEL2_CL0C0," hexmask.long.byte 0x28 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x2C "SGPPISEL3_CL0C0," hexmask.long.byte 0x2C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x30 "SGPPISEL4_CL0C0," hexmask.long.byte 0x30 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x34 "SGPPISEL5_CL0C0," hexmask.long.byte 0x34 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x38 "SGPPISEL6_CL0C0," hexmask.long.byte 0x38 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x3C "SGPPISEL7_CL0C0," hexmask.long.byte 0x3C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x40 "SGPPISEL8_CL0C0," hexmask.long.byte 0x40 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x44 "SGPPISEL9_CL0C0," hexmask.long.byte 0x44 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x48 "SGPPISEL10_CL0C0," hexmask.long.byte 0x48 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x4C "SGPPISEL11_CL0C0," hexmask.long.byte 0x4C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x50 "SGPPISEL12_CL0C0," hexmask.long.byte 0x50 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x54 "SGPPISEL13_CL0C0," hexmask.long.byte 0x54 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x58 "SGPPISEL14_CL0C0," hexmask.long.byte 0x58 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x5C "SGPPISEL15_CL0C0," hexmask.long.byte 0x5C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x60 "SGPPISEL16_CL0C0," hexmask.long.byte 0x60 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x64 "SGPPISEL17_CL0C0," hexmask.long.byte 0x64 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x68 "SGPPISEL18_CL0C0," hexmask.long.byte 0x68 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x6C "SGPPISEL19_CL0C0," hexmask.long.byte 0x6C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x70 "SGPPISEL20_CL0C0," hexmask.long.byte 0x70 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x74 "SGPPISEL21_CL0C0," hexmask.long.byte 0x74 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x78 "SGPPISEL22_CL0C0," hexmask.long.byte 0x78 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x7C "SGPPISEL23_CL0C0," hexmask.long.byte 0x7C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x80 "SGPPISEL24_CL0C0," hexmask.long.byte 0x80 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x84 "SGPPISEL25_CL0C0," hexmask.long.byte 0x84 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x88 "SGPPISEL26_CL0C0," hexmask.long.byte 0x88 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x8C "SGPPISEL27_CL0C0," hexmask.long.byte 0x8C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x90 "SGPPISEL28_CL0C0," hexmask.long.byte 0x90 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x94 "SGPPISEL29_CL0C0," hexmask.long.byte 0x94 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x98 "SGPPISEL30_CL0C0," hexmask.long.byte 0x98 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x9C "SGPPISEL31_CL0C0," hexmask.long.byte 0x9C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xA0 "SGPPISEL32_CL0C0," hexmask.long.byte 0xA0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xA4 "SGPPISEL33_CL0C0," hexmask.long.byte 0xA4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xA8 "SGPPISEL34_CL0C0," hexmask.long.byte 0xA8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xAC "SGPPISEL35_CL0C0," hexmask.long.byte 0xAC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xB0 "SGPPISEL36_CL0C0," hexmask.long.byte 0xB0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xB4 "SGPPISEL37_CL0C0," hexmask.long.byte 0xB4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xB8 "SGPPISEL38_CL0C0," hexmask.long.byte 0xB8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xBC "SGPPISEL39_CL0C0," hexmask.long.byte 0xBC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xC0 "SGPPISEL40_CL0C0," hexmask.long.byte 0xC0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xC4 "SGPPISEL41_CL0C0," hexmask.long.byte 0xC4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xC8 "SGPPISEL42_CL0C0," hexmask.long.byte 0xC8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xCC "SGPPISEL43_CL0C0," hexmask.long.byte 0xCC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xD0 "SGPPISEL44_CL0C0," hexmask.long.byte 0xD0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xD4 "SGPPISEL45_CL0C0," hexmask.long.byte 0xD4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xD8 "SGPPISEL46_CL0C0," hexmask.long.byte 0xD8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xDC "SGPPISEL47_CL0C0," hexmask.long.byte 0xDC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xE0 "SGPPICFG0_CL0C0," bitfld.long 0xE0 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xE4 "SGPPICFG1_CL0C0," bitfld.long 0xE4 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xE8 "SGPPICFG2_CL0C0," bitfld.long 0xE8 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xEC "SGPPICFG3_CL0C0," bitfld.long 0xEC 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xF0 "SGPPICFG4_CL0C0," bitfld.long 0xF0 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xF4 "SGPPICFG5_CL0C0," bitfld.long 0xF4 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" tree.end tree "CORE_DME_SIG" base ad:0xE0043000 group.long 0x0++0x1F line.long 0x0 "SGSPIREQ31_0_DME_CORE," bitfld.long 0x0 31. "SGSPIREQ31,DME Core triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 30. "SGSPIREQ30,DME Core triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 29. "SGSPIREQ29,DME Core triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 28. "SGSPIREQ28,DME Core triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 27. "SGSPIREQ27,DME Core triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 26. "SGSPIREQ26,DME Core triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 25. "SGSPIREQ25,DME Core triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 24. "SGSPIREQ24,DME Core triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 23. "SGSPIREQ23,DME Core triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 22. "SGSPIREQ22,DME Core triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 21. "SGSPIREQ21,DME Core triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 20. "SGSPIREQ20,DME Core triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 19. "SGSPIREQ19,DME Core triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 18. "SGSPIREQ18,DME Core triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 17. "SGSPIREQ17,DME Core triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 16. "SGSPIREQ16,DME Core triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 15. "SGSPIREQ15,DME Core triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 14. "SGSPIREQ14,DME Core triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 13. "SGSPIREQ13,DME Core triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 12. "SGSPIREQ12,DME Core triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 11. "SGSPIREQ11,DME Core triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 10. "SGSPIREQ10,DME Core triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 9. "SGSPIREQ9,DME Core triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 8. "SGSPIREQ8,DME Core triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 7. "SGSPIREQ7,DME Core triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 6. "SGSPIREQ6,DME Core triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 5. "SGSPIREQ5,DME Core triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 4. "SGSPIREQ4,DME Core triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 3. "SGSPIREQ3,DME Core triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 2. "SGSPIREQ2,DME Core triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 1. "SGSPIREQ1,DME Core triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 0. "SGSPIREQ0,DME Core triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" line.long 0x4 "SGSPIREQ63_32_DME_CORE," bitfld.long 0x4 27. "SGSPIREQ59,DME Core triggers interrupt to DSPH Core (cleared by hardware)" "0,1" bitfld.long 0x4 26. "SGSPIREQ58,DME Core triggers interrupt to DSPH Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 25. "SGSPIREQ57,DME Core triggers interrupt to DSPH Core (cleared by hardware)" "0,1" bitfld.long 0x4 24. "SGSPIREQ56,DME Core triggers interrupt to DSPH Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 15. "SGSPIREQ47,DME Core triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 14. "SGSPIREQ46,DME Core triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 13. "SGSPIREQ45,DME Core triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 12. "SGSPIREQ44,DME Core triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 11. "SGSPIREQ43,DME Core triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 10. "SGSPIREQ42,DME Core triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 9. "SGSPIREQ41,DME Core triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 8. "SGSPIREQ40,DME Core triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 7. "SGSPIREQ39,DME Core triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 6. "SGSPIREQ38,DME Core triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x4 5. "SGSPIREQ37,DME Core triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 4. "SGSPIREQ36,DME Core triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x4 3. "SGSPIREQ35,DME Core triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 2. "SGSPIREQ34,DME Core triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x4 1. "SGSPIREQ33,DME Core triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 0. "SGSPIREQ32,DME Core triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" line.long 0x8 "SGSPISETPEND31_0_DME_CORE," bitfld.long 0x8 27. "SGSPISETPEND27,Set pending software interrupt on DME Core triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 26. "SGSPISETPEND26,Set pending software interrupt on DME Core triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 25. "SGSPISETPEND25,Set pending software interrupt on DME Core triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 24. "SGSPISETPEND24,Set pending software interrupt on DME Core triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 19. "SGSPISETPEND19,Set pending software interrupt on DME Core triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 18. "SGSPISETPEND18,Set pending software interrupt on DME Core triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 17. "SGSPISETPEND17,Set pending software interrupt on DME Core triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 16. "SGSPISETPEND16,Set pending software interrupt on DME Core triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 11. "SGSPISETPEND11,Set pending software interrupt on DME Core triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 10. "SGSPISETPEND10,Set pending software interrupt on DME Core triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 9. "SGSPISETPEND9,Set pending software interrupt on DME Core triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 8. "SGSPISETPEND8,Set pending software interrupt on DME Core triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 3. "SGSPISETPEND3,Set pending software interrupt on DME Core triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 2. "SGSPISETPEND2,Set pending software interrupt on DME Core triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 1. "SGSPISETPEND1,Set pending software interrupt on DME Core triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 0. "SGSPISETPEND0,Set pending software interrupt on DME Core triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" line.long 0xC "SGSPISETPEND63_32_DME_CORE," bitfld.long 0xC 27. "SGSPISETPEND59,Set pending software interrupt on DME Core triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 26. "SGSPISETPEND58,Set pending software interrupt on DME Core triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 25. "SGSPISETPEND57,Set pending software interrupt on DME Core triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 24. "SGSPISETPEND56,Set pending software interrupt on DME Core triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 11. "SGSPISETPEND43,Set pending software interrupt on DME Core triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 10. "SGSPISETPEND42,Set pending software interrupt on DME Core triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 9. "SGSPISETPEND41,Set pending software interrupt on DME Core triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 8. "SGSPISETPEND40,Set pending software interrupt on DME Core triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 3. "SGSPISETPEND35,Set pending software interrupt on DME Core triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 2. "SGSPISETPEND34,Set pending software interrupt on DME Core triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 1. "SGSPISETPEND33,Set pending software interrupt on DME Core triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 0. "SGSPISETPEND32,Set pending software interrupt on DME Core triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" line.long 0x10 "SGSPICLRPEND31_0_DME_CORE," bitfld.long 0x10 27. "SGSPICLRPEND27,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 26. "SGSPICLRPEND26,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 25. "SGSPICLRPEND25,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 24. "SGSPICLRPEND24,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 19. "SGSPICLRPEND19,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 18. "SGSPICLRPEND18,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 17. "SGSPICLRPEND17,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 16. "SGSPICLRPEND16,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 11. "SGSPICLRPEND11,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 10. "SGSPICLRPEND10,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 9. "SGSPICLRPEND9,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 8. "SGSPICLRPEND8,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 3. "SGSPICLRPEND3,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 2. "SGSPICLRPEND2,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 1. "SGSPICLRPEND1,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 0. "SGSPICLRPEND0,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" line.long 0x14 "SGSPICLRPEND63_32_DME_CORE," bitfld.long 0x14 27. "SGSPICLRPEND59,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 26. "SGSPICLRPEND58,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 25. "SGSPICLRPEND57,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 24. "SGSPICLRPEND56,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 11. "SGSPICLRPEND43,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 10. "SGSPICLRPEND42,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 9. "SGSPICLRPEND41,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 8. "SGSPICLRPEND40,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 3. "SGSPICLRPEND35,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 2. "SGSPICLRPEND34,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 1. "SGSPICLRPEND33,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 0. "SGSPICLRPEND32,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" line.long 0x18 "SGSPIENABLE31_0_DME_CORE," bitfld.long 0x18 27. "SGSPIEN27,Enable SW SPI on DME." "0,1" bitfld.long 0x18 26. "SGSPIEN26,Enable SW SPI on DME." "0,1" newline bitfld.long 0x18 25. "SGSPIEN25,Enable SW SPI on DME." "0,1" bitfld.long 0x18 24. "SGSPIEN24,Enable SW SPI on DME." "0,1" newline bitfld.long 0x18 19. "SGSPIEN19,Enable SW SPI on DME." "0,1" bitfld.long 0x18 18. "SGSPIEN18,Enable SW SPI on DME." "0,1" newline bitfld.long 0x18 17. "SGSPIEN17,Enable SW SPI on DME." "0,1" bitfld.long 0x18 16. "SGSPIEN16,Enable SW SPI on DME." "0,1" newline bitfld.long 0x18 11. "SGSPIEN11,Enable SW SPI on DME." "0,1" bitfld.long 0x18 10. "SGSPIEN10,Enable SW SPI on DME." "0,1" newline bitfld.long 0x18 9. "SGSPIEN9,Enable SW SPI on DME." "0,1" bitfld.long 0x18 8. "SGSPIEN8,Enable SW SPI on DME." "0,1" newline bitfld.long 0x18 3. "SGSPIEN3,Enable SW SPI on DME." "0,1" bitfld.long 0x18 2. "SGSPIEN2,Enable SW SPI on DME." "0,1" newline bitfld.long 0x18 1. "SGSPIEN1,Enable SW SPI on DME." "0,1" bitfld.long 0x18 0. "SGSPIEN0,Enable SW SPI on DME." "0,1" line.long 0x1C "SGSPIENABLE63_32_DME_CORE," bitfld.long 0x1C 27. "SGSPIEN59,Enable SW SPI on DME." "0,1" bitfld.long 0x1C 26. "SGSPIEN58,Enable SW SPI on DME." "0,1" newline bitfld.long 0x1C 25. "SGSPIEN57,Enable SW SPI on DME." "0,1" bitfld.long 0x1C 24. "SGSPIEN56,Enable SW SPI on DME." "0,1" newline bitfld.long 0x1C 11. "SGSPIEN43,Enable SW SPI on DME." "0,1" bitfld.long 0x1C 10. "SGSPIEN42,Enable SW SPI on DME." "0,1" newline bitfld.long 0x1C 9. "SGSPIEN41,Enable SW SPI on DME." "0,1" bitfld.long 0x1C 8. "SGSPIEN40,Enable SW SPI on DME." "0,1" newline bitfld.long 0x1C 3. "SGSPIEN35,Enable SW SPI on DME." "0,1" bitfld.long 0x1C 2. "SGSPIEN34,Enable SW SPI on DME." "0,1" newline bitfld.long 0x1C 1. "SGSPIEN33,Enable SW SPI on DME." "0,1" bitfld.long 0x1C 0. "SGSPIEN32,Enable SW SPI on DME." "0,1" tree.end tree "CORE_DSPH_SIG" base ad:0xE0043000 group.long 0x0++0x1F line.long 0x0 "SGSPIREQ31_0_DSPH_CORE," bitfld.long 0x0 31. "SGSPIREQ31,DSPH Core triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 30. "SGSPIREQ30,DSPH Core triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 29. "SGSPIREQ29,DSPH Core triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 28. "SGSPIREQ28,DSPH Core triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 27. "SGSPIREQ27,DSPH Core triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 26. "SGSPIREQ26,DSPH Core triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 25. "SGSPIREQ25,DSPH Core triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 24. "SGSPIREQ24,DSPH Core triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 23. "SGSPIREQ23,DSPH Core triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 22. "SGSPIREQ22,DSPH Core triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 21. "SGSPIREQ21,DSPH Core triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 20. "SGSPIREQ20,DSPH Core triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 19. "SGSPIREQ19,DSPH Core triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 18. "SGSPIREQ18,DSPH Core triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 17. "SGSPIREQ17,DSPH Core triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 16. "SGSPIREQ16,DSPH Core triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 15. "SGSPIREQ15,DSPH Core triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 14. "SGSPIREQ14,DSPH Core triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 13. "SGSPIREQ13,DSPH Core triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 12. "SGSPIREQ12,DSPH Core triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 11. "SGSPIREQ11,DSPH Core triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 10. "SGSPIREQ10,DSPH Core triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 9. "SGSPIREQ9,DSPH Core triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 8. "SGSPIREQ8,DSPH Core triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 7. "SGSPIREQ7,DSPH Core triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 6. "SGSPIREQ6,DSPH Core triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 5. "SGSPIREQ5,DSPH Core triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 4. "SGSPIREQ4,DSPH Core triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 3. "SGSPIREQ3,DSPH Core triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 2. "SGSPIREQ2,DSPH Core triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 1. "SGSPIREQ1,DSPH Core triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 0. "SGSPIREQ0,DSPH Core triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" line.long 0x4 "SGSPIREQ63_32_DSPH_CORE," bitfld.long 0x4 19. "SGSPIREQ51,DSPH Core triggers interrupt to DME Core (cleared by hardware)" "0,1" bitfld.long 0x4 18. "SGSPIREQ50,DSPH Core triggers interrupt to DME Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 17. "SGSPIREQ49,DSPH Core triggers interrupt to DME Core (cleared by hardware)" "0,1" bitfld.long 0x4 16. "SGSPIREQ48,DSPH Core triggers interrupt to DME Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 15. "SGSPIREQ47,DSPH Core triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 14. "SGSPIREQ46,DSPH Core triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 13. "SGSPIREQ45,DSPH Core triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 12. "SGSPIREQ44,DSPH Core triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 11. "SGSPIREQ43,DSPH Core triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 10. "SGSPIREQ42,DSPH Core triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 9. "SGSPIREQ41,DSPH Core triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 8. "SGSPIREQ40,DSPH Core triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 7. "SGSPIREQ39,DSPH Core triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 6. "SGSPIREQ38,DSPH Core triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x4 5. "SGSPIREQ37,DSPH Core triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 4. "SGSPIREQ36,DSPH Core triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x4 3. "SGSPIREQ35,DSPH Core triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 2. "SGSPIREQ34,DSPH Core triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x4 1. "SGSPIREQ33,DSPH Core triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 0. "SGSPIREQ32,DSPH Core triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" line.long 0x8 "SGSPISETPEND31_0_DSPH_CORE," bitfld.long 0x8 27. "SGSPISETPEND27,Set pending software interrupt on DSPH Core triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 26. "SGSPISETPEND26,Set pending software interrupt on DSPH Core triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 25. "SGSPISETPEND25,Set pending software interrupt on DSPH Core triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 24. "SGSPISETPEND24,Set pending software interrupt on DSPH Core triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 19. "SGSPISETPEND19,Set pending software interrupt on DSPH Core triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 18. "SGSPISETPEND18,Set pending software interrupt on DSPH Core triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 17. "SGSPISETPEND17,Set pending software interrupt on DSPH Core triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 16. "SGSPISETPEND16,Set pending software interrupt on DSPH Core triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 11. "SGSPISETPEND11,Set pending software interrupt on DSPH Core triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 10. "SGSPISETPEND10,Set pending software interrupt on DSPH Core triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 9. "SGSPISETPEND9,Set pending software interrupt on DSPH Core triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 8. "SGSPISETPEND8,Set pending software interrupt on DSPH Core triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 3. "SGSPISETPEND3,Set pending software interrupt on DSPH Core triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 2. "SGSPISETPEND2,Set pending software interrupt on DSPH Core triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 1. "SGSPISETPEND1,Set pending software interrupt on DSPH Core triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 0. "SGSPISETPEND0,Set pending software interrupt on DSPH Core triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" line.long 0xC "SGSPISETPEND63_32_DSPH_CORE," bitfld.long 0xC 19. "SGSPISETPEND51,Set pending software interrupt on DSPH Core triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 18. "SGSPISETPEND50,Set pending software interrupt on DSPH Core triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 17. "SGSPISETPEND49,Set pending software interrupt on DSPH Core triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 16. "SGSPISETPEND48,Set pending software interrupt on DSPH Core triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 11. "SGSPISETPEND43,Set pending software interrupt on DSPH Core triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 10. "SGSPISETPEND42,Set pending software interrupt on DSPH Core triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 9. "SGSPISETPEND41,Set pending software interrupt on DSPH Core triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 8. "SGSPISETPEND40,Set pending software interrupt on DSPH Core triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 3. "SGSPISETPEND35,Set pending software interrupt on DSPH Core triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 2. "SGSPISETPEND34,Set pending software interrupt on DSPH Core triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 1. "SGSPISETPEND33,Set pending software interrupt on DSPH Core triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 0. "SGSPISETPEND32,Set pending software interrupt on DSPH Core triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" line.long 0x10 "SGSPICLRPEND31_0_DSPH_CORE," bitfld.long 0x10 27. "SGSPICLRPEND27,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 26. "SGSPICLRPEND26,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 25. "SGSPICLRPEND25,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 24. "SGSPICLRPEND24,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 19. "SGSPICLRPEND19,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 18. "SGSPICLRPEND18,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 17. "SGSPICLRPEND17,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 16. "SGSPICLRPEND16,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 11. "SGSPICLRPEND11,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 10. "SGSPICLRPEND10,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 9. "SGSPICLRPEND9,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 8. "SGSPICLRPEND8,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 3. "SGSPICLRPEND3,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 2. "SGSPICLRPEND2,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 1. "SGSPICLRPEND1,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 0. "SGSPICLRPEND0,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" line.long 0x14 "SGSPICLRPEND63_32_DSPH_CORE," bitfld.long 0x14 19. "SGSPICLRPEND51,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 18. "SGSPICLRPEND50,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 17. "SGSPICLRPEND49,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 16. "SGSPICLRPEND48,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 11. "SGSPICLRPEND43,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 10. "SGSPICLRPEND42,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 9. "SGSPICLRPEND41,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 8. "SGSPICLRPEND40,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 3. "SGSPICLRPEND35,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 2. "SGSPICLRPEND34,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 1. "SGSPICLRPEND33,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 0. "SGSPICLRPEND32,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" line.long 0x18 "SGSPIENABLE31_0_DSPH_CORE," bitfld.long 0x18 27. "SGSPIEN27,Enable SW SPI on DSPH." "0,1" bitfld.long 0x18 26. "SGSPIEN26,Enable SW SPI on DSPH." "0,1" newline bitfld.long 0x18 25. "SGSPIEN25,Enable SW SPI on DSPH." "0,1" bitfld.long 0x18 24. "SGSPIEN24,Enable SW SPI on DSPH." "0,1" newline bitfld.long 0x18 19. "SGSPIEN19,Enable SW SPI on DSPH." "0,1" bitfld.long 0x18 18. "SGSPIEN18,Enable SW SPI on DSPH." "0,1" newline bitfld.long 0x18 17. "SGSPIEN17,Enable SW SPI on DSPH." "0,1" bitfld.long 0x18 16. "SGSPIEN16,Enable SW SPI on DSPH." "0,1" newline bitfld.long 0x18 11. "SGSPIEN11,Enable SW SPI on DSPH." "0,1" bitfld.long 0x18 10. "SGSPIEN10,Enable SW SPI on DSPH." "0,1" newline bitfld.long 0x18 9. "SGSPIEN9,Enable SW SPI on DSPH." "0,1" bitfld.long 0x18 8. "SGSPIEN8,Enable SW SPI on DSPH." "0,1" newline bitfld.long 0x18 3. "SGSPIEN3,Enable SW SPI on DSPH." "0,1" bitfld.long 0x18 2. "SGSPIEN2,Enable SW SPI on DSPH." "0,1" newline bitfld.long 0x18 1. "SGSPIEN1,Enable SW SPI on DSPH." "0,1" bitfld.long 0x18 0. "SGSPIEN0,Enable SW SPI on DSPH." "0,1" line.long 0x1C "SGSPIENABLE63_32_DSPH_CORE," bitfld.long 0x1C 19. "SGSPIEN51,Enable SW SPI on DSPH." "0,1" bitfld.long 0x1C 18. "SGSPIEN50,Enable SW SPI on DSPH." "0,1" newline bitfld.long 0x1C 17. "SGSPIEN49,Enable SW SPI on DSPH." "0,1" bitfld.long 0x1C 16. "SGSPIEN48,Enable SW SPI on DSPH." "0,1" newline bitfld.long 0x1C 11. "SGSPIEN43,Enable SW SPI on DSPH." "0,1" bitfld.long 0x1C 10. "SGSPIEN42,Enable SW SPI on DSPH." "0,1" newline bitfld.long 0x1C 9. "SGSPIEN41,Enable SW SPI on DSPH." "0,1" bitfld.long 0x1C 8. "SGSPIEN40,Enable SW SPI on DSPH." "0,1" newline bitfld.long 0x1C 3. "SGSPIEN35,Enable SW SPI on DSPH." "0,1" bitfld.long 0x1C 2. "SGSPIEN34,Enable SW SPI on DSPH." "0,1" newline bitfld.long 0x1C 1. "SGSPIEN33,Enable SW SPI on DSPH." "0,1" bitfld.long 0x1C 0. "SGSPIEN32,Enable SW SPI on DSPH." "0,1" tree.end tree "IBCM_0" base ad:0x704BC000 group.long 0x0++0x1FF line.long 0x0 "SRCSEL0_DME," hexmask.long.byte 0x0 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x4 "SRCSEL1_DME," hexmask.long.byte 0x4 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x8 "SRCSEL2_DME," hexmask.long.byte 0x8 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xC "SRCSEL3_DME," hexmask.long.byte 0xC 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x10 "SRCSEL4_DME," hexmask.long.byte 0x10 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x14 "SRCSEL5_DME," hexmask.long.byte 0x14 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x18 "SRCSEL6_DME," hexmask.long.byte 0x18 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x1C "SRCSEL7_DME," hexmask.long.byte 0x1C 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x20 "SRCSEL8_DME," hexmask.long.byte 0x20 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x24 "SRCSEL9_DME," hexmask.long.byte 0x24 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x28 "SRCSEL10_DME," hexmask.long.byte 0x28 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x2C "SRCSEL11_DME," hexmask.long.byte 0x2C 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x30 "SRCSEL12_DME," hexmask.long.byte 0x30 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x34 "SRCSEL13_DME," hexmask.long.byte 0x34 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x38 "SRCSEL14_DME," hexmask.long.byte 0x38 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x3C "SRCSEL15_DME," hexmask.long.byte 0x3C 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x40 "SRCSEL16_DME," hexmask.long.byte 0x40 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x44 "SRCSEL17_DME," hexmask.long.byte 0x44 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x48 "SRCSEL18_DME," hexmask.long.byte 0x48 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x4C "SRCSEL19_DME," hexmask.long.byte 0x4C 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x50 "SRCSEL20_DME," hexmask.long.byte 0x50 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x54 "SRCSEL21_DME," hexmask.long.byte 0x54 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x58 "SRCSEL22_DME," hexmask.long.byte 0x58 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x5C "SRCSEL23_DME," hexmask.long.byte 0x5C 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x60 "SRCSEL24_DME," hexmask.long.byte 0x60 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x64 "SRCSEL25_DME," hexmask.long.byte 0x64 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x68 "SRCSEL26_DME," hexmask.long.byte 0x68 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x6C "SRCSEL27_DME," hexmask.long.byte 0x6C 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x70 "SRCSEL28_DME," hexmask.long.byte 0x70 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x74 "SRCSEL29_DME," hexmask.long.byte 0x74 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x78 "SRCSEL30_DME," hexmask.long.byte 0x78 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x7C "SRCSEL31_DME," hexmask.long.byte 0x7C 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x80 "SRCSEL32_DME," hexmask.long.byte 0x80 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x84 "SRCSEL33_DME," hexmask.long.byte 0x84 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x88 "SRCSEL34_DME," hexmask.long.byte 0x88 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x8C "SRCSEL35_DME," hexmask.long.byte 0x8C 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x90 "SRCSEL36_DME," hexmask.long.byte 0x90 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x94 "SRCSEL37_DME," hexmask.long.byte 0x94 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x98 "SRCSEL38_DME," hexmask.long.byte 0x98 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x9C "SRCSEL39_DME," hexmask.long.byte 0x9C 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xA0 "SRCSEL40_DME," hexmask.long.byte 0xA0 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xA4 "SRCSEL41_DME," hexmask.long.byte 0xA4 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xA8 "SRCSEL42_DME," hexmask.long.byte 0xA8 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xAC "SRCSEL43_DME," hexmask.long.byte 0xAC 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xB0 "SRCSEL44_DME," hexmask.long.byte 0xB0 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xB4 "SRCSEL45_DME," hexmask.long.byte 0xB4 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xB8 "SRCSEL46_DME," hexmask.long.byte 0xB8 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xBC "SRCSEL47_DME," hexmask.long.byte 0xBC 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xC0 "SRCSEL48_DME," hexmask.long.byte 0xC0 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xC4 "SRCSEL49_DME," hexmask.long.byte 0xC4 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xC8 "SRCSEL50_DME," hexmask.long.byte 0xC8 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xCC "SRCSEL51_DME," hexmask.long.byte 0xCC 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xD0 "SRCSEL52_DME," hexmask.long.byte 0xD0 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xD4 "SRCSEL53_DME," hexmask.long.byte 0xD4 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xD8 "SRCSEL54_DME," hexmask.long.byte 0xD8 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xDC "SRCSEL55_DME," hexmask.long.byte 0xDC 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xE0 "SRCSEL56_DME," hexmask.long.byte 0xE0 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xE4 "SRCSEL57_DME," hexmask.long.byte 0xE4 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xE8 "SRCSEL58_DME," hexmask.long.byte 0xE8 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xEC "SRCSEL59_DME," hexmask.long.byte 0xEC 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xF0 "SRCSEL60_DME," hexmask.long.byte 0xF0 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xF4 "SRCSEL61_DME," hexmask.long.byte 0xF4 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xF8 "SRCSEL62_DME," hexmask.long.byte 0xF8 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0xFC "SRCSEL63_DME," hexmask.long.byte 0xFC 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DME NVIC interface." line.long 0x100 "SRCSEL0_DSPH," hexmask.long.byte 0x100 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x104 "SRCSEL1_DSPH," hexmask.long.byte 0x104 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x108 "SRCSEL2_DSPH," hexmask.long.byte 0x108 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x10C "SRCSEL3_DSPH," hexmask.long.byte 0x10C 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x110 "SRCSEL4_DSPH," hexmask.long.byte 0x110 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x114 "SRCSEL5_DSPH," hexmask.long.byte 0x114 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x118 "SRCSEL6_DSPH," hexmask.long.byte 0x118 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x11C "SRCSEL7_DSPH," hexmask.long.byte 0x11C 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x120 "SRCSEL8_DSPH," hexmask.long.byte 0x120 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x124 "SRCSEL9_DSPH," hexmask.long.byte 0x124 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x128 "SRCSEL10_DSPH," hexmask.long.byte 0x128 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x12C "SRCSEL11_DSPH," hexmask.long.byte 0x12C 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x130 "SRCSEL12_DSPH," hexmask.long.byte 0x130 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x134 "SRCSEL13_DSPH," hexmask.long.byte 0x134 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x138 "SRCSEL14_DSPH," hexmask.long.byte 0x138 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x13C "SRCSEL15_DSPH," hexmask.long.byte 0x13C 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x140 "SRCSEL16_DSPH," hexmask.long.byte 0x140 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x144 "SRCSEL17_DSPH," hexmask.long.byte 0x144 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x148 "SRCSEL18_DSPH," hexmask.long.byte 0x148 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x14C "SRCSEL19_DSPH," hexmask.long.byte 0x14C 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x150 "SRCSEL20_DSPH," hexmask.long.byte 0x150 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x154 "SRCSEL21_DSPH," hexmask.long.byte 0x154 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x158 "SRCSEL22_DSPH," hexmask.long.byte 0x158 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x15C "SRCSEL23_DSPH," hexmask.long.byte 0x15C 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x160 "SRCSEL24_DSPH," hexmask.long.byte 0x160 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x164 "SRCSEL25_DSPH," hexmask.long.byte 0x164 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x168 "SRCSEL26_DSPH," hexmask.long.byte 0x168 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x16C "SRCSEL27_DSPH," hexmask.long.byte 0x16C 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x170 "SRCSEL28_DSPH," hexmask.long.byte 0x170 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x174 "SRCSEL29_DSPH," hexmask.long.byte 0x174 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x178 "SRCSEL30_DSPH," hexmask.long.byte 0x178 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x17C "SRCSEL31_DSPH," hexmask.long.byte 0x17C 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x180 "SRCSEL32_DSPH," hexmask.long.byte 0x180 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x184 "SRCSEL33_DSPH," hexmask.long.byte 0x184 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x188 "SRCSEL34_DSPH," hexmask.long.byte 0x188 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x18C "SRCSEL35_DSPH," hexmask.long.byte 0x18C 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x190 "SRCSEL36_DSPH," hexmask.long.byte 0x190 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x194 "SRCSEL37_DSPH," hexmask.long.byte 0x194 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x198 "SRCSEL38_DSPH," hexmask.long.byte 0x198 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x19C "SRCSEL39_DSPH," hexmask.long.byte 0x19C 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1A0 "SRCSEL40_DSPH," hexmask.long.byte 0x1A0 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1A4 "SRCSEL41_DSPH," hexmask.long.byte 0x1A4 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1A8 "SRCSEL42_DSPH," hexmask.long.byte 0x1A8 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1AC "SRCSEL43_DSPH," hexmask.long.byte 0x1AC 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1B0 "SRCSEL44_DSPH," hexmask.long.byte 0x1B0 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1B4 "SRCSEL45_DSPH," hexmask.long.byte 0x1B4 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1B8 "SRCSEL46_DSPH," hexmask.long.byte 0x1B8 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1BC "SRCSEL47_DSPH," hexmask.long.byte 0x1BC 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1C0 "SRCSEL48_DSPH," hexmask.long.byte 0x1C0 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1C4 "SRCSEL49_DSPH," hexmask.long.byte 0x1C4 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1C8 "SRCSEL50_DSPH," hexmask.long.byte 0x1C8 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1CC "SRCSEL51_DSPH," hexmask.long.byte 0x1CC 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1D0 "SRCSEL52_DSPH," hexmask.long.byte 0x1D0 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1D4 "SRCSEL53_DSPH," hexmask.long.byte 0x1D4 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1D8 "SRCSEL54_DSPH," hexmask.long.byte 0x1D8 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1DC "SRCSEL55_DSPH," hexmask.long.byte 0x1DC 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1E0 "SRCSEL56_DSPH," hexmask.long.byte 0x1E0 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1E4 "SRCSEL57_DSPH," hexmask.long.byte 0x1E4 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1E8 "SRCSEL58_DSPH," hexmask.long.byte 0x1E8 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1EC "SRCSEL59_DSPH," hexmask.long.byte 0x1EC 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1F0 "SRCSEL60_DSPH," hexmask.long.byte 0x1F0 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1F4 "SRCSEL61_DSPH," hexmask.long.byte 0x1F4 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1F8 "SRCSEL62_DSPH," hexmask.long.byte 0x1F8 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." line.long 0x1FC "SRCSEL63_DSPH," hexmask.long.byte 0x1FC 0.--7. 1. "SRCSEL,One of the 256 interrupts to be routed onto the DSPH NVIC interface." tree.end tree "IBCM_CORE_0_SIG" base ad:0x6C200000 group.long 0x0++0xF7 line.long 0x0 "SGPPIREQ31_0_CL0C1," bitfld.long 0x0 31. "SGPPIREQ31,Cluster 0 Core 1 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 30. "SGPPIREQ30,Cluster 0 Core 1 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 29. "SGPPIREQ29,Cluster 0 Core 1 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 28. "SGPPIREQ28,Cluster 0 Core 1 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 27. "SGPPIREQ27,Cluster 0 Core 1 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 26. "SGPPIREQ26,Cluster 0 Core 1 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 25. "SGPPIREQ25,Cluster 0 Core 1 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 24. "SGPPIREQ24,Cluster 0 Core 1 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 23. "SGPPIREQ23,Cluster 0 Core 1 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 22. "SGPPIREQ22,Cluster 0 Core 1 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 21. "SGPPIREQ21,Cluster 0 Core 1 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 20. "SGPPIREQ20,Cluster 0 Core 1 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 19. "SGPPIREQ19,Cluster 0 Core 1 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 18. "SGPPIREQ18,Cluster 0 Core 1 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 17. "SGPPIREQ17,Cluster 0 Core 1 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 16. "SGPPIREQ16,Cluster 0 Core 1 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" line.long 0x4 "SGPPIREQ63_32_CL0C1," bitfld.long 0x4 27. "SGPPIREQ59,Cluster 0 Core 1 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" bitfld.long 0x4 26. "SGPPIREQ58,Cluster 0 Core 1 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 25. "SGPPIREQ57,Cluster 0 Core 1 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" bitfld.long 0x4 24. "SGPPIREQ56,Cluster 0 Core 1 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 19. "SGPPIREQ51,Cluster 0 Core 1 triggers interrupt to DME Core (cleared by hardware)" "0,1" bitfld.long 0x4 18. "SGPPIREQ50,Cluster 0 Core 1 triggers interrupt to DME Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 17. "SGPPIREQ49,Cluster 0 Core 1 triggers interrupt to DME Core (cleared by hardware)" "0,1" bitfld.long 0x4 16. "SGPPIREQ48,Cluster 0 Core 1 triggers interrupt to DME Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 15. "SGPPIREQ47,Cluster 0 Core 1 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 14. "SGPPIREQ46,Cluster 0 Core 1 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 13. "SGPPIREQ45,Cluster 0 Core 1 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 12. "SGPPIREQ44,Cluster 0 Core 1 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 11. "SGPPIREQ43,Cluster 0 Core 1 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 10. "SGPPIREQ42,Cluster 0 Core 1 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 9. "SGPPIREQ41,Cluster 0 Core 1 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 8. "SGPPIREQ40,Cluster 0 Core 1 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 7. "SGPPIREQ39,Cluster 0 Core 1 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 6. "SGPPIREQ38,Cluster 0 Core 1 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x4 5. "SGPPIREQ37,Cluster 0 Core 1 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 4. "SGPPIREQ36,Cluster 0 Core 1 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x4 3. "SGPPIREQ35,Cluster 0 Core 1 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 2. "SGPPIREQ34,Cluster 0 Core 1 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x4 1. "SGPPIREQ33,Cluster 0 Core 1 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 0. "SGPPIREQ32,Cluster 0 Core 1 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" line.long 0x8 "SGPPISETPEND31_0_CL0C1," bitfld.long 0x8 31. "SGPPISETPEND31,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 30. "SGPPISETPEND30,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 29. "SGPPISETPEND29,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 28. "SGPPISETPEND28,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 27. "SGPPISETPEND27,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 26. "SGPPISETPEND26,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 25. "SGPPISETPEND25,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 24. "SGPPISETPEND24,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 23. "SGPPISETPEND23,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 22. "SGPPISETPEND22,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 21. "SGPPISETPEND21,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 20. "SGPPISETPEND20,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 19. "SGPPISETPEND19,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 18. "SGPPISETPEND18,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 17. "SGPPISETPEND17,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 16. "SGPPISETPEND16,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" line.long 0xC "SGPPISETPEND63_32_CL0C1," bitfld.long 0xC 31. "SGPPISETPEND63,Set pending software interrupt on Cluster 0 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 30. "SGPPISETPEND62,Set pending software interrupt on Cluster 0 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 29. "SGPPISETPEND61,Set pending software interrupt on Cluster 0 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 28. "SGPPISETPEND60,Set pending software interrupt on Cluster 0 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 27. "SGPPISETPEND59,Set pending software interrupt on Cluster 0 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 26. "SGPPISETPEND58,Set pending software interrupt on Cluster 0 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 25. "SGPPISETPEND57,Set pending software interrupt on Cluster 0 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 24. "SGPPISETPEND56,Set pending software interrupt on Cluster 0 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 23. "SGPPISETPEND55,Set pending software interrupt on Cluster 0 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 22. "SGPPISETPEND54,Set pending software interrupt on Cluster 0 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 21. "SGPPISETPEND53,Set pending software interrupt on Cluster 0 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 20. "SGPPISETPEND52,Set pending software interrupt on Cluster 0 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 19. "SGPPISETPEND51,Set pending software interrupt on Cluster 0 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 18. "SGPPISETPEND50,Set pending software interrupt on Cluster 0 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 17. "SGPPISETPEND49,Set pending software interrupt on Cluster 0 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 16. "SGPPISETPEND48,Set pending software interrupt on Cluster 0 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 15. "SGPPISETPEND47,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 14. "SGPPISETPEND46,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 13. "SGPPISETPEND45,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 12. "SGPPISETPEND44,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 11. "SGPPISETPEND43,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 10. "SGPPISETPEND42,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 9. "SGPPISETPEND41,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 8. "SGPPISETPEND40,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 7. "SGPPISETPEND39,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 6. "SGPPISETPEND38,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 5. "SGPPISETPEND37,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 4. "SGPPISETPEND36,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 3. "SGPPISETPEND35,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 2. "SGPPISETPEND34,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 1. "SGPPISETPEND33,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 0. "SGPPISETPEND32,Set pending software interrupt on Cluster 0 Core 1 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" line.long 0x10 "SGPPICLRPEND31_0_CL0C1," bitfld.long 0x10 31. "SGPPICLRPEND31,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 30. "SGPPICLRPEND30,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 29. "SGPPICLRPEND29,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 28. "SGPPICLRPEND28,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 27. "SGPPICLRPEND27,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 26. "SGPPICLRPEND26,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 25. "SGPPICLRPEND25,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 24. "SGPPICLRPEND24,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 23. "SGPPICLRPEND23,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 22. "SGPPICLRPEND22,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 21. "SGPPICLRPEND21,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 20. "SGPPICLRPEND20,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 19. "SGPPICLRPEND19,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 18. "SGPPICLRPEND18,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 17. "SGPPICLRPEND17,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 16. "SGPPICLRPEND16,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" line.long 0x14 "SGPPICLRPEND63_32_CL0C1," bitfld.long 0x14 31. "SGPPICLRPEND63,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 30. "SGPPICLRPEND62,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 29. "SGPPICLRPEND61,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 28. "SGPPICLRPEND60,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 27. "SGPPICLRPEND59,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 26. "SGPPICLRPEND58,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 25. "SGPPICLRPEND57,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 24. "SGPPICLRPEND56,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 23. "SGPPICLRPEND55,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 22. "SGPPICLRPEND54,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 21. "SGPPICLRPEND53,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 20. "SGPPICLRPEND52,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 19. "SGPPICLRPEND51,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 18. "SGPPICLRPEND50,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 17. "SGPPICLRPEND49,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 16. "SGPPICLRPEND48,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 15. "SGPPICLRPEND47,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 14. "SGPPICLRPEND46,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 13. "SGPPICLRPEND45,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 12. "SGPPICLRPEND44,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 11. "SGPPICLRPEND43,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 10. "SGPPICLRPEND42,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 9. "SGPPICLRPEND41,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 8. "SGPPICLRPEND40,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 7. "SGPPICLRPEND39,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 6. "SGPPICLRPEND38,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 5. "SGPPICLRPEND37,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 4. "SGPPICLRPEND36,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 3. "SGPPICLRPEND35,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 2. "SGPPICLRPEND34,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 1. "SGPPICLRPEND33,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 0. "SGPPICLRPEND32,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" line.long 0x18 "SGPPIENABLE31_0_CL0C1," bitfld.long 0x18 31. "SGPPIEN31,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x18 30. "SGPPIEN30,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x18 29. "SGPPIEN29,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x18 28. "SGPPIEN28,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x18 27. "SGPPIEN27,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x18 26. "SGPPIEN26,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x18 25. "SGPPIEN25,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x18 24. "SGPPIEN24,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x18 23. "SGPPIEN23,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x18 22. "SGPPIEN22,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x18 21. "SGPPIEN21,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x18 20. "SGPPIEN20,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x18 19. "SGPPIEN19,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x18 18. "SGPPIEN18,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x18 17. "SGPPIEN17,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x18 16. "SGPPIEN16,Enable SW PPI on Cluster0 Core1." "0,1" line.long 0x1C "SGPPIENABLE63_32_CL0C1," bitfld.long 0x1C 31. "SGPPIEN63,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x1C 30. "SGPPIEN62,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x1C 29. "SGPPIEN61,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x1C 28. "SGPPIEN60,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x1C 27. "SGPPIEN59,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x1C 26. "SGPPIEN58,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x1C 25. "SGPPIEN57,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x1C 24. "SGPPIEN56,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x1C 23. "SGPPIEN55,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x1C 22. "SGPPIEN54,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x1C 21. "SGPPIEN53,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x1C 20. "SGPPIEN52,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x1C 19. "SGPPIEN51,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x1C 18. "SGPPIEN50,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x1C 17. "SGPPIEN49,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x1C 16. "SGPPIEN48,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x1C 15. "SGPPIEN47,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x1C 14. "SGPPIEN46,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x1C 13. "SGPPIEN45,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x1C 12. "SGPPIEN44,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x1C 11. "SGPPIEN43,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x1C 10. "SGPPIEN42,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x1C 9. "SGPPIEN41,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x1C 8. "SGPPIEN40,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x1C 7. "SGPPIEN39,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x1C 6. "SGPPIEN38,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x1C 5. "SGPPIEN37,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x1C 4. "SGPPIEN36,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x1C 3. "SGPPIEN35,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x1C 2. "SGPPIEN34,Enable SW PPI on Cluster0 Core1." "0,1" newline bitfld.long 0x1C 1. "SGPPIEN33,Enable SW PPI on Cluster0 Core1." "0,1" bitfld.long 0x1C 0. "SGPPIEN32,Enable SW PPI on Cluster0 Core1." "0,1" line.long 0x20 "SGPPISEL0_CL0C1," hexmask.long.byte 0x20 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x24 "SGPPISEL1_CL0C1," hexmask.long.byte 0x24 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x28 "SGPPISEL2_CL0C1," hexmask.long.byte 0x28 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x2C "SGPPISEL3_CL0C1," hexmask.long.byte 0x2C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x30 "SGPPISEL4_CL0C1," hexmask.long.byte 0x30 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x34 "SGPPISEL5_CL0C1," hexmask.long.byte 0x34 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x38 "SGPPISEL6_CL0C1," hexmask.long.byte 0x38 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x3C "SGPPISEL7_CL0C1," hexmask.long.byte 0x3C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x40 "SGPPISEL8_CL0C1," hexmask.long.byte 0x40 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x44 "SGPPISEL9_CL0C1," hexmask.long.byte 0x44 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x48 "SGPPISEL10_CL0C1," hexmask.long.byte 0x48 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x4C "SGPPISEL11_CL0C1," hexmask.long.byte 0x4C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x50 "SGPPISEL12_CL0C1," hexmask.long.byte 0x50 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x54 "SGPPISEL13_CL0C1," hexmask.long.byte 0x54 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x58 "SGPPISEL14_CL0C1," hexmask.long.byte 0x58 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x5C "SGPPISEL15_CL0C1," hexmask.long.byte 0x5C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x60 "SGPPISEL16_CL0C1," hexmask.long.byte 0x60 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x64 "SGPPISEL17_CL0C1," hexmask.long.byte 0x64 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x68 "SGPPISEL18_CL0C1," hexmask.long.byte 0x68 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x6C "SGPPISEL19_CL0C1," hexmask.long.byte 0x6C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x70 "SGPPISEL20_CL0C1," hexmask.long.byte 0x70 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x74 "SGPPISEL21_CL0C1," hexmask.long.byte 0x74 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x78 "SGPPISEL22_CL0C1," hexmask.long.byte 0x78 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x7C "SGPPISEL23_CL0C1," hexmask.long.byte 0x7C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x80 "SGPPISEL24_CL0C1," hexmask.long.byte 0x80 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x84 "SGPPISEL25_CL0C1," hexmask.long.byte 0x84 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x88 "SGPPISEL26_CL0C1," hexmask.long.byte 0x88 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x8C "SGPPISEL27_CL0C1," hexmask.long.byte 0x8C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x90 "SGPPISEL28_CL0C1," hexmask.long.byte 0x90 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x94 "SGPPISEL29_CL0C1," hexmask.long.byte 0x94 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x98 "SGPPISEL30_CL0C1," hexmask.long.byte 0x98 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x9C "SGPPISEL31_CL0C1," hexmask.long.byte 0x9C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xA0 "SGPPISEL32_CL0C1," hexmask.long.byte 0xA0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xA4 "SGPPISEL33_CL0C1," hexmask.long.byte 0xA4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xA8 "SGPPISEL34_CL0C1," hexmask.long.byte 0xA8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xAC "SGPPISEL35_CL0C1," hexmask.long.byte 0xAC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xB0 "SGPPISEL36_CL0C1," hexmask.long.byte 0xB0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xB4 "SGPPISEL37_CL0C1," hexmask.long.byte 0xB4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xB8 "SGPPISEL38_CL0C1," hexmask.long.byte 0xB8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xBC "SGPPISEL39_CL0C1," hexmask.long.byte 0xBC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xC0 "SGPPISEL40_CL0C1," hexmask.long.byte 0xC0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xC4 "SGPPISEL41_CL0C1," hexmask.long.byte 0xC4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xC8 "SGPPISEL42_CL0C1," hexmask.long.byte 0xC8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xCC "SGPPISEL43_CL0C1," hexmask.long.byte 0xCC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xD0 "SGPPISEL44_CL0C1," hexmask.long.byte 0xD0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xD4 "SGPPISEL45_CL0C1," hexmask.long.byte 0xD4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xD8 "SGPPISEL46_CL0C1," hexmask.long.byte 0xD8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xDC "SGPPISEL47_CL0C1," hexmask.long.byte 0xDC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xE0 "SGPPICFG0_CL0C1," bitfld.long 0xE0 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xE4 "SGPPICFG1_CL0C1," bitfld.long 0xE4 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xE8 "SGPPICFG2_CL0C1," bitfld.long 0xE8 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xEC "SGPPICFG3_CL0C1," bitfld.long 0xEC 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xF0 "SGPPICFG4_CL0C1," bitfld.long 0xF0 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xF4 "SGPPICFG5_CL0C1," bitfld.long 0xF4 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" tree.end tree "IBCM_IBCM_LLPP_CL1C0_CORE_0_SIG" base ad:0x6C200000 group.long 0x0++0xF7 line.long 0x0 "SGPPIREQ31_0_CL1C0," bitfld.long 0x0 15. "SGPPIREQ15,Cluster 1 Core 0 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 14. "SGPPIREQ14,Cluster 1 Core 0 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 13. "SGPPIREQ13,Cluster 1 Core 0 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 12. "SGPPIREQ12,Cluster 1 Core 0 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 11. "SGPPIREQ11,Cluster 1 Core 0 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 10. "SGPPIREQ10,Cluster 1 Core 0 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 9. "SGPPIREQ9,Cluster 1 Core 0 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 8. "SGPPIREQ8,Cluster 1 Core 0 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 7. "SGPPIREQ7,Cluster 1 Core 0 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 6. "SGPPIREQ6,Cluster 1 Core 0 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 5. "SGPPIREQ5,Cluster 1 Core 0 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 4. "SGPPIREQ4,Cluster 1 Core 0 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 3. "SGPPIREQ3,Cluster 1 Core 0 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 2. "SGPPIREQ2,Cluster 1 Core 0 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 1. "SGPPIREQ1,Cluster 1 Core 0 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 0. "SGPPIREQ0,Cluster 1 Core 0 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" line.long 0x4 "SGPPIREQ63_32_CL1C0," bitfld.long 0x4 27. "SGPPIREQ59,Cluster 1 Core 0 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" bitfld.long 0x4 26. "SGPPIREQ58,Cluster 1 Core 0 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 25. "SGPPIREQ57,Cluster 1 Core 0 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" bitfld.long 0x4 24. "SGPPIREQ56,Cluster 1 Core 0 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 19. "SGPPIREQ51,Cluster 1 Core 0 triggers interrupt to DME Core (cleared by hardware)" "0,1" bitfld.long 0x4 18. "SGPPIREQ50,Cluster 1 Core 0 triggers interrupt to DME Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 17. "SGPPIREQ49,Cluster 1 Core 0 triggers interrupt to DME Core (cleared by hardware)" "0,1" bitfld.long 0x4 16. "SGPPIREQ48,Cluster 1 Core 0 triggers interrupt to DME Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 15. "SGPPIREQ47,Cluster 1 Core 0 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 14. "SGPPIREQ46,Cluster 1 Core 0 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 13. "SGPPIREQ45,Cluster 1 Core 0 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 12. "SGPPIREQ44,Cluster 1 Core 0 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 11. "SGPPIREQ43,Cluster 1 Core 0 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 10. "SGPPIREQ42,Cluster 1 Core 0 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 9. "SGPPIREQ41,Cluster 1 Core 0 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 8. "SGPPIREQ40,Cluster 1 Core 0 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 7. "SGPPIREQ39,Cluster 1 Core 0 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 6. "SGPPIREQ38,Cluster 1 Core 0 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x4 5. "SGPPIREQ37,Cluster 1 Core 0 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 4. "SGPPIREQ36,Cluster 1 Core 0 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x4 3. "SGPPIREQ35,Cluster 1 Core 0 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 2. "SGPPIREQ34,Cluster 1 Core 0 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x4 1. "SGPPIREQ33,Cluster 1 Core 0 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 0. "SGPPIREQ32,Cluster 1 Core 0 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" line.long 0x8 "SGPPISETPEND31_0_CL1C0," bitfld.long 0x8 15. "SGPPISETPEND15,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 14. "SGPPISETPEND14,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 13. "SGPPISETPEND13,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 12. "SGPPISETPEND12,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 11. "SGPPISETPEND11,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 10. "SGPPISETPEND10,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 9. "SGPPISETPEND9,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 8. "SGPPISETPEND8,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 7. "SGPPISETPEND7,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 6. "SGPPISETPEND6,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 5. "SGPPISETPEND5,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 4. "SGPPISETPEND4,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 3. "SGPPISETPEND3,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 2. "SGPPISETPEND2,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 1. "SGPPISETPEND1,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 0. "SGPPISETPEND0,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" line.long 0xC "SGPPISETPEND63_32_CL1C0," bitfld.long 0xC 31. "SGPPISETPEND63,Set pending software interrupt on Cluster 1 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 30. "SGPPISETPEND62,Set pending software interrupt on Cluster 1 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 29. "SGPPISETPEND61,Set pending software interrupt on Cluster 1 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 28. "SGPPISETPEND60,Set pending software interrupt on Cluster 1 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 27. "SGPPISETPEND59,Set pending software interrupt on Cluster 1 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 26. "SGPPISETPEND58,Set pending software interrupt on Cluster 1 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 25. "SGPPISETPEND57,Set pending software interrupt on Cluster 1 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 24. "SGPPISETPEND56,Set pending software interrupt on Cluster 1 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 23. "SGPPISETPEND55,Set pending software interrupt on Cluster 1 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 22. "SGPPISETPEND54,Set pending software interrupt on Cluster 1 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 21. "SGPPISETPEND53,Set pending software interrupt on Cluster 1 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 20. "SGPPISETPEND52,Set pending software interrupt on Cluster 1 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 19. "SGPPISETPEND51,Set pending software interrupt on Cluster 1 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 18. "SGPPISETPEND50,Set pending software interrupt on Cluster 1 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 17. "SGPPISETPEND49,Set pending software interrupt on Cluster 1 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 16. "SGPPISETPEND48,Set pending software interrupt on Cluster 1 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 15. "SGPPISETPEND47,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 14. "SGPPISETPEND46,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 13. "SGPPISETPEND45,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 12. "SGPPISETPEND44,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 11. "SGPPISETPEND43,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 10. "SGPPISETPEND42,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 9. "SGPPISETPEND41,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 8. "SGPPISETPEND40,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 7. "SGPPISETPEND39,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 6. "SGPPISETPEND38,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 5. "SGPPISETPEND37,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 4. "SGPPISETPEND36,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 3. "SGPPISETPEND35,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 2. "SGPPISETPEND34,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 1. "SGPPISETPEND33,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 0. "SGPPISETPEND32,Set pending software interrupt on Cluster 1 Core 0 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" line.long 0x10 "SGPPICLRPEND31_0_CL1C0," bitfld.long 0x10 15. "SGPPICLRPEND15,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 14. "SGPPICLRPEND14,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 13. "SGPPICLRPEND13,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 12. "SGPPICLRPEND12,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 11. "SGPPICLRPEND11,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 10. "SGPPICLRPEND10,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 9. "SGPPICLRPEND9,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 8. "SGPPICLRPEND8,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 7. "SGPPICLRPEND7,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 6. "SGPPICLRPEND6,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 5. "SGPPICLRPEND5,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 4. "SGPPICLRPEND4,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 3. "SGPPICLRPEND3,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 2. "SGPPICLRPEND2,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 1. "SGPPICLRPEND1,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 0. "SGPPICLRPEND0,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" line.long 0x14 "SGPPICLRPEND63_32_CL1C0," bitfld.long 0x14 31. "SGPPICLRPEND63,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 30. "SGPPICLRPEND62,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 29. "SGPPICLRPEND61,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 28. "SGPPICLRPEND60,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 27. "SGPPICLRPEND59,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 26. "SGPPICLRPEND58,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 25. "SGPPICLRPEND57,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 24. "SGPPICLRPEND56,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 23. "SGPPICLRPEND55,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 22. "SGPPICLRPEND54,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 21. "SGPPICLRPEND53,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 20. "SGPPICLRPEND52,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 19. "SGPPICLRPEND51,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 18. "SGPPICLRPEND50,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 17. "SGPPICLRPEND49,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 16. "SGPPICLRPEND48,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 15. "SGPPICLRPEND47,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 14. "SGPPICLRPEND46,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 13. "SGPPICLRPEND45,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 12. "SGPPICLRPEND44,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 11. "SGPPICLRPEND43,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 10. "SGPPICLRPEND42,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 9. "SGPPICLRPEND41,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 8. "SGPPICLRPEND40,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 7. "SGPPICLRPEND39,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 6. "SGPPICLRPEND38,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 5. "SGPPICLRPEND37,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 4. "SGPPICLRPEND36,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 3. "SGPPICLRPEND35,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 2. "SGPPICLRPEND34,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 1. "SGPPICLRPEND33,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 0. "SGPPICLRPEND32,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" line.long 0x18 "SGPPIENABLE31_0_CL1C0," bitfld.long 0x18 15. "SGPPIEN15,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x18 14. "SGPPIEN14,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x18 13. "SGPPIEN13,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x18 12. "SGPPIEN12,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x18 11. "SGPPIEN11,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x18 10. "SGPPIEN10,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x18 9. "SGPPIEN9,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x18 8. "SGPPIEN8,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x18 7. "SGPPIEN7,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x18 6. "SGPPIEN6,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x18 5. "SGPPIEN5,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x18 4. "SGPPIEN4,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x18 3. "SGPPIEN3,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x18 2. "SGPPIEN2,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x18 1. "SGPPIEN1,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x18 0. "SGPPIEN0,Enable SW PPI on Cluster1 Core0." "0,1" line.long 0x1C "SGPPIENABLE63_32_CL1C0," bitfld.long 0x1C 31. "SGPPIEN63,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x1C 30. "SGPPIEN62,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x1C 29. "SGPPIEN61,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x1C 28. "SGPPIEN60,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x1C 27. "SGPPIEN59,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x1C 26. "SGPPIEN58,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x1C 25. "SGPPIEN57,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x1C 24. "SGPPIEN56,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x1C 23. "SGPPIEN55,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x1C 22. "SGPPIEN54,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x1C 21. "SGPPIEN53,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x1C 20. "SGPPIEN52,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x1C 19. "SGPPIEN51,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x1C 18. "SGPPIEN50,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x1C 17. "SGPPIEN49,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x1C 16. "SGPPIEN48,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x1C 15. "SGPPIEN47,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x1C 14. "SGPPIEN46,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x1C 13. "SGPPIEN45,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x1C 12. "SGPPIEN44,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x1C 11. "SGPPIEN43,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x1C 10. "SGPPIEN42,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x1C 9. "SGPPIEN41,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x1C 8. "SGPPIEN40,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x1C 7. "SGPPIEN39,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x1C 6. "SGPPIEN38,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x1C 5. "SGPPIEN37,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x1C 4. "SGPPIEN36,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x1C 3. "SGPPIEN35,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x1C 2. "SGPPIEN34,Enable SW PPI on Cluster1 Core0." "0,1" newline bitfld.long 0x1C 1. "SGPPIEN33,Enable SW PPI on Cluster1 Core0." "0,1" bitfld.long 0x1C 0. "SGPPIEN32,Enable SW PPI on Cluster1 Core0." "0,1" line.long 0x20 "SGPPISEL0_CL1C0," hexmask.long.byte 0x20 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x24 "SGPPISEL1_CL1C0," hexmask.long.byte 0x24 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x28 "SGPPISEL2_CL1C0," hexmask.long.byte 0x28 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x2C "SGPPISEL3_CL1C0," hexmask.long.byte 0x2C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x30 "SGPPISEL4_CL1C0," hexmask.long.byte 0x30 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x34 "SGPPISEL5_CL1C0," hexmask.long.byte 0x34 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x38 "SGPPISEL6_CL1C0," hexmask.long.byte 0x38 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x3C "SGPPISEL7_CL1C0," hexmask.long.byte 0x3C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x40 "SGPPISEL8_CL1C0," hexmask.long.byte 0x40 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x44 "SGPPISEL9_CL1C0," hexmask.long.byte 0x44 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x48 "SGPPISEL10_CL1C0," hexmask.long.byte 0x48 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x4C "SGPPISEL11_CL1C0," hexmask.long.byte 0x4C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x50 "SGPPISEL12_CL1C0," hexmask.long.byte 0x50 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x54 "SGPPISEL13_CL1C0," hexmask.long.byte 0x54 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x58 "SGPPISEL14_CL1C0," hexmask.long.byte 0x58 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x5C "SGPPISEL15_CL1C0," hexmask.long.byte 0x5C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x60 "SGPPISEL16_CL1C0," hexmask.long.byte 0x60 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x64 "SGPPISEL17_CL1C0," hexmask.long.byte 0x64 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x68 "SGPPISEL18_CL1C0," hexmask.long.byte 0x68 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x6C "SGPPISEL19_CL1C0," hexmask.long.byte 0x6C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x70 "SGPPISEL20_CL1C0," hexmask.long.byte 0x70 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x74 "SGPPISEL21_CL1C0," hexmask.long.byte 0x74 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x78 "SGPPISEL22_CL1C0," hexmask.long.byte 0x78 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x7C "SGPPISEL23_CL1C0," hexmask.long.byte 0x7C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x80 "SGPPISEL24_CL1C0," hexmask.long.byte 0x80 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x84 "SGPPISEL25_CL1C0," hexmask.long.byte 0x84 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x88 "SGPPISEL26_CL1C0," hexmask.long.byte 0x88 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x8C "SGPPISEL27_CL1C0," hexmask.long.byte 0x8C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x90 "SGPPISEL28_CL1C0," hexmask.long.byte 0x90 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x94 "SGPPISEL29_CL1C0," hexmask.long.byte 0x94 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x98 "SGPPISEL30_CL1C0," hexmask.long.byte 0x98 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x9C "SGPPISEL31_CL1C0," hexmask.long.byte 0x9C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xA0 "SGPPISEL32_CL1C0," hexmask.long.byte 0xA0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xA4 "SGPPISEL33_CL1C0," hexmask.long.byte 0xA4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xA8 "SGPPISEL34_CL1C0," hexmask.long.byte 0xA8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xAC "SGPPISEL35_CL1C0," hexmask.long.byte 0xAC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xB0 "SGPPISEL36_CL1C0," hexmask.long.byte 0xB0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xB4 "SGPPISEL37_CL1C0," hexmask.long.byte 0xB4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xB8 "SGPPISEL38_CL1C0," hexmask.long.byte 0xB8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xBC "SGPPISEL39_CL1C0," hexmask.long.byte 0xBC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xC0 "SGPPISEL40_CL1C0," hexmask.long.byte 0xC0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xC4 "SGPPISEL41_CL1C0," hexmask.long.byte 0xC4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xC8 "SGPPISEL42_CL1C0," hexmask.long.byte 0xC8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xCC "SGPPISEL43_CL1C0," hexmask.long.byte 0xCC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xD0 "SGPPISEL44_CL1C0," hexmask.long.byte 0xD0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xD4 "SGPPISEL45_CL1C0," hexmask.long.byte 0xD4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xD8 "SGPPISEL46_CL1C0," hexmask.long.byte 0xD8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xDC "SGPPISEL47_CL1C0," hexmask.long.byte 0xDC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xE0 "SGPPICFG0_CL1C0," bitfld.long 0xE0 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xE4 "SGPPICFG1_CL1C0," bitfld.long 0xE4 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xE8 "SGPPICFG2_CL1C0," bitfld.long 0xE8 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xEC "SGPPICFG3_CL1C0," bitfld.long 0xEC 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xF0 "SGPPICFG4_CL1C0," bitfld.long 0xF0 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xF4 "SGPPICFG5_CL1C0," bitfld.long 0xF4 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" tree.end tree "IBCM_IBCM_LLPP_CL1C1_CORE_0_SIG" base ad:0x6C200000 group.long 0x0++0xF7 line.long 0x0 "SGPPIREQ31_0_CL1C1," bitfld.long 0x0 15. "SGPPIREQ15,Cluster 1 Core 1 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 14. "SGPPIREQ14,Cluster 1 Core 1 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 13. "SGPPIREQ13,Cluster 1 Core 1 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 12. "SGPPIREQ12,Cluster 1 Core 1 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 11. "SGPPIREQ11,Cluster 1 Core 1 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 10. "SGPPIREQ10,Cluster 1 Core 1 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 9. "SGPPIREQ9,Cluster 1 Core 1 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 8. "SGPPIREQ8,Cluster 1 Core 1 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 7. "SGPPIREQ7,Cluster 1 Core 1 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 6. "SGPPIREQ6,Cluster 1 Core 1 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 5. "SGPPIREQ5,Cluster 1 Core 1 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 4. "SGPPIREQ4,Cluster 1 Core 1 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 3. "SGPPIREQ3,Cluster 1 Core 1 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 2. "SGPPIREQ2,Cluster 1 Core 1 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 1. "SGPPIREQ1,Cluster 1 Core 1 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 0. "SGPPIREQ0,Cluster 1 Core 1 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" line.long 0x4 "SGPPIREQ63_32_CL1C1," bitfld.long 0x4 27. "SGPPIREQ59,Cluster 1 Core 1 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" bitfld.long 0x4 26. "SGPPIREQ58,Cluster 1 Core 1 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 25. "SGPPIREQ57,Cluster 1 Core 1 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" bitfld.long 0x4 24. "SGPPIREQ56,Cluster 1 Core 1 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 19. "SGPPIREQ51,Cluster 1 Core 1 triggers interrupt to DME Core (cleared by hardware)" "0,1" bitfld.long 0x4 18. "SGPPIREQ50,Cluster 1 Core 1 triggers interrupt to DME Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 17. "SGPPIREQ49,Cluster 1 Core 1 triggers interrupt to DME Core (cleared by hardware)" "0,1" bitfld.long 0x4 16. "SGPPIREQ48,Cluster 1 Core 1 triggers interrupt to DME Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 15. "SGPPIREQ47,Cluster 1 Core 1 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 14. "SGPPIREQ46,Cluster 1 Core 1 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 13. "SGPPIREQ45,Cluster 1 Core 1 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 12. "SGPPIREQ44,Cluster 1 Core 1 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 11. "SGPPIREQ43,Cluster 1 Core 1 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 10. "SGPPIREQ42,Cluster 1 Core 1 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 9. "SGPPIREQ41,Cluster 1 Core 1 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x4 8. "SGPPIREQ40,Cluster 1 Core 1 triggers interrupt to Cluster 2 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x4 7. "SGPPIREQ39,Cluster 1 Core 1 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 6. "SGPPIREQ38,Cluster 1 Core 1 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x4 5. "SGPPIREQ37,Cluster 1 Core 1 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 4. "SGPPIREQ36,Cluster 1 Core 1 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x4 3. "SGPPIREQ35,Cluster 1 Core 1 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 2. "SGPPIREQ34,Cluster 1 Core 1 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x4 1. "SGPPIREQ33,Cluster 1 Core 1 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x4 0. "SGPPIREQ32,Cluster 1 Core 1 triggers interrupt to Cluster 2 Core 0 (cleared by hardware)" "0,1" line.long 0x8 "SGPPISETPEND31_0_CL1C1," bitfld.long 0x8 15. "SGPPISETPEND15,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 14. "SGPPISETPEND14,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 13. "SGPPISETPEND13,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 12. "SGPPISETPEND12,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 11. "SGPPISETPEND11,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 10. "SGPPISETPEND10,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 9. "SGPPISETPEND9,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 8. "SGPPISETPEND8,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 7. "SGPPISETPEND7,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 6. "SGPPISETPEND6,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 5. "SGPPISETPEND5,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 4. "SGPPISETPEND4,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 3. "SGPPISETPEND3,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 2. "SGPPISETPEND2,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 1. "SGPPISETPEND1,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 0. "SGPPISETPEND0,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" line.long 0xC "SGPPISETPEND63_32_CL1C1," bitfld.long 0xC 31. "SGPPISETPEND63,Set pending software interrupt on Cluster 1 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 30. "SGPPISETPEND62,Set pending software interrupt on Cluster 1 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 29. "SGPPISETPEND61,Set pending software interrupt on Cluster 1 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 28. "SGPPISETPEND60,Set pending software interrupt on Cluster 1 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 27. "SGPPISETPEND59,Set pending software interrupt on Cluster 1 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 26. "SGPPISETPEND58,Set pending software interrupt on Cluster 1 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 25. "SGPPISETPEND57,Set pending software interrupt on Cluster 1 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 24. "SGPPISETPEND56,Set pending software interrupt on Cluster 1 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 23. "SGPPISETPEND55,Set pending software interrupt on Cluster 1 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 22. "SGPPISETPEND54,Set pending software interrupt on Cluster 1 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 21. "SGPPISETPEND53,Set pending software interrupt on Cluster 1 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 20. "SGPPISETPEND52,Set pending software interrupt on Cluster 1 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 19. "SGPPISETPEND51,Set pending software interrupt on Cluster 1 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 18. "SGPPISETPEND50,Set pending software interrupt on Cluster 1 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 17. "SGPPISETPEND49,Set pending software interrupt on Cluster 1 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 16. "SGPPISETPEND48,Set pending software interrupt on Cluster 1 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 15. "SGPPISETPEND47,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 14. "SGPPISETPEND46,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 13. "SGPPISETPEND45,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 12. "SGPPISETPEND44,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 11. "SGPPISETPEND43,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 10. "SGPPISETPEND42,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 9. "SGPPISETPEND41,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 8. "SGPPISETPEND40,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 2 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 7. "SGPPISETPEND39,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 6. "SGPPISETPEND38,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 5. "SGPPISETPEND37,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 4. "SGPPISETPEND36,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 3. "SGPPISETPEND35,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 2. "SGPPISETPEND34,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 1. "SGPPISETPEND33,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 0. "SGPPISETPEND32,Set pending software interrupt on Cluster 1 Core 1 triggered by Cluster 2 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" line.long 0x10 "SGPPICLRPEND31_0_CL1C1," bitfld.long 0x10 15. "SGPPICLRPEND15,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 14. "SGPPICLRPEND14,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 13. "SGPPICLRPEND13,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 12. "SGPPICLRPEND12,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 11. "SGPPICLRPEND11,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 10. "SGPPICLRPEND10,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 9. "SGPPICLRPEND9,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 8. "SGPPICLRPEND8,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 7. "SGPPICLRPEND7,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 6. "SGPPICLRPEND6,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 5. "SGPPICLRPEND5,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 4. "SGPPICLRPEND4,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 3. "SGPPICLRPEND3,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 2. "SGPPICLRPEND2,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 1. "SGPPICLRPEND1,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 0. "SGPPICLRPEND0,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" line.long 0x14 "SGPPICLRPEND63_32_CL1C1," bitfld.long 0x14 31. "SGPPICLRPEND63,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 30. "SGPPICLRPEND62,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 29. "SGPPICLRPEND61,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 28. "SGPPICLRPEND60,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 27. "SGPPICLRPEND59,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 26. "SGPPICLRPEND58,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 25. "SGPPICLRPEND57,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 24. "SGPPICLRPEND56,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 23. "SGPPICLRPEND55,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 22. "SGPPICLRPEND54,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 21. "SGPPICLRPEND53,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 20. "SGPPICLRPEND52,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 19. "SGPPICLRPEND51,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 18. "SGPPICLRPEND50,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 17. "SGPPICLRPEND49,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 16. "SGPPICLRPEND48,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 15. "SGPPICLRPEND47,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 14. "SGPPICLRPEND46,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 13. "SGPPICLRPEND45,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 12. "SGPPICLRPEND44,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 11. "SGPPICLRPEND43,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 10. "SGPPICLRPEND42,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 9. "SGPPICLRPEND41,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 8. "SGPPICLRPEND40,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 7. "SGPPICLRPEND39,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 6. "SGPPICLRPEND38,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 5. "SGPPICLRPEND37,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 4. "SGPPICLRPEND36,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 3. "SGPPICLRPEND35,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 2. "SGPPICLRPEND34,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 1. "SGPPICLRPEND33,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 0. "SGPPICLRPEND32,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" line.long 0x18 "SGPPIENABLE31_0_CL1C1," bitfld.long 0x18 15. "SGPPIEN15,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x18 14. "SGPPIEN14,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x18 13. "SGPPIEN13,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x18 12. "SGPPIEN12,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x18 11. "SGPPIEN11,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x18 10. "SGPPIEN10,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x18 9. "SGPPIEN9,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x18 8. "SGPPIEN8,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x18 7. "SGPPIEN7,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x18 6. "SGPPIEN6,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x18 5. "SGPPIEN5,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x18 4. "SGPPIEN4,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x18 3. "SGPPIEN3,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x18 2. "SGPPIEN2,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x18 1. "SGPPIEN1,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x18 0. "SGPPIEN0,Enable SW PPI on Cluster1 Core1." "0,1" line.long 0x1C "SGPPIENABLE63_32_CL1C1," bitfld.long 0x1C 31. "SGPPIEN63,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x1C 30. "SGPPIEN62,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x1C 29. "SGPPIEN61,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x1C 28. "SGPPIEN60,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x1C 27. "SGPPIEN59,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x1C 26. "SGPPIEN58,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x1C 25. "SGPPIEN57,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x1C 24. "SGPPIEN56,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x1C 23. "SGPPIEN55,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x1C 22. "SGPPIEN54,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x1C 21. "SGPPIEN53,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x1C 20. "SGPPIEN52,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x1C 19. "SGPPIEN51,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x1C 18. "SGPPIEN50,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x1C 17. "SGPPIEN49,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x1C 16. "SGPPIEN48,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x1C 15. "SGPPIEN47,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x1C 14. "SGPPIEN46,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x1C 13. "SGPPIEN45,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x1C 12. "SGPPIEN44,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x1C 11. "SGPPIEN43,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x1C 10. "SGPPIEN42,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x1C 9. "SGPPIEN41,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x1C 8. "SGPPIEN40,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x1C 7. "SGPPIEN39,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x1C 6. "SGPPIEN38,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x1C 5. "SGPPIEN37,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x1C 4. "SGPPIEN36,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x1C 3. "SGPPIEN35,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x1C 2. "SGPPIEN34,Enable SW PPI on Cluster1 Core1." "0,1" newline bitfld.long 0x1C 1. "SGPPIEN33,Enable SW PPI on Cluster1 Core1." "0,1" bitfld.long 0x1C 0. "SGPPIEN32,Enable SW PPI on Cluster1 Core1." "0,1" line.long 0x20 "SGPPISEL0_CL1C1," hexmask.long.byte 0x20 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x24 "SGPPISEL1_CL1C1," hexmask.long.byte 0x24 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x28 "SGPPISEL2_CL1C1," hexmask.long.byte 0x28 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x2C "SGPPISEL3_CL1C1," hexmask.long.byte 0x2C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x30 "SGPPISEL4_CL1C1," hexmask.long.byte 0x30 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x34 "SGPPISEL5_CL1C1," hexmask.long.byte 0x34 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x38 "SGPPISEL6_CL1C1," hexmask.long.byte 0x38 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x3C "SGPPISEL7_CL1C1," hexmask.long.byte 0x3C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x40 "SGPPISEL8_CL1C1," hexmask.long.byte 0x40 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x44 "SGPPISEL9_CL1C1," hexmask.long.byte 0x44 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x48 "SGPPISEL10_CL1C1," hexmask.long.byte 0x48 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x4C "SGPPISEL11_CL1C1," hexmask.long.byte 0x4C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x50 "SGPPISEL12_CL1C1," hexmask.long.byte 0x50 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x54 "SGPPISEL13_CL1C1," hexmask.long.byte 0x54 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x58 "SGPPISEL14_CL1C1," hexmask.long.byte 0x58 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x5C "SGPPISEL15_CL1C1," hexmask.long.byte 0x5C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x60 "SGPPISEL16_CL1C1," hexmask.long.byte 0x60 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x64 "SGPPISEL17_CL1C1," hexmask.long.byte 0x64 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x68 "SGPPISEL18_CL1C1," hexmask.long.byte 0x68 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x6C "SGPPISEL19_CL1C1," hexmask.long.byte 0x6C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x70 "SGPPISEL20_CL1C1," hexmask.long.byte 0x70 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x74 "SGPPISEL21_CL1C1," hexmask.long.byte 0x74 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x78 "SGPPISEL22_CL1C1," hexmask.long.byte 0x78 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x7C "SGPPISEL23_CL1C1," hexmask.long.byte 0x7C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x80 "SGPPISEL24_CL1C1," hexmask.long.byte 0x80 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x84 "SGPPISEL25_CL1C1," hexmask.long.byte 0x84 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x88 "SGPPISEL26_CL1C1," hexmask.long.byte 0x88 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x8C "SGPPISEL27_CL1C1," hexmask.long.byte 0x8C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x90 "SGPPISEL28_CL1C1," hexmask.long.byte 0x90 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x94 "SGPPISEL29_CL1C1," hexmask.long.byte 0x94 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x98 "SGPPISEL30_CL1C1," hexmask.long.byte 0x98 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x9C "SGPPISEL31_CL1C1," hexmask.long.byte 0x9C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xA0 "SGPPISEL32_CL1C1," hexmask.long.byte 0xA0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xA4 "SGPPISEL33_CL1C1," hexmask.long.byte 0xA4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xA8 "SGPPISEL34_CL1C1," hexmask.long.byte 0xA8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xAC "SGPPISEL35_CL1C1," hexmask.long.byte 0xAC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xB0 "SGPPISEL36_CL1C1," hexmask.long.byte 0xB0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xB4 "SGPPISEL37_CL1C1," hexmask.long.byte 0xB4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xB8 "SGPPISEL38_CL1C1," hexmask.long.byte 0xB8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xBC "SGPPISEL39_CL1C1," hexmask.long.byte 0xBC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xC0 "SGPPISEL40_CL1C1," hexmask.long.byte 0xC0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xC4 "SGPPISEL41_CL1C1," hexmask.long.byte 0xC4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xC8 "SGPPISEL42_CL1C1," hexmask.long.byte 0xC8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xCC "SGPPISEL43_CL1C1," hexmask.long.byte 0xCC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xD0 "SGPPISEL44_CL1C1," hexmask.long.byte 0xD0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xD4 "SGPPISEL45_CL1C1," hexmask.long.byte 0xD4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xD8 "SGPPISEL46_CL1C1," hexmask.long.byte 0xD8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xDC "SGPPISEL47_CL1C1," hexmask.long.byte 0xDC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xE0 "SGPPICFG0_CL1C1," bitfld.long 0xE0 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xE4 "SGPPICFG1_CL1C1," bitfld.long 0xE4 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xE8 "SGPPICFG2_CL1C1," bitfld.long 0xE8 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xEC "SGPPICFG3_CL1C1," bitfld.long 0xEC 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xF0 "SGPPICFG4_CL1C1," bitfld.long 0xF0 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xF4 "SGPPICFG5_CL1C1," bitfld.long 0xF4 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" tree.end tree "IBCM_IBCM_LLPP_CL2C0_CORE_0_SIG" base ad:0x6C200000 group.long 0x0++0xF7 line.long 0x0 "SGPPIREQ31_0_CL2C0," bitfld.long 0x0 31. "SGPPIREQ31,Cluster 2 Core 0 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 30. "SGPPIREQ30,Cluster 2 Core 0 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 29. "SGPPIREQ29,Cluster 2 Core 0 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 28. "SGPPIREQ28,Cluster 2 Core 0 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 27. "SGPPIREQ27,Cluster 2 Core 0 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 26. "SGPPIREQ26,Cluster 2 Core 0 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 25. "SGPPIREQ25,Cluster 2 Core 0 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 24. "SGPPIREQ24,Cluster 2 Core 0 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 23. "SGPPIREQ23,Cluster 2 Core 0 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 22. "SGPPIREQ22,Cluster 2 Core 0 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 21. "SGPPIREQ21,Cluster 2 Core 0 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 20. "SGPPIREQ20,Cluster 2 Core 0 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 19. "SGPPIREQ19,Cluster 2 Core 0 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 18. "SGPPIREQ18,Cluster 2 Core 0 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 17. "SGPPIREQ17,Cluster 2 Core 0 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 16. "SGPPIREQ16,Cluster 2 Core 0 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 15. "SGPPIREQ15,Cluster 2 Core 0 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 14. "SGPPIREQ14,Cluster 2 Core 0 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 13. "SGPPIREQ13,Cluster 2 Core 0 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 12. "SGPPIREQ12,Cluster 2 Core 0 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 11. "SGPPIREQ11,Cluster 2 Core 0 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 10. "SGPPIREQ10,Cluster 2 Core 0 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 9. "SGPPIREQ9,Cluster 2 Core 0 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 8. "SGPPIREQ8,Cluster 2 Core 0 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 7. "SGPPIREQ7,Cluster 2 Core 0 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 6. "SGPPIREQ6,Cluster 2 Core 0 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 5. "SGPPIREQ5,Cluster 2 Core 0 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 4. "SGPPIREQ4,Cluster 2 Core 0 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 3. "SGPPIREQ3,Cluster 2 Core 0 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 2. "SGPPIREQ2,Cluster 2 Core 0 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 1. "SGPPIREQ1,Cluster 2 Core 0 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 0. "SGPPIREQ0,Cluster 2 Core 0 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" line.long 0x4 "SGPPIREQ63_32_CL2C0," bitfld.long 0x4 27. "SGPPIREQ59,Cluster 2 Core 0 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" bitfld.long 0x4 26. "SGPPIREQ58,Cluster 2 Core 0 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 25. "SGPPIREQ57,Cluster 2 Core 0 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" bitfld.long 0x4 24. "SGPPIREQ56,Cluster 2 Core 0 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 19. "SGPPIREQ51,Cluster 2 Core 0 triggers interrupt to DME Core (cleared by hardware)" "0,1" bitfld.long 0x4 18. "SGPPIREQ50,Cluster 2 Core 0 triggers interrupt to DME Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 17. "SGPPIREQ49,Cluster 2 Core 0 triggers interrupt to DME Core (cleared by hardware)" "0,1" bitfld.long 0x4 16. "SGPPIREQ48,Cluster 2 Core 0 triggers interrupt to DME Core (cleared by hardware)" "0,1" line.long 0x8 "SGPPISETPEND31_0_CL2C0," bitfld.long 0x8 31. "SGPPISETPEND31,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 30. "SGPPISETPEND30,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 29. "SGPPISETPEND29,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 28. "SGPPISETPEND28,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 27. "SGPPISETPEND27,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 26. "SGPPISETPEND26,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 25. "SGPPISETPEND25,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 24. "SGPPISETPEND24,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 23. "SGPPISETPEND23,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 22. "SGPPISETPEND22,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 21. "SGPPISETPEND21,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 20. "SGPPISETPEND20,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 19. "SGPPISETPEND19,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 18. "SGPPISETPEND18,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 17. "SGPPISETPEND17,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 16. "SGPPISETPEND16,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 15. "SGPPISETPEND15,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 14. "SGPPISETPEND14,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 13. "SGPPISETPEND13,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 12. "SGPPISETPEND12,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 11. "SGPPISETPEND11,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 10. "SGPPISETPEND10,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 9. "SGPPISETPEND9,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 8. "SGPPISETPEND8,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 7. "SGPPISETPEND7,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 6. "SGPPISETPEND6,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 5. "SGPPISETPEND5,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 4. "SGPPISETPEND4,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 3. "SGPPISETPEND3,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 2. "SGPPISETPEND2,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 1. "SGPPISETPEND1,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 0. "SGPPISETPEND0,Set pending software interrupt on Cluster 2 Core 0 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" line.long 0xC "SGPPISETPEND63_32_CL2C0," bitfld.long 0xC 31. "SGPPISETPEND63,Set pending software interrupt on Cluster 2 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 30. "SGPPISETPEND62,Set pending software interrupt on Cluster 2 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 29. "SGPPISETPEND61,Set pending software interrupt on Cluster 2 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 28. "SGPPISETPEND60,Set pending software interrupt on Cluster 2 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 27. "SGPPISETPEND59,Set pending software interrupt on Cluster 2 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 26. "SGPPISETPEND58,Set pending software interrupt on Cluster 2 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 25. "SGPPISETPEND57,Set pending software interrupt on Cluster 2 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 24. "SGPPISETPEND56,Set pending software interrupt on Cluster 2 Core 0 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 23. "SGPPISETPEND55,Set pending software interrupt on Cluster 2 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 22. "SGPPISETPEND54,Set pending software interrupt on Cluster 2 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 21. "SGPPISETPEND53,Set pending software interrupt on Cluster 2 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 20. "SGPPISETPEND52,Set pending software interrupt on Cluster 2 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 19. "SGPPISETPEND51,Set pending software interrupt on Cluster 2 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 18. "SGPPISETPEND50,Set pending software interrupt on Cluster 2 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 17. "SGPPISETPEND49,Set pending software interrupt on Cluster 2 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 16. "SGPPISETPEND48,Set pending software interrupt on Cluster 2 Core 0 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" line.long 0x10 "SGPPICLRPEND31_0_CL2C0," bitfld.long 0x10 31. "SGPPICLRPEND31,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 30. "SGPPICLRPEND30,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 29. "SGPPICLRPEND29,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 28. "SGPPICLRPEND28,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 27. "SGPPICLRPEND27,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 26. "SGPPICLRPEND26,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 25. "SGPPICLRPEND25,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 24. "SGPPICLRPEND24,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 23. "SGPPICLRPEND23,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 22. "SGPPICLRPEND22,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 21. "SGPPICLRPEND21,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 20. "SGPPICLRPEND20,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 19. "SGPPICLRPEND19,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 18. "SGPPICLRPEND18,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 17. "SGPPICLRPEND17,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 16. "SGPPICLRPEND16,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 15. "SGPPICLRPEND15,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 14. "SGPPICLRPEND14,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 13. "SGPPICLRPEND13,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 12. "SGPPICLRPEND12,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 11. "SGPPICLRPEND11,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 10. "SGPPICLRPEND10,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 9. "SGPPICLRPEND9,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 8. "SGPPICLRPEND8,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 7. "SGPPICLRPEND7,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 6. "SGPPICLRPEND6,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 5. "SGPPICLRPEND5,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 4. "SGPPICLRPEND4,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 3. "SGPPICLRPEND3,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 2. "SGPPICLRPEND2,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 1. "SGPPICLRPEND1,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 0. "SGPPICLRPEND0,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" line.long 0x14 "SGPPICLRPEND63_32_CL2C0," bitfld.long 0x14 31. "SGPPICLRPEND63,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 30. "SGPPICLRPEND62,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 29. "SGPPICLRPEND61,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 28. "SGPPICLRPEND60,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 27. "SGPPICLRPEND59,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 26. "SGPPICLRPEND58,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 25. "SGPPICLRPEND57,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 24. "SGPPICLRPEND56,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 23. "SGPPICLRPEND55,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 22. "SGPPICLRPEND54,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 21. "SGPPICLRPEND53,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 20. "SGPPICLRPEND52,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 19. "SGPPICLRPEND51,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 18. "SGPPICLRPEND50,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 17. "SGPPICLRPEND49,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 16. "SGPPICLRPEND48,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" line.long 0x18 "SGPPIENABLE31_0_CL2C0," bitfld.long 0x18 31. "SGPPIEN31,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x18 30. "SGPPIEN30,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x18 29. "SGPPIEN29,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x18 28. "SGPPIEN28,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x18 27. "SGPPIEN27,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x18 26. "SGPPIEN26,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x18 25. "SGPPIEN25,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x18 24. "SGPPIEN24,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x18 23. "SGPPIEN23,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x18 22. "SGPPIEN22,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x18 21. "SGPPIEN21,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x18 20. "SGPPIEN20,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x18 19. "SGPPIEN19,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x18 18. "SGPPIEN18,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x18 17. "SGPPIEN17,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x18 16. "SGPPIEN16,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x18 15. "SGPPIEN15,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x18 14. "SGPPIEN14,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x18 13. "SGPPIEN13,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x18 12. "SGPPIEN12,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x18 11. "SGPPIEN11,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x18 10. "SGPPIEN10,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x18 9. "SGPPIEN9,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x18 8. "SGPPIEN8,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x18 7. "SGPPIEN7,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x18 6. "SGPPIEN6,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x18 5. "SGPPIEN5,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x18 4. "SGPPIEN4,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x18 3. "SGPPIEN3,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x18 2. "SGPPIEN2,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x18 1. "SGPPIEN1,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x18 0. "SGPPIEN0,Enable SW PPI on Cluster2 Core0." "0,1" line.long 0x1C "SGPPIENABLE63_32_CL2C0," bitfld.long 0x1C 31. "SGPPIEN63,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x1C 30. "SGPPIEN62,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x1C 29. "SGPPIEN61,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x1C 28. "SGPPIEN60,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x1C 27. "SGPPIEN59,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x1C 26. "SGPPIEN58,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x1C 25. "SGPPIEN57,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x1C 24. "SGPPIEN56,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x1C 23. "SGPPIEN55,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x1C 22. "SGPPIEN54,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x1C 21. "SGPPIEN53,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x1C 20. "SGPPIEN52,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x1C 19. "SGPPIEN51,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x1C 18. "SGPPIEN50,Enable SW PPI on Cluster2 Core0." "0,1" newline bitfld.long 0x1C 17. "SGPPIEN49,Enable SW PPI on Cluster2 Core0." "0,1" bitfld.long 0x1C 16. "SGPPIEN48,Enable SW PPI on Cluster2 Core0." "0,1" line.long 0x20 "SGPPISEL0_CL2C0," hexmask.long.byte 0x20 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x24 "SGPPISEL1_CL2C0," hexmask.long.byte 0x24 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x28 "SGPPISEL2_CL2C0," hexmask.long.byte 0x28 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x2C "SGPPISEL3_CL2C0," hexmask.long.byte 0x2C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x30 "SGPPISEL4_CL2C0," hexmask.long.byte 0x30 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x34 "SGPPISEL5_CL2C0," hexmask.long.byte 0x34 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x38 "SGPPISEL6_CL2C0," hexmask.long.byte 0x38 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x3C "SGPPISEL7_CL2C0," hexmask.long.byte 0x3C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x40 "SGPPISEL8_CL2C0," hexmask.long.byte 0x40 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x44 "SGPPISEL9_CL2C0," hexmask.long.byte 0x44 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x48 "SGPPISEL10_CL2C0," hexmask.long.byte 0x48 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x4C "SGPPISEL11_CL2C0," hexmask.long.byte 0x4C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x50 "SGPPISEL12_CL2C0," hexmask.long.byte 0x50 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x54 "SGPPISEL13_CL2C0," hexmask.long.byte 0x54 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x58 "SGPPISE14_CL2C0," hexmask.long.byte 0x58 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x5C "SGPPISEL15_CL2C0," hexmask.long.byte 0x5C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x60 "SGPPISEL16_CL2C0," hexmask.long.byte 0x60 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x64 "SGPPISEL17_CL2C0," hexmask.long.byte 0x64 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x68 "SGPPISEL18_CL2C0," hexmask.long.byte 0x68 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x6C "SGPPISEL19_CL2C0," hexmask.long.byte 0x6C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x70 "SGPPISEL20_CL2C0," hexmask.long.byte 0x70 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x74 "SGPPISEL21_CL2C0," hexmask.long.byte 0x74 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x78 "SGPPISEL22_CL2C0," hexmask.long.byte 0x78 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x7C "SGPPISEL23_CL2C0," hexmask.long.byte 0x7C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x80 "SGPPISEL24_CL2C0," hexmask.long.byte 0x80 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x84 "SGPPISEL25_CL2C0," hexmask.long.byte 0x84 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x88 "SGPPISEL26_CL2C0," hexmask.long.byte 0x88 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x8C "SGPPISEL27_CL2C0," hexmask.long.byte 0x8C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x90 "SGPPISEL28_CL2C0," hexmask.long.byte 0x90 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x94 "SGPPISEL29_CL2C0," hexmask.long.byte 0x94 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x98 "SGPPISEL30_CL2C0," hexmask.long.byte 0x98 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x9C "SGPPISEL31_CL2C0," hexmask.long.byte 0x9C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xA0 "SGPPISEL32_CL2C0," hexmask.long.byte 0xA0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xA4 "SGPPISEL33_CL2C0," hexmask.long.byte 0xA4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xA8 "SGPPISEL34_CL2C0," hexmask.long.byte 0xA8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xAC "SGPPISEL35_CL2C0," hexmask.long.byte 0xAC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xB0 "SGPPISEL36_CL2C0," hexmask.long.byte 0xB0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xB4 "SGPPISEL37_CL2C0," hexmask.long.byte 0xB4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xB8 "SGPPISEL38_CL2C0," hexmask.long.byte 0xB8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xBC "SGPPISEL39_CL2C0," hexmask.long.byte 0xBC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xC0 "SGPPISEL40_CL2C0," hexmask.long.byte 0xC0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xC4 "SGPPISEL41_CL2C0," hexmask.long.byte 0xC4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xC8 "SGPPISEL42_CL2C0," hexmask.long.byte 0xC8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xCC "SGPPISEL43_CL2C0," hexmask.long.byte 0xCC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xD0 "SGPPISEL44_CL2C0," hexmask.long.byte 0xD0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xD4 "SGPPISEL45_CL2C0," hexmask.long.byte 0xD4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xD8 "SGPPISEL46_CL2C0," hexmask.long.byte 0xD8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xDC "SGPPISEL47_CL2C0," hexmask.long.byte 0xDC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xE0 "SGPPICFG0_CL2C0," bitfld.long 0xE0 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xE4 "SGPPICFG1_CL2C0," bitfld.long 0xE4 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xE8 "SGPPICFG2_CL2C0," bitfld.long 0xE8 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xEC "SGPPICFG3_CL2C0," bitfld.long 0xEC 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xF0 "SGPPICFG4_CL2C0," bitfld.long 0xF0 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xF4 "SGPPICFG5_CL2C0," bitfld.long 0xF4 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" tree.end tree "IBCM_IBCM_LLPP_CL2C1_CORE_0_SIG" base ad:0x6C200000 group.long 0x0++0xF7 line.long 0x0 "SGPPIREQ31_0_CL2C1," bitfld.long 0x0 31. "SGPPIREQ31,Cluster 2 Core 1 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 30. "SGPPIREQ30,Cluster 2 Core 1 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 29. "SGPPIREQ29,Cluster 2 Core 1 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 28. "SGPPIREQ28,Cluster 2 Core 1 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 27. "SGPPIREQ27,Cluster 2 Core 1 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 26. "SGPPIREQ26,Cluster 2 Core 1 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 25. "SGPPIREQ25,Cluster 2 Core 1 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 24. "SGPPIREQ24,Cluster 2 Core 1 triggers interrupt to Cluster 1 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 23. "SGPPIREQ23,Cluster 2 Core 1 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 22. "SGPPIREQ22,Cluster 2 Core 1 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 21. "SGPPIREQ21,Cluster 2 Core 1 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 20. "SGPPIREQ20,Cluster 2 Core 1 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 19. "SGPPIREQ19,Cluster 2 Core 1 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 18. "SGPPIREQ18,Cluster 2 Core 1 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 17. "SGPPIREQ17,Cluster 2 Core 1 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 16. "SGPPIREQ16,Cluster 2 Core 1 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 15. "SGPPIREQ15,Cluster 2 Core 1 triggers interrupt to Cluster 1 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 14. "SGPPIREQ14,Cluster 2 Core 1 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 13. "SGPPIREQ13,Cluster 2 Core 1 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 12. "SGPPIREQ12,Cluster 2 Core 1 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 11. "SGPPIREQ11,Cluster 2 Core 1 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 10. "SGPPIREQ10,Cluster 2 Core 1 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 9. "SGPPIREQ9,Cluster 2 Core 1 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" bitfld.long 0x0 8. "SGPPIREQ8,Cluster 2 Core 1 triggers interrupt to Cluster 0 Core 1 (cleared by hardware)" "0,1" newline bitfld.long 0x0 7. "SGPPIREQ7,Cluster 2 Core 1 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 6. "SGPPIREQ6,Cluster 2 Core 1 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 5. "SGPPIREQ5,Cluster 2 Core 1 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 4. "SGPPIREQ4,Cluster 2 Core 1 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 3. "SGPPIREQ3,Cluster 2 Core 1 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 2. "SGPPIREQ2,Cluster 2 Core 1 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" newline bitfld.long 0x0 1. "SGPPIREQ1,Cluster 2 Core 1 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" bitfld.long 0x0 0. "SGPPIREQ0,Cluster 2 Core 1 triggers interrupt to Cluster 0 Core 0 (cleared by hardware)" "0,1" line.long 0x4 "SGPPIREQ63_32_CL2C1," bitfld.long 0x4 27. "SGPPIREQ59,Cluster 2 Core 1 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" bitfld.long 0x4 26. "SGPPIREQ58,Cluster 2 Core 1 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 25. "SGPPIREQ57,Cluster 2 Core 1 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" bitfld.long 0x4 24. "SGPPIREQ56,Cluster 2 Core 1 triggers interrupt to DSPH Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 19. "SGPPIREQ51,Cluster 2 Core 1 triggers interrupt to DME Core (cleared by hardware)" "0,1" bitfld.long 0x4 18. "SGPPIREQ50,Cluster 2 Core 1 triggers interrupt to DME Core (cleared by hardware)" "0,1" newline bitfld.long 0x4 17. "SGPPIREQ49,Cluster 2 Core 1 triggers interrupt to DME Core (cleared by hardware)" "0,1" bitfld.long 0x4 16. "SGPPIREQ48,Cluster 2 Core 1 triggers interrupt to DME Core (cleared by hardware)" "0,1" line.long 0x8 "SGPPISETPEND31_0_CL2C1," bitfld.long 0x8 31. "SGPPISETPEND31,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 30. "SGPPISETPEND30,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 29. "SGPPISETPEND29,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 28. "SGPPISETPEND28,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 27. "SGPPISETPEND27,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 26. "SGPPISETPEND26,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 25. "SGPPISETPEND25,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 24. "SGPPISETPEND24,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 1 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 23. "SGPPISETPEND23,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 22. "SGPPISETPEND22,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 21. "SGPPISETPEND21,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 20. "SGPPISETPEND20,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 19. "SGPPISETPEND19,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 18. "SGPPISETPEND18,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 17. "SGPPISETPEND17,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 16. "SGPPISETPEND16,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 1 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 15. "SGPPISETPEND15,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 14. "SGPPISETPEND14,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 13. "SGPPISETPEND13,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 12. "SGPPISETPEND12,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 11. "SGPPISETPEND11,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 10. "SGPPISETPEND10,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 9. "SGPPISETPEND9,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 8. "SGPPISETPEND8,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 0 Core 1. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 7. "SGPPISETPEND7,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 6. "SGPPISETPEND6,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 5. "SGPPISETPEND5,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 4. "SGPPISETPEND4,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 3. "SGPPISETPEND3,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 2. "SGPPISETPEND2,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0x8 1. "SGPPISETPEND1,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0x8 0. "SGPPISETPEND0,Set pending software interrupt on Cluster 2 Core 1 triggered by Cluster 0 Core 0. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" line.long 0xC "SGPPISETPEND63_32_CL2C1," bitfld.long 0xC 31. "SGPPISETPEND63,Set pending software interrupt on Cluster 2 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 30. "SGPPISETPEND62,Set pending software interrupt on Cluster 2 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 29. "SGPPISETPEND61,Set pending software interrupt on Cluster 2 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 28. "SGPPISETPEND60,Set pending software interrupt on Cluster 2 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 27. "SGPPISETPEND59,Set pending software interrupt on Cluster 2 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 26. "SGPPISETPEND58,Set pending software interrupt on Cluster 2 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 25. "SGPPISETPEND57,Set pending software interrupt on Cluster 2 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 24. "SGPPISETPEND56,Set pending software interrupt on Cluster 2 Core 1 triggered by DSPH Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 23. "SGPPISETPEND55,Set pending software interrupt on Cluster 2 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 22. "SGPPISETPEND54,Set pending software interrupt on Cluster 2 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 21. "SGPPISETPEND53,Set pending software interrupt on Cluster 2 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 20. "SGPPISETPEND52,Set pending software interrupt on Cluster 2 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 19. "SGPPISETPEND51,Set pending software interrupt on Cluster 2 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 18. "SGPPISETPEND50,Set pending software interrupt on Cluster 2 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" newline bitfld.long 0xC 17. "SGPPISETPEND49,Set pending software interrupt on Cluster 2 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" bitfld.long 0xC 16. "SGPPISETPEND48,Set pending software interrupt on Cluster 2 Core 1 triggered by DME Core. Its set and cleared by hardware." "0: Interrupt request not pending within IBCM,1: Interrupt request is pending within IBCM" line.long 0x10 "SGPPICLRPEND31_0_CL2C1," bitfld.long 0x10 31. "SGPPICLRPEND31,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 30. "SGPPICLRPEND30,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 29. "SGPPICLRPEND29,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 28. "SGPPICLRPEND28,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 27. "SGPPICLRPEND27,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 26. "SGPPICLRPEND26,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 25. "SGPPICLRPEND25,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 24. "SGPPICLRPEND24,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 23. "SGPPICLRPEND23,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 22. "SGPPICLRPEND22,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 21. "SGPPICLRPEND21,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 20. "SGPPICLRPEND20,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 19. "SGPPICLRPEND19,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 18. "SGPPICLRPEND18,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 17. "SGPPICLRPEND17,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 16. "SGPPICLRPEND16,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 15. "SGPPICLRPEND15,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 14. "SGPPICLRPEND14,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 13. "SGPPICLRPEND13,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 12. "SGPPICLRPEND12,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 11. "SGPPICLRPEND11,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 10. "SGPPICLRPEND10,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 9. "SGPPICLRPEND9,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 8. "SGPPICLRPEND8,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 7. "SGPPICLRPEND7,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 6. "SGPPICLRPEND6,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 5. "SGPPICLRPEND5,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 4. "SGPPICLRPEND4,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 3. "SGPPICLRPEND3,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 2. "SGPPICLRPEND2,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x10 1. "SGPPICLRPEND1,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x10 0. "SGPPICLRPEND0,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" line.long 0x14 "SGPPICLRPEND63_32_CL2C1," bitfld.long 0x14 31. "SGPPICLRPEND63,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 30. "SGPPICLRPEND62,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 29. "SGPPICLRPEND61,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 28. "SGPPICLRPEND60,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 27. "SGPPICLRPEND59,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 26. "SGPPICLRPEND58,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 25. "SGPPICLRPEND57,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 24. "SGPPICLRPEND56,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 23. "SGPPICLRPEND55,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 22. "SGPPICLRPEND54,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 21. "SGPPICLRPEND53,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 20. "SGPPICLRPEND52,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 19. "SGPPICLRPEND51,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 18. "SGPPICLRPEND50,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" newline bitfld.long 0x14 17. "SGPPICLRPEND49,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" bitfld.long 0x14 16. "SGPPICLRPEND48,Clear corresponding pending interrupt in SGPPISETPEND register." "0,1" line.long 0x18 "SGPPIENABLE31_0_CL2C1," bitfld.long 0x18 31. "SGPPIEN31,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x18 30. "SGPPIEN30,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x18 29. "SGPPIEN29,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x18 28. "SGPPIEN28,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x18 27. "SGPPIEN27,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x18 26. "SGPPIEN26,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x18 25. "SGPPIEN25,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x18 24. "SGPPIEN24,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x18 23. "SGPPIEN23,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x18 22. "SGPPIEN22,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x18 21. "SGPPIEN21,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x18 20. "SGPPIEN20,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x18 19. "SGPPIEN19,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x18 18. "SGPPIEN18,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x18 17. "SGPPIEN17,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x18 16. "SGPPIEN16,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x18 15. "SGPPIEN15,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x18 14. "SGPPIEN14,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x18 13. "SGPPIEN13,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x18 12. "SGPPIEN12,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x18 11. "SGPPIEN11,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x18 10. "SGPPIEN10,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x18 9. "SGPPIEN9,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x18 8. "SGPPIEN8,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x18 7. "SGPPIEN7,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x18 6. "SGPPIEN6,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x18 5. "SGPPIEN5,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x18 4. "SGPPIEN4,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x18 3. "SGPPIEN3,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x18 2. "SGPPIEN2,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x18 1. "SGPPIEN1,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x18 0. "SGPPIEN0,Enable SW PPI on Cluster2 Core1." "0,1" line.long 0x1C "SGPPIENABLE63_32_CL2C1," bitfld.long 0x1C 31. "SGPPIEN63,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x1C 30. "SGPPIEN62,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x1C 29. "SGPPIEN61,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x1C 28. "SGPPIEN60,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x1C 27. "SGPPIEN59,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x1C 26. "SGPPIEN58,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x1C 25. "SGPPIEN57,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x1C 24. "SGPPIEN56,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x1C 23. "SGPPIEN55,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x1C 22. "SGPPIEN54,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x1C 21. "SGPPIEN53,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x1C 20. "SGPPIEN52,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x1C 19. "SGPPIEN51,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x1C 18. "SGPPIEN50,Enable SW PPI on Cluster2 Core1." "0,1" newline bitfld.long 0x1C 17. "SGPPIEN49,Enable SW PPI on Cluster2 Core1." "0,1" bitfld.long 0x1C 16. "SGPPIEN48,Enable SW PPI on Cluster2 Core1." "0,1" line.long 0x20 "SGPPISEL0_CL2C1," hexmask.long.byte 0x20 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x24 "SGPPISEL1_CL2C1," hexmask.long.byte 0x24 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x28 "SGPPISEL2_CL2C1," hexmask.long.byte 0x28 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x2C "SGPPISEL3_CL2C1," hexmask.long.byte 0x2C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x30 "SGPPISEL4_CL2C1," hexmask.long.byte 0x30 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x34 "SGPPISEL5_CL2C1," hexmask.long.byte 0x34 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x38 "SGPPISEL6_CL2C1," hexmask.long.byte 0x38 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x3C "SGPPISEL7_CL2C1," hexmask.long.byte 0x3C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x40 "SGPPISEL8_CL2C1," hexmask.long.byte 0x40 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x44 "SGPPISEL9_CL2C1," hexmask.long.byte 0x44 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x48 "SGPPISEL10_CL2C1," hexmask.long.byte 0x48 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x4C "SGPPISEL11_CL2C1," hexmask.long.byte 0x4C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x50 "SGPPISEL12_CL2C1," hexmask.long.byte 0x50 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x54 "SGPPISEL13_CL2C1," hexmask.long.byte 0x54 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x58 "SGPPISEL14_CL2C1," hexmask.long.byte 0x58 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x5C "SGPPISEL15_CL2C1," hexmask.long.byte 0x5C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x60 "SGPPISEL16_CL2C1," hexmask.long.byte 0x60 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x64 "SGPPISEL17_CL2C1," hexmask.long.byte 0x64 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x68 "SGPPISEL18_CL2C1," hexmask.long.byte 0x68 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x6C "SGPPISEL19_CL2C1," hexmask.long.byte 0x6C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x70 "SGPPISEL20_CL2C1," hexmask.long.byte 0x70 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x74 "SGPPISEL21_CL2C1," hexmask.long.byte 0x74 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x78 "SGPPISEL22_CL2C1," hexmask.long.byte 0x78 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x7C "SGPPISEL23_CL2C1," hexmask.long.byte 0x7C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x80 "SGPPISEL24_CL2C1," hexmask.long.byte 0x80 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x84 "SGPPISEL25_CL2C1," hexmask.long.byte 0x84 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x88 "SGPPISEL26_CL2C1," hexmask.long.byte 0x88 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x8C "SGPPISEL27_CL2C1," hexmask.long.byte 0x8C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x90 "SGPPISEL28_CL2C1," hexmask.long.byte 0x90 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x94 "SGPPISEL29_CL2C1," hexmask.long.byte 0x94 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x98 "SGPPISEL30_CL2C1," hexmask.long.byte 0x98 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0x9C "SGPPISEL31_CL2C1," hexmask.long.byte 0x9C 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xA0 "SGPPISEL32_CL2C1," hexmask.long.byte 0xA0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xA4 "SGPPISEL33_CL2C1," hexmask.long.byte 0xA4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xA8 "SGPPISEL34_CL2C1," hexmask.long.byte 0xA8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xAC "SGPPISEL35_CL2C1," hexmask.long.byte 0xAC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xB0 "SGPPISEL36_CL2C1," hexmask.long.byte 0xB0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xB4 "SGPPISEL37_CL2C1," hexmask.long.byte 0xB4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xB8 "SGPPISEL38_CL2C1," hexmask.long.byte 0xB8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xBC "SGPPISEL39_CL2C1," hexmask.long.byte 0xBC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xC0 "SGPPISEL40_CL2C1," hexmask.long.byte 0xC0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xC4 "SGPPISEL41_CL2C1," hexmask.long.byte 0xC4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xC8 "SGPPISEL42_CL2C1," hexmask.long.byte 0xC8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xCC "SGPPISEL43_CL2C1," hexmask.long.byte 0xCC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xD0 "SGPPISEL44_CL2C1," hexmask.long.byte 0xD0 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xD4 "SGPPISEL45_CL2C1," hexmask.long.byte 0xD4 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xD8 "SGPPISEL46_CL2C1," hexmask.long.byte 0xD8 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xDC "SGPPISEL47_CL2C1," hexmask.long.byte 0xDC 0.--5. 1. "SGPPISEL,Select interrupt source for each mux to generate PPI" line.long 0xE0 "SGPPICFG0_CL2C1," bitfld.long 0xE0 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xE4 "SGPPICFG1_CL2C1," bitfld.long 0xE4 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xE8 "SGPPICFG2_CL2C1," bitfld.long 0xE8 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xEC "SGPPICFG3_CL2C1," bitfld.long 0xEC 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xF0 "SGPPICFG4_CL2C1," bitfld.long 0xF0 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" line.long 0xF4 "SGPPICFG5_CL2C1," bitfld.long 0xF4 0. "SGPPICFG,Select active level of SGPPI." "0: SGPPI is active low,1: SGPPI is active high" tree.end tree.end tree "IIC (Inter-Integrated Circuit)" base ad:0x0 tree "IIC_0" base ad:0x72114000 group.byte 0x0++0x6 line.byte 0x0 "IBAD,I2C Bus Address Register" hexmask.byte 0x0 1.--7. 1. "ADR,Slave Address" line.byte 0x1 "IBFD,I2C Bus Frequency Divider Register" hexmask.byte 0x1 0.--7. 1. "IBC,I-Bus Clock Rate" line.byte 0x2 "IBCR,I2C Bus Control Register" bitfld.byte 0x2 7. "MDIS,Module disable" "0: The I2C Bus module is enabled. This bit must be..,1: The module is reset and disabled. This is the.." bitfld.byte 0x2 6. "IBIE,I-Bus Interrupt Enable" "0: Interrupts from the I2C Bus module are disabled.,1: Interrupts from the I2C Bus module are enabled." newline bitfld.byte 0x2 5. "MSSL,Master/Slave mode select" "0: Slave Mode,1: Master Mode" bitfld.byte 0x2 4. "TXRX,Transmit/Receive mode select" "0: Receive,1: Transmit" newline bitfld.byte 0x2 3. "NOACK,Data Acknowledge disable" "0: An acknowledge signal will be sent out to the..,1: No acknowledge signal response is sent (that is.." bitfld.byte 0x2 2. "RSTA,Repeat Start" "0: No effect,1: Generate repeat start cycle" newline bitfld.byte 0x2 1. "DMAEN,DMA Enable" "0: Disable the DMA TX/RX request signals,1: Enable the DMA TX/RX request signals" line.byte 0x3 "IBSR,I2C Bus Status Register" bitfld.byte 0x3 7. "TCF,Transfer complete" "0: Transfer in progress,1: Transfer complete" bitfld.byte 0x3 6. "IAAS,Addressed as a slave" "0: Not addressed,1: Addressed as a slave" newline bitfld.byte 0x3 5. "IBB,Bus busy" "0: Bus is Idle,1: Bus is busy" bitfld.byte 0x3 4. "IBAL,Arbitration Lost" "0,1" newline bitfld.byte 0x3 2. "SRW,Slave Read/Write" "0: Slave receive master writing to slave,1: Slave transmit master reading from slave" bitfld.byte 0x3 1. "IBIF,I-Bus Interrupt Flag" "0,1" newline bitfld.byte 0x3 0. "RXAK,Received Acknowledge" "0: Acknowledge received,1: No acknowledge received" line.byte 0x4 "IBDR,I2C Bus Data I/O Register" hexmask.byte 0x4 0.--7. 1. "DATA,Data transmitted or received" line.byte 0x5 "IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x5 7. "BIIE,Bus Idle Interrupt Enable bit" "0: Bus Idle Interrupts disabled,1: Bus Idle Interrupts enabled" bitfld.byte 0x5 6. "BYTERXIE,Byte receive interrupt enable" "0,1" line.byte 0x6 "IBDBG,I2C Bus Debug Register" bitfld.byte 0x6 1. "IPG_DEBUG_HALTED,Debug Halted Bit" "0: IP is still executing a transaction,1: IP has entered the debug mode" bitfld.byte 0x6 0. "IPG_DEBUG_EN,Debug enable bit" "0: Normal operation Bus Idle Interrupts disabled,1: IP is in debug mode" tree.end tree "IIC_1" base ad:0x71514000 group.byte 0x0++0x6 line.byte 0x0 "IBAD,I2C Bus Address Register" hexmask.byte 0x0 1.--7. 1. "ADR,Slave Address" line.byte 0x1 "IBFD,I2C Bus Frequency Divider Register" hexmask.byte 0x1 0.--7. 1. "IBC,I-Bus Clock Rate" line.byte 0x2 "IBCR,I2C Bus Control Register" bitfld.byte 0x2 7. "MDIS,Module disable" "0: The I2C Bus module is enabled. This bit must be..,1: The module is reset and disabled. This is the.." bitfld.byte 0x2 6. "IBIE,I-Bus Interrupt Enable" "0: Interrupts from the I2C Bus module are disabled.,1: Interrupts from the I2C Bus module are enabled." newline bitfld.byte 0x2 5. "MSSL,Master/Slave mode select" "0: Slave Mode,1: Master Mode" bitfld.byte 0x2 4. "TXRX,Transmit/Receive mode select" "0: Receive,1: Transmit" newline bitfld.byte 0x2 3. "NOACK,Data Acknowledge disable" "0: An acknowledge signal will be sent out to the..,1: No acknowledge signal response is sent (that is.." bitfld.byte 0x2 2. "RSTA,Repeat Start" "0: No effect,1: Generate repeat start cycle" newline bitfld.byte 0x2 1. "DMAEN,DMA Enable" "0: Disable the DMA TX/RX request signals,1: Enable the DMA TX/RX request signals" line.byte 0x3 "IBSR,I2C Bus Status Register" bitfld.byte 0x3 7. "TCF,Transfer complete" "0: Transfer in progress,1: Transfer complete" bitfld.byte 0x3 6. "IAAS,Addressed as a slave" "0: Not addressed,1: Addressed as a slave" newline bitfld.byte 0x3 5. "IBB,Bus busy" "0: Bus is Idle,1: Bus is busy" bitfld.byte 0x3 4. "IBAL,Arbitration Lost" "0,1" newline bitfld.byte 0x3 2. "SRW,Slave Read/Write" "0: Slave receive master writing to slave,1: Slave transmit master reading from slave" bitfld.byte 0x3 1. "IBIF,I-Bus Interrupt Flag" "0,1" newline bitfld.byte 0x3 0. "RXAK,Received Acknowledge" "0: Acknowledge received,1: No acknowledge received" line.byte 0x4 "IBDR,I2C Bus Data I/O Register" hexmask.byte 0x4 0.--7. 1. "DATA,Data transmitted or received" line.byte 0x5 "IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x5 7. "BIIE,Bus Idle Interrupt Enable bit" "0: Bus Idle Interrupts disabled,1: Bus Idle Interrupts enabled" bitfld.byte 0x5 6. "BYTERXIE,Byte receive interrupt enable" "0,1" line.byte 0x6 "IBDBG,I2C Bus Debug Register" bitfld.byte 0x6 1. "IPG_DEBUG_HALTED,Debug Halted Bit" "0: IP is still executing a transaction,1: IP has entered the debug mode" bitfld.byte 0x6 0. "IPG_DEBUG_EN,Debug enable bit" "0: Normal operation Bus Idle Interrupts disabled,1: IP is in debug mode" tree.end tree.end tree "IMA (Indirect Memory Access)" base ad:0x0 tree "IMA_0" base ad:0x71154000 group.long 0x0++0x7 line.long 0x0 "CTRL,IMA Control register" bitfld.long 0x0 0. "READ,IMA Read" "0: The IMA access will be a write.,1: The IMA access will be a read." line.long 0x4 "ENABLE,IMA Enable Access register" bitfld.long 0x4 0. "EN,IMA Enable" "0: No IMA access will occur or the IMA has finished..,1: Start an IMA access or an IMA access is occurring." rgroup.long 0x8++0x3 line.long 0x0 "STATUS,IMA Status register" bitfld.long 0x0 8. "WRITE_LOCK,The ability of the IMA to do write accesses. The WRITE_LOCK bit shows the current status of the lock on IMA write accesses. If set the IMA does not write to the memories. If cleared the IMA is allowed to do writes to the memories." "0: Write accesses from the IMA to memories are..,1: Write accesses from the IMA to memories are not.." bitfld.long 0x0 0. "READ_LOCK,The ability of the IMA to do read accesses. The READ_LOCK bit shows the current status of the lock on IMA read accesses. If set the IMA does not do reads from the memories. If cleared the IMA is allowed to do reads from the memories." "0: Read accesses from the IMA to memories are..,1: Read accesses from the IMA to memories are not.." group.long 0xC++0xB line.long 0x0 "SLCT,IMA RAM Select register" hexmask.long.word 0x0 16.--31. 1. "ROW_SLCT,The ROW_SLCT value specifies the row of the current RAM array under test to be selected. Hence the largest RAM which the IMA can access is 256KB RAM." hexmask.long.byte 0x0 0.--5. 1. "ARRAY_SLCT,The ARRAY_SLCT specifies the RAM array to be tested. Up to 64 RAM instances can be supported." line.long 0x4 "WRITE_UNLOCK,IMA Write Unlock register" hexmask.long 0x4 0.--31. 1. "WRITE_KEY,Key to unlock the IMA." line.long 0x8 "READ_UNLOCK,IMA Read Unlock register" hexmask.long 0x8 0.--31. 1. "READ_KEY,Key to unlock the IMA Read Access to RAMs." group.long 0x2C++0x13 line.long 0x0 "WRITE_DATA_4,IMA RAM Write Data register n" hexmask.long 0x0 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." line.long 0x4 "WRITE_DATA_3,IMA RAM Write Data register 3" hexmask.long 0x4 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." line.long 0x8 "WRITE_DATA_2,IMA RAM Write Data register 2" hexmask.long 0x8 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." line.long 0xC "WRITE_DATA_1,IMA RAM Write Data register 1" hexmask.long 0xC 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." line.long 0x10 "WRITE_DATA_0,IMA RAM Write Data register 0" hexmask.long 0x10 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." rgroup.long 0x4C++0x13 line.long 0x0 "READ_DATA_4,IMA RAM Read Data register 4" hexmask.long 0x0 0.--31. 1. "READ_DATA,Contains data to be written to RAM." line.long 0x4 "READ_DATA_3,IMA RAM Read Data register n" hexmask.long 0x4 0.--31. 1. "READ_DATA,Contains data to be written to RAM." line.long 0x8 "READ_DATA_2,IMA RAM Read Data register 2" hexmask.long 0x8 0.--31. 1. "READ_DATA,Contains data to be written to RAM." line.long 0xC "READ_DATA_1,IMA RAM Read Data register 1" hexmask.long 0xC 0.--31. 1. "READ_DATA,Contains data to be written to RAM." line.long 0x10 "READ_DATA_0,IMA RAM Read Data register 0" hexmask.long 0x10 0.--31. 1. "READ_DATA,Contains data to be written to RAM." tree.end tree "IMA_1" base ad:0x71754000 group.long 0x0++0x7 line.long 0x0 "CTRL,IMA Control register" bitfld.long 0x0 0. "READ,IMA Read" "0: The IMA access will be a write.,1: The IMA access will be a read." line.long 0x4 "ENABLE,IMA Enable Access register" bitfld.long 0x4 0. "EN,IMA Enable" "0: No IMA access will occur or the IMA has finished..,1: Start an IMA access or an IMA access is occurring." rgroup.long 0x8++0x3 line.long 0x0 "STATUS,IMA Status register" bitfld.long 0x0 8. "WRITE_LOCK,The ability of the IMA to do write accesses. The WRITE_LOCK bit shows the current status of the lock on IMA write accesses. If set the IMA does not write to the memories. If cleared the IMA is allowed to do writes to the memories." "0: Write accesses from the IMA to memories are..,1: Write accesses from the IMA to memories are not.." bitfld.long 0x0 0. "READ_LOCK,The ability of the IMA to do read accesses. The READ_LOCK bit shows the current status of the lock on IMA read accesses. If set the IMA does not do reads from the memories. If cleared the IMA is allowed to do reads from the memories." "0: Read accesses from the IMA to memories are..,1: Read accesses from the IMA to memories are not.." group.long 0xC++0xB line.long 0x0 "SLCT,IMA RAM Select register" hexmask.long.word 0x0 16.--31. 1. "ROW_SLCT,The ROW_SLCT value specifies the row of the current RAM array under test to be selected. Hence the largest RAM which the IMA can access is 256KB RAM." hexmask.long.byte 0x0 0.--5. 1. "ARRAY_SLCT,The ARRAY_SLCT specifies the RAM array to be tested. Up to 64 RAM instances can be supported." line.long 0x4 "WRITE_UNLOCK,IMA Write Unlock register" hexmask.long 0x4 0.--31. 1. "WRITE_KEY,Key to unlock the IMA." line.long 0x8 "READ_UNLOCK,IMA Read Unlock register" hexmask.long 0x8 0.--31. 1. "READ_KEY,Key to unlock the IMA Read Access to RAMs." group.long 0x2C++0x13 line.long 0x0 "WRITE_DATA_4,IMA RAM Write Data register n" hexmask.long 0x0 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." line.long 0x4 "WRITE_DATA_3,IMA RAM Write Data register 3" hexmask.long 0x4 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." line.long 0x8 "WRITE_DATA_2,IMA RAM Write Data register 2" hexmask.long 0x8 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." line.long 0xC "WRITE_DATA_1,IMA RAM Write Data register 1" hexmask.long 0xC 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." line.long 0x10 "WRITE_DATA_0,IMA RAM Write Data register 0" hexmask.long 0x10 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." rgroup.long 0x4C++0x13 line.long 0x0 "READ_DATA_4,IMA RAM Read Data register 4" hexmask.long 0x0 0.--31. 1. "READ_DATA,Contains data to be written to RAM." line.long 0x4 "READ_DATA_3,IMA RAM Read Data register n" hexmask.long 0x4 0.--31. 1. "READ_DATA,Contains data to be written to RAM." line.long 0x8 "READ_DATA_2,IMA RAM Read Data register 2" hexmask.long 0x8 0.--31. 1. "READ_DATA,Contains data to be written to RAM." line.long 0xC "READ_DATA_1,IMA RAM Read Data register 1" hexmask.long 0xC 0.--31. 1. "READ_DATA,Contains data to be written to RAM." line.long 0x10 "READ_DATA_0,IMA RAM Read Data register 0" hexmask.long 0x10 0.--31. 1. "READ_DATA,Contains data to be written to RAM." tree.end tree "IMA_2" base ad:0x71158000 group.long 0x0++0x7 line.long 0x0 "CTRL,IMA Control register" bitfld.long 0x0 0. "READ,IMA Read" "0: The IMA access will be a write.,1: The IMA access will be a read." line.long 0x4 "ENABLE,IMA Enable Access register" bitfld.long 0x4 0. "EN,IMA Enable" "0: No IMA access will occur or the IMA has finished..,1: Start an IMA access or an IMA access is occurring." rgroup.long 0x8++0x3 line.long 0x0 "STATUS,IMA Status register" bitfld.long 0x0 8. "WRITE_LOCK,The ability of the IMA to do write accesses. The WRITE_LOCK bit shows the current status of the lock on IMA write accesses. If set the IMA does not write to the memories. If cleared the IMA is allowed to do writes to the memories." "0: Write accesses from the IMA to memories are..,1: Write accesses from the IMA to memories are not.." bitfld.long 0x0 0. "READ_LOCK,The ability of the IMA to do read accesses. The READ_LOCK bit shows the current status of the lock on IMA read accesses. If set the IMA does not do reads from the memories. If cleared the IMA is allowed to do reads from the memories." "0: Read accesses from the IMA to memories are..,1: Read accesses from the IMA to memories are not.." group.long 0xC++0xB line.long 0x0 "SLCT,IMA RAM Select register" hexmask.long.word 0x0 16.--31. 1. "ROW_SLCT,The ROW_SLCT value specifies the row of the current RAM array under test to be selected. Hence the largest RAM which the IMA can access is 256KB RAM." hexmask.long.byte 0x0 0.--5. 1. "ARRAY_SLCT,The ARRAY_SLCT specifies the RAM array to be tested. Up to 64 RAM instances can be supported." line.long 0x4 "WRITE_UNLOCK,IMA Write Unlock register" hexmask.long 0x4 0.--31. 1. "WRITE_KEY,Key to unlock the IMA." line.long 0x8 "READ_UNLOCK,IMA Read Unlock register" hexmask.long 0x8 0.--31. 1. "READ_KEY,Key to unlock the IMA Read Access to RAMs." group.long 0x2C++0x13 line.long 0x0 "WRITE_DATA_4,IMA RAM Write Data register n" hexmask.long 0x0 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." line.long 0x4 "WRITE_DATA_3,IMA RAM Write Data register 3" hexmask.long 0x4 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." line.long 0x8 "WRITE_DATA_2,IMA RAM Write Data register 2" hexmask.long 0x8 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." line.long 0xC "WRITE_DATA_1,IMA RAM Write Data register 1" hexmask.long 0xC 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." line.long 0x10 "WRITE_DATA_0,IMA RAM Write Data register 0" hexmask.long 0x10 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." rgroup.long 0x4C++0x13 line.long 0x0 "READ_DATA_4,IMA RAM Read Data register 4" hexmask.long 0x0 0.--31. 1. "READ_DATA,Contains data to be written to RAM." line.long 0x4 "READ_DATA_3,IMA RAM Read Data register n" hexmask.long 0x4 0.--31. 1. "READ_DATA,Contains data to be written to RAM." line.long 0x8 "READ_DATA_2,IMA RAM Read Data register 2" hexmask.long 0x8 0.--31. 1. "READ_DATA,Contains data to be written to RAM." line.long 0xC "READ_DATA_1,IMA RAM Read Data register 1" hexmask.long 0xC 0.--31. 1. "READ_DATA,Contains data to be written to RAM." line.long 0x10 "READ_DATA_0,IMA RAM Read Data register 0" hexmask.long 0x10 0.--31. 1. "READ_DATA,Contains data to be written to RAM." tree.end tree "IMA_3" base ad:0x71758000 group.long 0x0++0x7 line.long 0x0 "CTRL,IMA Control register" bitfld.long 0x0 0. "READ,IMA Read" "0: The IMA access will be a write.,1: The IMA access will be a read." line.long 0x4 "ENABLE,IMA Enable Access register" bitfld.long 0x4 0. "EN,IMA Enable" "0: No IMA access will occur or the IMA has finished..,1: Start an IMA access or an IMA access is occurring." rgroup.long 0x8++0x3 line.long 0x0 "STATUS,IMA Status register" bitfld.long 0x0 8. "WRITE_LOCK,The ability of the IMA to do write accesses. The WRITE_LOCK bit shows the current status of the lock on IMA write accesses. If set the IMA does not write to the memories. If cleared the IMA is allowed to do writes to the memories." "0: Write accesses from the IMA to memories are..,1: Write accesses from the IMA to memories are not.." bitfld.long 0x0 0. "READ_LOCK,The ability of the IMA to do read accesses. The READ_LOCK bit shows the current status of the lock on IMA read accesses. If set the IMA does not do reads from the memories. If cleared the IMA is allowed to do reads from the memories." "0: Read accesses from the IMA to memories are..,1: Read accesses from the IMA to memories are not.." group.long 0xC++0xB line.long 0x0 "SLCT,IMA RAM Select register" hexmask.long.word 0x0 16.--31. 1. "ROW_SLCT,The ROW_SLCT value specifies the row of the current RAM array under test to be selected. Hence the largest RAM which the IMA can access is 256KB RAM." hexmask.long.byte 0x0 0.--5. 1. "ARRAY_SLCT,The ARRAY_SLCT specifies the RAM array to be tested. Up to 64 RAM instances can be supported." line.long 0x4 "WRITE_UNLOCK,IMA Write Unlock register" hexmask.long 0x4 0.--31. 1. "WRITE_KEY,Key to unlock the IMA." line.long 0x8 "READ_UNLOCK,IMA Read Unlock register" hexmask.long 0x8 0.--31. 1. "READ_KEY,Key to unlock the IMA Read Access to RAMs." group.long 0x2C++0x13 line.long 0x0 "WRITE_DATA_4,IMA RAM Write Data register n" hexmask.long 0x0 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." line.long 0x4 "WRITE_DATA_3,IMA RAM Write Data register 3" hexmask.long 0x4 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." line.long 0x8 "WRITE_DATA_2,IMA RAM Write Data register 2" hexmask.long 0x8 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." line.long 0xC "WRITE_DATA_1,IMA RAM Write Data register 1" hexmask.long 0xC 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." line.long 0x10 "WRITE_DATA_0,IMA RAM Write Data register 0" hexmask.long 0x10 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." rgroup.long 0x4C++0x13 line.long 0x0 "READ_DATA_4,IMA RAM Read Data register 4" hexmask.long 0x0 0.--31. 1. "READ_DATA,Contains data to be written to RAM." line.long 0x4 "READ_DATA_3,IMA RAM Read Data register n" hexmask.long 0x4 0.--31. 1. "READ_DATA,Contains data to be written to RAM." line.long 0x8 "READ_DATA_2,IMA RAM Read Data register 2" hexmask.long 0x8 0.--31. 1. "READ_DATA,Contains data to be written to RAM." line.long 0xC "READ_DATA_1,IMA RAM Read Data register 1" hexmask.long 0xC 0.--31. 1. "READ_DATA,Contains data to be written to RAM." line.long 0x10 "READ_DATA_0,IMA RAM Read Data register 0" hexmask.long 0x10 0.--31. 1. "READ_DATA,Contains data to be written to RAM." tree.end tree "IMA_4" base ad:0x7115C000 group.long 0x0++0x7 line.long 0x0 "CTRL,IMA Control register" bitfld.long 0x0 0. "READ,IMA Read" "0: The IMA access will be a write.,1: The IMA access will be a read." line.long 0x4 "ENABLE,IMA Enable Access register" bitfld.long 0x4 0. "EN,IMA Enable" "0: No IMA access will occur or the IMA has finished..,1: Start an IMA access or an IMA access is occurring." rgroup.long 0x8++0x3 line.long 0x0 "STATUS,IMA Status register" bitfld.long 0x0 8. "WRITE_LOCK,The ability of the IMA to do write accesses. The WRITE_LOCK bit shows the current status of the lock on IMA write accesses. If set the IMA does not write to the memories. If cleared the IMA is allowed to do writes to the memories." "0: Write accesses from the IMA to memories are..,1: Write accesses from the IMA to memories are not.." bitfld.long 0x0 0. "READ_LOCK,The ability of the IMA to do read accesses. The READ_LOCK bit shows the current status of the lock on IMA read accesses. If set the IMA does not do reads from the memories. If cleared the IMA is allowed to do reads from the memories." "0: Read accesses from the IMA to memories are..,1: Read accesses from the IMA to memories are not.." group.long 0xC++0xB line.long 0x0 "SLCT,IMA RAM Select register" hexmask.long.word 0x0 16.--31. 1. "ROW_SLCT,The ROW_SLCT value specifies the row of the current RAM array under test to be selected. Hence the largest RAM which the IMA can access is 256KB RAM." hexmask.long.byte 0x0 0.--5. 1. "ARRAY_SLCT,The ARRAY_SLCT specifies the RAM array to be tested. Up to 64 RAM instances can be supported." line.long 0x4 "WRITE_UNLOCK,IMA Write Unlock register" hexmask.long 0x4 0.--31. 1. "WRITE_KEY,Key to unlock the IMA." line.long 0x8 "READ_UNLOCK,IMA Read Unlock register" hexmask.long 0x8 0.--31. 1. "READ_KEY,Key to unlock the IMA Read Access to RAMs." group.long 0x2C++0x13 line.long 0x0 "WRITE_DATA_4,IMA RAM Write Data register n" hexmask.long 0x0 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." line.long 0x4 "WRITE_DATA_3,IMA RAM Write Data register 3" hexmask.long 0x4 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." line.long 0x8 "WRITE_DATA_2,IMA RAM Write Data register 2" hexmask.long 0x8 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." line.long 0xC "WRITE_DATA_1,IMA RAM Write Data register 1" hexmask.long 0xC 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." line.long 0x10 "WRITE_DATA_0,IMA RAM Write Data register 0" hexmask.long 0x10 0.--31. 1. "WRITE_DATA,Contains data to be written to RAM." rgroup.long 0x4C++0x13 line.long 0x0 "READ_DATA_4,IMA RAM Read Data register 4" hexmask.long 0x0 0.--31. 1. "READ_DATA,Contains data to be written to RAM." line.long 0x4 "READ_DATA_3,IMA RAM Read Data register n" hexmask.long 0x4 0.--31. 1. "READ_DATA,Contains data to be written to RAM." line.long 0x8 "READ_DATA_2,IMA RAM Read Data register 2" hexmask.long 0x8 0.--31. 1. "READ_DATA,Contains data to be written to RAM." line.long 0xC "READ_DATA_1,IMA RAM Read Data register 1" hexmask.long 0xC 0.--31. 1. "READ_DATA,Contains data to be written to RAM." line.long 0x10 "READ_DATA_0,IMA RAM Read Data register 0" hexmask.long 0x10 0.--31. 1. "READ_DATA,Contains data to be written to RAM." tree.end tree.end tree "LFAST (LVDS Fast Asynchronous Serial Transmission)" base ad:0x0 tree "LFAST_0" base ad:0x7049C000 group.long 0x0++0x23 line.long 0x0 "MCR,Mode Configuration Register" bitfld.long 0x0 31. "MSEN,LFAST Master or Slave mode Enable" "0: Enable the modules LFAST Slave functionality only.,1: Enable the modules LFAST Master functionality.." bitfld.long 0x0 24. "IPGDBG,Control bit to enable support for IPG Debug mode" "0: IPG debug mode enable signal will be ignored.,1: IPG debug mode enable signal will not be ignored." newline bitfld.long 0x0 16. "LSSEL,Selects the fraction of sysclk in Low Speed Select mode" "0: Low Speed Mode in which where lfast_sysclk input..,1: Low Speed Mode in which where lfast_sysclk input.." bitfld.long 0x0 15. "DRFEN,LFAST Enable" "0: LFAST is immediately disabled. All..,1: LFAST is Enabled." newline bitfld.long 0x0 14. "RXEN,LFAST Receiver Enable" "0: Receiver Interface is disabled. If this bit is..,1: Receiver Interface is Enabled." bitfld.long 0x0 13. "TXEN,LFAST Transmitter Enable" "0: LFAST transmitter Interface is disabled. No new..,1: Transmitter is Enabled." newline bitfld.long 0x0 4. "TXARBD,Tx Arbiter Disable" "0: Enable Tx arbiter and framer. When enabled it..,1: Disable Tx arbiter and framer. All frame.." bitfld.long 0x0 3. "CTSEN,CTS Enable" "0: CTS mode is disabled. Indicates that the device..,1: CTS mode is enabled. The CTS bit of all transmit.." newline bitfld.long 0x0 1. "DRFRST,LFAST Soft Reset" "0: No soft reset.,1: Soft reset to LFAST is asserted. When set it.." bitfld.long 0x0 0. "DATAEN,DATA Frame Enable" "0: Data frame transmission and reception is..,1: Data frame transmission and reception is.." line.long 0x4 "SCR,Speed Control Register" bitfld.long 0x4 16. "DRMD,Data Rate Controller mode" "0: The software controls the Data Rate controller..,1: In LFAST Slave the reception of ICLC frame for.." bitfld.long 0x4 8. "RDR,Receiver Data Rate" "0: Data rate of Rx block is low speed.,1: Data rate of Rx block is high speed." newline bitfld.long 0x4 0. "TDR,Transmit Data Rate" "0: Data rate of Tx block is low speed.,1: Data rate of Tx block is high speed." line.long 0x8 "COCR,Correlator Control Register" hexmask.long.byte 0x8 24.--31. 1. "SMPSEL,Sampler Data Path Selector (overrides the correlator selection)" bitfld.long 0x8 1.--3. "CORRTH,Correlator threshold level. Defines the correlation threshold level." "0: 9 Bits of correlation,1: 10 Bits of correlation,?,?,?,?,6: 15 Bits of correlation,7: 16 Bits of correlation" newline bitfld.long 0x8 0. "PHSSEL,Polyphase 8 or 4 phase selection" "0: 8 phases,1: 4 phases" line.long 0xC "TMCR,Test Mode Control Register" bitfld.long 0xC 25. "CLKTST,Clock Test mode" "0: Clock Test mode disabled,1: Clock Test mode enabled" bitfld.long 0xC 24. "LPON,Loopback mode Logic Enable" "0: Loopback mode is disabled.,1: Loopback mode is enabled." newline bitfld.long 0xC 16.--18. "LPMOD,Loopback mode" "0: Rx loopback,1: Rx LVDS loopback,2: Tx loopback without automatic frame generation,3: Tx loopback with automatic frame generation,4: Tx LVDS loopback (external) with automatic frame..,?,?,?" hexmask.long.word 0xC 0.--15. 1. "LPFRMTH,Loopback check mode valid pass frames threshold value. Defines the number of frames to verify before setting GCR[LPFPDV] when running in Automatic Loopback Frame mode. The loopback frame is considered pass when the payload is CBh header is 13h.." line.long 0x10 "ALCR,Auto Loopback Control Register" bitfld.long 0x10 16. "LPCNTEN,Auto Loopback Frame Transmission Count Enable" "0: Infinite predefined loopback frame transmission..,1: Fixed count of predefined loopback frame.." hexmask.long.word 0x10 0.--15. 1. "LPFMCNT,Auto Loopback Frame Transmission Count" line.long 0x14 "RCDCR,Rate Change Delay Control Register" hexmask.long.byte 0x14 16.--19. 1. "DRCNT,Data Rate Controller Counter Value" line.long 0x18 "SLCR,Wakeup Delay Control Register" hexmask.long.byte 0x18 24.--31. 1. "HSCNT,High Speed Sleep mode Exit Time" hexmask.long.byte 0x18 16.--19. 1. "LSCNT,Low Speed Sleep mode Exit Time" newline hexmask.long.byte 0x18 8.--15. 1. "HWKCNT,Wake Up time for the LD" hexmask.long.byte 0x18 0.--3. 1. "LWKCNT,Wake Up time for the LD" line.long 0x1C "ICR,ICLC Control Register" bitfld.long 0x1C 17. "ICLCSEQ,ICLC enabled" "0: Single ICLC frame transfer,1: The software is performing ICLC frame transfers." bitfld.long 0x1C 16. "SNDICLC,ICLC frame request" "0: No Valid ICLC frame for transfer.,1: Valid ICLC frame for transfer." newline hexmask.long.byte 0x1C 0.--7. 1. "ICLCPLD,ICLC Payload" line.long 0x20 "PICR,Ping Control Register" bitfld.long 0x20 16. "PNGREQ,Ping Response Frame Request" "0: No pending Ping response frame transmission..,1: Ping response frame transmission request is.." bitfld.long 0x20 15. "PNGAUTO,Ping Response Enable" "0: Ping response should not be automatically sent.,1: Ping response should be automatically sent." newline hexmask.long.byte 0x20 0.--7. 1. "PNGPYLD,LFAST Slave: Defines the LFAST slaves ping reply frame payload content." group.long 0x2C++0x3F line.long 0x0 "RFCR,Rx FIFO CTS Control Register" hexmask.long.byte 0x0 16.--21. 1. "RCTSMX,Rx FIFO Maximum Threshold" hexmask.long.byte 0x0 0.--5. 1. "RCTSMN,Rx FIFO Minimum Threshold" line.long 0x4 "TIER,Tx Interrupt Enable Register" bitfld.long 0x4 17. "TXIIE,Tx Data Interface Not Enabled (Mask)" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x4 16. "TXOVIE,Transmit Data FIFO Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x4 4. "TXPNGIE,Ping Response Frame Transmitted Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x4 2. "TXUNSIE,Unsolicited Frame transmitted Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x4 1. "TXICLCIE,ICLC Frame transmitted Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x4 0. "TXDTIE,Data Frame transmitted Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." line.long 0x8 "RIER,Rx Interrupt Enable Register" bitfld.long 0x8 23. "RXUOIE,Unsolicited frame register overflow" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 22. "RXMNIE,Rx Data FIFO Min Threshold reached" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "RXMXIE,Rx Data FIFO Max Threshold reached" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 20. "RXUFIE,Rx Data FIFO Underflow" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "RXOFIE,Rx Data FIFO Overflow" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 18. "RXSZIE,Frame with unsupported frame size received" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "RXICIE,Invalid ICLC code Received" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 16. "RXLCEIE,Invalid Logical Channel Type" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 3. "RXCTSIE,Frame with CTS bit Low Received" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 2. "RXDIE,Data frame received" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 1. "RXUNSIE,Unsolicited Frame received" "0: Interrupt is disabled.,1: Interrupt is enabled." line.long 0xC "RIIER,Rx ICLC Interrupt Enable Register" bitfld.long 0xC 13. "ICPFIE,Ping Frame Response failed" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0xC 12. "ICPSIE,Ping Frame Response successful" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 11. "ICPRIE,ICLC frame for Ping Frame Request received" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0xC 10. "ICTOIE,ICLC frame for Test mode off received" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 9. "ICLPIE,ICLC frame for Loopback On received" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0xC 8. "ICCTIE,ICLC frame for Clk Test mode on received" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 7. "ICTDIE,ICLC frame for LFAST Slaves Tx Interface Disable received" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0xC 6. "ICTEIE,ICLC frame for LFAST Slaves Tx Interface Enable received" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 5. "ICRFIE,ICLC frame for LFAST Slaves Rx Interface fast mode switch received" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0xC 4. "ICRSIE,ICLC frame for LFAST Slaves Rx Interface slow mode switch received" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 3. "ICTFIE,ICLC frame for LFAST Slaves Tx Interface fast mode switch received" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0xC 2. "ICTSIE,ICLC frame for LFAST Slaves Tx Interface slow mode switch received" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 1. "ICPOFIE,ICLC frame for PLL OFF received" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0xC 0. "ICPONIE,ICLC frame for PLL ON received" "0: Interrupt is disabled.,1: Interrupt is enabled." line.long 0x10 "PLLCR,PLL Control Register" bitfld.long 0x10 29.--31. "IPTMOD,Test mode programmability" "0: Functional mode,1: Closed Loop 1,2: Force Vctrl,3: Charge Pump Up,4: Charge Pump Up Internal Test,5: Charge Pump Idle,6: Charge Pump Down,7: Closed Loop 2" bitfld.long 0x10 17. "SWPOFF,Software signal to turn OFF the PLL" "0: No effect,1: PLL will be turned OFF." newline bitfld.long 0x10 16. "SWPON,Software signal to turn ON the PLL" "0: No effect,1: PLL will be turned ON" bitfld.long 0x10 15. "REFINV,Inverts reference clock edge to PFD" "0: Not inverted,1: Invert" newline bitfld.long 0x10 13.--14. "LPCFG,PLL Loop Optimization. Adjusts charge pump bias current. Higher current increases PLL bandwidth decreasing jitter while degrading stability." "0: 1xIBASE,1: 0.5xIBASE,2: 1.5xIBASE,3: 2xIBASE" bitfld.long 0x10 9.--10. "PLCKCW,PLL Lock Ready Count Width" "0: 1040 cycles,1: 520 cycles,2: 320 cycles,3: 200 cycles" newline bitfld.long 0x10 8. "FDIVEN,Enable fraction division mode in feedback divider" "0: Fraction division mode not enabled,1: Fraction division mode enabled" hexmask.long.byte 0x10 2.--7. 1. "FBDIV,Feedback Division factor for VCO output clock" newline bitfld.long 0x10 0.--1. "PREDIV,Division factor for PLL Reference Clock input" "0: Direct clock passed,1: Divide by 2,2: Divide by 3,3: Divide by 4" line.long 0x14 "LCR,LVDS Control Register" bitfld.long 0x14 23. "SWWKLD,Software signal to take LVDS LD out of Sleep mode" "0: No effect,1: LVDS LD will be taken out of sleep (provided no.." bitfld.long 0x14 22. "SWSLPLD,Software signal to put LVDS LD into Sleep mode" "0: No effect,1: LVDS LD will be put in sleep." newline bitfld.long 0x14 21. "SWWKLR,Software signal to take LVDS LR out of Sleep mode" "0: No effect,1: LVDS LR will be taken out of sleep (provided no.." bitfld.long 0x14 20. "SWSLPLR,Software signal to put LVDS LR into Sleep mode" "0: No effect,1: LVDS LR will be put in sleep (provided no other.." newline bitfld.long 0x14 19. "SWOFFLD,Software signal to turn OFF the LVDS LD" "0: No effect,1: LVDS LD will be turned OFF (provided no other.." bitfld.long 0x14 18. "SWONLD,Software signal to turn ON the LVDS LD" "0: No effect,1: LVDS LD will be turned ON." newline bitfld.long 0x14 17. "SWOFFLR,Software signal to turn OFF the LVDS LR" "0: No effect,1: LVDS LR will be turned OFF (provided no other.." bitfld.long 0x14 16. "SWONLR,Software signal to turn ON the LVDS LR" "0: No effect,1: LVDS LR will be turned ON." newline bitfld.long 0x14 15. "LVRXOFF,Indicates the value driven onto LVDS LR output when in shutdown mode." "0,1" bitfld.long 0x14 14. "LVTXOE,LVDS LD output buffer enable" "0: LVDS LD output buffer enable is disabled.,1: LVDS LD output buffer enabled" newline bitfld.long 0x14 13. "TXCMUX,Tx and Clock Mux" "0: No effect,1: PLL Phase 0 clock will be brought out to Tx LVDS.." bitfld.long 0x14 12. "LVRFEN,LVDS pad reference enable" "0: LVDS reference pad disabled,1: LVDS reference pad enabled" newline bitfld.long 0x14 11. "LVLPEN,Tx LVDS internal loopback enable" "0: Tx LVDS normal mode enabled,1: Tx LVDS internal loopback mode enabled" bitfld.long 0x14 5. "LVRXOP_TR,Used to enable or disable the on-chip receiver termination resistor in LFAST mode (applies to LVDS pad use for LFAST only)." "0: Disable on-chip LFAST receiver termination,1: Enable on-chip LFAST receiver termination" newline bitfld.long 0x14 3. "LVRXOP_BR,Used to set the bias current for the receiver in LFAST mode. It is recommended to always write 1 to this bit when using the LFAST interface. Writing 0 will allow for a small power savings during lower baud rates (applies to LVDS pad use for.." "0: Use for LFAST receiver baud rates less than..,1: Required for LFAST receiver maximum baud rate" bitfld.long 0x14 2. "LVTXOP,Control signal for LFAST and Micro-Second Bus selection" "0: Micro-Second Bus selection,1: LFAST Bus selection" newline bitfld.long 0x14 1. "LVCKSS,LVDS Clock Sync Select" "0: Normal clock used to sample the LVDS data,1: Adjusted clock used to sample the LVDS data" bitfld.long 0x14 0. "LVCKP,LVDS clock select" "0: Direct pll clock to be used inside the LVDS,1: Inverted pll clock to be used inside the LVDS" line.long 0x18 "UNSTCR,Unsolicited Tx Control Register" bitfld.long 0x18 16. "USNDRQ,Tx Unsolicited send request. This field can only be written when MCR[DRFEN] = 1." "0: No valid Unsolicited frame exists,1: Valid Unsolicited frame exists for transmission" hexmask.long.byte 0x18 0.--6. 1. "UNSHDR,Tx Unsolicited message header" line.long 0x1C "UNSTDR8,LFAST Unsolicited Tx Data Registers" hexmask.long 0x1C 0.--31. 1. "UNTXD,Unsolicited Transmit Data 80x0:" line.long 0x20 "UNSTDR7,LFAST Unsolicited Tx Data Registers" hexmask.long 0x20 0.--31. 1. "UNTXD,Unsolicited Transmit Data 80x0:" line.long 0x24 "UNSTDR6,LFAST Unsolicited Tx Data Registers" hexmask.long 0x24 0.--31. 1. "UNTXD,Unsolicited Transmit Data 80x0:" line.long 0x28 "UNSTDR5,LFAST Unsolicited Tx Data Registers" hexmask.long 0x28 0.--31. 1. "UNTXD,Unsolicited Transmit Data 80x0:" line.long 0x2C "UNSTDR4,LFAST Unsolicited Tx Data Registers" hexmask.long 0x2C 0.--31. 1. "UNTXD,Unsolicited Transmit Data 80x0:" line.long 0x30 "UNSTDR3,LFAST Unsolicited Tx Data Registers" hexmask.long 0x30 0.--31. 1. "UNTXD,Unsolicited Transmit Data 80x0:" line.long 0x34 "UNSTDR2,LFAST Unsolicited Tx Data Registers" hexmask.long 0x34 0.--31. 1. "UNTXD,Unsolicited Transmit Data 80x0:" line.long 0x38 "UNSTDR1,LFAST Unsolicited Tx Data Registers" hexmask.long 0x38 0.--31. 1. "UNTXD,Unsolicited Transmit Data 80x0:" line.long 0x3C "UNSTDR0,LFAST Unsolicited Tx Data Registers" hexmask.long 0x3C 0.--31. 1. "UNTXD,Unsolicited Transmit Data 80x0:" rgroup.long 0x80++0x7 line.long 0x0 "GSR,Global Status Register" bitfld.long 0x0 31. "DUALMD,Indicates the LFAST module is in Dual mode" "0: LFAST Module Slave only mode,1: LFAST Module in dual mode" bitfld.long 0x0 18. "LRMD,Indicates if the Rx Controller is idle/active and that the Rx clocks are enabled. In functional mode this will always be active." "0: Rx Controller is in Idle state.,1: Rx Controller is active." newline bitfld.long 0x0 17. "LDSM,Transmit Interface Data Rate Status" "0: Data rate of LOW speed mode,1: Data rate of HIGH speed mode" bitfld.long 0x0 16. "DRSM,Receive Interface Data Rate Status" "0: Data rate of LOW speed mode,1: Data rate of HIGH speed mode" newline bitfld.long 0x0 4. "LPTXDN,Auto loopback frame transmission count reached" "0: Auto loopback frame transmission count not reached,1: Auto loopback frame transmission count reached" bitfld.long 0x0 3. "LPFPDV,Loopback frame pass threshold reached" "0: Pass frame threshold not reached,1: Pass frame threshold achieved" newline bitfld.long 0x0 2. "LPCPDV,Valid payload received during loopback check mode" "0: Payload received is not 0xCB.,1: Payload received is 0xCB." bitfld.long 0x0 1. "LPCHDV,Valid header received during loopback check mode" "0: Header received is not 0x13.,1: Header received is 0x13." newline bitfld.long 0x0 0. "LPCSDV,Valid synchronization received" "0: Valid Synchronization pattern not detected,1: Valid Synchronization pattern detected" line.long 0x4 "PISR,Ping Status Register" hexmask.long.byte 0x4 0.--7. 1. "RXPNGD,Ping Data Register" rgroup.long 0x94++0x3 line.long 0x0 "DFSR,Data frame Status Register" hexmask.long.byte 0x0 24.--29. 1. "RXDCNT,Unread Rx Frame Data Count" bitfld.long 0x0 16.--18. "RXFCNT,Unread Rx Frame Count" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--13. 1. "TXDCNT,Unread Tx Frame Data Count" bitfld.long 0x0 0.--2. "TXFCNT,Unread Tx Frame Count" "0,1,2,3,4,5,6,7" group.long 0x98++0xB line.long 0x0 "TISR,Tx Interrupt Status Register" bitfld.long 0x0 17. "TXIEF,Tx Data Interface not enabled" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x0 16. "TXOVF,Transmit Data FIFO Overflow Interrupt" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x0 4. "TXPNGF,Ping response frame transmitted interrupt" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x0 2. "TXUNSF,Unsolicited Frame transmitted Interrupt" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x0 1. "TXICLCF,ICLC Frame transmitted Interrupt" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x0 0. "TXDTF,Data Frame transmitted Interrupt" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." line.long 0x4 "RISR,Rx Interrupt Status Register" bitfld.long 0x4 23. "RXUOF,Unsolicited frame register overflow" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x4 22. "RXMNF,Rx Data FIFO Min Threshold reached" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x4 21. "RXMXF,Rx Data FIFO Max Threshold reached" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x4 20. "RXUFF,Rx Data FIFO Underflow" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x4 19. "RXOFF,Rx Data FIFO Overflow" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x4 18. "RXSZF,Frame with unsupported frame size received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred: On reception of.." newline bitfld.long 0x4 17. "RXICF,Invalid ICLC code Received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x4 16. "RXLCEF,Invalid Logical Channel Type" "0: Interrupt event has not occurred.,1: Interrupt event has occurred: On reception of.." newline bitfld.long 0x4 3. "RXCTSF,Frame with CTS bit Low Received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x4 2. "RXDF,Data frame received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x4 1. "RXUNSF,Unsolicited Frame received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." line.long 0x8 "RIISR,Rx ICLC Interrupt Status Register" bitfld.long 0x8 13. "ICPFF,Ping Frame Response failed" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x8 12. "ICPSF,Ping Frame Response successful" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x8 11. "ICPRF,ICLC Ping Frame Request received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x8 10. "ICTOF,ICLC frame for Test mode off received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x8 9. "ICLPF,ICLC frame for Loopback On received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x8 8. "ICCTF,ICLC frame for Clk Test mode received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x8 7. "ICTDF,ICLC frame for LFAST Slaves Tx Interface Disable received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x8 6. "ICTEF,ICLC frame for LFAST Slaves Tx Interface Enable received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x8 5. "ICRFF,ICLC frame for LFAST Slaves Rx Interface fast mode switch received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x8 4. "ICRSF,ICLC frame for LFAST Slaves Rx Interface slow mode switch received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x8 3. "ICTFF,ICLC frame for LFAST Slaves Tx Interface fast mode switch received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x8 2. "ICTSF,ICLC frame for LFAST Slaves Tx Interface slow mode switch received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x8 1. "ICPOFF,ICLC frame for PLL OFF received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x8 0. "ICPONF,ICLC frame for PLL ON received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." rgroup.long 0xA4++0x3 line.long 0x0 "PLLLSR,PLL and LVDS Status Register" bitfld.long 0x0 17. "PLLDIS,PLL disable Status" "0: PLL disable signal is negated.,1: PLL disable signal is asserted." bitfld.long 0x0 16. "PLDCR,PLL Lock Delay Counter Ready" "0: PLL Lock delay counter is not decremented to 0.,1: PLL Lock delay counter is decremented to 0." newline bitfld.long 0x0 3. "LRSLPS,This bit indicates the real time status of the LR sleep signal." "0: LR sleep signal is negated.,1: LR sleep signal is asserted." bitfld.long 0x0 2. "LDSLPS,This bit indicates the real time status of LD sleep signal." "0: LD power sleep signal is negated.,1: LD power sleep signal is asserted." newline bitfld.long 0x0 1. "LDPDS,This bit indicates the real time status of LD power down signal. When asserted LD is put in the power down state." "0: LD power down signal is negated.,1: LD power down signal is asserted." bitfld.long 0x0 0. "LRPDS,This bit indicates the real time status of LR power down signal. When asserted LR is put in the power down state." "0: LR power down signal is negated.,1: LR power down signal is asserted." group.long 0xA8++0x3 line.long 0x0 "UNSRSR,Unsolicited Rx Status Register" bitfld.long 0x0 8. "URXDV,Unsolicited data valid" "0,1" bitfld.long 0x0 0.--2. "URPCNT,Rx Unsolicited payload" "0,1,2,3,4,5,6,7" rgroup.long 0xAC++0x23 line.long 0x0 "UNSRDR8,Unsolicited Rx Data Registers" hexmask.long 0x0 0.--31. 1. "UNRXD,Unsolicited Receive Data" line.long 0x4 "UNSRDR7,Unsolicited Rx Data Registers" hexmask.long 0x4 0.--31. 1. "UNRXD,Unsolicited Receive Data" line.long 0x8 "UNSRDR6,Unsolicited Rx Data Registers" hexmask.long 0x8 0.--31. 1. "UNRXD,Unsolicited Receive Data" line.long 0xC "UNSRDR5,Unsolicited Rx Data Registers" hexmask.long 0xC 0.--31. 1. "UNRXD,Unsolicited Receive Data" line.long 0x10 "UNSRDR4,Unsolicited Rx Data Registers" hexmask.long 0x10 0.--31. 1. "UNRXD,Unsolicited Receive Data" line.long 0x14 "UNSRDR3,Unsolicited Rx Data Registers" hexmask.long 0x14 0.--31. 1. "UNRXD,Unsolicited Receive Data" line.long 0x18 "UNSRDR2,Unsolicited Rx Data Registers" hexmask.long 0x18 0.--31. 1. "UNRXD,Unsolicited Receive Data" line.long 0x1C "UNSRDR1,Unsolicited Rx Data Registers" hexmask.long 0x1C 0.--31. 1. "UNRXD,Unsolicited Receive Data" line.long 0x20 "UNSRDR0,Unsolicited Rx Data Registers" hexmask.long 0x20 0.--31. 1. "UNRXD,Unsolicited Receive Data" tree.end tree "LFAST_1" base ad:0x70A9C000 group.long 0x0++0x23 line.long 0x0 "MCR,Mode Configuration Register" bitfld.long 0x0 31. "MSEN,LFAST Master or Slave mode Enable" "0: Enable the modules LFAST Slave functionality only.,1: Enable the modules LFAST Master functionality.." bitfld.long 0x0 24. "IPGDBG,Control bit to enable support for IPG Debug mode" "0: IPG debug mode enable signal will be ignored.,1: IPG debug mode enable signal will not be ignored." newline bitfld.long 0x0 16. "LSSEL,Selects the fraction of sysclk in Low Speed Select mode" "0: Low Speed Mode in which where lfast_sysclk input..,1: Low Speed Mode in which where lfast_sysclk input.." bitfld.long 0x0 15. "DRFEN,LFAST Enable" "0: LFAST is immediately disabled. All..,1: LFAST is Enabled." newline bitfld.long 0x0 14. "RXEN,LFAST Receiver Enable" "0: Receiver Interface is disabled. If this bit is..,1: Receiver Interface is Enabled." bitfld.long 0x0 13. "TXEN,LFAST Transmitter Enable" "0: LFAST transmitter Interface is disabled. No new..,1: Transmitter is Enabled." newline bitfld.long 0x0 4. "TXARBD,Tx Arbiter Disable" "0: Enable Tx arbiter and framer. When enabled it..,1: Disable Tx arbiter and framer. All frame.." bitfld.long 0x0 3. "CTSEN,CTS Enable" "0: CTS mode is disabled. Indicates that the device..,1: CTS mode is enabled. The CTS bit of all transmit.." newline bitfld.long 0x0 1. "DRFRST,LFAST Soft Reset" "0: No soft reset.,1: Soft reset to LFAST is asserted. When set it.." bitfld.long 0x0 0. "DATAEN,DATA Frame Enable" "0: Data frame transmission and reception is..,1: Data frame transmission and reception is.." line.long 0x4 "SCR,Speed Control Register" bitfld.long 0x4 16. "DRMD,Data Rate Controller mode" "0: The software controls the Data Rate controller..,1: In LFAST Slave the reception of ICLC frame for.." bitfld.long 0x4 8. "RDR,Receiver Data Rate" "0: Data rate of Rx block is low speed.,1: Data rate of Rx block is high speed." newline bitfld.long 0x4 0. "TDR,Transmit Data Rate" "0: Data rate of Tx block is low speed.,1: Data rate of Tx block is high speed." line.long 0x8 "COCR,Correlator Control Register" hexmask.long.byte 0x8 24.--31. 1. "SMPSEL,Sampler Data Path Selector (overrides the correlator selection)" bitfld.long 0x8 1.--3. "CORRTH,Correlator threshold level. Defines the correlation threshold level." "0: 9 Bits of correlation,1: 10 Bits of correlation,?,?,?,?,6: 15 Bits of correlation,7: 16 Bits of correlation" newline bitfld.long 0x8 0. "PHSSEL,Polyphase 8 or 4 phase selection" "0: 8 phases,1: 4 phases" line.long 0xC "TMCR,Test Mode Control Register" bitfld.long 0xC 25. "CLKTST,Clock Test mode" "0: Clock Test mode disabled,1: Clock Test mode enabled" bitfld.long 0xC 24. "LPON,Loopback mode Logic Enable" "0: Loopback mode is disabled.,1: Loopback mode is enabled." newline bitfld.long 0xC 16.--18. "LPMOD,Loopback mode" "0: Rx loopback,1: Rx LVDS loopback,2: Tx loopback without automatic frame generation,3: Tx loopback with automatic frame generation,4: Tx LVDS loopback (external) with automatic frame..,?,?,?" hexmask.long.word 0xC 0.--15. 1. "LPFRMTH,Loopback check mode valid pass frames threshold value. Defines the number of frames to verify before setting GCR[LPFPDV] when running in Automatic Loopback Frame mode. The loopback frame is considered pass when the payload is CBh header is 13h.." line.long 0x10 "ALCR,Auto Loopback Control Register" bitfld.long 0x10 16. "LPCNTEN,Auto Loopback Frame Transmission Count Enable" "0: Infinite predefined loopback frame transmission..,1: Fixed count of predefined loopback frame.." hexmask.long.word 0x10 0.--15. 1. "LPFMCNT,Auto Loopback Frame Transmission Count" line.long 0x14 "RCDCR,Rate Change Delay Control Register" hexmask.long.byte 0x14 16.--19. 1. "DRCNT,Data Rate Controller Counter Value" line.long 0x18 "SLCR,Wakeup Delay Control Register" hexmask.long.byte 0x18 24.--31. 1. "HSCNT,High Speed Sleep mode Exit Time" hexmask.long.byte 0x18 16.--19. 1. "LSCNT,Low Speed Sleep mode Exit Time" newline hexmask.long.byte 0x18 8.--15. 1. "HWKCNT,Wake Up time for the LD" hexmask.long.byte 0x18 0.--3. 1. "LWKCNT,Wake Up time for the LD" line.long 0x1C "ICR,ICLC Control Register" bitfld.long 0x1C 17. "ICLCSEQ,ICLC enabled" "0: Single ICLC frame transfer,1: The software is performing ICLC frame transfers." bitfld.long 0x1C 16. "SNDICLC,ICLC frame request" "0: No Valid ICLC frame for transfer.,1: Valid ICLC frame for transfer." newline hexmask.long.byte 0x1C 0.--7. 1. "ICLCPLD,ICLC Payload" line.long 0x20 "PICR,Ping Control Register" bitfld.long 0x20 16. "PNGREQ,Ping Response Frame Request" "0: No pending Ping response frame transmission..,1: Ping response frame transmission request is.." bitfld.long 0x20 15. "PNGAUTO,Ping Response Enable" "0: Ping response should not be automatically sent.,1: Ping response should be automatically sent." newline hexmask.long.byte 0x20 0.--7. 1. "PNGPYLD,LFAST Slave: Defines the LFAST slaves ping reply frame payload content." group.long 0x2C++0x3F line.long 0x0 "RFCR,Rx FIFO CTS Control Register" hexmask.long.byte 0x0 16.--21. 1. "RCTSMX,Rx FIFO Maximum Threshold" hexmask.long.byte 0x0 0.--5. 1. "RCTSMN,Rx FIFO Minimum Threshold" line.long 0x4 "TIER,Tx Interrupt Enable Register" bitfld.long 0x4 17. "TXIIE,Tx Data Interface Not Enabled (Mask)" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x4 16. "TXOVIE,Transmit Data FIFO Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x4 4. "TXPNGIE,Ping Response Frame Transmitted Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x4 2. "TXUNSIE,Unsolicited Frame transmitted Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x4 1. "TXICLCIE,ICLC Frame transmitted Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x4 0. "TXDTIE,Data Frame transmitted Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." line.long 0x8 "RIER,Rx Interrupt Enable Register" bitfld.long 0x8 23. "RXUOIE,Unsolicited frame register overflow" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 22. "RXMNIE,Rx Data FIFO Min Threshold reached" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "RXMXIE,Rx Data FIFO Max Threshold reached" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 20. "RXUFIE,Rx Data FIFO Underflow" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "RXOFIE,Rx Data FIFO Overflow" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 18. "RXSZIE,Frame with unsupported frame size received" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "RXICIE,Invalid ICLC code Received" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 16. "RXLCEIE,Invalid Logical Channel Type" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 3. "RXCTSIE,Frame with CTS bit Low Received" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 2. "RXDIE,Data frame received" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 1. "RXUNSIE,Unsolicited Frame received" "0: Interrupt is disabled.,1: Interrupt is enabled." line.long 0xC "RIIER,Rx ICLC Interrupt Enable Register" bitfld.long 0xC 13. "ICPFIE,Ping Frame Response failed" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0xC 12. "ICPSIE,Ping Frame Response successful" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 11. "ICPRIE,ICLC frame for Ping Frame Request received" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0xC 10. "ICTOIE,ICLC frame for Test mode off received" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 9. "ICLPIE,ICLC frame for Loopback On received" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0xC 8. "ICCTIE,ICLC frame for Clk Test mode on received" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 7. "ICTDIE,ICLC frame for LFAST Slaves Tx Interface Disable received" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0xC 6. "ICTEIE,ICLC frame for LFAST Slaves Tx Interface Enable received" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 5. "ICRFIE,ICLC frame for LFAST Slaves Rx Interface fast mode switch received" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0xC 4. "ICRSIE,ICLC frame for LFAST Slaves Rx Interface slow mode switch received" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 3. "ICTFIE,ICLC frame for LFAST Slaves Tx Interface fast mode switch received" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0xC 2. "ICTSIE,ICLC frame for LFAST Slaves Tx Interface slow mode switch received" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 1. "ICPOFIE,ICLC frame for PLL OFF received" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0xC 0. "ICPONIE,ICLC frame for PLL ON received" "0: Interrupt is disabled.,1: Interrupt is enabled." line.long 0x10 "PLLCR,PLL Control Register" bitfld.long 0x10 29.--31. "IPTMOD,Test mode programmability" "0: Functional mode,1: Closed Loop 1,2: Force Vctrl,3: Charge Pump Up,4: Charge Pump Up Internal Test,5: Charge Pump Idle,6: Charge Pump Down,7: Closed Loop 2" bitfld.long 0x10 17. "SWPOFF,Software signal to turn OFF the PLL" "0: No effect,1: PLL will be turned OFF." newline bitfld.long 0x10 16. "SWPON,Software signal to turn ON the PLL" "0: No effect,1: PLL will be turned ON" bitfld.long 0x10 15. "REFINV,Inverts reference clock edge to PFD" "0: Not inverted,1: Invert" newline bitfld.long 0x10 13.--14. "LPCFG,PLL Loop Optimization. Adjusts charge pump bias current. Higher current increases PLL bandwidth decreasing jitter while degrading stability." "0: 1xIBASE,1: 0.5xIBASE,2: 1.5xIBASE,3: 2xIBASE" bitfld.long 0x10 9.--10. "PLCKCW,PLL Lock Ready Count Width" "0: 1040 cycles,1: 520 cycles,2: 320 cycles,3: 200 cycles" newline bitfld.long 0x10 8. "FDIVEN,Enable fraction division mode in feedback divider" "0: Fraction division mode not enabled,1: Fraction division mode enabled" hexmask.long.byte 0x10 2.--7. 1. "FBDIV,Feedback Division factor for VCO output clock" newline bitfld.long 0x10 0.--1. "PREDIV,Division factor for PLL Reference Clock input" "0: Direct clock passed,1: Divide by 2,2: Divide by 3,3: Divide by 4" line.long 0x14 "LCR,LVDS Control Register" bitfld.long 0x14 23. "SWWKLD,Software signal to take LVDS LD out of Sleep mode" "0: No effect,1: LVDS LD will be taken out of sleep (provided no.." bitfld.long 0x14 22. "SWSLPLD,Software signal to put LVDS LD into Sleep mode" "0: No effect,1: LVDS LD will be put in sleep." newline bitfld.long 0x14 21. "SWWKLR,Software signal to take LVDS LR out of Sleep mode" "0: No effect,1: LVDS LR will be taken out of sleep (provided no.." bitfld.long 0x14 20. "SWSLPLR,Software signal to put LVDS LR into Sleep mode" "0: No effect,1: LVDS LR will be put in sleep (provided no other.." newline bitfld.long 0x14 19. "SWOFFLD,Software signal to turn OFF the LVDS LD" "0: No effect,1: LVDS LD will be turned OFF (provided no other.." bitfld.long 0x14 18. "SWONLD,Software signal to turn ON the LVDS LD" "0: No effect,1: LVDS LD will be turned ON." newline bitfld.long 0x14 17. "SWOFFLR,Software signal to turn OFF the LVDS LR" "0: No effect,1: LVDS LR will be turned OFF (provided no other.." bitfld.long 0x14 16. "SWONLR,Software signal to turn ON the LVDS LR" "0: No effect,1: LVDS LR will be turned ON." newline bitfld.long 0x14 15. "LVRXOFF,Indicates the value driven onto LVDS LR output when in shutdown mode." "0,1" bitfld.long 0x14 14. "LVTXOE,LVDS LD output buffer enable" "0: LVDS LD output buffer enable is disabled.,1: LVDS LD output buffer enabled" newline bitfld.long 0x14 13. "TXCMUX,Tx and Clock Mux" "0: No effect,1: PLL Phase 0 clock will be brought out to Tx LVDS.." bitfld.long 0x14 12. "LVRFEN,LVDS pad reference enable" "0: LVDS reference pad disabled,1: LVDS reference pad enabled" newline bitfld.long 0x14 11. "LVLPEN,Tx LVDS internal loopback enable" "0: Tx LVDS normal mode enabled,1: Tx LVDS internal loopback mode enabled" bitfld.long 0x14 5. "LVRXOP_TR,Used to enable or disable the on-chip receiver termination resistor in LFAST mode (applies to LVDS pad use for LFAST only)." "0: Disable on-chip LFAST receiver termination,1: Enable on-chip LFAST receiver termination" newline bitfld.long 0x14 3. "LVRXOP_BR,Used to set the bias current for the receiver in LFAST mode. It is recommended to always write 1 to this bit when using the LFAST interface. Writing 0 will allow for a small power savings during lower baud rates (applies to LVDS pad use for.." "0: Use for LFAST receiver baud rates less than..,1: Required for LFAST receiver maximum baud rate" bitfld.long 0x14 2. "LVTXOP,Control signal for LFAST and Micro-Second Bus selection" "0: Micro-Second Bus selection,1: LFAST Bus selection" newline bitfld.long 0x14 1. "LVCKSS,LVDS Clock Sync Select" "0: Normal clock used to sample the LVDS data,1: Adjusted clock used to sample the LVDS data" bitfld.long 0x14 0. "LVCKP,LVDS clock select" "0: Direct pll clock to be used inside the LVDS,1: Inverted pll clock to be used inside the LVDS" line.long 0x18 "UNSTCR,Unsolicited Tx Control Register" bitfld.long 0x18 16. "USNDRQ,Tx Unsolicited send request. This field can only be written when MCR[DRFEN] = 1." "0: No valid Unsolicited frame exists,1: Valid Unsolicited frame exists for transmission" hexmask.long.byte 0x18 0.--6. 1. "UNSHDR,Tx Unsolicited message header" line.long 0x1C "UNSTDR8,LFAST Unsolicited Tx Data Registers" hexmask.long 0x1C 0.--31. 1. "UNTXD,Unsolicited Transmit Data 80x0:" line.long 0x20 "UNSTDR7,LFAST Unsolicited Tx Data Registers" hexmask.long 0x20 0.--31. 1. "UNTXD,Unsolicited Transmit Data 80x0:" line.long 0x24 "UNSTDR6,LFAST Unsolicited Tx Data Registers" hexmask.long 0x24 0.--31. 1. "UNTXD,Unsolicited Transmit Data 80x0:" line.long 0x28 "UNSTDR5,LFAST Unsolicited Tx Data Registers" hexmask.long 0x28 0.--31. 1. "UNTXD,Unsolicited Transmit Data 80x0:" line.long 0x2C "UNSTDR4,LFAST Unsolicited Tx Data Registers" hexmask.long 0x2C 0.--31. 1. "UNTXD,Unsolicited Transmit Data 80x0:" line.long 0x30 "UNSTDR3,LFAST Unsolicited Tx Data Registers" hexmask.long 0x30 0.--31. 1. "UNTXD,Unsolicited Transmit Data 80x0:" line.long 0x34 "UNSTDR2,LFAST Unsolicited Tx Data Registers" hexmask.long 0x34 0.--31. 1. "UNTXD,Unsolicited Transmit Data 80x0:" line.long 0x38 "UNSTDR1,LFAST Unsolicited Tx Data Registers" hexmask.long 0x38 0.--31. 1. "UNTXD,Unsolicited Transmit Data 80x0:" line.long 0x3C "UNSTDR0,LFAST Unsolicited Tx Data Registers" hexmask.long 0x3C 0.--31. 1. "UNTXD,Unsolicited Transmit Data 80x0:" rgroup.long 0x80++0x7 line.long 0x0 "GSR,Global Status Register" bitfld.long 0x0 31. "DUALMD,Indicates the LFAST module is in Dual mode" "0: LFAST Module Slave only mode,1: LFAST Module in dual mode" bitfld.long 0x0 18. "LRMD,Indicates if the Rx Controller is idle/active and that the Rx clocks are enabled. In functional mode this will always be active." "0: Rx Controller is in Idle state.,1: Rx Controller is active." newline bitfld.long 0x0 17. "LDSM,Transmit Interface Data Rate Status" "0: Data rate of LOW speed mode,1: Data rate of HIGH speed mode" bitfld.long 0x0 16. "DRSM,Receive Interface Data Rate Status" "0: Data rate of LOW speed mode,1: Data rate of HIGH speed mode" newline bitfld.long 0x0 4. "LPTXDN,Auto loopback frame transmission count reached" "0: Auto loopback frame transmission count not reached,1: Auto loopback frame transmission count reached" bitfld.long 0x0 3. "LPFPDV,Loopback frame pass threshold reached" "0: Pass frame threshold not reached,1: Pass frame threshold achieved" newline bitfld.long 0x0 2. "LPCPDV,Valid payload received during loopback check mode" "0: Payload received is not 0xCB.,1: Payload received is 0xCB." bitfld.long 0x0 1. "LPCHDV,Valid header received during loopback check mode" "0: Header received is not 0x13.,1: Header received is 0x13." newline bitfld.long 0x0 0. "LPCSDV,Valid synchronization received" "0: Valid Synchronization pattern not detected,1: Valid Synchronization pattern detected" line.long 0x4 "PISR,Ping Status Register" hexmask.long.byte 0x4 0.--7. 1. "RXPNGD,Ping Data Register" rgroup.long 0x94++0x3 line.long 0x0 "DFSR,Data frame Status Register" hexmask.long.byte 0x0 24.--29. 1. "RXDCNT,Unread Rx Frame Data Count" bitfld.long 0x0 16.--18. "RXFCNT,Unread Rx Frame Count" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--13. 1. "TXDCNT,Unread Tx Frame Data Count" bitfld.long 0x0 0.--2. "TXFCNT,Unread Tx Frame Count" "0,1,2,3,4,5,6,7" group.long 0x98++0xB line.long 0x0 "TISR,Tx Interrupt Status Register" bitfld.long 0x0 17. "TXIEF,Tx Data Interface not enabled" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x0 16. "TXOVF,Transmit Data FIFO Overflow Interrupt" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x0 4. "TXPNGF,Ping response frame transmitted interrupt" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x0 2. "TXUNSF,Unsolicited Frame transmitted Interrupt" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x0 1. "TXICLCF,ICLC Frame transmitted Interrupt" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x0 0. "TXDTF,Data Frame transmitted Interrupt" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." line.long 0x4 "RISR,Rx Interrupt Status Register" bitfld.long 0x4 23. "RXUOF,Unsolicited frame register overflow" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x4 22. "RXMNF,Rx Data FIFO Min Threshold reached" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x4 21. "RXMXF,Rx Data FIFO Max Threshold reached" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x4 20. "RXUFF,Rx Data FIFO Underflow" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x4 19. "RXOFF,Rx Data FIFO Overflow" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x4 18. "RXSZF,Frame with unsupported frame size received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred: On reception of.." newline bitfld.long 0x4 17. "RXICF,Invalid ICLC code Received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x4 16. "RXLCEF,Invalid Logical Channel Type" "0: Interrupt event has not occurred.,1: Interrupt event has occurred: On reception of.." newline bitfld.long 0x4 3. "RXCTSF,Frame with CTS bit Low Received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x4 2. "RXDF,Data frame received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x4 1. "RXUNSF,Unsolicited Frame received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." line.long 0x8 "RIISR,Rx ICLC Interrupt Status Register" bitfld.long 0x8 13. "ICPFF,Ping Frame Response failed" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x8 12. "ICPSF,Ping Frame Response successful" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x8 11. "ICPRF,ICLC Ping Frame Request received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x8 10. "ICTOF,ICLC frame for Test mode off received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x8 9. "ICLPF,ICLC frame for Loopback On received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x8 8. "ICCTF,ICLC frame for Clk Test mode received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x8 7. "ICTDF,ICLC frame for LFAST Slaves Tx Interface Disable received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x8 6. "ICTEF,ICLC frame for LFAST Slaves Tx Interface Enable received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x8 5. "ICRFF,ICLC frame for LFAST Slaves Rx Interface fast mode switch received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x8 4. "ICRSF,ICLC frame for LFAST Slaves Rx Interface slow mode switch received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x8 3. "ICTFF,ICLC frame for LFAST Slaves Tx Interface fast mode switch received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x8 2. "ICTSF,ICLC frame for LFAST Slaves Tx Interface slow mode switch received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." newline bitfld.long 0x8 1. "ICPOFF,ICLC frame for PLL OFF received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." bitfld.long 0x8 0. "ICPONF,ICLC frame for PLL ON received" "0: Interrupt event has not occurred.,1: Interrupt event has occurred." rgroup.long 0xA4++0x3 line.long 0x0 "PLLLSR,PLL and LVDS Status Register" bitfld.long 0x0 17. "PLLDIS,PLL disable Status" "0: PLL disable signal is negated.,1: PLL disable signal is asserted." bitfld.long 0x0 16. "PLDCR,PLL Lock Delay Counter Ready" "0: PLL Lock delay counter is not decremented to 0.,1: PLL Lock delay counter is decremented to 0." newline bitfld.long 0x0 3. "LRSLPS,This bit indicates the real time status of the LR sleep signal." "0: LR sleep signal is negated.,1: LR sleep signal is asserted." bitfld.long 0x0 2. "LDSLPS,This bit indicates the real time status of LD sleep signal." "0: LD power sleep signal is negated.,1: LD power sleep signal is asserted." newline bitfld.long 0x0 1. "LDPDS,This bit indicates the real time status of LD power down signal. When asserted LD is put in the power down state." "0: LD power down signal is negated.,1: LD power down signal is asserted." bitfld.long 0x0 0. "LRPDS,This bit indicates the real time status of LR power down signal. When asserted LR is put in the power down state." "0: LR power down signal is negated.,1: LR power down signal is asserted." group.long 0xA8++0x3 line.long 0x0 "UNSRSR,Unsolicited Rx Status Register" bitfld.long 0x0 8. "URXDV,Unsolicited data valid" "0,1" bitfld.long 0x0 0.--2. "URPCNT,Rx Unsolicited payload" "0,1,2,3,4,5,6,7" rgroup.long 0xAC++0x23 line.long 0x0 "UNSRDR8,Unsolicited Rx Data Registers" hexmask.long 0x0 0.--31. 1. "UNRXD,Unsolicited Receive Data" line.long 0x4 "UNSRDR7,Unsolicited Rx Data Registers" hexmask.long 0x4 0.--31. 1. "UNRXD,Unsolicited Receive Data" line.long 0x8 "UNSRDR6,Unsolicited Rx Data Registers" hexmask.long 0x8 0.--31. 1. "UNRXD,Unsolicited Receive Data" line.long 0xC "UNSRDR5,Unsolicited Rx Data Registers" hexmask.long 0xC 0.--31. 1. "UNRXD,Unsolicited Receive Data" line.long 0x10 "UNSRDR4,Unsolicited Rx Data Registers" hexmask.long 0x10 0.--31. 1. "UNRXD,Unsolicited Receive Data" line.long 0x14 "UNSRDR3,Unsolicited Rx Data Registers" hexmask.long 0x14 0.--31. 1. "UNRXD,Unsolicited Receive Data" line.long 0x18 "UNSRDR2,Unsolicited Rx Data Registers" hexmask.long 0x18 0.--31. 1. "UNRXD,Unsolicited Receive Data" line.long 0x1C "UNSRDR1,Unsolicited Rx Data Registers" hexmask.long 0x1C 0.--31. 1. "UNRXD,Unsolicited Receive Data" line.long 0x20 "UNSRDR0,Unsolicited Rx Data Registers" hexmask.long 0x20 0.--31. 1. "UNRXD,Unsolicited Receive Data" tree.end tree.end tree "LINFLEXD" base ad:0x0 tree "LINFLEXD_0" base ad:0x720B8000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x4B line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" line.long 0x4 "IFCR0,Identifier Filter Control Register" hexmask.long.byte 0x4 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x4 9. "DIR,Direction" "0: LINFlexD receives data and copies to the BDR..,1: LINFlexD transmits data from the BDR registers" newline bitfld.long 0x4 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x4 0.--5. 1. "ID,Identifier" line.long 0x8 "IFCR1,Identifier Filter Control Register" hexmask.long.byte 0x8 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x8 9. "DIR,Direction" "0: LINFlexD receives data and copies to the BDR..,1: LINFlexD transmits data from the BDR registers" newline bitfld.long 0x8 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x8 0.--5. 1. "ID,Identifier" line.long 0xC "IFCR2,Identifier Filter Control Register" hexmask.long.byte 0xC 10.--15. 1. "DFL,Data Field Length" bitfld.long 0xC 9. "DIR,Direction" "0: LINFlexD receives data and copies to the BDR..,1: LINFlexD transmits data from the BDR registers" newline bitfld.long 0xC 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0xC 0.--5. 1. "ID,Identifier" line.long 0x10 "IFCR3,Identifier Filter Control Register" hexmask.long.byte 0x10 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x10 9. "DIR,Direction" "0: LINFlexD receives data and copies to the BDR..,1: LINFlexD transmits data from the BDR registers" newline bitfld.long 0x10 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x10 0.--5. 1. "ID,Identifier" line.long 0x14 "IFCR4,Identifier Filter Control Register" hexmask.long.byte 0x14 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x14 9. "DIR,Direction" "0: LINFlexD receives data and copies to the BDR..,1: LINFlexD transmits data from the BDR registers" newline bitfld.long 0x14 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x14 0.--5. 1. "ID,Identifier" line.long 0x18 "IFCR5,Identifier Filter Control Register" hexmask.long.byte 0x18 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x18 9. "DIR,Direction" "0: LINFlexD receives data and copies to the BDR..,1: LINFlexD transmits data from the BDR registers" newline bitfld.long 0x18 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x18 0.--5. 1. "ID,Identifier" line.long 0x1C "IFCR6,Identifier Filter Control Register" hexmask.long.byte 0x1C 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x1C 9. "DIR,Direction" "0: LINFlexD receives data and copies to the BDR..,1: LINFlexD transmits data from the BDR registers" newline bitfld.long 0x1C 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x1C 0.--5. 1. "ID,Identifier" line.long 0x20 "IFCR7,Identifier Filter Control Register" hexmask.long.byte 0x20 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x20 9. "DIR,Direction" "0: LINFlexD receives data and copies to the BDR..,1: LINFlexD transmits data from the BDR registers" newline bitfld.long 0x20 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x20 0.--5. 1. "ID,Identifier" line.long 0x24 "IFCR8,Identifier Filter Control Register" hexmask.long.byte 0x24 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x24 9. "DIR,Direction" "0: LINFlexD receives data and copies to the BDR..,1: LINFlexD transmits data from the BDR registers" newline bitfld.long 0x24 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x24 0.--5. 1. "ID,Identifier" line.long 0x28 "IFCR9,Identifier Filter Control Register" hexmask.long.byte 0x28 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x28 9. "DIR,Direction" "0: LINFlexD receives data and copies to the BDR..,1: LINFlexD transmits data from the BDR registers" newline bitfld.long 0x28 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x28 0.--5. 1. "ID,Identifier" line.long 0x2C "IFCR10,Identifier Filter Control Register" hexmask.long.byte 0x2C 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x2C 9. "DIR,Direction" "0: LINFlexD receives data and copies to the BDR..,1: LINFlexD transmits data from the BDR registers" newline bitfld.long 0x2C 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x2C 0.--5. 1. "ID,Identifier" line.long 0x30 "IFCR11,Identifier Filter Control Register" hexmask.long.byte 0x30 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x30 9. "DIR,Direction" "0: LINFlexD receives data and copies to the BDR..,1: LINFlexD transmits data from the BDR registers" newline bitfld.long 0x30 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x30 0.--5. 1. "ID,Identifier" line.long 0x34 "IFCR12,Identifier Filter Control Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives data and copies to the BDR..,1: LINFlexD transmits data from the BDR registers" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "IFCR13,Identifier Filter Control Register" hexmask.long.byte 0x38 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x38 9. "DIR,Direction" "0: LINFlexD receives data and copies to the BDR..,1: LINFlexD transmits data from the BDR registers" newline bitfld.long 0x38 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x38 0.--5. 1. "ID,Identifier" line.long 0x3C "IFCR14,Identifier Filter Control Register" hexmask.long.byte 0x3C 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x3C 9. "DIR,Direction" "0: LINFlexD receives data and copies to the BDR..,1: LINFlexD transmits data from the BDR registers" newline bitfld.long 0x3C 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x3C 0.--5. 1. "ID,Identifier" line.long 0x40 "IFCR15,Identifier Filter Control Register" hexmask.long.byte 0x40 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x40 9. "DIR,Direction" "0: LINFlexD receives data and copies to the BDR..,1: LINFlexD transmits data from the BDR registers" newline bitfld.long 0x40 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x40 0.--5. 1. "ID,Identifier" line.long 0x44 "GCR,Global Control Register" bitfld.long 0x44 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x44 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x44 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x44 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x44 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x44 0. "SR,Soft reset" "0,1" line.long 0x48 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x48 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" group.long 0x98++0x7 line.long 0x0 "DMATXE,DMA Tx Enable Register" bitfld.long 0x0 0. "DTE,DMA Tx channel Y enable" "0: DMA Tx channel Y disabled,1: DMA Tx channel Y enabled" line.long 0x4 "DMARXE,DMA Rx Enable Register" bitfld.long 0x4 0. "DRE,DMA Rx channel Y enable" "0: DMA Rx channel Y disabled,1: DMA Rx channel Y enabled" tree.end tree "LINFLEXD_1" base ad:0x720BC000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" group.long 0x98++0x7 line.long 0x0 "DMATXE,DMA Tx Enable Register" bitfld.long 0x0 0. "DTE,DMA Tx channel Y enable" "0: DMA Tx channel Y disabled,1: DMA Tx channel Y enabled" line.long 0x4 "DMARXE,DMA Rx Enable Register" bitfld.long 0x4 0. "DRE,DMA Rx channel Y enable" "0: DMA Rx channel Y disabled,1: DMA Rx channel Y enabled" tree.end tree "LINFLEXD_2" base ad:0x70EBC000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" group.long 0x98++0x7 line.long 0x0 "DMATXE,DMA Tx Enable Register" bitfld.long 0x0 0. "DTE,DMA Tx channel Y enable" "0: DMA Tx channel Y disabled,1: DMA Tx channel Y enabled" line.long 0x4 "DMARXE,DMA Rx Enable Register" bitfld.long 0x4 0. "DRE,DMA Rx channel Y enable" "0: DMA Rx channel Y disabled,1: DMA Rx channel Y enabled" tree.end tree "LINFLEXD_3" base ad:0x714BC000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" group.long 0x98++0x7 line.long 0x0 "DMATXE,DMA Tx Enable Register" bitfld.long 0x0 0. "DTE,DMA Tx channel Y enable" "0: DMA Tx channel Y disabled,1: DMA Tx channel Y enabled" line.long 0x4 "DMARXE,DMA Rx Enable Register" bitfld.long 0x4 0. "DRE,DMA Rx channel Y enable" "0: DMA Rx channel Y disabled,1: DMA Rx channel Y enabled" tree.end tree "LINFLEXD_4" base ad:0x70EC0000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" group.long 0x98++0x7 line.long 0x0 "DMATXE,DMA Tx Enable Register" bitfld.long 0x0 0. "DTE,DMA Tx channel Y enable" "0: DMA Tx channel Y disabled,1: DMA Tx channel Y enabled" line.long 0x4 "DMARXE,DMA Rx Enable Register" bitfld.long 0x4 0. "DRE,DMA Rx channel Y enable" "0: DMA Rx channel Y disabled,1: DMA Rx channel Y enabled" tree.end tree "LINFLEXD_5" base ad:0x714C0000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" group.long 0x98++0x7 line.long 0x0 "DMATXE,DMA Tx Enable Register" bitfld.long 0x0 0. "DTE,DMA Tx channel Y enable" "0: DMA Tx channel Y disabled,1: DMA Tx channel Y enabled" line.long 0x4 "DMARXE,DMA Rx Enable Register" bitfld.long 0x4 0. "DRE,DMA Rx channel Y enable" "0: DMA Rx channel Y disabled,1: DMA Rx channel Y enabled" tree.end tree "LINFLEXD_6" base ad:0x70EC4000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" group.long 0x98++0x7 line.long 0x0 "DMATXE,DMA Tx Enable Register" bitfld.long 0x0 0. "DTE,DMA Tx channel Y enable" "0: DMA Tx channel Y disabled,1: DMA Tx channel Y enabled" line.long 0x4 "DMARXE,DMA Rx Enable Register" bitfld.long 0x4 0. "DRE,DMA Rx channel Y enable" "0: DMA Rx channel Y disabled,1: DMA Rx channel Y enabled" tree.end tree "LINFLEXD_7" base ad:0x714C4000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" group.long 0x98++0x7 line.long 0x0 "DMATXE,DMA Tx Enable Register" bitfld.long 0x0 0. "DTE,DMA Tx channel Y enable" "0: DMA Tx channel Y disabled,1: DMA Tx channel Y enabled" line.long 0x4 "DMARXE,DMA Rx Enable Register" bitfld.long 0x4 0. "DRE,DMA Rx channel Y enable" "0: DMA Rx channel Y disabled,1: DMA Rx channel Y enabled" tree.end tree "LINFLEXD_8" base ad:0x70EC8000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" group.long 0x98++0x7 line.long 0x0 "DMATXE,DMA Tx Enable Register" bitfld.long 0x0 0. "DTE,DMA Tx channel Y enable" "0: DMA Tx channel Y disabled,1: DMA Tx channel Y enabled" line.long 0x4 "DMARXE,DMA Rx Enable Register" bitfld.long 0x4 0. "DRE,DMA Rx channel Y enable" "0: DMA Rx channel Y disabled,1: DMA Rx channel Y enabled" tree.end tree "LINFLEXD_9" base ad:0x714C8000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" group.long 0x98++0x7 line.long 0x0 "DMATXE,DMA Tx Enable Register" bitfld.long 0x0 0. "DTE,DMA Tx channel Y enable" "0: DMA Tx channel Y disabled,1: DMA Tx channel Y enabled" line.long 0x4 "DMARXE,DMA Rx Enable Register" bitfld.long 0x4 0. "DRE,DMA Rx channel Y enable" "0: DMA Rx channel Y disabled,1: DMA Rx channel Y enabled" tree.end tree "LINFLEXD_10" base ad:0x70ECC000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" group.long 0x98++0x7 line.long 0x0 "DMATXE,DMA Tx Enable Register" bitfld.long 0x0 0. "DTE,DMA Tx channel Y enable" "0: DMA Tx channel Y disabled,1: DMA Tx channel Y enabled" line.long 0x4 "DMARXE,DMA Rx Enable Register" bitfld.long 0x4 0. "DRE,DMA Rx channel Y enable" "0: DMA Rx channel Y disabled,1: DMA Rx channel Y enabled" tree.end tree "LINFLEXD_11" base ad:0x714CC000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" group.long 0x98++0x7 line.long 0x0 "DMATXE,DMA Tx Enable Register" bitfld.long 0x0 0. "DTE,DMA Tx channel Y enable" "0: DMA Tx channel Y disabled,1: DMA Tx channel Y enabled" line.long 0x4 "DMARXE,DMA Rx Enable Register" bitfld.long 0x4 0. "DRE,DMA Rx channel Y enable" "0: DMA Rx channel Y disabled,1: DMA Rx channel Y enabled" tree.end tree "LINFLEXD_12" base ad:0x70ED0000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" group.long 0x98++0x7 line.long 0x0 "DMATXE,DMA Tx Enable Register" bitfld.long 0x0 0. "DTE,DMA Tx channel Y enable" "0: DMA Tx channel Y disabled,1: DMA Tx channel Y enabled" line.long 0x4 "DMARXE,DMA Rx Enable Register" bitfld.long 0x4 0. "DRE,DMA Rx channel Y enable" "0: DMA Rx channel Y disabled,1: DMA Rx channel Y enabled" tree.end tree "LINFLEXD_13" base ad:0x714D0000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" group.long 0x98++0x7 line.long 0x0 "DMATXE,DMA Tx Enable Register" bitfld.long 0x0 0. "DTE,DMA Tx channel Y enable" "0: DMA Tx channel Y disabled,1: DMA Tx channel Y enabled" line.long 0x4 "DMARXE,DMA Rx Enable Register" bitfld.long 0x4 0. "DRE,DMA Rx channel Y enable" "0: DMA Rx channel Y disabled,1: DMA Rx channel Y enabled" tree.end tree "LINFLEXD_14" base ad:0x70ED4000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" tree.end tree "LINFLEXD_15" base ad:0x714D4000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" tree.end tree "LINFLEXD_16" base ad:0x70ED8000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" tree.end tree "LINFLEXD_17" base ad:0x714D8000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" tree.end tree "LINFLEXD_18" base ad:0x70EDC000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" tree.end tree "LINFLEXD_19" base ad:0x714DC000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" tree.end tree "LINFLEXD_20" base ad:0x70E90000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" tree.end tree "LINFLEXD_21" base ad:0x71490000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" tree.end tree "LINFLEXD_22" base ad:0x70E94000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" tree.end tree "LINFLEXD_23" base ad:0x71494000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" tree.end tree "LINFLEXD_24" base ad:0x70E98000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" tree.end tree "LINFLEXD_25" base ad:0x71498000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" tree.end tree "LINFLEXD_26" base ad:0x70E9C000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" tree.end tree "LINFLEXD_27" base ad:0x7149C000 group.long 0x0++0x43 line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 15. "CCD,Calculation disable" "0: Checksum calculation is done by hardware. When..,1: Checksum calculation is disabled. When this bit.." bitfld.long 0x0 14. "CFD,Checksum field disable" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" newline bitfld.long 0x0 13. "LASE,LIN Auto Synchronization Enable" "0: Auto synchronization disabled,1: Auto synchronization enabled" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length" bitfld.long 0x0 7. "BF,By-pass filter" "0: No IRQ if ID does not match any filter,1: A RX IRQ is generated on ID not matching any.." newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" bitfld.long 0x0 4. "MME,Master mode enable" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length" "0: 11-bit break length,1: 10-bit break length" bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode" "0: Receiver Buffer not locked next incoming message..,1: Receiver buffer locked against overrun. Once the.." newline bitfld.long 0x0 1. "SLEEP,Sleep Mode Request" "0,1" bitfld.long 0x0 0. "INIT,Initialization Mode Request" "0,1" line.long 0x4 "LINIER,LIN Interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN state Interrupt enable" "0: No interrupt,1: Interrupt generated on entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 4. "DBFIE,Data Buffer Full Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 3. "DBEIE_TOIE,Data Buffer Empty Interrupt enable/Timeout Interrupt Enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 0. "HRIE,Header Received Interrupt" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" bitfld.long 0x8 19. "AUTOSYNC_COMP,Autosynchronization Completed" "0,1" bitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" newline hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN state" bitfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free. Reset by hardware in when..,1: Buffer data ready to be read by software." newline bitfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty Flag" "0,1" bitfld.long 0x8 7. "RXBUSY,Receiver Busy flag" "0: Receiver is idle,1: Reception ongoing" newline bitfld.long 0x8 6. "RDI,LIN Receive signal" "0,1" bitfld.long 0x8 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x8 4. "DBFF,Data Buffer full flag" "0,1" bitfld.long 0x8 3. "DBEF,Data Buffer empty flag" "0,1" newline bitfld.long 0x8 2. "DRF,Data Reception Completed flag" "0,1" bitfld.long 0x8 1. "DTF,Data Transmission Completed flag" "0,1" newline bitfld.long 0x8 0. "HRF,Header Received flag" "0,1" line.long 0xC "LINESR,LIN Error Status Register" bitfld.long 0xC 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline bitfld.long 0xC 13. "BEF,Bit Error flag" "0,1" bitfld.long 0xC 12. "CEF,Checksum Error flag" "0,1" newline bitfld.long 0xC 11. "SFEF,Sync Field Error flag" "0,1" bitfld.long 0xC 10. "SDEF,Sync Delimiter Error flag" "0,1" newline bitfld.long 0xC 9. "IDPEF,ID Parity Error flag" "0,1" bitfld.long 0xC 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0xC 7. "BOF,Buffer overrun flag" "0,1" bitfld.long 0xC 0. "NF,Noise flag" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point (i)" "?,?,?,?,4: CSP 2,5: CSP 2,6: CSP 3,?" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frame" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop bits in UART reception mode" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 16. "WLS,Special Word Length in UART mode" "0: This bit is disabled.,1: This bit enables 12-bit + parity bit in.." newline bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter" "0: empty,1: 1-byte,2: 2-bytes,3: 3-bytes,4: 4-bytes,?,?,?" bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter" "0: Empty,1: 1-byte,2: 2-bytes/1.5 byte in case of WLS bit setting,3: 3-bytes,4: 4-bytes/2×1.5 byte in case of WLS bit setting,?,?,?" newline bitfld.long 0x10 9. "RFBM,RFBM Rx FIFO/Buffer mode" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer mode" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" newline bitfld.long 0x10 7. "WL1,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 6. "PC1,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" newline bitfld.long 0x10 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" bitfld.long 0x10 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x10 3. "PC0,Parity Control" "0: Parity sent is Even,1: Parity sent is Odd" bitfld.long 0x10 2. "PCE,Parity Control Enable" "0: Parity transmission reception and checking..,1: Parity transmission reception and checking enabled" newline bitfld.long 0x10 1. "WL0,Word Length in UART mode" "0: 7 bits data + parity,1: 8 bits data when PCE = 0 or 8 bits data + parity.." bitfld.long 0x10 0. "UART,UART Mode" "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" bitfld.long 0x14 15. "SZF,Stuck at Zero flag" "0,1" bitfld.long 0x14 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error flag" bitfld.long 0x14 9. "RMB,Release Message Buffer" "0: Buffer data is free,1: Buffer data ready to be read by software" newline bitfld.long 0x14 8. "FEF,Framing Error flag" "0,1" bitfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag" "0,1" newline bitfld.long 0x14 6. "RDI,Receiver Data Input signal" "0,1" bitfld.long 0x14 5. "WUF,Wakeup flag" "0,1" newline bitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty" "0,1" bitfld.long 0x14 3. "TO,Timeout" "0,1" newline bitfld.long 0x14 2. "DRF_RFE,Data Reception Completed Flag/Rx FIFO Empty Flag" "0,1" bitfld.long 0x14 1. "DTF_TFF,Data Transmission Completed Flag/TX FIFO Full Flag" "0,1" newline bitfld.long 0x14 0. "NF,Noise flag" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates" line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" hexmask.long.byte 0x34 10.--15. 1. "DFL,Data Field Length" bitfld.long 0x34 9. "DIR,Direction" "0: LINFlexD receives the data and copies them in..,1: LINFlexD transmits the data from the BDRs" newline bitfld.long 0x34 8. "CCS,Classic Checksum" "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data field only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3" hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2" newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1" hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0" line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7" hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6" newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5" hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4" line.long 0x40 "IFER,Identifier Filter Enable Register" hexmask.long.word 0x40 0.--15. 1. "FACT,Filter active" rgroup.long 0x44++0x3 line.long 0x0 "IFMI,Identifier Filter Match Index" hexmask.long.byte 0x0 0.--4. 1. "IFMI,Filter match index" group.long 0x48++0x3 line.long 0x0 "IFMR,Identifier Filter Mode Register" hexmask.long.byte 0x0 0.--7. 1. "IFM,Filter mode" group.long 0x8C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout" rgroup.long 0x94++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout" tree.end tree.end tree "MC_CGM (Clock Generation Module)" base ad:0x0 tree "MC_CGM_DOMAIN_0" base ad:0x710C0600 group.byte 0x103++0x0 line.byte 0x0 "PCS_SDUR,PCS switch duration register" hexmask.byte 0x0 0.--7. 1. "SDUR,Switch Duration" group.long 0x104++0x3B line.long 0x0 "PCS_DIVC1,PCS divider change register 1" hexmask.long.word 0x0 16.--31. 1. "INIT,Divider Change Initial Value" hexmask.long.byte 0x0 0.--7. 1. "RATE,Divider Change Rate" line.long 0x4 "PCS_DIVE1,PCS divider end register 1" hexmask.long.tbyte 0x4 0.--19. 1. "DIVE,Divider End Value" line.long 0x8 "PCS_DIVS1,PCS divider start register 1" hexmask.long.tbyte 0x8 0.--19. 1. "DIVS,Divider Start Value" line.long 0xC "PCS_DIVC2,PCS divider change register 2" hexmask.long.word 0xC 16.--31. 1. "INIT,Divider Change Initial Value" hexmask.long.byte 0xC 0.--7. 1. "RATE,Divider Change Rate" line.long 0x10 "PCS_DIVE2,PCS divider end register 2" hexmask.long.tbyte 0x10 0.--19. 1. "DIVE,Divider End Value" line.long 0x14 "PCS_DIVS2,PCS divider start register 2" hexmask.long.tbyte 0x14 0.--19. 1. "DIVS,Divider Start Value" line.long 0x18 "PCS_DIVC3,PCS divider change register 3" hexmask.long.word 0x18 16.--31. 1. "INIT,Divider Change Initial Value" hexmask.long.byte 0x18 0.--7. 1. "RATE,Divider Change Rate" line.long 0x1C "PCS_DIVE3,PCS divider end register 3" hexmask.long.tbyte 0x1C 0.--19. 1. "DIVE,Divider End Value" line.long 0x20 "PCS_DIVS3,PCS divider start register 3" hexmask.long.tbyte 0x20 0.--19. 1. "DIVS,Divider Start Value" line.long 0x24 "PCS_DIVC4,PCS divider change register 4" hexmask.long.word 0x24 16.--31. 1. "INIT,Divider Change Initial Value" hexmask.long.byte 0x24 0.--7. 1. "RATE,Divider Change Rate" line.long 0x28 "PCS_DIVE4,PCS divider end register 4" hexmask.long.tbyte 0x28 0.--19. 1. "DIVE,Divider End Value" line.long 0x2C "PCS_DIVS4,PCS divider start register 4" hexmask.long.tbyte 0x2C 0.--19. 1. "DIVS,Divider Start Value" line.long 0x30 "PCS_DIVC5,PCS divider change register 5" hexmask.long.word 0x30 16.--31. 1. "INIT,Divider Change Initial Value" hexmask.long.byte 0x30 0.--7. 1. "RATE,Divider Change Rate" line.long 0x34 "PCS_DIVE5,PCS divider end register 5" hexmask.long.tbyte 0x34 0.--19. 1. "DIVE,Divider End Value" line.long 0x38 "PCS_DIVS5,PCS divider start register 5" hexmask.long.tbyte 0x38 0.--19. 1. "DIVS,Divider Start Value" group.long 0x1D0++0xB line.long 0x0 "SC_DIV_RC,System clock divider ratio change register" bitfld.long 0x0 0. "SYS_DIV_RATIO_CHNG,System Clock Divider Ratio Change" "0: The system clock divider ratios does not change..,1: The system clock divider ratios changes with the.." line.long 0x4 "DIV_UPD_TYPE,Divider update type register" bitfld.long 0x4 31. "SYS_UPD_TYPE,System Clock Divider Update Type" "0: The configuration for each system clock divider..,1: The configuration for each system clock divider.." line.long 0x8 "DIV_UPD_TRIG,Divider update trigger register" hexmask.long 0x8 0.--31. 1. "DIV_UPD_TRIGGER,Writing any value to this register causes all dividers that have corresponding bits set to '1' in the DIV_UPD_TYPE register and have pre-loaded configurations to be updated immediately. Reading this register always returns all zeros." rgroup.long 0x1DC++0x3 line.long 0x0 "DIV_UPD_STAT,Divider update status register" bitfld.long 0x0 31. "SYS_UPD_STAT,System Clock Divider Update Status" "0: The configuration for at least one system clock..,1: The configuration for at least one system clock.." rgroup.long 0x1E4++0x3 line.long 0x0 "SC_SS,System clock select status register" hexmask.long.byte 0x0 24.--27. 1. "SELSTAT,System Clock Source Selection Status" bitfld.long 0x0 17.--19. "SWTRG,Switch Trigger cause" "?,1: switch after request from MC_ME succeeded,2: switch after request from MC_ME failed due..,3: switch after request from MC_ME failed due..,4: switch to IRCOSC due to SAFE mode request or..,5: switch to IRCOSC due to SAFE mode request or..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch In Progress" "0: clock source switching has completed,1: clock source switching is in progress" group.long 0x1E8++0x13 line.long 0x0 "SC_DC0,System clock divider 0 configuration register" bitfld.long 0x0 31. "DE,Divider 0 Enable" "0,1" bitfld.long 0x0 16.--18. "DIV,Divider 0 Division Value" "0,1,2,3,4,5,6,7" line.long 0x4 "SC_DC1,System clock divider 1 configuration register" bitfld.long 0x4 31. "DE,Divider 1 Enable" "0,1" bitfld.long 0x4 16.--18. "DIV,Divider 1 Division Value" "0,1,2,3,4,5,6,7" line.long 0x8 "SC_DC2,System clock divider 2 configuration register" bitfld.long 0x8 31. "DE,Divider 2 Enable" "0,1" hexmask.long.byte 0x8 16.--21. 1. "DIV,Divider 2 Division Value" line.long 0xC "SC_DC3,System clock divider 3 configuration register" bitfld.long 0xC 31. "DE,Divider 3 Enable" "0,1" hexmask.long.byte 0xC 16.--21. 1. "DIV,Divider 3 Division Value" line.long 0x10 "SC_DC4,System clock divider 4 configuration register" bitfld.long 0x10 31. "DE,Divider 4 Enable" "0,1" bitfld.long 0x10 16.--17. "DIV,Divider 4 Division Value" "0,1,2,3" group.long 0x200++0x3 line.long 0x0 "AC0_SC,Auxiliary clock 0 select control register" hexmask.long.byte 0x0 24.--27. 1. "SELCTL,Auxiliary Clock 0 Source Selection Control" rgroup.long 0x204++0x3 line.long 0x0 "AC0_SS,Auxiliary clock 0 select status register" hexmask.long.byte 0x0 24.--27. 1. "SELSTAT,Auxiliary Clock 1 Source Selection Status" tree.end tree "MC_CGM_DOMAIN_1" base ad:0x716C0600 group.byte 0x103++0x0 line.byte 0x0 "PCS_SDUR,PCS switch duration register" hexmask.byte 0x0 0.--7. 1. "SDUR,Switch Duration" group.long 0x104++0x3B line.long 0x0 "PCS_DIVC1,PCS divider change register 1" hexmask.long.word 0x0 16.--31. 1. "INIT,Divider Change Initial Value" hexmask.long.byte 0x0 0.--7. 1. "RATE,Divider Change Rate" line.long 0x4 "PCS_DIVE1,PCS divider end register 1" hexmask.long.tbyte 0x4 0.--19. 1. "DIVE,Divider End Value" line.long 0x8 "PCS_DIVS1,PCS divider start register 1" hexmask.long.tbyte 0x8 0.--19. 1. "DIVS,Divider Start Value" line.long 0xC "PCS_DIVC2,PCS divider change register 2" hexmask.long.word 0xC 16.--31. 1. "INIT,Divider Change Initial Value" hexmask.long.byte 0xC 0.--7. 1. "RATE,Divider Change Rate" line.long 0x10 "PCS_DIVE2,PCS divider end register 2" hexmask.long.tbyte 0x10 0.--19. 1. "DIVE,Divider End Value" line.long 0x14 "PCS_DIVS2,PCS divider start register 2" hexmask.long.tbyte 0x14 0.--19. 1. "DIVS,Divider Start Value" line.long 0x18 "PCS_DIVC3,PCS divider change register 3" hexmask.long.word 0x18 16.--31. 1. "INIT,Divider Change Initial Value" hexmask.long.byte 0x18 0.--7. 1. "RATE,Divider Change Rate" line.long 0x1C "PCS_DIVE3,PCS divider end register 3" hexmask.long.tbyte 0x1C 0.--19. 1. "DIVE,Divider End Value" line.long 0x20 "PCS_DIVS3,PCS divider start register 3" hexmask.long.tbyte 0x20 0.--19. 1. "DIVS,Divider Start Value" line.long 0x24 "PCS_DIVC4,PCS divider change register 4" hexmask.long.word 0x24 16.--31. 1. "INIT,Divider Change Initial Value" hexmask.long.byte 0x24 0.--7. 1. "RATE,Divider Change Rate" line.long 0x28 "PCS_DIVE4,PCS divider end register 4" hexmask.long.tbyte 0x28 0.--19. 1. "DIVE,Divider End Value" line.long 0x2C "PCS_DIVS4,PCS divider start register 4" hexmask.long.tbyte 0x2C 0.--19. 1. "DIVS,Divider Start Value" line.long 0x30 "PCS_DIVC5,PCS divider change register 5" hexmask.long.word 0x30 16.--31. 1. "INIT,Divider Change Initial Value" hexmask.long.byte 0x30 0.--7. 1. "RATE,Divider Change Rate" line.long 0x34 "PCS_DIVE5,PCS divider end register 5" hexmask.long.tbyte 0x34 0.--19. 1. "DIVE,Divider End Value" line.long 0x38 "PCS_DIVS5,PCS divider start register 5" hexmask.long.tbyte 0x38 0.--19. 1. "DIVS,Divider Start Value" group.long 0x1D0++0xB line.long 0x0 "SC_DIV_RC,System clock divider ratio change register" bitfld.long 0x0 0. "SYS_DIV_RATIO_CHNG,System Clock Divider Ratio Change" "0: The system clock divider ratios does not change..,1: The system clock divider ratios changes with the.." line.long 0x4 "DIV_UPD_TYPE,Divider update type register" bitfld.long 0x4 31. "SYS_UPD_TYPE,System Clock Divider Update Type" "0: The configuration for each system clock divider..,1: The configuration for each system clock divider.." line.long 0x8 "DIV_UPD_TRIG,Divider update trigger register" hexmask.long 0x8 0.--31. 1. "DIV_UPD_TRIGGER,Writing any value to this register causes all dividers that have corresponding bits set to '1' in the DIV_UPD_TYPE register and have pre-loaded configurations to be updated immediately. Reading this register always returns all zeros." rgroup.long 0x1DC++0x3 line.long 0x0 "DIV_UPD_STAT,Divider update status register" bitfld.long 0x0 31. "SYS_UPD_STAT,System Clock Divider Update Status" "0: The configuration for at least one system clock..,1: The configuration for at least one system clock.." rgroup.long 0x1E4++0x3 line.long 0x0 "SC_SS,System clock select status register" hexmask.long.byte 0x0 24.--27. 1. "SELSTAT,System Clock Source Selection Status" bitfld.long 0x0 17.--19. "SWTRG,Switch Trigger cause" "?,1: switch after request from MC_ME succeeded,2: switch after request from MC_ME failed due..,3: switch after request from MC_ME failed due..,4: switch to IRCOSC due to SAFE mode request or..,5: switch to IRCOSC due to SAFE mode request or..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch In Progress" "0: clock source switching has completed,1: clock source switching is in progress" group.long 0x1E8++0x7 line.long 0x0 "SC_DC0,System clock divider 0 configuration register" bitfld.long 0x0 31. "DE,Divider 0 Enable" "0,1" bitfld.long 0x0 16.--18. "DIV,Divider 0 Division Value" "0,1,2,3,4,5,6,7" line.long 0x4 "SC_DC1,System clock divider 1 configuration register" bitfld.long 0x4 31. "DE,Divider 1 Enable" "0,1" bitfld.long 0x4 16.--18. "DIV,Divider 1 Division Value" "0,1,2,3,4,5,6,7" group.long 0x200++0x3 line.long 0x0 "AC0_SC,Auxiliary clock 0 select control register" hexmask.long.byte 0x0 24.--27. 1. "SELCTL,Auxiliary Clock 0 Source Selection Control" rgroup.long 0x204++0x3 line.long 0x0 "AC0_SS,Auxiliary clock 0 select status register" hexmask.long.byte 0x0 24.--27. 1. "SELSTAT,Auxiliary Clock 1 Source Selection Status" tree.end tree "MC_CGM_DOMAIN_2" base ad:0x710C4600 group.byte 0x103++0x0 line.byte 0x0 "PCS_SDUR,PCS switch duration register" hexmask.byte 0x0 0.--7. 1. "SDUR,Switch Duration" group.long 0x104++0x3B line.long 0x0 "PCS_DIVC1,PCS divider change register 1" hexmask.long.word 0x0 16.--31. 1. "INIT,Divider Change Initial Value" hexmask.long.byte 0x0 0.--7. 1. "RATE,Divider Change Rate" line.long 0x4 "PCS_DIVE1,PCS divider end register 1" hexmask.long.tbyte 0x4 0.--19. 1. "DIVE,Divider End Value" line.long 0x8 "PCS_DIVS1,PCS divider start register 1" hexmask.long.tbyte 0x8 0.--19. 1. "DIVS,Divider Start Value" line.long 0xC "PCS_DIVC2,PCS divider change register 2" hexmask.long.word 0xC 16.--31. 1. "INIT,Divider Change Initial Value" hexmask.long.byte 0xC 0.--7. 1. "RATE,Divider Change Rate" line.long 0x10 "PCS_DIVE2,PCS divider end register 2" hexmask.long.tbyte 0x10 0.--19. 1. "DIVE,Divider End Value" line.long 0x14 "PCS_DIVS2,PCS divider start register 2" hexmask.long.tbyte 0x14 0.--19. 1. "DIVS,Divider Start Value" line.long 0x18 "PCS_DIVC3,PCS divider change register 3" hexmask.long.word 0x18 16.--31. 1. "INIT,Divider Change Initial Value" hexmask.long.byte 0x18 0.--7. 1. "RATE,Divider Change Rate" line.long 0x1C "PCS_DIVE3,PCS divider end register 3" hexmask.long.tbyte 0x1C 0.--19. 1. "DIVE,Divider End Value" line.long 0x20 "PCS_DIVS3,PCS divider start register 3" hexmask.long.tbyte 0x20 0.--19. 1. "DIVS,Divider Start Value" line.long 0x24 "PCS_DIVC4,PCS divider change register 4" hexmask.long.word 0x24 16.--31. 1. "INIT,Divider Change Initial Value" hexmask.long.byte 0x24 0.--7. 1. "RATE,Divider Change Rate" line.long 0x28 "PCS_DIVE4,PCS divider end register 4" hexmask.long.tbyte 0x28 0.--19. 1. "DIVE,Divider End Value" line.long 0x2C "PCS_DIVS4,PCS divider start register 4" hexmask.long.tbyte 0x2C 0.--19. 1. "DIVS,Divider Start Value" line.long 0x30 "PCS_DIVC5,PCS divider change register 5" hexmask.long.word 0x30 16.--31. 1. "INIT,Divider Change Initial Value" hexmask.long.byte 0x30 0.--7. 1. "RATE,Divider Change Rate" line.long 0x34 "PCS_DIVE5,PCS divider end register 5" hexmask.long.tbyte 0x34 0.--19. 1. "DIVE,Divider End Value" line.long 0x38 "PCS_DIVS5,PCS divider start register 5" hexmask.long.tbyte 0x38 0.--19. 1. "DIVS,Divider Start Value" group.long 0x1D0++0xB line.long 0x0 "SC_DIV_RC,System clock divider ratio change register" bitfld.long 0x0 0. "SYS_DIV_RATIO_CHNG,System Clock Divider Ratio Change" "0: The system clock divider ratios does not change..,1: The system clock divider ratios changes with the.." line.long 0x4 "DIV_UPD_TYPE,Divider update type register" bitfld.long 0x4 31. "SYS_UPD_TYPE,System Clock Divider Update Type" "0: The configuration for each system clock divider..,1: The configuration for each system clock divider.." line.long 0x8 "DIV_UPD_TRIG,Divider update trigger register" hexmask.long 0x8 0.--31. 1. "DIV_UPD_TRIGGER,Writing any value to this register causes all dividers that have corresponding bits set to '1' in the DIV_UPD_TYPE register and have pre-loaded configurations to be updated immediately. Reading this register always returns all zeros." rgroup.long 0x1DC++0x3 line.long 0x0 "DIV_UPD_STAT,Divider update status register" bitfld.long 0x0 31. "SYS_UPD_STAT,System Clock Divider Update Status" "0: The configuration for at least one system clock..,1: The configuration for at least one system clock.." rgroup.long 0x1E4++0x3 line.long 0x0 "SC_SS,System clock select status register" hexmask.long.byte 0x0 24.--27. 1. "SELSTAT,System Clock Source Selection Status" bitfld.long 0x0 17.--19. "SWTRG,Switch Trigger cause" "?,1: switch after request from MC_ME succeeded,2: switch after request from MC_ME failed due..,3: switch after request from MC_ME failed due..,4: switch to IRCOSC due to SAFE mode request or..,5: switch to IRCOSC due to SAFE mode request or..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch In Progress" "0: clock source switching has completed,1: clock source switching is in progress" group.long 0x1E8++0x7 line.long 0x0 "SC_DC0,System clock divider 0 configuration register" bitfld.long 0x0 31. "DE,Divider 0 Enable" "0,1" bitfld.long 0x0 16.--18. "DIV,Divider 0 Division Value" "0,1,2,3,4,5,6,7" line.long 0x4 "SC_DC1,System clock divider 1 configuration register" bitfld.long 0x4 31. "DE,Divider 1 Enable" "0,1" bitfld.long 0x4 16.--18. "DIV,Divider 1 Division Value" "0,1,2,3,4,5,6,7" group.long 0x200++0x3 line.long 0x0 "AC0_SC,Auxiliary clock 0 select control register" hexmask.long.byte 0x0 24.--27. 1. "SELCTL,Auxiliary Clock 0 Source Selection Control" rgroup.long 0x204++0x3 line.long 0x0 "AC0_SS,Auxiliary clock 0 select status register" hexmask.long.byte 0x0 24.--27. 1. "SELSTAT,Auxiliary Clock 1 Source Selection Status" tree.end tree "MC_CGM_PERIPHERAL_DOMAIN" base ad:0x722C8600 group.long 0x80++0xB line.long 0x0 "AC5_CDC0,Auxiliary clock 5 cascaded divider 0 configuration register" bitfld.long 0x0 31. "DE,Divider Enable." "0: Disable auxiliary clock 5 cascaded divider 0,1: Enable auxiliary clock 5 cascaded divider 0" newline hexmask.long.word 0x0 16.--25. 1. "DIV,Divider Division Value" line.long 0x4 "AC5_CDC1,Auxiliary clock 5 cascaded divider 1 configuration register" bitfld.long 0x4 31. "DE,Divider Enable." "0: Disable auxiliary clock 5 cascaded divider 1,1: Enable auxiliary clock 5 cascaded divider 1" newline hexmask.long.word 0x4 16.--25. 1. "DIV,Divider Division Value" line.long 0x8 "AC5_CDC2,Auxiliary clock 5 cascaded divider 2 configuration register" bitfld.long 0x8 31. "DE,Divider Enable." "0: Disable auxiliary clock 5 cascaded divider 2,1: Enable auxiliary clock 5 cascaded divider 2" newline hexmask.long.word 0x8 16.--25. 1. "DIV,Divider Division Value" group.long 0x90++0x1F line.long 0x0 "AC5_CDC10,Auxiliary clock 5 cascaded divider 10 configuration register" bitfld.long 0x0 31. "DE,Divider Enable" "0: Disable auxiliary clock 5 cascaded divider 10,1: Enable auxiliary clock 5 cascaded divider 10" newline hexmask.long.word 0x0 16.--25. 1. "DIV,Divider Division Value" line.long 0x4 "AC5_CDC11,Auxiliary clock 5 cascaded divider 11 configuration register" bitfld.long 0x4 31. "DE,Divider Enable" "0: Disable auxiliary clock 5 cascaded divider 11,1: Enable auxiliary clock 5 cascaded divider 11" newline hexmask.long.word 0x4 16.--25. 1. "DIV,Divider Division Value" line.long 0x8 "AC5_CDC12,Auxiliary clock 5 cascaded divider 12 configuration register" bitfld.long 0x8 31. "DE,Divider Enable" "0: Disable auxiliary clock 5 cascaded divider 12,1: Enable auxiliary clock 5 cascaded divider 12" newline hexmask.long.word 0x8 16.--25. 1. "DIV,Divider Division Value" line.long 0xC "AC5_CDC13,Auxiliary clock 5 cascaded divider 13 configuration register" bitfld.long 0xC 31. "DE,Divider Enable" "0: Disable auxiliary clock 5 cascaded divider 13,1: Enable auxiliary clock 5 cascaded divider 13" newline hexmask.long.word 0xC 16.--25. 1. "DIV,Divider Division Value" line.long 0x10 "AC5_CDC20,Auxiliary clock 5 cascaded divider 20 configuration register" bitfld.long 0x10 31. "DE,Divider Enable" "0: Disable auxiliary clock 5 cascaded divider 20,1: Enable auxiliary clock 5 cascaded divider 20" newline hexmask.long.word 0x10 16.--25. 1. "DIV,Divider Division Value" line.long 0x14 "AC5_CDC21,Auxiliary clock 5 cascaded divider 21 configuration register" bitfld.long 0x14 31. "DE,Divider Enable" "0: Disable auxiliary clock 5 cascaded divider 21,1: Enable auxiliary clock 5 cascaded divider 21" newline hexmask.long.word 0x14 16.--25. 1. "DIV,Divider Division Value" line.long 0x18 "AC5_CDC22,Auxiliary clock 5 cascaded divider 22 configuration register" bitfld.long 0x18 31. "DE,Divider Enable" "0: Disable auxiliary clock 5 cascaded divider 22,1: Enable auxiliary clock 5 cascaded divider 22" newline hexmask.long.word 0x18 16.--25. 1. "DIV,Divider Division Value" line.long 0x1C "AC5_CDC23,Auxiliary clock 5 cascaded divider 23 configuration register" bitfld.long 0x1C 31. "DE,Divider Enable" "0: Disable auxiliary clock 5 cascaded divider 23,1: Enable auxiliary clock 5 cascaded divider 23" newline hexmask.long.word 0x1C 16.--25. 1. "DIV,Divider Division Value" group.byte 0x103++0x0 line.byte 0x0 "PCS_SDUR,PCS switch duration register" hexmask.byte 0x0 0.--7. 1. "SDUR,Switch Duration" group.long 0x104++0x23 line.long 0x0 "PCS_DIVC1,PCS divider change register 1" hexmask.long.word 0x0 16.--31. 1. "INIT,Divider Change Initial Value" newline hexmask.long.byte 0x0 0.--7. 1. "RATE,Divider Change Rate" line.long 0x4 "PCS_DIVE1,PCS divider end register 1" hexmask.long.tbyte 0x4 0.--19. 1. "DIVE,Divider End Value" line.long 0x8 "PCS_DIVS1,PCS divider start register 1" hexmask.long.tbyte 0x8 0.--19. 1. "DIVS,Divider Start Value" line.long 0xC "PCS_DIVC2,PCS divider change register 2" hexmask.long.word 0xC 16.--31. 1. "INIT,Divider Change Initial Value" newline hexmask.long.byte 0xC 0.--7. 1. "RATE,Divider Change Rate" line.long 0x10 "PCS_DIVE2,PCS divider end register 2" hexmask.long.tbyte 0x10 0.--19. 1. "DIVE,Divider End Value" line.long 0x14 "PCS_DIVS2,PCS divider start register 2" hexmask.long.tbyte 0x14 0.--19. 1. "DIVS,Divider Start Value" line.long 0x18 "PCS_DIVC3,PCS divider change register 3" hexmask.long.word 0x18 16.--31. 1. "INIT,Divider Change Initial Value" newline hexmask.long.byte 0x18 0.--7. 1. "RATE,Divider Change Rate" line.long 0x1C "PCS_DIVE3,PCS divider end register 3" hexmask.long.tbyte 0x1C 0.--19. 1. "DIVE,Divider End Value" line.long 0x20 "PCS_DIVS3,PCS divider start register 3" hexmask.long.tbyte 0x20 0.--19. 1. "DIVS,Divider Start Value" group.long 0x188++0xB line.long 0x0 "PCS_DIVC12,PCS divider change register 12" hexmask.long.word 0x0 16.--31. 1. "INIT,Divider Change Initial Value" newline hexmask.long.byte 0x0 0.--7. 1. "RATE,Divider Change Rate" line.long 0x4 "PCS_DIVE12,PCS divider end register 12" hexmask.long.tbyte 0x4 0.--19. 1. "DIVE,Divider End Value" line.long 0x8 "PCS_DIVS12,PCS divider start register 12" hexmask.long.tbyte 0x8 0.--19. 1. "DIVS,Divider Start Value" group.long 0x1D0++0xF line.long 0x0 "SC_DIV_RC,System clock divider ratio change register" bitfld.long 0x0 0. "SYS_DIV_RATIO_CHNG,System Clock Divider Ratio Change" "0: The system clock divider ratios does not change..,1: The system clock divider ratios changes with the.." line.long 0x4 "DIV_UPD_TYPE,Divider update type register" bitfld.long 0x4 31. "SYS_UPD_TYPE,System Clock Divider Update Type" "0: The configuration for each system clock divider..,1: The configuration for each system clock divider.." newline bitfld.long 0x4 13. "AUX13_UPD_TYPE,Auxiliary Clock n Divider Update Type" "0,1" newline bitfld.long 0x4 12. "AUX12_UPD_TYPE,Auxiliary Clock n Divider Update Type" "0,1" newline bitfld.long 0x4 11. "AUX11_UPD_TYPE,Auxiliary Clock n Divider Update Type" "0,1" newline bitfld.long 0x4 10. "AUX10_UPD_TYPE,Auxiliary Clock n Divider Update Type" "0,1" newline bitfld.long 0x4 9. "AUX9_UPD_TYPE,Auxiliary Clock n Divider Update Type" "0,1" newline bitfld.long 0x4 8. "AUX8_UPD_TYPE,Auxiliary Clock n Divider Update Type" "0,1" newline bitfld.long 0x4 7. "AUX7_UPD_TYPE,Auxiliary Clock n Divider Update Type" "0,1" newline bitfld.long 0x4 6. "AUX6_UPD_TYPE,Auxiliary Clock n Divider Update Type" "0,1" newline bitfld.long 0x4 5. "AUX5_UPD_TYPE,Auxiliary Clock n Divider Update Type" "0,1" newline bitfld.long 0x4 4. "AUX4_UPD_TYPE,Auxiliary Clock n Divider Update Type" "0,1" newline bitfld.long 0x4 3. "AUX3_UPD_TYPE,Auxiliary Clock n Divider Update Type" "0,1" newline bitfld.long 0x4 2. "AUX2_UPD_TYPE,Auxiliary Clock n Divider Update Type" "0,1" line.long 0x8 "DIV_UPD_TRIG,Divider update trigger register" hexmask.long 0x8 0.--31. 1. "DIV_UPD_TRIGGER,Writing any value to this register causes all dividers that have corresponding bits set to '1' in the DIV_UPD_TYPE register and have pre-loaded configurations to be updated immediately. Reading this register always returns all zeroes." line.long 0xC "DIV_UPD_STAT,Divider update status register" bitfld.long 0xC 31. "SYS_UPD_STAT,System Clock Divider Update Status" "0: The configuration for at least one system clock..,1: The configuration for at least one system clock.." newline bitfld.long 0xC 13. "AUX13_UPD_STAT,Auxiliary Clock n Divider Update Status" "0,1" newline bitfld.long 0xC 12. "AUX12_UPD_STAT,Auxiliary Clock n Divider Update Status" "0,1" newline bitfld.long 0xC 11. "AUX11_UPD_STAT,Auxiliary Clock n Divider Update Status" "0,1" newline bitfld.long 0xC 10. "AUX10_UPD_STAT,Auxiliary Clock n Divider Update Status" "0,1" newline bitfld.long 0xC 9. "AUX9_UPD_STAT,Auxiliary Clock n Divider Update Status" "0,1" newline bitfld.long 0xC 8. "AUX8_UPD_STAT,Auxiliary Clock n Divider Update Status" "0,1" newline bitfld.long 0xC 7. "AUX7_UPD_STAT,Auxiliary Clock n Divider Update Status" "0,1" newline bitfld.long 0xC 6. "AUX6_UPD_STAT,Auxiliary Clock n Divider Update Status" "0,1" newline bitfld.long 0xC 5. "AUX5_UPD_STAT,Auxiliary Clock n Divider Update Status" "0,1" newline bitfld.long 0xC 4. "AUX4_UPD_STAT,Auxiliary Clock n Divider Update Status" "0,1" newline bitfld.long 0xC 3. "AUX3_UPD_STAT,Auxiliary Clock n Divider Update Status" "0,1" newline bitfld.long 0xC 2. "AUX2_UPD_STAT,Auxiliary Clock n Divider Update Status" "0,1" rgroup.long 0x1E4++0x3 line.long 0x0 "SC_SS,System clock select status register" hexmask.long.byte 0x0 24.--27. 1. "SELSTAT,System Clock Source Selection Status" newline bitfld.long 0x0 17.--19. "SWTRG,Switch Trigger cause" "?,1: switch after request from MC_ME succeeded,2: switch after request from MC_ME failed due..,3: switch after request from MC_ME failed due..,4: switch to IRCOSC due to SAFE mode request or..,5: switch to IRCOSC due to SAFE mode request or..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch In Progress" "0: clock source switching has completed,1: clock source switching is in progress" group.long 0x1E8++0x3 line.long 0x0 "SC_DC0,System clock divider 0 configuration register" bitfld.long 0x0 31. "DE,Divider 0 Enable" "0,1" newline bitfld.long 0x0 16.--17. "DIV,Divider 0 Division Value" "0,1,2,3" group.long 0x220++0x3 line.long 0x0 "AC1_SC,Auxiliary clock 1 select control register" bitfld.long 0x0 24. "SELCTL,Auxiliary Clock 1 Source Selection Control" "0: IRCOSC,1: XOSC" rgroup.long 0x224++0x3 line.long 0x0 "AC1_SS,Auxiliary clock 1 select status register" bitfld.long 0x0 24. "SELSTAT,Auxiliary Clock 1 Source Selection Status" "0: IRCOSC,1: XOSC" group.long 0x248++0x3 line.long 0x0 "AC2_DC0,Auxiliary clock 2 divider 0 configuration register" bitfld.long 0x0 31. "DE,Divider Enable" "0: Disable auxiliary clock 2 divider 0,1: Enable auxiliary clock 2 divider 0" newline bitfld.long 0x0 16.--18. "DIV,Divider Division Value" "0,1,2,3,4,5,6,7" group.long 0x260++0x3 line.long 0x0 "AC3_SC,Auxiliary clock 3 select control register" bitfld.long 0x0 24.--25. "SELCTL,Auxiliary Clock 3 Source Selection Control" "0: IRCOSC,1: XOSC,2: PLL0 PHI,?" rgroup.long 0x264++0x3 line.long 0x0 "AC3_SS,Auxiliary clock 3 select status register" bitfld.long 0x0 24.--25. "SELSTAT,Auxiliary Clock 3 Source Selection Status" "0: IRCOSC,1: XOSC,2: PLL0 PHI,?" group.long 0x268++0xF line.long 0x0 "AC3_DC0,Auxiliary clock 3 divider 0 configuration register" bitfld.long 0x0 31. "DE,Divider Enable" "0: Disable auxiliary clock 3 divider 0,1: Enable auxiliary clock 3 divider 0" newline bitfld.long 0x0 16.--17. "DIV,Divider Division Value" "0,1,2,3" line.long 0x4 "AC3_DC1,Auxiliary clock 3 divider 1 configuration register" bitfld.long 0x4 31. "DE,Divider Enable" "0: Disable auxiliary clock 3 divider 1,1: Enable auxiliary clock 3 divider 1" newline hexmask.long.byte 0x4 16.--21. 1. "DIV,Divider Division Value" line.long 0x8 "AC3_DC2,Auxiliary clock 3 divider 2 configuration register" bitfld.long 0x8 31. "DE,Divider Enable" "0: Disable auxiliary clock 3 divider 2,1: Enable auxiliary clock 3 divider 2" newline hexmask.long.byte 0x8 16.--21. 1. "DIV,Divider Division Value" line.long 0xC "AC3_DC3,Auxiliary clock 3 divider 3 configuration register" bitfld.long 0xC 31. "DE,Divider Enable" "0: Disable auxiliary clock 3 divider 3,1: Enable auxiliary clock 3 divider 3" newline bitfld.long 0xC 16.--18. "DIV,Divider Division Value" "0,1,2,3,4,5,6,7" group.long 0x280++0x3 line.long 0x0 "AC4_SC,Auxiliary clock 4 select control register" hexmask.long.byte 0x0 24.--27. 1. "SELCTL,Auxiliary Clock 4 Source Selection Control" rgroup.long 0x284++0x3 line.long 0x0 "AC4_SS,Auxiliary clock 4 select status register" hexmask.long.byte 0x0 24.--27. 1. "SELSTAT,Auxiliary Clock 4 Source Selection Status" group.long 0x288++0x3 line.long 0x0 "AC4_DC0,Auxiliary clock 4 divider 0 configuration register" bitfld.long 0x0 31. "DE,Divider Enable" "0: Disable auxiliary clock 4 divider 0,1: Enable auxiliary clock 4 divider 0" newline hexmask.long.byte 0x0 16.--22. 1. "DIV,Divider Division Value" group.long 0x2A8++0xB line.long 0x0 "AC5_DC0,Auxiliary clock 5 divider 0 configuration register" bitfld.long 0x0 31. "DE,Divider Enable" "0: Disable auxiliary clock 5 divider 0,1: Enable auxiliary clock 5 divider 0" newline hexmask.long.word 0x0 16.--28. 1. "DIV,Divider Division Value" newline bitfld.long 0x0 0.--1. "DIV_FMT,Divider Value Format" "0: Division factor = (DIV + 1) / 1,1: Division factor = (DIV + 1) / 10,2: Division factor = (DIV + 1) / 100,3: Division factor = (DIV + 1) / 1 000" line.long 0x4 "AC5_DC1,Auxiliary clock 5 divider 1 configuration register" bitfld.long 0x4 31. "DE,Divider Enable" "0: Disable auxiliary clock 5 divider 1,1: Enable auxiliary clock 5 divider 1" newline hexmask.long.word 0x4 16.--25. 1. "DIV,Divider Division Value" line.long 0x8 "AC5_DC2,Auxiliary clock 5 divider 2 configuration register" bitfld.long 0x8 31. "DE,Divider Enable" "0: Disable auxiliary clock 5 divider 2,1: Enable auxiliary clock 5 divider 2" newline hexmask.long.word 0x8 16.--25. 1. "DIV,Divider Division Value" group.long 0x2C0++0x3 line.long 0x0 "AC6_SC,Auxiliary clock 6 select control register" hexmask.long.byte 0x0 24.--27. 1. "SELCTL,Auxiliary Clock 6 Source Selection Control" rgroup.long 0x2C4++0x3 line.long 0x0 "AC6_SS,Auxiliary clock 6 select status register" hexmask.long.byte 0x0 24.--27. 1. "SELSTAT,Auxiliary Clock 6 Source Selection Status" group.long 0x2C8++0x3 line.long 0x0 "AC6_DC0,Auxiliary clock 6 divider 0 configuration register" bitfld.long 0x0 31. "DE,Divider Enable" "0: Disable auxiliary clock 6 divider 0,1: Enable auxiliary clock 6 divider 0" newline hexmask.long.word 0x0 16.--24. 1. "DIV,Divider Division Value" group.long 0x2E0++0x3 line.long 0x0 "AC7_SC,Auxiliary clock 7 select control register" bitfld.long 0x0 24.--26. "SELCTL,Auxiliary Clock 7 Source Selection Control" "0: IRCOSC,1: XOSC,2: PLL0 PHI,?,4: PLL1_D0 PHI_HP,5: PLL1_D0 PHI_LC,?,?" rgroup.long 0x2E4++0x3 line.long 0x0 "AC7_SS,Auxiliary clock 7 select status register" bitfld.long 0x0 24.--26. "SELSTAT,Auxiliary Clock 7 Source Selection Status" "0: IRCOSC,1: XOSC,2: PLL0 PHI,?,4: PLL1_D0 PHI_HP,5: PLL1_D0 PHI_LC,?,?" group.long 0x2E8++0x3 line.long 0x0 "AC7_DC0,Auxiliary clock 7 divider 0 configuration register" bitfld.long 0x0 31. "DE,Divider Enable" "0: Disable auxiliary clock 7 divider 0,1: Enable auxiliary clock 7 divider 0" newline hexmask.long.word 0x0 16.--24. 1. "DIV,Divider Division Value" group.long 0x300++0x3 line.long 0x0 "AC8_SC,Auxiliary clock 8 select control register" bitfld.long 0x0 24.--25. "SELCTL,Auxiliary Clock 8 Source Selection Control" "?,1: XOSC,2: PLL0 PHI,?" rgroup.long 0x304++0x3 line.long 0x0 "AC8_SS,Auxiliary clock 8 select status register" bitfld.long 0x0 24.--25. "SELSTAT,Auxiliary Clock 8 Source Selection Status" "?,1: XOSC,2: PLL0 PHI,?" group.long 0x308++0x7 line.long 0x0 "AC8_DC0,Auxiliary clock 8 divider 0 configuration register" bitfld.long 0x0 31. "DE,Divider Enable" "0: Disable auxiliary clock 8 divider 0,1: Enable auxiliary clock 8 divider 0" newline hexmask.long.byte 0x0 16.--21. 1. "DIV,Divider Division Value" line.long 0x4 "AC8_DC1,Auxiliary clock 8 divider 1 configuration register" bitfld.long 0x4 31. "DE,Divider Enable" "0: Disable auxiliary clock 8 divider 1,1: Enable auxiliary clock 8 divider 1" newline hexmask.long.byte 0x4 16.--21. 1. "DIV,Divider Division Value" group.long 0x320++0x3 line.long 0x0 "AC9_SC,Auxiliary clock 9 select control register" bitfld.long 0x0 24.--25. "SELCTL,Auxiliary Clock 9 Source Selection Control" "?,1: XOSC,2: PLL0 PHI,?" rgroup.long 0x324++0x3 line.long 0x0 "AC9_SS,Auxiliary clock 9 select status register" bitfld.long 0x0 24.--25. "SELSTAT,Auxiliary Clock 9 Source Selection Status" "?,1: XOSC,2: PLL0 PHI,?" group.long 0x328++0x3 line.long 0x0 "AC9_DC0,Auxiliary clock 9 divider 0 configuration register" bitfld.long 0x0 31. "DE,Divider Enable" "0: Disable auxiliary clock 9 divider 0,1: Enable auxiliary clock 9 divider 0" newline hexmask.long.byte 0x0 16.--21. 1. "DIV,Divider Division Value" group.long 0x340++0x3 line.long 0x0 "AC10_SC,Auxiliary clock 10 select control register" hexmask.long.byte 0x0 24.--27. 1. "SELCTL,Auxiliary Clock 10 Source Selection Control" rgroup.long 0x344++0x3 line.long 0x0 "AC10_SS,Auxiliary clock 10 select status register" hexmask.long.byte 0x0 24.--27. 1. "SELSTAT,Auxiliary Clock 10 Source Selection Status" group.long 0x348++0x3 line.long 0x0 "AC10_DC0,Auxiliary clock 10 divider 0 configuration register" bitfld.long 0x0 31. "DE,Divider Enable" "0: Disable auxiliary clock 10 divider 0,1: Enable auxiliary clock 10 divider 0" newline bitfld.long 0x0 16.--18. "DIV,Divider Division Value" "0,1,2,3,4,5,6,7" group.long 0x360++0x3 line.long 0x0 "AC11_SC,Auxiliary clock 11 select control register" bitfld.long 0x0 24.--25. "SELCTL,Auxiliary Clock 11 Source Selection Control" "0: IRCOSC,1: XOSC,2: PLL0 PHI,?" rgroup.long 0x364++0x3 line.long 0x0 "AC11_SS,Auxiliary clock 11 select status register" bitfld.long 0x0 24.--25. "SELSTAT,Auxiliary Clock 11 Source Selection Status" "0: IRCOSC,1: XOSC,2: PLL0 PHI,?" group.long 0x368++0xB line.long 0x0 "AC11_DC0,Auxiliary clock 11 divider 0 configuration register" bitfld.long 0x0 31. "DE,Divider Enable" "0: Disable auxiliary clock 11 divider 0,1: Enable auxiliary clock 11 divider 0" newline bitfld.long 0x0 16.--18. "DIV,Divider Division Value" "0,1,2,3,4,5,6,7" line.long 0x4 "AC11_DC1,Auxiliary clock 11 divider 1 configuration register" bitfld.long 0x4 31. "DE,Divider Enable" "0: Disable auxiliary clock 11 divider 0,1: Enable auxiliary clock 11 divider 0" newline bitfld.long 0x4 16.--18. "DIV,Divider Division Value" "0,1,2,3,4,5,6,7" line.long 0x8 "AC11_DC2,Auxiliary clock 11 divider 2 configuration register" bitfld.long 0x8 31. "DE,Divider Enable" "0: Disable auxiliary clock 11 divider 0,1: Enable auxiliary clock 11 divider 0" newline bitfld.long 0x8 16.--17. "DIV,Divider Division Value" "0,1,2,3" group.long 0x380++0x3 line.long 0x0 "AC12_SC,Auxiliary clock 12 select control register" bitfld.long 0x0 24.--25. "SELCTL,Auxiliary Clock 12 Source Selection Control" "0: IRCOSC,1: XOSC,2: PLL0 PHI,?" rgroup.long 0x384++0x3 line.long 0x0 "AC12_SS,Auxiliary clock 12 select status register" bitfld.long 0x0 24.--25. "SELSTAT,Auxiliary Clock 12 Source Selection Status" "0: IRCOSC,1: XOSC,2: PLL0 PHI,?" group.long 0x388++0x13 line.long 0x0 "AC12_DC0,Auxiliary clock 12 divider 0 configuration register" bitfld.long 0x0 31. "DE,Divider Enable" "0: Disable auxiliary clock 12 divider 0,1: Enable auxiliary clock 12 divider 0" newline bitfld.long 0x0 16.--18. "DIV,Divider Division Value" "0,1,2,3,4,5,6,7" line.long 0x4 "AC12_DC1,Auxiliary clock 12 divider 1 configuration register" bitfld.long 0x4 31. "DE,Divider Enable" "0: Disable auxiliary clock 12 divider 1,1: Enable auxiliary clock 12 divider 1" newline bitfld.long 0x4 16.--18. "DIV,Divider Division Value" "0,1,2,3,4,5,6,7" line.long 0x8 "AC12_DC2,Auxiliary clock 12 divider 2 configuration register" bitfld.long 0x8 31. "DE,Divider Enable" "0: Disable auxiliary clock 12 divider 2,1: Enable auxiliary clock 12 divider 2" newline hexmask.long.byte 0x8 16.--19. 1. "DIV,Divider Division Value" line.long 0xC "AC12_DC3,Auxiliary clock 12 divider 3 configuration register" bitfld.long 0xC 31. "DE,Divider Enable" "0: Disable auxiliary clock 12 divider 3,1: Enable auxiliary clock 12 divider 3" newline bitfld.long 0xC 16.--17. "DIV,Divider Division Value" "0,1,2,3" line.long 0x10 "AC12_DC4,Auxiliary clock 12 divider 4 configuration register" bitfld.long 0x10 31. "DE,Divider Enable" "0: Disable auxiliary clock 12 divider 4,1: Enable auxiliary clock 12 divider 4" newline bitfld.long 0x10 16.--18. "DIV,Divider Division Value" "0,1,2,3,4,5,6,7" group.long 0x3A0++0x3 line.long 0x0 "AC13_SC,Auxiliary clock 13 select control register" bitfld.long 0x0 24.--25. "SELCTL,Auxiliary Clock 13 Source Selection Control" "?,1: XOSC,2: PLL0 PHI,?" rgroup.long 0x3A4++0x3 line.long 0x0 "AC13_SS,Auxiliary clock 13 select status register" bitfld.long 0x0 24.--25. "SELSTAT,Auxiliary Clock 13 Source Selection Status" "?,1: XOSC,2: PLL0 PHI,?" group.long 0x3A8++0x3 line.long 0x0 "AC13_DC0,Auxiliary clock 13 divider 0 configuration register" bitfld.long 0x0 31. "DE,Divider Enable" "0: Disable auxiliary clock 13 divider 0,1: Enable auxiliary clock 13 divider 0" newline hexmask.long.byte 0x0 16.--20. 1. "DIV,Divider Division Value" tree.end tree.end tree "MC_ME (Mode Entry Module)" base ad:0x0 tree "MC_ME_DOMAIN_0" base ad:0x710D0000 rgroup.long 0x0++0x3 line.long 0x0 "GS,Global Status register" hexmask.long.byte 0x0 28.--31. 1. "S_CURRENT_MODE,Current chip mode status" bitfld.long 0x0 27. "S_MTRANS,Mode transition status" "0: Mode transition process is not active,1: Mode transition is ongoing" newline bitfld.long 0x0 23. "S_PDO,Output power-down status" "0: No automatic safe gating of I/Os used and pads..,?" bitfld.long 0x0 20. "S_MVR,Main voltage regulator status" "0: Main voltage regulator is not ready,1: Main voltage regulator is ready for use" newline bitfld.long 0x0 16.--17. "S_FLA,NVM availability status" "0: NVM is not available,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode and available for use" bitfld.long 0x0 7. "S_PLL1,PLL1 status" "0: PLL1 is not stable,1: PLL0 is providing a stable clock" newline bitfld.long 0x0 6. "S_PLL0,PLL0 status" "0: PLL0 is not stable,1: PLL0 is providing a stable clock" bitfld.long 0x0 5. "S_XOSC,XOSC status" "0: XOSC is not stable,1: XOSC is providing a stable clock" newline bitfld.long 0x0 4. "S_IRC,IRCOSC status" "0: IRCOSC is not stable,1: IRCOSC is providing a stable clock" hexmask.long.byte 0x0 0.--3. 1. "S_SYSCLK,System clock switch status" group.long 0x4++0x13 line.long 0x0 "MCTL,Mode Control register" hexmask.long.byte 0x0 28.--31. 1. "TARGET_MODE,Target chip mode" hexmask.long.word 0x0 0.--15. 1. "KEY,Control key" line.long 0x4 "ME,Mode Enable register" bitfld.long 0x4 15. "RESET_DEST,Destructive RESET mode enable" "?,1: destructive RESET mode is enabled" bitfld.long 0x4 7. "RUN3,RUN3 mode enable" "0: RUN3 mode is disabled,1: RUN3 mode is enabled" newline bitfld.long 0x4 6. "RUN2,RUN2 mode enable" "0: RUN2 mode is disabled,1: RUN2 mode is enabled" bitfld.long 0x4 5. "RUN1,RUN1 mode enable" "0: RUN1 mode is disabled,1: RUN1 mode is enabled" newline bitfld.long 0x4 4. "RUN0,RUN0 mode enable" "?,1: RUN0 mode is enabled" bitfld.long 0x4 3. "DRUN,DRUN mode enable" "?,1: DRUN mode is enabled" newline bitfld.long 0x4 2. "SAFE,SAFE mode enable" "?,1: SAFE mode is enabled" bitfld.long 0x4 1. "TEST,TEST mode enable" "0: TEST mode is disabled,1: TEST mode is enabled" newline bitfld.long 0x4 0. "RESET_FUNC,Functional RESET mode enable" "?,1: functional RESET mode is enabled" line.long 0x8 "IS,Interrupt Status register" bitfld.long 0x8 5. "I_ICONF_CC,Invalid mode configuration interrupt (core configuration)" "0: No write to an ME_CADDRn register was attempted..,1: A write to an ME_CADDRn register was attempted.." bitfld.long 0x8 4. "I_ICONF_CU,Invalid mode configuration interrupt (Clock Usage)" "0: No invalid mode configuration (clock usage)..,1: ' to this bit" newline bitfld.long 0x8 3. "I_ICONF,Invalid mode configuration interrupt" "0: No invalid mode configuration interrupt occurred,1: ' to this bit" bitfld.long 0x8 2. "I_IMODE,Invalid mode interrupt" "0: No invalid mode interrupt occurred,1: ' to this bit" newline bitfld.long 0x8 1. "I_SAFE,SAFE mode interrupt" "0: No SAFE mode interrupt occurred,1: ' to this bit" bitfld.long 0x8 0. "I_MTC,Mode transition complete interrupt" "0: No mode transition complete interrupt occurred,1: ' to this bit" line.long 0xC "IM,Interrupt Mask register" bitfld.long 0xC 5. "M_ICONF_CC,Invalid mode configuration (core configuration) interrupt mask" "0: Invalid mode interrupt is masked,1: Invalid mode interrupt is enabled" bitfld.long 0xC 4. "M_ICONF_CU,Invalid mode configuration (clock usage) interrupt mask" "0: Invalid mode interrupt is masked,1: Invalid mode interrupt is enabled" newline bitfld.long 0xC 3. "M_ICONF,Invalid mode configuration interrupt mask" "0: Invalid mode interrupt is masked,1: Invalid mode interrupt is enabled" bitfld.long 0xC 2. "M_IMODE,Invalid mode interrupt mask" "0: Invalid mode interrupt is masked,1: Invalid mode interrupt is enabled" newline bitfld.long 0xC 1. "M_SAFE,SAFE mode interrupt mask" "0: SAFE mode interrupt is masked,1: SAFE mode interrupt is enabled" bitfld.long 0xC 0. "M_MTC,Mode transition complete interrupt mask" "0: Mode transition complete interrupt is masked,1: Mode transition complete interrupt is enabled" line.long 0x10 "IMTS,Invalid Mode Transition Status register" bitfld.long 0x10 5. "S_MRIG,Mode Request Ignored status" "0: Mode transition requested is not ignored,1: ' to this bit" bitfld.long 0x10 4. "S_MTI,Mode Transition Illegal status" "0: Mode transition requested is not illegal,1: ' to this bit" newline bitfld.long 0x10 3. "S_MRI,Mode Request Illegal status" "0: Target mode requested is not illegal with..,1: ' to this bit" bitfld.long 0x10 2. "S_DMA,Disabled Mode Access status" "0: Target mode requested is not a disabled mode,1: ' to this bit" newline bitfld.long 0x10 1. "S_NMA,Non-existing Mode Access status" "0: Target mode requested is an existing mode,1: ' to this bit" bitfld.long 0x10 0. "S_SEA,SAFE Event Active status" "0: No new mode requested other than RESET/SAFE..,1: ' to this bit" rgroup.long 0x18++0x3 line.long 0x0 "DMTS,Debug Mode Transition Status register" hexmask.long.byte 0x0 28.--31. 1. "PREVIOUS_MODE,Previous chip mode" bitfld.long 0x0 23. "MPH_BUSY,MC_ME Core/MC_PCU Handshake Busy indicator" "0: Handshake is not busy,1: Handshake is busy" newline bitfld.long 0x0 20. "PMC_PROG,MC_PCU Mode Change in Progress indicator" "0: Power-up/down transition is not in progress,1: Power-up/down transition is in progress" bitfld.long 0x0 19. "DBG_MODE,Debug mode indicator" "0: The chip is not in debug mode,1: The chip is in debug mode" newline bitfld.long 0x0 18. "CCKL_PROG,Core Clock Enable/Disable in Progress" "0: No core clock is being enabled or disabled,1: A core clock is being enabled or disabled" bitfld.long 0x0 17. "PCS_PROG,Progressive System Clock Switching in Progress" "0: PCS is not in progress,1: PCS is in progress" newline bitfld.long 0x0 16. "SMR,SAFE mode request from MC_RGM is active indicator" "0: A SAFE mode request is not active,1: A SAFE mode request is active" bitfld.long 0x0 14. "VREG_CSRC_SC,Main VREG dependent Clock Source State Change during mode transition indicator" "0: No state change is taking place,1: A state change is taking place" newline bitfld.long 0x0 13. "CSRC_CSRC_SC,(Other) Clock Source dependent Clock Source State Change during mode transition indicator" "0: No state change is taking place,1: A state change is taking place" bitfld.long 0x0 12. "IRC_SC,IRCOSC State Change during mode transition indicator" "0: No state change is taking place,1: A state change is taking place" newline bitfld.long 0x0 11. "SCSRC_SC,Secondary Clock Sources State Change during mode transition indicator" "0: No state change is taking place,1: A state change is taking place" bitfld.long 0x0 10. "SYSCLK_SW,System Clock Switching pending status" "0: No system clock source switching is pending,1: A system clock source switching is pending" newline bitfld.long 0x0 8. "NVM_SC,NVM State Change during mode transition indicator" "0: No state change is taking place,1: A state change is taking place" rgroup.long 0x20++0x3 line.long 0x0 "RESET_MC,RESET Mode Configuration register" bitfld.long 0x0 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." bitfld.long 0x0 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" newline bitfld.long 0x0 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" bitfld.long 0x0 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" newline bitfld.long 0x0 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" bitfld.long 0x0 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" newline bitfld.long 0x0 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" hexmask.long.byte 0x0 0.--3. 1. "SYSCLK,System clock switch control" group.long 0x24++0x1B line.long 0x0 "TEST_MC,TEST Mode Configuration register" bitfld.long 0x0 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x0 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" bitfld.long 0x0 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" newline bitfld.long 0x0 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" bitfld.long 0x0 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x0 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" bitfld.long 0x0 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x0 0.--3. 1. "SYSCLK,System clock switch control" line.long 0x4 "SAFE_MC,SAFE Mode Configuration register" bitfld.long 0x4 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" bitfld.long 0x4 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x4 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" bitfld.long 0x4 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" newline bitfld.long 0x4 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" bitfld.long 0x4 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x4 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" bitfld.long 0x4 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x4 0.--3. 1. "SYSCLK,System clock switch control" line.long 0x8 "DRUN_MC,DRUN Mode Configuration register" bitfld.long 0x8 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" bitfld.long 0x8 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x8 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" bitfld.long 0x8 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" newline bitfld.long 0x8 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" bitfld.long 0x8 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x8 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" bitfld.long 0x8 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x8 0.--3. 1. "SYSCLK,System clock switch control" line.long 0xC "RUN0_MC,RUNn Mode Configuration registers" bitfld.long 0xC 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" bitfld.long 0xC 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0xC 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" bitfld.long 0xC 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" newline bitfld.long 0xC 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" bitfld.long 0xC 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0xC 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" bitfld.long 0xC 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0xC 0.--3. 1. "SYSCLK,System clock switch control" line.long 0x10 "RUN1_MC,RUNn Mode Configuration registers" bitfld.long 0x10 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" bitfld.long 0x10 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x10 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" bitfld.long 0x10 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" newline bitfld.long 0x10 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" bitfld.long 0x10 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x10 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" bitfld.long 0x10 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x10 0.--3. 1. "SYSCLK,System clock switch control" line.long 0x14 "RUN2_MC,RUNn Mode Configuration registers" bitfld.long 0x14 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" bitfld.long 0x14 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x14 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" bitfld.long 0x14 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" newline bitfld.long 0x14 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" bitfld.long 0x14 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x14 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" bitfld.long 0x14 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x14 0.--3. 1. "SYSCLK,System clock switch control" line.long 0x18 "RUN3_MC,RUNn Mode Configuration registers" bitfld.long 0x18 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" bitfld.long 0x18 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x18 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" bitfld.long 0x18 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" newline bitfld.long 0x18 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" bitfld.long 0x18 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x18 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" bitfld.long 0x18 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x18 0.--3. 1. "SYSCLK,System clock switch control" group.long 0x80++0x1F line.long 0x0 "RUN_PC0,Run Peripheral Configuration registers" bitfld.long 0x0 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x0 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x0 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x0 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x0 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x0 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x0 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x0 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x4 "RUN_PC1,Run Peripheral Configuration registers" bitfld.long 0x4 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x4 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x4 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x4 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x4 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x4 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x4 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x4 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x8 "RUN_PC2,Run Peripheral Configuration registers" bitfld.long 0x8 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x8 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x8 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x8 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x8 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x8 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x8 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x8 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0xC "RUN_PC3,Run Peripheral Configuration registers" bitfld.long 0xC 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0xC 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0xC 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0xC 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0xC 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0xC 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0xC 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0xC 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x10 "RUN_PC4,Run Peripheral Configuration registers" bitfld.long 0x10 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x10 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x10 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x10 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x10 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x10 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x10 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x10 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x14 "RUN_PC5,Run Peripheral Configuration registers" bitfld.long 0x14 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x14 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x14 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x14 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x14 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x14 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x14 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x14 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x18 "RUN_PC6,Run Peripheral Configuration registers" bitfld.long 0x18 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x18 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x18 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x18 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x18 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x18 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x18 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x18 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x1C "RUN_PC7,Run Peripheral Configuration registers" bitfld.long 0x1C 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x1C 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x1C 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x1C 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x1C 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x1C 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x1C 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x1C 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" rgroup.long 0x1C0++0x3 line.long 0x0 "CS,Core Status register" bitfld.long 0x0 15. "S_CLUSTER_CORE1,Cluster n core 1" "0: cluster n core 1 is running.,1: cluster n core 1 is in WFI/WFE state." bitfld.long 0x0 14. "S_CLUSTER_CORE0,Cluster n core 0" "0: cluster n core 0 is running.,1: cluster n core 0 is in WFI/WFE state." newline bitfld.long 0x0 1. "S_CORE1,Core 1 status" "0: core 1 is disabled.,1: core 1 is running." bitfld.long 0x0 0. "S_CORE0,Core 0 status" "0: core 0 is disabled.,1: core 0 is running." group.word 0x1C4++0x3 line.word 0x0 "CCTL1,Core Control register" bitfld.word 0x0 7. "RUN3,Core control during RUN3" "0: core 1 is disabled with clock gated,1: core 1 is running" bitfld.word 0x0 6. "RUN2,Core control during RUN2" "0: core 1 is disabled with clock gated,1: core 1 is running" newline bitfld.word 0x0 5. "RUN1,Core control during RUN1" "0: core 1 is disabled with clock gated,1: core 1 is running" bitfld.word 0x0 4. "RUN0,Core control during RUN0" "0: core 1 is frozen with clock gated,1: core 1 is running" newline bitfld.word 0x0 3. "DRUN,Core control during DRUN" "0: core 1 is frozen with clock gated,1: core 1 is running" bitfld.word 0x0 2. "SAFE,Core control during SAFE" "0: core 1 is frozen with clock gated,1: core 1 is running" newline bitfld.word 0x0 1. "TEST,Core control during TEST" "0: core 1 is frozen with clock gated,1: core 1 is running" bitfld.word 0x0 0. "RESET,Core control during RESET" "0,1" line.word 0x2 "CCTL0,Core Control register 0" bitfld.word 0x2 7. "RUN3,Core control during RUN3" "0: core 0 is disabled with clock gated,1: core 0 is running" bitfld.word 0x2 6. "RUN2,Core control during RUN2" "0: core 0 is disabled with clock gated,1: core 0 is running" newline bitfld.word 0x2 5. "RUN1,Core control during RUN1" "0: core 0 is disabled with clock gated,1: core 0 is running" bitfld.word 0x2 4. "RUN0,Core control during RUN0" "0: core 0 is frozen with clock gated,1: core 0 is running" newline bitfld.word 0x2 3. "DRUN,Core control during DRUN" "0: core 0 is frozen with clock gated,1: core 0 is running" bitfld.word 0x2 2. "SAFE,Core control during SAFE" "0: core 0 is frozen with clock gated,1: core 0 is running" newline bitfld.word 0x2 1. "TEST,Core control during TEST" "0: core 0 is frozen with clock gated,1: core 0 is running" bitfld.word 0x2 0. "RESET,Core control during RESET" "0,1" group.long 0x1E0++0x7 line.long 0x0 "CADDR0,Core Address register 0" hexmask.long 0x0 2.--31. 1. "ADDR,Core Address" bitfld.long 0x0 0. "RMC,Reset on Mode Change" "0: Core 0 is not reset on the next mode change.,1: Core 0 is reset on the next mode change that has.." line.long 0x4 "CADDR1,Core Address register 1" hexmask.long 0x4 2.--31. 1. "ADDR,Core Address" bitfld.long 0x4 0. "RMC,Reset on Mode Change" "0: Core 1 is not reset on the next mode change,1: Core 1 is reset on the next mode change that has.." tree.end tree "MC_ME_DOMAIN_1" base ad:0x716D0000 rgroup.long 0x0++0x3 line.long 0x0 "GS,Global Status register" hexmask.long.byte 0x0 28.--31. 1. "S_CURRENT_MODE,Current chip mode status" bitfld.long 0x0 27. "S_MTRANS,Mode transition status" "0: Mode transition process is not active,1: Mode transition is ongoing" newline bitfld.long 0x0 23. "S_PDO,Output power-down status" "0: No automatic safe gating of I/Os used and pads..,?" bitfld.long 0x0 20. "S_MVR,Main voltage regulator status" "0: Main voltage regulator is not ready,1: Main voltage regulator is ready for use" newline bitfld.long 0x0 16.--17. "S_FLA,NVM availability status" "0: NVM is not available,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode and available for use" bitfld.long 0x0 7. "S_PLL1,PLL1 status" "0: PLL1 is not stable,1: PLL0 is providing a stable clock" newline bitfld.long 0x0 6. "S_PLL0,PLL0 status" "0: PLL0 is not stable,1: PLL0 is providing a stable clock" bitfld.long 0x0 5. "S_XOSC,XOSC status" "0: XOSC is not stable,1: XOSC is providing a stable clock" newline bitfld.long 0x0 4. "S_IRC,IRCOSC status" "0: IRCOSC is not stable,1: IRCOSC is providing a stable clock" hexmask.long.byte 0x0 0.--3. 1. "S_SYSCLK,System clock switch status" group.long 0x4++0x13 line.long 0x0 "MCTL,Mode Control register" hexmask.long.byte 0x0 28.--31. 1. "TARGET_MODE,Target chip mode" hexmask.long.word 0x0 0.--15. 1. "KEY,Control key" line.long 0x4 "ME,Mode Enable register" bitfld.long 0x4 15. "RESET_DEST,Destructive RESET mode enable" "?,1: destructive RESET mode is enabled" bitfld.long 0x4 7. "RUN3,RUN3 mode enable" "0: RUN3 mode is disabled,1: RUN3 mode is enabled" newline bitfld.long 0x4 6. "RUN2,RUN2 mode enable" "0: RUN2 mode is disabled,1: RUN2 mode is enabled" bitfld.long 0x4 5. "RUN1,RUN1 mode enable" "0: RUN1 mode is disabled,1: RUN1 mode is enabled" newline bitfld.long 0x4 4. "RUN0,RUN0 mode enable" "?,1: RUN0 mode is enabled" bitfld.long 0x4 3. "DRUN,DRUN mode enable" "?,1: DRUN mode is enabled" newline bitfld.long 0x4 2. "SAFE,SAFE mode enable" "?,1: SAFE mode is enabled" bitfld.long 0x4 1. "TEST,TEST mode enable" "0: TEST mode is disabled,1: TEST mode is enabled" newline bitfld.long 0x4 0. "RESET_FUNC,Functional RESET mode enable" "?,1: functional RESET mode is enabled" line.long 0x8 "IS,Interrupt Status register" bitfld.long 0x8 5. "I_ICONF_CC,Invalid mode configuration interrupt (core configuration)" "0: No write to an ME_CADDRn register was attempted..,1: A write to an ME_CADDRn register was attempted.." bitfld.long 0x8 4. "I_ICONF_CU,Invalid mode configuration interrupt (Clock Usage)" "0: No invalid mode configuration (clock usage)..,1: ' to this bit" newline bitfld.long 0x8 3. "I_ICONF,Invalid mode configuration interrupt" "0: No invalid mode configuration interrupt occurred,1: ' to this bit" bitfld.long 0x8 2. "I_IMODE,Invalid mode interrupt" "0: No invalid mode interrupt occurred,1: ' to this bit" newline bitfld.long 0x8 1. "I_SAFE,SAFE mode interrupt" "0: No SAFE mode interrupt occurred,1: ' to this bit" bitfld.long 0x8 0. "I_MTC,Mode transition complete interrupt" "0: No mode transition complete interrupt occurred,1: ' to this bit" line.long 0xC "IM,Interrupt Mask register" bitfld.long 0xC 5. "M_ICONF_CC,Invalid mode configuration (core configuration) interrupt mask" "0: Invalid mode interrupt is masked,1: Invalid mode interrupt is enabled" bitfld.long 0xC 4. "M_ICONF_CU,Invalid mode configuration (clock usage) interrupt mask" "0: Invalid mode interrupt is masked,1: Invalid mode interrupt is enabled" newline bitfld.long 0xC 3. "M_ICONF,Invalid mode configuration interrupt mask" "0: Invalid mode interrupt is masked,1: Invalid mode interrupt is enabled" bitfld.long 0xC 2. "M_IMODE,Invalid mode interrupt mask" "0: Invalid mode interrupt is masked,1: Invalid mode interrupt is enabled" newline bitfld.long 0xC 1. "M_SAFE,SAFE mode interrupt mask" "0: SAFE mode interrupt is masked,1: SAFE mode interrupt is enabled" bitfld.long 0xC 0. "M_MTC,Mode transition complete interrupt mask" "0: Mode transition complete interrupt is masked,1: Mode transition complete interrupt is enabled" line.long 0x10 "IMTS,Invalid Mode Transition Status register" bitfld.long 0x10 5. "S_MRIG,Mode Request Ignored status" "0: Mode transition requested is not ignored,1: ' to this bit" bitfld.long 0x10 4. "S_MTI,Mode Transition Illegal status" "0: Mode transition requested is not illegal,1: ' to this bit" newline bitfld.long 0x10 3. "S_MRI,Mode Request Illegal status" "0: Target mode requested is not illegal with..,1: ' to this bit" bitfld.long 0x10 2. "S_DMA,Disabled Mode Access status" "0: Target mode requested is not a disabled mode,1: ' to this bit" newline bitfld.long 0x10 1. "S_NMA,Non-existing Mode Access status" "0: Target mode requested is an existing mode,1: ' to this bit" bitfld.long 0x10 0. "S_SEA,SAFE Event Active status" "0: No new mode requested other than RESET/SAFE..,1: ' to this bit" rgroup.long 0x18++0x3 line.long 0x0 "DMTS,Debug Mode Transition Status register" hexmask.long.byte 0x0 28.--31. 1. "PREVIOUS_MODE,Previous chip mode" bitfld.long 0x0 23. "MPH_BUSY,MC_ME Core/MC_PCU Handshake Busy indicator" "0: Handshake is not busy,1: Handshake is busy" newline bitfld.long 0x0 20. "PMC_PROG,MC_PCU Mode Change in Progress indicator" "0: Power-up/down transition is not in progress,1: Power-up/down transition is in progress" bitfld.long 0x0 19. "DBG_MODE,Debug mode indicator" "0: The chip is not in debug mode,1: The chip is in debug mode" newline bitfld.long 0x0 18. "CCKL_PROG,Core Clock Enable/Disable in Progress" "0: No core clock is being enabled or disabled,1: A core clock is being enabled or disabled" bitfld.long 0x0 17. "PCS_PROG,Progressive System Clock Switching in Progress" "0: PCS is not in progress,1: PCS is in progress" newline bitfld.long 0x0 16. "SMR,SAFE mode request from MC_RGM is active indicator" "0: A SAFE mode request is not active,1: A SAFE mode request is active" bitfld.long 0x0 14. "VREG_CSRC_SC,Main VREG dependent Clock Source State Change during mode transition indicator" "0: No state change is taking place,1: A state change is taking place" newline bitfld.long 0x0 13. "CSRC_CSRC_SC,(Other) Clock Source dependent Clock Source State Change during mode transition indicator" "0: No state change is taking place,1: A state change is taking place" bitfld.long 0x0 12. "IRC_SC,IRCOSC State Change during mode transition indicator" "0: No state change is taking place,1: A state change is taking place" newline bitfld.long 0x0 11. "SCSRC_SC,Secondary Clock Sources State Change during mode transition indicator" "0: No state change is taking place,1: A state change is taking place" bitfld.long 0x0 10. "SYSCLK_SW,System Clock Switching pending status" "0: No system clock source switching is pending,1: A system clock source switching is pending" newline bitfld.long 0x0 8. "NVM_SC,NVM State Change during mode transition indicator" "0: No state change is taking place,1: A state change is taking place" rgroup.long 0x20++0x3 line.long 0x0 "RESET_MC,RESET Mode Configuration register" bitfld.long 0x0 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." bitfld.long 0x0 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" newline bitfld.long 0x0 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" bitfld.long 0x0 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" newline bitfld.long 0x0 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" bitfld.long 0x0 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" newline bitfld.long 0x0 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" hexmask.long.byte 0x0 0.--3. 1. "SYSCLK,System clock switch control" group.long 0x24++0x1B line.long 0x0 "TEST_MC,TEST Mode Configuration register" bitfld.long 0x0 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x0 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" bitfld.long 0x0 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" newline bitfld.long 0x0 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" bitfld.long 0x0 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x0 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" bitfld.long 0x0 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x0 0.--3. 1. "SYSCLK,System clock switch control" line.long 0x4 "SAFE_MC,SAFE Mode Configuration register" bitfld.long 0x4 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" bitfld.long 0x4 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x4 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" bitfld.long 0x4 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" newline bitfld.long 0x4 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" bitfld.long 0x4 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x4 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" bitfld.long 0x4 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x4 0.--3. 1. "SYSCLK,System clock switch control" line.long 0x8 "DRUN_MC,DRUN Mode Configuration register" bitfld.long 0x8 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" bitfld.long 0x8 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x8 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" bitfld.long 0x8 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" newline bitfld.long 0x8 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" bitfld.long 0x8 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x8 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" bitfld.long 0x8 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x8 0.--3. 1. "SYSCLK,System clock switch control" line.long 0xC "RUN0_MC,RUNn Mode Configuration registers" bitfld.long 0xC 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" bitfld.long 0xC 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0xC 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" bitfld.long 0xC 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" newline bitfld.long 0xC 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" bitfld.long 0xC 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0xC 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" bitfld.long 0xC 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0xC 0.--3. 1. "SYSCLK,System clock switch control" line.long 0x10 "RUN1_MC,RUNn Mode Configuration registers" bitfld.long 0x10 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" bitfld.long 0x10 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x10 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" bitfld.long 0x10 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" newline bitfld.long 0x10 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" bitfld.long 0x10 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x10 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" bitfld.long 0x10 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x10 0.--3. 1. "SYSCLK,System clock switch control" line.long 0x14 "RUN2_MC,RUNn Mode Configuration registers" bitfld.long 0x14 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" bitfld.long 0x14 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x14 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" bitfld.long 0x14 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" newline bitfld.long 0x14 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" bitfld.long 0x14 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x14 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" bitfld.long 0x14 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x14 0.--3. 1. "SYSCLK,System clock switch control" line.long 0x18 "RUN3_MC,RUNn Mode Configuration registers" bitfld.long 0x18 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" bitfld.long 0x18 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x18 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" bitfld.long 0x18 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" newline bitfld.long 0x18 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" bitfld.long 0x18 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x18 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" bitfld.long 0x18 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x18 0.--3. 1. "SYSCLK,System clock switch control" group.long 0x80++0x1F line.long 0x0 "RUN_PC0,Run Peripheral Configuration registers" bitfld.long 0x0 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x0 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x0 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x0 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x0 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x0 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x0 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x0 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x4 "RUN_PC1,Run Peripheral Configuration registers" bitfld.long 0x4 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x4 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x4 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x4 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x4 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x4 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x4 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x4 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x8 "RUN_PC2,Run Peripheral Configuration registers" bitfld.long 0x8 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x8 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x8 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x8 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x8 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x8 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x8 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x8 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0xC "RUN_PC3,Run Peripheral Configuration registers" bitfld.long 0xC 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0xC 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0xC 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0xC 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0xC 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0xC 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0xC 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0xC 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x10 "RUN_PC4,Run Peripheral Configuration registers" bitfld.long 0x10 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x10 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x10 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x10 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x10 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x10 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x10 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x10 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x14 "RUN_PC5,Run Peripheral Configuration registers" bitfld.long 0x14 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x14 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x14 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x14 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x14 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x14 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x14 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x14 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x18 "RUN_PC6,Run Peripheral Configuration registers" bitfld.long 0x18 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x18 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x18 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x18 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x18 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x18 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x18 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x18 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x1C "RUN_PC7,Run Peripheral Configuration registers" bitfld.long 0x1C 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x1C 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x1C 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x1C 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x1C 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x1C 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x1C 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x1C 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" rgroup.long 0x1C0++0x3 line.long 0x0 "CS,Core Status register" bitfld.long 0x0 15. "S_CLUSTER_CORE1,Cluster n core 1" "0: cluster n core 1 is running.,1: cluster n core 1 is in WFI/WFE state." bitfld.long 0x0 14. "S_CLUSTER_CORE0,Cluster n core 0" "0: cluster n core 0 is running.,1: cluster n core 0 is in WFI/WFE state." newline bitfld.long 0x0 1. "S_CORE1,Core 1 status" "0: core 1 is disabled.,1: core 1 is running." bitfld.long 0x0 0. "S_CORE0,Core 0 status" "0: core 0 is disabled.,1: core 0 is running." group.word 0x1C4++0x3 line.word 0x0 "CCTL1,Core Control register" bitfld.word 0x0 7. "RUN3,Core control during RUN3" "0: core 1 is disabled with clock gated,1: core 1 is running" bitfld.word 0x0 6. "RUN2,Core control during RUN2" "0: core 1 is disabled with clock gated,1: core 1 is running" newline bitfld.word 0x0 5. "RUN1,Core control during RUN1" "0: core 1 is disabled with clock gated,1: core 1 is running" bitfld.word 0x0 4. "RUN0,Core control during RUN0" "0: core 1 is frozen with clock gated,1: core 1 is running" newline bitfld.word 0x0 3. "DRUN,Core control during DRUN" "0: core 1 is frozen with clock gated,1: core 1 is running" bitfld.word 0x0 2. "SAFE,Core control during SAFE" "0: core 1 is frozen with clock gated,1: core 1 is running" newline bitfld.word 0x0 1. "TEST,Core control during TEST" "0: core 1 is frozen with clock gated,1: core 1 is running" bitfld.word 0x0 0. "RESET,Core control during RESET" "0,1" line.word 0x2 "CCTL0,Core Control register 0" bitfld.word 0x2 7. "RUN3,Core control during RUN3" "0: core 0 is disabled with clock gated,1: core 0 is running" bitfld.word 0x2 6. "RUN2,Core control during RUN2" "0: core 0 is disabled with clock gated,1: core 0 is running" newline bitfld.word 0x2 5. "RUN1,Core control during RUN1" "0: core 0 is disabled with clock gated,1: core 0 is running" bitfld.word 0x2 4. "RUN0,Core control during RUN0" "0: core 0 is frozen with clock gated,1: core 0 is running" newline bitfld.word 0x2 3. "DRUN,Core control during DRUN" "0: core 0 is frozen with clock gated,1: core 0 is running" bitfld.word 0x2 2. "SAFE,Core control during SAFE" "0: core 0 is frozen with clock gated,1: core 0 is running" newline bitfld.word 0x2 1. "TEST,Core control during TEST" "0: core 0 is frozen with clock gated,1: core 0 is running" bitfld.word 0x2 0. "RESET,Core control during RESET" "0,1" group.long 0x1E0++0x7 line.long 0x0 "CADDR0,Core Address register 0" hexmask.long 0x0 2.--31. 1. "ADDR,Core Address" bitfld.long 0x0 0. "RMC,Reset on Mode Change" "0: Core 0 is not reset on the next mode change.,1: Core 0 is reset on the next mode change that has.." line.long 0x4 "CADDR1,Core Address register 1" hexmask.long 0x4 2.--31. 1. "ADDR,Core Address" bitfld.long 0x4 0. "RMC,Reset on Mode Change" "0: Core 1 is not reset on the next mode change,1: Core 1 is reset on the next mode change that has.." tree.end tree "MC_ME_DOMAIN_2" base ad:0x710D4000 rgroup.long 0x0++0x3 line.long 0x0 "GS,Global Status register" hexmask.long.byte 0x0 28.--31. 1. "S_CURRENT_MODE,Current chip mode status" bitfld.long 0x0 27. "S_MTRANS,Mode transition status" "0: Mode transition process is not active,1: Mode transition is ongoing" newline bitfld.long 0x0 23. "S_PDO,Output power-down status" "0: No automatic safe gating of I/Os used and pads..,?" bitfld.long 0x0 20. "S_MVR,Main voltage regulator status" "0: Main voltage regulator is not ready,1: Main voltage regulator is ready for use" newline bitfld.long 0x0 16.--17. "S_FLA,NVM availability status" "0: NVM is not available,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode and available for use" bitfld.long 0x0 7. "S_PLL1,PLL1 status" "0: PLL1 is not stable,1: PLL0 is providing a stable clock" newline bitfld.long 0x0 6. "S_PLL0,PLL0 status" "0: PLL0 is not stable,1: PLL0 is providing a stable clock" bitfld.long 0x0 5. "S_XOSC,XOSC status" "0: XOSC is not stable,1: XOSC is providing a stable clock" newline bitfld.long 0x0 4. "S_IRC,IRCOSC status" "0: IRCOSC is not stable,1: IRCOSC is providing a stable clock" hexmask.long.byte 0x0 0.--3. 1. "S_SYSCLK,System clock switch status" group.long 0x4++0x13 line.long 0x0 "MCTL,Mode Control register" hexmask.long.byte 0x0 28.--31. 1. "TARGET_MODE,Target chip mode" hexmask.long.word 0x0 0.--15. 1. "KEY,Control key" line.long 0x4 "ME,Mode Enable register" bitfld.long 0x4 15. "RESET_DEST,Destructive RESET mode enable" "?,1: destructive RESET mode is enabled" bitfld.long 0x4 7. "RUN3,RUN3 mode enable" "0: RUN3 mode is disabled,1: RUN3 mode is enabled" newline bitfld.long 0x4 6. "RUN2,RUN2 mode enable" "0: RUN2 mode is disabled,1: RUN2 mode is enabled" bitfld.long 0x4 5. "RUN1,RUN1 mode enable" "0: RUN1 mode is disabled,1: RUN1 mode is enabled" newline bitfld.long 0x4 4. "RUN0,RUN0 mode enable" "?,1: RUN0 mode is enabled" bitfld.long 0x4 3. "DRUN,DRUN mode enable" "?,1: DRUN mode is enabled" newline bitfld.long 0x4 2. "SAFE,SAFE mode enable" "?,1: SAFE mode is enabled" bitfld.long 0x4 1. "TEST,TEST mode enable" "0: TEST mode is disabled,1: TEST mode is enabled" newline bitfld.long 0x4 0. "RESET_FUNC,Functional RESET mode enable" "?,1: functional RESET mode is enabled" line.long 0x8 "IS,Interrupt Status register" bitfld.long 0x8 5. "I_ICONF_CC,Invalid mode configuration interrupt (core configuration)" "0: No write to an ME_CADDRn register was attempted..,1: A write to an ME_CADDRn register was attempted.." bitfld.long 0x8 4. "I_ICONF_CU,Invalid mode configuration interrupt (Clock Usage)" "0: No invalid mode configuration (clock usage)..,1: ' to this bit" newline bitfld.long 0x8 3. "I_ICONF,Invalid mode configuration interrupt" "0: No invalid mode configuration interrupt occurred,1: ' to this bit" bitfld.long 0x8 2. "I_IMODE,Invalid mode interrupt" "0: No invalid mode interrupt occurred,1: ' to this bit" newline bitfld.long 0x8 1. "I_SAFE,SAFE mode interrupt" "0: No SAFE mode interrupt occurred,1: ' to this bit" bitfld.long 0x8 0. "I_MTC,Mode transition complete interrupt" "0: No mode transition complete interrupt occurred,1: ' to this bit" line.long 0xC "IM,Interrupt Mask register" bitfld.long 0xC 5. "M_ICONF_CC,Invalid mode configuration (core configuration) interrupt mask" "0: Invalid mode interrupt is masked,1: Invalid mode interrupt is enabled" bitfld.long 0xC 4. "M_ICONF_CU,Invalid mode configuration (clock usage) interrupt mask" "0: Invalid mode interrupt is masked,1: Invalid mode interrupt is enabled" newline bitfld.long 0xC 3. "M_ICONF,Invalid mode configuration interrupt mask" "0: Invalid mode interrupt is masked,1: Invalid mode interrupt is enabled" bitfld.long 0xC 2. "M_IMODE,Invalid mode interrupt mask" "0: Invalid mode interrupt is masked,1: Invalid mode interrupt is enabled" newline bitfld.long 0xC 1. "M_SAFE,SAFE mode interrupt mask" "0: SAFE mode interrupt is masked,1: SAFE mode interrupt is enabled" bitfld.long 0xC 0. "M_MTC,Mode transition complete interrupt mask" "0: Mode transition complete interrupt is masked,1: Mode transition complete interrupt is enabled" line.long 0x10 "IMTS,Invalid Mode Transition Status register" bitfld.long 0x10 5. "S_MRIG,Mode Request Ignored status" "0: Mode transition requested is not ignored,1: ' to this bit" bitfld.long 0x10 4. "S_MTI,Mode Transition Illegal status" "0: Mode transition requested is not illegal,1: ' to this bit" newline bitfld.long 0x10 3. "S_MRI,Mode Request Illegal status" "0: Target mode requested is not illegal with..,1: ' to this bit" bitfld.long 0x10 2. "S_DMA,Disabled Mode Access status" "0: Target mode requested is not a disabled mode,1: ' to this bit" newline bitfld.long 0x10 1. "S_NMA,Non-existing Mode Access status" "0: Target mode requested is an existing mode,1: ' to this bit" bitfld.long 0x10 0. "S_SEA,SAFE Event Active status" "0: No new mode requested other than RESET/SAFE..,1: ' to this bit" rgroup.long 0x18++0x3 line.long 0x0 "DMTS,Debug Mode Transition Status register" hexmask.long.byte 0x0 28.--31. 1. "PREVIOUS_MODE,Previous chip mode" bitfld.long 0x0 23. "MPH_BUSY,MC_ME Core/MC_PCU Handshake Busy indicator" "0: Handshake is not busy,1: Handshake is busy" newline bitfld.long 0x0 20. "PMC_PROG,MC_PCU Mode Change in Progress indicator" "0: Power-up/down transition is not in progress,1: Power-up/down transition is in progress" bitfld.long 0x0 19. "DBG_MODE,Debug mode indicator" "0: The chip is not in debug mode,1: The chip is in debug mode" newline bitfld.long 0x0 18. "CCKL_PROG,Core Clock Enable/Disable in Progress" "0: No core clock is being enabled or disabled,1: A core clock is being enabled or disabled" bitfld.long 0x0 17. "PCS_PROG,Progressive System Clock Switching in Progress" "0: PCS is not in progress,1: PCS is in progress" newline bitfld.long 0x0 16. "SMR,SAFE mode request from MC_RGM is active indicator" "0: A SAFE mode request is not active,1: A SAFE mode request is active" bitfld.long 0x0 14. "VREG_CSRC_SC,Main VREG dependent Clock Source State Change during mode transition indicator" "0: No state change is taking place,1: A state change is taking place" newline bitfld.long 0x0 13. "CSRC_CSRC_SC,(Other) Clock Source dependent Clock Source State Change during mode transition indicator" "0: No state change is taking place,1: A state change is taking place" bitfld.long 0x0 12. "IRC_SC,IRCOSC State Change during mode transition indicator" "0: No state change is taking place,1: A state change is taking place" newline bitfld.long 0x0 11. "SCSRC_SC,Secondary Clock Sources State Change during mode transition indicator" "0: No state change is taking place,1: A state change is taking place" bitfld.long 0x0 10. "SYSCLK_SW,System Clock Switching pending status" "0: No system clock source switching is pending,1: A system clock source switching is pending" newline bitfld.long 0x0 8. "NVM_SC,NVM State Change during mode transition indicator" "0: No state change is taking place,1: A state change is taking place" rgroup.long 0x20++0x3 line.long 0x0 "RESET_MC,RESET Mode Configuration register" bitfld.long 0x0 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." bitfld.long 0x0 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" newline bitfld.long 0x0 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" bitfld.long 0x0 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" newline bitfld.long 0x0 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" bitfld.long 0x0 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" newline bitfld.long 0x0 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" hexmask.long.byte 0x0 0.--3. 1. "SYSCLK,System clock switch control" group.long 0x24++0x1B line.long 0x0 "TEST_MC,TEST Mode Configuration register" bitfld.long 0x0 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x0 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" bitfld.long 0x0 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" newline bitfld.long 0x0 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" bitfld.long 0x0 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x0 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" bitfld.long 0x0 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x0 0.--3. 1. "SYSCLK,System clock switch control" line.long 0x4 "SAFE_MC,SAFE Mode Configuration register" bitfld.long 0x4 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" bitfld.long 0x4 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x4 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" bitfld.long 0x4 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" newline bitfld.long 0x4 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" bitfld.long 0x4 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x4 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" bitfld.long 0x4 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x4 0.--3. 1. "SYSCLK,System clock switch control" line.long 0x8 "DRUN_MC,DRUN Mode Configuration register" bitfld.long 0x8 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" bitfld.long 0x8 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x8 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" bitfld.long 0x8 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" newline bitfld.long 0x8 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" bitfld.long 0x8 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x8 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" bitfld.long 0x8 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x8 0.--3. 1. "SYSCLK,System clock switch control" line.long 0xC "RUN0_MC,RUNn Mode Configuration registers" bitfld.long 0xC 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" bitfld.long 0xC 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0xC 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" bitfld.long 0xC 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" newline bitfld.long 0xC 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" bitfld.long 0xC 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0xC 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" bitfld.long 0xC 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0xC 0.--3. 1. "SYSCLK,System clock switch control" line.long 0x10 "RUN1_MC,RUNn Mode Configuration registers" bitfld.long 0x10 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" bitfld.long 0x10 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x10 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" bitfld.long 0x10 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" newline bitfld.long 0x10 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" bitfld.long 0x10 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x10 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" bitfld.long 0x10 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x10 0.--3. 1. "SYSCLK,System clock switch control" line.long 0x14 "RUN2_MC,RUNn Mode Configuration registers" bitfld.long 0x14 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" bitfld.long 0x14 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x14 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" bitfld.long 0x14 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" newline bitfld.long 0x14 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" bitfld.long 0x14 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x14 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" bitfld.long 0x14 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x14 0.--3. 1. "SYSCLK,System clock switch control" line.long 0x18 "RUN3_MC,RUNn Mode Configuration registers" bitfld.long 0x18 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" bitfld.long 0x18 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x18 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" bitfld.long 0x18 16.--17. "FLAON,NVM power-down control" "?,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode" newline bitfld.long 0x18 7. "PLL1ON,PLL1 control" "0: PLL1 is switched off,1: PLL1 is switched on" bitfld.long 0x18 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x18 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" bitfld.long 0x18 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x18 0.--3. 1. "SYSCLK,System clock switch control" group.long 0x80++0x1F line.long 0x0 "RUN_PC0,Run Peripheral Configuration registers" bitfld.long 0x0 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x0 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x0 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x0 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x0 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x0 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x0 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x0 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x4 "RUN_PC1,Run Peripheral Configuration registers" bitfld.long 0x4 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x4 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x4 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x4 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x4 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x4 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x4 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x4 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x8 "RUN_PC2,Run Peripheral Configuration registers" bitfld.long 0x8 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x8 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x8 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x8 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x8 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x8 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x8 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x8 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0xC "RUN_PC3,Run Peripheral Configuration registers" bitfld.long 0xC 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0xC 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0xC 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0xC 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0xC 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0xC 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0xC 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0xC 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x10 "RUN_PC4,Run Peripheral Configuration registers" bitfld.long 0x10 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x10 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x10 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x10 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x10 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x10 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x10 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x10 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x14 "RUN_PC5,Run Peripheral Configuration registers" bitfld.long 0x14 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x14 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x14 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x14 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x14 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x14 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x14 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x14 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x18 "RUN_PC6,Run Peripheral Configuration registers" bitfld.long 0x18 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x18 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x18 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x18 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x18 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x18 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x18 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x18 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x1C "RUN_PC7,Run Peripheral Configuration registers" bitfld.long 0x1C 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x1C 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x1C 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x1C 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x1C 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x1C 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x1C 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" bitfld.long 0x1C 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" rgroup.long 0x1C0++0x3 line.long 0x0 "CS,Core Status register" bitfld.long 0x0 15. "S_CLUSTER_CORE1,Cluster n core 1" "0: cluster n core 1 is running.,1: cluster n core 1 is in WFI/WFE state." bitfld.long 0x0 14. "S_CLUSTER_CORE0,Cluster n core 0" "0: cluster n core 0 is running.,1: cluster n core 0 is in WFI/WFE state." newline bitfld.long 0x0 1. "S_CORE1,Core 1 status" "0: core 1 is disabled.,1: core 1 is running." bitfld.long 0x0 0. "S_CORE0,Core 0 status" "0: core 0 is disabled.,1: core 0 is running." group.word 0x1C4++0x3 line.word 0x0 "CCTL1,Core Control register" bitfld.word 0x0 7. "RUN3,Core control during RUN3" "0: core 1 is disabled with clock gated,1: core 1 is running" bitfld.word 0x0 6. "RUN2,Core control during RUN2" "0: core 1 is disabled with clock gated,1: core 1 is running" newline bitfld.word 0x0 5. "RUN1,Core control during RUN1" "0: core 1 is disabled with clock gated,1: core 1 is running" bitfld.word 0x0 4. "RUN0,Core control during RUN0" "0: core 1 is frozen with clock gated,1: core 1 is running" newline bitfld.word 0x0 3. "DRUN,Core control during DRUN" "0: core 1 is frozen with clock gated,1: core 1 is running" bitfld.word 0x0 2. "SAFE,Core control during SAFE" "0: core 1 is frozen with clock gated,1: core 1 is running" newline bitfld.word 0x0 1. "TEST,Core control during TEST" "0: core 1 is frozen with clock gated,1: core 1 is running" bitfld.word 0x0 0. "RESET,Core control during RESET" "0,1" line.word 0x2 "CCTL0,Core Control register 0" bitfld.word 0x2 7. "RUN3,Core control during RUN3" "0: core 0 is disabled with clock gated,1: core 0 is running" bitfld.word 0x2 6. "RUN2,Core control during RUN2" "0: core 0 is disabled with clock gated,1: core 0 is running" newline bitfld.word 0x2 5. "RUN1,Core control during RUN1" "0: core 0 is disabled with clock gated,1: core 0 is running" bitfld.word 0x2 4. "RUN0,Core control during RUN0" "0: core 0 is frozen with clock gated,1: core 0 is running" newline bitfld.word 0x2 3. "DRUN,Core control during DRUN" "0: core 0 is frozen with clock gated,1: core 0 is running" bitfld.word 0x2 2. "SAFE,Core control during SAFE" "0: core 0 is frozen with clock gated,1: core 0 is running" newline bitfld.word 0x2 1. "TEST,Core control during TEST" "0: core 0 is frozen with clock gated,1: core 0 is running" bitfld.word 0x2 0. "RESET,Core control during RESET" "0,1" group.long 0x1E0++0x7 line.long 0x0 "CADDR0,Core Address register 0" hexmask.long 0x0 2.--31. 1. "ADDR,Core Address" bitfld.long 0x0 0. "RMC,Reset on Mode Change" "0: Core 0 is not reset on the next mode change.,1: Core 0 is reset on the next mode change that has.." line.long 0x4 "CADDR1,Core Address register 1" hexmask.long 0x4 2.--31. 1. "ADDR,Core Address" bitfld.long 0x4 0. "RMC,Reset on Mode Change" "0: Core 1 is not reset on the next mode change,1: Core 1 is reset on the next mode change that has.." tree.end tree "MC_ME_PERIPHERAL_DOMAIN" base ad:0x722E8000 rgroup.long 0x0++0x3 line.long 0x0 "GS,Global Status register" hexmask.long.byte 0x0 28.--31. 1. "S_CURRENT_MODE,Current chip mode status" newline bitfld.long 0x0 27. "S_MTRANS,Mode transition status" "0: Mode transition process is not active,1: Mode transition is ongoing" newline bitfld.long 0x0 23. "S_PDO,Output power-down status (see Device configuration chapter)" "0: No automatic safe gating of I/Os used and pads..,1: In STOP0 mode the slew rate control mechanism of.." newline bitfld.long 0x0 20. "S_MVR,Main voltage regulator status" "0: Main voltage regulator is not ready,1: Main voltage regulator is ready for use" newline bitfld.long 0x0 16.--17. "S_FLA,NVM availability status" "0: NVM is not available,1: NVM is in power-down mode,2: NVM is in low-power mode,3: NVM is in normal mode and available for use" newline bitfld.long 0x0 7. "S_PLL0_JM,PLL0_JM status" "0: PLL0_JM is not stable,1: PLL0_JM is providing a stable clock" newline bitfld.long 0x0 6. "S_PLL0,PLL0 status" "0: PLL0 is not stable,1: PLL0 is providing a stable clock" newline bitfld.long 0x0 5. "S_XOSC,XOSC status" "0: XOSC is not stable,1: XOSC is providing a stable clock" newline bitfld.long 0x0 4. "S_IRC,IRCOSC status" "0: IRCOSC is not stable,1: IRCOSC is providing a stable clock" newline hexmask.long.byte 0x0 0.--3. 1. "S_SYSCLK,System clock switch status" group.long 0x4++0x13 line.long 0x0 "MCTL,Mode Control register" hexmask.long.byte 0x0 28.--31. 1. "TARGET_MODE,Target chip mode" newline hexmask.long.word 0x0 0.--15. 1. "KEY,Control key" line.long 0x4 "ME,Mode Enable register" bitfld.long 0x4 15. "RESET_DEST,Destructive RESET mode enable" "?,1: destructive RESET mode is enabled" newline bitfld.long 0x4 13. "STANDBY0,STANDBY0 mode enable" "0: STANDBY0 mode is disabled,1: STANDBY0 mode is enabled" newline bitfld.long 0x4 10. "STOP0,STOP0 mode enable" "0: STOP0 mode is disabled,1: STOP0 mode is enabled" newline bitfld.long 0x4 7. "RUN3,RUN3 mode enable" "0: RUN3 mode is disabled,1: RUN3 mode is enabled" newline bitfld.long 0x4 6. "RUN2,RUN2 mode enable" "0: RUN2 mode is disabled,1: RUN2 mode is enabled" newline bitfld.long 0x4 5. "RUN1,RUN1 mode enable" "0: RUN1 mode is disabled,1: RUN1 mode is enabled" newline bitfld.long 0x4 4. "RUN0,RUN0 mode enable" "?,1: RUN0 mode is enabled" newline bitfld.long 0x4 3. "DRUN,DRUN mode enable" "?,1: DRUN mode is enabled" newline bitfld.long 0x4 2. "SAFE,SAFE mode enable" "?,1: SAFE mode is enabled" newline bitfld.long 0x4 1. "TEST,TEST mode enable" "0: TEST mode is disabled,1: TEST mode is enabled" newline bitfld.long 0x4 0. "RESET_FUNC,Functional RESET mode enable" "?,1: functional RESET mode is enabled" line.long 0x8 "IS,Interrupt Status register" bitfld.long 0x8 5. "I_ICONF_CC,Invalid mode configuration interrupt (core configuration)" "0: No write to an ME_CADDRn register was attempted..,1: A write to an ME_CADDRn register was attempted.." newline bitfld.long 0x8 4. "I_ICONF_CU,Invalid mode configuration interrupt (Clock Usage)" "0: No invalid mode configuration (clock usage)..,1: Invalid mode configuration (clock usage).." newline bitfld.long 0x8 3. "I_ICONF,Invalid mode configuration interrupt" "0: No invalid mode configuration interrupt occurred,1: Invalid mode configuration interrupt is pending" newline bitfld.long 0x8 2. "I_IMODE,Invalid mode interrupt" "0: No invalid mode interrupt occurred,1: Invalid mode interrupt is pending" newline bitfld.long 0x8 1. "I_SAFE,SAFE mode interrupt" "0: No SAFE mode interrupt occurred,1: SAFE mode interrupt is pending" newline bitfld.long 0x8 0. "I_MTC,Mode transition complete interrupt" "0: No mode transition complete interrupt occurred,1: Mode transition complete interrupt is pending" line.long 0xC "IM,Interrupt Mask register" bitfld.long 0xC 5. "M_ICONF_CC,Invalid mode configuration (core configuration) interrupt mask" "0: Invalid mode interrupt is masked,1: Invalid mode interrupt is enabled" newline bitfld.long 0xC 4. "M_ICONF_CU,Invalid mode configuration (clock usage) interrupt mask" "0: Invalid mode interrupt is masked,1: Invalid mode interrupt is enabled" newline bitfld.long 0xC 3. "M_ICONF,Invalid mode configuration interrupt mask" "0: Invalid mode interrupt is masked,1: Invalid mode interrupt is enabled" newline bitfld.long 0xC 2. "M_IMODE,Invalid mode interrupt mask" "0: Invalid mode interrupt is masked,1: Invalid mode interrupt is enabled" newline bitfld.long 0xC 1. "M_SAFE,SAFE mode interrupt mask" "0: SAFE mode interrupt is masked,1: SAFE mode interrupt is enabled" newline bitfld.long 0xC 0. "M_MTC,Mode transition complete interrupt mask" "0: Mode transition complete interrupt is masked,1: Mode transition complete interrupt is enabled" line.long 0x10 "IMTS,Invalid Mode Transition Status register" bitfld.long 0x10 5. "S_MRIG,Mode Request Ignored status" "0: Mode transition requested is not ignored,1: Mode transition requested is ignored" newline bitfld.long 0x10 4. "S_MTI,Mode Transition Illegal status" "0: Mode transition requested is not illegal,1: Mode transition requested is illegal" newline bitfld.long 0x10 3. "S_MRI,Mode Request Illegal status" "0: Target mode requested is not illegal with..,1: Target mode requested is illegal with respect to.." newline bitfld.long 0x10 2. "S_DMA,Disabled Mode Access status" "0: Target mode requested is not a disabled mode,1: Target mode requested is a disabled mode" newline bitfld.long 0x10 1. "S_NMA,Non-existing Mode Access status" "0: Target mode requested is an existing mode,1: Target mode requested is a non-existing mode" newline bitfld.long 0x10 0. "S_SEA,SAFE Event Active status" "0: No new mode requested other than RESET/SAFE..,1: New mode requested other than RESET/SAFE while.." rgroup.long 0x18++0x3 line.long 0x0 "DMTS,Debug Mode Transition Status register" hexmask.long.byte 0x0 28.--31. 1. "PREVIOUS_MODE,Previous chip mode" newline bitfld.long 0x0 23. "MPH_BUSY,MC_ME peripheral/MC_PCU Handshake Busy indicator" "0: Handshake is not busy,1: Handshake is busy" newline bitfld.long 0x0 20. "PMC_PROG,MC_PCU Mode Change in Progress indicator" "0: Power-up/down transition is not in progress,1: Power-up/down transition is in progress" newline bitfld.long 0x0 19. "DBG_MODE,Debug mode indicator" "0: The chip is not in debug mode,1: The chip is in debug mode" newline bitfld.long 0x0 18. "CCKL_PROG,Core Clock Enable/Disable in Progress" "0: No core clock is being enabled or disabled,1: A core clock is being enabled or disabled" newline bitfld.long 0x0 17. "PCS_PROG,Progressive System Clock Switching in Progress" "0: PCS is not in progress,1: PCS is in progress" newline bitfld.long 0x0 16. "SMR,SAFE mode request from MC_RGM Peripheral is active indicator" "0: A SAFE mode request is not active,1: A SAFE mode request is active" newline bitfld.long 0x0 15. "CDP_PRPH_0_255,Clock Disable Process Pending status for Peripherals 0-255" "0: No peripheral clock disabling is pending,1: Clock disabling is pending for at least one.." newline bitfld.long 0x0 14. "VREG_CSRC_SC,Main VREG dependent Clock Source State Change during mode transition indicator" "0: No state change is taking place,1: A state change is taking place" newline bitfld.long 0x0 13. "CSRC_CSRC_SC,(Other) Clock Source dependent Clock Source State Change during mode transition indicator" "0: No state change is taking place,1: A state change is taking place" newline bitfld.long 0x0 12. "IRC_SC,IRCOSC State Change during mode transition indicator" "0: No state change is taking place,1: A state change is taking place" newline bitfld.long 0x0 11. "SCSRC_SC,Secondary Clock Sources State Change during mode transition indicator" "0: No state change is taking place,1: A state change is taking place" newline bitfld.long 0x0 10. "SYSCLK_SW,System Clock Switching pending status" "0: No system clock source switching is pending,1: A system clock source switching is pending" newline bitfld.long 0x0 8. "NVM_SC,NVM State Change during mode transition indicator" "0: No state change is taking place,1: A state change is taking place" newline bitfld.long 0x0 7. "CDP_PRPH_224_255,Clock Disable Process Pending status for Peripherals 224-255(2)" "0: No peripheral clock disabling is pending,1: Clock disabling is pending for at least one.." newline bitfld.long 0x0 6. "CDP_PRPH_192_223,Clock Disable Process Pending status for Peripherals 192-223" "0: No peripheral clock disabling is pending,1: Clock disabling is pending for at least one.." newline bitfld.long 0x0 5. "CDP_PRPH_160_191,Clock Disable Process Pending status for Peripherals 160-191" "0: No peripheral clock disabling is pending,1: Clock disabling is pending for at least one.." newline bitfld.long 0x0 4. "CDP_PRPH_128_159,Clock Disable Process Pending status for Peripherals 128-159" "0: No peripheral clock disabling is pending,1: Clock disabling is pending for at least one.." newline bitfld.long 0x0 3. "CDP_PRPH_96_127,Clock Disable Process Pending status for Peripherals 96-127" "0: No peripheral clock disabling is pending,1: Clock disabling is pending for at least one.." newline bitfld.long 0x0 2. "CDP_PRPH_64_95,Clock Disable Process Pending status for Peripherals 64-95" "0: No peripheral clock disabling is pending,1: Clock disabling is pending for at least one.." newline bitfld.long 0x0 1. "CDP_PRPH_32_63,Clock Disable Process Pending status for Peripherals 32-63" "0: No peripheral clock disabling is pending,1: Clock disabling is pending for at least one.." newline bitfld.long 0x0 0. "CDP_PRPH_0_31,Clock Disable Process Pending status for Peripherals 0-31" "0: No peripheral clock disabling is pending,1: Clock disabling is pending for at least one.." rgroup.long 0x20++0x3 line.long 0x0 "RESET_MC,RESET Mode Configuration register" bitfld.long 0x0 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x0 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" newline bitfld.long 0x0 16.--17. "FLAON,NVM power-down control" "0,1,2,3" newline bitfld.long 0x0 7. "PLL_JM_ON,PLL0_JM control" "0: PLL0_JM is switched off,1: PLL0_JM is switched on" newline bitfld.long 0x0 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x0 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" newline bitfld.long 0x0 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x0 0.--3. 1. "SYSCLK,System clock switch control" group.long 0x24++0x1B line.long 0x0 "TEST_MC,TEST Mode Configuration register" bitfld.long 0x0 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x0 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" newline bitfld.long 0x0 16.--17. "FLAON,NVM power-down control" "0,1,2,3" newline bitfld.long 0x0 7. "PLL_JM_ON,PLL0_JM control" "0: PLL0_JM is switched off,1: PLL0_JM is switched on" newline bitfld.long 0x0 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x0 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" newline bitfld.long 0x0 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x0 0.--3. 1. "SYSCLK,System clock switch control" line.long 0x4 "SAFE_MC,SAFE Mode Configuration register" bitfld.long 0x4 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x4 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" newline bitfld.long 0x4 16.--17. "FLAON,NVM power-down control" "0,1,2,3" newline bitfld.long 0x4 7. "PLL_JM_ON,PLL0_JM control" "0: PLL0_JM is switched off,1: PLL0_JM is switched on" newline bitfld.long 0x4 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x4 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" newline bitfld.long 0x4 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x4 0.--3. 1. "SYSCLK,System clock switch control" line.long 0x8 "DRUN_MC,DRUN Mode Configuration register" bitfld.long 0x8 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x8 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" newline bitfld.long 0x8 16.--17. "FLAON,NVM power-down control" "0,1,2,3" newline bitfld.long 0x8 7. "PLL_JM_ON,PLL0_JM control" "0: PLL0_JM is switched off,1: PLL0_JM is switched on" newline bitfld.long 0x8 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x8 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" newline bitfld.long 0x8 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x8 0.--3. 1. "SYSCLK,System clock switch control" line.long 0xC "RUN0_MC,RUNn Mode Configuration registers" bitfld.long 0xC 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0xC 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" newline bitfld.long 0xC 16.--17. "FLAON,NVM power-down control" "0,1,2,3" newline bitfld.long 0xC 7. "PLL_JM_ON,PLL0_JM control" "0: PLL0_JM is switched off,1: PLL0_JM is switched on" newline bitfld.long 0xC 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0xC 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" newline bitfld.long 0xC 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0xC 0.--3. 1. "SYSCLK,System clock switch control" line.long 0x10 "RUN1_MC,RUNn Mode Configuration registers" bitfld.long 0x10 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x10 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" newline bitfld.long 0x10 16.--17. "FLAON,NVM power-down control" "0,1,2,3" newline bitfld.long 0x10 7. "PLL_JM_ON,PLL0_JM control" "0: PLL0_JM is switched off,1: PLL0_JM is switched on" newline bitfld.long 0x10 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x10 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" newline bitfld.long 0x10 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x10 0.--3. 1. "SYSCLK,System clock switch control" line.long 0x14 "RUN2_MC,RUNn Mode Configuration registers" bitfld.long 0x14 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x14 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" newline bitfld.long 0x14 16.--17. "FLAON,NVM power-down control" "0,1,2,3" newline bitfld.long 0x14 7. "PLL_JM_ON,PLL0_JM control" "0: PLL0_JM is switched off,1: PLL0_JM is switched on" newline bitfld.long 0x14 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x14 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" newline bitfld.long 0x14 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x14 0.--3. 1. "SYSCLK,System clock switch control" line.long 0x18 "RUN3_MC,RUNn Mode Configuration registers" bitfld.long 0x18 28.--30. "PWRLVL,Power level" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x18 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" newline bitfld.long 0x18 16.--17. "FLAON,NVM power-down control" "0,1,2,3" newline bitfld.long 0x18 7. "PLL_JM_ON,PLL0_JM control" "0: PLL0_JM is switched off,1: PLL0_JM is switched on" newline bitfld.long 0x18 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x18 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" newline bitfld.long 0x18 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x18 0.--3. 1. "SYSCLK,System clock switch control" group.long 0x48++0x3 line.long 0x0 "STOP0_MC,STOP0 Mode Configuration register" bitfld.long 0x0 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x0 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" newline bitfld.long 0x0 16.--17. "FLAON,NVM power-down control" "0,1,2,3" newline bitfld.long 0x0 7. "PLL_JM_ON,PLL0_JM control" "0: PLL0_JM is switched off,1: PLL0_JM is switched on" newline bitfld.long 0x0 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x0 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" newline bitfld.long 0x0 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x0 0.--3. 1. "SYSCLK,System clock switch control" group.long 0x54++0x3 line.long 0x0 "STANDBY0_MC,STANDBY0 Mode Configuration register" bitfld.long 0x0 23. "PDO,I/O output power-down control" "0: No automatic safe gating of I/Os used and pads..,1: In SAFE/TEST modes outputs of pads are forced to.." newline bitfld.long 0x0 20. "MVRON,Main voltage regulator control" "?,1: Main voltage regulator is switched on" newline bitfld.long 0x0 16.--17. "FLAON,NVM power-down control" "0,1,2,3" newline bitfld.long 0x0 7. "PLL_JM_ON,PLL0_JM control" "0: PLL0_JM is switched off,1: PLL0_JM is switched on" newline bitfld.long 0x0 6. "PLL0ON,PLL0 control" "0: PLL0 is switched off,1: PLL0 is switched on" newline bitfld.long 0x0 5. "XOSCON,XOSC control" "0: XOSC is switched off,1: XOSC is switched on" newline bitfld.long 0x0 4. "IRCON,IRCOSC control" "0: IRCOSC is switched off,1: IRCOSC is switched on" newline hexmask.long.byte 0x0 0.--3. 1. "SYSCLK,System clock switch control" group.long 0x80++0x3F line.long 0x0 "RUN_PC0,Run Peripheral Configuration registers" bitfld.long 0x0 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x0 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x0 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x0 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x0 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x0 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x0 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x0 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x4 "RUN_PC1,Run Peripheral Configuration registers" bitfld.long 0x4 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x4 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x4 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x4 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x4 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x4 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x4 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x4 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x8 "RUN_PC2,Run Peripheral Configuration registers" bitfld.long 0x8 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x8 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x8 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x8 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x8 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x8 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x8 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x8 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0xC "RUN_PC3,Run Peripheral Configuration registers" bitfld.long 0xC 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0xC 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0xC 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0xC 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0xC 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0xC 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0xC 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0xC 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x10 "RUN_PC4,Run Peripheral Configuration registers" bitfld.long 0x10 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x10 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x10 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x10 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x10 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x10 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x10 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x10 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x14 "RUN_PC5,Run Peripheral Configuration registers" bitfld.long 0x14 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x14 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x14 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x14 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x14 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x14 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x14 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x14 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x18 "RUN_PC6,Run Peripheral Configuration registers" bitfld.long 0x18 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x18 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x18 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x18 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x18 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x18 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x18 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x18 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x1C "RUN_PC7,Run Peripheral Configuration registers" bitfld.long 0x1C 7. "RUN3,Peripheral control during RUN3" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x1C 6. "RUN2,Peripheral control during RUN2" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x1C 5. "RUN1,Peripheral control during RUN1" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x1C 4. "RUN0,Peripheral control during RUN0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x1C 3. "DRUN,Peripheral control during DRUN" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x1C 2. "SAFE,Peripheral control during SAFE" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x1C 1. "TEST,Peripheral control during TEST" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x1C 0. "RESET,Peripheral control during RESET" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x20 "LP_PC0,Low-Power Peripheral Configuration registers" bitfld.long 0x20 13. "STANDBY0,Peripheral control during STANDBY0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x20 10. "STOP0,Peripheral control during STOP0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x24 "LP_PC1,Low-Power Peripheral Configuration registers" bitfld.long 0x24 13. "STANDBY0,Peripheral control during STANDBY0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x24 10. "STOP0,Peripheral control during STOP0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x28 "LP_PC2,Low-Power Peripheral Configuration registers" bitfld.long 0x28 13. "STANDBY0,Peripheral control during STANDBY0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x28 10. "STOP0,Peripheral control during STOP0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x2C "LP_PC3,Low-Power Peripheral Configuration registers" bitfld.long 0x2C 13. "STANDBY0,Peripheral control during STANDBY0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x2C 10. "STOP0,Peripheral control during STOP0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x30 "LP_PC4,Low-Power Peripheral Configuration registers" bitfld.long 0x30 13. "STANDBY0,Peripheral control during STANDBY0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x30 10. "STOP0,Peripheral control during STOP0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x34 "LP_PC5,Low-Power Peripheral Configuration registers" bitfld.long 0x34 13. "STANDBY0,Peripheral control during STANDBY0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x34 10. "STOP0,Peripheral control during STOP0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x38 "LP_PC6,Low-Power Peripheral Configuration registers" bitfld.long 0x38 13. "STANDBY0,Peripheral control during STANDBY0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x38 10. "STOP0,Peripheral control during STOP0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" line.long 0x3C "LP_PC7,Low-Power Peripheral Configuration registers" bitfld.long 0x3C 13. "STANDBY0,Peripheral control during STANDBY0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" newline bitfld.long 0x3C 10. "STOP0,Peripheral control during STOP0" "0: Peripheral is frozen with clock gated,1: Peripheral is active" rgroup.long 0x1C0++0x3 line.long 0x0 "CS,Core Status register" bitfld.long 0x0 15. "S_DSPH,DSPH core SLEEPING status" "0: DSPH core not in SLEEPING state,1: DSPH core in SLEEPING state" newline bitfld.long 0x0 14. "S_DME,DME core SLEEPING status" "0: DME core not in SLEEPING state,1: DME core in SLEEPING state" newline bitfld.long 0x0 1. "S_CORE1,DSPH clock status" "0: DSPH clock is disabled,1: DSPH clock is enabled" newline bitfld.long 0x0 0. "S_CORE0,DME clock status" "0: DME clock is disabled,1: DME clock is enabled" group.word 0x1C4++0x3 line.word 0x0 "CCTL1,Core Control register" bitfld.word 0x0 13. "STANDBY0,Core control during STANDBY0" "0,1" newline bitfld.word 0x0 10. "STOP0,Core control during STOP0" "0,1" newline bitfld.word 0x0 7. "RUN3,Core control during RUN3" "0: DSPH is disabled with clock gated,1: DSPH is running" newline bitfld.word 0x0 6. "RUN2,Core control during RUN2" "0: DSPH is disabled with clock gated,1: DSPH is running" newline bitfld.word 0x0 5. "RUN1,Core control during RUN1" "0: DSPH is disabled with clock gated,1: DSPH is running" newline bitfld.word 0x0 4. "RUN0,Core control during RUN0" "0: DSPH is frozen with clock gated,1: DSPH is running" newline bitfld.word 0x0 3. "DRUN,Core control during DRUN" "0: DSPH is frozen with clock gated,1: DSPH is running" newline bitfld.word 0x0 2. "SAFE,Core control during SAFE" "0: DSPH is frozen with clock gated,1: DSPH is running" newline bitfld.word 0x0 1. "TEST,Core control during TEST" "0: DSPH is frozen with clock gated,1: DSPH is running" newline bitfld.word 0x0 0. "RESET,Core control during RESET" "0,1" line.word 0x2 "CCTL0,Core Control register 0" bitfld.word 0x2 13. "STANDBY0,Core control during STANDBY0" "0,1" newline bitfld.word 0x2 10. "STOP0,Core control during STOP0" "0,1" newline bitfld.word 0x2 7. "RUN3,Core control during RUN3" "0: DME is disabled with clock gated,1: DME is running" newline bitfld.word 0x2 6. "RUN2,Core control during RUN2" "0: DME is disabled with clock gated,1: DME is running" newline bitfld.word 0x2 5. "RUN1,Core control during RUN1" "0: DME is disabled with clock gated,1: DME is running" newline bitfld.word 0x2 4. "RUN0,Core control during RUN0" "0: DME is frozen with clock gated,1: DME is running" newline bitfld.word 0x2 3. "DRUN,Core control during DRUN" "0: DME is frozen with clock gated,1: DME is running" newline bitfld.word 0x2 2. "SAFE,Core control during SAFE" "0: DME is frozen with clock gated,1: DME is running" newline bitfld.word 0x2 1. "TEST,Core control during TEST" "0: DME is frozen with clock gated,1: DME is running" newline bitfld.word 0x2 0. "RESET,Core control during RESET" "0,1" group.word 0x1CA++0x1 line.word 0x0 "CCTL2,Core Control register" bitfld.word 0x0 13. "STANDBY0,Core control during STANDBY0" "0,1" newline bitfld.word 0x0 10. "STOP0,Core control during STOP0" "0,1" newline bitfld.word 0x0 7. "RUN3,Core control during RUN3" "0: PD2 cores are disabled with clock gated,1: PD2 cores are running" newline bitfld.word 0x0 6. "RUN2,Core control during RUN2" "0: PD2 cores are disabled with clock gated,1: PD2 cores are running" newline bitfld.word 0x0 5. "RUN1,Core control during RUN1" "0: PD2 cores are disabled with clock gated,1: PD2 cores are running" newline bitfld.word 0x0 4. "RUN0,Core control during RUN0" "0: PD2 cores are frozen with clock gated,1: PD2 cores are running" newline bitfld.word 0x0 3. "DRUN,Core control during DRUN" "0: PD2 cores are frozen with clock gated,1: PD2 cores are running" newline bitfld.word 0x0 2. "SAFE,Core control during SAFE" "0: PD2 cores are frozen with clock gated,1: PD2 cores are running" newline bitfld.word 0x0 1. "TEST,Core control during TEST" "0: PD2 cores are frozen with clock gated,1: PD2 cores are running" newline bitfld.word 0x0 0. "RESET,Core control during RESET" "0,1" group.long 0x1E0++0xB line.long 0x0 "CADDR0,Core Address register 0" hexmask.long 0x0 2.--31. 1. "ADDR,Core Address" newline bitfld.long 0x0 0. "RMC,Reset on Mode Change" "0: DME is not reset on the next mode change.,1: DME is reset on the next mode change that has.." line.long 0x4 "CADDR1,Core Address register 1" hexmask.long 0x4 2.--31. 1. "ADDR,Core Address" newline bitfld.long 0x4 0. "RMC,Reset on Mode Change" "0: DSPH is not reset on the next mode change,1: DSPH is reset on the next mode change that has.." line.long 0x8 "CADDR2,Core Address register 2" hexmask.long 0x8 2.--31. 1. "ADDR,Core Address" newline bitfld.long 0x8 0. "RMC,Reset on Mode Change" "0,1" rgroup.long 0x204++0x1B line.long 0x0 "PS1_M0,Peripheral status register 1 for MODS0" bitfld.long 0x0 31. "S_GTM_0,GTM_0 status" "0: Peripheral is frozen,1: Peripheral is active" line.long 0x4 "PS2_M0,Peripheral status register 2 for MODS 0" bitfld.long 0x4 24. "S_LFAST_0,GTM_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 20. "S_SIPI_0,SIPI_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 1. "S_SYSCONF_0,SYSCONF_0 status" "0: Peripheral is frozen,1: Peripheral is active" line.long 0x8 "PS3_M0,Peripheral status register 3 for MODS 0" bitfld.long 0x8 30. "S_DSPL_0,DSPL_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 29. "S_DSPL_2,DSPL_2 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 28. "S_DSPL_4,DSPL_4 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 27. "S_DSPL_6,DSPL_6 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 26. "S_DSPL_8,DSPL_8 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 25. "S_DSPL_10,DSPL_10 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 19. "S_SAR_ADC_9BIT_0,SAR_ADC_9BIT_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 18. "S_SAR_ADC_9BIT_0_SEQ,SAR_ADC_9BIT_0_SEQ status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 17. "S_SAR_ADC_9BIT_2,SAR_ADC_9BIT_2 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 16. "S_SAR_ADC_9BIT_2_SEQ,SAR_ADC_9BIT_2_SEQ status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 13. "S_SAR_ADC_9BIT_6,SAR_ADC_9BIT_6 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 12. "S_SAR_ADC_9BIT_6_SEQ,SAR_ADC_9BIT_6_SEQ status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 5. "S_GST_0,GST_0 status" "0: Peripheral is frozen,1: Peripheral is active" line.long 0xC "PS4_M0,Peripheral status register 4 for MODS 0" bitfld.long 0xC 31. "S_SD_ADC_6,SDADC_6 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0xC 30. "S_SD_ADC_8,SDADC_8 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0xC 29. "S_SD_ADC_10,SDADC_10 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0xC 8. "S_DMAMUX_1_0_SYS_0,DMAMUX_1_0_SYS_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0xC 7. "S_DMAMUX_1_0_SYS_2,DMAMUX_1_0_SYS_2 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0xC 4. "S_CRC_0,CRC_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0xC 3. "S_CRC_2,CRC_2 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0xC 2. "S_CRC_4,CRC_4 status" "0: Peripheral is frozen,1: Peripheral is active" line.long 0x10 "PS5_M0,Peripheral status register 5 for MODS 0" bitfld.long 0x10 22. "S_SAR_ADCQ_12BIT_SV_0,SAR_ADCQ_12BIT_SV_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x10 21. "S_SAR_ADCQ_12BIT_0,SAR_ADCQ_12BIT_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x10 20. "S_SAR_ADCQ_12BIT_2,SAR_ADCQ_12BIT_2 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x10 19. "S_SAR_ADCQ_12BIT_4,SAR_ADCQ_12BIT_4 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x10 18. "S_SAR_ADCQ_12BIT_6,SAR_ADCQ_12BIT_6 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x10 17. "S_SAR_ADCQ_12BIT_8,SAR_ADCQ_12BIT_8 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x10 16. "S_SAR_ADCQ_12BIT_10,SAR_ADCQ_12BIT_10 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x10 2. "S_SD_ADC_0,SDADC_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x10 1. "S_SD_ADC_2,SDADC_2 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x10 0. "S_SD_ADC_4,SDADC_4 status" "0: Peripheral is frozen,1: Peripheral is active" line.long 0x14 "PS6_M0,Peripheral status register 6 for MODS 0" bitfld.long 0x14 30. "S_SAR_ADC_12BIT_SV_0,SAR_ADC_12BIT_SV_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 29. "S_SAR_ADC_12BIT_SV_0_SEQ,SAR_ADC_12BIT_SV_0_SEQ status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 28. "S_SAR_ADC_12BIT_0,SAR_ADC_12BIT_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 27. "S_SAR_ADC_12BIT_0_SEQ,SAR_ADC_12BIT_0_SEQ status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 26. "S_SAR_ADC_12BIT_2,SAR_ADC_12BIT_2 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 25. "S_SAR_ADC_12BIT_2_SEQ,SAR_ADC_12BIT_2_SEQ status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 24. "S_SAR_ADC_12BIT_4,SAR_ADC_12BIT_4 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 23. "S_SAR_ADC_12BIT_4_SEQ,SAR_ADC_12BIT_4_SEQ status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 22. "S_SAR_ADC_12BIT_6,SAR_ADC_12BIT_6 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 21. "S_SAR_ADC_12BIT_6_SEQ,SAR_ADC_12BIT_6_SEQ status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 20. "S_SAR_ADC_12BIT_8,SAR_ADC_12BIT_8 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 19. "S_SAR_ADC_12BIT_8_SEQ,SAR_ADC_12BIT_8_SEQ status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 18. "S_SAR_ADC_12BIT_10,SAR_ADC_12BIT_10 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 17. "S_SAR_ADC_12BIT_10_SEQ,SAR_ADC_12BIT_10_SEQ status" "0: Peripheral is frozen,1: Peripheral is active" line.long 0x18 "PS7_M0,Peripheral status register 7 for MODS 0" bitfld.long 0x18 19. "S_M_CAN_1_SUB_2,M_CAN_1_SUB_2 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x18 18. "S_M_CAN_2_SUB_2,M_CAN_2_SUB_2 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x18 17. "S_M_CAN_3_SUB_2,M_CAN_3_SUB_2 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x18 16. "S_M_CAN_4_SUB_2,M_CAN_4_SUB_2 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x18 13. "S_CAN_RAM_SUB_2,CAN_RAM_SUB_2 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x18 8. "S_M_CAN_1_SUB_4,M_CAN_1_SUB_4 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x18 7. "S_M_CAN_2_SUB_4,M_CAN_2_SUB_4 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x18 6. "S_M_CAN_3_SUB_4,M_CAN_3_SUB_4 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x18 5. "S_M_CAN_4_SUB_4,M_CAN_4_SUB_4 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x18 2. "S_CAN_RAM_SUB_4,CAN_RAM_SUB_4 status" "0: Peripheral is frozen,1: Peripheral is active" rgroup.long 0x224++0x1B line.long 0x0 "PS1_M1,Peripheral status register 1 for MODS 1" bitfld.long 0x0 31. "S_GTM_1,GTM_1 status" "0: Peripheral is frozen,1: Peripheral is active" line.long 0x4 "PS2_M1,Peripheral status register 2 for MODS 1" bitfld.long 0x4 24. "S_LFAST_1,LFAST_1 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 20. "S_SIPI_1,SIPI_1 status" "0: Peripheral is frozen,1: Peripheral is active" line.long 0x8 "PS3_M1,Peripheral status register 3 for MODS 1" bitfld.long 0x8 30. "S_DSPL_1,DSPL_1 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 29. "S_DSPL_3,DSPL_3 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 28. "S_DSPL_5,DSPL_5 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 27. "S_DSPL_7,DSPL_7 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 26. "S_DSPL_9,DSPL_9 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 25. "S_DSPL_11,DSPL_11 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 17. "S_SAR_ADC_9BIT_3,SAR_ADC_9BIT_3 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 16. "S_SAR_ADC_9BIT_3_SEQ,SAR_ADC_9BIT_3_SEQ status" "0: Peripheral is frozen,1: Peripheral is active" line.long 0xC "PS4_M1,Peripheral status register 4 for MODS 1" bitfld.long 0xC 31. "S_SD_ADC_7,SDADC_7 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0xC 30. "S_SD_ADC_9,SDADC_9 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0xC 29. "S_SD_ADC_11,SDADC_11 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0xC 8. "S_DMAMUX_1_0_SYS_1,DMAMUX_1_0_SYS_1 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0xC 7. "S_DMAMUX_3_0_SYS_3,DMAMUX_3_0_SYS_3 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0xC 4. "S_CRC_1,CRC_1 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0xC 3. "S_CRC_3,CRC_3 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0xC 2. "S_CRC_5,CRC_5 status" "0: Peripheral is frozen,1: Peripheral is active" line.long 0x10 "PS5_M1,Peripheral status register 5 for MODS 1" bitfld.long 0x10 21. "S_SAR_ADCQ_12BIT_1,SAR_ADCQ_12BIT_1 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x10 20. "S_SAR_ADCQ_12BIT_3,SAR_ADCQ_12BIT_3 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x10 19. "S_SAR_ADCQ_12BIT_5,SAR_ADCQ_12BIT_5 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x10 18. "S_SAR_ADCQ_12BIT_7,SAR_ADCQ_12BIT_7 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x10 17. "S_SAR_ADCQ_12BIT_9,SAR_ADCQ_12BIT_9 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x10 2. "S_SD_ADC_1,SDADC_1 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x10 1. "S_SD_ADC_3,SDADC_3 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x10 0. "S_SD_ADC_5,SDADC_5 status" "0: Peripheral is frozen,1: Peripheral is active" line.long 0x14 "PS6_M1,Peripheral status register 6 for MODS 1" bitfld.long 0x14 28. "S_SAR_ADC_12BIT_1,SAR_ADC_12BIT_1 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 27. "S_SAR_ADC_12BIT_1_SEQ,SAR_ADC_12BIT_1_SEQ status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 26. "S_SAR_ADC_12BIT_3,SAR_ADC_12BIT_3 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 25. "S_SAR_ADC_12BIT_3_SEQ,SAR_ADC_12BIT_3_SEQ status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 24. "S_SAR_ADC_12BIT_5,SAR_ADC_12BIT_5 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 23. "S_SAR_ADC_12BIT_5_SEQ,SAR_ADC_12BIT_5_SEQ status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 22. "S_SAR_ADC_12BIT_7,SAR_ADC_12BIT_7 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 21. "S_SAR_ADC_12BIT_7_SEQ,SAR_ADC_12BIT_7_SEQ status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 20. "S_SAR_ADC_12BIT_9,SAR_ADC_12BIT_9 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x14 19. "S_SAR_ADC_12BIT_9_SEQ,SAR_ADC_12BIT_9_SEQ status" "0: Peripheral is frozen,1: Peripheral is active" line.long 0x18 "PS7_M1,Peripheral status register 7 for MODS 1" bitfld.long 0x18 30. "S_M_CAN_1_SUB_1,M_CAN_1_SUB_1 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x18 29. "S_M_CAN_2_SUB_1,M_CAN_2_SUB_1 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x18 28. "S_M_CAN_3_SUB_1,M_CAN_3_SUB_1 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x18 27. "S_M_CAN_4_SUB_1,M_CAN_4_SUB_1 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x18 24. "S_CAN_RAM_SUB_1,CAN_RAM_SUB_1 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x18 19. "S_M_CAN_1_SUB_3,M_CAN_1_SUB_3 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x18 18. "S_M_CAN_2_SUB_3,M_CAN_2_SUB_3 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x18 17. "S_M_CAN_3_SUB_3,M_CAN_3_SUB_3 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x18 16. "S_M_CAN_4_SUB_3,M_CAN_4_SUB_3 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x18 13. "S_CAN_RAM_SUB_3,CAN_RAM_SUB_3 status" "0: Peripheral is frozen,1: Peripheral is active" rgroup.long 0x244++0x3 line.long 0x0 "PS1_M2,Peripheral status register 1 for MODS 2" bitfld.long 0x0 5. "S_SIUL_0,S_SIUL_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x0 4. "S_SIUL_2,S_SIUL_1 status" "0: Peripheral is frozen,1: Peripheral is active" rgroup.long 0x254++0xB line.long 0x0 "PS5_M2,Peripheral status register 5 for MODS 2" bitfld.long 0x0 29. "S_PSI5S_0,PSI5S_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x0 10. "S_OCTOSPI_0,OCTOSPI_0 status" "0: Peripheral is frozen,1: Peripheral is active" line.long 0x4 "PS6_M2,Peripheral status register 6 for MODS 2" bitfld.long 0x4 31. "S_SPIQ_8,SPIQ_8 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 27. "S_LINFLEXD_20,LINFLEXD_20 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 26. "S_LINFLEXD_22,LINFLEXD_22 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 25. "S_LINFLEXD_24,LINFLEXD_24 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 24. "S_LINFLEXD_26,LINFLEXD_26 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 16. "S_LINFLEXD_2,LINFLEXD_2 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 15. "S_LINFLEXD_4,LINFLEXD_4 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 14. "S_LINFLEXD_6,LINFLEXD_6 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 13. "S_LINFLEXD_8,LINFLEXD_8 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 12. "S_LINFLEXD_10,LINFLEXD_10 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 11. "S_LINFLEXD_12,LINFLEXD_12 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 10. "S_LINFLEXD_14,LINFLEXD_14 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 9. "S_LINFLEXD_16,LINFLEXD_16 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 8. "S_LINFLEXD_18,LINFLEXD_18 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 5. "S_SENT_0,SENT_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 1. "S_PSI5_0,PSI5_0 status" "0: Peripheral is frozen,1: Peripheral is active" line.long 0x8 "PS7_M2,Peripheral status register 7 for MODS 2" bitfld.long 0x8 25. "S_FLEXRAY_0,FLEXRAY_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 11. "S_DSPI_0,DSPI_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 9. "S_DSPI_4,DSPI_4 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 3. "S_SPIQ_0,SPIQ_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 1. "S_SPIQ_4,SPIQ_4 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 0. "S_SPIQ_6,SPIQ_6 status" "0: Peripheral is frozen,1: Peripheral is active" rgroup.long 0x274++0xB line.long 0x0 "PS5_M3,Peripheral status register 5 for MODS 3" bitfld.long 0x0 29. "S_PSI5S_1,PSI5S_1 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x0 26. "S_IIC_1,IIC_1 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x0 3. "S_MSCP_1,MSCP_1 status" "0: Peripheral is frozen,1: Peripheral is active" line.long 0x4 "PS6_M3,Peripheral status register 6 for MODS 3" bitfld.long 0x4 27. "S_LINFLEXD_21,LINFLEXD_21 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 26. "S_LINFLEXD_23,LINFLEXD_23 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 25. "S_LINFLEXD_25,LINFLEXD_25 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 24. "S_LINFLEXD_27,LINFLEXD_27 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 16. "S_LINFLEXD_3,LINFLEXD_3 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 15. "S_LINFLEXD_5,LINFLEXD_5 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 14. "S_LINFLEXD_7,LINFLEXD_7 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 13. "S_LINFLEXD_9,LINFLEXD_9 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 12. "S_LINFLEXD_11,LINFLEXD_11 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 11. "S_LINFLEXD_13,LINFLEXD_13 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 10. "S_LINFLEXD_15,LINFLEXD_15 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 9. "S_LINFLEXD_17,LINFLEXD_17 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 8. "S_LINFLEXD_19,LINFLEXD_19 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 5. "S_SENT_1,SENT_1 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 1. "S_PSI5_1,PSI5_1 status" "0: Peripheral is frozen,1: Peripheral is active" line.long 0x8 "PS7_M3,Peripheral status register 7 for MODS 3" bitfld.long 0x8 25. "S_FLEXRAY_1,FLEXRAY_1 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 17. "S_MSC_1,MSC_1 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 8. "S_DSPI_7,DSPI_7 status" "0: Peripheral is frozen,1: Peripheral is active" rgroup.long 0x288++0x3 line.long 0x0 "PS2_M4,Peripheral status register 2 for MODS 4" bitfld.long 0x0 1. "S_SYSCONF_4,SYSCONF_4 status" "0: Peripheral is frozen,1: Peripheral is active" rgroup.long 0x298++0x7 line.long 0x0 "PS6_M4,Peripheral status register 6 for MODS 4" bitfld.long 0x0 28. "S_DSPI_1,DSPI_1 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x0 27. "S_DSPI_2,DSPI_2 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x0 26. "S_DSPI_3,DSPI_3 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x0 24. "S_DSPI_5,DSPI_5 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x0 23. "S_DSPI_6,DSPI_6 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x0 21. "S_DSPI_8,DSPI_8 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x0 20. "S_DSPI_9,DSPI_9 status" "0: Peripheral is frozen,1: Peripheral is active" line.long 0x4 "PS7_M4,Peripheral status register 7 for MODS 4" bitfld.long 0x4 31. "S_ETHERNET_0,ETHERNET_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 30. "S_ETHERNET_1,ETHERNET_1 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 27. "S_CM_1,CM_1 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 26. "S_CM_2,CM_2 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 20. "S_SPIQ_1,SPIQ_1 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 18. "S_SPIQ_3,SPIQ_3 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 14. "S_SPIQ_7,SPIQ_7 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 12. "S_SPIQ_9,SPIQ_9 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 7. "S_MSC_0,MSC_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 5. "S_MSC_2,MSC_2 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 4. "S_MSC_3,MSC_3 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 1. "S_MSCP_0,MSCP_0 status" "0: Peripheral is frozen,1: Peripheral is active" rgroup.long 0x2A8++0x7 line.long 0x0 "PS2_M5,Peripheral status register 2 for MODS 5" bitfld.long 0x0 1. "S_SYSCONF_5,SYSCONF_5 status" "0: Peripheral is frozen,1: Peripheral is active" line.long 0x4 "PS3_M5,Peripheral status register 3 for MODS 5" bitfld.long 0x4 19. "S_SAR_ADC_LP_RUN_0,SAR_ADC_LP_RUN_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 18. "S_SAR_ADC_LP_RUN_0_SEQ,SAR_ADC_LP_RUN_0_SEQ status" "0: Peripheral is frozen,1: Peripheral is active" rgroup.long 0x2B4++0xB line.long 0x0 "PS5_M5,Peripheral status register 5 for MODS 5" bitfld.long 0x0 26. "S_IIC_0,IIC_0 status" "0: Peripheral is frozen,1: Peripheral is active" line.long 0x4 "PS6_M5,Peripheral status register 6 for MODS 5" bitfld.long 0x4 17. "S_LINFLEXD_0,S_LINFLEXD_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x4 16. "S_LINFLEXD_1,S_LINFLEXD_1 status" "0: Peripheral is frozen,1: Peripheral is active" line.long 0x8 "PS7_M5,Peripheral status register 7 for MODS 5" bitfld.long 0x8 31. "S_M_TTCAN_0_SUB_0,M_TTCAN_0_SUB_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 30. "S_M_CAN_1_SUB_0,M_CAN_1_SUB_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 29. "S_M_CAN_2_SUB_0,M_CAN_2_SUB_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 28. "S_M_CAN_3_SUB_0,M_CAN_3_SUB_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 24. "S_CAN_RAM_SUB_0,CAN_RAM_SUB_0 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 19. "S_SPIQ_2,SPIQ_2 status" "0: Peripheral is frozen,1: Peripheral is active" newline bitfld.long 0x8 16. "S_SPIQ_5,SPIQ_5 status" "0: Peripheral is frozen,1: Peripheral is active" group.byte 0x43C++0x0 line.byte 0x0 "PCTL63,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x442++0x0 line.byte 0x0 "PCTL65,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x457++0x0 line.byte 0x0 "PCTL84,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x45B++0x0 line.byte 0x0 "PCTL88,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x466++0x0 line.byte 0x0 "PCTL101,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x46E++0x5 line.byte 0x0 "PCTL109,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL108,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL115,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x3 "PCTL114,Peripheral Control registers" bitfld.byte 0x3 6. "RES,Reserved" "0,1" newline bitfld.byte 0x3 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x3 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x4 "PCTL113,Peripheral Control registers" bitfld.byte 0x4 6. "RES,Reserved" "0,1" newline bitfld.byte 0x4 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x4 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x5 "PCTL112,Peripheral Control registers" bitfld.byte 0x5 6. "RES,Reserved" "0,1" newline bitfld.byte 0x5 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x5 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x478++0x2 line.byte 0x0 "PCTL123,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL122,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL121,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x47D++0x4 line.byte 0x0 "PCTL126,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL125,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL124,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x3 "PCTL131,Peripheral Control registers" bitfld.byte 0x3 6. "RES,Reserved" "0,1" newline bitfld.byte 0x3 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x3 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x4 "PCTL130,Peripheral Control registers" bitfld.byte 0x4 6. "RES,Reserved" "0,1" newline bitfld.byte 0x4 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x4 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x484++0x0 line.byte 0x0 "PCTL135,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x487++0x0 line.byte 0x0 "PCTL132,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x48B++0x0 line.byte 0x0 "PCTL136,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x49C++0x2 line.byte 0x0 "PCTL159,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL158,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL157,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x4A1++0x2 line.byte 0x0 "PCTL162,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL161,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL160,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x4B0++0x3 line.byte 0x0 "PCTL179,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL178,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL177,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x3 "PCTL176,Peripheral Control registers" bitfld.byte 0x3 6. "RES,Reserved" "0,1" newline bitfld.byte 0x3 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x3 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x4B5++0x2 line.byte 0x0 "PCTL182,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL181,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL180,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x4D0++0x2 line.byte 0x0 "PCTL211,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL210,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL209,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x4D4++0x7 line.byte 0x0 "PCTL215,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL214,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL213,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x3 "PCTL212,Peripheral Control registers" bitfld.byte 0x3 6. "RES,Reserved" "0,1" newline bitfld.byte 0x3 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x3 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x4 "PCTL219,Peripheral Control registers" bitfld.byte 0x4 6. "RES,Reserved" "0,1" newline bitfld.byte 0x4 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x4 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x5 "PCTL218,Peripheral Control registers" bitfld.byte 0x5 6. "RES,Reserved" "0,1" newline bitfld.byte 0x5 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x5 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x6 "PCTL217,Peripheral Control registers" bitfld.byte 0x6 6. "RES,Reserved" "0,1" newline bitfld.byte 0x6 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x6 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x7 "PCTL216,Peripheral Control registers" bitfld.byte 0x7 6. "RES,Reserved" "0,1" newline bitfld.byte 0x7 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x7 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x4DD++0x2 line.byte 0x0 "PCTL222,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL221,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL220,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x4E1++0x0 line.byte 0x0 "PCTL226,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x4E4++0x2 line.byte 0x0 "PCTL231,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL230,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL229,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x4EB++0x0 line.byte 0x0 "PCTL232,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x4EE++0x0 line.byte 0x0 "PCTL237,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x4F0++0x3 line.byte 0x0 "PCTL243,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL242,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL241,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x3 "PCTL240,Peripheral Control registers" bitfld.byte 0x3 6. "RES,Reserved" "0,1" newline bitfld.byte 0x3 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x3 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x53C++0x0 line.byte 0x0 "PCTL319,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x557++0x0 line.byte 0x0 "PCTL340,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x55B++0x0 line.byte 0x0 "PCTL344,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x572++0x1 line.byte 0x0 "PCTL369,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL368,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x578++0x2 line.byte 0x0 "PCTL379,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL378,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL377,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x57D++0x4 line.byte 0x0 "PCTL382,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL381,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL380,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x3 "PCTL387,Peripheral Control registers" bitfld.byte 0x3 6. "RES,Reserved" "0,1" newline bitfld.byte 0x3 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x3 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x4 "PCTL386,Peripheral Control registers" bitfld.byte 0x4 6. "RES,Reserved" "0,1" newline bitfld.byte 0x4 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x4 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x584++0x0 line.byte 0x0 "PCTL391,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x587++0x0 line.byte 0x0 "PCTL388,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x58B++0x0 line.byte 0x0 "PCTL392,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x59C++0x2 line.byte 0x0 "PCTL415,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL414,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL413,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x5A1++0x2 line.byte 0x0 "PCTL418,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL417,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL416,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x5B0++0x2 line.byte 0x0 "PCTL435,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL434,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL433,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x5B6++0x1 line.byte 0x0 "PCTL437,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL436,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x5D0++0x0 line.byte 0x0 "PCTL467,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x5D4++0x7 line.byte 0x0 "PCTL471,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL470,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL469,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x3 "PCTL468,Peripheral Control registers" bitfld.byte 0x3 6. "RES,Reserved" "0,1" newline bitfld.byte 0x3 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x3 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x4 "PCTL475,Peripheral Control registers" bitfld.byte 0x4 6. "RES,Reserved" "0,1" newline bitfld.byte 0x4 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x4 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x5 "PCTL474,Peripheral Control registers" bitfld.byte 0x5 6. "RES,Reserved" "0,1" newline bitfld.byte 0x5 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x5 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x6 "PCTL473,Peripheral Control registers" bitfld.byte 0x6 6. "RES,Reserved" "0,1" newline bitfld.byte 0x6 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x6 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x7 "PCTL472,Peripheral Control registers" bitfld.byte 0x7 6. "RES,Reserved" "0,1" newline bitfld.byte 0x7 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x7 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x5DF++0x0 line.byte 0x0 "PCTL476,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x5EE++0x0 line.byte 0x0 "PCTL493,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x5F0++0x3 line.byte 0x0 "PCTL499,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL498,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL497,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x3 "PCTL496,Peripheral Control registers" bitfld.byte 0x3 6. "RES,Reserved" "0,1" newline bitfld.byte 0x3 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x3 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x5F8++0x0 line.byte 0x0 "PCTL507,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x5FB++0x0 line.byte 0x0 "PCTL504,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x5FD++0x2 line.byte 0x0 "PCTL510,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL509,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL508,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x626++0x1 line.byte 0x0 "PCTL549,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL548,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x6A9++0x0 line.byte 0x0 "PCTL682,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x6BE++0x0 line.byte 0x0 "PCTL701,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x6C2++0x0 line.byte 0x0 "PCTL705,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x6C6++0x0 line.byte 0x0 "PCTL709,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x6C8++0x7 line.byte 0x0 "PCTL715,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL714,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL713,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x3 "PCTL712,Peripheral Control registers" bitfld.byte 0x3 6. "RES,Reserved" "0,1" newline bitfld.byte 0x3 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x3 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x4 "PCTL719,Peripheral Control registers" bitfld.byte 0x4 6. "RES,Reserved" "0,1" newline bitfld.byte 0x4 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x4 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x5 "PCTL718,Peripheral Control registers" bitfld.byte 0x5 6. "RES,Reserved" "0,1" newline bitfld.byte 0x5 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x5 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x6 "PCTL717,Peripheral Control registers" bitfld.byte 0x6 6. "RES,Reserved" "0,1" newline bitfld.byte 0x6 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x6 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x7 "PCTL716,Peripheral Control registers" bitfld.byte 0x7 6. "RES,Reserved" "0,1" newline bitfld.byte 0x7 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x7 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x6D3++0x0 line.byte 0x0 "PCTL720,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x6D8++0x4 line.byte 0x0 "PCTL731,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL730,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL729,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x3 "PCTL728,Peripheral Control registers" bitfld.byte 0x3 6. "RES,Reserved" "0,1" newline bitfld.byte 0x3 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x3 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x4 "PCTL735,Peripheral Control registers" bitfld.byte 0x4 6. "RES,Reserved" "0,1" newline bitfld.byte 0x4 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x4 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x6E0++0x0 line.byte 0x0 "PCTL739,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x6E2++0x1 line.byte 0x0 "PCTL737,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL736,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x6E8++0x0 line.byte 0x0 "PCTL747,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x6EA++0x0 line.byte 0x0 "PCTL745,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x6FA++0x0 line.byte 0x0 "PCTL761,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x7A0++0x0 line.byte 0x0 "PCTL931,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x7B9++0x0 line.byte 0x0 "PCTL954,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x7BE++0x0 line.byte 0x0 "PCTL957,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x7C2++0x0 line.byte 0x0 "PCTL961,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x7C6++0x0 line.byte 0x0 "PCTL965,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x7C8++0x7 line.byte 0x0 "PCTL971,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL970,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL969,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x3 "PCTL968,Peripheral Control registers" bitfld.byte 0x3 6. "RES,Reserved" "0,1" newline bitfld.byte 0x3 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x3 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x4 "PCTL975,Peripheral Control registers" bitfld.byte 0x4 6. "RES,Reserved" "0,1" newline bitfld.byte 0x4 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x4 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x5 "PCTL974,Peripheral Control registers" bitfld.byte 0x5 6. "RES,Reserved" "0,1" newline bitfld.byte 0x5 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x5 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x6 "PCTL973,Peripheral Control registers" bitfld.byte 0x6 6. "RES,Reserved" "0,1" newline bitfld.byte 0x6 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x6 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x7 "PCTL972,Peripheral Control registers" bitfld.byte 0x7 6. "RES,Reserved" "0,1" newline bitfld.byte 0x7 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x7 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x7D3++0x0 line.byte 0x0 "PCTL976,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x7D8++0x3 line.byte 0x0 "PCTL987,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL986,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL985,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x3 "PCTL984,Peripheral Control registers" bitfld.byte 0x3 6. "RES,Reserved" "0,1" newline bitfld.byte 0x3 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x3 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x7EB++0x0 line.byte 0x0 "PCTL1000,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x7F2++0x0 line.byte 0x0 "PCTL1009,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x7FA++0x0 line.byte 0x0 "PCTL1017,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x842++0x0 line.byte 0x0 "PCTL1089,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x8D4++0x0 line.byte 0x0 "PCTL1239,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x8D6++0x3 line.byte 0x0 "PCTL1237,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL1236,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL1243,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x3 "PCTL1242,Peripheral Control registers" bitfld.byte 0x3 6. "RES,Reserved" "0,1" newline bitfld.byte 0x3 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x3 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x8DB++0x0 line.byte 0x0 "PCTL1240,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x8DF++0x0 line.byte 0x0 "PCTL1244,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x8E2++0x0 line.byte 0x0 "PCTL1249,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x8E4++0x0 line.byte 0x0 "PCTL1255,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x8E6++0x1 line.byte 0x0 "PCTL1253,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL1252,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x8ED++0x0 line.byte 0x0 "PCTL1262,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x8EF++0x0 line.byte 0x0 "PCTL1260,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x8F1++0x0 line.byte 0x0 "PCTL1266,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x8F7++0x2 line.byte 0x0 "PCTL1268,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL1275,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL1274,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x8FC++0x1 line.byte 0x0 "PCTL1279,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL1278,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x942++0x0 line.byte 0x0 "PCTL1345,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x970++0x1 line.byte 0x0 "PCTL1395,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL1394,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x9B9++0x0 line.byte 0x0 "PCTL1466,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x9D2++0x1 line.byte 0x0 "PCTL1489,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL1488,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x9F0++0x0 line.byte 0x0 "PCTL1523,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x9F3++0x0 line.byte 0x0 "PCTL1520,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" group.byte 0x9FB++0x4 line.byte 0x0 "PCTL1528,Peripheral Control registers" bitfld.byte 0x0 6. "RES,Reserved" "0,1" newline bitfld.byte 0x0 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x0 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x1 "PCTL1535,Peripheral Control registers" bitfld.byte 0x1 6. "RES,Reserved" "0,1" newline bitfld.byte 0x1 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x1 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x2 "PCTL1534,Peripheral Control registers" bitfld.byte 0x2 6. "RES,Reserved" "0,1" newline bitfld.byte 0x2 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x2 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x3 "PCTL1533,Peripheral Control registers" bitfld.byte 0x3 6. "RES,Reserved" "0,1" newline bitfld.byte 0x3 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x3 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" line.byte 0x4 "PCTL1532,Peripheral Control registers" bitfld.byte 0x4 6. "RES,Reserved" "0,1" newline bitfld.byte 0x4 3.--5. "LP_CFG,Peripheral configuration select for non-run modes" "0: Selects ME_LP_PC0 configuration,1: Selects ME_LP_PC1 configuration,2: Selects ME_LP_PC2 configuration,3: Selects ME_LP_PC3 configuration,4: Selects ME_LP_PC4 configuration,5: Selects ME_LP_PC5 configuration,6: Selects ME_LP_PC6 configuration,7: Selects ME_LP_PC7 configuration" newline bitfld.byte 0x4 0.--2. "RUN_CFG,Peripheral configuration select for run modes" "0: Selects ME_RUN_PC0 configuration,1: Selects ME_RUN_PC1 configuration,2: Selects ME_RUN_PC2 configuration,3: Selects ME_RUN_PC3 configuration,4: Selects ME_RUN_PC4 configuration,5: Selects ME_RUN_PC5 configuration,6: Selects ME_RUN_PC6 configuration,7: Selects ME_RUN_PC7 configuration" tree.end tree.end tree "MC_PCU (Power Control Unit)" base ad:0x0 tree "MC_PCU_PERIPHERAL_DOMAIN" base ad:0x722B0000 rgroup.long 0x0++0x7 line.long 0x0 "PCONF0,Power domain #0 configuration register" bitfld.long 0x0 13. "STBY0,Power domain control during STANDBY mode" "0: Power domain off,1: Power domain on" bitfld.long 0x0 10. "STOP,Power domain control during STOP mode" "0: Power domain off,1: Power domain on" bitfld.long 0x0 8. "HALT,Power domain control during HALT mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0x0 7. "RUN3,Power domain control during RUN3 mode" "0: Power domain off,1: Power domain on" bitfld.long 0x0 6. "RUN2,Power domain control during RUN2 mode" "0: Power domain off,1: Power domain on" bitfld.long 0x0 5. "RUN1,Power domain control during RUN1 mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0x0 4. "RUN0,Power domain control during RUN0 mode" "0: Power domain off,1: Power domain on" bitfld.long 0x0 3. "DRUN,Power domain control during DRUN mode" "0: Power domain off,1: Power domain on" bitfld.long 0x0 2. "SAFE,Power domain control during SAFE mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0x0 1. "TEST,Power domain control during TEST mode" "0: Power domain off,1: Power domain on" bitfld.long 0x0 0. "RST,Power domain control during RESET mode" "0: Power domain off,1: Power domain on" line.long 0x4 "PCONF1,Power domain #1 configuration register" bitfld.long 0x4 13. "STBY0,Power domain control during STANDBY mode" "0: Power domain off,1: Power domain on" bitfld.long 0x4 10. "STOP,Power domain control during STOP mode" "0: Power domain off,1: Power domain on" bitfld.long 0x4 8. "HALT,Power domain control during HALT mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0x4 7. "RUN3,Power domain control during RUN3 mode" "0: Power domain off,1: Power domain on" bitfld.long 0x4 6. "RUN2,Power domain control during RUN2 mode" "0: Power domain off,1: Power domain on" bitfld.long 0x4 5. "RUN1,Power domain control during RUN1 mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0x4 4. "RUN0,Power domain control during RUN0 mode" "0: Power domain off,1: Power domain on" bitfld.long 0x4 3. "DRUN,Power domain control during DRUN mode" "0: Power domain off,1: Power domain on" bitfld.long 0x4 2. "SAFE,Power domain control during SAFE mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0x4 1. "TEST,Power domain control during TEST mode" "0: Power domain off,1: Power domain on" bitfld.long 0x4 0. "RST,Power domain control during RESET mode" "0: Power domain off,1: Power domain on" group.long 0x8++0x17 line.long 0x0 "PCONF2,Power domain #2 configuration register" bitfld.long 0x0 13. "STBY0,Power domain control during STANDBY mode" "0: Power domain off,1: Power domain on" bitfld.long 0x0 10. "STOP,Power domain control during STOP mode" "0: Power domain off,1: Power domain on" bitfld.long 0x0 8. "HALT,Power domain control during HALT mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0x0 7. "RUN3,Power domain control during RUN3 mode" "0: Power domain off,1: Power domain on" bitfld.long 0x0 6. "RUN2,Power domain control during RUN2 mode" "0: Power domain off,1: Power domain on" bitfld.long 0x0 5. "RUN1,Power domain control during RUN1 mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0x0 4. "RUN0,Power domain control during RUN0 mode" "0: Power domain off,1: Power domain on" bitfld.long 0x0 3. "DRUN,Power domain control during DRUN mode" "0: Power domain off,1: Power domain on" bitfld.long 0x0 2. "SAFE,Power domain control during SAFE mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0x0 1. "TEST,Power domain control during TEST mode" "0: Power domain off,1: Power domain on" bitfld.long 0x0 0. "RST,Power domain control during RESET mode" "0: Power domain off,1: Power domain on" line.long 0x4 "PCONF3,Power domain #3 configuration register" bitfld.long 0x4 13. "STBY0,Power domain control during STANDBY mode" "0: Power domain off,1: Power domain on" bitfld.long 0x4 10. "STOP,Power domain control during STOP mode" "0: Power domain off,1: Power domain on" bitfld.long 0x4 8. "HALT,Power domain control during HALT mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0x4 7. "RUN3,Power domain control during RUN3 mode" "0: Power domain off,1: Power domain on" bitfld.long 0x4 6. "RUN2,Power domain control during RUN2 mode" "0: Power domain off,1: Power domain on" bitfld.long 0x4 5. "RUN1,Power domain control during RUN1 mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0x4 4. "RUN0,Power domain control during RUN0 mode" "0: Power domain off,1: Power domain on" bitfld.long 0x4 3. "DRUN,Power domain control during DRUN mode" "0: Power domain off,1: Power domain on" bitfld.long 0x4 2. "SAFE,Power domain control during SAFE mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0x4 1. "TEST,Power domain control during TEST mode" "0: Power domain off,1: Power domain on" bitfld.long 0x4 0. "RST,Power domain control during RESET mode" "0: Power domain off,1: Power domain on" line.long 0x8 "PCONF4,Power domain #4 configuration register" bitfld.long 0x8 13. "STBY0,Power domain control during STANDBY mode" "0: Power domain off,1: Power domain on" bitfld.long 0x8 10. "STOP,Power domain control during STOP mode" "0: Power domain off,1: Power domain on" bitfld.long 0x8 8. "HALT,Power domain control during HALT mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0x8 7. "RUN3,Power domain control during RUN3 mode" "0: Power domain off,1: Power domain on" bitfld.long 0x8 6. "RUN2,Power domain control during RUN2 mode" "0: Power domain off,1: Power domain on" bitfld.long 0x8 5. "RUN1,Power domain control during RUN1 mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0x8 4. "RUN0,Power domain control during RUN0 mode" "0: Power domain off,1: Power domain on" bitfld.long 0x8 3. "DRUN,Power domain control during DRUN mode" "0: Power domain off,1: Power domain on" bitfld.long 0x8 2. "SAFE,Power domain control during SAFE mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0x8 1. "TEST,Power domain control during TEST mode" "0: Power domain off,1: Power domain on" bitfld.long 0x8 0. "RST,Power domain control during RESET mode" "0: Power domain off,1: Power domain on" line.long 0xC "PCONF5,Power domain #5 configuration register" bitfld.long 0xC 13. "STBY0,Power domain control during STANDBY mode" "0: Power domain off,1: Power domain on" bitfld.long 0xC 10. "STOP,Power domain control during STOP mode" "0: Power domain off,1: Power domain on" bitfld.long 0xC 8. "HALT,Power domain control during HALT mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0xC 7. "RUN3,Power domain control during RUN3 mode" "0: Power domain off,1: Power domain on" bitfld.long 0xC 6. "RUN2,Power domain control during RUN2 mode" "0: Power domain off,1: Power domain on" bitfld.long 0xC 5. "RUN1,Power domain control during RUN1 mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0xC 4. "RUN0,Power domain control during RUN0 mode" "0: Power domain off,1: Power domain on" bitfld.long 0xC 3. "DRUN,Power domain control during DRUN mode" "0: Power domain off,1: Power domain on" bitfld.long 0xC 2. "SAFE,Power domain control during SAFE mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0xC 1. "TEST,Power domain control during TEST mode" "0: Power domain off,1: Power domain on" bitfld.long 0xC 0. "RST,Power domain control during RESET mode" "0: Power domain off,1: Power domain on" line.long 0x10 "PCONF6,Power domain #6 configuration register" bitfld.long 0x10 13. "STBY0,Power domain control during STANDBY mode" "0: Power domain off,1: Power domain on" bitfld.long 0x10 10. "STOP,Power domain control during STOP mode" "0: Power domain off,1: Power domain on" bitfld.long 0x10 8. "HALT,Power domain control during HALT mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0x10 7. "RUN3,Power domain control during RUN3 mode" "0: Power domain off,1: Power domain on" bitfld.long 0x10 6. "RUN2,Power domain control during RUN2 mode" "0: Power domain off,1: Power domain on" bitfld.long 0x10 5. "RUN1,Power domain control during RUN1 mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0x10 4. "RUN0,Power domain control during RUN0 mode" "0: Power domain off,1: Power domain on" bitfld.long 0x10 3. "DRUN,Power domain control during DRUN mode" "0: Power domain off,1: Power domain on" bitfld.long 0x10 2. "SAFE,Power domain control during SAFE mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0x10 1. "TEST,Power domain control during TEST mode" "0: Power domain off,1: Power domain on" bitfld.long 0x10 0. "RST,Power domain control during RESET mode" "0: Power domain off,1: Power domain on" line.long 0x14 "PCONF7,Power domain #7 configuration register" bitfld.long 0x14 13. "STBY0,Power domain control during STANDBY mode" "0: Power domain off,1: Power domain on" bitfld.long 0x14 10. "STOP,Power domain control during STOP mode" "0: Power domain off,1: Power domain on" bitfld.long 0x14 8. "HALT,Power domain control during HALT mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0x14 7. "RUN3,Power domain control during RUN3 mode" "0: Power domain off,1: Power domain on" bitfld.long 0x14 6. "RUN2,Power domain control during RUN2 mode" "0: Power domain off,1: Power domain on" bitfld.long 0x14 5. "RUN1,Power domain control during RUN1 mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0x14 4. "RUN0,Power domain control during RUN0 mode" "0: Power domain off,1: Power domain on" bitfld.long 0x14 3. "DRUN,Power domain control during DRUN mode" "0: Power domain off,1: Power domain on" bitfld.long 0x14 2. "SAFE,Power domain control during SAFE mode" "0: Power domain off,1: Power domain on" newline bitfld.long 0x14 1. "TEST,Power domain control during TEST mode" "0: Power domain off,1: Power domain on" bitfld.long 0x14 0. "RST,Power domain control during RESET mode" "0: Power domain off,1: Power domain on" rgroup.long 0x40++0x3 line.long 0x0 "PSTAT,Power domain status register" bitfld.long 0x0 7. "PD7,Power status for power domain #7" "0: Power domain is inoperable.,1: Power domain is operable." bitfld.long 0x0 6. "PD6,Power status for power domain #6" "0: Power domain is inoperable.,1: Power domain is operable." bitfld.long 0x0 5. "PD5,Power status for power domain #5" "0: Power domain is inoperable.,1: Power domain is operable." newline bitfld.long 0x0 4. "PD4,Power status for power domain #4" "0: Power domain is inoperable.,1: Power domain is operable." bitfld.long 0x0 3. "PD3,Power status for power domain #3" "0: Power domain is inoperable.,1: Power domain is operable." bitfld.long 0x0 2. "PD2,Power status for power domain #2" "0: Power domain is inoperable.,1: Power domain is operable." newline bitfld.long 0x0 1. "PD1,Power status for power domain #1" "0: Power domain is inoperable.,1: Power domain is operable." bitfld.long 0x0 0. "PD0,Power status for power domain #0" "0: Power domain is inoperable.,1: Power domain is operable." tree.end tree.end tree "MC_RGM (Reset Generation Module)" base ad:0x0 tree "MC_RGM_DOMAIN_0" base ad:0x710DC000 group.long 0x0++0x3 line.long 0x0 "DES,xd4 Destructive' Event Status Register" bitfld.long 0x0 3. "F_SOFT_DEST,Flag for software 'destructive' reset from MC_ME_0/1/2" "0: No software 'destructive' reset event has..,1: A software 'destructive' reset event has occurred" bitfld.long 0x0 1. "F_RGM,Flag for 'destructive' reset from MC_RGM_PER" "0: No 'destructive' reset event has occurred since..,1: A 'destructive' reset event has occurred" newline bitfld.long 0x0 0. "F_POR,Flag for Power-On reset" "0: No power-on event has occurred since the last..,1: A power-on event has occurred" group.long 0x300++0x3 line.long 0x0 "FES,xd4 Functional' Event Status Register" bitfld.long 0x0 3. "F_SOFT_FUNC,Flag for software 'functional' reset from MC_ME_0/1/2" "0: No software 'functional' reset event has..,1: A software 'functional' reset event has occurred" bitfld.long 0x0 1. "F_RGM,Flag for software 'functional' reset from RGM_PER" "0: No software 'functional' reset event has..,1: A software 'functional' reset event has occurred" group.long 0x340++0x3 line.long 0x0 "FESS,xd4 Functional' Event Short Sequence Register" bitfld.long 0x0 3. "SS_SOFT_FUNC,Short Sequence for software 'functional' reset from MC_ME_0/1/2" "0: The reset sequence triggered by a software..,1: The reset sequence triggered by a software.." tree.end tree "MC_RGM_DOMAIN_1" base ad:0x716DC000 group.long 0x0++0x3 line.long 0x0 "DES,xd4 Destructive' Event Status Register" bitfld.long 0x0 3. "F_SOFT_DEST,Flag for software 'destructive' reset from MC_ME_0/1/2" "0: No software 'destructive' reset event has..,1: A software 'destructive' reset event has occurred" bitfld.long 0x0 1. "F_RGM,Flag for 'destructive' reset from MC_RGM_PER" "0: No 'destructive' reset event has occurred since..,1: A 'destructive' reset event has occurred" newline bitfld.long 0x0 0. "F_POR,Flag for Power-On reset" "0: No power-on event has occurred since the last..,1: A power-on event has occurred" group.long 0x300++0x3 line.long 0x0 "FES,xd4 Functional' Event Status Register" bitfld.long 0x0 3. "F_SOFT_FUNC,Flag for software 'functional' reset from MC_ME_0/1/2" "0: No software 'functional' reset event has..,1: A software 'functional' reset event has occurred" bitfld.long 0x0 1. "F_RGM,Flag for software 'functional' reset from RGM_PER" "0: No software 'functional' reset event has..,1: A software 'functional' reset event has occurred" group.long 0x340++0x3 line.long 0x0 "FESS,xd4 Functional' Event Short Sequence Register" bitfld.long 0x0 3. "SS_SOFT_FUNC,Short Sequence for software 'functional' reset from MC_ME_0/1/2" "0: The reset sequence triggered by a software..,1: The reset sequence triggered by a software.." tree.end tree "MC_RGM_DOMAIN_2" base ad:0x710E0000 group.long 0x0++0x3 line.long 0x0 "DES,xd4 Destructive' Event Status Register" bitfld.long 0x0 3. "F_SOFT_DEST,Flag for software 'destructive' reset from MC_ME_0/1/2" "0: No software 'destructive' reset event has..,1: A software 'destructive' reset event has occurred" bitfld.long 0x0 1. "F_RGM,Flag for 'destructive' reset from MC_RGM_PER" "0: No 'destructive' reset event has occurred since..,1: A 'destructive' reset event has occurred" newline bitfld.long 0x0 0. "F_POR,Flag for Power-On reset" "0: No power-on event has occurred since the last..,1: A power-on event has occurred" group.long 0x300++0x3 line.long 0x0 "FES,xd4 Functional' Event Status Register" bitfld.long 0x0 3. "F_SOFT_FUNC,Flag for software 'functional' reset from MC_ME_0/1/2" "0: No software 'functional' reset event has..,1: A software 'functional' reset event has occurred" bitfld.long 0x0 1. "F_RGM,Flag for software 'functional' reset from RGM_PER" "0: No software 'functional' reset event has..,1: A software 'functional' reset event has occurred" group.long 0x340++0x3 line.long 0x0 "FESS,xd4 Functional' Event Short Sequence Register" bitfld.long 0x0 3. "SS_SOFT_FUNC,Short Sequence for software 'functional' reset from MC_ME_0/1/2" "0: The reset sequence triggered by a software..,1: The reset sequence triggered by a software.." tree.end tree "MC_RGM_PERIPHERAL_DOMAIN" base ad:0x722F0000 group.long 0x0++0x3 line.long 0x0 "DES,Destructive event status register" bitfld.long 0x0 29. "F_VD_HSM_DEST,Flag for voltage detector destructive reset for domain HSM" "0: No voltage detector destructive reset event has..,1: A voltage detector destructive reset event has.." newline bitfld.long 0x0 27. "F_VD_D2_DEST,Flag for voltage detector destructive reset for domain 2" "0: No voltage detector destructive reset event has..,1: A voltage detector destructive reset event has.." newline bitfld.long 0x0 26. "F_VD_D1_DEST,Flag for voltage detector destructive reset for domain 1" "0: No voltage detector destructive reset event has..,1: A voltage detector destructive reset event has.." newline bitfld.long 0x0 25. "F_VD_D0_DEST,Flag for voltage detector destructive reset for domain 0" "0: No voltage detector destructive reset event has..,1: A voltage detector destructive reset event has.." newline bitfld.long 0x0 24. "F_VD_DP_DEST,Flag for voltage detector destructive reset for peripheral domain" "0: No voltage detector destructive reset event has..,1: A voltage detector destructive reset event has.." newline bitfld.long 0x0 16. "F_TSR_DEST,Flag for temperature sensor destructive reset" "0: No temperature sensor destructive reset event..,1: A temperature sensor destructive reset event has.." newline bitfld.long 0x0 15. "F_HSM_DEST,Flag for HSM destructive reset request" "0: No HSM destructive reset request event has..,1: A HSM destructive reset request event has occurred" newline bitfld.long 0x0 14. "F_SSCM_DEST,Flag for SSCM destructive reset request" "0: No SSCM destructive reset request event has..,1: A SSCM destructive reset request event has.." newline bitfld.long 0x0 10. "F_JTAG_DEST,Flag for JTAG destructive reset request" "0: No JTAG destructive reset request event has..,1: A JTAG destructive reset request event has.." newline bitfld.long 0x0 9. "F_FIF,Flag for NVM memory initialization failure" "0: No NVM memory initialization failure event has..,1: A NVM memory initialization failure event has.." newline bitfld.long 0x0 8. "F_EDR,Flag for functional reset escalation" "0: No functional reset escalation event has..,1: A functional reset escalation event has occurred" newline bitfld.long 0x0 5. "F_SUF,Flag for STCU unrecoverable fault" "0: No STCU unrecoverable fault event has occurred..,1: A STCU unrecoverable fault event has occurred" newline bitfld.long 0x0 4. "F_FFRR,Flag for FCCU failure to react reset" "0: No FCCU failure to react reset event has..,1: A FCCU failure to react reset event has occurred" newline bitfld.long 0x0 3. "F_SOFT_DEST,Flag for software destructive reset from MC_ME_PER" "0: No software destructive reset event has occurred..,1: A software destructive reset event has occurred" newline bitfld.long 0x0 2. "F_RESET_B,Flag for reset B" "0: No reset B has occurred since the last time this..,1: Reset B event has occurred" newline bitfld.long 0x0 1. "F_RESET_A,Flag for reset A" "0: No reset A has occurred since the last time this..,1: Reset A event has occurred" newline bitfld.long 0x0 0. "F_POR,Flag for power-on reset" "0: No power-on event has occurred since the last..,1: A power-on event has occurred" group.long 0x10++0x3 line.long 0x0 "DERD,Destructive event reset disable register" bitfld.long 0x0 29. "D_VD_HSM_DEST,Disable voltage detector destructive reset for domain HSM" "0: A voltage detector destructive reset event..,?" newline bitfld.long 0x0 27. "D_VD_D2_DEST,Disable voltage detector destructive reset for domain 2" "0: A voltage detector destructive reset event..,?" newline bitfld.long 0x0 26. "D_VD_D1_DEST,Disable voltage detector destructive reset for domain 1" "0: A voltage detector destructive reset event..,?" newline bitfld.long 0x0 25. "D_VD_D0_DEST,Disable voltage detector destructive reset for domain 0" "0: A voltage detector destructive reset event..,?" newline bitfld.long 0x0 24. "D_VD_DP_DEST,Disable voltage detector destructive reset for peripheral domain" "0: A voltage detector destructive reset event..,?" newline bitfld.long 0x0 16. "D_TSR_DEST,Disable temperature sensor destructive reset" "0: A temperature sensor destructive reset event..,1: A temperature sensor destructive reset event.." newline bitfld.long 0x0 15. "D_HSM_DEST,Disable HSM destructive reset request" "0: A HSM destructive reset request event triggers a..,?" newline bitfld.long 0x0 14. "D_SSCM_DEST,Disable SSCM destructive reset request" "0: A SSCM destructive reset request event triggers..,?" newline bitfld.long 0x0 10. "D_JTAG_DEST,Disable JTAG destructive reset request" "0: A JTAG destructive reset request event triggers..,?" newline bitfld.long 0x0 9. "D_FIF,Disable NVM memory initialization failure" "0: A NVM memory initialization failure event..,?" newline bitfld.long 0x0 8. "D_EDR,Disable functional reset escalation" "0: A functional reset escalation event triggers a..,?" newline bitfld.long 0x0 5. "D_SUF,Disable STCU unrecoverable fault" "0: A STCU unrecoverable fault event triggers a..,?" newline bitfld.long 0x0 4. "D_FFRR,Disable FCCU failure to react reset" "0: A FCCU failure to react reset event triggers a..,?" newline bitfld.long 0x0 3. "D_SOFT_DEST,Disable software destructive reset from MC_ME_PER" "0: A software destructive reset triggers a reset..,?" newline bitfld.long 0x0 2. "D_RESET_B,Disable reset B" "0: A reset B event triggers a reset sequence,1: A reset B event generates either a SAFE mode or.." newline bitfld.long 0x0 1. "D_RESET_A,Disable reset A" "0: A reset A event triggers a reset sequence,1: A reset A event generates either a SAFE mode or.." newline bitfld.long 0x0 0. "D_POR,Disable Power-On reset" "0: A power-on event triggers a reset sequence,?" group.long 0x20++0x3 line.long 0x0 "DEAR,Destructive event alternate request register" bitfld.long 0x0 16. "AR_TSR_DEST,Alternate request for temperature sensor" "0: Generate a SAFE mode request on a temperature..,1: Generate an interrupt request on a temperature.." newline bitfld.long 0x0 2. "AR_RESET_B,Alternate request for reset B" "0: Generate a SAFE mode request on a reset B event..,1: Generate an interrupt request on a reset B event.." newline bitfld.long 0x0 1. "AR_RESET_A,Alternate request for reset A" "0: Generate a SAFE mode request on a reset A event..,1: Generate an interrupt request on a reset A event.." group.long 0x30++0x3 line.long 0x0 "DBRE,Destructive bidirectional reset enable register" bitfld.long 0x0 29. "BE_VD_HSM_DEST,Bidirectional reset enable for voltage detector destructive reset for domain HSM" "0: reset A is asserted on a voltage detector..,?" newline bitfld.long 0x0 27. "BE_VD_D2_DEST,Bidirectional reset enable for voltage detector destructive reset for domain 2" "0: reset A is asserted on a voltage detector..,?" newline bitfld.long 0x0 26. "BE_VD_D1_DEST,Bidirectional reset enable for voltage detector destructive reset for domain 1" "0: reset A is asserted on a voltage detector..,?" newline bitfld.long 0x0 25. "BE_VD_D0_DEST,Bidirectional reset enable for voltage detector destructive reset for domain 0" "0: reset A is asserted on a voltage detector..,?" newline bitfld.long 0x0 24. "BE_VD_DP_DEST,Bidirectional reset enable for voltage detector destructive reset for peripheral domain" "0: reset A is asserted on a voltage detector..,?" newline bitfld.long 0x0 16. "BE_TSR_DEST,Bidirectional reset enable for temperature sensor destructive reset" "0: reset A is asserted on a temperature sensor..,?" newline bitfld.long 0x0 15. "BE_HSM_DEST,Bidirectional reset enable for HSM destructive reset request" "0: reset A is asserted on a HSM destructive reset..,?" newline bitfld.long 0x0 14. "BE_SSCM_DEST,Bidirectional reset enable for SSCM destructive reset request" "0: reset A is asserted on a SSCM destructive reset..,?" newline bitfld.long 0x0 10. "BE_JTAG_DEST,Bidirectional reset enable for JTAG destructive reset request" "0: reset A is asserted on a JTAG destructive reset..,1: reset A is not asserted on a JTAG destructive.." newline bitfld.long 0x0 9. "BE_FIF,Bidirectional reset enable for NVM memory initialization failure" "0: reset A is asserted on a NVM memory..,?" newline bitfld.long 0x0 8. "BE_EDR,Bidirectional reset enable for functional reset escalation" "0: reset A is asserted on a functional reset..,?" newline bitfld.long 0x0 5. "BE_SUF,Bidirectional reset enable for STCU unrecoverable fault" "0: reset A is asserted on a STCU unrecoverable..,?" newline bitfld.long 0x0 4. "BE_FFRR,Bidirectional reset enable for FCCU failure to react reset" "0: reset A is asserted on a FCCU failure to react..,?" newline bitfld.long 0x0 3. "BE_SOFT_DEST,Bidirectional reset enable for software destructive reset from MC_ME_PER" "0: reset A is asserted on a software destructive..,?" newline bitfld.long 0x0 2. "BE_RESET_B,Bidirectional reset enable for reset B" "0: reset A is asserted on a reset B event if the..,?" newline bitfld.long 0x0 1. "BE_RESET_A,Bidirectional reset enable for reset A" "0: reset A is asserted on a reset A event if the..,?" newline bitfld.long 0x0 0. "BE_POR,Bidirectional reset enable for power-on reset" "0: reset A is asserted on a power-on reset event,?" group.long 0x300++0x3 line.long 0x0 "FES,Functional event status register" bitfld.long 0x0 29. "F_VD_HSM_FUNC,Flag for voltage detector functional reset for domain HSM" "0: No voltage detector functional reset event has..,1: A voltage detector functional reset event has.." newline bitfld.long 0x0 27. "F_VD_D2_FUNC,Flag for voltage detector functional reset for domain 2" "0: No voltage detector functional reset event has..,1: A voltage detector functional reset event has.." newline bitfld.long 0x0 26. "F_VD_D1_FUNC,Flag for voltage detector functional reset for domain 1" "0: No voltage detector functional reset event has..,1: A voltage detector functional reset event has.." newline bitfld.long 0x0 25. "F_VD_D0_FUNC,Flag for voltage detector functional reset for domain 0" "0: No voltage detector functional reset event has..,1: A voltage detector functional reset event has.." newline bitfld.long 0x0 24. "F_VD_DP_FUNC,Flag for voltage detector functional reset for peripheral domain" "0: No voltage detector functional reset event has..,1: A voltage detector functional reset event has.." newline bitfld.long 0x0 16. "F_TSR_FUNC,Flag for temperature sensor functional reset" "0: No temperature sensor functional reset event has..,1: A temperature sensor functional reset event has.." newline bitfld.long 0x0 15. "F_HSM_FUNC,Flag for HSM functional reset request" "0: No HSM functional reset request event has..,1: A HSM functional reset request event has occurred" newline bitfld.long 0x0 10. "F_JTAG_FUNC,Flag for JTAG functional reset" "0: No JTAG functional reset event has occurred..,1: A JTAG functional reset event has occurred or.." newline bitfld.long 0x0 6. "F_FCCU_SOFT,Flag for FCCU soft reaction (short functional reset request)" "0: No FCCU soft reaction event has occurred since..,1: A FCCU soft reaction event has occurred" newline bitfld.long 0x0 5. "F_FCCU_HARD,Flag for FCCU hard reaction reset (long functional reset request)" "0: No FCCU hard reaction reset event has occurred..,1: A FCCU hard reaction reset event has occurred" newline bitfld.long 0x0 3. "F_SOFT_FUNC,Flag for software functional reset from MC_ME_PER" "0: No software functional reset event has occurred..,1: A software functional reset event has occurred.." newline bitfld.long 0x0 2. "F_ST_DONE,Flag for self test completed" "0: No self test completed event has occurred since..,1: A self test completed event has occurred or.." newline bitfld.long 0x0 0. "F_RESET_B,Flag for reset B" "0: No reset B event has occurred since either the..,1: A reset B event has occurred or destructive.." group.long 0x310++0x3 line.long 0x0 "FERD,Functional event reset disable register" bitfld.long 0x0 29. "D_VD_HSM_FUNC,Disable voltage detector functional reset for domain HSM" "0: A voltage detector functional reset event..,1: A voltage detector functional reset event.." newline bitfld.long 0x0 27. "D_VD_D2_FUNC,Disable voltage detector functional reset for domain 2" "0: A voltage detector functional reset event..,1: A voltage detector functional reset event.." newline bitfld.long 0x0 26. "D_VD_D1_FUNC,Disable voltage detector functional reset for domain 1" "0: A voltage detector functional reset event..,1: A voltage detector functional reset event.." newline bitfld.long 0x0 25. "D_VD_D0_FUNC,Disable voltage detector functional reset for domain 0" "0: A voltage detector functional reset event..,1: A voltage detector functional reset event.." newline bitfld.long 0x0 24. "D_VD_DP_FUNC,Disable voltage detector functional reset for peripheral domain" "0: A voltage detector functional reset event..,1: A voltage detector functional reset event.." newline bitfld.long 0x0 16. "D_TSR_FUNC,Disable temperature sensor functional reset" "0: A temperature sensor functional reset event..,1: A temperature sensor functional reset event.." newline bitfld.long 0x0 15. "D_HSM_FUNC,Disable HSM functional reset request" "0: A HSM functional reset request event triggers a..,?" newline bitfld.long 0x0 10. "D_JTAG_FUNC,Disable JTAG functional reset" "0: A JTAG functional reset event triggers a reset..,?" newline bitfld.long 0x0 6. "D_FCCU_SOFT,Disable FCCU soft reaction (short functional reset request)" "0: A FCCU soft reaction event triggers a reset..,?" newline bitfld.long 0x0 5. "D_FCCU_HARD,Disable FCCU hard reaction reset (long functional reset request)" "0: A FCCU hard reaction reset event triggers a..,?" newline bitfld.long 0x0 3. "D_SOFT_FUNC,Disable software functional reset from MC_ME_PER" "0: A software functional reset event triggers a..,?" newline bitfld.long 0x0 2. "D_ST_DONE,Disable self test completed" "0: A self test completed event triggers a reset..,?" newline bitfld.long 0x0 0. "D_RESET_B,Disable reset B" "0: A reset B event triggers a reset sequence,?" group.long 0x320++0x3 line.long 0x0 "FEAR,Functional event alternate request register" bitfld.long 0x0 29. "AR_VD_HSM_FUNC,Alternate request for voltage detector functional reset for domain HSM" "0: Generate a SAFE mode request on a voltage..,1: Generate an interrupt request on a voltage.." newline bitfld.long 0x0 27. "AR_VD_D2_FUNC,Alternate request for voltage detector functional reset for domain 2" "0: Generate a SAFE mode request on a voltage..,1: Generate an interrupt request on a voltage.." newline bitfld.long 0x0 26. "AR_VD_D1_FUNC,Alternate request for voltage detector functional reset for domain 1" "0: Generate a SAFE mode request on a voltage..,1: Generate an interrupt request on a voltage.." newline bitfld.long 0x0 25. "AR_VD_D0_FUNC,Alternate request for voltage detector functional reset for domain 0" "0: Generate a SAFE mode request on a voltage..,1: Generate an interrupt request on a voltage.." newline bitfld.long 0x0 24. "AR_VD_DP_FUNC,Alternate request for voltage detector functional reset for peripheral domain" "0: Generate a SAFE mode request on a voltage..,1: Generate an interrupt request on a voltage.." newline bitfld.long 0x0 16. "AR_TSR_FUNC,Alternate request for temperature sensor functional reset" "0: Generate a SAFE mode request on a temperature..,1: Generate an interrupt request on a temperature.." group.long 0x330++0x3 line.long 0x0 "FBRE,Functional bidirectional reset enable register" bitfld.long 0x0 29. "BE_VD_HSM_FUNC,Bidirectional reset enable for voltage detector functional reset for domain HSM" "0: reset A is asserted on a voltage detector..,1: reset A is not asserted on a voltage detector.." newline bitfld.long 0x0 27. "BE_VD_D2_FUNC,Bidirectional reset enable for voltage detector functional reset for domain 2" "0: reset A is asserted on a voltage detector..,1: reset A is not asserted on a voltage detector.." newline bitfld.long 0x0 26. "BE_VD_D1_FUNC,Bidirectional reset enable for voltage detector functional reset for domain 1" "0: reset A is asserted on a voltage detector..,1: reset A is not asserted on a voltage detector.." newline bitfld.long 0x0 25. "BE_VD_D0_FUNC,Bidirectional reset enable for voltage detector functional reset for domain 0" "0: reset A is asserted on a voltage detector..,1: reset A is not asserted on a voltage detector.." newline bitfld.long 0x0 24. "BE_VD_DP_FUNC,Bidirectional reset enable for voltage detector functional reset for peripheral domain" "0: reset A is asserted on a voltage detector..,1: reset A is not asserted on a voltage detector.." newline bitfld.long 0x0 16. "BE_TSR_FUNC,Bidirectional reset enable for temperature sensor functional reset" "0: reset A is asserted on a temperature sensor..,1: reset A is not asserted on a temperature sensor.." newline bitfld.long 0x0 15. "BE_HSM_FUNC,Bidirectional reset enable for HSM functional reset request" "0: reset A is asserted on a HSM functional reset..,1: reset A is not asserted on a HSM functional.." newline bitfld.long 0x0 10. "BE_JTAG_FUNC,Bidirectional reset enable for JTAG functional reset" "0: reset A is asserted on a JTAG functional reset..,1: reset A is not asserted on a JTAG functional.." newline bitfld.long 0x0 6. "BE_FCCU_SOFT,Bidirectional reset enable for FCCU soft reaction (short functional reset request)" "0: reset A is asserted on a FCCU soft reaction event,1: reset A is not asserted on a FCCU soft reaction.." newline bitfld.long 0x0 5. "BE_FCCU_HARD,Bidirectional reset enable for a FCCU hard reaction (long functional reset request)" "0: reset A is asserted on a FCCU hard reaction..,1: reset A is not asserted on a FCCU hard reaction.." newline bitfld.long 0x0 3. "BE_SOFT_FUNC,Bidirectional reset enable for software functional reset from MC_ME_PER" "0: reset A is asserted on a software functional..,1: reset A is not asserted on a software functional.." newline bitfld.long 0x0 2. "BE_ST_DONE,Bidirectional reset enable for self test completed" "0: reset A is asserted on a self test completed event,?" newline bitfld.long 0x0 0. "BE_RESET_B,Bidirectional reset enable for reset B" "0: reset A is asserted on a reset B event if the..,1: reset A is not asserted on a reset B event" group.long 0x340++0x3 line.long 0x0 "FESS,Functional event short sequence register" bitfld.long 0x0 29. "SS_VD_HSM_FUNC,Short sequence for voltage detector functional reset for domain HSM" "0: The reset sequence triggered by a voltage..,1: The reset sequence triggered by a voltage.." newline bitfld.long 0x0 27. "SS_VD_D2_FUNC,Short sequence for voltage detector functional reset for domain 2" "0: The reset sequence triggered by a voltage..,1: The reset sequence triggered by a voltage.." newline bitfld.long 0x0 26. "SS_VD_D1_FUNC,Short sequence for voltage detector functional reset for domain 1" "0: The reset sequence triggered by a voltage..,1: The reset sequence triggered by a voltage.." newline bitfld.long 0x0 25. "SS_VD_D0_FUNC,Short sequence for voltage detector functional reset for domain 0" "0: The reset sequence triggered by a voltage..,1: The reset sequence triggered by a voltage.." newline bitfld.long 0x0 24. "SS_VD_DP_FUNC,Short sequence for voltage detector functional reset for peripheral domain" "0: The reset sequence triggered by a voltage..,1: The reset sequence triggered by a voltage.." newline bitfld.long 0x0 16. "SS_TSR_FUNC,Short sequence for temperature sensor functional reset" "0: The reset sequence triggered by a temperature..,1: The reset sequence triggered by a temperature.." newline bitfld.long 0x0 15. "SS_HSM_FUNC,Short sequence for HSM functional reset request" "?,1: The reset sequence triggered by a HSM functional.." newline bitfld.long 0x0 10. "SS_JTAG_FUNC,Short sequence for JTAG functional reset" "0: The reset sequence triggered by a JTAG..,1: The reset sequence triggered by a JTAG.." newline bitfld.long 0x0 6. "SS_FCCU_SOFT,Short sequence for FCCU soft reaction (short functional reset request)" "?,1: The reset sequence triggered by a FCCU soft.." newline bitfld.long 0x0 5. "SS_FCCU_HARD,Short sequence for a FCCU hard reaction (long functional reset request)" "0: The reset sequence triggered by a FCCU hard..,?" newline bitfld.long 0x0 3. "SS_SOFT_FUNC,Short sequence for software functional reset from MC_ME_PER" "0: The reset sequence triggered by a software..,1: The reset sequence triggered by a software.." newline bitfld.long 0x0 2. "SS_ST_DONE,Short sequence for self test completed" "0: The reset sequence triggered by a self test..,?" newline bitfld.long 0x0 0. "SS_RESET_B,Short sequence for reset B" "0: The reset sequence triggered by a reset B event..,1: The reset sequence triggered by a reset B event.." group.byte 0x607++0x0 line.byte 0x0 "FRET,Functional reset escalation threshold register" hexmask.byte 0x0 0.--3. 1. "FRESET,Functional reset escalation threshold" group.byte 0x60B++0x0 line.byte 0x0 "DRET,Destructive reset escalation threshold register" hexmask.byte 0x0 0.--3. 1. "DRESET,Destructive reset escalation threshold" group.byte 0x60F++0x0 line.byte 0x0 "EROEC,External reset output extension control register" bitfld.byte 0x0 1. "ERIS,External reset input status" "0: A '0' is being observed on reset B if configured..,1: A '1' is being observed on reset Bif configured.." newline bitfld.byte 0x0 0. "EROAC,External reset output assertion control" "0: reset A is not being asserted by the MC_RGM,1: reset A is being asserted by the MC_RGM" group.long 0x610++0x1F line.long 0x0 "PRST0_M0,Peripheral reset register 0 for MODS 0" bitfld.long 0x0 2. "CLUSTER_2_RST,CLUSTER_2 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x0 1. "CLUSTER_1_RST,CLUSTER_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x0 0. "CLUSTER_0_RST,CLUSTER_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" line.long 0x4 "PRST1_M0,Peripheral reset register 1 for MODS 0" bitfld.long 0x4 31. "GTM_0_RST,GTM_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" line.long 0x8 "PRST2_M0,Peripheral reset register 2 for MODS 0" bitfld.long 0x8 24. "LFAST_0_RST,LFAST_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 20. "SIPI_0_RST,SIPI_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 1. "SYSCONF_0_RST,SYSCONF_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" line.long 0xC "PRST3_M0,Peripheral reset register 3 for MODS 0" bitfld.long 0xC 30. "DSPL_0_RST,DSPL_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0xC 29. "DSPL_2_RST,DSPL_2 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0xC 28. "DSPL_4_RST,DSPL_4 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0xC 27. "DSPL_6_RST,DSPL_6 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0xC 26. "DSPL_8_RST,DSPL_8 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0xC 25. "DSPL_10_RST,DSPL_10 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0xC 19. "SAR_ADC_9BIT_0_RST,SAR_ADC_9BIT_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0xC 18. "SAR_ADC_9BIT_0_SEQ_RST,SAR_ADC_9BIT_0_SEQ reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0xC 17. "SAR_ADC_9BIT_2_RST,SAR_ADC_9BIT_2 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0xC 16. "SAR_ADC_9BIT_2_SEQ_RST,SAR_ADC_9BIT_2_SEQ reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0xC 13. "SAR_ADC_9BIT_6_RST,SAR_ADC_9BIT_6 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0xC 12. "SAR_ADC_9BIT_6_SEQ_RST,SAR_ADC_9BIT_6_SEQ reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0xC 5. "GST_0_RST,GST_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" line.long 0x10 "PRST4_M0,Peripheral reset register 4 for MODS 0" bitfld.long 0x10 31. "SD_ADC_6_RST,SD_ADC_6 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x10 30. "SD_ADC_8_RST,SD_ADC_8 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x10 29. "SD_ADC_10_RST,SD_ADC_10 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x10 8. "DMAMUX_1_0_SYS_0_RST,DMAMUX_1_0_SYS_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x10 7. "DMAMUX_1_0_SYS_2_RST,DMAMUX_1_0_SYS_2 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x10 4. "CRC_0_RST,CRC_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x10 3. "CRC_2_RST,CRC_2 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x10 2. "CRC_4_RST,CRC_4 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" line.long 0x14 "PRST5_M0,Peripheral reset register 5 for MODS 0" bitfld.long 0x14 22. "SAR_ADCQ_12BIT_SV_0_RST,SAR_ADCQ_12BIT_SV_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x14 21. "SAR_ADCQ_12BIT_0_RST,SAR_ADCQ_12BIT_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x14 20. "SAR_ADCQ_12BIT_2_RST,SAR_ADCQ_12BIT_2 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x14 19. "SAR_ADCQ_12BIT_4_RST,SAR_ADCQ_12BIT_4 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x14 18. "SAR_ADCQ_12BIT_6_RST,SAR_ADCQ_12BIT_6 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x14 17. "SAR_ADCQ_12BIT_8_RST,SAR_ADCQ_12BIT_8 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x14 16. "SAR_ADCQ_12BIT_10_RST,SAR_ADCQ_12BIT_10 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x14 2. "SD_ADC_0_RST,SD_ADC_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x14 1. "SD_ADC_2_RST,SD_ADC_2 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x14 0. "SD_ADC_4_RST,SD_ADC_4 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" line.long 0x18 "PRST6_M0,Peripheral reset register 6 for MODS 0" bitfld.long 0x18 30. "SAR_ADC_12BIT_SV_0_RST,SAR_ADC_12BIT_SV_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 29. "SAR_ADC_12BIT_SV_0_SEQ_RST,SAR_ADC_12BIT_SV_0_SEQ reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 28. "SAR_ADC_12BIT_0_RST,SAR_ADC_12BIT_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 27. "SAR_ADC_12BIT_0_SEQ_RST,SAR_ADC_12BIT_0_SEQ reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 26. "SAR_ADC_12BIT_2_RST,SAR_ADC_12BIT_2 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 25. "SAR_ADC_12BIT_2_SEQ_RST,SAR_ADC_12BIT_2_SEQ reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 24. "SAR_ADC_12BIT_4_RST,SAR_ADC_12BIT_4 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 23. "SAR_ADC_12BIT_4_SEQ_RST,SAR_ADC_12BIT_4_SEQ reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 22. "SAR_ADC_12BIT_6_RST,SAR_ADC_12BIT_6 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 21. "SAR_ADC_12BIT_6_SEQ_RST,SAR_ADC_12BIT_6_SEQ reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 20. "SAR_ADC_12BIT_8_RST,SAR_ADC_12BIT_8 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 19. "SAR_ADC_12BIT_8_SEQ_RST,SAR_ADC_12BIT_8_SEQ reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 18. "SAR_ADC_12BIT_10_RST,SAR_ADC_12BIT_10 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 17. "SAR_ADC_12BIT_10_SEQ_RST,SAR_ADC_12BIT_10_SEQ reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" line.long 0x1C "PRST7_M0,Peripheral reset register 7 for MODS 0" bitfld.long 0x1C 19. "M_CAN_1_SUB_2_RST,M_CAN_1_SUB_2 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x1C 18. "M_CAN_2_SUB_2_RST,M_CAN_2_SUB_2 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x1C 17. "M_CAN_3_SUB_2_RST,M_CAN_3_SUB_2 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x1C 16. "M_CAN_4_SUB_2_RST,M_CAN_4_SUB_2 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x1C 13. "CAN_RAM_SUB_2_RST,CAN_RAM_SUB_2 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x1C 8. "M_CAN_1_SUB_4_RST,M_CAN_1_SUB_4 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x1C 7. "M_CAN_2_SUB_4_RST,M_CAN_2_SUB_4 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x1C 6. "M_CAN_3_SUB_4_RST,M_CAN_3_SUB_4 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x1C 5. "M_CAN_4_SUB_4_RST,M_CAN_4_SUB_4 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x1C 2. "CAN_RAM_SUB_4_RST,CAN_RAM_SUB_4 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" rgroup.long 0x630++0x1F line.long 0x0 "PSTAT0_M0,Peripheral reset status register 0 for MODS 0" bitfld.long 0x0 2. "CLUSTER_2_STAT,CLUSTER_2 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x0 1. "CLUSTER_1_STAT,CLUSTER_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x0 0. "CLUSTER_0_STAT,CLUSTER_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" line.long 0x4 "PSTAT1_M0,Peripheral reset status register 1 for MODS 0" bitfld.long 0x4 31. "GTM_0_STAT,GTM_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" line.long 0x8 "PSTAT2_M0,Peripheral reset status register 2 for MODS 0" bitfld.long 0x8 24. "LFAST_0_STAT,LFAST_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 20. "SIPI_0_STAT,SIPI_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 1. "SYSCONF_0_STAT,SYSCONF_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" line.long 0xC "PSTAT3_M0,Peripheral reset status register 3 for MODS 0" bitfld.long 0xC 30. "DSPL_0_STAT,DSPL_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0xC 29. "DSPL_2_STAT,DSPL_2 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0xC 28. "DSPL_4_STAT,DSPL_4 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0xC 27. "DSPL_6_STAT,DSPL_6 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0xC 26. "DSPL_8_STAT,DSPL_8 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0xC 25. "DSPL_10_STAT,DSPL_10 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0xC 19. "SAR_ADC_9BIT_0_STAT,SAR_ADC_9BIT_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0xC 18. "SAR_ADC_9BIT_0_SEQ_STAT,SAR_ADC_9BIT_0_SEQ reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0xC 17. "SAR_ADC_9BIT_2_STAT,SAR_ADC_9BIT_2 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0xC 16. "SAR_ADC_9BIT_2_SEQ_STAT,SAR_ADC_9BIT_2_SEQ reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0xC 13. "SAR_ADC_9BIT_6_STAT,SAR_ADC_9BIT_6 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0xC 12. "SAR_ADC_9BIT_6_SEQ_STAT,SAR_ADC_9BIT_6_SEQ reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0xC 5. "GST_0_STAT,GST_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" line.long 0x10 "PSTAT4_M0,Peripheral reset status register 4 for MODS 0" bitfld.long 0x10 31. "SD_ADC_6_STAT,SD_ADC_6 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x10 30. "SD_ADC_8_STAT,SD_ADC_8 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x10 29. "SD_ADC_10_STAT,SD_ADC_10 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x10 8. "DMAMUX_1_0_SYS_0_STAT,DMAMUX_1_0_SYS_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x10 7. "DMAMUX_1_0_SYS_2_STAT,DMAMUX_1_0_SYS_2 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x10 4. "CRC_0_STAT,CRC_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x10 3. "CRC_2_STAT,CRC_2 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x10 2. "CRC_4_STAT,CRC_4 reset status" "0: peripheral is not in reset,1: peripheral is in reset" line.long 0x14 "PSTAT5_M0,Peripheral reset status register 5 for MODS 0" bitfld.long 0x14 22. "SAR_ADCQ_12BIT_SV_0_STAT,SAR_ADCQ_12BIT_SV_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x14 21. "SAR_ADCQ_12BIT_0_STAT,SAR_ADCQ_12BIT_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x14 20. "SAR_ADCQ_12BIT_2_STAT,SAR_ADCQ_12BIT_2 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x14 19. "SAR_ADCQ_12BIT_4_STAT,SAR_ADCQ_12BIT_4 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x14 18. "SAR_ADCQ_12BIT_6_STAT,SAR_ADCQ_12BIT_6 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x14 17. "SAR_ADCQ_12BIT_8_STAT,SAR_ADCQ_12BIT_8 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x14 16. "SAR_ADCQ_12BIT_10_STAT,SAR_ADCQ_12BIT_10 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x14 2. "SD_ADC_0_STAT,SD_ADC_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x14 1. "SD_ADC_2_STAT,SD_ADC_2 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x14 0. "SD_ADC_4_STAT,SD_ADC_4 reset status" "0: peripheral is not in reset,1: peripheral is in reset" line.long 0x18 "PSTAT6_M0,Peripheral reset status register 6 for MODS 0" bitfld.long 0x18 30. "SAR_ADC_12BIT_SV_0_STAT,SAR_ADC_12BIT_SV_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 29. "SAR_ADC_12BIT_SV_0_SEQ_STAT,SAR_ADC_12BIT_SV_0_SEQ reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 28. "SAR_ADC_12BIT_0_STAT,SAR_ADC_12BIT_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 27. "SAR_ADC_12BIT_0_SEQ_STAT,SAR_ADC_12BIT_0_SEQ reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 26. "SAR_ADC_12BIT_2_STAT,SAR_ADC_12BIT_2 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 25. "SAR_ADC_12BIT_2_SEQ_STAT,SAR_ADC_12BIT_2_SEQ reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 24. "SAR_ADC_12BIT_4_STAT,SAR_ADC_12BIT_4 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 23. "SAR_ADC_12BIT_4_SEQ_STAT,SAR_ADC_12BIT_4_SEQ reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 22. "SAR_ADC_12BIT_6_STAT,SAR_ADC_12BIT_6 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 21. "SAR_ADC_12BIT_6_SEQ_STAT,SAR_ADC_12BIT_6_SEQ reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 20. "SAR_ADC_12BIT_8_STAT,SAR_ADC_12BIT_8 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 19. "SAR_ADC_12BIT_8_SEQ_STAT,SAR_ADC_12BIT_8_SEQ reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 18. "SAR_ADC_12BIT_10_STAT,SAR_ADC_12BIT_10 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 17. "SAR_ADC_12BIT_10_SEQ_STAT,SAR_ADC_12BIT_10_SEQ reset status" "0: peripheral is not in reset,1: peripheral is in reset" line.long 0x1C "PSTAT7_M0,Peripheral reset status register 7 for MODS 0" bitfld.long 0x1C 19. "M_CAN_1_SUB_2_STAT,M_CAN_1_SUB_2 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x1C 18. "M_CAN_2_SUB_2_STAT,M_CAN_2_SUB_2 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x1C 17. "M_CAN_3_SUB_2_STAT,M_CAN_3_SUB_2 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x1C 16. "M_CAN_4_SUB_2_STAT,M_CAN_4_SUB_2 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x1C 13. "CAN_RAM_SUB_2_STAT,CAN_RAM_SUB_2 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x1C 8. "M_CAN_1_SUB_4_STAT,M_CAN_1_SUB_4 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x1C 7. "M_CAN_2_SUB_4_STAT,M_CAN_2_SUB_4 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x1C 6. "M_CAN_3_SUB_4_STAT,M_CAN_3_SUB_4 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x1C 5. "M_CAN_4_SUB_4_STAT,M_CAN_4_SUB_4 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x1C 2. "CAN_RAM_SUB_4_STAT,CAN_RAM_SUB_4 reset status" "0: peripheral is not in reset,1: peripheral is in reset" group.long 0x654++0x1B line.long 0x0 "PRST1_M1,Peripheral reset register 1 for MODS 1" bitfld.long 0x0 31. "GTM_1_RST,GTM_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" line.long 0x4 "PRST2_M1,Peripheral reset register 2 for MODS 1" bitfld.long 0x4 24. "LFAST_1_RST,LFAST_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 20. "SIPI_1_RST,SIPI_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" line.long 0x8 "PRST3_M1,Peripheral reset register 3 for MODS 1" bitfld.long 0x8 30. "DSPL_1_RST,DSPL_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 29. "DSPL_3_RST,DSPL_3 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 28. "DSPL_5_RST,DSPL_5 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 27. "DSPL_7_RST,DSPL_7 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 26. "DSPL_9_RST,DSPL_9 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 25. "DSPL_11_RST,DSPL_11 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 17. "SAR_ADC_9BIT_3_RST,SAR_ADC_9BIT_3 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 16. "SAR_ADC_9BIT_3_SEQ_RST,SAR_ADC_9BIT_3_SEQ reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" line.long 0xC "PRST4_M1,Peripheral reset register 4 for MODS 1" bitfld.long 0xC 31. "SD_ADC_7_RST,SD_ADC_7 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0xC 30. "SD_ADC_9_RST,SD_ADC_9 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0xC 29. "SD_ADC_11_RST,SD_ADC_11 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0xC 8. "DMAMUX_1_0_SYS_1_RST,DMAMUX_1_0_SYS_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0xC 7. "DMAMUX_3_0_SYS_3_RST,DMAMUX_3_0_SYS_3 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0xC 4. "CRC_1_RST,CRC_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0xC 3. "CRC_3_RST,CRC_3 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0xC 2. "CRC_5_RST,CRC_5 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" line.long 0x10 "PRST5_M1,Peripheral reset register 5 for MODS 1" bitfld.long 0x10 21. "SAR_ADCQ_12BIT_1_RST,SAR_ADCQ_12BIT_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x10 20. "SAR_ADCQ_12BIT_3_RST,SAR_ADCQ_12BIT_3 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x10 19. "SAR_ADCQ_12BIT_5_RST,SAR_ADCQ_12BIT_5 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x10 18. "SAR_ADCQ_12BIT_7_RST,SAR_ADCQ_12BIT_7 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x10 17. "SAR_ADCQ_12BIT_9_RST,SAR_ADCQ_12BIT_9 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x10 2. "SD_ADC_1_RST,SD_ADC_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x10 1. "SD_ADC_3_RST,SD_ADC_3 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x10 0. "SD_ADC_5_RST,SD_ADC_5 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" line.long 0x14 "PRST6_M1,Peripheral reset register 6 for MODS 1" bitfld.long 0x14 28. "SAR_ADC_12BIT_1_RST,SAR_ADC_12BIT_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x14 27. "SAR_ADC_12BIT_1_SEQ_RST,SAR_ADC_12BIT_1_SEQ reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x14 26. "SAR_ADC_12BIT_3_RST,SAR_ADC_12BIT_3 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x14 25. "SAR_ADC_12BIT_3_SEQ_RST,SAR_ADC_12BIT_3_SEQ reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x14 24. "SAR_ADC_12BIT_5_RST,SAR_ADC_12BIT_5 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x14 23. "SAR_ADC_12BIT_5_SEQ_RST,SAR_ADC_12BIT_5_SEQ reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x14 22. "SAR_ADC_12BIT_7_RST,SAR_ADC_12BIT_7 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x14 21. "SAR_ADC_12BIT_7_SEQ_RST,SAR_ADC_12BIT_7_SEQ reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x14 20. "SAR_ADC_12BIT_9_RST,SAR_ADC_12BIT_9 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x14 19. "SAR_ADC_12BIT_9_SEQ_RST,SAR_ADC_12BIT_9_SEQ reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" line.long 0x18 "PRST7_M1,Peripheral reset register 7 for MODS 1" bitfld.long 0x18 30. "M_CAN_1_SUB_1_RST,M_CAN_1_SUB_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 29. "M_CAN_2_SUB_1_RST,M_CAN_2_SUB_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 28. "M_CAN_3_SUB_1_RST,M_CAN_3_SUB_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 27. "M_CAN_4_SUB_1_RST,M_CAN_4_SUB_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 24. "CAN_RAM_SUB_1_RST,CAN_RAM_SUB_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 19. "M_CAN_1_SUB_3_RST,M_CAN_1_SUB_3 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 18. "M_CAN_2_SUB_3_RST,M_CAN_2_SUB_3 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 17. "M_CAN_3_SUB_3_RST,M_CAN_3_SUB_3 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 16. "M_CAN_4_SUB_3_RST,M_CAN_4_SUB_3 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x18 13. "CAN_RAM_SUB_3_RST,CAN_RAM_SUB_3 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" rgroup.long 0x674++0x1B line.long 0x0 "PSTAT1_M1,Peripheral reset status register 1 for MODS 1" bitfld.long 0x0 31. "GTM_1_STAT,GTM_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" line.long 0x4 "PSTAT2_M1,Peripheral reset status register 2 for MODS 1" bitfld.long 0x4 24. "LFAST_1_STAT,LFAST_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 20. "SIPI_1_STAT,SIPI_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" line.long 0x8 "PSTAT3_M1,Peripheral reset status register 3 for MODS 1" bitfld.long 0x8 30. "DSPL_1_STAT,DSPL_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 29. "DSPL_3_STAT,DSPL_3 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 28. "DSPL_5_STAT,DSPL_5 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 27. "DSPL_7_STAT,DSPL_7 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 26. "DSPL_9_STAT,DSPL_9 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 25. "DSPL_11_STAT,DSPL_11 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 17. "SAR_ADC_9BIT_3_STAT,SAR_ADC_9BIT_3 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 16. "SAR_ADC_9BIT_3_SEQ_STAT,SAR_ADC_9BIT_3_SEQ reset status" "0: peripheral is not in reset,1: peripheral is in reset" line.long 0xC "PSTAT4_M1,Peripheral reset status register 4 for MODS 1" bitfld.long 0xC 31. "SD_ADC_7_STAT,SD_ADC_7 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0xC 30. "SD_ADC_9_STAT,SD_ADC_9 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0xC 29. "SD_ADC_11_STAT,SD_ADC_11 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0xC 8. "DMAMUX_1_0_SYS_1_STAT,DMAMUX_1_0_SYS_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0xC 7. "DMAMUX_3_0_SYS_3_STAT,DMAMUX_3_0_SYS_3 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0xC 4. "CRC_1_STAT,CRC_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0xC 3. "CRC_3_STAT,CRC_3 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0xC 2. "CRC_5_STAT,CRC_5 reset status" "0: peripheral is not in reset,1: peripheral is in reset" line.long 0x10 "PSTAT5_M1,Peripheral reset status register 5 for MODS 1" bitfld.long 0x10 21. "SAR_ADCQ_12BIT_1_STAT,SAR_ADCQ_12BIT_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x10 20. "SAR_ADCQ_12BIT_3_STAT,SAR_ADCQ_12BIT_3 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x10 19. "SAR_ADCQ_12BIT_5_STAT,SAR_ADCQ_12BIT_5 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x10 18. "SAR_ADCQ_12BIT_7_STAT,SAR_ADCQ_12BIT_7 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x10 17. "SAR_ADCQ_12BIT_9_STAT,SAR_ADCQ_12BIT_9 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x10 2. "SD_ADC_1_STAT,SD_ADC_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x10 1. "SD_ADC_3_STAT,SD_ADC_3 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x10 0. "SD_ADC_5_STAT,SD_ADC_5 reset status" "0: peripheral is not in reset,1: peripheral is in reset" line.long 0x14 "PSTAT6_M1,Peripheral reset status register 6 for MODS 1" bitfld.long 0x14 28. "SAR_ADC_12BIT_1_STAT,SAR_ADC_12BIT_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x14 27. "SAR_ADC_12BIT_1_SEQ_STAT,SAR_ADC_12BIT_1_SEQ reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x14 26. "SAR_ADC_12BIT_3_STAT,SAR_ADC_12BIT_3 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x14 25. "SAR_ADC_12BIT_3_SEQ_STAT,SAR_ADC_12BIT_3_SEQ reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x14 24. "SAR_ADC_12BIT_5_STAT,SAR_ADC_12BIT_5 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x14 23. "SAR_ADC_12BIT_5_SEQ_STAT,SAR_ADC_12BIT_5_SEQ reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x14 22. "SAR_ADC_12BIT_7_STAT,SAR_ADC_12BIT_7 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x14 21. "SAR_ADC_12BIT_7_SEQ_STAT,SAR_ADC_12BIT_7_SEQ reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x14 20. "SAR_ADC_12BIT_9_STAT,SAR_ADC_12BIT_9 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x14 19. "SAR_ADC_12BIT_9_SEQ_STAT,SAR_ADC_12BIT_9_SEQ reset status" "0: peripheral is not in reset,1: peripheral is in reset" line.long 0x18 "PSTAT7_M1,Peripheral reset status register 7 for MODS 1" bitfld.long 0x18 30. "M_CAN_1_SUB_1_STAT,M_CAN_1_SUB_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 29. "M_CAN_2_SUB_1_STAT,M_CAN_2_SUB_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 28. "M_CAN_3_SUB_1_STAT,M_CAN_3_SUB_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 27. "M_CAN_4_SUB_1_STAT,M_CAN_4_SUB_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 24. "CAN_RAM_SUB_1_STAT,CAN_RAM_SUB_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 19. "M_CAN_1_SUB_3_STAT,M_CAN_1_SUB_3 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 18. "M_CAN_2_SUB_3_STAT,M_CAN_2_SUB_3 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 17. "M_CAN_3_SUB_3_STAT,M_CAN_3_SUB_3 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 16. "M_CAN_4_SUB_3_STAT,M_CAN_4_SUB_3 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x18 13. "CAN_RAM_SUB_3_STAT,CAN_RAM_SUB_3 reset status" "0: peripheral is not in reset,1: peripheral is in reset" group.long 0x694++0x3 line.long 0x0 "PRST1_M2,Peripheral reset register 1 for MODS 2" bitfld.long 0x0 5. "SIUL_0_RST,SIUL_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x0 4. "SIUL_2_RST,SIUL_2 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" group.long 0x6A4++0xB line.long 0x0 "PRST5_M2,Peripheral reset register 5 for MODS 2" bitfld.long 0x0 29. "PSI5S_0_RST,PSI5S_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x0 11. "SDMMC_0_RST,SDMMC_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x0 10. "OCTOSPI_0_RST,OCTOSPI_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x0 9. "AESLIGHT_0_RST,AESLIGHT_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x0 8. "DFA_0_RST,DFA_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" line.long 0x4 "PRST6_M2,Peripheral reset register 6 for MODS 2" bitfld.long 0x4 31. "SPIQ_8_RST,SPIQ_8 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 27. "LINFLEXD_20_RST,LINFLEXD_20 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 26. "LINFLEXD_22_RST,LINFLEXD_22 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 25. "LINFLEXD_24_RST,LINFLEXD_24 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 24. "LINFLEXD_26_RST,LINFLEXD_26 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 16. "LINFLEXD_2_RST,LINFLEXD_2 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 15. "LINFLEXD_4_RST,LINFLEXD_4 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 14. "LINFLEXD_6_RST,LINFLEXD_6 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 13. "LINFLEXD_8_RST,LINFLEXD_8 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 12. "LINFLEXD_10_RST,LINFLEXD_10 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 11. "LINFLEXD_12_RST,LINFLEXD_12 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 10. "LINFLEXD_14_RST,LINFLEXD_14 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 9. "LINFLEXD_16_RST,LINFLEXD_16 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 8. "LINFLEXD_18_RST,LINFLEXD_18 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 5. "SENT_0_RST,SENT_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 1. "PSI5_0_RST,PSI5_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" line.long 0x8 "PRST7_M2,Peripheral reset register 7 for MODS 2" bitfld.long 0x8 25. "FLEXRAY_0_RST,FLEXRAY_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 11. "DSPI_0_RST,DSPI_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 9. "DSPI_4_RST,DSPI_4 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 3. "SPIQ_0_RST,SPIQ_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 1. "SPIQ_4_RST,SPIQ_4 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 0. "SPIQ_6_RST,SPIQ_6 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" rgroup.long 0x6B4++0x3 line.long 0x0 "PSTAT1_M2,Peripheral reset status register 1 for MODS 2" bitfld.long 0x0 5. "SIUL_0_STAT,SIUL_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x0 4. "SIUL_2_STAT,SIUL_2 reset status" "0: peripheral is not in reset,1: peripheral is in reset" rgroup.long 0x6C4++0xB line.long 0x0 "PSTAT5_M2,Peripheral reset status register 5 for MODS 2" bitfld.long 0x0 29. "PSI5S_0_STAT,PSI5S_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x0 11. "SDMMC_0_STAT,SDMMC_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x0 10. "OCTOSPI_0_STAT,OCTOSPI_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x0 9. "AESLIGHT_0_STAT,AESLIGHT_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x0 8. "DFA_0_STAT,DFA_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" line.long 0x4 "PSTAT6_M2,Peripheral reset status register 6 for MODS 2" bitfld.long 0x4 31. "SPIQ_8_STAT,SPIQ_8 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 27. "LINFLEXD_20_STAT,LINFLEXD_20 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 26. "LINFLEXD_22_STAT,LINFLEXD_22 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 25. "LINFLEXD_24_STAT,LINFLEXD_24 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 24. "LINFLEXD_26_STAT,LINFLEXD_26 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 16. "LINFLEXD_2_STAT,LINFLEXD_2 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 15. "LINFLEXD_4_STAT,LINFLEXD_4 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 14. "LINFLEXD_6_STAT,LINFLEXD_6 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 13. "LINFLEXD_8_STAT,LINFLEXD_8 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 12. "LINFLEXD_10_STAT,LINFLEXD_10 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 11. "LINFLEXD_12_STAT,LINFLEXD_12 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 10. "LINFLEXD_14_STAT,LINFLEXD_14 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 9. "LINFLEXD_16_STAT,LINFLEXD_16 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 8. "LINFLEXD_18_STAT,LINFLEXD_18 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 5. "SENT_0_STAT,SENT_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 1. "PSI5_0_STAT,PSI5_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" line.long 0x8 "PSTAT7_M2,Peripheral reset status register 7 for MODS 2" bitfld.long 0x8 25. "FLEXRAY_0_STAT,FLEXRAY_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 11. "DSPI_0_STAT,DSPI_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 9. "DSPI_4_STAT,DSPI_4 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 3. "SPIQ_0_STAT,SPIQ_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 1. "SPIQ_4_STAT,SPIQ_4 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 0. "SPIQ_6_STAT,SPIQ_6 reset status" "0: peripheral is not in reset,1: peripheral is in reset" group.long 0x6D4++0x3 line.long 0x0 "PRST1_M3,Peripheral reset register 1 for MODS 3" bitfld.long 0x0 17. "FCCU2_0_RST,FCCU2_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" group.long 0x6E4++0xB line.long 0x0 "PRST5_M3,Peripheral reset register 5 for MODS 3" bitfld.long 0x0 29. "PSI5S_1_RST,PSI5S_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x0 26. "IIC_1_RST,IIC_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x0 3. "MSCP_0_RST,MSCP_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" line.long 0x4 "PRST6_M3,Peripheral reset register 6 for MODS 3" bitfld.long 0x4 27. "LINFLEXD_21_RST,LINFLEXD_21 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 26. "LINFLEXD_23_RST,LINFLEXD_23 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 25. "LINFLEXD_25_RST,LINFLEXD_25 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 24. "LINFLEXD_27_RST,LINFLEXD_27 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 16. "LINFLEXD_3_RST,LINFLEXD_3 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 15. "LINFLEXD_5_RST,LINFLEXD_5 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 14. "LINFLEXD_7_RST,LINFLEXD_7 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 13. "LINFLEXD_9_RST,LINFLEXD_9 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 12. "LINFLEXD_11_RST,LINFLEXD_11 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 11. "LINFLEXD_13_RST,LINFLEXD_13 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 10. "LINFLEXD_15_RST,LINFLEXD_15 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 9. "LINFLEXD_17_RST,LINFLEXD_17 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 8. "LINFLEXD_19_RST,LINFLEXD_19 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 5. "SENT_1_RST,SENT_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 1. "PSI5_1_RST,PSI5_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" line.long 0x8 "PRST7_M3,Peripheral reset register 7 for MODS 3" bitfld.long 0x8 25. "FLEXRAY_1_RST,FLEXRAY_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 17. "MSC_1_RST,MSC_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 8. "DSPI_7_RST,DSPI_7 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" rgroup.long 0x6F4++0x3 line.long 0x0 "PSTAT1_M3,Peripheral reset status register 1 for MODS 3" bitfld.long 0x0 17. "FCCU2_0_STAT,FCCU2_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" rgroup.long 0x704++0xB line.long 0x0 "PSTAT5_M3,Peripheral reset status register 5 for MODS 3" bitfld.long 0x0 29. "PSI5S_1_STAT,PSI5S_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x0 26. "IIC_1_STAT,IIC_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x0 3. "MSCP_0_STAT,MSCP_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" line.long 0x4 "PSTAT6_M3,Peripheral reset status register 6 for MODS 3" bitfld.long 0x4 27. "LINFLEXD_21_STAT,LINFLEXD_21 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 26. "LINFLEXD_23_STAT,LINFLEXD_23 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 25. "LINFLEXD_25_STAT,LINFLEXD_25 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 24. "LINFLEXD_27_STAT,LINFLEXD_27 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 16. "LINFLEXD_3_STAT,LINFLEXD_3 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 15. "LINFLEXD_5_STAT,LINFLEXD_5 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 14. "LINFLEXD_7_STAT,LINFLEXD_7 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 13. "LINFLEXD_9_STAT,LINFLEXD_9 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 12. "LINFLEXD_11_STAT,LINFLEXD_11 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 11. "LINFLEXD_13_STAT,LINFLEXD_13 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 10. "LINFLEXD_15_STAT,LINFLEXD_15 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 9. "LINFLEXD_17_STAT,LINFLEXD_17 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 8. "LINFLEXD_19_STAT,LINFLEXD_19 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 5. "SENT_1_STAT,SENT_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 1. "PSI5_1_STAT,PSI5_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" line.long 0x8 "PSTAT7_M3,Peripheral reset status register 7 for MODS 3" bitfld.long 0x8 25. "FLEXRAY_1_STAT,FLEXRAY_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 17. "MSC_1_STAT,MSC_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 8. "DSPI_7_STAT,DSPI_7 reset status" "0: peripheral is not in reset,1: peripheral is in reset" group.long 0x718++0x3 line.long 0x0 "PRST2_M4,Peripheral reset register 2 for MODS 4" bitfld.long 0x0 1. "SYSCONF_4_RST,SYSCONF_4 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" group.long 0x728++0x7 line.long 0x0 "PRST6_M4,Peripheral reset register 6 for MODS 4" bitfld.long 0x0 28. "DSPI_1_RST,DSPI_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x0 27. "DSPI_2_RST,DSPI_2 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x0 26. "DSPI_3_RST,DSPI_3 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x0 24. "DSPI_5_RST,DSPI_5 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x0 23. "DSPI_6_RST,DSPI_6 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x0 21. "DSPI_8_RST,DSPI_8 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x0 20. "DSPI_9_RST,DSPI_9 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" line.long 0x4 "PRST7_M4,Peripheral reset register 7 for MODS 4" bitfld.long 0x4 31. "ETHERNET_0_RST,ETHERNET_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 30. "ETHERNET_1_RST,ETHERNET_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 27. "CM_1_RST,CM_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 26. "CM_2_RST,CM_2 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 20. "SPIQ_1_RST,SPIQ_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 18. "SPIQ_3_RST,SPIQ_3 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 14. "SPIQ_7_RST,SPIQ_7 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 12. "SPIQ_9_RST,SPIQ_9 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 7. "MSC_0_RST,MSC_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 5. "MSC_2_RST,MSC_2 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 4. "MSC_3_RST,MSC_3 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 1. "MSCP_1_RST,MSCP_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" rgroup.long 0x738++0x3 line.long 0x0 "PSTAT2_M4,Peripheral reset status register 2 for MODS 4" bitfld.long 0x0 1. "SYSCONF_4_STAT,SYSCONF_4 reset status" "0: peripheral is not in reset,1: peripheral is in reset" rgroup.long 0x748++0x7 line.long 0x0 "PSTAT6_M4,Peripheral reset status register 6 for MODS 4" bitfld.long 0x0 28. "DSPI_1_STAT,DSPI_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x0 27. "DSPI_2_STAT,DSPI_2 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x0 26. "DSPI_3_STAT,DSPI_3 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x0 24. "DSPI_5_STAT,DSPI_5 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x0 23. "DSPI_6_STAT,DSPI_6 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x0 21. "DSPI_8_STAT,DSPI_8 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x0 20. "DSPI_9_STAT,DSPI_9 reset status" "0: peripheral is not in reset,1: peripheral is in reset" line.long 0x4 "PSTAT7_M4,Peripheral reset status register 7 for MODS 4" bitfld.long 0x4 31. "ETHERNET_0_STAT,ETHERNET_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 30. "ETHERNET_1_STAT,ETHERNET_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 27. "CM_1_STAT,CM_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 26. "CM_2_STAT,CM_2 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 20. "SPIQ_1_STAT,SPIQ_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 18. "SPIQ_3_STAT,SPIQ_3 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 14. "SPIQ_7_STAT,SPIQ_7 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 12. "SPIQ_9_STAT,SPIQ_9 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 7. "MSC_0_STAT,MSC_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 5. "MSC_2_STAT,MSC_2 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 4. "MSC_3_STAT,MSC_3 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 1. "MSCP_1_STAT,MSCP_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" group.long 0x758++0x7 line.long 0x0 "PRST2_M5,Peripheral reset register 2 for MODS 5" bitfld.long 0x0 1. "SYSCONF_5_RST,SYSCONF_5 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" line.long 0x4 "PRST3_M5,Peripheral reset register 3 for MODS 5" bitfld.long 0x4 19. "SAR_ADC_LP_RUN_0_RST,SAR_ADC_LP_RUN_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 18. "SAR_ADC_LP_RUN_0_SEQ_RST,SAR_ADC_LP_RUN_0_SEQ reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" group.long 0x764++0xB line.long 0x0 "PRST5_M5,Peripheral reset register 5 for MODS 5" bitfld.long 0x0 26. "IIC_0_RST,IIC_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" line.long 0x4 "PRST6_M5,Peripheral reset register 6 for MODS 5" bitfld.long 0x4 17. "LINFLEXD_0_RST,LINFLEXD_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x4 16. "LINFLEXD_1_RST,LINFLEXD_1 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" line.long 0x8 "PRST7_M5,Peripheral reset register 7 for MODS 5" bitfld.long 0x8 31. "M_TTCAN_0_SUB_0_RST,M_TTCAN_0_SUB_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 30. "M_CAN_1_SUB_0_RST,M_CAN_1_SUB_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 29. "M_CAN_2_SUB_0_RST,M_CAN_2_SUB_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 28. "M_CAN_3_SUB_0_RST,M_CAN_3_SUB_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 24. "CAN_RAM_SUB_0_RST,CAN_RAM_SUB_0 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 19. "SPIQ_2_RST,SPIQ_2 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" newline bitfld.long 0x8 16. "SPIQ_5_RST,SPIQ_5 reset" "0: No forced reset of peripheral,1: Forced reset of peripheral" rgroup.long 0x778++0x7 line.long 0x0 "PSTAT2_M5,Peripheral reset status register 2 for MODS 5" bitfld.long 0x0 1. "SYSCONF_5_STAT,SYSCONF_5 reset status" "0: peripheral is not in reset,1: peripheral is in reset" line.long 0x4 "PSTAT3_M5,Peripheral reset status register 3 for MODS 5" bitfld.long 0x4 19. "SAR_ADC_LP_RUN_0_STAT,SAR_ADC_LP_RUN_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 18. "SAR_ADC_LP_RUN_0_SEQ_STAT,SAR_ADC_LP_RUN_0_SEQ reset status" "0: peripheral is not in reset,1: peripheral is in reset" rgroup.long 0x784++0xB line.long 0x0 "PSTAT5_M5,Peripheral reset status register 5 for MODS 5" bitfld.long 0x0 26. "IIC_0_STAT,IIC_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" line.long 0x4 "PSTAT6_M5,Peripheral reset status register 6 for MODS 5" bitfld.long 0x4 17. "LINFLEXD_0_STAT,LINFLEXD_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x4 16. "LINFLEXD_1_STAT,LINFLEXD_1 reset status" "0: peripheral is not in reset,1: peripheral is in reset" line.long 0x8 "PSTAT7_M5,Peripheral reset status register 7 for MODS 5" bitfld.long 0x8 31. "M_TTCAN_0_SUB_0_STAT,M_TTCAN_0_SUB_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 30. "M_CAN_1_SUB_0_STAT,M_CAN_1_SUB_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 29. "M_CAN_2_SUB_0_STAT,M_CAN_2_SUB_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 28. "M_CAN_3_SUB_0_STAT,M_CAN_3_SUB_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 24. "CAN_RAM_SUB_0_STAT,CAN_RAM_SUB_0 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 19. "SPIQ_2_STAT,SPIQ_2 reset status" "0: peripheral is not in reset,1: peripheral is in reset" newline bitfld.long 0x8 16. "SPIQ_5_STAT,SPIQ_5 reset status" "0: peripheral is not in reset,1: peripheral is in reset" tree.end tree.end tree "MEMU2 (Memory Error Management Unit)" base ad:0x71130000 group.long 0x0++0x7 line.long 0x0 "CTRL,Control register" bitfld.long 0x0 15. "SWR,Software reset bit." "0: No reset.,1: Reset asserted." line.long 0x4 "ERR_FLAG,Error Flag register" bitfld.long 0x4 20. "PR_CE,Peripheral RAM ECC correctable error detect flag." "0: No new and unique error detected.,1: New entry in correctable error reporting table.." newline bitfld.long 0x4 19. "PR_UCE,Peripheral RAM ECC uncorrectable error detect flag." "0: No new and unique error detected.,1: New entry in uncorrectable error reporting table.." newline bitfld.long 0x4 18. "PR_CEO,Peripheral RAM ECC correctable error overflow flag." "0: No overflow.,1: Overflow in the correctable error reporting.." newline bitfld.long 0x4 17. "PR_UCEO,Peripheral RAM ECC uncorrectable error overflow flag." "0: No overflow.,1: Overflow in the uncorrectable error reporting.." newline bitfld.long 0x4 14. "F_SCE,NVM ECC single correctable error detect flag." "0: No new and unique error detected.,1: New entry in correctable error reporting table.." newline bitfld.long 0x4 13. "F_DCE,NVM ECC double correctable error detect flag." "0: No new and unique error detected.,1: New entry in correctable error reporting table.." newline bitfld.long 0x4 12. "F_UCE,NVM ECC uncorrectable error detect flag." "0: No new and unique error detected.,1: New entry in uncorrectable error reporting table.." newline bitfld.long 0x4 11. "F_SCEO,NVM ECC single correctable error overflow flag." "0: No overflow.,1: Overflow in the correctable error reporting.." newline bitfld.long 0x4 10. "F_DCEO,NVM ECC double correctable error overflow flag." "0: No overflow.,1: Overflow in the correctable error reporting.." newline bitfld.long 0x4 9. "F_UCEO,NVM ECC uncorrectable error overflow flag." "0: No overflow.,1: Overflow in the uncorrectable error reporting.." newline bitfld.long 0x4 4. "SR_CE,System RAM ECC and MBIST correctable error detect flag." "0: No new and unique error detected.,1: New entry in correctable error reporting table.." newline bitfld.long 0x4 3. "SR_UCE,System RAM ECC and MBIST uncorrectable error detect flag." "0: No new and unique error detected.,1: New entry in uncorrectable error reporting table.." newline bitfld.long 0x4 2. "SR_CEO,System RAM ECC and MBIST correctable error overflow flag." "0: No overflow.,1: Overflow in the correctable error reporting.." newline bitfld.long 0x4 1. "SR_UCEO,System RAM ECC and MBIST uncorrectable error overflow flag." "0: No overflow.,1: Overflow in the uncorrectable error reporting.." group.long 0xC++0xB line.long 0x0 "SYS_RAM_OUT_TRIG_CTRL,System RAM output trigger control register" bitfld.long 0x0 31. "FR_SR_FCCU_TRIG0,Forces FCCU_TRIG0 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x0 30. "FR_SR_FCCU_TRIG1,Forces FCCU_TRIG1 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x0 29. "FR_SR_FCCU_TRIG2,Forces FCCU_TRIG2 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x0 28. "FR_SR_FCCU_TRIG3,Forces FCCU_TRIG3 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x0 27. "FR_SR_FCCU_TRIG4,Forces FCCU_TRIG4 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x0 26. "FR_SR_FCCU_TRIG5,Forces FCCU_TRIG5 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x0 25. "FR_SR_FCCU_TRIG6,Forces FCCU_TRIG6 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x0 24. "FR_SR_FCCU_TRIG7,Forces FCCU_TRIG7 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x0 23. "FR_SR_FCCU_TRIG8,Forces FCCU_TRIG8 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x0 22. "FR_SR_FCCU_TRIG9,Forces FCCU_TRIG9 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x0 2. "FR_SR_CEO,Forces System RAM correctable error overflow flag" "0: Forcing is disabled.,1: Forces SR_CEO flag going towards FCCU2 to 1." newline bitfld.long 0x0 1. "FR_SR_UCEO,Forces System RAM uncorrectable error overflow flag" "0: Forcing is disabled.,1: Forces SR_UCEO flag going towards FCCU2 to 1." line.long 0x4 "PERIPH_RAM_OUT_TRIG_CTRL,Peripheral RAM output trigger control register" bitfld.long 0x4 18. "FR_PR_CEO,Force Peripheral RAM correctable error overflow flag" "0: Forcing is disabled.,1: Forces PR_CEO flag going towards FCCU2 to 1." newline bitfld.long 0x4 17. "FR_PR_UCEO,Forces Peripheral RAM uncorrectable error overflow flag." "0: Forcing is disabled.,1: Forces PR_UCEO flag going towards FCCU2 to 1." newline bitfld.long 0x4 9. "FR_PR_FCCU_TRIG9,Forces FCCU_TRIG9 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x4 8. "FR_PR_FCCU_TRIG8,Forces FCCU_TRIG8 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x4 7. "FR_PR_FCCU_TRIG7,Forces FCCU_TRIG7 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x4 6. "FR_PR_FCCU_TRIG6,Forces FCCU_TRIG6 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x4 5. "FR_PR_FCCU_TRIG5,Forces FCCU_TRIG5 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x4 4. "FR_PR_FCCU_TRIG4,Forces FCCU_TRIG4 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x4 3. "FR_PR_FCCU_TRIG3,Forces FCCU_TRIG3 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x4 2. "FR_PR_FCCU_TRIG2,Forces FCCU_TRIG2 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x4 1. "FR_PR_FCCU_TRIG1,Forces FCCU_TRIG1 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x4 0. "FR_PR_FCCU_TRIG0,Forces FCCU_TRIG0 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." line.long 0x8 "NVM_OUT_TRIG_CTRL,NVM output trigger control register" bitfld.long 0x8 31. "FR_F_FCCU_TRIG0,Forces FCCU_TRIG0 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x8 30. "FR_F_FCCU_TRIG1,Forces FCCU_TRIG1 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x8 29. "FR_F_FCCU_TRIG2,Forces FCCU_TRIG2 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x8 28. "FR_F_FCCU_TRIG3,Forces FCCU_TRIG3 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x8 27. "FR_F_FCCU_TRIG4,Forces FCCU_TRIG4 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x8 26. "FR_F_FCCU_TRIG5,Forces FCCU_TRIG5 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x8 25. "FR_F_FCCU_TRIG6,Forces FCCU_TRIG6 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x8 24. "FR_F_FCCU_TRIG7,Forces FCCU_TRIG7 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x8 23. "FR_F_FCCU_TRIG8,Forces FCCU_TRIG8 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x8 22. "FR_F_FCCU_TRIG9,Forces FCCU_TRIG9 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x8 21. "FR_F_FCCU_TRIG10,Forces FCCU_TRIG10 to 1" "0: Forcing is disabled.,1: Forces trigger going to FCCU2 to 1." newline bitfld.long 0x8 10. "FR_F_SCEO,Forces NVM single correctable error overflow flag" "0: Forcing is disabled.,1: Forces F_SCEO flag going towards FCCU2 to 1." newline bitfld.long 0x8 9. "FR_F_UCEO,Forces NVM uncorrectable error overflow flag" "0: Forcing is disabled.,1: Forces F_UCEO flag going towards FCCU2 to 1." newline bitfld.long 0x8 8. "FR_F_DCEO,Forces NVM double correctable error overflow flag" "0: Forcing is disabled.,1: Forces F_DCEO flag going towards FCCU2 to 1." group.long 0x20++0xFF line.long 0x0 "SYS_RAM_CERR_STS0,System RAM correctable error reporting table status register" bitfld.long 0x0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x0 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x0 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x4 "SYS_RAM_CERR_ADDR0,System RAM correctable error reporting table address register" hexmask.long 0x4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x8 "SYS_RAM_CERR_STS1,System RAM correctable error reporting table status register" bitfld.long 0x8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x8 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x8 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0xC "SYS_RAM_CERR_ADDR1,System RAM correctable error reporting table address register" hexmask.long 0xC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x10 "SYS_RAM_CERR_STS2,System RAM correctable error reporting table status register" bitfld.long 0x10 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x10 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x10 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x10 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x14 "SYS_RAM_CERR_ADDR2,System RAM correctable error reporting table address register" hexmask.long 0x14 0.--31. 1. "ERR_ADD,Error address field" line.long 0x18 "SYS_RAM_CERR_STS3,System RAM correctable error reporting table status register" bitfld.long 0x18 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x18 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x18 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x18 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x1C "SYS_RAM_CERR_ADDR3,System RAM correctable error reporting table address register" hexmask.long 0x1C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x20 "SYS_RAM_CERR_STS4,System RAM correctable error reporting table status register" bitfld.long 0x20 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x20 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x20 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x20 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x24 "SYS_RAM_CERR_ADDR4,System RAM correctable error reporting table address register" hexmask.long 0x24 0.--31. 1. "ERR_ADD,Error address field" line.long 0x28 "SYS_RAM_CERR_STS5,System RAM correctable error reporting table status register" bitfld.long 0x28 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x28 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x28 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x28 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x2C "SYS_RAM_CERR_ADDR5,System RAM correctable error reporting table address register" hexmask.long 0x2C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x30 "SYS_RAM_CERR_STS6,System RAM correctable error reporting table status register" bitfld.long 0x30 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x30 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x30 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x30 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x34 "SYS_RAM_CERR_ADDR6,System RAM correctable error reporting table address register" hexmask.long 0x34 0.--31. 1. "ERR_ADD,Error address field" line.long 0x38 "SYS_RAM_CERR_STS7,System RAM correctable error reporting table status register" bitfld.long 0x38 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x38 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x38 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x38 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x3C "SYS_RAM_CERR_ADDR7,System RAM correctable error reporting table address register" hexmask.long 0x3C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x40 "SYS_RAM_CERR_STS8,System RAM correctable error reporting table status register" bitfld.long 0x40 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x40 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x40 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x40 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x44 "SYS_RAM_CERR_ADDR8,System RAM correctable error reporting table address register" hexmask.long 0x44 0.--31. 1. "ERR_ADD,Error address field" line.long 0x48 "SYS_RAM_CERR_STS9,System RAM correctable error reporting table status register" bitfld.long 0x48 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x48 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x48 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x48 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x4C "SYS_RAM_CERR_ADDR9,System RAM correctable error reporting table address register" hexmask.long 0x4C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x50 "SYS_RAM_CERR_STS10,System RAM correctable error reporting table status register" bitfld.long 0x50 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x50 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x50 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x50 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x54 "SYS_RAM_CERR_ADDR10,System RAM correctable error reporting table address register" hexmask.long 0x54 0.--31. 1. "ERR_ADD,Error address field" line.long 0x58 "SYS_RAM_CERR_STS11,System RAM correctable error reporting table status register" bitfld.long 0x58 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x58 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x58 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x58 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x5C "SYS_RAM_CERR_ADDR11,System RAM correctable error reporting table address register" hexmask.long 0x5C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x60 "SYS_RAM_CERR_STS12,System RAM correctable error reporting table status register" bitfld.long 0x60 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x60 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x60 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x60 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x64 "SYS_RAM_CERR_ADDR12,System RAM correctable error reporting table address register" hexmask.long 0x64 0.--31. 1. "ERR_ADD,Error address field" line.long 0x68 "SYS_RAM_CERR_STS13,System RAM correctable error reporting table status register" bitfld.long 0x68 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x68 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x68 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x68 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x6C "SYS_RAM_CERR_ADDR13,System RAM correctable error reporting table address register" hexmask.long 0x6C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x70 "SYS_RAM_CERR_STS14,System RAM correctable error reporting table status register" bitfld.long 0x70 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x70 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x70 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x70 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x74 "SYS_RAM_CERR_ADDR14,System RAM correctable error reporting table address register" hexmask.long 0x74 0.--31. 1. "ERR_ADD,Error address field" line.long 0x78 "SYS_RAM_CERR_STS15,System RAM correctable error reporting table status register" bitfld.long 0x78 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x78 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x78 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x78 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x7C "SYS_RAM_CERR_ADDR15,System RAM correctable error reporting table address register" hexmask.long 0x7C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x80 "SYS_RAM_CERR_STS16,System RAM correctable error reporting table status register" bitfld.long 0x80 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x80 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x80 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x80 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x84 "SYS_RAM_CERR_ADDR16,System RAM correctable error reporting table address register" hexmask.long 0x84 0.--31. 1. "ERR_ADD,Error address field" line.long 0x88 "SYS_RAM_CERR_STS17,System RAM correctable error reporting table status register" bitfld.long 0x88 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x88 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x88 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x88 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x8C "SYS_RAM_CERR_ADDR17,System RAM correctable error reporting table address register" hexmask.long 0x8C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x90 "SYS_RAM_CERR_STS18,System RAM correctable error reporting table status register" bitfld.long 0x90 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x90 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x90 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x90 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x94 "SYS_RAM_CERR_ADDR18,System RAM correctable error reporting table address register" hexmask.long 0x94 0.--31. 1. "ERR_ADD,Error address field" line.long 0x98 "SYS_RAM_CERR_STS19,System RAM correctable error reporting table status register" bitfld.long 0x98 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x98 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x98 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x98 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x9C "SYS_RAM_CERR_ADDR19,System RAM correctable error reporting table address register" hexmask.long 0x9C 0.--31. 1. "ERR_ADD,Error address field" line.long 0xA0 "SYS_RAM_CERR_STS20,System RAM correctable error reporting table status register" bitfld.long 0xA0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xA0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xA0 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0xA0 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0xA4 "SYS_RAM_CERR_ADDR20,System RAM correctable error reporting table address register" hexmask.long 0xA4 0.--31. 1. "ERR_ADD,Error address field" line.long 0xA8 "SYS_RAM_CERR_STS21,System RAM correctable error reporting table status register" bitfld.long 0xA8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xA8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xA8 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0xA8 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0xAC "SYS_RAM_CERR_ADDR21,System RAM correctable error reporting table address register" hexmask.long 0xAC 0.--31. 1. "ERR_ADD,Error address field" line.long 0xB0 "SYS_RAM_CERR_STS22,System RAM correctable error reporting table status register" bitfld.long 0xB0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xB0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xB0 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0xB0 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0xB4 "SYS_RAM_CERR_ADDR22,System RAM correctable error reporting table address register" hexmask.long 0xB4 0.--31. 1. "ERR_ADD,Error address field" line.long 0xB8 "SYS_RAM_CERR_STS23,System RAM correctable error reporting table status register" bitfld.long 0xB8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xB8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xB8 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0xB8 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0xBC "SYS_RAM_CERR_ADDR23,System RAM correctable error reporting table address register" hexmask.long 0xBC 0.--31. 1. "ERR_ADD,Error address field" line.long 0xC0 "SYS_RAM_CERR_STS24,System RAM correctable error reporting table status register" bitfld.long 0xC0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xC0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xC0 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0xC0 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0xC4 "SYS_RAM_CERR_ADDR24,System RAM correctable error reporting table address register" hexmask.long 0xC4 0.--31. 1. "ERR_ADD,Error address field" line.long 0xC8 "SYS_RAM_CERR_STS25,System RAM correctable error reporting table status register" bitfld.long 0xC8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xC8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xC8 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0xC8 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0xCC "SYS_RAM_CERR_ADDR25,System RAM correctable error reporting table address register" hexmask.long 0xCC 0.--31. 1. "ERR_ADD,Error address field" line.long 0xD0 "SYS_RAM_CERR_STS26,System RAM correctable error reporting table status register" bitfld.long 0xD0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xD0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xD0 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0xD0 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0xD4 "SYS_RAM_CERR_ADDR26,System RAM correctable error reporting table address register" hexmask.long 0xD4 0.--31. 1. "ERR_ADD,Error address field" line.long 0xD8 "SYS_RAM_CERR_STS27,System RAM correctable error reporting table status register" bitfld.long 0xD8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xD8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xD8 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0xD8 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0xDC "SYS_RAM_CERR_ADDR27,System RAM correctable error reporting table address register" hexmask.long 0xDC 0.--31. 1. "ERR_ADD,Error address field" line.long 0xE0 "SYS_RAM_CERR_STS28,System RAM correctable error reporting table status register" bitfld.long 0xE0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xE0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xE0 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0xE0 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0xE4 "SYS_RAM_CERR_ADDR28,System RAM correctable error reporting table address register" hexmask.long 0xE4 0.--31. 1. "ERR_ADD,Error address field" line.long 0xE8 "SYS_RAM_CERR_STS29,System RAM correctable error reporting table status register" bitfld.long 0xE8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xE8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xE8 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0xE8 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0xEC "SYS_RAM_CERR_ADDR29,System RAM correctable error reporting table address register" hexmask.long 0xEC 0.--31. 1. "ERR_ADD,Error address field" line.long 0xF0 "SYS_RAM_CERR_STS30,System RAM correctable error reporting table status register" bitfld.long 0xF0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xF0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xF0 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0xF0 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0xF4 "SYS_RAM_CERR_ADDR30,System RAM correctable error reporting table address register" hexmask.long 0xF4 0.--31. 1. "ERR_ADD,Error address field" line.long 0xF8 "SYS_RAM_CERR_STS31,System RAM correctable error reporting table status register" bitfld.long 0xF8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xF8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xF8 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0xF8 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0xFC "SYS_RAM_CERR_ADDR31,System RAM correctable error reporting table address register" hexmask.long 0xFC 0.--31. 1. "ERR_ADD,Error address field" rgroup.long 0x120++0x3 line.long 0x0 "SYS_RAM_CERR_TBL_FILL_STAT,System RAM correctable error reporting table fill status register" hexmask.long.byte 0x0 0.--7. 1. "CERR_TBL_FILL_VAL,This value indicates the number of valid entries in the correctable table for System RAM" group.long 0x430++0x7F line.long 0x0 "SYS_RAM_UNCERR_STS0,System RAM uncorrectable error reporting table status register" bitfld.long 0x0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x4 "SYS_RAM_UNCERR_ADDR0,System RAM uncorrectable error reporting table address register" hexmask.long 0x4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x8 "SYS_RAM_UNCERR_STS1,System RAM uncorrectable error reporting table status register" bitfld.long 0x8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0xC "SYS_RAM_UNCERR_ADDR1,System RAM uncorrectable error reporting table address register" hexmask.long 0xC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x10 "SYS_RAM_UNCERR_STS2,System RAM uncorrectable error reporting table status register" bitfld.long 0x10 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x14 "SYS_RAM_UNCERR_ADDR2,System RAM uncorrectable error reporting table address register" hexmask.long 0x14 0.--31. 1. "ERR_ADD,Error address field" line.long 0x18 "SYS_RAM_UNCERR_STS3,System RAM uncorrectable error reporting table status register" bitfld.long 0x18 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x1C "SYS_RAM_UNCERR_ADDR3,System RAM uncorrectable error reporting table address register" hexmask.long 0x1C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x20 "SYS_RAM_UNCERR_STS4,System RAM uncorrectable error reporting table status register" bitfld.long 0x20 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x24 "SYS_RAM_UNCERR_ADDR4,System RAM uncorrectable error reporting table address register" hexmask.long 0x24 0.--31. 1. "ERR_ADD,Error address field" line.long 0x28 "SYS_RAM_UNCERR_STS5,System RAM uncorrectable error reporting table status register" bitfld.long 0x28 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x2C "SYS_RAM_UNCERR_ADDR5,System RAM uncorrectable error reporting table address register" hexmask.long 0x2C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x30 "SYS_RAM_UNCERR_STS6,System RAM uncorrectable error reporting table status register" bitfld.long 0x30 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x34 "SYS_RAM_UNCERR_ADDR6,System RAM uncorrectable error reporting table address register" hexmask.long 0x34 0.--31. 1. "ERR_ADD,Error address field" line.long 0x38 "SYS_RAM_UNCERR_STS7,System RAM uncorrectable error reporting table status register" bitfld.long 0x38 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x3C "SYS_RAM_UNCERR_ADDR7,System RAM uncorrectable error reporting table address register" hexmask.long 0x3C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x40 "SYS_RAM_UNCERR_STS8,System RAM uncorrectable error reporting table status register" bitfld.long 0x40 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x44 "SYS_RAM_UNCERR_ADDR8,System RAM uncorrectable error reporting table address register" hexmask.long 0x44 0.--31. 1. "ERR_ADD,Error address field" line.long 0x48 "SYS_RAM_UNCERR_STS9,System RAM uncorrectable error reporting table status register" bitfld.long 0x48 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x4C "SYS_RAM_UNCERR_ADDR9,System RAM uncorrectable error reporting table address register" hexmask.long 0x4C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x50 "SYS_RAM_UNCERR_STS10,System RAM uncorrectable error reporting table status register" bitfld.long 0x50 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x54 "SYS_RAM_UNCERR_ADDR10,System RAM uncorrectable error reporting table address register" hexmask.long 0x54 0.--31. 1. "ERR_ADD,Error address field" line.long 0x58 "SYS_RAM_UNCERR_STS11,System RAM uncorrectable error reporting table status register" bitfld.long 0x58 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x5C "SYS_RAM_UNCERR_ADDR11,System RAM uncorrectable error reporting table address register" hexmask.long 0x5C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x60 "SYS_RAM_UNCERR_STS12,System RAM uncorrectable error reporting table status register" bitfld.long 0x60 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x64 "SYS_RAM_UNCERR_ADDR12,System RAM uncorrectable error reporting table address register" hexmask.long 0x64 0.--31. 1. "ERR_ADD,Error address field" line.long 0x68 "SYS_RAM_UNCERR_STS13,System RAM uncorrectable error reporting table status register" bitfld.long 0x68 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x6C "SYS_RAM_UNCERR_ADDR13,System RAM uncorrectable error reporting table address register" hexmask.long 0x6C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x70 "SYS_RAM_UNCERR_STS14,System RAM uncorrectable error reporting table status register" bitfld.long 0x70 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x74 "SYS_RAM_UNCERR_ADDR14,System RAM uncorrectable error reporting table address register" hexmask.long 0x74 0.--31. 1. "ERR_ADD,Error address field" line.long 0x78 "SYS_RAM_UNCERR_STS15,System RAM uncorrectable error reporting table status register" bitfld.long 0x78 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x7C "SYS_RAM_UNCERR_ADDR15,System RAM uncorrectable error reporting table address register" hexmask.long 0x7C 0.--31. 1. "ERR_ADD,Error address field" rgroup.long 0x4B0++0x3 line.long 0x0 "SYS_RAM_UNCERR_TBL_FILL_STAT,System RAM uncorrectable error reporting table fill status register" hexmask.long.byte 0x0 0.--7. 1. "UNCERR_TBL_FILL_VAL,This value indicates the number of valid entries in the uncorrectable table for System RAM" group.long 0x640++0x7 line.long 0x0 "SYS_RAM_OFLW0,System RAM concurrent overflow registers" hexmask.long 0x0 0.--31. 1. "OFLW,Overflow Bit" line.long 0x4 "SYS_RAM_OFLW1,System RAM concurrent overflow registers" hexmask.long 0x4 0.--31. 1. "OFLW,Overflow Bit" group.long 0x660++0x187 line.long 0x0 "SYS_RAM_ECC_FD_CTRL0,System RAM ECC fault descriptor control registers" bitfld.long 0x0 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x0 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x0 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x0 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x0 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x4 "SYS_RAM_ECC_FD_START0,System RAM ECC fault descriptor start address registers" hexmask.long 0x4 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x8 "SYS_RAM_ECC_FD_END0,System RAM ECC fault descriptor end address registers" hexmask.long 0x8 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xC "SYS_RAM_ECC_FD_CTRL1,System RAM ECC fault descriptor control registers" bitfld.long 0xC 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xC 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xC 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xC 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xC 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x10 "SYS_RAM_ECC_FD_START1,System RAM ECC fault descriptor start address registers" hexmask.long 0x10 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x14 "SYS_RAM_ECC_FD_END1,System RAM ECC fault descriptor end address registers" hexmask.long 0x14 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x18 "SYS_RAM_ECC_FD_CTRL2,System RAM ECC fault descriptor control registers" bitfld.long 0x18 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x18 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x18 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x18 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x18 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x1C "SYS_RAM_ECC_FD_START2,System RAM ECC fault descriptor start address registers" hexmask.long 0x1C 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x20 "SYS_RAM_ECC_FD_END2,System RAM ECC fault descriptor end address registers" hexmask.long 0x20 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x24 "SYS_RAM_ECC_FD_CTRL3,System RAM ECC fault descriptor control registers" bitfld.long 0x24 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x24 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x24 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x24 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x24 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x28 "SYS_RAM_ECC_FD_START3,System RAM ECC fault descriptor start address registers" hexmask.long 0x28 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x2C "SYS_RAM_ECC_FD_END3,System RAM ECC fault descriptor end address registers" hexmask.long 0x2C 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x30 "SYS_RAM_ECC_FD_CTRL4,System RAM ECC fault descriptor control registers" bitfld.long 0x30 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x30 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x30 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x30 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x30 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x34 "SYS_RAM_ECC_FD_START4,System RAM ECC fault descriptor start address registers" hexmask.long 0x34 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x38 "SYS_RAM_ECC_FD_END4,System RAM ECC fault descriptor end address registers" hexmask.long 0x38 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x3C "SYS_RAM_ECC_FD_CTRL5,System RAM ECC fault descriptor control registers" bitfld.long 0x3C 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x3C 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x3C 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x3C 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x3C 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x40 "SYS_RAM_ECC_FD_START5,System RAM ECC fault descriptor start address registers" hexmask.long 0x40 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x44 "SYS_RAM_ECC_FD_END5,System RAM ECC fault descriptor end address registers" hexmask.long 0x44 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x48 "SYS_RAM_ECC_FD_CTRL6,System RAM ECC fault descriptor control registers" bitfld.long 0x48 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x48 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x48 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x48 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x48 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x4C "SYS_RAM_ECC_FD_START6,System RAM ECC fault descriptor start address registers" hexmask.long 0x4C 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x50 "SYS_RAM_ECC_FD_END6,System RAM ECC fault descriptor end address registers" hexmask.long 0x50 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x54 "SYS_RAM_ECC_FD_CTRL7,System RAM ECC fault descriptor control registers" bitfld.long 0x54 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x54 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x54 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x54 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x54 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x58 "SYS_RAM_ECC_FD_START7,System RAM ECC fault descriptor start address registers" hexmask.long 0x58 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x5C "SYS_RAM_ECC_FD_END7,System RAM ECC fault descriptor end address registers" hexmask.long 0x5C 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x60 "SYS_RAM_ECC_FD_CTRL8,System RAM ECC fault descriptor control registers" bitfld.long 0x60 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x60 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x60 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x60 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x60 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x64 "SYS_RAM_ECC_FD_START8,System RAM ECC fault descriptor start address registers" hexmask.long 0x64 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x68 "SYS_RAM_ECC_FD_END8,System RAM ECC fault descriptor end address registers" hexmask.long 0x68 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x6C "SYS_RAM_ECC_FD_CTRL9,System RAM ECC fault descriptor control registers" bitfld.long 0x6C 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x6C 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x6C 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x6C 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x6C 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x70 "SYS_RAM_ECC_FD_START9,System RAM ECC fault descriptor start address registers" hexmask.long 0x70 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x74 "SYS_RAM_ECC_FD_END9,System RAM ECC fault descriptor end address registers" hexmask.long 0x74 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x78 "SYS_RAM_ECC_FD_CTRL10,System RAM ECC fault descriptor control registers" bitfld.long 0x78 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x78 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x78 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x78 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x78 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x7C "SYS_RAM_ECC_FD_START10,System RAM ECC fault descriptor start address registers" hexmask.long 0x7C 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x80 "SYS_RAM_ECC_FD_END10,System RAM ECC fault descriptor end address registers" hexmask.long 0x80 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x84 "SYS_RAM_ECC_FD_CTRL11,System RAM ECC fault descriptor control registers" bitfld.long 0x84 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x84 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x84 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x84 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x84 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x88 "SYS_RAM_ECC_FD_START11,System RAM ECC fault descriptor start address registers" hexmask.long 0x88 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x8C "SYS_RAM_ECC_FD_END11,System RAM ECC fault descriptor end address registers" hexmask.long 0x8C 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x90 "SYS_RAM_ECC_FD_CTRL12,System RAM ECC fault descriptor control registers" bitfld.long 0x90 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x90 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x90 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x90 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x90 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x94 "SYS_RAM_ECC_FD_START12,System RAM ECC fault descriptor start address registers" hexmask.long 0x94 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x98 "SYS_RAM_ECC_FD_END12,System RAM ECC fault descriptor end address registers" hexmask.long 0x98 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x9C "SYS_RAM_ECC_FD_CTRL13,System RAM ECC fault descriptor control registers" bitfld.long 0x9C 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x9C 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x9C 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x9C 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x9C 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xA0 "SYS_RAM_ECC_FD_START13,System RAM ECC fault descriptor start address registers" hexmask.long 0xA0 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xA4 "SYS_RAM_ECC_FD_END13,System RAM ECC fault descriptor end address registers" hexmask.long 0xA4 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xA8 "SYS_RAM_ECC_FD_CTRL14,System RAM ECC fault descriptor control registers" bitfld.long 0xA8 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xA8 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xA8 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xA8 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xA8 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xAC "SYS_RAM_ECC_FD_START14,System RAM ECC fault descriptor start address registers" hexmask.long 0xAC 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xB0 "SYS_RAM_ECC_FD_END14,System RAM ECC fault descriptor end address registers" hexmask.long 0xB0 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xB4 "SYS_RAM_ECC_FD_CTRL15,System RAM ECC fault descriptor control registers" bitfld.long 0xB4 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xB4 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xB4 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xB4 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xB4 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xB8 "SYS_RAM_ECC_FD_START15,System RAM ECC fault descriptor start address registers" hexmask.long 0xB8 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xBC "SYS_RAM_ECC_FD_END15,System RAM ECC fault descriptor end address registers" hexmask.long 0xBC 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xC0 "SYS_RAM_ECC_FD_CTRL16,System RAM ECC fault descriptor control registers" bitfld.long 0xC0 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xC0 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xC0 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xC0 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xC0 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xC4 "SYS_RAM_ECC_FD_START16,System RAM ECC fault descriptor start address registers" hexmask.long 0xC4 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xC8 "SYS_RAM_ECC_FD_END16,System RAM ECC fault descriptor end address registers" hexmask.long 0xC8 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xCC "SYS_RAM_ECC_FD_CTRL17,System RAM ECC fault descriptor control registers" bitfld.long 0xCC 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xCC 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xCC 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xCC 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xCC 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xD0 "SYS_RAM_ECC_FD_START17,System RAM ECC fault descriptor start address registers" hexmask.long 0xD0 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xD4 "SYS_RAM_ECC_FD_END17,System RAM ECC fault descriptor end address registers" hexmask.long 0xD4 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xD8 "SYS_RAM_ECC_FD_CTRL18,System RAM ECC fault descriptor control registers" bitfld.long 0xD8 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xD8 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xD8 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xD8 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xD8 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xDC "SYS_RAM_ECC_FD_START18,System RAM ECC fault descriptor start address registers" hexmask.long 0xDC 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xE0 "SYS_RAM_ECC_FD_END18,System RAM ECC fault descriptor end address registers" hexmask.long 0xE0 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xE4 "SYS_RAM_ECC_FD_CTRL19,System RAM ECC fault descriptor control registers" bitfld.long 0xE4 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xE4 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xE4 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xE4 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xE4 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xE8 "SYS_RAM_ECC_FD_START19,System RAM ECC fault descriptor start address registers" hexmask.long 0xE8 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xEC "SYS_RAM_ECC_FD_END19,System RAM ECC fault descriptor end address registers" hexmask.long 0xEC 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xF0 "SYS_RAM_ECC_FD_CTRL20,System RAM ECC fault descriptor control registers" bitfld.long 0xF0 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xF0 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xF0 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xF0 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xF0 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xF4 "SYS_RAM_ECC_FD_START20,System RAM ECC fault descriptor start address registers" hexmask.long 0xF4 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xF8 "SYS_RAM_ECC_FD_END20,System RAM ECC fault descriptor end address registers" hexmask.long 0xF8 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xFC "SYS_RAM_ECC_FD_CTRL21,System RAM ECC fault descriptor control registers" bitfld.long 0xFC 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xFC 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xFC 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xFC 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xFC 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x100 "SYS_RAM_ECC_FD_START21,System RAM ECC fault descriptor start address registers" hexmask.long 0x100 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x104 "SYS_RAM_ECC_FD_END21,System RAM ECC fault descriptor end address registers" hexmask.long 0x104 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x108 "SYS_RAM_ECC_FD_CTRL22,System RAM ECC fault descriptor control registers" bitfld.long 0x108 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x108 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x108 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x108 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x108 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x10C "SYS_RAM_ECC_FD_START22,System RAM ECC fault descriptor start address registers" hexmask.long 0x10C 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x110 "SYS_RAM_ECC_FD_END22,System RAM ECC fault descriptor end address registers" hexmask.long 0x110 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x114 "SYS_RAM_ECC_FD_CTRL23,System RAM ECC fault descriptor control registers" bitfld.long 0x114 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x114 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x114 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x114 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x114 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x118 "SYS_RAM_ECC_FD_START23,System RAM ECC fault descriptor start address registers" hexmask.long 0x118 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x11C "SYS_RAM_ECC_FD_END23,System RAM ECC fault descriptor end address registers" hexmask.long 0x11C 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x120 "SYS_RAM_ECC_FD_CTRL24,System RAM ECC fault descriptor control registers" bitfld.long 0x120 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x120 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x120 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x120 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x120 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x124 "SYS_RAM_ECC_FD_START24,System RAM ECC fault descriptor start address registers" hexmask.long 0x124 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x128 "SYS_RAM_ECC_FD_END24,System RAM ECC fault descriptor end address registers" hexmask.long 0x128 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x12C "SYS_RAM_ECC_FD_CTRL25,System RAM ECC fault descriptor control registers" bitfld.long 0x12C 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x12C 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x12C 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x12C 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x12C 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x130 "SYS_RAM_ECC_FD_START25,System RAM ECC fault descriptor start address registers" hexmask.long 0x130 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x134 "SYS_RAM_ECC_FD_END25,System RAM ECC fault descriptor end address registers" hexmask.long 0x134 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x138 "SYS_RAM_ECC_FD_CTRL26,System RAM ECC fault descriptor control registers" bitfld.long 0x138 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x138 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x138 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x138 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x138 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x13C "SYS_RAM_ECC_FD_START26,System RAM ECC fault descriptor start address registers" hexmask.long 0x13C 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x140 "SYS_RAM_ECC_FD_END26,System RAM ECC fault descriptor end address registers" hexmask.long 0x140 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x144 "SYS_RAM_ECC_FD_CTRL27,System RAM ECC fault descriptor control registers" bitfld.long 0x144 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x144 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x144 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x144 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x144 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x148 "SYS_RAM_ECC_FD_START27,System RAM ECC fault descriptor start address registers" hexmask.long 0x148 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x14C "SYS_RAM_ECC_FD_END27,System RAM ECC fault descriptor end address registers" hexmask.long 0x14C 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x150 "SYS_RAM_ECC_FD_CTRL28,System RAM ECC fault descriptor control registers" bitfld.long 0x150 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x150 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x150 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x150 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x150 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x154 "SYS_RAM_ECC_FD_START28,System RAM ECC fault descriptor start address registers" hexmask.long 0x154 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x158 "SYS_RAM_ECC_FD_END28,System RAM ECC fault descriptor end address registers" hexmask.long 0x158 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x15C "SYS_RAM_ECC_FD_CTRL29,System RAM ECC fault descriptor control registers" bitfld.long 0x15C 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x15C 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x15C 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x15C 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x15C 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x160 "SYS_RAM_ECC_FD_START29,System RAM ECC fault descriptor start address registers" hexmask.long 0x160 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x164 "SYS_RAM_ECC_FD_END29,System RAM ECC fault descriptor end address registers" hexmask.long 0x164 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x168 "SYS_RAM_ECC_FD_CTRL30,System RAM ECC fault descriptor control registers" bitfld.long 0x168 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x168 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x168 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x168 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x168 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x16C "SYS_RAM_ECC_FD_START30,System RAM ECC fault descriptor start address registers" hexmask.long 0x16C 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x170 "SYS_RAM_ECC_FD_END30,System RAM ECC fault descriptor end address registers" hexmask.long 0x170 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x174 "SYS_RAM_ECC_FD_CTRL31,System RAM ECC fault descriptor control registers" bitfld.long 0x174 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x174 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x174 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x174 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x174 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x178 "SYS_RAM_ECC_FD_START31,System RAM ECC fault descriptor start address registers" hexmask.long 0x178 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x17C "SYS_RAM_ECC_FD_END31,System RAM ECC fault descriptor end address registers" hexmask.long 0x17C 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x180 "SYS_RAM_T320,System RAM address extension registers" bitfld.long 0x180 31. "T31,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 30. "T30,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 29. "T29,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 28. "T28,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 27. "T27,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 26. "T26,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 25. "T25,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 24. "T24,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 23. "T23,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 22. "T22,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 21. "T21,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 20. "T20,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 19. "T19,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 18. "T18,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 17. "T17,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 16. "T16,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 15. "T15,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 14. "T14,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 13. "T13,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 12. "T12,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 11. "T11,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 10. "T10,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 9. "T9,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 8. "T8,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 7. "T7,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 6. "T6,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 5. "T5,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 4. "T4,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 3. "T3,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 2. "T2,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 1. "T1,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 0. "T0,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" line.long 0x184 "SYS_RAM_T321,System RAM address extension registers" bitfld.long 0x184 31. "T31,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 30. "T30,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 29. "T29,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 28. "T28,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 27. "T27,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 26. "T26,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 25. "T25,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 24. "T24,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 23. "T23,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 22. "T22,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 21. "T21,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 20. "T20,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 19. "T19,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 18. "T18,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 17. "T17,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 16. "T16,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 15. "T15,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 14. "T14,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 13. "T13,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 12. "T12,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 11. "T11,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 10. "T10,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 9. "T9,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 8. "T8,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 7. "T7,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 6. "T6,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 5. "T5,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 4. "T4,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 3. "T3,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 2. "T2,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 1. "T1,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 0. "T0,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" group.long 0xB00++0x7F line.long 0x0 "PERIPH_RAM_CERR_STS0,Peripheral RAM correctable error reporting table status register" bitfld.long 0x0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x0 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x0 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x4 "PERIPH_RAM_CERR_ADDR0,Peripheral RAM correctable error reporting table address register" hexmask.long 0x4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x8 "PERIPH_RAM_CERR_STS1,Peripheral RAM correctable error reporting table status register" bitfld.long 0x8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x8 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x8 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0xC "PERIPH_RAM_CERR_ADDR1,Peripheral RAM correctable error reporting table address register" hexmask.long 0xC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x10 "PERIPH_RAM_CERR_STS2,Peripheral RAM correctable error reporting table status register" bitfld.long 0x10 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x10 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x10 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x10 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x14 "PERIPH_RAM_CERR_ADDR2,Peripheral RAM correctable error reporting table address register" hexmask.long 0x14 0.--31. 1. "ERR_ADD,Error address field" line.long 0x18 "PERIPH_RAM_CERR_STS3,Peripheral RAM correctable error reporting table status register" bitfld.long 0x18 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x18 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x18 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x18 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x1C "PERIPH_RAM_CERR_ADDR3,Peripheral RAM correctable error reporting table address register" hexmask.long 0x1C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x20 "PERIPH_RAM_CERR_STS4,Peripheral RAM correctable error reporting table status register" bitfld.long 0x20 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x20 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x20 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x20 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x24 "PERIPH_RAM_CERR_ADDR4,Peripheral RAM correctable error reporting table address register" hexmask.long 0x24 0.--31. 1. "ERR_ADD,Error address field" line.long 0x28 "PERIPH_RAM_CERR_STS5,Peripheral RAM correctable error reporting table status register" bitfld.long 0x28 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x28 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x28 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x28 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x2C "PERIPH_RAM_CERR_ADDR5,Peripheral RAM correctable error reporting table address register" hexmask.long 0x2C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x30 "PERIPH_RAM_CERR_STS6,Peripheral RAM correctable error reporting table status register" bitfld.long 0x30 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x30 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x30 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x30 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x34 "PERIPH_RAM_CERR_ADDR6,Peripheral RAM correctable error reporting table address register" hexmask.long 0x34 0.--31. 1. "ERR_ADD,Error address field" line.long 0x38 "PERIPH_RAM_CERR_STS7,Peripheral RAM correctable error reporting table status register" bitfld.long 0x38 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x38 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x38 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x38 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x3C "PERIPH_RAM_CERR_ADDR7,Peripheral RAM correctable error reporting table address register" hexmask.long 0x3C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x40 "PERIPH_RAM_CERR_STS8,Peripheral RAM correctable error reporting table status register" bitfld.long 0x40 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x40 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x40 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x40 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x44 "PERIPH_RAM_CERR_ADDR8,Peripheral RAM correctable error reporting table address register" hexmask.long 0x44 0.--31. 1. "ERR_ADD,Error address field" line.long 0x48 "PERIPH_RAM_CERR_STS9,Peripheral RAM correctable error reporting table status register" bitfld.long 0x48 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x48 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x48 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x48 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x4C "PERIPH_RAM_CERR_ADDR9,Peripheral RAM correctable error reporting table address register" hexmask.long 0x4C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x50 "PERIPH_RAM_CERR_STS10,Peripheral RAM correctable error reporting table status register" bitfld.long 0x50 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x50 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x50 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x50 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x54 "PERIPH_RAM_CERR_ADDR10,Peripheral RAM correctable error reporting table address register" hexmask.long 0x54 0.--31. 1. "ERR_ADD,Error address field" line.long 0x58 "PERIPH_RAM_CERR_STS11,Peripheral RAM correctable error reporting table status register" bitfld.long 0x58 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x58 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x58 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x58 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x5C "PERIPH_RAM_CERR_ADDR11,Peripheral RAM correctable error reporting table address register" hexmask.long 0x5C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x60 "PERIPH_RAM_CERR_STS12,Peripheral RAM correctable error reporting table status register" bitfld.long 0x60 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x60 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x60 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x60 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x64 "PERIPH_RAM_CERR_ADDR12,Peripheral RAM correctable error reporting table address register" hexmask.long 0x64 0.--31. 1. "ERR_ADD,Error address field" line.long 0x68 "PERIPH_RAM_CERR_STS13,Peripheral RAM correctable error reporting table status register" bitfld.long 0x68 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x68 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x68 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x68 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x6C "PERIPH_RAM_CERR_ADDR13,Peripheral RAM correctable error reporting table address register" hexmask.long 0x6C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x70 "PERIPH_RAM_CERR_STS14,Peripheral RAM correctable error reporting table status register" bitfld.long 0x70 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x70 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x70 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x70 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x74 "PERIPH_RAM_CERR_ADDR14,Peripheral RAM correctable error reporting table address register" hexmask.long 0x74 0.--31. 1. "ERR_ADD,Error address field" line.long 0x78 "PERIPH_RAM_CERR_STS15,Peripheral RAM correctable error reporting table status register" bitfld.long 0x78 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x78 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x78 16.--23. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.byte 0x78 0.--7. 1. "BAD_BIT,Bad bit field" line.long 0x7C "PERIPH_RAM_CERR_ADDR15,Peripheral RAM correctable error reporting table address register" hexmask.long 0x7C 0.--31. 1. "ERR_ADD,Error address field" rgroup.long 0xB80++0x3 line.long 0x0 "PERIPH_RAM_CERR_TBL_FILL_STAT,Peripheral RAM correctable error reporting table fill status register" hexmask.long.byte 0x0 0.--7. 1. "CERR_TBL_FILL_VAL,This value indicates the number of valid entries in the correctable table for Peripheral RAM." group.long 0xF10++0x7F line.long 0x0 "PERIPH_RAM_UNCERR_STS0,Peripheral RAM uncorrectable error reporting table status register" bitfld.long 0x0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x4 "PERIPH_RAM_UNCERR_ADDR0,Peripheral RAM uncorrectable error reporting table address register" hexmask.long 0x4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x8 "PERIPH_RAM_UNCERR_STS1,Peripheral RAM uncorrectable error reporting table status register" bitfld.long 0x8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0xC "PERIPH_RAM_UNCERR_ADDR1,Peripheral RAM uncorrectable error reporting table address register" hexmask.long 0xC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x10 "PERIPH_RAM_UNCERR_STS2,Peripheral RAM uncorrectable error reporting table status register" bitfld.long 0x10 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x14 "PERIPH_RAM_UNCERR_ADDR2,Peripheral RAM uncorrectable error reporting table address register" hexmask.long 0x14 0.--31. 1. "ERR_ADD,Error address field" line.long 0x18 "PERIPH_RAM_UNCERR_STS3,Peripheral RAM uncorrectable error reporting table status register" bitfld.long 0x18 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x1C "PERIPH_RAM_UNCERR_ADDR3,Peripheral RAM uncorrectable error reporting table address register" hexmask.long 0x1C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x20 "PERIPH_RAM_UNCERR_STS4,Peripheral RAM uncorrectable error reporting table status register" bitfld.long 0x20 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x24 "PERIPH_RAM_UNCERR_ADDR4,Peripheral RAM uncorrectable error reporting table address register" hexmask.long 0x24 0.--31. 1. "ERR_ADD,Error address field" line.long 0x28 "PERIPH_RAM_UNCERR_STS5,Peripheral RAM uncorrectable error reporting table status register" bitfld.long 0x28 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x2C "PERIPH_RAM_UNCERR_ADDR5,Peripheral RAM uncorrectable error reporting table address register" hexmask.long 0x2C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x30 "PERIPH_RAM_UNCERR_STS6,Peripheral RAM uncorrectable error reporting table status register" bitfld.long 0x30 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x34 "PERIPH_RAM_UNCERR_ADDR6,Peripheral RAM uncorrectable error reporting table address register" hexmask.long 0x34 0.--31. 1. "ERR_ADD,Error address field" line.long 0x38 "PERIPH_RAM_UNCERR_STS7,Peripheral RAM uncorrectable error reporting table status register" bitfld.long 0x38 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x3C "PERIPH_RAM_UNCERR_ADDR7,Peripheral RAM uncorrectable error reporting table address register" hexmask.long 0x3C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x40 "PERIPH_RAM_UNCERR_STS8,Peripheral RAM uncorrectable error reporting table status register" bitfld.long 0x40 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x44 "PERIPH_RAM_UNCERR_ADDR8,Peripheral RAM uncorrectable error reporting table address register" hexmask.long 0x44 0.--31. 1. "ERR_ADD,Error address field" line.long 0x48 "PERIPH_RAM_UNCERR_STS9,Peripheral RAM uncorrectable error reporting table status register" bitfld.long 0x48 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x4C "PERIPH_RAM_UNCERR_ADDR9,Peripheral RAM uncorrectable error reporting table address register" hexmask.long 0x4C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x50 "PERIPH_RAM_UNCERR_STS10,Peripheral RAM uncorrectable error reporting table status register" bitfld.long 0x50 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x54 "PERIPH_RAM_UNCERR_ADDR10,Peripheral RAM uncorrectable error reporting table address register" hexmask.long 0x54 0.--31. 1. "ERR_ADD,Error address field" line.long 0x58 "PERIPH_RAM_UNCERR_STS11,Peripheral RAM uncorrectable error reporting table status register" bitfld.long 0x58 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x5C "PERIPH_RAM_UNCERR_ADDR11,Peripheral RAM uncorrectable error reporting table address register" hexmask.long 0x5C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x60 "PERIPH_RAM_UNCERR_STS12,Peripheral RAM uncorrectable error reporting table status register" bitfld.long 0x60 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x64 "PERIPH_RAM_UNCERR_ADDR12,Peripheral RAM uncorrectable error reporting table address register" hexmask.long 0x64 0.--31. 1. "ERR_ADD,Error address field" line.long 0x68 "PERIPH_RAM_UNCERR_STS13,Peripheral RAM uncorrectable error reporting table status register" bitfld.long 0x68 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x6C "PERIPH_RAM_UNCERR_ADDR13,Peripheral RAM uncorrectable error reporting table address register" hexmask.long 0x6C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x70 "PERIPH_RAM_UNCERR_STS14,Peripheral RAM uncorrectable error reporting table status register" bitfld.long 0x70 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x74 "PERIPH_RAM_UNCERR_ADDR14,Peripheral RAM uncorrectable error reporting table address register" hexmask.long 0x74 0.--31. 1. "ERR_ADD,Error address field" line.long 0x78 "PERIPH_RAM_UNCERR_STS15,Peripheral RAM uncorrectable error reporting table status register" bitfld.long 0x78 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x7C "PERIPH_RAM_UNCERR_ADDR15,Peripheral RAM uncorrectable error reporting table address register" hexmask.long 0x7C 0.--31. 1. "ERR_ADD,Error address field" rgroup.long 0xF90++0x3 line.long 0x0 "PERIPH_RAM_UNCERR_TBL_FILL_STAT,Peripheral RAM uncorrectable error reporting table fill status register" hexmask.long.byte 0x0 0.--7. 1. "UNCERR_TBL_FILL_VAL,This value indicates the number of valid entries in the uncorrectable table for Peripheral RAM." group.long 0x1120++0x7 line.long 0x0 "PERIPH_RAM_OFLW0,Peripheral RAM concurrent overflow registers" hexmask.long 0x0 0.--31. 1. "OFLW,Overflow Bit" line.long 0x4 "PERIPH_RAM_OFLW1,Peripheral RAM concurrent overflow registers" hexmask.long 0x4 0.--31. 1. "OFLW,Overflow Bit" group.long 0x1140++0x187 line.long 0x0 "PERIPH_RAM_ECC_FD_CTRL0,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x0 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x0 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x0 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x0 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x0 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x4 "PERIPH_RAM_ECC_FD_START0,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x4 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x8 "PERIPH_RAM_ECC_FD_END0,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x8 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xC "PERIPH_RAM_ECC_FD_CTRL1,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0xC 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xC 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xC 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xC 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xC 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x10 "PERIPH_RAM_ECC_FD_START1,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x10 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x14 "PERIPH_RAM_ECC_FD_END1,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x14 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x18 "PERIPH_RAM_ECC_FD_CTRL2,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x18 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x18 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x18 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x18 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x18 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x1C "PERIPH_RAM_ECC_FD_START2,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x1C 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x20 "PERIPH_RAM_ECC_FD_END2,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x20 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x24 "PERIPH_RAM_ECC_FD_CTRL3,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x24 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x24 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x24 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x24 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x24 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x28 "PERIPH_RAM_ECC_FD_START3,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x28 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x2C "PERIPH_RAM_ECC_FD_END3,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x2C 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x30 "PERIPH_RAM_ECC_FD_CTRL4,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x30 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x30 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x30 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x30 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x30 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x34 "PERIPH_RAM_ECC_FD_START4,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x34 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x38 "PERIPH_RAM_ECC_FD_END4,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x38 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x3C "PERIPH_RAM_ECC_FD_CTRL5,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x3C 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x3C 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x3C 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x3C 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x3C 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x40 "PERIPH_RAM_ECC_FD_START5,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x40 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x44 "PERIPH_RAM_ECC_FD_END5,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x44 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x48 "PERIPH_RAM_ECC_FD_CTRL6,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x48 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x48 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x48 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x48 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x48 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x4C "PERIPH_RAM_ECC_FD_START6,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x4C 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x50 "PERIPH_RAM_ECC_FD_END6,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x50 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x54 "PERIPH_RAM_ECC_FD_CTRL7,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x54 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x54 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x54 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x54 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x54 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x58 "PERIPH_RAM_ECC_FD_START7,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x58 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x5C "PERIPH_RAM_ECC_FD_END7,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x5C 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x60 "PERIPH_RAM_ECC_FD_CTRL8,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x60 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x60 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x60 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x60 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x60 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x64 "PERIPH_RAM_ECC_FD_START8,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x64 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x68 "PERIPH_RAM_ECC_FD_END8,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x68 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x6C "PERIPH_RAM_ECC_FD_CTRL9,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x6C 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x6C 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x6C 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x6C 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x6C 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x70 "PERIPH_RAM_ECC_FD_START9,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x70 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x74 "PERIPH_RAM_ECC_FD_END9,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x74 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x78 "PERIPH_RAM_ECC_FD_CTRL10,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x78 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x78 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x78 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x78 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x78 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x7C "PERIPH_RAM_ECC_FD_START10,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x7C 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x80 "PERIPH_RAM_ECC_FD_END10,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x80 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x84 "PERIPH_RAM_ECC_FD_CTRL11,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x84 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x84 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x84 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x84 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x84 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x88 "PERIPH_RAM_ECC_FD_START11,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x88 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x8C "PERIPH_RAM_ECC_FD_END11,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x8C 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x90 "PERIPH_RAM_ECC_FD_CTRL12,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x90 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x90 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x90 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x90 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x90 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x94 "PERIPH_RAM_ECC_FD_START12,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x94 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x98 "PERIPH_RAM_ECC_FD_END12,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x98 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x9C "PERIPH_RAM_ECC_FD_CTRL13,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x9C 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x9C 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x9C 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x9C 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x9C 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xA0 "PERIPH_RAM_ECC_FD_START13,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0xA0 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xA4 "PERIPH_RAM_ECC_FD_END13,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0xA4 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xA8 "PERIPH_RAM_ECC_FD_CTRL14,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0xA8 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xA8 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xA8 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xA8 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xA8 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xAC "PERIPH_RAM_ECC_FD_START14,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0xAC 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xB0 "PERIPH_RAM_ECC_FD_END14,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0xB0 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xB4 "PERIPH_RAM_ECC_FD_CTRL15,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0xB4 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xB4 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xB4 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xB4 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xB4 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xB8 "PERIPH_RAM_ECC_FD_START15,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0xB8 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xBC "PERIPH_RAM_ECC_FD_END15,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0xBC 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xC0 "PERIPH_RAM_ECC_FD_CTRL16,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0xC0 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xC0 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xC0 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xC0 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xC0 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xC4 "PERIPH_RAM_ECC_FD_START16,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0xC4 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xC8 "PERIPH_RAM_ECC_FD_END16,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0xC8 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xCC "PERIPH_RAM_ECC_FD_CTRL17,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0xCC 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xCC 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xCC 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xCC 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xCC 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xD0 "PERIPH_RAM_ECC_FD_START17,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0xD0 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xD4 "PERIPH_RAM_ECC_FD_END17,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0xD4 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xD8 "PERIPH_RAM_ECC_FD_CTRL18,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0xD8 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xD8 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xD8 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xD8 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xD8 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xDC "PERIPH_RAM_ECC_FD_START18,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0xDC 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xE0 "PERIPH_RAM_ECC_FD_END18,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0xE0 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xE4 "PERIPH_RAM_ECC_FD_CTRL19,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0xE4 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xE4 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xE4 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xE4 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xE4 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xE8 "PERIPH_RAM_ECC_FD_START19,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0xE8 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xEC "PERIPH_RAM_ECC_FD_END19,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0xEC 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xF0 "PERIPH_RAM_ECC_FD_CTRL20,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0xF0 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xF0 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xF0 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xF0 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xF0 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xF4 "PERIPH_RAM_ECC_FD_START20,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0xF4 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xF8 "PERIPH_RAM_ECC_FD_END20,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0xF8 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xFC "PERIPH_RAM_ECC_FD_CTRL21,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0xFC 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xFC 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xFC 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xFC 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xFC 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x100 "PERIPH_RAM_ECC_FD_START21,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x100 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x104 "PERIPH_RAM_ECC_FD_END21,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x104 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x108 "PERIPH_RAM_ECC_FD_CTRL22,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x108 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x108 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x108 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x108 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x108 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x10C "PERIPH_RAM_ECC_FD_START22,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x10C 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x110 "PERIPH_RAM_ECC_FD_END22,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x110 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x114 "PERIPH_RAM_ECC_FD_CTRL23,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x114 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x114 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x114 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x114 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x114 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x118 "PERIPH_RAM_ECC_FD_START23,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x118 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x11C "PERIPH_RAM_ECC_FD_END23,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x11C 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x120 "PERIPH_RAM_ECC_FD_CTRL24,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x120 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x120 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x120 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x120 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x120 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x124 "PERIPH_RAM_ECC_FD_START24,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x124 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x128 "PERIPH_RAM_ECC_FD_END24,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x128 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x12C "PERIPH_RAM_ECC_FD_CTRL25,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x12C 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x12C 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x12C 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x12C 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x12C 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x130 "PERIPH_RAM_ECC_FD_START25,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x130 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x134 "PERIPH_RAM_ECC_FD_END25,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x134 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x138 "PERIPH_RAM_ECC_FD_CTRL26,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x138 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x138 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x138 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x138 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x138 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x13C "PERIPH_RAM_ECC_FD_START26,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x13C 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x140 "PERIPH_RAM_ECC_FD_END26,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x140 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x144 "PERIPH_RAM_ECC_FD_CTRL27,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x144 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x144 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x144 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x144 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x144 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x148 "PERIPH_RAM_ECC_FD_START27,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x148 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x14C "PERIPH_RAM_ECC_FD_END27,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x14C 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x150 "PERIPH_RAM_ECC_FD_CTRL28,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x150 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x150 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x150 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x150 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x150 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x154 "PERIPH_RAM_ECC_FD_START28,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x154 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x158 "PERIPH_RAM_ECC_FD_END28,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x158 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x15C "PERIPH_RAM_ECC_FD_CTRL29,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x15C 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x15C 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x15C 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x15C 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x15C 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x160 "PERIPH_RAM_ECC_FD_START29,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x160 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x164 "PERIPH_RAM_ECC_FD_END29,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x164 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x168 "PERIPH_RAM_ECC_FD_CTRL30,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x168 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x168 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x168 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x168 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x168 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x16C "PERIPH_RAM_ECC_FD_START30,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x16C 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x170 "PERIPH_RAM_ECC_FD_END30,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x170 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x174 "PERIPH_RAM_ECC_FD_CTRL31,Peripheral RAM ECC fault descriptor control registers" bitfld.long 0x174 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x174 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x174 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x174 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x174 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x178 "PERIPH_RAM_ECC_FD_START31,Peripheral RAM ECC fault descriptor start address registers" hexmask.long 0x178 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x17C "PERIPH_RAM_ECC_FD_END31,Peripheral RAM ECC fault descriptor end address registers" hexmask.long 0x17C 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x180 "PERIPH_RAM_T320,Peripheral RAM address extension registers" bitfld.long 0x180 31. "T31,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 30. "T30,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 29. "T29,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 28. "T28,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 27. "T27,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 26. "T26,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 25. "T25,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 24. "T24,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 23. "T23,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 22. "T22,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 21. "T21,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 20. "T20,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 19. "T19,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 18. "T18,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 17. "T17,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 16. "T16,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 15. "T15,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 14. "T14,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 13. "T13,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 12. "T12,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 11. "T11,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 10. "T10,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 9. "T9,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 8. "T8,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 7. "T7,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 6. "T6,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 5. "T5,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 4. "T4,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 3. "T3,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 2. "T2,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 1. "T1,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x180 0. "T0,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" line.long 0x184 "PERIPH_RAM_T321,Peripheral RAM address extension registers" bitfld.long 0x184 31. "T31,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 30. "T30,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 29. "T29,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 28. "T28,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 27. "T27,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 26. "T26,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 25. "T25,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 24. "T24,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 23. "T23,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 22. "T22,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 21. "T21,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 20. "T20,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 19. "T19,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 18. "T18,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 17. "T17,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 16. "T16,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 15. "T15,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 14. "T14,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 13. "T13,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 12. "T12,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 11. "T11,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 10. "T10,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 9. "T9,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 8. "T8,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 7. "T7,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 6. "T6,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 5. "T5,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 4. "T4,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 3. "T3,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 2. "T2,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 1. "T1,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x184 0. "T0,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" group.long 0x1600++0x3FF line.long 0x0 "NVM_SB_CERR_STS0,NVM single-bit correctable error reporting table status register" bitfld.long 0x0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x4 "NVM_SB_CERR_ADDR0,NVM single-bit correctable error reporting table address register" hexmask.long 0x4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x8 "NVM_SB_CERR_STS1,NVM single-bit correctable error reporting table status register" bitfld.long 0x8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0xC "NVM_SB_CERR_ADDR1,NVM single-bit correctable error reporting table address register" hexmask.long 0xC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x10 "NVM_SB_CERR_STS2,NVM single-bit correctable error reporting table status register" bitfld.long 0x10 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x10 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x10 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x10 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x14 "NVM_SB_CERR_ADDR2,NVM single-bit correctable error reporting table address register" hexmask.long 0x14 0.--31. 1. "ERR_ADD,Error address field" line.long 0x18 "NVM_SB_CERR_STS3,NVM single-bit correctable error reporting table status register" bitfld.long 0x18 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x18 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x18 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x18 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x1C "NVM_SB_CERR_ADDR3,NVM single-bit correctable error reporting table address register" hexmask.long 0x1C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x20 "NVM_SB_CERR_STS4,NVM single-bit correctable error reporting table status register" bitfld.long 0x20 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x20 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x20 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x20 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x24 "NVM_SB_CERR_ADDR4,NVM single-bit correctable error reporting table address register" hexmask.long 0x24 0.--31. 1. "ERR_ADD,Error address field" line.long 0x28 "NVM_SB_CERR_STS5,NVM single-bit correctable error reporting table status register" bitfld.long 0x28 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x28 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x28 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x28 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x2C "NVM_SB_CERR_ADDR5,NVM single-bit correctable error reporting table address register" hexmask.long 0x2C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x30 "NVM_SB_CERR_STS6,NVM single-bit correctable error reporting table status register" bitfld.long 0x30 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x30 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x30 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x30 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x34 "NVM_SB_CERR_ADDR6,NVM single-bit correctable error reporting table address register" hexmask.long 0x34 0.--31. 1. "ERR_ADD,Error address field" line.long 0x38 "NVM_SB_CERR_STS7,NVM single-bit correctable error reporting table status register" bitfld.long 0x38 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x38 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x38 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x38 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x3C "NVM_SB_CERR_ADDR7,NVM single-bit correctable error reporting table address register" hexmask.long 0x3C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x40 "NVM_SB_CERR_STS8,NVM single-bit correctable error reporting table status register" bitfld.long 0x40 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x40 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x40 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x40 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x44 "NVM_SB_CERR_ADDR8,NVM single-bit correctable error reporting table address register" hexmask.long 0x44 0.--31. 1. "ERR_ADD,Error address field" line.long 0x48 "NVM_SB_CERR_STS9,NVM single-bit correctable error reporting table status register" bitfld.long 0x48 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x48 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x48 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x48 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x4C "NVM_SB_CERR_ADDR9,NVM single-bit correctable error reporting table address register" hexmask.long 0x4C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x50 "NVM_SB_CERR_STS10,NVM single-bit correctable error reporting table status register" bitfld.long 0x50 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x50 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x50 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x50 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x54 "NVM_SB_CERR_ADDR10,NVM single-bit correctable error reporting table address register" hexmask.long 0x54 0.--31. 1. "ERR_ADD,Error address field" line.long 0x58 "NVM_SB_CERR_STS11,NVM single-bit correctable error reporting table status register" bitfld.long 0x58 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x58 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x58 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x58 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x5C "NVM_SB_CERR_ADDR11,NVM single-bit correctable error reporting table address register" hexmask.long 0x5C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x60 "NVM_SB_CERR_STS12,NVM single-bit correctable error reporting table status register" bitfld.long 0x60 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x60 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x60 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x60 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x64 "NVM_SB_CERR_ADDR12,NVM single-bit correctable error reporting table address register" hexmask.long 0x64 0.--31. 1. "ERR_ADD,Error address field" line.long 0x68 "NVM_SB_CERR_STS13,NVM single-bit correctable error reporting table status register" bitfld.long 0x68 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x68 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x68 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x68 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x6C "NVM_SB_CERR_ADDR13,NVM single-bit correctable error reporting table address register" hexmask.long 0x6C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x70 "NVM_SB_CERR_STS14,NVM single-bit correctable error reporting table status register" bitfld.long 0x70 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x70 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x70 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x70 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x74 "NVM_SB_CERR_ADDR14,NVM single-bit correctable error reporting table address register" hexmask.long 0x74 0.--31. 1. "ERR_ADD,Error address field" line.long 0x78 "NVM_SB_CERR_STS15,NVM single-bit correctable error reporting table status register" bitfld.long 0x78 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x78 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x78 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x78 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x7C "NVM_SB_CERR_ADDR15,NVM single-bit correctable error reporting table address register" hexmask.long 0x7C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x80 "NVM_SB_CERR_STS16,NVM single-bit correctable error reporting table status register" bitfld.long 0x80 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x80 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x80 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x80 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x84 "NVM_SB_CERR_ADDR16,NVM single-bit correctable error reporting table address register" hexmask.long 0x84 0.--31. 1. "ERR_ADD,Error address field" line.long 0x88 "NVM_SB_CERR_STS17,NVM single-bit correctable error reporting table status register" bitfld.long 0x88 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x88 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x88 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x88 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x8C "NVM_SB_CERR_ADDR17,NVM single-bit correctable error reporting table address register" hexmask.long 0x8C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x90 "NVM_SB_CERR_STS18,NVM single-bit correctable error reporting table status register" bitfld.long 0x90 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x90 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x90 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x90 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x94 "NVM_SB_CERR_ADDR18,NVM single-bit correctable error reporting table address register" hexmask.long 0x94 0.--31. 1. "ERR_ADD,Error address field" line.long 0x98 "NVM_SB_CERR_STS19,NVM single-bit correctable error reporting table status register" bitfld.long 0x98 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x98 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x98 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x98 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x9C "NVM_SB_CERR_ADDR19,NVM single-bit correctable error reporting table address register" hexmask.long 0x9C 0.--31. 1. "ERR_ADD,Error address field" line.long 0xA0 "NVM_SB_CERR_STS20,NVM single-bit correctable error reporting table status register" bitfld.long 0xA0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xA0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xA0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0xA0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0xA4 "NVM_SB_CERR_ADDR20,NVM single-bit correctable error reporting table address register" hexmask.long 0xA4 0.--31. 1. "ERR_ADD,Error address field" line.long 0xA8 "NVM_SB_CERR_STS21,NVM single-bit correctable error reporting table status register" bitfld.long 0xA8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xA8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xA8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0xA8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0xAC "NVM_SB_CERR_ADDR21,NVM single-bit correctable error reporting table address register" hexmask.long 0xAC 0.--31. 1. "ERR_ADD,Error address field" line.long 0xB0 "NVM_SB_CERR_STS22,NVM single-bit correctable error reporting table status register" bitfld.long 0xB0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xB0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xB0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0xB0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0xB4 "NVM_SB_CERR_ADDR22,NVM single-bit correctable error reporting table address register" hexmask.long 0xB4 0.--31. 1. "ERR_ADD,Error address field" line.long 0xB8 "NVM_SB_CERR_STS23,NVM single-bit correctable error reporting table status register" bitfld.long 0xB8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xB8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xB8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0xB8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0xBC "NVM_SB_CERR_ADDR23,NVM single-bit correctable error reporting table address register" hexmask.long 0xBC 0.--31. 1. "ERR_ADD,Error address field" line.long 0xC0 "NVM_SB_CERR_STS24,NVM single-bit correctable error reporting table status register" bitfld.long 0xC0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xC0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xC0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0xC0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0xC4 "NVM_SB_CERR_ADDR24,NVM single-bit correctable error reporting table address register" hexmask.long 0xC4 0.--31. 1. "ERR_ADD,Error address field" line.long 0xC8 "NVM_SB_CERR_STS25,NVM single-bit correctable error reporting table status register" bitfld.long 0xC8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xC8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xC8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0xC8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0xCC "NVM_SB_CERR_ADDR25,NVM single-bit correctable error reporting table address register" hexmask.long 0xCC 0.--31. 1. "ERR_ADD,Error address field" line.long 0xD0 "NVM_SB_CERR_STS26,NVM single-bit correctable error reporting table status register" bitfld.long 0xD0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xD0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xD0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0xD0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0xD4 "NVM_SB_CERR_ADDR26,NVM single-bit correctable error reporting table address register" hexmask.long 0xD4 0.--31. 1. "ERR_ADD,Error address field" line.long 0xD8 "NVM_SB_CERR_STS27,NVM single-bit correctable error reporting table status register" bitfld.long 0xD8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xD8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xD8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0xD8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0xDC "NVM_SB_CERR_ADDR27,NVM single-bit correctable error reporting table address register" hexmask.long 0xDC 0.--31. 1. "ERR_ADD,Error address field" line.long 0xE0 "NVM_SB_CERR_STS28,NVM single-bit correctable error reporting table status register" bitfld.long 0xE0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xE0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xE0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0xE0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0xE4 "NVM_SB_CERR_ADDR28,NVM single-bit correctable error reporting table address register" hexmask.long 0xE4 0.--31. 1. "ERR_ADD,Error address field" line.long 0xE8 "NVM_SB_CERR_STS29,NVM single-bit correctable error reporting table status register" bitfld.long 0xE8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xE8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xE8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0xE8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0xEC "NVM_SB_CERR_ADDR29,NVM single-bit correctable error reporting table address register" hexmask.long 0xEC 0.--31. 1. "ERR_ADD,Error address field" line.long 0xF0 "NVM_SB_CERR_STS30,NVM single-bit correctable error reporting table status register" bitfld.long 0xF0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xF0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xF0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0xF0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0xF4 "NVM_SB_CERR_ADDR30,NVM single-bit correctable error reporting table address register" hexmask.long 0xF4 0.--31. 1. "ERR_ADD,Error address field" line.long 0xF8 "NVM_SB_CERR_STS31,NVM single-bit correctable error reporting table status register" bitfld.long 0xF8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0xF8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0xF8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0xF8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0xFC "NVM_SB_CERR_ADDR31,NVM single-bit correctable error reporting table address register" hexmask.long 0xFC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x100 "NVM_SB_CERR_STS32,NVM single-bit correctable error reporting table status register" bitfld.long 0x100 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x100 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x100 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x100 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x104 "NVM_SB_CERR_ADDR32,NVM single-bit correctable error reporting table address register" hexmask.long 0x104 0.--31. 1. "ERR_ADD,Error address field" line.long 0x108 "NVM_SB_CERR_STS33,NVM single-bit correctable error reporting table status register" bitfld.long 0x108 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x108 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x108 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x108 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x10C "NVM_SB_CERR_ADDR33,NVM single-bit correctable error reporting table address register" hexmask.long 0x10C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x110 "NVM_SB_CERR_STS34,NVM single-bit correctable error reporting table status register" bitfld.long 0x110 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x110 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x110 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x110 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x114 "NVM_SB_CERR_ADDR34,NVM single-bit correctable error reporting table address register" hexmask.long 0x114 0.--31. 1. "ERR_ADD,Error address field" line.long 0x118 "NVM_SB_CERR_STS35,NVM single-bit correctable error reporting table status register" bitfld.long 0x118 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x118 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x118 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x118 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x11C "NVM_SB_CERR_ADDR35,NVM single-bit correctable error reporting table address register" hexmask.long 0x11C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x120 "NVM_SB_CERR_STS36,NVM single-bit correctable error reporting table status register" bitfld.long 0x120 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x120 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x120 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x120 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x124 "NVM_SB_CERR_ADDR36,NVM single-bit correctable error reporting table address register" hexmask.long 0x124 0.--31. 1. "ERR_ADD,Error address field" line.long 0x128 "NVM_SB_CERR_STS37,NVM single-bit correctable error reporting table status register" bitfld.long 0x128 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x128 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x128 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x128 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x12C "NVM_SB_CERR_ADDR37,NVM single-bit correctable error reporting table address register" hexmask.long 0x12C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x130 "NVM_SB_CERR_STS38,NVM single-bit correctable error reporting table status register" bitfld.long 0x130 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x130 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x130 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x130 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x134 "NVM_SB_CERR_ADDR38,NVM single-bit correctable error reporting table address register" hexmask.long 0x134 0.--31. 1. "ERR_ADD,Error address field" line.long 0x138 "NVM_SB_CERR_STS39,NVM single-bit correctable error reporting table status register" bitfld.long 0x138 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x138 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x138 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x138 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x13C "NVM_SB_CERR_ADDR39,NVM single-bit correctable error reporting table address register" hexmask.long 0x13C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x140 "NVM_SB_CERR_STS40,NVM single-bit correctable error reporting table status register" bitfld.long 0x140 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x140 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x140 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x140 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x144 "NVM_SB_CERR_ADDR40,NVM single-bit correctable error reporting table address register" hexmask.long 0x144 0.--31. 1. "ERR_ADD,Error address field" line.long 0x148 "NVM_SB_CERR_STS41,NVM single-bit correctable error reporting table status register" bitfld.long 0x148 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x148 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x148 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x148 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x14C "NVM_SB_CERR_ADDR41,NVM single-bit correctable error reporting table address register" hexmask.long 0x14C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x150 "NVM_SB_CERR_STS42,NVM single-bit correctable error reporting table status register" bitfld.long 0x150 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x150 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x150 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x150 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x154 "NVM_SB_CERR_ADDR42,NVM single-bit correctable error reporting table address register" hexmask.long 0x154 0.--31. 1. "ERR_ADD,Error address field" line.long 0x158 "NVM_SB_CERR_STS43,NVM single-bit correctable error reporting table status register" bitfld.long 0x158 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x158 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x158 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x158 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x15C "NVM_SB_CERR_ADDR43,NVM single-bit correctable error reporting table address register" hexmask.long 0x15C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x160 "NVM_SB_CERR_STS44,NVM single-bit correctable error reporting table status register" bitfld.long 0x160 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x160 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x160 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x160 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x164 "NVM_SB_CERR_ADDR44,NVM single-bit correctable error reporting table address register" hexmask.long 0x164 0.--31. 1. "ERR_ADD,Error address field" line.long 0x168 "NVM_SB_CERR_STS45,NVM single-bit correctable error reporting table status register" bitfld.long 0x168 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x168 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x168 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x168 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x16C "NVM_SB_CERR_ADDR45,NVM single-bit correctable error reporting table address register" hexmask.long 0x16C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x170 "NVM_SB_CERR_STS46,NVM single-bit correctable error reporting table status register" bitfld.long 0x170 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x170 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x170 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x170 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x174 "NVM_SB_CERR_ADDR46,NVM single-bit correctable error reporting table address register" hexmask.long 0x174 0.--31. 1. "ERR_ADD,Error address field" line.long 0x178 "NVM_SB_CERR_STS47,NVM single-bit correctable error reporting table status register" bitfld.long 0x178 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x178 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x178 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x178 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x17C "NVM_SB_CERR_ADDR47,NVM single-bit correctable error reporting table address register" hexmask.long 0x17C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x180 "NVM_SB_CERR_STS48,NVM single-bit correctable error reporting table status register" bitfld.long 0x180 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x180 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x180 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x180 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x184 "NVM_SB_CERR_ADDR48,NVM single-bit correctable error reporting table address register" hexmask.long 0x184 0.--31. 1. "ERR_ADD,Error address field" line.long 0x188 "NVM_SB_CERR_STS49,NVM single-bit correctable error reporting table status register" bitfld.long 0x188 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x188 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x188 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x188 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x18C "NVM_SB_CERR_ADDR49,NVM single-bit correctable error reporting table address register" hexmask.long 0x18C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x190 "NVM_SB_CERR_STS50,NVM single-bit correctable error reporting table status register" bitfld.long 0x190 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x190 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x190 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x190 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x194 "NVM_SB_CERR_ADDR50,NVM single-bit correctable error reporting table address register" hexmask.long 0x194 0.--31. 1. "ERR_ADD,Error address field" line.long 0x198 "NVM_SB_CERR_STS51,NVM single-bit correctable error reporting table status register" bitfld.long 0x198 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x198 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x198 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x198 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x19C "NVM_SB_CERR_ADDR51,NVM single-bit correctable error reporting table address register" hexmask.long 0x19C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x1A0 "NVM_SB_CERR_STS52,NVM single-bit correctable error reporting table status register" bitfld.long 0x1A0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x1A0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x1A0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x1A0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x1A4 "NVM_SB_CERR_ADDR52,NVM single-bit correctable error reporting table address register" hexmask.long 0x1A4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x1A8 "NVM_SB_CERR_STS53,NVM single-bit correctable error reporting table status register" bitfld.long 0x1A8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x1A8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x1A8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x1A8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x1AC "NVM_SB_CERR_ADDR53,NVM single-bit correctable error reporting table address register" hexmask.long 0x1AC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x1B0 "NVM_SB_CERR_STS54,NVM single-bit correctable error reporting table status register" bitfld.long 0x1B0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x1B0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x1B0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x1B0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x1B4 "NVM_SB_CERR_ADDR54,NVM single-bit correctable error reporting table address register" hexmask.long 0x1B4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x1B8 "NVM_SB_CERR_STS55,NVM single-bit correctable error reporting table status register" bitfld.long 0x1B8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x1B8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x1B8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x1B8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x1BC "NVM_SB_CERR_ADDR55,NVM single-bit correctable error reporting table address register" hexmask.long 0x1BC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x1C0 "NVM_SB_CERR_STS56,NVM single-bit correctable error reporting table status register" bitfld.long 0x1C0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x1C0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x1C0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x1C0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x1C4 "NVM_SB_CERR_ADDR56,NVM single-bit correctable error reporting table address register" hexmask.long 0x1C4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x1C8 "NVM_SB_CERR_STS57,NVM single-bit correctable error reporting table status register" bitfld.long 0x1C8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x1C8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x1C8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x1C8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x1CC "NVM_SB_CERR_ADDR57,NVM single-bit correctable error reporting table address register" hexmask.long 0x1CC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x1D0 "NVM_SB_CERR_STS58,NVM single-bit correctable error reporting table status register" bitfld.long 0x1D0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x1D0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x1D0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x1D0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x1D4 "NVM_SB_CERR_ADDR58,NVM single-bit correctable error reporting table address register" hexmask.long 0x1D4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x1D8 "NVM_SB_CERR_STS59,NVM single-bit correctable error reporting table status register" bitfld.long 0x1D8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x1D8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x1D8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x1D8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x1DC "NVM_SB_CERR_ADDR59,NVM single-bit correctable error reporting table address register" hexmask.long 0x1DC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x1E0 "NVM_SB_CERR_STS60,NVM single-bit correctable error reporting table status register" bitfld.long 0x1E0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x1E0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x1E0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x1E0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x1E4 "NVM_SB_CERR_ADDR60,NVM single-bit correctable error reporting table address register" hexmask.long 0x1E4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x1E8 "NVM_SB_CERR_STS61,NVM single-bit correctable error reporting table status register" bitfld.long 0x1E8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x1E8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x1E8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x1E8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x1EC "NVM_SB_CERR_ADDR61,NVM single-bit correctable error reporting table address register" hexmask.long 0x1EC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x1F0 "NVM_SB_CERR_STS62,NVM single-bit correctable error reporting table status register" bitfld.long 0x1F0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x1F0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x1F0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x1F0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x1F4 "NVM_SB_CERR_ADDR62,NVM single-bit correctable error reporting table address register" hexmask.long 0x1F4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x1F8 "NVM_SB_CERR_STS63,NVM single-bit correctable error reporting table status register" bitfld.long 0x1F8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x1F8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x1F8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x1F8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x1FC "NVM_SB_CERR_ADDR63,NVM single-bit correctable error reporting table address register" hexmask.long 0x1FC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x200 "NVM_SB_CERR_STS64,NVM single-bit correctable error reporting table status register" bitfld.long 0x200 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x200 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x200 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x200 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x204 "NVM_SB_CERR_ADDR64,NVM single-bit correctable error reporting table address register" hexmask.long 0x204 0.--31. 1. "ERR_ADD,Error address field" line.long 0x208 "NVM_SB_CERR_STS65,NVM single-bit correctable error reporting table status register" bitfld.long 0x208 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x208 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x208 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x208 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x20C "NVM_SB_CERR_ADDR65,NVM single-bit correctable error reporting table address register" hexmask.long 0x20C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x210 "NVM_SB_CERR_STS66,NVM single-bit correctable error reporting table status register" bitfld.long 0x210 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x210 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x210 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x210 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x214 "NVM_SB_CERR_ADDR66,NVM single-bit correctable error reporting table address register" hexmask.long 0x214 0.--31. 1. "ERR_ADD,Error address field" line.long 0x218 "NVM_SB_CERR_STS67,NVM single-bit correctable error reporting table status register" bitfld.long 0x218 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x218 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x218 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x218 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x21C "NVM_SB_CERR_ADDR67,NVM single-bit correctable error reporting table address register" hexmask.long 0x21C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x220 "NVM_SB_CERR_STS68,NVM single-bit correctable error reporting table status register" bitfld.long 0x220 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x220 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x220 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x220 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x224 "NVM_SB_CERR_ADDR68,NVM single-bit correctable error reporting table address register" hexmask.long 0x224 0.--31. 1. "ERR_ADD,Error address field" line.long 0x228 "NVM_SB_CERR_STS69,NVM single-bit correctable error reporting table status register" bitfld.long 0x228 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x228 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x228 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x228 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x22C "NVM_SB_CERR_ADDR69,NVM single-bit correctable error reporting table address register" hexmask.long 0x22C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x230 "NVM_SB_CERR_STS70,NVM single-bit correctable error reporting table status register" bitfld.long 0x230 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x230 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x230 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x230 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x234 "NVM_SB_CERR_ADDR70,NVM single-bit correctable error reporting table address register" hexmask.long 0x234 0.--31. 1. "ERR_ADD,Error address field" line.long 0x238 "NVM_SB_CERR_STS71,NVM single-bit correctable error reporting table status register" bitfld.long 0x238 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x238 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x238 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x238 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x23C "NVM_SB_CERR_ADDR71,NVM single-bit correctable error reporting table address register" hexmask.long 0x23C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x240 "NVM_SB_CERR_STS72,NVM single-bit correctable error reporting table status register" bitfld.long 0x240 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x240 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x240 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x240 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x244 "NVM_SB_CERR_ADDR72,NVM single-bit correctable error reporting table address register" hexmask.long 0x244 0.--31. 1. "ERR_ADD,Error address field" line.long 0x248 "NVM_SB_CERR_STS73,NVM single-bit correctable error reporting table status register" bitfld.long 0x248 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x248 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x248 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x248 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x24C "NVM_SB_CERR_ADDR73,NVM single-bit correctable error reporting table address register" hexmask.long 0x24C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x250 "NVM_SB_CERR_STS74,NVM single-bit correctable error reporting table status register" bitfld.long 0x250 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x250 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x250 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x250 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x254 "NVM_SB_CERR_ADDR74,NVM single-bit correctable error reporting table address register" hexmask.long 0x254 0.--31. 1. "ERR_ADD,Error address field" line.long 0x258 "NVM_SB_CERR_STS75,NVM single-bit correctable error reporting table status register" bitfld.long 0x258 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x258 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x258 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x258 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x25C "NVM_SB_CERR_ADDR75,NVM single-bit correctable error reporting table address register" hexmask.long 0x25C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x260 "NVM_SB_CERR_STS76,NVM single-bit correctable error reporting table status register" bitfld.long 0x260 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x260 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x260 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x260 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x264 "NVM_SB_CERR_ADDR76,NVM single-bit correctable error reporting table address register" hexmask.long 0x264 0.--31. 1. "ERR_ADD,Error address field" line.long 0x268 "NVM_SB_CERR_STS77,NVM single-bit correctable error reporting table status register" bitfld.long 0x268 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x268 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x268 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x268 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x26C "NVM_SB_CERR_ADDR77,NVM single-bit correctable error reporting table address register" hexmask.long 0x26C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x270 "NVM_SB_CERR_STS78,NVM single-bit correctable error reporting table status register" bitfld.long 0x270 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x270 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x270 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x270 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x274 "NVM_SB_CERR_ADDR78,NVM single-bit correctable error reporting table address register" hexmask.long 0x274 0.--31. 1. "ERR_ADD,Error address field" line.long 0x278 "NVM_SB_CERR_STS79,NVM single-bit correctable error reporting table status register" bitfld.long 0x278 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x278 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x278 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x278 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x27C "NVM_SB_CERR_ADDR79,NVM single-bit correctable error reporting table address register" hexmask.long 0x27C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x280 "NVM_SB_CERR_STS80,NVM single-bit correctable error reporting table status register" bitfld.long 0x280 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x280 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x280 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x280 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x284 "NVM_SB_CERR_ADDR80,NVM single-bit correctable error reporting table address register" hexmask.long 0x284 0.--31. 1. "ERR_ADD,Error address field" line.long 0x288 "NVM_SB_CERR_STS81,NVM single-bit correctable error reporting table status register" bitfld.long 0x288 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x288 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x288 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x288 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x28C "NVM_SB_CERR_ADDR81,NVM single-bit correctable error reporting table address register" hexmask.long 0x28C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x290 "NVM_SB_CERR_STS82,NVM single-bit correctable error reporting table status register" bitfld.long 0x290 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x290 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x290 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x290 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x294 "NVM_SB_CERR_ADDR82,NVM single-bit correctable error reporting table address register" hexmask.long 0x294 0.--31. 1. "ERR_ADD,Error address field" line.long 0x298 "NVM_SB_CERR_STS83,NVM single-bit correctable error reporting table status register" bitfld.long 0x298 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x298 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x298 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x298 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x29C "NVM_SB_CERR_ADDR83,NVM single-bit correctable error reporting table address register" hexmask.long 0x29C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x2A0 "NVM_SB_CERR_STS84,NVM single-bit correctable error reporting table status register" bitfld.long 0x2A0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x2A0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x2A0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x2A0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x2A4 "NVM_SB_CERR_ADDR84,NVM single-bit correctable error reporting table address register" hexmask.long 0x2A4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x2A8 "NVM_SB_CERR_STS85,NVM single-bit correctable error reporting table status register" bitfld.long 0x2A8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x2A8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x2A8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x2A8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x2AC "NVM_SB_CERR_ADDR85,NVM single-bit correctable error reporting table address register" hexmask.long 0x2AC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x2B0 "NVM_SB_CERR_STS86,NVM single-bit correctable error reporting table status register" bitfld.long 0x2B0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x2B0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x2B0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x2B0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x2B4 "NVM_SB_CERR_ADDR86,NVM single-bit correctable error reporting table address register" hexmask.long 0x2B4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x2B8 "NVM_SB_CERR_STS87,NVM single-bit correctable error reporting table status register" bitfld.long 0x2B8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x2B8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x2B8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x2B8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x2BC "NVM_SB_CERR_ADDR87,NVM single-bit correctable error reporting table address register" hexmask.long 0x2BC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x2C0 "NVM_SB_CERR_STS88,NVM single-bit correctable error reporting table status register" bitfld.long 0x2C0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x2C0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x2C0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x2C0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x2C4 "NVM_SB_CERR_ADDR88,NVM single-bit correctable error reporting table address register" hexmask.long 0x2C4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x2C8 "NVM_SB_CERR_STS89,NVM single-bit correctable error reporting table status register" bitfld.long 0x2C8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x2C8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x2C8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x2C8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x2CC "NVM_SB_CERR_ADDR89,NVM single-bit correctable error reporting table address register" hexmask.long 0x2CC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x2D0 "NVM_SB_CERR_STS90,NVM single-bit correctable error reporting table status register" bitfld.long 0x2D0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x2D0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x2D0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x2D0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x2D4 "NVM_SB_CERR_ADDR90,NVM single-bit correctable error reporting table address register" hexmask.long 0x2D4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x2D8 "NVM_SB_CERR_STS91,NVM single-bit correctable error reporting table status register" bitfld.long 0x2D8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x2D8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x2D8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x2D8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x2DC "NVM_SB_CERR_ADDR91,NVM single-bit correctable error reporting table address register" hexmask.long 0x2DC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x2E0 "NVM_SB_CERR_STS92,NVM single-bit correctable error reporting table status register" bitfld.long 0x2E0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x2E0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x2E0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x2E0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x2E4 "NVM_SB_CERR_ADDR92,NVM single-bit correctable error reporting table address register" hexmask.long 0x2E4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x2E8 "NVM_SB_CERR_STS93,NVM single-bit correctable error reporting table status register" bitfld.long 0x2E8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x2E8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x2E8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x2E8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x2EC "NVM_SB_CERR_ADDR93,NVM single-bit correctable error reporting table address register" hexmask.long 0x2EC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x2F0 "NVM_SB_CERR_STS94,NVM single-bit correctable error reporting table status register" bitfld.long 0x2F0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x2F0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x2F0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x2F0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x2F4 "NVM_SB_CERR_ADDR94,NVM single-bit correctable error reporting table address register" hexmask.long 0x2F4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x2F8 "NVM_SB_CERR_STS95,NVM single-bit correctable error reporting table status register" bitfld.long 0x2F8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x2F8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x2F8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x2F8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x2FC "NVM_SB_CERR_ADDR95,NVM single-bit correctable error reporting table address register" hexmask.long 0x2FC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x300 "NVM_SB_CERR_STS96,NVM single-bit correctable error reporting table status register" bitfld.long 0x300 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x300 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x300 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x300 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x304 "NVM_SB_CERR_ADDR96,NVM single-bit correctable error reporting table address register" hexmask.long 0x304 0.--31. 1. "ERR_ADD,Error address field" line.long 0x308 "NVM_SB_CERR_STS97,NVM single-bit correctable error reporting table status register" bitfld.long 0x308 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x308 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x308 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x308 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x30C "NVM_SB_CERR_ADDR97,NVM single-bit correctable error reporting table address register" hexmask.long 0x30C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x310 "NVM_SB_CERR_STS98,NVM single-bit correctable error reporting table status register" bitfld.long 0x310 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x310 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x310 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x310 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x314 "NVM_SB_CERR_ADDR98,NVM single-bit correctable error reporting table address register" hexmask.long 0x314 0.--31. 1. "ERR_ADD,Error address field" line.long 0x318 "NVM_SB_CERR_STS99,NVM single-bit correctable error reporting table status register" bitfld.long 0x318 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x318 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x318 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x318 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x31C "NVM_SB_CERR_ADDR99,NVM single-bit correctable error reporting table address register" hexmask.long 0x31C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x320 "NVM_SB_CERR_STS100,NVM single-bit correctable error reporting table status register" bitfld.long 0x320 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x320 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x320 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x320 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x324 "NVM_SB_CERR_ADDR100,NVM single-bit correctable error reporting table address register" hexmask.long 0x324 0.--31. 1. "ERR_ADD,Error address field" line.long 0x328 "NVM_SB_CERR_STS101,NVM single-bit correctable error reporting table status register" bitfld.long 0x328 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x328 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x328 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x328 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x32C "NVM_SB_CERR_ADDR101,NVM single-bit correctable error reporting table address register" hexmask.long 0x32C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x330 "NVM_SB_CERR_STS102,NVM single-bit correctable error reporting table status register" bitfld.long 0x330 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x330 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x330 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x330 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x334 "NVM_SB_CERR_ADDR102,NVM single-bit correctable error reporting table address register" hexmask.long 0x334 0.--31. 1. "ERR_ADD,Error address field" line.long 0x338 "NVM_SB_CERR_STS103,NVM single-bit correctable error reporting table status register" bitfld.long 0x338 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x338 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x338 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x338 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x33C "NVM_SB_CERR_ADDR103,NVM single-bit correctable error reporting table address register" hexmask.long 0x33C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x340 "NVM_SB_CERR_STS104,NVM single-bit correctable error reporting table status register" bitfld.long 0x340 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x340 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x340 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x340 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x344 "NVM_SB_CERR_ADDR104,NVM single-bit correctable error reporting table address register" hexmask.long 0x344 0.--31. 1. "ERR_ADD,Error address field" line.long 0x348 "NVM_SB_CERR_STS105,NVM single-bit correctable error reporting table status register" bitfld.long 0x348 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x348 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x348 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x348 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x34C "NVM_SB_CERR_ADDR105,NVM single-bit correctable error reporting table address register" hexmask.long 0x34C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x350 "NVM_SB_CERR_STS106,NVM single-bit correctable error reporting table status register" bitfld.long 0x350 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x350 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x350 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x350 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x354 "NVM_SB_CERR_ADDR106,NVM single-bit correctable error reporting table address register" hexmask.long 0x354 0.--31. 1. "ERR_ADD,Error address field" line.long 0x358 "NVM_SB_CERR_STS107,NVM single-bit correctable error reporting table status register" bitfld.long 0x358 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x358 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x358 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x358 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x35C "NVM_SB_CERR_ADDR107,NVM single-bit correctable error reporting table address register" hexmask.long 0x35C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x360 "NVM_SB_CERR_STS108,NVM single-bit correctable error reporting table status register" bitfld.long 0x360 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x360 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x360 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x360 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x364 "NVM_SB_CERR_ADDR108,NVM single-bit correctable error reporting table address register" hexmask.long 0x364 0.--31. 1. "ERR_ADD,Error address field" line.long 0x368 "NVM_SB_CERR_STS109,NVM single-bit correctable error reporting table status register" bitfld.long 0x368 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x368 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x368 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x368 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x36C "NVM_SB_CERR_ADDR109,NVM single-bit correctable error reporting table address register" hexmask.long 0x36C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x370 "NVM_SB_CERR_STS110,NVM single-bit correctable error reporting table status register" bitfld.long 0x370 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x370 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x370 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x370 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x374 "NVM_SB_CERR_ADDR110,NVM single-bit correctable error reporting table address register" hexmask.long 0x374 0.--31. 1. "ERR_ADD,Error address field" line.long 0x378 "NVM_SB_CERR_STS111,NVM single-bit correctable error reporting table status register" bitfld.long 0x378 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x378 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x378 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x378 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x37C "NVM_SB_CERR_ADDR111,NVM single-bit correctable error reporting table address register" hexmask.long 0x37C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x380 "NVM_SB_CERR_STS112,NVM single-bit correctable error reporting table status register" bitfld.long 0x380 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x380 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x380 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x380 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x384 "NVM_SB_CERR_ADDR112,NVM single-bit correctable error reporting table address register" hexmask.long 0x384 0.--31. 1. "ERR_ADD,Error address field" line.long 0x388 "NVM_SB_CERR_STS113,NVM single-bit correctable error reporting table status register" bitfld.long 0x388 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x388 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x388 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x388 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x38C "NVM_SB_CERR_ADDR113,NVM single-bit correctable error reporting table address register" hexmask.long 0x38C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x390 "NVM_SB_CERR_STS114,NVM single-bit correctable error reporting table status register" bitfld.long 0x390 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x390 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x390 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x390 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x394 "NVM_SB_CERR_ADDR114,NVM single-bit correctable error reporting table address register" hexmask.long 0x394 0.--31. 1. "ERR_ADD,Error address field" line.long 0x398 "NVM_SB_CERR_STS115,NVM single-bit correctable error reporting table status register" bitfld.long 0x398 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x398 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x398 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x398 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x39C "NVM_SB_CERR_ADDR115,NVM single-bit correctable error reporting table address register" hexmask.long 0x39C 0.--31. 1. "ERR_ADD,Error address field" line.long 0x3A0 "NVM_SB_CERR_STS116,NVM single-bit correctable error reporting table status register" bitfld.long 0x3A0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x3A0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x3A0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x3A0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x3A4 "NVM_SB_CERR_ADDR116,NVM single-bit correctable error reporting table address register" hexmask.long 0x3A4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x3A8 "NVM_SB_CERR_STS117,NVM single-bit correctable error reporting table status register" bitfld.long 0x3A8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x3A8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x3A8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x3A8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x3AC "NVM_SB_CERR_ADDR117,NVM single-bit correctable error reporting table address register" hexmask.long 0x3AC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x3B0 "NVM_SB_CERR_STS118,NVM single-bit correctable error reporting table status register" bitfld.long 0x3B0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x3B0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x3B0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x3B0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x3B4 "NVM_SB_CERR_ADDR118,NVM single-bit correctable error reporting table address register" hexmask.long 0x3B4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x3B8 "NVM_SB_CERR_STS119,NVM single-bit correctable error reporting table status register" bitfld.long 0x3B8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x3B8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x3B8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x3B8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x3BC "NVM_SB_CERR_ADDR119,NVM single-bit correctable error reporting table address register" hexmask.long 0x3BC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x3C0 "NVM_SB_CERR_STS120,NVM single-bit correctable error reporting table status register" bitfld.long 0x3C0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x3C0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x3C0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x3C0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x3C4 "NVM_SB_CERR_ADDR120,NVM single-bit correctable error reporting table address register" hexmask.long 0x3C4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x3C8 "NVM_SB_CERR_STS121,NVM single-bit correctable error reporting table status register" bitfld.long 0x3C8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x3C8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x3C8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x3C8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x3CC "NVM_SB_CERR_ADDR121,NVM single-bit correctable error reporting table address register" hexmask.long 0x3CC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x3D0 "NVM_SB_CERR_STS122,NVM single-bit correctable error reporting table status register" bitfld.long 0x3D0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x3D0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x3D0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x3D0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x3D4 "NVM_SB_CERR_ADDR122,NVM single-bit correctable error reporting table address register" hexmask.long 0x3D4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x3D8 "NVM_SB_CERR_STS123,NVM single-bit correctable error reporting table status register" bitfld.long 0x3D8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x3D8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x3D8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x3D8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x3DC "NVM_SB_CERR_ADDR123,NVM single-bit correctable error reporting table address register" hexmask.long 0x3DC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x3E0 "NVM_SB_CERR_STS124,NVM single-bit correctable error reporting table status register" bitfld.long 0x3E0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x3E0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x3E0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x3E0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x3E4 "NVM_SB_CERR_ADDR124,NVM single-bit correctable error reporting table address register" hexmask.long 0x3E4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x3E8 "NVM_SB_CERR_STS125,NVM single-bit correctable error reporting table status register" bitfld.long 0x3E8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x3E8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x3E8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x3E8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x3EC "NVM_SB_CERR_ADDR125,NVM single-bit correctable error reporting table address register" hexmask.long 0x3EC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x3F0 "NVM_SB_CERR_STS126,NVM single-bit correctable error reporting table status register" bitfld.long 0x3F0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x3F0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x3F0 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x3F0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x3F4 "NVM_SB_CERR_ADDR126,NVM single-bit correctable error reporting table address register" hexmask.long 0x3F4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x3F8 "NVM_SB_CERR_STS127,NVM single-bit correctable error reporting table status register" bitfld.long 0x3F8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x3F8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x3F8 20.--27. 1. "MEM_ID,This field indicates the error source index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x3F8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x3FC "NVM_SB_CERR_ADDR127,NVM single-bit correctable error reporting table address register" hexmask.long 0x3FC 0.--31. 1. "ERR_ADD,Error address field" rgroup.long 0x1A00++0x3 line.long 0x0 "NVM_SB_CERR_TBL_FILL_STAT,NVM single-bit correctable error reporting table fill status register" hexmask.long.byte 0x0 0.--7. 1. "SB_CERR_TBL_FILL_VAL,This value indicates the number of valid entries in the single correctable table for NVM" group.long 0x1A10++0x1F line.long 0x0 "NVM_DB_CERR_STS0,NVM double-bit correctable error reporting table status register" bitfld.long 0x0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x0 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x0 20.--27. 1. "MEM_ID,This field indicates the channel index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x0 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x4 "NVM_DB_CERR_ADDR0,NVM double-bit correctable error reporting table address register" hexmask.long 0x4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x8 "NVM_DB_CERR_STS1,NVM double-bit correctable error reporting table status register" bitfld.long 0x8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x8 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x8 20.--27. 1. "MEM_ID,This field indicates the channel index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x8 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0xC "NVM_DB_CERR_ADDR1,NVM double-bit correctable error reporting table address register" hexmask.long 0xC 0.--31. 1. "ERR_ADD,Error address field" line.long 0x10 "NVM_DB_CERR_STS2,NVM double-bit correctable error reporting table status register" bitfld.long 0x10 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x10 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x10 20.--27. 1. "MEM_ID,This field indicates the channel index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x10 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x14 "NVM_DB_CERR_ADDR2,NVM double-bit correctable error reporting table address register" hexmask.long 0x14 0.--31. 1. "ERR_ADD,Error address field" line.long 0x18 "NVM_DB_CERR_STS3,NVM double-bit correctable error reporting table status register" bitfld.long 0x18 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." newline bitfld.long 0x18 28. "ECC_OR_MBIST,This field indicates whether the error logged in the reporting table entry is an ECC or MBIST error." "0: MBIST error.,1: ECC error." newline hexmask.long.byte 0x18 20.--27. 1. "MEM_ID,This field indicates the channel index corresponding to the BAD_BIT captured. The 6 MSB bits indicate 1 of the 64 MEMU channels while the 2 LSBs indicate one of the 4 sources connected to a single MEMU channel." newline hexmask.long.tbyte 0x18 0.--16. 1. "BAD_BIT,Bad bit field" line.long 0x1C "NVM_DB_CERR_ADDR3,NVM double-bit correctable error reporting table address register" hexmask.long 0x1C 0.--31. 1. "ERR_ADD,Error address field" rgroup.long 0x1A30++0x3 line.long 0x0 "NVM_DB_CERR_TBL_FILL_STAT,NVM double-bit correctable error reporting table fill status register" hexmask.long.byte 0x0 0.--7. 1. "DB_CERR_TBL_FILL_VAL,This value indicates the number of valid entries in the double correctable table for NVM." group.long 0x1E20++0xF line.long 0x0 "NVM_UNCERR_STS0,NVM uncorrectable error reporting table status register" bitfld.long 0x0 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0x4 "NVM_UNCERR_ADDR0,NVM uncorrectable error reporting table address register" hexmask.long 0x4 0.--31. 1. "ERR_ADD,Error address field" line.long 0x8 "NVM_UNCERR_STS1,NVM uncorrectable error reporting table status register" bitfld.long 0x8 31. "VLD,Valid bit" "0: entry is not valid.,1: entry is valid." line.long 0xC "NVM_UNCERR_ADDR1,NVM uncorrectable error reporting table address register" hexmask.long 0xC 0.--31. 1. "ERR_ADD,Error address field" rgroup.long 0x1E30++0x3 line.long 0x0 "NVM_UNCERR_TBL_FILL_STAT,NVM uncorrectable error reporting table fill status register" hexmask.long.byte 0x0 0.--7. 1. "UNCERR_TBL_FILL_VAL,This value indicates the number of valid entries in the uncorrectable table for NVM." group.long 0x2030++0x3 line.long 0x0 "NVM_OFLW0,NVM concurrent overflow registers" hexmask.long 0x0 0.--31. 1. "OFLW,Overflow Bit" group.long 0x2050++0x147 line.long 0x0 "NVM_ECC_FD_CTRL0,NVM ECC fault descriptor control registers" bitfld.long 0x0 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x0 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x0 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0x0 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x0 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x0 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x4 "NVM_ECC_FD_START0,NVM ECC fault descriptor start address registers" hexmask.long 0x4 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x8 "NVM_ECC_FD_END0,NVM ECC fault descriptor end address registers" hexmask.long 0x8 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xC "NVM_ECC_FD_CTRL1,NVM ECC fault descriptor control registers" bitfld.long 0xC 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xC 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xC 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0xC 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xC 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xC 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x10 "NVM_ECC_FD_START1,NVM ECC fault descriptor start address registers" hexmask.long 0x10 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x14 "NVM_ECC_FD_END1,NVM ECC fault descriptor end address registers" hexmask.long 0x14 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x18 "NVM_ECC_FD_CTRL2,NVM ECC fault descriptor control registers" bitfld.long 0x18 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x18 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x18 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0x18 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x18 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x18 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x1C "NVM_ECC_FD_START2,NVM ECC fault descriptor start address registers" hexmask.long 0x1C 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x20 "NVM_ECC_FD_END2,NVM ECC fault descriptor end address registers" hexmask.long 0x20 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x24 "NVM_ECC_FD_CTRL3,NVM ECC fault descriptor control registers" bitfld.long 0x24 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x24 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x24 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0x24 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x24 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x24 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x28 "NVM_ECC_FD_START3,NVM ECC fault descriptor start address registers" hexmask.long 0x28 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x2C "NVM_ECC_FD_END3,NVM ECC fault descriptor end address registers" hexmask.long 0x2C 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x30 "NVM_ECC_FD_CTRL4,NVM ECC fault descriptor control registers" bitfld.long 0x30 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x30 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x30 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0x30 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x30 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x30 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x34 "NVM_ECC_FD_START4,NVM ECC fault descriptor start address registers" hexmask.long 0x34 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x38 "NVM_ECC_FD_END4,NVM ECC fault descriptor end address registers" hexmask.long 0x38 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x3C "NVM_ECC_FD_CTRL5,NVM ECC fault descriptor control registers" bitfld.long 0x3C 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x3C 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x3C 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0x3C 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x3C 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x3C 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x40 "NVM_ECC_FD_START5,NVM ECC fault descriptor start address registers" hexmask.long 0x40 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x44 "NVM_ECC_FD_END5,NVM ECC fault descriptor end address registers" hexmask.long 0x44 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x48 "NVM_ECC_FD_CTRL6,NVM ECC fault descriptor control registers" bitfld.long 0x48 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x48 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x48 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0x48 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x48 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x48 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x4C "NVM_ECC_FD_START6,NVM ECC fault descriptor start address registers" hexmask.long 0x4C 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x50 "NVM_ECC_FD_END6,NVM ECC fault descriptor end address registers" hexmask.long 0x50 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x54 "NVM_ECC_FD_CTRL7,NVM ECC fault descriptor control registers" bitfld.long 0x54 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x54 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x54 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0x54 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x54 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x54 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x58 "NVM_ECC_FD_START7,NVM ECC fault descriptor start address registers" hexmask.long 0x58 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x5C "NVM_ECC_FD_END7,NVM ECC fault descriptor end address registers" hexmask.long 0x5C 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x60 "NVM_ECC_FD_CTRL8,NVM ECC fault descriptor control registers" bitfld.long 0x60 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x60 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x60 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0x60 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x60 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x60 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x64 "NVM_ECC_FD_START8,NVM ECC fault descriptor start address registers" hexmask.long 0x64 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x68 "NVM_ECC_FD_END8,NVM ECC fault descriptor end address registers" hexmask.long 0x68 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x6C "NVM_ECC_FD_CTRL9,NVM ECC fault descriptor control registers" bitfld.long 0x6C 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x6C 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x6C 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0x6C 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x6C 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x6C 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x70 "NVM_ECC_FD_START9,NVM ECC fault descriptor start address registers" hexmask.long 0x70 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x74 "NVM_ECC_FD_END9,NVM ECC fault descriptor end address registers" hexmask.long 0x74 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x78 "NVM_ECC_FD_CTRL10,NVM ECC fault descriptor control registers" bitfld.long 0x78 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x78 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x78 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0x78 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x78 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x78 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x7C "NVM_ECC_FD_START10,NVM ECC fault descriptor start address registers" hexmask.long 0x7C 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x80 "NVM_ECC_FD_END10,NVM ECC fault descriptor end address registers" hexmask.long 0x80 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x84 "NVM_ECC_FD_CTRL11,NVM ECC fault descriptor control registers" bitfld.long 0x84 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x84 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x84 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0x84 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x84 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x84 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x88 "NVM_ECC_FD_START11,NVM ECC fault descriptor start address registers" hexmask.long 0x88 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x8C "NVM_ECC_FD_END11,NVM ECC fault descriptor end address registers" hexmask.long 0x8C 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x90 "NVM_ECC_FD_CTRL12,NVM ECC fault descriptor control registers" bitfld.long 0x90 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x90 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x90 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0x90 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x90 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x90 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x94 "NVM_ECC_FD_START12,NVM ECC fault descriptor start address registers" hexmask.long 0x94 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x98 "NVM_ECC_FD_END12,NVM ECC fault descriptor end address registers" hexmask.long 0x98 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x9C "NVM_ECC_FD_CTRL13,NVM ECC fault descriptor control registers" bitfld.long 0x9C 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x9C 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x9C 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0x9C 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x9C 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x9C 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xA0 "NVM_ECC_FD_START13,NVM ECC fault descriptor start address registers" hexmask.long 0xA0 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xA4 "NVM_ECC_FD_END13,NVM ECC fault descriptor end address registers" hexmask.long 0xA4 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xA8 "NVM_ECC_FD_CTRL14,NVM ECC fault descriptor control registers" bitfld.long 0xA8 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xA8 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xA8 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0xA8 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xA8 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xA8 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xAC "NVM_ECC_FD_START14,NVM ECC fault descriptor start address registers" hexmask.long 0xAC 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xB0 "NVM_ECC_FD_END14,NVM ECC fault descriptor end address registers" hexmask.long 0xB0 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xB4 "NVM_ECC_FD_CTRL15,NVM ECC fault descriptor control registers" bitfld.long 0xB4 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xB4 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xB4 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0xB4 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xB4 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xB4 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xB8 "NVM_ECC_FD_START15,NVM ECC fault descriptor start address registers" hexmask.long 0xB8 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xBC "NVM_ECC_FD_END15,NVM ECC fault descriptor end address registers" hexmask.long 0xBC 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xC0 "NVM_ECC_FD_CTRL16,NVM ECC fault descriptor control registers" bitfld.long 0xC0 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xC0 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xC0 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0xC0 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xC0 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xC0 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xC4 "NVM_ECC_FD_START16,NVM ECC fault descriptor start address registers" hexmask.long 0xC4 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xC8 "NVM_ECC_FD_END16,NVM ECC fault descriptor end address registers" hexmask.long 0xC8 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xCC "NVM_ECC_FD_CTRL17,NVM ECC fault descriptor control registers" bitfld.long 0xCC 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xCC 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xCC 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0xCC 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xCC 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xCC 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xD0 "NVM_ECC_FD_START17,NVM ECC fault descriptor start address registers" hexmask.long 0xD0 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xD4 "NVM_ECC_FD_END17,NVM ECC fault descriptor end address registers" hexmask.long 0xD4 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xD8 "NVM_ECC_FD_CTRL18,NVM ECC fault descriptor control registers" bitfld.long 0xD8 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xD8 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xD8 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0xD8 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xD8 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xD8 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xDC "NVM_ECC_FD_START18,NVM ECC fault descriptor start address registers" hexmask.long 0xDC 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xE0 "NVM_ECC_FD_END18,NVM ECC fault descriptor end address registers" hexmask.long 0xE0 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xE4 "NVM_ECC_FD_CTRL19,NVM ECC fault descriptor control registers" bitfld.long 0xE4 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xE4 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xE4 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0xE4 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xE4 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xE4 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xE8 "NVM_ECC_FD_START19,NVM ECC fault descriptor start address registers" hexmask.long 0xE8 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xEC "NVM_ECC_FD_END19,NVM ECC fault descriptor end address registers" hexmask.long 0xEC 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xF0 "NVM_ECC_FD_CTRL20,NVM ECC fault descriptor control registers" bitfld.long 0xF0 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xF0 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xF0 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0xF0 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xF0 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xF0 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0xF4 "NVM_ECC_FD_START20,NVM ECC fault descriptor start address registers" hexmask.long 0xF4 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0xF8 "NVM_ECC_FD_END20,NVM ECC fault descriptor end address registers" hexmask.long 0xF8 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0xFC "NVM_ECC_FD_CTRL21,NVM ECC fault descriptor control registers" bitfld.long 0xFC 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0xFC 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0xFC 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0xFC 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0xFC 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0xFC 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x100 "NVM_ECC_FD_START21,NVM ECC fault descriptor start address registers" hexmask.long 0x100 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x104 "NVM_ECC_FD_END21,NVM ECC fault descriptor end address registers" hexmask.long 0x104 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x108 "NVM_ECC_FD_CTRL22,NVM ECC fault descriptor control registers" bitfld.long 0x108 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x108 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x108 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0x108 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x108 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x108 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x10C "NVM_ECC_FD_START22,NVM ECC fault descriptor start address registers" hexmask.long 0x10C 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x110 "NVM_ECC_FD_END22,NVM ECC fault descriptor end address registers" hexmask.long 0x110 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x114 "NVM_ECC_FD_CTRL23,NVM ECC fault descriptor control registers" bitfld.long 0x114 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x114 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x114 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0x114 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x114 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x114 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x118 "NVM_ECC_FD_START23,NVM ECC fault descriptor start address registers" hexmask.long 0x118 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x11C "NVM_ECC_FD_END23,NVM ECC fault descriptor end address registers" hexmask.long 0x11C 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x120 "NVM_ECC_FD_CTRL24,NVM ECC fault descriptor control registers" bitfld.long 0x120 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x120 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x120 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0x120 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x120 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x120 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x124 "NVM_ECC_FD_START24,NVM ECC fault descriptor start address registers" hexmask.long 0x124 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x128 "NVM_ECC_FD_END24,NVM ECC fault descriptor end address registers" hexmask.long 0x128 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x12C "NVM_ECC_FD_CTRL25,NVM ECC fault descriptor control registers" bitfld.long 0x12C 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x12C 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x12C 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0x12C 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x12C 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x12C 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x130 "NVM_ECC_FD_START25,NVM ECC fault descriptor start address registers" hexmask.long 0x130 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x134 "NVM_ECC_FD_END25,NVM ECC fault descriptor end address registers" hexmask.long 0x134 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x138 "NVM_ECC_FD_CTRL26,NVM ECC fault descriptor control registers" bitfld.long 0x138 31. "EN,EN" "0: ECC fault descriptor shall not be used,1: ECC fault descriptor shall be used" newline bitfld.long 0x138 18. "UC,UC" "0: Uncorrectable ECC errors shall be ignored,1: Uncorrectable ECC errors shall be taken in account" newline bitfld.long 0x138 17. "DBC,DBC" "0: Double-bit ECC errors shall be ignored,1: Double-bit ECC errors shall be taken in account" newline bitfld.long 0x138 16. "SBC,SBC" "0: Single-bit ECC errors shall be ignored,1: Single-bit ECC errors shall be taken in account" newline bitfld.long 0x138 15. "T32,T32" "0: addresses used for the comparison are the ones..,1: addresses used for the comparison are the ones.." newline hexmask.long.byte 0x138 0.--3. 1. "FCCU_TRG,Others: number of FCCU trigger channel" line.long 0x13C "NVM_ECC_FD_START26,NVM ECC fault descriptor start address registers" hexmask.long 0x13C 0.--31. 1. "START_ADR,Address indicating the region start address." line.long 0x140 "NVM_ECC_FD_END26,NVM ECC fault descriptor end address registers" hexmask.long 0x140 0.--31. 1. "END_ADR,Address indicating the region end address." line.long 0x144 "NVM_T320,NVM address extension registers" bitfld.long 0x144 31. "T31,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 30. "T30,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 29. "T29,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 28. "T28,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 27. "T27,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 26. "T26,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 25. "T25,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 24. "T24,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 23. "T23,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 22. "T22,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 21. "T21,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 20. "T20,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 19. "T19,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 18. "T18,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 17. "T17,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 16. "T16,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 15. "T15,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 14. "T14,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 13. "T13,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 12. "T12,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 11. "T11,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 10. "T10,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 9. "T9,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 8. "T8,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 7. "T7,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 6. "T6,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 5. "T5,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 4. "T4,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 3. "T3,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 2. "T2,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 1. "T1,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" newline bitfld.long 0x144 0. "T0,MSB bit to be added to extend the reported address of the MEMU2 input ECC fault channel n*32+i (where i is the bit number of the corresponding bit field Ti)." "0,1" tree.end tree "MSC (Micro Second Channel)" base ad:0x0 tree "MSC_0" base ad:0x71A60000 group.long 0x0++0x7 line.long 0x0 "MSCCCR,MSC Clock Control Register" bitfld.long 0x0 16. "EN_RX_RSTN,ENable RX ReSeTN. EN_RX_RSTN is a Read/Write bit field. The EN_RX_RSTN bit enables an HW Synchronous Reset on all MSC RX of msc_uck domain circuitry triggered when [UECR]UNMATCH asserts." "0: The [UECR]UNMATCH never resets the MSC RX..,1: On [UECR]UNMATCH field asserting the MSC RX.." hexmask.long.byte 0x0 0.--7. 1. "MSCCK_DIV,MSC ClocK DIVider. MSCCK_DIV is a 8-bits Read/Write field. According to the following definition the msc_clk clock frequency is divisible for: 4 6 8 10 12 16 20 24 40." line.long 0x4 "MSCIOR,MSC Inputs Outputs Register" bitfld.long 0x4 19. "CKP,Clock Polarity" "0: Normal polarity.,1: Inverse polarity." bitfld.long 0x4 18. "CKA,Clock always Active" "0: It means msc_dclk is active only when enables..,1: It means msc_dclk is always active." newline bitfld.long 0x4 17. "CK_DIFF,Clock output Differential" "0: The MSC msc_dclk Downstream Clock is not in..,1: The MSC msc_dclk Downstream Clock is in.." bitfld.long 0x4 16. "CK_OBE,ClocK Output Buffer Enable" "0: The MSC msc_dclk Downstream clock output is not..,1: The MSC msc_dclk Downstream clock output is.." newline bitfld.long 0x4 4. "ENP,Enable Polarity" "0: Normal polarity.,1: " bitfld.long 0x4 3. "DSOP,Downstream Serial Output Polarity register" "0: Normal polarity.,1: Inverse polarity." newline bitfld.long 0x4 1. "DSO_DIFF,Data Serial Output Differential" "0: The MSC msc_dso Downstream Serial data Out is..,1: The MSC msc_dso Downstream Serial data Out is in.." bitfld.long 0x4 0. "DSO_OBE,Data Serial Output Buffer Enable" "0: The MSC msc_dso Downstream Serial data Out is..,1: The MSC msc_dso Downstream Serial data Out is.." rgroup.long 0xC++0x3 line.long 0x0 "UFIFOR,Upstream FIFO Register" hexmask.long 0x0 0.--31. 1. "UFIFO,Upstream FIFO frame" group.long 0x10++0x27 line.long 0x0 "UFR0,Upstream Frame Register 0" bitfld.long 0x0 28. "EN_OWRERF,Enable Overwrite Error Frame" "0: The rx_owrerf interrupt request is disabled in..,1: The rx_owrerf interrupt request is enabled in.." bitfld.long 0x0 27. "EN_STOPBERF,Enable Stop Bit Error Frame" "0: The rx_stopbiterf interrupt request is disabled..,1: The rx_stopbiterf interrupt request is enabled.." newline bitfld.long 0x0 26. "EN_PARERF,Enable Parity Error Frame n" "0: The rx_parerf interrupt request is disabled in..,1: The rx_parerf interrupt request is enabled in.." bitfld.long 0x0 25. "EN_CONSBERF,Enable Consistency Bit Error Frame" "0: The rx_consbiterf interrupt request is disabled..,1: The rx_consbiterf interrupt request is enabled.." newline bitfld.long 0x0 24. "EN_NEWF,Enable New Frame" "0: The rx_newf interrupt request is disabled in UFRn.,1: The rx_newf interrupt request is enabled in UFRn." bitfld.long 0x0 20. "OWRERF,Overwrite Error Frame" "0: The OWRERF pending bit is cleared setting by SW..,1: The OWRERF pending bit is set by HW when on a.." newline bitfld.long 0x0 19. "STOPBERF,Stop Bit Error Frame" "0: The STOPBERF pending bit is cleared setting by..,1: The STOPBERF pending bit is set by HW when one.." bitfld.long 0x0 18. "PARERF,Parity Error Frame" "0: The PARERF pending bit is cleared setting by SW..,1: The PARERF pending bit is set by HW only and it.." newline bitfld.long 0x0 17. "CONSBITERF,Consistency Bit Error Frame n" "0: The CONSBERF pending bit is cleared by a SW..,1: The CONSBERF pending bit is set by HW only when.." bitfld.long 0x0 16. "NEWF,New Frame" "0: The NEWF pending bit is cleared by a SW setting.,1: The NEWF pending bit is set by HW only when a.." newline bitfld.long 0x0 15. "PARITY,UFRn Parity field" "0: The received upstream has parity 0.,1: The received upstream has parity 1." bitfld.long 0x0 12.--14. "STOP,UFRn Stop bits" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ADD,UFRn Address" hexmask.long.byte 0x0 0.--7. 1. "DATA,UFRn Data" line.long 0x4 "UFR1,Upstream Frame Register 1" bitfld.long 0x4 28. "EN_OWRERF,Enable Overwrite Error Frame" "0: The rx_owrerf interrupt request is disabled in..,1: The rx_owrerf interrupt request is enabled in.." bitfld.long 0x4 27. "EN_STOPBERF,Enable Stop Bit Error Frame" "0: The rx_stopbiterf interrupt request is disabled..,1: The rx_stopbiterf interrupt request is enabled.." newline bitfld.long 0x4 26. "EN_PARERF,Enable Parity Error Frame n" "0: The rx_parerf interrupt request is disabled in..,1: The rx_parerf interrupt request is enabled in.." bitfld.long 0x4 25. "EN_CONSBERF,Enable Consistency Bit Error Frame" "0: The rx_consbiterf interrupt request is disabled..,1: The rx_consbiterf interrupt request is enabled.." newline bitfld.long 0x4 24. "EN_NEWF,Enable New Frame" "0: The rx_newf interrupt request is disabled in UFRn.,1: The rx_newf interrupt request is enabled in UFRn." bitfld.long 0x4 20. "OWRERF,Overwrite Error Frame" "0: The OWRERF pending bit is cleared setting by SW..,1: The OWRERF pending bit is set by HW when on a.." newline bitfld.long 0x4 19. "STOPBERF,Stop Bit Error Frame" "0: The STOPBERF pending bit is cleared setting by..,1: The STOPBERF pending bit is set by HW when one.." bitfld.long 0x4 18. "PARERF,Parity Error Frame" "0: The PARERF pending bit is cleared setting by SW..,1: The PARERF pending bit is set by HW only and it.." newline bitfld.long 0x4 17. "CONSBITERF,Consistency Bit Error Frame n" "0: The CONSBERF pending bit is cleared by a SW..,1: The CONSBERF pending bit is set by HW only when.." bitfld.long 0x4 16. "NEWF,New Frame" "0: The NEWF pending bit is cleared by a SW setting.,1: The NEWF pending bit is set by HW only when a.." newline bitfld.long 0x4 15. "PARITY,UFRn Parity field" "0: The received upstream has parity 0.,1: The received upstream has parity 1." bitfld.long 0x4 12.--14. "STOP,UFRn Stop bits" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "ADD,UFRn Address" hexmask.long.byte 0x4 0.--7. 1. "DATA,UFRn Data" line.long 0x8 "UFR2,Upstream Frame Register 2" bitfld.long 0x8 28. "EN_OWRERF,Enable Overwrite Error Frame" "0: The rx_owrerf interrupt request is disabled in..,1: The rx_owrerf interrupt request is enabled in.." bitfld.long 0x8 27. "EN_STOPBERF,Enable Stop Bit Error Frame" "0: The rx_stopbiterf interrupt request is disabled..,1: The rx_stopbiterf interrupt request is enabled.." newline bitfld.long 0x8 26. "EN_PARERF,Enable Parity Error Frame n" "0: The rx_parerf interrupt request is disabled in..,1: The rx_parerf interrupt request is enabled in.." bitfld.long 0x8 25. "EN_CONSBERF,Enable Consistency Bit Error Frame" "0: The rx_consbiterf interrupt request is disabled..,1: The rx_consbiterf interrupt request is enabled.." newline bitfld.long 0x8 24. "EN_NEWF,Enable New Frame" "0: The rx_newf interrupt request is disabled in UFRn.,1: The rx_newf interrupt request is enabled in UFRn." bitfld.long 0x8 20. "OWRERF,Overwrite Error Frame" "0: The OWRERF pending bit is cleared setting by SW..,1: The OWRERF pending bit is set by HW when on a.." newline bitfld.long 0x8 19. "STOPBERF,Stop Bit Error Frame" "0: The STOPBERF pending bit is cleared setting by..,1: The STOPBERF pending bit is set by HW when one.." bitfld.long 0x8 18. "PARERF,Parity Error Frame" "0: The PARERF pending bit is cleared setting by SW..,1: The PARERF pending bit is set by HW only and it.." newline bitfld.long 0x8 17. "CONSBITERF,Consistency Bit Error Frame n" "0: The CONSBERF pending bit is cleared by a SW..,1: The CONSBERF pending bit is set by HW only when.." bitfld.long 0x8 16. "NEWF,New Frame" "0: The NEWF pending bit is cleared by a SW setting.,1: The NEWF pending bit is set by HW only when a.." newline bitfld.long 0x8 15. "PARITY,UFRn Parity field" "0: The received upstream has parity 0.,1: The received upstream has parity 1." bitfld.long 0x8 12.--14. "STOP,UFRn Stop bits" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "ADD,UFRn Address" hexmask.long.byte 0x8 0.--7. 1. "DATA,UFRn Data" line.long 0xC "UFR3,Upstream Frame Register 3" bitfld.long 0xC 28. "EN_OWRERF,Enable Overwrite Error Frame" "0: The rx_owrerf interrupt request is disabled in..,1: The rx_owrerf interrupt request is enabled in.." bitfld.long 0xC 27. "EN_STOPBERF,Enable Stop Bit Error Frame" "0: The rx_stopbiterf interrupt request is disabled..,1: The rx_stopbiterf interrupt request is enabled.." newline bitfld.long 0xC 26. "EN_PARERF,Enable Parity Error Frame n" "0: The rx_parerf interrupt request is disabled in..,1: The rx_parerf interrupt request is enabled in.." bitfld.long 0xC 25. "EN_CONSBERF,Enable Consistency Bit Error Frame" "0: The rx_consbiterf interrupt request is disabled..,1: The rx_consbiterf interrupt request is enabled.." newline bitfld.long 0xC 24. "EN_NEWF,Enable New Frame" "0: The rx_newf interrupt request is disabled in UFRn.,1: The rx_newf interrupt request is enabled in UFRn." bitfld.long 0xC 20. "OWRERF,Overwrite Error Frame" "0: The OWRERF pending bit is cleared setting by SW..,1: The OWRERF pending bit is set by HW when on a.." newline bitfld.long 0xC 19. "STOPBERF,Stop Bit Error Frame" "0: The STOPBERF pending bit is cleared setting by..,1: The STOPBERF pending bit is set by HW when one.." bitfld.long 0xC 18. "PARERF,Parity Error Frame" "0: The PARERF pending bit is cleared setting by SW..,1: The PARERF pending bit is set by HW only and it.." newline bitfld.long 0xC 17. "CONSBITERF,Consistency Bit Error Frame n" "0: The CONSBERF pending bit is cleared by a SW..,1: The CONSBERF pending bit is set by HW only when.." bitfld.long 0xC 16. "NEWF,New Frame" "0: The NEWF pending bit is cleared by a SW setting.,1: The NEWF pending bit is set by HW only when a.." newline bitfld.long 0xC 15. "PARITY,UFRn Parity field" "0: The received upstream has parity 0.,1: The received upstream has parity 1." bitfld.long 0xC 12.--14. "STOP,UFRn Stop bits" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "ADD,UFRn Address" hexmask.long.byte 0xC 0.--7. 1. "DATA,UFRn Data" line.long 0x10 "UKERCR,Upstream Kernel Control Register" bitfld.long 0x10 31. "US_REQ,Upstream Setup Request" "0: The USREQ is cleared by HW a clk cycle after its..,1: The USREQ setting is kept for one clk cycle only." bitfld.long 0x10 30. "US_ACK,Upstream Setup Acknowledge" "0: Meanwhile the new set up values are loaded to..,1: The Rx kernel has received the new setup values." newline bitfld.long 0x10 29. "USRA_R,Upstream Setup Request Acknowledge Reset" "0: Both US_REQ and US_ACK bits can be accessed.,1: Both US_REQ and US_ACK bits are forced low." bitfld.long 0x10 20. "IUIS,Inverted Upstream Input Selector field" "0: The msc_usi input will be evaluated with no..,1: The msc_usi input will be evaluated forcing a.." newline bitfld.long 0x10 16.--18. "USISEL,Upstream Serial Input Selections" "0: Selects the msc_usi[0] input line,1: Selects the msc_usi[1] input line,2: Selects the msc_usi[2] input line,3: Selects the msc_usi[3] input line,4: Selects the msc_usi[4] input line,5: Selects the msc_usi[5] input line,6: Selects the msc_usi[6] input line,7: Selects the msc_usi[7] input line" bitfld.long 0x10 4.--5. "USBN,Upstream Stop Bits Number" "0: 2 Stop Bits,1: 1 Stop Bit,2: 2 Stop Bits,3: 3 Stop Bits" newline bitfld.long 0x10 0.--2. "UBR,Upstream Baud Rate" "0: Rx kernel disabled,1: Baud Rate = fMSC/4,2: Baud Rate = fMSC/8,3: Baud Rate = fMSC/16,4: Baud Rate = fMSC/32,5: Baud Rate = fMSC/64,6: Baud Rate = fMSC/128,7: Baud Rate = fMSC/256" line.long 0x14 "UREGCR,Upstream Registers Control Register" bitfld.long 0x14 31. "UREG_EN,Upstream Register Enable" "0,1" bitfld.long 0x14 12. "UPT,Upstream Parity Type" "0: The msc_usi input will be evaluated with an even..,1: The msc_usi input will be evaluated with an odd.." newline bitfld.long 0x14 8. "UAE,Upstream Address Enable" "0: The received frame is without the address field:..,1: The received frame has the address field: a 16.." bitfld.long 0x14 4. "SAM,Self Addressing Mode field" "0: Frame loaded into UFRn at UREGCR[FADD].,1: Frame loaded at receiving address. So with SAM=1.." newline bitfld.long 0x14 0.--1. "FADD,Frames Addressing" "0: UFR0 Upstream Frame Register.,1: UFR1 Upstream Frame Register.,2: UFR2 Upstream Frame Register.,3: UFR3 Upstream Frame Register." line.long 0x18 "UFINTR,Upstream Buffers INTerrupt Register" bitfld.long 0x18 28. "EN_OWRERF,Enable Overwrite Error Frame" "0: The rx_owrerf interrupt request is disabled for..,1: The rx_owrerf interrupt request is enabled for.." bitfld.long 0x18 27. "EN_STOPBERF,Enable Stop Bit Error Frame" "0: The rx_stopbiterf interrupt request is disabled..,1: The rx_stopbiterf interrupt request is enabled.." newline bitfld.long 0x18 26. "EN_PARERF,Enable Parity Error Frame" "0: The rx_paref interrupt request is disabled for..,1: The rx_paref interrupt request is enabled for UCF." bitfld.long 0x18 25. "EN_CONSBERF,Enable Consistency Bit Error Frame" "0: The rx_consbiterf interrupt request is disabled..,1: The rx_consbiterf interrupt request is enabled.." newline bitfld.long 0x18 24. "EN_NEWF,Enable New Frame" "0: The rx_newf interrupt request is disabled for UCF.,1: The rx_newf interrupt request is enabled for UCF." bitfld.long 0x18 20. "OWRERF,Overwrite Error Frame" "0: The OWRERF pending bit is cleared setting by SW..,1: The OWRERF pending bit is set by HW when on a.." newline bitfld.long 0x18 19. "STOPBERF,Stop Bit Error Frame" "0: The STOPBERF pending bit is cleared setting by..,1: The STOPBERF pending bit is set by HW when one.." bitfld.long 0x18 18. "PARERF,Parity Error Frame" "0: The PARERF pending bit is cleared setting by SW..,1: The PARERF pending bit is set by HW only and it.." newline bitfld.long 0x18 17. "CONSBITERF,Consistency Bit Error Frame" "0: The CONSBITERF pending bit is cleared by a SW..,1: The CONSBITERF pending bit is set by HW only.." bitfld.long 0x18 16. "NEWF,New Frame" "0: The NEWF pending bit is cleared by a SW setting.,1: The NEWF pending bit is set by HW only when a.." newline bitfld.long 0x18 15. "PARITY,Frame Parity" "0: The received upstream has parity 0.,1: The received upstream has parity 1." bitfld.long 0x18 12.--14. "STOP,Frame Stop bits field" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 8.--11. 1. "ADD,Frame Address" hexmask.long.byte 0x18 0.--7. 1. "DATA,Frame DATA" line.long 0x1C "UFIFOFR,Upstream FIFO Flag Register" bitfld.long 0x1C 30.--31. "URX_RGFI,Upstream Receiver Register FIFO" "0: both UCF and UFRn disabled.,1: UCF disabled UFRn enabled.,2: UCF enabled not in DMA UFRn disabled.,3: UCF enabled in DMA UFRn disabled." bitfld.long 0x1C 29. "UCF_DMARUN,Upstream Circular FIFO DMA Running" "0: The DMA UCF interface is not working.,1: The DMA UCF interface is working." newline bitfld.long 0x1C 28. "UCF_DMAREQ,Upstream Circular FIFO DMA Request" "0: DMA request is '0'.,1: DMA request is '1'." bitfld.long 0x1C 27. "UCF_FULL,Upstream Circular FIFO Full" "0: The UCF_FULL pending bit is cleared setting by..,1: The UCF_FULL pending bit is set by HW when the.." newline bitfld.long 0x1C 26. "UCF_TVR,Upstream Circular FIFO Threshold Value Reached" "0: The UCF_TVR pending bit is cleared because the..,1: The UCF_TVR pending bit has set because once.." bitfld.long 0x1C 25. "UCF_EMPTY,Upstream Circular FIFO Empty" "0: The UCF_EMPTY pending bit is cleared by setting..,1: The UCF_EMPTY pending bit is set by HW when the.." newline hexmask.long.byte 0x1C 16.--19. 1. "UCF_CT,UCF_CT" bitfld.long 0x1C 9. "UCF_PTRNC,UCF_PTRNC" "0: No rx_ucf_ptrnc interrupt pending.,1: rx_ucf_ptrnc interrupt is pending." newline bitfld.long 0x1C 8. "UCF_PTRCL,UCF_PTRCL" "0: A UCF read/write pointers clearing has been..,1: UCF read/write pointers clearing is running." line.long 0x20 "UFIFOCR,Upstream FIFO Control Register" bitfld.long 0x20 31. "UCF_EN,Upstream Circular FIFO On" "0: The Upstream Circular FIFO is disabled.,1: The Upstream Circular FIFO is enabled." bitfld.long 0x20 30. "UCF_DMA,Upstream Circular FIFO DMA" "0: The enabled Upstream Circular FIFO is accessible..,1: The enabled Upstream Circular FIFO is accessible.." newline bitfld.long 0x20 27. "EN_UCF_FULL,Enable Upstream Circular FIFO FULL" "0: Disable any rx_ucf_full interrupt request.,1: Enable the rx_ucf_full interrupt request coming.." bitfld.long 0x20 26. "EN_UCF_TVR,Enable Upstream Circular FIFO Threshold Value Reached" "0: Disable any rx_ucf_tvr interrupt request.,1: Enable the rx_ucf_tvr interrupt request coming.." newline bitfld.long 0x20 25. "EN_UCF_EMPTY,Enable Upstream Circular FIFO Empty" "0: Disable any rx_ucf_empty interrupt request.,1: Enable the rx_ucf_empty interrupt request coming.." bitfld.long 0x20 16.--18. "UCF_TV,Upstream Circular FIFO Threshold Value" "0: When UFIFOFR[UCF_CT] is equal to 0x1: then..,1: When UFIFOFR[UCF_CT] is equal to 2 then..,2: When UFIFOFR[UCF_CT] is equal to 3 then..,3: When UFIFOFR[UCF_CT] is equal to 4 then..,4: When UFIFOFR[UCF_CT] is equal to 5 then..,5: When UFIFOFR[UCF_CT] is equal to 6 then..,6: When UFIFOFR[UCF_CT] is equal to 7 then..,7: When UFIFOFR[UCF_CT] is equal to 8 then.." newline bitfld.long 0x20 9. "EN_UCF_PTRNC,Enable Upstream Circular FIFO read/write POINTERS Not Cleared" "0: Disable any rx_ucf_ptrnc interrupt request.,1: Enable the rx_ucf_ptrnc interrupt request on.." line.long 0x24 "UECR,Upstream Event Counter Register" bitfld.long 0x24 31. "EN_UNMATCH,Enable Unmatch" "0: The rx_unmatch interrupt is disabled.,1: The rx_unmatch interrupt is enabled." bitfld.long 0x24 30. "UNMATCH,Unmatch flag" "0: The UNMATCH pending bit is cleared setting by SW..,1: The UNMATCH pending bit is set by HW only when.." newline bitfld.long 0x24 27. "STOP0_RUN1,Stop 0 Run 1" "0: The clear stops the down counter and display..,1: The current baud frequency stops the down.." bitfld.long 0x24 24.--26. "EVENTS_OFF,Events number Off" "0: 0 oct,1: 1 oct,2: 2 oct,?,?,?,?,7: 7 oct" newline bitfld.long 0x24 23. "FREER0_SINGLES1,Free Running at 0 Single Shot at 1 mode" "0: On clear it is in free-running mode once the..,1: On set it is in single-shot mode once the down.." bitfld.long 0x24 20.--22. "EVENTS_MIN,Events Minimum number" "0: 0 oct,1: 1 oct,2: 2 oct,?,?,?,?,7: 7 oct" newline hexmask.long.byte 0x24 16.--19. 1. "EVENTS_END,Rx Events on last End Unmatch" hexmask.long.word 0x24 0.--15. 1. "UCYCLESN,Upstream Cycles Number" wgroup.long 0x70++0x3 line.long 0x0 "DFIFOR,Downstream FIFO Register" hexmask.long 0x0 0.--31. 1. "DFIFO,Downstream FIFO frame. A write by SW or by DMA will push the written frame into the Downstream FIFO DCF." group.long 0x74++0x7 line.long 0x0 "DFIFOFR,Downstream FIFO Flag Register" bitfld.long 0x0 30.--31. "DTX_DMAINT,Downstream Transmitter DMA/Interrupt" "0: Both DCF and DMA disabled.,1: Not possible. DFIFOCR[DCF_EN] ='0'..,2: Interrupt/Polling mode for the DCF enabled.,3: DMA mode for the DCF enabled." bitfld.long 0x0 29. "DCF_DMARUN,Downstream Circular FIFO DMA Running" "0: The DMA interface is not working.,1: The DMA interface is working." newline bitfld.long 0x0 28. "DCF_DMAREQ,Downstream Circular FIFO DMA Request" "0: No DMA request is running.,1: A DMA request is running." bitfld.long 0x0 27. "DCF_FULL,Downstream Circular FIFO FULL" "0: The DCF_FULL pending bit is cleared.,1: The DCF_FULL pending bit is set by HW when the.." newline bitfld.long 0x0 26. "DCF_TVR,Downstream Circular FIFO Threshold Value Reached" "0: The DCF_TVR bit is cleared.,1: The DCF_TVR bit is set meaning that the.." bitfld.long 0x0 25. "DCF_EMPTY,Downstream Circular FIFO Empty" "0: The DCF_EMPTY pending bit is cleared.,1: The DCF_EMPTY pending bit is set the DCF is.." newline hexmask.long.byte 0x0 16.--19. 1. "DCF_CT,Downstream Circular FIFO Current Threshold" bitfld.long 0x0 8. "DCF_PTRCL,Downstream Circular FIFO read/write Pointers Clear action" "0: A DCF read/write pointers clearing has been done..,1: DCF read/write pointers clearing is running." line.long 0x4 "DFIFOCR,Downstream FIFO Control Register" bitfld.long 0x4 31. "DCF_EN,Downstream Circular FIFO Enable" "0: The Downstream Circular FIFO is disabled.,1: The Downstream Circular FIFO is Enabled." bitfld.long 0x4 30. "DCF_DMA,Downstream Circular FIFO DMA Selection" "0: The Downstream Circular FIFO is manageable by..,1: The Downstream Circular FIFO is manageable by.." newline bitfld.long 0x4 27. "EN_DCF_FULL,ENable Downstream Circular FIFO Full" "0: Disable any tx_dcf_full interrupt request.,1: Enable the tx_dcf_full interrupt request coming.." bitfld.long 0x4 26. "EN_DCF_TVR,ENable Downstream Circular FIFO Threshold Value Reached" "0: Disable any tx_dcf_tvr interrupt request.,1: Enable the tx_dcf_tvr interrupt request coming.." newline bitfld.long 0x4 25. "EN_DCF_EMPTY,ENable Downstream Circular FIFO Empty" "0: Disable any tx_dcf_empty interrupt request.,1: Enable the tx_dcf_empty interrupt request coming.." bitfld.long 0x4 16.--18. "DCF_TV,Downstream Circular FIFO Threshold Value" "0: When DFIFOFR[DCF_CT] is equal to 0 then..,1: When DFIFOFR[DCF_CT] is equal to 1 then..,2: When DFIFOFR[DCF_CT] is equal to 2 then..,3: When DFIFOFR[DCF_CT] is equal to 3 then..,4: When DFIFOFR[DCF_CT] is equal to 4 then..,5: When DFIFOFR[DCF_CT] is equal to 5 then..,6: When DFIFOFR[DCF_CT] is equal to 6 then..,7: When DFIFOFR[DCF_CT] is equal to 7 then.." rgroup.long 0x7C++0x3 line.long 0x0 "DSR,Downstream Status Register" bitfld.long 0x0 4. "DGT32OR_REQ,DGT32OR update request status bit" "0: DGT32OR register can be updated by SW.,1: DGT32OR has been written by SW and the TX kernel.." bitfld.long 0x0 3. "DFI64OR_REQ,DFI64OR update request status bit" "0: DFI64OR register can be updated by SW.,1: DFI64OR has been written by SW and the TX kernel.." newline bitfld.long 0x0 2. "DTSCR_REQ,DTSCR update request status bit" "0: DTSCR register can be update by SW.,1: DTSCR has been written by SW and the TX kernel.." bitfld.long 0x0 1. "MSCIOR_REQ,MSCIOR update request status bit" "0: MSCIOR register can be updated by SW.,1: MSCIOR has been written by SW and the TX kernel.." newline bitfld.long 0x0 0. "TX_IDLE,Downstream transmitter status bit" "0: A frame transmission is in progress.,1: The asynchronous TX FIFO inside the Downstream.." group.long 0x80++0x6F line.long 0x0 "DH64FR,Downstream High 64-bit Frame Register" hexmask.long 0x0 0.--31. 1. "DH64F,DH64F is a Read/Write bit field which stores the high part bits from 32 up to 63 of a single receiver frame or the data for the second receiver of a dual receiver data frame." line.long 0x4 "DL64FR,Downstream Low 64-bit Frame Register" hexmask.long 0x4 0.--31. 1. "DL64F,DL64F is a Read/Write register field which stores the low part bits from 0 up to 31 of a single receiver frame or the data for the first receiver and eventually also the second receiver of a dual receiver data frame." line.long 0x8 "DHTSFR,Downstream High Generic Timers Frame Register" hexmask.long 0x8 0.--31. 1. "DHGTF,Downstream High Generic Timers Frame" line.long 0xC "DLTSFR,Downstream Low Generic Timers Frame Register" hexmask.long 0xC 0.--31. 1. "DLGTF,Downstream Low Generic Timers Frame" line.long 0x10 "D32FR,Downstream 32-bit Frame Register" hexmask.long 0x10 0.--31. 1. "D32F,Downstream 32 Frame" line.long 0x14 "D64SUR,Downstream 64-bit Set Up Register" bitfld.long 0x14 31. "DS_64,Data Selection bit in a 64 bits TX" "0: It means the single receiver Data frame has not..,1: It means the single receiver Data frame has a.." bitfld.long 0x14 30. "HDS_64,High Data Selection bit in a 64 bits TX" "0: It means the data transmission for the second..,1: It means the data transmission for the second.." newline hexmask.long.byte 0x14 24.--29. 1. "HDN_64,High Data Number in a 64 bits TX" bitfld.long 0x14 23. "C1D0_64,Command 1 Data 0 bit in a 64 bits Tx" "0: The frame to be transmitted is a Data frame.,1: The frame to be transmitted is a Command frame." newline bitfld.long 0x14 22. "LDS_64,Low Data Selection bit in a 64 bits TX" "0: It means the data transmission for the first..,1: It means the data transmission for the first.." hexmask.long.byte 0x14 16.--21. 1. "LDN_64,Low Data Number in a 64 bits TX" newline bitfld.long 0x14 15. "REQ_64,This bit is set by SW in order to issue a new frame transmission and it is cleared only by HW. The SW can use this bit for polling when to write a new request." "0: No transmission request is pending and a new..,1: A new transmission request has been issued by SW.." hexmask.long.byte 0x14 8.--12. 1. "PPN_64,Passive Phases Number in a 64 bits Tx" newline bitfld.long 0x14 7. "ENN_64,Enable Number bit in a 64 bits Tx" "0: Dual receiver data frame the internal Enables..,1: Single receiver data frame the internal Enable.." hexmask.long.byte 0x14 0.--6. 1. "CDN_64,Command Data 64 bits Number" line.long 0x18 "DGTSUR,Downstream Generic Timers Set Up Register" bitfld.long 0x18 31. "DS_GT,Data Selection bit in a GT TX" "0: It means the single receiver Data frame has not..,1: It means the single receiver Data frame has a.." bitfld.long 0x18 30. "HDS_GT,High Data Selection bit in a GT TX" "0: It means the data transmission for the second..,1: It means the data transmission for the second.." newline hexmask.long.byte 0x18 24.--29. 1. "HDN_GT,High Data Number in a GT TX" bitfld.long 0x18 23. "C1D0_GT,Command 1 Data 0 bit in a GT Tx" "0: The frame to be transmitted is a Data frame.,1: receiver" newline bitfld.long 0x18 22. "LDS_GT,Low Data Selection bit in a GT TX" "0: It means the data transmission for the first..,1: It means the data transmission for the first.." hexmask.long.byte 0x18 16.--21. 1. "LDN_GT,Low Data Number in a GT TX" newline bitfld.long 0x18 15. "REQ_GT,This bit is set by SW or HW in order to issue a new frame transmission and it is cleared only by HW. The SW can use this bit for polling when to write a new request." "0: No transmission request is pending and a new..,1: A new transmission request has been issued by SW.." hexmask.long.byte 0x18 8.--12. 1. "PPN_GT,Passive Phases Number in a GT Tx" newline bitfld.long 0x18 7. "ENN_GT,Enable Number bit in a GT Tx" "0: Dual receiver data frame the internal Enables..,1: Single receiver data frame the internal Enable.." hexmask.long.byte 0x18 0.--6. 1. "CDN_GT,Command Data bits Number in a GT Tx" line.long 0x1C "D32SUR,Downstream 32-bit Set Up Register" bitfld.long 0x1C 31. "DS_32,Data Selection bit in a 32 bits TX" "0: It means the single receiver Data frame has not..,1: It means the single receiver Data frame has a.." bitfld.long 0x1C 30. "HDS_32,High Data Selection bit in a 32 bits TX" "0: It means the data transmission for the second..,1: It means the data transmission for the second.." newline hexmask.long.byte 0x1C 24.--29. 1. "HDN_32,High Data Number in a 32 bits TX" bitfld.long 0x1C 23. "C1D0_32,Command 1 Data 0 bit in a 32 bits Tx" "0: The frame to be transmitted is a Data frame.,1: The frame to be transmitted is a Command frame." newline bitfld.long 0x1C 22. "LDS_32,Low Data Selection bit in a 32 bits TX" "0: It means the data transmission for the first..,1: It means the data transmission for the first.." hexmask.long.byte 0x1C 16.--21. 1. "LDN_32,Low Data Number in a 32 bits TX" newline bitfld.long 0x1C 15. "REQ_32,This bit is set by SW in order to issue a new frame transmission and it is cleared by HW only. The SW can use this bit for polling when to write a new request." "0: No transmission request is pending and a new..,1: A new transmission request has been issued by SW.." hexmask.long.byte 0x1C 8.--12. 1. "PPN_32,Passive Phases Number in a 32 bits Tx" newline bitfld.long 0x1C 7. "ENN_32,Enable Number bit in a 32 bits Tx" "0: Dual receiver data frame the internal Enables..,1: Single receiver data frame the internal Enable.." hexmask.long.byte 0x1C 0.--6. 1. "CDN_32,Command Data bits Number in a 32 bits Tx" line.long 0x20 "DFISUR,Downstream FIFO SetUp Register" bitfld.long 0x20 31. "DS_FI,Data Selection bit in a FI TX" "0: It means the single receiver Data frame has not..,1: It means the single receiver Data frame has a.." bitfld.long 0x20 30. "HDS_FI,High Data Selection bit in a FI TX" "0: It means the data transmission for the second..,1: It means the data transmission for the second.." newline hexmask.long.byte 0x20 24.--29. 1. "HDN_FI,High Data Number in a FI TX" bitfld.long 0x20 23. "C1D0_FI,Command 1 Data 0 bit in a FI Tx" "0: The frame to be transmitted is a Data frame.,1: The frame to be transmitted is a Command frame." newline bitfld.long 0x20 22. "LDS_FI,Low Data Selection bit in a FI TX" "0: It means the data transmission for the first..,1: It means the data transmission for the first.." hexmask.long.byte 0x20 16.--21. 1. "LDN_FI,Low Data Number in a FI TX" newline bitfld.long 0x20 15. "REQ_FI,This bit is set by SW or HW in order to issue a new frame transmission and it is cleared only by HW. The SW can use this bit for polling when to write a new request." "0: No transmission request is pending and a new..,1: A new transmission request has been issued by SW.." hexmask.long.byte 0x20 8.--12. 1. "PPN_FI,Passive Phases Number in a FI Tx" newline bitfld.long 0x20 7. "ENN_FI,Enable Number bit in a FI Tx" "0: Dual receiver data frame the internal Enables..,1: Single receiver data frame the internal Enable.." hexmask.long.byte 0x20 0.--6. 1. "CDN_FI,Command Data bits Number in a FI Tx" line.long 0x24 "DGT32OR,Downstream GT/32 Output Register" bitfld.long 0x24 31. "EN_GT,ENable GT 64-bit frames" "0: The DGTSUR register is not writable by SW.,1: The DGTSUR register is writable by SW." bitfld.long 0x24 24.--26. "ENO_GT,ENable to Output GT source configuration bit" "0: msc_deo[0] IP Output displays en.,1: msc_deo[1] IP Output displays en.,2: msc_deo[2] IP Output displays en.,3: msc_deo[3] IP Output displays en.,4: msc_deo[4] IP Output displays en.,5: msc_deo[5] IP Output displays en.,6: msc_deo[6] IP Output displays en.,7: msc_deo[7] IP Output displays en." newline bitfld.long 0x24 20.--22. "HENO_GT,High ENable to Output GT source configuration bit" "0: msc_deo[0] IP Output displays hen.,1: msc_deo[1] IP Output displays hen.,2: msc_deo[2] IP Output displays hen.,3: msc_deo[3] IP Output displays hen.,4: msc_deo[4] IP Output displays hen.,5: msc_deo[5] IP Output displays hen.,6: msc_deo[6] IP Output displays hen.,7: msc_deo[7] IP Output displays hen." bitfld.long 0x24 16.--18. "LENO_GT,Low ENable to Output GT source configuration bit" "0: msc_deo[0] IP Output displays len.,1: msc_deo[1] IP Output displays len.,2: msc_deo[2] IP Output displays len.,3: msc_deo[3] IP Output displays len.,4: msc_deo[4] IP Output displays len.,5: msc_deo[5] IP Output displays len.,6: msc_deo[6] IP Output displays len.,7: msc_deo[7] IP Output displays len." newline bitfld.long 0x24 15. "EN_32,ENable 32 32-bit frames" "0: The D32SUR register is not writable by SW.,1: The D32SUR register is writable by SW." bitfld.long 0x24 8.--10. "ENO_32,Enable to Output 32 source configuration bit" "0: msc_deo[0] IP Output displays en.,1: msc_deo[1] IP Output displays en.,2: msc_deo[2] IP Output displays en.,3: msc_deo[3] IP Output displays en.,4: msc_deo[4] IP Output displays en.,5: msc_deo[5] IP Output displays en.,6: msc_deo[6] IP Output displays en.,7: msc_deo[7] IP Output displays en." newline bitfld.long 0x24 4.--6. "HENO_32,High Enable to Output 32 source configuration bit" "0: msc_deo[0] IP Output displays hen.,1: msc_deo[1] IP Output displays hen.,2: msc_deo[2] IP Output displays hen.,3: msc_deo[3] IP Output displays hen.,4: msc_deo[4] IP Output displays hen.,5: msc_deo[5] IP Output displays hen.,6: msc_deo[6] IP Output displays hen.,7: msc_deo[7] IP Output displays hen." bitfld.long 0x24 0.--2. "LENO_32,Low Enable to Output 32 source configuration bit" "0: msc_deo[0] IP Output displays len.,1: msc_deo[1] IP Output displays len.,2: msc_deo[2] IP Output displays len.,3: msc_deo[3] IP Output displays len.,4: msc_deo[4] IP Output displays len.,5: msc_deo[5] IP Output displays len.,6: msc_deo[6] IP Output displays len.,7: msc_deo[7] IP Output displays len." line.long 0x28 "DFI64OR,Downstream FI/64 Output Register" bitfld.long 0x28 31. "EN_FI,ENable FI frame source" "0: The DFISUR register is not writable by SW.,1: The DFISUR[31:0] register is writable by SW." bitfld.long 0x28 24.--26. "ENO_FI,ENable to Output FI source configuration bits" "0: msc_deo[0] IP Output displays en.,1: msc_deo[1] IP Output displays en.,2: msc_deo[2] IP Output displays en.,3: msc_deo[3] IP Output displays en.,4: msc_deo[4] IP Output displays en.,5: msc_deo[5] IP Output displays en.,6: msc_deo[6] IP Output displays en.,7: msc_deo[7] IP Output displays en." newline bitfld.long 0x28 20.--22. "HENO_FI,High ENable to Output FI source configuration bits" "0: msc_deo[0] IP Output displays hen.,1: msc_deo[1] IP Output displays hen.,2: msc_deo[2] IP Output displays hen.,3: msc_deo[3] IP Output displays hen.,4: msc_deo[4] IP Output displays hen.,5: msc_deo[5] IP Output displays hen.,6: msc_deo[6] IP Output displays hen.,7: msc_deo[7] IP Output displays hen." bitfld.long 0x28 16.--18. "LENO_FI,Low ENable to Output FI source configuration bits" "0: 0x0: msc_deo[0] IP Output displays len.,1: msc_deo[1] IP Output displays len.,2: msc_deo[2] IP Output displays len.,3: msc_deo[3] IP Output displays len.,4: msc_deo[4] IP Output displays len.,5: msc_deo[5] IP Output displays len.,6: msc_deo[6] IP Output displays len.,7: msc_deo[7] IP Output displays len." newline bitfld.long 0x28 15. "EN_64,ENable 64-bit frames source" "0: The D64SUR register is not writable by SW.,1: The D64SUR register is writable by SW." bitfld.long 0x28 8.--10. "ENO_64,ENable to Output 64-bits source configuration bits" "0: msc_deo[0] IP Output displays en.,1: msc_deo[1] IP Output displays en.,2: msc_deo[2] IP Output displays en.,3: msc_deo[3] IP Output displays en.,4: msc_deo[4] IP Output displays en.,5: msc_deo[5] IP Output displays en.,6: msc_deo[6] IP Output displays en.,7: msc_deo[7] IP Output displays en." newline bitfld.long 0x28 4.--6. "HENO_64,High ENable to Output 64-bits source configuration bits" "0: msc_deo[0] IP Output displays hen.,1: msc_deo[1] IP Output displays hen.,2: msc_deo[2] IP Output displays hen.,3: msc_deo[3] IP Output displays hen.,4: msc_deo[4] IP Output displays hen.,5: msc_deo[5] IP Output displays hen.,6: msc_deo[6] IP Output displays hen.,7: msc_deo[7] IP Output displays hen." bitfld.long 0x28 0.--2. "LENO_64,Low ENable to Output 64-bits source configuration bits" "0: msc_deo[0] IP Output displays len.,1: msc_deo[1] IP Output displays len.,2: msc_deo[2] IP Output displays len.,3: msc_deo[3] IP Output displays len.,4: msc_deo[4] IP Output displays len.,5: msc_deo[5] IP Output displays len.,6: msc_deo[6] IP Output displays len.,7: msc_deo[7] IP Output displays len." line.long 0x2C "DPPMPR,Downstream Passive Phase Modulation Priority Register" bitfld.long 0x2C 28.--29. "PRI_32,PRIority 32-bits source configuration bits" "0: The priority value is 0.,1: The priority value is 1.,2: The priority value is 2.,3: The priority value is 3." bitfld.long 0x2C 24.--25. "PRI_64,PRIority 64-bits source configuration bits" "0: The priority value is 0.,1: The priority value is 1.,2: The priority value is 2.,3: The priority value is 3." newline bitfld.long 0x2C 20.--21. "PRI_GT,PRIority Generic-Timers source configuration bits" "0: The priority value is 0.,1: The priority value is 1.,2: The priority value is 2.,3: The priority value is 3." bitfld.long 0x2C 16.--17. "PRI_FI,Priority FI source configuration bits" "0: The priority value is 0.,1: The priority value is 1.,2: The priority value is 2.,3: The priority value is 3." newline bitfld.long 0x2C 8. "ENH_32B,Enable High on dedicated 32-bit register" "0: Only the low register of a 64-bits source is..,1: Both the high and low register of a 64-bits.." bitfld.long 0x2C 6. "PPM,Passive Phase Modulation" "0: The passive phase modulation is not enabled.,1: The passive phase modulation is enabled." line.long 0x30 "DTSCR,Downstream Timer Siul Counter Register" bitfld.long 0x30 31. "H0S1_SAMPLE,Hardware 0 Software 1 SAMPLE. H0S1_SAMPLE is a Read/Write bit field. The H0S1_SAMPLE control bit selects a SW or HW sampling for the input data of the DTSFR source." "0: Hardware sampling from siul_sample input selected.,1: Software sampling from Down-counter EOC selected." bitfld.long 0x30 30. "DSTART_CNT,START CouNTer. DSTART_CNT is a Read/Write bit field. The DSTART_CNT control field starts the counter if it is set otherwise the down-counter is stopped." "0: The counter is stopped.,1: The counter is started." newline hexmask.long.tbyte 0x30 0.--23. 1. "DCYCLESN,Downstream CYCLES Number" line.long 0x34 "DHTSMR,Downstream High Timers SIUL Mux Register" hexmask.long 0x34 0.--31. 1. "DHTSM,Downstream High SIUL Mux" line.long 0x38 "DLTSMR,Downstream Low Timers SIUL Mux Register" hexmask.long 0x38 0.--31. 1. "DLTSM,Downstream Low Timers SIUL Mux" line.long 0x3C "DFR,Downstream Flag Register" bitfld.long 0x3C 31. "EN_NOPEND_32REQ,This bit enable/disable the corresponding NOPEND_32REQ interrupt." "0: The NOPEND_32REQ interrupt is disabled.,1: The NOPEND_32REQ interrupt is enabled." bitfld.long 0x3C 30. "NOPEND_32REQ,Interrupt bit for the 32 bits frame source." "0: A request is pending.,1: A new request can be issued by the SW." newline bitfld.long 0x3C 29. "EN_NOPEND_64REQ,This bit enable/disable the corresponding NOPEND_64REQ interrupt." "0: The NOPEND_64REQ interrupt is disabled.,1: The NOPEND_64REQ interrupt is enabled." bitfld.long 0x3C 28. "NOPEND_64REQ,Interrupt bit for the 64 bits frame source." "0: A request is pending.,1: A new request can be issued by the SW." newline bitfld.long 0x3C 27. "EN_NOPEND_FIREQ,This bit enable/disable the corresponding NOPEND_64REQ interrupt." "0: The NOPEND_FIREQ interrupt is disabled.,1: The NOPEND_FIREQ interrupt is enabled." bitfld.long 0x3C 26. "NOPEND_FIREQ,Interrupt bit for the Downstream Circular FIFO DCF frame source." "0: A request is pending.,1: A new request can be issued by SW or by HW." newline bitfld.long 0x3C 25. "EN_NOPEND_GTREQ,This bit enable/disable the corresponding NOPEND_GTREQ interrupt." "0: The NOPEND_GTREQ interrupt is disabled.,1: The NOPEND_GTREQ interrupt is enabled." bitfld.long 0x3C 24. "NOPEND_GTREQ,Interrupt bit for the DTSFR frame source." "0: A request is pending.,1: A new request can be issued by SW or by HW." line.long 0x40 "DHPISR0,Downstream Hardware Parallel Input Select Register 0" hexmask.long.byte 0x40 28.--31. 1. "DHPIS7,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x40 24.--27. 1. "DHPIS6,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x40 20.--23. 1. "DHPIS5,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x40 16.--19. 1. "DHPIS4,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x40 12.--15. 1. "DHPIS3,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x40 8.--11. 1. "DHPIS2,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x40 4.--7. 1. "DHPIS1,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x40 0.--3. 1. "DHPIS0,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x44 "DHPISR1,Downstream Hardware Parallel Input Select Register 1" hexmask.long.byte 0x44 28.--31. 1. "DHPIS15,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x44 24.--27. 1. "DHPIS14,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x44 20.--23. 1. "DHPIS13,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x44 16.--19. 1. "DHPIS12,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x44 12.--15. 1. "DHPIS11,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x44 8.--11. 1. "DHPIS10,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x44 4.--7. 1. "DHPIS9,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x44 0.--3. 1. "DHPIS8,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x48 "DHPISR2,Downstream Hardware Parallel Input Select Register 2" hexmask.long.byte 0x48 28.--31. 1. "DHPIS23,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x48 24.--27. 1. "DHPIS22,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x48 20.--23. 1. "DHPIS21,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x48 16.--19. 1. "DHPIS20,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x48 12.--15. 1. "DHPIS19,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x48 8.--11. 1. "DHPIS18,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x48 4.--7. 1. "DHPIS17,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x48 0.--3. 1. "DHPIS16,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x4C "DHPISR3,Downstream Hardware Parallel Input Select Register 3" hexmask.long.byte 0x4C 28.--31. 1. "DHPIS31,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x4C 24.--27. 1. "DHPIS30,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x4C 20.--23. 1. "DHPIS29,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x4C 16.--19. 1. "DHPIS28,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x4C 12.--15. 1. "DHPIS27,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x4C 8.--11. 1. "DHPIS26,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x4C 4.--7. 1. "DHPIS25,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x4C 0.--3. 1. "DHPIS24,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x50 "DHPISR4,Downstream Hardware Parallel Input Select Register 4" hexmask.long.byte 0x50 28.--31. 1. "DHPIS39,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x50 24.--27. 1. "DHPIS38,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x50 20.--23. 1. "DHPIS37,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x50 16.--19. 1. "DHPIS36,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x50 12.--15. 1. "DHPIS35,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x50 8.--11. 1. "DHPIS34,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x50 4.--7. 1. "DHPIS33,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x50 0.--3. 1. "DHPIS32,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x54 "DHPISR5,Downstream Hardware Parallel Input Select Register 5" hexmask.long.byte 0x54 28.--31. 1. "DHPIS47,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x54 24.--27. 1. "DHPIS46,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x54 20.--23. 1. "DHPIS45,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x54 16.--19. 1. "DHPIS44,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x54 12.--15. 1. "DHPIS43,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x54 8.--11. 1. "DHPIS42,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x54 4.--7. 1. "DHPIS41,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x54 0.--3. 1. "DHPIS40,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x58 "DHPISR6,Downstream Hardware Parallel Input Select Register 6" hexmask.long.byte 0x58 28.--31. 1. "DHPIS55,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x58 24.--27. 1. "DHPIS54,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x58 20.--23. 1. "DHPIS53,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x58 16.--19. 1. "DHPIS52,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x58 12.--15. 1. "DHPIS51,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x58 8.--11. 1. "DHPIS50,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x58 4.--7. 1. "DHPIS49,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x58 0.--3. 1. "DHPIS48,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x5C "DHPISR7,Downstream Hardware Parallel Input Select Register 7" hexmask.long.byte 0x5C 28.--31. 1. "DHPIS63,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x5C 24.--27. 1. "DHPIS62,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x5C 20.--23. 1. "DHPIS61,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x5C 16.--19. 1. "DHPIS60,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x5C 12.--15. 1. "DHPIS59,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x5C 8.--11. 1. "DHPIS58,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x5C 4.--7. 1. "DHPIS57,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x5C 0.--3. 1. "DHPIS56,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x60 "DHSBSR,Downstream High SIUL By Software Register" hexmask.long 0x60 0.--31. 1. "DHSBSW,Downstream High SIUL By Software" line.long 0x64 "DLSBSR,Downstream Low SIUL By Software Register" hexmask.long 0x64 0.--31. 1. "DLSBSW,Downstream Low SIUL By Software" line.long 0x68 "DHSBHR,Downstream High SIUL By Hardware Register" hexmask.long 0x68 0.--31. 1. "DHSBHW,Downstream High SIUL By Hardware" line.long 0x6C "DLSBHR,Downstream Low SIUL By Hardware Register" hexmask.long 0x6C 0.--31. 1. "DLSBHW,Downstream Low SIUL By Hardware" tree.end tree "MSC_1" base ad:0x71438000 group.long 0x0++0x7 line.long 0x0 "MSCCCR,MSC Clock Control Register" bitfld.long 0x0 16. "EN_RX_RSTN,ENable RX ReSeTN. EN_RX_RSTN is a Read/Write bit field. The EN_RX_RSTN bit enables an HW Synchronous Reset on all MSC RX of msc_uck domain circuitry triggered when [UECR]UNMATCH asserts." "0: The [UECR]UNMATCH never resets the MSC RX..,1: On [UECR]UNMATCH field asserting the MSC RX.." hexmask.long.byte 0x0 0.--7. 1. "MSCCK_DIV,MSC ClocK DIVider. MSCCK_DIV is a 8-bits Read/Write field. According to the following definition the msc_clk clock frequency is divisible for: 4 6 8 10 12 16 20 24 40." line.long 0x4 "MSCIOR,MSC Inputs Outputs Register" bitfld.long 0x4 19. "CKP,Clock Polarity" "0: Normal polarity.,1: Inverse polarity." bitfld.long 0x4 18. "CKA,Clock always Active" "0: It means msc_dclk is active only when enables..,1: It means msc_dclk is always active." newline bitfld.long 0x4 17. "CK_DIFF,Clock output Differential" "0: The MSC msc_dclk Downstream Clock is not in..,1: The MSC msc_dclk Downstream Clock is in.." bitfld.long 0x4 16. "CK_OBE,ClocK Output Buffer Enable" "0: The MSC msc_dclk Downstream clock output is not..,1: The MSC msc_dclk Downstream clock output is.." newline bitfld.long 0x4 4. "ENP,Enable Polarity" "0: Normal polarity.,1: " bitfld.long 0x4 3. "DSOP,Downstream Serial Output Polarity register" "0: Normal polarity.,1: Inverse polarity." newline bitfld.long 0x4 1. "DSO_DIFF,Data Serial Output Differential" "0: The MSC msc_dso Downstream Serial data Out is..,1: The MSC msc_dso Downstream Serial data Out is in.." bitfld.long 0x4 0. "DSO_OBE,Data Serial Output Buffer Enable" "0: The MSC msc_dso Downstream Serial data Out is..,1: The MSC msc_dso Downstream Serial data Out is.." rgroup.long 0xC++0x3 line.long 0x0 "UFIFOR,Upstream FIFO Register" hexmask.long 0x0 0.--31. 1. "UFIFO,Upstream FIFO frame" group.long 0x10++0x27 line.long 0x0 "UFR0,Upstream Frame Register 0" bitfld.long 0x0 28. "EN_OWRERF,Enable Overwrite Error Frame" "0: The rx_owrerf interrupt request is disabled in..,1: The rx_owrerf interrupt request is enabled in.." bitfld.long 0x0 27. "EN_STOPBERF,Enable Stop Bit Error Frame" "0: The rx_stopbiterf interrupt request is disabled..,1: The rx_stopbiterf interrupt request is enabled.." newline bitfld.long 0x0 26. "EN_PARERF,Enable Parity Error Frame n" "0: The rx_parerf interrupt request is disabled in..,1: The rx_parerf interrupt request is enabled in.." bitfld.long 0x0 25. "EN_CONSBERF,Enable Consistency Bit Error Frame" "0: The rx_consbiterf interrupt request is disabled..,1: The rx_consbiterf interrupt request is enabled.." newline bitfld.long 0x0 24. "EN_NEWF,Enable New Frame" "0: The rx_newf interrupt request is disabled in UFRn.,1: The rx_newf interrupt request is enabled in UFRn." bitfld.long 0x0 20. "OWRERF,Overwrite Error Frame" "0: The OWRERF pending bit is cleared setting by SW..,1: The OWRERF pending bit is set by HW when on a.." newline bitfld.long 0x0 19. "STOPBERF,Stop Bit Error Frame" "0: The STOPBERF pending bit is cleared setting by..,1: The STOPBERF pending bit is set by HW when one.." bitfld.long 0x0 18. "PARERF,Parity Error Frame" "0: The PARERF pending bit is cleared setting by SW..,1: The PARERF pending bit is set by HW only and it.." newline bitfld.long 0x0 17. "CONSBITERF,Consistency Bit Error Frame n" "0: The CONSBERF pending bit is cleared by a SW..,1: The CONSBERF pending bit is set by HW only when.." bitfld.long 0x0 16. "NEWF,New Frame" "0: The NEWF pending bit is cleared by a SW setting.,1: The NEWF pending bit is set by HW only when a.." newline bitfld.long 0x0 15. "PARITY,UFRn Parity field" "0: The received upstream has parity 0.,1: The received upstream has parity 1." bitfld.long 0x0 12.--14. "STOP,UFRn Stop bits" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ADD,UFRn Address" hexmask.long.byte 0x0 0.--7. 1. "DATA,UFRn Data" line.long 0x4 "UFR1,Upstream Frame Register 1" bitfld.long 0x4 28. "EN_OWRERF,Enable Overwrite Error Frame" "0: The rx_owrerf interrupt request is disabled in..,1: The rx_owrerf interrupt request is enabled in.." bitfld.long 0x4 27. "EN_STOPBERF,Enable Stop Bit Error Frame" "0: The rx_stopbiterf interrupt request is disabled..,1: The rx_stopbiterf interrupt request is enabled.." newline bitfld.long 0x4 26. "EN_PARERF,Enable Parity Error Frame n" "0: The rx_parerf interrupt request is disabled in..,1: The rx_parerf interrupt request is enabled in.." bitfld.long 0x4 25. "EN_CONSBERF,Enable Consistency Bit Error Frame" "0: The rx_consbiterf interrupt request is disabled..,1: The rx_consbiterf interrupt request is enabled.." newline bitfld.long 0x4 24. "EN_NEWF,Enable New Frame" "0: The rx_newf interrupt request is disabled in UFRn.,1: The rx_newf interrupt request is enabled in UFRn." bitfld.long 0x4 20. "OWRERF,Overwrite Error Frame" "0: The OWRERF pending bit is cleared setting by SW..,1: The OWRERF pending bit is set by HW when on a.." newline bitfld.long 0x4 19. "STOPBERF,Stop Bit Error Frame" "0: The STOPBERF pending bit is cleared setting by..,1: The STOPBERF pending bit is set by HW when one.." bitfld.long 0x4 18. "PARERF,Parity Error Frame" "0: The PARERF pending bit is cleared setting by SW..,1: The PARERF pending bit is set by HW only and it.." newline bitfld.long 0x4 17. "CONSBITERF,Consistency Bit Error Frame n" "0: The CONSBERF pending bit is cleared by a SW..,1: The CONSBERF pending bit is set by HW only when.." bitfld.long 0x4 16. "NEWF,New Frame" "0: The NEWF pending bit is cleared by a SW setting.,1: The NEWF pending bit is set by HW only when a.." newline bitfld.long 0x4 15. "PARITY,UFRn Parity field" "0: The received upstream has parity 0.,1: The received upstream has parity 1." bitfld.long 0x4 12.--14. "STOP,UFRn Stop bits" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "ADD,UFRn Address" hexmask.long.byte 0x4 0.--7. 1. "DATA,UFRn Data" line.long 0x8 "UFR2,Upstream Frame Register 2" bitfld.long 0x8 28. "EN_OWRERF,Enable Overwrite Error Frame" "0: The rx_owrerf interrupt request is disabled in..,1: The rx_owrerf interrupt request is enabled in.." bitfld.long 0x8 27. "EN_STOPBERF,Enable Stop Bit Error Frame" "0: The rx_stopbiterf interrupt request is disabled..,1: The rx_stopbiterf interrupt request is enabled.." newline bitfld.long 0x8 26. "EN_PARERF,Enable Parity Error Frame n" "0: The rx_parerf interrupt request is disabled in..,1: The rx_parerf interrupt request is enabled in.." bitfld.long 0x8 25. "EN_CONSBERF,Enable Consistency Bit Error Frame" "0: The rx_consbiterf interrupt request is disabled..,1: The rx_consbiterf interrupt request is enabled.." newline bitfld.long 0x8 24. "EN_NEWF,Enable New Frame" "0: The rx_newf interrupt request is disabled in UFRn.,1: The rx_newf interrupt request is enabled in UFRn." bitfld.long 0x8 20. "OWRERF,Overwrite Error Frame" "0: The OWRERF pending bit is cleared setting by SW..,1: The OWRERF pending bit is set by HW when on a.." newline bitfld.long 0x8 19. "STOPBERF,Stop Bit Error Frame" "0: The STOPBERF pending bit is cleared setting by..,1: The STOPBERF pending bit is set by HW when one.." bitfld.long 0x8 18. "PARERF,Parity Error Frame" "0: The PARERF pending bit is cleared setting by SW..,1: The PARERF pending bit is set by HW only and it.." newline bitfld.long 0x8 17. "CONSBITERF,Consistency Bit Error Frame n" "0: The CONSBERF pending bit is cleared by a SW..,1: The CONSBERF pending bit is set by HW only when.." bitfld.long 0x8 16. "NEWF,New Frame" "0: The NEWF pending bit is cleared by a SW setting.,1: The NEWF pending bit is set by HW only when a.." newline bitfld.long 0x8 15. "PARITY,UFRn Parity field" "0: The received upstream has parity 0.,1: The received upstream has parity 1." bitfld.long 0x8 12.--14. "STOP,UFRn Stop bits" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "ADD,UFRn Address" hexmask.long.byte 0x8 0.--7. 1. "DATA,UFRn Data" line.long 0xC "UFR3,Upstream Frame Register 3" bitfld.long 0xC 28. "EN_OWRERF,Enable Overwrite Error Frame" "0: The rx_owrerf interrupt request is disabled in..,1: The rx_owrerf interrupt request is enabled in.." bitfld.long 0xC 27. "EN_STOPBERF,Enable Stop Bit Error Frame" "0: The rx_stopbiterf interrupt request is disabled..,1: The rx_stopbiterf interrupt request is enabled.." newline bitfld.long 0xC 26. "EN_PARERF,Enable Parity Error Frame n" "0: The rx_parerf interrupt request is disabled in..,1: The rx_parerf interrupt request is enabled in.." bitfld.long 0xC 25. "EN_CONSBERF,Enable Consistency Bit Error Frame" "0: The rx_consbiterf interrupt request is disabled..,1: The rx_consbiterf interrupt request is enabled.." newline bitfld.long 0xC 24. "EN_NEWF,Enable New Frame" "0: The rx_newf interrupt request is disabled in UFRn.,1: The rx_newf interrupt request is enabled in UFRn." bitfld.long 0xC 20. "OWRERF,Overwrite Error Frame" "0: The OWRERF pending bit is cleared setting by SW..,1: The OWRERF pending bit is set by HW when on a.." newline bitfld.long 0xC 19. "STOPBERF,Stop Bit Error Frame" "0: The STOPBERF pending bit is cleared setting by..,1: The STOPBERF pending bit is set by HW when one.." bitfld.long 0xC 18. "PARERF,Parity Error Frame" "0: The PARERF pending bit is cleared setting by SW..,1: The PARERF pending bit is set by HW only and it.." newline bitfld.long 0xC 17. "CONSBITERF,Consistency Bit Error Frame n" "0: The CONSBERF pending bit is cleared by a SW..,1: The CONSBERF pending bit is set by HW only when.." bitfld.long 0xC 16. "NEWF,New Frame" "0: The NEWF pending bit is cleared by a SW setting.,1: The NEWF pending bit is set by HW only when a.." newline bitfld.long 0xC 15. "PARITY,UFRn Parity field" "0: The received upstream has parity 0.,1: The received upstream has parity 1." bitfld.long 0xC 12.--14. "STOP,UFRn Stop bits" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "ADD,UFRn Address" hexmask.long.byte 0xC 0.--7. 1. "DATA,UFRn Data" line.long 0x10 "UKERCR,Upstream Kernel Control Register" bitfld.long 0x10 31. "US_REQ,Upstream Setup Request" "0: The USREQ is cleared by HW a clk cycle after its..,1: The USREQ setting is kept for one clk cycle only." bitfld.long 0x10 30. "US_ACK,Upstream Setup Acknowledge" "0: Meanwhile the new set up values are loaded to..,1: The Rx kernel has received the new setup values." newline bitfld.long 0x10 29. "USRA_R,Upstream Setup Request Acknowledge Reset" "0: Both US_REQ and US_ACK bits can be accessed.,1: Both US_REQ and US_ACK bits are forced low." bitfld.long 0x10 20. "IUIS,Inverted Upstream Input Selector field" "0: The msc_usi input will be evaluated with no..,1: The msc_usi input will be evaluated forcing a.." newline bitfld.long 0x10 16.--18. "USISEL,Upstream Serial Input Selections" "0: Selects the msc_usi[0] input line,1: Selects the msc_usi[1] input line,2: Selects the msc_usi[2] input line,3: Selects the msc_usi[3] input line,4: Selects the msc_usi[4] input line,5: Selects the msc_usi[5] input line,6: Selects the msc_usi[6] input line,7: Selects the msc_usi[7] input line" bitfld.long 0x10 4.--5. "USBN,Upstream Stop Bits Number" "0: 2 Stop Bits,1: 1 Stop Bit,2: 2 Stop Bits,3: 3 Stop Bits" newline bitfld.long 0x10 0.--2. "UBR,Upstream Baud Rate" "0: Rx kernel disabled,1: Baud Rate = fMSC/4,2: Baud Rate = fMSC/8,3: Baud Rate = fMSC/16,4: Baud Rate = fMSC/32,5: Baud Rate = fMSC/64,6: Baud Rate = fMSC/128,7: Baud Rate = fMSC/256" line.long 0x14 "UREGCR,Upstream Registers Control Register" bitfld.long 0x14 31. "UREG_EN,Upstream Register Enable" "0,1" bitfld.long 0x14 12. "UPT,Upstream Parity Type" "0: The msc_usi input will be evaluated with an even..,1: The msc_usi input will be evaluated with an odd.." newline bitfld.long 0x14 8. "UAE,Upstream Address Enable" "0: The received frame is without the address field:..,1: The received frame has the address field: a 16.." bitfld.long 0x14 4. "SAM,Self Addressing Mode field" "0: Frame loaded into UFRn at UREGCR[FADD].,1: Frame loaded at receiving address. So with SAM=1.." newline bitfld.long 0x14 0.--1. "FADD,Frames Addressing" "0: UFR0 Upstream Frame Register.,1: UFR1 Upstream Frame Register.,2: UFR2 Upstream Frame Register.,3: UFR3 Upstream Frame Register." line.long 0x18 "UFINTR,Upstream Buffers INTerrupt Register" bitfld.long 0x18 28. "EN_OWRERF,Enable Overwrite Error Frame" "0: The rx_owrerf interrupt request is disabled for..,1: The rx_owrerf interrupt request is enabled for.." bitfld.long 0x18 27. "EN_STOPBERF,Enable Stop Bit Error Frame" "0: The rx_stopbiterf interrupt request is disabled..,1: The rx_stopbiterf interrupt request is enabled.." newline bitfld.long 0x18 26. "EN_PARERF,Enable Parity Error Frame" "0: The rx_paref interrupt request is disabled for..,1: The rx_paref interrupt request is enabled for UCF." bitfld.long 0x18 25. "EN_CONSBERF,Enable Consistency Bit Error Frame" "0: The rx_consbiterf interrupt request is disabled..,1: The rx_consbiterf interrupt request is enabled.." newline bitfld.long 0x18 24. "EN_NEWF,Enable New Frame" "0: The rx_newf interrupt request is disabled for UCF.,1: The rx_newf interrupt request is enabled for UCF." bitfld.long 0x18 20. "OWRERF,Overwrite Error Frame" "0: The OWRERF pending bit is cleared setting by SW..,1: The OWRERF pending bit is set by HW when on a.." newline bitfld.long 0x18 19. "STOPBERF,Stop Bit Error Frame" "0: The STOPBERF pending bit is cleared setting by..,1: The STOPBERF pending bit is set by HW when one.." bitfld.long 0x18 18. "PARERF,Parity Error Frame" "0: The PARERF pending bit is cleared setting by SW..,1: The PARERF pending bit is set by HW only and it.." newline bitfld.long 0x18 17. "CONSBITERF,Consistency Bit Error Frame" "0: The CONSBITERF pending bit is cleared by a SW..,1: The CONSBITERF pending bit is set by HW only.." bitfld.long 0x18 16. "NEWF,New Frame" "0: The NEWF pending bit is cleared by a SW setting.,1: The NEWF pending bit is set by HW only when a.." newline bitfld.long 0x18 15. "PARITY,Frame Parity" "0: The received upstream has parity 0.,1: The received upstream has parity 1." bitfld.long 0x18 12.--14. "STOP,Frame Stop bits field" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 8.--11. 1. "ADD,Frame Address" hexmask.long.byte 0x18 0.--7. 1. "DATA,Frame DATA" line.long 0x1C "UFIFOFR,Upstream FIFO Flag Register" bitfld.long 0x1C 30.--31. "URX_RGFI,Upstream Receiver Register FIFO" "0: both UCF and UFRn disabled.,1: UCF disabled UFRn enabled.,2: UCF enabled not in DMA UFRn disabled.,3: UCF enabled in DMA UFRn disabled." bitfld.long 0x1C 29. "UCF_DMARUN,Upstream Circular FIFO DMA Running" "0: The DMA UCF interface is not working.,1: The DMA UCF interface is working." newline bitfld.long 0x1C 28. "UCF_DMAREQ,Upstream Circular FIFO DMA Request" "0: DMA request is '0'.,1: DMA request is '1'." bitfld.long 0x1C 27. "UCF_FULL,Upstream Circular FIFO Full" "0: The UCF_FULL pending bit is cleared setting by..,1: The UCF_FULL pending bit is set by HW when the.." newline bitfld.long 0x1C 26. "UCF_TVR,Upstream Circular FIFO Threshold Value Reached" "0: The UCF_TVR pending bit is cleared because the..,1: The UCF_TVR pending bit has set because once.." bitfld.long 0x1C 25. "UCF_EMPTY,Upstream Circular FIFO Empty" "0: The UCF_EMPTY pending bit is cleared by setting..,1: The UCF_EMPTY pending bit is set by HW when the.." newline hexmask.long.byte 0x1C 16.--19. 1. "UCF_CT,UCF_CT" bitfld.long 0x1C 9. "UCF_PTRNC,UCF_PTRNC" "0: No rx_ucf_ptrnc interrupt pending.,1: rx_ucf_ptrnc interrupt is pending." newline bitfld.long 0x1C 8. "UCF_PTRCL,UCF_PTRCL" "0: A UCF read/write pointers clearing has been..,1: UCF read/write pointers clearing is running." line.long 0x20 "UFIFOCR,Upstream FIFO Control Register" bitfld.long 0x20 31. "UCF_EN,Upstream Circular FIFO On" "0: The Upstream Circular FIFO is disabled.,1: The Upstream Circular FIFO is enabled." bitfld.long 0x20 30. "UCF_DMA,Upstream Circular FIFO DMA" "0: The enabled Upstream Circular FIFO is accessible..,1: The enabled Upstream Circular FIFO is accessible.." newline bitfld.long 0x20 27. "EN_UCF_FULL,Enable Upstream Circular FIFO FULL" "0: Disable any rx_ucf_full interrupt request.,1: Enable the rx_ucf_full interrupt request coming.." bitfld.long 0x20 26. "EN_UCF_TVR,Enable Upstream Circular FIFO Threshold Value Reached" "0: Disable any rx_ucf_tvr interrupt request.,1: Enable the rx_ucf_tvr interrupt request coming.." newline bitfld.long 0x20 25. "EN_UCF_EMPTY,Enable Upstream Circular FIFO Empty" "0: Disable any rx_ucf_empty interrupt request.,1: Enable the rx_ucf_empty interrupt request coming.." bitfld.long 0x20 16.--18. "UCF_TV,Upstream Circular FIFO Threshold Value" "0: When UFIFOFR[UCF_CT] is equal to 0x1: then..,1: When UFIFOFR[UCF_CT] is equal to 2 then..,2: When UFIFOFR[UCF_CT] is equal to 3 then..,3: When UFIFOFR[UCF_CT] is equal to 4 then..,4: When UFIFOFR[UCF_CT] is equal to 5 then..,5: When UFIFOFR[UCF_CT] is equal to 6 then..,6: When UFIFOFR[UCF_CT] is equal to 7 then..,7: When UFIFOFR[UCF_CT] is equal to 8 then.." newline bitfld.long 0x20 9. "EN_UCF_PTRNC,Enable Upstream Circular FIFO read/write POINTERS Not Cleared" "0: Disable any rx_ucf_ptrnc interrupt request.,1: Enable the rx_ucf_ptrnc interrupt request on.." line.long 0x24 "UECR,Upstream Event Counter Register" bitfld.long 0x24 31. "EN_UNMATCH,Enable Unmatch" "0: The rx_unmatch interrupt is disabled.,1: The rx_unmatch interrupt is enabled." bitfld.long 0x24 30. "UNMATCH,Unmatch flag" "0: The UNMATCH pending bit is cleared setting by SW..,1: The UNMATCH pending bit is set by HW only when.." newline bitfld.long 0x24 27. "STOP0_RUN1,Stop 0 Run 1" "0: The clear stops the down counter and display..,1: The current baud frequency stops the down.." bitfld.long 0x24 24.--26. "EVENTS_OFF,Events number Off" "0: 0 oct,1: 1 oct,2: 2 oct,?,?,?,?,7: 7 oct" newline bitfld.long 0x24 23. "FREER0_SINGLES1,Free Running at 0 Single Shot at 1 mode" "0: On clear it is in free-running mode once the..,1: On set it is in single-shot mode once the down.." bitfld.long 0x24 20.--22. "EVENTS_MIN,Events Minimum number" "0: 0 oct,1: 1 oct,2: 2 oct,?,?,?,?,7: 7 oct" newline hexmask.long.byte 0x24 16.--19. 1. "EVENTS_END,Rx Events on last End Unmatch" hexmask.long.word 0x24 0.--15. 1. "UCYCLESN,Upstream Cycles Number" wgroup.long 0x70++0x3 line.long 0x0 "DFIFOR,Downstream FIFO Register" hexmask.long 0x0 0.--31. 1. "DFIFO,Downstream FIFO frame. A write by SW or by DMA will push the written frame into the Downstream FIFO DCF." group.long 0x74++0x7 line.long 0x0 "DFIFOFR,Downstream FIFO Flag Register" bitfld.long 0x0 30.--31. "DTX_DMAINT,Downstream Transmitter DMA/Interrupt" "0: Both DCF and DMA disabled.,1: Not possible. DFIFOCR[DCF_EN] ='0'..,2: Interrupt/Polling mode for the DCF enabled.,3: DMA mode for the DCF enabled." bitfld.long 0x0 29. "DCF_DMARUN,Downstream Circular FIFO DMA Running" "0: The DMA interface is not working.,1: The DMA interface is working." newline bitfld.long 0x0 28. "DCF_DMAREQ,Downstream Circular FIFO DMA Request" "0: No DMA request is running.,1: A DMA request is running." bitfld.long 0x0 27. "DCF_FULL,Downstream Circular FIFO FULL" "0: The DCF_FULL pending bit is cleared.,1: The DCF_FULL pending bit is set by HW when the.." newline bitfld.long 0x0 26. "DCF_TVR,Downstream Circular FIFO Threshold Value Reached" "0: The DCF_TVR bit is cleared.,1: The DCF_TVR bit is set meaning that the.." bitfld.long 0x0 25. "DCF_EMPTY,Downstream Circular FIFO Empty" "0: The DCF_EMPTY pending bit is cleared.,1: The DCF_EMPTY pending bit is set the DCF is.." newline hexmask.long.byte 0x0 16.--19. 1. "DCF_CT,Downstream Circular FIFO Current Threshold" bitfld.long 0x0 8. "DCF_PTRCL,Downstream Circular FIFO read/write Pointers Clear action" "0: A DCF read/write pointers clearing has been done..,1: DCF read/write pointers clearing is running." line.long 0x4 "DFIFOCR,Downstream FIFO Control Register" bitfld.long 0x4 31. "DCF_EN,Downstream Circular FIFO Enable" "0: The Downstream Circular FIFO is disabled.,1: The Downstream Circular FIFO is Enabled." bitfld.long 0x4 30. "DCF_DMA,Downstream Circular FIFO DMA Selection" "0: The Downstream Circular FIFO is manageable by..,1: The Downstream Circular FIFO is manageable by.." newline bitfld.long 0x4 27. "EN_DCF_FULL,ENable Downstream Circular FIFO Full" "0: Disable any tx_dcf_full interrupt request.,1: Enable the tx_dcf_full interrupt request coming.." bitfld.long 0x4 26. "EN_DCF_TVR,ENable Downstream Circular FIFO Threshold Value Reached" "0: Disable any tx_dcf_tvr interrupt request.,1: Enable the tx_dcf_tvr interrupt request coming.." newline bitfld.long 0x4 25. "EN_DCF_EMPTY,ENable Downstream Circular FIFO Empty" "0: Disable any tx_dcf_empty interrupt request.,1: Enable the tx_dcf_empty interrupt request coming.." bitfld.long 0x4 16.--18. "DCF_TV,Downstream Circular FIFO Threshold Value" "0: When DFIFOFR[DCF_CT] is equal to 0 then..,1: When DFIFOFR[DCF_CT] is equal to 1 then..,2: When DFIFOFR[DCF_CT] is equal to 2 then..,3: When DFIFOFR[DCF_CT] is equal to 3 then..,4: When DFIFOFR[DCF_CT] is equal to 4 then..,5: When DFIFOFR[DCF_CT] is equal to 5 then..,6: When DFIFOFR[DCF_CT] is equal to 6 then..,7: When DFIFOFR[DCF_CT] is equal to 7 then.." rgroup.long 0x7C++0x3 line.long 0x0 "DSR,Downstream Status Register" bitfld.long 0x0 4. "DGT32OR_REQ,DGT32OR update request status bit" "0: DGT32OR register can be updated by SW.,1: DGT32OR has been written by SW and the TX kernel.." bitfld.long 0x0 3. "DFI64OR_REQ,DFI64OR update request status bit" "0: DFI64OR register can be updated by SW.,1: DFI64OR has been written by SW and the TX kernel.." newline bitfld.long 0x0 2. "DTSCR_REQ,DTSCR update request status bit" "0: DTSCR register can be update by SW.,1: DTSCR has been written by SW and the TX kernel.." bitfld.long 0x0 1. "MSCIOR_REQ,MSCIOR update request status bit" "0: MSCIOR register can be updated by SW.,1: MSCIOR has been written by SW and the TX kernel.." newline bitfld.long 0x0 0. "TX_IDLE,Downstream transmitter status bit" "0: A frame transmission is in progress.,1: The asynchronous TX FIFO inside the Downstream.." group.long 0x80++0x6F line.long 0x0 "DH64FR,Downstream High 64-bit Frame Register" hexmask.long 0x0 0.--31. 1. "DH64F,DH64F is a Read/Write bit field which stores the high part bits from 32 up to 63 of a single receiver frame or the data for the second receiver of a dual receiver data frame." line.long 0x4 "DL64FR,Downstream Low 64-bit Frame Register" hexmask.long 0x4 0.--31. 1. "DL64F,DL64F is a Read/Write register field which stores the low part bits from 0 up to 31 of a single receiver frame or the data for the first receiver and eventually also the second receiver of a dual receiver data frame." line.long 0x8 "DHTSFR,Downstream High Generic Timers Frame Register" hexmask.long 0x8 0.--31. 1. "DHGTF,Downstream High Generic Timers Frame" line.long 0xC "DLTSFR,Downstream Low Generic Timers Frame Register" hexmask.long 0xC 0.--31. 1. "DLGTF,Downstream Low Generic Timers Frame" line.long 0x10 "D32FR,Downstream 32-bit Frame Register" hexmask.long 0x10 0.--31. 1. "D32F,Downstream 32 Frame" line.long 0x14 "D64SUR,Downstream 64-bit Set Up Register" bitfld.long 0x14 31. "DS_64,Data Selection bit in a 64 bits TX" "0: It means the single receiver Data frame has not..,1: It means the single receiver Data frame has a.." bitfld.long 0x14 30. "HDS_64,High Data Selection bit in a 64 bits TX" "0: It means the data transmission for the second..,1: It means the data transmission for the second.." newline hexmask.long.byte 0x14 24.--29. 1. "HDN_64,High Data Number in a 64 bits TX" bitfld.long 0x14 23. "C1D0_64,Command 1 Data 0 bit in a 64 bits Tx" "0: The frame to be transmitted is a Data frame.,1: The frame to be transmitted is a Command frame." newline bitfld.long 0x14 22. "LDS_64,Low Data Selection bit in a 64 bits TX" "0: It means the data transmission for the first..,1: It means the data transmission for the first.." hexmask.long.byte 0x14 16.--21. 1. "LDN_64,Low Data Number in a 64 bits TX" newline bitfld.long 0x14 15. "REQ_64,This bit is set by SW in order to issue a new frame transmission and it is cleared only by HW. The SW can use this bit for polling when to write a new request." "0: No transmission request is pending and a new..,1: A new transmission request has been issued by SW.." hexmask.long.byte 0x14 8.--12. 1. "PPN_64,Passive Phases Number in a 64 bits Tx" newline bitfld.long 0x14 7. "ENN_64,Enable Number bit in a 64 bits Tx" "0: Dual receiver data frame the internal Enables..,1: Single receiver data frame the internal Enable.." hexmask.long.byte 0x14 0.--6. 1. "CDN_64,Command Data 64 bits Number" line.long 0x18 "DGTSUR,Downstream Generic Timers Set Up Register" bitfld.long 0x18 31. "DS_GT,Data Selection bit in a GT TX" "0: It means the single receiver Data frame has not..,1: It means the single receiver Data frame has a.." bitfld.long 0x18 30. "HDS_GT,High Data Selection bit in a GT TX" "0: It means the data transmission for the second..,1: It means the data transmission for the second.." newline hexmask.long.byte 0x18 24.--29. 1. "HDN_GT,High Data Number in a GT TX" bitfld.long 0x18 23. "C1D0_GT,Command 1 Data 0 bit in a GT Tx" "0: The frame to be transmitted is a Data frame.,1: receiver" newline bitfld.long 0x18 22. "LDS_GT,Low Data Selection bit in a GT TX" "0: It means the data transmission for the first..,1: It means the data transmission for the first.." hexmask.long.byte 0x18 16.--21. 1. "LDN_GT,Low Data Number in a GT TX" newline bitfld.long 0x18 15. "REQ_GT,This bit is set by SW or HW in order to issue a new frame transmission and it is cleared only by HW. The SW can use this bit for polling when to write a new request." "0: No transmission request is pending and a new..,1: A new transmission request has been issued by SW.." hexmask.long.byte 0x18 8.--12. 1. "PPN_GT,Passive Phases Number in a GT Tx" newline bitfld.long 0x18 7. "ENN_GT,Enable Number bit in a GT Tx" "0: Dual receiver data frame the internal Enables..,1: Single receiver data frame the internal Enable.." hexmask.long.byte 0x18 0.--6. 1. "CDN_GT,Command Data bits Number in a GT Tx" line.long 0x1C "D32SUR,Downstream 32-bit Set Up Register" bitfld.long 0x1C 31. "DS_32,Data Selection bit in a 32 bits TX" "0: It means the single receiver Data frame has not..,1: It means the single receiver Data frame has a.." bitfld.long 0x1C 30. "HDS_32,High Data Selection bit in a 32 bits TX" "0: It means the data transmission for the second..,1: It means the data transmission for the second.." newline hexmask.long.byte 0x1C 24.--29. 1. "HDN_32,High Data Number in a 32 bits TX" bitfld.long 0x1C 23. "C1D0_32,Command 1 Data 0 bit in a 32 bits Tx" "0: The frame to be transmitted is a Data frame.,1: The frame to be transmitted is a Command frame." newline bitfld.long 0x1C 22. "LDS_32,Low Data Selection bit in a 32 bits TX" "0: It means the data transmission for the first..,1: It means the data transmission for the first.." hexmask.long.byte 0x1C 16.--21. 1. "LDN_32,Low Data Number in a 32 bits TX" newline bitfld.long 0x1C 15. "REQ_32,This bit is set by SW in order to issue a new frame transmission and it is cleared by HW only. The SW can use this bit for polling when to write a new request." "0: No transmission request is pending and a new..,1: A new transmission request has been issued by SW.." hexmask.long.byte 0x1C 8.--12. 1. "PPN_32,Passive Phases Number in a 32 bits Tx" newline bitfld.long 0x1C 7. "ENN_32,Enable Number bit in a 32 bits Tx" "0: Dual receiver data frame the internal Enables..,1: Single receiver data frame the internal Enable.." hexmask.long.byte 0x1C 0.--6. 1. "CDN_32,Command Data bits Number in a 32 bits Tx" line.long 0x20 "DFISUR,Downstream FIFO SetUp Register" bitfld.long 0x20 31. "DS_FI,Data Selection bit in a FI TX" "0: It means the single receiver Data frame has not..,1: It means the single receiver Data frame has a.." bitfld.long 0x20 30. "HDS_FI,High Data Selection bit in a FI TX" "0: It means the data transmission for the second..,1: It means the data transmission for the second.." newline hexmask.long.byte 0x20 24.--29. 1. "HDN_FI,High Data Number in a FI TX" bitfld.long 0x20 23. "C1D0_FI,Command 1 Data 0 bit in a FI Tx" "0: The frame to be transmitted is a Data frame.,1: The frame to be transmitted is a Command frame." newline bitfld.long 0x20 22. "LDS_FI,Low Data Selection bit in a FI TX" "0: It means the data transmission for the first..,1: It means the data transmission for the first.." hexmask.long.byte 0x20 16.--21. 1. "LDN_FI,Low Data Number in a FI TX" newline bitfld.long 0x20 15. "REQ_FI,This bit is set by SW or HW in order to issue a new frame transmission and it is cleared only by HW. The SW can use this bit for polling when to write a new request." "0: No transmission request is pending and a new..,1: A new transmission request has been issued by SW.." hexmask.long.byte 0x20 8.--12. 1. "PPN_FI,Passive Phases Number in a FI Tx" newline bitfld.long 0x20 7. "ENN_FI,Enable Number bit in a FI Tx" "0: Dual receiver data frame the internal Enables..,1: Single receiver data frame the internal Enable.." hexmask.long.byte 0x20 0.--6. 1. "CDN_FI,Command Data bits Number in a FI Tx" line.long 0x24 "DGT32OR,Downstream GT/32 Output Register" bitfld.long 0x24 31. "EN_GT,ENable GT 64-bit frames" "0: The DGTSUR register is not writable by SW.,1: The DGTSUR register is writable by SW." bitfld.long 0x24 24.--26. "ENO_GT,ENable to Output GT source configuration bit" "0: msc_deo[0] IP Output displays en.,1: msc_deo[1] IP Output displays en.,2: msc_deo[2] IP Output displays en.,3: msc_deo[3] IP Output displays en.,4: msc_deo[4] IP Output displays en.,5: msc_deo[5] IP Output displays en.,6: msc_deo[6] IP Output displays en.,7: msc_deo[7] IP Output displays en." newline bitfld.long 0x24 20.--22. "HENO_GT,High ENable to Output GT source configuration bit" "0: msc_deo[0] IP Output displays hen.,1: msc_deo[1] IP Output displays hen.,2: msc_deo[2] IP Output displays hen.,3: msc_deo[3] IP Output displays hen.,4: msc_deo[4] IP Output displays hen.,5: msc_deo[5] IP Output displays hen.,6: msc_deo[6] IP Output displays hen.,7: msc_deo[7] IP Output displays hen." bitfld.long 0x24 16.--18. "LENO_GT,Low ENable to Output GT source configuration bit" "0: msc_deo[0] IP Output displays len.,1: msc_deo[1] IP Output displays len.,2: msc_deo[2] IP Output displays len.,3: msc_deo[3] IP Output displays len.,4: msc_deo[4] IP Output displays len.,5: msc_deo[5] IP Output displays len.,6: msc_deo[6] IP Output displays len.,7: msc_deo[7] IP Output displays len." newline bitfld.long 0x24 15. "EN_32,ENable 32 32-bit frames" "0: The D32SUR register is not writable by SW.,1: The D32SUR register is writable by SW." bitfld.long 0x24 8.--10. "ENO_32,Enable to Output 32 source configuration bit" "0: msc_deo[0] IP Output displays en.,1: msc_deo[1] IP Output displays en.,2: msc_deo[2] IP Output displays en.,3: msc_deo[3] IP Output displays en.,4: msc_deo[4] IP Output displays en.,5: msc_deo[5] IP Output displays en.,6: msc_deo[6] IP Output displays en.,7: msc_deo[7] IP Output displays en." newline bitfld.long 0x24 4.--6. "HENO_32,High Enable to Output 32 source configuration bit" "0: msc_deo[0] IP Output displays hen.,1: msc_deo[1] IP Output displays hen.,2: msc_deo[2] IP Output displays hen.,3: msc_deo[3] IP Output displays hen.,4: msc_deo[4] IP Output displays hen.,5: msc_deo[5] IP Output displays hen.,6: msc_deo[6] IP Output displays hen.,7: msc_deo[7] IP Output displays hen." bitfld.long 0x24 0.--2. "LENO_32,Low Enable to Output 32 source configuration bit" "0: msc_deo[0] IP Output displays len.,1: msc_deo[1] IP Output displays len.,2: msc_deo[2] IP Output displays len.,3: msc_deo[3] IP Output displays len.,4: msc_deo[4] IP Output displays len.,5: msc_deo[5] IP Output displays len.,6: msc_deo[6] IP Output displays len.,7: msc_deo[7] IP Output displays len." line.long 0x28 "DFI64OR,Downstream FI/64 Output Register" bitfld.long 0x28 31. "EN_FI,ENable FI frame source" "0: The DFISUR register is not writable by SW.,1: The DFISUR[31:0] register is writable by SW." bitfld.long 0x28 24.--26. "ENO_FI,ENable to Output FI source configuration bits" "0: msc_deo[0] IP Output displays en.,1: msc_deo[1] IP Output displays en.,2: msc_deo[2] IP Output displays en.,3: msc_deo[3] IP Output displays en.,4: msc_deo[4] IP Output displays en.,5: msc_deo[5] IP Output displays en.,6: msc_deo[6] IP Output displays en.,7: msc_deo[7] IP Output displays en." newline bitfld.long 0x28 20.--22. "HENO_FI,High ENable to Output FI source configuration bits" "0: msc_deo[0] IP Output displays hen.,1: msc_deo[1] IP Output displays hen.,2: msc_deo[2] IP Output displays hen.,3: msc_deo[3] IP Output displays hen.,4: msc_deo[4] IP Output displays hen.,5: msc_deo[5] IP Output displays hen.,6: msc_deo[6] IP Output displays hen.,7: msc_deo[7] IP Output displays hen." bitfld.long 0x28 16.--18. "LENO_FI,Low ENable to Output FI source configuration bits" "0: 0x0: msc_deo[0] IP Output displays len.,1: msc_deo[1] IP Output displays len.,2: msc_deo[2] IP Output displays len.,3: msc_deo[3] IP Output displays len.,4: msc_deo[4] IP Output displays len.,5: msc_deo[5] IP Output displays len.,6: msc_deo[6] IP Output displays len.,7: msc_deo[7] IP Output displays len." newline bitfld.long 0x28 15. "EN_64,ENable 64-bit frames source" "0: The D64SUR register is not writable by SW.,1: The D64SUR register is writable by SW." bitfld.long 0x28 8.--10. "ENO_64,ENable to Output 64-bits source configuration bits" "0: msc_deo[0] IP Output displays en.,1: msc_deo[1] IP Output displays en.,2: msc_deo[2] IP Output displays en.,3: msc_deo[3] IP Output displays en.,4: msc_deo[4] IP Output displays en.,5: msc_deo[5] IP Output displays en.,6: msc_deo[6] IP Output displays en.,7: msc_deo[7] IP Output displays en." newline bitfld.long 0x28 4.--6. "HENO_64,High ENable to Output 64-bits source configuration bits" "0: msc_deo[0] IP Output displays hen.,1: msc_deo[1] IP Output displays hen.,2: msc_deo[2] IP Output displays hen.,3: msc_deo[3] IP Output displays hen.,4: msc_deo[4] IP Output displays hen.,5: msc_deo[5] IP Output displays hen.,6: msc_deo[6] IP Output displays hen.,7: msc_deo[7] IP Output displays hen." bitfld.long 0x28 0.--2. "LENO_64,Low ENable to Output 64-bits source configuration bits" "0: msc_deo[0] IP Output displays len.,1: msc_deo[1] IP Output displays len.,2: msc_deo[2] IP Output displays len.,3: msc_deo[3] IP Output displays len.,4: msc_deo[4] IP Output displays len.,5: msc_deo[5] IP Output displays len.,6: msc_deo[6] IP Output displays len.,7: msc_deo[7] IP Output displays len." line.long 0x2C "DPPMPR,Downstream Passive Phase Modulation Priority Register" bitfld.long 0x2C 28.--29. "PRI_32,PRIority 32-bits source configuration bits" "0: The priority value is 0.,1: The priority value is 1.,2: The priority value is 2.,3: The priority value is 3." bitfld.long 0x2C 24.--25. "PRI_64,PRIority 64-bits source configuration bits" "0: The priority value is 0.,1: The priority value is 1.,2: The priority value is 2.,3: The priority value is 3." newline bitfld.long 0x2C 20.--21. "PRI_GT,PRIority Generic-Timers source configuration bits" "0: The priority value is 0.,1: The priority value is 1.,2: The priority value is 2.,3: The priority value is 3." bitfld.long 0x2C 16.--17. "PRI_FI,Priority FI source configuration bits" "0: The priority value is 0.,1: The priority value is 1.,2: The priority value is 2.,3: The priority value is 3." newline bitfld.long 0x2C 8. "ENH_32B,Enable High on dedicated 32-bit register" "0: Only the low register of a 64-bits source is..,1: Both the high and low register of a 64-bits.." bitfld.long 0x2C 6. "PPM,Passive Phase Modulation" "0: The passive phase modulation is not enabled.,1: The passive phase modulation is enabled." line.long 0x30 "DTSCR,Downstream Timer Siul Counter Register" bitfld.long 0x30 31. "H0S1_SAMPLE,Hardware 0 Software 1 SAMPLE. H0S1_SAMPLE is a Read/Write bit field. The H0S1_SAMPLE control bit selects a SW or HW sampling for the input data of the DTSFR source." "0: Hardware sampling from siul_sample input selected.,1: Software sampling from Down-counter EOC selected." bitfld.long 0x30 30. "DSTART_CNT,START CouNTer. DSTART_CNT is a Read/Write bit field. The DSTART_CNT control field starts the counter if it is set otherwise the down-counter is stopped." "0: The counter is stopped.,1: The counter is started." newline hexmask.long.tbyte 0x30 0.--23. 1. "DCYCLESN,Downstream CYCLES Number" line.long 0x34 "DHTSMR,Downstream High Timers SIUL Mux Register" hexmask.long 0x34 0.--31. 1. "DHTSM,Downstream High SIUL Mux" line.long 0x38 "DLTSMR,Downstream Low Timers SIUL Mux Register" hexmask.long 0x38 0.--31. 1. "DLTSM,Downstream Low Timers SIUL Mux" line.long 0x3C "DFR,Downstream Flag Register" bitfld.long 0x3C 31. "EN_NOPEND_32REQ,This bit enable/disable the corresponding NOPEND_32REQ interrupt." "0: The NOPEND_32REQ interrupt is disabled.,1: The NOPEND_32REQ interrupt is enabled." bitfld.long 0x3C 30. "NOPEND_32REQ,Interrupt bit for the 32 bits frame source." "0: A request is pending.,1: A new request can be issued by the SW." newline bitfld.long 0x3C 29. "EN_NOPEND_64REQ,This bit enable/disable the corresponding NOPEND_64REQ interrupt." "0: The NOPEND_64REQ interrupt is disabled.,1: The NOPEND_64REQ interrupt is enabled." bitfld.long 0x3C 28. "NOPEND_64REQ,Interrupt bit for the 64 bits frame source." "0: A request is pending.,1: A new request can be issued by the SW." newline bitfld.long 0x3C 27. "EN_NOPEND_FIREQ,This bit enable/disable the corresponding NOPEND_64REQ interrupt." "0: The NOPEND_FIREQ interrupt is disabled.,1: The NOPEND_FIREQ interrupt is enabled." bitfld.long 0x3C 26. "NOPEND_FIREQ,Interrupt bit for the Downstream Circular FIFO DCF frame source." "0: A request is pending.,1: A new request can be issued by SW or by HW." newline bitfld.long 0x3C 25. "EN_NOPEND_GTREQ,This bit enable/disable the corresponding NOPEND_GTREQ interrupt." "0: The NOPEND_GTREQ interrupt is disabled.,1: The NOPEND_GTREQ interrupt is enabled." bitfld.long 0x3C 24. "NOPEND_GTREQ,Interrupt bit for the DTSFR frame source." "0: A request is pending.,1: A new request can be issued by SW or by HW." line.long 0x40 "DHPISR0,Downstream Hardware Parallel Input Select Register 0" hexmask.long.byte 0x40 28.--31. 1. "DHPIS7,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x40 24.--27. 1. "DHPIS6,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x40 20.--23. 1. "DHPIS5,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x40 16.--19. 1. "DHPIS4,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x40 12.--15. 1. "DHPIS3,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x40 8.--11. 1. "DHPIS2,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x40 4.--7. 1. "DHPIS1,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x40 0.--3. 1. "DHPIS0,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x44 "DHPISR1,Downstream Hardware Parallel Input Select Register 1" hexmask.long.byte 0x44 28.--31. 1. "DHPIS15,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x44 24.--27. 1. "DHPIS14,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x44 20.--23. 1. "DHPIS13,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x44 16.--19. 1. "DHPIS12,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x44 12.--15. 1. "DHPIS11,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x44 8.--11. 1. "DHPIS10,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x44 4.--7. 1. "DHPIS9,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x44 0.--3. 1. "DHPIS8,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x48 "DHPISR2,Downstream Hardware Parallel Input Select Register 2" hexmask.long.byte 0x48 28.--31. 1. "DHPIS23,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x48 24.--27. 1. "DHPIS22,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x48 20.--23. 1. "DHPIS21,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x48 16.--19. 1. "DHPIS20,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x48 12.--15. 1. "DHPIS19,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x48 8.--11. 1. "DHPIS18,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x48 4.--7. 1. "DHPIS17,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x48 0.--3. 1. "DHPIS16,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x4C "DHPISR3,Downstream Hardware Parallel Input Select Register 3" hexmask.long.byte 0x4C 28.--31. 1. "DHPIS31,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x4C 24.--27. 1. "DHPIS30,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x4C 20.--23. 1. "DHPIS29,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x4C 16.--19. 1. "DHPIS28,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x4C 12.--15. 1. "DHPIS27,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x4C 8.--11. 1. "DHPIS26,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x4C 4.--7. 1. "DHPIS25,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x4C 0.--3. 1. "DHPIS24,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x50 "DHPISR4,Downstream Hardware Parallel Input Select Register 4" hexmask.long.byte 0x50 28.--31. 1. "DHPIS39,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x50 24.--27. 1. "DHPIS38,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x50 20.--23. 1. "DHPIS37,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x50 16.--19. 1. "DHPIS36,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x50 12.--15. 1. "DHPIS35,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x50 8.--11. 1. "DHPIS34,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x50 4.--7. 1. "DHPIS33,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x50 0.--3. 1. "DHPIS32,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x54 "DHPISR5,Downstream Hardware Parallel Input Select Register 5" hexmask.long.byte 0x54 28.--31. 1. "DHPIS47,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x54 24.--27. 1. "DHPIS46,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x54 20.--23. 1. "DHPIS45,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x54 16.--19. 1. "DHPIS44,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x54 12.--15. 1. "DHPIS43,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x54 8.--11. 1. "DHPIS42,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x54 4.--7. 1. "DHPIS41,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x54 0.--3. 1. "DHPIS40,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x58 "DHPISR6,Downstream Hardware Parallel Input Select Register 6" hexmask.long.byte 0x58 28.--31. 1. "DHPIS55,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x58 24.--27. 1. "DHPIS54,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x58 20.--23. 1. "DHPIS53,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x58 16.--19. 1. "DHPIS52,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x58 12.--15. 1. "DHPIS51,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x58 8.--11. 1. "DHPIS50,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x58 4.--7. 1. "DHPIS49,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x58 0.--3. 1. "DHPIS48,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x5C "DHPISR7,Downstream Hardware Parallel Input Select Register 7" hexmask.long.byte 0x5C 28.--31. 1. "DHPIS63,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x5C 24.--27. 1. "DHPIS62,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x5C 20.--23. 1. "DHPIS61,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x5C 16.--19. 1. "DHPIS60,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x5C 12.--15. 1. "DHPIS59,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x5C 8.--11. 1. "DHPIS58,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x5C 4.--7. 1. "DHPIS57,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x5C 0.--3. 1. "DHPIS56,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x60 "DHSBSR,Downstream High SIUL By Software Register" hexmask.long 0x60 0.--31. 1. "DHSBSW,Downstream High SIUL By Software" line.long 0x64 "DLSBSR,Downstream Low SIUL By Software Register" hexmask.long 0x64 0.--31. 1. "DLSBSW,Downstream Low SIUL By Software" line.long 0x68 "DHSBHR,Downstream High SIUL By Hardware Register" hexmask.long 0x68 0.--31. 1. "DHSBHW,Downstream High SIUL By Hardware" line.long 0x6C "DLSBHR,Downstream Low SIUL By Hardware Register" hexmask.long 0x6C 0.--31. 1. "DLSBHW,Downstream Low SIUL By Hardware" tree.end tree "MSC_2" base ad:0x71A68000 group.long 0x0++0x7 line.long 0x0 "MSCCCR,MSC Clock Control Register" bitfld.long 0x0 16. "EN_RX_RSTN,ENable RX ReSeTN. EN_RX_RSTN is a Read/Write bit field. The EN_RX_RSTN bit enables an HW Synchronous Reset on all MSC RX of msc_uck domain circuitry triggered when [UECR]UNMATCH asserts." "0: The [UECR]UNMATCH never resets the MSC RX..,1: On [UECR]UNMATCH field asserting the MSC RX.." hexmask.long.byte 0x0 0.--7. 1. "MSCCK_DIV,MSC ClocK DIVider. MSCCK_DIV is a 8-bits Read/Write field. According to the following definition the msc_clk clock frequency is divisible for: 4 6 8 10 12 16 20 24 40." line.long 0x4 "MSCIOR,MSC Inputs Outputs Register" bitfld.long 0x4 19. "CKP,Clock Polarity" "0: Normal polarity.,1: Inverse polarity." bitfld.long 0x4 18. "CKA,Clock always Active" "0: It means msc_dclk is active only when enables..,1: It means msc_dclk is always active." newline bitfld.long 0x4 17. "CK_DIFF,Clock output Differential" "0: The MSC msc_dclk Downstream Clock is not in..,1: The MSC msc_dclk Downstream Clock is in.." bitfld.long 0x4 16. "CK_OBE,ClocK Output Buffer Enable" "0: The MSC msc_dclk Downstream clock output is not..,1: The MSC msc_dclk Downstream clock output is.." newline bitfld.long 0x4 4. "ENP,Enable Polarity" "0: Normal polarity.,1: " bitfld.long 0x4 3. "DSOP,Downstream Serial Output Polarity register" "0: Normal polarity.,1: Inverse polarity." newline bitfld.long 0x4 1. "DSO_DIFF,Data Serial Output Differential" "0: The MSC msc_dso Downstream Serial data Out is..,1: The MSC msc_dso Downstream Serial data Out is in.." bitfld.long 0x4 0. "DSO_OBE,Data Serial Output Buffer Enable" "0: The MSC msc_dso Downstream Serial data Out is..,1: The MSC msc_dso Downstream Serial data Out is.." rgroup.long 0xC++0x3 line.long 0x0 "UFIFOR,Upstream FIFO Register" hexmask.long 0x0 0.--31. 1. "UFIFO,Upstream FIFO frame" group.long 0x10++0x27 line.long 0x0 "UFR0,Upstream Frame Register 0" bitfld.long 0x0 28. "EN_OWRERF,Enable Overwrite Error Frame" "0: The rx_owrerf interrupt request is disabled in..,1: The rx_owrerf interrupt request is enabled in.." bitfld.long 0x0 27. "EN_STOPBERF,Enable Stop Bit Error Frame" "0: The rx_stopbiterf interrupt request is disabled..,1: The rx_stopbiterf interrupt request is enabled.." newline bitfld.long 0x0 26. "EN_PARERF,Enable Parity Error Frame n" "0: The rx_parerf interrupt request is disabled in..,1: The rx_parerf interrupt request is enabled in.." bitfld.long 0x0 25. "EN_CONSBERF,Enable Consistency Bit Error Frame" "0: The rx_consbiterf interrupt request is disabled..,1: The rx_consbiterf interrupt request is enabled.." newline bitfld.long 0x0 24. "EN_NEWF,Enable New Frame" "0: The rx_newf interrupt request is disabled in UFRn.,1: The rx_newf interrupt request is enabled in UFRn." bitfld.long 0x0 20. "OWRERF,Overwrite Error Frame" "0: The OWRERF pending bit is cleared setting by SW..,1: The OWRERF pending bit is set by HW when on a.." newline bitfld.long 0x0 19. "STOPBERF,Stop Bit Error Frame" "0: The STOPBERF pending bit is cleared setting by..,1: The STOPBERF pending bit is set by HW when one.." bitfld.long 0x0 18. "PARERF,Parity Error Frame" "0: The PARERF pending bit is cleared setting by SW..,1: The PARERF pending bit is set by HW only and it.." newline bitfld.long 0x0 17. "CONSBITERF,Consistency Bit Error Frame n" "0: The CONSBERF pending bit is cleared by a SW..,1: The CONSBERF pending bit is set by HW only when.." bitfld.long 0x0 16. "NEWF,New Frame" "0: The NEWF pending bit is cleared by a SW setting.,1: The NEWF pending bit is set by HW only when a.." newline bitfld.long 0x0 15. "PARITY,UFRn Parity field" "0: The received upstream has parity 0.,1: The received upstream has parity 1." bitfld.long 0x0 12.--14. "STOP,UFRn Stop bits" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ADD,UFRn Address" hexmask.long.byte 0x0 0.--7. 1. "DATA,UFRn Data" line.long 0x4 "UFR1,Upstream Frame Register 1" bitfld.long 0x4 28. "EN_OWRERF,Enable Overwrite Error Frame" "0: The rx_owrerf interrupt request is disabled in..,1: The rx_owrerf interrupt request is enabled in.." bitfld.long 0x4 27. "EN_STOPBERF,Enable Stop Bit Error Frame" "0: The rx_stopbiterf interrupt request is disabled..,1: The rx_stopbiterf interrupt request is enabled.." newline bitfld.long 0x4 26. "EN_PARERF,Enable Parity Error Frame n" "0: The rx_parerf interrupt request is disabled in..,1: The rx_parerf interrupt request is enabled in.." bitfld.long 0x4 25. "EN_CONSBERF,Enable Consistency Bit Error Frame" "0: The rx_consbiterf interrupt request is disabled..,1: The rx_consbiterf interrupt request is enabled.." newline bitfld.long 0x4 24. "EN_NEWF,Enable New Frame" "0: The rx_newf interrupt request is disabled in UFRn.,1: The rx_newf interrupt request is enabled in UFRn." bitfld.long 0x4 20. "OWRERF,Overwrite Error Frame" "0: The OWRERF pending bit is cleared setting by SW..,1: The OWRERF pending bit is set by HW when on a.." newline bitfld.long 0x4 19. "STOPBERF,Stop Bit Error Frame" "0: The STOPBERF pending bit is cleared setting by..,1: The STOPBERF pending bit is set by HW when one.." bitfld.long 0x4 18. "PARERF,Parity Error Frame" "0: The PARERF pending bit is cleared setting by SW..,1: The PARERF pending bit is set by HW only and it.." newline bitfld.long 0x4 17. "CONSBITERF,Consistency Bit Error Frame n" "0: The CONSBERF pending bit is cleared by a SW..,1: The CONSBERF pending bit is set by HW only when.." bitfld.long 0x4 16. "NEWF,New Frame" "0: The NEWF pending bit is cleared by a SW setting.,1: The NEWF pending bit is set by HW only when a.." newline bitfld.long 0x4 15. "PARITY,UFRn Parity field" "0: The received upstream has parity 0.,1: The received upstream has parity 1." bitfld.long 0x4 12.--14. "STOP,UFRn Stop bits" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "ADD,UFRn Address" hexmask.long.byte 0x4 0.--7. 1. "DATA,UFRn Data" line.long 0x8 "UFR2,Upstream Frame Register 2" bitfld.long 0x8 28. "EN_OWRERF,Enable Overwrite Error Frame" "0: The rx_owrerf interrupt request is disabled in..,1: The rx_owrerf interrupt request is enabled in.." bitfld.long 0x8 27. "EN_STOPBERF,Enable Stop Bit Error Frame" "0: The rx_stopbiterf interrupt request is disabled..,1: The rx_stopbiterf interrupt request is enabled.." newline bitfld.long 0x8 26. "EN_PARERF,Enable Parity Error Frame n" "0: The rx_parerf interrupt request is disabled in..,1: The rx_parerf interrupt request is enabled in.." bitfld.long 0x8 25. "EN_CONSBERF,Enable Consistency Bit Error Frame" "0: The rx_consbiterf interrupt request is disabled..,1: The rx_consbiterf interrupt request is enabled.." newline bitfld.long 0x8 24. "EN_NEWF,Enable New Frame" "0: The rx_newf interrupt request is disabled in UFRn.,1: The rx_newf interrupt request is enabled in UFRn." bitfld.long 0x8 20. "OWRERF,Overwrite Error Frame" "0: The OWRERF pending bit is cleared setting by SW..,1: The OWRERF pending bit is set by HW when on a.." newline bitfld.long 0x8 19. "STOPBERF,Stop Bit Error Frame" "0: The STOPBERF pending bit is cleared setting by..,1: The STOPBERF pending bit is set by HW when one.." bitfld.long 0x8 18. "PARERF,Parity Error Frame" "0: The PARERF pending bit is cleared setting by SW..,1: The PARERF pending bit is set by HW only and it.." newline bitfld.long 0x8 17. "CONSBITERF,Consistency Bit Error Frame n" "0: The CONSBERF pending bit is cleared by a SW..,1: The CONSBERF pending bit is set by HW only when.." bitfld.long 0x8 16. "NEWF,New Frame" "0: The NEWF pending bit is cleared by a SW setting.,1: The NEWF pending bit is set by HW only when a.." newline bitfld.long 0x8 15. "PARITY,UFRn Parity field" "0: The received upstream has parity 0.,1: The received upstream has parity 1." bitfld.long 0x8 12.--14. "STOP,UFRn Stop bits" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "ADD,UFRn Address" hexmask.long.byte 0x8 0.--7. 1. "DATA,UFRn Data" line.long 0xC "UFR3,Upstream Frame Register 3" bitfld.long 0xC 28. "EN_OWRERF,Enable Overwrite Error Frame" "0: The rx_owrerf interrupt request is disabled in..,1: The rx_owrerf interrupt request is enabled in.." bitfld.long 0xC 27. "EN_STOPBERF,Enable Stop Bit Error Frame" "0: The rx_stopbiterf interrupt request is disabled..,1: The rx_stopbiterf interrupt request is enabled.." newline bitfld.long 0xC 26. "EN_PARERF,Enable Parity Error Frame n" "0: The rx_parerf interrupt request is disabled in..,1: The rx_parerf interrupt request is enabled in.." bitfld.long 0xC 25. "EN_CONSBERF,Enable Consistency Bit Error Frame" "0: The rx_consbiterf interrupt request is disabled..,1: The rx_consbiterf interrupt request is enabled.." newline bitfld.long 0xC 24. "EN_NEWF,Enable New Frame" "0: The rx_newf interrupt request is disabled in UFRn.,1: The rx_newf interrupt request is enabled in UFRn." bitfld.long 0xC 20. "OWRERF,Overwrite Error Frame" "0: The OWRERF pending bit is cleared setting by SW..,1: The OWRERF pending bit is set by HW when on a.." newline bitfld.long 0xC 19. "STOPBERF,Stop Bit Error Frame" "0: The STOPBERF pending bit is cleared setting by..,1: The STOPBERF pending bit is set by HW when one.." bitfld.long 0xC 18. "PARERF,Parity Error Frame" "0: The PARERF pending bit is cleared setting by SW..,1: The PARERF pending bit is set by HW only and it.." newline bitfld.long 0xC 17. "CONSBITERF,Consistency Bit Error Frame n" "0: The CONSBERF pending bit is cleared by a SW..,1: The CONSBERF pending bit is set by HW only when.." bitfld.long 0xC 16. "NEWF,New Frame" "0: The NEWF pending bit is cleared by a SW setting.,1: The NEWF pending bit is set by HW only when a.." newline bitfld.long 0xC 15. "PARITY,UFRn Parity field" "0: The received upstream has parity 0.,1: The received upstream has parity 1." bitfld.long 0xC 12.--14. "STOP,UFRn Stop bits" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "ADD,UFRn Address" hexmask.long.byte 0xC 0.--7. 1. "DATA,UFRn Data" line.long 0x10 "UKERCR,Upstream Kernel Control Register" bitfld.long 0x10 31. "US_REQ,Upstream Setup Request" "0: The USREQ is cleared by HW a clk cycle after its..,1: The USREQ setting is kept for one clk cycle only." bitfld.long 0x10 30. "US_ACK,Upstream Setup Acknowledge" "0: Meanwhile the new set up values are loaded to..,1: The Rx kernel has received the new setup values." newline bitfld.long 0x10 29. "USRA_R,Upstream Setup Request Acknowledge Reset" "0: Both US_REQ and US_ACK bits can be accessed.,1: Both US_REQ and US_ACK bits are forced low." bitfld.long 0x10 20. "IUIS,Inverted Upstream Input Selector field" "0: The msc_usi input will be evaluated with no..,1: The msc_usi input will be evaluated forcing a.." newline bitfld.long 0x10 16.--18. "USISEL,Upstream Serial Input Selections" "0: Selects the msc_usi[0] input line,1: Selects the msc_usi[1] input line,2: Selects the msc_usi[2] input line,3: Selects the msc_usi[3] input line,4: Selects the msc_usi[4] input line,5: Selects the msc_usi[5] input line,6: Selects the msc_usi[6] input line,7: Selects the msc_usi[7] input line" bitfld.long 0x10 4.--5. "USBN,Upstream Stop Bits Number" "0: 2 Stop Bits,1: 1 Stop Bit,2: 2 Stop Bits,3: 3 Stop Bits" newline bitfld.long 0x10 0.--2. "UBR,Upstream Baud Rate" "0: Rx kernel disabled,1: Baud Rate = fMSC/4,2: Baud Rate = fMSC/8,3: Baud Rate = fMSC/16,4: Baud Rate = fMSC/32,5: Baud Rate = fMSC/64,6: Baud Rate = fMSC/128,7: Baud Rate = fMSC/256" line.long 0x14 "UREGCR,Upstream Registers Control Register" bitfld.long 0x14 31. "UREG_EN,Upstream Register Enable" "0,1" bitfld.long 0x14 12. "UPT,Upstream Parity Type" "0: The msc_usi input will be evaluated with an even..,1: The msc_usi input will be evaluated with an odd.." newline bitfld.long 0x14 8. "UAE,Upstream Address Enable" "0: The received frame is without the address field:..,1: The received frame has the address field: a 16.." bitfld.long 0x14 4. "SAM,Self Addressing Mode field" "0: Frame loaded into UFRn at UREGCR[FADD].,1: Frame loaded at receiving address. So with SAM=1.." newline bitfld.long 0x14 0.--1. "FADD,Frames Addressing" "0: UFR0 Upstream Frame Register.,1: UFR1 Upstream Frame Register.,2: UFR2 Upstream Frame Register.,3: UFR3 Upstream Frame Register." line.long 0x18 "UFINTR,Upstream Buffers INTerrupt Register" bitfld.long 0x18 28. "EN_OWRERF,Enable Overwrite Error Frame" "0: The rx_owrerf interrupt request is disabled for..,1: The rx_owrerf interrupt request is enabled for.." bitfld.long 0x18 27. "EN_STOPBERF,Enable Stop Bit Error Frame" "0: The rx_stopbiterf interrupt request is disabled..,1: The rx_stopbiterf interrupt request is enabled.." newline bitfld.long 0x18 26. "EN_PARERF,Enable Parity Error Frame" "0: The rx_paref interrupt request is disabled for..,1: The rx_paref interrupt request is enabled for UCF." bitfld.long 0x18 25. "EN_CONSBERF,Enable Consistency Bit Error Frame" "0: The rx_consbiterf interrupt request is disabled..,1: The rx_consbiterf interrupt request is enabled.." newline bitfld.long 0x18 24. "EN_NEWF,Enable New Frame" "0: The rx_newf interrupt request is disabled for UCF.,1: The rx_newf interrupt request is enabled for UCF." bitfld.long 0x18 20. "OWRERF,Overwrite Error Frame" "0: The OWRERF pending bit is cleared setting by SW..,1: The OWRERF pending bit is set by HW when on a.." newline bitfld.long 0x18 19. "STOPBERF,Stop Bit Error Frame" "0: The STOPBERF pending bit is cleared setting by..,1: The STOPBERF pending bit is set by HW when one.." bitfld.long 0x18 18. "PARERF,Parity Error Frame" "0: The PARERF pending bit is cleared setting by SW..,1: The PARERF pending bit is set by HW only and it.." newline bitfld.long 0x18 17. "CONSBITERF,Consistency Bit Error Frame" "0: The CONSBITERF pending bit is cleared by a SW..,1: The CONSBITERF pending bit is set by HW only.." bitfld.long 0x18 16. "NEWF,New Frame" "0: The NEWF pending bit is cleared by a SW setting.,1: The NEWF pending bit is set by HW only when a.." newline bitfld.long 0x18 15. "PARITY,Frame Parity" "0: The received upstream has parity 0.,1: The received upstream has parity 1." bitfld.long 0x18 12.--14. "STOP,Frame Stop bits field" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 8.--11. 1. "ADD,Frame Address" hexmask.long.byte 0x18 0.--7. 1. "DATA,Frame DATA" line.long 0x1C "UFIFOFR,Upstream FIFO Flag Register" bitfld.long 0x1C 30.--31. "URX_RGFI,Upstream Receiver Register FIFO" "0: both UCF and UFRn disabled.,1: UCF disabled UFRn enabled.,2: UCF enabled not in DMA UFRn disabled.,3: UCF enabled in DMA UFRn disabled." bitfld.long 0x1C 29. "UCF_DMARUN,Upstream Circular FIFO DMA Running" "0: The DMA UCF interface is not working.,1: The DMA UCF interface is working." newline bitfld.long 0x1C 28. "UCF_DMAREQ,Upstream Circular FIFO DMA Request" "0: DMA request is '0'.,1: DMA request is '1'." bitfld.long 0x1C 27. "UCF_FULL,Upstream Circular FIFO Full" "0: The UCF_FULL pending bit is cleared setting by..,1: The UCF_FULL pending bit is set by HW when the.." newline bitfld.long 0x1C 26. "UCF_TVR,Upstream Circular FIFO Threshold Value Reached" "0: The UCF_TVR pending bit is cleared because the..,1: The UCF_TVR pending bit has set because once.." bitfld.long 0x1C 25. "UCF_EMPTY,Upstream Circular FIFO Empty" "0: The UCF_EMPTY pending bit is cleared by setting..,1: The UCF_EMPTY pending bit is set by HW when the.." newline hexmask.long.byte 0x1C 16.--19. 1. "UCF_CT,UCF_CT" bitfld.long 0x1C 9. "UCF_PTRNC,UCF_PTRNC" "0: No rx_ucf_ptrnc interrupt pending.,1: rx_ucf_ptrnc interrupt is pending." newline bitfld.long 0x1C 8. "UCF_PTRCL,UCF_PTRCL" "0: A UCF read/write pointers clearing has been..,1: UCF read/write pointers clearing is running." line.long 0x20 "UFIFOCR,Upstream FIFO Control Register" bitfld.long 0x20 31. "UCF_EN,Upstream Circular FIFO On" "0: The Upstream Circular FIFO is disabled.,1: The Upstream Circular FIFO is enabled." bitfld.long 0x20 30. "UCF_DMA,Upstream Circular FIFO DMA" "0: The enabled Upstream Circular FIFO is accessible..,1: The enabled Upstream Circular FIFO is accessible.." newline bitfld.long 0x20 27. "EN_UCF_FULL,Enable Upstream Circular FIFO FULL" "0: Disable any rx_ucf_full interrupt request.,1: Enable the rx_ucf_full interrupt request coming.." bitfld.long 0x20 26. "EN_UCF_TVR,Enable Upstream Circular FIFO Threshold Value Reached" "0: Disable any rx_ucf_tvr interrupt request.,1: Enable the rx_ucf_tvr interrupt request coming.." newline bitfld.long 0x20 25. "EN_UCF_EMPTY,Enable Upstream Circular FIFO Empty" "0: Disable any rx_ucf_empty interrupt request.,1: Enable the rx_ucf_empty interrupt request coming.." bitfld.long 0x20 16.--18. "UCF_TV,Upstream Circular FIFO Threshold Value" "0: When UFIFOFR[UCF_CT] is equal to 0x1: then..,1: When UFIFOFR[UCF_CT] is equal to 2 then..,2: When UFIFOFR[UCF_CT] is equal to 3 then..,3: When UFIFOFR[UCF_CT] is equal to 4 then..,4: When UFIFOFR[UCF_CT] is equal to 5 then..,5: When UFIFOFR[UCF_CT] is equal to 6 then..,6: When UFIFOFR[UCF_CT] is equal to 7 then..,7: When UFIFOFR[UCF_CT] is equal to 8 then.." newline bitfld.long 0x20 9. "EN_UCF_PTRNC,Enable Upstream Circular FIFO read/write POINTERS Not Cleared" "0: Disable any rx_ucf_ptrnc interrupt request.,1: Enable the rx_ucf_ptrnc interrupt request on.." line.long 0x24 "UECR,Upstream Event Counter Register" bitfld.long 0x24 31. "EN_UNMATCH,Enable Unmatch" "0: The rx_unmatch interrupt is disabled.,1: The rx_unmatch interrupt is enabled." bitfld.long 0x24 30. "UNMATCH,Unmatch flag" "0: The UNMATCH pending bit is cleared setting by SW..,1: The UNMATCH pending bit is set by HW only when.." newline bitfld.long 0x24 27. "STOP0_RUN1,Stop 0 Run 1" "0: The clear stops the down counter and display..,1: The current baud frequency stops the down.." bitfld.long 0x24 24.--26. "EVENTS_OFF,Events number Off" "0: 0 oct,1: 1 oct,2: 2 oct,?,?,?,?,7: 7 oct" newline bitfld.long 0x24 23. "FREER0_SINGLES1,Free Running at 0 Single Shot at 1 mode" "0: On clear it is in free-running mode once the..,1: On set it is in single-shot mode once the down.." bitfld.long 0x24 20.--22. "EVENTS_MIN,Events Minimum number" "0: 0 oct,1: 1 oct,2: 2 oct,?,?,?,?,7: 7 oct" newline hexmask.long.byte 0x24 16.--19. 1. "EVENTS_END,Rx Events on last End Unmatch" hexmask.long.word 0x24 0.--15. 1. "UCYCLESN,Upstream Cycles Number" wgroup.long 0x70++0x3 line.long 0x0 "DFIFOR,Downstream FIFO Register" hexmask.long 0x0 0.--31. 1. "DFIFO,Downstream FIFO frame. A write by SW or by DMA will push the written frame into the Downstream FIFO DCF." group.long 0x74++0x7 line.long 0x0 "DFIFOFR,Downstream FIFO Flag Register" bitfld.long 0x0 30.--31. "DTX_DMAINT,Downstream Transmitter DMA/Interrupt" "0: Both DCF and DMA disabled.,1: Not possible. DFIFOCR[DCF_EN] ='0'..,2: Interrupt/Polling mode for the DCF enabled.,3: DMA mode for the DCF enabled." bitfld.long 0x0 29. "DCF_DMARUN,Downstream Circular FIFO DMA Running" "0: The DMA interface is not working.,1: The DMA interface is working." newline bitfld.long 0x0 28. "DCF_DMAREQ,Downstream Circular FIFO DMA Request" "0: No DMA request is running.,1: A DMA request is running." bitfld.long 0x0 27. "DCF_FULL,Downstream Circular FIFO FULL" "0: The DCF_FULL pending bit is cleared.,1: The DCF_FULL pending bit is set by HW when the.." newline bitfld.long 0x0 26. "DCF_TVR,Downstream Circular FIFO Threshold Value Reached" "0: The DCF_TVR bit is cleared.,1: The DCF_TVR bit is set meaning that the.." bitfld.long 0x0 25. "DCF_EMPTY,Downstream Circular FIFO Empty" "0: The DCF_EMPTY pending bit is cleared.,1: The DCF_EMPTY pending bit is set the DCF is.." newline hexmask.long.byte 0x0 16.--19. 1. "DCF_CT,Downstream Circular FIFO Current Threshold" bitfld.long 0x0 8. "DCF_PTRCL,Downstream Circular FIFO read/write Pointers Clear action" "0: A DCF read/write pointers clearing has been done..,1: DCF read/write pointers clearing is running." line.long 0x4 "DFIFOCR,Downstream FIFO Control Register" bitfld.long 0x4 31. "DCF_EN,Downstream Circular FIFO Enable" "0: The Downstream Circular FIFO is disabled.,1: The Downstream Circular FIFO is Enabled." bitfld.long 0x4 30. "DCF_DMA,Downstream Circular FIFO DMA Selection" "0: The Downstream Circular FIFO is manageable by..,1: The Downstream Circular FIFO is manageable by.." newline bitfld.long 0x4 27. "EN_DCF_FULL,ENable Downstream Circular FIFO Full" "0: Disable any tx_dcf_full interrupt request.,1: Enable the tx_dcf_full interrupt request coming.." bitfld.long 0x4 26. "EN_DCF_TVR,ENable Downstream Circular FIFO Threshold Value Reached" "0: Disable any tx_dcf_tvr interrupt request.,1: Enable the tx_dcf_tvr interrupt request coming.." newline bitfld.long 0x4 25. "EN_DCF_EMPTY,ENable Downstream Circular FIFO Empty" "0: Disable any tx_dcf_empty interrupt request.,1: Enable the tx_dcf_empty interrupt request coming.." bitfld.long 0x4 16.--18. "DCF_TV,Downstream Circular FIFO Threshold Value" "0: When DFIFOFR[DCF_CT] is equal to 0 then..,1: When DFIFOFR[DCF_CT] is equal to 1 then..,2: When DFIFOFR[DCF_CT] is equal to 2 then..,3: When DFIFOFR[DCF_CT] is equal to 3 then..,4: When DFIFOFR[DCF_CT] is equal to 4 then..,5: When DFIFOFR[DCF_CT] is equal to 5 then..,6: When DFIFOFR[DCF_CT] is equal to 6 then..,7: When DFIFOFR[DCF_CT] is equal to 7 then.." rgroup.long 0x7C++0x3 line.long 0x0 "DSR,Downstream Status Register" bitfld.long 0x0 4. "DGT32OR_REQ,DGT32OR update request status bit" "0: DGT32OR register can be updated by SW.,1: DGT32OR has been written by SW and the TX kernel.." bitfld.long 0x0 3. "DFI64OR_REQ,DFI64OR update request status bit" "0: DFI64OR register can be updated by SW.,1: DFI64OR has been written by SW and the TX kernel.." newline bitfld.long 0x0 2. "DTSCR_REQ,DTSCR update request status bit" "0: DTSCR register can be update by SW.,1: DTSCR has been written by SW and the TX kernel.." bitfld.long 0x0 1. "MSCIOR_REQ,MSCIOR update request status bit" "0: MSCIOR register can be updated by SW.,1: MSCIOR has been written by SW and the TX kernel.." newline bitfld.long 0x0 0. "TX_IDLE,Downstream transmitter status bit" "0: A frame transmission is in progress.,1: The asynchronous TX FIFO inside the Downstream.." group.long 0x80++0x6F line.long 0x0 "DH64FR,Downstream High 64-bit Frame Register" hexmask.long 0x0 0.--31. 1. "DH64F,DH64F is a Read/Write bit field which stores the high part bits from 32 up to 63 of a single receiver frame or the data for the second receiver of a dual receiver data frame." line.long 0x4 "DL64FR,Downstream Low 64-bit Frame Register" hexmask.long 0x4 0.--31. 1. "DL64F,DL64F is a Read/Write register field which stores the low part bits from 0 up to 31 of a single receiver frame or the data for the first receiver and eventually also the second receiver of a dual receiver data frame." line.long 0x8 "DHTSFR,Downstream High Generic Timers Frame Register" hexmask.long 0x8 0.--31. 1. "DHGTF,Downstream High Generic Timers Frame" line.long 0xC "DLTSFR,Downstream Low Generic Timers Frame Register" hexmask.long 0xC 0.--31. 1. "DLGTF,Downstream Low Generic Timers Frame" line.long 0x10 "D32FR,Downstream 32-bit Frame Register" hexmask.long 0x10 0.--31. 1. "D32F,Downstream 32 Frame" line.long 0x14 "D64SUR,Downstream 64-bit Set Up Register" bitfld.long 0x14 31. "DS_64,Data Selection bit in a 64 bits TX" "0: It means the single receiver Data frame has not..,1: It means the single receiver Data frame has a.." bitfld.long 0x14 30. "HDS_64,High Data Selection bit in a 64 bits TX" "0: It means the data transmission for the second..,1: It means the data transmission for the second.." newline hexmask.long.byte 0x14 24.--29. 1. "HDN_64,High Data Number in a 64 bits TX" bitfld.long 0x14 23. "C1D0_64,Command 1 Data 0 bit in a 64 bits Tx" "0: The frame to be transmitted is a Data frame.,1: The frame to be transmitted is a Command frame." newline bitfld.long 0x14 22. "LDS_64,Low Data Selection bit in a 64 bits TX" "0: It means the data transmission for the first..,1: It means the data transmission for the first.." hexmask.long.byte 0x14 16.--21. 1. "LDN_64,Low Data Number in a 64 bits TX" newline bitfld.long 0x14 15. "REQ_64,This bit is set by SW in order to issue a new frame transmission and it is cleared only by HW. The SW can use this bit for polling when to write a new request." "0: No transmission request is pending and a new..,1: A new transmission request has been issued by SW.." hexmask.long.byte 0x14 8.--12. 1. "PPN_64,Passive Phases Number in a 64 bits Tx" newline bitfld.long 0x14 7. "ENN_64,Enable Number bit in a 64 bits Tx" "0: Dual receiver data frame the internal Enables..,1: Single receiver data frame the internal Enable.." hexmask.long.byte 0x14 0.--6. 1. "CDN_64,Command Data 64 bits Number" line.long 0x18 "DGTSUR,Downstream Generic Timers Set Up Register" bitfld.long 0x18 31. "DS_GT,Data Selection bit in a GT TX" "0: It means the single receiver Data frame has not..,1: It means the single receiver Data frame has a.." bitfld.long 0x18 30. "HDS_GT,High Data Selection bit in a GT TX" "0: It means the data transmission for the second..,1: It means the data transmission for the second.." newline hexmask.long.byte 0x18 24.--29. 1. "HDN_GT,High Data Number in a GT TX" bitfld.long 0x18 23. "C1D0_GT,Command 1 Data 0 bit in a GT Tx" "0: The frame to be transmitted is a Data frame.,1: receiver" newline bitfld.long 0x18 22. "LDS_GT,Low Data Selection bit in a GT TX" "0: It means the data transmission for the first..,1: It means the data transmission for the first.." hexmask.long.byte 0x18 16.--21. 1. "LDN_GT,Low Data Number in a GT TX" newline bitfld.long 0x18 15. "REQ_GT,This bit is set by SW or HW in order to issue a new frame transmission and it is cleared only by HW. The SW can use this bit for polling when to write a new request." "0: No transmission request is pending and a new..,1: A new transmission request has been issued by SW.." hexmask.long.byte 0x18 8.--12. 1. "PPN_GT,Passive Phases Number in a GT Tx" newline bitfld.long 0x18 7. "ENN_GT,Enable Number bit in a GT Tx" "0: Dual receiver data frame the internal Enables..,1: Single receiver data frame the internal Enable.." hexmask.long.byte 0x18 0.--6. 1. "CDN_GT,Command Data bits Number in a GT Tx" line.long 0x1C "D32SUR,Downstream 32-bit Set Up Register" bitfld.long 0x1C 31. "DS_32,Data Selection bit in a 32 bits TX" "0: It means the single receiver Data frame has not..,1: It means the single receiver Data frame has a.." bitfld.long 0x1C 30. "HDS_32,High Data Selection bit in a 32 bits TX" "0: It means the data transmission for the second..,1: It means the data transmission for the second.." newline hexmask.long.byte 0x1C 24.--29. 1. "HDN_32,High Data Number in a 32 bits TX" bitfld.long 0x1C 23. "C1D0_32,Command 1 Data 0 bit in a 32 bits Tx" "0: The frame to be transmitted is a Data frame.,1: The frame to be transmitted is a Command frame." newline bitfld.long 0x1C 22. "LDS_32,Low Data Selection bit in a 32 bits TX" "0: It means the data transmission for the first..,1: It means the data transmission for the first.." hexmask.long.byte 0x1C 16.--21. 1. "LDN_32,Low Data Number in a 32 bits TX" newline bitfld.long 0x1C 15. "REQ_32,This bit is set by SW in order to issue a new frame transmission and it is cleared by HW only. The SW can use this bit for polling when to write a new request." "0: No transmission request is pending and a new..,1: A new transmission request has been issued by SW.." hexmask.long.byte 0x1C 8.--12. 1. "PPN_32,Passive Phases Number in a 32 bits Tx" newline bitfld.long 0x1C 7. "ENN_32,Enable Number bit in a 32 bits Tx" "0: Dual receiver data frame the internal Enables..,1: Single receiver data frame the internal Enable.." hexmask.long.byte 0x1C 0.--6. 1. "CDN_32,Command Data bits Number in a 32 bits Tx" line.long 0x20 "DFISUR,Downstream FIFO SetUp Register" bitfld.long 0x20 31. "DS_FI,Data Selection bit in a FI TX" "0: It means the single receiver Data frame has not..,1: It means the single receiver Data frame has a.." bitfld.long 0x20 30. "HDS_FI,High Data Selection bit in a FI TX" "0: It means the data transmission for the second..,1: It means the data transmission for the second.." newline hexmask.long.byte 0x20 24.--29. 1. "HDN_FI,High Data Number in a FI TX" bitfld.long 0x20 23. "C1D0_FI,Command 1 Data 0 bit in a FI Tx" "0: The frame to be transmitted is a Data frame.,1: The frame to be transmitted is a Command frame." newline bitfld.long 0x20 22. "LDS_FI,Low Data Selection bit in a FI TX" "0: It means the data transmission for the first..,1: It means the data transmission for the first.." hexmask.long.byte 0x20 16.--21. 1. "LDN_FI,Low Data Number in a FI TX" newline bitfld.long 0x20 15. "REQ_FI,This bit is set by SW or HW in order to issue a new frame transmission and it is cleared only by HW. The SW can use this bit for polling when to write a new request." "0: No transmission request is pending and a new..,1: A new transmission request has been issued by SW.." hexmask.long.byte 0x20 8.--12. 1. "PPN_FI,Passive Phases Number in a FI Tx" newline bitfld.long 0x20 7. "ENN_FI,Enable Number bit in a FI Tx" "0: Dual receiver data frame the internal Enables..,1: Single receiver data frame the internal Enable.." hexmask.long.byte 0x20 0.--6. 1. "CDN_FI,Command Data bits Number in a FI Tx" line.long 0x24 "DGT32OR,Downstream GT/32 Output Register" bitfld.long 0x24 31. "EN_GT,ENable GT 64-bit frames" "0: The DGTSUR register is not writable by SW.,1: The DGTSUR register is writable by SW." bitfld.long 0x24 24.--26. "ENO_GT,ENable to Output GT source configuration bit" "0: msc_deo[0] IP Output displays en.,1: msc_deo[1] IP Output displays en.,2: msc_deo[2] IP Output displays en.,3: msc_deo[3] IP Output displays en.,4: msc_deo[4] IP Output displays en.,5: msc_deo[5] IP Output displays en.,6: msc_deo[6] IP Output displays en.,7: msc_deo[7] IP Output displays en." newline bitfld.long 0x24 20.--22. "HENO_GT,High ENable to Output GT source configuration bit" "0: msc_deo[0] IP Output displays hen.,1: msc_deo[1] IP Output displays hen.,2: msc_deo[2] IP Output displays hen.,3: msc_deo[3] IP Output displays hen.,4: msc_deo[4] IP Output displays hen.,5: msc_deo[5] IP Output displays hen.,6: msc_deo[6] IP Output displays hen.,7: msc_deo[7] IP Output displays hen." bitfld.long 0x24 16.--18. "LENO_GT,Low ENable to Output GT source configuration bit" "0: msc_deo[0] IP Output displays len.,1: msc_deo[1] IP Output displays len.,2: msc_deo[2] IP Output displays len.,3: msc_deo[3] IP Output displays len.,4: msc_deo[4] IP Output displays len.,5: msc_deo[5] IP Output displays len.,6: msc_deo[6] IP Output displays len.,7: msc_deo[7] IP Output displays len." newline bitfld.long 0x24 15. "EN_32,ENable 32 32-bit frames" "0: The D32SUR register is not writable by SW.,1: The D32SUR register is writable by SW." bitfld.long 0x24 8.--10. "ENO_32,Enable to Output 32 source configuration bit" "0: msc_deo[0] IP Output displays en.,1: msc_deo[1] IP Output displays en.,2: msc_deo[2] IP Output displays en.,3: msc_deo[3] IP Output displays en.,4: msc_deo[4] IP Output displays en.,5: msc_deo[5] IP Output displays en.,6: msc_deo[6] IP Output displays en.,7: msc_deo[7] IP Output displays en." newline bitfld.long 0x24 4.--6. "HENO_32,High Enable to Output 32 source configuration bit" "0: msc_deo[0] IP Output displays hen.,1: msc_deo[1] IP Output displays hen.,2: msc_deo[2] IP Output displays hen.,3: msc_deo[3] IP Output displays hen.,4: msc_deo[4] IP Output displays hen.,5: msc_deo[5] IP Output displays hen.,6: msc_deo[6] IP Output displays hen.,7: msc_deo[7] IP Output displays hen." bitfld.long 0x24 0.--2. "LENO_32,Low Enable to Output 32 source configuration bit" "0: msc_deo[0] IP Output displays len.,1: msc_deo[1] IP Output displays len.,2: msc_deo[2] IP Output displays len.,3: msc_deo[3] IP Output displays len.,4: msc_deo[4] IP Output displays len.,5: msc_deo[5] IP Output displays len.,6: msc_deo[6] IP Output displays len.,7: msc_deo[7] IP Output displays len." line.long 0x28 "DFI64OR,Downstream FI/64 Output Register" bitfld.long 0x28 31. "EN_FI,ENable FI frame source" "0: The DFISUR register is not writable by SW.,1: The DFISUR[31:0] register is writable by SW." bitfld.long 0x28 24.--26. "ENO_FI,ENable to Output FI source configuration bits" "0: msc_deo[0] IP Output displays en.,1: msc_deo[1] IP Output displays en.,2: msc_deo[2] IP Output displays en.,3: msc_deo[3] IP Output displays en.,4: msc_deo[4] IP Output displays en.,5: msc_deo[5] IP Output displays en.,6: msc_deo[6] IP Output displays en.,7: msc_deo[7] IP Output displays en." newline bitfld.long 0x28 20.--22. "HENO_FI,High ENable to Output FI source configuration bits" "0: msc_deo[0] IP Output displays hen.,1: msc_deo[1] IP Output displays hen.,2: msc_deo[2] IP Output displays hen.,3: msc_deo[3] IP Output displays hen.,4: msc_deo[4] IP Output displays hen.,5: msc_deo[5] IP Output displays hen.,6: msc_deo[6] IP Output displays hen.,7: msc_deo[7] IP Output displays hen." bitfld.long 0x28 16.--18. "LENO_FI,Low ENable to Output FI source configuration bits" "0: 0x0: msc_deo[0] IP Output displays len.,1: msc_deo[1] IP Output displays len.,2: msc_deo[2] IP Output displays len.,3: msc_deo[3] IP Output displays len.,4: msc_deo[4] IP Output displays len.,5: msc_deo[5] IP Output displays len.,6: msc_deo[6] IP Output displays len.,7: msc_deo[7] IP Output displays len." newline bitfld.long 0x28 15. "EN_64,ENable 64-bit frames source" "0: The D64SUR register is not writable by SW.,1: The D64SUR register is writable by SW." bitfld.long 0x28 8.--10. "ENO_64,ENable to Output 64-bits source configuration bits" "0: msc_deo[0] IP Output displays en.,1: msc_deo[1] IP Output displays en.,2: msc_deo[2] IP Output displays en.,3: msc_deo[3] IP Output displays en.,4: msc_deo[4] IP Output displays en.,5: msc_deo[5] IP Output displays en.,6: msc_deo[6] IP Output displays en.,7: msc_deo[7] IP Output displays en." newline bitfld.long 0x28 4.--6. "HENO_64,High ENable to Output 64-bits source configuration bits" "0: msc_deo[0] IP Output displays hen.,1: msc_deo[1] IP Output displays hen.,2: msc_deo[2] IP Output displays hen.,3: msc_deo[3] IP Output displays hen.,4: msc_deo[4] IP Output displays hen.,5: msc_deo[5] IP Output displays hen.,6: msc_deo[6] IP Output displays hen.,7: msc_deo[7] IP Output displays hen." bitfld.long 0x28 0.--2. "LENO_64,Low ENable to Output 64-bits source configuration bits" "0: msc_deo[0] IP Output displays len.,1: msc_deo[1] IP Output displays len.,2: msc_deo[2] IP Output displays len.,3: msc_deo[3] IP Output displays len.,4: msc_deo[4] IP Output displays len.,5: msc_deo[5] IP Output displays len.,6: msc_deo[6] IP Output displays len.,7: msc_deo[7] IP Output displays len." line.long 0x2C "DPPMPR,Downstream Passive Phase Modulation Priority Register" bitfld.long 0x2C 28.--29. "PRI_32,PRIority 32-bits source configuration bits" "0: The priority value is 0.,1: The priority value is 1.,2: The priority value is 2.,3: The priority value is 3." bitfld.long 0x2C 24.--25. "PRI_64,PRIority 64-bits source configuration bits" "0: The priority value is 0.,1: The priority value is 1.,2: The priority value is 2.,3: The priority value is 3." newline bitfld.long 0x2C 20.--21. "PRI_GT,PRIority Generic-Timers source configuration bits" "0: The priority value is 0.,1: The priority value is 1.,2: The priority value is 2.,3: The priority value is 3." bitfld.long 0x2C 16.--17. "PRI_FI,Priority FI source configuration bits" "0: The priority value is 0.,1: The priority value is 1.,2: The priority value is 2.,3: The priority value is 3." newline bitfld.long 0x2C 8. "ENH_32B,Enable High on dedicated 32-bit register" "0: Only the low register of a 64-bits source is..,1: Both the high and low register of a 64-bits.." bitfld.long 0x2C 6. "PPM,Passive Phase Modulation" "0: The passive phase modulation is not enabled.,1: The passive phase modulation is enabled." line.long 0x30 "DTSCR,Downstream Timer Siul Counter Register" bitfld.long 0x30 31. "H0S1_SAMPLE,Hardware 0 Software 1 SAMPLE. H0S1_SAMPLE is a Read/Write bit field. The H0S1_SAMPLE control bit selects a SW or HW sampling for the input data of the DTSFR source." "0: Hardware sampling from siul_sample input selected.,1: Software sampling from Down-counter EOC selected." bitfld.long 0x30 30. "DSTART_CNT,START CouNTer. DSTART_CNT is a Read/Write bit field. The DSTART_CNT control field starts the counter if it is set otherwise the down-counter is stopped." "0: The counter is stopped.,1: The counter is started." newline hexmask.long.tbyte 0x30 0.--23. 1. "DCYCLESN,Downstream CYCLES Number" line.long 0x34 "DHTSMR,Downstream High Timers SIUL Mux Register" hexmask.long 0x34 0.--31. 1. "DHTSM,Downstream High SIUL Mux" line.long 0x38 "DLTSMR,Downstream Low Timers SIUL Mux Register" hexmask.long 0x38 0.--31. 1. "DLTSM,Downstream Low Timers SIUL Mux" line.long 0x3C "DFR,Downstream Flag Register" bitfld.long 0x3C 31. "EN_NOPEND_32REQ,This bit enable/disable the corresponding NOPEND_32REQ interrupt." "0: The NOPEND_32REQ interrupt is disabled.,1: The NOPEND_32REQ interrupt is enabled." bitfld.long 0x3C 30. "NOPEND_32REQ,Interrupt bit for the 32 bits frame source." "0: A request is pending.,1: A new request can be issued by the SW." newline bitfld.long 0x3C 29. "EN_NOPEND_64REQ,This bit enable/disable the corresponding NOPEND_64REQ interrupt." "0: The NOPEND_64REQ interrupt is disabled.,1: The NOPEND_64REQ interrupt is enabled." bitfld.long 0x3C 28. "NOPEND_64REQ,Interrupt bit for the 64 bits frame source." "0: A request is pending.,1: A new request can be issued by the SW." newline bitfld.long 0x3C 27. "EN_NOPEND_FIREQ,This bit enable/disable the corresponding NOPEND_64REQ interrupt." "0: The NOPEND_FIREQ interrupt is disabled.,1: The NOPEND_FIREQ interrupt is enabled." bitfld.long 0x3C 26. "NOPEND_FIREQ,Interrupt bit for the Downstream Circular FIFO DCF frame source." "0: A request is pending.,1: A new request can be issued by SW or by HW." newline bitfld.long 0x3C 25. "EN_NOPEND_GTREQ,This bit enable/disable the corresponding NOPEND_GTREQ interrupt." "0: The NOPEND_GTREQ interrupt is disabled.,1: The NOPEND_GTREQ interrupt is enabled." bitfld.long 0x3C 24. "NOPEND_GTREQ,Interrupt bit for the DTSFR frame source." "0: A request is pending.,1: A new request can be issued by SW or by HW." line.long 0x40 "DHPISR0,Downstream Hardware Parallel Input Select Register 0" hexmask.long.byte 0x40 28.--31. 1. "DHPIS7,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x40 24.--27. 1. "DHPIS6,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x40 20.--23. 1. "DHPIS5,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x40 16.--19. 1. "DHPIS4,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x40 12.--15. 1. "DHPIS3,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x40 8.--11. 1. "DHPIS2,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x40 4.--7. 1. "DHPIS1,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x40 0.--3. 1. "DHPIS0,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x44 "DHPISR1,Downstream Hardware Parallel Input Select Register 1" hexmask.long.byte 0x44 28.--31. 1. "DHPIS15,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x44 24.--27. 1. "DHPIS14,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x44 20.--23. 1. "DHPIS13,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x44 16.--19. 1. "DHPIS12,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x44 12.--15. 1. "DHPIS11,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x44 8.--11. 1. "DHPIS10,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x44 4.--7. 1. "DHPIS9,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x44 0.--3. 1. "DHPIS8,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x48 "DHPISR2,Downstream Hardware Parallel Input Select Register 2" hexmask.long.byte 0x48 28.--31. 1. "DHPIS23,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x48 24.--27. 1. "DHPIS22,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x48 20.--23. 1. "DHPIS21,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x48 16.--19. 1. "DHPIS20,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x48 12.--15. 1. "DHPIS19,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x48 8.--11. 1. "DHPIS18,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x48 4.--7. 1. "DHPIS17,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x48 0.--3. 1. "DHPIS16,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x4C "DHPISR3,Downstream Hardware Parallel Input Select Register 3" hexmask.long.byte 0x4C 28.--31. 1. "DHPIS31,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x4C 24.--27. 1. "DHPIS30,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x4C 20.--23. 1. "DHPIS29,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x4C 16.--19. 1. "DHPIS28,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x4C 12.--15. 1. "DHPIS27,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x4C 8.--11. 1. "DHPIS26,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x4C 4.--7. 1. "DHPIS25,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x4C 0.--3. 1. "DHPIS24,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x50 "DHPISR4,Downstream Hardware Parallel Input Select Register 4" hexmask.long.byte 0x50 28.--31. 1. "DHPIS39,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x50 24.--27. 1. "DHPIS38,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x50 20.--23. 1. "DHPIS37,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x50 16.--19. 1. "DHPIS36,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x50 12.--15. 1. "DHPIS35,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x50 8.--11. 1. "DHPIS34,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x50 4.--7. 1. "DHPIS33,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x50 0.--3. 1. "DHPIS32,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x54 "DHPISR5,Downstream Hardware Parallel Input Select Register 5" hexmask.long.byte 0x54 28.--31. 1. "DHPIS47,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x54 24.--27. 1. "DHPIS46,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x54 20.--23. 1. "DHPIS45,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x54 16.--19. 1. "DHPIS44,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x54 12.--15. 1. "DHPIS43,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x54 8.--11. 1. "DHPIS42,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x54 4.--7. 1. "DHPIS41,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x54 0.--3. 1. "DHPIS40,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x58 "DHPISR6,Downstream Hardware Parallel Input Select Register 6" hexmask.long.byte 0x58 28.--31. 1. "DHPIS55,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x58 24.--27. 1. "DHPIS54,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x58 20.--23. 1. "DHPIS53,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x58 16.--19. 1. "DHPIS52,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x58 12.--15. 1. "DHPIS51,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x58 8.--11. 1. "DHPIS50,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x58 4.--7. 1. "DHPIS49,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x58 0.--3. 1. "DHPIS48,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x5C "DHPISR7,Downstream Hardware Parallel Input Select Register 7" hexmask.long.byte 0x5C 28.--31. 1. "DHPIS63,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x5C 24.--27. 1. "DHPIS62,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x5C 20.--23. 1. "DHPIS61,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x5C 16.--19. 1. "DHPIS60,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x5C 12.--15. 1. "DHPIS59,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x5C 8.--11. 1. "DHPIS58,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x5C 4.--7. 1. "DHPIS57,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x5C 0.--3. 1. "DHPIS56,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x60 "DHSBSR,Downstream High SIUL By Software Register" hexmask.long 0x60 0.--31. 1. "DHSBSW,Downstream High SIUL By Software" line.long 0x64 "DLSBSR,Downstream Low SIUL By Software Register" hexmask.long 0x64 0.--31. 1. "DLSBSW,Downstream Low SIUL By Software" line.long 0x68 "DHSBHR,Downstream High SIUL By Hardware Register" hexmask.long 0x68 0.--31. 1. "DHSBHW,Downstream High SIUL By Hardware" line.long 0x6C "DLSBHR,Downstream Low SIUL By Hardware Register" hexmask.long 0x6C 0.--31. 1. "DLSBHW,Downstream Low SIUL By Hardware" tree.end tree "MSC_3" base ad:0x71A6C000 group.long 0x0++0x7 line.long 0x0 "MSCCCR,MSC Clock Control Register" bitfld.long 0x0 16. "EN_RX_RSTN,ENable RX ReSeTN. EN_RX_RSTN is a Read/Write bit field. The EN_RX_RSTN bit enables an HW Synchronous Reset on all MSC RX of msc_uck domain circuitry triggered when [UECR]UNMATCH asserts." "0: The [UECR]UNMATCH never resets the MSC RX..,1: On [UECR]UNMATCH field asserting the MSC RX.." hexmask.long.byte 0x0 0.--7. 1. "MSCCK_DIV,MSC ClocK DIVider. MSCCK_DIV is a 8-bits Read/Write field. According to the following definition the msc_clk clock frequency is divisible for: 4 6 8 10 12 16 20 24 40." line.long 0x4 "MSCIOR,MSC Inputs Outputs Register" bitfld.long 0x4 19. "CKP,Clock Polarity" "0: Normal polarity.,1: Inverse polarity." bitfld.long 0x4 18. "CKA,Clock always Active" "0: It means msc_dclk is active only when enables..,1: It means msc_dclk is always active." newline bitfld.long 0x4 17. "CK_DIFF,Clock output Differential" "0: The MSC msc_dclk Downstream Clock is not in..,1: The MSC msc_dclk Downstream Clock is in.." bitfld.long 0x4 16. "CK_OBE,ClocK Output Buffer Enable" "0: The MSC msc_dclk Downstream clock output is not..,1: The MSC msc_dclk Downstream clock output is.." newline bitfld.long 0x4 4. "ENP,Enable Polarity" "0: Normal polarity.,1: " bitfld.long 0x4 3. "DSOP,Downstream Serial Output Polarity register" "0: Normal polarity.,1: Inverse polarity." newline bitfld.long 0x4 1. "DSO_DIFF,Data Serial Output Differential" "0: The MSC msc_dso Downstream Serial data Out is..,1: The MSC msc_dso Downstream Serial data Out is in.." bitfld.long 0x4 0. "DSO_OBE,Data Serial Output Buffer Enable" "0: The MSC msc_dso Downstream Serial data Out is..,1: The MSC msc_dso Downstream Serial data Out is.." rgroup.long 0xC++0x3 line.long 0x0 "UFIFOR,Upstream FIFO Register" hexmask.long 0x0 0.--31. 1. "UFIFO,Upstream FIFO frame" group.long 0x10++0x27 line.long 0x0 "UFR0,Upstream Frame Register 0" bitfld.long 0x0 28. "EN_OWRERF,Enable Overwrite Error Frame" "0: The rx_owrerf interrupt request is disabled in..,1: The rx_owrerf interrupt request is enabled in.." bitfld.long 0x0 27. "EN_STOPBERF,Enable Stop Bit Error Frame" "0: The rx_stopbiterf interrupt request is disabled..,1: The rx_stopbiterf interrupt request is enabled.." newline bitfld.long 0x0 26. "EN_PARERF,Enable Parity Error Frame n" "0: The rx_parerf interrupt request is disabled in..,1: The rx_parerf interrupt request is enabled in.." bitfld.long 0x0 25. "EN_CONSBERF,Enable Consistency Bit Error Frame" "0: The rx_consbiterf interrupt request is disabled..,1: The rx_consbiterf interrupt request is enabled.." newline bitfld.long 0x0 24. "EN_NEWF,Enable New Frame" "0: The rx_newf interrupt request is disabled in UFRn.,1: The rx_newf interrupt request is enabled in UFRn." bitfld.long 0x0 20. "OWRERF,Overwrite Error Frame" "0: The OWRERF pending bit is cleared setting by SW..,1: The OWRERF pending bit is set by HW when on a.." newline bitfld.long 0x0 19. "STOPBERF,Stop Bit Error Frame" "0: The STOPBERF pending bit is cleared setting by..,1: The STOPBERF pending bit is set by HW when one.." bitfld.long 0x0 18. "PARERF,Parity Error Frame" "0: The PARERF pending bit is cleared setting by SW..,1: The PARERF pending bit is set by HW only and it.." newline bitfld.long 0x0 17. "CONSBITERF,Consistency Bit Error Frame n" "0: The CONSBERF pending bit is cleared by a SW..,1: The CONSBERF pending bit is set by HW only when.." bitfld.long 0x0 16. "NEWF,New Frame" "0: The NEWF pending bit is cleared by a SW setting.,1: The NEWF pending bit is set by HW only when a.." newline bitfld.long 0x0 15. "PARITY,UFRn Parity field" "0: The received upstream has parity 0.,1: The received upstream has parity 1." bitfld.long 0x0 12.--14. "STOP,UFRn Stop bits" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "ADD,UFRn Address" hexmask.long.byte 0x0 0.--7. 1. "DATA,UFRn Data" line.long 0x4 "UFR1,Upstream Frame Register 1" bitfld.long 0x4 28. "EN_OWRERF,Enable Overwrite Error Frame" "0: The rx_owrerf interrupt request is disabled in..,1: The rx_owrerf interrupt request is enabled in.." bitfld.long 0x4 27. "EN_STOPBERF,Enable Stop Bit Error Frame" "0: The rx_stopbiterf interrupt request is disabled..,1: The rx_stopbiterf interrupt request is enabled.." newline bitfld.long 0x4 26. "EN_PARERF,Enable Parity Error Frame n" "0: The rx_parerf interrupt request is disabled in..,1: The rx_parerf interrupt request is enabled in.." bitfld.long 0x4 25. "EN_CONSBERF,Enable Consistency Bit Error Frame" "0: The rx_consbiterf interrupt request is disabled..,1: The rx_consbiterf interrupt request is enabled.." newline bitfld.long 0x4 24. "EN_NEWF,Enable New Frame" "0: The rx_newf interrupt request is disabled in UFRn.,1: The rx_newf interrupt request is enabled in UFRn." bitfld.long 0x4 20. "OWRERF,Overwrite Error Frame" "0: The OWRERF pending bit is cleared setting by SW..,1: The OWRERF pending bit is set by HW when on a.." newline bitfld.long 0x4 19. "STOPBERF,Stop Bit Error Frame" "0: The STOPBERF pending bit is cleared setting by..,1: The STOPBERF pending bit is set by HW when one.." bitfld.long 0x4 18. "PARERF,Parity Error Frame" "0: The PARERF pending bit is cleared setting by SW..,1: The PARERF pending bit is set by HW only and it.." newline bitfld.long 0x4 17. "CONSBITERF,Consistency Bit Error Frame n" "0: The CONSBERF pending bit is cleared by a SW..,1: The CONSBERF pending bit is set by HW only when.." bitfld.long 0x4 16. "NEWF,New Frame" "0: The NEWF pending bit is cleared by a SW setting.,1: The NEWF pending bit is set by HW only when a.." newline bitfld.long 0x4 15. "PARITY,UFRn Parity field" "0: The received upstream has parity 0.,1: The received upstream has parity 1." bitfld.long 0x4 12.--14. "STOP,UFRn Stop bits" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "ADD,UFRn Address" hexmask.long.byte 0x4 0.--7. 1. "DATA,UFRn Data" line.long 0x8 "UFR2,Upstream Frame Register 2" bitfld.long 0x8 28. "EN_OWRERF,Enable Overwrite Error Frame" "0: The rx_owrerf interrupt request is disabled in..,1: The rx_owrerf interrupt request is enabled in.." bitfld.long 0x8 27. "EN_STOPBERF,Enable Stop Bit Error Frame" "0: The rx_stopbiterf interrupt request is disabled..,1: The rx_stopbiterf interrupt request is enabled.." newline bitfld.long 0x8 26. "EN_PARERF,Enable Parity Error Frame n" "0: The rx_parerf interrupt request is disabled in..,1: The rx_parerf interrupt request is enabled in.." bitfld.long 0x8 25. "EN_CONSBERF,Enable Consistency Bit Error Frame" "0: The rx_consbiterf interrupt request is disabled..,1: The rx_consbiterf interrupt request is enabled.." newline bitfld.long 0x8 24. "EN_NEWF,Enable New Frame" "0: The rx_newf interrupt request is disabled in UFRn.,1: The rx_newf interrupt request is enabled in UFRn." bitfld.long 0x8 20. "OWRERF,Overwrite Error Frame" "0: The OWRERF pending bit is cleared setting by SW..,1: The OWRERF pending bit is set by HW when on a.." newline bitfld.long 0x8 19. "STOPBERF,Stop Bit Error Frame" "0: The STOPBERF pending bit is cleared setting by..,1: The STOPBERF pending bit is set by HW when one.." bitfld.long 0x8 18. "PARERF,Parity Error Frame" "0: The PARERF pending bit is cleared setting by SW..,1: The PARERF pending bit is set by HW only and it.." newline bitfld.long 0x8 17. "CONSBITERF,Consistency Bit Error Frame n" "0: The CONSBERF pending bit is cleared by a SW..,1: The CONSBERF pending bit is set by HW only when.." bitfld.long 0x8 16. "NEWF,New Frame" "0: The NEWF pending bit is cleared by a SW setting.,1: The NEWF pending bit is set by HW only when a.." newline bitfld.long 0x8 15. "PARITY,UFRn Parity field" "0: The received upstream has parity 0.,1: The received upstream has parity 1." bitfld.long 0x8 12.--14. "STOP,UFRn Stop bits" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "ADD,UFRn Address" hexmask.long.byte 0x8 0.--7. 1. "DATA,UFRn Data" line.long 0xC "UFR3,Upstream Frame Register 3" bitfld.long 0xC 28. "EN_OWRERF,Enable Overwrite Error Frame" "0: The rx_owrerf interrupt request is disabled in..,1: The rx_owrerf interrupt request is enabled in.." bitfld.long 0xC 27. "EN_STOPBERF,Enable Stop Bit Error Frame" "0: The rx_stopbiterf interrupt request is disabled..,1: The rx_stopbiterf interrupt request is enabled.." newline bitfld.long 0xC 26. "EN_PARERF,Enable Parity Error Frame n" "0: The rx_parerf interrupt request is disabled in..,1: The rx_parerf interrupt request is enabled in.." bitfld.long 0xC 25. "EN_CONSBERF,Enable Consistency Bit Error Frame" "0: The rx_consbiterf interrupt request is disabled..,1: The rx_consbiterf interrupt request is enabled.." newline bitfld.long 0xC 24. "EN_NEWF,Enable New Frame" "0: The rx_newf interrupt request is disabled in UFRn.,1: The rx_newf interrupt request is enabled in UFRn." bitfld.long 0xC 20. "OWRERF,Overwrite Error Frame" "0: The OWRERF pending bit is cleared setting by SW..,1: The OWRERF pending bit is set by HW when on a.." newline bitfld.long 0xC 19. "STOPBERF,Stop Bit Error Frame" "0: The STOPBERF pending bit is cleared setting by..,1: The STOPBERF pending bit is set by HW when one.." bitfld.long 0xC 18. "PARERF,Parity Error Frame" "0: The PARERF pending bit is cleared setting by SW..,1: The PARERF pending bit is set by HW only and it.." newline bitfld.long 0xC 17. "CONSBITERF,Consistency Bit Error Frame n" "0: The CONSBERF pending bit is cleared by a SW..,1: The CONSBERF pending bit is set by HW only when.." bitfld.long 0xC 16. "NEWF,New Frame" "0: The NEWF pending bit is cleared by a SW setting.,1: The NEWF pending bit is set by HW only when a.." newline bitfld.long 0xC 15. "PARITY,UFRn Parity field" "0: The received upstream has parity 0.,1: The received upstream has parity 1." bitfld.long 0xC 12.--14. "STOP,UFRn Stop bits" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "ADD,UFRn Address" hexmask.long.byte 0xC 0.--7. 1. "DATA,UFRn Data" line.long 0x10 "UKERCR,Upstream Kernel Control Register" bitfld.long 0x10 31. "US_REQ,Upstream Setup Request" "0: The USREQ is cleared by HW a clk cycle after its..,1: The USREQ setting is kept for one clk cycle only." bitfld.long 0x10 30. "US_ACK,Upstream Setup Acknowledge" "0: Meanwhile the new set up values are loaded to..,1: The Rx kernel has received the new setup values." newline bitfld.long 0x10 29. "USRA_R,Upstream Setup Request Acknowledge Reset" "0: Both US_REQ and US_ACK bits can be accessed.,1: Both US_REQ and US_ACK bits are forced low." bitfld.long 0x10 20. "IUIS,Inverted Upstream Input Selector field" "0: The msc_usi input will be evaluated with no..,1: The msc_usi input will be evaluated forcing a.." newline bitfld.long 0x10 16.--18. "USISEL,Upstream Serial Input Selections" "0: Selects the msc_usi[0] input line,1: Selects the msc_usi[1] input line,2: Selects the msc_usi[2] input line,3: Selects the msc_usi[3] input line,4: Selects the msc_usi[4] input line,5: Selects the msc_usi[5] input line,6: Selects the msc_usi[6] input line,7: Selects the msc_usi[7] input line" bitfld.long 0x10 4.--5. "USBN,Upstream Stop Bits Number" "0: 2 Stop Bits,1: 1 Stop Bit,2: 2 Stop Bits,3: 3 Stop Bits" newline bitfld.long 0x10 0.--2. "UBR,Upstream Baud Rate" "0: Rx kernel disabled,1: Baud Rate = fMSC/4,2: Baud Rate = fMSC/8,3: Baud Rate = fMSC/16,4: Baud Rate = fMSC/32,5: Baud Rate = fMSC/64,6: Baud Rate = fMSC/128,7: Baud Rate = fMSC/256" line.long 0x14 "UREGCR,Upstream Registers Control Register" bitfld.long 0x14 31. "UREG_EN,Upstream Register Enable" "0,1" bitfld.long 0x14 12. "UPT,Upstream Parity Type" "0: The msc_usi input will be evaluated with an even..,1: The msc_usi input will be evaluated with an odd.." newline bitfld.long 0x14 8. "UAE,Upstream Address Enable" "0: The received frame is without the address field:..,1: The received frame has the address field: a 16.." bitfld.long 0x14 4. "SAM,Self Addressing Mode field" "0: Frame loaded into UFRn at UREGCR[FADD].,1: Frame loaded at receiving address. So with SAM=1.." newline bitfld.long 0x14 0.--1. "FADD,Frames Addressing" "0: UFR0 Upstream Frame Register.,1: UFR1 Upstream Frame Register.,2: UFR2 Upstream Frame Register.,3: UFR3 Upstream Frame Register." line.long 0x18 "UFINTR,Upstream Buffers INTerrupt Register" bitfld.long 0x18 28. "EN_OWRERF,Enable Overwrite Error Frame" "0: The rx_owrerf interrupt request is disabled for..,1: The rx_owrerf interrupt request is enabled for.." bitfld.long 0x18 27. "EN_STOPBERF,Enable Stop Bit Error Frame" "0: The rx_stopbiterf interrupt request is disabled..,1: The rx_stopbiterf interrupt request is enabled.." newline bitfld.long 0x18 26. "EN_PARERF,Enable Parity Error Frame" "0: The rx_paref interrupt request is disabled for..,1: The rx_paref interrupt request is enabled for UCF." bitfld.long 0x18 25. "EN_CONSBERF,Enable Consistency Bit Error Frame" "0: The rx_consbiterf interrupt request is disabled..,1: The rx_consbiterf interrupt request is enabled.." newline bitfld.long 0x18 24. "EN_NEWF,Enable New Frame" "0: The rx_newf interrupt request is disabled for UCF.,1: The rx_newf interrupt request is enabled for UCF." bitfld.long 0x18 20. "OWRERF,Overwrite Error Frame" "0: The OWRERF pending bit is cleared setting by SW..,1: The OWRERF pending bit is set by HW when on a.." newline bitfld.long 0x18 19. "STOPBERF,Stop Bit Error Frame" "0: The STOPBERF pending bit is cleared setting by..,1: The STOPBERF pending bit is set by HW when one.." bitfld.long 0x18 18. "PARERF,Parity Error Frame" "0: The PARERF pending bit is cleared setting by SW..,1: The PARERF pending bit is set by HW only and it.." newline bitfld.long 0x18 17. "CONSBITERF,Consistency Bit Error Frame" "0: The CONSBITERF pending bit is cleared by a SW..,1: The CONSBITERF pending bit is set by HW only.." bitfld.long 0x18 16. "NEWF,New Frame" "0: The NEWF pending bit is cleared by a SW setting.,1: The NEWF pending bit is set by HW only when a.." newline bitfld.long 0x18 15. "PARITY,Frame Parity" "0: The received upstream has parity 0.,1: The received upstream has parity 1." bitfld.long 0x18 12.--14. "STOP,Frame Stop bits field" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 8.--11. 1. "ADD,Frame Address" hexmask.long.byte 0x18 0.--7. 1. "DATA,Frame DATA" line.long 0x1C "UFIFOFR,Upstream FIFO Flag Register" bitfld.long 0x1C 30.--31. "URX_RGFI,Upstream Receiver Register FIFO" "0: both UCF and UFRn disabled.,1: UCF disabled UFRn enabled.,2: UCF enabled not in DMA UFRn disabled.,3: UCF enabled in DMA UFRn disabled." bitfld.long 0x1C 29. "UCF_DMARUN,Upstream Circular FIFO DMA Running" "0: The DMA UCF interface is not working.,1: The DMA UCF interface is working." newline bitfld.long 0x1C 28. "UCF_DMAREQ,Upstream Circular FIFO DMA Request" "0: DMA request is '0'.,1: DMA request is '1'." bitfld.long 0x1C 27. "UCF_FULL,Upstream Circular FIFO Full" "0: The UCF_FULL pending bit is cleared setting by..,1: The UCF_FULL pending bit is set by HW when the.." newline bitfld.long 0x1C 26. "UCF_TVR,Upstream Circular FIFO Threshold Value Reached" "0: The UCF_TVR pending bit is cleared because the..,1: The UCF_TVR pending bit has set because once.." bitfld.long 0x1C 25. "UCF_EMPTY,Upstream Circular FIFO Empty" "0: The UCF_EMPTY pending bit is cleared by setting..,1: The UCF_EMPTY pending bit is set by HW when the.." newline hexmask.long.byte 0x1C 16.--19. 1. "UCF_CT,UCF_CT" bitfld.long 0x1C 9. "UCF_PTRNC,UCF_PTRNC" "0: No rx_ucf_ptrnc interrupt pending.,1: rx_ucf_ptrnc interrupt is pending." newline bitfld.long 0x1C 8. "UCF_PTRCL,UCF_PTRCL" "0: A UCF read/write pointers clearing has been..,1: UCF read/write pointers clearing is running." line.long 0x20 "UFIFOCR,Upstream FIFO Control Register" bitfld.long 0x20 31. "UCF_EN,Upstream Circular FIFO On" "0: The Upstream Circular FIFO is disabled.,1: The Upstream Circular FIFO is enabled." bitfld.long 0x20 30. "UCF_DMA,Upstream Circular FIFO DMA" "0: The enabled Upstream Circular FIFO is accessible..,1: The enabled Upstream Circular FIFO is accessible.." newline bitfld.long 0x20 27. "EN_UCF_FULL,Enable Upstream Circular FIFO FULL" "0: Disable any rx_ucf_full interrupt request.,1: Enable the rx_ucf_full interrupt request coming.." bitfld.long 0x20 26. "EN_UCF_TVR,Enable Upstream Circular FIFO Threshold Value Reached" "0: Disable any rx_ucf_tvr interrupt request.,1: Enable the rx_ucf_tvr interrupt request coming.." newline bitfld.long 0x20 25. "EN_UCF_EMPTY,Enable Upstream Circular FIFO Empty" "0: Disable any rx_ucf_empty interrupt request.,1: Enable the rx_ucf_empty interrupt request coming.." bitfld.long 0x20 16.--18. "UCF_TV,Upstream Circular FIFO Threshold Value" "0: When UFIFOFR[UCF_CT] is equal to 0x1: then..,1: When UFIFOFR[UCF_CT] is equal to 2 then..,2: When UFIFOFR[UCF_CT] is equal to 3 then..,3: When UFIFOFR[UCF_CT] is equal to 4 then..,4: When UFIFOFR[UCF_CT] is equal to 5 then..,5: When UFIFOFR[UCF_CT] is equal to 6 then..,6: When UFIFOFR[UCF_CT] is equal to 7 then..,7: When UFIFOFR[UCF_CT] is equal to 8 then.." newline bitfld.long 0x20 9. "EN_UCF_PTRNC,Enable Upstream Circular FIFO read/write POINTERS Not Cleared" "0: Disable any rx_ucf_ptrnc interrupt request.,1: Enable the rx_ucf_ptrnc interrupt request on.." line.long 0x24 "UECR,Upstream Event Counter Register" bitfld.long 0x24 31. "EN_UNMATCH,Enable Unmatch" "0: The rx_unmatch interrupt is disabled.,1: The rx_unmatch interrupt is enabled." bitfld.long 0x24 30. "UNMATCH,Unmatch flag" "0: The UNMATCH pending bit is cleared setting by SW..,1: The UNMATCH pending bit is set by HW only when.." newline bitfld.long 0x24 27. "STOP0_RUN1,Stop 0 Run 1" "0: The clear stops the down counter and display..,1: The current baud frequency stops the down.." bitfld.long 0x24 24.--26. "EVENTS_OFF,Events number Off" "0: 0 oct,1: 1 oct,2: 2 oct,?,?,?,?,7: 7 oct" newline bitfld.long 0x24 23. "FREER0_SINGLES1,Free Running at 0 Single Shot at 1 mode" "0: On clear it is in free-running mode once the..,1: On set it is in single-shot mode once the down.." bitfld.long 0x24 20.--22. "EVENTS_MIN,Events Minimum number" "0: 0 oct,1: 1 oct,2: 2 oct,?,?,?,?,7: 7 oct" newline hexmask.long.byte 0x24 16.--19. 1. "EVENTS_END,Rx Events on last End Unmatch" hexmask.long.word 0x24 0.--15. 1. "UCYCLESN,Upstream Cycles Number" wgroup.long 0x70++0x3 line.long 0x0 "DFIFOR,Downstream FIFO Register" hexmask.long 0x0 0.--31. 1. "DFIFO,Downstream FIFO frame. A write by SW or by DMA will push the written frame into the Downstream FIFO DCF." group.long 0x74++0x7 line.long 0x0 "DFIFOFR,Downstream FIFO Flag Register" bitfld.long 0x0 30.--31. "DTX_DMAINT,Downstream Transmitter DMA/Interrupt" "0: Both DCF and DMA disabled.,1: Not possible. DFIFOCR[DCF_EN] ='0'..,2: Interrupt/Polling mode for the DCF enabled.,3: DMA mode for the DCF enabled." bitfld.long 0x0 29. "DCF_DMARUN,Downstream Circular FIFO DMA Running" "0: The DMA interface is not working.,1: The DMA interface is working." newline bitfld.long 0x0 28. "DCF_DMAREQ,Downstream Circular FIFO DMA Request" "0: No DMA request is running.,1: A DMA request is running." bitfld.long 0x0 27. "DCF_FULL,Downstream Circular FIFO FULL" "0: The DCF_FULL pending bit is cleared.,1: The DCF_FULL pending bit is set by HW when the.." newline bitfld.long 0x0 26. "DCF_TVR,Downstream Circular FIFO Threshold Value Reached" "0: The DCF_TVR bit is cleared.,1: The DCF_TVR bit is set meaning that the.." bitfld.long 0x0 25. "DCF_EMPTY,Downstream Circular FIFO Empty" "0: The DCF_EMPTY pending bit is cleared.,1: The DCF_EMPTY pending bit is set the DCF is.." newline hexmask.long.byte 0x0 16.--19. 1. "DCF_CT,Downstream Circular FIFO Current Threshold" bitfld.long 0x0 8. "DCF_PTRCL,Downstream Circular FIFO read/write Pointers Clear action" "0: A DCF read/write pointers clearing has been done..,1: DCF read/write pointers clearing is running." line.long 0x4 "DFIFOCR,Downstream FIFO Control Register" bitfld.long 0x4 31. "DCF_EN,Downstream Circular FIFO Enable" "0: The Downstream Circular FIFO is disabled.,1: The Downstream Circular FIFO is Enabled." bitfld.long 0x4 30. "DCF_DMA,Downstream Circular FIFO DMA Selection" "0: The Downstream Circular FIFO is manageable by..,1: The Downstream Circular FIFO is manageable by.." newline bitfld.long 0x4 27. "EN_DCF_FULL,ENable Downstream Circular FIFO Full" "0: Disable any tx_dcf_full interrupt request.,1: Enable the tx_dcf_full interrupt request coming.." bitfld.long 0x4 26. "EN_DCF_TVR,ENable Downstream Circular FIFO Threshold Value Reached" "0: Disable any tx_dcf_tvr interrupt request.,1: Enable the tx_dcf_tvr interrupt request coming.." newline bitfld.long 0x4 25. "EN_DCF_EMPTY,ENable Downstream Circular FIFO Empty" "0: Disable any tx_dcf_empty interrupt request.,1: Enable the tx_dcf_empty interrupt request coming.." bitfld.long 0x4 16.--18. "DCF_TV,Downstream Circular FIFO Threshold Value" "0: When DFIFOFR[DCF_CT] is equal to 0 then..,1: When DFIFOFR[DCF_CT] is equal to 1 then..,2: When DFIFOFR[DCF_CT] is equal to 2 then..,3: When DFIFOFR[DCF_CT] is equal to 3 then..,4: When DFIFOFR[DCF_CT] is equal to 4 then..,5: When DFIFOFR[DCF_CT] is equal to 5 then..,6: When DFIFOFR[DCF_CT] is equal to 6 then..,7: When DFIFOFR[DCF_CT] is equal to 7 then.." rgroup.long 0x7C++0x3 line.long 0x0 "DSR,Downstream Status Register" bitfld.long 0x0 4. "DGT32OR_REQ,DGT32OR update request status bit" "0: DGT32OR register can be updated by SW.,1: DGT32OR has been written by SW and the TX kernel.." bitfld.long 0x0 3. "DFI64OR_REQ,DFI64OR update request status bit" "0: DFI64OR register can be updated by SW.,1: DFI64OR has been written by SW and the TX kernel.." newline bitfld.long 0x0 2. "DTSCR_REQ,DTSCR update request status bit" "0: DTSCR register can be update by SW.,1: DTSCR has been written by SW and the TX kernel.." bitfld.long 0x0 1. "MSCIOR_REQ,MSCIOR update request status bit" "0: MSCIOR register can be updated by SW.,1: MSCIOR has been written by SW and the TX kernel.." newline bitfld.long 0x0 0. "TX_IDLE,Downstream transmitter status bit" "0: A frame transmission is in progress.,1: The asynchronous TX FIFO inside the Downstream.." group.long 0x80++0x6F line.long 0x0 "DH64FR,Downstream High 64-bit Frame Register" hexmask.long 0x0 0.--31. 1. "DH64F,DH64F is a Read/Write bit field which stores the high part bits from 32 up to 63 of a single receiver frame or the data for the second receiver of a dual receiver data frame." line.long 0x4 "DL64FR,Downstream Low 64-bit Frame Register" hexmask.long 0x4 0.--31. 1. "DL64F,DL64F is a Read/Write register field which stores the low part bits from 0 up to 31 of a single receiver frame or the data for the first receiver and eventually also the second receiver of a dual receiver data frame." line.long 0x8 "DHTSFR,Downstream High Generic Timers Frame Register" hexmask.long 0x8 0.--31. 1. "DHGTF,Downstream High Generic Timers Frame" line.long 0xC "DLTSFR,Downstream Low Generic Timers Frame Register" hexmask.long 0xC 0.--31. 1. "DLGTF,Downstream Low Generic Timers Frame" line.long 0x10 "D32FR,Downstream 32-bit Frame Register" hexmask.long 0x10 0.--31. 1. "D32F,Downstream 32 Frame" line.long 0x14 "D64SUR,Downstream 64-bit Set Up Register" bitfld.long 0x14 31. "DS_64,Data Selection bit in a 64 bits TX" "0: It means the single receiver Data frame has not..,1: It means the single receiver Data frame has a.." bitfld.long 0x14 30. "HDS_64,High Data Selection bit in a 64 bits TX" "0: It means the data transmission for the second..,1: It means the data transmission for the second.." newline hexmask.long.byte 0x14 24.--29. 1. "HDN_64,High Data Number in a 64 bits TX" bitfld.long 0x14 23. "C1D0_64,Command 1 Data 0 bit in a 64 bits Tx" "0: The frame to be transmitted is a Data frame.,1: The frame to be transmitted is a Command frame." newline bitfld.long 0x14 22. "LDS_64,Low Data Selection bit in a 64 bits TX" "0: It means the data transmission for the first..,1: It means the data transmission for the first.." hexmask.long.byte 0x14 16.--21. 1. "LDN_64,Low Data Number in a 64 bits TX" newline bitfld.long 0x14 15. "REQ_64,This bit is set by SW in order to issue a new frame transmission and it is cleared only by HW. The SW can use this bit for polling when to write a new request." "0: No transmission request is pending and a new..,1: A new transmission request has been issued by SW.." hexmask.long.byte 0x14 8.--12. 1. "PPN_64,Passive Phases Number in a 64 bits Tx" newline bitfld.long 0x14 7. "ENN_64,Enable Number bit in a 64 bits Tx" "0: Dual receiver data frame the internal Enables..,1: Single receiver data frame the internal Enable.." hexmask.long.byte 0x14 0.--6. 1. "CDN_64,Command Data 64 bits Number" line.long 0x18 "DGTSUR,Downstream Generic Timers Set Up Register" bitfld.long 0x18 31. "DS_GT,Data Selection bit in a GT TX" "0: It means the single receiver Data frame has not..,1: It means the single receiver Data frame has a.." bitfld.long 0x18 30. "HDS_GT,High Data Selection bit in a GT TX" "0: It means the data transmission for the second..,1: It means the data transmission for the second.." newline hexmask.long.byte 0x18 24.--29. 1. "HDN_GT,High Data Number in a GT TX" bitfld.long 0x18 23. "C1D0_GT,Command 1 Data 0 bit in a GT Tx" "0: The frame to be transmitted is a Data frame.,1: receiver" newline bitfld.long 0x18 22. "LDS_GT,Low Data Selection bit in a GT TX" "0: It means the data transmission for the first..,1: It means the data transmission for the first.." hexmask.long.byte 0x18 16.--21. 1. "LDN_GT,Low Data Number in a GT TX" newline bitfld.long 0x18 15. "REQ_GT,This bit is set by SW or HW in order to issue a new frame transmission and it is cleared only by HW. The SW can use this bit for polling when to write a new request." "0: No transmission request is pending and a new..,1: A new transmission request has been issued by SW.." hexmask.long.byte 0x18 8.--12. 1. "PPN_GT,Passive Phases Number in a GT Tx" newline bitfld.long 0x18 7. "ENN_GT,Enable Number bit in a GT Tx" "0: Dual receiver data frame the internal Enables..,1: Single receiver data frame the internal Enable.." hexmask.long.byte 0x18 0.--6. 1. "CDN_GT,Command Data bits Number in a GT Tx" line.long 0x1C "D32SUR,Downstream 32-bit Set Up Register" bitfld.long 0x1C 31. "DS_32,Data Selection bit in a 32 bits TX" "0: It means the single receiver Data frame has not..,1: It means the single receiver Data frame has a.." bitfld.long 0x1C 30. "HDS_32,High Data Selection bit in a 32 bits TX" "0: It means the data transmission for the second..,1: It means the data transmission for the second.." newline hexmask.long.byte 0x1C 24.--29. 1. "HDN_32,High Data Number in a 32 bits TX" bitfld.long 0x1C 23. "C1D0_32,Command 1 Data 0 bit in a 32 bits Tx" "0: The frame to be transmitted is a Data frame.,1: The frame to be transmitted is a Command frame." newline bitfld.long 0x1C 22. "LDS_32,Low Data Selection bit in a 32 bits TX" "0: It means the data transmission for the first..,1: It means the data transmission for the first.." hexmask.long.byte 0x1C 16.--21. 1. "LDN_32,Low Data Number in a 32 bits TX" newline bitfld.long 0x1C 15. "REQ_32,This bit is set by SW in order to issue a new frame transmission and it is cleared by HW only. The SW can use this bit for polling when to write a new request." "0: No transmission request is pending and a new..,1: A new transmission request has been issued by SW.." hexmask.long.byte 0x1C 8.--12. 1. "PPN_32,Passive Phases Number in a 32 bits Tx" newline bitfld.long 0x1C 7. "ENN_32,Enable Number bit in a 32 bits Tx" "0: Dual receiver data frame the internal Enables..,1: Single receiver data frame the internal Enable.." hexmask.long.byte 0x1C 0.--6. 1. "CDN_32,Command Data bits Number in a 32 bits Tx" line.long 0x20 "DFISUR,Downstream FIFO SetUp Register" bitfld.long 0x20 31. "DS_FI,Data Selection bit in a FI TX" "0: It means the single receiver Data frame has not..,1: It means the single receiver Data frame has a.." bitfld.long 0x20 30. "HDS_FI,High Data Selection bit in a FI TX" "0: It means the data transmission for the second..,1: It means the data transmission for the second.." newline hexmask.long.byte 0x20 24.--29. 1. "HDN_FI,High Data Number in a FI TX" bitfld.long 0x20 23. "C1D0_FI,Command 1 Data 0 bit in a FI Tx" "0: The frame to be transmitted is a Data frame.,1: The frame to be transmitted is a Command frame." newline bitfld.long 0x20 22. "LDS_FI,Low Data Selection bit in a FI TX" "0: It means the data transmission for the first..,1: It means the data transmission for the first.." hexmask.long.byte 0x20 16.--21. 1. "LDN_FI,Low Data Number in a FI TX" newline bitfld.long 0x20 15. "REQ_FI,This bit is set by SW or HW in order to issue a new frame transmission and it is cleared only by HW. The SW can use this bit for polling when to write a new request." "0: No transmission request is pending and a new..,1: A new transmission request has been issued by SW.." hexmask.long.byte 0x20 8.--12. 1. "PPN_FI,Passive Phases Number in a FI Tx" newline bitfld.long 0x20 7. "ENN_FI,Enable Number bit in a FI Tx" "0: Dual receiver data frame the internal Enables..,1: Single receiver data frame the internal Enable.." hexmask.long.byte 0x20 0.--6. 1. "CDN_FI,Command Data bits Number in a FI Tx" line.long 0x24 "DGT32OR,Downstream GT/32 Output Register" bitfld.long 0x24 31. "EN_GT,ENable GT 64-bit frames" "0: The DGTSUR register is not writable by SW.,1: The DGTSUR register is writable by SW." bitfld.long 0x24 24.--26. "ENO_GT,ENable to Output GT source configuration bit" "0: msc_deo[0] IP Output displays en.,1: msc_deo[1] IP Output displays en.,2: msc_deo[2] IP Output displays en.,3: msc_deo[3] IP Output displays en.,4: msc_deo[4] IP Output displays en.,5: msc_deo[5] IP Output displays en.,6: msc_deo[6] IP Output displays en.,7: msc_deo[7] IP Output displays en." newline bitfld.long 0x24 20.--22. "HENO_GT,High ENable to Output GT source configuration bit" "0: msc_deo[0] IP Output displays hen.,1: msc_deo[1] IP Output displays hen.,2: msc_deo[2] IP Output displays hen.,3: msc_deo[3] IP Output displays hen.,4: msc_deo[4] IP Output displays hen.,5: msc_deo[5] IP Output displays hen.,6: msc_deo[6] IP Output displays hen.,7: msc_deo[7] IP Output displays hen." bitfld.long 0x24 16.--18. "LENO_GT,Low ENable to Output GT source configuration bit" "0: msc_deo[0] IP Output displays len.,1: msc_deo[1] IP Output displays len.,2: msc_deo[2] IP Output displays len.,3: msc_deo[3] IP Output displays len.,4: msc_deo[4] IP Output displays len.,5: msc_deo[5] IP Output displays len.,6: msc_deo[6] IP Output displays len.,7: msc_deo[7] IP Output displays len." newline bitfld.long 0x24 15. "EN_32,ENable 32 32-bit frames" "0: The D32SUR register is not writable by SW.,1: The D32SUR register is writable by SW." bitfld.long 0x24 8.--10. "ENO_32,Enable to Output 32 source configuration bit" "0: msc_deo[0] IP Output displays en.,1: msc_deo[1] IP Output displays en.,2: msc_deo[2] IP Output displays en.,3: msc_deo[3] IP Output displays en.,4: msc_deo[4] IP Output displays en.,5: msc_deo[5] IP Output displays en.,6: msc_deo[6] IP Output displays en.,7: msc_deo[7] IP Output displays en." newline bitfld.long 0x24 4.--6. "HENO_32,High Enable to Output 32 source configuration bit" "0: msc_deo[0] IP Output displays hen.,1: msc_deo[1] IP Output displays hen.,2: msc_deo[2] IP Output displays hen.,3: msc_deo[3] IP Output displays hen.,4: msc_deo[4] IP Output displays hen.,5: msc_deo[5] IP Output displays hen.,6: msc_deo[6] IP Output displays hen.,7: msc_deo[7] IP Output displays hen." bitfld.long 0x24 0.--2. "LENO_32,Low Enable to Output 32 source configuration bit" "0: msc_deo[0] IP Output displays len.,1: msc_deo[1] IP Output displays len.,2: msc_deo[2] IP Output displays len.,3: msc_deo[3] IP Output displays len.,4: msc_deo[4] IP Output displays len.,5: msc_deo[5] IP Output displays len.,6: msc_deo[6] IP Output displays len.,7: msc_deo[7] IP Output displays len." line.long 0x28 "DFI64OR,Downstream FI/64 Output Register" bitfld.long 0x28 31. "EN_FI,ENable FI frame source" "0: The DFISUR register is not writable by SW.,1: The DFISUR[31:0] register is writable by SW." bitfld.long 0x28 24.--26. "ENO_FI,ENable to Output FI source configuration bits" "0: msc_deo[0] IP Output displays en.,1: msc_deo[1] IP Output displays en.,2: msc_deo[2] IP Output displays en.,3: msc_deo[3] IP Output displays en.,4: msc_deo[4] IP Output displays en.,5: msc_deo[5] IP Output displays en.,6: msc_deo[6] IP Output displays en.,7: msc_deo[7] IP Output displays en." newline bitfld.long 0x28 20.--22. "HENO_FI,High ENable to Output FI source configuration bits" "0: msc_deo[0] IP Output displays hen.,1: msc_deo[1] IP Output displays hen.,2: msc_deo[2] IP Output displays hen.,3: msc_deo[3] IP Output displays hen.,4: msc_deo[4] IP Output displays hen.,5: msc_deo[5] IP Output displays hen.,6: msc_deo[6] IP Output displays hen.,7: msc_deo[7] IP Output displays hen." bitfld.long 0x28 16.--18. "LENO_FI,Low ENable to Output FI source configuration bits" "0: 0x0: msc_deo[0] IP Output displays len.,1: msc_deo[1] IP Output displays len.,2: msc_deo[2] IP Output displays len.,3: msc_deo[3] IP Output displays len.,4: msc_deo[4] IP Output displays len.,5: msc_deo[5] IP Output displays len.,6: msc_deo[6] IP Output displays len.,7: msc_deo[7] IP Output displays len." newline bitfld.long 0x28 15. "EN_64,ENable 64-bit frames source" "0: The D64SUR register is not writable by SW.,1: The D64SUR register is writable by SW." bitfld.long 0x28 8.--10. "ENO_64,ENable to Output 64-bits source configuration bits" "0: msc_deo[0] IP Output displays en.,1: msc_deo[1] IP Output displays en.,2: msc_deo[2] IP Output displays en.,3: msc_deo[3] IP Output displays en.,4: msc_deo[4] IP Output displays en.,5: msc_deo[5] IP Output displays en.,6: msc_deo[6] IP Output displays en.,7: msc_deo[7] IP Output displays en." newline bitfld.long 0x28 4.--6. "HENO_64,High ENable to Output 64-bits source configuration bits" "0: msc_deo[0] IP Output displays hen.,1: msc_deo[1] IP Output displays hen.,2: msc_deo[2] IP Output displays hen.,3: msc_deo[3] IP Output displays hen.,4: msc_deo[4] IP Output displays hen.,5: msc_deo[5] IP Output displays hen.,6: msc_deo[6] IP Output displays hen.,7: msc_deo[7] IP Output displays hen." bitfld.long 0x28 0.--2. "LENO_64,Low ENable to Output 64-bits source configuration bits" "0: msc_deo[0] IP Output displays len.,1: msc_deo[1] IP Output displays len.,2: msc_deo[2] IP Output displays len.,3: msc_deo[3] IP Output displays len.,4: msc_deo[4] IP Output displays len.,5: msc_deo[5] IP Output displays len.,6: msc_deo[6] IP Output displays len.,7: msc_deo[7] IP Output displays len." line.long 0x2C "DPPMPR,Downstream Passive Phase Modulation Priority Register" bitfld.long 0x2C 28.--29. "PRI_32,PRIority 32-bits source configuration bits" "0: The priority value is 0.,1: The priority value is 1.,2: The priority value is 2.,3: The priority value is 3." bitfld.long 0x2C 24.--25. "PRI_64,PRIority 64-bits source configuration bits" "0: The priority value is 0.,1: The priority value is 1.,2: The priority value is 2.,3: The priority value is 3." newline bitfld.long 0x2C 20.--21. "PRI_GT,PRIority Generic-Timers source configuration bits" "0: The priority value is 0.,1: The priority value is 1.,2: The priority value is 2.,3: The priority value is 3." bitfld.long 0x2C 16.--17. "PRI_FI,Priority FI source configuration bits" "0: The priority value is 0.,1: The priority value is 1.,2: The priority value is 2.,3: The priority value is 3." newline bitfld.long 0x2C 8. "ENH_32B,Enable High on dedicated 32-bit register" "0: Only the low register of a 64-bits source is..,1: Both the high and low register of a 64-bits.." bitfld.long 0x2C 6. "PPM,Passive Phase Modulation" "0: The passive phase modulation is not enabled.,1: The passive phase modulation is enabled." line.long 0x30 "DTSCR,Downstream Timer Siul Counter Register" bitfld.long 0x30 31. "H0S1_SAMPLE,Hardware 0 Software 1 SAMPLE. H0S1_SAMPLE is a Read/Write bit field. The H0S1_SAMPLE control bit selects a SW or HW sampling for the input data of the DTSFR source." "0: Hardware sampling from siul_sample input selected.,1: Software sampling from Down-counter EOC selected." bitfld.long 0x30 30. "DSTART_CNT,START CouNTer. DSTART_CNT is a Read/Write bit field. The DSTART_CNT control field starts the counter if it is set otherwise the down-counter is stopped." "0: The counter is stopped.,1: The counter is started." newline hexmask.long.tbyte 0x30 0.--23. 1. "DCYCLESN,Downstream CYCLES Number" line.long 0x34 "DHTSMR,Downstream High Timers SIUL Mux Register" hexmask.long 0x34 0.--31. 1. "DHTSM,Downstream High SIUL Mux" line.long 0x38 "DLTSMR,Downstream Low Timers SIUL Mux Register" hexmask.long 0x38 0.--31. 1. "DLTSM,Downstream Low Timers SIUL Mux" line.long 0x3C "DFR,Downstream Flag Register" bitfld.long 0x3C 31. "EN_NOPEND_32REQ,This bit enable/disable the corresponding NOPEND_32REQ interrupt." "0: The NOPEND_32REQ interrupt is disabled.,1: The NOPEND_32REQ interrupt is enabled." bitfld.long 0x3C 30. "NOPEND_32REQ,Interrupt bit for the 32 bits frame source." "0: A request is pending.,1: A new request can be issued by the SW." newline bitfld.long 0x3C 29. "EN_NOPEND_64REQ,This bit enable/disable the corresponding NOPEND_64REQ interrupt." "0: The NOPEND_64REQ interrupt is disabled.,1: The NOPEND_64REQ interrupt is enabled." bitfld.long 0x3C 28. "NOPEND_64REQ,Interrupt bit for the 64 bits frame source." "0: A request is pending.,1: A new request can be issued by the SW." newline bitfld.long 0x3C 27. "EN_NOPEND_FIREQ,This bit enable/disable the corresponding NOPEND_64REQ interrupt." "0: The NOPEND_FIREQ interrupt is disabled.,1: The NOPEND_FIREQ interrupt is enabled." bitfld.long 0x3C 26. "NOPEND_FIREQ,Interrupt bit for the Downstream Circular FIFO DCF frame source." "0: A request is pending.,1: A new request can be issued by SW or by HW." newline bitfld.long 0x3C 25. "EN_NOPEND_GTREQ,This bit enable/disable the corresponding NOPEND_GTREQ interrupt." "0: The NOPEND_GTREQ interrupt is disabled.,1: The NOPEND_GTREQ interrupt is enabled." bitfld.long 0x3C 24. "NOPEND_GTREQ,Interrupt bit for the DTSFR frame source." "0: A request is pending.,1: A new request can be issued by SW or by HW." line.long 0x40 "DHPISR0,Downstream Hardware Parallel Input Select Register 0" hexmask.long.byte 0x40 28.--31. 1. "DHPIS7,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x40 24.--27. 1. "DHPIS6,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x40 20.--23. 1. "DHPIS5,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x40 16.--19. 1. "DHPIS4,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x40 12.--15. 1. "DHPIS3,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x40 8.--11. 1. "DHPIS2,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x40 4.--7. 1. "DHPIS1,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x40 0.--3. 1. "DHPIS0,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x44 "DHPISR1,Downstream Hardware Parallel Input Select Register 1" hexmask.long.byte 0x44 28.--31. 1. "DHPIS15,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x44 24.--27. 1. "DHPIS14,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x44 20.--23. 1. "DHPIS13,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x44 16.--19. 1. "DHPIS12,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x44 12.--15. 1. "DHPIS11,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x44 8.--11. 1. "DHPIS10,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x44 4.--7. 1. "DHPIS9,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x44 0.--3. 1. "DHPIS8,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x48 "DHPISR2,Downstream Hardware Parallel Input Select Register 2" hexmask.long.byte 0x48 28.--31. 1. "DHPIS23,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x48 24.--27. 1. "DHPIS22,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x48 20.--23. 1. "DHPIS21,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x48 16.--19. 1. "DHPIS20,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x48 12.--15. 1. "DHPIS19,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x48 8.--11. 1. "DHPIS18,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x48 4.--7. 1. "DHPIS17,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x48 0.--3. 1. "DHPIS16,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x4C "DHPISR3,Downstream Hardware Parallel Input Select Register 3" hexmask.long.byte 0x4C 28.--31. 1. "DHPIS31,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x4C 24.--27. 1. "DHPIS30,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x4C 20.--23. 1. "DHPIS29,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x4C 16.--19. 1. "DHPIS28,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x4C 12.--15. 1. "DHPIS27,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x4C 8.--11. 1. "DHPIS26,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x4C 4.--7. 1. "DHPIS25,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x4C 0.--3. 1. "DHPIS24,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x50 "DHPISR4,Downstream Hardware Parallel Input Select Register 4" hexmask.long.byte 0x50 28.--31. 1. "DHPIS39,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x50 24.--27. 1. "DHPIS38,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x50 20.--23. 1. "DHPIS37,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x50 16.--19. 1. "DHPIS36,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x50 12.--15. 1. "DHPIS35,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x50 8.--11. 1. "DHPIS34,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x50 4.--7. 1. "DHPIS33,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x50 0.--3. 1. "DHPIS32,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x54 "DHPISR5,Downstream Hardware Parallel Input Select Register 5" hexmask.long.byte 0x54 28.--31. 1. "DHPIS47,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x54 24.--27. 1. "DHPIS46,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x54 20.--23. 1. "DHPIS45,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x54 16.--19. 1. "DHPIS44,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x54 12.--15. 1. "DHPIS43,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x54 8.--11. 1. "DHPIS42,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x54 4.--7. 1. "DHPIS41,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x54 0.--3. 1. "DHPIS40,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x58 "DHPISR6,Downstream Hardware Parallel Input Select Register 6" hexmask.long.byte 0x58 28.--31. 1. "DHPIS55,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x58 24.--27. 1. "DHPIS54,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x58 20.--23. 1. "DHPIS53,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x58 16.--19. 1. "DHPIS52,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x58 12.--15. 1. "DHPIS51,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x58 8.--11. 1. "DHPIS50,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x58 4.--7. 1. "DHPIS49,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x58 0.--3. 1. "DHPIS48,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x5C "DHPISR7,Downstream Hardware Parallel Input Select Register 7" hexmask.long.byte 0x5C 28.--31. 1. "DHPIS63,Downstream Hardware Parallel Input Select [(8*n)+7]. DHPIS[(8*n)+7] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+7] of the frame to be transmitted." hexmask.long.byte 0x5C 24.--27. 1. "DHPIS62,Downstream Hardware Parallel Input Select [(8*n)+6]. DHPIS[(8*n)+6] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+6] of the frame to be transmitted." newline hexmask.long.byte 0x5C 20.--23. 1. "DHPIS61,Downstream Hardware Parallel Input Select [(8*n)+5]. DHPIS[(8*n)+5] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+5] of the frame to be transmitted." hexmask.long.byte 0x5C 16.--19. 1. "DHPIS60,Downstream Hardware Parallel Input Select [(8*n)+4]. DHPIS[(8*n)+4] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+4] of the frame to be transmitted." newline hexmask.long.byte 0x5C 12.--15. 1. "DHPIS59,Downstream Hardware Parallel Input Select [(8*n)+3]. DHPIS[(8*n)+3] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+3] of the frame to be transmitted." hexmask.long.byte 0x5C 8.--11. 1. "DHPIS58,Downstream Hardware Parallel Input Select [(8*n)+2]. DHPIS[(8*n)+2] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+2] of the frame to be transmitted." newline hexmask.long.byte 0x5C 4.--7. 1. "DHPIS57,Downstream Hardware Parallel Input Select [(8*n)+1]. DHPIS[(8*n)+1] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [(8*n)+1] of the frame to be transmitted." hexmask.long.byte 0x5C 0.--3. 1. "DHPIS56,Downstream Hardware Parallel Input Select [8*n]. DHPIS[8*n] is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit [8*n] of the frame to be transmitted." line.long 0x60 "DHSBSR,Downstream High SIUL By Software Register" hexmask.long 0x60 0.--31. 1. "DHSBSW,Downstream High SIUL By Software" line.long 0x64 "DLSBSR,Downstream Low SIUL By Software Register" hexmask.long 0x64 0.--31. 1. "DLSBSW,Downstream Low SIUL By Software" line.long 0x68 "DHSBHR,Downstream High SIUL By Hardware Register" hexmask.long 0x68 0.--31. 1. "DHSBHW,Downstream High SIUL By Hardware" line.long 0x6C "DLSBHR,Downstream Low SIUL By Hardware Register" hexmask.long 0x6C 0.--31. 1. "DLSBHW,Downstream Low SIUL By Hardware" tree.end tree.end tree "MSCP (Micro Second Channel Plus)" base ad:0x0 tree "MSCP_0" base ad:0x71A78000 group.long 0x0++0x7 line.long 0x0 "MSCCCR,MSCP Clock Control Register" bitfld.long 0x0 31. "UCK_READY,Read/Clear bit field. When the mscp_uck clock is stable after setting a new clock frequency on Upstream channel this bit is set to 1 by hardware." "0: The UCK_READY pending bit is cleared by a SW..,1: The UCK_READY pending bit is set by HW when new.." bitfld.long 0x0 30. "DCK_READY,Read/Clear bit field. When the mscp_dck clock is stable after setting a new clock frequency on Downstream channel this bit is set to 1 by hardware." "0: The DCK_READY pending bit is cleared by a SW..,1: The DCK_READY pending bit is set by HW when new.." newline hexmask.long.byte 0x0 16.--23. 1. "MSCPUCK_DIV,MSCPlus Upstream ClocK DIVider. MSCPUCK_DIV is a 8-bit Read/Write field. According to the following definition the mscp_ck clock frequency is divisible for: 1 2 4 8 16 32 64 128." hexmask.long.byte 0x0 0.--7. 1. "MSCPCK_DIV,MSCPlus ClocK DIVider. MSCPCK_DIV is a 8-bit Read/Write field. According to the following definition the mscp_clk clock frequency is divisible for: 4 8 16 32 64 128." line.long 0x4 "MSCIOR,MSCs Inputs Outputs Register" bitfld.long 0x4 31. "U1LINE_MCODE,Enable Manchester input line for upstream module. If both U1line_mcode and U2line_ckdt are selected the U1line_mcode only will be chosen." "0: Manchester input is disabled,1: Manchester input is enabled" bitfld.long 0x4 30. "U2LINE_CKDT,Enable separate data and clock input lines for upstream module. If both U1line_mcode and U2line_ckdt are selected the U1line_mcode only will be chosen." "0: Data and clock input lines are disabled,1: Data and clock input lines are enabled" newline bitfld.long 0x4 15. "D1LINE_MCODE,Enable Manchester output line for downstream module." "0: Manchester output is disabled,1: Manchester output is enabled" bitfld.long 0x4 14. "D2LINE_CKDT,Enable separate data and clock output lines for downstream module." "0: Data and clock output lines are disabled,1: Data and clock output lines are enabled" newline bitfld.long 0x4 0. "DSO_OBE,Data Serial Output Buffer Enable. The DSO_OBE field enables the output buffer on the PAD." "0: PAD output buffer is not enabled.,1: PAD output buffer is enabled." group.long 0xC++0x7 line.long 0x0 "UFIFOR,Upstream FIFO Register" hexmask.long 0x0 0.--31. 1. "UFIFO,Upstream FIFO frame. UFIFO is a Software Read bit field. The 32-bit UFIFO is individually accessible in Write by hardware from the Upstream data UART and the same UFIFO is accessible in Read both by both software and by DMA. Once the UFIFO register.." line.long 0x4 "USWDR,Upstream SoftWare Data Register" hexmask.long 0x4 0.--31. 1. "USD,Upstream Software Data is a Read/Write bit field. The 32-bit USD[31:0] is individually accessible in Write by hardware from the Upstream software UART and both in Read and Write by software. The hardware Write has greater priority than the software.." group.long 0x20++0x3 line.long 0x0 "USWSUR,Upstream SoftWare SetUp Register" bitfld.long 0x0 31. "USS_REQ,Upstream Software Setup REQuest. Setting the USS_REQ bit the reception parameters USWSUR[US_Y] USWSUR[US_I] USWSUR[US_SB] USWSUR[US_PAR] and UHWSUR[UH_K] UHWSUR[UH_PP] will be loaded to the Upstream Data Receiver. This register is readable.." "0: The USS_REQ is cleared by HW a clk cycle after..,1: The USS_REQ setting is kept for one clk cycle.." bitfld.long 0x0 30. "USS_ACK,Upstream Software Setup ACKnowledge. USS_ACK is a Read bit field. Setting the USS_REQ bit once the setup values have been loaded into the Upstream Data Receiver USS_ACK bit is set. The setting of this bit ensures that the reception parameters.." "0: USS_ACK bit is cleared by setting the USS_RAR..,1: The Upstream Data Receiver has received the new.." newline bitfld.long 0x0 29. "USS_RAR,Upstream Software Setup Request Acknowledge Reset. USS_RAR is a Read/Write bit field. Setting the USS_RAR bit Both USS_REQ and USS_ACK bits will be cleared. When USS_RAR field has been set by SW it remains high during one ipg_clk clock cycle.." "0: Both USS_REQ and USS_ACK bits can be accessed.,1: Both USS_REQ and USS_ACK bits are forced low." bitfld.long 0x0 24. "USWDR_EN,Upstream Software Data Register Enable. USWDR_EN is a Read/Write bit field. This register bit enables the reception of the Software data on the USWDR register while it disables the reception on UFIFOR. Clearing both the USWDR_EN bit and the.." "0: USWDR cannot be accessed.,1: USWDR can be accessed." newline hexmask.long.byte 0x0 16.--20. 1. "US_Y,Upstream Software Y number. US_Y is a Read/Write bits field. Writing the US_Y bits the 'Y' reception parameter (that is the total number of UART data bits expected to be received in the complete Software Data frame) is defined. The meaning of the.." hexmask.long.byte 0x0 8.--13. 1. "US_I,Upstream Software I number. US_I is a Read/Write bits field. Writing the US_I bits the 'I' reception parameter which is the number of serialized UART bits expected in the received Software data fragment is defined. The meaning of the selected code.." newline bitfld.long 0x0 4.--5. "US_SB,Upstream Software Stop Bits number. US_SB is a Read/Write bit field. The US_SB bit defines the number of UART stop bits expected in the received UART frame. The default value US_SB=0 means 2 Stop Bits. According to the US_SB value the stop bit.." "0: 2 Stop Bits,1: 1 Stop Bit,2: 2 Stop Bits,3: 3 Stop Bits" bitfld.long 0x0 0. "US_PAR,Upstream Software PARity kind. US_PAR is a Read/Write bit field. The US_PAR bit defines the UART parity kind expected in the received UART frame which means if the expected parity of received software data is odd or even." "0: Even parity.,1: Odd parity." group.long 0x28++0xB line.long 0x0 "USWIR,Upstream SoftWare Interrupt Register" bitfld.long 0x0 28. "EN_US_OWRE,ENable OverWRite ERror. EN_US_OWRE is a Read/Write bit field. The EN_US_OWRE bit enables or disables the overwrite error interrupt both for UCF and for USWDR." "0: The mscp_usw_owre interrupt request is disabled.,1: The mscp_usw_owre interrupt request is enabled." bitfld.long 0x0 27. "EN_US_STOPBE,ENable STOP Bit ERror. EN_US_STOPBE is a Read/Write bit field. The EN_US_STOPBE bit enables or disables the overwrite error interrupt both for UCF and for USWDR." "0: The mscp_usw_stopbe interrupt request is disabled.,1: The mscp_usw_stopbe interrupt request is enabled." newline bitfld.long 0x0 26. "EN_US_PARE,ENable Upstream Software PARity ERror. EN_US_PARE is a Read/Write bit field. The EN_US_PARE bit enables or disables the parity error interrupt both for UCF and for USWDR." "0: The mscp_usw_pare interrupt request is disabled.,1: The mscp_usw_pare interrupt request is enabled." bitfld.long 0x0 24. "EN_US_NEWF,ENable Upstream Software NEW Frame. EN_US_NEWF is a Read/Write bit field. The EN_US_NEWF bit enables or disables the new frame interrupt both for UCF and for USWDR." "0: The mscp_usw_newf interrupt request is disabled.,1: The mscp_usw_newf interrupt request is enabled." newline bitfld.long 0x0 20. "US_OWRE,Upstream Software OverWRite ERror. US_OWRE is a Read/Clear bit field. The US_OWRE pending bit rises when on a US_NEWF bit already set a new set (reception) occurs." "0: The US_OWRE pending bit is cleared setting by SW..,1: The US_OWRE pending bit is set by HW when on a.." bitfld.long 0x0 19. "US_STOPBE,Upstream Software STOP Bit ERror. US_STOPBE is a Read/Clear bit field. The US_STOPBE pending bit rises when one or both stop bits of the received UART frame is/are logical '0' instead of '1' that is when the number of received stop bits is.." "0: The US_STOPBE pending bit is cleared setting by..,1: The US_STOPBE pending bit is set by HW when one.." newline bitfld.long 0x0 18. "US_PARE,Upstream Software PARity ERror. US_PARE is a Read/Clear bit field. The US_PARE pending bit rises when a parity error occurs on the received UART frame according to the USWSUR[US_PAR] setting." "0: The US_PARE pending bit is cleared setting by SW..,1: The US_PARE pending bit is set by HW only and it.." bitfld.long 0x0 16. "US_NEWF,Upstream Software NEW Frame. US_NEWF is a Read/Clear bit field. The US_NEWF pending bit rises when the whole UART frame received by the Upstream Software UART is transferred into UCF/USWDR." "0: The US_NEWF pending bit is cleared by a SW..,1: The US_NEWF pending bit is set by HW only when a.." line.long 0x4 "UFIFOFR,Upstream FIFO Flag Register" bitfld.long 0x4 30.--31. "URX_RGFI,Upstream Receiver ReGister FIfo. URX_RGFI is a 2-bit Read only field." "0: both UCF and USWDR are disabled.,1: UCF disabled USWDR enabled.,2: UCF enabled not in DMA USWDR disabled.,3: UCF enabled in DMA USWDR disabled." bitfld.long 0x4 29. "UCF_DMARUN,Upstream Circular Fifo DMA RUNning. UCF_DMARUN is a Read only bit field. While a data transfer on DMA UCF interface is running the UCF_DMARUN register bit asserts." "0: Data transfer on DMA UCF interface not running.,1: Data transfer on DMA UCF interface running." newline bitfld.long 0x4 28. "UCF_DMAREQ,Upstream Circular Fifo DMA REQuest. UCF_DMAREQ is a Read only bit field. If the DMA is enabled (UFIFOCR[UCF_DMA]='1') the UFIFOFR[UCF_DMAREQ] flag bit asserts when the IP is requiring a DMA request." "0: DMA request is '0'.,1: DMA request is '1'." bitfld.long 0x4 27. "UCF_FULL,Upstream Circular Fifo FULL. UCF_FULL is a Read/Set to Clear bit field. When the received" "0: The UCF_FULL pending bit is cleared setting by..,1: The UCF_FULL pending bit is set by HW when the.." newline bitfld.long 0x4 26. "UCF_TVR,Upstream Circular Fifo Threshold Value Reached. UCF_TVR is a Read/Set to Clear bit field." "0: The UCF_TVR pending bit is cleared by SW or by..,1: The UCF_TVR pending bit has set because once.." bitfld.long 0x4 25. "UCF_EMPTY,Upstream Circular Fifo EMPTY. UCF_EMPTY is a Read/Set to Clear bit field. When the last Upstream Circular FIFO location has been read the UFIFOFR[UCF_EMPTY] flag bit rises and if the UFIFOFR[EN_UCF_EMPTY] bit is 'high' a rx_ucf_empty interrupt.." "0: The UCF_EMPTY pending bit is cleared by setting..,1: The UCF_EMPTY pending bit is set by HW when the.." newline hexmask.long.byte 0x4 16.--19. 1. "UCF_CT,Upstream Circular Fifo Current Threshold. The UCF_CT is a Read only bit field. It states how many written FIFO elements have to be read." bitfld.long 0x4 8. "UCF_PTRCL,Upstream Circular Fifo read/write PoinTeRs CLear action. UCF_PTRCL is a Read/Write bit field. In order to perform a clear action of the ucf read/write pointers it is required to clear the UFIFOFR[UCF_PTRCL] bit." "0: a UCF read/write pointers clearing has been done..,1: UCF read/write pointers clearing is running." line.long 0x8 "UFIFOCR,Upstream FIFO Control Register" bitfld.long 0x8 31. "UCF_EN,Upstream Circular Fifo ENabled. UCF_EN is a Read/Write bit field. The UFIFOCR[UCF_EN] bit enables the Upstream Circular FIFO to be used instead of USWDR register." "0: the Upstream Circular FIFO is disabled.,1: the Upstream Circular FIFO is enabled." bitfld.long 0x8 30. "UCF_DMA,Upstream Circular Fifo DMA. UFIFOCR[UCF_DMA] is a Read/Write bit field. If the" "0: the enabled Upstream Circular FIFO is accessible..,1: the enabled Upstream Circular FIFO is accessible.." newline bitfld.long 0x8 27. "EN_UCF_FULL,ENable Upstream Circular Fifo FULL. EN_UCF_FULL is a Read/Write bit field. When the received frame has been copied in the last Upstream Circular FIFO free location the UFIFOFR[UCF_FULL] flag bit rises and if the UFIFOFR[EN_UCF_FULL] bit is.." "0: Disable any rx_ucf_full interrupt request.,1: Enable the rx_ucf_full interrupt request coming.." bitfld.long 0x8 26. "EN_UCF_TVR,ENable Upstream Circular Fifo Threshold Value Reached. EN_UCF_TVR is a Read/Write bit field. When UFIFOFR[UCF_CT(2:0)] becomes greater than UFIFOCR[UCF_TV(2:0)] the UFIFOFR[UCF_TVR] flag bit rises and if the UFIFOFR[UCF_TVR] bit is 'high' the.." "0: Disable any rx_ucf_tvr interrupt request.,1: Enable the rx_ucf_tvr interrupt request coming.." newline bitfld.long 0x8 25. "EN_UCF_EMPTY,ENable Upstream Circular Fifo EMPTY. EN_UCF_EMPTY is a Read/Write bit field. When the last Upstream Circular FIFO location has been copied by CPU bus the UFIFOFR[UCF_EMPTY] flag bit rises and if the UFIFOFR[EN_UCF_EMPTY] bit is 'high' the.." "0: Disable any rx_ucf_empty interrupt request.,1: Enable the rx_ucf_empty interrupt request coming.." bitfld.long 0x8 16.--18. "UCF_TV,Upstream Circular Fifo Threshold Value. The 3-bit UCF_TV is a Read/Write bit field. The difference between written ucf registers and read ucf registers affects the UFIFOFR[UCF_TVR] bit as follows:" "0: When UFIFOFR[UCF_CT] is equal to 0 then..,1: When UFIFOFR[UCF_CT] is equal to 1 then..,2: When UFIFOFR[UCF_CT] is equal to 2 then..,3: When UFIFOFR[UCF_CT] is equal to 3 then..,4: When UFIFOFR[UCF_CT] is equal to 4 then..,5: When UFIFOFR[UCF_CT] is equal to 5 then..,6: When UFIFOFR[UCF_CT] is equal to 6 then..,7: When UFIFOFR[UCF_CT] is equal to 7 then.." group.long 0x40++0x13 line.long 0x0 "UHWHDR,Upstream HardWare High Data Register" hexmask.long 0x0 0.--31. 1. "UHHD,Upstream Hardware High Data. UHHD is a Read/Write bit field. The 32-bit UHHD [31:0] contain the Upstream high part of the received Upstream Hardware Data UHD[61:32]. UHHD is accessible in Write by hardware from the Hardware Channel and both in Read.." line.long 0x4 "UHWLDR,Upstream HardWare Low Data Register" hexmask.long 0x4 0.--31. 1. "UHLD,Upstream Hardware Low Data. UHLD is a Read/Write bit field. The 32-bit UHLD [31:0] contain the Upstream low part of the received Upstream Hardware Data UHD[31:0]. UHLD is accessible in Write by hardware from the Hardware Channel and both in Read and.." line.long 0x8 "UHWSUR,Upstream HardWare SetUp Register" hexmask.long.byte 0x8 16.--22. 1. "UH_K,Upstream Hardware K number. UH_K is a Read/Write bits field. Writing the UH_K bits the Upstream hardware K number is defined. The meaning of the selected code is defined in the following:" hexmask.long.byte 0x8 8.--12. 1. "UH_PP,Upstream Hardware Passive Phase Number. UH_PP is a Read/Write bits field. Writing the UH_PP bits the number of Upstream hardware passive phases is defined. The meaning of the selected code is defined in the following:" newline bitfld.long 0x8 1. "UH_OUTE,Upstream Hardware Output data Enable. UH_OUTE is a specific Read/Write bit field." "0: The UH_OUTE bit at '0' means the Upstream..,1: The UH_OUTE bit at '1' means the Upstream.." bitfld.long 0x8 0. "UH_OFF,Upstream Hardware OFF. UH_OFF is a Read/Write bit field. The UH_OFF bit when set enables to turn off the Upstream Data Receiver." "0: The UH_OFF bit at '0' means the Upstream Data..,1: The UH_OFF bit at '1' means the Upstream Data.." line.long 0xC "UHWIR,Upstream HardWare Interrupt Register" bitfld.long 0xC 31. "EN_IRQ0,ENable upstream hardware Interrupt ReQuest 0. EN_IRQ0 is a Read/Write bit field. The EN_IRQ0 bit enables or disables the IRQ_0." "0: The mscp_uhw_irq0 interrupt request is disabled.,1: The mscp_uhw_irq0 interrupt request is enabled." bitfld.long 0xC 30. "EN_IRQ1,ENable upstream hardware Interrupt ReQuest 1. EN_IRQ1 is a Read/Write bit field. The EN_IRQ1 bit enables or disables the IRQ_1." "0: The mscp_uhw_irq1 interrupt request is disabled.,1: The mscp_uhw_irq1 interrupt request is enabled." newline bitfld.long 0xC 28. "EN_UH_SSVE,ENable Upstream Hardware Start Selection bit Value Error. EN_UH_SSVE is a Read/Write bit field. The EN_UH_SSVE bit enables or disables the start selection bit value error interrupt." "0: The mscp_uhw_ssve interrupt request is disabled.,1: The mscp_uhw_ssve interrupt request is enabled." bitfld.long 0xC 27. "EN_UH_PPNE,ENable Upstream Hardware Passive Phase bits Number Error. EN_UH_PPNE is a Read/Write bit field. The EN_UH_PPNE bit enables or disables the passive phase bits number error interrupt." "0: The mscp_uhw_ppne interrupt request is disabled.,1: The mscp_uhw_ppne interrupt request is enabled." newline bitfld.long 0xC 26. "EN_UH_PVBNE,ENable Upstream Hardware channel Protocol Violation Bit Number Error. EN_UH_PVBNE is a Read/Write bit field." "0: The mscp_uhw_pvbne interrupt request is disabled.,1: The mscp_uhw_pvbne interrupt request is enabled." bitfld.long 0xC 25. "EN_UH_OWR,ENable Upstream Hardware OverWRite data previously received. EN_UH_OWR is a Read/Write bit field. The EN_UH_OWR bit enables or disables the overwrite hardware data interrupt." "0: The mscp_uhw_owr interrupt request is disabled.,1: The mscp_uhw_owr interrupt request is enabled." newline bitfld.long 0xC 24. "EN_UH_NEWD,ENable Upstream Hardware NEW Data reception. EN_UH_NEWD is a Read/Write bit field. The EN_UH_NEWD bit enables or disables the new hardware data reception interrupt." "0: The mscp_uhw_newd interrupt request is disabled.,1: The mscp_uhw_newd interrupt request is enabled." bitfld.long 0xC 23. "IRQ0,Interrupt ReQuest 0. IRQ0 is a Read only bit field. The IRQ0 gives the interrupt pending bit received from the last reception. The IRQ0 is hardware set by the mscp_uho[N] where (N=0 1 ... 7) and it is defined in the UHOWR[UH_I0MAP] register field" "0: no mscp_uhw_irq0 Interrupt request pending bit..,1: mscp_uhw_irq0 Interrupt request pending bit has.." newline bitfld.long 0xC 22. "IRQ1,Interrupt ReQuest 1. IRQ1 is a Read only bit field. The IRQ1 gives the interrupt pending bit received from the last reception. The IRQ1 is hardware set by the mscp_uho[N] where (N=0 1 ... 7) and it is defined in the UHOWR[UH_I1MAP] register field" "0: no mscp_uhw_irq1 Interrupt request pending bit..,1: mscp_uhw_irq1 Interrupt request pending bit has.." bitfld.long 0xC 20. "UH_SSVE,Upstream Hardware Start Selection bit Value Error. UH_SSVE is a Read/Clear bit field. The UH_SSVE flag bit rises when the Upstream Hardware Receiver has received a start selection bit (which is the first bit in the received Data frame) different.." "0: The UH_SSVE pending bit is cleared by a SW..,1: The UH_SSVE pending bit is set by HW only when.." newline bitfld.long 0xC 19. "UH_PPNE,Upstream Hardware Passive Phase bits Number Error. UH_PPNE is a Read/Clear bit field. The UH_PPNE flag bit rises when the Upstream Hardware Receiver has received a passive phase bits number UH_CURR_PPN different than the expected number.." "0: The UH_PPNE pending bit is cleared by a SW..,1: The UH_PPNE pending bit is set by HW only when.." bitfld.long 0xC 18. "UH_PVBNE,Upstream Hardware channel Protocol Violation Bit Number Error. UH_PVBNE is a Read/Clear bit field. The UH_PVBNE pending bit rises when a protocol violation occurs. A protocol violation arises when the number of bits of received frame is.." "0: The UH_PVBNE pending bit is cleared by a SW..,1: The UH_PVBNE pending bit is set by HW only." newline bitfld.long 0xC 17. "UH_OWR,Upstream Hardware OverWrite Data previously received. UH_OWR is a Read/Clear bit field. UH_OWR pending bit rises when on a UH_NEWD bit already set a new set occurs." "0: The UH_OWR pending bit is cleared setting by SW..,1: The UH_OWR pending bit is set by HW when on a.." bitfld.long 0xC 16. "UH_NEWD,Upstream Hardware NEW Data. UH_NEWD is a Read/Clear bit field. The UH_NEWD pending bit rises when the whole Data frame received by Upstream Channel is transferred into UHWDR[63:0] (= UHWHDR[63:32] UHWLDR[31:0])." "0: The UH_NEWD pending bit is cleared by a SW..,1: The UH_NEWD pending bit is set by HW only when a.." line.long 0x10 "UHWMSR,Upstream Hardware Muxes Setup Register" bitfld.long 0x10 25.--27. "UH_I1MAP,Upstream Hardware data Interrupt 1 MAP. UH_I1MAP is a specific Read/Write 3 bits field. When a value N is written into UH_I1MAP (where N=1 ... 7) and the UH_I1ME bit is '1' it means the External Modulator data is on the bit N of the mscp_uho.." "0: mscp_uho[0] will be written into irq1 pending bit,1: mscp_uho[1] will be written into irq1 pending bit,2: mscp_uho[2] will be written into irq1 pending bit,3: mscp_uho[3] will be written into irq1 pending bit,4: mscp_uho[4] will be written into irq1 pending bit,5: mscp_uho[5] will be written into irq1 pending bit,6: mscp_uho[6] will be written into irq1 pending bit,7: mscp_uho[7] will be written into irq1 pending bit." bitfld.long 0x10 24. "UH_I1ME,Upstream Hardware Interrupt request 1 Mapping Enable. UH_I1ME is a specific Read/Write bit field. Setting both the UHWSUR[UH_OFF] and the UH_I1ME register bits the Upstream Hardware permits to map the Upstream Hardware data interrupt 1 detection.." "0: The UH_I1ME bit at '0' means the Upstream..,1: The UH_I1ME bit at '1' means the Upstream.." newline bitfld.long 0x10 17.--19. "UH_I0MAP,Upstream Hardware data Interrupt 0 MAP. UH_I0MAP is a specific Read/Write 3 bits field. When a value N is written into UH_I0MAP (where N=1 ... 7) and the UH_I0ME bit is '1' it means the External Modulator data is on the bit N of the mscp_uho.." "0: mscp_uho[0] will be written into irq1 pending bit,1: mscp_uho[1] will be written into irq1 pending bit,2: mscp_uho[2] will be written into irq1 pending bit,3: mscp_uho[3] will be written into irq1 pending bit,4: mscp_uho[4] will be written into irq1 pending bit,5: mscp_uho[5] will be written into irq1 pending bit,6: mscp_uho[6] will be written into irq1 pending bit,7: mscp_uho[7] will be written into irq1 pending bit." bitfld.long 0x10 16. "UH_I0ME,Upstream Hardware Interrupt request 0 Mapping Enable. UH_I0ME is a specific Read/Write bit field. Setting both the UHWSUR[UH_OFF] and the UH_I0ME register bits the Upstream Hardware permits to map the Upstream Hardware data interrupt 0 detection.." "0: The UH_I0ME bit at '0' means the Upstream..,1: The UH_I0ME bit at '1' means the Upstream.." newline bitfld.long 0x10 1.--3. "UH_EMMAP,Upstream Hardware data External Modulator Mode MAP. UH_EMMAP is a specific Read/Write 3 bits field. When a value N is written into UH_EMMAP (where N=0 1 ... 7) and the UH_EMME bit is '1' it means the External Modulator data is on the bit N of.." "0: mscp_uho[0] will be written into mscp_em[0] output,1: mscp_uho[1] will be written into mscp_em[0] output,2: mscp_uho[2] will be written into mscp_em[0] output,3: mscp_uho[3] will be written into mscp_em[0] output,4: mscp_uho[4] will be written into mscp_em[0] output,5: mscp_uho[5] will be written into mscp_em[0] output,6: mscp_uho[6] will be written into mscp_em[0] output,7: mscp_uho[7] will be written into mscp_em[0] output" bitfld.long 0x10 0. "UH_EMME,Upstream Hardware data External Modulator Mode Enable. UH_EMME is a specific Read/Write bit field. Setting the UH_EMME register bits the Upstream Hardware data enters the External Modulator Mode following this actions sequence:" "0: The UH_EMME bit at '0' means the Upstream..,1: The UH_EMME bit at '1' means the Upstream.." group.long 0x70++0x27 line.long 0x0 "DFIFOR,Downstream FIFO Register" hexmask.long 0x0 0.--31. 1. "DFIFO,Downstream FIFO frame. DFIFO is a Software write only bit field. The 32-bit DFIFO is individually accessible in Read by hardware from the Downstream data UART and the same DFIFO is accessible in Write both by both software and by DMA. Once the.." line.long 0x4 "DSWDR,Downstream SoftWare Data Register" hexmask.long 0x4 0.--31. 1. "DSD,Downstream Software Data is a Read/Write bit field. The 32-bit DSD[31:0] is individually accessible in Read by hardware from the Downstream software UART and both in Read and Write by software. The hardware Read has greater priority than the software.." line.long 0x8 "DSWSUR,Downstream SoftWare SetUp Register" bitfld.long 0x8 31. "DSS_REQ,Downstream Software Setup REQuest. Setting the DSS_REQ bit both the transmission parameters DSWSUR[DS_X] DSWSUR[DS_N] DSWSUR[DS_SB] DSWSUR[DS_PAR] DHWSUR[DH_M] DHWSUR[DH_PP] and the DSWDR register content (if DSWSUR[DSWDR_EN] bit is 1) will.." "0: The DSS_REQ is cleared by HW a clk cycle after..,1: The DSS_REQ setting is kept for one clk cycle.." bitfld.long 0x8 30. "DSS_ACK,Downstream Software Setup ACKnowledge. DSS_ACK is a Read bit field. Setting the DSS_REQ bit once the transmission parameters and the updated content of DSWDR register (if DSWSUR[DSWDR_EN] = 1) have been loaded into the Downstream Data.." "0: DSS_ACK bit is cleared by setting the DSS_RAR bit.,1: The Downstream Data Transmitter has received the.." newline bitfld.long 0x8 29. "DSS_RAR,Downstream Software Setup Request Acknowledge Reset. DSS_RAR is a Read/Write bit field. Setting the DSS_RAR bit Both DSS_REQ and DSS_ACK bits will be cleared. When DSS_RAR field has been set by SW it remains high during one ipg_clk clock cycle.." "0: Both DSS_REQ and DSS_ACK bits can be accessed.,1: Both DSS_REQ and DSS_ACK bits are forced low." bitfld.long 0x8 24. "DSWDR_EN,Downstream Software Data Register Enable. DSWDR_EN is a Read/Write bit field. This register bit enables the transmission of the Software data from the DSWDR register while disables the transmission from DFIFOR. Clearing both the DSWDR_EN bit and.." "0: DSWDR cannot be accessed.,1: DSWDR can be accessed." newline hexmask.long.byte 0x8 16.--20. 1. "DS_X,Downstream Software X number. DS_X is a Read/Write bits field. Writing the DS_X bits the Downstream software X number is defined. The meaning of the selected code is defined in the following:" hexmask.long.byte 0x8 8.--13. 1. "DS_N,Downstream Software N number. DS_N is a Read/Write bits field. Writing the DS_N bits the Downstream software N number (number of serialized UART bits) is defined. The meaning of the selected code is defined in the following:" newline bitfld.long 0x8 4.--5. "DS_SB,Downstream Software Stop Bits number. DS_SB is a Read/Write bit field. The DS_SB bit defines the Downstream Software UART stop bits number which means how many bits are expected as stop bits. The default value DS_SB=0 means 2 Stop Bits. According.." "0: 2 Stop Bits,1: 1 Stop Bit,2: 2 Stop Bits,3: 3 Stop Bits" bitfld.long 0x8 0. "DS_PAR,Downstream Software PARity kind. DS_PAR is a Read/Write bit field. The DS_PAR bit defines the Downstream Software UART parity kind which means if the expected parity of received software data is odd or even." "0: Even parity,1: Odd parity" line.long 0xC "DSWIR,Downstream SoftWare Interrupt Register" bitfld.long 0xC 31. "EN_DSW_START,ENable Downstream SoftWare START. EN_DSW_START is a Read/Write bit field. The EN_DSW_START bit enables or disables the transmission start interrupt both for DCF and for DSWDR." "0: The mscp_dsw_start interrupt request is disabled.,1: The mscp_dsw_start interrupt request is enabled." bitfld.long 0xC 30. "DSW_START,Downstream Software START. DSW_START is a Read/set to clear bit field. It asserts when transmission of a UART frame (SW Data) starts." "0: The DSW_START pending bit is cleared by a SW..,1: The DSW_START pending bit is set by HW only when.." newline bitfld.long 0xC 15. "EN_DSW_END,ENable Downstream SoftWare END. EN_DSW_END is a Read/Write bit field. The EN_DSW_END bit enables or disables the transmission end interrupt both for DCF and for DSWDR." "0: The mscp_dsw_end interrupt request is disabled.,1: The mscp_dsw_end interrupt request is enabled." bitfld.long 0xC 14. "DSW_END,Downstream Software END. DSW_END is a Read/set to clear bit field. It asserts when the transmission of the current UART frame (SW Data) has completed." "0: The DSW_END pending bit is cleared by a SW..,1: The DSW_END pending bit is set by HW only when.." line.long 0x10 "DFIFOFR,Downstream FIFO Flag Register" bitfld.long 0x10 30.--31. "DTX_RGFI,Downstream Receiver ReGister FIfo. DTX_RGFI is a 2-bit Read only field." "0: both DCF and DSWDR are disabled.,1: DCF disabled DSWDR enabled.,2: DCF enabled not in DMA DSWDR disabled.,3: DCF enabled in DMA DSWDR disabled." bitfld.long 0x10 29. "DCF_DMARUN,Downstream Circular Fifo DMA RUNning. DCF_DMARUN is a Read only bit field. While a data transfer on DMA UCF the DMA DCF interface is running the DCF_DMARUN register bit asserts." "0: Data transfer on DMA UCF interface not running.,1: Data transfer on DMA UCF interface running." newline bitfld.long 0x10 28. "DCF_DMAREQ,Downstream Circular Fifo DMA REQuest. DCF_DMAREQ is a Read only bit field. If the DMA is enabled (DFIFOCR[DCF_DMA]='1') the DFIFOFR[DCF_DMAREQ] flag bit asserts when the IP is requiring a DMA request." "0: DMA request is '0'.,1: DMA request is '1'." bitfld.long 0x10 27. "DCF_FULL,Downstream Circular Fifo FULL. DCF_FULL is a Read/Set to Clear bit field. When the received frame has been copied in the last available Downstream FIFO location the DFIFOFR[DCF_FULL] flag bit rises and if DFIFOCR[EN_DCF_FULL] = '1' the.." "0: The DCF_FULL pending bit is cleared setting by..,1: The DCF_FULL pending bit is set by HW when the.." newline bitfld.long 0x10 26. "DCF_TVR,Downstream Circular Fifo Threshold Value Reached. DCF_TVR is a Read/Set to Clear bit field. This pending bit asserts when the number of elements in the DCF is less or equal than the threshold value. This means that if DFIFOFR[DCF_CT(2:0)].." "0: The DCF_TVR pending bit is cleared because the..,1: The DCF_TVR pending bit has set because once.." bitfld.long 0x10 25. "DCF_EMPTY,Downstream Circular Fifo EMPTY. DCF_EMPTY is a Read/Set to Clear bit field. When the last Downstream Circular FIFO location has been read the DFIFOFR[DCF_EMPTY] flag bit rises and if the DFIFOFR[EN_DCF_EMPTY] bit is 'high' a tx_dcf_empty.." "0: The DCF_EMPTY pending bit is cleared by setting..,1: The DCF_EMPTY pending bit is set by HW when the.." newline hexmask.long.byte 0x10 16.--19. 1. "DCF_CT,Downstream Circular Fifo Current Threshold. The DCF_CT is a Read only bit field. It states how many DFIFO elements written are still not read in the Downstream Circular FIFO." bitfld.long 0x10 8. "DCF_PTRCL,Downstream Circular Fifo read/write PoinTeRs CLear action. DCF_PTRCL is a Read/Write bit field. In order to perform a clear action of the dcf read/write pointers it is required to clear the DFIFOFR[DCF_PTRCL] bit." "0: A DCF read/write pointers clearing has been..,1: DCF read/write pointers clearing is running." line.long 0x14 "DFIFOCR,Downstream FIFO Control Register" bitfld.long 0x14 31. "DCF_EN,Downstream Circular Fifo ENabled. DCF_EN is a Read/Write bit field. The DFIFOCR[DCF_EN] bit enables the Downstream Circular FIFO to be used instead of DSWDR register." "0: the Downstream Circular FIFO is disabled.,1: the Downstream Circular FIFO is enabled." bitfld.long 0x14 30. "DCF_DMA,Downstream Circular Fifo DMA. DFIFOCR[DCF_DMA] is a Read/Write bit field. If the DFIFOCR[DCF_EN] is 'high' when DFIFOCR[DCF_DMA] is set the Downstream Circular FIFO is managed by DMA." "0: the enabled Downstream Circular FIFO is..,1: the enabled Downstream Circular FIFO is.." newline bitfld.long 0x14 27. "EN_DCF_FULL,ENable Downstream Circular Fifo FULL. EN_DCF_FULL is a Read/Write bit field. When the received frame has been copied in the last Downstream Circular FIFO free location the DFIFOFR[DCF_FULL] flag bit rises and if the DFIFOFR[EN_DCF_FULL] bit.." "0: Disable any tx_dcf_full interrupt request.,1: Enable the tx_dcf_full interrupt request coming.." bitfld.long 0x14 26. "EN_DCF_TVR,ENable Downstream Circular Fifo Threshold Value Reached. EN_DCF_TVR is a Read/Write bit field. When DFIFOFR[DCF_CT(2:0)] becomes less or equal than DFIFOCR[DCF_TV(2:0)] the DFIFOFR[DCF_TVR] flag bit rises and if the DFIFOFR[DCF_TVR] bit is.." "0: Disable any tx_dcf_tvr interrupt request.,1: Enable the tx_dcf_tvr interrupt request coming.." newline bitfld.long 0x14 25. "EN_DCF_EMPTY,ENable Downstream Circular Fifo EMPTY. EN_DCF_EMPTY is a Read/Write bit field. When the last Upstream Circular FIFO location has been read the DFIFOFR[DCF_EMPTY] flag bit rises and if the DFIFOFR[EN_DCF_EMPTY] bit is 'high' the tx_dcf_empty.." "0: Disable any tx_dcf_empty interrupt request.,1: Enable the tx_dcf_empty interrupt request coming.." bitfld.long 0x14 16.--18. "DCF_TV,Downstream Circular Fifo Threshold Value. The DCF_TV is a Read/Write bit field. The difference between written dcf registers and read dcf registers affects the DFIFOFR[DCF_TVR] bit as follows:" "0: When DFIFOFR[DCF_CT] is equal to 0 then..,1: When DFIFOFR[DCF_CT] is equal to 1 then..,2: When DFIFOFR[DCF_CT] is equal to 2 then..,3: When DFIFOFR[DCF_CT] is equal to 3 then..,4: When DFIFOFR[DCF_CT] is equal to 4 then..,5: When DFIFOFR[DCF_CT] is equal to 5 then..,6: When DFIFOFR[DCF_CT] is equal to 6 then..,7: When DFIFOFR[DCF_CT] is equal to 7 then.." line.long 0x18 "DHWHDR,Downstream HardWare High Data Register" hexmask.long 0x18 0.--31. 1. "DHHD,Downstream Hardware High Data. DHHD is a Read/Write bit field. The 32-bit DHHD [31:0] contain the Downstream high part of the Downstream Hardware Data DHD[61:32] to be transmitted. DHHD is accessible in Read by hardware from the Hardware Channel and.." line.long 0x1C "DHWLDR,Downstream HardWare Low Data Register" hexmask.long 0x1C 0.--31. 1. "DHLD,Downstream Hardware Low Data. DHLD is a Read/Write bit field. The 32-bit DHLD [31:0] contain the Downstream low part of the Downstream Hardware Data DHD[31:0] to be transmitted. DHLD is accessible in Read by hardware from the Hardware Channel and.." line.long 0x20 "DHWSUR,Downstream HardWare SetUp Register" bitfld.long 0x20 31. "DHS_REQ,Downstream Hardware Setup REQuest. Setting the DHS_REQ bit the SIUL_HWSW is sampled and loaded both into DHWDR register and into Downstream Data Transmitter to be transmitted (refer to Figure2481) Downstream Tx architecture). This bit can be.." "0: The DHS_REQ is cleared by HW a clk cycle after..,1: The DHS_REQ setting is kept for one clk cycle.." bitfld.long 0x20 30. "DHS_ACK,Downstream Hardware Setup ACKnowledge. DHS_ACK is a Read bit field. Setting the DHS_REQ bit once the SAMPLED_HWSW(63:0) (refer to Figure2481) Downstream Tx architecture) has been loaded into the Downstream Data Transmitter to be transmitted .." "0: DHS_ACK bit is cleared by setting the DHS_RAR..,1: The Downstream Data Transmitter has received the.." newline bitfld.long 0x20 29. "DHS_RAR,Downstream Hardware Setup Request Acknowledge Reset. DHS_RAR is a Read/Write bit field. Setting the DHS_RAR bit Both DHS_REQ and DHS_ACK bits will be cleared. When DHS_RAR field has been set by SW it remains high during one ipg_clk clock cycle.." "0: Both DHS_REQ and DHS_ACK bits can be accessed.,1: Both DHS_REQ and DHS_ACK bits are forced low." hexmask.long.byte 0x20 16.--22. 1. "DH_M,Downstream Hardware M number. DH_M is a Read/Write bits field. Writing the DH_M bits the Upstream hardware M number is defined. The meaning of the selected code is defined in the following:" newline hexmask.long.byte 0x20 8.--12. 1. "DH_PP,Downstream Hardware Passive Phase Number. DH_PP is a Read/Write bits field. Writing the DH_PP bits the number of Downstream hardware passive phases is defined. The meaning of the selected code is defined in the following:" bitfld.long 0x20 1. "TX_ON,Transmission on. TX_ON is a Read/Write bit field. The TX_ON bit when set activates the transmission of data frames. Transmission runs as long as TX_ON bit is set." "0: Data frames transmission off,1: Data frames transmission running" newline bitfld.long 0x20 0. "DH_OFF,Downstream Hardware OFF. DH_OFF is a Read/Write bit field. The DH_OFF disables the downstream hardware transmitter immediately and remains 1." "0: Transmitter is enabled.,1: Transmitter is disabled." line.long 0x24 "DHWIR,Downstream HardWare Interrupt Register" bitfld.long 0x24 31. "EN_DH_START,ENable Downstream Hardware data frame transmission START. EN_DH_START is a Read/Write bit field. The EN_TX_START bit enables or disables the data frame transmission start interrupt both for DCF and for DSWDR." "0: The mscp_dhw_start interrupt request is disabled.,1: The mscp_dhw_start interrupt request is enabled." bitfld.long 0x24 28. "EN_DH_END,ENable Downstream Hardware data frame transmission END. EN_DH_END is a Read/Write bit field. The EN_DH_END bit enables or disables the data frame transmission end interrupt both for DCF and for DSWDR." "0: The mscp_dhw_end interrupt request is disabled.,1: The mscp_dhw_end interrupt request is enabled." newline bitfld.long 0x24 23. "DH_START,Downstream Hardware new data frame Transmission START. DH_START is a Read/Clear bit field. The DH_START flag bit rises when a new Data frame transmission starts." "0: The DH_START pending bit is cleared by a SW..,1: The DH_START pending bit is set by HW when a new.." bitfld.long 0x24 20. "DH_END,Downstream Hardware data frame transmission END. DH_END is a Read/Clear bit field. The DH_END flag bit rises when the Data frame transmission ends." "0: The DH_END pending bit is cleared by a SW setting.,1: The DH_END pending bit is set by HW when the.." group.long 0xB0++0xB line.long 0x0 "DHWTSCR,Downstream HardWare Timer Siul Counter Register" bitfld.long 0x0 31. "H0S1_SAMPLE,Hardware 0 Software 1 SAMPLE. H0S1_SAMPLE is a Read/Write bit field. The H0S1_SAMPLE control bit selects a SW or HW sampling." "0: Hardware sampling from siul_dhi_sample input..,1: Software sampling from Down-counter EOC selected." bitfld.long 0x0 30. "DSTART_CNT,START CouNTer. DSTART_CNT is a Read/Write bit field. The DSTART_CNT control field if 'high' starts the counter and keeps the free-running 'low' the down count is cleared and stopped." "0: The counter is kept on stop.,1: The counter is kept in free-running." newline hexmask.long.tbyte 0x0 0.--23. 1. "DCYCLESN,Downstream DCYCLES Number. DCYCLESN is a Read/Write bit field. The 24 DCYCLESN bits state the number of IPS clock cycles to wait for the End Of Count EOC. The counter is a free running down count and at the start the value to decrement.." line.long 0x4 "DHWSHMR,Downstream HardWare data Siul High Mux Register" hexmask.long 0x4 0.--31. 1. "DHWSHM,Downstream Hardware High SIUL Mux. DHTSHM is a Read/Write bit field. The 32 DHTSHM bits if cleared select as SIUL_HWSW[63:32] bits the bits coming from the SIUL source otherwise if set the DHWISR[63:32]. The mux selection refers to each bit.." line.long 0x8 "DHWSLMR,Downstream HardWare data Siul Low Mux Register" hexmask.long 0x8 0.--31. 1. "DHWSLM,Downstream Hardware Low SIUL Mux. DHTSLM is a Read/Write bit field. The 32 DHTSLM bits if cleared select as SIUL_HWSW[31:0] bits the bits coming from the SIUL source otherwise if set the DHWISR[31:0]. The mux selection refers to each bit.." group.long 0xC0++0x2F line.long 0x0 "DHPISR0,Downstream HardWare Parallel Input Select Register 0" hexmask.long.byte 0x0 28.--31. 1. "DHPIS7,Downstream Hardware Parallel Input Select 7. DHPIS7 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 7 of the frame to be transmitted." hexmask.long.byte 0x0 24.--27. 1. "DHPIS6,Downstream Hardware Parallel Input Select 6. DHPIS6 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 6of the frame to be transmitted." newline hexmask.long.byte 0x0 20.--23. 1. "DHPIS5,Downstream Hardware Parallel Input Select 5. DHPIS5 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 5 of the frame to be transmitted." hexmask.long.byte 0x0 16.--19. 1. "DHPIS4,Downstream Hardware Parallel Input Select 4. DHPIS4 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 4 of the frame to be transmitted." newline hexmask.long.byte 0x0 12.--15. 1. "DHPIS3,Downstream Hardware Parallel Input Select 3. DHPIS3 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 3 of the frame to be transmitted." hexmask.long.byte 0x0 8.--11. 1. "DHPIS2,Downstream Hardware Parallel Input Select 2. DHPIS2 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 2 of the frame to be transmitted." newline hexmask.long.byte 0x0 4.--7. 1. "DHPIS1,Downstream Hardware Parallel Input Select 1. DHPIS1 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 1 of the frame to be transmitted." hexmask.long.byte 0x0 0.--3. 1. "DHPIS0,Downstream Hardware Parallel Input Select 0. DHPIS0 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 0 of the frame to be transmitted." line.long 0x4 "DHPISR1,Downstream HardWare Parallel Input Select Register 1" hexmask.long.byte 0x4 28.--31. 1. "DHPIS15,Downstream Hardware Parallel Input Select 15. DHPIS15 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 15 of the frame to be transmitted." hexmask.long.byte 0x4 24.--27. 1. "DHPIS14,Downstream Hardware Parallel Input Select 14. DHPIS14 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 14 of the frame to be transmitted." newline hexmask.long.byte 0x4 20.--23. 1. "DHPIS13,Downstream Hardware Parallel Input Select 13. DHPIS13 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 13 of the frame to be transmitted." hexmask.long.byte 0x4 16.--19. 1. "DHPIS12,Downstream Hardware Parallel Input Select 12. DHPIS12 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 12 of the frame to be transmitted." newline hexmask.long.byte 0x4 12.--15. 1. "DHPIS11,Downstream Hardware Parallel Input Select 11. DHPIS11 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 11 of the frame to be transmitted." hexmask.long.byte 0x4 8.--11. 1. "DHPIS10,Downstream Hardware Parallel Input Select 10. DHPIS10 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 10 of the frame to be transmitted." newline hexmask.long.byte 0x4 4.--7. 1. "DHPIS9,Downstream Hardware Parallel Input Select 9. DHPIS9 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 9 of the frame to be transmitted." hexmask.long.byte 0x4 0.--3. 1. "DHPIS8,Downstream Hardware Parallel Input Select 8. DHPIS8 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 8 of the frame to be transmitted." line.long 0x8 "DHPISR2,Downstream HardWare Parallel Input Select Register 2" hexmask.long.byte 0x8 28.--31. 1. "DHPIS23,Downstream Hardware Parallel Input Select 23. DHPIS23 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 23 of the frame to be transmitted." hexmask.long.byte 0x8 24.--27. 1. "DHPIS22,Downstream Hardware Parallel Input Select 22. DHPIS22 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 22 of the frame to be transmitted." newline hexmask.long.byte 0x8 20.--23. 1. "DHPIS21,Downstream Hardware Parallel Input Select 21. DHPIS21 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 21 of the frame to be transmitted." hexmask.long.byte 0x8 16.--19. 1. "DHPIS20,Downstream Hardware Parallel Input Select 20. DHPIS20 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 20 of the frame to be transmitted." newline hexmask.long.byte 0x8 12.--15. 1. "DHPIS19,Downstream Hardware Parallel Input Select 19. DHPIS19 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 19 of the frame to be transmitted." hexmask.long.byte 0x8 8.--11. 1. "DHPIS18,Downstream Hardware Parallel Input Select 18. DHPIS18 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 18 of the frame to be transmitted." newline hexmask.long.byte 0x8 4.--7. 1. "DHPIS17,Downstream Hardware Parallel Input Select 17. DHPIS17 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 17 of the frame to be transmitted." hexmask.long.byte 0x8 0.--3. 1. "DHPIS16,Downstream Hardware Parallel Input Select 16. DHPIS16 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 16 of the frame to be transmitted." line.long 0xC "DHPISR3,Downstream HardWare Parallel Input Select Register 3" hexmask.long.byte 0xC 28.--31. 1. "DHPIS31,Downstream Hardware Parallel Input Select 31. DHPIS31 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 31 of the frame to be transmitted." hexmask.long.byte 0xC 24.--27. 1. "DHPIS30,Downstream Hardware Parallel Input Select 30. DHPIS30 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 30 of the frame to be transmitted." newline hexmask.long.byte 0xC 20.--23. 1. "DHPIS29,Downstream Hardware Parallel Input Select 29. DHPIS29 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 29 of the frame to be transmitted." hexmask.long.byte 0xC 16.--19. 1. "DHPIS28,Downstream Hardware Parallel Input Select 28. DHPIS28 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 28 of the frame to be transmitted." newline hexmask.long.byte 0xC 12.--15. 1. "DHPIS27,Downstream Hardware Parallel Input Select 27. DHPIS27 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 27 of the frame to be transmitted." hexmask.long.byte 0xC 8.--11. 1. "DHPIS26,Downstream Hardware Parallel Input Select 26. DHPIS26 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 26 of the frame to be transmitted." newline hexmask.long.byte 0xC 4.--7. 1. "DHPIS25,Downstream Hardware Parallel Input Select 25. DHPIS25 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 25 of the frame to be transmitted." hexmask.long.byte 0xC 0.--3. 1. "DHPIS24,Downstream Hardware Parallel Input Select 24. DHPIS24 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 24 of the frame to be transmitted." line.long 0x10 "DHPISR4,Downstream HardWare Parallel Input Select Register 4" hexmask.long.byte 0x10 28.--31. 1. "DHPIS39,Downstream Hardware Parallel Input Select 39. DHPIS39 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 39 of the frame to be transmitted." hexmask.long.byte 0x10 24.--27. 1. "DHPIS38,Downstream Hardware Parallel Input Select 38. DHPIS38 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 38 of the frame to be transmitted." newline hexmask.long.byte 0x10 20.--23. 1. "DHPIS37,Downstream Hardware Parallel Input Select 37. DHPIS37 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 37 of the frame to be transmitted." hexmask.long.byte 0x10 16.--19. 1. "DHPIS36,Downstream Hardware Parallel Input Select 36. DHPIS36 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 36 of the frame to be transmitted." newline hexmask.long.byte 0x10 12.--15. 1. "DHPIS35,Downstream Hardware Parallel Input Select 35. DHPIS35 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 35 of the frame to be transmitted." hexmask.long.byte 0x10 8.--11. 1. "DHPIS34,Downstream Hardware Parallel Input Select 34. DHPIS34 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 34 of the frame to be transmitted." newline hexmask.long.byte 0x10 4.--7. 1. "DHPIS33,Downstream Hardware Parallel Input Select 33. DHPIS33 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 33 of the frame to be transmitted." hexmask.long.byte 0x10 0.--3. 1. "DHPIS32,Downstream Hardware Parallel Input Select 32. DHPIS32 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 32 of the frame to be transmitted." line.long 0x14 "DHPISR5,Downstream HardWare Parallel Input Select Register 5" hexmask.long.byte 0x14 28.--31. 1. "DHPIS47,Downstream Hardware Parallel Input Select 47. DHPIS47 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 47 of the frame to be transmitted." hexmask.long.byte 0x14 24.--27. 1. "DHPIS46,Downstream Hardware Parallel Input Select 46. DHPIS46 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 46 of the frame to be transmitted." newline hexmask.long.byte 0x14 20.--23. 1. "DHPIS45,Downstream Hardware Parallel Input Select 45. DHPIS45 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 45 of the frame to be transmitted." hexmask.long.byte 0x14 16.--19. 1. "DHPIS44,Downstream Hardware Parallel Input Select 44. DHPIS44 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 44 of the frame to be transmitted." newline hexmask.long.byte 0x14 12.--15. 1. "DHPIS43,Downstream Hardware Parallel Input Select 43. DHPIS43 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 43 of the frame to be transmitted." hexmask.long.byte 0x14 8.--11. 1. "DHPIS42,Downstream Hardware Parallel Input Select 42. DHPIS42 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 42 of the frame to be transmitted." newline hexmask.long.byte 0x14 4.--7. 1. "DHPIS41,Downstream Hardware Parallel Input Select 41. DHPIS41 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 41 of the frame to be transmitted." hexmask.long.byte 0x14 0.--3. 1. "DHPIS40,Downstream Hardware Parallel Input Select 40. DHPIS40 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 40 of the frame to be transmitted." line.long 0x18 "DHPISR6,Downstream HardWare Parallel Input Select Register 6" hexmask.long.byte 0x18 28.--31. 1. "DHPIS55,Downstream Hardware Parallel Input Select 55. DHPIS55 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 55 of the frame to be transmitted." hexmask.long.byte 0x18 24.--27. 1. "DHPIS54,Downstream Hardware Parallel Input Select 54. DHPIS54 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 54 of the frame to be transmitted." newline hexmask.long.byte 0x18 20.--23. 1. "DHPIS53,Downstream Hardware Parallel Input Select 53. DHPIS53 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 53 of the frame to be transmitted." hexmask.long.byte 0x18 16.--19. 1. "DHPIS52,Downstream Hardware Parallel Input Select 52. DHPIS52 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 52 of the frame to be transmitted." newline hexmask.long.byte 0x18 12.--15. 1. "DHPIS51,Downstream Hardware Parallel Input Select 51. DHPIS51 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 51 of the frame to be transmitted." hexmask.long.byte 0x18 8.--11. 1. "DHPIS50,Downstream Hardware Parallel Input Select 50. DHPIS50 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 50 of the frame to be transmitted." newline hexmask.long.byte 0x18 4.--7. 1. "DHPIS49,Downstream Hardware Parallel Input Select 49. DHPIS49 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 49 of the frame to be transmitted." hexmask.long.byte 0x18 0.--3. 1. "DHPIS48,Downstream Hardware Parallel Input Select 48. DHPIS48 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 48 of the frame to be transmitted." line.long 0x1C "DHPISR7,Downstream HardWare Parallel Input Select Register 7" hexmask.long.byte 0x1C 28.--31. 1. "DHPIS63,Downstream Hardware Parallel Input Select 63. DHPIS63 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 63 of the frame to be transmitted." hexmask.long.byte 0x1C 24.--27. 1. "DHPIS62,Downstream Hardware Parallel Input Select 62. DHPIS62 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 62 of the frame to be transmitted." newline hexmask.long.byte 0x1C 20.--23. 1. "DHPIS61,Downstream Hardware Parallel Input Select 61. DHPIS61 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 61 of the frame to be transmitted." hexmask.long.byte 0x1C 16.--19. 1. "DHPIS60,Downstream Hardware Parallel Input Select 60. DHPIS60 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 60 of the frame to be transmitted." newline hexmask.long.byte 0x1C 12.--15. 1. "DHPIS59,Downstream Hardware Parallel Input Select 59. DHPIS59 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 59 of the frame to be transmitted." hexmask.long.byte 0x1C 8.--11. 1. "DHPIS58,Downstream Hardware Parallel Input Select 58. DHPIS58 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 58 of the frame to be transmitted." newline hexmask.long.byte 0x1C 4.--7. 1. "DHPIS57,Downstream Hardware Parallel Input Select 57. DHPIS57 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 57 of the frame to be transmitted." hexmask.long.byte 0x1C 0.--3. 1. "DHPIS56,Downstream Hardware Parallel Input Select 56. DHPIS56 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 56 of the frame to be transmitted." line.long 0x20 "DHWIHSR,Downstream HardWare data Internal High Siul Register" hexmask.long 0x20 0.--31. 1. "DHWIHS,Downstream Hardware data Internal High SIUL Register. DHWIHS is a Read/Write bit field. The DHWIHS field keeps the highest 32 bits of the DHWISR register." line.long 0x24 "DHWILSR,Downstream HardWare data Internal Low Siul Register" hexmask.long 0x24 0.--31. 1. "DHWILS,Downstream Hardware data Internal Low SIUL Register. DHWILS is a Read/Write bit field. The DHWILS field keeps the lowest 32 bits of the DHWISR." line.long 0x28 "DHWEHSR,Downstream HardWare data External High Siul Register" hexmask.long 0x28 0.--31. 1. "DHWEHS,Downstream Hardware data External High SIUL Register. DHWEHS is a Read/Write bit field. The DHWEHS field keeps the highest 32 bits of the DHWESR." line.long 0x2C "DHWELSR,Downstream HardWare data External Low Siul Register" hexmask.long 0x2C 0.--31. 1. "DHWELS,Downstream Hardware data External Low SIUL Register. DHWELS is a Read/Write bit field. The DHWELS field keeps the lowest 32 bits of the DHWESR." tree.end tree "MSCP_1" base ad:0x71570000 group.long 0x0++0x7 line.long 0x0 "MSCCCR,MSCP Clock Control Register" bitfld.long 0x0 31. "UCK_READY,Read/Clear bit field. When the mscp_uck clock is stable after setting a new clock frequency on Upstream channel this bit is set to 1 by hardware." "0: The UCK_READY pending bit is cleared by a SW..,1: The UCK_READY pending bit is set by HW when new.." bitfld.long 0x0 30. "DCK_READY,Read/Clear bit field. When the mscp_dck clock is stable after setting a new clock frequency on Downstream channel this bit is set to 1 by hardware." "0: The DCK_READY pending bit is cleared by a SW..,1: The DCK_READY pending bit is set by HW when new.." newline hexmask.long.byte 0x0 16.--23. 1. "MSCPUCK_DIV,MSCPlus Upstream ClocK DIVider. MSCPUCK_DIV is a 8-bit Read/Write field. According to the following definition the mscp_ck clock frequency is divisible for: 1 2 4 8 16 32 64 128." hexmask.long.byte 0x0 0.--7. 1. "MSCPCK_DIV,MSCPlus ClocK DIVider. MSCPCK_DIV is a 8-bit Read/Write field. According to the following definition the mscp_clk clock frequency is divisible for: 4 8 16 32 64 128." line.long 0x4 "MSCIOR,MSCs Inputs Outputs Register" bitfld.long 0x4 31. "U1LINE_MCODE,Enable Manchester input line for upstream module. If both U1line_mcode and U2line_ckdt are selected the U1line_mcode only will be chosen." "0: Manchester input is disabled,1: Manchester input is enabled" bitfld.long 0x4 30. "U2LINE_CKDT,Enable separate data and clock input lines for upstream module. If both U1line_mcode and U2line_ckdt are selected the U1line_mcode only will be chosen." "0: Data and clock input lines are disabled,1: Data and clock input lines are enabled" newline bitfld.long 0x4 15. "D1LINE_MCODE,Enable Manchester output line for downstream module." "0: Manchester output is disabled,1: Manchester output is enabled" bitfld.long 0x4 14. "D2LINE_CKDT,Enable separate data and clock output lines for downstream module." "0: Data and clock output lines are disabled,1: Data and clock output lines are enabled" newline bitfld.long 0x4 0. "DSO_OBE,Data Serial Output Buffer Enable. The DSO_OBE field enables the output buffer on the PAD." "0: PAD output buffer is not enabled.,1: PAD output buffer is enabled." group.long 0xC++0x7 line.long 0x0 "UFIFOR,Upstream FIFO Register" hexmask.long 0x0 0.--31. 1. "UFIFO,Upstream FIFO frame. UFIFO is a Software Read bit field. The 32-bit UFIFO is individually accessible in Write by hardware from the Upstream data UART and the same UFIFO is accessible in Read both by both software and by DMA. Once the UFIFO register.." line.long 0x4 "USWDR,Upstream SoftWare Data Register" hexmask.long 0x4 0.--31. 1. "USD,Upstream Software Data is a Read/Write bit field. The 32-bit USD[31:0] is individually accessible in Write by hardware from the Upstream software UART and both in Read and Write by software. The hardware Write has greater priority than the software.." group.long 0x20++0x3 line.long 0x0 "USWSUR,Upstream SoftWare SetUp Register" bitfld.long 0x0 31. "USS_REQ,Upstream Software Setup REQuest. Setting the USS_REQ bit the reception parameters USWSUR[US_Y] USWSUR[US_I] USWSUR[US_SB] USWSUR[US_PAR] and UHWSUR[UH_K] UHWSUR[UH_PP] will be loaded to the Upstream Data Receiver. This register is readable.." "0: The USS_REQ is cleared by HW a clk cycle after..,1: The USS_REQ setting is kept for one clk cycle.." bitfld.long 0x0 30. "USS_ACK,Upstream Software Setup ACKnowledge. USS_ACK is a Read bit field. Setting the USS_REQ bit once the setup values have been loaded into the Upstream Data Receiver USS_ACK bit is set. The setting of this bit ensures that the reception parameters.." "0: USS_ACK bit is cleared by setting the USS_RAR..,1: The Upstream Data Receiver has received the new.." newline bitfld.long 0x0 29. "USS_RAR,Upstream Software Setup Request Acknowledge Reset. USS_RAR is a Read/Write bit field. Setting the USS_RAR bit Both USS_REQ and USS_ACK bits will be cleared. When USS_RAR field has been set by SW it remains high during one ipg_clk clock cycle.." "0: Both USS_REQ and USS_ACK bits can be accessed.,1: Both USS_REQ and USS_ACK bits are forced low." bitfld.long 0x0 24. "USWDR_EN,Upstream Software Data Register Enable. USWDR_EN is a Read/Write bit field. This register bit enables the reception of the Software data on the USWDR register while it disables the reception on UFIFOR. Clearing both the USWDR_EN bit and the.." "0: USWDR cannot be accessed.,1: USWDR can be accessed." newline hexmask.long.byte 0x0 16.--20. 1. "US_Y,Upstream Software Y number. US_Y is a Read/Write bits field. Writing the US_Y bits the 'Y' reception parameter (that is the total number of UART data bits expected to be received in the complete Software Data frame) is defined. The meaning of the.." hexmask.long.byte 0x0 8.--13. 1. "US_I,Upstream Software I number. US_I is a Read/Write bits field. Writing the US_I bits the 'I' reception parameter which is the number of serialized UART bits expected in the received Software data fragment is defined. The meaning of the selected code.." newline bitfld.long 0x0 4.--5. "US_SB,Upstream Software Stop Bits number. US_SB is a Read/Write bit field. The US_SB bit defines the number of UART stop bits expected in the received UART frame. The default value US_SB=0 means 2 Stop Bits. According to the US_SB value the stop bit.." "0: 2 Stop Bits,1: 1 Stop Bit,2: 2 Stop Bits,3: 3 Stop Bits" bitfld.long 0x0 0. "US_PAR,Upstream Software PARity kind. US_PAR is a Read/Write bit field. The US_PAR bit defines the UART parity kind expected in the received UART frame which means if the expected parity of received software data is odd or even." "0: Even parity.,1: Odd parity." group.long 0x28++0xB line.long 0x0 "USWIR,Upstream SoftWare Interrupt Register" bitfld.long 0x0 28. "EN_US_OWRE,ENable OverWRite ERror. EN_US_OWRE is a Read/Write bit field. The EN_US_OWRE bit enables or disables the overwrite error interrupt both for UCF and for USWDR." "0: The mscp_usw_owre interrupt request is disabled.,1: The mscp_usw_owre interrupt request is enabled." bitfld.long 0x0 27. "EN_US_STOPBE,ENable STOP Bit ERror. EN_US_STOPBE is a Read/Write bit field. The EN_US_STOPBE bit enables or disables the overwrite error interrupt both for UCF and for USWDR." "0: The mscp_usw_stopbe interrupt request is disabled.,1: The mscp_usw_stopbe interrupt request is enabled." newline bitfld.long 0x0 26. "EN_US_PARE,ENable Upstream Software PARity ERror. EN_US_PARE is a Read/Write bit field. The EN_US_PARE bit enables or disables the parity error interrupt both for UCF and for USWDR." "0: The mscp_usw_pare interrupt request is disabled.,1: The mscp_usw_pare interrupt request is enabled." bitfld.long 0x0 24. "EN_US_NEWF,ENable Upstream Software NEW Frame. EN_US_NEWF is a Read/Write bit field. The EN_US_NEWF bit enables or disables the new frame interrupt both for UCF and for USWDR." "0: The mscp_usw_newf interrupt request is disabled.,1: The mscp_usw_newf interrupt request is enabled." newline bitfld.long 0x0 20. "US_OWRE,Upstream Software OverWRite ERror. US_OWRE is a Read/Clear bit field. The US_OWRE pending bit rises when on a US_NEWF bit already set a new set (reception) occurs." "0: The US_OWRE pending bit is cleared setting by SW..,1: The US_OWRE pending bit is set by HW when on a.." bitfld.long 0x0 19. "US_STOPBE,Upstream Software STOP Bit ERror. US_STOPBE is a Read/Clear bit field. The US_STOPBE pending bit rises when one or both stop bits of the received UART frame is/are logical '0' instead of '1' that is when the number of received stop bits is.." "0: The US_STOPBE pending bit is cleared setting by..,1: The US_STOPBE pending bit is set by HW when one.." newline bitfld.long 0x0 18. "US_PARE,Upstream Software PARity ERror. US_PARE is a Read/Clear bit field. The US_PARE pending bit rises when a parity error occurs on the received UART frame according to the USWSUR[US_PAR] setting." "0: The US_PARE pending bit is cleared setting by SW..,1: The US_PARE pending bit is set by HW only and it.." bitfld.long 0x0 16. "US_NEWF,Upstream Software NEW Frame. US_NEWF is a Read/Clear bit field. The US_NEWF pending bit rises when the whole UART frame received by the Upstream Software UART is transferred into UCF/USWDR." "0: The US_NEWF pending bit is cleared by a SW..,1: The US_NEWF pending bit is set by HW only when a.." line.long 0x4 "UFIFOFR,Upstream FIFO Flag Register" bitfld.long 0x4 30.--31. "URX_RGFI,Upstream Receiver ReGister FIfo. URX_RGFI is a 2-bit Read only field." "0: both UCF and USWDR are disabled.,1: UCF disabled USWDR enabled.,2: UCF enabled not in DMA USWDR disabled.,3: UCF enabled in DMA USWDR disabled." bitfld.long 0x4 29. "UCF_DMARUN,Upstream Circular Fifo DMA RUNning. UCF_DMARUN is a Read only bit field. While a data transfer on DMA UCF interface is running the UCF_DMARUN register bit asserts." "0: Data transfer on DMA UCF interface not running.,1: Data transfer on DMA UCF interface running." newline bitfld.long 0x4 28. "UCF_DMAREQ,Upstream Circular Fifo DMA REQuest. UCF_DMAREQ is a Read only bit field. If the DMA is enabled (UFIFOCR[UCF_DMA]='1') the UFIFOFR[UCF_DMAREQ] flag bit asserts when the IP is requiring a DMA request." "0: DMA request is '0'.,1: DMA request is '1'." bitfld.long 0x4 27. "UCF_FULL,Upstream Circular Fifo FULL. UCF_FULL is a Read/Set to Clear bit field. When the received" "0: The UCF_FULL pending bit is cleared setting by..,1: The UCF_FULL pending bit is set by HW when the.." newline bitfld.long 0x4 26. "UCF_TVR,Upstream Circular Fifo Threshold Value Reached. UCF_TVR is a Read/Set to Clear bit field." "0: The UCF_TVR pending bit is cleared by SW or by..,1: The UCF_TVR pending bit has set because once.." bitfld.long 0x4 25. "UCF_EMPTY,Upstream Circular Fifo EMPTY. UCF_EMPTY is a Read/Set to Clear bit field. When the last Upstream Circular FIFO location has been read the UFIFOFR[UCF_EMPTY] flag bit rises and if the UFIFOFR[EN_UCF_EMPTY] bit is 'high' a rx_ucf_empty interrupt.." "0: The UCF_EMPTY pending bit is cleared by setting..,1: The UCF_EMPTY pending bit is set by HW when the.." newline hexmask.long.byte 0x4 16.--19. 1. "UCF_CT,Upstream Circular Fifo Current Threshold. The UCF_CT is a Read only bit field. It states how many written FIFO elements have to be read." bitfld.long 0x4 8. "UCF_PTRCL,Upstream Circular Fifo read/write PoinTeRs CLear action. UCF_PTRCL is a Read/Write bit field. In order to perform a clear action of the ucf read/write pointers it is required to clear the UFIFOFR[UCF_PTRCL] bit." "0: a UCF read/write pointers clearing has been done..,1: UCF read/write pointers clearing is running." line.long 0x8 "UFIFOCR,Upstream FIFO Control Register" bitfld.long 0x8 31. "UCF_EN,Upstream Circular Fifo ENabled. UCF_EN is a Read/Write bit field. The UFIFOCR[UCF_EN] bit enables the Upstream Circular FIFO to be used instead of USWDR register." "0: the Upstream Circular FIFO is disabled.,1: the Upstream Circular FIFO is enabled." bitfld.long 0x8 30. "UCF_DMA,Upstream Circular Fifo DMA. UFIFOCR[UCF_DMA] is a Read/Write bit field. If the" "0: the enabled Upstream Circular FIFO is accessible..,1: the enabled Upstream Circular FIFO is accessible.." newline bitfld.long 0x8 27. "EN_UCF_FULL,ENable Upstream Circular Fifo FULL. EN_UCF_FULL is a Read/Write bit field. When the received frame has been copied in the last Upstream Circular FIFO free location the UFIFOFR[UCF_FULL] flag bit rises and if the UFIFOFR[EN_UCF_FULL] bit is.." "0: Disable any rx_ucf_full interrupt request.,1: Enable the rx_ucf_full interrupt request coming.." bitfld.long 0x8 26. "EN_UCF_TVR,ENable Upstream Circular Fifo Threshold Value Reached. EN_UCF_TVR is a Read/Write bit field. When UFIFOFR[UCF_CT(2:0)] becomes greater than UFIFOCR[UCF_TV(2:0)] the UFIFOFR[UCF_TVR] flag bit rises and if the UFIFOFR[UCF_TVR] bit is 'high' the.." "0: Disable any rx_ucf_tvr interrupt request.,1: Enable the rx_ucf_tvr interrupt request coming.." newline bitfld.long 0x8 25. "EN_UCF_EMPTY,ENable Upstream Circular Fifo EMPTY. EN_UCF_EMPTY is a Read/Write bit field. When the last Upstream Circular FIFO location has been copied by CPU bus the UFIFOFR[UCF_EMPTY] flag bit rises and if the UFIFOFR[EN_UCF_EMPTY] bit is 'high' the.." "0: Disable any rx_ucf_empty interrupt request.,1: Enable the rx_ucf_empty interrupt request coming.." bitfld.long 0x8 16.--18. "UCF_TV,Upstream Circular Fifo Threshold Value. The 3-bit UCF_TV is a Read/Write bit field. The difference between written ucf registers and read ucf registers affects the UFIFOFR[UCF_TVR] bit as follows:" "0: When UFIFOFR[UCF_CT] is equal to 0 then..,1: When UFIFOFR[UCF_CT] is equal to 1 then..,2: When UFIFOFR[UCF_CT] is equal to 2 then..,3: When UFIFOFR[UCF_CT] is equal to 3 then..,4: When UFIFOFR[UCF_CT] is equal to 4 then..,5: When UFIFOFR[UCF_CT] is equal to 5 then..,6: When UFIFOFR[UCF_CT] is equal to 6 then..,7: When UFIFOFR[UCF_CT] is equal to 7 then.." group.long 0x40++0x13 line.long 0x0 "UHWHDR,Upstream HardWare High Data Register" hexmask.long 0x0 0.--31. 1. "UHHD,Upstream Hardware High Data. UHHD is a Read/Write bit field. The 32-bit UHHD [31:0] contain the Upstream high part of the received Upstream Hardware Data UHD[61:32]. UHHD is accessible in Write by hardware from the Hardware Channel and both in Read.." line.long 0x4 "UHWLDR,Upstream HardWare Low Data Register" hexmask.long 0x4 0.--31. 1. "UHLD,Upstream Hardware Low Data. UHLD is a Read/Write bit field. The 32-bit UHLD [31:0] contain the Upstream low part of the received Upstream Hardware Data UHD[31:0]. UHLD is accessible in Write by hardware from the Hardware Channel and both in Read and.." line.long 0x8 "UHWSUR,Upstream HardWare SetUp Register" hexmask.long.byte 0x8 16.--22. 1. "UH_K,Upstream Hardware K number. UH_K is a Read/Write bits field. Writing the UH_K bits the Upstream hardware K number is defined. The meaning of the selected code is defined in the following:" hexmask.long.byte 0x8 8.--12. 1. "UH_PP,Upstream Hardware Passive Phase Number. UH_PP is a Read/Write bits field. Writing the UH_PP bits the number of Upstream hardware passive phases is defined. The meaning of the selected code is defined in the following:" newline bitfld.long 0x8 1. "UH_OUTE,Upstream Hardware Output data Enable. UH_OUTE is a specific Read/Write bit field." "0: The UH_OUTE bit at '0' means the Upstream..,1: The UH_OUTE bit at '1' means the Upstream.." bitfld.long 0x8 0. "UH_OFF,Upstream Hardware OFF. UH_OFF is a Read/Write bit field. The UH_OFF bit when set enables to turn off the Upstream Data Receiver." "0: The UH_OFF bit at '0' means the Upstream Data..,1: The UH_OFF bit at '1' means the Upstream Data.." line.long 0xC "UHWIR,Upstream HardWare Interrupt Register" bitfld.long 0xC 31. "EN_IRQ0,ENable upstream hardware Interrupt ReQuest 0. EN_IRQ0 is a Read/Write bit field. The EN_IRQ0 bit enables or disables the IRQ_0." "0: The mscp_uhw_irq0 interrupt request is disabled.,1: The mscp_uhw_irq0 interrupt request is enabled." bitfld.long 0xC 30. "EN_IRQ1,ENable upstream hardware Interrupt ReQuest 1. EN_IRQ1 is a Read/Write bit field. The EN_IRQ1 bit enables or disables the IRQ_1." "0: The mscp_uhw_irq1 interrupt request is disabled.,1: The mscp_uhw_irq1 interrupt request is enabled." newline bitfld.long 0xC 28. "EN_UH_SSVE,ENable Upstream Hardware Start Selection bit Value Error. EN_UH_SSVE is a Read/Write bit field. The EN_UH_SSVE bit enables or disables the start selection bit value error interrupt." "0: The mscp_uhw_ssve interrupt request is disabled.,1: The mscp_uhw_ssve interrupt request is enabled." bitfld.long 0xC 27. "EN_UH_PPNE,ENable Upstream Hardware Passive Phase bits Number Error. EN_UH_PPNE is a Read/Write bit field. The EN_UH_PPNE bit enables or disables the passive phase bits number error interrupt." "0: The mscp_uhw_ppne interrupt request is disabled.,1: The mscp_uhw_ppne interrupt request is enabled." newline bitfld.long 0xC 26. "EN_UH_PVBNE,ENable Upstream Hardware channel Protocol Violation Bit Number Error. EN_UH_PVBNE is a Read/Write bit field." "0: The mscp_uhw_pvbne interrupt request is disabled.,1: The mscp_uhw_pvbne interrupt request is enabled." bitfld.long 0xC 25. "EN_UH_OWR,ENable Upstream Hardware OverWRite data previously received. EN_UH_OWR is a Read/Write bit field. The EN_UH_OWR bit enables or disables the overwrite hardware data interrupt." "0: The mscp_uhw_owr interrupt request is disabled.,1: The mscp_uhw_owr interrupt request is enabled." newline bitfld.long 0xC 24. "EN_UH_NEWD,ENable Upstream Hardware NEW Data reception. EN_UH_NEWD is a Read/Write bit field. The EN_UH_NEWD bit enables or disables the new hardware data reception interrupt." "0: The mscp_uhw_newd interrupt request is disabled.,1: The mscp_uhw_newd interrupt request is enabled." bitfld.long 0xC 23. "IRQ0,Interrupt ReQuest 0. IRQ0 is a Read only bit field. The IRQ0 gives the interrupt pending bit received from the last reception. The IRQ0 is hardware set by the mscp_uho[N] where (N=0 1 ... 7) and it is defined in the UHOWR[UH_I0MAP] register field" "0: no mscp_uhw_irq0 Interrupt request pending bit..,1: mscp_uhw_irq0 Interrupt request pending bit has.." newline bitfld.long 0xC 22. "IRQ1,Interrupt ReQuest 1. IRQ1 is a Read only bit field. The IRQ1 gives the interrupt pending bit received from the last reception. The IRQ1 is hardware set by the mscp_uho[N] where (N=0 1 ... 7) and it is defined in the UHOWR[UH_I1MAP] register field" "0: no mscp_uhw_irq1 Interrupt request pending bit..,1: mscp_uhw_irq1 Interrupt request pending bit has.." bitfld.long 0xC 20. "UH_SSVE,Upstream Hardware Start Selection bit Value Error. UH_SSVE is a Read/Clear bit field. The UH_SSVE flag bit rises when the Upstream Hardware Receiver has received a start selection bit (which is the first bit in the received Data frame) different.." "0: The UH_SSVE pending bit is cleared by a SW..,1: The UH_SSVE pending bit is set by HW only when.." newline bitfld.long 0xC 19. "UH_PPNE,Upstream Hardware Passive Phase bits Number Error. UH_PPNE is a Read/Clear bit field. The UH_PPNE flag bit rises when the Upstream Hardware Receiver has received a passive phase bits number UH_CURR_PPN different than the expected number.." "0: The UH_PPNE pending bit is cleared by a SW..,1: The UH_PPNE pending bit is set by HW only when.." bitfld.long 0xC 18. "UH_PVBNE,Upstream Hardware channel Protocol Violation Bit Number Error. UH_PVBNE is a Read/Clear bit field. The UH_PVBNE pending bit rises when a protocol violation occurs. A protocol violation arises when the number of bits of received frame is.." "0: The UH_PVBNE pending bit is cleared by a SW..,1: The UH_PVBNE pending bit is set by HW only." newline bitfld.long 0xC 17. "UH_OWR,Upstream Hardware OverWrite Data previously received. UH_OWR is a Read/Clear bit field. UH_OWR pending bit rises when on a UH_NEWD bit already set a new set occurs." "0: The UH_OWR pending bit is cleared setting by SW..,1: The UH_OWR pending bit is set by HW when on a.." bitfld.long 0xC 16. "UH_NEWD,Upstream Hardware NEW Data. UH_NEWD is a Read/Clear bit field. The UH_NEWD pending bit rises when the whole Data frame received by Upstream Channel is transferred into UHWDR[63:0] (= UHWHDR[63:32] UHWLDR[31:0])." "0: The UH_NEWD pending bit is cleared by a SW..,1: The UH_NEWD pending bit is set by HW only when a.." line.long 0x10 "UHWMSR,Upstream Hardware Muxes Setup Register" bitfld.long 0x10 25.--27. "UH_I1MAP,Upstream Hardware data Interrupt 1 MAP. UH_I1MAP is a specific Read/Write 3 bits field. When a value N is written into UH_I1MAP (where N=1 ... 7) and the UH_I1ME bit is '1' it means the External Modulator data is on the bit N of the mscp_uho.." "0: mscp_uho[0] will be written into irq1 pending bit,1: mscp_uho[1] will be written into irq1 pending bit,2: mscp_uho[2] will be written into irq1 pending bit,3: mscp_uho[3] will be written into irq1 pending bit,4: mscp_uho[4] will be written into irq1 pending bit,5: mscp_uho[5] will be written into irq1 pending bit,6: mscp_uho[6] will be written into irq1 pending bit,7: mscp_uho[7] will be written into irq1 pending bit." bitfld.long 0x10 24. "UH_I1ME,Upstream Hardware Interrupt request 1 Mapping Enable. UH_I1ME is a specific Read/Write bit field. Setting both the UHWSUR[UH_OFF] and the UH_I1ME register bits the Upstream Hardware permits to map the Upstream Hardware data interrupt 1 detection.." "0: The UH_I1ME bit at '0' means the Upstream..,1: The UH_I1ME bit at '1' means the Upstream.." newline bitfld.long 0x10 17.--19. "UH_I0MAP,Upstream Hardware data Interrupt 0 MAP. UH_I0MAP is a specific Read/Write 3 bits field. When a value N is written into UH_I0MAP (where N=1 ... 7) and the UH_I0ME bit is '1' it means the External Modulator data is on the bit N of the mscp_uho.." "0: mscp_uho[0] will be written into irq1 pending bit,1: mscp_uho[1] will be written into irq1 pending bit,2: mscp_uho[2] will be written into irq1 pending bit,3: mscp_uho[3] will be written into irq1 pending bit,4: mscp_uho[4] will be written into irq1 pending bit,5: mscp_uho[5] will be written into irq1 pending bit,6: mscp_uho[6] will be written into irq1 pending bit,7: mscp_uho[7] will be written into irq1 pending bit." bitfld.long 0x10 16. "UH_I0ME,Upstream Hardware Interrupt request 0 Mapping Enable. UH_I0ME is a specific Read/Write bit field. Setting both the UHWSUR[UH_OFF] and the UH_I0ME register bits the Upstream Hardware permits to map the Upstream Hardware data interrupt 0 detection.." "0: The UH_I0ME bit at '0' means the Upstream..,1: The UH_I0ME bit at '1' means the Upstream.." newline bitfld.long 0x10 1.--3. "UH_EMMAP,Upstream Hardware data External Modulator Mode MAP. UH_EMMAP is a specific Read/Write 3 bits field. When a value N is written into UH_EMMAP (where N=0 1 ... 7) and the UH_EMME bit is '1' it means the External Modulator data is on the bit N of.." "0: mscp_uho[0] will be written into mscp_em[0] output,1: mscp_uho[1] will be written into mscp_em[0] output,2: mscp_uho[2] will be written into mscp_em[0] output,3: mscp_uho[3] will be written into mscp_em[0] output,4: mscp_uho[4] will be written into mscp_em[0] output,5: mscp_uho[5] will be written into mscp_em[0] output,6: mscp_uho[6] will be written into mscp_em[0] output,7: mscp_uho[7] will be written into mscp_em[0] output" bitfld.long 0x10 0. "UH_EMME,Upstream Hardware data External Modulator Mode Enable. UH_EMME is a specific Read/Write bit field. Setting the UH_EMME register bits the Upstream Hardware data enters the External Modulator Mode following this actions sequence:" "0: The UH_EMME bit at '0' means the Upstream..,1: The UH_EMME bit at '1' means the Upstream.." group.long 0x70++0x27 line.long 0x0 "DFIFOR,Downstream FIFO Register" hexmask.long 0x0 0.--31. 1. "DFIFO,Downstream FIFO frame. DFIFO is a Software write only bit field. The 32-bit DFIFO is individually accessible in Read by hardware from the Downstream data UART and the same DFIFO is accessible in Write both by both software and by DMA. Once the.." line.long 0x4 "DSWDR,Downstream SoftWare Data Register" hexmask.long 0x4 0.--31. 1. "DSD,Downstream Software Data is a Read/Write bit field. The 32-bit DSD[31:0] is individually accessible in Read by hardware from the Downstream software UART and both in Read and Write by software. The hardware Read has greater priority than the software.." line.long 0x8 "DSWSUR,Downstream SoftWare SetUp Register" bitfld.long 0x8 31. "DSS_REQ,Downstream Software Setup REQuest. Setting the DSS_REQ bit both the transmission parameters DSWSUR[DS_X] DSWSUR[DS_N] DSWSUR[DS_SB] DSWSUR[DS_PAR] DHWSUR[DH_M] DHWSUR[DH_PP] and the DSWDR register content (if DSWSUR[DSWDR_EN] bit is 1) will.." "0: The DSS_REQ is cleared by HW a clk cycle after..,1: The DSS_REQ setting is kept for one clk cycle.." bitfld.long 0x8 30. "DSS_ACK,Downstream Software Setup ACKnowledge. DSS_ACK is a Read bit field. Setting the DSS_REQ bit once the transmission parameters and the updated content of DSWDR register (if DSWSUR[DSWDR_EN] = 1) have been loaded into the Downstream Data.." "0: DSS_ACK bit is cleared by setting the DSS_RAR bit.,1: The Downstream Data Transmitter has received the.." newline bitfld.long 0x8 29. "DSS_RAR,Downstream Software Setup Request Acknowledge Reset. DSS_RAR is a Read/Write bit field. Setting the DSS_RAR bit Both DSS_REQ and DSS_ACK bits will be cleared. When DSS_RAR field has been set by SW it remains high during one ipg_clk clock cycle.." "0: Both DSS_REQ and DSS_ACK bits can be accessed.,1: Both DSS_REQ and DSS_ACK bits are forced low." bitfld.long 0x8 24. "DSWDR_EN,Downstream Software Data Register Enable. DSWDR_EN is a Read/Write bit field. This register bit enables the transmission of the Software data from the DSWDR register while disables the transmission from DFIFOR. Clearing both the DSWDR_EN bit and.." "0: DSWDR cannot be accessed.,1: DSWDR can be accessed." newline hexmask.long.byte 0x8 16.--20. 1. "DS_X,Downstream Software X number. DS_X is a Read/Write bits field. Writing the DS_X bits the Downstream software X number is defined. The meaning of the selected code is defined in the following:" hexmask.long.byte 0x8 8.--13. 1. "DS_N,Downstream Software N number. DS_N is a Read/Write bits field. Writing the DS_N bits the Downstream software N number (number of serialized UART bits) is defined. The meaning of the selected code is defined in the following:" newline bitfld.long 0x8 4.--5. "DS_SB,Downstream Software Stop Bits number. DS_SB is a Read/Write bit field. The DS_SB bit defines the Downstream Software UART stop bits number which means how many bits are expected as stop bits. The default value DS_SB=0 means 2 Stop Bits. According.." "0: 2 Stop Bits,1: 1 Stop Bit,2: 2 Stop Bits,3: 3 Stop Bits" bitfld.long 0x8 0. "DS_PAR,Downstream Software PARity kind. DS_PAR is a Read/Write bit field. The DS_PAR bit defines the Downstream Software UART parity kind which means if the expected parity of received software data is odd or even." "0: Even parity,1: Odd parity" line.long 0xC "DSWIR,Downstream SoftWare Interrupt Register" bitfld.long 0xC 31. "EN_DSW_START,ENable Downstream SoftWare START. EN_DSW_START is a Read/Write bit field. The EN_DSW_START bit enables or disables the transmission start interrupt both for DCF and for DSWDR." "0: The mscp_dsw_start interrupt request is disabled.,1: The mscp_dsw_start interrupt request is enabled." bitfld.long 0xC 30. "DSW_START,Downstream Software START. DSW_START is a Read/set to clear bit field. It asserts when transmission of a UART frame (SW Data) starts." "0: The DSW_START pending bit is cleared by a SW..,1: The DSW_START pending bit is set by HW only when.." newline bitfld.long 0xC 15. "EN_DSW_END,ENable Downstream SoftWare END. EN_DSW_END is a Read/Write bit field. The EN_DSW_END bit enables or disables the transmission end interrupt both for DCF and for DSWDR." "0: The mscp_dsw_end interrupt request is disabled.,1: The mscp_dsw_end interrupt request is enabled." bitfld.long 0xC 14. "DSW_END,Downstream Software END. DSW_END is a Read/set to clear bit field. It asserts when the transmission of the current UART frame (SW Data) has completed." "0: The DSW_END pending bit is cleared by a SW..,1: The DSW_END pending bit is set by HW only when.." line.long 0x10 "DFIFOFR,Downstream FIFO Flag Register" bitfld.long 0x10 30.--31. "DTX_RGFI,Downstream Receiver ReGister FIfo. DTX_RGFI is a 2-bit Read only field." "0: both DCF and DSWDR are disabled.,1: DCF disabled DSWDR enabled.,2: DCF enabled not in DMA DSWDR disabled.,3: DCF enabled in DMA DSWDR disabled." bitfld.long 0x10 29. "DCF_DMARUN,Downstream Circular Fifo DMA RUNning. DCF_DMARUN is a Read only bit field. While a data transfer on DMA UCF the DMA DCF interface is running the DCF_DMARUN register bit asserts." "0: Data transfer on DMA UCF interface not running.,1: Data transfer on DMA UCF interface running." newline bitfld.long 0x10 28. "DCF_DMAREQ,Downstream Circular Fifo DMA REQuest. DCF_DMAREQ is a Read only bit field. If the DMA is enabled (DFIFOCR[DCF_DMA]='1') the DFIFOFR[DCF_DMAREQ] flag bit asserts when the IP is requiring a DMA request." "0: DMA request is '0'.,1: DMA request is '1'." bitfld.long 0x10 27. "DCF_FULL,Downstream Circular Fifo FULL. DCF_FULL is a Read/Set to Clear bit field. When the received frame has been copied in the last available Downstream FIFO location the DFIFOFR[DCF_FULL] flag bit rises and if DFIFOCR[EN_DCF_FULL] = '1' the.." "0: The DCF_FULL pending bit is cleared setting by..,1: The DCF_FULL pending bit is set by HW when the.." newline bitfld.long 0x10 26. "DCF_TVR,Downstream Circular Fifo Threshold Value Reached. DCF_TVR is a Read/Set to Clear bit field. This pending bit asserts when the number of elements in the DCF is less or equal than the threshold value. This means that if DFIFOFR[DCF_CT(2:0)].." "0: The DCF_TVR pending bit is cleared because the..,1: The DCF_TVR pending bit has set because once.." bitfld.long 0x10 25. "DCF_EMPTY,Downstream Circular Fifo EMPTY. DCF_EMPTY is a Read/Set to Clear bit field. When the last Downstream Circular FIFO location has been read the DFIFOFR[DCF_EMPTY] flag bit rises and if the DFIFOFR[EN_DCF_EMPTY] bit is 'high' a tx_dcf_empty.." "0: The DCF_EMPTY pending bit is cleared by setting..,1: The DCF_EMPTY pending bit is set by HW when the.." newline hexmask.long.byte 0x10 16.--19. 1. "DCF_CT,Downstream Circular Fifo Current Threshold. The DCF_CT is a Read only bit field. It states how many DFIFO elements written are still not read in the Downstream Circular FIFO." bitfld.long 0x10 8. "DCF_PTRCL,Downstream Circular Fifo read/write PoinTeRs CLear action. DCF_PTRCL is a Read/Write bit field. In order to perform a clear action of the dcf read/write pointers it is required to clear the DFIFOFR[DCF_PTRCL] bit." "0: A DCF read/write pointers clearing has been..,1: DCF read/write pointers clearing is running." line.long 0x14 "DFIFOCR,Downstream FIFO Control Register" bitfld.long 0x14 31. "DCF_EN,Downstream Circular Fifo ENabled. DCF_EN is a Read/Write bit field. The DFIFOCR[DCF_EN] bit enables the Downstream Circular FIFO to be used instead of DSWDR register." "0: the Downstream Circular FIFO is disabled.,1: the Downstream Circular FIFO is enabled." bitfld.long 0x14 30. "DCF_DMA,Downstream Circular Fifo DMA. DFIFOCR[DCF_DMA] is a Read/Write bit field. If the DFIFOCR[DCF_EN] is 'high' when DFIFOCR[DCF_DMA] is set the Downstream Circular FIFO is managed by DMA." "0: the enabled Downstream Circular FIFO is..,1: the enabled Downstream Circular FIFO is.." newline bitfld.long 0x14 27. "EN_DCF_FULL,ENable Downstream Circular Fifo FULL. EN_DCF_FULL is a Read/Write bit field. When the received frame has been copied in the last Downstream Circular FIFO free location the DFIFOFR[DCF_FULL] flag bit rises and if the DFIFOFR[EN_DCF_FULL] bit.." "0: Disable any tx_dcf_full interrupt request.,1: Enable the tx_dcf_full interrupt request coming.." bitfld.long 0x14 26. "EN_DCF_TVR,ENable Downstream Circular Fifo Threshold Value Reached. EN_DCF_TVR is a Read/Write bit field. When DFIFOFR[DCF_CT(2:0)] becomes less or equal than DFIFOCR[DCF_TV(2:0)] the DFIFOFR[DCF_TVR] flag bit rises and if the DFIFOFR[DCF_TVR] bit is.." "0: Disable any tx_dcf_tvr interrupt request.,1: Enable the tx_dcf_tvr interrupt request coming.." newline bitfld.long 0x14 25. "EN_DCF_EMPTY,ENable Downstream Circular Fifo EMPTY. EN_DCF_EMPTY is a Read/Write bit field. When the last Upstream Circular FIFO location has been read the DFIFOFR[DCF_EMPTY] flag bit rises and if the DFIFOFR[EN_DCF_EMPTY] bit is 'high' the tx_dcf_empty.." "0: Disable any tx_dcf_empty interrupt request.,1: Enable the tx_dcf_empty interrupt request coming.." bitfld.long 0x14 16.--18. "DCF_TV,Downstream Circular Fifo Threshold Value. The DCF_TV is a Read/Write bit field. The difference between written dcf registers and read dcf registers affects the DFIFOFR[DCF_TVR] bit as follows:" "0: When DFIFOFR[DCF_CT] is equal to 0 then..,1: When DFIFOFR[DCF_CT] is equal to 1 then..,2: When DFIFOFR[DCF_CT] is equal to 2 then..,3: When DFIFOFR[DCF_CT] is equal to 3 then..,4: When DFIFOFR[DCF_CT] is equal to 4 then..,5: When DFIFOFR[DCF_CT] is equal to 5 then..,6: When DFIFOFR[DCF_CT] is equal to 6 then..,7: When DFIFOFR[DCF_CT] is equal to 7 then.." line.long 0x18 "DHWHDR,Downstream HardWare High Data Register" hexmask.long 0x18 0.--31. 1. "DHHD,Downstream Hardware High Data. DHHD is a Read/Write bit field. The 32-bit DHHD [31:0] contain the Downstream high part of the Downstream Hardware Data DHD[61:32] to be transmitted. DHHD is accessible in Read by hardware from the Hardware Channel and.." line.long 0x1C "DHWLDR,Downstream HardWare Low Data Register" hexmask.long 0x1C 0.--31. 1. "DHLD,Downstream Hardware Low Data. DHLD is a Read/Write bit field. The 32-bit DHLD [31:0] contain the Downstream low part of the Downstream Hardware Data DHD[31:0] to be transmitted. DHLD is accessible in Read by hardware from the Hardware Channel and.." line.long 0x20 "DHWSUR,Downstream HardWare SetUp Register" bitfld.long 0x20 31. "DHS_REQ,Downstream Hardware Setup REQuest. Setting the DHS_REQ bit the SIUL_HWSW is sampled and loaded both into DHWDR register and into Downstream Data Transmitter to be transmitted (refer to Figure2481) Downstream Tx architecture). This bit can be.." "0: The DHS_REQ is cleared by HW a clk cycle after..,1: The DHS_REQ setting is kept for one clk cycle.." bitfld.long 0x20 30. "DHS_ACK,Downstream Hardware Setup ACKnowledge. DHS_ACK is a Read bit field. Setting the DHS_REQ bit once the SAMPLED_HWSW(63:0) (refer to Figure2481) Downstream Tx architecture) has been loaded into the Downstream Data Transmitter to be transmitted .." "0: DHS_ACK bit is cleared by setting the DHS_RAR..,1: The Downstream Data Transmitter has received the.." newline bitfld.long 0x20 29. "DHS_RAR,Downstream Hardware Setup Request Acknowledge Reset. DHS_RAR is a Read/Write bit field. Setting the DHS_RAR bit Both DHS_REQ and DHS_ACK bits will be cleared. When DHS_RAR field has been set by SW it remains high during one ipg_clk clock cycle.." "0: Both DHS_REQ and DHS_ACK bits can be accessed.,1: Both DHS_REQ and DHS_ACK bits are forced low." hexmask.long.byte 0x20 16.--22. 1. "DH_M,Downstream Hardware M number. DH_M is a Read/Write bits field. Writing the DH_M bits the Upstream hardware M number is defined. The meaning of the selected code is defined in the following:" newline hexmask.long.byte 0x20 8.--12. 1. "DH_PP,Downstream Hardware Passive Phase Number. DH_PP is a Read/Write bits field. Writing the DH_PP bits the number of Downstream hardware passive phases is defined. The meaning of the selected code is defined in the following:" bitfld.long 0x20 1. "TX_ON,Transmission on. TX_ON is a Read/Write bit field. The TX_ON bit when set activates the transmission of data frames. Transmission runs as long as TX_ON bit is set." "0: Data frames transmission off,1: Data frames transmission running" newline bitfld.long 0x20 0. "DH_OFF,Downstream Hardware OFF. DH_OFF is a Read/Write bit field. The DH_OFF disables the downstream hardware transmitter immediately and remains 1." "0: Transmitter is enabled.,1: Transmitter is disabled." line.long 0x24 "DHWIR,Downstream HardWare Interrupt Register" bitfld.long 0x24 31. "EN_DH_START,ENable Downstream Hardware data frame transmission START. EN_DH_START is a Read/Write bit field. The EN_TX_START bit enables or disables the data frame transmission start interrupt both for DCF and for DSWDR." "0: The mscp_dhw_start interrupt request is disabled.,1: The mscp_dhw_start interrupt request is enabled." bitfld.long 0x24 28. "EN_DH_END,ENable Downstream Hardware data frame transmission END. EN_DH_END is a Read/Write bit field. The EN_DH_END bit enables or disables the data frame transmission end interrupt both for DCF and for DSWDR." "0: The mscp_dhw_end interrupt request is disabled.,1: The mscp_dhw_end interrupt request is enabled." newline bitfld.long 0x24 23. "DH_START,Downstream Hardware new data frame Transmission START. DH_START is a Read/Clear bit field. The DH_START flag bit rises when a new Data frame transmission starts." "0: The DH_START pending bit is cleared by a SW..,1: The DH_START pending bit is set by HW when a new.." bitfld.long 0x24 20. "DH_END,Downstream Hardware data frame transmission END. DH_END is a Read/Clear bit field. The DH_END flag bit rises when the Data frame transmission ends." "0: The DH_END pending bit is cleared by a SW setting.,1: The DH_END pending bit is set by HW when the.." group.long 0xB0++0xB line.long 0x0 "DHWTSCR,Downstream HardWare Timer Siul Counter Register" bitfld.long 0x0 31. "H0S1_SAMPLE,Hardware 0 Software 1 SAMPLE. H0S1_SAMPLE is a Read/Write bit field. The H0S1_SAMPLE control bit selects a SW or HW sampling." "0: Hardware sampling from siul_dhi_sample input..,1: Software sampling from Down-counter EOC selected." bitfld.long 0x0 30. "DSTART_CNT,START CouNTer. DSTART_CNT is a Read/Write bit field. The DSTART_CNT control field if 'high' starts the counter and keeps the free-running 'low' the down count is cleared and stopped." "0: The counter is kept on stop.,1: The counter is kept in free-running." newline hexmask.long.tbyte 0x0 0.--23. 1. "DCYCLESN,Downstream DCYCLES Number. DCYCLESN is a Read/Write bit field. The 24 DCYCLESN bits state the number of IPS clock cycles to wait for the End Of Count EOC. The counter is a free running down count and at the start the value to decrement.." line.long 0x4 "DHWSHMR,Downstream HardWare data Siul High Mux Register" hexmask.long 0x4 0.--31. 1. "DHWSHM,Downstream Hardware High SIUL Mux. DHTSHM is a Read/Write bit field. The 32 DHTSHM bits if cleared select as SIUL_HWSW[63:32] bits the bits coming from the SIUL source otherwise if set the DHWISR[63:32]. The mux selection refers to each bit.." line.long 0x8 "DHWSLMR,Downstream HardWare data Siul Low Mux Register" hexmask.long 0x8 0.--31. 1. "DHWSLM,Downstream Hardware Low SIUL Mux. DHTSLM is a Read/Write bit field. The 32 DHTSLM bits if cleared select as SIUL_HWSW[31:0] bits the bits coming from the SIUL source otherwise if set the DHWISR[31:0]. The mux selection refers to each bit.." group.long 0xC0++0x2F line.long 0x0 "DHPISR0,Downstream HardWare Parallel Input Select Register 0" hexmask.long.byte 0x0 28.--31. 1. "DHPIS7,Downstream Hardware Parallel Input Select 7. DHPIS7 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 7 of the frame to be transmitted." hexmask.long.byte 0x0 24.--27. 1. "DHPIS6,Downstream Hardware Parallel Input Select 6. DHPIS6 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 6of the frame to be transmitted." newline hexmask.long.byte 0x0 20.--23. 1. "DHPIS5,Downstream Hardware Parallel Input Select 5. DHPIS5 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 5 of the frame to be transmitted." hexmask.long.byte 0x0 16.--19. 1. "DHPIS4,Downstream Hardware Parallel Input Select 4. DHPIS4 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 4 of the frame to be transmitted." newline hexmask.long.byte 0x0 12.--15. 1. "DHPIS3,Downstream Hardware Parallel Input Select 3. DHPIS3 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 3 of the frame to be transmitted." hexmask.long.byte 0x0 8.--11. 1. "DHPIS2,Downstream Hardware Parallel Input Select 2. DHPIS2 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 2 of the frame to be transmitted." newline hexmask.long.byte 0x0 4.--7. 1. "DHPIS1,Downstream Hardware Parallel Input Select 1. DHPIS1 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 1 of the frame to be transmitted." hexmask.long.byte 0x0 0.--3. 1. "DHPIS0,Downstream Hardware Parallel Input Select 0. DHPIS0 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 0 of the frame to be transmitted." line.long 0x4 "DHPISR1,Downstream HardWare Parallel Input Select Register 1" hexmask.long.byte 0x4 28.--31. 1. "DHPIS15,Downstream Hardware Parallel Input Select 15. DHPIS15 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 15 of the frame to be transmitted." hexmask.long.byte 0x4 24.--27. 1. "DHPIS14,Downstream Hardware Parallel Input Select 14. DHPIS14 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 14 of the frame to be transmitted." newline hexmask.long.byte 0x4 20.--23. 1. "DHPIS13,Downstream Hardware Parallel Input Select 13. DHPIS13 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 13 of the frame to be transmitted." hexmask.long.byte 0x4 16.--19. 1. "DHPIS12,Downstream Hardware Parallel Input Select 12. DHPIS12 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 12 of the frame to be transmitted." newline hexmask.long.byte 0x4 12.--15. 1. "DHPIS11,Downstream Hardware Parallel Input Select 11. DHPIS11 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 11 of the frame to be transmitted." hexmask.long.byte 0x4 8.--11. 1. "DHPIS10,Downstream Hardware Parallel Input Select 10. DHPIS10 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 10 of the frame to be transmitted." newline hexmask.long.byte 0x4 4.--7. 1. "DHPIS9,Downstream Hardware Parallel Input Select 9. DHPIS9 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 9 of the frame to be transmitted." hexmask.long.byte 0x4 0.--3. 1. "DHPIS8,Downstream Hardware Parallel Input Select 8. DHPIS8 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 8 of the frame to be transmitted." line.long 0x8 "DHPISR2,Downstream HardWare Parallel Input Select Register 2" hexmask.long.byte 0x8 28.--31. 1. "DHPIS23,Downstream Hardware Parallel Input Select 23. DHPIS23 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 23 of the frame to be transmitted." hexmask.long.byte 0x8 24.--27. 1. "DHPIS22,Downstream Hardware Parallel Input Select 22. DHPIS22 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 22 of the frame to be transmitted." newline hexmask.long.byte 0x8 20.--23. 1. "DHPIS21,Downstream Hardware Parallel Input Select 21. DHPIS21 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 21 of the frame to be transmitted." hexmask.long.byte 0x8 16.--19. 1. "DHPIS20,Downstream Hardware Parallel Input Select 20. DHPIS20 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 20 of the frame to be transmitted." newline hexmask.long.byte 0x8 12.--15. 1. "DHPIS19,Downstream Hardware Parallel Input Select 19. DHPIS19 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 19 of the frame to be transmitted." hexmask.long.byte 0x8 8.--11. 1. "DHPIS18,Downstream Hardware Parallel Input Select 18. DHPIS18 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 18 of the frame to be transmitted." newline hexmask.long.byte 0x8 4.--7. 1. "DHPIS17,Downstream Hardware Parallel Input Select 17. DHPIS17 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 17 of the frame to be transmitted." hexmask.long.byte 0x8 0.--3. 1. "DHPIS16,Downstream Hardware Parallel Input Select 16. DHPIS16 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 16 of the frame to be transmitted." line.long 0xC "DHPISR3,Downstream HardWare Parallel Input Select Register 3" hexmask.long.byte 0xC 28.--31. 1. "DHPIS31,Downstream Hardware Parallel Input Select 31. DHPIS31 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 31 of the frame to be transmitted." hexmask.long.byte 0xC 24.--27. 1. "DHPIS30,Downstream Hardware Parallel Input Select 30. DHPIS30 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 30 of the frame to be transmitted." newline hexmask.long.byte 0xC 20.--23. 1. "DHPIS29,Downstream Hardware Parallel Input Select 29. DHPIS29 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 29 of the frame to be transmitted." hexmask.long.byte 0xC 16.--19. 1. "DHPIS28,Downstream Hardware Parallel Input Select 28. DHPIS28 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 28 of the frame to be transmitted." newline hexmask.long.byte 0xC 12.--15. 1. "DHPIS27,Downstream Hardware Parallel Input Select 27. DHPIS27 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 27 of the frame to be transmitted." hexmask.long.byte 0xC 8.--11. 1. "DHPIS26,Downstream Hardware Parallel Input Select 26. DHPIS26 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 26 of the frame to be transmitted." newline hexmask.long.byte 0xC 4.--7. 1. "DHPIS25,Downstream Hardware Parallel Input Select 25. DHPIS25 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 25 of the frame to be transmitted." hexmask.long.byte 0xC 0.--3. 1. "DHPIS24,Downstream Hardware Parallel Input Select 24. DHPIS24 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 24 of the frame to be transmitted." line.long 0x10 "DHPISR4,Downstream HardWare Parallel Input Select Register 4" hexmask.long.byte 0x10 28.--31. 1. "DHPIS39,Downstream Hardware Parallel Input Select 39. DHPIS39 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 39 of the frame to be transmitted." hexmask.long.byte 0x10 24.--27. 1. "DHPIS38,Downstream Hardware Parallel Input Select 38. DHPIS38 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 38 of the frame to be transmitted." newline hexmask.long.byte 0x10 20.--23. 1. "DHPIS37,Downstream Hardware Parallel Input Select 37. DHPIS37 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 37 of the frame to be transmitted." hexmask.long.byte 0x10 16.--19. 1. "DHPIS36,Downstream Hardware Parallel Input Select 36. DHPIS36 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 36 of the frame to be transmitted." newline hexmask.long.byte 0x10 12.--15. 1. "DHPIS35,Downstream Hardware Parallel Input Select 35. DHPIS35 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 35 of the frame to be transmitted." hexmask.long.byte 0x10 8.--11. 1. "DHPIS34,Downstream Hardware Parallel Input Select 34. DHPIS34 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 34 of the frame to be transmitted." newline hexmask.long.byte 0x10 4.--7. 1. "DHPIS33,Downstream Hardware Parallel Input Select 33. DHPIS33 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 33 of the frame to be transmitted." hexmask.long.byte 0x10 0.--3. 1. "DHPIS32,Downstream Hardware Parallel Input Select 32. DHPIS32 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 32 of the frame to be transmitted." line.long 0x14 "DHPISR5,Downstream HardWare Parallel Input Select Register 5" hexmask.long.byte 0x14 28.--31. 1. "DHPIS47,Downstream Hardware Parallel Input Select 47. DHPIS47 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 47 of the frame to be transmitted." hexmask.long.byte 0x14 24.--27. 1. "DHPIS46,Downstream Hardware Parallel Input Select 46. DHPIS46 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 46 of the frame to be transmitted." newline hexmask.long.byte 0x14 20.--23. 1. "DHPIS45,Downstream Hardware Parallel Input Select 45. DHPIS45 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 45 of the frame to be transmitted." hexmask.long.byte 0x14 16.--19. 1. "DHPIS44,Downstream Hardware Parallel Input Select 44. DHPIS44 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 44 of the frame to be transmitted." newline hexmask.long.byte 0x14 12.--15. 1. "DHPIS43,Downstream Hardware Parallel Input Select 43. DHPIS43 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 43 of the frame to be transmitted." hexmask.long.byte 0x14 8.--11. 1. "DHPIS42,Downstream Hardware Parallel Input Select 42. DHPIS42 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 42 of the frame to be transmitted." newline hexmask.long.byte 0x14 4.--7. 1. "DHPIS41,Downstream Hardware Parallel Input Select 41. DHPIS41 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 41 of the frame to be transmitted." hexmask.long.byte 0x14 0.--3. 1. "DHPIS40,Downstream Hardware Parallel Input Select 40. DHPIS40 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 40 of the frame to be transmitted." line.long 0x18 "DHPISR6,Downstream HardWare Parallel Input Select Register 6" hexmask.long.byte 0x18 28.--31. 1. "DHPIS55,Downstream Hardware Parallel Input Select 55. DHPIS55 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 55 of the frame to be transmitted." hexmask.long.byte 0x18 24.--27. 1. "DHPIS54,Downstream Hardware Parallel Input Select 54. DHPIS54 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 54 of the frame to be transmitted." newline hexmask.long.byte 0x18 20.--23. 1. "DHPIS53,Downstream Hardware Parallel Input Select 53. DHPIS53 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 53 of the frame to be transmitted." hexmask.long.byte 0x18 16.--19. 1. "DHPIS52,Downstream Hardware Parallel Input Select 52. DHPIS52 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 52 of the frame to be transmitted." newline hexmask.long.byte 0x18 12.--15. 1. "DHPIS51,Downstream Hardware Parallel Input Select 51. DHPIS51 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 51 of the frame to be transmitted." hexmask.long.byte 0x18 8.--11. 1. "DHPIS50,Downstream Hardware Parallel Input Select 50. DHPIS50 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 50 of the frame to be transmitted." newline hexmask.long.byte 0x18 4.--7. 1. "DHPIS49,Downstream Hardware Parallel Input Select 49. DHPIS49 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 49 of the frame to be transmitted." hexmask.long.byte 0x18 0.--3. 1. "DHPIS48,Downstream Hardware Parallel Input Select 48. DHPIS48 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 48 of the frame to be transmitted." line.long 0x1C "DHPISR7,Downstream HardWare Parallel Input Select Register 7" hexmask.long.byte 0x1C 28.--31. 1. "DHPIS63,Downstream Hardware Parallel Input Select 63. DHPIS63 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 63 of the frame to be transmitted." hexmask.long.byte 0x1C 24.--27. 1. "DHPIS62,Downstream Hardware Parallel Input Select 62. DHPIS62 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 62 of the frame to be transmitted." newline hexmask.long.byte 0x1C 20.--23. 1. "DHPIS61,Downstream Hardware Parallel Input Select 61. DHPIS61 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 61 of the frame to be transmitted." hexmask.long.byte 0x1C 16.--19. 1. "DHPIS60,Downstream Hardware Parallel Input Select 60. DHPIS60 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 60 of the frame to be transmitted." newline hexmask.long.byte 0x1C 12.--15. 1. "DHPIS59,Downstream Hardware Parallel Input Select 59. DHPIS59 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 59 of the frame to be transmitted." hexmask.long.byte 0x1C 8.--11. 1. "DHPIS58,Downstream Hardware Parallel Input Select 58. DHPIS58 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 58 of the frame to be transmitted." newline hexmask.long.byte 0x1C 4.--7. 1. "DHPIS57,Downstream Hardware Parallel Input Select 57. DHPIS57 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 57 of the frame to be transmitted." hexmask.long.byte 0x1C 0.--3. 1. "DHPIS56,Downstream Hardware Parallel Input Select 56. DHPIS56 is a Read/Write bitfield. Writing the 4 bits of this bitfield defines the parallel input pin bit 56 of the frame to be transmitted." line.long 0x20 "DHWIHSR,Downstream HardWare data Internal High Siul Register" hexmask.long 0x20 0.--31. 1. "DHWIHS,Downstream Hardware data Internal High SIUL Register. DHWIHS is a Read/Write bit field. The DHWIHS field keeps the highest 32 bits of the DHWISR register." line.long 0x24 "DHWILSR,Downstream HardWare data Internal Low Siul Register" hexmask.long 0x24 0.--31. 1. "DHWILS,Downstream Hardware data Internal Low SIUL Register. DHWILS is a Read/Write bit field. The DHWILS field keeps the lowest 32 bits of the DHWISR." line.long 0x28 "DHWEHSR,Downstream HardWare data External High Siul Register" hexmask.long 0x28 0.--31. 1. "DHWEHS,Downstream Hardware data External High SIUL Register. DHWEHS is a Read/Write bit field. The DHWEHS field keeps the highest 32 bits of the DHWESR." line.long 0x2C "DHWELSR,Downstream HardWare data External Low Siul Register" hexmask.long 0x2C 0.--31. 1. "DHWELS,Downstream Hardware data External Low SIUL Register. DHWELS is a Read/Write bit field. The DHWELS field keeps the lowest 32 bits of the DHWESR." tree.end tree.end tree "MTM (MRP Trace Macrocell)" base ad:0x0 tree "CLUSTER0_MTM_CORE0" base ad:0x7E006000 group.long 0x0++0x7 line.long 0x0 "MTM_EN,MTM enable register" bitfld.long 0x0 0. "MTM_ENABLE,MTM enable" "0: MTM disabled,1: MTM enabled" line.long 0x4 "MTM_TRC_EN,MTM trace enable" bitfld.long 0x4 1. "INVLD_FIFO,Invalidate FIFO" "0: Packet FIFO pointers is not invalidated old..,1: Invalidate Packet FIFO old trace data is lost." newline bitfld.long 0x4 0. "TRACE_EN,Trace Enable" "0: Trace filtering is disabled. When disabled TAG..,1: Trace filtering is enabled." group.long 0x20++0x7 line.long 0x0 "MTM_TRC_STALL_CTRL,MTM trace stall control register" hexmask.long.byte 0x0 1.--4. 1. "LEVEL,Level" newline bitfld.long 0x0 0. "STALL,Stall" "0: Backpressure form MTM does not stall the..,1: Backpressure form MTM can stall the processor or.." line.long 0x4 "MTM_TRC_ID,MTM trace ID register" hexmask.long.byte 0x4 0.--6. 1. "TRACE_ID,Trace ID value" rgroup.long 0x100++0x3 line.long 0x0 "MTM_BKP_STAT,MTM Backpressure status register" bitfld.long 0x0 1. "PCK_FIFO_FULL,Packet FIFO full" "0: Packet FIFO buffer not full.,1: Packet FIFO buffer full Backpressure scenario is.." group.long 0x200++0x3 line.long 0x0 "MTM_TAG_RGN_CONFIG,MTM TAG RAM configuration register" bitfld.long 0x0 2. "TAG_RGN_C,TAG region C" "0: Region C of the TAG RAM is not used.,1: Region C of the TAG RAM is used." newline bitfld.long 0x0 1. "TAG_RGN_B,TAG region B" "0: Region B of the TAG RAM is not used.,1: Region B of the TAG RAM is used." newline bitfld.long 0x0 0. "TAG_RGN_A,TAG region A" "0: Region A of the TAG RAM is not used.,1: Region A of the TAG RAM is used." group.long 0x210++0xB line.long 0x0 "MTM_TAG_RGN_BADR_A,MTM TAG RAM base address region A register" hexmask.long.tbyte 0x0 10.--31. 1. "A_REGION_BASE_ADR,A REGION BASE ADR value" line.long 0x4 "MTM_TAG_RGN_BADR_B,MTM TAG RAM base address region B register" hexmask.long.tbyte 0x4 10.--31. 1. "B_REGION_BASE_ADR,B REGION BASE ADR value" line.long 0x8 "MTM_TAG_RGN_BADR_C,MTM TAG RAM base address region C register" hexmask.long.tbyte 0x8 10.--31. 1. "C_REGION_BASE_ADR,C REGION BASE ADR value" rgroup.long 0x220++0xF line.long 0x0 "MTM_TAG_RGN_SZ_A,MTM TAG RAM region A size register" hexmask.long.word 0x0 0.--9. 1. "RGN_A_SIZE,RGN A size value" line.long 0x4 "MTM_TAG_RGN_SZ_B,MTM TAG RAM region B size register" hexmask.long.word 0x4 0.--9. 1. "RGN_B_SIZE,RGN B size value" line.long 0x8 "MTM_TAG_RGN_SZ_C,MTM TAG RAM size C size register" hexmask.long.word 0x8 0.--9. 1. "RGN_C_SIZE,RGN C size value" line.long 0xC "MTM_TAG_RGN_STAT,MTM TAG RAM region status register" bitfld.long 0xC 2. "RGN_C_BOUND_CROSS,RGN C bound cross" "0: Region C boundary not crossed.,1: Region C boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 1. "RGN_B_BOUND_CROSS,RGN B bound cross" "0: Region B boundary not crossed.,1: Region B boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 0. "RGN_A_BOUND_CROSS,RGN A bound cross" "0: Region A boundary not crossed.,1: Region A boundary crossed due to wrong 'PAGES'.." group.long 0x230++0x7 line.long 0x0 "MTM_TAG_ADR,MTM TAG RAM address register" bitfld.long 0x0 31. "AUTO_PROG_DONE,Auto programming done goes high when updates to tag RAM are completed by MTM. Debugger must clear this bit once set. Though this bit always provides the status of latest auto increment request even when debugger did not clear the.." "0: Auto programming is not completed.,1: Auto programming is completed." newline hexmask.long.word 0x0 10.--18. 1. "PAGES,Specifies the number of consecutive TAG RAM lines needs to be updated when Auto Increment address mode is enabled. Debugger must program PAGES field to 'required number of pages - 1'." newline hexmask.long.word 0x0 1.--9. 1. "ADDRESS_PAGE,Address page" newline bitfld.long 0x0 0. "AUTO_INCR,Auto increment" "0: Auto increment of the TAG address is disabled.,1: Auto increment of the TAG address is enabled." line.long 0x4 "MTM_TAG_DATA_CONFIG,MTM TAG RAM data configuration register" bitfld.long 0x4 17. "DATA_READ_STATUS,Data read status gives read completion status against the request set in DATA_READ bit." "0: Data read is not requested or completed.,1: Data read is completed for requested read." newline bitfld.long 0x4 16. "DATA_READ,Read control bit must be set by the debugger when it needs to read TAG RAM from the address programmed in ADDRESS_PAGE field of MTM_TAG_ADR register." "0: Read command is not set.,1: Read command is set." newline bitfld.long 0x4 5.--7. "SLICE_SIZE,Specify 3 most significant bits of every TAG RAM content line called ." "0: 8 byte,1: Filtering unit,2: 32 byte,3: 64 byte,4: 128 byte,5: 256 byte,6: 512 byte,7: 1K byte" newline hexmask.long.byte 0x4 1.--4. 1. "WORD_STROBE,WORD_STROBE bits are used to enable MTM_TAG_DATA_STROBE_W[n] registers. nth bit of WORD_STROBE corresponds to nth MTM_TAG_DATA_STROBE_W[n] register. For details refer to Section89.5.2.16: MTM TAG RAM strobe word n register.." newline bitfld.long 0x4 0. "DATA_VALID,Data valid controls write to TAG RAM" "0: TAG RAM content update is disabled.,1: TAG RAM content update is enabled." group.long 0x240++0xF line.long 0x0 "MTM_TAG_DATA_STROBE_W1,MTM TAG RAM strobe word 1 register" hexmask.long 0x0 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x4 "MTM_TAG_DATA_STROBE_W2,MTM TAG RAM strobe word 2 register" hexmask.long 0x4 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x8 "MTM_TAG_DATA_STROBE_W3,MTM TAG RAM strobe word 3 register" hexmask.long 0x8 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0xC "MTM_TAG_DATA_STROBE_W4,MTM TAG RAM strobe word 4 register" hexmask.long 0xC 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." group.long 0x400++0xB line.long 0x0 "MTM_TS_EN,MTM timestamp enable register" bitfld.long 0x0 0. "TS_EN,Timestamp enable" "0: TS packet generation disabled.,1: TS packet generation enabled." line.long 0x4 "MTM_TS_WIN_CNT,MTM Timestamp window counter register" hexmask.long 0x4 0.--31. 1. "WIND_COUNTER,Timestamp window counter value" line.long 0x8 "MTM_TS_CLK_SCL,MTM Timestamp clock scaler register" hexmask.long.word 0x8 0.--8. 1. "CLK_SCALER,Clock scaler value" group.long 0x410++0xB line.long 0x0 "AL_EN,Alignment message enable register" bitfld.long 0x0 0. "AL_EN,Alignment Synchronization (A-Sync) enable" "0: A-Sync packet generation disabled.,1: A-Sync packet generation enabled." line.long 0x4 "AL_WIN_CNT,Alignment message window counter register" hexmask.long 0x4 0.--31. 1. "AL_WIND_COUNTER,Alignment synchronization messages window counter value" line.long 0x8 "AL_CLK_SCL,Alignment window counter clock scaler register" hexmask.long.word 0x8 0.--8. 1. "AL_CLK_SCALER,Clock scaler value" group.long 0xFA0++0x7 line.long 0x0 "MTM_CLAIM_TAG_SET,MTM claim TAG set register" hexmask.long.byte 0x0 0.--3. 1. "CLAIM_SET,Claim set" line.long 0x4 "MTM_CLAIM_TAG_CLR,MTM claim TAG clear register" hexmask.long.byte 0x4 0.--3. 1. "CLAIM_CLEAR,Claim clear" wgroup.long 0xFB0++0x3 line.long 0x0 "MTM_LAR,MTM lock access register" hexmask.long 0x0 0.--31. 1. "SW_KEY,Software lock key value" rgroup.long 0xFB4++0xB line.long 0x0 "MTM_LSR,MTM lock status register" bitfld.long 0x0 2. "NTT,nTT" "0: Only value: MTM_LAR register is 32 bit wide (MTM..,?" newline bitfld.long 0x0 1. "SLK,SLK returns the software lock status." "0: Accesses permitted.,1: Write accesses to control registers of the MTM.." newline bitfld.long 0x0 0. "SLI,Software Lock Implementation" "0: Software lock is not implemented: returned for..,1: Software lock is implemented: returned for all.." line.long 0x4 "MTM_AUTH_STAT,MTM authentification status register" bitfld.long 0x4 6.--7. "SNID,Secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 4.--5. "SID,Secure invasive debug" "0: Functionality not implemented.,?,?,?" newline bitfld.long 0x4 2.--3. "NSNID,Non-secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 0.--1. "NSID,Non-secure invasive debug" "0: Functionality not implemented.,?,?,?" line.long 0x8 "MTM_DEV_ARCH,MTM device architecture register" hexmask.long.word 0x8 21.--31. 1. "ARCHITECT,Defines the Architect of the component:" newline bitfld.long 0x8 20. "PRES,Presence" "?,1: Device Architecture register is present." newline hexmask.long.byte 0x8 16.--19. 1. "ARCH_REVISION,Architecture revision" newline hexmask.long.word 0x8 0.--15. 1. "ARCH_ID,Architecture ID" rgroup.long 0xFC8++0x37 line.long 0x0 "MTM_DEV_ID,MTM device ID register" hexmask.long 0x0 0.--31. 1. "FUTURE_USE,Reserved" line.long 0x4 "MTM_DEV_TYPE,MTM device type register" hexmask.long.byte 0x4 4.--7. 1. "SUB,Based on ARM©defined codes (refer to Table B2-8 in document [5])." newline hexmask.long.byte 0x4 0.--3. 1. "MAJOR,Based on ARM©defined codes (refer to Table B2-8 in document [5])." line.long 0x8 "MTM_PID4,MTM peripheral ID4 register" bitfld.long 0x8 2.--3. "SIZE,Size" "0: MTM memory map occupies 4KB.,?,?,?" newline bitfld.long 0x8 0.--1. "DES_2,DES_2" "0: ST JEP106 continuation code (refer to the..,?,?,?" line.long 0xC "MTM_PID5,MTM peripheral ID5 register" hexmask.long 0xC 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x10 "MTM_PID6,MTM peripheral ID6 register" hexmask.long 0x10 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x14 "MTM_PID7,MTM peripheral ID7 register" hexmask.long 0x14 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x18 "MTM_PID0,MTM peripheral ID0 register" hexmask.long.byte 0x18 4.--7. 1. "PART_0M,Part 0M" newline hexmask.long.byte 0x18 0.--3. 1. "PART_0L,Part 0L" line.long 0x1C "MTM_PID1,MTM peripheral ID1 register" hexmask.long.byte 0x1C 4.--7. 1. "DES_0,DES 0" newline hexmask.long.byte 0x1C 0.--3. 1. "PART_1,Part 1" line.long 0x20 "MTM_PID2,MTM peripheral ID2 register" hexmask.long.byte 0x20 4.--7. 1. "REVISION,Revision" newline bitfld.long 0x20 3. "JEDEC,JEDEC" "?,1: Indicates that a JEDEC assigned value is used." newline bitfld.long 0x20 0.--2. "DES_1,DES 1" "?,?,2: ST JEP106 identification code [7] bits[6:4].,?,?,?,?,?" line.long 0x24 "MTM_PID3,MTM peripheral ID3 register" hexmask.long.byte 0x24 4.--7. 1. "REVAND,REVAND" newline hexmask.long.byte 0x24 0.--3. 1. "CMOD,CMOD" line.long 0x28 "MTM_CID0,MTM CS ID0 register" hexmask.long.byte 0x28 0.--7. 1. "PRMB0,Preamble 0" line.long 0x2C "MTM_CID1,MTM CS ID1 register" hexmask.long.byte 0x2C 4.--7. 1. "CLASS,Class" newline hexmask.long.byte 0x2C 0.--3. 1. "PRMB1,Preamble 1" line.long 0x30 "MTM_CID2,MTM CS ID2 register" hexmask.long.byte 0x30 0.--7. 1. "PRMB2,Preamble 2" line.long 0x34 "MTM_CID3,MTM CS ID3 register" hexmask.long.byte 0x34 0.--7. 1. "PRMB3,Preamble 3" tree.end tree "CLUSTER0_MTM_CORE1" base ad:0x7E008000 group.long 0x0++0x7 line.long 0x0 "MTM_EN,MTM enable register" bitfld.long 0x0 0. "MTM_ENABLE,MTM enable" "0: MTM disabled,1: MTM enabled" line.long 0x4 "MTM_TRC_EN,MTM trace enable" bitfld.long 0x4 1. "INVLD_FIFO,Invalidate FIFO" "0: Packet FIFO pointers is not invalidated old..,1: Invalidate Packet FIFO old trace data is lost." newline bitfld.long 0x4 0. "TRACE_EN,Trace Enable" "0: Trace filtering is disabled. When disabled TAG..,1: Trace filtering is enabled." group.long 0x20++0x7 line.long 0x0 "MTM_TRC_STALL_CTRL,MTM trace stall control register" hexmask.long.byte 0x0 1.--4. 1. "LEVEL,Level" newline bitfld.long 0x0 0. "STALL,Stall" "0: Backpressure form MTM does not stall the..,1: Backpressure form MTM can stall the processor or.." line.long 0x4 "MTM_TRC_ID,MTM trace ID register" hexmask.long.byte 0x4 0.--6. 1. "TRACE_ID,Trace ID value" rgroup.long 0x100++0x3 line.long 0x0 "MTM_BKP_STAT,MTM Backpressure status register" bitfld.long 0x0 1. "PCK_FIFO_FULL,Packet FIFO full" "0: Packet FIFO buffer not full.,1: Packet FIFO buffer full Backpressure scenario is.." group.long 0x200++0x3 line.long 0x0 "MTM_TAG_RGN_CONFIG,MTM TAG RAM configuration register" bitfld.long 0x0 2. "TAG_RGN_C,TAG region C" "0: Region C of the TAG RAM is not used.,1: Region C of the TAG RAM is used." newline bitfld.long 0x0 1. "TAG_RGN_B,TAG region B" "0: Region B of the TAG RAM is not used.,1: Region B of the TAG RAM is used." newline bitfld.long 0x0 0. "TAG_RGN_A,TAG region A" "0: Region A of the TAG RAM is not used.,1: Region A of the TAG RAM is used." group.long 0x210++0xB line.long 0x0 "MTM_TAG_RGN_BADR_A,MTM TAG RAM base address region A register" hexmask.long.tbyte 0x0 10.--31. 1. "A_REGION_BASE_ADR,A REGION BASE ADR value" line.long 0x4 "MTM_TAG_RGN_BADR_B,MTM TAG RAM base address region B register" hexmask.long.tbyte 0x4 10.--31. 1. "B_REGION_BASE_ADR,B REGION BASE ADR value" line.long 0x8 "MTM_TAG_RGN_BADR_C,MTM TAG RAM base address region C register" hexmask.long.tbyte 0x8 10.--31. 1. "C_REGION_BASE_ADR,C REGION BASE ADR value" rgroup.long 0x220++0xF line.long 0x0 "MTM_TAG_RGN_SZ_A,MTM TAG RAM region A size register" hexmask.long.word 0x0 0.--9. 1. "RGN_A_SIZE,RGN A size value" line.long 0x4 "MTM_TAG_RGN_SZ_B,MTM TAG RAM region B size register" hexmask.long.word 0x4 0.--9. 1. "RGN_B_SIZE,RGN B size value" line.long 0x8 "MTM_TAG_RGN_SZ_C,MTM TAG RAM size C size register" hexmask.long.word 0x8 0.--9. 1. "RGN_C_SIZE,RGN C size value" line.long 0xC "MTM_TAG_RGN_STAT,MTM TAG RAM region status register" bitfld.long 0xC 2. "RGN_C_BOUND_CROSS,RGN C bound cross" "0: Region C boundary not crossed.,1: Region C boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 1. "RGN_B_BOUND_CROSS,RGN B bound cross" "0: Region B boundary not crossed.,1: Region B boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 0. "RGN_A_BOUND_CROSS,RGN A bound cross" "0: Region A boundary not crossed.,1: Region A boundary crossed due to wrong 'PAGES'.." group.long 0x230++0x7 line.long 0x0 "MTM_TAG_ADR,MTM TAG RAM address register" bitfld.long 0x0 31. "AUTO_PROG_DONE,Auto programming done goes high when updates to tag RAM are completed by MTM. Debugger must clear this bit once set. Though this bit always provides the status of latest auto increment request even when debugger did not clear the.." "0: Auto programming is not completed.,1: Auto programming is completed." newline hexmask.long.word 0x0 10.--18. 1. "PAGES,Specifies the number of consecutive TAG RAM lines needs to be updated when Auto Increment address mode is enabled. Debugger must program PAGES field to 'required number of pages - 1'." newline hexmask.long.word 0x0 1.--9. 1. "ADDRESS_PAGE,Address page" newline bitfld.long 0x0 0. "AUTO_INCR,Auto increment" "0: Auto increment of the TAG address is disabled.,1: Auto increment of the TAG address is enabled." line.long 0x4 "MTM_TAG_DATA_CONFIG,MTM TAG RAM data configuration register" bitfld.long 0x4 17. "DATA_READ_STATUS,Data read status gives read completion status against the request set in DATA_READ bit." "0: Data read is not requested or completed.,1: Data read is completed for requested read." newline bitfld.long 0x4 16. "DATA_READ,Read control bit must be set by the debugger when it needs to read TAG RAM from the address programmed in ADDRESS_PAGE field of MTM_TAG_ADR register." "0: Read command is not set.,1: Read command is set." newline bitfld.long 0x4 5.--7. "SLICE_SIZE,Specify 3 most significant bits of every TAG RAM content line called ." "0: 8 byte,1: Filtering unit,2: 32 byte,3: 64 byte,4: 128 byte,5: 256 byte,6: 512 byte,7: 1K byte" newline hexmask.long.byte 0x4 1.--4. 1. "WORD_STROBE,WORD_STROBE bits are used to enable MTM_TAG_DATA_STROBE_W[n] registers. nth bit of WORD_STROBE corresponds to nth MTM_TAG_DATA_STROBE_W[n] register. For details refer to Section89.5.2.16: MTM TAG RAM strobe word n register.." newline bitfld.long 0x4 0. "DATA_VALID,Data valid controls write to TAG RAM" "0: TAG RAM content update is disabled.,1: TAG RAM content update is enabled." group.long 0x240++0xF line.long 0x0 "MTM_TAG_DATA_STROBE_W1,MTM TAG RAM strobe word 1 register" hexmask.long 0x0 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x4 "MTM_TAG_DATA_STROBE_W2,MTM TAG RAM strobe word 2 register" hexmask.long 0x4 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x8 "MTM_TAG_DATA_STROBE_W3,MTM TAG RAM strobe word 3 register" hexmask.long 0x8 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0xC "MTM_TAG_DATA_STROBE_W4,MTM TAG RAM strobe word 4 register" hexmask.long 0xC 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." group.long 0x400++0xB line.long 0x0 "MTM_TS_EN,MTM timestamp enable register" bitfld.long 0x0 0. "TS_EN,Timestamp enable" "0: TS packet generation disabled.,1: TS packet generation enabled." line.long 0x4 "MTM_TS_WIN_CNT,MTM Timestamp window counter register" hexmask.long 0x4 0.--31. 1. "WIND_COUNTER,Timestamp window counter value" line.long 0x8 "MTM_TS_CLK_SCL,MTM Timestamp clock scaler register" hexmask.long.word 0x8 0.--8. 1. "CLK_SCALER,Clock scaler value" group.long 0x410++0xB line.long 0x0 "AL_EN,Alignment message enable register" bitfld.long 0x0 0. "AL_EN,Alignment Synchronization (A-Sync) enable" "0: A-Sync packet generation disabled.,1: A-Sync packet generation enabled." line.long 0x4 "AL_WIN_CNT,Alignment message window counter register" hexmask.long 0x4 0.--31. 1. "AL_WIND_COUNTER,Alignment synchronization messages window counter value" line.long 0x8 "AL_CLK_SCL,Alignment window counter clock scaler register" hexmask.long.word 0x8 0.--8. 1. "AL_CLK_SCALER,Clock scaler value" group.long 0xFA0++0x7 line.long 0x0 "MTM_CLAIM_TAG_SET,MTM claim TAG set register" hexmask.long.byte 0x0 0.--3. 1. "CLAIM_SET,Claim set" line.long 0x4 "MTM_CLAIM_TAG_CLR,MTM claim TAG clear register" hexmask.long.byte 0x4 0.--3. 1. "CLAIM_CLEAR,Claim clear" wgroup.long 0xFB0++0x3 line.long 0x0 "MTM_LAR,MTM lock access register" hexmask.long 0x0 0.--31. 1. "SW_KEY,Software lock key value" rgroup.long 0xFB4++0xB line.long 0x0 "MTM_LSR,MTM lock status register" bitfld.long 0x0 2. "NTT,nTT" "0: Only value: MTM_LAR register is 32 bit wide (MTM..,?" newline bitfld.long 0x0 1. "SLK,SLK returns the software lock status." "0: Accesses permitted.,1: Write accesses to control registers of the MTM.." newline bitfld.long 0x0 0. "SLI,Software Lock Implementation" "0: Software lock is not implemented: returned for..,1: Software lock is implemented: returned for all.." line.long 0x4 "MTM_AUTH_STAT,MTM authentification status register" bitfld.long 0x4 6.--7. "SNID,Secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 4.--5. "SID,Secure invasive debug" "0: Functionality not implemented.,?,?,?" newline bitfld.long 0x4 2.--3. "NSNID,Non-secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 0.--1. "NSID,Non-secure invasive debug" "0: Functionality not implemented.,?,?,?" line.long 0x8 "MTM_DEV_ARCH,MTM device architecture register" hexmask.long.word 0x8 21.--31. 1. "ARCHITECT,Defines the Architect of the component:" newline bitfld.long 0x8 20. "PRES,Presence" "?,1: Device Architecture register is present." newline hexmask.long.byte 0x8 16.--19. 1. "ARCH_REVISION,Architecture revision" newline hexmask.long.word 0x8 0.--15. 1. "ARCH_ID,Architecture ID" rgroup.long 0xFC8++0x37 line.long 0x0 "MTM_DEV_ID,MTM device ID register" hexmask.long 0x0 0.--31. 1. "FUTURE_USE,Reserved" line.long 0x4 "MTM_DEV_TYPE,MTM device type register" hexmask.long.byte 0x4 4.--7. 1. "SUB,Based on ARM©defined codes (refer to Table B2-8 in document [5])." newline hexmask.long.byte 0x4 0.--3. 1. "MAJOR,Based on ARM©defined codes (refer to Table B2-8 in document [5])." line.long 0x8 "MTM_PID4,MTM peripheral ID4 register" bitfld.long 0x8 2.--3. "SIZE,Size" "0: MTM memory map occupies 4KB.,?,?,?" newline bitfld.long 0x8 0.--1. "DES_2,DES_2" "0: ST JEP106 continuation code (refer to the..,?,?,?" line.long 0xC "MTM_PID5,MTM peripheral ID5 register" hexmask.long 0xC 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x10 "MTM_PID6,MTM peripheral ID6 register" hexmask.long 0x10 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x14 "MTM_PID7,MTM peripheral ID7 register" hexmask.long 0x14 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x18 "MTM_PID0,MTM peripheral ID0 register" hexmask.long.byte 0x18 4.--7. 1. "PART_0M,Part 0M" newline hexmask.long.byte 0x18 0.--3. 1. "PART_0L,Part 0L" line.long 0x1C "MTM_PID1,MTM peripheral ID1 register" hexmask.long.byte 0x1C 4.--7. 1. "DES_0,DES 0" newline hexmask.long.byte 0x1C 0.--3. 1. "PART_1,Part 1" line.long 0x20 "MTM_PID2,MTM peripheral ID2 register" hexmask.long.byte 0x20 4.--7. 1. "REVISION,Revision" newline bitfld.long 0x20 3. "JEDEC,JEDEC" "?,1: Indicates that a JEDEC assigned value is used." newline bitfld.long 0x20 0.--2. "DES_1,DES 1" "?,?,2: ST JEP106 identification code [7] bits[6:4].,?,?,?,?,?" line.long 0x24 "MTM_PID3,MTM peripheral ID3 register" hexmask.long.byte 0x24 4.--7. 1. "REVAND,REVAND" newline hexmask.long.byte 0x24 0.--3. 1. "CMOD,CMOD" line.long 0x28 "MTM_CID0,MTM CS ID0 register" hexmask.long.byte 0x28 0.--7. 1. "PRMB0,Preamble 0" line.long 0x2C "MTM_CID1,MTM CS ID1 register" hexmask.long.byte 0x2C 4.--7. 1. "CLASS,Class" newline hexmask.long.byte 0x2C 0.--3. 1. "PRMB1,Preamble 1" line.long 0x30 "MTM_CID2,MTM CS ID2 register" hexmask.long.byte 0x30 0.--7. 1. "PRMB2,Preamble 2" line.long 0x34 "MTM_CID3,MTM CS ID3 register" hexmask.long.byte 0x34 0.--7. 1. "PRMB3,Preamble 3" tree.end tree "CLUSTER0_MTM_PRCTL0" base ad:0x7E00A000 group.long 0x0++0x7 line.long 0x0 "MTM_EN,MTM enable register" bitfld.long 0x0 0. "MTM_ENABLE,MTM enable" "0: MTM disabled,1: MTM enabled" line.long 0x4 "MTM_TRC_EN,MTM trace enable" bitfld.long 0x4 1. "INVLD_FIFO,Invalidate FIFO" "0: Packet FIFO pointers is not invalidated old..,1: Invalidate Packet FIFO old trace data is lost." newline bitfld.long 0x4 0. "TRACE_EN,Trace Enable" "0: Trace filtering is disabled. When disabled TAG..,1: Trace filtering is enabled." group.long 0x20++0x7 line.long 0x0 "MTM_TRC_STALL_CTRL,MTM trace stall control register" hexmask.long.byte 0x0 1.--4. 1. "LEVEL,Level" newline bitfld.long 0x0 0. "STALL,Stall" "0: Backpressure form MTM does not stall the..,1: Backpressure form MTM can stall the processor or.." line.long 0x4 "MTM_TRC_ID,MTM trace ID register" hexmask.long.byte 0x4 0.--6. 1. "TRACE_ID,Trace ID value" rgroup.long 0x100++0x3 line.long 0x0 "MTM_BKP_STAT,MTM Backpressure status register" bitfld.long 0x0 1. "PCK_FIFO_FULL,Packet FIFO full" "0: Packet FIFO buffer not full.,1: Packet FIFO buffer full Backpressure scenario is.." group.long 0x200++0x3 line.long 0x0 "MTM_TAG_RGN_CONFIG,MTM TAG RAM configuration register" bitfld.long 0x0 2. "TAG_RGN_C,TAG region C" "0: Region C of the TAG RAM is not used.,1: Region C of the TAG RAM is used." newline bitfld.long 0x0 1. "TAG_RGN_B,TAG region B" "0: Region B of the TAG RAM is not used.,1: Region B of the TAG RAM is used." newline bitfld.long 0x0 0. "TAG_RGN_A,TAG region A" "0: Region A of the TAG RAM is not used.,1: Region A of the TAG RAM is used." group.long 0x210++0xB line.long 0x0 "MTM_TAG_RGN_BADR_A,MTM TAG RAM base address region A register" hexmask.long.tbyte 0x0 10.--31. 1. "A_REGION_BASE_ADR,A REGION BASE ADR value" line.long 0x4 "MTM_TAG_RGN_BADR_B,MTM TAG RAM base address region B register" hexmask.long.tbyte 0x4 10.--31. 1. "B_REGION_BASE_ADR,B REGION BASE ADR value" line.long 0x8 "MTM_TAG_RGN_BADR_C,MTM TAG RAM base address region C register" hexmask.long.tbyte 0x8 10.--31. 1. "C_REGION_BASE_ADR,C REGION BASE ADR value" rgroup.long 0x220++0xF line.long 0x0 "MTM_TAG_RGN_SZ_A,MTM TAG RAM region A size register" hexmask.long.word 0x0 0.--9. 1. "RGN_A_SIZE,RGN A size value" line.long 0x4 "MTM_TAG_RGN_SZ_B,MTM TAG RAM region B size register" hexmask.long.word 0x4 0.--9. 1. "RGN_B_SIZE,RGN B size value" line.long 0x8 "MTM_TAG_RGN_SZ_C,MTM TAG RAM size C size register" hexmask.long.word 0x8 0.--9. 1. "RGN_C_SIZE,RGN C size value" line.long 0xC "MTM_TAG_RGN_STAT,MTM TAG RAM region status register" bitfld.long 0xC 2. "RGN_C_BOUND_CROSS,RGN C bound cross" "0: Region C boundary not crossed.,1: Region C boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 1. "RGN_B_BOUND_CROSS,RGN B bound cross" "0: Region B boundary not crossed.,1: Region B boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 0. "RGN_A_BOUND_CROSS,RGN A bound cross" "0: Region A boundary not crossed.,1: Region A boundary crossed due to wrong 'PAGES'.." group.long 0x230++0x7 line.long 0x0 "MTM_TAG_ADR,MTM TAG RAM address register" bitfld.long 0x0 31. "AUTO_PROG_DONE,Auto programming done goes high when updates to tag RAM are completed by MTM. Debugger must clear this bit once set. Though this bit always provides the status of latest auto increment request even when debugger did not clear the.." "0: Auto programming is not completed.,1: Auto programming is completed." newline hexmask.long.word 0x0 10.--18. 1. "PAGES,Specifies the number of consecutive TAG RAM lines needs to be updated when Auto Increment address mode is enabled. Debugger must program PAGES field to 'required number of pages - 1'." newline hexmask.long.word 0x0 1.--9. 1. "ADDRESS_PAGE,Address page" newline bitfld.long 0x0 0. "AUTO_INCR,Auto increment" "0: Auto increment of the TAG address is disabled.,1: Auto increment of the TAG address is enabled." line.long 0x4 "MTM_TAG_DATA_CONFIG,MTM TAG RAM data configuration register" bitfld.long 0x4 17. "DATA_READ_STATUS,Data read status gives read completion status against the request set in DATA_READ bit." "0: Data read is not requested or completed.,1: Data read is completed for requested read." newline bitfld.long 0x4 16. "DATA_READ,Read control bit must be set by the debugger when it needs to read TAG RAM from the address programmed in ADDRESS_PAGE field of MTM_TAG_ADR register." "0: Read command is not set.,1: Read command is set." newline bitfld.long 0x4 5.--7. "SLICE_SIZE,Specify 3 most significant bits of every TAG RAM content line called ." "0: 8 byte,1: Filtering unit,2: 32 byte,3: 64 byte,4: 128 byte,5: 256 byte,6: 512 byte,7: 1K byte" newline hexmask.long.byte 0x4 1.--4. 1. "WORD_STROBE,WORD_STROBE bits are used to enable MTM_TAG_DATA_STROBE_W[n] registers. nth bit of WORD_STROBE corresponds to nth MTM_TAG_DATA_STROBE_W[n] register. For details refer to Section89.5.2.16: MTM TAG RAM strobe word n register.." newline bitfld.long 0x4 0. "DATA_VALID,Data valid controls write to TAG RAM" "0: TAG RAM content update is disabled.,1: TAG RAM content update is enabled." group.long 0x240++0xF line.long 0x0 "MTM_TAG_DATA_STROBE_W1,MTM TAG RAM strobe word 1 register" hexmask.long 0x0 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x4 "MTM_TAG_DATA_STROBE_W2,MTM TAG RAM strobe word 2 register" hexmask.long 0x4 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x8 "MTM_TAG_DATA_STROBE_W3,MTM TAG RAM strobe word 3 register" hexmask.long 0x8 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0xC "MTM_TAG_DATA_STROBE_W4,MTM TAG RAM strobe word 4 register" hexmask.long 0xC 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." group.long 0x400++0xB line.long 0x0 "MTM_TS_EN,MTM timestamp enable register" bitfld.long 0x0 0. "TS_EN,Timestamp enable" "0: TS packet generation disabled.,1: TS packet generation enabled." line.long 0x4 "MTM_TS_WIN_CNT,MTM Timestamp window counter register" hexmask.long 0x4 0.--31. 1. "WIND_COUNTER,Timestamp window counter value" line.long 0x8 "MTM_TS_CLK_SCL,MTM Timestamp clock scaler register" hexmask.long.word 0x8 0.--8. 1. "CLK_SCALER,Clock scaler value" group.long 0x410++0xB line.long 0x0 "AL_EN,Alignment message enable register" bitfld.long 0x0 0. "AL_EN,Alignment Synchronization (A-Sync) enable" "0: A-Sync packet generation disabled.,1: A-Sync packet generation enabled." line.long 0x4 "AL_WIN_CNT,Alignment message window counter register" hexmask.long 0x4 0.--31. 1. "AL_WIND_COUNTER,Alignment synchronization messages window counter value" line.long 0x8 "AL_CLK_SCL,Alignment window counter clock scaler register" hexmask.long.word 0x8 0.--8. 1. "AL_CLK_SCALER,Clock scaler value" group.long 0xFA0++0x7 line.long 0x0 "MTM_CLAIM_TAG_SET,MTM claim TAG set register" hexmask.long.byte 0x0 0.--3. 1. "CLAIM_SET,Claim set" line.long 0x4 "MTM_CLAIM_TAG_CLR,MTM claim TAG clear register" hexmask.long.byte 0x4 0.--3. 1. "CLAIM_CLEAR,Claim clear" wgroup.long 0xFB0++0x3 line.long 0x0 "MTM_LAR,MTM lock access register" hexmask.long 0x0 0.--31. 1. "SW_KEY,Software lock key value" rgroup.long 0xFB4++0xB line.long 0x0 "MTM_LSR,MTM lock status register" bitfld.long 0x0 2. "NTT,nTT" "0: Only value: MTM_LAR register is 32 bit wide (MTM..,?" newline bitfld.long 0x0 1. "SLK,SLK returns the software lock status." "0: Accesses permitted.,1: Write accesses to control registers of the MTM.." newline bitfld.long 0x0 0. "SLI,Software Lock Implementation" "0: Software lock is not implemented: returned for..,1: Software lock is implemented: returned for all.." line.long 0x4 "MTM_AUTH_STAT,MTM authentification status register" bitfld.long 0x4 6.--7. "SNID,Secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 4.--5. "SID,Secure invasive debug" "0: Functionality not implemented.,?,?,?" newline bitfld.long 0x4 2.--3. "NSNID,Non-secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 0.--1. "NSID,Non-secure invasive debug" "0: Functionality not implemented.,?,?,?" line.long 0x8 "MTM_DEV_ARCH,MTM device architecture register" hexmask.long.word 0x8 21.--31. 1. "ARCHITECT,Defines the Architect of the component:" newline bitfld.long 0x8 20. "PRES,Presence" "?,1: Device Architecture register is present." newline hexmask.long.byte 0x8 16.--19. 1. "ARCH_REVISION,Architecture revision" newline hexmask.long.word 0x8 0.--15. 1. "ARCH_ID,Architecture ID" rgroup.long 0xFC8++0x37 line.long 0x0 "MTM_DEV_ID,MTM device ID register" hexmask.long 0x0 0.--31. 1. "FUTURE_USE,Reserved" line.long 0x4 "MTM_DEV_TYPE,MTM device type register" hexmask.long.byte 0x4 4.--7. 1. "SUB,Based on ARM©defined codes (refer to Table B2-8 in document [5])." newline hexmask.long.byte 0x4 0.--3. 1. "MAJOR,Based on ARM©defined codes (refer to Table B2-8 in document [5])." line.long 0x8 "MTM_PID4,MTM peripheral ID4 register" bitfld.long 0x8 2.--3. "SIZE,Size" "0: MTM memory map occupies 4KB.,?,?,?" newline bitfld.long 0x8 0.--1. "DES_2,DES_2" "0: ST JEP106 continuation code (refer to the..,?,?,?" line.long 0xC "MTM_PID5,MTM peripheral ID5 register" hexmask.long 0xC 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x10 "MTM_PID6,MTM peripheral ID6 register" hexmask.long 0x10 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x14 "MTM_PID7,MTM peripheral ID7 register" hexmask.long 0x14 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x18 "MTM_PID0,MTM peripheral ID0 register" hexmask.long.byte 0x18 4.--7. 1. "PART_0M,Part 0M" newline hexmask.long.byte 0x18 0.--3. 1. "PART_0L,Part 0L" line.long 0x1C "MTM_PID1,MTM peripheral ID1 register" hexmask.long.byte 0x1C 4.--7. 1. "DES_0,DES 0" newline hexmask.long.byte 0x1C 0.--3. 1. "PART_1,Part 1" line.long 0x20 "MTM_PID2,MTM peripheral ID2 register" hexmask.long.byte 0x20 4.--7. 1. "REVISION,Revision" newline bitfld.long 0x20 3. "JEDEC,JEDEC" "?,1: Indicates that a JEDEC assigned value is used." newline bitfld.long 0x20 0.--2. "DES_1,DES 1" "?,?,2: ST JEP106 identification code [7] bits[6:4].,?,?,?,?,?" line.long 0x24 "MTM_PID3,MTM peripheral ID3 register" hexmask.long.byte 0x24 4.--7. 1. "REVAND,REVAND" newline hexmask.long.byte 0x24 0.--3. 1. "CMOD,CMOD" line.long 0x28 "MTM_CID0,MTM CS ID0 register" hexmask.long.byte 0x28 0.--7. 1. "PRMB0,Preamble 0" line.long 0x2C "MTM_CID1,MTM CS ID1 register" hexmask.long.byte 0x2C 4.--7. 1. "CLASS,Class" newline hexmask.long.byte 0x2C 0.--3. 1. "PRMB1,Preamble 1" line.long 0x30 "MTM_CID2,MTM CS ID2 register" hexmask.long.byte 0x30 0.--7. 1. "PRMB2,Preamble 2" line.long 0x34 "MTM_CID3,MTM CS ID3 register" hexmask.long.byte 0x34 0.--7. 1. "PRMB3,Preamble 3" tree.end tree "CLUSTER0_MTM_PRCTL1" base ad:0x7E00C000 group.long 0x0++0x7 line.long 0x0 "MTM_EN,MTM enable register" bitfld.long 0x0 0. "MTM_ENABLE,MTM enable" "0: MTM disabled,1: MTM enabled" line.long 0x4 "MTM_TRC_EN,MTM trace enable" bitfld.long 0x4 1. "INVLD_FIFO,Invalidate FIFO" "0: Packet FIFO pointers is not invalidated old..,1: Invalidate Packet FIFO old trace data is lost." newline bitfld.long 0x4 0. "TRACE_EN,Trace Enable" "0: Trace filtering is disabled. When disabled TAG..,1: Trace filtering is enabled." group.long 0x20++0x7 line.long 0x0 "MTM_TRC_STALL_CTRL,MTM trace stall control register" hexmask.long.byte 0x0 1.--4. 1. "LEVEL,Level" newline bitfld.long 0x0 0. "STALL,Stall" "0: Backpressure form MTM does not stall the..,1: Backpressure form MTM can stall the processor or.." line.long 0x4 "MTM_TRC_ID,MTM trace ID register" hexmask.long.byte 0x4 0.--6. 1. "TRACE_ID,Trace ID value" rgroup.long 0x100++0x3 line.long 0x0 "MTM_BKP_STAT,MTM Backpressure status register" bitfld.long 0x0 1. "PCK_FIFO_FULL,Packet FIFO full" "0: Packet FIFO buffer not full.,1: Packet FIFO buffer full Backpressure scenario is.." group.long 0x200++0x3 line.long 0x0 "MTM_TAG_RGN_CONFIG,MTM TAG RAM configuration register" bitfld.long 0x0 2. "TAG_RGN_C,TAG region C" "0: Region C of the TAG RAM is not used.,1: Region C of the TAG RAM is used." newline bitfld.long 0x0 1. "TAG_RGN_B,TAG region B" "0: Region B of the TAG RAM is not used.,1: Region B of the TAG RAM is used." newline bitfld.long 0x0 0. "TAG_RGN_A,TAG region A" "0: Region A of the TAG RAM is not used.,1: Region A of the TAG RAM is used." group.long 0x210++0xB line.long 0x0 "MTM_TAG_RGN_BADR_A,MTM TAG RAM base address region A register" hexmask.long.tbyte 0x0 10.--31. 1. "A_REGION_BASE_ADR,A REGION BASE ADR value" line.long 0x4 "MTM_TAG_RGN_BADR_B,MTM TAG RAM base address region B register" hexmask.long.tbyte 0x4 10.--31. 1. "B_REGION_BASE_ADR,B REGION BASE ADR value" line.long 0x8 "MTM_TAG_RGN_BADR_C,MTM TAG RAM base address region C register" hexmask.long.tbyte 0x8 10.--31. 1. "C_REGION_BASE_ADR,C REGION BASE ADR value" rgroup.long 0x220++0xF line.long 0x0 "MTM_TAG_RGN_SZ_A,MTM TAG RAM region A size register" hexmask.long.word 0x0 0.--9. 1. "RGN_A_SIZE,RGN A size value" line.long 0x4 "MTM_TAG_RGN_SZ_B,MTM TAG RAM region B size register" hexmask.long.word 0x4 0.--9. 1. "RGN_B_SIZE,RGN B size value" line.long 0x8 "MTM_TAG_RGN_SZ_C,MTM TAG RAM size C size register" hexmask.long.word 0x8 0.--9. 1. "RGN_C_SIZE,RGN C size value" line.long 0xC "MTM_TAG_RGN_STAT,MTM TAG RAM region status register" bitfld.long 0xC 2. "RGN_C_BOUND_CROSS,RGN C bound cross" "0: Region C boundary not crossed.,1: Region C boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 1. "RGN_B_BOUND_CROSS,RGN B bound cross" "0: Region B boundary not crossed.,1: Region B boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 0. "RGN_A_BOUND_CROSS,RGN A bound cross" "0: Region A boundary not crossed.,1: Region A boundary crossed due to wrong 'PAGES'.." group.long 0x230++0x7 line.long 0x0 "MTM_TAG_ADR,MTM TAG RAM address register" bitfld.long 0x0 31. "AUTO_PROG_DONE,Auto programming done goes high when updates to tag RAM are completed by MTM. Debugger must clear this bit once set. Though this bit always provides the status of latest auto increment request even when debugger did not clear the.." "0: Auto programming is not completed.,1: Auto programming is completed." newline hexmask.long.word 0x0 10.--18. 1. "PAGES,Specifies the number of consecutive TAG RAM lines needs to be updated when Auto Increment address mode is enabled. Debugger must program PAGES field to 'required number of pages - 1'." newline hexmask.long.word 0x0 1.--9. 1. "ADDRESS_PAGE,Address page" newline bitfld.long 0x0 0. "AUTO_INCR,Auto increment" "0: Auto increment of the TAG address is disabled.,1: Auto increment of the TAG address is enabled." line.long 0x4 "MTM_TAG_DATA_CONFIG,MTM TAG RAM data configuration register" bitfld.long 0x4 17. "DATA_READ_STATUS,Data read status gives read completion status against the request set in DATA_READ bit." "0: Data read is not requested or completed.,1: Data read is completed for requested read." newline bitfld.long 0x4 16. "DATA_READ,Read control bit must be set by the debugger when it needs to read TAG RAM from the address programmed in ADDRESS_PAGE field of MTM_TAG_ADR register." "0: Read command is not set.,1: Read command is set." newline bitfld.long 0x4 5.--7. "SLICE_SIZE,Specify 3 most significant bits of every TAG RAM content line called ." "0: 8 byte,1: Filtering unit,2: 32 byte,3: 64 byte,4: 128 byte,5: 256 byte,6: 512 byte,7: 1K byte" newline hexmask.long.byte 0x4 1.--4. 1. "WORD_STROBE,WORD_STROBE bits are used to enable MTM_TAG_DATA_STROBE_W[n] registers. nth bit of WORD_STROBE corresponds to nth MTM_TAG_DATA_STROBE_W[n] register. For details refer to Section89.5.2.16: MTM TAG RAM strobe word n register.." newline bitfld.long 0x4 0. "DATA_VALID,Data valid controls write to TAG RAM" "0: TAG RAM content update is disabled.,1: TAG RAM content update is enabled." group.long 0x240++0xF line.long 0x0 "MTM_TAG_DATA_STROBE_W1,MTM TAG RAM strobe word 1 register" hexmask.long 0x0 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x4 "MTM_TAG_DATA_STROBE_W2,MTM TAG RAM strobe word 2 register" hexmask.long 0x4 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x8 "MTM_TAG_DATA_STROBE_W3,MTM TAG RAM strobe word 3 register" hexmask.long 0x8 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0xC "MTM_TAG_DATA_STROBE_W4,MTM TAG RAM strobe word 4 register" hexmask.long 0xC 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." group.long 0x400++0xB line.long 0x0 "MTM_TS_EN,MTM timestamp enable register" bitfld.long 0x0 0. "TS_EN,Timestamp enable" "0: TS packet generation disabled.,1: TS packet generation enabled." line.long 0x4 "MTM_TS_WIN_CNT,MTM Timestamp window counter register" hexmask.long 0x4 0.--31. 1. "WIND_COUNTER,Timestamp window counter value" line.long 0x8 "MTM_TS_CLK_SCL,MTM Timestamp clock scaler register" hexmask.long.word 0x8 0.--8. 1. "CLK_SCALER,Clock scaler value" group.long 0x410++0xB line.long 0x0 "AL_EN,Alignment message enable register" bitfld.long 0x0 0. "AL_EN,Alignment Synchronization (A-Sync) enable" "0: A-Sync packet generation disabled.,1: A-Sync packet generation enabled." line.long 0x4 "AL_WIN_CNT,Alignment message window counter register" hexmask.long 0x4 0.--31. 1. "AL_WIND_COUNTER,Alignment synchronization messages window counter value" line.long 0x8 "AL_CLK_SCL,Alignment window counter clock scaler register" hexmask.long.word 0x8 0.--8. 1. "AL_CLK_SCALER,Clock scaler value" group.long 0xFA0++0x7 line.long 0x0 "MTM_CLAIM_TAG_SET,MTM claim TAG set register" hexmask.long.byte 0x0 0.--3. 1. "CLAIM_SET,Claim set" line.long 0x4 "MTM_CLAIM_TAG_CLR,MTM claim TAG clear register" hexmask.long.byte 0x4 0.--3. 1. "CLAIM_CLEAR,Claim clear" wgroup.long 0xFB0++0x3 line.long 0x0 "MTM_LAR,MTM lock access register" hexmask.long 0x0 0.--31. 1. "SW_KEY,Software lock key value" rgroup.long 0xFB4++0xB line.long 0x0 "MTM_LSR,MTM lock status register" bitfld.long 0x0 2. "NTT,nTT" "0: Only value: MTM_LAR register is 32 bit wide (MTM..,?" newline bitfld.long 0x0 1. "SLK,SLK returns the software lock status." "0: Accesses permitted.,1: Write accesses to control registers of the MTM.." newline bitfld.long 0x0 0. "SLI,Software Lock Implementation" "0: Software lock is not implemented: returned for..,1: Software lock is implemented: returned for all.." line.long 0x4 "MTM_AUTH_STAT,MTM authentification status register" bitfld.long 0x4 6.--7. "SNID,Secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 4.--5. "SID,Secure invasive debug" "0: Functionality not implemented.,?,?,?" newline bitfld.long 0x4 2.--3. "NSNID,Non-secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 0.--1. "NSID,Non-secure invasive debug" "0: Functionality not implemented.,?,?,?" line.long 0x8 "MTM_DEV_ARCH,MTM device architecture register" hexmask.long.word 0x8 21.--31. 1. "ARCHITECT,Defines the Architect of the component:" newline bitfld.long 0x8 20. "PRES,Presence" "?,1: Device Architecture register is present." newline hexmask.long.byte 0x8 16.--19. 1. "ARCH_REVISION,Architecture revision" newline hexmask.long.word 0x8 0.--15. 1. "ARCH_ID,Architecture ID" rgroup.long 0xFC8++0x37 line.long 0x0 "MTM_DEV_ID,MTM device ID register" hexmask.long 0x0 0.--31. 1. "FUTURE_USE,Reserved" line.long 0x4 "MTM_DEV_TYPE,MTM device type register" hexmask.long.byte 0x4 4.--7. 1. "SUB,Based on ARM©defined codes (refer to Table B2-8 in document [5])." newline hexmask.long.byte 0x4 0.--3. 1. "MAJOR,Based on ARM©defined codes (refer to Table B2-8 in document [5])." line.long 0x8 "MTM_PID4,MTM peripheral ID4 register" bitfld.long 0x8 2.--3. "SIZE,Size" "0: MTM memory map occupies 4KB.,?,?,?" newline bitfld.long 0x8 0.--1. "DES_2,DES_2" "0: ST JEP106 continuation code (refer to the..,?,?,?" line.long 0xC "MTM_PID5,MTM peripheral ID5 register" hexmask.long 0xC 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x10 "MTM_PID6,MTM peripheral ID6 register" hexmask.long 0x10 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x14 "MTM_PID7,MTM peripheral ID7 register" hexmask.long 0x14 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x18 "MTM_PID0,MTM peripheral ID0 register" hexmask.long.byte 0x18 4.--7. 1. "PART_0M,Part 0M" newline hexmask.long.byte 0x18 0.--3. 1. "PART_0L,Part 0L" line.long 0x1C "MTM_PID1,MTM peripheral ID1 register" hexmask.long.byte 0x1C 4.--7. 1. "DES_0,DES 0" newline hexmask.long.byte 0x1C 0.--3. 1. "PART_1,Part 1" line.long 0x20 "MTM_PID2,MTM peripheral ID2 register" hexmask.long.byte 0x20 4.--7. 1. "REVISION,Revision" newline bitfld.long 0x20 3. "JEDEC,JEDEC" "?,1: Indicates that a JEDEC assigned value is used." newline bitfld.long 0x20 0.--2. "DES_1,DES 1" "?,?,2: ST JEP106 identification code [7] bits[6:4].,?,?,?,?,?" line.long 0x24 "MTM_PID3,MTM peripheral ID3 register" hexmask.long.byte 0x24 4.--7. 1. "REVAND,REVAND" newline hexmask.long.byte 0x24 0.--3. 1. "CMOD,CMOD" line.long 0x28 "MTM_CID0,MTM CS ID0 register" hexmask.long.byte 0x28 0.--7. 1. "PRMB0,Preamble 0" line.long 0x2C "MTM_CID1,MTM CS ID1 register" hexmask.long.byte 0x2C 4.--7. 1. "CLASS,Class" newline hexmask.long.byte 0x2C 0.--3. 1. "PRMB1,Preamble 1" line.long 0x30 "MTM_CID2,MTM CS ID2 register" hexmask.long.byte 0x30 0.--7. 1. "PRMB2,Preamble 2" line.long 0x34 "MTM_CID3,MTM CS ID3 register" hexmask.long.byte 0x34 0.--7. 1. "PRMB3,Preamble 3" tree.end tree "CLUSTER1_MTM_CORE0" base ad:0x7E014000 group.long 0x0++0x7 line.long 0x0 "MTM_EN,MTM enable register" bitfld.long 0x0 0. "MTM_ENABLE,MTM enable" "0: MTM disabled,1: MTM enabled" line.long 0x4 "MTM_TRC_EN,MTM trace enable" bitfld.long 0x4 1. "INVLD_FIFO,Invalidate FIFO" "0: Packet FIFO pointers is not invalidated old..,1: Invalidate Packet FIFO old trace data is lost." newline bitfld.long 0x4 0. "TRACE_EN,Trace Enable" "0: Trace filtering is disabled. When disabled TAG..,1: Trace filtering is enabled." group.long 0x20++0x7 line.long 0x0 "MTM_TRC_STALL_CTRL,MTM trace stall control register" hexmask.long.byte 0x0 1.--4. 1. "LEVEL,Level" newline bitfld.long 0x0 0. "STALL,Stall" "0: Backpressure form MTM does not stall the..,1: Backpressure form MTM can stall the processor or.." line.long 0x4 "MTM_TRC_ID,MTM trace ID register" hexmask.long.byte 0x4 0.--6. 1. "TRACE_ID,Trace ID value" rgroup.long 0x100++0x3 line.long 0x0 "MTM_BKP_STAT,MTM Backpressure status register" bitfld.long 0x0 1. "PCK_FIFO_FULL,Packet FIFO full" "0: Packet FIFO buffer not full.,1: Packet FIFO buffer full Backpressure scenario is.." group.long 0x200++0x3 line.long 0x0 "MTM_TAG_RGN_CONFIG,MTM TAG RAM configuration register" bitfld.long 0x0 2. "TAG_RGN_C,TAG region C" "0: Region C of the TAG RAM is not used.,1: Region C of the TAG RAM is used." newline bitfld.long 0x0 1. "TAG_RGN_B,TAG region B" "0: Region B of the TAG RAM is not used.,1: Region B of the TAG RAM is used." newline bitfld.long 0x0 0. "TAG_RGN_A,TAG region A" "0: Region A of the TAG RAM is not used.,1: Region A of the TAG RAM is used." group.long 0x210++0xB line.long 0x0 "MTM_TAG_RGN_BADR_A,MTM TAG RAM base address region A register" hexmask.long.tbyte 0x0 10.--31. 1. "A_REGION_BASE_ADR,A REGION BASE ADR value" line.long 0x4 "MTM_TAG_RGN_BADR_B,MTM TAG RAM base address region B register" hexmask.long.tbyte 0x4 10.--31. 1. "B_REGION_BASE_ADR,B REGION BASE ADR value" line.long 0x8 "MTM_TAG_RGN_BADR_C,MTM TAG RAM base address region C register" hexmask.long.tbyte 0x8 10.--31. 1. "C_REGION_BASE_ADR,C REGION BASE ADR value" rgroup.long 0x220++0xF line.long 0x0 "MTM_TAG_RGN_SZ_A,MTM TAG RAM region A size register" hexmask.long.word 0x0 0.--9. 1. "RGN_A_SIZE,RGN A size value" line.long 0x4 "MTM_TAG_RGN_SZ_B,MTM TAG RAM region B size register" hexmask.long.word 0x4 0.--9. 1. "RGN_B_SIZE,RGN B size value" line.long 0x8 "MTM_TAG_RGN_SZ_C,MTM TAG RAM size C size register" hexmask.long.word 0x8 0.--9. 1. "RGN_C_SIZE,RGN C size value" line.long 0xC "MTM_TAG_RGN_STAT,MTM TAG RAM region status register" bitfld.long 0xC 2. "RGN_C_BOUND_CROSS,RGN C bound cross" "0: Region C boundary not crossed.,1: Region C boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 1. "RGN_B_BOUND_CROSS,RGN B bound cross" "0: Region B boundary not crossed.,1: Region B boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 0. "RGN_A_BOUND_CROSS,RGN A bound cross" "0: Region A boundary not crossed.,1: Region A boundary crossed due to wrong 'PAGES'.." group.long 0x230++0x7 line.long 0x0 "MTM_TAG_ADR,MTM TAG RAM address register" bitfld.long 0x0 31. "AUTO_PROG_DONE,Auto programming done goes high when updates to tag RAM are completed by MTM. Debugger must clear this bit once set. Though this bit always provides the status of latest auto increment request even when debugger did not clear the.." "0: Auto programming is not completed.,1: Auto programming is completed." newline hexmask.long.word 0x0 10.--18. 1. "PAGES,Specifies the number of consecutive TAG RAM lines needs to be updated when Auto Increment address mode is enabled. Debugger must program PAGES field to 'required number of pages - 1'." newline hexmask.long.word 0x0 1.--9. 1. "ADDRESS_PAGE,Address page" newline bitfld.long 0x0 0. "AUTO_INCR,Auto increment" "0: Auto increment of the TAG address is disabled.,1: Auto increment of the TAG address is enabled." line.long 0x4 "MTM_TAG_DATA_CONFIG,MTM TAG RAM data configuration register" bitfld.long 0x4 17. "DATA_READ_STATUS,Data read status gives read completion status against the request set in DATA_READ bit." "0: Data read is not requested or completed.,1: Data read is completed for requested read." newline bitfld.long 0x4 16. "DATA_READ,Read control bit must be set by the debugger when it needs to read TAG RAM from the address programmed in ADDRESS_PAGE field of MTM_TAG_ADR register." "0: Read command is not set.,1: Read command is set." newline bitfld.long 0x4 5.--7. "SLICE_SIZE,Specify 3 most significant bits of every TAG RAM content line called ." "0: 8 byte,1: Filtering unit,2: 32 byte,3: 64 byte,4: 128 byte,5: 256 byte,6: 512 byte,7: 1K byte" newline hexmask.long.byte 0x4 1.--4. 1. "WORD_STROBE,WORD_STROBE bits are used to enable MTM_TAG_DATA_STROBE_W[n] registers. nth bit of WORD_STROBE corresponds to nth MTM_TAG_DATA_STROBE_W[n] register. For details refer to Section89.5.2.16: MTM TAG RAM strobe word n register.." newline bitfld.long 0x4 0. "DATA_VALID,Data valid controls write to TAG RAM" "0: TAG RAM content update is disabled.,1: TAG RAM content update is enabled." group.long 0x240++0xF line.long 0x0 "MTM_TAG_DATA_STROBE_W1,MTM TAG RAM strobe word 1 register" hexmask.long 0x0 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x4 "MTM_TAG_DATA_STROBE_W2,MTM TAG RAM strobe word 2 register" hexmask.long 0x4 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x8 "MTM_TAG_DATA_STROBE_W3,MTM TAG RAM strobe word 3 register" hexmask.long 0x8 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0xC "MTM_TAG_DATA_STROBE_W4,MTM TAG RAM strobe word 4 register" hexmask.long 0xC 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." group.long 0x400++0xB line.long 0x0 "MTM_TS_EN,MTM timestamp enable register" bitfld.long 0x0 0. "TS_EN,Timestamp enable" "0: TS packet generation disabled.,1: TS packet generation enabled." line.long 0x4 "MTM_TS_WIN_CNT,MTM Timestamp window counter register" hexmask.long 0x4 0.--31. 1. "WIND_COUNTER,Timestamp window counter value" line.long 0x8 "MTM_TS_CLK_SCL,MTM Timestamp clock scaler register" hexmask.long.word 0x8 0.--8. 1. "CLK_SCALER,Clock scaler value" group.long 0x410++0xB line.long 0x0 "AL_EN,Alignment message enable register" bitfld.long 0x0 0. "AL_EN,Alignment Synchronization (A-Sync) enable" "0: A-Sync packet generation disabled.,1: A-Sync packet generation enabled." line.long 0x4 "AL_WIN_CNT,Alignment message window counter register" hexmask.long 0x4 0.--31. 1. "AL_WIND_COUNTER,Alignment synchronization messages window counter value" line.long 0x8 "AL_CLK_SCL,Alignment window counter clock scaler register" hexmask.long.word 0x8 0.--8. 1. "AL_CLK_SCALER,Clock scaler value" group.long 0xFA0++0x7 line.long 0x0 "MTM_CLAIM_TAG_SET,MTM claim TAG set register" hexmask.long.byte 0x0 0.--3. 1. "CLAIM_SET,Claim set" line.long 0x4 "MTM_CLAIM_TAG_CLR,MTM claim TAG clear register" hexmask.long.byte 0x4 0.--3. 1. "CLAIM_CLEAR,Claim clear" wgroup.long 0xFB0++0x3 line.long 0x0 "MTM_LAR,MTM lock access register" hexmask.long 0x0 0.--31. 1. "SW_KEY,Software lock key value" rgroup.long 0xFB4++0xB line.long 0x0 "MTM_LSR,MTM lock status register" bitfld.long 0x0 2. "NTT,nTT" "0: Only value: MTM_LAR register is 32 bit wide (MTM..,?" newline bitfld.long 0x0 1. "SLK,SLK returns the software lock status." "0: Accesses permitted.,1: Write accesses to control registers of the MTM.." newline bitfld.long 0x0 0. "SLI,Software Lock Implementation" "0: Software lock is not implemented: returned for..,1: Software lock is implemented: returned for all.." line.long 0x4 "MTM_AUTH_STAT,MTM authentification status register" bitfld.long 0x4 6.--7. "SNID,Secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 4.--5. "SID,Secure invasive debug" "0: Functionality not implemented.,?,?,?" newline bitfld.long 0x4 2.--3. "NSNID,Non-secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 0.--1. "NSID,Non-secure invasive debug" "0: Functionality not implemented.,?,?,?" line.long 0x8 "MTM_DEV_ARCH,MTM device architecture register" hexmask.long.word 0x8 21.--31. 1. "ARCHITECT,Defines the Architect of the component:" newline bitfld.long 0x8 20. "PRES,Presence" "?,1: Device Architecture register is present." newline hexmask.long.byte 0x8 16.--19. 1. "ARCH_REVISION,Architecture revision" newline hexmask.long.word 0x8 0.--15. 1. "ARCH_ID,Architecture ID" rgroup.long 0xFC8++0x37 line.long 0x0 "MTM_DEV_ID,MTM device ID register" hexmask.long 0x0 0.--31. 1. "FUTURE_USE,Reserved" line.long 0x4 "MTM_DEV_TYPE,MTM device type register" hexmask.long.byte 0x4 4.--7. 1. "SUB,Based on ARM©defined codes (refer to Table B2-8 in document [5])." newline hexmask.long.byte 0x4 0.--3. 1. "MAJOR,Based on ARM©defined codes (refer to Table B2-8 in document [5])." line.long 0x8 "MTM_PID4,MTM peripheral ID4 register" bitfld.long 0x8 2.--3. "SIZE,Size" "0: MTM memory map occupies 4KB.,?,?,?" newline bitfld.long 0x8 0.--1. "DES_2,DES_2" "0: ST JEP106 continuation code (refer to the..,?,?,?" line.long 0xC "MTM_PID5,MTM peripheral ID5 register" hexmask.long 0xC 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x10 "MTM_PID6,MTM peripheral ID6 register" hexmask.long 0x10 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x14 "MTM_PID7,MTM peripheral ID7 register" hexmask.long 0x14 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x18 "MTM_PID0,MTM peripheral ID0 register" hexmask.long.byte 0x18 4.--7. 1. "PART_0M,Part 0M" newline hexmask.long.byte 0x18 0.--3. 1. "PART_0L,Part 0L" line.long 0x1C "MTM_PID1,MTM peripheral ID1 register" hexmask.long.byte 0x1C 4.--7. 1. "DES_0,DES 0" newline hexmask.long.byte 0x1C 0.--3. 1. "PART_1,Part 1" line.long 0x20 "MTM_PID2,MTM peripheral ID2 register" hexmask.long.byte 0x20 4.--7. 1. "REVISION,Revision" newline bitfld.long 0x20 3. "JEDEC,JEDEC" "?,1: Indicates that a JEDEC assigned value is used." newline bitfld.long 0x20 0.--2. "DES_1,DES 1" "?,?,2: ST JEP106 identification code [7] bits[6:4].,?,?,?,?,?" line.long 0x24 "MTM_PID3,MTM peripheral ID3 register" hexmask.long.byte 0x24 4.--7. 1. "REVAND,REVAND" newline hexmask.long.byte 0x24 0.--3. 1. "CMOD,CMOD" line.long 0x28 "MTM_CID0,MTM CS ID0 register" hexmask.long.byte 0x28 0.--7. 1. "PRMB0,Preamble 0" line.long 0x2C "MTM_CID1,MTM CS ID1 register" hexmask.long.byte 0x2C 4.--7. 1. "CLASS,Class" newline hexmask.long.byte 0x2C 0.--3. 1. "PRMB1,Preamble 1" line.long 0x30 "MTM_CID2,MTM CS ID2 register" hexmask.long.byte 0x30 0.--7. 1. "PRMB2,Preamble 2" line.long 0x34 "MTM_CID3,MTM CS ID3 register" hexmask.long.byte 0x34 0.--7. 1. "PRMB3,Preamble 3" tree.end tree "CLUSTER1_MTM_CORE1" base ad:0x7E016000 group.long 0x0++0x7 line.long 0x0 "MTM_EN,MTM enable register" bitfld.long 0x0 0. "MTM_ENABLE,MTM enable" "0: MTM disabled,1: MTM enabled" line.long 0x4 "MTM_TRC_EN,MTM trace enable" bitfld.long 0x4 1. "INVLD_FIFO,Invalidate FIFO" "0: Packet FIFO pointers is not invalidated old..,1: Invalidate Packet FIFO old trace data is lost." newline bitfld.long 0x4 0. "TRACE_EN,Trace Enable" "0: Trace filtering is disabled. When disabled TAG..,1: Trace filtering is enabled." group.long 0x20++0x7 line.long 0x0 "MTM_TRC_STALL_CTRL,MTM trace stall control register" hexmask.long.byte 0x0 1.--4. 1. "LEVEL,Level" newline bitfld.long 0x0 0. "STALL,Stall" "0: Backpressure form MTM does not stall the..,1: Backpressure form MTM can stall the processor or.." line.long 0x4 "MTM_TRC_ID,MTM trace ID register" hexmask.long.byte 0x4 0.--6. 1. "TRACE_ID,Trace ID value" rgroup.long 0x100++0x3 line.long 0x0 "MTM_BKP_STAT,MTM Backpressure status register" bitfld.long 0x0 1. "PCK_FIFO_FULL,Packet FIFO full" "0: Packet FIFO buffer not full.,1: Packet FIFO buffer full Backpressure scenario is.." group.long 0x200++0x3 line.long 0x0 "MTM_TAG_RGN_CONFIG,MTM TAG RAM configuration register" bitfld.long 0x0 2. "TAG_RGN_C,TAG region C" "0: Region C of the TAG RAM is not used.,1: Region C of the TAG RAM is used." newline bitfld.long 0x0 1. "TAG_RGN_B,TAG region B" "0: Region B of the TAG RAM is not used.,1: Region B of the TAG RAM is used." newline bitfld.long 0x0 0. "TAG_RGN_A,TAG region A" "0: Region A of the TAG RAM is not used.,1: Region A of the TAG RAM is used." group.long 0x210++0xB line.long 0x0 "MTM_TAG_RGN_BADR_A,MTM TAG RAM base address region A register" hexmask.long.tbyte 0x0 10.--31. 1. "A_REGION_BASE_ADR,A REGION BASE ADR value" line.long 0x4 "MTM_TAG_RGN_BADR_B,MTM TAG RAM base address region B register" hexmask.long.tbyte 0x4 10.--31. 1. "B_REGION_BASE_ADR,B REGION BASE ADR value" line.long 0x8 "MTM_TAG_RGN_BADR_C,MTM TAG RAM base address region C register" hexmask.long.tbyte 0x8 10.--31. 1. "C_REGION_BASE_ADR,C REGION BASE ADR value" rgroup.long 0x220++0xF line.long 0x0 "MTM_TAG_RGN_SZ_A,MTM TAG RAM region A size register" hexmask.long.word 0x0 0.--9. 1. "RGN_A_SIZE,RGN A size value" line.long 0x4 "MTM_TAG_RGN_SZ_B,MTM TAG RAM region B size register" hexmask.long.word 0x4 0.--9. 1. "RGN_B_SIZE,RGN B size value" line.long 0x8 "MTM_TAG_RGN_SZ_C,MTM TAG RAM size C size register" hexmask.long.word 0x8 0.--9. 1. "RGN_C_SIZE,RGN C size value" line.long 0xC "MTM_TAG_RGN_STAT,MTM TAG RAM region status register" bitfld.long 0xC 2. "RGN_C_BOUND_CROSS,RGN C bound cross" "0: Region C boundary not crossed.,1: Region C boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 1. "RGN_B_BOUND_CROSS,RGN B bound cross" "0: Region B boundary not crossed.,1: Region B boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 0. "RGN_A_BOUND_CROSS,RGN A bound cross" "0: Region A boundary not crossed.,1: Region A boundary crossed due to wrong 'PAGES'.." group.long 0x230++0x7 line.long 0x0 "MTM_TAG_ADR,MTM TAG RAM address register" bitfld.long 0x0 31. "AUTO_PROG_DONE,Auto programming done goes high when updates to tag RAM are completed by MTM. Debugger must clear this bit once set. Though this bit always provides the status of latest auto increment request even when debugger did not clear the.." "0: Auto programming is not completed.,1: Auto programming is completed." newline hexmask.long.word 0x0 10.--18. 1. "PAGES,Specifies the number of consecutive TAG RAM lines needs to be updated when Auto Increment address mode is enabled. Debugger must program PAGES field to 'required number of pages - 1'." newline hexmask.long.word 0x0 1.--9. 1. "ADDRESS_PAGE,Address page" newline bitfld.long 0x0 0. "AUTO_INCR,Auto increment" "0: Auto increment of the TAG address is disabled.,1: Auto increment of the TAG address is enabled." line.long 0x4 "MTM_TAG_DATA_CONFIG,MTM TAG RAM data configuration register" bitfld.long 0x4 17. "DATA_READ_STATUS,Data read status gives read completion status against the request set in DATA_READ bit." "0: Data read is not requested or completed.,1: Data read is completed for requested read." newline bitfld.long 0x4 16. "DATA_READ,Read control bit must be set by the debugger when it needs to read TAG RAM from the address programmed in ADDRESS_PAGE field of MTM_TAG_ADR register." "0: Read command is not set.,1: Read command is set." newline bitfld.long 0x4 5.--7. "SLICE_SIZE,Specify 3 most significant bits of every TAG RAM content line called ." "0: 8 byte,1: Filtering unit,2: 32 byte,3: 64 byte,4: 128 byte,5: 256 byte,6: 512 byte,7: 1K byte" newline hexmask.long.byte 0x4 1.--4. 1. "WORD_STROBE,WORD_STROBE bits are used to enable MTM_TAG_DATA_STROBE_W[n] registers. nth bit of WORD_STROBE corresponds to nth MTM_TAG_DATA_STROBE_W[n] register. For details refer to Section89.5.2.16: MTM TAG RAM strobe word n register.." newline bitfld.long 0x4 0. "DATA_VALID,Data valid controls write to TAG RAM" "0: TAG RAM content update is disabled.,1: TAG RAM content update is enabled." group.long 0x240++0xF line.long 0x0 "MTM_TAG_DATA_STROBE_W1,MTM TAG RAM strobe word 1 register" hexmask.long 0x0 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x4 "MTM_TAG_DATA_STROBE_W2,MTM TAG RAM strobe word 2 register" hexmask.long 0x4 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x8 "MTM_TAG_DATA_STROBE_W3,MTM TAG RAM strobe word 3 register" hexmask.long 0x8 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0xC "MTM_TAG_DATA_STROBE_W4,MTM TAG RAM strobe word 4 register" hexmask.long 0xC 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." group.long 0x400++0xB line.long 0x0 "MTM_TS_EN,MTM timestamp enable register" bitfld.long 0x0 0. "TS_EN,Timestamp enable" "0: TS packet generation disabled.,1: TS packet generation enabled." line.long 0x4 "MTM_TS_WIN_CNT,MTM Timestamp window counter register" hexmask.long 0x4 0.--31. 1. "WIND_COUNTER,Timestamp window counter value" line.long 0x8 "MTM_TS_CLK_SCL,MTM Timestamp clock scaler register" hexmask.long.word 0x8 0.--8. 1. "CLK_SCALER,Clock scaler value" group.long 0x410++0xB line.long 0x0 "AL_EN,Alignment message enable register" bitfld.long 0x0 0. "AL_EN,Alignment Synchronization (A-Sync) enable" "0: A-Sync packet generation disabled.,1: A-Sync packet generation enabled." line.long 0x4 "AL_WIN_CNT,Alignment message window counter register" hexmask.long 0x4 0.--31. 1. "AL_WIND_COUNTER,Alignment synchronization messages window counter value" line.long 0x8 "AL_CLK_SCL,Alignment window counter clock scaler register" hexmask.long.word 0x8 0.--8. 1. "AL_CLK_SCALER,Clock scaler value" group.long 0xFA0++0x7 line.long 0x0 "MTM_CLAIM_TAG_SET,MTM claim TAG set register" hexmask.long.byte 0x0 0.--3. 1. "CLAIM_SET,Claim set" line.long 0x4 "MTM_CLAIM_TAG_CLR,MTM claim TAG clear register" hexmask.long.byte 0x4 0.--3. 1. "CLAIM_CLEAR,Claim clear" wgroup.long 0xFB0++0x3 line.long 0x0 "MTM_LAR,MTM lock access register" hexmask.long 0x0 0.--31. 1. "SW_KEY,Software lock key value" rgroup.long 0xFB4++0xB line.long 0x0 "MTM_LSR,MTM lock status register" bitfld.long 0x0 2. "NTT,nTT" "0: Only value: MTM_LAR register is 32 bit wide (MTM..,?" newline bitfld.long 0x0 1. "SLK,SLK returns the software lock status." "0: Accesses permitted.,1: Write accesses to control registers of the MTM.." newline bitfld.long 0x0 0. "SLI,Software Lock Implementation" "0: Software lock is not implemented: returned for..,1: Software lock is implemented: returned for all.." line.long 0x4 "MTM_AUTH_STAT,MTM authentification status register" bitfld.long 0x4 6.--7. "SNID,Secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 4.--5. "SID,Secure invasive debug" "0: Functionality not implemented.,?,?,?" newline bitfld.long 0x4 2.--3. "NSNID,Non-secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 0.--1. "NSID,Non-secure invasive debug" "0: Functionality not implemented.,?,?,?" line.long 0x8 "MTM_DEV_ARCH,MTM device architecture register" hexmask.long.word 0x8 21.--31. 1. "ARCHITECT,Defines the Architect of the component:" newline bitfld.long 0x8 20. "PRES,Presence" "?,1: Device Architecture register is present." newline hexmask.long.byte 0x8 16.--19. 1. "ARCH_REVISION,Architecture revision" newline hexmask.long.word 0x8 0.--15. 1. "ARCH_ID,Architecture ID" rgroup.long 0xFC8++0x37 line.long 0x0 "MTM_DEV_ID,MTM device ID register" hexmask.long 0x0 0.--31. 1. "FUTURE_USE,Reserved" line.long 0x4 "MTM_DEV_TYPE,MTM device type register" hexmask.long.byte 0x4 4.--7. 1. "SUB,Based on ARM©defined codes (refer to Table B2-8 in document [5])." newline hexmask.long.byte 0x4 0.--3. 1. "MAJOR,Based on ARM©defined codes (refer to Table B2-8 in document [5])." line.long 0x8 "MTM_PID4,MTM peripheral ID4 register" bitfld.long 0x8 2.--3. "SIZE,Size" "0: MTM memory map occupies 4KB.,?,?,?" newline bitfld.long 0x8 0.--1. "DES_2,DES_2" "0: ST JEP106 continuation code (refer to the..,?,?,?" line.long 0xC "MTM_PID5,MTM peripheral ID5 register" hexmask.long 0xC 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x10 "MTM_PID6,MTM peripheral ID6 register" hexmask.long 0x10 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x14 "MTM_PID7,MTM peripheral ID7 register" hexmask.long 0x14 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x18 "MTM_PID0,MTM peripheral ID0 register" hexmask.long.byte 0x18 4.--7. 1. "PART_0M,Part 0M" newline hexmask.long.byte 0x18 0.--3. 1. "PART_0L,Part 0L" line.long 0x1C "MTM_PID1,MTM peripheral ID1 register" hexmask.long.byte 0x1C 4.--7. 1. "DES_0,DES 0" newline hexmask.long.byte 0x1C 0.--3. 1. "PART_1,Part 1" line.long 0x20 "MTM_PID2,MTM peripheral ID2 register" hexmask.long.byte 0x20 4.--7. 1. "REVISION,Revision" newline bitfld.long 0x20 3. "JEDEC,JEDEC" "?,1: Indicates that a JEDEC assigned value is used." newline bitfld.long 0x20 0.--2. "DES_1,DES 1" "?,?,2: ST JEP106 identification code [7] bits[6:4].,?,?,?,?,?" line.long 0x24 "MTM_PID3,MTM peripheral ID3 register" hexmask.long.byte 0x24 4.--7. 1. "REVAND,REVAND" newline hexmask.long.byte 0x24 0.--3. 1. "CMOD,CMOD" line.long 0x28 "MTM_CID0,MTM CS ID0 register" hexmask.long.byte 0x28 0.--7. 1. "PRMB0,Preamble 0" line.long 0x2C "MTM_CID1,MTM CS ID1 register" hexmask.long.byte 0x2C 4.--7. 1. "CLASS,Class" newline hexmask.long.byte 0x2C 0.--3. 1. "PRMB1,Preamble 1" line.long 0x30 "MTM_CID2,MTM CS ID2 register" hexmask.long.byte 0x30 0.--7. 1. "PRMB2,Preamble 2" line.long 0x34 "MTM_CID3,MTM CS ID3 register" hexmask.long.byte 0x34 0.--7. 1. "PRMB3,Preamble 3" tree.end tree "CLUSTER1_MTM_PRCTL0" base ad:0x7E018000 group.long 0x0++0x7 line.long 0x0 "MTM_EN,MTM enable register" bitfld.long 0x0 0. "MTM_ENABLE,MTM enable" "0: MTM disabled,1: MTM enabled" line.long 0x4 "MTM_TRC_EN,MTM trace enable" bitfld.long 0x4 1. "INVLD_FIFO,Invalidate FIFO" "0: Packet FIFO pointers is not invalidated old..,1: Invalidate Packet FIFO old trace data is lost." newline bitfld.long 0x4 0. "TRACE_EN,Trace Enable" "0: Trace filtering is disabled. When disabled TAG..,1: Trace filtering is enabled." group.long 0x20++0x7 line.long 0x0 "MTM_TRC_STALL_CTRL,MTM trace stall control register" hexmask.long.byte 0x0 1.--4. 1. "LEVEL,Level" newline bitfld.long 0x0 0. "STALL,Stall" "0: Backpressure form MTM does not stall the..,1: Backpressure form MTM can stall the processor or.." line.long 0x4 "MTM_TRC_ID,MTM trace ID register" hexmask.long.byte 0x4 0.--6. 1. "TRACE_ID,Trace ID value" rgroup.long 0x100++0x3 line.long 0x0 "MTM_BKP_STAT,MTM Backpressure status register" bitfld.long 0x0 1. "PCK_FIFO_FULL,Packet FIFO full" "0: Packet FIFO buffer not full.,1: Packet FIFO buffer full Backpressure scenario is.." group.long 0x200++0x3 line.long 0x0 "MTM_TAG_RGN_CONFIG,MTM TAG RAM configuration register" bitfld.long 0x0 2. "TAG_RGN_C,TAG region C" "0: Region C of the TAG RAM is not used.,1: Region C of the TAG RAM is used." newline bitfld.long 0x0 1. "TAG_RGN_B,TAG region B" "0: Region B of the TAG RAM is not used.,1: Region B of the TAG RAM is used." newline bitfld.long 0x0 0. "TAG_RGN_A,TAG region A" "0: Region A of the TAG RAM is not used.,1: Region A of the TAG RAM is used." group.long 0x210++0xB line.long 0x0 "MTM_TAG_RGN_BADR_A,MTM TAG RAM base address region A register" hexmask.long.tbyte 0x0 10.--31. 1. "A_REGION_BASE_ADR,A REGION BASE ADR value" line.long 0x4 "MTM_TAG_RGN_BADR_B,MTM TAG RAM base address region B register" hexmask.long.tbyte 0x4 10.--31. 1. "B_REGION_BASE_ADR,B REGION BASE ADR value" line.long 0x8 "MTM_TAG_RGN_BADR_C,MTM TAG RAM base address region C register" hexmask.long.tbyte 0x8 10.--31. 1. "C_REGION_BASE_ADR,C REGION BASE ADR value" rgroup.long 0x220++0xF line.long 0x0 "MTM_TAG_RGN_SZ_A,MTM TAG RAM region A size register" hexmask.long.word 0x0 0.--9. 1. "RGN_A_SIZE,RGN A size value" line.long 0x4 "MTM_TAG_RGN_SZ_B,MTM TAG RAM region B size register" hexmask.long.word 0x4 0.--9. 1. "RGN_B_SIZE,RGN B size value" line.long 0x8 "MTM_TAG_RGN_SZ_C,MTM TAG RAM size C size register" hexmask.long.word 0x8 0.--9. 1. "RGN_C_SIZE,RGN C size value" line.long 0xC "MTM_TAG_RGN_STAT,MTM TAG RAM region status register" bitfld.long 0xC 2. "RGN_C_BOUND_CROSS,RGN C bound cross" "0: Region C boundary not crossed.,1: Region C boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 1. "RGN_B_BOUND_CROSS,RGN B bound cross" "0: Region B boundary not crossed.,1: Region B boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 0. "RGN_A_BOUND_CROSS,RGN A bound cross" "0: Region A boundary not crossed.,1: Region A boundary crossed due to wrong 'PAGES'.." group.long 0x230++0x7 line.long 0x0 "MTM_TAG_ADR,MTM TAG RAM address register" bitfld.long 0x0 31. "AUTO_PROG_DONE,Auto programming done goes high when updates to tag RAM are completed by MTM. Debugger must clear this bit once set. Though this bit always provides the status of latest auto increment request even when debugger did not clear the.." "0: Auto programming is not completed.,1: Auto programming is completed." newline hexmask.long.word 0x0 10.--18. 1. "PAGES,Specifies the number of consecutive TAG RAM lines needs to be updated when Auto Increment address mode is enabled. Debugger must program PAGES field to 'required number of pages - 1'." newline hexmask.long.word 0x0 1.--9. 1. "ADDRESS_PAGE,Address page" newline bitfld.long 0x0 0. "AUTO_INCR,Auto increment" "0: Auto increment of the TAG address is disabled.,1: Auto increment of the TAG address is enabled." line.long 0x4 "MTM_TAG_DATA_CONFIG,MTM TAG RAM data configuration register" bitfld.long 0x4 17. "DATA_READ_STATUS,Data read status gives read completion status against the request set in DATA_READ bit." "0: Data read is not requested or completed.,1: Data read is completed for requested read." newline bitfld.long 0x4 16. "DATA_READ,Read control bit must be set by the debugger when it needs to read TAG RAM from the address programmed in ADDRESS_PAGE field of MTM_TAG_ADR register." "0: Read command is not set.,1: Read command is set." newline bitfld.long 0x4 5.--7. "SLICE_SIZE,Specify 3 most significant bits of every TAG RAM content line called ." "0: 8 byte,1: Filtering unit,2: 32 byte,3: 64 byte,4: 128 byte,5: 256 byte,6: 512 byte,7: 1K byte" newline hexmask.long.byte 0x4 1.--4. 1. "WORD_STROBE,WORD_STROBE bits are used to enable MTM_TAG_DATA_STROBE_W[n] registers. nth bit of WORD_STROBE corresponds to nth MTM_TAG_DATA_STROBE_W[n] register. For details refer to Section89.5.2.16: MTM TAG RAM strobe word n register.." newline bitfld.long 0x4 0. "DATA_VALID,Data valid controls write to TAG RAM" "0: TAG RAM content update is disabled.,1: TAG RAM content update is enabled." group.long 0x240++0xF line.long 0x0 "MTM_TAG_DATA_STROBE_W1,MTM TAG RAM strobe word 1 register" hexmask.long 0x0 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x4 "MTM_TAG_DATA_STROBE_W2,MTM TAG RAM strobe word 2 register" hexmask.long 0x4 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x8 "MTM_TAG_DATA_STROBE_W3,MTM TAG RAM strobe word 3 register" hexmask.long 0x8 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0xC "MTM_TAG_DATA_STROBE_W4,MTM TAG RAM strobe word 4 register" hexmask.long 0xC 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." group.long 0x400++0xB line.long 0x0 "MTM_TS_EN,MTM timestamp enable register" bitfld.long 0x0 0. "TS_EN,Timestamp enable" "0: TS packet generation disabled.,1: TS packet generation enabled." line.long 0x4 "MTM_TS_WIN_CNT,MTM Timestamp window counter register" hexmask.long 0x4 0.--31. 1. "WIND_COUNTER,Timestamp window counter value" line.long 0x8 "MTM_TS_CLK_SCL,MTM Timestamp clock scaler register" hexmask.long.word 0x8 0.--8. 1. "CLK_SCALER,Clock scaler value" group.long 0x410++0xB line.long 0x0 "AL_EN,Alignment message enable register" bitfld.long 0x0 0. "AL_EN,Alignment Synchronization (A-Sync) enable" "0: A-Sync packet generation disabled.,1: A-Sync packet generation enabled." line.long 0x4 "AL_WIN_CNT,Alignment message window counter register" hexmask.long 0x4 0.--31. 1. "AL_WIND_COUNTER,Alignment synchronization messages window counter value" line.long 0x8 "AL_CLK_SCL,Alignment window counter clock scaler register" hexmask.long.word 0x8 0.--8. 1. "AL_CLK_SCALER,Clock scaler value" group.long 0xFA0++0x7 line.long 0x0 "MTM_CLAIM_TAG_SET,MTM claim TAG set register" hexmask.long.byte 0x0 0.--3. 1. "CLAIM_SET,Claim set" line.long 0x4 "MTM_CLAIM_TAG_CLR,MTM claim TAG clear register" hexmask.long.byte 0x4 0.--3. 1. "CLAIM_CLEAR,Claim clear" wgroup.long 0xFB0++0x3 line.long 0x0 "MTM_LAR,MTM lock access register" hexmask.long 0x0 0.--31. 1. "SW_KEY,Software lock key value" rgroup.long 0xFB4++0xB line.long 0x0 "MTM_LSR,MTM lock status register" bitfld.long 0x0 2. "NTT,nTT" "0: Only value: MTM_LAR register is 32 bit wide (MTM..,?" newline bitfld.long 0x0 1. "SLK,SLK returns the software lock status." "0: Accesses permitted.,1: Write accesses to control registers of the MTM.." newline bitfld.long 0x0 0. "SLI,Software Lock Implementation" "0: Software lock is not implemented: returned for..,1: Software lock is implemented: returned for all.." line.long 0x4 "MTM_AUTH_STAT,MTM authentification status register" bitfld.long 0x4 6.--7. "SNID,Secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 4.--5. "SID,Secure invasive debug" "0: Functionality not implemented.,?,?,?" newline bitfld.long 0x4 2.--3. "NSNID,Non-secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 0.--1. "NSID,Non-secure invasive debug" "0: Functionality not implemented.,?,?,?" line.long 0x8 "MTM_DEV_ARCH,MTM device architecture register" hexmask.long.word 0x8 21.--31. 1. "ARCHITECT,Defines the Architect of the component:" newline bitfld.long 0x8 20. "PRES,Presence" "?,1: Device Architecture register is present." newline hexmask.long.byte 0x8 16.--19. 1. "ARCH_REVISION,Architecture revision" newline hexmask.long.word 0x8 0.--15. 1. "ARCH_ID,Architecture ID" rgroup.long 0xFC8++0x37 line.long 0x0 "MTM_DEV_ID,MTM device ID register" hexmask.long 0x0 0.--31. 1. "FUTURE_USE,Reserved" line.long 0x4 "MTM_DEV_TYPE,MTM device type register" hexmask.long.byte 0x4 4.--7. 1. "SUB,Based on ARM©defined codes (refer to Table B2-8 in document [5])." newline hexmask.long.byte 0x4 0.--3. 1. "MAJOR,Based on ARM©defined codes (refer to Table B2-8 in document [5])." line.long 0x8 "MTM_PID4,MTM peripheral ID4 register" bitfld.long 0x8 2.--3. "SIZE,Size" "0: MTM memory map occupies 4KB.,?,?,?" newline bitfld.long 0x8 0.--1. "DES_2,DES_2" "0: ST JEP106 continuation code (refer to the..,?,?,?" line.long 0xC "MTM_PID5,MTM peripheral ID5 register" hexmask.long 0xC 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x10 "MTM_PID6,MTM peripheral ID6 register" hexmask.long 0x10 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x14 "MTM_PID7,MTM peripheral ID7 register" hexmask.long 0x14 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x18 "MTM_PID0,MTM peripheral ID0 register" hexmask.long.byte 0x18 4.--7. 1. "PART_0M,Part 0M" newline hexmask.long.byte 0x18 0.--3. 1. "PART_0L,Part 0L" line.long 0x1C "MTM_PID1,MTM peripheral ID1 register" hexmask.long.byte 0x1C 4.--7. 1. "DES_0,DES 0" newline hexmask.long.byte 0x1C 0.--3. 1. "PART_1,Part 1" line.long 0x20 "MTM_PID2,MTM peripheral ID2 register" hexmask.long.byte 0x20 4.--7. 1. "REVISION,Revision" newline bitfld.long 0x20 3. "JEDEC,JEDEC" "?,1: Indicates that a JEDEC assigned value is used." newline bitfld.long 0x20 0.--2. "DES_1,DES 1" "?,?,2: ST JEP106 identification code [7] bits[6:4].,?,?,?,?,?" line.long 0x24 "MTM_PID3,MTM peripheral ID3 register" hexmask.long.byte 0x24 4.--7. 1. "REVAND,REVAND" newline hexmask.long.byte 0x24 0.--3. 1. "CMOD,CMOD" line.long 0x28 "MTM_CID0,MTM CS ID0 register" hexmask.long.byte 0x28 0.--7. 1. "PRMB0,Preamble 0" line.long 0x2C "MTM_CID1,MTM CS ID1 register" hexmask.long.byte 0x2C 4.--7. 1. "CLASS,Class" newline hexmask.long.byte 0x2C 0.--3. 1. "PRMB1,Preamble 1" line.long 0x30 "MTM_CID2,MTM CS ID2 register" hexmask.long.byte 0x30 0.--7. 1. "PRMB2,Preamble 2" line.long 0x34 "MTM_CID3,MTM CS ID3 register" hexmask.long.byte 0x34 0.--7. 1. "PRMB3,Preamble 3" tree.end tree "CLUSTER1_MTM_PRCTL1" base ad:0x7E01A000 group.long 0x0++0x7 line.long 0x0 "MTM_EN,MTM enable register" bitfld.long 0x0 0. "MTM_ENABLE,MTM enable" "0: MTM disabled,1: MTM enabled" line.long 0x4 "MTM_TRC_EN,MTM trace enable" bitfld.long 0x4 1. "INVLD_FIFO,Invalidate FIFO" "0: Packet FIFO pointers is not invalidated old..,1: Invalidate Packet FIFO old trace data is lost." newline bitfld.long 0x4 0. "TRACE_EN,Trace Enable" "0: Trace filtering is disabled. When disabled TAG..,1: Trace filtering is enabled." group.long 0x20++0x7 line.long 0x0 "MTM_TRC_STALL_CTRL,MTM trace stall control register" hexmask.long.byte 0x0 1.--4. 1. "LEVEL,Level" newline bitfld.long 0x0 0. "STALL,Stall" "0: Backpressure form MTM does not stall the..,1: Backpressure form MTM can stall the processor or.." line.long 0x4 "MTM_TRC_ID,MTM trace ID register" hexmask.long.byte 0x4 0.--6. 1. "TRACE_ID,Trace ID value" rgroup.long 0x100++0x3 line.long 0x0 "MTM_BKP_STAT,MTM Backpressure status register" bitfld.long 0x0 1. "PCK_FIFO_FULL,Packet FIFO full" "0: Packet FIFO buffer not full.,1: Packet FIFO buffer full Backpressure scenario is.." group.long 0x200++0x3 line.long 0x0 "MTM_TAG_RGN_CONFIG,MTM TAG RAM configuration register" bitfld.long 0x0 2. "TAG_RGN_C,TAG region C" "0: Region C of the TAG RAM is not used.,1: Region C of the TAG RAM is used." newline bitfld.long 0x0 1. "TAG_RGN_B,TAG region B" "0: Region B of the TAG RAM is not used.,1: Region B of the TAG RAM is used." newline bitfld.long 0x0 0. "TAG_RGN_A,TAG region A" "0: Region A of the TAG RAM is not used.,1: Region A of the TAG RAM is used." group.long 0x210++0xB line.long 0x0 "MTM_TAG_RGN_BADR_A,MTM TAG RAM base address region A register" hexmask.long.tbyte 0x0 10.--31. 1. "A_REGION_BASE_ADR,A REGION BASE ADR value" line.long 0x4 "MTM_TAG_RGN_BADR_B,MTM TAG RAM base address region B register" hexmask.long.tbyte 0x4 10.--31. 1. "B_REGION_BASE_ADR,B REGION BASE ADR value" line.long 0x8 "MTM_TAG_RGN_BADR_C,MTM TAG RAM base address region C register" hexmask.long.tbyte 0x8 10.--31. 1. "C_REGION_BASE_ADR,C REGION BASE ADR value" rgroup.long 0x220++0xF line.long 0x0 "MTM_TAG_RGN_SZ_A,MTM TAG RAM region A size register" hexmask.long.word 0x0 0.--9. 1. "RGN_A_SIZE,RGN A size value" line.long 0x4 "MTM_TAG_RGN_SZ_B,MTM TAG RAM region B size register" hexmask.long.word 0x4 0.--9. 1. "RGN_B_SIZE,RGN B size value" line.long 0x8 "MTM_TAG_RGN_SZ_C,MTM TAG RAM size C size register" hexmask.long.word 0x8 0.--9. 1. "RGN_C_SIZE,RGN C size value" line.long 0xC "MTM_TAG_RGN_STAT,MTM TAG RAM region status register" bitfld.long 0xC 2. "RGN_C_BOUND_CROSS,RGN C bound cross" "0: Region C boundary not crossed.,1: Region C boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 1. "RGN_B_BOUND_CROSS,RGN B bound cross" "0: Region B boundary not crossed.,1: Region B boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 0. "RGN_A_BOUND_CROSS,RGN A bound cross" "0: Region A boundary not crossed.,1: Region A boundary crossed due to wrong 'PAGES'.." group.long 0x230++0x7 line.long 0x0 "MTM_TAG_ADR,MTM TAG RAM address register" bitfld.long 0x0 31. "AUTO_PROG_DONE,Auto programming done goes high when updates to tag RAM are completed by MTM. Debugger must clear this bit once set. Though this bit always provides the status of latest auto increment request even when debugger did not clear the.." "0: Auto programming is not completed.,1: Auto programming is completed." newline hexmask.long.word 0x0 10.--18. 1. "PAGES,Specifies the number of consecutive TAG RAM lines needs to be updated when Auto Increment address mode is enabled. Debugger must program PAGES field to 'required number of pages - 1'." newline hexmask.long.word 0x0 1.--9. 1. "ADDRESS_PAGE,Address page" newline bitfld.long 0x0 0. "AUTO_INCR,Auto increment" "0: Auto increment of the TAG address is disabled.,1: Auto increment of the TAG address is enabled." line.long 0x4 "MTM_TAG_DATA_CONFIG,MTM TAG RAM data configuration register" bitfld.long 0x4 17. "DATA_READ_STATUS,Data read status gives read completion status against the request set in DATA_READ bit." "0: Data read is not requested or completed.,1: Data read is completed for requested read." newline bitfld.long 0x4 16. "DATA_READ,Read control bit must be set by the debugger when it needs to read TAG RAM from the address programmed in ADDRESS_PAGE field of MTM_TAG_ADR register." "0: Read command is not set.,1: Read command is set." newline bitfld.long 0x4 5.--7. "SLICE_SIZE,Specify 3 most significant bits of every TAG RAM content line called ." "0: 8 byte,1: Filtering unit,2: 32 byte,3: 64 byte,4: 128 byte,5: 256 byte,6: 512 byte,7: 1K byte" newline hexmask.long.byte 0x4 1.--4. 1. "WORD_STROBE,WORD_STROBE bits are used to enable MTM_TAG_DATA_STROBE_W[n] registers. nth bit of WORD_STROBE corresponds to nth MTM_TAG_DATA_STROBE_W[n] register. For details refer to Section89.5.2.16: MTM TAG RAM strobe word n register.." newline bitfld.long 0x4 0. "DATA_VALID,Data valid controls write to TAG RAM" "0: TAG RAM content update is disabled.,1: TAG RAM content update is enabled." group.long 0x240++0xF line.long 0x0 "MTM_TAG_DATA_STROBE_W1,MTM TAG RAM strobe word 1 register" hexmask.long 0x0 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x4 "MTM_TAG_DATA_STROBE_W2,MTM TAG RAM strobe word 2 register" hexmask.long 0x4 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x8 "MTM_TAG_DATA_STROBE_W3,MTM TAG RAM strobe word 3 register" hexmask.long 0x8 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0xC "MTM_TAG_DATA_STROBE_W4,MTM TAG RAM strobe word 4 register" hexmask.long 0xC 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." group.long 0x400++0xB line.long 0x0 "MTM_TS_EN,MTM timestamp enable register" bitfld.long 0x0 0. "TS_EN,Timestamp enable" "0: TS packet generation disabled.,1: TS packet generation enabled." line.long 0x4 "MTM_TS_WIN_CNT,MTM Timestamp window counter register" hexmask.long 0x4 0.--31. 1. "WIND_COUNTER,Timestamp window counter value" line.long 0x8 "MTM_TS_CLK_SCL,MTM Timestamp clock scaler register" hexmask.long.word 0x8 0.--8. 1. "CLK_SCALER,Clock scaler value" group.long 0x410++0xB line.long 0x0 "AL_EN,Alignment message enable register" bitfld.long 0x0 0. "AL_EN,Alignment Synchronization (A-Sync) enable" "0: A-Sync packet generation disabled.,1: A-Sync packet generation enabled." line.long 0x4 "AL_WIN_CNT,Alignment message window counter register" hexmask.long 0x4 0.--31. 1. "AL_WIND_COUNTER,Alignment synchronization messages window counter value" line.long 0x8 "AL_CLK_SCL,Alignment window counter clock scaler register" hexmask.long.word 0x8 0.--8. 1. "AL_CLK_SCALER,Clock scaler value" group.long 0xFA0++0x7 line.long 0x0 "MTM_CLAIM_TAG_SET,MTM claim TAG set register" hexmask.long.byte 0x0 0.--3. 1. "CLAIM_SET,Claim set" line.long 0x4 "MTM_CLAIM_TAG_CLR,MTM claim TAG clear register" hexmask.long.byte 0x4 0.--3. 1. "CLAIM_CLEAR,Claim clear" wgroup.long 0xFB0++0x3 line.long 0x0 "MTM_LAR,MTM lock access register" hexmask.long 0x0 0.--31. 1. "SW_KEY,Software lock key value" rgroup.long 0xFB4++0xB line.long 0x0 "MTM_LSR,MTM lock status register" bitfld.long 0x0 2. "NTT,nTT" "0: Only value: MTM_LAR register is 32 bit wide (MTM..,?" newline bitfld.long 0x0 1. "SLK,SLK returns the software lock status." "0: Accesses permitted.,1: Write accesses to control registers of the MTM.." newline bitfld.long 0x0 0. "SLI,Software Lock Implementation" "0: Software lock is not implemented: returned for..,1: Software lock is implemented: returned for all.." line.long 0x4 "MTM_AUTH_STAT,MTM authentification status register" bitfld.long 0x4 6.--7. "SNID,Secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 4.--5. "SID,Secure invasive debug" "0: Functionality not implemented.,?,?,?" newline bitfld.long 0x4 2.--3. "NSNID,Non-secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 0.--1. "NSID,Non-secure invasive debug" "0: Functionality not implemented.,?,?,?" line.long 0x8 "MTM_DEV_ARCH,MTM device architecture register" hexmask.long.word 0x8 21.--31. 1. "ARCHITECT,Defines the Architect of the component:" newline bitfld.long 0x8 20. "PRES,Presence" "?,1: Device Architecture register is present." newline hexmask.long.byte 0x8 16.--19. 1. "ARCH_REVISION,Architecture revision" newline hexmask.long.word 0x8 0.--15. 1. "ARCH_ID,Architecture ID" rgroup.long 0xFC8++0x37 line.long 0x0 "MTM_DEV_ID,MTM device ID register" hexmask.long 0x0 0.--31. 1. "FUTURE_USE,Reserved" line.long 0x4 "MTM_DEV_TYPE,MTM device type register" hexmask.long.byte 0x4 4.--7. 1. "SUB,Based on ARM©defined codes (refer to Table B2-8 in document [5])." newline hexmask.long.byte 0x4 0.--3. 1. "MAJOR,Based on ARM©defined codes (refer to Table B2-8 in document [5])." line.long 0x8 "MTM_PID4,MTM peripheral ID4 register" bitfld.long 0x8 2.--3. "SIZE,Size" "0: MTM memory map occupies 4KB.,?,?,?" newline bitfld.long 0x8 0.--1. "DES_2,DES_2" "0: ST JEP106 continuation code (refer to the..,?,?,?" line.long 0xC "MTM_PID5,MTM peripheral ID5 register" hexmask.long 0xC 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x10 "MTM_PID6,MTM peripheral ID6 register" hexmask.long 0x10 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x14 "MTM_PID7,MTM peripheral ID7 register" hexmask.long 0x14 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x18 "MTM_PID0,MTM peripheral ID0 register" hexmask.long.byte 0x18 4.--7. 1. "PART_0M,Part 0M" newline hexmask.long.byte 0x18 0.--3. 1. "PART_0L,Part 0L" line.long 0x1C "MTM_PID1,MTM peripheral ID1 register" hexmask.long.byte 0x1C 4.--7. 1. "DES_0,DES 0" newline hexmask.long.byte 0x1C 0.--3. 1. "PART_1,Part 1" line.long 0x20 "MTM_PID2,MTM peripheral ID2 register" hexmask.long.byte 0x20 4.--7. 1. "REVISION,Revision" newline bitfld.long 0x20 3. "JEDEC,JEDEC" "?,1: Indicates that a JEDEC assigned value is used." newline bitfld.long 0x20 0.--2. "DES_1,DES 1" "?,?,2: ST JEP106 identification code [7] bits[6:4].,?,?,?,?,?" line.long 0x24 "MTM_PID3,MTM peripheral ID3 register" hexmask.long.byte 0x24 4.--7. 1. "REVAND,REVAND" newline hexmask.long.byte 0x24 0.--3. 1. "CMOD,CMOD" line.long 0x28 "MTM_CID0,MTM CS ID0 register" hexmask.long.byte 0x28 0.--7. 1. "PRMB0,Preamble 0" line.long 0x2C "MTM_CID1,MTM CS ID1 register" hexmask.long.byte 0x2C 4.--7. 1. "CLASS,Class" newline hexmask.long.byte 0x2C 0.--3. 1. "PRMB1,Preamble 1" line.long 0x30 "MTM_CID2,MTM CS ID2 register" hexmask.long.byte 0x30 0.--7. 1. "PRMB2,Preamble 2" line.long 0x34 "MTM_CID3,MTM CS ID3 register" hexmask.long.byte 0x34 0.--7. 1. "PRMB3,Preamble 3" tree.end tree "CLUSTER2_MTM_CORE0" base ad:0x7E022000 group.long 0x0++0x7 line.long 0x0 "MTM_EN,MTM enable register" bitfld.long 0x0 0. "MTM_ENABLE,MTM enable" "0: MTM disabled,1: MTM enabled" line.long 0x4 "MTM_TRC_EN,MTM trace enable" bitfld.long 0x4 1. "INVLD_FIFO,Invalidate FIFO" "0: Packet FIFO pointers is not invalidated old..,1: Invalidate Packet FIFO old trace data is lost." newline bitfld.long 0x4 0. "TRACE_EN,Trace Enable" "0: Trace filtering is disabled. When disabled TAG..,1: Trace filtering is enabled." group.long 0x20++0x7 line.long 0x0 "MTM_TRC_STALL_CTRL,MTM trace stall control register" hexmask.long.byte 0x0 1.--4. 1. "LEVEL,Level" newline bitfld.long 0x0 0. "STALL,Stall" "0: Backpressure form MTM does not stall the..,1: Backpressure form MTM can stall the processor or.." line.long 0x4 "MTM_TRC_ID,MTM trace ID register" hexmask.long.byte 0x4 0.--6. 1. "TRACE_ID,Trace ID value" rgroup.long 0x100++0x3 line.long 0x0 "MTM_BKP_STAT,MTM Backpressure status register" bitfld.long 0x0 1. "PCK_FIFO_FULL,Packet FIFO full" "0: Packet FIFO buffer not full.,1: Packet FIFO buffer full Backpressure scenario is.." group.long 0x200++0x3 line.long 0x0 "MTM_TAG_RGN_CONFIG,MTM TAG RAM configuration register" bitfld.long 0x0 2. "TAG_RGN_C,TAG region C" "0: Region C of the TAG RAM is not used.,1: Region C of the TAG RAM is used." newline bitfld.long 0x0 1. "TAG_RGN_B,TAG region B" "0: Region B of the TAG RAM is not used.,1: Region B of the TAG RAM is used." newline bitfld.long 0x0 0. "TAG_RGN_A,TAG region A" "0: Region A of the TAG RAM is not used.,1: Region A of the TAG RAM is used." group.long 0x210++0xB line.long 0x0 "MTM_TAG_RGN_BADR_A,MTM TAG RAM base address region A register" hexmask.long.tbyte 0x0 10.--31. 1. "A_REGION_BASE_ADR,A REGION BASE ADR value" line.long 0x4 "MTM_TAG_RGN_BADR_B,MTM TAG RAM base address region B register" hexmask.long.tbyte 0x4 10.--31. 1. "B_REGION_BASE_ADR,B REGION BASE ADR value" line.long 0x8 "MTM_TAG_RGN_BADR_C,MTM TAG RAM base address region C register" hexmask.long.tbyte 0x8 10.--31. 1. "C_REGION_BASE_ADR,C REGION BASE ADR value" rgroup.long 0x220++0xF line.long 0x0 "MTM_TAG_RGN_SZ_A,MTM TAG RAM region A size register" hexmask.long.word 0x0 0.--9. 1. "RGN_A_SIZE,RGN A size value" line.long 0x4 "MTM_TAG_RGN_SZ_B,MTM TAG RAM region B size register" hexmask.long.word 0x4 0.--9. 1. "RGN_B_SIZE,RGN B size value" line.long 0x8 "MTM_TAG_RGN_SZ_C,MTM TAG RAM size C size register" hexmask.long.word 0x8 0.--9. 1. "RGN_C_SIZE,RGN C size value" line.long 0xC "MTM_TAG_RGN_STAT,MTM TAG RAM region status register" bitfld.long 0xC 2. "RGN_C_BOUND_CROSS,RGN C bound cross" "0: Region C boundary not crossed.,1: Region C boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 1. "RGN_B_BOUND_CROSS,RGN B bound cross" "0: Region B boundary not crossed.,1: Region B boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 0. "RGN_A_BOUND_CROSS,RGN A bound cross" "0: Region A boundary not crossed.,1: Region A boundary crossed due to wrong 'PAGES'.." group.long 0x230++0x7 line.long 0x0 "MTM_TAG_ADR,MTM TAG RAM address register" bitfld.long 0x0 31. "AUTO_PROG_DONE,Auto programming done goes high when updates to tag RAM are completed by MTM. Debugger must clear this bit once set. Though this bit always provides the status of latest auto increment request even when debugger did not clear the.." "0: Auto programming is not completed.,1: Auto programming is completed." newline hexmask.long.word 0x0 10.--18. 1. "PAGES,Specifies the number of consecutive TAG RAM lines needs to be updated when Auto Increment address mode is enabled. Debugger must program PAGES field to 'required number of pages - 1'." newline hexmask.long.word 0x0 1.--9. 1. "ADDRESS_PAGE,Address page" newline bitfld.long 0x0 0. "AUTO_INCR,Auto increment" "0: Auto increment of the TAG address is disabled.,1: Auto increment of the TAG address is enabled." line.long 0x4 "MTM_TAG_DATA_CONFIG,MTM TAG RAM data configuration register" bitfld.long 0x4 17. "DATA_READ_STATUS,Data read status gives read completion status against the request set in DATA_READ bit." "0: Data read is not requested or completed.,1: Data read is completed for requested read." newline bitfld.long 0x4 16. "DATA_READ,Read control bit must be set by the debugger when it needs to read TAG RAM from the address programmed in ADDRESS_PAGE field of MTM_TAG_ADR register." "0: Read command is not set.,1: Read command is set." newline bitfld.long 0x4 5.--7. "SLICE_SIZE,Specify 3 most significant bits of every TAG RAM content line called ." "0: 8 byte,1: Filtering unit,2: 32 byte,3: 64 byte,4: 128 byte,5: 256 byte,6: 512 byte,7: 1K byte" newline hexmask.long.byte 0x4 1.--4. 1. "WORD_STROBE,WORD_STROBE bits are used to enable MTM_TAG_DATA_STROBE_W[n] registers. nth bit of WORD_STROBE corresponds to nth MTM_TAG_DATA_STROBE_W[n] register. For details refer to Section89.5.2.16: MTM TAG RAM strobe word n register.." newline bitfld.long 0x4 0. "DATA_VALID,Data valid controls write to TAG RAM" "0: TAG RAM content update is disabled.,1: TAG RAM content update is enabled." group.long 0x240++0xF line.long 0x0 "MTM_TAG_DATA_STROBE_W1,MTM TAG RAM strobe word 1 register" hexmask.long 0x0 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x4 "MTM_TAG_DATA_STROBE_W2,MTM TAG RAM strobe word 2 register" hexmask.long 0x4 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x8 "MTM_TAG_DATA_STROBE_W3,MTM TAG RAM strobe word 3 register" hexmask.long 0x8 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0xC "MTM_TAG_DATA_STROBE_W4,MTM TAG RAM strobe word 4 register" hexmask.long 0xC 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." group.long 0x400++0xB line.long 0x0 "MTM_TS_EN,MTM timestamp enable register" bitfld.long 0x0 0. "TS_EN,Timestamp enable" "0: TS packet generation disabled.,1: TS packet generation enabled." line.long 0x4 "MTM_TS_WIN_CNT,MTM Timestamp window counter register" hexmask.long 0x4 0.--31. 1. "WIND_COUNTER,Timestamp window counter value" line.long 0x8 "MTM_TS_CLK_SCL,MTM Timestamp clock scaler register" hexmask.long.word 0x8 0.--8. 1. "CLK_SCALER,Clock scaler value" group.long 0x410++0xB line.long 0x0 "AL_EN,Alignment message enable register" bitfld.long 0x0 0. "AL_EN,Alignment Synchronization (A-Sync) enable" "0: A-Sync packet generation disabled.,1: A-Sync packet generation enabled." line.long 0x4 "AL_WIN_CNT,Alignment message window counter register" hexmask.long 0x4 0.--31. 1. "AL_WIND_COUNTER,Alignment synchronization messages window counter value" line.long 0x8 "AL_CLK_SCL,Alignment window counter clock scaler register" hexmask.long.word 0x8 0.--8. 1. "AL_CLK_SCALER,Clock scaler value" group.long 0xFA0++0x7 line.long 0x0 "MTM_CLAIM_TAG_SET,MTM claim TAG set register" hexmask.long.byte 0x0 0.--3. 1. "CLAIM_SET,Claim set" line.long 0x4 "MTM_CLAIM_TAG_CLR,MTM claim TAG clear register" hexmask.long.byte 0x4 0.--3. 1. "CLAIM_CLEAR,Claim clear" wgroup.long 0xFB0++0x3 line.long 0x0 "MTM_LAR,MTM lock access register" hexmask.long 0x0 0.--31. 1. "SW_KEY,Software lock key value" rgroup.long 0xFB4++0xB line.long 0x0 "MTM_LSR,MTM lock status register" bitfld.long 0x0 2. "NTT,nTT" "0: Only value: MTM_LAR register is 32 bit wide (MTM..,?" newline bitfld.long 0x0 1. "SLK,SLK returns the software lock status." "0: Accesses permitted.,1: Write accesses to control registers of the MTM.." newline bitfld.long 0x0 0. "SLI,Software Lock Implementation" "0: Software lock is not implemented: returned for..,1: Software lock is implemented: returned for all.." line.long 0x4 "MTM_AUTH_STAT,MTM authentification status register" bitfld.long 0x4 6.--7. "SNID,Secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 4.--5. "SID,Secure invasive debug" "0: Functionality not implemented.,?,?,?" newline bitfld.long 0x4 2.--3. "NSNID,Non-secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 0.--1. "NSID,Non-secure invasive debug" "0: Functionality not implemented.,?,?,?" line.long 0x8 "MTM_DEV_ARCH,MTM device architecture register" hexmask.long.word 0x8 21.--31. 1. "ARCHITECT,Defines the Architect of the component:" newline bitfld.long 0x8 20. "PRES,Presence" "?,1: Device Architecture register is present." newline hexmask.long.byte 0x8 16.--19. 1. "ARCH_REVISION,Architecture revision" newline hexmask.long.word 0x8 0.--15. 1. "ARCH_ID,Architecture ID" rgroup.long 0xFC8++0x37 line.long 0x0 "MTM_DEV_ID,MTM device ID register" hexmask.long 0x0 0.--31. 1. "FUTURE_USE,Reserved" line.long 0x4 "MTM_DEV_TYPE,MTM device type register" hexmask.long.byte 0x4 4.--7. 1. "SUB,Based on ARM©defined codes (refer to Table B2-8 in document [5])." newline hexmask.long.byte 0x4 0.--3. 1. "MAJOR,Based on ARM©defined codes (refer to Table B2-8 in document [5])." line.long 0x8 "MTM_PID4,MTM peripheral ID4 register" bitfld.long 0x8 2.--3. "SIZE,Size" "0: MTM memory map occupies 4KB.,?,?,?" newline bitfld.long 0x8 0.--1. "DES_2,DES_2" "0: ST JEP106 continuation code (refer to the..,?,?,?" line.long 0xC "MTM_PID5,MTM peripheral ID5 register" hexmask.long 0xC 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x10 "MTM_PID6,MTM peripheral ID6 register" hexmask.long 0x10 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x14 "MTM_PID7,MTM peripheral ID7 register" hexmask.long 0x14 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x18 "MTM_PID0,MTM peripheral ID0 register" hexmask.long.byte 0x18 4.--7. 1. "PART_0M,Part 0M" newline hexmask.long.byte 0x18 0.--3. 1. "PART_0L,Part 0L" line.long 0x1C "MTM_PID1,MTM peripheral ID1 register" hexmask.long.byte 0x1C 4.--7. 1. "DES_0,DES 0" newline hexmask.long.byte 0x1C 0.--3. 1. "PART_1,Part 1" line.long 0x20 "MTM_PID2,MTM peripheral ID2 register" hexmask.long.byte 0x20 4.--7. 1. "REVISION,Revision" newline bitfld.long 0x20 3. "JEDEC,JEDEC" "?,1: Indicates that a JEDEC assigned value is used." newline bitfld.long 0x20 0.--2. "DES_1,DES 1" "?,?,2: ST JEP106 identification code [7] bits[6:4].,?,?,?,?,?" line.long 0x24 "MTM_PID3,MTM peripheral ID3 register" hexmask.long.byte 0x24 4.--7. 1. "REVAND,REVAND" newline hexmask.long.byte 0x24 0.--3. 1. "CMOD,CMOD" line.long 0x28 "MTM_CID0,MTM CS ID0 register" hexmask.long.byte 0x28 0.--7. 1. "PRMB0,Preamble 0" line.long 0x2C "MTM_CID1,MTM CS ID1 register" hexmask.long.byte 0x2C 4.--7. 1. "CLASS,Class" newline hexmask.long.byte 0x2C 0.--3. 1. "PRMB1,Preamble 1" line.long 0x30 "MTM_CID2,MTM CS ID2 register" hexmask.long.byte 0x30 0.--7. 1. "PRMB2,Preamble 2" line.long 0x34 "MTM_CID3,MTM CS ID3 register" hexmask.long.byte 0x34 0.--7. 1. "PRMB3,Preamble 3" tree.end tree "CLUSTER2_MTM_CORE1" base ad:0x7E024000 group.long 0x0++0x7 line.long 0x0 "MTM_EN,MTM enable register" bitfld.long 0x0 0. "MTM_ENABLE,MTM enable" "0: MTM disabled,1: MTM enabled" line.long 0x4 "MTM_TRC_EN,MTM trace enable" bitfld.long 0x4 1. "INVLD_FIFO,Invalidate FIFO" "0: Packet FIFO pointers is not invalidated old..,1: Invalidate Packet FIFO old trace data is lost." newline bitfld.long 0x4 0. "TRACE_EN,Trace Enable" "0: Trace filtering is disabled. When disabled TAG..,1: Trace filtering is enabled." group.long 0x20++0x7 line.long 0x0 "MTM_TRC_STALL_CTRL,MTM trace stall control register" hexmask.long.byte 0x0 1.--4. 1. "LEVEL,Level" newline bitfld.long 0x0 0. "STALL,Stall" "0: Backpressure form MTM does not stall the..,1: Backpressure form MTM can stall the processor or.." line.long 0x4 "MTM_TRC_ID,MTM trace ID register" hexmask.long.byte 0x4 0.--6. 1. "TRACE_ID,Trace ID value" rgroup.long 0x100++0x3 line.long 0x0 "MTM_BKP_STAT,MTM Backpressure status register" bitfld.long 0x0 1. "PCK_FIFO_FULL,Packet FIFO full" "0: Packet FIFO buffer not full.,1: Packet FIFO buffer full Backpressure scenario is.." group.long 0x200++0x3 line.long 0x0 "MTM_TAG_RGN_CONFIG,MTM TAG RAM configuration register" bitfld.long 0x0 2. "TAG_RGN_C,TAG region C" "0: Region C of the TAG RAM is not used.,1: Region C of the TAG RAM is used." newline bitfld.long 0x0 1. "TAG_RGN_B,TAG region B" "0: Region B of the TAG RAM is not used.,1: Region B of the TAG RAM is used." newline bitfld.long 0x0 0. "TAG_RGN_A,TAG region A" "0: Region A of the TAG RAM is not used.,1: Region A of the TAG RAM is used." group.long 0x210++0xB line.long 0x0 "MTM_TAG_RGN_BADR_A,MTM TAG RAM base address region A register" hexmask.long.tbyte 0x0 10.--31. 1. "A_REGION_BASE_ADR,A REGION BASE ADR value" line.long 0x4 "MTM_TAG_RGN_BADR_B,MTM TAG RAM base address region B register" hexmask.long.tbyte 0x4 10.--31. 1. "B_REGION_BASE_ADR,B REGION BASE ADR value" line.long 0x8 "MTM_TAG_RGN_BADR_C,MTM TAG RAM base address region C register" hexmask.long.tbyte 0x8 10.--31. 1. "C_REGION_BASE_ADR,C REGION BASE ADR value" rgroup.long 0x220++0xF line.long 0x0 "MTM_TAG_RGN_SZ_A,MTM TAG RAM region A size register" hexmask.long.word 0x0 0.--9. 1. "RGN_A_SIZE,RGN A size value" line.long 0x4 "MTM_TAG_RGN_SZ_B,MTM TAG RAM region B size register" hexmask.long.word 0x4 0.--9. 1. "RGN_B_SIZE,RGN B size value" line.long 0x8 "MTM_TAG_RGN_SZ_C,MTM TAG RAM size C size register" hexmask.long.word 0x8 0.--9. 1. "RGN_C_SIZE,RGN C size value" line.long 0xC "MTM_TAG_RGN_STAT,MTM TAG RAM region status register" bitfld.long 0xC 2. "RGN_C_BOUND_CROSS,RGN C bound cross" "0: Region C boundary not crossed.,1: Region C boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 1. "RGN_B_BOUND_CROSS,RGN B bound cross" "0: Region B boundary not crossed.,1: Region B boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 0. "RGN_A_BOUND_CROSS,RGN A bound cross" "0: Region A boundary not crossed.,1: Region A boundary crossed due to wrong 'PAGES'.." group.long 0x230++0x7 line.long 0x0 "MTM_TAG_ADR,MTM TAG RAM address register" bitfld.long 0x0 31. "AUTO_PROG_DONE,Auto programming done goes high when updates to tag RAM are completed by MTM. Debugger must clear this bit once set. Though this bit always provides the status of latest auto increment request even when debugger did not clear the.." "0: Auto programming is not completed.,1: Auto programming is completed." newline hexmask.long.word 0x0 10.--18. 1. "PAGES,Specifies the number of consecutive TAG RAM lines needs to be updated when Auto Increment address mode is enabled. Debugger must program PAGES field to 'required number of pages - 1'." newline hexmask.long.word 0x0 1.--9. 1. "ADDRESS_PAGE,Address page" newline bitfld.long 0x0 0. "AUTO_INCR,Auto increment" "0: Auto increment of the TAG address is disabled.,1: Auto increment of the TAG address is enabled." line.long 0x4 "MTM_TAG_DATA_CONFIG,MTM TAG RAM data configuration register" bitfld.long 0x4 17. "DATA_READ_STATUS,Data read status gives read completion status against the request set in DATA_READ bit." "0: Data read is not requested or completed.,1: Data read is completed for requested read." newline bitfld.long 0x4 16. "DATA_READ,Read control bit must be set by the debugger when it needs to read TAG RAM from the address programmed in ADDRESS_PAGE field of MTM_TAG_ADR register." "0: Read command is not set.,1: Read command is set." newline bitfld.long 0x4 5.--7. "SLICE_SIZE,Specify 3 most significant bits of every TAG RAM content line called ." "0: 8 byte,1: Filtering unit,2: 32 byte,3: 64 byte,4: 128 byte,5: 256 byte,6: 512 byte,7: 1K byte" newline hexmask.long.byte 0x4 1.--4. 1. "WORD_STROBE,WORD_STROBE bits are used to enable MTM_TAG_DATA_STROBE_W[n] registers. nth bit of WORD_STROBE corresponds to nth MTM_TAG_DATA_STROBE_W[n] register. For details refer to Section89.5.2.16: MTM TAG RAM strobe word n register.." newline bitfld.long 0x4 0. "DATA_VALID,Data valid controls write to TAG RAM" "0: TAG RAM content update is disabled.,1: TAG RAM content update is enabled." group.long 0x240++0xF line.long 0x0 "MTM_TAG_DATA_STROBE_W1,MTM TAG RAM strobe word 1 register" hexmask.long 0x0 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x4 "MTM_TAG_DATA_STROBE_W2,MTM TAG RAM strobe word 2 register" hexmask.long 0x4 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x8 "MTM_TAG_DATA_STROBE_W3,MTM TAG RAM strobe word 3 register" hexmask.long 0x8 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0xC "MTM_TAG_DATA_STROBE_W4,MTM TAG RAM strobe word 4 register" hexmask.long 0xC 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." group.long 0x400++0xB line.long 0x0 "MTM_TS_EN,MTM timestamp enable register" bitfld.long 0x0 0. "TS_EN,Timestamp enable" "0: TS packet generation disabled.,1: TS packet generation enabled." line.long 0x4 "MTM_TS_WIN_CNT,MTM Timestamp window counter register" hexmask.long 0x4 0.--31. 1. "WIND_COUNTER,Timestamp window counter value" line.long 0x8 "MTM_TS_CLK_SCL,MTM Timestamp clock scaler register" hexmask.long.word 0x8 0.--8. 1. "CLK_SCALER,Clock scaler value" group.long 0x410++0xB line.long 0x0 "AL_EN,Alignment message enable register" bitfld.long 0x0 0. "AL_EN,Alignment Synchronization (A-Sync) enable" "0: A-Sync packet generation disabled.,1: A-Sync packet generation enabled." line.long 0x4 "AL_WIN_CNT,Alignment message window counter register" hexmask.long 0x4 0.--31. 1. "AL_WIND_COUNTER,Alignment synchronization messages window counter value" line.long 0x8 "AL_CLK_SCL,Alignment window counter clock scaler register" hexmask.long.word 0x8 0.--8. 1. "AL_CLK_SCALER,Clock scaler value" group.long 0xFA0++0x7 line.long 0x0 "MTM_CLAIM_TAG_SET,MTM claim TAG set register" hexmask.long.byte 0x0 0.--3. 1. "CLAIM_SET,Claim set" line.long 0x4 "MTM_CLAIM_TAG_CLR,MTM claim TAG clear register" hexmask.long.byte 0x4 0.--3. 1. "CLAIM_CLEAR,Claim clear" wgroup.long 0xFB0++0x3 line.long 0x0 "MTM_LAR,MTM lock access register" hexmask.long 0x0 0.--31. 1. "SW_KEY,Software lock key value" rgroup.long 0xFB4++0xB line.long 0x0 "MTM_LSR,MTM lock status register" bitfld.long 0x0 2. "NTT,nTT" "0: Only value: MTM_LAR register is 32 bit wide (MTM..,?" newline bitfld.long 0x0 1. "SLK,SLK returns the software lock status." "0: Accesses permitted.,1: Write accesses to control registers of the MTM.." newline bitfld.long 0x0 0. "SLI,Software Lock Implementation" "0: Software lock is not implemented: returned for..,1: Software lock is implemented: returned for all.." line.long 0x4 "MTM_AUTH_STAT,MTM authentification status register" bitfld.long 0x4 6.--7. "SNID,Secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 4.--5. "SID,Secure invasive debug" "0: Functionality not implemented.,?,?,?" newline bitfld.long 0x4 2.--3. "NSNID,Non-secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 0.--1. "NSID,Non-secure invasive debug" "0: Functionality not implemented.,?,?,?" line.long 0x8 "MTM_DEV_ARCH,MTM device architecture register" hexmask.long.word 0x8 21.--31. 1. "ARCHITECT,Defines the Architect of the component:" newline bitfld.long 0x8 20. "PRES,Presence" "?,1: Device Architecture register is present." newline hexmask.long.byte 0x8 16.--19. 1. "ARCH_REVISION,Architecture revision" newline hexmask.long.word 0x8 0.--15. 1. "ARCH_ID,Architecture ID" rgroup.long 0xFC8++0x37 line.long 0x0 "MTM_DEV_ID,MTM device ID register" hexmask.long 0x0 0.--31. 1. "FUTURE_USE,Reserved" line.long 0x4 "MTM_DEV_TYPE,MTM device type register" hexmask.long.byte 0x4 4.--7. 1. "SUB,Based on ARM©defined codes (refer to Table B2-8 in document [5])." newline hexmask.long.byte 0x4 0.--3. 1. "MAJOR,Based on ARM©defined codes (refer to Table B2-8 in document [5])." line.long 0x8 "MTM_PID4,MTM peripheral ID4 register" bitfld.long 0x8 2.--3. "SIZE,Size" "0: MTM memory map occupies 4KB.,?,?,?" newline bitfld.long 0x8 0.--1. "DES_2,DES_2" "0: ST JEP106 continuation code (refer to the..,?,?,?" line.long 0xC "MTM_PID5,MTM peripheral ID5 register" hexmask.long 0xC 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x10 "MTM_PID6,MTM peripheral ID6 register" hexmask.long 0x10 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x14 "MTM_PID7,MTM peripheral ID7 register" hexmask.long 0x14 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x18 "MTM_PID0,MTM peripheral ID0 register" hexmask.long.byte 0x18 4.--7. 1. "PART_0M,Part 0M" newline hexmask.long.byte 0x18 0.--3. 1. "PART_0L,Part 0L" line.long 0x1C "MTM_PID1,MTM peripheral ID1 register" hexmask.long.byte 0x1C 4.--7. 1. "DES_0,DES 0" newline hexmask.long.byte 0x1C 0.--3. 1. "PART_1,Part 1" line.long 0x20 "MTM_PID2,MTM peripheral ID2 register" hexmask.long.byte 0x20 4.--7. 1. "REVISION,Revision" newline bitfld.long 0x20 3. "JEDEC,JEDEC" "?,1: Indicates that a JEDEC assigned value is used." newline bitfld.long 0x20 0.--2. "DES_1,DES 1" "?,?,2: ST JEP106 identification code [7] bits[6:4].,?,?,?,?,?" line.long 0x24 "MTM_PID3,MTM peripheral ID3 register" hexmask.long.byte 0x24 4.--7. 1. "REVAND,REVAND" newline hexmask.long.byte 0x24 0.--3. 1. "CMOD,CMOD" line.long 0x28 "MTM_CID0,MTM CS ID0 register" hexmask.long.byte 0x28 0.--7. 1. "PRMB0,Preamble 0" line.long 0x2C "MTM_CID1,MTM CS ID1 register" hexmask.long.byte 0x2C 4.--7. 1. "CLASS,Class" newline hexmask.long.byte 0x2C 0.--3. 1. "PRMB1,Preamble 1" line.long 0x30 "MTM_CID2,MTM CS ID2 register" hexmask.long.byte 0x30 0.--7. 1. "PRMB2,Preamble 2" line.long 0x34 "MTM_CID3,MTM CS ID3 register" hexmask.long.byte 0x34 0.--7. 1. "PRMB3,Preamble 3" tree.end tree "CLUSTER2_MTM_PRCTL0" base ad:0x7E026000 group.long 0x0++0x7 line.long 0x0 "MTM_EN,MTM enable register" bitfld.long 0x0 0. "MTM_ENABLE,MTM enable" "0: MTM disabled,1: MTM enabled" line.long 0x4 "MTM_TRC_EN,MTM trace enable" bitfld.long 0x4 1. "INVLD_FIFO,Invalidate FIFO" "0: Packet FIFO pointers is not invalidated old..,1: Invalidate Packet FIFO old trace data is lost." newline bitfld.long 0x4 0. "TRACE_EN,Trace Enable" "0: Trace filtering is disabled. When disabled TAG..,1: Trace filtering is enabled." group.long 0x20++0x7 line.long 0x0 "MTM_TRC_STALL_CTRL,MTM trace stall control register" hexmask.long.byte 0x0 1.--4. 1. "LEVEL,Level" newline bitfld.long 0x0 0. "STALL,Stall" "0: Backpressure form MTM does not stall the..,1: Backpressure form MTM can stall the processor or.." line.long 0x4 "MTM_TRC_ID,MTM trace ID register" hexmask.long.byte 0x4 0.--6. 1. "TRACE_ID,Trace ID value" rgroup.long 0x100++0x3 line.long 0x0 "MTM_BKP_STAT,MTM Backpressure status register" bitfld.long 0x0 1. "PCK_FIFO_FULL,Packet FIFO full" "0: Packet FIFO buffer not full.,1: Packet FIFO buffer full Backpressure scenario is.." group.long 0x200++0x3 line.long 0x0 "MTM_TAG_RGN_CONFIG,MTM TAG RAM configuration register" bitfld.long 0x0 2. "TAG_RGN_C,TAG region C" "0: Region C of the TAG RAM is not used.,1: Region C of the TAG RAM is used." newline bitfld.long 0x0 1. "TAG_RGN_B,TAG region B" "0: Region B of the TAG RAM is not used.,1: Region B of the TAG RAM is used." newline bitfld.long 0x0 0. "TAG_RGN_A,TAG region A" "0: Region A of the TAG RAM is not used.,1: Region A of the TAG RAM is used." group.long 0x210++0xB line.long 0x0 "MTM_TAG_RGN_BADR_A,MTM TAG RAM base address region A register" hexmask.long.tbyte 0x0 10.--31. 1. "A_REGION_BASE_ADR,A REGION BASE ADR value" line.long 0x4 "MTM_TAG_RGN_BADR_B,MTM TAG RAM base address region B register" hexmask.long.tbyte 0x4 10.--31. 1. "B_REGION_BASE_ADR,B REGION BASE ADR value" line.long 0x8 "MTM_TAG_RGN_BADR_C,MTM TAG RAM base address region C register" hexmask.long.tbyte 0x8 10.--31. 1. "C_REGION_BASE_ADR,C REGION BASE ADR value" rgroup.long 0x220++0xF line.long 0x0 "MTM_TAG_RGN_SZ_A,MTM TAG RAM region A size register" hexmask.long.word 0x0 0.--9. 1. "RGN_A_SIZE,RGN A size value" line.long 0x4 "MTM_TAG_RGN_SZ_B,MTM TAG RAM region B size register" hexmask.long.word 0x4 0.--9. 1. "RGN_B_SIZE,RGN B size value" line.long 0x8 "MTM_TAG_RGN_SZ_C,MTM TAG RAM size C size register" hexmask.long.word 0x8 0.--9. 1. "RGN_C_SIZE,RGN C size value" line.long 0xC "MTM_TAG_RGN_STAT,MTM TAG RAM region status register" bitfld.long 0xC 2. "RGN_C_BOUND_CROSS,RGN C bound cross" "0: Region C boundary not crossed.,1: Region C boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 1. "RGN_B_BOUND_CROSS,RGN B bound cross" "0: Region B boundary not crossed.,1: Region B boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 0. "RGN_A_BOUND_CROSS,RGN A bound cross" "0: Region A boundary not crossed.,1: Region A boundary crossed due to wrong 'PAGES'.." group.long 0x230++0x7 line.long 0x0 "MTM_TAG_ADR,MTM TAG RAM address register" bitfld.long 0x0 31. "AUTO_PROG_DONE,Auto programming done goes high when updates to tag RAM are completed by MTM. Debugger must clear this bit once set. Though this bit always provides the status of latest auto increment request even when debugger did not clear the.." "0: Auto programming is not completed.,1: Auto programming is completed." newline hexmask.long.word 0x0 10.--18. 1. "PAGES,Specifies the number of consecutive TAG RAM lines needs to be updated when Auto Increment address mode is enabled. Debugger must program PAGES field to 'required number of pages - 1'." newline hexmask.long.word 0x0 1.--9. 1. "ADDRESS_PAGE,Address page" newline bitfld.long 0x0 0. "AUTO_INCR,Auto increment" "0: Auto increment of the TAG address is disabled.,1: Auto increment of the TAG address is enabled." line.long 0x4 "MTM_TAG_DATA_CONFIG,MTM TAG RAM data configuration register" bitfld.long 0x4 17. "DATA_READ_STATUS,Data read status gives read completion status against the request set in DATA_READ bit." "0: Data read is not requested or completed.,1: Data read is completed for requested read." newline bitfld.long 0x4 16. "DATA_READ,Read control bit must be set by the debugger when it needs to read TAG RAM from the address programmed in ADDRESS_PAGE field of MTM_TAG_ADR register." "0: Read command is not set.,1: Read command is set." newline bitfld.long 0x4 5.--7. "SLICE_SIZE,Specify 3 most significant bits of every TAG RAM content line called ." "0: 8 byte,1: Filtering unit,2: 32 byte,3: 64 byte,4: 128 byte,5: 256 byte,6: 512 byte,7: 1K byte" newline hexmask.long.byte 0x4 1.--4. 1. "WORD_STROBE,WORD_STROBE bits are used to enable MTM_TAG_DATA_STROBE_W[n] registers. nth bit of WORD_STROBE corresponds to nth MTM_TAG_DATA_STROBE_W[n] register. For details refer to Section89.5.2.16: MTM TAG RAM strobe word n register.." newline bitfld.long 0x4 0. "DATA_VALID,Data valid controls write to TAG RAM" "0: TAG RAM content update is disabled.,1: TAG RAM content update is enabled." group.long 0x240++0xF line.long 0x0 "MTM_TAG_DATA_STROBE_W1,MTM TAG RAM strobe word 1 register" hexmask.long 0x0 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x4 "MTM_TAG_DATA_STROBE_W2,MTM TAG RAM strobe word 2 register" hexmask.long 0x4 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x8 "MTM_TAG_DATA_STROBE_W3,MTM TAG RAM strobe word 3 register" hexmask.long 0x8 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0xC "MTM_TAG_DATA_STROBE_W4,MTM TAG RAM strobe word 4 register" hexmask.long 0xC 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." group.long 0x400++0xB line.long 0x0 "MTM_TS_EN,MTM timestamp enable register" bitfld.long 0x0 0. "TS_EN,Timestamp enable" "0: TS packet generation disabled.,1: TS packet generation enabled." line.long 0x4 "MTM_TS_WIN_CNT,MTM Timestamp window counter register" hexmask.long 0x4 0.--31. 1. "WIND_COUNTER,Timestamp window counter value" line.long 0x8 "MTM_TS_CLK_SCL,MTM Timestamp clock scaler register" hexmask.long.word 0x8 0.--8. 1. "CLK_SCALER,Clock scaler value" group.long 0x410++0xB line.long 0x0 "AL_EN,Alignment message enable register" bitfld.long 0x0 0. "AL_EN,Alignment Synchronization (A-Sync) enable" "0: A-Sync packet generation disabled.,1: A-Sync packet generation enabled." line.long 0x4 "AL_WIN_CNT,Alignment message window counter register" hexmask.long 0x4 0.--31. 1. "AL_WIND_COUNTER,Alignment synchronization messages window counter value" line.long 0x8 "AL_CLK_SCL,Alignment window counter clock scaler register" hexmask.long.word 0x8 0.--8. 1. "AL_CLK_SCALER,Clock scaler value" group.long 0xFA0++0x7 line.long 0x0 "MTM_CLAIM_TAG_SET,MTM claim TAG set register" hexmask.long.byte 0x0 0.--3. 1. "CLAIM_SET,Claim set" line.long 0x4 "MTM_CLAIM_TAG_CLR,MTM claim TAG clear register" hexmask.long.byte 0x4 0.--3. 1. "CLAIM_CLEAR,Claim clear" wgroup.long 0xFB0++0x3 line.long 0x0 "MTM_LAR,MTM lock access register" hexmask.long 0x0 0.--31. 1. "SW_KEY,Software lock key value" rgroup.long 0xFB4++0xB line.long 0x0 "MTM_LSR,MTM lock status register" bitfld.long 0x0 2. "NTT,nTT" "0: Only value: MTM_LAR register is 32 bit wide (MTM..,?" newline bitfld.long 0x0 1. "SLK,SLK returns the software lock status." "0: Accesses permitted.,1: Write accesses to control registers of the MTM.." newline bitfld.long 0x0 0. "SLI,Software Lock Implementation" "0: Software lock is not implemented: returned for..,1: Software lock is implemented: returned for all.." line.long 0x4 "MTM_AUTH_STAT,MTM authentification status register" bitfld.long 0x4 6.--7. "SNID,Secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 4.--5. "SID,Secure invasive debug" "0: Functionality not implemented.,?,?,?" newline bitfld.long 0x4 2.--3. "NSNID,Non-secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 0.--1. "NSID,Non-secure invasive debug" "0: Functionality not implemented.,?,?,?" line.long 0x8 "MTM_DEV_ARCH,MTM device architecture register" hexmask.long.word 0x8 21.--31. 1. "ARCHITECT,Defines the Architect of the component:" newline bitfld.long 0x8 20. "PRES,Presence" "?,1: Device Architecture register is present." newline hexmask.long.byte 0x8 16.--19. 1. "ARCH_REVISION,Architecture revision" newline hexmask.long.word 0x8 0.--15. 1. "ARCH_ID,Architecture ID" rgroup.long 0xFC8++0x37 line.long 0x0 "MTM_DEV_ID,MTM device ID register" hexmask.long 0x0 0.--31. 1. "FUTURE_USE,Reserved" line.long 0x4 "MTM_DEV_TYPE,MTM device type register" hexmask.long.byte 0x4 4.--7. 1. "SUB,Based on ARM©defined codes (refer to Table B2-8 in document [5])." newline hexmask.long.byte 0x4 0.--3. 1. "MAJOR,Based on ARM©defined codes (refer to Table B2-8 in document [5])." line.long 0x8 "MTM_PID4,MTM peripheral ID4 register" bitfld.long 0x8 2.--3. "SIZE,Size" "0: MTM memory map occupies 4KB.,?,?,?" newline bitfld.long 0x8 0.--1. "DES_2,DES_2" "0: ST JEP106 continuation code (refer to the..,?,?,?" line.long 0xC "MTM_PID5,MTM peripheral ID5 register" hexmask.long 0xC 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x10 "MTM_PID6,MTM peripheral ID6 register" hexmask.long 0x10 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x14 "MTM_PID7,MTM peripheral ID7 register" hexmask.long 0x14 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x18 "MTM_PID0,MTM peripheral ID0 register" hexmask.long.byte 0x18 4.--7. 1. "PART_0M,Part 0M" newline hexmask.long.byte 0x18 0.--3. 1. "PART_0L,Part 0L" line.long 0x1C "MTM_PID1,MTM peripheral ID1 register" hexmask.long.byte 0x1C 4.--7. 1. "DES_0,DES 0" newline hexmask.long.byte 0x1C 0.--3. 1. "PART_1,Part 1" line.long 0x20 "MTM_PID2,MTM peripheral ID2 register" hexmask.long.byte 0x20 4.--7. 1. "REVISION,Revision" newline bitfld.long 0x20 3. "JEDEC,JEDEC" "?,1: Indicates that a JEDEC assigned value is used." newline bitfld.long 0x20 0.--2. "DES_1,DES 1" "?,?,2: ST JEP106 identification code [7] bits[6:4].,?,?,?,?,?" line.long 0x24 "MTM_PID3,MTM peripheral ID3 register" hexmask.long.byte 0x24 4.--7. 1. "REVAND,REVAND" newline hexmask.long.byte 0x24 0.--3. 1. "CMOD,CMOD" line.long 0x28 "MTM_CID0,MTM CS ID0 register" hexmask.long.byte 0x28 0.--7. 1. "PRMB0,Preamble 0" line.long 0x2C "MTM_CID1,MTM CS ID1 register" hexmask.long.byte 0x2C 4.--7. 1. "CLASS,Class" newline hexmask.long.byte 0x2C 0.--3. 1. "PRMB1,Preamble 1" line.long 0x30 "MTM_CID2,MTM CS ID2 register" hexmask.long.byte 0x30 0.--7. 1. "PRMB2,Preamble 2" line.long 0x34 "MTM_CID3,MTM CS ID3 register" hexmask.long.byte 0x34 0.--7. 1. "PRMB3,Preamble 3" tree.end tree "CLUSTER2_MTM_PRCTL1" base ad:0x7E028000 group.long 0x0++0x7 line.long 0x0 "MTM_EN,MTM enable register" bitfld.long 0x0 0. "MTM_ENABLE,MTM enable" "0: MTM disabled,1: MTM enabled" line.long 0x4 "MTM_TRC_EN,MTM trace enable" bitfld.long 0x4 1. "INVLD_FIFO,Invalidate FIFO" "0: Packet FIFO pointers is not invalidated old..,1: Invalidate Packet FIFO old trace data is lost." newline bitfld.long 0x4 0. "TRACE_EN,Trace Enable" "0: Trace filtering is disabled. When disabled TAG..,1: Trace filtering is enabled." group.long 0x20++0x7 line.long 0x0 "MTM_TRC_STALL_CTRL,MTM trace stall control register" hexmask.long.byte 0x0 1.--4. 1. "LEVEL,Level" newline bitfld.long 0x0 0. "STALL,Stall" "0: Backpressure form MTM does not stall the..,1: Backpressure form MTM can stall the processor or.." line.long 0x4 "MTM_TRC_ID,MTM trace ID register" hexmask.long.byte 0x4 0.--6. 1. "TRACE_ID,Trace ID value" rgroup.long 0x100++0x3 line.long 0x0 "MTM_BKP_STAT,MTM Backpressure status register" bitfld.long 0x0 1. "PCK_FIFO_FULL,Packet FIFO full" "0: Packet FIFO buffer not full.,1: Packet FIFO buffer full Backpressure scenario is.." group.long 0x200++0x3 line.long 0x0 "MTM_TAG_RGN_CONFIG,MTM TAG RAM configuration register" bitfld.long 0x0 2. "TAG_RGN_C,TAG region C" "0: Region C of the TAG RAM is not used.,1: Region C of the TAG RAM is used." newline bitfld.long 0x0 1. "TAG_RGN_B,TAG region B" "0: Region B of the TAG RAM is not used.,1: Region B of the TAG RAM is used." newline bitfld.long 0x0 0. "TAG_RGN_A,TAG region A" "0: Region A of the TAG RAM is not used.,1: Region A of the TAG RAM is used." group.long 0x210++0xB line.long 0x0 "MTM_TAG_RGN_BADR_A,MTM TAG RAM base address region A register" hexmask.long.tbyte 0x0 10.--31. 1. "A_REGION_BASE_ADR,A REGION BASE ADR value" line.long 0x4 "MTM_TAG_RGN_BADR_B,MTM TAG RAM base address region B register" hexmask.long.tbyte 0x4 10.--31. 1. "B_REGION_BASE_ADR,B REGION BASE ADR value" line.long 0x8 "MTM_TAG_RGN_BADR_C,MTM TAG RAM base address region C register" hexmask.long.tbyte 0x8 10.--31. 1. "C_REGION_BASE_ADR,C REGION BASE ADR value" rgroup.long 0x220++0xF line.long 0x0 "MTM_TAG_RGN_SZ_A,MTM TAG RAM region A size register" hexmask.long.word 0x0 0.--9. 1. "RGN_A_SIZE,RGN A size value" line.long 0x4 "MTM_TAG_RGN_SZ_B,MTM TAG RAM region B size register" hexmask.long.word 0x4 0.--9. 1. "RGN_B_SIZE,RGN B size value" line.long 0x8 "MTM_TAG_RGN_SZ_C,MTM TAG RAM size C size register" hexmask.long.word 0x8 0.--9. 1. "RGN_C_SIZE,RGN C size value" line.long 0xC "MTM_TAG_RGN_STAT,MTM TAG RAM region status register" bitfld.long 0xC 2. "RGN_C_BOUND_CROSS,RGN C bound cross" "0: Region C boundary not crossed.,1: Region C boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 1. "RGN_B_BOUND_CROSS,RGN B bound cross" "0: Region B boundary not crossed.,1: Region B boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 0. "RGN_A_BOUND_CROSS,RGN A bound cross" "0: Region A boundary not crossed.,1: Region A boundary crossed due to wrong 'PAGES'.." group.long 0x230++0x7 line.long 0x0 "MTM_TAG_ADR,MTM TAG RAM address register" bitfld.long 0x0 31. "AUTO_PROG_DONE,Auto programming done goes high when updates to tag RAM are completed by MTM. Debugger must clear this bit once set. Though this bit always provides the status of latest auto increment request even when debugger did not clear the.." "0: Auto programming is not completed.,1: Auto programming is completed." newline hexmask.long.word 0x0 10.--18. 1. "PAGES,Specifies the number of consecutive TAG RAM lines needs to be updated when Auto Increment address mode is enabled. Debugger must program PAGES field to 'required number of pages - 1'." newline hexmask.long.word 0x0 1.--9. 1. "ADDRESS_PAGE,Address page" newline bitfld.long 0x0 0. "AUTO_INCR,Auto increment" "0: Auto increment of the TAG address is disabled.,1: Auto increment of the TAG address is enabled." line.long 0x4 "MTM_TAG_DATA_CONFIG,MTM TAG RAM data configuration register" bitfld.long 0x4 17. "DATA_READ_STATUS,Data read status gives read completion status against the request set in DATA_READ bit." "0: Data read is not requested or completed.,1: Data read is completed for requested read." newline bitfld.long 0x4 16. "DATA_READ,Read control bit must be set by the debugger when it needs to read TAG RAM from the address programmed in ADDRESS_PAGE field of MTM_TAG_ADR register." "0: Read command is not set.,1: Read command is set." newline bitfld.long 0x4 5.--7. "SLICE_SIZE,Specify 3 most significant bits of every TAG RAM content line called ." "0: 8 byte,1: Filtering unit,2: 32 byte,3: 64 byte,4: 128 byte,5: 256 byte,6: 512 byte,7: 1K byte" newline hexmask.long.byte 0x4 1.--4. 1. "WORD_STROBE,WORD_STROBE bits are used to enable MTM_TAG_DATA_STROBE_W[n] registers. nth bit of WORD_STROBE corresponds to nth MTM_TAG_DATA_STROBE_W[n] register. For details refer to Section89.5.2.16: MTM TAG RAM strobe word n register.." newline bitfld.long 0x4 0. "DATA_VALID,Data valid controls write to TAG RAM" "0: TAG RAM content update is disabled.,1: TAG RAM content update is enabled." group.long 0x240++0xF line.long 0x0 "MTM_TAG_DATA_STROBE_W1,MTM TAG RAM strobe word 1 register" hexmask.long 0x0 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x4 "MTM_TAG_DATA_STROBE_W2,MTM TAG RAM strobe word 2 register" hexmask.long 0x4 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x8 "MTM_TAG_DATA_STROBE_W3,MTM TAG RAM strobe word 3 register" hexmask.long 0x8 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0xC "MTM_TAG_DATA_STROBE_W4,MTM TAG RAM strobe word 4 register" hexmask.long 0xC 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." group.long 0x400++0xB line.long 0x0 "MTM_TS_EN,MTM timestamp enable register" bitfld.long 0x0 0. "TS_EN,Timestamp enable" "0: TS packet generation disabled.,1: TS packet generation enabled." line.long 0x4 "MTM_TS_WIN_CNT,MTM Timestamp window counter register" hexmask.long 0x4 0.--31. 1. "WIND_COUNTER,Timestamp window counter value" line.long 0x8 "MTM_TS_CLK_SCL,MTM Timestamp clock scaler register" hexmask.long.word 0x8 0.--8. 1. "CLK_SCALER,Clock scaler value" group.long 0x410++0xB line.long 0x0 "AL_EN,Alignment message enable register" bitfld.long 0x0 0. "AL_EN,Alignment Synchronization (A-Sync) enable" "0: A-Sync packet generation disabled.,1: A-Sync packet generation enabled." line.long 0x4 "AL_WIN_CNT,Alignment message window counter register" hexmask.long 0x4 0.--31. 1. "AL_WIND_COUNTER,Alignment synchronization messages window counter value" line.long 0x8 "AL_CLK_SCL,Alignment window counter clock scaler register" hexmask.long.word 0x8 0.--8. 1. "AL_CLK_SCALER,Clock scaler value" group.long 0xFA0++0x7 line.long 0x0 "MTM_CLAIM_TAG_SET,MTM claim TAG set register" hexmask.long.byte 0x0 0.--3. 1. "CLAIM_SET,Claim set" line.long 0x4 "MTM_CLAIM_TAG_CLR,MTM claim TAG clear register" hexmask.long.byte 0x4 0.--3. 1. "CLAIM_CLEAR,Claim clear" wgroup.long 0xFB0++0x3 line.long 0x0 "MTM_LAR,MTM lock access register" hexmask.long 0x0 0.--31. 1. "SW_KEY,Software lock key value" rgroup.long 0xFB4++0xB line.long 0x0 "MTM_LSR,MTM lock status register" bitfld.long 0x0 2. "NTT,nTT" "0: Only value: MTM_LAR register is 32 bit wide (MTM..,?" newline bitfld.long 0x0 1. "SLK,SLK returns the software lock status." "0: Accesses permitted.,1: Write accesses to control registers of the MTM.." newline bitfld.long 0x0 0. "SLI,Software Lock Implementation" "0: Software lock is not implemented: returned for..,1: Software lock is implemented: returned for all.." line.long 0x4 "MTM_AUTH_STAT,MTM authentification status register" bitfld.long 0x4 6.--7. "SNID,Secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 4.--5. "SID,Secure invasive debug" "0: Functionality not implemented.,?,?,?" newline bitfld.long 0x4 2.--3. "NSNID,Non-secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 0.--1. "NSID,Non-secure invasive debug" "0: Functionality not implemented.,?,?,?" line.long 0x8 "MTM_DEV_ARCH,MTM device architecture register" hexmask.long.word 0x8 21.--31. 1. "ARCHITECT,Defines the Architect of the component:" newline bitfld.long 0x8 20. "PRES,Presence" "?,1: Device Architecture register is present." newline hexmask.long.byte 0x8 16.--19. 1. "ARCH_REVISION,Architecture revision" newline hexmask.long.word 0x8 0.--15. 1. "ARCH_ID,Architecture ID" rgroup.long 0xFC8++0x37 line.long 0x0 "MTM_DEV_ID,MTM device ID register" hexmask.long 0x0 0.--31. 1. "FUTURE_USE,Reserved" line.long 0x4 "MTM_DEV_TYPE,MTM device type register" hexmask.long.byte 0x4 4.--7. 1. "SUB,Based on ARM©defined codes (refer to Table B2-8 in document [5])." newline hexmask.long.byte 0x4 0.--3. 1. "MAJOR,Based on ARM©defined codes (refer to Table B2-8 in document [5])." line.long 0x8 "MTM_PID4,MTM peripheral ID4 register" bitfld.long 0x8 2.--3. "SIZE,Size" "0: MTM memory map occupies 4KB.,?,?,?" newline bitfld.long 0x8 0.--1. "DES_2,DES_2" "0: ST JEP106 continuation code (refer to the..,?,?,?" line.long 0xC "MTM_PID5,MTM peripheral ID5 register" hexmask.long 0xC 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x10 "MTM_PID6,MTM peripheral ID6 register" hexmask.long 0x10 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x14 "MTM_PID7,MTM peripheral ID7 register" hexmask.long 0x14 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x18 "MTM_PID0,MTM peripheral ID0 register" hexmask.long.byte 0x18 4.--7. 1. "PART_0M,Part 0M" newline hexmask.long.byte 0x18 0.--3. 1. "PART_0L,Part 0L" line.long 0x1C "MTM_PID1,MTM peripheral ID1 register" hexmask.long.byte 0x1C 4.--7. 1. "DES_0,DES 0" newline hexmask.long.byte 0x1C 0.--3. 1. "PART_1,Part 1" line.long 0x20 "MTM_PID2,MTM peripheral ID2 register" hexmask.long.byte 0x20 4.--7. 1. "REVISION,Revision" newline bitfld.long 0x20 3. "JEDEC,JEDEC" "?,1: Indicates that a JEDEC assigned value is used." newline bitfld.long 0x20 0.--2. "DES_1,DES 1" "?,?,2: ST JEP106 identification code [7] bits[6:4].,?,?,?,?,?" line.long 0x24 "MTM_PID3,MTM peripheral ID3 register" hexmask.long.byte 0x24 4.--7. 1. "REVAND,REVAND" newline hexmask.long.byte 0x24 0.--3. 1. "CMOD,CMOD" line.long 0x28 "MTM_CID0,MTM CS ID0 register" hexmask.long.byte 0x28 0.--7. 1. "PRMB0,Preamble 0" line.long 0x2C "MTM_CID1,MTM CS ID1 register" hexmask.long.byte 0x2C 4.--7. 1. "CLASS,Class" newline hexmask.long.byte 0x2C 0.--3. 1. "PRMB1,Preamble 1" line.long 0x30 "MTM_CID2,MTM CS ID2 register" hexmask.long.byte 0x30 0.--7. 1. "PRMB2,Preamble 2" line.long 0x34 "MTM_CID3,MTM CS ID3 register" hexmask.long.byte 0x34 0.--7. 1. "PRMB3,Preamble 3" tree.end tree "SYSRAM0_MTM_PRCTL" base ad:0x7C10C000 group.long 0x0++0x7 line.long 0x0 "MTM_EN,MTM enable register" bitfld.long 0x0 0. "MTM_ENABLE,MTM enable" "0: MTM disabled,1: MTM enabled" line.long 0x4 "MTM_TRC_EN,MTM trace enable" bitfld.long 0x4 1. "INVLD_FIFO,Invalidate FIFO" "0: Packet FIFO pointers is not invalidated old..,1: Invalidate Packet FIFO old trace data is lost." newline bitfld.long 0x4 0. "TRACE_EN,Trace Enable" "0: Trace filtering is disabled. When disabled TAG..,1: Trace filtering is enabled." group.long 0x20++0x7 line.long 0x0 "MTM_TRC_STALL_CTRL,MTM trace stall control register" hexmask.long.byte 0x0 1.--4. 1. "LEVEL,Level" newline bitfld.long 0x0 0. "STALL,Stall" "0: Backpressure form MTM does not stall the..,1: Backpressure form MTM can stall the processor or.." line.long 0x4 "MTM_TRC_ID,MTM trace ID register" hexmask.long.byte 0x4 0.--6. 1. "TRACE_ID,Trace ID value" rgroup.long 0x100++0x3 line.long 0x0 "MTM_BKP_STAT,MTM Backpressure status register" bitfld.long 0x0 1. "PCK_FIFO_FULL,Packet FIFO full" "0: Packet FIFO buffer not full.,1: Packet FIFO buffer full Backpressure scenario is.." group.long 0x200++0x3 line.long 0x0 "MTM_TAG_RGN_CONFIG,MTM TAG RAM configuration register" bitfld.long 0x0 2. "TAG_RGN_C,TAG region C" "0: Region C of the TAG RAM is not used.,1: Region C of the TAG RAM is used." newline bitfld.long 0x0 1. "TAG_RGN_B,TAG region B" "0: Region B of the TAG RAM is not used.,1: Region B of the TAG RAM is used." newline bitfld.long 0x0 0. "TAG_RGN_A,TAG region A" "0: Region A of the TAG RAM is not used.,1: Region A of the TAG RAM is used." group.long 0x210++0xB line.long 0x0 "MTM_TAG_RGN_BADR_A,MTM TAG RAM base address region A register" hexmask.long.tbyte 0x0 10.--31. 1. "A_REGION_BASE_ADR,A REGION BASE ADR value" line.long 0x4 "MTM_TAG_RGN_BADR_B,MTM TAG RAM base address region B register" hexmask.long.tbyte 0x4 10.--31. 1. "B_REGION_BASE_ADR,B REGION BASE ADR value" line.long 0x8 "MTM_TAG_RGN_BADR_C,MTM TAG RAM base address region C register" hexmask.long.tbyte 0x8 10.--31. 1. "C_REGION_BASE_ADR,C REGION BASE ADR value" rgroup.long 0x220++0xF line.long 0x0 "MTM_TAG_RGN_SZ_A,MTM TAG RAM region A size register" hexmask.long.word 0x0 0.--9. 1. "RGN_A_SIZE,RGN A size value" line.long 0x4 "MTM_TAG_RGN_SZ_B,MTM TAG RAM region B size register" hexmask.long.word 0x4 0.--9. 1. "RGN_B_SIZE,RGN B size value" line.long 0x8 "MTM_TAG_RGN_SZ_C,MTM TAG RAM size C size register" hexmask.long.word 0x8 0.--9. 1. "RGN_C_SIZE,RGN C size value" line.long 0xC "MTM_TAG_RGN_STAT,MTM TAG RAM region status register" bitfld.long 0xC 2. "RGN_C_BOUND_CROSS,RGN C bound cross" "0: Region C boundary not crossed.,1: Region C boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 1. "RGN_B_BOUND_CROSS,RGN B bound cross" "0: Region B boundary not crossed.,1: Region B boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 0. "RGN_A_BOUND_CROSS,RGN A bound cross" "0: Region A boundary not crossed.,1: Region A boundary crossed due to wrong 'PAGES'.." group.long 0x230++0x7 line.long 0x0 "MTM_TAG_ADR,MTM TAG RAM address register" bitfld.long 0x0 31. "AUTO_PROG_DONE,Auto programming done goes high when updates to tag RAM are completed by MTM. Debugger must clear this bit once set. Though this bit always provides the status of latest auto increment request even when debugger did not clear the.." "0: Auto programming is not completed.,1: Auto programming is completed." newline hexmask.long.word 0x0 10.--18. 1. "PAGES,Specifies the number of consecutive TAG RAM lines needs to be updated when Auto Increment address mode is enabled. Debugger must program PAGES field to 'required number of pages - 1'." newline hexmask.long.word 0x0 1.--9. 1. "ADDRESS_PAGE,Address page" newline bitfld.long 0x0 0. "AUTO_INCR,Auto increment" "0: Auto increment of the TAG address is disabled.,1: Auto increment of the TAG address is enabled." line.long 0x4 "MTM_TAG_DATA_CONFIG,MTM TAG RAM data configuration register" bitfld.long 0x4 17. "DATA_READ_STATUS,Data read status gives read completion status against the request set in DATA_READ bit." "0: Data read is not requested or completed.,1: Data read is completed for requested read." newline bitfld.long 0x4 16. "DATA_READ,Read control bit must be set by the debugger when it needs to read TAG RAM from the address programmed in ADDRESS_PAGE field of MTM_TAG_ADR register." "0: Read command is not set.,1: Read command is set." newline bitfld.long 0x4 5.--7. "SLICE_SIZE,Specify 3 most significant bits of every TAG RAM content line called ." "0: 8 byte,1: Filtering unit,2: 32 byte,3: 64 byte,4: 128 byte,5: 256 byte,6: 512 byte,7: 1K byte" newline hexmask.long.byte 0x4 1.--4. 1. "WORD_STROBE,WORD_STROBE bits are used to enable MTM_TAG_DATA_STROBE_W[n] registers. nth bit of WORD_STROBE corresponds to nth MTM_TAG_DATA_STROBE_W[n] register. For details refer to Section89.5.2.16: MTM TAG RAM strobe word n register.." newline bitfld.long 0x4 0. "DATA_VALID,Data valid controls write to TAG RAM" "0: TAG RAM content update is disabled.,1: TAG RAM content update is enabled." group.long 0x240++0xF line.long 0x0 "MTM_TAG_DATA_STROBE_W1,MTM TAG RAM strobe word 1 register" hexmask.long 0x0 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x4 "MTM_TAG_DATA_STROBE_W2,MTM TAG RAM strobe word 2 register" hexmask.long 0x4 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x8 "MTM_TAG_DATA_STROBE_W3,MTM TAG RAM strobe word 3 register" hexmask.long 0x8 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0xC "MTM_TAG_DATA_STROBE_W4,MTM TAG RAM strobe word 4 register" hexmask.long 0xC 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." group.long 0x400++0xB line.long 0x0 "MTM_TS_EN,MTM timestamp enable register" bitfld.long 0x0 0. "TS_EN,Timestamp enable" "0: TS packet generation disabled.,1: TS packet generation enabled." line.long 0x4 "MTM_TS_WIN_CNT,MTM Timestamp window counter register" hexmask.long 0x4 0.--31. 1. "WIND_COUNTER,Timestamp window counter value" line.long 0x8 "MTM_TS_CLK_SCL,MTM Timestamp clock scaler register" hexmask.long.word 0x8 0.--8. 1. "CLK_SCALER,Clock scaler value" group.long 0x410++0xB line.long 0x0 "AL_EN,Alignment message enable register" bitfld.long 0x0 0. "AL_EN,Alignment Synchronization (A-Sync) enable" "0: A-Sync packet generation disabled.,1: A-Sync packet generation enabled." line.long 0x4 "AL_WIN_CNT,Alignment message window counter register" hexmask.long 0x4 0.--31. 1. "AL_WIND_COUNTER,Alignment synchronization messages window counter value" line.long 0x8 "AL_CLK_SCL,Alignment window counter clock scaler register" hexmask.long.word 0x8 0.--8. 1. "AL_CLK_SCALER,Clock scaler value" group.long 0xFA0++0x7 line.long 0x0 "MTM_CLAIM_TAG_SET,MTM claim TAG set register" hexmask.long.byte 0x0 0.--3. 1. "CLAIM_SET,Claim set" line.long 0x4 "MTM_CLAIM_TAG_CLR,MTM claim TAG clear register" hexmask.long.byte 0x4 0.--3. 1. "CLAIM_CLEAR,Claim clear" wgroup.long 0xFB0++0x3 line.long 0x0 "MTM_LAR,MTM lock access register" hexmask.long 0x0 0.--31. 1. "SW_KEY,Software lock key value" rgroup.long 0xFB4++0xB line.long 0x0 "MTM_LSR,MTM lock status register" bitfld.long 0x0 2. "NTT,nTT" "0: Only value: MTM_LAR register is 32 bit wide (MTM..,?" newline bitfld.long 0x0 1. "SLK,SLK returns the software lock status." "0: Accesses permitted.,1: Write accesses to control registers of the MTM.." newline bitfld.long 0x0 0. "SLI,Software Lock Implementation" "0: Software lock is not implemented: returned for..,1: Software lock is implemented: returned for all.." line.long 0x4 "MTM_AUTH_STAT,MTM authentification status register" bitfld.long 0x4 6.--7. "SNID,Secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 4.--5. "SID,Secure invasive debug" "0: Functionality not implemented.,?,?,?" newline bitfld.long 0x4 2.--3. "NSNID,Non-secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 0.--1. "NSID,Non-secure invasive debug" "0: Functionality not implemented.,?,?,?" line.long 0x8 "MTM_DEV_ARCH,MTM device architecture register" hexmask.long.word 0x8 21.--31. 1. "ARCHITECT,Defines the Architect of the component:" newline bitfld.long 0x8 20. "PRES,Presence" "?,1: Device Architecture register is present." newline hexmask.long.byte 0x8 16.--19. 1. "ARCH_REVISION,Architecture revision" newline hexmask.long.word 0x8 0.--15. 1. "ARCH_ID,Architecture ID" rgroup.long 0xFC8++0x37 line.long 0x0 "MTM_DEV_ID,MTM device ID register" hexmask.long 0x0 0.--31. 1. "FUTURE_USE,Reserved" line.long 0x4 "MTM_DEV_TYPE,MTM device type register" hexmask.long.byte 0x4 4.--7. 1. "SUB,Based on ARM©defined codes (refer to Table B2-8 in document [5])." newline hexmask.long.byte 0x4 0.--3. 1. "MAJOR,Based on ARM©defined codes (refer to Table B2-8 in document [5])." line.long 0x8 "MTM_PID4,MTM peripheral ID4 register" bitfld.long 0x8 2.--3. "SIZE,Size" "0: MTM memory map occupies 4KB.,?,?,?" newline bitfld.long 0x8 0.--1. "DES_2,DES_2" "0: ST JEP106 continuation code (refer to the..,?,?,?" line.long 0xC "MTM_PID5,MTM peripheral ID5 register" hexmask.long 0xC 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x10 "MTM_PID6,MTM peripheral ID6 register" hexmask.long 0x10 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x14 "MTM_PID7,MTM peripheral ID7 register" hexmask.long 0x14 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x18 "MTM_PID0,MTM peripheral ID0 register" hexmask.long.byte 0x18 4.--7. 1. "PART_0M,Part 0M" newline hexmask.long.byte 0x18 0.--3. 1. "PART_0L,Part 0L" line.long 0x1C "MTM_PID1,MTM peripheral ID1 register" hexmask.long.byte 0x1C 4.--7. 1. "DES_0,DES 0" newline hexmask.long.byte 0x1C 0.--3. 1. "PART_1,Part 1" line.long 0x20 "MTM_PID2,MTM peripheral ID2 register" hexmask.long.byte 0x20 4.--7. 1. "REVISION,Revision" newline bitfld.long 0x20 3. "JEDEC,JEDEC" "?,1: Indicates that a JEDEC assigned value is used." newline bitfld.long 0x20 0.--2. "DES_1,DES 1" "?,?,2: ST JEP106 identification code [7] bits[6:4].,?,?,?,?,?" line.long 0x24 "MTM_PID3,MTM peripheral ID3 register" hexmask.long.byte 0x24 4.--7. 1. "REVAND,REVAND" newline hexmask.long.byte 0x24 0.--3. 1. "CMOD,CMOD" line.long 0x28 "MTM_CID0,MTM CS ID0 register" hexmask.long.byte 0x28 0.--7. 1. "PRMB0,Preamble 0" line.long 0x2C "MTM_CID1,MTM CS ID1 register" hexmask.long.byte 0x2C 4.--7. 1. "CLASS,Class" newline hexmask.long.byte 0x2C 0.--3. 1. "PRMB1,Preamble 1" line.long 0x30 "MTM_CID2,MTM CS ID2 register" hexmask.long.byte 0x30 0.--7. 1. "PRMB2,Preamble 2" line.long 0x34 "MTM_CID3,MTM CS ID3 register" hexmask.long.byte 0x34 0.--7. 1. "PRMB3,Preamble 3" tree.end tree "SYSRAM1_MTM_PRCTL" base ad:0x7C10E000 group.long 0x0++0x7 line.long 0x0 "MTM_EN,MTM enable register" bitfld.long 0x0 0. "MTM_ENABLE,MTM enable" "0: MTM disabled,1: MTM enabled" line.long 0x4 "MTM_TRC_EN,MTM trace enable" bitfld.long 0x4 1. "INVLD_FIFO,Invalidate FIFO" "0: Packet FIFO pointers is not invalidated old..,1: Invalidate Packet FIFO old trace data is lost." newline bitfld.long 0x4 0. "TRACE_EN,Trace Enable" "0: Trace filtering is disabled. When disabled TAG..,1: Trace filtering is enabled." group.long 0x20++0x7 line.long 0x0 "MTM_TRC_STALL_CTRL,MTM trace stall control register" hexmask.long.byte 0x0 1.--4. 1. "LEVEL,Level" newline bitfld.long 0x0 0. "STALL,Stall" "0: Backpressure form MTM does not stall the..,1: Backpressure form MTM can stall the processor or.." line.long 0x4 "MTM_TRC_ID,MTM trace ID register" hexmask.long.byte 0x4 0.--6. 1. "TRACE_ID,Trace ID value" rgroup.long 0x100++0x3 line.long 0x0 "MTM_BKP_STAT,MTM Backpressure status register" bitfld.long 0x0 1. "PCK_FIFO_FULL,Packet FIFO full" "0: Packet FIFO buffer not full.,1: Packet FIFO buffer full Backpressure scenario is.." group.long 0x200++0x3 line.long 0x0 "MTM_TAG_RGN_CONFIG,MTM TAG RAM configuration register" bitfld.long 0x0 2. "TAG_RGN_C,TAG region C" "0: Region C of the TAG RAM is not used.,1: Region C of the TAG RAM is used." newline bitfld.long 0x0 1. "TAG_RGN_B,TAG region B" "0: Region B of the TAG RAM is not used.,1: Region B of the TAG RAM is used." newline bitfld.long 0x0 0. "TAG_RGN_A,TAG region A" "0: Region A of the TAG RAM is not used.,1: Region A of the TAG RAM is used." group.long 0x210++0xB line.long 0x0 "MTM_TAG_RGN_BADR_A,MTM TAG RAM base address region A register" hexmask.long.tbyte 0x0 10.--31. 1. "A_REGION_BASE_ADR,A REGION BASE ADR value" line.long 0x4 "MTM_TAG_RGN_BADR_B,MTM TAG RAM base address region B register" hexmask.long.tbyte 0x4 10.--31. 1. "B_REGION_BASE_ADR,B REGION BASE ADR value" line.long 0x8 "MTM_TAG_RGN_BADR_C,MTM TAG RAM base address region C register" hexmask.long.tbyte 0x8 10.--31. 1. "C_REGION_BASE_ADR,C REGION BASE ADR value" rgroup.long 0x220++0xF line.long 0x0 "MTM_TAG_RGN_SZ_A,MTM TAG RAM region A size register" hexmask.long.word 0x0 0.--9. 1. "RGN_A_SIZE,RGN A size value" line.long 0x4 "MTM_TAG_RGN_SZ_B,MTM TAG RAM region B size register" hexmask.long.word 0x4 0.--9. 1. "RGN_B_SIZE,RGN B size value" line.long 0x8 "MTM_TAG_RGN_SZ_C,MTM TAG RAM size C size register" hexmask.long.word 0x8 0.--9. 1. "RGN_C_SIZE,RGN C size value" line.long 0xC "MTM_TAG_RGN_STAT,MTM TAG RAM region status register" bitfld.long 0xC 2. "RGN_C_BOUND_CROSS,RGN C bound cross" "0: Region C boundary not crossed.,1: Region C boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 1. "RGN_B_BOUND_CROSS,RGN B bound cross" "0: Region B boundary not crossed.,1: Region B boundary crossed due to wrong 'PAGES'.." newline bitfld.long 0xC 0. "RGN_A_BOUND_CROSS,RGN A bound cross" "0: Region A boundary not crossed.,1: Region A boundary crossed due to wrong 'PAGES'.." group.long 0x230++0x7 line.long 0x0 "MTM_TAG_ADR,MTM TAG RAM address register" bitfld.long 0x0 31. "AUTO_PROG_DONE,Auto programming done goes high when updates to tag RAM are completed by MTM. Debugger must clear this bit once set. Though this bit always provides the status of latest auto increment request even when debugger did not clear the.." "0: Auto programming is not completed.,1: Auto programming is completed." newline hexmask.long.word 0x0 10.--18. 1. "PAGES,Specifies the number of consecutive TAG RAM lines needs to be updated when Auto Increment address mode is enabled. Debugger must program PAGES field to 'required number of pages - 1'." newline hexmask.long.word 0x0 1.--9. 1. "ADDRESS_PAGE,Address page" newline bitfld.long 0x0 0. "AUTO_INCR,Auto increment" "0: Auto increment of the TAG address is disabled.,1: Auto increment of the TAG address is enabled." line.long 0x4 "MTM_TAG_DATA_CONFIG,MTM TAG RAM data configuration register" bitfld.long 0x4 17. "DATA_READ_STATUS,Data read status gives read completion status against the request set in DATA_READ bit." "0: Data read is not requested or completed.,1: Data read is completed for requested read." newline bitfld.long 0x4 16. "DATA_READ,Read control bit must be set by the debugger when it needs to read TAG RAM from the address programmed in ADDRESS_PAGE field of MTM_TAG_ADR register." "0: Read command is not set.,1: Read command is set." newline bitfld.long 0x4 5.--7. "SLICE_SIZE,Specify 3 most significant bits of every TAG RAM content line called ." "0: 8 byte,1: Filtering unit,2: 32 byte,3: 64 byte,4: 128 byte,5: 256 byte,6: 512 byte,7: 1K byte" newline hexmask.long.byte 0x4 1.--4. 1. "WORD_STROBE,WORD_STROBE bits are used to enable MTM_TAG_DATA_STROBE_W[n] registers. nth bit of WORD_STROBE corresponds to nth MTM_TAG_DATA_STROBE_W[n] register. For details refer to Section89.5.2.16: MTM TAG RAM strobe word n register.." newline bitfld.long 0x4 0. "DATA_VALID,Data valid controls write to TAG RAM" "0: TAG RAM content update is disabled.,1: TAG RAM content update is enabled." group.long 0x240++0xF line.long 0x0 "MTM_TAG_DATA_STROBE_W1,MTM TAG RAM strobe word 1 register" hexmask.long 0x0 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x4 "MTM_TAG_DATA_STROBE_W2,MTM TAG RAM strobe word 2 register" hexmask.long 0x4 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0x8 "MTM_TAG_DATA_STROBE_W3,MTM TAG RAM strobe word 3 register" hexmask.long 0x8 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." line.long 0xC "MTM_TAG_DATA_STROBE_W4,MTM TAG RAM strobe word 4 register" hexmask.long 0xC 0.--31. 1. "TAG_DATA_CONTENT,Specify the low [31:0] low intermediate [63:32] the high intermediate [95:64] and the high [127:96] words of the address slice strobe called (see Table2557) MTM_TAG_DATA_STROBE_Wn registers to bit association)." group.long 0x400++0xB line.long 0x0 "MTM_TS_EN,MTM timestamp enable register" bitfld.long 0x0 0. "TS_EN,Timestamp enable" "0: TS packet generation disabled.,1: TS packet generation enabled." line.long 0x4 "MTM_TS_WIN_CNT,MTM Timestamp window counter register" hexmask.long 0x4 0.--31. 1. "WIND_COUNTER,Timestamp window counter value" line.long 0x8 "MTM_TS_CLK_SCL,MTM Timestamp clock scaler register" hexmask.long.word 0x8 0.--8. 1. "CLK_SCALER,Clock scaler value" group.long 0x410++0xB line.long 0x0 "AL_EN,Alignment message enable register" bitfld.long 0x0 0. "AL_EN,Alignment Synchronization (A-Sync) enable" "0: A-Sync packet generation disabled.,1: A-Sync packet generation enabled." line.long 0x4 "AL_WIN_CNT,Alignment message window counter register" hexmask.long 0x4 0.--31. 1. "AL_WIND_COUNTER,Alignment synchronization messages window counter value" line.long 0x8 "AL_CLK_SCL,Alignment window counter clock scaler register" hexmask.long.word 0x8 0.--8. 1. "AL_CLK_SCALER,Clock scaler value" group.long 0xFA0++0x7 line.long 0x0 "MTM_CLAIM_TAG_SET,MTM claim TAG set register" hexmask.long.byte 0x0 0.--3. 1. "CLAIM_SET,Claim set" line.long 0x4 "MTM_CLAIM_TAG_CLR,MTM claim TAG clear register" hexmask.long.byte 0x4 0.--3. 1. "CLAIM_CLEAR,Claim clear" wgroup.long 0xFB0++0x3 line.long 0x0 "MTM_LAR,MTM lock access register" hexmask.long 0x0 0.--31. 1. "SW_KEY,Software lock key value" rgroup.long 0xFB4++0xB line.long 0x0 "MTM_LSR,MTM lock status register" bitfld.long 0x0 2. "NTT,nTT" "0: Only value: MTM_LAR register is 32 bit wide (MTM..,?" newline bitfld.long 0x0 1. "SLK,SLK returns the software lock status." "0: Accesses permitted.,1: Write accesses to control registers of the MTM.." newline bitfld.long 0x0 0. "SLI,Software Lock Implementation" "0: Software lock is not implemented: returned for..,1: Software lock is implemented: returned for all.." line.long 0x4 "MTM_AUTH_STAT,MTM authentification status register" bitfld.long 0x4 6.--7. "SNID,Secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 4.--5. "SID,Secure invasive debug" "0: Functionality not implemented.,?,?,?" newline bitfld.long 0x4 2.--3. "NSNID,Non-secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." newline bitfld.long 0x4 0.--1. "NSID,Non-secure invasive debug" "0: Functionality not implemented.,?,?,?" line.long 0x8 "MTM_DEV_ARCH,MTM device architecture register" hexmask.long.word 0x8 21.--31. 1. "ARCHITECT,Defines the Architect of the component:" newline bitfld.long 0x8 20. "PRES,Presence" "?,1: Device Architecture register is present." newline hexmask.long.byte 0x8 16.--19. 1. "ARCH_REVISION,Architecture revision" newline hexmask.long.word 0x8 0.--15. 1. "ARCH_ID,Architecture ID" rgroup.long 0xFC8++0x37 line.long 0x0 "MTM_DEV_ID,MTM device ID register" hexmask.long 0x0 0.--31. 1. "FUTURE_USE,Reserved" line.long 0x4 "MTM_DEV_TYPE,MTM device type register" hexmask.long.byte 0x4 4.--7. 1. "SUB,Based on ARM©defined codes (refer to Table B2-8 in document [5])." newline hexmask.long.byte 0x4 0.--3. 1. "MAJOR,Based on ARM©defined codes (refer to Table B2-8 in document [5])." line.long 0x8 "MTM_PID4,MTM peripheral ID4 register" bitfld.long 0x8 2.--3. "SIZE,Size" "0: MTM memory map occupies 4KB.,?,?,?" newline bitfld.long 0x8 0.--1. "DES_2,DES_2" "0: ST JEP106 continuation code (refer to the..,?,?,?" line.long 0xC "MTM_PID5,MTM peripheral ID5 register" hexmask.long 0xC 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x10 "MTM_PID6,MTM peripheral ID6 register" hexmask.long 0x10 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x14 "MTM_PID7,MTM peripheral ID7 register" hexmask.long 0x14 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x18 "MTM_PID0,MTM peripheral ID0 register" hexmask.long.byte 0x18 4.--7. 1. "PART_0M,Part 0M" newline hexmask.long.byte 0x18 0.--3. 1. "PART_0L,Part 0L" line.long 0x1C "MTM_PID1,MTM peripheral ID1 register" hexmask.long.byte 0x1C 4.--7. 1. "DES_0,DES 0" newline hexmask.long.byte 0x1C 0.--3. 1. "PART_1,Part 1" line.long 0x20 "MTM_PID2,MTM peripheral ID2 register" hexmask.long.byte 0x20 4.--7. 1. "REVISION,Revision" newline bitfld.long 0x20 3. "JEDEC,JEDEC" "?,1: Indicates that a JEDEC assigned value is used." newline bitfld.long 0x20 0.--2. "DES_1,DES 1" "?,?,2: ST JEP106 identification code [7] bits[6:4].,?,?,?,?,?" line.long 0x24 "MTM_PID3,MTM peripheral ID3 register" hexmask.long.byte 0x24 4.--7. 1. "REVAND,REVAND" newline hexmask.long.byte 0x24 0.--3. 1. "CMOD,CMOD" line.long 0x28 "MTM_CID0,MTM CS ID0 register" hexmask.long.byte 0x28 0.--7. 1. "PRMB0,Preamble 0" line.long 0x2C "MTM_CID1,MTM CS ID1 register" hexmask.long.byte 0x2C 4.--7. 1. "CLASS,Class" newline hexmask.long.byte 0x2C 0.--3. 1. "PRMB1,Preamble 1" line.long 0x30 "MTM_CID2,MTM CS ID2 register" hexmask.long.byte 0x30 0.--7. 1. "PRMB2,Preamble 2" line.long 0x34 "MTM_CID3,MTM CS ID3 register" hexmask.long.byte 0x34 0.--7. 1. "PRMB3,Preamble 3" tree.end tree.end tree "NOC (Interconnect)" base ad:0x0 tree "DAP0_AXI" tree "DAP0_AXI_IA_DAP0_AXI_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000000 group.long 0x0++0x7F line.long 0x0 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP0_AXI_IA_DAP1_AXI_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000080 group.long 0x0++0x7F line.long 0x0 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP0_AXI_IA_DFA_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000100 group.long 0x0++0x7F line.long 0x0 "DFA_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DFA_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DFA_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "DFA_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "DFA_IN_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--12. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "DFA_IN_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "DFA_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP0_AXI_IA_DMA0_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B500000 group.long 0x0++0x3FF line.long 0x0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_PORTSEL," bitfld.long 0x270 0. "COUNTERS_7_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x274 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x284 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x288 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x28C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x290 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x294 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x298 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x29C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x2A0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x2A4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x2A8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x2AC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x2B0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x2B4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x2B8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x2BC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2C0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2C4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2C8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2CC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2D0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2D4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2D8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2DC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2E0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2E4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2E8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2EC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2F0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2F4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2F8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2FC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x300 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x304 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x308 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x30C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x310 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x314 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x318 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x31C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x320 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x324 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x328 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x32C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x330 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x334 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x338 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x33C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x340 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x344 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x348 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x34C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x350 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x354 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x358 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x35C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x360 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x364 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x368 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x36C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x370 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x374 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x378 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x37C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x380 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x384 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x388 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x38C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x390 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x394 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x398 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x39C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x3A0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x3A4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x3A8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x3AC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x3B0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x3B4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x3B8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x3BC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3C0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3C4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3C8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3CC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3D0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3D4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3D8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3DC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3E0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3E4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3E8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3EC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3F0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3F4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3F8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3FC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," tree.end tree "DAP0_AXI_IA_DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505800 group.long 0x0++0x1FF line.long 0x0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x4C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x50 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x54 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x58 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x5C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x60 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x64 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x68 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_5," hexmask.long.byte 0x7C 0.--3. 1. "THRESHOLDS_1_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x80 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_6," hexmask.long.byte 0x80 0.--3. 1. "THRESHOLDS_1_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x84 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x88 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x8C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x90 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x94 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x98 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x9C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0xA0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0xA4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0xA8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0xAC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xB0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xB4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xB8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xBC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xC0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xC4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xC8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xCC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xD0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xD4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xD8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xDC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xE0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xE4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xE8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xEC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xF0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xF4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xF8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xFC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0x100 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0x104 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0x108 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0x10C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x110 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x114 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x118 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x11C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x130 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x134 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x138 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x13C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x140 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x144 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x148 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x14C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x150 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x154 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x158 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x15C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x160 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x164 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x168 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x16C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x170 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x174 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x178 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x17C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x180 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x184 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x188 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x18C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x190 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x194 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x198 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x19C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x1A0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x1A4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x1A8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x1AC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1B0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1B4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1B8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1BC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1C0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1C4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1C8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1CC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1D0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1D4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1D8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1DC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1E0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1E4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1E8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1EC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1F0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1F4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1F8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1FC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," tree.end tree "DAP0_AXI_IA_DMA0_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B500400 group.long 0x0++0x3FF line.long 0x0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "DAP0_AXI_IA_DMA1_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B500800 group.long 0x0++0x3FF line.long 0x0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x274 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x278 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x27C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x280 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x284 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x288 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x28C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x290 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x294 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x298 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x29C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x2A0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x2A4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x2A8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x2AC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2B0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2B4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2B8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2BC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2C0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2C4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2C8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2CC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2D0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2D4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2D8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2DC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2E0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2E4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2E8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2EC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2F0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2F4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2F8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2FC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x300 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x304 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x308 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x30C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x310 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x314 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x318 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x31C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x320 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x324 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x328 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x32C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x330 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x334 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x338 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x33C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x340 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x344 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x348 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x34C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x350 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x354 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x358 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x35C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x360 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x364 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x368 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x36C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x370 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x374 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x378 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x37C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x380 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x384 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x388 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x38C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x390 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x394 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x398 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x39C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x3A0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x3A4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x3A8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x3AC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3B0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3B4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3B8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3BC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3C0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3C4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3C8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3CC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3D0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3D4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3D8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3DC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3E0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3E4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3E8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3EC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3F0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3F4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3F8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3FC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," tree.end tree "DAP0_AXI_IA_DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505A00 group.long 0x0++0x1FF line.long 0x0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x48 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x4C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x50 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x54 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x58 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x5C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x60 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x64 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x68 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_5," hexmask.long.byte 0x7C 0.--3. 1. "THRESHOLDS_1_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x80 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x84 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x88 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x8C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x90 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x94 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x98 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x9C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0xA0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0xA4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xAC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xB0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xB4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xBC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xC0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xC4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xCC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xD0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xD4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xDC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xE0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xE4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xEC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xF0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xF4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xFC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0x100 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0x104 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x108 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x10C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x110 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x114 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x118 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x11C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x130 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x134 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x138 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x13C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x140 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x144 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x148 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x14C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x150 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x154 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x158 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x15C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x160 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x164 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x168 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x16C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x170 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x174 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x178 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x17C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x180 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x184 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x188 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x18C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x190 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x194 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x198 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x19C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x1A0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x1A4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1AC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1B0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1B4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1BC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1C0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1C4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1CC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1D0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1D4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1DC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1E0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1E4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1EC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1F0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1F4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1FC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," tree.end tree "DAP0_AXI_IA_DMA1_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B500C00 group.long 0x0++0x3FF line.long 0x0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "DAP0_AXI_IA_EDMA_0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000980 group.long 0x0++0x7F line.long 0x0 "EDMA_0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP0_AXI_IA_EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001180 group.long 0x0++0x7F line.long 0x0 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP0_AXI_IA_EDMA_1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000A00 group.long 0x0++0x7F line.long 0x0 "EDMA_1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP0_AXI_IA_EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001200 group.long 0x0++0x7F line.long 0x0 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP0_AXI_IA_EDMA_2_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000A80 group.long 0x0++0x7F line.long 0x0 "EDMA_2_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_2_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_2_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_2_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_2_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP0_AXI_IA_EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001280 group.long 0x0++0x7F line.long 0x0 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP0_AXI_IA_EDMA_3_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000B00 group.long 0x0++0x7F line.long 0x0 "EDMA_3_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_3_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_3_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_3_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_3_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP0_AXI_IA_EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001300 group.long 0x0++0x7F line.long 0x0 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP0_AXI_IA_ETHER0_I_MAIN_QOSGENERATOR" base ad:0x7B000180 group.long 0x0++0x7F line.long 0x0 "ETHER0_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER0_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER0_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ETHER0_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ETHER0_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ETHER0_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ETHER0_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP0_AXI_IA_ETHER0_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000B80 group.long 0x0++0x7F line.long 0x0 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP0_AXI_IA_ETHER1_I_MAIN_QOSGENERATOR" base ad:0x7B000200 group.long 0x0++0x7F line.long 0x0 "ETHER1_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER1_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER1_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ETHER1_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ETHER1_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ETHER1_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ETHER1_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP0_AXI_IA_ETHER1_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000C00 group.long 0x0++0x7F line.long 0x0 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP0_AXI_IA_ETHR_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B501000 group.long 0x0++0x3FF line.long 0x0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x264 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x268 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x26C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x270 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x274 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x278 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x27C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x280 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x284 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x288 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x28C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x290 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x294 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x298 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x29C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2A0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2AC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2B0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2BC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2C0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2CC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2D0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2DC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2E0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2EC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2F0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2FC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x300 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x304 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x308 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x30C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x310 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x314 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x318 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x31C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x320 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x324 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x328 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x32C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x330 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x334 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x338 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x33C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x340 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x344 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x348 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x34C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x350 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x354 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x358 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x35C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x360 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x364 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x368 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x36C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x370 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x374 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x378 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x37C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x380 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x384 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x388 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x38C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x390 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x394 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x398 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x39C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3A0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3AC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3B0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3BC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3C0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3CC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3D0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3DC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3E0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3EC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3F0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3FC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," tree.end tree "DAP0_AXI_IA_ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505C00 group.long 0x0++0x1FF line.long 0x0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x44 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x48 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x4C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x50 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x54 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x58 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x5C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x60 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x64 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x68 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x80 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x84 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x88 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x8C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x90 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x94 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x98 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x9C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xA4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xA8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xAC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xB4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xB8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xBC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xC4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xC8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xCC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xD4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xD8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xDC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xE4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xE8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xEC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xF4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xF8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xFC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x100 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x104 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x108 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x10C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x110 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x114 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x118 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x11C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x130 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x134 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x138 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x13C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x140 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x144 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x148 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x14C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x150 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x154 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x158 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x15C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x160 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x164 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x168 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x16C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x170 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x174 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x178 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x17C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x180 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x184 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x188 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x18C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x190 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x194 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x198 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x19C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1A4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1A8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1AC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1B4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1B8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1BC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1C4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1C8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1CC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1D4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1D8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1DC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1E4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1E8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1EC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1F4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1F8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1FC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," tree.end tree "DAP0_AXI_IA_ETHR_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B501400 group.long 0x0++0x3FF line.long 0x0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "DAP0_AXI_IA_FLEX0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000280 group.long 0x0++0x7F line.long 0x0 "FLEX0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "FLEX0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "FLEX0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP0_AXI_IA_FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000C80 group.long 0x0++0x7F line.long 0x0 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP0_AXI_IA_FLEX1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000300 group.long 0x0++0x7F line.long 0x0 "FLEX1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "FLEX1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "FLEX1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP0_AXI_IA_FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000D00 group.long 0x0++0x7F line.long 0x0 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP0_AXI_IA_FR_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B501800 group.long 0x0++0x3FF line.long 0x0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "FR_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x264 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x268 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x26C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x270 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x274 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x278 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x27C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x280 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x284 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x288 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x28C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x290 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x294 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x298 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x29C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2A0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2AC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2B0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2BC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2C0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2CC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2D0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2DC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2E0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2EC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2F0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2FC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x300 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x304 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x308 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x30C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x310 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x314 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x318 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x31C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x320 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x324 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x328 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x32C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x330 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x334 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x338 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x33C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x340 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x344 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x348 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x34C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x350 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x354 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x358 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x35C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x360 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x364 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x368 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x36C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x370 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x374 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x378 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x37C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x380 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x384 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x388 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x38C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x390 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x394 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x398 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x39C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3A0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3AC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3B0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3BC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3C0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3CC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3D0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3DC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3E0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3EC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3F0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3FC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," tree.end tree "DAP0_AXI_IA_FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505E00 group.long 0x0++0x1FF line.long 0x0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x44 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x48 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x4C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x50 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x54 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x58 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x5C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x60 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x64 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x68 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x80 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x84 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x88 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x8C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x90 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x94 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x98 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x9C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xA4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xA8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xAC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xB4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xB8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xBC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xC4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xC8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xCC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xD4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xD8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xDC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xE4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xE8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xEC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xF4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xF8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xFC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x100 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x104 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x108 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x10C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x110 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x114 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x118 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x11C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x130 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x134 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x138 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x13C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x140 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x144 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x148 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x14C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x150 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x154 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x158 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x15C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x160 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x164 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x168 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x16C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x170 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x174 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x178 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x17C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x180 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x184 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x188 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x18C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x190 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x194 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x198 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x19C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1A4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1A8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1AC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1B4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1B8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1BC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1C4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1C8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1CC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1D4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1D8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1DC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1E4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1E8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1EC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1F4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1F8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1FC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," tree.end tree "DAP0_AXI_IA_FR_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B501C00 group.long 0x0++0x3FF line.long 0x0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "FR_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "DAP0_AXI_IA_GTM_M_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000380 group.long 0x0++0x7F line.long 0x0 "GTM_M_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "GTM_M_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "GTM_M_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "GTM_M_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "GTM_M_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "GTM_M_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "GTM_M_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP0_AXI_IA_KITE0_PACKET_PROBE_MAIN_PROBE" base ad:0x7B502000 group.long 0x0++0x3FF line.long 0x0 "KITE0_PACKET_PROBE_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE0_PACKET_PROBE_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE0_PACKET_PROBE_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE0_PACKET_PROBE_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE0_PACKET_PROBE_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE0_PACKET_PROBE_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_PORTSEL," bitfld.long 0x270 0. "COUNTERS_7_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x274 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_104," line.long 0x284 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_105," line.long 0x288 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_106," line.long 0x28C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_107," line.long 0x290 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_108," line.long 0x294 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_109," line.long 0x298 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_110," line.long 0x29C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_111," line.long 0x2A0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_112," line.long 0x2A4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_113," line.long 0x2A8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_114," line.long 0x2AC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_115," line.long 0x2B0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_116," line.long 0x2B4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_117," line.long 0x2B8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_118," line.long 0x2BC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_119," line.long 0x2C0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_120," line.long 0x2C4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_121," line.long 0x2C8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_122," line.long 0x2CC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_123," line.long 0x2D0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_124," line.long 0x2D4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_125," line.long 0x2D8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_126," line.long 0x2DC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_127," line.long 0x2E0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_128," line.long 0x2E4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_129," line.long 0x2E8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_130," line.long 0x2EC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_131," line.long 0x2F0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_132," line.long 0x2F4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_133," line.long 0x2F8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_134," line.long 0x2FC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_135," line.long 0x300 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_136," line.long 0x304 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_137," line.long 0x308 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_138," line.long 0x30C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_139," line.long 0x310 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_140," line.long 0x314 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_141," line.long 0x318 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_142," line.long 0x31C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_143," line.long 0x320 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_144," line.long 0x324 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_145," line.long 0x328 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_146," line.long 0x32C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_147," line.long 0x330 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_148," line.long 0x334 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_149," line.long 0x338 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_150," line.long 0x33C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_151," line.long 0x340 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_152," line.long 0x344 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_153," line.long 0x348 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_154," line.long 0x34C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_155," line.long 0x350 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_156," line.long 0x354 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_157," line.long 0x358 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_158," line.long 0x35C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_159," line.long 0x360 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_160," line.long 0x364 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_161," line.long 0x368 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_162," line.long 0x36C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_163," line.long 0x370 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_164," line.long 0x374 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_165," line.long 0x378 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_166," line.long 0x37C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_167," line.long 0x380 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_168," line.long 0x384 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_169," line.long 0x388 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_170," line.long 0x38C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_171," line.long 0x390 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_172," line.long 0x394 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_173," line.long 0x398 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_174," line.long 0x39C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_175," line.long 0x3A0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_176," line.long 0x3A4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_177," line.long 0x3A8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_178," line.long 0x3AC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_179," line.long 0x3B0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_180," line.long 0x3B4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_181," line.long 0x3B8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_182," line.long 0x3BC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_183," line.long 0x3C0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_184," line.long 0x3C4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_185," line.long 0x3C8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_186," line.long 0x3CC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_187," line.long 0x3D0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_188," line.long 0x3D4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_189," line.long 0x3D8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_190," line.long 0x3DC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_191," line.long 0x3E0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_192," line.long 0x3E4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_193," line.long 0x3E8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_194," line.long 0x3EC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_195," line.long 0x3F0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_196," line.long 0x3F4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_197," line.long 0x3F8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_198," line.long 0x3FC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_199," tree.end tree "DAP0_AXI_IA_KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506000 group.long 0x0++0x1FF line.long 0x0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x70 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x74 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x78 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x7C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x80 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x84 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0x88 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0x8C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0x90 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0x94 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0x98 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0x9C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xA0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xA4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xA8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xAC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xB0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xB4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xB8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xBC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xC0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xC4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xC8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xCC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xD0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xD4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xD8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xDC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xE0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xE4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0xE8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0xEC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0xF0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0xF4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0xF8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0xFC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x100 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x104 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x108 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x10C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x110 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x114 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x118 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x11C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x120 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x124 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x130 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x134 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x138 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x13C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x140 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x144 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x148 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x14C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x150 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x154 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x158 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x15C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x160 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x164 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x168 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x16C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x170 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x174 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x178 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x17C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x180 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x184 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x188 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x18C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x190 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x194 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x198 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x19C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1A0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1A4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1A8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1AC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1B0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1B4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1B8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1BC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1C0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1C4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1C8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1CC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1D0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1D4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1D8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1DC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1E0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1E4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," line.long 0x1E8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_107," line.long 0x1EC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_108," line.long 0x1F0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_109," line.long 0x1F4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_110," line.long 0x1F8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_111," line.long 0x1FC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_112," tree.end tree "DAP0_AXI_IA_KITE0_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B502400 group.long 0x0++0x3FF line.long 0x0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "DAP0_AXI_IA_KITE1_PACKET_PROBE_MAIN_PROBE" base ad:0x7B502800 group.long 0x0++0x3FF line.long 0x0 "KITE1_PACKET_PROBE_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE1_PACKET_PROBE_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE1_PACKET_PROBE_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE1_PACKET_PROBE_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE1_PACKET_PROBE_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE1_PACKET_PROBE_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_PORTSEL," bitfld.long 0x270 0. "COUNTERS_7_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x274 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_104," line.long 0x284 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_105," line.long 0x288 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_106," line.long 0x28C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_107," line.long 0x290 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_108," line.long 0x294 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_109," line.long 0x298 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_110," line.long 0x29C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_111," line.long 0x2A0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_112," line.long 0x2A4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_113," line.long 0x2A8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_114," line.long 0x2AC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_115," line.long 0x2B0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_116," line.long 0x2B4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_117," line.long 0x2B8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_118," line.long 0x2BC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_119," line.long 0x2C0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_120," line.long 0x2C4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_121," line.long 0x2C8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_122," line.long 0x2CC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_123," line.long 0x2D0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_124," line.long 0x2D4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_125," line.long 0x2D8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_126," line.long 0x2DC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_127," line.long 0x2E0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_128," line.long 0x2E4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_129," line.long 0x2E8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_130," line.long 0x2EC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_131," line.long 0x2F0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_132," line.long 0x2F4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_133," line.long 0x2F8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_134," line.long 0x2FC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_135," line.long 0x300 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_136," line.long 0x304 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_137," line.long 0x308 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_138," line.long 0x30C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_139," line.long 0x310 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_140," line.long 0x314 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_141," line.long 0x318 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_142," line.long 0x31C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_143," line.long 0x320 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_144," line.long 0x324 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_145," line.long 0x328 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_146," line.long 0x32C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_147," line.long 0x330 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_148," line.long 0x334 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_149," line.long 0x338 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_150," line.long 0x33C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_151," line.long 0x340 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_152," line.long 0x344 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_153," line.long 0x348 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_154," line.long 0x34C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_155," line.long 0x350 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_156," line.long 0x354 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_157," line.long 0x358 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_158," line.long 0x35C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_159," line.long 0x360 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_160," line.long 0x364 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_161," line.long 0x368 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_162," line.long 0x36C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_163," line.long 0x370 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_164," line.long 0x374 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_165," line.long 0x378 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_166," line.long 0x37C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_167," line.long 0x380 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_168," line.long 0x384 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_169," line.long 0x388 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_170," line.long 0x38C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_171," line.long 0x390 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_172," line.long 0x394 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_173," line.long 0x398 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_174," line.long 0x39C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_175," line.long 0x3A0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_176," line.long 0x3A4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_177," line.long 0x3A8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_178," line.long 0x3AC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_179," line.long 0x3B0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_180," line.long 0x3B4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_181," line.long 0x3B8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_182," line.long 0x3BC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_183," line.long 0x3C0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_184," line.long 0x3C4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_185," line.long 0x3C8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_186," line.long 0x3CC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_187," line.long 0x3D0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_188," line.long 0x3D4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_189," line.long 0x3D8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_190," line.long 0x3DC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_191," line.long 0x3E0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_192," line.long 0x3E4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_193," line.long 0x3E8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_194," line.long 0x3EC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_195," line.long 0x3F0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_196," line.long 0x3F4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_197," line.long 0x3F8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_198," line.long 0x3FC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_199," tree.end tree "DAP0_AXI_IA_KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506200 group.long 0x0++0x1FF line.long 0x0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x70 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x74 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x78 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x7C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x80 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x84 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0x88 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0x8C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0x90 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0x94 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0x98 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0x9C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xA0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xA4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xA8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xAC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xB0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xB4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xB8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xBC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xC0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xC4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xC8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xCC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xD0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xD4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xD8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xDC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xE0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xE4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0xE8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0xEC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0xF0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0xF4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0xF8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0xFC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x100 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x104 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x108 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x10C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x110 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x114 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x118 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x11C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x120 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x124 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x130 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x134 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x138 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x13C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x140 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x144 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x148 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x14C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x150 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x154 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x158 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x15C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x160 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x164 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x168 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x16C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x170 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x174 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x178 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x17C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x180 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x184 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x188 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x18C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x190 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x194 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x198 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x19C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1A0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1A4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1A8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1AC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1B0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1B4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1B8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1BC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1C0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1C4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1C8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1CC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1D0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1D4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1D8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1DC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1E0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1E4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," line.long 0x1E8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_107," line.long 0x1EC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_108," line.long 0x1F0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_109," line.long 0x1F4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_110," line.long 0x1F8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_111," line.long 0x1FC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_112," tree.end tree "DAP0_AXI_IA_KITE1_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B502C00 group.long 0x0++0x3FF line.long 0x0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "DAP0_AXI_IA_KITE2_PACKET_PROBE_MAIN_PROBE" base ad:0x7B503000 group.long 0x0++0x3FF line.long 0x0 "KITE2_PACKET_PROBE_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE2_PACKET_PROBE_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE2_PACKET_PROBE_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE2_PACKET_PROBE_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE2_PACKET_PROBE_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE2_PACKET_PROBE_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_211," tree.end tree "DAP0_AXI_IA_KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506800 group.long 0x0++0x7F line.long 0x0 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x40 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x44 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x48 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x4C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x50 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x54 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x58 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x5C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x60 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x64 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x68 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x6C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x6C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x70 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x70 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x74 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x74 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x78 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x78 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x7C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," tree.end tree "DAP0_AXI_IA_KITE2_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B503400 group.long 0x0++0x3FF line.long 0x0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "DAP0_AXI_IA_NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000400 group.long 0x0++0x7F line.long 0x0 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP0_AXI_IA_NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000D80 group.long 0x0++0x7F line.long 0x0 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP0_AXI_IA_NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000480 group.long 0x0++0x7F line.long 0x0 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP0_AXI_IA_NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000E00 group.long 0x0++0x7F line.long 0x0 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP0_AXI_IA_NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000500 group.long 0x0++0x7F line.long 0x0 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP0_AXI_IA_NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000E80 group.long 0x0++0x7F line.long 0x0 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP0_AXI_IA_OBSERVER_HSM_MAIN_ERRORLOGGER_0" base ad:0x7B506A80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "DAP0_AXI_IA_OBSERVER_KITE0_MAIN_ERRORLOGGER_0" base ad:0x7B506B00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "DAP0_AXI_IA_OBSERVER_KITE1_MAIN_ERRORLOGGER_0" base ad:0x7B506B80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "DAP0_AXI_IA_OBSERVER_KITE2_MAIN_ERRORLOGGER_0" base ad:0x7B506C00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "DAP0_AXI_IA_OBSERVER_MAIN0_MAIN_ATBENDPOINT" base ad:0x7B506900 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ATBID," hexmask.long.byte 0x8 0.--6. 1. "ATBID,ATB AtId" line.long 0xC "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ATBEN," bitfld.long 0xC 0. "ATBEN,ATB Unit Enable" "0,1" line.long 0x10 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_SYNCPERIOD," hexmask.long.byte 0x10 0.--4. 1. "SYNCPERIOD,ATB Synchro Period" line.long 0x14 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_00," line.long 0x18 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_01," line.long 0x1C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_02," line.long 0x20 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_03," line.long 0x24 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_04," line.long 0x28 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_05," line.long 0x2C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_06," line.long 0x30 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_07," line.long 0x34 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_08," line.long 0x38 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_09," line.long 0x3C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_10," line.long 0x40 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_11," line.long 0x44 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_12," line.long 0x48 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_13," line.long 0x4C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_14," line.long 0x50 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_15," line.long 0x54 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_16," line.long 0x58 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_17," line.long 0x5C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_18," line.long 0x60 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_19," line.long 0x64 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_20," line.long 0x68 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_21," line.long 0x6C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_22," line.long 0x70 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_23," line.long 0x74 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_24," line.long 0x78 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_25," line.long 0x7C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_26," tree.end tree "DAP0_AXI_IA_OBSERVER_MAIN0_MAIN_ERRORLOGGER_0" base ad:0x7B506C80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "DAP0_AXI_IA_OBSERVER_MAIN1_MAIN_ATBENDPOINT" base ad:0x7B506980 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ATBID," hexmask.long.byte 0x8 0.--6. 1. "ATBID,ATB AtId" line.long 0xC "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ATBEN," bitfld.long 0xC 0. "ATBEN,ATB Unit Enable" "0,1" line.long 0x10 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_SYNCPERIOD," hexmask.long.byte 0x10 0.--4. 1. "SYNCPERIOD,ATB Synchro Period" line.long 0x14 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_00," line.long 0x18 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_01," line.long 0x1C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_02," line.long 0x20 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_03," line.long 0x24 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_04," line.long 0x28 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_05," line.long 0x2C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_06," line.long 0x30 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_07," line.long 0x34 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_08," line.long 0x38 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_09," line.long 0x3C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_10," line.long 0x40 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_11," line.long 0x44 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_12," line.long 0x48 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_13," line.long 0x4C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_14," line.long 0x50 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_15," line.long 0x54 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_16," line.long 0x58 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_17," line.long 0x5C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_18," line.long 0x60 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_19," line.long 0x64 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_20," line.long 0x68 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_21," line.long 0x6C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_22," line.long 0x70 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_23," line.long 0x74 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_24," line.long 0x78 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_25," line.long 0x7C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_26," tree.end tree "DAP0_AXI_IA_OBSERVER_MAIN1_MAIN_ERRORLOGGER_0" base ad:0x7B506D00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "DAP0_AXI_IA_OBSERVER_PCIE_MAIN_ATBENDPOINT" base ad:0x7B506A00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_PCIE_MAIN_ATBENDPOINT_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_PCIE_MAIN_ATBENDPOINT_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_PCIE_MAIN_ATBENDPOINT_ATBID," hexmask.long.byte 0x8 0.--6. 1. "ATBID,ATB AtId" line.long 0xC "OBSERVER_PCIE_MAIN_ATBENDPOINT_ATBEN," bitfld.long 0xC 0. "ATBEN,ATB Unit Enable" "0,1" line.long 0x10 "OBSERVER_PCIE_MAIN_ATBENDPOINT_SYNCPERIOD," hexmask.long.byte 0x10 0.--4. 1. "SYNCPERIOD,ATB Synchro Period" line.long 0x14 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_00," line.long 0x18 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_01," line.long 0x1C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_02," line.long 0x20 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_03," line.long 0x24 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_04," line.long 0x28 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_05," line.long 0x2C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_06," line.long 0x30 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_07," line.long 0x34 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_08," line.long 0x38 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_09," line.long 0x3C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_10," line.long 0x40 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_11," line.long 0x44 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_12," line.long 0x48 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_13," line.long 0x4C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_14," line.long 0x50 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_15," line.long 0x54 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_16," line.long 0x58 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_17," line.long 0x5C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_18," line.long 0x60 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_19," line.long 0x64 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_20," line.long 0x68 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_21," line.long 0x6C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_22," line.long 0x70 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_23," line.long 0x74 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_24," line.long 0x78 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_25," line.long 0x7C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_26," tree.end tree "DAP0_AXI_IA_OBSERVER_PCIE_MAIN_ERRORLOGGER_0" base ad:0x7B506D80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "DAP0_AXI_IA_PCIE_0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000580 group.long 0x0++0x7F line.long 0x0 "PCIE_0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "PCIE_0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "PCIE_0_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "PCIE_0_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "PCIE_0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP0_AXI_IA_PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000F00 group.long 0x0++0x7F line.long 0x0 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP0_AXI_IA_PCIE_1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000600 group.long 0x0++0x7F line.long 0x0 "PCIE_1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "PCIE_1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "PCIE_1_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "PCIE_1_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "PCIE_1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP0_AXI_IA_PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000F80 group.long 0x0++0x7F line.long 0x0 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP0_AXI_IA_PCIE_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B503800 group.long 0x0++0x3FF line.long 0x0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x234 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x238 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x23C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x240 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x244 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x248 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x24C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x250 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x254 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x258 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x25C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x260 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x264 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x268 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x26C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x270 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x274 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x278 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x27C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x280 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x284 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x288 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x28C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x290 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x294 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x298 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x29C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2A0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2A4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2A8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2AC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2B0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2B4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2B8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2BC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2C0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2C4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2C8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2CC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x2D0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x2D4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x2D8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x2DC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x2E0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x2E4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x2E8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x2EC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x2F0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x2F4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x2F8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x2FC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x300 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x304 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x308 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x30C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x310 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x314 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x318 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x31C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x320 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x324 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x328 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x32C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x330 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x334 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x338 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x33C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x340 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x344 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x348 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x34C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x350 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x354 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x358 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x35C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x360 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x364 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x368 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x36C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x370 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x374 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x378 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x37C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x380 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x384 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x388 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x38C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x390 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x394 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x398 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x39C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3A0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3A4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3A8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3AC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3B0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3B4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3B8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3BC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3C0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3C4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3C8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3CC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," line.long 0x3D0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_208," line.long 0x3D4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_209," line.long 0x3D8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_210," line.long 0x3DC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_211," line.long 0x3E0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_212," line.long 0x3E4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_213," line.long 0x3E8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_214," line.long 0x3EC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_215," line.long 0x3F0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_216," line.long 0x3F4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_217," line.long 0x3F8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_218," line.long 0x3FC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_219," tree.end tree "DAP0_AXI_IA_PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506880 group.long 0x0++0x7F line.long 0x0 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x38 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x3C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x40 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x44 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x48 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x6C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x70 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x70 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x74 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x74 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x78 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x78 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x7C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," tree.end tree "DAP0_AXI_IA_PCIE_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B503C00 group.long 0x0++0x3FF line.long 0x0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "DAP0_AXI_IA_POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER" base ad:0x7B506E00 group.long 0x0++0x7F line.long 0x0 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT0," hexmask.long 0x8 0.--31. 1. "MISSIONFAULT0,MissionFault0 register" line.long 0xC "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT1," hexmask.long 0xC 0.--31. 1. "MISSIONFAULT1,MissionFault1 register" line.long 0x10 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT2," hexmask.long 0x10 0.--31. 1. "MISSIONFAULT2,MissionFault2 register" line.long 0x14 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT3," hexmask.long 0x14 0.--31. 1. "MISSIONFAULT3,MissionFault3 register" line.long 0x18 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT0," hexmask.long 0x18 0.--31. 1. "LATENTFAULT0,LatentFault0 register" line.long 0x1C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT1," hexmask.long 0x1C 0.--31. 1. "LATENTFAULT1,LatentFault1 register" line.long 0x20 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT2," hexmask.long 0x20 0.--31. 1. "LATENTFAULT2,LatentFault2 register" line.long 0x24 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT3," hexmask.long 0x24 0.--31. 1. "LATENTFAULT3,LatentFault3 register" line.long 0x28 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_FAULTS," bitfld.long 0x28 1. "MISSIONFAULT,Mission Fault" "0,1" bitfld.long 0x28 0. "LATENTFAULT,Latent Fault" "0,1" line.long 0x2C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_INTEN," bitfld.long 0x2C 1. "MISSIONFAULTEN,MissionFault Interrupt enable" "0,1" bitfld.long 0x2C 0. "BISTDONEEN,BistDone Interrupt enable" "0,1" line.long 0x30 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_INTCLR," bitfld.long 0x30 1. "MISSIONFAULTCLR,Clear Mission Fault" "0,1" bitfld.long 0x30 0. "LATENTFAULTCLR,Clear Latent Fault" "0,1" line.long 0x34 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTCTL," bitfld.long 0x34 1. "BISTDONECLR,Clear BistDone" "0,1" bitfld.long 0x34 0. "BISTSTART,Start Bist sequence" "0,1" line.long 0x38 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTDONE," bitfld.long 0x38 1. "MISSIONMODE,Mission Mode Status" "0,1" bitfld.long 0x38 0. "BISTDONE,BistDone Status" "0,1" line.long 0x3C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO1," hexmask.long.word 0x3C 0.--15. 1. "BISTTO1,BistTimeOut register" line.long 0x40 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO2," hexmask.long.byte 0x40 0.--7. 1. "BISTTO2,BistTimeOut register" line.long 0x44 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_00," line.long 0x48 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_01," line.long 0x4C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_02," line.long 0x50 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_03," line.long 0x54 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_04," line.long 0x58 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_05," line.long 0x5C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_06," line.long 0x60 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_07," line.long 0x64 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_08," line.long 0x68 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_09," line.long 0x6C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_10," line.long 0x70 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_11," line.long 0x74 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_12," line.long 0x78 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_13," line.long 0x7C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_14," tree.end tree "DAP0_AXI_IA_POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER" base ad:0x7B506E80 group.long 0x0++0x7F line.long 0x0 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT0," hexmask.long 0x8 0.--31. 1. "MISSIONFAULT0,MissionFault0 register" line.long 0xC "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT1," hexmask.long 0xC 0.--31. 1. "MISSIONFAULT1,MissionFault1 register" line.long 0x10 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT2," hexmask.long 0x10 0.--31. 1. "MISSIONFAULT2,MissionFault2 register" line.long 0x14 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT3," hexmask.long 0x14 0.--31. 1. "MISSIONFAULT3,MissionFault3 register" line.long 0x18 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT0," hexmask.long 0x18 0.--31. 1. "LATENTFAULT0,LatentFault0 register" line.long 0x1C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT1," hexmask.long 0x1C 0.--31. 1. "LATENTFAULT1,LatentFault1 register" line.long 0x20 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT2," hexmask.long 0x20 0.--31. 1. "LATENTFAULT2,LatentFault2 register" line.long 0x24 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT3," hexmask.long 0x24 0.--31. 1. "LATENTFAULT3,LatentFault3 register" line.long 0x28 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_FAULTS," bitfld.long 0x28 1. "MISSIONFAULT,Mission Fault" "0,1" bitfld.long 0x28 0. "LATENTFAULT,Latent Fault" "0,1" line.long 0x2C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_INTEN," bitfld.long 0x2C 1. "MISSIONFAULTEN,MissionFault Interrupt enable" "0,1" bitfld.long 0x2C 0. "BISTDONEEN,BistDone Interrupt enable" "0,1" line.long 0x30 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_INTCLR," bitfld.long 0x30 1. "MISSIONFAULTCLR,Clear Mission Fault" "0,1" bitfld.long 0x30 0. "LATENTFAULTCLR,Clear Latent Fault" "0,1" line.long 0x34 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTCTL," bitfld.long 0x34 1. "BISTDONECLR,Clear BistDone" "0,1" bitfld.long 0x34 0. "BISTSTART,Start Bist sequence" "0,1" line.long 0x38 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTDONE," bitfld.long 0x38 1. "MISSIONMODE,Mission Mode Status" "0,1" bitfld.long 0x38 0. "BISTDONE,BistDone Status" "0,1" line.long 0x3C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO1," hexmask.long.word 0x3C 0.--15. 1. "BISTTO1,BistTimeOut register" line.long 0x40 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO2," hexmask.long.byte 0x40 0.--7. 1. "BISTTO2,BistTimeOut register" line.long 0x44 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_00," line.long 0x48 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_01," line.long 0x4C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_02," line.long 0x50 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_03," line.long 0x54 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_04," line.long 0x58 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_05," line.long 0x5C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_06," line.long 0x60 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_07," line.long 0x64 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_08," line.long 0x68 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_09," line.long 0x6C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_10," line.long 0x70 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_11," line.long 0x74 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_12," line.long 0x78 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_13," line.long 0x7C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_14," tree.end tree "DAP0_AXI_IA_SDMMC_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000680 group.long 0x0++0x7F line.long 0x0 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP0_AXI_IA_SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001000 group.long 0x0++0x7F line.long 0x0 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP0_AXI_IA_SDMMC_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B504000 group.long 0x0++0x3FF line.long 0x0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x14 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x34 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x3C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x4C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x50 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x54 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x58 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x5C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x60 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x64 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x68 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x6C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x70 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x74 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x78 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x7C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x80 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x90 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x98 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0x9C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xB8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xBC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xC8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xCC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xD8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xDC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xE8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xEC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xF8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0xFC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x100 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x104 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x108 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x10C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x110 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x114 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x118 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x11C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x120 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x124 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x128 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x12C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x130 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x134 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x138 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x13C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x140 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x144 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x148 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x14C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x150 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x154 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x158 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x15C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x160 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x164 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x168 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x16C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x170 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x174 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x178 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x17C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x180 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x184 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x188 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x18C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x190 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x194 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x198 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x19C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1A8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1AC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1B8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1BC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1C8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1CC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1D8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1DC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1E8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1EC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1F8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x1FC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x200 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x204 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x214 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x224 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x234 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x244 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x254 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x264 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x274 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x284 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x288 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x28C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x290 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x294 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x298 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x29C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2A8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2AC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2B8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2BC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2C8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2CC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2D8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2DC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2E8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2EC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2F8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x2FC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x300 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x304 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x308 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x30C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x310 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x314 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x318 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x31C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x320 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x324 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x328 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x32C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x330 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x334 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x338 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x33C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x340 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x344 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x348 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x34C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x350 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x354 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x358 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x35C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x360 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x364 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x368 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x36C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x370 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x374 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x378 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x37C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x380 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x384 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x388 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x38C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x390 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x394 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x398 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x39C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3A8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3AC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3B8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3BC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3C8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3CC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3D8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3DC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3E8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3EC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3F8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," line.long 0x3FC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_208," tree.end tree "DAP0_AXI_IA_SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506400 group.long 0x0++0x1FF line.long 0x0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x70 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x74 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x78 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x7C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x80 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x84 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0x88 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0x8C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0x90 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0x94 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0x98 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0x9C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xA0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xA4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xA8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xAC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xB0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xB4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xB8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xBC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xC0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xC4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xC8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xCC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xD0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xD4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xD8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xDC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xE0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xE4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0xE8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0xEC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0xF0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0xF4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0xF8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0xFC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x100 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x104 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x108 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x10C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x110 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x114 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x118 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x11C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x120 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x124 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x130 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x134 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x138 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x13C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x140 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x144 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x148 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x14C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x150 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x154 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x158 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x15C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x160 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x164 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x168 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x16C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x170 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x174 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x178 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x17C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x180 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x184 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x188 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x18C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x190 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x194 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x198 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x19C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1A0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1A4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1A8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1AC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1B0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1B4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1B8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1BC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1C0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1C4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1C8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1CC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1D0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1D4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1D8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1DC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1E0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1E4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," line.long 0x1E8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_107," line.long 0x1EC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_108," line.long 0x1F0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_109," line.long 0x1F4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_110," line.long 0x1F8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_111," line.long 0x1FC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_112," tree.end tree "DAP0_AXI_IA_SDMMC_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B504400 group.long 0x0++0x3FF line.long 0x0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x14 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x34 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x3C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x4C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x50 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x54 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x58 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x5C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x60 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x64 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x68 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x6C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x70 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x74 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x78 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x7C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x80 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x90 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x98 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0x9C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xB8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xBC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xC8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xCC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xD8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xDC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xE8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xEC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xF8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0xFC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x100 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x104 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x108 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x10C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x110 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x114 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x118 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x11C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x120 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x124 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x128 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x12C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x130 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x134 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x138 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x13C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x140 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x144 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x148 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x14C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x150 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x154 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x158 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x15C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x160 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x164 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x168 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x16C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x170 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x174 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x178 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x17C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x180 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x184 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x188 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x18C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x190 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x194 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x198 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x19C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1A8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1AC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1B8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1BC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1C8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1CC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1D8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1DC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1E8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1EC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1F8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x1FC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x200 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x204 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x214 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x218 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x21C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x220 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x224 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x228 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x22C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x230 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x234 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x238 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x23C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x240 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x244 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x248 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x24C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x250 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x254 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x258 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x25C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x260 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x264 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x268 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x26C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x270 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x274 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x278 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x27C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x280 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x284 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x288 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x28C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x290 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x294 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x298 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x29C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2A4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2A8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2AC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2B4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2B8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2BC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2C4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2C8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2CC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2D4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2D8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2DC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2E4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2E8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2EC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2F4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x2F8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x2FC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x300 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x304 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x308 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x30C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x310 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x314 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x318 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x31C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x320 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x324 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x328 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x32C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x330 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x334 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x338 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x33C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x340 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x344 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x348 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x34C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x350 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x354 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x358 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x35C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x360 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x364 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x368 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x36C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x370 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x374 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x378 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x37C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x380 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x384 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x388 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x38C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x390 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x394 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x398 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x39C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3A4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3A8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3AC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3B4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3B8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3BC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3C4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3C8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3CC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3D4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3D8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3DC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3E4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3E8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3EC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3F4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," line.long 0x3F8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_228," line.long 0x3FC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_229," tree.end tree "DAP0_AXI_IA_SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000700 group.long 0x0++0x7F line.long 0x0 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP0_AXI_IA_SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000780 group.long 0x0++0x7F line.long 0x0 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP0_AXI_IA_SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000800 group.long 0x0++0x7F line.long 0x0 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP0_AXI_IA_SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B504800 group.long 0x0++0x3FF line.long 0x0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "DAP0_AXI_IA_SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B504C00 group.long 0x0++0x3FF line.long 0x0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "DAP0_AXI_IA_ZIPW0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000880 group.long 0x0++0x7F line.long 0x0 "ZIPW0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ZIPW0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ZIPW0_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ZIPW0_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ZIPW0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP0_AXI_IA_ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001080 group.long 0x0++0x7F line.long 0x0 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP0_AXI_IA_ZIPW1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000900 group.long 0x0++0x7F line.long 0x0 "ZIPW1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ZIPW1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ZIPW1_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ZIPW1_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ZIPW1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP0_AXI_IA_ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001100 group.long 0x0++0x7F line.long 0x0 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP0_AXI_IA_ZIPW_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B505000 group.long 0x0++0x3FF line.long 0x0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x264 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x268 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x26C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x270 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x274 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x278 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x27C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x280 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x284 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x288 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x28C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x290 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x294 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x298 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x29C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2A0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2AC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2B0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2BC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2C0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2CC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2D0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2DC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2E0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2EC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2F0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2FC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x300 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x304 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x308 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x30C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x310 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x314 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x318 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x31C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x320 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x324 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x328 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x32C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x330 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x334 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x338 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x33C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x340 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x344 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x348 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x34C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x350 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x354 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x358 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x35C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x360 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x364 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x368 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x36C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x370 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x374 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x378 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x37C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x380 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x384 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x388 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x38C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x390 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x394 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x398 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x39C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3A0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3AC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3B0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3BC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3C0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3CC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3D0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3DC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3E0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3EC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3F0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3FC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," tree.end tree "DAP0_AXI_IA_ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506600 group.long 0x0++0x1FF line.long 0x0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x44 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x48 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x4C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x50 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x54 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x58 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x5C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x60 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x64 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x68 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x80 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x84 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x88 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x8C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x90 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x94 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x98 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x9C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xA4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xA8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xAC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xB4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xB8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xBC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xC4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xC8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xCC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xD4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xD8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xDC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xE4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xE8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xEC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xF4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xF8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xFC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x100 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x104 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x108 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x10C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x110 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x114 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x118 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x11C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x130 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x134 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x138 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x13C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x140 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x144 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x148 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x14C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x150 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x154 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x158 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x15C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x160 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x164 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x168 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x16C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x170 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x174 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x178 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x17C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x180 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x184 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x188 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x18C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x190 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x194 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x198 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x19C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1A4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1A8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1AC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1B4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1B8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1BC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1C4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1C8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1CC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1D4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1D8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1DC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1E4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1E8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1EC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1F4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1F8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1FC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," tree.end tree "DAP0_AXI_IA_ZIPW_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B505400 group.long 0x0++0x3FF line.long 0x0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree.end tree "DAP1_AXI" tree "DAP1_AXI_IA_DAP0_AXI_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000000 group.long 0x0++0x7F line.long 0x0 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP1_AXI_IA_DAP1_AXI_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000080 group.long 0x0++0x7F line.long 0x0 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP1_AXI_IA_DFA_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000100 group.long 0x0++0x7F line.long 0x0 "DFA_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DFA_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DFA_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "DFA_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "DFA_IN_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--12. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "DFA_IN_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "DFA_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP1_AXI_IA_DMA0_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B500000 group.long 0x0++0x3FF line.long 0x0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_PORTSEL," bitfld.long 0x270 0. "COUNTERS_7_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x274 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x284 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x288 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x28C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x290 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x294 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x298 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x29C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x2A0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x2A4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x2A8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x2AC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x2B0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x2B4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x2B8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x2BC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2C0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2C4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2C8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2CC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2D0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2D4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2D8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2DC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2E0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2E4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2E8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2EC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2F0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2F4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2F8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2FC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x300 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x304 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x308 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x30C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x310 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x314 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x318 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x31C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x320 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x324 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x328 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x32C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x330 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x334 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x338 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x33C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x340 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x344 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x348 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x34C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x350 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x354 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x358 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x35C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x360 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x364 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x368 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x36C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x370 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x374 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x378 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x37C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x380 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x384 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x388 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x38C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x390 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x394 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x398 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x39C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x3A0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x3A4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x3A8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x3AC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x3B0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x3B4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x3B8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x3BC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3C0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3C4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3C8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3CC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3D0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3D4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3D8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3DC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3E0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3E4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3E8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3EC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3F0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3F4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3F8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3FC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," tree.end tree "DAP1_AXI_IA_DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505800 group.long 0x0++0x1FF line.long 0x0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x4C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x50 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x54 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x58 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x5C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x60 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x64 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x68 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_5," hexmask.long.byte 0x7C 0.--3. 1. "THRESHOLDS_1_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x80 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_6," hexmask.long.byte 0x80 0.--3. 1. "THRESHOLDS_1_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x84 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x88 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x8C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x90 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x94 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x98 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x9C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0xA0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0xA4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0xA8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0xAC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xB0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xB4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xB8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xBC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xC0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xC4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xC8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xCC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xD0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xD4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xD8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xDC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xE0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xE4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xE8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xEC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xF0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xF4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xF8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xFC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0x100 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0x104 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0x108 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0x10C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x110 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x114 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x118 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x11C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x130 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x134 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x138 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x13C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x140 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x144 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x148 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x14C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x150 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x154 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x158 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x15C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x160 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x164 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x168 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x16C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x170 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x174 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x178 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x17C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x180 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x184 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x188 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x18C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x190 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x194 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x198 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x19C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x1A0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x1A4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x1A8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x1AC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1B0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1B4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1B8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1BC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1C0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1C4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1C8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1CC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1D0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1D4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1D8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1DC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1E0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1E4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1E8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1EC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1F0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1F4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1F8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1FC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," tree.end tree "DAP1_AXI_IA_DMA0_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B500400 group.long 0x0++0x3FF line.long 0x0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "DAP1_AXI_IA_DMA1_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B500800 group.long 0x0++0x3FF line.long 0x0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x274 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x278 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x27C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x280 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x284 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x288 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x28C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x290 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x294 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x298 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x29C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x2A0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x2A4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x2A8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x2AC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2B0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2B4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2B8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2BC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2C0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2C4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2C8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2CC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2D0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2D4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2D8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2DC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2E0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2E4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2E8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2EC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2F0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2F4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2F8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2FC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x300 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x304 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x308 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x30C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x310 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x314 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x318 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x31C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x320 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x324 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x328 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x32C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x330 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x334 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x338 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x33C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x340 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x344 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x348 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x34C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x350 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x354 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x358 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x35C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x360 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x364 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x368 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x36C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x370 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x374 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x378 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x37C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x380 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x384 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x388 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x38C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x390 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x394 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x398 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x39C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x3A0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x3A4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x3A8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x3AC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3B0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3B4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3B8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3BC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3C0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3C4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3C8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3CC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3D0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3D4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3D8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3DC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3E0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3E4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3E8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3EC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3F0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3F4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3F8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3FC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," tree.end tree "DAP1_AXI_IA_DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505A00 group.long 0x0++0x1FF line.long 0x0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x48 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x4C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x50 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x54 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x58 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x5C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x60 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x64 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x68 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_5," hexmask.long.byte 0x7C 0.--3. 1. "THRESHOLDS_1_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x80 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x84 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x88 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x8C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x90 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x94 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x98 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x9C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0xA0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0xA4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xAC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xB0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xB4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xBC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xC0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xC4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xCC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xD0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xD4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xDC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xE0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xE4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xEC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xF0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xF4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xFC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0x100 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0x104 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x108 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x10C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x110 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x114 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x118 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x11C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x130 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x134 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x138 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x13C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x140 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x144 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x148 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x14C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x150 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x154 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x158 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x15C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x160 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x164 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x168 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x16C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x170 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x174 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x178 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x17C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x180 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x184 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x188 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x18C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x190 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x194 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x198 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x19C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x1A0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x1A4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1AC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1B0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1B4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1BC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1C0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1C4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1CC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1D0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1D4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1DC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1E0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1E4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1EC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1F0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1F4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1FC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," tree.end tree "DAP1_AXI_IA_DMA1_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B500C00 group.long 0x0++0x3FF line.long 0x0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "DAP1_AXI_IA_EDMA_0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000980 group.long 0x0++0x7F line.long 0x0 "EDMA_0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP1_AXI_IA_EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001180 group.long 0x0++0x7F line.long 0x0 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP1_AXI_IA_EDMA_1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000A00 group.long 0x0++0x7F line.long 0x0 "EDMA_1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP1_AXI_IA_EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001200 group.long 0x0++0x7F line.long 0x0 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP1_AXI_IA_EDMA_2_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000A80 group.long 0x0++0x7F line.long 0x0 "EDMA_2_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_2_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_2_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_2_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_2_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP1_AXI_IA_EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001280 group.long 0x0++0x7F line.long 0x0 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP1_AXI_IA_EDMA_3_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000B00 group.long 0x0++0x7F line.long 0x0 "EDMA_3_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_3_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_3_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_3_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_3_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP1_AXI_IA_EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001300 group.long 0x0++0x7F line.long 0x0 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP1_AXI_IA_ETHER0_I_MAIN_QOSGENERATOR" base ad:0x7B000180 group.long 0x0++0x7F line.long 0x0 "ETHER0_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER0_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER0_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ETHER0_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ETHER0_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ETHER0_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ETHER0_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP1_AXI_IA_ETHER0_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000B80 group.long 0x0++0x7F line.long 0x0 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP1_AXI_IA_ETHER1_I_MAIN_QOSGENERATOR" base ad:0x7B000200 group.long 0x0++0x7F line.long 0x0 "ETHER1_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER1_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER1_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ETHER1_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ETHER1_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ETHER1_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ETHER1_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP1_AXI_IA_ETHER1_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000C00 group.long 0x0++0x7F line.long 0x0 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP1_AXI_IA_ETHR_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B501000 group.long 0x0++0x3FF line.long 0x0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x264 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x268 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x26C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x270 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x274 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x278 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x27C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x280 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x284 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x288 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x28C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x290 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x294 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x298 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x29C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2A0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2AC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2B0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2BC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2C0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2CC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2D0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2DC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2E0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2EC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2F0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2FC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x300 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x304 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x308 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x30C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x310 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x314 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x318 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x31C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x320 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x324 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x328 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x32C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x330 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x334 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x338 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x33C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x340 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x344 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x348 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x34C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x350 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x354 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x358 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x35C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x360 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x364 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x368 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x36C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x370 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x374 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x378 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x37C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x380 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x384 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x388 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x38C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x390 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x394 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x398 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x39C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3A0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3AC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3B0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3BC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3C0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3CC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3D0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3DC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3E0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3EC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3F0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3FC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," tree.end tree "DAP1_AXI_IA_ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505C00 group.long 0x0++0x1FF line.long 0x0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x44 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x48 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x4C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x50 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x54 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x58 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x5C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x60 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x64 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x68 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x80 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x84 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x88 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x8C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x90 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x94 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x98 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x9C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xA4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xA8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xAC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xB4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xB8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xBC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xC4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xC8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xCC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xD4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xD8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xDC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xE4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xE8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xEC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xF4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xF8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xFC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x100 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x104 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x108 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x10C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x110 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x114 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x118 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x11C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x130 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x134 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x138 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x13C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x140 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x144 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x148 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x14C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x150 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x154 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x158 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x15C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x160 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x164 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x168 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x16C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x170 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x174 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x178 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x17C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x180 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x184 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x188 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x18C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x190 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x194 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x198 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x19C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1A4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1A8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1AC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1B4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1B8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1BC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1C4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1C8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1CC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1D4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1D8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1DC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1E4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1E8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1EC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1F4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1F8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1FC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," tree.end tree "DAP1_AXI_IA_ETHR_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B501400 group.long 0x0++0x3FF line.long 0x0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "DAP1_AXI_IA_FLEX0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000280 group.long 0x0++0x7F line.long 0x0 "FLEX0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "FLEX0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "FLEX0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP1_AXI_IA_FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000C80 group.long 0x0++0x7F line.long 0x0 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP1_AXI_IA_FLEX1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000300 group.long 0x0++0x7F line.long 0x0 "FLEX1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "FLEX1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "FLEX1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP1_AXI_IA_FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000D00 group.long 0x0++0x7F line.long 0x0 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP1_AXI_IA_FR_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B501800 group.long 0x0++0x3FF line.long 0x0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "FR_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x264 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x268 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x26C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x270 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x274 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x278 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x27C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x280 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x284 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x288 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x28C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x290 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x294 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x298 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x29C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2A0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2AC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2B0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2BC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2C0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2CC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2D0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2DC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2E0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2EC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2F0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2FC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x300 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x304 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x308 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x30C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x310 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x314 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x318 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x31C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x320 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x324 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x328 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x32C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x330 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x334 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x338 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x33C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x340 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x344 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x348 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x34C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x350 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x354 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x358 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x35C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x360 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x364 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x368 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x36C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x370 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x374 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x378 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x37C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x380 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x384 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x388 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x38C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x390 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x394 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x398 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x39C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3A0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3AC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3B0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3BC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3C0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3CC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3D0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3DC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3E0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3EC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3F0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3FC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," tree.end tree "DAP1_AXI_IA_FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505E00 group.long 0x0++0x1FF line.long 0x0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x44 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x48 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x4C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x50 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x54 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x58 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x5C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x60 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x64 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x68 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x80 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x84 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x88 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x8C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x90 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x94 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x98 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x9C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xA4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xA8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xAC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xB4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xB8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xBC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xC4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xC8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xCC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xD4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xD8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xDC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xE4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xE8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xEC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xF4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xF8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xFC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x100 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x104 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x108 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x10C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x110 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x114 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x118 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x11C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x130 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x134 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x138 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x13C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x140 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x144 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x148 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x14C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x150 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x154 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x158 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x15C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x160 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x164 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x168 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x16C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x170 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x174 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x178 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x17C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x180 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x184 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x188 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x18C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x190 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x194 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x198 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x19C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1A4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1A8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1AC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1B4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1B8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1BC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1C4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1C8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1CC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1D4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1D8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1DC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1E4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1E8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1EC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1F4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1F8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1FC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," tree.end tree "DAP1_AXI_IA_FR_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B501C00 group.long 0x0++0x3FF line.long 0x0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "FR_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "DAP1_AXI_IA_GTM_M_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000380 group.long 0x0++0x7F line.long 0x0 "GTM_M_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "GTM_M_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "GTM_M_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "GTM_M_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "GTM_M_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "GTM_M_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "GTM_M_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP1_AXI_IA_KITE0_PACKET_PROBE_MAIN_PROBE" base ad:0x7B502000 group.long 0x0++0x3FF line.long 0x0 "KITE0_PACKET_PROBE_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE0_PACKET_PROBE_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE0_PACKET_PROBE_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE0_PACKET_PROBE_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE0_PACKET_PROBE_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE0_PACKET_PROBE_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_PORTSEL," bitfld.long 0x270 0. "COUNTERS_7_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x274 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_104," line.long 0x284 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_105," line.long 0x288 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_106," line.long 0x28C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_107," line.long 0x290 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_108," line.long 0x294 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_109," line.long 0x298 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_110," line.long 0x29C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_111," line.long 0x2A0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_112," line.long 0x2A4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_113," line.long 0x2A8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_114," line.long 0x2AC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_115," line.long 0x2B0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_116," line.long 0x2B4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_117," line.long 0x2B8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_118," line.long 0x2BC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_119," line.long 0x2C0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_120," line.long 0x2C4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_121," line.long 0x2C8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_122," line.long 0x2CC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_123," line.long 0x2D0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_124," line.long 0x2D4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_125," line.long 0x2D8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_126," line.long 0x2DC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_127," line.long 0x2E0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_128," line.long 0x2E4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_129," line.long 0x2E8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_130," line.long 0x2EC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_131," line.long 0x2F0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_132," line.long 0x2F4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_133," line.long 0x2F8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_134," line.long 0x2FC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_135," line.long 0x300 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_136," line.long 0x304 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_137," line.long 0x308 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_138," line.long 0x30C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_139," line.long 0x310 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_140," line.long 0x314 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_141," line.long 0x318 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_142," line.long 0x31C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_143," line.long 0x320 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_144," line.long 0x324 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_145," line.long 0x328 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_146," line.long 0x32C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_147," line.long 0x330 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_148," line.long 0x334 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_149," line.long 0x338 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_150," line.long 0x33C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_151," line.long 0x340 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_152," line.long 0x344 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_153," line.long 0x348 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_154," line.long 0x34C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_155," line.long 0x350 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_156," line.long 0x354 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_157," line.long 0x358 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_158," line.long 0x35C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_159," line.long 0x360 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_160," line.long 0x364 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_161," line.long 0x368 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_162," line.long 0x36C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_163," line.long 0x370 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_164," line.long 0x374 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_165," line.long 0x378 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_166," line.long 0x37C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_167," line.long 0x380 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_168," line.long 0x384 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_169," line.long 0x388 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_170," line.long 0x38C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_171," line.long 0x390 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_172," line.long 0x394 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_173," line.long 0x398 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_174," line.long 0x39C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_175," line.long 0x3A0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_176," line.long 0x3A4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_177," line.long 0x3A8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_178," line.long 0x3AC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_179," line.long 0x3B0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_180," line.long 0x3B4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_181," line.long 0x3B8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_182," line.long 0x3BC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_183," line.long 0x3C0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_184," line.long 0x3C4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_185," line.long 0x3C8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_186," line.long 0x3CC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_187," line.long 0x3D0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_188," line.long 0x3D4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_189," line.long 0x3D8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_190," line.long 0x3DC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_191," line.long 0x3E0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_192," line.long 0x3E4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_193," line.long 0x3E8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_194," line.long 0x3EC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_195," line.long 0x3F0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_196," line.long 0x3F4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_197," line.long 0x3F8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_198," line.long 0x3FC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_199," tree.end tree "DAP1_AXI_IA_KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506000 group.long 0x0++0x1FF line.long 0x0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x70 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x74 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x78 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x7C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x80 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x84 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0x88 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0x8C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0x90 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0x94 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0x98 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0x9C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xA0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xA4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xA8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xAC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xB0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xB4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xB8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xBC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xC0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xC4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xC8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xCC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xD0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xD4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xD8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xDC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xE0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xE4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0xE8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0xEC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0xF0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0xF4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0xF8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0xFC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x100 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x104 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x108 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x10C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x110 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x114 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x118 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x11C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x120 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x124 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x130 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x134 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x138 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x13C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x140 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x144 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x148 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x14C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x150 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x154 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x158 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x15C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x160 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x164 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x168 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x16C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x170 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x174 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x178 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x17C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x180 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x184 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x188 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x18C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x190 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x194 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x198 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x19C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1A0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1A4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1A8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1AC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1B0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1B4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1B8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1BC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1C0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1C4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1C8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1CC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1D0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1D4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1D8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1DC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1E0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1E4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," line.long 0x1E8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_107," line.long 0x1EC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_108," line.long 0x1F0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_109," line.long 0x1F4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_110," line.long 0x1F8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_111," line.long 0x1FC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_112," tree.end tree "DAP1_AXI_IA_KITE0_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B502400 group.long 0x0++0x3FF line.long 0x0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "DAP1_AXI_IA_KITE1_PACKET_PROBE_MAIN_PROBE" base ad:0x7B502800 group.long 0x0++0x3FF line.long 0x0 "KITE1_PACKET_PROBE_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE1_PACKET_PROBE_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE1_PACKET_PROBE_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE1_PACKET_PROBE_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE1_PACKET_PROBE_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE1_PACKET_PROBE_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_PORTSEL," bitfld.long 0x270 0. "COUNTERS_7_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x274 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_104," line.long 0x284 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_105," line.long 0x288 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_106," line.long 0x28C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_107," line.long 0x290 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_108," line.long 0x294 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_109," line.long 0x298 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_110," line.long 0x29C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_111," line.long 0x2A0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_112," line.long 0x2A4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_113," line.long 0x2A8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_114," line.long 0x2AC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_115," line.long 0x2B0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_116," line.long 0x2B4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_117," line.long 0x2B8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_118," line.long 0x2BC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_119," line.long 0x2C0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_120," line.long 0x2C4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_121," line.long 0x2C8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_122," line.long 0x2CC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_123," line.long 0x2D0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_124," line.long 0x2D4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_125," line.long 0x2D8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_126," line.long 0x2DC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_127," line.long 0x2E0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_128," line.long 0x2E4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_129," line.long 0x2E8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_130," line.long 0x2EC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_131," line.long 0x2F0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_132," line.long 0x2F4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_133," line.long 0x2F8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_134," line.long 0x2FC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_135," line.long 0x300 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_136," line.long 0x304 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_137," line.long 0x308 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_138," line.long 0x30C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_139," line.long 0x310 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_140," line.long 0x314 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_141," line.long 0x318 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_142," line.long 0x31C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_143," line.long 0x320 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_144," line.long 0x324 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_145," line.long 0x328 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_146," line.long 0x32C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_147," line.long 0x330 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_148," line.long 0x334 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_149," line.long 0x338 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_150," line.long 0x33C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_151," line.long 0x340 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_152," line.long 0x344 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_153," line.long 0x348 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_154," line.long 0x34C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_155," line.long 0x350 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_156," line.long 0x354 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_157," line.long 0x358 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_158," line.long 0x35C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_159," line.long 0x360 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_160," line.long 0x364 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_161," line.long 0x368 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_162," line.long 0x36C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_163," line.long 0x370 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_164," line.long 0x374 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_165," line.long 0x378 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_166," line.long 0x37C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_167," line.long 0x380 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_168," line.long 0x384 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_169," line.long 0x388 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_170," line.long 0x38C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_171," line.long 0x390 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_172," line.long 0x394 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_173," line.long 0x398 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_174," line.long 0x39C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_175," line.long 0x3A0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_176," line.long 0x3A4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_177," line.long 0x3A8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_178," line.long 0x3AC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_179," line.long 0x3B0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_180," line.long 0x3B4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_181," line.long 0x3B8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_182," line.long 0x3BC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_183," line.long 0x3C0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_184," line.long 0x3C4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_185," line.long 0x3C8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_186," line.long 0x3CC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_187," line.long 0x3D0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_188," line.long 0x3D4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_189," line.long 0x3D8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_190," line.long 0x3DC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_191," line.long 0x3E0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_192," line.long 0x3E4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_193," line.long 0x3E8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_194," line.long 0x3EC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_195," line.long 0x3F0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_196," line.long 0x3F4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_197," line.long 0x3F8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_198," line.long 0x3FC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_199," tree.end tree "DAP1_AXI_IA_KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506200 group.long 0x0++0x1FF line.long 0x0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x70 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x74 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x78 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x7C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x80 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x84 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0x88 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0x8C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0x90 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0x94 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0x98 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0x9C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xA0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xA4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xA8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xAC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xB0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xB4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xB8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xBC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xC0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xC4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xC8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xCC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xD0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xD4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xD8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xDC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xE0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xE4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0xE8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0xEC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0xF0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0xF4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0xF8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0xFC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x100 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x104 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x108 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x10C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x110 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x114 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x118 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x11C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x120 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x124 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x130 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x134 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x138 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x13C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x140 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x144 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x148 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x14C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x150 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x154 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x158 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x15C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x160 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x164 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x168 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x16C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x170 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x174 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x178 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x17C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x180 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x184 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x188 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x18C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x190 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x194 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x198 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x19C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1A0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1A4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1A8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1AC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1B0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1B4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1B8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1BC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1C0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1C4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1C8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1CC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1D0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1D4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1D8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1DC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1E0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1E4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," line.long 0x1E8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_107," line.long 0x1EC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_108," line.long 0x1F0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_109," line.long 0x1F4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_110," line.long 0x1F8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_111," line.long 0x1FC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_112," tree.end tree "DAP1_AXI_IA_KITE1_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B502C00 group.long 0x0++0x3FF line.long 0x0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "DAP1_AXI_IA_KITE2_PACKET_PROBE_MAIN_PROBE" base ad:0x7B503000 group.long 0x0++0x3FF line.long 0x0 "KITE2_PACKET_PROBE_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE2_PACKET_PROBE_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE2_PACKET_PROBE_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE2_PACKET_PROBE_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE2_PACKET_PROBE_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE2_PACKET_PROBE_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_211," tree.end tree "DAP1_AXI_IA_KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506800 group.long 0x0++0x7F line.long 0x0 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x40 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x44 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x48 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x4C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x50 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x54 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x58 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x5C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x60 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x64 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x68 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x6C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x6C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x70 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x70 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x74 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x74 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x78 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x78 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x7C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," tree.end tree "DAP1_AXI_IA_KITE2_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B503400 group.long 0x0++0x3FF line.long 0x0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "DAP1_AXI_IA_NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000400 group.long 0x0++0x7F line.long 0x0 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP1_AXI_IA_NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000D80 group.long 0x0++0x7F line.long 0x0 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP1_AXI_IA_NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000480 group.long 0x0++0x7F line.long 0x0 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP1_AXI_IA_NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000E00 group.long 0x0++0x7F line.long 0x0 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP1_AXI_IA_NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000500 group.long 0x0++0x7F line.long 0x0 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP1_AXI_IA_NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000E80 group.long 0x0++0x7F line.long 0x0 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP1_AXI_IA_OBSERVER_HSM_MAIN_ERRORLOGGER_0" base ad:0x7B506A80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "DAP1_AXI_IA_OBSERVER_KITE0_MAIN_ERRORLOGGER_0" base ad:0x7B506B00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "DAP1_AXI_IA_OBSERVER_KITE1_MAIN_ERRORLOGGER_0" base ad:0x7B506B80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "DAP1_AXI_IA_OBSERVER_KITE2_MAIN_ERRORLOGGER_0" base ad:0x7B506C00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "DAP1_AXI_IA_OBSERVER_MAIN0_MAIN_ATBENDPOINT" base ad:0x7B506900 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ATBID," hexmask.long.byte 0x8 0.--6. 1. "ATBID,ATB AtId" line.long 0xC "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ATBEN," bitfld.long 0xC 0. "ATBEN,ATB Unit Enable" "0,1" line.long 0x10 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_SYNCPERIOD," hexmask.long.byte 0x10 0.--4. 1. "SYNCPERIOD,ATB Synchro Period" line.long 0x14 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_00," line.long 0x18 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_01," line.long 0x1C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_02," line.long 0x20 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_03," line.long 0x24 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_04," line.long 0x28 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_05," line.long 0x2C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_06," line.long 0x30 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_07," line.long 0x34 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_08," line.long 0x38 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_09," line.long 0x3C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_10," line.long 0x40 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_11," line.long 0x44 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_12," line.long 0x48 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_13," line.long 0x4C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_14," line.long 0x50 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_15," line.long 0x54 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_16," line.long 0x58 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_17," line.long 0x5C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_18," line.long 0x60 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_19," line.long 0x64 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_20," line.long 0x68 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_21," line.long 0x6C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_22," line.long 0x70 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_23," line.long 0x74 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_24," line.long 0x78 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_25," line.long 0x7C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_26," tree.end tree "DAP1_AXI_IA_OBSERVER_MAIN0_MAIN_ERRORLOGGER_0" base ad:0x7B506C80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "DAP1_AXI_IA_OBSERVER_MAIN1_MAIN_ATBENDPOINT" base ad:0x7B506980 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ATBID," hexmask.long.byte 0x8 0.--6. 1. "ATBID,ATB AtId" line.long 0xC "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ATBEN," bitfld.long 0xC 0. "ATBEN,ATB Unit Enable" "0,1" line.long 0x10 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_SYNCPERIOD," hexmask.long.byte 0x10 0.--4. 1. "SYNCPERIOD,ATB Synchro Period" line.long 0x14 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_00," line.long 0x18 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_01," line.long 0x1C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_02," line.long 0x20 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_03," line.long 0x24 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_04," line.long 0x28 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_05," line.long 0x2C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_06," line.long 0x30 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_07," line.long 0x34 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_08," line.long 0x38 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_09," line.long 0x3C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_10," line.long 0x40 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_11," line.long 0x44 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_12," line.long 0x48 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_13," line.long 0x4C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_14," line.long 0x50 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_15," line.long 0x54 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_16," line.long 0x58 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_17," line.long 0x5C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_18," line.long 0x60 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_19," line.long 0x64 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_20," line.long 0x68 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_21," line.long 0x6C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_22," line.long 0x70 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_23," line.long 0x74 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_24," line.long 0x78 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_25," line.long 0x7C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_26," tree.end tree "DAP1_AXI_IA_OBSERVER_MAIN1_MAIN_ERRORLOGGER_0" base ad:0x7B506D00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "DAP1_AXI_IA_OBSERVER_PCIE_MAIN_ATBENDPOINT" base ad:0x7B506A00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_PCIE_MAIN_ATBENDPOINT_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_PCIE_MAIN_ATBENDPOINT_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_PCIE_MAIN_ATBENDPOINT_ATBID," hexmask.long.byte 0x8 0.--6. 1. "ATBID,ATB AtId" line.long 0xC "OBSERVER_PCIE_MAIN_ATBENDPOINT_ATBEN," bitfld.long 0xC 0. "ATBEN,ATB Unit Enable" "0,1" line.long 0x10 "OBSERVER_PCIE_MAIN_ATBENDPOINT_SYNCPERIOD," hexmask.long.byte 0x10 0.--4. 1. "SYNCPERIOD,ATB Synchro Period" line.long 0x14 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_00," line.long 0x18 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_01," line.long 0x1C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_02," line.long 0x20 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_03," line.long 0x24 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_04," line.long 0x28 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_05," line.long 0x2C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_06," line.long 0x30 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_07," line.long 0x34 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_08," line.long 0x38 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_09," line.long 0x3C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_10," line.long 0x40 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_11," line.long 0x44 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_12," line.long 0x48 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_13," line.long 0x4C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_14," line.long 0x50 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_15," line.long 0x54 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_16," line.long 0x58 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_17," line.long 0x5C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_18," line.long 0x60 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_19," line.long 0x64 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_20," line.long 0x68 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_21," line.long 0x6C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_22," line.long 0x70 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_23," line.long 0x74 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_24," line.long 0x78 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_25," line.long 0x7C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_26," tree.end tree "DAP1_AXI_IA_OBSERVER_PCIE_MAIN_ERRORLOGGER_0" base ad:0x7B506D80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "DAP1_AXI_IA_PCIE_0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000580 group.long 0x0++0x7F line.long 0x0 "PCIE_0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "PCIE_0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "PCIE_0_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "PCIE_0_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "PCIE_0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP1_AXI_IA_PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000F00 group.long 0x0++0x7F line.long 0x0 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP1_AXI_IA_PCIE_1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000600 group.long 0x0++0x7F line.long 0x0 "PCIE_1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "PCIE_1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "PCIE_1_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "PCIE_1_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "PCIE_1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP1_AXI_IA_PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000F80 group.long 0x0++0x7F line.long 0x0 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP1_AXI_IA_PCIE_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B503800 group.long 0x0++0x3FF line.long 0x0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x234 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x238 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x23C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x240 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x244 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x248 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x24C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x250 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x254 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x258 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x25C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x260 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x264 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x268 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x26C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x270 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x274 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x278 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x27C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x280 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x284 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x288 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x28C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x290 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x294 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x298 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x29C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2A0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2A4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2A8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2AC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2B0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2B4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2B8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2BC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2C0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2C4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2C8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2CC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x2D0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x2D4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x2D8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x2DC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x2E0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x2E4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x2E8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x2EC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x2F0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x2F4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x2F8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x2FC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x300 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x304 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x308 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x30C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x310 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x314 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x318 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x31C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x320 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x324 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x328 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x32C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x330 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x334 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x338 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x33C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x340 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x344 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x348 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x34C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x350 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x354 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x358 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x35C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x360 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x364 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x368 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x36C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x370 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x374 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x378 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x37C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x380 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x384 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x388 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x38C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x390 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x394 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x398 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x39C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3A0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3A4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3A8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3AC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3B0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3B4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3B8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3BC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3C0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3C4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3C8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3CC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," line.long 0x3D0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_208," line.long 0x3D4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_209," line.long 0x3D8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_210," line.long 0x3DC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_211," line.long 0x3E0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_212," line.long 0x3E4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_213," line.long 0x3E8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_214," line.long 0x3EC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_215," line.long 0x3F0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_216," line.long 0x3F4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_217," line.long 0x3F8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_218," line.long 0x3FC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_219," tree.end tree "DAP1_AXI_IA_PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506880 group.long 0x0++0x7F line.long 0x0 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x38 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x3C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x40 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x44 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x48 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x6C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x70 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x70 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x74 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x74 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x78 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x78 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x7C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," tree.end tree "DAP1_AXI_IA_PCIE_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B503C00 group.long 0x0++0x3FF line.long 0x0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "DAP1_AXI_IA_POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER" base ad:0x7B506E00 group.long 0x0++0x7F line.long 0x0 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT0," hexmask.long 0x8 0.--31. 1. "MISSIONFAULT0,MissionFault0 register" line.long 0xC "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT1," hexmask.long 0xC 0.--31. 1. "MISSIONFAULT1,MissionFault1 register" line.long 0x10 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT2," hexmask.long 0x10 0.--31. 1. "MISSIONFAULT2,MissionFault2 register" line.long 0x14 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT3," hexmask.long 0x14 0.--31. 1. "MISSIONFAULT3,MissionFault3 register" line.long 0x18 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT0," hexmask.long 0x18 0.--31. 1. "LATENTFAULT0,LatentFault0 register" line.long 0x1C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT1," hexmask.long 0x1C 0.--31. 1. "LATENTFAULT1,LatentFault1 register" line.long 0x20 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT2," hexmask.long 0x20 0.--31. 1. "LATENTFAULT2,LatentFault2 register" line.long 0x24 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT3," hexmask.long 0x24 0.--31. 1. "LATENTFAULT3,LatentFault3 register" line.long 0x28 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_FAULTS," bitfld.long 0x28 1. "MISSIONFAULT,Mission Fault" "0,1" bitfld.long 0x28 0. "LATENTFAULT,Latent Fault" "0,1" line.long 0x2C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_INTEN," bitfld.long 0x2C 1. "MISSIONFAULTEN,MissionFault Interrupt enable" "0,1" bitfld.long 0x2C 0. "BISTDONEEN,BistDone Interrupt enable" "0,1" line.long 0x30 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_INTCLR," bitfld.long 0x30 1. "MISSIONFAULTCLR,Clear Mission Fault" "0,1" bitfld.long 0x30 0. "LATENTFAULTCLR,Clear Latent Fault" "0,1" line.long 0x34 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTCTL," bitfld.long 0x34 1. "BISTDONECLR,Clear BistDone" "0,1" bitfld.long 0x34 0. "BISTSTART,Start Bist sequence" "0,1" line.long 0x38 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTDONE," bitfld.long 0x38 1. "MISSIONMODE,Mission Mode Status" "0,1" bitfld.long 0x38 0. "BISTDONE,BistDone Status" "0,1" line.long 0x3C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO1," hexmask.long.word 0x3C 0.--15. 1. "BISTTO1,BistTimeOut register" line.long 0x40 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO2," hexmask.long.byte 0x40 0.--7. 1. "BISTTO2,BistTimeOut register" line.long 0x44 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_00," line.long 0x48 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_01," line.long 0x4C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_02," line.long 0x50 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_03," line.long 0x54 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_04," line.long 0x58 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_05," line.long 0x5C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_06," line.long 0x60 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_07," line.long 0x64 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_08," line.long 0x68 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_09," line.long 0x6C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_10," line.long 0x70 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_11," line.long 0x74 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_12," line.long 0x78 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_13," line.long 0x7C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_14," tree.end tree "DAP1_AXI_IA_POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER" base ad:0x7B506E80 group.long 0x0++0x7F line.long 0x0 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT0," hexmask.long 0x8 0.--31. 1. "MISSIONFAULT0,MissionFault0 register" line.long 0xC "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT1," hexmask.long 0xC 0.--31. 1. "MISSIONFAULT1,MissionFault1 register" line.long 0x10 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT2," hexmask.long 0x10 0.--31. 1. "MISSIONFAULT2,MissionFault2 register" line.long 0x14 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT3," hexmask.long 0x14 0.--31. 1. "MISSIONFAULT3,MissionFault3 register" line.long 0x18 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT0," hexmask.long 0x18 0.--31. 1. "LATENTFAULT0,LatentFault0 register" line.long 0x1C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT1," hexmask.long 0x1C 0.--31. 1. "LATENTFAULT1,LatentFault1 register" line.long 0x20 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT2," hexmask.long 0x20 0.--31. 1. "LATENTFAULT2,LatentFault2 register" line.long 0x24 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT3," hexmask.long 0x24 0.--31. 1. "LATENTFAULT3,LatentFault3 register" line.long 0x28 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_FAULTS," bitfld.long 0x28 1. "MISSIONFAULT,Mission Fault" "0,1" bitfld.long 0x28 0. "LATENTFAULT,Latent Fault" "0,1" line.long 0x2C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_INTEN," bitfld.long 0x2C 1. "MISSIONFAULTEN,MissionFault Interrupt enable" "0,1" bitfld.long 0x2C 0. "BISTDONEEN,BistDone Interrupt enable" "0,1" line.long 0x30 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_INTCLR," bitfld.long 0x30 1. "MISSIONFAULTCLR,Clear Mission Fault" "0,1" bitfld.long 0x30 0. "LATENTFAULTCLR,Clear Latent Fault" "0,1" line.long 0x34 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTCTL," bitfld.long 0x34 1. "BISTDONECLR,Clear BistDone" "0,1" bitfld.long 0x34 0. "BISTSTART,Start Bist sequence" "0,1" line.long 0x38 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTDONE," bitfld.long 0x38 1. "MISSIONMODE,Mission Mode Status" "0,1" bitfld.long 0x38 0. "BISTDONE,BistDone Status" "0,1" line.long 0x3C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO1," hexmask.long.word 0x3C 0.--15. 1. "BISTTO1,BistTimeOut register" line.long 0x40 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO2," hexmask.long.byte 0x40 0.--7. 1. "BISTTO2,BistTimeOut register" line.long 0x44 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_00," line.long 0x48 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_01," line.long 0x4C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_02," line.long 0x50 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_03," line.long 0x54 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_04," line.long 0x58 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_05," line.long 0x5C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_06," line.long 0x60 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_07," line.long 0x64 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_08," line.long 0x68 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_09," line.long 0x6C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_10," line.long 0x70 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_11," line.long 0x74 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_12," line.long 0x78 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_13," line.long 0x7C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_14," tree.end tree "DAP1_AXI_IA_SDMMC_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000680 group.long 0x0++0x7F line.long 0x0 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP1_AXI_IA_SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001000 group.long 0x0++0x7F line.long 0x0 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP1_AXI_IA_SDMMC_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B504000 group.long 0x0++0x3FF line.long 0x0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x14 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x34 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x3C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x4C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x50 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x54 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x58 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x5C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x60 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x64 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x68 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x6C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x70 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x74 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x78 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x7C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x80 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x90 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x98 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0x9C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xB8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xBC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xC8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xCC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xD8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xDC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xE8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xEC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xF8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0xFC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x100 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x104 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x108 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x10C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x110 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x114 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x118 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x11C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x120 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x124 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x128 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x12C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x130 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x134 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x138 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x13C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x140 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x144 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x148 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x14C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x150 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x154 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x158 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x15C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x160 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x164 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x168 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x16C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x170 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x174 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x178 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x17C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x180 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x184 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x188 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x18C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x190 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x194 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x198 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x19C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1A8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1AC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1B8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1BC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1C8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1CC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1D8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1DC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1E8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1EC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1F8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x1FC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x200 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x204 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x214 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x224 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x234 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x244 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x254 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x264 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x274 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x284 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x288 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x28C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x290 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x294 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x298 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x29C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2A8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2AC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2B8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2BC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2C8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2CC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2D8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2DC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2E8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2EC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2F8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x2FC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x300 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x304 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x308 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x30C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x310 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x314 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x318 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x31C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x320 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x324 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x328 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x32C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x330 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x334 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x338 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x33C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x340 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x344 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x348 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x34C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x350 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x354 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x358 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x35C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x360 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x364 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x368 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x36C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x370 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x374 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x378 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x37C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x380 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x384 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x388 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x38C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x390 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x394 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x398 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x39C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3A8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3AC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3B8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3BC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3C8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3CC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3D8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3DC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3E8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3EC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3F8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," line.long 0x3FC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_208," tree.end tree "DAP1_AXI_IA_SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506400 group.long 0x0++0x1FF line.long 0x0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x70 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x74 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x78 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x7C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x80 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x84 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0x88 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0x8C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0x90 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0x94 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0x98 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0x9C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xA0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xA4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xA8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xAC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xB0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xB4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xB8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xBC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xC0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xC4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xC8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xCC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xD0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xD4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xD8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xDC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xE0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xE4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0xE8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0xEC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0xF0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0xF4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0xF8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0xFC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x100 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x104 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x108 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x10C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x110 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x114 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x118 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x11C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x120 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x124 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x130 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x134 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x138 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x13C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x140 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x144 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x148 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x14C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x150 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x154 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x158 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x15C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x160 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x164 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x168 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x16C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x170 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x174 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x178 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x17C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x180 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x184 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x188 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x18C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x190 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x194 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x198 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x19C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1A0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1A4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1A8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1AC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1B0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1B4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1B8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1BC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1C0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1C4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1C8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1CC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1D0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1D4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1D8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1DC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1E0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1E4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," line.long 0x1E8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_107," line.long 0x1EC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_108," line.long 0x1F0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_109," line.long 0x1F4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_110," line.long 0x1F8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_111," line.long 0x1FC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_112," tree.end tree "DAP1_AXI_IA_SDMMC_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B504400 group.long 0x0++0x3FF line.long 0x0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x14 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x34 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x3C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x4C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x50 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x54 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x58 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x5C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x60 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x64 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x68 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x6C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x70 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x74 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x78 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x7C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x80 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x90 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x98 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0x9C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xB8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xBC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xC8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xCC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xD8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xDC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xE8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xEC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xF8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0xFC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x100 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x104 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x108 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x10C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x110 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x114 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x118 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x11C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x120 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x124 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x128 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x12C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x130 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x134 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x138 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x13C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x140 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x144 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x148 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x14C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x150 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x154 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x158 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x15C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x160 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x164 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x168 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x16C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x170 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x174 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x178 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x17C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x180 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x184 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x188 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x18C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x190 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x194 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x198 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x19C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1A8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1AC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1B8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1BC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1C8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1CC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1D8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1DC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1E8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1EC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1F8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x1FC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x200 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x204 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x214 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x218 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x21C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x220 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x224 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x228 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x22C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x230 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x234 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x238 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x23C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x240 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x244 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x248 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x24C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x250 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x254 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x258 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x25C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x260 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x264 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x268 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x26C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x270 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x274 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x278 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x27C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x280 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x284 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x288 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x28C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x290 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x294 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x298 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x29C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2A4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2A8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2AC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2B4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2B8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2BC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2C4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2C8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2CC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2D4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2D8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2DC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2E4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2E8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2EC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2F4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x2F8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x2FC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x300 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x304 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x308 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x30C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x310 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x314 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x318 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x31C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x320 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x324 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x328 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x32C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x330 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x334 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x338 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x33C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x340 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x344 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x348 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x34C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x350 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x354 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x358 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x35C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x360 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x364 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x368 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x36C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x370 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x374 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x378 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x37C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x380 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x384 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x388 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x38C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x390 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x394 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x398 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x39C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3A4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3A8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3AC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3B4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3B8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3BC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3C4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3C8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3CC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3D4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3D8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3DC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3E4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3E8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3EC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3F4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," line.long 0x3F8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_228," line.long 0x3FC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_229," tree.end tree "DAP1_AXI_IA_SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000700 group.long 0x0++0x7F line.long 0x0 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP1_AXI_IA_SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000780 group.long 0x0++0x7F line.long 0x0 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP1_AXI_IA_SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000800 group.long 0x0++0x7F line.long 0x0 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "DAP1_AXI_IA_SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B504800 group.long 0x0++0x3FF line.long 0x0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "DAP1_AXI_IA_SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B504C00 group.long 0x0++0x3FF line.long 0x0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "DAP1_AXI_IA_ZIPW0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000880 group.long 0x0++0x7F line.long 0x0 "ZIPW0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ZIPW0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ZIPW0_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ZIPW0_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ZIPW0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP1_AXI_IA_ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001080 group.long 0x0++0x7F line.long 0x0 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP1_AXI_IA_ZIPW1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000900 group.long 0x0++0x7F line.long 0x0 "ZIPW1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ZIPW1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ZIPW1_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ZIPW1_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ZIPW1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "DAP1_AXI_IA_ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001100 group.long 0x0++0x7F line.long 0x0 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "DAP1_AXI_IA_ZIPW_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B505000 group.long 0x0++0x3FF line.long 0x0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x264 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x268 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x26C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x270 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x274 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x278 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x27C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x280 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x284 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x288 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x28C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x290 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x294 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x298 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x29C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2A0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2AC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2B0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2BC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2C0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2CC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2D0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2DC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2E0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2EC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2F0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2FC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x300 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x304 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x308 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x30C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x310 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x314 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x318 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x31C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x320 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x324 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x328 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x32C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x330 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x334 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x338 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x33C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x340 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x344 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x348 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x34C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x350 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x354 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x358 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x35C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x360 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x364 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x368 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x36C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x370 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x374 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x378 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x37C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x380 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x384 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x388 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x38C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x390 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x394 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x398 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x39C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3A0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3AC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3B0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3BC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3C0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3CC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3D0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3DC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3E0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3EC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3F0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3FC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," tree.end tree "DAP1_AXI_IA_ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506600 group.long 0x0++0x1FF line.long 0x0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x44 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x48 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x4C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x50 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x54 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x58 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x5C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x60 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x64 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x68 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x80 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x84 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x88 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x8C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x90 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x94 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x98 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x9C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xA4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xA8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xAC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xB4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xB8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xBC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xC4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xC8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xCC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xD4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xD8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xDC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xE4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xE8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xEC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xF4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xF8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xFC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x100 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x104 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x108 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x10C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x110 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x114 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x118 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x11C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x130 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x134 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x138 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x13C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x140 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x144 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x148 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x14C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x150 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x154 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x158 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x15C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x160 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x164 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x168 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x16C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x170 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x174 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x178 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x17C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x180 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x184 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x188 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x18C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x190 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x194 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x198 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x19C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1A4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1A8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1AC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1B4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1B8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1BC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1C4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1C8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1CC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1D4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1D8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1DC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1E4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1E8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1EC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1F4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1F8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1FC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," tree.end tree "DAP1_AXI_IA_ZIPW_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B505400 group.long 0x0++0x3FF line.long 0x0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree.end tree "NOC_KITE0" tree "NOC_KITE0_IN_IA_DAP0_AXI_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000000 group.long 0x0++0x7F line.long 0x0 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE0_IN_IA_DAP1_AXI_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000080 group.long 0x0++0x7F line.long 0x0 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE0_IN_IA_DFA_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000100 group.long 0x0++0x7F line.long 0x0 "DFA_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DFA_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DFA_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "DFA_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "DFA_IN_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--12. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "DFA_IN_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "DFA_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE0_IN_IA_DMA0_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B500000 group.long 0x0++0x3FF line.long 0x0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_PORTSEL," bitfld.long 0x270 0. "COUNTERS_7_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x274 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x284 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x288 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x28C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x290 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x294 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x298 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x29C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x2A0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x2A4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x2A8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x2AC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x2B0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x2B4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x2B8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x2BC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2C0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2C4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2C8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2CC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2D0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2D4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2D8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2DC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2E0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2E4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2E8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2EC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2F0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2F4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2F8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2FC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x300 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x304 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x308 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x30C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x310 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x314 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x318 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x31C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x320 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x324 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x328 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x32C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x330 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x334 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x338 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x33C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x340 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x344 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x348 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x34C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x350 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x354 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x358 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x35C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x360 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x364 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x368 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x36C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x370 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x374 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x378 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x37C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x380 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x384 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x388 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x38C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x390 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x394 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x398 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x39C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x3A0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x3A4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x3A8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x3AC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x3B0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x3B4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x3B8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x3BC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3C0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3C4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3C8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3CC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3D0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3D4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3D8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3DC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3E0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3E4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3E8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3EC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3F0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3F4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3F8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3FC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," tree.end tree "NOC_KITE0_IN_IA_DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505800 group.long 0x0++0x1FF line.long 0x0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x4C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x50 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x54 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x58 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x5C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x60 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x64 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x68 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_5," hexmask.long.byte 0x7C 0.--3. 1. "THRESHOLDS_1_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x80 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_6," hexmask.long.byte 0x80 0.--3. 1. "THRESHOLDS_1_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x84 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x88 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x8C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x90 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x94 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x98 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x9C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0xA0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0xA4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0xA8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0xAC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xB0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xB4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xB8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xBC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xC0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xC4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xC8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xCC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xD0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xD4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xD8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xDC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xE0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xE4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xE8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xEC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xF0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xF4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xF8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xFC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0x100 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0x104 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0x108 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0x10C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x110 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x114 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x118 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x11C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x130 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x134 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x138 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x13C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x140 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x144 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x148 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x14C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x150 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x154 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x158 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x15C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x160 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x164 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x168 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x16C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x170 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x174 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x178 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x17C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x180 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x184 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x188 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x18C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x190 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x194 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x198 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x19C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x1A0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x1A4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x1A8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x1AC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1B0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1B4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1B8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1BC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1C0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1C4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1C8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1CC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1D0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1D4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1D8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1DC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1E0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1E4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1E8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1EC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1F0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1F4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1F8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1FC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," tree.end tree "NOC_KITE0_IN_IA_DMA0_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B500400 group.long 0x0++0x3FF line.long 0x0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "NOC_KITE0_IN_IA_DMA1_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B500800 group.long 0x0++0x3FF line.long 0x0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x274 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x278 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x27C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x280 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x284 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x288 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x28C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x290 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x294 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x298 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x29C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x2A0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x2A4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x2A8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x2AC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2B0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2B4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2B8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2BC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2C0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2C4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2C8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2CC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2D0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2D4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2D8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2DC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2E0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2E4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2E8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2EC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2F0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2F4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2F8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2FC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x300 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x304 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x308 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x30C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x310 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x314 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x318 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x31C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x320 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x324 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x328 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x32C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x330 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x334 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x338 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x33C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x340 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x344 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x348 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x34C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x350 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x354 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x358 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x35C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x360 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x364 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x368 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x36C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x370 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x374 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x378 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x37C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x380 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x384 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x388 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x38C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x390 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x394 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x398 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x39C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x3A0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x3A4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x3A8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x3AC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3B0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3B4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3B8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3BC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3C0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3C4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3C8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3CC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3D0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3D4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3D8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3DC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3E0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3E4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3E8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3EC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3F0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3F4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3F8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3FC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," tree.end tree "NOC_KITE0_IN_IA_DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505A00 group.long 0x0++0x1FF line.long 0x0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x48 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x4C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x50 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x54 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x58 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x5C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x60 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x64 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x68 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_5," hexmask.long.byte 0x7C 0.--3. 1. "THRESHOLDS_1_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x80 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x84 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x88 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x8C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x90 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x94 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x98 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x9C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0xA0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0xA4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xAC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xB0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xB4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xBC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xC0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xC4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xCC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xD0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xD4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xDC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xE0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xE4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xEC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xF0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xF4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xFC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0x100 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0x104 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x108 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x10C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x110 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x114 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x118 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x11C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x130 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x134 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x138 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x13C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x140 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x144 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x148 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x14C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x150 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x154 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x158 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x15C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x160 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x164 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x168 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x16C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x170 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x174 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x178 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x17C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x180 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x184 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x188 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x18C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x190 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x194 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x198 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x19C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x1A0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x1A4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1AC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1B0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1B4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1BC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1C0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1C4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1CC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1D0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1D4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1DC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1E0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1E4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1EC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1F0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1F4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1FC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," tree.end tree "NOC_KITE0_IN_IA_DMA1_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B500C00 group.long 0x0++0x3FF line.long 0x0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "NOC_KITE0_IN_IA_EDMA_0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000980 group.long 0x0++0x7F line.long 0x0 "EDMA_0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE0_IN_IA_EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001180 group.long 0x0++0x7F line.long 0x0 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE0_IN_IA_EDMA_1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000A00 group.long 0x0++0x7F line.long 0x0 "EDMA_1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE0_IN_IA_EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001200 group.long 0x0++0x7F line.long 0x0 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE0_IN_IA_EDMA_2_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000A80 group.long 0x0++0x7F line.long 0x0 "EDMA_2_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_2_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_2_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_2_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_2_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE0_IN_IA_EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001280 group.long 0x0++0x7F line.long 0x0 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE0_IN_IA_EDMA_3_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000B00 group.long 0x0++0x7F line.long 0x0 "EDMA_3_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_3_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_3_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_3_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_3_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE0_IN_IA_EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001300 group.long 0x0++0x7F line.long 0x0 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE0_IN_IA_ETHER0_I_MAIN_QOSGENERATOR" base ad:0x7B000180 group.long 0x0++0x7F line.long 0x0 "ETHER0_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER0_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER0_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ETHER0_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ETHER0_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ETHER0_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ETHER0_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE0_IN_IA_ETHER0_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000B80 group.long 0x0++0x7F line.long 0x0 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE0_IN_IA_ETHER1_I_MAIN_QOSGENERATOR" base ad:0x7B000200 group.long 0x0++0x7F line.long 0x0 "ETHER1_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER1_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER1_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ETHER1_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ETHER1_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ETHER1_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ETHER1_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE0_IN_IA_ETHER1_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000C00 group.long 0x0++0x7F line.long 0x0 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE0_IN_IA_ETHR_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B501000 group.long 0x0++0x3FF line.long 0x0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x264 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x268 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x26C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x270 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x274 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x278 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x27C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x280 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x284 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x288 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x28C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x290 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x294 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x298 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x29C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2A0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2AC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2B0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2BC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2C0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2CC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2D0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2DC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2E0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2EC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2F0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2FC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x300 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x304 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x308 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x30C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x310 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x314 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x318 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x31C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x320 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x324 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x328 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x32C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x330 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x334 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x338 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x33C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x340 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x344 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x348 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x34C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x350 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x354 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x358 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x35C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x360 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x364 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x368 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x36C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x370 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x374 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x378 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x37C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x380 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x384 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x388 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x38C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x390 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x394 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x398 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x39C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3A0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3AC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3B0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3BC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3C0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3CC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3D0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3DC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3E0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3EC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3F0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3FC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," tree.end tree "NOC_KITE0_IN_IA_ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505C00 group.long 0x0++0x1FF line.long 0x0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x44 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x48 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x4C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x50 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x54 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x58 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x5C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x60 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x64 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x68 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x80 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x84 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x88 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x8C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x90 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x94 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x98 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x9C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xA4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xA8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xAC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xB4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xB8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xBC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xC4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xC8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xCC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xD4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xD8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xDC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xE4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xE8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xEC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xF4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xF8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xFC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x100 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x104 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x108 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x10C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x110 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x114 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x118 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x11C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x130 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x134 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x138 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x13C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x140 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x144 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x148 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x14C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x150 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x154 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x158 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x15C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x160 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x164 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x168 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x16C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x170 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x174 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x178 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x17C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x180 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x184 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x188 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x18C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x190 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x194 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x198 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x19C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1A4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1A8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1AC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1B4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1B8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1BC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1C4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1C8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1CC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1D4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1D8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1DC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1E4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1E8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1EC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1F4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1F8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1FC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," tree.end tree "NOC_KITE0_IN_IA_ETHR_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B501400 group.long 0x0++0x3FF line.long 0x0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "NOC_KITE0_IN_IA_FLEX0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000280 group.long 0x0++0x7F line.long 0x0 "FLEX0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "FLEX0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "FLEX0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE0_IN_IA_FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000C80 group.long 0x0++0x7F line.long 0x0 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE0_IN_IA_FLEX1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000300 group.long 0x0++0x7F line.long 0x0 "FLEX1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "FLEX1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "FLEX1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE0_IN_IA_FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000D00 group.long 0x0++0x7F line.long 0x0 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE0_IN_IA_FR_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B501800 group.long 0x0++0x3FF line.long 0x0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "FR_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x264 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x268 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x26C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x270 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x274 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x278 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x27C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x280 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x284 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x288 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x28C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x290 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x294 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x298 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x29C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2A0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2AC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2B0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2BC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2C0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2CC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2D0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2DC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2E0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2EC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2F0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2FC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x300 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x304 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x308 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x30C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x310 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x314 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x318 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x31C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x320 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x324 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x328 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x32C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x330 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x334 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x338 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x33C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x340 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x344 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x348 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x34C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x350 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x354 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x358 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x35C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x360 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x364 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x368 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x36C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x370 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x374 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x378 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x37C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x380 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x384 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x388 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x38C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x390 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x394 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x398 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x39C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3A0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3AC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3B0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3BC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3C0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3CC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3D0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3DC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3E0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3EC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3F0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3FC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," tree.end tree "NOC_KITE0_IN_IA_FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505E00 group.long 0x0++0x1FF line.long 0x0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x44 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x48 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x4C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x50 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x54 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x58 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x5C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x60 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x64 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x68 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x80 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x84 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x88 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x8C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x90 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x94 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x98 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x9C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xA4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xA8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xAC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xB4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xB8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xBC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xC4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xC8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xCC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xD4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xD8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xDC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xE4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xE8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xEC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xF4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xF8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xFC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x100 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x104 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x108 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x10C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x110 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x114 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x118 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x11C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x130 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x134 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x138 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x13C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x140 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x144 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x148 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x14C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x150 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x154 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x158 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x15C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x160 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x164 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x168 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x16C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x170 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x174 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x178 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x17C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x180 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x184 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x188 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x18C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x190 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x194 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x198 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x19C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1A4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1A8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1AC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1B4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1B8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1BC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1C4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1C8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1CC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1D4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1D8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1DC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1E4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1E8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1EC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1F4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1F8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1FC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," tree.end tree "NOC_KITE0_IN_IA_FR_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B501C00 group.long 0x0++0x3FF line.long 0x0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "FR_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "NOC_KITE0_IN_IA_GTM_M_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000380 group.long 0x0++0x7F line.long 0x0 "GTM_M_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "GTM_M_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "GTM_M_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "GTM_M_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "GTM_M_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "GTM_M_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "GTM_M_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE0_IN_IA_KITE0_PACKET_PROBE_MAIN_PROBE" base ad:0x7B502000 group.long 0x0++0x3FF line.long 0x0 "KITE0_PACKET_PROBE_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE0_PACKET_PROBE_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE0_PACKET_PROBE_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE0_PACKET_PROBE_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE0_PACKET_PROBE_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE0_PACKET_PROBE_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_PORTSEL," bitfld.long 0x270 0. "COUNTERS_7_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x274 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_104," line.long 0x284 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_105," line.long 0x288 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_106," line.long 0x28C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_107," line.long 0x290 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_108," line.long 0x294 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_109," line.long 0x298 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_110," line.long 0x29C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_111," line.long 0x2A0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_112," line.long 0x2A4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_113," line.long 0x2A8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_114," line.long 0x2AC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_115," line.long 0x2B0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_116," line.long 0x2B4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_117," line.long 0x2B8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_118," line.long 0x2BC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_119," line.long 0x2C0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_120," line.long 0x2C4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_121," line.long 0x2C8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_122," line.long 0x2CC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_123," line.long 0x2D0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_124," line.long 0x2D4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_125," line.long 0x2D8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_126," line.long 0x2DC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_127," line.long 0x2E0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_128," line.long 0x2E4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_129," line.long 0x2E8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_130," line.long 0x2EC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_131," line.long 0x2F0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_132," line.long 0x2F4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_133," line.long 0x2F8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_134," line.long 0x2FC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_135," line.long 0x300 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_136," line.long 0x304 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_137," line.long 0x308 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_138," line.long 0x30C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_139," line.long 0x310 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_140," line.long 0x314 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_141," line.long 0x318 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_142," line.long 0x31C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_143," line.long 0x320 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_144," line.long 0x324 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_145," line.long 0x328 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_146," line.long 0x32C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_147," line.long 0x330 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_148," line.long 0x334 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_149," line.long 0x338 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_150," line.long 0x33C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_151," line.long 0x340 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_152," line.long 0x344 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_153," line.long 0x348 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_154," line.long 0x34C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_155," line.long 0x350 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_156," line.long 0x354 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_157," line.long 0x358 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_158," line.long 0x35C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_159," line.long 0x360 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_160," line.long 0x364 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_161," line.long 0x368 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_162," line.long 0x36C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_163," line.long 0x370 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_164," line.long 0x374 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_165," line.long 0x378 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_166," line.long 0x37C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_167," line.long 0x380 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_168," line.long 0x384 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_169," line.long 0x388 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_170," line.long 0x38C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_171," line.long 0x390 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_172," line.long 0x394 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_173," line.long 0x398 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_174," line.long 0x39C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_175," line.long 0x3A0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_176," line.long 0x3A4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_177," line.long 0x3A8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_178," line.long 0x3AC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_179," line.long 0x3B0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_180," line.long 0x3B4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_181," line.long 0x3B8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_182," line.long 0x3BC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_183," line.long 0x3C0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_184," line.long 0x3C4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_185," line.long 0x3C8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_186," line.long 0x3CC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_187," line.long 0x3D0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_188," line.long 0x3D4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_189," line.long 0x3D8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_190," line.long 0x3DC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_191," line.long 0x3E0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_192," line.long 0x3E4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_193," line.long 0x3E8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_194," line.long 0x3EC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_195," line.long 0x3F0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_196," line.long 0x3F4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_197," line.long 0x3F8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_198," line.long 0x3FC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_199," tree.end tree "NOC_KITE0_IN_IA_KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506000 group.long 0x0++0x1FF line.long 0x0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x70 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x74 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x78 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x7C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x80 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x84 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0x88 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0x8C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0x90 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0x94 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0x98 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0x9C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xA0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xA4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xA8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xAC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xB0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xB4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xB8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xBC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xC0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xC4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xC8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xCC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xD0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xD4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xD8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xDC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xE0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xE4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0xE8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0xEC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0xF0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0xF4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0xF8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0xFC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x100 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x104 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x108 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x10C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x110 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x114 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x118 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x11C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x120 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x124 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x130 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x134 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x138 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x13C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x140 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x144 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x148 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x14C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x150 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x154 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x158 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x15C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x160 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x164 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x168 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x16C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x170 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x174 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x178 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x17C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x180 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x184 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x188 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x18C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x190 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x194 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x198 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x19C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1A0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1A4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1A8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1AC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1B0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1B4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1B8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1BC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1C0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1C4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1C8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1CC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1D0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1D4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1D8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1DC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1E0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1E4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," line.long 0x1E8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_107," line.long 0x1EC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_108," line.long 0x1F0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_109," line.long 0x1F4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_110," line.long 0x1F8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_111," line.long 0x1FC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_112," tree.end tree "NOC_KITE0_IN_IA_KITE0_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B502400 group.long 0x0++0x3FF line.long 0x0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "NOC_KITE0_IN_IA_KITE1_PACKET_PROBE_MAIN_PROBE" base ad:0x7B502800 group.long 0x0++0x3FF line.long 0x0 "KITE1_PACKET_PROBE_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE1_PACKET_PROBE_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE1_PACKET_PROBE_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE1_PACKET_PROBE_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE1_PACKET_PROBE_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE1_PACKET_PROBE_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_PORTSEL," bitfld.long 0x270 0. "COUNTERS_7_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x274 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_104," line.long 0x284 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_105," line.long 0x288 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_106," line.long 0x28C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_107," line.long 0x290 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_108," line.long 0x294 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_109," line.long 0x298 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_110," line.long 0x29C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_111," line.long 0x2A0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_112," line.long 0x2A4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_113," line.long 0x2A8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_114," line.long 0x2AC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_115," line.long 0x2B0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_116," line.long 0x2B4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_117," line.long 0x2B8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_118," line.long 0x2BC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_119," line.long 0x2C0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_120," line.long 0x2C4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_121," line.long 0x2C8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_122," line.long 0x2CC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_123," line.long 0x2D0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_124," line.long 0x2D4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_125," line.long 0x2D8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_126," line.long 0x2DC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_127," line.long 0x2E0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_128," line.long 0x2E4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_129," line.long 0x2E8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_130," line.long 0x2EC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_131," line.long 0x2F0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_132," line.long 0x2F4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_133," line.long 0x2F8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_134," line.long 0x2FC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_135," line.long 0x300 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_136," line.long 0x304 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_137," line.long 0x308 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_138," line.long 0x30C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_139," line.long 0x310 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_140," line.long 0x314 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_141," line.long 0x318 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_142," line.long 0x31C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_143," line.long 0x320 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_144," line.long 0x324 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_145," line.long 0x328 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_146," line.long 0x32C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_147," line.long 0x330 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_148," line.long 0x334 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_149," line.long 0x338 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_150," line.long 0x33C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_151," line.long 0x340 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_152," line.long 0x344 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_153," line.long 0x348 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_154," line.long 0x34C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_155," line.long 0x350 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_156," line.long 0x354 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_157," line.long 0x358 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_158," line.long 0x35C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_159," line.long 0x360 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_160," line.long 0x364 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_161," line.long 0x368 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_162," line.long 0x36C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_163," line.long 0x370 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_164," line.long 0x374 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_165," line.long 0x378 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_166," line.long 0x37C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_167," line.long 0x380 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_168," line.long 0x384 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_169," line.long 0x388 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_170," line.long 0x38C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_171," line.long 0x390 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_172," line.long 0x394 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_173," line.long 0x398 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_174," line.long 0x39C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_175," line.long 0x3A0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_176," line.long 0x3A4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_177," line.long 0x3A8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_178," line.long 0x3AC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_179," line.long 0x3B0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_180," line.long 0x3B4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_181," line.long 0x3B8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_182," line.long 0x3BC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_183," line.long 0x3C0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_184," line.long 0x3C4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_185," line.long 0x3C8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_186," line.long 0x3CC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_187," line.long 0x3D0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_188," line.long 0x3D4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_189," line.long 0x3D8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_190," line.long 0x3DC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_191," line.long 0x3E0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_192," line.long 0x3E4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_193," line.long 0x3E8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_194," line.long 0x3EC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_195," line.long 0x3F0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_196," line.long 0x3F4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_197," line.long 0x3F8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_198," line.long 0x3FC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_199," tree.end tree "NOC_KITE0_IN_IA_KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506200 group.long 0x0++0x1FF line.long 0x0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x70 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x74 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x78 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x7C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x80 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x84 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0x88 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0x8C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0x90 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0x94 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0x98 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0x9C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xA0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xA4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xA8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xAC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xB0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xB4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xB8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xBC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xC0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xC4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xC8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xCC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xD0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xD4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xD8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xDC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xE0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xE4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0xE8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0xEC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0xF0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0xF4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0xF8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0xFC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x100 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x104 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x108 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x10C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x110 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x114 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x118 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x11C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x120 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x124 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x130 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x134 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x138 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x13C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x140 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x144 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x148 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x14C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x150 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x154 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x158 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x15C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x160 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x164 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x168 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x16C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x170 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x174 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x178 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x17C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x180 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x184 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x188 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x18C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x190 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x194 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x198 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x19C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1A0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1A4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1A8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1AC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1B0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1B4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1B8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1BC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1C0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1C4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1C8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1CC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1D0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1D4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1D8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1DC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1E0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1E4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," line.long 0x1E8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_107," line.long 0x1EC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_108," line.long 0x1F0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_109," line.long 0x1F4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_110," line.long 0x1F8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_111," line.long 0x1FC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_112," tree.end tree "NOC_KITE0_IN_IA_KITE1_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B502C00 group.long 0x0++0x3FF line.long 0x0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "NOC_KITE0_IN_IA_KITE2_PACKET_PROBE_MAIN_PROBE" base ad:0x7B503000 group.long 0x0++0x3FF line.long 0x0 "KITE2_PACKET_PROBE_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE2_PACKET_PROBE_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE2_PACKET_PROBE_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE2_PACKET_PROBE_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE2_PACKET_PROBE_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE2_PACKET_PROBE_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_211," tree.end tree "NOC_KITE0_IN_IA_KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506800 group.long 0x0++0x7F line.long 0x0 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x40 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x44 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x48 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x4C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x50 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x54 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x58 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x5C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x60 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x64 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x68 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x6C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x6C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x70 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x70 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x74 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x74 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x78 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x78 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x7C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," tree.end tree "NOC_KITE0_IN_IA_KITE2_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B503400 group.long 0x0++0x3FF line.long 0x0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "NOC_KITE0_IN_IA_NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000400 group.long 0x0++0x7F line.long 0x0 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE0_IN_IA_NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000D80 group.long 0x0++0x7F line.long 0x0 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE0_IN_IA_NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000480 group.long 0x0++0x7F line.long 0x0 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE0_IN_IA_NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000E00 group.long 0x0++0x7F line.long 0x0 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE0_IN_IA_NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000500 group.long 0x0++0x7F line.long 0x0 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE0_IN_IA_NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000E80 group.long 0x0++0x7F line.long 0x0 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE0_IN_IA_OBSERVER_HSM_MAIN_ERRORLOGGER_0" base ad:0x7B506A80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "NOC_KITE0_IN_IA_OBSERVER_KITE0_MAIN_ERRORLOGGER_0" base ad:0x7B506B00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "NOC_KITE0_IN_IA_OBSERVER_KITE1_MAIN_ERRORLOGGER_0" base ad:0x7B506B80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "NOC_KITE0_IN_IA_OBSERVER_KITE2_MAIN_ERRORLOGGER_0" base ad:0x7B506C00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "NOC_KITE0_IN_IA_OBSERVER_MAIN0_MAIN_ATBENDPOINT" base ad:0x7B506900 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ATBID," hexmask.long.byte 0x8 0.--6. 1. "ATBID,ATB AtId" line.long 0xC "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ATBEN," bitfld.long 0xC 0. "ATBEN,ATB Unit Enable" "0,1" line.long 0x10 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_SYNCPERIOD," hexmask.long.byte 0x10 0.--4. 1. "SYNCPERIOD,ATB Synchro Period" line.long 0x14 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_00," line.long 0x18 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_01," line.long 0x1C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_02," line.long 0x20 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_03," line.long 0x24 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_04," line.long 0x28 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_05," line.long 0x2C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_06," line.long 0x30 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_07," line.long 0x34 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_08," line.long 0x38 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_09," line.long 0x3C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_10," line.long 0x40 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_11," line.long 0x44 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_12," line.long 0x48 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_13," line.long 0x4C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_14," line.long 0x50 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_15," line.long 0x54 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_16," line.long 0x58 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_17," line.long 0x5C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_18," line.long 0x60 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_19," line.long 0x64 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_20," line.long 0x68 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_21," line.long 0x6C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_22," line.long 0x70 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_23," line.long 0x74 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_24," line.long 0x78 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_25," line.long 0x7C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_26," tree.end tree "NOC_KITE0_IN_IA_OBSERVER_MAIN0_MAIN_ERRORLOGGER_0" base ad:0x7B506C80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "NOC_KITE0_IN_IA_OBSERVER_MAIN1_MAIN_ATBENDPOINT" base ad:0x7B506980 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ATBID," hexmask.long.byte 0x8 0.--6. 1. "ATBID,ATB AtId" line.long 0xC "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ATBEN," bitfld.long 0xC 0. "ATBEN,ATB Unit Enable" "0,1" line.long 0x10 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_SYNCPERIOD," hexmask.long.byte 0x10 0.--4. 1. "SYNCPERIOD,ATB Synchro Period" line.long 0x14 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_00," line.long 0x18 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_01," line.long 0x1C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_02," line.long 0x20 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_03," line.long 0x24 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_04," line.long 0x28 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_05," line.long 0x2C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_06," line.long 0x30 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_07," line.long 0x34 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_08," line.long 0x38 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_09," line.long 0x3C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_10," line.long 0x40 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_11," line.long 0x44 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_12," line.long 0x48 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_13," line.long 0x4C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_14," line.long 0x50 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_15," line.long 0x54 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_16," line.long 0x58 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_17," line.long 0x5C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_18," line.long 0x60 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_19," line.long 0x64 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_20," line.long 0x68 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_21," line.long 0x6C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_22," line.long 0x70 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_23," line.long 0x74 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_24," line.long 0x78 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_25," line.long 0x7C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_26," tree.end tree "NOC_KITE0_IN_IA_OBSERVER_MAIN1_MAIN_ERRORLOGGER_0" base ad:0x7B506D00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "NOC_KITE0_IN_IA_OBSERVER_PCIE_MAIN_ATBENDPOINT" base ad:0x7B506A00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_PCIE_MAIN_ATBENDPOINT_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_PCIE_MAIN_ATBENDPOINT_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_PCIE_MAIN_ATBENDPOINT_ATBID," hexmask.long.byte 0x8 0.--6. 1. "ATBID,ATB AtId" line.long 0xC "OBSERVER_PCIE_MAIN_ATBENDPOINT_ATBEN," bitfld.long 0xC 0. "ATBEN,ATB Unit Enable" "0,1" line.long 0x10 "OBSERVER_PCIE_MAIN_ATBENDPOINT_SYNCPERIOD," hexmask.long.byte 0x10 0.--4. 1. "SYNCPERIOD,ATB Synchro Period" line.long 0x14 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_00," line.long 0x18 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_01," line.long 0x1C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_02," line.long 0x20 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_03," line.long 0x24 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_04," line.long 0x28 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_05," line.long 0x2C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_06," line.long 0x30 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_07," line.long 0x34 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_08," line.long 0x38 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_09," line.long 0x3C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_10," line.long 0x40 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_11," line.long 0x44 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_12," line.long 0x48 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_13," line.long 0x4C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_14," line.long 0x50 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_15," line.long 0x54 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_16," line.long 0x58 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_17," line.long 0x5C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_18," line.long 0x60 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_19," line.long 0x64 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_20," line.long 0x68 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_21," line.long 0x6C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_22," line.long 0x70 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_23," line.long 0x74 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_24," line.long 0x78 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_25," line.long 0x7C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_26," tree.end tree "NOC_KITE0_IN_IA_OBSERVER_PCIE_MAIN_ERRORLOGGER_0" base ad:0x7B506D80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "NOC_KITE0_IN_IA_PCIE_0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000580 group.long 0x0++0x7F line.long 0x0 "PCIE_0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "PCIE_0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "PCIE_0_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "PCIE_0_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "PCIE_0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE0_IN_IA_PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000F00 group.long 0x0++0x7F line.long 0x0 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE0_IN_IA_PCIE_1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000600 group.long 0x0++0x7F line.long 0x0 "PCIE_1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "PCIE_1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "PCIE_1_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "PCIE_1_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "PCIE_1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE0_IN_IA_PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000F80 group.long 0x0++0x7F line.long 0x0 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE0_IN_IA_PCIE_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B503800 group.long 0x0++0x3FF line.long 0x0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x234 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x238 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x23C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x240 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x244 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x248 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x24C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x250 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x254 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x258 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x25C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x260 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x264 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x268 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x26C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x270 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x274 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x278 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x27C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x280 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x284 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x288 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x28C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x290 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x294 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x298 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x29C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2A0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2A4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2A8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2AC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2B0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2B4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2B8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2BC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2C0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2C4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2C8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2CC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x2D0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x2D4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x2D8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x2DC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x2E0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x2E4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x2E8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x2EC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x2F0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x2F4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x2F8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x2FC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x300 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x304 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x308 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x30C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x310 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x314 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x318 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x31C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x320 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x324 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x328 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x32C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x330 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x334 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x338 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x33C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x340 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x344 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x348 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x34C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x350 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x354 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x358 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x35C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x360 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x364 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x368 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x36C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x370 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x374 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x378 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x37C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x380 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x384 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x388 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x38C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x390 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x394 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x398 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x39C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3A0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3A4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3A8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3AC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3B0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3B4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3B8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3BC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3C0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3C4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3C8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3CC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," line.long 0x3D0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_208," line.long 0x3D4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_209," line.long 0x3D8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_210," line.long 0x3DC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_211," line.long 0x3E0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_212," line.long 0x3E4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_213," line.long 0x3E8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_214," line.long 0x3EC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_215," line.long 0x3F0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_216," line.long 0x3F4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_217," line.long 0x3F8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_218," line.long 0x3FC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_219," tree.end tree "NOC_KITE0_IN_IA_PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506880 group.long 0x0++0x7F line.long 0x0 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x38 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x3C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x40 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x44 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x48 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x6C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x70 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x70 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x74 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x74 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x78 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x78 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x7C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," tree.end tree "NOC_KITE0_IN_IA_PCIE_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B503C00 group.long 0x0++0x3FF line.long 0x0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "NOC_KITE0_IN_IA_POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER" base ad:0x7B506E00 group.long 0x0++0x7F line.long 0x0 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT0," hexmask.long 0x8 0.--31. 1. "MISSIONFAULT0,MissionFault0 register" line.long 0xC "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT1," hexmask.long 0xC 0.--31. 1. "MISSIONFAULT1,MissionFault1 register" line.long 0x10 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT2," hexmask.long 0x10 0.--31. 1. "MISSIONFAULT2,MissionFault2 register" line.long 0x14 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT3," hexmask.long 0x14 0.--31. 1. "MISSIONFAULT3,MissionFault3 register" line.long 0x18 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT0," hexmask.long 0x18 0.--31. 1. "LATENTFAULT0,LatentFault0 register" line.long 0x1C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT1," hexmask.long 0x1C 0.--31. 1. "LATENTFAULT1,LatentFault1 register" line.long 0x20 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT2," hexmask.long 0x20 0.--31. 1. "LATENTFAULT2,LatentFault2 register" line.long 0x24 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT3," hexmask.long 0x24 0.--31. 1. "LATENTFAULT3,LatentFault3 register" line.long 0x28 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_FAULTS," bitfld.long 0x28 1. "MISSIONFAULT,Mission Fault" "0,1" bitfld.long 0x28 0. "LATENTFAULT,Latent Fault" "0,1" line.long 0x2C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_INTEN," bitfld.long 0x2C 1. "MISSIONFAULTEN,MissionFault Interrupt enable" "0,1" bitfld.long 0x2C 0. "BISTDONEEN,BistDone Interrupt enable" "0,1" line.long 0x30 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_INTCLR," bitfld.long 0x30 1. "MISSIONFAULTCLR,Clear Mission Fault" "0,1" bitfld.long 0x30 0. "LATENTFAULTCLR,Clear Latent Fault" "0,1" line.long 0x34 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTCTL," bitfld.long 0x34 1. "BISTDONECLR,Clear BistDone" "0,1" bitfld.long 0x34 0. "BISTSTART,Start Bist sequence" "0,1" line.long 0x38 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTDONE," bitfld.long 0x38 1. "MISSIONMODE,Mission Mode Status" "0,1" bitfld.long 0x38 0. "BISTDONE,BistDone Status" "0,1" line.long 0x3C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO1," hexmask.long.word 0x3C 0.--15. 1. "BISTTO1,BistTimeOut register" line.long 0x40 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO2," hexmask.long.byte 0x40 0.--7. 1. "BISTTO2,BistTimeOut register" line.long 0x44 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_00," line.long 0x48 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_01," line.long 0x4C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_02," line.long 0x50 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_03," line.long 0x54 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_04," line.long 0x58 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_05," line.long 0x5C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_06," line.long 0x60 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_07," line.long 0x64 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_08," line.long 0x68 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_09," line.long 0x6C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_10," line.long 0x70 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_11," line.long 0x74 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_12," line.long 0x78 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_13," line.long 0x7C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_14," tree.end tree "NOC_KITE0_IN_IA_POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER" base ad:0x7B506E80 group.long 0x0++0x7F line.long 0x0 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT0," hexmask.long 0x8 0.--31. 1. "MISSIONFAULT0,MissionFault0 register" line.long 0xC "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT1," hexmask.long 0xC 0.--31. 1. "MISSIONFAULT1,MissionFault1 register" line.long 0x10 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT2," hexmask.long 0x10 0.--31. 1. "MISSIONFAULT2,MissionFault2 register" line.long 0x14 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT3," hexmask.long 0x14 0.--31. 1. "MISSIONFAULT3,MissionFault3 register" line.long 0x18 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT0," hexmask.long 0x18 0.--31. 1. "LATENTFAULT0,LatentFault0 register" line.long 0x1C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT1," hexmask.long 0x1C 0.--31. 1. "LATENTFAULT1,LatentFault1 register" line.long 0x20 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT2," hexmask.long 0x20 0.--31. 1. "LATENTFAULT2,LatentFault2 register" line.long 0x24 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT3," hexmask.long 0x24 0.--31. 1. "LATENTFAULT3,LatentFault3 register" line.long 0x28 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_FAULTS," bitfld.long 0x28 1. "MISSIONFAULT,Mission Fault" "0,1" bitfld.long 0x28 0. "LATENTFAULT,Latent Fault" "0,1" line.long 0x2C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_INTEN," bitfld.long 0x2C 1. "MISSIONFAULTEN,MissionFault Interrupt enable" "0,1" bitfld.long 0x2C 0. "BISTDONEEN,BistDone Interrupt enable" "0,1" line.long 0x30 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_INTCLR," bitfld.long 0x30 1. "MISSIONFAULTCLR,Clear Mission Fault" "0,1" bitfld.long 0x30 0. "LATENTFAULTCLR,Clear Latent Fault" "0,1" line.long 0x34 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTCTL," bitfld.long 0x34 1. "BISTDONECLR,Clear BistDone" "0,1" bitfld.long 0x34 0. "BISTSTART,Start Bist sequence" "0,1" line.long 0x38 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTDONE," bitfld.long 0x38 1. "MISSIONMODE,Mission Mode Status" "0,1" bitfld.long 0x38 0. "BISTDONE,BistDone Status" "0,1" line.long 0x3C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO1," hexmask.long.word 0x3C 0.--15. 1. "BISTTO1,BistTimeOut register" line.long 0x40 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO2," hexmask.long.byte 0x40 0.--7. 1. "BISTTO2,BistTimeOut register" line.long 0x44 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_00," line.long 0x48 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_01," line.long 0x4C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_02," line.long 0x50 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_03," line.long 0x54 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_04," line.long 0x58 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_05," line.long 0x5C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_06," line.long 0x60 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_07," line.long 0x64 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_08," line.long 0x68 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_09," line.long 0x6C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_10," line.long 0x70 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_11," line.long 0x74 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_12," line.long 0x78 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_13," line.long 0x7C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_14," tree.end tree "NOC_KITE0_IN_IA_SDMMC_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000680 group.long 0x0++0x7F line.long 0x0 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE0_IN_IA_SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001000 group.long 0x0++0x7F line.long 0x0 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE0_IN_IA_SDMMC_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B504000 group.long 0x0++0x3FF line.long 0x0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x14 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x34 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x3C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x4C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x50 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x54 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x58 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x5C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x60 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x64 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x68 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x6C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x70 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x74 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x78 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x7C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x80 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x90 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x98 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0x9C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xB8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xBC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xC8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xCC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xD8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xDC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xE8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xEC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xF8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0xFC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x100 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x104 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x108 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x10C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x110 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x114 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x118 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x11C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x120 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x124 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x128 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x12C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x130 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x134 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x138 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x13C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x140 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x144 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x148 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x14C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x150 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x154 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x158 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x15C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x160 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x164 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x168 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x16C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x170 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x174 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x178 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x17C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x180 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x184 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x188 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x18C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x190 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x194 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x198 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x19C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1A8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1AC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1B8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1BC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1C8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1CC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1D8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1DC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1E8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1EC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1F8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x1FC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x200 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x204 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x214 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x224 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x234 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x244 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x254 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x264 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x274 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x284 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x288 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x28C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x290 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x294 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x298 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x29C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2A8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2AC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2B8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2BC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2C8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2CC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2D8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2DC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2E8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2EC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2F8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x2FC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x300 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x304 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x308 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x30C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x310 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x314 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x318 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x31C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x320 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x324 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x328 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x32C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x330 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x334 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x338 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x33C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x340 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x344 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x348 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x34C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x350 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x354 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x358 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x35C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x360 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x364 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x368 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x36C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x370 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x374 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x378 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x37C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x380 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x384 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x388 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x38C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x390 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x394 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x398 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x39C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3A8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3AC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3B8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3BC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3C8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3CC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3D8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3DC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3E8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3EC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3F8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," line.long 0x3FC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_208," tree.end tree "NOC_KITE0_IN_IA_SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506400 group.long 0x0++0x1FF line.long 0x0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x70 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x74 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x78 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x7C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x80 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x84 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0x88 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0x8C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0x90 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0x94 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0x98 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0x9C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xA0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xA4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xA8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xAC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xB0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xB4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xB8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xBC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xC0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xC4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xC8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xCC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xD0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xD4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xD8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xDC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xE0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xE4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0xE8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0xEC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0xF0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0xF4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0xF8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0xFC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x100 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x104 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x108 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x10C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x110 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x114 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x118 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x11C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x120 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x124 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x130 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x134 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x138 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x13C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x140 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x144 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x148 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x14C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x150 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x154 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x158 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x15C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x160 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x164 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x168 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x16C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x170 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x174 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x178 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x17C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x180 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x184 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x188 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x18C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x190 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x194 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x198 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x19C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1A0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1A4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1A8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1AC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1B0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1B4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1B8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1BC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1C0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1C4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1C8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1CC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1D0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1D4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1D8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1DC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1E0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1E4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," line.long 0x1E8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_107," line.long 0x1EC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_108," line.long 0x1F0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_109," line.long 0x1F4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_110," line.long 0x1F8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_111," line.long 0x1FC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_112," tree.end tree "NOC_KITE0_IN_IA_SDMMC_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B504400 group.long 0x0++0x3FF line.long 0x0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x14 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x34 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x3C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x4C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x50 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x54 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x58 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x5C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x60 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x64 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x68 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x6C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x70 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x74 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x78 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x7C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x80 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x90 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x98 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0x9C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xB8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xBC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xC8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xCC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xD8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xDC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xE8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xEC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xF8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0xFC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x100 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x104 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x108 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x10C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x110 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x114 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x118 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x11C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x120 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x124 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x128 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x12C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x130 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x134 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x138 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x13C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x140 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x144 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x148 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x14C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x150 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x154 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x158 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x15C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x160 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x164 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x168 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x16C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x170 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x174 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x178 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x17C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x180 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x184 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x188 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x18C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x190 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x194 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x198 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x19C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1A8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1AC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1B8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1BC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1C8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1CC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1D8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1DC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1E8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1EC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1F8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x1FC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x200 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x204 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x214 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x218 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x21C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x220 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x224 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x228 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x22C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x230 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x234 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x238 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x23C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x240 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x244 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x248 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x24C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x250 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x254 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x258 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x25C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x260 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x264 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x268 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x26C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x270 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x274 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x278 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x27C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x280 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x284 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x288 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x28C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x290 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x294 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x298 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x29C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2A4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2A8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2AC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2B4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2B8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2BC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2C4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2C8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2CC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2D4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2D8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2DC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2E4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2E8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2EC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2F4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x2F8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x2FC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x300 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x304 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x308 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x30C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x310 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x314 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x318 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x31C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x320 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x324 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x328 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x32C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x330 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x334 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x338 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x33C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x340 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x344 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x348 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x34C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x350 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x354 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x358 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x35C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x360 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x364 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x368 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x36C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x370 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x374 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x378 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x37C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x380 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x384 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x388 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x38C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x390 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x394 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x398 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x39C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3A4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3A8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3AC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3B4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3B8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3BC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3C4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3C8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3CC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3D4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3D8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3DC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3E4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3E8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3EC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3F4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," line.long 0x3F8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_228," line.long 0x3FC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_229," tree.end tree "NOC_KITE0_IN_IA_SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000700 group.long 0x0++0x7F line.long 0x0 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE0_IN_IA_SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000780 group.long 0x0++0x7F line.long 0x0 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE0_IN_IA_SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000800 group.long 0x0++0x7F line.long 0x0 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE0_IN_IA_SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B504800 group.long 0x0++0x3FF line.long 0x0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "NOC_KITE0_IN_IA_SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B504C00 group.long 0x0++0x3FF line.long 0x0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "NOC_KITE0_IN_IA_ZIPW0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000880 group.long 0x0++0x7F line.long 0x0 "ZIPW0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ZIPW0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ZIPW0_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ZIPW0_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ZIPW0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE0_IN_IA_ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001080 group.long 0x0++0x7F line.long 0x0 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE0_IN_IA_ZIPW1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000900 group.long 0x0++0x7F line.long 0x0 "ZIPW1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ZIPW1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ZIPW1_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ZIPW1_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ZIPW1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE0_IN_IA_ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001100 group.long 0x0++0x7F line.long 0x0 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE0_IN_IA_ZIPW_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B505000 group.long 0x0++0x3FF line.long 0x0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x264 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x268 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x26C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x270 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x274 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x278 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x27C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x280 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x284 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x288 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x28C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x290 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x294 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x298 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x29C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2A0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2AC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2B0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2BC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2C0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2CC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2D0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2DC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2E0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2EC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2F0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2FC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x300 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x304 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x308 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x30C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x310 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x314 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x318 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x31C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x320 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x324 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x328 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x32C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x330 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x334 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x338 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x33C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x340 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x344 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x348 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x34C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x350 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x354 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x358 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x35C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x360 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x364 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x368 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x36C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x370 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x374 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x378 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x37C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x380 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x384 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x388 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x38C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x390 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x394 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x398 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x39C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3A0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3AC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3B0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3BC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3C0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3CC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3D0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3DC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3E0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3EC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3F0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3FC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," tree.end tree "NOC_KITE0_IN_IA_ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506600 group.long 0x0++0x1FF line.long 0x0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x44 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x48 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x4C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x50 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x54 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x58 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x5C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x60 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x64 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x68 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x80 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x84 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x88 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x8C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x90 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x94 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x98 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x9C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xA4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xA8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xAC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xB4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xB8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xBC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xC4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xC8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xCC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xD4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xD8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xDC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xE4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xE8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xEC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xF4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xF8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xFC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x100 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x104 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x108 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x10C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x110 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x114 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x118 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x11C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x130 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x134 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x138 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x13C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x140 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x144 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x148 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x14C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x150 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x154 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x158 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x15C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x160 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x164 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x168 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x16C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x170 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x174 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x178 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x17C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x180 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x184 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x188 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x18C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x190 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x194 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x198 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x19C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1A4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1A8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1AC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1B4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1B8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1BC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1C4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1C8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1CC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1D4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1D8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1DC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1E4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1E8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1EC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1F4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1F8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1FC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," tree.end tree "NOC_KITE0_IN_IA_ZIPW_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B505400 group.long 0x0++0x3FF line.long 0x0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree.end tree "NOC_KITE1" tree "NOC_KITE1_IN_IA_DAP0_AXI_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000000 group.long 0x0++0x7F line.long 0x0 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE1_IN_IA_DAP1_AXI_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000080 group.long 0x0++0x7F line.long 0x0 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE1_IN_IA_DFA_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000100 group.long 0x0++0x7F line.long 0x0 "DFA_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DFA_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DFA_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "DFA_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "DFA_IN_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--12. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "DFA_IN_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "DFA_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE1_IN_IA_DMA0_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B500000 group.long 0x0++0x3FF line.long 0x0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_PORTSEL," bitfld.long 0x270 0. "COUNTERS_7_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x274 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x284 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x288 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x28C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x290 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x294 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x298 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x29C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x2A0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x2A4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x2A8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x2AC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x2B0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x2B4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x2B8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x2BC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2C0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2C4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2C8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2CC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2D0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2D4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2D8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2DC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2E0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2E4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2E8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2EC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2F0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2F4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2F8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2FC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x300 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x304 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x308 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x30C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x310 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x314 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x318 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x31C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x320 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x324 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x328 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x32C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x330 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x334 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x338 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x33C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x340 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x344 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x348 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x34C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x350 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x354 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x358 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x35C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x360 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x364 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x368 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x36C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x370 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x374 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x378 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x37C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x380 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x384 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x388 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x38C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x390 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x394 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x398 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x39C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x3A0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x3A4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x3A8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x3AC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x3B0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x3B4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x3B8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x3BC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3C0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3C4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3C8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3CC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3D0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3D4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3D8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3DC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3E0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3E4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3E8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3EC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3F0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3F4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3F8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3FC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," tree.end tree "NOC_KITE1_IN_IA_DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505800 group.long 0x0++0x1FF line.long 0x0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x4C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x50 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x54 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x58 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x5C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x60 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x64 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x68 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_5," hexmask.long.byte 0x7C 0.--3. 1. "THRESHOLDS_1_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x80 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_6," hexmask.long.byte 0x80 0.--3. 1. "THRESHOLDS_1_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x84 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x88 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x8C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x90 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x94 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x98 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x9C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0xA0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0xA4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0xA8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0xAC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xB0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xB4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xB8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xBC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xC0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xC4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xC8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xCC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xD0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xD4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xD8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xDC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xE0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xE4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xE8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xEC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xF0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xF4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xF8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xFC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0x100 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0x104 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0x108 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0x10C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x110 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x114 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x118 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x11C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x130 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x134 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x138 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x13C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x140 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x144 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x148 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x14C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x150 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x154 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x158 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x15C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x160 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x164 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x168 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x16C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x170 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x174 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x178 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x17C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x180 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x184 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x188 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x18C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x190 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x194 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x198 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x19C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x1A0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x1A4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x1A8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x1AC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1B0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1B4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1B8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1BC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1C0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1C4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1C8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1CC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1D0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1D4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1D8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1DC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1E0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1E4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1E8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1EC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1F0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1F4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1F8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1FC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," tree.end tree "NOC_KITE1_IN_IA_DMA0_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B500400 group.long 0x0++0x3FF line.long 0x0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "NOC_KITE1_IN_IA_DMA1_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B500800 group.long 0x0++0x3FF line.long 0x0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x274 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x278 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x27C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x280 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x284 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x288 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x28C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x290 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x294 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x298 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x29C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x2A0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x2A4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x2A8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x2AC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2B0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2B4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2B8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2BC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2C0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2C4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2C8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2CC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2D0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2D4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2D8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2DC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2E0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2E4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2E8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2EC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2F0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2F4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2F8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2FC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x300 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x304 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x308 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x30C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x310 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x314 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x318 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x31C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x320 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x324 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x328 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x32C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x330 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x334 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x338 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x33C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x340 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x344 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x348 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x34C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x350 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x354 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x358 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x35C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x360 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x364 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x368 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x36C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x370 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x374 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x378 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x37C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x380 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x384 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x388 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x38C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x390 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x394 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x398 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x39C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x3A0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x3A4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x3A8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x3AC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3B0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3B4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3B8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3BC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3C0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3C4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3C8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3CC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3D0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3D4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3D8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3DC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3E0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3E4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3E8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3EC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3F0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3F4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3F8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3FC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," tree.end tree "NOC_KITE1_IN_IA_DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505A00 group.long 0x0++0x1FF line.long 0x0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x48 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x4C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x50 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x54 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x58 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x5C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x60 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x64 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x68 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_5," hexmask.long.byte 0x7C 0.--3. 1. "THRESHOLDS_1_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x80 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x84 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x88 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x8C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x90 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x94 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x98 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x9C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0xA0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0xA4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xAC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xB0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xB4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xBC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xC0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xC4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xCC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xD0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xD4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xDC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xE0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xE4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xEC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xF0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xF4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xFC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0x100 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0x104 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x108 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x10C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x110 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x114 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x118 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x11C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x130 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x134 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x138 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x13C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x140 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x144 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x148 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x14C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x150 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x154 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x158 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x15C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x160 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x164 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x168 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x16C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x170 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x174 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x178 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x17C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x180 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x184 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x188 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x18C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x190 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x194 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x198 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x19C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x1A0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x1A4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1AC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1B0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1B4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1BC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1C0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1C4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1CC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1D0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1D4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1DC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1E0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1E4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1EC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1F0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1F4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1FC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," tree.end tree "NOC_KITE1_IN_IA_DMA1_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B500C00 group.long 0x0++0x3FF line.long 0x0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "NOC_KITE1_IN_IA_EDMA_0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000980 group.long 0x0++0x7F line.long 0x0 "EDMA_0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE1_IN_IA_EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001180 group.long 0x0++0x7F line.long 0x0 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE1_IN_IA_EDMA_1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000A00 group.long 0x0++0x7F line.long 0x0 "EDMA_1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE1_IN_IA_EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001200 group.long 0x0++0x7F line.long 0x0 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE1_IN_IA_EDMA_2_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000A80 group.long 0x0++0x7F line.long 0x0 "EDMA_2_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_2_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_2_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_2_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_2_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE1_IN_IA_EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001280 group.long 0x0++0x7F line.long 0x0 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE1_IN_IA_EDMA_3_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000B00 group.long 0x0++0x7F line.long 0x0 "EDMA_3_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_3_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_3_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_3_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_3_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE1_IN_IA_EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001300 group.long 0x0++0x7F line.long 0x0 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE1_IN_IA_ETHER0_I_MAIN_QOSGENERATOR" base ad:0x7B000180 group.long 0x0++0x7F line.long 0x0 "ETHER0_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER0_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER0_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ETHER0_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ETHER0_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ETHER0_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ETHER0_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE1_IN_IA_ETHER0_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000B80 group.long 0x0++0x7F line.long 0x0 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE1_IN_IA_ETHER1_I_MAIN_QOSGENERATOR" base ad:0x7B000200 group.long 0x0++0x7F line.long 0x0 "ETHER1_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER1_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER1_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ETHER1_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ETHER1_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ETHER1_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ETHER1_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE1_IN_IA_ETHER1_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000C00 group.long 0x0++0x7F line.long 0x0 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE1_IN_IA_ETHR_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B501000 group.long 0x0++0x3FF line.long 0x0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x264 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x268 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x26C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x270 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x274 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x278 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x27C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x280 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x284 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x288 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x28C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x290 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x294 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x298 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x29C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2A0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2AC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2B0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2BC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2C0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2CC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2D0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2DC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2E0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2EC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2F0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2FC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x300 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x304 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x308 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x30C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x310 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x314 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x318 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x31C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x320 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x324 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x328 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x32C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x330 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x334 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x338 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x33C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x340 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x344 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x348 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x34C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x350 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x354 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x358 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x35C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x360 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x364 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x368 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x36C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x370 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x374 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x378 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x37C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x380 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x384 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x388 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x38C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x390 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x394 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x398 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x39C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3A0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3AC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3B0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3BC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3C0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3CC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3D0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3DC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3E0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3EC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3F0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3FC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," tree.end tree "NOC_KITE1_IN_IA_ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505C00 group.long 0x0++0x1FF line.long 0x0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x44 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x48 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x4C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x50 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x54 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x58 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x5C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x60 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x64 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x68 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x80 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x84 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x88 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x8C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x90 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x94 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x98 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x9C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xA4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xA8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xAC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xB4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xB8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xBC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xC4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xC8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xCC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xD4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xD8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xDC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xE4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xE8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xEC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xF4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xF8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xFC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x100 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x104 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x108 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x10C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x110 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x114 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x118 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x11C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x130 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x134 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x138 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x13C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x140 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x144 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x148 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x14C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x150 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x154 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x158 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x15C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x160 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x164 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x168 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x16C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x170 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x174 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x178 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x17C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x180 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x184 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x188 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x18C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x190 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x194 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x198 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x19C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1A4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1A8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1AC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1B4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1B8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1BC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1C4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1C8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1CC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1D4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1D8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1DC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1E4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1E8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1EC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1F4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1F8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1FC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," tree.end tree "NOC_KITE1_IN_IA_ETHR_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B501400 group.long 0x0++0x3FF line.long 0x0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "NOC_KITE1_IN_IA_FLEX0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000280 group.long 0x0++0x7F line.long 0x0 "FLEX0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "FLEX0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "FLEX0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE1_IN_IA_FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000C80 group.long 0x0++0x7F line.long 0x0 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE1_IN_IA_FLEX1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000300 group.long 0x0++0x7F line.long 0x0 "FLEX1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "FLEX1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "FLEX1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE1_IN_IA_FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000D00 group.long 0x0++0x7F line.long 0x0 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE1_IN_IA_FR_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B501800 group.long 0x0++0x3FF line.long 0x0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "FR_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x264 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x268 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x26C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x270 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x274 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x278 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x27C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x280 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x284 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x288 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x28C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x290 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x294 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x298 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x29C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2A0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2AC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2B0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2BC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2C0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2CC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2D0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2DC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2E0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2EC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2F0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2FC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x300 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x304 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x308 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x30C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x310 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x314 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x318 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x31C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x320 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x324 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x328 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x32C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x330 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x334 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x338 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x33C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x340 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x344 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x348 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x34C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x350 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x354 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x358 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x35C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x360 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x364 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x368 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x36C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x370 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x374 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x378 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x37C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x380 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x384 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x388 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x38C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x390 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x394 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x398 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x39C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3A0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3AC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3B0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3BC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3C0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3CC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3D0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3DC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3E0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3EC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3F0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3FC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," tree.end tree "NOC_KITE1_IN_IA_FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505E00 group.long 0x0++0x1FF line.long 0x0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x44 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x48 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x4C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x50 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x54 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x58 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x5C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x60 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x64 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x68 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x80 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x84 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x88 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x8C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x90 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x94 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x98 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x9C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xA4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xA8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xAC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xB4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xB8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xBC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xC4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xC8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xCC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xD4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xD8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xDC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xE4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xE8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xEC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xF4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xF8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xFC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x100 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x104 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x108 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x10C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x110 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x114 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x118 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x11C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x130 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x134 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x138 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x13C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x140 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x144 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x148 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x14C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x150 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x154 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x158 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x15C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x160 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x164 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x168 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x16C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x170 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x174 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x178 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x17C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x180 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x184 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x188 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x18C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x190 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x194 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x198 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x19C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1A4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1A8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1AC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1B4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1B8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1BC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1C4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1C8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1CC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1D4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1D8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1DC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1E4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1E8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1EC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1F4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1F8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1FC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," tree.end tree "NOC_KITE1_IN_IA_FR_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B501C00 group.long 0x0++0x3FF line.long 0x0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "FR_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "NOC_KITE1_IN_IA_GTM_M_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000380 group.long 0x0++0x7F line.long 0x0 "GTM_M_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "GTM_M_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "GTM_M_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "GTM_M_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "GTM_M_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "GTM_M_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "GTM_M_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE1_IN_IA_KITE0_PACKET_PROBE_MAIN_PROBE" base ad:0x7B502000 group.long 0x0++0x3FF line.long 0x0 "KITE0_PACKET_PROBE_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE0_PACKET_PROBE_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE0_PACKET_PROBE_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE0_PACKET_PROBE_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE0_PACKET_PROBE_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE0_PACKET_PROBE_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_PORTSEL," bitfld.long 0x270 0. "COUNTERS_7_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x274 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_104," line.long 0x284 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_105," line.long 0x288 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_106," line.long 0x28C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_107," line.long 0x290 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_108," line.long 0x294 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_109," line.long 0x298 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_110," line.long 0x29C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_111," line.long 0x2A0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_112," line.long 0x2A4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_113," line.long 0x2A8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_114," line.long 0x2AC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_115," line.long 0x2B0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_116," line.long 0x2B4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_117," line.long 0x2B8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_118," line.long 0x2BC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_119," line.long 0x2C0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_120," line.long 0x2C4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_121," line.long 0x2C8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_122," line.long 0x2CC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_123," line.long 0x2D0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_124," line.long 0x2D4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_125," line.long 0x2D8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_126," line.long 0x2DC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_127," line.long 0x2E0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_128," line.long 0x2E4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_129," line.long 0x2E8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_130," line.long 0x2EC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_131," line.long 0x2F0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_132," line.long 0x2F4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_133," line.long 0x2F8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_134," line.long 0x2FC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_135," line.long 0x300 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_136," line.long 0x304 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_137," line.long 0x308 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_138," line.long 0x30C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_139," line.long 0x310 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_140," line.long 0x314 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_141," line.long 0x318 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_142," line.long 0x31C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_143," line.long 0x320 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_144," line.long 0x324 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_145," line.long 0x328 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_146," line.long 0x32C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_147," line.long 0x330 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_148," line.long 0x334 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_149," line.long 0x338 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_150," line.long 0x33C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_151," line.long 0x340 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_152," line.long 0x344 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_153," line.long 0x348 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_154," line.long 0x34C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_155," line.long 0x350 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_156," line.long 0x354 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_157," line.long 0x358 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_158," line.long 0x35C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_159," line.long 0x360 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_160," line.long 0x364 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_161," line.long 0x368 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_162," line.long 0x36C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_163," line.long 0x370 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_164," line.long 0x374 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_165," line.long 0x378 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_166," line.long 0x37C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_167," line.long 0x380 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_168," line.long 0x384 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_169," line.long 0x388 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_170," line.long 0x38C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_171," line.long 0x390 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_172," line.long 0x394 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_173," line.long 0x398 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_174," line.long 0x39C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_175," line.long 0x3A0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_176," line.long 0x3A4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_177," line.long 0x3A8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_178," line.long 0x3AC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_179," line.long 0x3B0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_180," line.long 0x3B4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_181," line.long 0x3B8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_182," line.long 0x3BC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_183," line.long 0x3C0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_184," line.long 0x3C4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_185," line.long 0x3C8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_186," line.long 0x3CC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_187," line.long 0x3D0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_188," line.long 0x3D4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_189," line.long 0x3D8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_190," line.long 0x3DC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_191," line.long 0x3E0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_192," line.long 0x3E4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_193," line.long 0x3E8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_194," line.long 0x3EC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_195," line.long 0x3F0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_196," line.long 0x3F4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_197," line.long 0x3F8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_198," line.long 0x3FC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_199," tree.end tree "NOC_KITE1_IN_IA_KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506000 group.long 0x0++0x1FF line.long 0x0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x70 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x74 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x78 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x7C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x80 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x84 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0x88 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0x8C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0x90 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0x94 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0x98 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0x9C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xA0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xA4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xA8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xAC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xB0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xB4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xB8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xBC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xC0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xC4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xC8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xCC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xD0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xD4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xD8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xDC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xE0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xE4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0xE8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0xEC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0xF0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0xF4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0xF8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0xFC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x100 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x104 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x108 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x10C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x110 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x114 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x118 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x11C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x120 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x124 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x130 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x134 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x138 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x13C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x140 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x144 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x148 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x14C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x150 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x154 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x158 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x15C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x160 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x164 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x168 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x16C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x170 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x174 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x178 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x17C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x180 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x184 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x188 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x18C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x190 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x194 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x198 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x19C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1A0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1A4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1A8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1AC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1B0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1B4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1B8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1BC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1C0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1C4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1C8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1CC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1D0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1D4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1D8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1DC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1E0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1E4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," line.long 0x1E8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_107," line.long 0x1EC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_108," line.long 0x1F0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_109," line.long 0x1F4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_110," line.long 0x1F8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_111," line.long 0x1FC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_112," tree.end tree "NOC_KITE1_IN_IA_KITE0_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B502400 group.long 0x0++0x3FF line.long 0x0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "NOC_KITE1_IN_IA_KITE1_PACKET_PROBE_MAIN_PROBE" base ad:0x7B502800 group.long 0x0++0x3FF line.long 0x0 "KITE1_PACKET_PROBE_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE1_PACKET_PROBE_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE1_PACKET_PROBE_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE1_PACKET_PROBE_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE1_PACKET_PROBE_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE1_PACKET_PROBE_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_PORTSEL," bitfld.long 0x270 0. "COUNTERS_7_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x274 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_104," line.long 0x284 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_105," line.long 0x288 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_106," line.long 0x28C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_107," line.long 0x290 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_108," line.long 0x294 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_109," line.long 0x298 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_110," line.long 0x29C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_111," line.long 0x2A0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_112," line.long 0x2A4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_113," line.long 0x2A8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_114," line.long 0x2AC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_115," line.long 0x2B0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_116," line.long 0x2B4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_117," line.long 0x2B8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_118," line.long 0x2BC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_119," line.long 0x2C0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_120," line.long 0x2C4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_121," line.long 0x2C8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_122," line.long 0x2CC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_123," line.long 0x2D0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_124," line.long 0x2D4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_125," line.long 0x2D8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_126," line.long 0x2DC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_127," line.long 0x2E0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_128," line.long 0x2E4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_129," line.long 0x2E8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_130," line.long 0x2EC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_131," line.long 0x2F0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_132," line.long 0x2F4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_133," line.long 0x2F8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_134," line.long 0x2FC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_135," line.long 0x300 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_136," line.long 0x304 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_137," line.long 0x308 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_138," line.long 0x30C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_139," line.long 0x310 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_140," line.long 0x314 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_141," line.long 0x318 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_142," line.long 0x31C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_143," line.long 0x320 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_144," line.long 0x324 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_145," line.long 0x328 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_146," line.long 0x32C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_147," line.long 0x330 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_148," line.long 0x334 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_149," line.long 0x338 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_150," line.long 0x33C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_151," line.long 0x340 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_152," line.long 0x344 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_153," line.long 0x348 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_154," line.long 0x34C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_155," line.long 0x350 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_156," line.long 0x354 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_157," line.long 0x358 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_158," line.long 0x35C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_159," line.long 0x360 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_160," line.long 0x364 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_161," line.long 0x368 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_162," line.long 0x36C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_163," line.long 0x370 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_164," line.long 0x374 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_165," line.long 0x378 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_166," line.long 0x37C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_167," line.long 0x380 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_168," line.long 0x384 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_169," line.long 0x388 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_170," line.long 0x38C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_171," line.long 0x390 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_172," line.long 0x394 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_173," line.long 0x398 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_174," line.long 0x39C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_175," line.long 0x3A0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_176," line.long 0x3A4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_177," line.long 0x3A8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_178," line.long 0x3AC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_179," line.long 0x3B0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_180," line.long 0x3B4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_181," line.long 0x3B8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_182," line.long 0x3BC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_183," line.long 0x3C0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_184," line.long 0x3C4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_185," line.long 0x3C8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_186," line.long 0x3CC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_187," line.long 0x3D0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_188," line.long 0x3D4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_189," line.long 0x3D8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_190," line.long 0x3DC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_191," line.long 0x3E0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_192," line.long 0x3E4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_193," line.long 0x3E8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_194," line.long 0x3EC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_195," line.long 0x3F0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_196," line.long 0x3F4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_197," line.long 0x3F8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_198," line.long 0x3FC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_199," tree.end tree "NOC_KITE1_IN_IA_KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506200 group.long 0x0++0x1FF line.long 0x0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x70 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x74 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x78 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x7C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x80 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x84 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0x88 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0x8C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0x90 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0x94 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0x98 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0x9C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xA0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xA4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xA8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xAC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xB0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xB4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xB8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xBC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xC0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xC4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xC8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xCC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xD0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xD4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xD8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xDC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xE0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xE4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0xE8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0xEC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0xF0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0xF4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0xF8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0xFC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x100 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x104 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x108 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x10C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x110 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x114 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x118 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x11C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x120 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x124 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x130 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x134 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x138 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x13C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x140 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x144 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x148 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x14C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x150 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x154 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x158 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x15C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x160 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x164 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x168 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x16C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x170 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x174 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x178 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x17C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x180 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x184 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x188 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x18C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x190 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x194 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x198 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x19C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1A0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1A4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1A8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1AC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1B0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1B4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1B8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1BC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1C0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1C4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1C8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1CC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1D0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1D4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1D8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1DC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1E0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1E4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," line.long 0x1E8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_107," line.long 0x1EC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_108," line.long 0x1F0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_109," line.long 0x1F4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_110," line.long 0x1F8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_111," line.long 0x1FC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_112," tree.end tree "NOC_KITE1_IN_IA_KITE1_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B502C00 group.long 0x0++0x3FF line.long 0x0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "NOC_KITE1_IN_IA_KITE2_PACKET_PROBE_MAIN_PROBE" base ad:0x7B503000 group.long 0x0++0x3FF line.long 0x0 "KITE2_PACKET_PROBE_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE2_PACKET_PROBE_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE2_PACKET_PROBE_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE2_PACKET_PROBE_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE2_PACKET_PROBE_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE2_PACKET_PROBE_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_211," tree.end tree "NOC_KITE1_IN_IA_KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506800 group.long 0x0++0x7F line.long 0x0 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x40 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x44 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x48 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x4C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x50 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x54 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x58 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x5C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x60 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x64 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x68 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x6C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x6C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x70 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x70 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x74 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x74 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x78 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x78 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x7C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," tree.end tree "NOC_KITE1_IN_IA_KITE2_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B503400 group.long 0x0++0x3FF line.long 0x0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "NOC_KITE1_IN_IA_NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000400 group.long 0x0++0x7F line.long 0x0 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE1_IN_IA_NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000D80 group.long 0x0++0x7F line.long 0x0 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE1_IN_IA_NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000480 group.long 0x0++0x7F line.long 0x0 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE1_IN_IA_NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000E00 group.long 0x0++0x7F line.long 0x0 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE1_IN_IA_NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000500 group.long 0x0++0x7F line.long 0x0 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE1_IN_IA_NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000E80 group.long 0x0++0x7F line.long 0x0 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE1_IN_IA_OBSERVER_HSM_MAIN_ERRORLOGGER_0" base ad:0x7B506A80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "NOC_KITE1_IN_IA_OBSERVER_KITE0_MAIN_ERRORLOGGER_0" base ad:0x7B506B00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "NOC_KITE1_IN_IA_OBSERVER_KITE1_MAIN_ERRORLOGGER_0" base ad:0x7B506B80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "NOC_KITE1_IN_IA_OBSERVER_KITE2_MAIN_ERRORLOGGER_0" base ad:0x7B506C00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "NOC_KITE1_IN_IA_OBSERVER_MAIN0_MAIN_ATBENDPOINT" base ad:0x7B506900 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ATBID," hexmask.long.byte 0x8 0.--6. 1. "ATBID,ATB AtId" line.long 0xC "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ATBEN," bitfld.long 0xC 0. "ATBEN,ATB Unit Enable" "0,1" line.long 0x10 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_SYNCPERIOD," hexmask.long.byte 0x10 0.--4. 1. "SYNCPERIOD,ATB Synchro Period" line.long 0x14 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_00," line.long 0x18 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_01," line.long 0x1C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_02," line.long 0x20 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_03," line.long 0x24 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_04," line.long 0x28 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_05," line.long 0x2C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_06," line.long 0x30 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_07," line.long 0x34 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_08," line.long 0x38 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_09," line.long 0x3C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_10," line.long 0x40 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_11," line.long 0x44 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_12," line.long 0x48 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_13," line.long 0x4C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_14," line.long 0x50 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_15," line.long 0x54 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_16," line.long 0x58 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_17," line.long 0x5C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_18," line.long 0x60 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_19," line.long 0x64 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_20," line.long 0x68 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_21," line.long 0x6C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_22," line.long 0x70 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_23," line.long 0x74 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_24," line.long 0x78 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_25," line.long 0x7C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_26," tree.end tree "NOC_KITE1_IN_IA_OBSERVER_MAIN0_MAIN_ERRORLOGGER_0" base ad:0x7B506C80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "NOC_KITE1_IN_IA_OBSERVER_MAIN1_MAIN_ATBENDPOINT" base ad:0x7B506980 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ATBID," hexmask.long.byte 0x8 0.--6. 1. "ATBID,ATB AtId" line.long 0xC "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ATBEN," bitfld.long 0xC 0. "ATBEN,ATB Unit Enable" "0,1" line.long 0x10 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_SYNCPERIOD," hexmask.long.byte 0x10 0.--4. 1. "SYNCPERIOD,ATB Synchro Period" line.long 0x14 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_00," line.long 0x18 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_01," line.long 0x1C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_02," line.long 0x20 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_03," line.long 0x24 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_04," line.long 0x28 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_05," line.long 0x2C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_06," line.long 0x30 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_07," line.long 0x34 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_08," line.long 0x38 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_09," line.long 0x3C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_10," line.long 0x40 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_11," line.long 0x44 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_12," line.long 0x48 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_13," line.long 0x4C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_14," line.long 0x50 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_15," line.long 0x54 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_16," line.long 0x58 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_17," line.long 0x5C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_18," line.long 0x60 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_19," line.long 0x64 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_20," line.long 0x68 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_21," line.long 0x6C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_22," line.long 0x70 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_23," line.long 0x74 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_24," line.long 0x78 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_25," line.long 0x7C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_26," tree.end tree "NOC_KITE1_IN_IA_OBSERVER_MAIN1_MAIN_ERRORLOGGER_0" base ad:0x7B506D00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "NOC_KITE1_IN_IA_OBSERVER_PCIE_MAIN_ATBENDPOINT" base ad:0x7B506A00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_PCIE_MAIN_ATBENDPOINT_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_PCIE_MAIN_ATBENDPOINT_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_PCIE_MAIN_ATBENDPOINT_ATBID," hexmask.long.byte 0x8 0.--6. 1. "ATBID,ATB AtId" line.long 0xC "OBSERVER_PCIE_MAIN_ATBENDPOINT_ATBEN," bitfld.long 0xC 0. "ATBEN,ATB Unit Enable" "0,1" line.long 0x10 "OBSERVER_PCIE_MAIN_ATBENDPOINT_SYNCPERIOD," hexmask.long.byte 0x10 0.--4. 1. "SYNCPERIOD,ATB Synchro Period" line.long 0x14 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_00," line.long 0x18 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_01," line.long 0x1C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_02," line.long 0x20 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_03," line.long 0x24 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_04," line.long 0x28 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_05," line.long 0x2C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_06," line.long 0x30 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_07," line.long 0x34 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_08," line.long 0x38 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_09," line.long 0x3C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_10," line.long 0x40 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_11," line.long 0x44 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_12," line.long 0x48 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_13," line.long 0x4C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_14," line.long 0x50 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_15," line.long 0x54 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_16," line.long 0x58 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_17," line.long 0x5C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_18," line.long 0x60 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_19," line.long 0x64 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_20," line.long 0x68 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_21," line.long 0x6C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_22," line.long 0x70 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_23," line.long 0x74 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_24," line.long 0x78 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_25," line.long 0x7C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_26," tree.end tree "NOC_KITE1_IN_IA_OBSERVER_PCIE_MAIN_ERRORLOGGER_0" base ad:0x7B506D80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "NOC_KITE1_IN_IA_PCIE_0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000580 group.long 0x0++0x7F line.long 0x0 "PCIE_0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "PCIE_0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "PCIE_0_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "PCIE_0_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "PCIE_0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE1_IN_IA_PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000F00 group.long 0x0++0x7F line.long 0x0 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE1_IN_IA_PCIE_1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000600 group.long 0x0++0x7F line.long 0x0 "PCIE_1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "PCIE_1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "PCIE_1_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "PCIE_1_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "PCIE_1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE1_IN_IA_PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000F80 group.long 0x0++0x7F line.long 0x0 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE1_IN_IA_PCIE_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B503800 group.long 0x0++0x3FF line.long 0x0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x234 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x238 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x23C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x240 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x244 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x248 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x24C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x250 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x254 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x258 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x25C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x260 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x264 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x268 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x26C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x270 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x274 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x278 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x27C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x280 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x284 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x288 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x28C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x290 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x294 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x298 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x29C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2A0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2A4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2A8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2AC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2B0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2B4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2B8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2BC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2C0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2C4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2C8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2CC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x2D0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x2D4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x2D8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x2DC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x2E0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x2E4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x2E8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x2EC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x2F0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x2F4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x2F8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x2FC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x300 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x304 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x308 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x30C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x310 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x314 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x318 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x31C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x320 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x324 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x328 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x32C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x330 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x334 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x338 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x33C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x340 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x344 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x348 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x34C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x350 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x354 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x358 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x35C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x360 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x364 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x368 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x36C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x370 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x374 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x378 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x37C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x380 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x384 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x388 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x38C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x390 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x394 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x398 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x39C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3A0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3A4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3A8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3AC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3B0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3B4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3B8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3BC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3C0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3C4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3C8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3CC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," line.long 0x3D0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_208," line.long 0x3D4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_209," line.long 0x3D8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_210," line.long 0x3DC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_211," line.long 0x3E0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_212," line.long 0x3E4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_213," line.long 0x3E8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_214," line.long 0x3EC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_215," line.long 0x3F0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_216," line.long 0x3F4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_217," line.long 0x3F8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_218," line.long 0x3FC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_219," tree.end tree "NOC_KITE1_IN_IA_PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506880 group.long 0x0++0x7F line.long 0x0 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x38 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x3C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x40 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x44 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x48 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x6C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x70 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x70 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x74 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x74 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x78 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x78 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x7C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," tree.end tree "NOC_KITE1_IN_IA_PCIE_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B503C00 group.long 0x0++0x3FF line.long 0x0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "NOC_KITE1_IN_IA_POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER" base ad:0x7B506E00 group.long 0x0++0x7F line.long 0x0 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT0," hexmask.long 0x8 0.--31. 1. "MISSIONFAULT0,MissionFault0 register" line.long 0xC "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT1," hexmask.long 0xC 0.--31. 1. "MISSIONFAULT1,MissionFault1 register" line.long 0x10 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT2," hexmask.long 0x10 0.--31. 1. "MISSIONFAULT2,MissionFault2 register" line.long 0x14 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT3," hexmask.long 0x14 0.--31. 1. "MISSIONFAULT3,MissionFault3 register" line.long 0x18 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT0," hexmask.long 0x18 0.--31. 1. "LATENTFAULT0,LatentFault0 register" line.long 0x1C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT1," hexmask.long 0x1C 0.--31. 1. "LATENTFAULT1,LatentFault1 register" line.long 0x20 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT2," hexmask.long 0x20 0.--31. 1. "LATENTFAULT2,LatentFault2 register" line.long 0x24 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT3," hexmask.long 0x24 0.--31. 1. "LATENTFAULT3,LatentFault3 register" line.long 0x28 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_FAULTS," bitfld.long 0x28 1. "MISSIONFAULT,Mission Fault" "0,1" bitfld.long 0x28 0. "LATENTFAULT,Latent Fault" "0,1" line.long 0x2C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_INTEN," bitfld.long 0x2C 1. "MISSIONFAULTEN,MissionFault Interrupt enable" "0,1" bitfld.long 0x2C 0. "BISTDONEEN,BistDone Interrupt enable" "0,1" line.long 0x30 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_INTCLR," bitfld.long 0x30 1. "MISSIONFAULTCLR,Clear Mission Fault" "0,1" bitfld.long 0x30 0. "LATENTFAULTCLR,Clear Latent Fault" "0,1" line.long 0x34 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTCTL," bitfld.long 0x34 1. "BISTDONECLR,Clear BistDone" "0,1" bitfld.long 0x34 0. "BISTSTART,Start Bist sequence" "0,1" line.long 0x38 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTDONE," bitfld.long 0x38 1. "MISSIONMODE,Mission Mode Status" "0,1" bitfld.long 0x38 0. "BISTDONE,BistDone Status" "0,1" line.long 0x3C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO1," hexmask.long.word 0x3C 0.--15. 1. "BISTTO1,BistTimeOut register" line.long 0x40 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO2," hexmask.long.byte 0x40 0.--7. 1. "BISTTO2,BistTimeOut register" line.long 0x44 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_00," line.long 0x48 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_01," line.long 0x4C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_02," line.long 0x50 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_03," line.long 0x54 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_04," line.long 0x58 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_05," line.long 0x5C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_06," line.long 0x60 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_07," line.long 0x64 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_08," line.long 0x68 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_09," line.long 0x6C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_10," line.long 0x70 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_11," line.long 0x74 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_12," line.long 0x78 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_13," line.long 0x7C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_14," tree.end tree "NOC_KITE1_IN_IA_POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER" base ad:0x7B506E80 group.long 0x0++0x7F line.long 0x0 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT0," hexmask.long 0x8 0.--31. 1. "MISSIONFAULT0,MissionFault0 register" line.long 0xC "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT1," hexmask.long 0xC 0.--31. 1. "MISSIONFAULT1,MissionFault1 register" line.long 0x10 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT2," hexmask.long 0x10 0.--31. 1. "MISSIONFAULT2,MissionFault2 register" line.long 0x14 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT3," hexmask.long 0x14 0.--31. 1. "MISSIONFAULT3,MissionFault3 register" line.long 0x18 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT0," hexmask.long 0x18 0.--31. 1. "LATENTFAULT0,LatentFault0 register" line.long 0x1C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT1," hexmask.long 0x1C 0.--31. 1. "LATENTFAULT1,LatentFault1 register" line.long 0x20 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT2," hexmask.long 0x20 0.--31. 1. "LATENTFAULT2,LatentFault2 register" line.long 0x24 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT3," hexmask.long 0x24 0.--31. 1. "LATENTFAULT3,LatentFault3 register" line.long 0x28 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_FAULTS," bitfld.long 0x28 1. "MISSIONFAULT,Mission Fault" "0,1" bitfld.long 0x28 0. "LATENTFAULT,Latent Fault" "0,1" line.long 0x2C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_INTEN," bitfld.long 0x2C 1. "MISSIONFAULTEN,MissionFault Interrupt enable" "0,1" bitfld.long 0x2C 0. "BISTDONEEN,BistDone Interrupt enable" "0,1" line.long 0x30 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_INTCLR," bitfld.long 0x30 1. "MISSIONFAULTCLR,Clear Mission Fault" "0,1" bitfld.long 0x30 0. "LATENTFAULTCLR,Clear Latent Fault" "0,1" line.long 0x34 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTCTL," bitfld.long 0x34 1. "BISTDONECLR,Clear BistDone" "0,1" bitfld.long 0x34 0. "BISTSTART,Start Bist sequence" "0,1" line.long 0x38 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTDONE," bitfld.long 0x38 1. "MISSIONMODE,Mission Mode Status" "0,1" bitfld.long 0x38 0. "BISTDONE,BistDone Status" "0,1" line.long 0x3C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO1," hexmask.long.word 0x3C 0.--15. 1. "BISTTO1,BistTimeOut register" line.long 0x40 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO2," hexmask.long.byte 0x40 0.--7. 1. "BISTTO2,BistTimeOut register" line.long 0x44 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_00," line.long 0x48 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_01," line.long 0x4C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_02," line.long 0x50 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_03," line.long 0x54 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_04," line.long 0x58 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_05," line.long 0x5C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_06," line.long 0x60 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_07," line.long 0x64 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_08," line.long 0x68 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_09," line.long 0x6C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_10," line.long 0x70 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_11," line.long 0x74 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_12," line.long 0x78 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_13," line.long 0x7C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_14," tree.end tree "NOC_KITE1_IN_IA_SDMMC_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000680 group.long 0x0++0x7F line.long 0x0 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE1_IN_IA_SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001000 group.long 0x0++0x7F line.long 0x0 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE1_IN_IA_SDMMC_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B504000 group.long 0x0++0x3FF line.long 0x0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x14 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x34 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x3C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x4C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x50 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x54 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x58 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x5C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x60 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x64 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x68 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x6C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x70 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x74 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x78 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x7C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x80 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x90 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x98 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0x9C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xB8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xBC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xC8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xCC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xD8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xDC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xE8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xEC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xF8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0xFC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x100 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x104 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x108 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x10C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x110 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x114 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x118 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x11C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x120 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x124 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x128 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x12C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x130 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x134 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x138 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x13C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x140 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x144 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x148 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x14C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x150 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x154 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x158 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x15C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x160 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x164 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x168 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x16C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x170 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x174 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x178 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x17C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x180 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x184 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x188 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x18C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x190 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x194 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x198 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x19C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1A8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1AC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1B8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1BC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1C8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1CC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1D8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1DC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1E8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1EC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1F8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x1FC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x200 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x204 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x214 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x224 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x234 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x244 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x254 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x264 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x274 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x284 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x288 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x28C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x290 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x294 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x298 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x29C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2A8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2AC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2B8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2BC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2C8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2CC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2D8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2DC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2E8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2EC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2F8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x2FC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x300 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x304 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x308 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x30C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x310 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x314 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x318 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x31C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x320 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x324 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x328 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x32C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x330 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x334 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x338 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x33C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x340 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x344 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x348 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x34C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x350 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x354 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x358 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x35C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x360 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x364 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x368 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x36C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x370 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x374 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x378 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x37C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x380 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x384 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x388 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x38C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x390 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x394 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x398 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x39C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3A8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3AC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3B8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3BC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3C8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3CC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3D8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3DC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3E8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3EC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3F8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," line.long 0x3FC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_208," tree.end tree "NOC_KITE1_IN_IA_SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506400 group.long 0x0++0x1FF line.long 0x0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x70 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x74 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x78 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x7C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x80 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x84 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0x88 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0x8C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0x90 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0x94 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0x98 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0x9C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xA0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xA4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xA8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xAC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xB0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xB4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xB8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xBC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xC0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xC4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xC8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xCC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xD0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xD4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xD8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xDC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xE0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xE4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0xE8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0xEC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0xF0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0xF4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0xF8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0xFC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x100 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x104 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x108 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x10C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x110 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x114 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x118 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x11C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x120 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x124 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x130 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x134 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x138 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x13C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x140 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x144 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x148 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x14C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x150 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x154 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x158 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x15C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x160 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x164 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x168 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x16C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x170 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x174 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x178 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x17C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x180 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x184 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x188 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x18C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x190 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x194 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x198 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x19C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1A0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1A4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1A8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1AC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1B0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1B4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1B8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1BC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1C0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1C4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1C8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1CC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1D0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1D4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1D8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1DC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1E0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1E4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," line.long 0x1E8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_107," line.long 0x1EC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_108," line.long 0x1F0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_109," line.long 0x1F4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_110," line.long 0x1F8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_111," line.long 0x1FC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_112," tree.end tree "NOC_KITE1_IN_IA_SDMMC_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B504400 group.long 0x0++0x3FF line.long 0x0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x14 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x34 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x3C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x4C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x50 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x54 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x58 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x5C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x60 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x64 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x68 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x6C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x70 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x74 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x78 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x7C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x80 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x90 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x98 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0x9C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xB8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xBC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xC8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xCC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xD8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xDC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xE8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xEC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xF8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0xFC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x100 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x104 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x108 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x10C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x110 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x114 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x118 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x11C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x120 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x124 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x128 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x12C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x130 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x134 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x138 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x13C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x140 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x144 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x148 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x14C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x150 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x154 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x158 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x15C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x160 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x164 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x168 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x16C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x170 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x174 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x178 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x17C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x180 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x184 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x188 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x18C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x190 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x194 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x198 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x19C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1A8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1AC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1B8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1BC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1C8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1CC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1D8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1DC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1E8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1EC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1F8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x1FC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x200 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x204 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x214 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x218 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x21C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x220 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x224 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x228 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x22C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x230 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x234 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x238 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x23C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x240 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x244 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x248 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x24C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x250 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x254 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x258 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x25C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x260 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x264 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x268 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x26C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x270 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x274 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x278 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x27C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x280 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x284 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x288 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x28C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x290 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x294 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x298 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x29C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2A4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2A8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2AC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2B4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2B8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2BC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2C4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2C8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2CC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2D4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2D8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2DC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2E4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2E8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2EC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2F4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x2F8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x2FC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x300 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x304 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x308 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x30C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x310 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x314 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x318 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x31C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x320 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x324 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x328 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x32C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x330 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x334 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x338 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x33C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x340 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x344 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x348 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x34C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x350 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x354 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x358 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x35C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x360 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x364 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x368 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x36C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x370 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x374 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x378 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x37C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x380 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x384 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x388 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x38C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x390 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x394 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x398 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x39C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3A4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3A8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3AC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3B4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3B8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3BC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3C4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3C8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3CC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3D4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3D8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3DC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3E4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3E8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3EC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3F4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," line.long 0x3F8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_228," line.long 0x3FC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_229," tree.end tree "NOC_KITE1_IN_IA_SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000700 group.long 0x0++0x7F line.long 0x0 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE1_IN_IA_SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000780 group.long 0x0++0x7F line.long 0x0 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE1_IN_IA_SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000800 group.long 0x0++0x7F line.long 0x0 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE1_IN_IA_SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B504800 group.long 0x0++0x3FF line.long 0x0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "NOC_KITE1_IN_IA_SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B504C00 group.long 0x0++0x3FF line.long 0x0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "NOC_KITE1_IN_IA_ZIPW0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000880 group.long 0x0++0x7F line.long 0x0 "ZIPW0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ZIPW0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ZIPW0_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ZIPW0_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ZIPW0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE1_IN_IA_ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001080 group.long 0x0++0x7F line.long 0x0 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE1_IN_IA_ZIPW1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000900 group.long 0x0++0x7F line.long 0x0 "ZIPW1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ZIPW1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ZIPW1_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ZIPW1_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ZIPW1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE1_IN_IA_ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001100 group.long 0x0++0x7F line.long 0x0 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE1_IN_IA_ZIPW_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B505000 group.long 0x0++0x3FF line.long 0x0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x264 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x268 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x26C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x270 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x274 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x278 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x27C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x280 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x284 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x288 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x28C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x290 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x294 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x298 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x29C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2A0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2AC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2B0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2BC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2C0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2CC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2D0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2DC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2E0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2EC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2F0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2FC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x300 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x304 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x308 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x30C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x310 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x314 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x318 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x31C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x320 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x324 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x328 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x32C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x330 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x334 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x338 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x33C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x340 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x344 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x348 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x34C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x350 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x354 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x358 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x35C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x360 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x364 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x368 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x36C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x370 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x374 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x378 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x37C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x380 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x384 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x388 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x38C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x390 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x394 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x398 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x39C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3A0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3AC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3B0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3BC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3C0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3CC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3D0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3DC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3E0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3EC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3F0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3FC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," tree.end tree "NOC_KITE1_IN_IA_ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506600 group.long 0x0++0x1FF line.long 0x0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x44 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x48 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x4C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x50 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x54 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x58 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x5C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x60 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x64 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x68 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x80 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x84 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x88 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x8C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x90 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x94 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x98 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x9C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xA4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xA8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xAC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xB4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xB8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xBC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xC4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xC8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xCC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xD4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xD8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xDC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xE4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xE8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xEC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xF4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xF8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xFC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x100 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x104 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x108 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x10C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x110 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x114 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x118 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x11C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x130 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x134 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x138 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x13C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x140 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x144 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x148 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x14C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x150 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x154 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x158 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x15C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x160 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x164 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x168 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x16C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x170 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x174 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x178 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x17C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x180 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x184 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x188 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x18C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x190 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x194 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x198 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x19C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1A4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1A8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1AC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1B4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1B8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1BC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1C4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1C8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1CC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1D4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1D8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1DC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1E4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1E8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1EC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1F4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1F8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1FC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," tree.end tree "NOC_KITE1_IN_IA_ZIPW_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B505400 group.long 0x0++0x3FF line.long 0x0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree.end tree "NOC_KITE2" tree "NOC_KITE2_IN_IA_DAP0_AXI_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000000 group.long 0x0++0x7F line.long 0x0 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE2_IN_IA_DAP1_AXI_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000080 group.long 0x0++0x7F line.long 0x0 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE2_IN_IA_DFA_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000100 group.long 0x0++0x7F line.long 0x0 "DFA_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DFA_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DFA_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "DFA_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "DFA_IN_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--12. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "DFA_IN_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "DFA_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE2_IN_IA_DMA0_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B500000 group.long 0x0++0x3FF line.long 0x0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_PORTSEL," bitfld.long 0x270 0. "COUNTERS_7_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x274 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x284 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x288 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x28C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x290 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x294 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x298 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x29C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x2A0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x2A4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x2A8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x2AC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x2B0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x2B4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x2B8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x2BC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2C0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2C4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2C8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2CC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2D0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2D4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2D8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2DC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2E0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2E4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2E8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2EC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2F0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2F4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2F8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2FC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x300 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x304 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x308 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x30C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x310 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x314 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x318 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x31C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x320 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x324 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x328 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x32C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x330 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x334 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x338 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x33C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x340 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x344 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x348 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x34C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x350 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x354 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x358 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x35C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x360 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x364 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x368 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x36C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x370 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x374 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x378 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x37C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x380 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x384 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x388 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x38C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x390 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x394 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x398 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x39C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x3A0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x3A4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x3A8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x3AC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x3B0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x3B4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x3B8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x3BC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3C0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3C4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3C8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3CC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3D0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3D4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3D8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3DC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3E0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3E4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3E8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3EC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3F0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3F4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3F8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3FC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," tree.end tree "NOC_KITE2_IN_IA_DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505800 group.long 0x0++0x1FF line.long 0x0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x4C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x50 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x54 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x58 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x5C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x60 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x64 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x68 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_5," hexmask.long.byte 0x7C 0.--3. 1. "THRESHOLDS_1_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x80 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_6," hexmask.long.byte 0x80 0.--3. 1. "THRESHOLDS_1_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x84 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x88 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x8C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x90 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x94 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x98 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x9C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0xA0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0xA4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0xA8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0xAC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xB0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xB4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xB8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xBC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xC0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xC4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xC8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xCC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xD0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xD4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xD8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xDC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xE0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xE4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xE8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xEC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xF0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xF4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xF8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xFC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0x100 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0x104 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0x108 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0x10C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x110 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x114 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x118 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x11C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x130 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x134 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x138 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x13C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x140 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x144 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x148 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x14C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x150 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x154 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x158 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x15C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x160 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x164 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x168 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x16C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x170 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x174 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x178 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x17C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x180 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x184 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x188 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x18C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x190 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x194 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x198 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x19C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x1A0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x1A4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x1A8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x1AC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1B0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1B4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1B8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1BC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1C0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1C4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1C8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1CC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1D0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1D4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1D8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1DC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1E0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1E4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1E8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1EC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1F0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1F4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1F8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1FC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," tree.end tree "NOC_KITE2_IN_IA_DMA0_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B500400 group.long 0x0++0x3FF line.long 0x0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "NOC_KITE2_IN_IA_DMA1_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B500800 group.long 0x0++0x3FF line.long 0x0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x274 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x278 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x27C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x280 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x284 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x288 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x28C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x290 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x294 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x298 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x29C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x2A0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x2A4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x2A8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x2AC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2B0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2B4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2B8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2BC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2C0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2C4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2C8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2CC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2D0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2D4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2D8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2DC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2E0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2E4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2E8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2EC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2F0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2F4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2F8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2FC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x300 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x304 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x308 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x30C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x310 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x314 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x318 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x31C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x320 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x324 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x328 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x32C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x330 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x334 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x338 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x33C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x340 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x344 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x348 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x34C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x350 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x354 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x358 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x35C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x360 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x364 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x368 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x36C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x370 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x374 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x378 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x37C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x380 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x384 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x388 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x38C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x390 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x394 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x398 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x39C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x3A0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x3A4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x3A8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x3AC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3B0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3B4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3B8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3BC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3C0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3C4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3C8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3CC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3D0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3D4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3D8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3DC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3E0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3E4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3E8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3EC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3F0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3F4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3F8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3FC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," tree.end tree "NOC_KITE2_IN_IA_DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505A00 group.long 0x0++0x1FF line.long 0x0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x48 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x4C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x50 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x54 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x58 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x5C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x60 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x64 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x68 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_5," hexmask.long.byte 0x7C 0.--3. 1. "THRESHOLDS_1_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x80 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x84 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x88 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x8C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x90 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x94 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x98 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x9C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0xA0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0xA4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xAC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xB0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xB4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xBC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xC0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xC4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xCC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xD0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xD4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xDC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xE0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xE4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xEC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xF0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xF4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xFC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0x100 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0x104 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x108 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x10C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x110 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x114 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x118 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x11C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x130 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x134 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x138 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x13C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x140 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x144 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x148 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x14C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x150 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x154 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x158 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x15C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x160 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x164 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x168 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x16C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x170 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x174 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x178 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x17C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x180 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x184 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x188 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x18C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x190 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x194 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x198 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x19C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x1A0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x1A4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1AC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1B0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1B4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1BC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1C0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1C4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1CC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1D0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1D4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1DC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1E0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1E4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1EC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1F0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1F4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1FC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," tree.end tree "NOC_KITE2_IN_IA_DMA1_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B500C00 group.long 0x0++0x3FF line.long 0x0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "NOC_KITE2_IN_IA_EDMA_0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000980 group.long 0x0++0x7F line.long 0x0 "EDMA_0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE2_IN_IA_EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001180 group.long 0x0++0x7F line.long 0x0 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE2_IN_IA_EDMA_1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000A00 group.long 0x0++0x7F line.long 0x0 "EDMA_1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE2_IN_IA_EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001200 group.long 0x0++0x7F line.long 0x0 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE2_IN_IA_EDMA_2_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000A80 group.long 0x0++0x7F line.long 0x0 "EDMA_2_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_2_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_2_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_2_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_2_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE2_IN_IA_EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001280 group.long 0x0++0x7F line.long 0x0 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE2_IN_IA_EDMA_3_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000B00 group.long 0x0++0x7F line.long 0x0 "EDMA_3_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_3_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_3_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_3_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_3_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE2_IN_IA_EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001300 group.long 0x0++0x7F line.long 0x0 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE2_IN_IA_ETHER0_I_MAIN_QOSGENERATOR" base ad:0x7B000180 group.long 0x0++0x7F line.long 0x0 "ETHER0_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER0_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER0_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ETHER0_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ETHER0_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ETHER0_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ETHER0_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE2_IN_IA_ETHER0_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000B80 group.long 0x0++0x7F line.long 0x0 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE2_IN_IA_ETHER1_I_MAIN_QOSGENERATOR" base ad:0x7B000200 group.long 0x0++0x7F line.long 0x0 "ETHER1_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER1_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER1_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ETHER1_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ETHER1_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ETHER1_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ETHER1_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE2_IN_IA_ETHER1_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000C00 group.long 0x0++0x7F line.long 0x0 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE2_IN_IA_ETHR_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B501000 group.long 0x0++0x3FF line.long 0x0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x264 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x268 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x26C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x270 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x274 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x278 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x27C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x280 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x284 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x288 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x28C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x290 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x294 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x298 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x29C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2A0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2AC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2B0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2BC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2C0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2CC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2D0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2DC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2E0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2EC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2F0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2FC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x300 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x304 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x308 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x30C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x310 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x314 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x318 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x31C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x320 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x324 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x328 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x32C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x330 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x334 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x338 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x33C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x340 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x344 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x348 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x34C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x350 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x354 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x358 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x35C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x360 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x364 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x368 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x36C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x370 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x374 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x378 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x37C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x380 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x384 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x388 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x38C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x390 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x394 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x398 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x39C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3A0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3AC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3B0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3BC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3C0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3CC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3D0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3DC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3E0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3EC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3F0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3FC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," tree.end tree "NOC_KITE2_IN_IA_ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505C00 group.long 0x0++0x1FF line.long 0x0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x44 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x48 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x4C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x50 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x54 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x58 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x5C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x60 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x64 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x68 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x80 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x84 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x88 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x8C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x90 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x94 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x98 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x9C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xA4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xA8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xAC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xB4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xB8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xBC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xC4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xC8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xCC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xD4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xD8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xDC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xE4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xE8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xEC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xF4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xF8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xFC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x100 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x104 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x108 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x10C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x110 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x114 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x118 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x11C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x130 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x134 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x138 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x13C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x140 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x144 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x148 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x14C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x150 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x154 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x158 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x15C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x160 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x164 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x168 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x16C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x170 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x174 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x178 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x17C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x180 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x184 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x188 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x18C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x190 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x194 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x198 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x19C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1A4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1A8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1AC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1B4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1B8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1BC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1C4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1C8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1CC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1D4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1D8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1DC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1E4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1E8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1EC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1F4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1F8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1FC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," tree.end tree "NOC_KITE2_IN_IA_ETHR_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B501400 group.long 0x0++0x3FF line.long 0x0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "NOC_KITE2_IN_IA_FLEX0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000280 group.long 0x0++0x7F line.long 0x0 "FLEX0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "FLEX0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "FLEX0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE2_IN_IA_FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000C80 group.long 0x0++0x7F line.long 0x0 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE2_IN_IA_FLEX1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000300 group.long 0x0++0x7F line.long 0x0 "FLEX1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "FLEX1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "FLEX1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE2_IN_IA_FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000D00 group.long 0x0++0x7F line.long 0x0 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE2_IN_IA_FR_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B501800 group.long 0x0++0x3FF line.long 0x0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "FR_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x264 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x268 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x26C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x270 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x274 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x278 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x27C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x280 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x284 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x288 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x28C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x290 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x294 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x298 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x29C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2A0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2AC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2B0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2BC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2C0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2CC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2D0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2DC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2E0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2EC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2F0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2FC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x300 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x304 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x308 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x30C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x310 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x314 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x318 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x31C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x320 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x324 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x328 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x32C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x330 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x334 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x338 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x33C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x340 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x344 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x348 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x34C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x350 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x354 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x358 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x35C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x360 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x364 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x368 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x36C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x370 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x374 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x378 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x37C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x380 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x384 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x388 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x38C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x390 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x394 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x398 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x39C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3A0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3AC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3B0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3BC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3C0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3CC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3D0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3DC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3E0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3EC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3F0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3FC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," tree.end tree "NOC_KITE2_IN_IA_FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505E00 group.long 0x0++0x1FF line.long 0x0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x44 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x48 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x4C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x50 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x54 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x58 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x5C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x60 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x64 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x68 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x80 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x84 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x88 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x8C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x90 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x94 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x98 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x9C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xA4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xA8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xAC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xB4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xB8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xBC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xC4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xC8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xCC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xD4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xD8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xDC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xE4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xE8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xEC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xF4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xF8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xFC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x100 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x104 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x108 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x10C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x110 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x114 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x118 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x11C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x130 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x134 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x138 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x13C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x140 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x144 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x148 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x14C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x150 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x154 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x158 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x15C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x160 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x164 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x168 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x16C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x170 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x174 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x178 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x17C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x180 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x184 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x188 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x18C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x190 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x194 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x198 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x19C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1A4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1A8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1AC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1B4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1B8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1BC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1C4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1C8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1CC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1D4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1D8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1DC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1E4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1E8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1EC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1F4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1F8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1FC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," tree.end tree "NOC_KITE2_IN_IA_FR_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B501C00 group.long 0x0++0x3FF line.long 0x0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "FR_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "NOC_KITE2_IN_IA_GTM_M_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000380 group.long 0x0++0x7F line.long 0x0 "GTM_M_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "GTM_M_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "GTM_M_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "GTM_M_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "GTM_M_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "GTM_M_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "GTM_M_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE2_IN_IA_KITE0_PACKET_PROBE_MAIN_PROBE" base ad:0x7B502000 group.long 0x0++0x3FF line.long 0x0 "KITE0_PACKET_PROBE_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE0_PACKET_PROBE_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE0_PACKET_PROBE_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE0_PACKET_PROBE_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE0_PACKET_PROBE_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE0_PACKET_PROBE_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_PORTSEL," bitfld.long 0x270 0. "COUNTERS_7_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x274 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_104," line.long 0x284 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_105," line.long 0x288 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_106," line.long 0x28C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_107," line.long 0x290 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_108," line.long 0x294 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_109," line.long 0x298 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_110," line.long 0x29C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_111," line.long 0x2A0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_112," line.long 0x2A4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_113," line.long 0x2A8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_114," line.long 0x2AC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_115," line.long 0x2B0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_116," line.long 0x2B4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_117," line.long 0x2B8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_118," line.long 0x2BC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_119," line.long 0x2C0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_120," line.long 0x2C4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_121," line.long 0x2C8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_122," line.long 0x2CC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_123," line.long 0x2D0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_124," line.long 0x2D4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_125," line.long 0x2D8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_126," line.long 0x2DC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_127," line.long 0x2E0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_128," line.long 0x2E4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_129," line.long 0x2E8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_130," line.long 0x2EC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_131," line.long 0x2F0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_132," line.long 0x2F4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_133," line.long 0x2F8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_134," line.long 0x2FC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_135," line.long 0x300 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_136," line.long 0x304 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_137," line.long 0x308 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_138," line.long 0x30C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_139," line.long 0x310 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_140," line.long 0x314 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_141," line.long 0x318 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_142," line.long 0x31C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_143," line.long 0x320 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_144," line.long 0x324 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_145," line.long 0x328 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_146," line.long 0x32C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_147," line.long 0x330 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_148," line.long 0x334 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_149," line.long 0x338 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_150," line.long 0x33C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_151," line.long 0x340 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_152," line.long 0x344 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_153," line.long 0x348 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_154," line.long 0x34C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_155," line.long 0x350 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_156," line.long 0x354 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_157," line.long 0x358 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_158," line.long 0x35C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_159," line.long 0x360 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_160," line.long 0x364 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_161," line.long 0x368 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_162," line.long 0x36C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_163," line.long 0x370 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_164," line.long 0x374 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_165," line.long 0x378 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_166," line.long 0x37C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_167," line.long 0x380 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_168," line.long 0x384 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_169," line.long 0x388 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_170," line.long 0x38C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_171," line.long 0x390 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_172," line.long 0x394 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_173," line.long 0x398 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_174," line.long 0x39C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_175," line.long 0x3A0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_176," line.long 0x3A4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_177," line.long 0x3A8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_178," line.long 0x3AC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_179," line.long 0x3B0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_180," line.long 0x3B4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_181," line.long 0x3B8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_182," line.long 0x3BC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_183," line.long 0x3C0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_184," line.long 0x3C4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_185," line.long 0x3C8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_186," line.long 0x3CC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_187," line.long 0x3D0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_188," line.long 0x3D4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_189," line.long 0x3D8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_190," line.long 0x3DC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_191," line.long 0x3E0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_192," line.long 0x3E4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_193," line.long 0x3E8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_194," line.long 0x3EC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_195," line.long 0x3F0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_196," line.long 0x3F4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_197," line.long 0x3F8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_198," line.long 0x3FC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_199," tree.end tree "NOC_KITE2_IN_IA_KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506000 group.long 0x0++0x1FF line.long 0x0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x70 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x74 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x78 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x7C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x80 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x84 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0x88 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0x8C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0x90 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0x94 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0x98 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0x9C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xA0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xA4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xA8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xAC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xB0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xB4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xB8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xBC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xC0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xC4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xC8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xCC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xD0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xD4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xD8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xDC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xE0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xE4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0xE8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0xEC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0xF0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0xF4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0xF8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0xFC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x100 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x104 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x108 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x10C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x110 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x114 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x118 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x11C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x120 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x124 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x130 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x134 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x138 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x13C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x140 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x144 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x148 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x14C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x150 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x154 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x158 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x15C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x160 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x164 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x168 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x16C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x170 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x174 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x178 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x17C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x180 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x184 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x188 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x18C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x190 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x194 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x198 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x19C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1A0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1A4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1A8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1AC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1B0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1B4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1B8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1BC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1C0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1C4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1C8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1CC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1D0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1D4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1D8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1DC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1E0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1E4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," line.long 0x1E8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_107," line.long 0x1EC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_108," line.long 0x1F0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_109," line.long 0x1F4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_110," line.long 0x1F8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_111," line.long 0x1FC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_112," tree.end tree "NOC_KITE2_IN_IA_KITE0_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B502400 group.long 0x0++0x3FF line.long 0x0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "NOC_KITE2_IN_IA_KITE1_PACKET_PROBE_MAIN_PROBE" base ad:0x7B502800 group.long 0x0++0x3FF line.long 0x0 "KITE1_PACKET_PROBE_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE1_PACKET_PROBE_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE1_PACKET_PROBE_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE1_PACKET_PROBE_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE1_PACKET_PROBE_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE1_PACKET_PROBE_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_PORTSEL," bitfld.long 0x270 0. "COUNTERS_7_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x274 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_104," line.long 0x284 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_105," line.long 0x288 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_106," line.long 0x28C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_107," line.long 0x290 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_108," line.long 0x294 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_109," line.long 0x298 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_110," line.long 0x29C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_111," line.long 0x2A0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_112," line.long 0x2A4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_113," line.long 0x2A8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_114," line.long 0x2AC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_115," line.long 0x2B0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_116," line.long 0x2B4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_117," line.long 0x2B8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_118," line.long 0x2BC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_119," line.long 0x2C0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_120," line.long 0x2C4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_121," line.long 0x2C8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_122," line.long 0x2CC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_123," line.long 0x2D0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_124," line.long 0x2D4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_125," line.long 0x2D8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_126," line.long 0x2DC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_127," line.long 0x2E0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_128," line.long 0x2E4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_129," line.long 0x2E8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_130," line.long 0x2EC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_131," line.long 0x2F0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_132," line.long 0x2F4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_133," line.long 0x2F8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_134," line.long 0x2FC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_135," line.long 0x300 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_136," line.long 0x304 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_137," line.long 0x308 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_138," line.long 0x30C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_139," line.long 0x310 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_140," line.long 0x314 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_141," line.long 0x318 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_142," line.long 0x31C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_143," line.long 0x320 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_144," line.long 0x324 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_145," line.long 0x328 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_146," line.long 0x32C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_147," line.long 0x330 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_148," line.long 0x334 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_149," line.long 0x338 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_150," line.long 0x33C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_151," line.long 0x340 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_152," line.long 0x344 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_153," line.long 0x348 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_154," line.long 0x34C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_155," line.long 0x350 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_156," line.long 0x354 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_157," line.long 0x358 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_158," line.long 0x35C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_159," line.long 0x360 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_160," line.long 0x364 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_161," line.long 0x368 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_162," line.long 0x36C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_163," line.long 0x370 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_164," line.long 0x374 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_165," line.long 0x378 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_166," line.long 0x37C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_167," line.long 0x380 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_168," line.long 0x384 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_169," line.long 0x388 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_170," line.long 0x38C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_171," line.long 0x390 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_172," line.long 0x394 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_173," line.long 0x398 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_174," line.long 0x39C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_175," line.long 0x3A0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_176," line.long 0x3A4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_177," line.long 0x3A8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_178," line.long 0x3AC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_179," line.long 0x3B0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_180," line.long 0x3B4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_181," line.long 0x3B8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_182," line.long 0x3BC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_183," line.long 0x3C0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_184," line.long 0x3C4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_185," line.long 0x3C8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_186," line.long 0x3CC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_187," line.long 0x3D0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_188," line.long 0x3D4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_189," line.long 0x3D8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_190," line.long 0x3DC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_191," line.long 0x3E0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_192," line.long 0x3E4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_193," line.long 0x3E8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_194," line.long 0x3EC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_195," line.long 0x3F0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_196," line.long 0x3F4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_197," line.long 0x3F8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_198," line.long 0x3FC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_199," tree.end tree "NOC_KITE2_IN_IA_KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506200 group.long 0x0++0x1FF line.long 0x0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x70 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x74 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x78 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x7C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x80 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x84 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0x88 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0x8C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0x90 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0x94 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0x98 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0x9C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xA0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xA4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xA8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xAC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xB0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xB4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xB8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xBC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xC0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xC4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xC8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xCC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xD0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xD4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xD8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xDC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xE0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xE4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0xE8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0xEC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0xF0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0xF4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0xF8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0xFC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x100 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x104 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x108 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x10C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x110 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x114 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x118 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x11C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x120 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x124 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x130 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x134 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x138 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x13C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x140 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x144 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x148 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x14C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x150 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x154 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x158 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x15C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x160 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x164 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x168 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x16C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x170 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x174 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x178 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x17C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x180 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x184 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x188 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x18C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x190 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x194 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x198 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x19C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1A0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1A4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1A8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1AC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1B0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1B4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1B8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1BC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1C0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1C4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1C8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1CC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1D0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1D4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1D8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1DC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1E0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1E4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," line.long 0x1E8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_107," line.long 0x1EC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_108," line.long 0x1F0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_109," line.long 0x1F4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_110," line.long 0x1F8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_111," line.long 0x1FC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_112," tree.end tree "NOC_KITE2_IN_IA_KITE1_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B502C00 group.long 0x0++0x3FF line.long 0x0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "NOC_KITE2_IN_IA_KITE2_PACKET_PROBE_MAIN_PROBE" base ad:0x7B503000 group.long 0x0++0x3FF line.long 0x0 "KITE2_PACKET_PROBE_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE2_PACKET_PROBE_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE2_PACKET_PROBE_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE2_PACKET_PROBE_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE2_PACKET_PROBE_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE2_PACKET_PROBE_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_211," tree.end tree "NOC_KITE2_IN_IA_KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506800 group.long 0x0++0x7F line.long 0x0 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x40 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x44 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x48 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x4C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x50 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x54 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x58 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x5C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x60 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x64 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x68 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x6C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x6C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x70 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x70 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x74 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x74 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x78 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x78 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x7C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," tree.end tree "NOC_KITE2_IN_IA_KITE2_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B503400 group.long 0x0++0x3FF line.long 0x0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "NOC_KITE2_IN_IA_NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000400 group.long 0x0++0x7F line.long 0x0 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE2_IN_IA_NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000D80 group.long 0x0++0x7F line.long 0x0 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE2_IN_IA_NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000480 group.long 0x0++0x7F line.long 0x0 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE2_IN_IA_NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000E00 group.long 0x0++0x7F line.long 0x0 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE2_IN_IA_NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000500 group.long 0x0++0x7F line.long 0x0 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE2_IN_IA_NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000E80 group.long 0x0++0x7F line.long 0x0 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE2_IN_IA_OBSERVER_HSM_MAIN_ERRORLOGGER_0" base ad:0x7B506A80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "NOC_KITE2_IN_IA_OBSERVER_KITE0_MAIN_ERRORLOGGER_0" base ad:0x7B506B00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "NOC_KITE2_IN_IA_OBSERVER_KITE1_MAIN_ERRORLOGGER_0" base ad:0x7B506B80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "NOC_KITE2_IN_IA_OBSERVER_KITE2_MAIN_ERRORLOGGER_0" base ad:0x7B506C00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "NOC_KITE2_IN_IA_OBSERVER_MAIN0_MAIN_ATBENDPOINT" base ad:0x7B506900 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ATBID," hexmask.long.byte 0x8 0.--6. 1. "ATBID,ATB AtId" line.long 0xC "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ATBEN," bitfld.long 0xC 0. "ATBEN,ATB Unit Enable" "0,1" line.long 0x10 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_SYNCPERIOD," hexmask.long.byte 0x10 0.--4. 1. "SYNCPERIOD,ATB Synchro Period" line.long 0x14 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_00," line.long 0x18 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_01," line.long 0x1C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_02," line.long 0x20 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_03," line.long 0x24 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_04," line.long 0x28 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_05," line.long 0x2C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_06," line.long 0x30 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_07," line.long 0x34 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_08," line.long 0x38 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_09," line.long 0x3C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_10," line.long 0x40 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_11," line.long 0x44 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_12," line.long 0x48 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_13," line.long 0x4C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_14," line.long 0x50 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_15," line.long 0x54 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_16," line.long 0x58 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_17," line.long 0x5C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_18," line.long 0x60 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_19," line.long 0x64 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_20," line.long 0x68 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_21," line.long 0x6C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_22," line.long 0x70 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_23," line.long 0x74 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_24," line.long 0x78 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_25," line.long 0x7C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_26," tree.end tree "NOC_KITE2_IN_IA_OBSERVER_MAIN0_MAIN_ERRORLOGGER_0" base ad:0x7B506C80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "NOC_KITE2_IN_IA_OBSERVER_MAIN1_MAIN_ATBENDPOINT" base ad:0x7B506980 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ATBID," hexmask.long.byte 0x8 0.--6. 1. "ATBID,ATB AtId" line.long 0xC "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ATBEN," bitfld.long 0xC 0. "ATBEN,ATB Unit Enable" "0,1" line.long 0x10 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_SYNCPERIOD," hexmask.long.byte 0x10 0.--4. 1. "SYNCPERIOD,ATB Synchro Period" line.long 0x14 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_00," line.long 0x18 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_01," line.long 0x1C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_02," line.long 0x20 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_03," line.long 0x24 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_04," line.long 0x28 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_05," line.long 0x2C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_06," line.long 0x30 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_07," line.long 0x34 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_08," line.long 0x38 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_09," line.long 0x3C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_10," line.long 0x40 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_11," line.long 0x44 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_12," line.long 0x48 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_13," line.long 0x4C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_14," line.long 0x50 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_15," line.long 0x54 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_16," line.long 0x58 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_17," line.long 0x5C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_18," line.long 0x60 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_19," line.long 0x64 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_20," line.long 0x68 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_21," line.long 0x6C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_22," line.long 0x70 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_23," line.long 0x74 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_24," line.long 0x78 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_25," line.long 0x7C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_26," tree.end tree "NOC_KITE2_IN_IA_OBSERVER_MAIN1_MAIN_ERRORLOGGER_0" base ad:0x7B506D00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "NOC_KITE2_IN_IA_OBSERVER_PCIE_MAIN_ATBENDPOINT" base ad:0x7B506A00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_PCIE_MAIN_ATBENDPOINT_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_PCIE_MAIN_ATBENDPOINT_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_PCIE_MAIN_ATBENDPOINT_ATBID," hexmask.long.byte 0x8 0.--6. 1. "ATBID,ATB AtId" line.long 0xC "OBSERVER_PCIE_MAIN_ATBENDPOINT_ATBEN," bitfld.long 0xC 0. "ATBEN,ATB Unit Enable" "0,1" line.long 0x10 "OBSERVER_PCIE_MAIN_ATBENDPOINT_SYNCPERIOD," hexmask.long.byte 0x10 0.--4. 1. "SYNCPERIOD,ATB Synchro Period" line.long 0x14 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_00," line.long 0x18 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_01," line.long 0x1C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_02," line.long 0x20 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_03," line.long 0x24 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_04," line.long 0x28 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_05," line.long 0x2C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_06," line.long 0x30 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_07," line.long 0x34 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_08," line.long 0x38 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_09," line.long 0x3C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_10," line.long 0x40 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_11," line.long 0x44 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_12," line.long 0x48 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_13," line.long 0x4C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_14," line.long 0x50 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_15," line.long 0x54 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_16," line.long 0x58 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_17," line.long 0x5C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_18," line.long 0x60 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_19," line.long 0x64 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_20," line.long 0x68 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_21," line.long 0x6C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_22," line.long 0x70 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_23," line.long 0x74 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_24," line.long 0x78 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_25," line.long 0x7C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_26," tree.end tree "NOC_KITE2_IN_IA_OBSERVER_PCIE_MAIN_ERRORLOGGER_0" base ad:0x7B506D80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "NOC_KITE2_IN_IA_PCIE_0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000580 group.long 0x0++0x7F line.long 0x0 "PCIE_0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "PCIE_0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "PCIE_0_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "PCIE_0_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "PCIE_0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE2_IN_IA_PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000F00 group.long 0x0++0x7F line.long 0x0 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE2_IN_IA_PCIE_1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000600 group.long 0x0++0x7F line.long 0x0 "PCIE_1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "PCIE_1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "PCIE_1_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "PCIE_1_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "PCIE_1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE2_IN_IA_PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000F80 group.long 0x0++0x7F line.long 0x0 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE2_IN_IA_PCIE_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B503800 group.long 0x0++0x3FF line.long 0x0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x234 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x238 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x23C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x240 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x244 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x248 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x24C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x250 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x254 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x258 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x25C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x260 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x264 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x268 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x26C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x270 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x274 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x278 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x27C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x280 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x284 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x288 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x28C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x290 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x294 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x298 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x29C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2A0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2A4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2A8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2AC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2B0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2B4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2B8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2BC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2C0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2C4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2C8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2CC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x2D0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x2D4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x2D8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x2DC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x2E0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x2E4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x2E8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x2EC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x2F0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x2F4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x2F8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x2FC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x300 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x304 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x308 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x30C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x310 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x314 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x318 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x31C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x320 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x324 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x328 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x32C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x330 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x334 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x338 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x33C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x340 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x344 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x348 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x34C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x350 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x354 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x358 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x35C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x360 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x364 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x368 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x36C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x370 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x374 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x378 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x37C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x380 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x384 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x388 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x38C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x390 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x394 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x398 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x39C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3A0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3A4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3A8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3AC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3B0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3B4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3B8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3BC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3C0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3C4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3C8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3CC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," line.long 0x3D0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_208," line.long 0x3D4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_209," line.long 0x3D8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_210," line.long 0x3DC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_211," line.long 0x3E0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_212," line.long 0x3E4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_213," line.long 0x3E8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_214," line.long 0x3EC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_215," line.long 0x3F0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_216," line.long 0x3F4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_217," line.long 0x3F8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_218," line.long 0x3FC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_219," tree.end tree "NOC_KITE2_IN_IA_PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506880 group.long 0x0++0x7F line.long 0x0 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x38 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x3C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x40 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x44 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x48 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x6C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x70 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x70 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x74 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x74 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x78 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x78 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x7C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," tree.end tree "NOC_KITE2_IN_IA_PCIE_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B503C00 group.long 0x0++0x3FF line.long 0x0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "NOC_KITE2_IN_IA_POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER" base ad:0x7B506E00 group.long 0x0++0x7F line.long 0x0 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT0," hexmask.long 0x8 0.--31. 1. "MISSIONFAULT0,MissionFault0 register" line.long 0xC "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT1," hexmask.long 0xC 0.--31. 1. "MISSIONFAULT1,MissionFault1 register" line.long 0x10 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT2," hexmask.long 0x10 0.--31. 1. "MISSIONFAULT2,MissionFault2 register" line.long 0x14 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT3," hexmask.long 0x14 0.--31. 1. "MISSIONFAULT3,MissionFault3 register" line.long 0x18 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT0," hexmask.long 0x18 0.--31. 1. "LATENTFAULT0,LatentFault0 register" line.long 0x1C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT1," hexmask.long 0x1C 0.--31. 1. "LATENTFAULT1,LatentFault1 register" line.long 0x20 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT2," hexmask.long 0x20 0.--31. 1. "LATENTFAULT2,LatentFault2 register" line.long 0x24 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT3," hexmask.long 0x24 0.--31. 1. "LATENTFAULT3,LatentFault3 register" line.long 0x28 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_FAULTS," bitfld.long 0x28 1. "MISSIONFAULT,Mission Fault" "0,1" bitfld.long 0x28 0. "LATENTFAULT,Latent Fault" "0,1" line.long 0x2C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_INTEN," bitfld.long 0x2C 1. "MISSIONFAULTEN,MissionFault Interrupt enable" "0,1" bitfld.long 0x2C 0. "BISTDONEEN,BistDone Interrupt enable" "0,1" line.long 0x30 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_INTCLR," bitfld.long 0x30 1. "MISSIONFAULTCLR,Clear Mission Fault" "0,1" bitfld.long 0x30 0. "LATENTFAULTCLR,Clear Latent Fault" "0,1" line.long 0x34 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTCTL," bitfld.long 0x34 1. "BISTDONECLR,Clear BistDone" "0,1" bitfld.long 0x34 0. "BISTSTART,Start Bist sequence" "0,1" line.long 0x38 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTDONE," bitfld.long 0x38 1. "MISSIONMODE,Mission Mode Status" "0,1" bitfld.long 0x38 0. "BISTDONE,BistDone Status" "0,1" line.long 0x3C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO1," hexmask.long.word 0x3C 0.--15. 1. "BISTTO1,BistTimeOut register" line.long 0x40 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO2," hexmask.long.byte 0x40 0.--7. 1. "BISTTO2,BistTimeOut register" line.long 0x44 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_00," line.long 0x48 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_01," line.long 0x4C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_02," line.long 0x50 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_03," line.long 0x54 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_04," line.long 0x58 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_05," line.long 0x5C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_06," line.long 0x60 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_07," line.long 0x64 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_08," line.long 0x68 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_09," line.long 0x6C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_10," line.long 0x70 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_11," line.long 0x74 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_12," line.long 0x78 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_13," line.long 0x7C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_14," tree.end tree "NOC_KITE2_IN_IA_POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER" base ad:0x7B506E80 group.long 0x0++0x7F line.long 0x0 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT0," hexmask.long 0x8 0.--31. 1. "MISSIONFAULT0,MissionFault0 register" line.long 0xC "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT1," hexmask.long 0xC 0.--31. 1. "MISSIONFAULT1,MissionFault1 register" line.long 0x10 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT2," hexmask.long 0x10 0.--31. 1. "MISSIONFAULT2,MissionFault2 register" line.long 0x14 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT3," hexmask.long 0x14 0.--31. 1. "MISSIONFAULT3,MissionFault3 register" line.long 0x18 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT0," hexmask.long 0x18 0.--31. 1. "LATENTFAULT0,LatentFault0 register" line.long 0x1C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT1," hexmask.long 0x1C 0.--31. 1. "LATENTFAULT1,LatentFault1 register" line.long 0x20 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT2," hexmask.long 0x20 0.--31. 1. "LATENTFAULT2,LatentFault2 register" line.long 0x24 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT3," hexmask.long 0x24 0.--31. 1. "LATENTFAULT3,LatentFault3 register" line.long 0x28 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_FAULTS," bitfld.long 0x28 1. "MISSIONFAULT,Mission Fault" "0,1" bitfld.long 0x28 0. "LATENTFAULT,Latent Fault" "0,1" line.long 0x2C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_INTEN," bitfld.long 0x2C 1. "MISSIONFAULTEN,MissionFault Interrupt enable" "0,1" bitfld.long 0x2C 0. "BISTDONEEN,BistDone Interrupt enable" "0,1" line.long 0x30 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_INTCLR," bitfld.long 0x30 1. "MISSIONFAULTCLR,Clear Mission Fault" "0,1" bitfld.long 0x30 0. "LATENTFAULTCLR,Clear Latent Fault" "0,1" line.long 0x34 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTCTL," bitfld.long 0x34 1. "BISTDONECLR,Clear BistDone" "0,1" bitfld.long 0x34 0. "BISTSTART,Start Bist sequence" "0,1" line.long 0x38 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTDONE," bitfld.long 0x38 1. "MISSIONMODE,Mission Mode Status" "0,1" bitfld.long 0x38 0. "BISTDONE,BistDone Status" "0,1" line.long 0x3C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO1," hexmask.long.word 0x3C 0.--15. 1. "BISTTO1,BistTimeOut register" line.long 0x40 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO2," hexmask.long.byte 0x40 0.--7. 1. "BISTTO2,BistTimeOut register" line.long 0x44 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_00," line.long 0x48 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_01," line.long 0x4C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_02," line.long 0x50 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_03," line.long 0x54 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_04," line.long 0x58 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_05," line.long 0x5C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_06," line.long 0x60 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_07," line.long 0x64 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_08," line.long 0x68 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_09," line.long 0x6C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_10," line.long 0x70 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_11," line.long 0x74 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_12," line.long 0x78 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_13," line.long 0x7C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_14," tree.end tree "NOC_KITE2_IN_IA_SDMMC_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000680 group.long 0x0++0x7F line.long 0x0 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE2_IN_IA_SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001000 group.long 0x0++0x7F line.long 0x0 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE2_IN_IA_SDMMC_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B504000 group.long 0x0++0x3FF line.long 0x0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x14 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x34 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x3C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x4C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x50 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x54 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x58 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x5C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x60 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x64 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x68 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x6C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x70 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x74 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x78 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x7C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x80 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x90 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x98 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0x9C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xB8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xBC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xC8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xCC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xD8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xDC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xE8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xEC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xF8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0xFC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x100 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x104 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x108 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x10C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x110 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x114 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x118 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x11C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x120 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x124 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x128 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x12C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x130 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x134 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x138 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x13C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x140 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x144 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x148 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x14C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x150 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x154 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x158 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x15C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x160 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x164 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x168 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x16C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x170 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x174 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x178 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x17C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x180 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x184 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x188 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x18C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x190 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x194 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x198 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x19C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1A8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1AC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1B8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1BC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1C8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1CC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1D8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1DC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1E8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1EC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1F8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x1FC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x200 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x204 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x214 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x224 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x234 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x244 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x254 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x264 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x274 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x284 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x288 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x28C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x290 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x294 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x298 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x29C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2A8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2AC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2B8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2BC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2C8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2CC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2D8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2DC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2E8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2EC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2F8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x2FC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x300 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x304 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x308 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x30C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x310 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x314 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x318 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x31C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x320 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x324 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x328 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x32C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x330 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x334 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x338 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x33C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x340 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x344 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x348 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x34C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x350 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x354 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x358 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x35C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x360 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x364 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x368 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x36C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x370 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x374 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x378 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x37C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x380 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x384 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x388 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x38C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x390 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x394 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x398 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x39C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3A8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3AC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3B8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3BC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3C8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3CC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3D8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3DC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3E8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3EC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3F8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," line.long 0x3FC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_208," tree.end tree "NOC_KITE2_IN_IA_SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506400 group.long 0x0++0x1FF line.long 0x0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x70 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x74 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x78 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x7C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x80 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x84 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0x88 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0x8C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0x90 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0x94 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0x98 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0x9C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xA0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xA4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xA8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xAC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xB0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xB4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xB8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xBC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xC0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xC4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xC8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xCC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xD0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xD4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xD8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xDC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xE0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xE4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0xE8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0xEC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0xF0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0xF4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0xF8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0xFC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x100 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x104 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x108 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x10C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x110 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x114 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x118 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x11C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x120 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x124 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x130 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x134 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x138 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x13C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x140 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x144 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x148 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x14C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x150 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x154 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x158 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x15C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x160 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x164 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x168 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x16C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x170 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x174 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x178 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x17C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x180 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x184 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x188 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x18C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x190 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x194 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x198 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x19C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1A0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1A4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1A8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1AC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1B0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1B4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1B8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1BC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1C0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1C4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1C8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1CC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1D0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1D4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1D8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1DC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1E0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1E4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," line.long 0x1E8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_107," line.long 0x1EC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_108," line.long 0x1F0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_109," line.long 0x1F4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_110," line.long 0x1F8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_111," line.long 0x1FC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_112," tree.end tree "NOC_KITE2_IN_IA_SDMMC_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B504400 group.long 0x0++0x3FF line.long 0x0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x14 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x34 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x3C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x4C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x50 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x54 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x58 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x5C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x60 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x64 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x68 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x6C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x70 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x74 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x78 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x7C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x80 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x90 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x98 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0x9C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xB8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xBC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xC8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xCC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xD8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xDC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xE8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xEC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xF8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0xFC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x100 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x104 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x108 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x10C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x110 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x114 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x118 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x11C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x120 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x124 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x128 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x12C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x130 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x134 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x138 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x13C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x140 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x144 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x148 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x14C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x150 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x154 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x158 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x15C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x160 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x164 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x168 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x16C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x170 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x174 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x178 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x17C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x180 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x184 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x188 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x18C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x190 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x194 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x198 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x19C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1A8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1AC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1B8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1BC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1C8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1CC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1D8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1DC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1E8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1EC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1F8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x1FC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x200 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x204 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x214 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x218 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x21C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x220 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x224 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x228 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x22C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x230 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x234 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x238 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x23C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x240 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x244 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x248 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x24C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x250 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x254 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x258 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x25C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x260 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x264 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x268 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x26C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x270 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x274 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x278 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x27C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x280 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x284 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x288 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x28C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x290 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x294 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x298 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x29C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2A4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2A8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2AC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2B4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2B8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2BC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2C4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2C8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2CC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2D4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2D8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2DC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2E4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2E8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2EC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2F4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x2F8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x2FC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x300 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x304 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x308 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x30C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x310 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x314 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x318 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x31C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x320 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x324 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x328 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x32C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x330 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x334 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x338 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x33C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x340 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x344 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x348 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x34C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x350 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x354 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x358 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x35C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x360 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x364 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x368 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x36C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x370 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x374 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x378 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x37C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x380 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x384 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x388 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x38C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x390 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x394 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x398 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x39C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3A4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3A8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3AC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3B4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3B8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3BC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3C4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3C8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3CC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3D4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3D8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3DC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3E4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3E8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3EC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3F4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," line.long 0x3F8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_228," line.long 0x3FC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_229," tree.end tree "NOC_KITE2_IN_IA_SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000700 group.long 0x0++0x7F line.long 0x0 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE2_IN_IA_SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000780 group.long 0x0++0x7F line.long 0x0 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE2_IN_IA_SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000800 group.long 0x0++0x7F line.long 0x0 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "NOC_KITE2_IN_IA_SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B504800 group.long 0x0++0x3FF line.long 0x0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "NOC_KITE2_IN_IA_SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B504C00 group.long 0x0++0x3FF line.long 0x0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "NOC_KITE2_IN_IA_ZIPW0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000880 group.long 0x0++0x7F line.long 0x0 "ZIPW0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ZIPW0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ZIPW0_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ZIPW0_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ZIPW0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE2_IN_IA_ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001080 group.long 0x0++0x7F line.long 0x0 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE2_IN_IA_ZIPW1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000900 group.long 0x0++0x7F line.long 0x0 "ZIPW1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ZIPW1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ZIPW1_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ZIPW1_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ZIPW1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "NOC_KITE2_IN_IA_ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001100 group.long 0x0++0x7F line.long 0x0 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "NOC_KITE2_IN_IA_ZIPW_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B505000 group.long 0x0++0x3FF line.long 0x0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x264 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x268 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x26C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x270 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x274 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x278 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x27C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x280 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x284 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x288 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x28C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x290 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x294 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x298 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x29C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2A0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2AC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2B0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2BC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2C0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2CC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2D0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2DC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2E0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2EC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2F0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2FC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x300 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x304 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x308 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x30C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x310 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x314 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x318 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x31C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x320 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x324 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x328 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x32C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x330 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x334 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x338 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x33C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x340 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x344 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x348 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x34C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x350 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x354 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x358 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x35C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x360 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x364 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x368 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x36C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x370 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x374 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x378 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x37C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x380 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x384 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x388 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x38C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x390 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x394 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x398 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x39C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3A0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3AC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3B0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3BC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3C0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3CC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3D0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3DC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3E0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3EC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3F0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3FC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," tree.end tree "NOC_KITE2_IN_IA_ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506600 group.long 0x0++0x1FF line.long 0x0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x44 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x48 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x4C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x50 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x54 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x58 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x5C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x60 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x64 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x68 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x80 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x84 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x88 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x8C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x90 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x94 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x98 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x9C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xA4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xA8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xAC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xB4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xB8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xBC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xC4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xC8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xCC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xD4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xD8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xDC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xE4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xE8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xEC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xF4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xF8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xFC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x100 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x104 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x108 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x10C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x110 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x114 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x118 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x11C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x130 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x134 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x138 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x13C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x140 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x144 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x148 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x14C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x150 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x154 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x158 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x15C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x160 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x164 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x168 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x16C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x170 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x174 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x178 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x17C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x180 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x184 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x188 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x18C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x190 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x194 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x198 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x19C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1A4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1A8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1AC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1B4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1B8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1BC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1C4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1C8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1CC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1D4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1D8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1DC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1E4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1E8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1EC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1F4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1F8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1FC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," tree.end tree "NOC_KITE2_IN_IA_ZIPW_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B505400 group.long 0x0++0x3FF line.long 0x0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree.end tree "SUBNOC_DME" tree "SUBNOC_DME_IN_IA_DAP0_AXI_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000000 group.long 0x0++0x7F line.long 0x0 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_DME_IN_IA_DAP1_AXI_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000080 group.long 0x0++0x7F line.long 0x0 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_DME_IN_IA_DFA_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000100 group.long 0x0++0x7F line.long 0x0 "DFA_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DFA_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DFA_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "DFA_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "DFA_IN_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--12. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "DFA_IN_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "DFA_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_DME_IN_IA_DMA0_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B500000 group.long 0x0++0x3FF line.long 0x0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_PORTSEL," bitfld.long 0x270 0. "COUNTERS_7_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x274 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x284 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x288 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x28C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x290 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x294 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x298 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x29C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x2A0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x2A4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x2A8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x2AC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x2B0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x2B4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x2B8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x2BC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2C0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2C4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2C8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2CC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2D0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2D4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2D8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2DC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2E0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2E4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2E8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2EC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2F0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2F4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2F8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2FC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x300 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x304 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x308 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x30C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x310 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x314 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x318 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x31C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x320 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x324 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x328 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x32C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x330 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x334 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x338 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x33C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x340 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x344 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x348 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x34C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x350 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x354 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x358 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x35C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x360 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x364 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x368 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x36C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x370 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x374 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x378 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x37C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x380 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x384 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x388 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x38C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x390 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x394 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x398 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x39C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x3A0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x3A4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x3A8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x3AC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x3B0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x3B4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x3B8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x3BC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3C0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3C4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3C8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3CC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3D0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3D4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3D8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3DC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3E0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3E4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3E8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3EC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3F0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3F4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3F8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3FC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," tree.end tree "SUBNOC_DME_IN_IA_DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505800 group.long 0x0++0x1FF line.long 0x0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x4C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x50 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x54 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x58 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x5C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x60 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x64 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x68 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_5," hexmask.long.byte 0x7C 0.--3. 1. "THRESHOLDS_1_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x80 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_6," hexmask.long.byte 0x80 0.--3. 1. "THRESHOLDS_1_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x84 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x88 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x8C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x90 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x94 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x98 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x9C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0xA0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0xA4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0xA8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0xAC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xB0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xB4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xB8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xBC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xC0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xC4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xC8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xCC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xD0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xD4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xD8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xDC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xE0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xE4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xE8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xEC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xF0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xF4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xF8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xFC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0x100 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0x104 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0x108 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0x10C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x110 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x114 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x118 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x11C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x130 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x134 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x138 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x13C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x140 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x144 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x148 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x14C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x150 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x154 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x158 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x15C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x160 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x164 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x168 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x16C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x170 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x174 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x178 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x17C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x180 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x184 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x188 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x18C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x190 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x194 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x198 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x19C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x1A0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x1A4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x1A8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x1AC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1B0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1B4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1B8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1BC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1C0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1C4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1C8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1CC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1D0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1D4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1D8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1DC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1E0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1E4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1E8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1EC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1F0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1F4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1F8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1FC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," tree.end tree "SUBNOC_DME_IN_IA_DMA0_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B500400 group.long 0x0++0x3FF line.long 0x0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "SUBNOC_DME_IN_IA_DMA1_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B500800 group.long 0x0++0x3FF line.long 0x0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x274 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x278 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x27C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x280 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x284 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x288 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x28C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x290 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x294 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x298 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x29C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x2A0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x2A4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x2A8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x2AC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2B0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2B4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2B8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2BC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2C0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2C4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2C8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2CC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2D0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2D4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2D8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2DC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2E0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2E4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2E8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2EC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2F0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2F4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2F8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2FC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x300 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x304 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x308 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x30C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x310 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x314 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x318 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x31C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x320 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x324 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x328 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x32C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x330 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x334 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x338 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x33C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x340 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x344 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x348 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x34C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x350 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x354 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x358 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x35C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x360 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x364 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x368 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x36C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x370 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x374 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x378 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x37C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x380 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x384 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x388 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x38C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x390 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x394 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x398 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x39C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x3A0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x3A4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x3A8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x3AC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3B0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3B4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3B8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3BC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3C0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3C4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3C8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3CC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3D0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3D4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3D8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3DC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3E0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3E4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3E8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3EC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3F0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3F4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3F8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3FC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," tree.end tree "SUBNOC_DME_IN_IA_DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505A00 group.long 0x0++0x1FF line.long 0x0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x48 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x4C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x50 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x54 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x58 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x5C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x60 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x64 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x68 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_5," hexmask.long.byte 0x7C 0.--3. 1. "THRESHOLDS_1_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x80 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x84 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x88 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x8C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x90 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x94 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x98 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x9C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0xA0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0xA4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xAC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xB0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xB4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xBC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xC0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xC4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xCC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xD0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xD4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xDC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xE0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xE4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xEC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xF0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xF4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xFC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0x100 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0x104 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x108 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x10C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x110 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x114 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x118 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x11C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x130 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x134 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x138 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x13C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x140 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x144 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x148 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x14C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x150 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x154 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x158 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x15C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x160 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x164 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x168 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x16C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x170 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x174 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x178 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x17C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x180 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x184 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x188 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x18C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x190 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x194 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x198 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x19C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x1A0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x1A4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1AC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1B0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1B4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1BC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1C0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1C4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1CC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1D0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1D4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1DC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1E0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1E4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1EC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1F0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1F4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1FC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," tree.end tree "SUBNOC_DME_IN_IA_DMA1_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B500C00 group.long 0x0++0x3FF line.long 0x0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "SUBNOC_DME_IN_IA_EDMA_0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000980 group.long 0x0++0x7F line.long 0x0 "EDMA_0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_DME_IN_IA_EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001180 group.long 0x0++0x7F line.long 0x0 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_DME_IN_IA_EDMA_1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000A00 group.long 0x0++0x7F line.long 0x0 "EDMA_1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_DME_IN_IA_EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001200 group.long 0x0++0x7F line.long 0x0 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_DME_IN_IA_EDMA_2_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000A80 group.long 0x0++0x7F line.long 0x0 "EDMA_2_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_2_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_2_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_2_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_2_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_DME_IN_IA_EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001280 group.long 0x0++0x7F line.long 0x0 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_DME_IN_IA_EDMA_3_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000B00 group.long 0x0++0x7F line.long 0x0 "EDMA_3_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_3_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_3_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_3_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_3_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_DME_IN_IA_EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001300 group.long 0x0++0x7F line.long 0x0 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_DME_IN_IA_ETHER0_I_MAIN_QOSGENERATOR" base ad:0x7B000180 group.long 0x0++0x7F line.long 0x0 "ETHER0_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER0_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER0_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ETHER0_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ETHER0_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ETHER0_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ETHER0_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_DME_IN_IA_ETHER0_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000B80 group.long 0x0++0x7F line.long 0x0 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_DME_IN_IA_ETHER1_I_MAIN_QOSGENERATOR" base ad:0x7B000200 group.long 0x0++0x7F line.long 0x0 "ETHER1_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER1_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER1_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ETHER1_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ETHER1_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ETHER1_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ETHER1_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_DME_IN_IA_ETHER1_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000C00 group.long 0x0++0x7F line.long 0x0 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_DME_IN_IA_ETHR_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B501000 group.long 0x0++0x3FF line.long 0x0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x264 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x268 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x26C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x270 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x274 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x278 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x27C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x280 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x284 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x288 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x28C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x290 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x294 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x298 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x29C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2A0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2AC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2B0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2BC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2C0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2CC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2D0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2DC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2E0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2EC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2F0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2FC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x300 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x304 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x308 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x30C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x310 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x314 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x318 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x31C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x320 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x324 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x328 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x32C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x330 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x334 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x338 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x33C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x340 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x344 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x348 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x34C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x350 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x354 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x358 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x35C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x360 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x364 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x368 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x36C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x370 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x374 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x378 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x37C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x380 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x384 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x388 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x38C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x390 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x394 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x398 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x39C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3A0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3AC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3B0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3BC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3C0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3CC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3D0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3DC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3E0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3EC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3F0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3FC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," tree.end tree "SUBNOC_DME_IN_IA_ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505C00 group.long 0x0++0x1FF line.long 0x0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x44 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x48 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x4C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x50 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x54 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x58 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x5C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x60 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x64 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x68 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x80 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x84 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x88 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x8C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x90 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x94 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x98 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x9C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xA4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xA8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xAC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xB4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xB8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xBC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xC4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xC8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xCC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xD4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xD8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xDC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xE4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xE8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xEC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xF4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xF8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xFC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x100 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x104 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x108 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x10C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x110 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x114 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x118 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x11C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x130 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x134 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x138 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x13C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x140 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x144 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x148 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x14C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x150 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x154 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x158 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x15C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x160 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x164 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x168 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x16C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x170 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x174 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x178 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x17C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x180 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x184 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x188 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x18C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x190 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x194 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x198 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x19C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1A4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1A8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1AC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1B4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1B8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1BC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1C4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1C8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1CC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1D4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1D8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1DC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1E4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1E8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1EC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1F4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1F8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1FC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," tree.end tree "SUBNOC_DME_IN_IA_ETHR_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B501400 group.long 0x0++0x3FF line.long 0x0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "SUBNOC_DME_IN_IA_FLEX0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000280 group.long 0x0++0x7F line.long 0x0 "FLEX0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "FLEX0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "FLEX0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_DME_IN_IA_FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000C80 group.long 0x0++0x7F line.long 0x0 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_DME_IN_IA_FLEX1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000300 group.long 0x0++0x7F line.long 0x0 "FLEX1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "FLEX1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "FLEX1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_DME_IN_IA_FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000D00 group.long 0x0++0x7F line.long 0x0 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_DME_IN_IA_FR_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B501800 group.long 0x0++0x3FF line.long 0x0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "FR_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x264 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x268 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x26C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x270 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x274 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x278 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x27C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x280 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x284 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x288 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x28C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x290 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x294 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x298 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x29C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2A0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2AC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2B0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2BC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2C0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2CC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2D0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2DC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2E0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2EC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2F0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2FC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x300 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x304 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x308 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x30C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x310 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x314 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x318 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x31C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x320 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x324 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x328 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x32C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x330 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x334 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x338 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x33C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x340 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x344 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x348 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x34C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x350 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x354 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x358 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x35C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x360 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x364 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x368 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x36C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x370 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x374 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x378 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x37C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x380 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x384 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x388 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x38C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x390 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x394 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x398 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x39C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3A0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3AC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3B0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3BC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3C0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3CC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3D0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3DC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3E0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3EC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3F0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3FC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," tree.end tree "SUBNOC_DME_IN_IA_FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505E00 group.long 0x0++0x1FF line.long 0x0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x44 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x48 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x4C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x50 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x54 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x58 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x5C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x60 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x64 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x68 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x80 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x84 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x88 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x8C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x90 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x94 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x98 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x9C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xA4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xA8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xAC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xB4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xB8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xBC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xC4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xC8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xCC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xD4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xD8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xDC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xE4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xE8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xEC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xF4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xF8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xFC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x100 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x104 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x108 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x10C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x110 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x114 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x118 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x11C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x130 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x134 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x138 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x13C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x140 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x144 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x148 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x14C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x150 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x154 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x158 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x15C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x160 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x164 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x168 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x16C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x170 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x174 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x178 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x17C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x180 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x184 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x188 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x18C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x190 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x194 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x198 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x19C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1A4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1A8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1AC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1B4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1B8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1BC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1C4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1C8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1CC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1D4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1D8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1DC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1E4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1E8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1EC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1F4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1F8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1FC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," tree.end tree "SUBNOC_DME_IN_IA_FR_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B501C00 group.long 0x0++0x3FF line.long 0x0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "FR_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "SUBNOC_DME_IN_IA_GTM_M_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000380 group.long 0x0++0x7F line.long 0x0 "GTM_M_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "GTM_M_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "GTM_M_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "GTM_M_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "GTM_M_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "GTM_M_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "GTM_M_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_DME_IN_IA_KITE0_PACKET_PROBE_MAIN_PROBE" base ad:0x7B502000 group.long 0x0++0x3FF line.long 0x0 "KITE0_PACKET_PROBE_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE0_PACKET_PROBE_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE0_PACKET_PROBE_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE0_PACKET_PROBE_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE0_PACKET_PROBE_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE0_PACKET_PROBE_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_PORTSEL," bitfld.long 0x270 0. "COUNTERS_7_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x274 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_104," line.long 0x284 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_105," line.long 0x288 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_106," line.long 0x28C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_107," line.long 0x290 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_108," line.long 0x294 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_109," line.long 0x298 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_110," line.long 0x29C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_111," line.long 0x2A0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_112," line.long 0x2A4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_113," line.long 0x2A8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_114," line.long 0x2AC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_115," line.long 0x2B0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_116," line.long 0x2B4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_117," line.long 0x2B8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_118," line.long 0x2BC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_119," line.long 0x2C0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_120," line.long 0x2C4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_121," line.long 0x2C8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_122," line.long 0x2CC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_123," line.long 0x2D0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_124," line.long 0x2D4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_125," line.long 0x2D8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_126," line.long 0x2DC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_127," line.long 0x2E0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_128," line.long 0x2E4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_129," line.long 0x2E8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_130," line.long 0x2EC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_131," line.long 0x2F0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_132," line.long 0x2F4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_133," line.long 0x2F8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_134," line.long 0x2FC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_135," line.long 0x300 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_136," line.long 0x304 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_137," line.long 0x308 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_138," line.long 0x30C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_139," line.long 0x310 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_140," line.long 0x314 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_141," line.long 0x318 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_142," line.long 0x31C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_143," line.long 0x320 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_144," line.long 0x324 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_145," line.long 0x328 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_146," line.long 0x32C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_147," line.long 0x330 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_148," line.long 0x334 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_149," line.long 0x338 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_150," line.long 0x33C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_151," line.long 0x340 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_152," line.long 0x344 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_153," line.long 0x348 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_154," line.long 0x34C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_155," line.long 0x350 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_156," line.long 0x354 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_157," line.long 0x358 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_158," line.long 0x35C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_159," line.long 0x360 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_160," line.long 0x364 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_161," line.long 0x368 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_162," line.long 0x36C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_163," line.long 0x370 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_164," line.long 0x374 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_165," line.long 0x378 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_166," line.long 0x37C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_167," line.long 0x380 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_168," line.long 0x384 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_169," line.long 0x388 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_170," line.long 0x38C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_171," line.long 0x390 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_172," line.long 0x394 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_173," line.long 0x398 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_174," line.long 0x39C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_175," line.long 0x3A0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_176," line.long 0x3A4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_177," line.long 0x3A8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_178," line.long 0x3AC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_179," line.long 0x3B0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_180," line.long 0x3B4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_181," line.long 0x3B8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_182," line.long 0x3BC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_183," line.long 0x3C0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_184," line.long 0x3C4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_185," line.long 0x3C8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_186," line.long 0x3CC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_187," line.long 0x3D0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_188," line.long 0x3D4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_189," line.long 0x3D8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_190," line.long 0x3DC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_191," line.long 0x3E0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_192," line.long 0x3E4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_193," line.long 0x3E8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_194," line.long 0x3EC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_195," line.long 0x3F0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_196," line.long 0x3F4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_197," line.long 0x3F8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_198," line.long 0x3FC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_199," tree.end tree "SUBNOC_DME_IN_IA_KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506000 group.long 0x0++0x1FF line.long 0x0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x70 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x74 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x78 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x7C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x80 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x84 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0x88 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0x8C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0x90 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0x94 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0x98 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0x9C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xA0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xA4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xA8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xAC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xB0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xB4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xB8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xBC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xC0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xC4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xC8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xCC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xD0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xD4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xD8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xDC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xE0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xE4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0xE8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0xEC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0xF0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0xF4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0xF8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0xFC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x100 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x104 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x108 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x10C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x110 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x114 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x118 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x11C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x120 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x124 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x130 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x134 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x138 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x13C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x140 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x144 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x148 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x14C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x150 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x154 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x158 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x15C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x160 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x164 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x168 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x16C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x170 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x174 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x178 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x17C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x180 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x184 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x188 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x18C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x190 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x194 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x198 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x19C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1A0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1A4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1A8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1AC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1B0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1B4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1B8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1BC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1C0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1C4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1C8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1CC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1D0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1D4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1D8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1DC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1E0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1E4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," line.long 0x1E8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_107," line.long 0x1EC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_108," line.long 0x1F0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_109," line.long 0x1F4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_110," line.long 0x1F8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_111," line.long 0x1FC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_112," tree.end tree "SUBNOC_DME_IN_IA_KITE0_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B502400 group.long 0x0++0x3FF line.long 0x0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "SUBNOC_DME_IN_IA_KITE1_PACKET_PROBE_MAIN_PROBE" base ad:0x7B502800 group.long 0x0++0x3FF line.long 0x0 "KITE1_PACKET_PROBE_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE1_PACKET_PROBE_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE1_PACKET_PROBE_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE1_PACKET_PROBE_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE1_PACKET_PROBE_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE1_PACKET_PROBE_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_PORTSEL," bitfld.long 0x270 0. "COUNTERS_7_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x274 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_104," line.long 0x284 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_105," line.long 0x288 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_106," line.long 0x28C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_107," line.long 0x290 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_108," line.long 0x294 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_109," line.long 0x298 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_110," line.long 0x29C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_111," line.long 0x2A0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_112," line.long 0x2A4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_113," line.long 0x2A8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_114," line.long 0x2AC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_115," line.long 0x2B0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_116," line.long 0x2B4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_117," line.long 0x2B8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_118," line.long 0x2BC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_119," line.long 0x2C0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_120," line.long 0x2C4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_121," line.long 0x2C8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_122," line.long 0x2CC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_123," line.long 0x2D0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_124," line.long 0x2D4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_125," line.long 0x2D8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_126," line.long 0x2DC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_127," line.long 0x2E0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_128," line.long 0x2E4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_129," line.long 0x2E8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_130," line.long 0x2EC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_131," line.long 0x2F0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_132," line.long 0x2F4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_133," line.long 0x2F8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_134," line.long 0x2FC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_135," line.long 0x300 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_136," line.long 0x304 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_137," line.long 0x308 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_138," line.long 0x30C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_139," line.long 0x310 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_140," line.long 0x314 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_141," line.long 0x318 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_142," line.long 0x31C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_143," line.long 0x320 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_144," line.long 0x324 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_145," line.long 0x328 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_146," line.long 0x32C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_147," line.long 0x330 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_148," line.long 0x334 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_149," line.long 0x338 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_150," line.long 0x33C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_151," line.long 0x340 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_152," line.long 0x344 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_153," line.long 0x348 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_154," line.long 0x34C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_155," line.long 0x350 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_156," line.long 0x354 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_157," line.long 0x358 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_158," line.long 0x35C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_159," line.long 0x360 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_160," line.long 0x364 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_161," line.long 0x368 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_162," line.long 0x36C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_163," line.long 0x370 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_164," line.long 0x374 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_165," line.long 0x378 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_166," line.long 0x37C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_167," line.long 0x380 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_168," line.long 0x384 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_169," line.long 0x388 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_170," line.long 0x38C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_171," line.long 0x390 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_172," line.long 0x394 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_173," line.long 0x398 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_174," line.long 0x39C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_175," line.long 0x3A0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_176," line.long 0x3A4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_177," line.long 0x3A8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_178," line.long 0x3AC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_179," line.long 0x3B0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_180," line.long 0x3B4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_181," line.long 0x3B8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_182," line.long 0x3BC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_183," line.long 0x3C0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_184," line.long 0x3C4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_185," line.long 0x3C8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_186," line.long 0x3CC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_187," line.long 0x3D0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_188," line.long 0x3D4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_189," line.long 0x3D8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_190," line.long 0x3DC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_191," line.long 0x3E0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_192," line.long 0x3E4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_193," line.long 0x3E8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_194," line.long 0x3EC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_195," line.long 0x3F0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_196," line.long 0x3F4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_197," line.long 0x3F8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_198," line.long 0x3FC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_199," tree.end tree "SUBNOC_DME_IN_IA_KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506200 group.long 0x0++0x1FF line.long 0x0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x70 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x74 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x78 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x7C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x80 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x84 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0x88 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0x8C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0x90 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0x94 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0x98 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0x9C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xA0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xA4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xA8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xAC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xB0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xB4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xB8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xBC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xC0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xC4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xC8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xCC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xD0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xD4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xD8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xDC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xE0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xE4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0xE8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0xEC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0xF0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0xF4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0xF8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0xFC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x100 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x104 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x108 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x10C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x110 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x114 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x118 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x11C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x120 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x124 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x130 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x134 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x138 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x13C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x140 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x144 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x148 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x14C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x150 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x154 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x158 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x15C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x160 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x164 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x168 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x16C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x170 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x174 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x178 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x17C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x180 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x184 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x188 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x18C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x190 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x194 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x198 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x19C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1A0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1A4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1A8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1AC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1B0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1B4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1B8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1BC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1C0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1C4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1C8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1CC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1D0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1D4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1D8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1DC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1E0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1E4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," line.long 0x1E8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_107," line.long 0x1EC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_108," line.long 0x1F0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_109," line.long 0x1F4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_110," line.long 0x1F8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_111," line.long 0x1FC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_112," tree.end tree "SUBNOC_DME_IN_IA_KITE1_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B502C00 group.long 0x0++0x3FF line.long 0x0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "SUBNOC_DME_IN_IA_KITE2_PACKET_PROBE_MAIN_PROBE" base ad:0x7B503000 group.long 0x0++0x3FF line.long 0x0 "KITE2_PACKET_PROBE_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE2_PACKET_PROBE_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE2_PACKET_PROBE_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE2_PACKET_PROBE_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE2_PACKET_PROBE_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE2_PACKET_PROBE_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_211," tree.end tree "SUBNOC_DME_IN_IA_KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506800 group.long 0x0++0x7F line.long 0x0 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x40 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x44 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x48 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x4C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x50 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x54 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x58 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x5C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x60 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x64 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x68 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x6C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x6C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x70 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x70 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x74 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x74 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x78 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x78 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x7C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," tree.end tree "SUBNOC_DME_IN_IA_KITE2_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B503400 group.long 0x0++0x3FF line.long 0x0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "SUBNOC_DME_IN_IA_NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000400 group.long 0x0++0x7F line.long 0x0 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_DME_IN_IA_NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000D80 group.long 0x0++0x7F line.long 0x0 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_DME_IN_IA_NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000480 group.long 0x0++0x7F line.long 0x0 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_DME_IN_IA_NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000E00 group.long 0x0++0x7F line.long 0x0 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_DME_IN_IA_NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000500 group.long 0x0++0x7F line.long 0x0 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_DME_IN_IA_NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000E80 group.long 0x0++0x7F line.long 0x0 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_DME_IN_IA_OBSERVER_HSM_MAIN_ERRORLOGGER_0" base ad:0x7B506A80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "SUBNOC_DME_IN_IA_OBSERVER_KITE0_MAIN_ERRORLOGGER_0" base ad:0x7B506B00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "SUBNOC_DME_IN_IA_OBSERVER_KITE1_MAIN_ERRORLOGGER_0" base ad:0x7B506B80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "SUBNOC_DME_IN_IA_OBSERVER_KITE2_MAIN_ERRORLOGGER_0" base ad:0x7B506C00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "SUBNOC_DME_IN_IA_OBSERVER_MAIN0_MAIN_ATBENDPOINT" base ad:0x7B506900 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ATBID," hexmask.long.byte 0x8 0.--6. 1. "ATBID,ATB AtId" line.long 0xC "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ATBEN," bitfld.long 0xC 0. "ATBEN,ATB Unit Enable" "0,1" line.long 0x10 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_SYNCPERIOD," hexmask.long.byte 0x10 0.--4. 1. "SYNCPERIOD,ATB Synchro Period" line.long 0x14 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_00," line.long 0x18 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_01," line.long 0x1C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_02," line.long 0x20 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_03," line.long 0x24 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_04," line.long 0x28 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_05," line.long 0x2C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_06," line.long 0x30 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_07," line.long 0x34 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_08," line.long 0x38 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_09," line.long 0x3C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_10," line.long 0x40 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_11," line.long 0x44 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_12," line.long 0x48 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_13," line.long 0x4C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_14," line.long 0x50 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_15," line.long 0x54 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_16," line.long 0x58 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_17," line.long 0x5C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_18," line.long 0x60 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_19," line.long 0x64 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_20," line.long 0x68 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_21," line.long 0x6C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_22," line.long 0x70 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_23," line.long 0x74 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_24," line.long 0x78 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_25," line.long 0x7C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_26," tree.end tree "SUBNOC_DME_IN_IA_OBSERVER_MAIN0_MAIN_ERRORLOGGER_0" base ad:0x7B506C80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "SUBNOC_DME_IN_IA_OBSERVER_MAIN1_MAIN_ATBENDPOINT" base ad:0x7B506980 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ATBID," hexmask.long.byte 0x8 0.--6. 1. "ATBID,ATB AtId" line.long 0xC "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ATBEN," bitfld.long 0xC 0. "ATBEN,ATB Unit Enable" "0,1" line.long 0x10 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_SYNCPERIOD," hexmask.long.byte 0x10 0.--4. 1. "SYNCPERIOD,ATB Synchro Period" line.long 0x14 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_00," line.long 0x18 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_01," line.long 0x1C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_02," line.long 0x20 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_03," line.long 0x24 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_04," line.long 0x28 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_05," line.long 0x2C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_06," line.long 0x30 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_07," line.long 0x34 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_08," line.long 0x38 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_09," line.long 0x3C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_10," line.long 0x40 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_11," line.long 0x44 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_12," line.long 0x48 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_13," line.long 0x4C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_14," line.long 0x50 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_15," line.long 0x54 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_16," line.long 0x58 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_17," line.long 0x5C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_18," line.long 0x60 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_19," line.long 0x64 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_20," line.long 0x68 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_21," line.long 0x6C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_22," line.long 0x70 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_23," line.long 0x74 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_24," line.long 0x78 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_25," line.long 0x7C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_26," tree.end tree "SUBNOC_DME_IN_IA_OBSERVER_MAIN1_MAIN_ERRORLOGGER_0" base ad:0x7B506D00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "SUBNOC_DME_IN_IA_OBSERVER_PCIE_MAIN_ATBENDPOINT" base ad:0x7B506A00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_PCIE_MAIN_ATBENDPOINT_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_PCIE_MAIN_ATBENDPOINT_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_PCIE_MAIN_ATBENDPOINT_ATBID," hexmask.long.byte 0x8 0.--6. 1. "ATBID,ATB AtId" line.long 0xC "OBSERVER_PCIE_MAIN_ATBENDPOINT_ATBEN," bitfld.long 0xC 0. "ATBEN,ATB Unit Enable" "0,1" line.long 0x10 "OBSERVER_PCIE_MAIN_ATBENDPOINT_SYNCPERIOD," hexmask.long.byte 0x10 0.--4. 1. "SYNCPERIOD,ATB Synchro Period" line.long 0x14 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_00," line.long 0x18 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_01," line.long 0x1C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_02," line.long 0x20 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_03," line.long 0x24 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_04," line.long 0x28 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_05," line.long 0x2C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_06," line.long 0x30 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_07," line.long 0x34 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_08," line.long 0x38 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_09," line.long 0x3C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_10," line.long 0x40 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_11," line.long 0x44 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_12," line.long 0x48 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_13," line.long 0x4C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_14," line.long 0x50 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_15," line.long 0x54 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_16," line.long 0x58 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_17," line.long 0x5C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_18," line.long 0x60 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_19," line.long 0x64 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_20," line.long 0x68 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_21," line.long 0x6C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_22," line.long 0x70 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_23," line.long 0x74 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_24," line.long 0x78 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_25," line.long 0x7C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_26," tree.end tree "SUBNOC_DME_IN_IA_OBSERVER_PCIE_MAIN_ERRORLOGGER_0" base ad:0x7B506D80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "SUBNOC_DME_IN_IA_PCIE_0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000580 group.long 0x0++0x7F line.long 0x0 "PCIE_0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "PCIE_0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "PCIE_0_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "PCIE_0_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "PCIE_0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_DME_IN_IA_PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000F00 group.long 0x0++0x7F line.long 0x0 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_DME_IN_IA_PCIE_1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000600 group.long 0x0++0x7F line.long 0x0 "PCIE_1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "PCIE_1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "PCIE_1_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "PCIE_1_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "PCIE_1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_DME_IN_IA_PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000F80 group.long 0x0++0x7F line.long 0x0 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_DME_IN_IA_PCIE_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B503800 group.long 0x0++0x3FF line.long 0x0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x234 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x238 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x23C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x240 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x244 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x248 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x24C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x250 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x254 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x258 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x25C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x260 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x264 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x268 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x26C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x270 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x274 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x278 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x27C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x280 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x284 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x288 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x28C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x290 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x294 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x298 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x29C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2A0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2A4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2A8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2AC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2B0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2B4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2B8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2BC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2C0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2C4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2C8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2CC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x2D0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x2D4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x2D8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x2DC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x2E0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x2E4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x2E8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x2EC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x2F0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x2F4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x2F8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x2FC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x300 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x304 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x308 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x30C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x310 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x314 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x318 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x31C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x320 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x324 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x328 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x32C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x330 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x334 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x338 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x33C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x340 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x344 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x348 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x34C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x350 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x354 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x358 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x35C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x360 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x364 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x368 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x36C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x370 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x374 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x378 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x37C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x380 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x384 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x388 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x38C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x390 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x394 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x398 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x39C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3A0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3A4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3A8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3AC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3B0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3B4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3B8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3BC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3C0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3C4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3C8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3CC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," line.long 0x3D0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_208," line.long 0x3D4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_209," line.long 0x3D8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_210," line.long 0x3DC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_211," line.long 0x3E0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_212," line.long 0x3E4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_213," line.long 0x3E8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_214," line.long 0x3EC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_215," line.long 0x3F0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_216," line.long 0x3F4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_217," line.long 0x3F8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_218," line.long 0x3FC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_219," tree.end tree "SUBNOC_DME_IN_IA_PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506880 group.long 0x0++0x7F line.long 0x0 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x38 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x3C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x40 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x44 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x48 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x6C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x70 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x70 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x74 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x74 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x78 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x78 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x7C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," tree.end tree "SUBNOC_DME_IN_IA_PCIE_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B503C00 group.long 0x0++0x3FF line.long 0x0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "SUBNOC_DME_IN_IA_POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER" base ad:0x7B506E00 group.long 0x0++0x7F line.long 0x0 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT0," hexmask.long 0x8 0.--31. 1. "MISSIONFAULT0,MissionFault0 register" line.long 0xC "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT1," hexmask.long 0xC 0.--31. 1. "MISSIONFAULT1,MissionFault1 register" line.long 0x10 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT2," hexmask.long 0x10 0.--31. 1. "MISSIONFAULT2,MissionFault2 register" line.long 0x14 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT3," hexmask.long 0x14 0.--31. 1. "MISSIONFAULT3,MissionFault3 register" line.long 0x18 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT0," hexmask.long 0x18 0.--31. 1. "LATENTFAULT0,LatentFault0 register" line.long 0x1C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT1," hexmask.long 0x1C 0.--31. 1. "LATENTFAULT1,LatentFault1 register" line.long 0x20 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT2," hexmask.long 0x20 0.--31. 1. "LATENTFAULT2,LatentFault2 register" line.long 0x24 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT3," hexmask.long 0x24 0.--31. 1. "LATENTFAULT3,LatentFault3 register" line.long 0x28 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_FAULTS," bitfld.long 0x28 1. "MISSIONFAULT,Mission Fault" "0,1" bitfld.long 0x28 0. "LATENTFAULT,Latent Fault" "0,1" line.long 0x2C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_INTEN," bitfld.long 0x2C 1. "MISSIONFAULTEN,MissionFault Interrupt enable" "0,1" bitfld.long 0x2C 0. "BISTDONEEN,BistDone Interrupt enable" "0,1" line.long 0x30 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_INTCLR," bitfld.long 0x30 1. "MISSIONFAULTCLR,Clear Mission Fault" "0,1" bitfld.long 0x30 0. "LATENTFAULTCLR,Clear Latent Fault" "0,1" line.long 0x34 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTCTL," bitfld.long 0x34 1. "BISTDONECLR,Clear BistDone" "0,1" bitfld.long 0x34 0. "BISTSTART,Start Bist sequence" "0,1" line.long 0x38 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTDONE," bitfld.long 0x38 1. "MISSIONMODE,Mission Mode Status" "0,1" bitfld.long 0x38 0. "BISTDONE,BistDone Status" "0,1" line.long 0x3C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO1," hexmask.long.word 0x3C 0.--15. 1. "BISTTO1,BistTimeOut register" line.long 0x40 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO2," hexmask.long.byte 0x40 0.--7. 1. "BISTTO2,BistTimeOut register" line.long 0x44 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_00," line.long 0x48 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_01," line.long 0x4C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_02," line.long 0x50 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_03," line.long 0x54 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_04," line.long 0x58 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_05," line.long 0x5C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_06," line.long 0x60 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_07," line.long 0x64 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_08," line.long 0x68 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_09," line.long 0x6C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_10," line.long 0x70 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_11," line.long 0x74 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_12," line.long 0x78 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_13," line.long 0x7C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_14," tree.end tree "SUBNOC_DME_IN_IA_POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER" base ad:0x7B506E80 group.long 0x0++0x7F line.long 0x0 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT0," hexmask.long 0x8 0.--31. 1. "MISSIONFAULT0,MissionFault0 register" line.long 0xC "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT1," hexmask.long 0xC 0.--31. 1. "MISSIONFAULT1,MissionFault1 register" line.long 0x10 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT2," hexmask.long 0x10 0.--31. 1. "MISSIONFAULT2,MissionFault2 register" line.long 0x14 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT3," hexmask.long 0x14 0.--31. 1. "MISSIONFAULT3,MissionFault3 register" line.long 0x18 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT0," hexmask.long 0x18 0.--31. 1. "LATENTFAULT0,LatentFault0 register" line.long 0x1C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT1," hexmask.long 0x1C 0.--31. 1. "LATENTFAULT1,LatentFault1 register" line.long 0x20 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT2," hexmask.long 0x20 0.--31. 1. "LATENTFAULT2,LatentFault2 register" line.long 0x24 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT3," hexmask.long 0x24 0.--31. 1. "LATENTFAULT3,LatentFault3 register" line.long 0x28 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_FAULTS," bitfld.long 0x28 1. "MISSIONFAULT,Mission Fault" "0,1" bitfld.long 0x28 0. "LATENTFAULT,Latent Fault" "0,1" line.long 0x2C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_INTEN," bitfld.long 0x2C 1. "MISSIONFAULTEN,MissionFault Interrupt enable" "0,1" bitfld.long 0x2C 0. "BISTDONEEN,BistDone Interrupt enable" "0,1" line.long 0x30 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_INTCLR," bitfld.long 0x30 1. "MISSIONFAULTCLR,Clear Mission Fault" "0,1" bitfld.long 0x30 0. "LATENTFAULTCLR,Clear Latent Fault" "0,1" line.long 0x34 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTCTL," bitfld.long 0x34 1. "BISTDONECLR,Clear BistDone" "0,1" bitfld.long 0x34 0. "BISTSTART,Start Bist sequence" "0,1" line.long 0x38 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTDONE," bitfld.long 0x38 1. "MISSIONMODE,Mission Mode Status" "0,1" bitfld.long 0x38 0. "BISTDONE,BistDone Status" "0,1" line.long 0x3C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO1," hexmask.long.word 0x3C 0.--15. 1. "BISTTO1,BistTimeOut register" line.long 0x40 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO2," hexmask.long.byte 0x40 0.--7. 1. "BISTTO2,BistTimeOut register" line.long 0x44 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_00," line.long 0x48 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_01," line.long 0x4C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_02," line.long 0x50 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_03," line.long 0x54 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_04," line.long 0x58 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_05," line.long 0x5C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_06," line.long 0x60 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_07," line.long 0x64 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_08," line.long 0x68 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_09," line.long 0x6C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_10," line.long 0x70 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_11," line.long 0x74 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_12," line.long 0x78 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_13," line.long 0x7C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_14," tree.end tree "SUBNOC_DME_IN_IA_SDMMC_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000680 group.long 0x0++0x7F line.long 0x0 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_DME_IN_IA_SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001000 group.long 0x0++0x7F line.long 0x0 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_DME_IN_IA_SDMMC_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B504000 group.long 0x0++0x3FF line.long 0x0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x14 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x34 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x3C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x4C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x50 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x54 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x58 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x5C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x60 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x64 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x68 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x6C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x70 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x74 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x78 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x7C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x80 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x90 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x98 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0x9C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xB8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xBC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xC8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xCC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xD8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xDC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xE8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xEC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xF8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0xFC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x100 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x104 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x108 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x10C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x110 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x114 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x118 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x11C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x120 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x124 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x128 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x12C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x130 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x134 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x138 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x13C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x140 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x144 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x148 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x14C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x150 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x154 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x158 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x15C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x160 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x164 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x168 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x16C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x170 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x174 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x178 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x17C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x180 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x184 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x188 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x18C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x190 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x194 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x198 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x19C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1A8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1AC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1B8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1BC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1C8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1CC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1D8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1DC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1E8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1EC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1F8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x1FC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x200 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x204 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x214 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x224 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x234 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x244 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x254 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x264 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x274 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x284 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x288 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x28C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x290 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x294 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x298 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x29C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2A8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2AC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2B8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2BC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2C8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2CC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2D8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2DC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2E8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2EC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2F8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x2FC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x300 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x304 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x308 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x30C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x310 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x314 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x318 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x31C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x320 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x324 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x328 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x32C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x330 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x334 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x338 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x33C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x340 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x344 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x348 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x34C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x350 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x354 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x358 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x35C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x360 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x364 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x368 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x36C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x370 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x374 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x378 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x37C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x380 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x384 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x388 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x38C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x390 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x394 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x398 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x39C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3A8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3AC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3B8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3BC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3C8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3CC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3D8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3DC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3E8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3EC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3F8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," line.long 0x3FC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_208," tree.end tree "SUBNOC_DME_IN_IA_SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506400 group.long 0x0++0x1FF line.long 0x0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x70 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x74 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x78 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x7C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x80 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x84 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0x88 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0x8C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0x90 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0x94 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0x98 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0x9C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xA0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xA4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xA8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xAC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xB0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xB4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xB8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xBC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xC0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xC4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xC8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xCC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xD0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xD4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xD8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xDC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xE0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xE4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0xE8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0xEC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0xF0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0xF4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0xF8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0xFC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x100 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x104 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x108 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x10C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x110 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x114 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x118 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x11C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x120 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x124 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x130 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x134 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x138 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x13C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x140 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x144 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x148 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x14C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x150 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x154 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x158 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x15C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x160 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x164 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x168 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x16C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x170 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x174 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x178 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x17C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x180 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x184 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x188 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x18C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x190 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x194 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x198 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x19C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1A0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1A4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1A8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1AC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1B0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1B4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1B8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1BC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1C0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1C4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1C8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1CC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1D0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1D4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1D8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1DC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1E0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1E4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," line.long 0x1E8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_107," line.long 0x1EC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_108," line.long 0x1F0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_109," line.long 0x1F4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_110," line.long 0x1F8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_111," line.long 0x1FC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_112," tree.end tree "SUBNOC_DME_IN_IA_SDMMC_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B504400 group.long 0x0++0x3FF line.long 0x0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x14 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x34 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x3C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x4C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x50 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x54 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x58 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x5C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x60 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x64 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x68 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x6C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x70 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x74 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x78 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x7C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x80 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x90 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x98 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0x9C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xB8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xBC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xC8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xCC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xD8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xDC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xE8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xEC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xF8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0xFC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x100 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x104 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x108 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x10C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x110 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x114 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x118 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x11C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x120 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x124 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x128 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x12C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x130 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x134 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x138 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x13C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x140 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x144 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x148 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x14C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x150 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x154 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x158 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x15C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x160 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x164 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x168 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x16C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x170 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x174 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x178 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x17C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x180 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x184 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x188 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x18C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x190 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x194 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x198 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x19C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1A8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1AC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1B8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1BC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1C8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1CC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1D8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1DC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1E8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1EC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1F8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x1FC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x200 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x204 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x214 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x218 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x21C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x220 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x224 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x228 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x22C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x230 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x234 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x238 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x23C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x240 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x244 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x248 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x24C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x250 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x254 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x258 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x25C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x260 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x264 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x268 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x26C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x270 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x274 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x278 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x27C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x280 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x284 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x288 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x28C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x290 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x294 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x298 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x29C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2A4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2A8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2AC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2B4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2B8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2BC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2C4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2C8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2CC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2D4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2D8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2DC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2E4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2E8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2EC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2F4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x2F8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x2FC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x300 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x304 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x308 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x30C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x310 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x314 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x318 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x31C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x320 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x324 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x328 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x32C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x330 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x334 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x338 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x33C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x340 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x344 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x348 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x34C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x350 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x354 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x358 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x35C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x360 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x364 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x368 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x36C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x370 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x374 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x378 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x37C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x380 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x384 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x388 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x38C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x390 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x394 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x398 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x39C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3A4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3A8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3AC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3B4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3B8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3BC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3C4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3C8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3CC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3D4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3D8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3DC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3E4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3E8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3EC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3F4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," line.long 0x3F8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_228," line.long 0x3FC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_229," tree.end tree "SUBNOC_DME_IN_IA_SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000700 group.long 0x0++0x7F line.long 0x0 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_DME_IN_IA_SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000780 group.long 0x0++0x7F line.long 0x0 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_DME_IN_IA_SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000800 group.long 0x0++0x7F line.long 0x0 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_DME_IN_IA_SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B504800 group.long 0x0++0x3FF line.long 0x0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "SUBNOC_DME_IN_IA_SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B504C00 group.long 0x0++0x3FF line.long 0x0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "SUBNOC_DME_IN_IA_ZIPW0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000880 group.long 0x0++0x7F line.long 0x0 "ZIPW0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ZIPW0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ZIPW0_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ZIPW0_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ZIPW0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_DME_IN_IA_ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001080 group.long 0x0++0x7F line.long 0x0 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_DME_IN_IA_ZIPW1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000900 group.long 0x0++0x7F line.long 0x0 "ZIPW1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ZIPW1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ZIPW1_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ZIPW1_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ZIPW1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_DME_IN_IA_ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001100 group.long 0x0++0x7F line.long 0x0 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_DME_IN_IA_ZIPW_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B505000 group.long 0x0++0x3FF line.long 0x0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x264 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x268 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x26C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x270 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x274 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x278 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x27C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x280 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x284 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x288 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x28C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x290 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x294 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x298 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x29C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2A0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2AC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2B0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2BC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2C0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2CC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2D0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2DC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2E0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2EC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2F0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2FC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x300 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x304 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x308 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x30C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x310 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x314 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x318 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x31C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x320 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x324 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x328 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x32C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x330 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x334 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x338 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x33C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x340 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x344 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x348 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x34C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x350 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x354 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x358 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x35C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x360 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x364 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x368 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x36C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x370 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x374 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x378 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x37C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x380 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x384 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x388 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x38C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x390 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x394 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x398 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x39C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3A0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3AC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3B0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3BC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3C0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3CC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3D0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3DC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3E0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3EC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3F0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3FC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," tree.end tree "SUBNOC_DME_IN_IA_ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506600 group.long 0x0++0x1FF line.long 0x0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x44 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x48 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x4C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x50 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x54 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x58 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x5C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x60 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x64 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x68 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x80 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x84 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x88 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x8C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x90 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x94 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x98 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x9C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xA4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xA8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xAC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xB4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xB8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xBC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xC4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xC8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xCC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xD4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xD8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xDC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xE4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xE8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xEC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xF4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xF8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xFC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x100 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x104 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x108 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x10C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x110 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x114 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x118 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x11C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x130 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x134 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x138 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x13C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x140 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x144 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x148 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x14C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x150 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x154 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x158 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x15C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x160 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x164 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x168 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x16C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x170 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x174 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x178 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x17C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x180 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x184 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x188 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x18C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x190 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x194 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x198 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x19C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1A4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1A8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1AC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1B4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1B8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1BC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1C4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1C8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1CC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1D4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1D8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1DC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1E4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1E8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1EC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1F4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1F8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1FC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," tree.end tree "SUBNOC_DME_IN_IA_ZIPW_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B505400 group.long 0x0++0x3FF line.long 0x0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree.end tree "SUBNOC_HSM" tree "SUBNOC_HSM_IN_IA_DAP0_AXI_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000000 group.long 0x0++0x7F line.long 0x0 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "DAP0_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_HSM_IN_IA_DAP1_AXI_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000080 group.long 0x0++0x7F line.long 0x0 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "DAP1_AXI_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_HSM_IN_IA_DFA_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000100 group.long 0x0++0x7F line.long 0x0 "DFA_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DFA_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DFA_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "DFA_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "DFA_IN_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--12. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "DFA_IN_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "DFA_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "DFA_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_HSM_IN_IA_DMA0_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B500000 group.long 0x0++0x3FF line.long 0x0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_PORTSEL," bitfld.long 0x270 0. "COUNTERS_7_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x274 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x284 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x288 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x28C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x290 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x294 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x298 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x29C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x2A0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x2A4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x2A8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x2AC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x2B0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x2B4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x2B8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x2BC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2C0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2C4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2C8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2CC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2D0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2D4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2D8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2DC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2E0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2E4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2E8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2EC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2F0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2F4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2F8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2FC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x300 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x304 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x308 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x30C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x310 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x314 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x318 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x31C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x320 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x324 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x328 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x32C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x330 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x334 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x338 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x33C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x340 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x344 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x348 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x34C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x350 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x354 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x358 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x35C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x360 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x364 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x368 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x36C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x370 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x374 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x378 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x37C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x380 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x384 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x388 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x38C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x390 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x394 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x398 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x39C "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x3A0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x3A4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x3A8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x3AC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x3B0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x3B4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x3B8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x3BC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3C0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3C4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3C8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3CC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3D0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3D4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3D8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3DC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3E0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3E4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3E8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3EC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3F0 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3F4 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3F8 "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3FC "DMA0_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," tree.end tree "SUBNOC_HSM_IN_IA_DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505800 group.long 0x0++0x1FF line.long 0x0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x4C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x50 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x54 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x58 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x5C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x60 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x64 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x68 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_5," hexmask.long.byte 0x7C 0.--3. 1. "THRESHOLDS_1_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x80 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_6," hexmask.long.byte 0x80 0.--3. 1. "THRESHOLDS_1_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x84 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x88 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x8C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x90 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x94 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x98 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x9C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0xA0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0xA4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0xA8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0xAC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xB0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xB4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xB8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xBC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xC0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xC4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xC8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xCC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xD0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xD4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xD8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xDC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xE0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xE4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xE8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xEC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xF0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xF4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xF8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xFC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0x100 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0x104 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0x108 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0x10C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x110 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x114 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x118 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x11C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x130 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x134 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x138 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x13C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x140 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x144 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x148 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x14C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x150 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x154 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x158 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x15C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x160 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x164 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x168 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x16C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x170 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x174 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x178 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x17C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x180 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x184 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x188 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x18C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x190 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x194 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x198 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x19C "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x1A0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x1A4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x1A8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x1AC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1B0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1B4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1B8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1BC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1C0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1C4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1C8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1CC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1D0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1D4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1D8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1DC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1E0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1E4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1E8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1EC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1F0 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1F4 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1F8 "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1FC "DMA0_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," tree.end tree "SUBNOC_HSM_IN_IA_DMA0_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B500400 group.long 0x0++0x3FF line.long 0x0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "DMA0_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "SUBNOC_HSM_IN_IA_DMA1_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B500800 group.long 0x0++0x3FF line.long 0x0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x274 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x278 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x27C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x280 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x284 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x288 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x28C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x290 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x294 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x298 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x29C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x2A0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x2A4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x2A8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x2AC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2B0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2B4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2B8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2BC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2C0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2C4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2C8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2CC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2D0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2D4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2D8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2DC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2E0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2E4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2E8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2EC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2F0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2F4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2F8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2FC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x300 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x304 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x308 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x30C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x310 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x314 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x318 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x31C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x320 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x324 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x328 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x32C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x330 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x334 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x338 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x33C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x340 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x344 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x348 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x34C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x350 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x354 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x358 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x35C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x360 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x364 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x368 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x36C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x370 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x374 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x378 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x37C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x380 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x384 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x388 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x38C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x390 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x394 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x398 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x39C "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x3A0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x3A4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x3A8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x3AC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3B0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3B4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3B8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3BC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3C0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3C4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3C8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3CC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3D0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3D4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3D8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3DC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3E0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3E4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3E8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3EC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3F0 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3F4 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3F8 "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3FC "DMA1_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," tree.end tree "SUBNOC_HSM_IN_IA_DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505A00 group.long 0x0++0x1FF line.long 0x0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x48 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x4C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x50 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x54 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x58 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x5C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x60 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x64 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x68 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_5," hexmask.long.byte 0x7C 0.--3. 1. "THRESHOLDS_1_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x80 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x84 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x88 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x8C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x90 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x94 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x98 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x9C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0xA0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0xA4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xAC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xB0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xB4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xBC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xC0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xC4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xCC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xD0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xD4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xDC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xE0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xE4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xEC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xF0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xF4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xFC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0x100 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0x104 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x108 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x10C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x110 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x114 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x118 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x11C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x130 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x134 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x138 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x13C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x140 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x144 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x148 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x14C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x150 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x154 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x158 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x15C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x160 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x164 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x168 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x16C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x170 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x174 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x178 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x17C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x180 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x184 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x188 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x18C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x190 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x194 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x198 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x19C "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x1A0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x1A4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1AC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1B0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1B4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1BC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1C0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1C4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1CC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1D0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1D4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1DC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1E0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1E4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1EC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1F0 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1F4 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F8 "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1FC "DMA1_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," tree.end tree "SUBNOC_HSM_IN_IA_DMA1_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B500C00 group.long 0x0++0x3FF line.long 0x0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "DMA1_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "SUBNOC_HSM_IN_IA_EDMA_0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000980 group.long 0x0++0x7F line.long 0x0 "EDMA_0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_0_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_HSM_IN_IA_EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001180 group.long 0x0++0x7F line.long 0x0 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_HSM_IN_IA_EDMA_1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000A00 group.long 0x0++0x7F line.long 0x0 "EDMA_1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_1_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_HSM_IN_IA_EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001200 group.long 0x0++0x7F line.long 0x0 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_HSM_IN_IA_EDMA_2_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000A80 group.long 0x0++0x7F line.long 0x0 "EDMA_2_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_2_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_2_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_2_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_2_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_2_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_HSM_IN_IA_EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001280 group.long 0x0++0x7F line.long 0x0 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_2_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_HSM_IN_IA_EDMA_3_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000B00 group.long 0x0++0x7F line.long 0x0 "EDMA_3_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_3_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_3_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "EDMA_3_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "EDMA_3_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "EDMA_3_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_HSM_IN_IA_EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001300 group.long 0x0++0x7F line.long 0x0 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "EDMA_3_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_HSM_IN_IA_ETHER0_I_MAIN_QOSGENERATOR" base ad:0x7B000180 group.long 0x0++0x7F line.long 0x0 "ETHER0_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER0_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER0_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ETHER0_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ETHER0_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ETHER0_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ETHER0_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ETHER0_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_HSM_IN_IA_ETHER0_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000B80 group.long 0x0++0x7F line.long 0x0 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ETHER0_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_HSM_IN_IA_ETHER1_I_MAIN_QOSGENERATOR" base ad:0x7B000200 group.long 0x0++0x7F line.long 0x0 "ETHER1_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER1_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER1_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ETHER1_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ETHER1_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ETHER1_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ETHER1_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ETHER1_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_HSM_IN_IA_ETHER1_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000C00 group.long 0x0++0x7F line.long 0x0 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ETHER1_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_HSM_IN_IA_ETHR_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B501000 group.long 0x0++0x3FF line.long 0x0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x264 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x268 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x26C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x270 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x274 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x278 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x27C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x280 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x284 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x288 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x28C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x290 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x294 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x298 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x29C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2A0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2AC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2B0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2BC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2C0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2CC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2D0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2DC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2E0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2EC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2F0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2FC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x300 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x304 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x308 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x30C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x310 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x314 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x318 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x31C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x320 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x324 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x328 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x32C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x330 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x334 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x338 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x33C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x340 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x344 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x348 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x34C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x350 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x354 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x358 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x35C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x360 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x364 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x368 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x36C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x370 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x374 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x378 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x37C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x380 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x384 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x388 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x38C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x390 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x394 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x398 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x39C "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3A0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3AC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3B0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3BC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3C0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3CC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3D0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3DC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3E0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3EC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3F0 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F4 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F8 "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3FC "ETHR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," tree.end tree "SUBNOC_HSM_IN_IA_ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505C00 group.long 0x0++0x1FF line.long 0x0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x44 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x48 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x4C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x50 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x54 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x58 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x5C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x60 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x64 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x68 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x80 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x84 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x88 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x8C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x90 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x94 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x98 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x9C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xA4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xA8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xAC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xB4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xB8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xBC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xC4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xC8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xCC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xD4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xD8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xDC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xE4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xE8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xEC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xF4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xF8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xFC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x100 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x104 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x108 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x10C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x110 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x114 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x118 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x11C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x130 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x134 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x138 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x13C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x140 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x144 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x148 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x14C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x150 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x154 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x158 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x15C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x160 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x164 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x168 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x16C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x170 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x174 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x178 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x17C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x180 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x184 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x188 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x18C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x190 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x194 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x198 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x19C "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1A4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1A8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1AC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1B4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1B8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1BC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1C4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1C8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1CC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1D4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1D8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1DC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1E4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1E8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1EC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F0 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1F4 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1F8 "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1FC "ETHR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," tree.end tree "SUBNOC_HSM_IN_IA_ETHR_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B501400 group.long 0x0++0x3FF line.long 0x0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "ETHR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "SUBNOC_HSM_IN_IA_FLEX0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000280 group.long 0x0++0x7F line.long 0x0 "FLEX0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "FLEX0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "FLEX0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "FLEX0_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_HSM_IN_IA_FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000C80 group.long 0x0++0x7F line.long 0x0 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "FLEX0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_HSM_IN_IA_FLEX1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000300 group.long 0x0++0x7F line.long 0x0 "FLEX1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "FLEX1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "FLEX1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "FLEX1_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_HSM_IN_IA_FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000D00 group.long 0x0++0x7F line.long 0x0 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "FLEX1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_HSM_IN_IA_FR_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B501800 group.long 0x0++0x3FF line.long 0x0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "FR_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "FR_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "FR_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "FR_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x264 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x268 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x26C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x270 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x274 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x278 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x27C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x280 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x284 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x288 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x28C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x290 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x294 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x298 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x29C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2A0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2AC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2B0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2BC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2C0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2CC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2D0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2DC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2E0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2EC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2F0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2FC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x300 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x304 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x308 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x30C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x310 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x314 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x318 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x31C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x320 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x324 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x328 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x32C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x330 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x334 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x338 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x33C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x340 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x344 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x348 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x34C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x350 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x354 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x358 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x35C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x360 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x364 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x368 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x36C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x370 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x374 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x378 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x37C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x380 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x384 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x388 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x38C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x390 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x394 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x398 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x39C "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3A0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3AC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3B0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3BC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3C0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3CC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3D0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3DC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3E0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3EC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3F0 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F4 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F8 "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3FC "FR_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," tree.end tree "SUBNOC_HSM_IN_IA_FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B505E00 group.long 0x0++0x1FF line.long 0x0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x44 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x48 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x4C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x50 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x54 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x58 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x5C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x60 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x64 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x68 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x80 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x84 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x88 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x8C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x90 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x94 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x98 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x9C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xA4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xA8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xAC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xB4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xB8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xBC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xC4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xC8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xCC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xD4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xD8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xDC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xE4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xE8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xEC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xF4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xF8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xFC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x100 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x104 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x108 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x10C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x110 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x114 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x118 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x11C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x130 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x134 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x138 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x13C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x140 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x144 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x148 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x14C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x150 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x154 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x158 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x15C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x160 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x164 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x168 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x16C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x170 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x174 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x178 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x17C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x180 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x184 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x188 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x18C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x190 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x194 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x198 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x19C "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1A4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1A8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1AC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1B4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1B8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1BC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1C4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1C8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1CC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1D4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1D8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1DC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1E4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1E8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1EC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F0 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1F4 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1F8 "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1FC "FR_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," tree.end tree "SUBNOC_HSM_IN_IA_FR_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B501C00 group.long 0x0++0x3FF line.long 0x0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "FR_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "FR_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "FR_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "FR_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "FR_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "SUBNOC_HSM_IN_IA_GTM_M_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000380 group.long 0x0++0x7F line.long 0x0 "GTM_M_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "GTM_M_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "GTM_M_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "GTM_M_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "GTM_M_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "GTM_M_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "GTM_M_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "GTM_M_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_HSM_IN_IA_KITE0_PACKET_PROBE_MAIN_PROBE" base ad:0x7B502000 group.long 0x0++0x3FF line.long 0x0 "KITE0_PACKET_PROBE_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE0_PACKET_PROBE_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE0_PACKET_PROBE_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE0_PACKET_PROBE_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE0_PACKET_PROBE_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE0_PACKET_PROBE_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE0_PACKET_PROBE_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE0_PACKET_PROBE_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE0_PACKET_PROBE_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_PORTSEL," bitfld.long 0x270 0. "COUNTERS_7_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x274 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "KITE0_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_104," line.long 0x284 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_105," line.long 0x288 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_106," line.long 0x28C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_107," line.long 0x290 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_108," line.long 0x294 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_109," line.long 0x298 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_110," line.long 0x29C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_111," line.long 0x2A0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_112," line.long 0x2A4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_113," line.long 0x2A8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_114," line.long 0x2AC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_115," line.long 0x2B0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_116," line.long 0x2B4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_117," line.long 0x2B8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_118," line.long 0x2BC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_119," line.long 0x2C0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_120," line.long 0x2C4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_121," line.long 0x2C8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_122," line.long 0x2CC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_123," line.long 0x2D0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_124," line.long 0x2D4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_125," line.long 0x2D8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_126," line.long 0x2DC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_127," line.long 0x2E0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_128," line.long 0x2E4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_129," line.long 0x2E8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_130," line.long 0x2EC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_131," line.long 0x2F0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_132," line.long 0x2F4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_133," line.long 0x2F8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_134," line.long 0x2FC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_135," line.long 0x300 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_136," line.long 0x304 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_137," line.long 0x308 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_138," line.long 0x30C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_139," line.long 0x310 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_140," line.long 0x314 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_141," line.long 0x318 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_142," line.long 0x31C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_143," line.long 0x320 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_144," line.long 0x324 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_145," line.long 0x328 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_146," line.long 0x32C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_147," line.long 0x330 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_148," line.long 0x334 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_149," line.long 0x338 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_150," line.long 0x33C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_151," line.long 0x340 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_152," line.long 0x344 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_153," line.long 0x348 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_154," line.long 0x34C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_155," line.long 0x350 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_156," line.long 0x354 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_157," line.long 0x358 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_158," line.long 0x35C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_159," line.long 0x360 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_160," line.long 0x364 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_161," line.long 0x368 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_162," line.long 0x36C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_163," line.long 0x370 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_164," line.long 0x374 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_165," line.long 0x378 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_166," line.long 0x37C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_167," line.long 0x380 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_168," line.long 0x384 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_169," line.long 0x388 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_170," line.long 0x38C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_171," line.long 0x390 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_172," line.long 0x394 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_173," line.long 0x398 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_174," line.long 0x39C "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_175," line.long 0x3A0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_176," line.long 0x3A4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_177," line.long 0x3A8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_178," line.long 0x3AC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_179," line.long 0x3B0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_180," line.long 0x3B4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_181," line.long 0x3B8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_182," line.long 0x3BC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_183," line.long 0x3C0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_184," line.long 0x3C4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_185," line.long 0x3C8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_186," line.long 0x3CC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_187," line.long 0x3D0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_188," line.long 0x3D4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_189," line.long 0x3D8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_190," line.long 0x3DC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_191," line.long 0x3E0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_192," line.long 0x3E4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_193," line.long 0x3E8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_194," line.long 0x3EC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_195," line.long 0x3F0 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_196," line.long 0x3F4 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_197," line.long 0x3F8 "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_198," line.long 0x3FC "KITE0_PACKET_PROBE_MAIN_PROBE_RESERVED_199," tree.end tree "SUBNOC_HSM_IN_IA_KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506000 group.long 0x0++0x1FF line.long 0x0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x70 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x74 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x78 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x7C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x80 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x84 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0x88 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0x8C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0x90 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0x94 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0x98 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0x9C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xA0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xA4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xA8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xAC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xB0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xB4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xB8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xBC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xC0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xC4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xC8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xCC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xD0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xD4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xD8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xDC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xE0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xE4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0xE8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0xEC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0xF0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0xF4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0xF8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0xFC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x100 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x104 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x108 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x10C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x110 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x114 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x118 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x11C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x120 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x124 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x130 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x134 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x138 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x13C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x140 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x144 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x148 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x14C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x150 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x154 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x158 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x15C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x160 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x164 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x168 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x16C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x170 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x174 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x178 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x17C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x180 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x184 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x188 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x18C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x190 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x194 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x198 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x19C "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1A0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1A4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1A8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1AC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1B0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1B4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1B8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1BC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1C0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1C4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1C8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1CC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1D0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1D4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1D8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1DC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1E0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1E4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," line.long 0x1E8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_107," line.long 0x1EC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_108," line.long 0x1F0 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_109," line.long 0x1F4 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_110," line.long 0x1F8 "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_111," line.long 0x1FC "KITE0_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_112," tree.end tree "SUBNOC_HSM_IN_IA_KITE0_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B502400 group.long 0x0++0x3FF line.long 0x0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "SUBNOC_HSM_IN_IA_KITE1_PACKET_PROBE_MAIN_PROBE" base ad:0x7B502800 group.long 0x0++0x3FF line.long 0x0 "KITE1_PACKET_PROBE_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE1_PACKET_PROBE_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE1_PACKET_PROBE_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE1_PACKET_PROBE_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE1_PACKET_PROBE_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE1_PACKET_PROBE_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE1_PACKET_PROBE_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE1_PACKET_PROBE_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE1_PACKET_PROBE_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_PORTSEL," bitfld.long 0x260 0. "COUNTERS_6_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x264 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_PORTSEL," bitfld.long 0x270 0. "COUNTERS_7_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x274 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "KITE1_PACKET_PROBE_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_104," line.long 0x284 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_105," line.long 0x288 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_106," line.long 0x28C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_107," line.long 0x290 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_108," line.long 0x294 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_109," line.long 0x298 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_110," line.long 0x29C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_111," line.long 0x2A0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_112," line.long 0x2A4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_113," line.long 0x2A8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_114," line.long 0x2AC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_115," line.long 0x2B0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_116," line.long 0x2B4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_117," line.long 0x2B8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_118," line.long 0x2BC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_119," line.long 0x2C0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_120," line.long 0x2C4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_121," line.long 0x2C8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_122," line.long 0x2CC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_123," line.long 0x2D0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_124," line.long 0x2D4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_125," line.long 0x2D8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_126," line.long 0x2DC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_127," line.long 0x2E0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_128," line.long 0x2E4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_129," line.long 0x2E8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_130," line.long 0x2EC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_131," line.long 0x2F0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_132," line.long 0x2F4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_133," line.long 0x2F8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_134," line.long 0x2FC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_135," line.long 0x300 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_136," line.long 0x304 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_137," line.long 0x308 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_138," line.long 0x30C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_139," line.long 0x310 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_140," line.long 0x314 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_141," line.long 0x318 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_142," line.long 0x31C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_143," line.long 0x320 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_144," line.long 0x324 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_145," line.long 0x328 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_146," line.long 0x32C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_147," line.long 0x330 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_148," line.long 0x334 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_149," line.long 0x338 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_150," line.long 0x33C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_151," line.long 0x340 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_152," line.long 0x344 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_153," line.long 0x348 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_154," line.long 0x34C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_155," line.long 0x350 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_156," line.long 0x354 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_157," line.long 0x358 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_158," line.long 0x35C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_159," line.long 0x360 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_160," line.long 0x364 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_161," line.long 0x368 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_162," line.long 0x36C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_163," line.long 0x370 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_164," line.long 0x374 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_165," line.long 0x378 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_166," line.long 0x37C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_167," line.long 0x380 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_168," line.long 0x384 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_169," line.long 0x388 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_170," line.long 0x38C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_171," line.long 0x390 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_172," line.long 0x394 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_173," line.long 0x398 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_174," line.long 0x39C "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_175," line.long 0x3A0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_176," line.long 0x3A4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_177," line.long 0x3A8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_178," line.long 0x3AC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_179," line.long 0x3B0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_180," line.long 0x3B4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_181," line.long 0x3B8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_182," line.long 0x3BC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_183," line.long 0x3C0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_184," line.long 0x3C4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_185," line.long 0x3C8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_186," line.long 0x3CC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_187," line.long 0x3D0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_188," line.long 0x3D4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_189," line.long 0x3D8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_190," line.long 0x3DC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_191," line.long 0x3E0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_192," line.long 0x3E4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_193," line.long 0x3E8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_194," line.long 0x3EC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_195," line.long 0x3F0 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_196," line.long 0x3F4 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_197," line.long 0x3F8 "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_198," line.long 0x3FC "KITE1_PACKET_PROBE_MAIN_PROBE_RESERVED_199," tree.end tree "SUBNOC_HSM_IN_IA_KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506200 group.long 0x0++0x1FF line.long 0x0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x70 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x74 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x78 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x7C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x80 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x84 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0x88 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0x8C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0x90 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0x94 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0x98 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0x9C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xA0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xA4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xA8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xAC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xB0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xB4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xB8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xBC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xC0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xC4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xC8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xCC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xD0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xD4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xD8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xDC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xE0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xE4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0xE8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0xEC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0xF0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0xF4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0xF8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0xFC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x100 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x104 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x108 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x10C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x110 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x114 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x118 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x11C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x120 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x124 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x130 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x134 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x138 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x13C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x140 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x144 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x148 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x14C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x150 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x154 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x158 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x15C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x160 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x164 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x168 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x16C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x170 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x174 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x178 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x17C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x180 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x184 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x188 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x18C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x190 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x194 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x198 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x19C "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1A0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1A4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1A8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1AC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1B0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1B4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1B8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1BC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1C0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1C4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1C8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1CC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1D0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1D4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1D8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1DC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1E0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1E4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," line.long 0x1E8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_107," line.long 0x1EC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_108," line.long 0x1F0 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_109," line.long 0x1F4 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_110," line.long 0x1F8 "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_111," line.long 0x1FC "KITE1_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_112," tree.end tree "SUBNOC_HSM_IN_IA_KITE1_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B502C00 group.long 0x0++0x3FF line.long 0x0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "SUBNOC_HSM_IN_IA_KITE2_PACKET_PROBE_MAIN_PROBE" base ad:0x7B503000 group.long 0x0++0x3FF line.long 0x0 "KITE2_PACKET_PROBE_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE2_PACKET_PROBE_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE2_PACKET_PROBE_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE2_PACKET_PROBE_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE2_PACKET_PROBE_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE2_PACKET_PROBE_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE2_PACKET_PROBE_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE2_PACKET_PROBE_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE2_PACKET_PROBE_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE2_PACKET_PROBE_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE2_PACKET_PROBE_MAIN_PROBE_RESERVED_211," tree.end tree "SUBNOC_HSM_IN_IA_KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506800 group.long 0x0++0x7F line.long 0x0 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x40 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x44 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x48 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x4C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x50 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x54 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x58 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x5C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x60 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x64 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x68 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x6C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x6C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x70 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x70 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x74 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x74 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x78 "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x78 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x7C "KITE2_PACKET_PROBE_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," tree.end tree "SUBNOC_HSM_IN_IA_KITE2_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B503400 group.long 0x0++0x3FF line.long 0x0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "KITE2_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "SUBNOC_HSM_IN_IA_NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000400 group.long 0x0++0x7F line.long 0x0 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "NOC_KITE0_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_HSM_IN_IA_NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000D80 group.long 0x0++0x7F line.long 0x0 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "NOC_KITE0_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_HSM_IN_IA_NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000480 group.long 0x0++0x7F line.long 0x0 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "NOC_KITE1_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_HSM_IN_IA_NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000E00 group.long 0x0++0x7F line.long 0x0 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "NOC_KITE1_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_HSM_IN_IA_NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000500 group.long 0x0++0x7F line.long 0x0 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "NOC_KITE2_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_HSM_IN_IA_NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000E80 group.long 0x0++0x7F line.long 0x0 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "NOC_KITE2_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_HSM_IN_IA_OBSERVER_HSM_MAIN_ERRORLOGGER_0" base ad:0x7B506A80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_HSM_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "SUBNOC_HSM_IN_IA_OBSERVER_KITE0_MAIN_ERRORLOGGER_0" base ad:0x7B506B00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_KITE0_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "SUBNOC_HSM_IN_IA_OBSERVER_KITE1_MAIN_ERRORLOGGER_0" base ad:0x7B506B80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_KITE1_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "SUBNOC_HSM_IN_IA_OBSERVER_KITE2_MAIN_ERRORLOGGER_0" base ad:0x7B506C00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_KITE2_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "SUBNOC_HSM_IN_IA_OBSERVER_MAIN0_MAIN_ATBENDPOINT" base ad:0x7B506900 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ATBID," hexmask.long.byte 0x8 0.--6. 1. "ATBID,ATB AtId" line.long 0xC "OBSERVER_MAIN0_MAIN_ATBENDPOINT_ATBEN," bitfld.long 0xC 0. "ATBEN,ATB Unit Enable" "0,1" line.long 0x10 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_SYNCPERIOD," hexmask.long.byte 0x10 0.--4. 1. "SYNCPERIOD,ATB Synchro Period" line.long 0x14 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_00," line.long 0x18 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_01," line.long 0x1C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_02," line.long 0x20 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_03," line.long 0x24 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_04," line.long 0x28 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_05," line.long 0x2C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_06," line.long 0x30 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_07," line.long 0x34 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_08," line.long 0x38 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_09," line.long 0x3C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_10," line.long 0x40 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_11," line.long 0x44 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_12," line.long 0x48 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_13," line.long 0x4C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_14," line.long 0x50 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_15," line.long 0x54 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_16," line.long 0x58 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_17," line.long 0x5C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_18," line.long 0x60 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_19," line.long 0x64 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_20," line.long 0x68 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_21," line.long 0x6C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_22," line.long 0x70 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_23," line.long 0x74 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_24," line.long 0x78 "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_25," line.long 0x7C "OBSERVER_MAIN0_MAIN_ATBENDPOINT_RESERVED_26," tree.end tree "SUBNOC_HSM_IN_IA_OBSERVER_MAIN0_MAIN_ERRORLOGGER_0" base ad:0x7B506C80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_MAIN0_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "SUBNOC_HSM_IN_IA_OBSERVER_MAIN1_MAIN_ATBENDPOINT" base ad:0x7B506980 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ATBID," hexmask.long.byte 0x8 0.--6. 1. "ATBID,ATB AtId" line.long 0xC "OBSERVER_MAIN1_MAIN_ATBENDPOINT_ATBEN," bitfld.long 0xC 0. "ATBEN,ATB Unit Enable" "0,1" line.long 0x10 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_SYNCPERIOD," hexmask.long.byte 0x10 0.--4. 1. "SYNCPERIOD,ATB Synchro Period" line.long 0x14 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_00," line.long 0x18 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_01," line.long 0x1C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_02," line.long 0x20 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_03," line.long 0x24 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_04," line.long 0x28 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_05," line.long 0x2C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_06," line.long 0x30 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_07," line.long 0x34 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_08," line.long 0x38 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_09," line.long 0x3C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_10," line.long 0x40 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_11," line.long 0x44 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_12," line.long 0x48 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_13," line.long 0x4C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_14," line.long 0x50 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_15," line.long 0x54 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_16," line.long 0x58 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_17," line.long 0x5C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_18," line.long 0x60 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_19," line.long 0x64 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_20," line.long 0x68 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_21," line.long 0x6C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_22," line.long 0x70 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_23," line.long 0x74 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_24," line.long 0x78 "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_25," line.long 0x7C "OBSERVER_MAIN1_MAIN_ATBENDPOINT_RESERVED_26," tree.end tree "SUBNOC_HSM_IN_IA_OBSERVER_MAIN1_MAIN_ERRORLOGGER_0" base ad:0x7B506D00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_MAIN1_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "SUBNOC_HSM_IN_IA_OBSERVER_PCIE_MAIN_ATBENDPOINT" base ad:0x7B506A00 group.long 0x0++0x7F line.long 0x0 "OBSERVER_PCIE_MAIN_ATBENDPOINT_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_PCIE_MAIN_ATBENDPOINT_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_PCIE_MAIN_ATBENDPOINT_ATBID," hexmask.long.byte 0x8 0.--6. 1. "ATBID,ATB AtId" line.long 0xC "OBSERVER_PCIE_MAIN_ATBENDPOINT_ATBEN," bitfld.long 0xC 0. "ATBEN,ATB Unit Enable" "0,1" line.long 0x10 "OBSERVER_PCIE_MAIN_ATBENDPOINT_SYNCPERIOD," hexmask.long.byte 0x10 0.--4. 1. "SYNCPERIOD,ATB Synchro Period" line.long 0x14 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_00," line.long 0x18 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_01," line.long 0x1C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_02," line.long 0x20 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_03," line.long 0x24 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_04," line.long 0x28 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_05," line.long 0x2C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_06," line.long 0x30 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_07," line.long 0x34 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_08," line.long 0x38 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_09," line.long 0x3C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_10," line.long 0x40 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_11," line.long 0x44 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_12," line.long 0x48 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_13," line.long 0x4C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_14," line.long 0x50 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_15," line.long 0x54 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_16," line.long 0x58 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_17," line.long 0x5C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_18," line.long 0x60 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_19," line.long 0x64 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_20," line.long 0x68 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_21," line.long 0x6C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_22," line.long 0x70 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_23," line.long 0x74 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_24," line.long 0x78 "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_25," line.long 0x7C "OBSERVER_PCIE_MAIN_ATBENDPOINT_RESERVED_26," tree.end tree "SUBNOC_HSM_IN_IA_OBSERVER_PCIE_MAIN_ERRORLOGGER_0" base ad:0x7B506D80 group.long 0x0++0x7F line.long 0x0 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_FAULTEN," bitfld.long 0x8 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1" line.long 0xC "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRVLD," bitfld.long 0xC 0. "ERRVLD,1 indicates an error has been logged" "0,1" line.long 0x10 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1" line.long 0x14 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG0," bitfld.long 0x14 31. "FORMAT,NTTP transport protocol version" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Len1" bitfld.long 0x14 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 1.--4. 1. "OPC,Opc" bitfld.long 0x14 0. "LOCK,Lock" "0,1" line.long 0x18 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG1," hexmask.long.tbyte 0x18 0.--19. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error" line.long 0x1C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_00," line.long 0x20 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG3," hexmask.long 0x20 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error" line.long 0x24 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_01," line.long 0x28 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG5," hexmask.long 0x28 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error" line.long 0x2C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_ERRLOG6," hexmask.long.word 0x2C 0.--13. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error" line.long 0x30 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_02," line.long 0x34 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_03," line.long 0x38 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_04," line.long 0x3C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_05," line.long 0x40 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_06," line.long 0x44 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_07," line.long 0x48 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_08," line.long 0x4C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_STALLEN," bitfld.long 0x4C 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1" line.long 0x50 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_09," line.long 0x54 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_10," line.long 0x58 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_11," line.long 0x5C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_12," line.long 0x60 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_13," line.long 0x64 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_14," line.long 0x68 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_15," line.long 0x6C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_16," line.long 0x70 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_17," line.long 0x74 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_18," line.long 0x78 "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_19," line.long 0x7C "OBSERVER_PCIE_MAIN_ERRORLOGGER_0_RESERVED_20," tree.end tree "SUBNOC_HSM_IN_IA_PCIE_0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000580 group.long 0x0++0x7F line.long 0x0 "PCIE_0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "PCIE_0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "PCIE_0_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "PCIE_0_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "PCIE_0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "PCIE_0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_HSM_IN_IA_PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000F00 group.long 0x0++0x7F line.long 0x0 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "PCIE_0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_HSM_IN_IA_PCIE_1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000600 group.long 0x0++0x7F line.long 0x0 "PCIE_1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "PCIE_1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "PCIE_1_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "PCIE_1_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "PCIE_1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "PCIE_1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_HSM_IN_IA_PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B000F80 group.long 0x0++0x7F line.long 0x0 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "PCIE_1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_HSM_IN_IA_PCIE_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B503800 group.long 0x0++0x3FF line.long 0x0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x234 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x238 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x23C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x240 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x244 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x248 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x24C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x250 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x254 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x258 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x25C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x260 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x264 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x268 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x26C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x270 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x274 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x278 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x27C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x280 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x284 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x288 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x28C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x290 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x294 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x298 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x29C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2A0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2A4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2A8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2AC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2B0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2B4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2B8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2BC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2C0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2C4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2C8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2CC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x2D0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x2D4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x2D8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x2DC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x2E0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x2E4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x2E8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x2EC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x2F0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x2F4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x2F8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x2FC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x300 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x304 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x308 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x30C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x310 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x314 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x318 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x31C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x320 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x324 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x328 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x32C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x330 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x334 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x338 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x33C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x340 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x344 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x348 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x34C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x350 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x354 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x358 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x35C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x360 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x364 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x368 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x36C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x370 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x374 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x378 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x37C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x380 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x384 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x388 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x38C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x390 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x394 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x398 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x39C "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3A0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3A4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3A8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3AC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3B0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3B4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3B8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3BC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3C0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3C4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3C8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3CC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," line.long 0x3D0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_208," line.long 0x3D4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_209," line.long 0x3D8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_210," line.long 0x3DC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_211," line.long 0x3E0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_212," line.long 0x3E4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_213," line.long 0x3E8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_214," line.long 0x3EC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_215," line.long 0x3F0 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_216," line.long 0x3F4 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_217," line.long 0x3F8 "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_218," line.long 0x3FC "PCIE_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_219," tree.end tree "SUBNOC_HSM_IN_IA_PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506880 group.long 0x0++0x7F line.long 0x0 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x38 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x3C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x40 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x44 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x48 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x6C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x70 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x70 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x74 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x74 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x78 "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x78 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x7C "PCIE_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," tree.end tree "SUBNOC_HSM_IN_IA_PCIE_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B503C00 group.long 0x0++0x3FF line.long 0x0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "PCIE_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree "SUBNOC_HSM_IN_IA_POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER" base ad:0x7B506E00 group.long 0x0++0x7F line.long 0x0 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT0," hexmask.long 0x8 0.--31. 1. "MISSIONFAULT0,MissionFault0 register" line.long 0xC "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT1," hexmask.long 0xC 0.--31. 1. "MISSIONFAULT1,MissionFault1 register" line.long 0x10 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT2," hexmask.long 0x10 0.--31. 1. "MISSIONFAULT2,MissionFault2 register" line.long 0x14 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT3," hexmask.long 0x14 0.--31. 1. "MISSIONFAULT3,MissionFault3 register" line.long 0x18 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT0," hexmask.long 0x18 0.--31. 1. "LATENTFAULT0,LatentFault0 register" line.long 0x1C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT1," hexmask.long 0x1C 0.--31. 1. "LATENTFAULT1,LatentFault1 register" line.long 0x20 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT2," hexmask.long 0x20 0.--31. 1. "LATENTFAULT2,LatentFault2 register" line.long 0x24 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT3," hexmask.long 0x24 0.--31. 1. "LATENTFAULT3,LatentFault3 register" line.long 0x28 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_FAULTS," bitfld.long 0x28 1. "MISSIONFAULT,Mission Fault" "0,1" bitfld.long 0x28 0. "LATENTFAULT,Latent Fault" "0,1" line.long 0x2C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_INTEN," bitfld.long 0x2C 1. "MISSIONFAULTEN,MissionFault Interrupt enable" "0,1" bitfld.long 0x2C 0. "BISTDONEEN,BistDone Interrupt enable" "0,1" line.long 0x30 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_INTCLR," bitfld.long 0x30 1. "MISSIONFAULTCLR,Clear Mission Fault" "0,1" bitfld.long 0x30 0. "LATENTFAULTCLR,Clear Latent Fault" "0,1" line.long 0x34 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTCTL," bitfld.long 0x34 1. "BISTDONECLR,Clear BistDone" "0,1" bitfld.long 0x34 0. "BISTSTART,Start Bist sequence" "0,1" line.long 0x38 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTDONE," bitfld.long 0x38 1. "MISSIONMODE,Mission Mode Status" "0,1" bitfld.long 0x38 0. "BISTDONE,BistDone Status" "0,1" line.long 0x3C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO1," hexmask.long.word 0x3C 0.--15. 1. "BISTTO1,BistTimeOut register" line.long 0x40 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO2," hexmask.long.byte 0x40 0.--7. 1. "BISTTO2,BistTimeOut register" line.long 0x44 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_00," line.long 0x48 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_01," line.long 0x4C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_02," line.long 0x50 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_03," line.long 0x54 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_04," line.long 0x58 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_05," line.long 0x5C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_06," line.long 0x60 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_07," line.long 0x64 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_08," line.long 0x68 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_09," line.long 0x6C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_10," line.long 0x70 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_11," line.long 0x74 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_12," line.long 0x78 "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_13," line.long 0x7C "POWER_PD1_1_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_14," tree.end tree "SUBNOC_HSM_IN_IA_POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER" base ad:0x7B506E80 group.long 0x0++0x7F line.long 0x0 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT0," hexmask.long 0x8 0.--31. 1. "MISSIONFAULT0,MissionFault0 register" line.long 0xC "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT1," hexmask.long 0xC 0.--31. 1. "MISSIONFAULT1,MissionFault1 register" line.long 0x10 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT2," hexmask.long 0x10 0.--31. 1. "MISSIONFAULT2,MissionFault2 register" line.long 0x14 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_MISSIONFAULT3," hexmask.long 0x14 0.--31. 1. "MISSIONFAULT3,MissionFault3 register" line.long 0x18 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT0," hexmask.long 0x18 0.--31. 1. "LATENTFAULT0,LatentFault0 register" line.long 0x1C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT1," hexmask.long 0x1C 0.--31. 1. "LATENTFAULT1,LatentFault1 register" line.long 0x20 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT2," hexmask.long 0x20 0.--31. 1. "LATENTFAULT2,LatentFault2 register" line.long 0x24 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_LATENTFAULT3," hexmask.long 0x24 0.--31. 1. "LATENTFAULT3,LatentFault3 register" line.long 0x28 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_FAULTS," bitfld.long 0x28 1. "MISSIONFAULT,Mission Fault" "0,1" bitfld.long 0x28 0. "LATENTFAULT,Latent Fault" "0,1" line.long 0x2C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_INTEN," bitfld.long 0x2C 1. "MISSIONFAULTEN,MissionFault Interrupt enable" "0,1" bitfld.long 0x2C 0. "BISTDONEEN,BistDone Interrupt enable" "0,1" line.long 0x30 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_INTCLR," bitfld.long 0x30 1. "MISSIONFAULTCLR,Clear Mission Fault" "0,1" bitfld.long 0x30 0. "LATENTFAULTCLR,Clear Latent Fault" "0,1" line.long 0x34 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTCTL," bitfld.long 0x34 1. "BISTDONECLR,Clear BistDone" "0,1" bitfld.long 0x34 0. "BISTSTART,Start Bist sequence" "0,1" line.long 0x38 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTDONE," bitfld.long 0x38 1. "MISSIONMODE,Mission Mode Status" "0,1" bitfld.long 0x38 0. "BISTDONE,BistDone Status" "0,1" line.long 0x3C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO1," hexmask.long.word 0x3C 0.--15. 1. "BISTTO1,BistTimeOut register" line.long 0x40 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_BISTTO2," hexmask.long.byte 0x40 0.--7. 1. "BISTTO2,BistTimeOut register" line.long 0x44 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_00," line.long 0x48 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_01," line.long 0x4C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_02," line.long 0x50 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_03," line.long 0x54 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_04," line.long 0x58 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_05," line.long 0x5C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_06," line.long 0x60 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_07," line.long 0x64 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_08," line.long 0x68 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_09," line.long 0x6C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_10," line.long 0x70 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_11," line.long 0x74 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_12," line.long 0x78 "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_13," line.long 0x7C "POWER_PD1_2_MAIN_RESILIENCEFAULTCONTROLLER_RESERVED_14," tree.end tree "SUBNOC_HSM_IN_IA_SDMMC_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000680 group.long 0x0++0x7F line.long 0x0 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "SDMMC_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_HSM_IN_IA_SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001000 group.long 0x0++0x7F line.long 0x0 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "SDMMC_IN_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_HSM_IN_IA_SDMMC_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B504000 group.long 0x0++0x3FF line.long 0x0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x14 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x34 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x3C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x4C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x50 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x54 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x58 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x5C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x60 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x64 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x68 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x6C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x70 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x74 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x78 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x7C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x80 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x90 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x98 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0x9C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xB8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xBC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xC8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xCC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xD8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xDC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xE8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xEC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xF8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0xFC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x100 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x104 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x108 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x10C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x110 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x114 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x118 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x11C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x120 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x124 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x128 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x12C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x130 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x134 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x138 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x13C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x140 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x144 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x148 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x14C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x150 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x154 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x158 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x15C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x160 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x164 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x168 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x16C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x170 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x174 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x178 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x17C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x180 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x184 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x188 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x18C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x190 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x194 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x198 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x19C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1A8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1AC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1B8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1BC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1C8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1CC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1D8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1DC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1E8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1EC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1F8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x1FC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x200 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x204 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x214 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x224 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x234 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x244 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x254 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x264 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_SRC," bitfld.long 0x264 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x264 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x268 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_ALARMMODE," bitfld.long 0x268 0.--1. "COUNTERS_6_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x26C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_6_VAL," hexmask.long.word 0x26C 0.--13. 1. "COUNTERS_6_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x270 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x274 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_SRC," bitfld.long 0x274 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x274 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x278 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_ALARMMODE," bitfld.long 0x278 0.--1. "COUNTERS_7_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x27C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_7_VAL," hexmask.long.word 0x27C 0.--13. 1. "COUNTERS_7_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x280 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x284 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x288 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x28C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x290 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x294 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x298 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x29C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2A8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2AC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2B8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2BC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2C8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2CC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2D8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2DC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2E8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2EC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2F8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x2FC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x300 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x304 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x308 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x30C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x310 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x314 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x318 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x31C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x320 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x324 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x328 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x32C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x330 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x334 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x338 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x33C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x340 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x344 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x348 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x34C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x350 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x354 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x358 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x35C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x360 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x364 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x368 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x36C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x370 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x374 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x378 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x37C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x380 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x384 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x388 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x38C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x390 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x394 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x398 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x39C "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3A8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3AC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3B8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3BC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3C8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3CC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3D8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3DC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3E8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3EC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F0 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F4 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3F8 "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," line.long 0x3FC "SDMMC_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_208," tree.end tree "SUBNOC_HSM_IN_IA_SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506400 group.long 0x0++0x1FF line.long 0x0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1" line.long 0x10 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x14 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x18 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x1C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x20 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x24 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x28 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x2C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_5," hexmask.long.byte 0x40 0.--3. 1. "THRESHOLDS_0_5,Register Thresholds_i_j contains the threshold index '5' that allows computation of threshold values." line.long 0x44 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_6," hexmask.long.byte 0x44 0.--3. 1. "THRESHOLDS_0_6,Register Thresholds_i_j contains the threshold index '6' that allows computation of threshold values." line.long 0x48 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x4C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x50 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x54 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x58 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x5C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x60 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x64 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x68 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x6C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x70 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x74 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x78 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x7C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x80 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x84 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0x88 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0x8C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0x90 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0x94 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0x98 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0x9C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xA0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xA4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xA8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xAC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xB0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xB4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xB8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xBC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xC0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xC4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xC8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xCC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xD0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xD4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xD8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xDC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xE0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xE4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0xE8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0xEC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0xF0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0xF4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0xF8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0xFC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x100 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x104 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x108 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x10C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x110 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x114 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x118 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x11C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1" line.long 0x120 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1" line.long 0x124 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x130 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x134 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x138 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x13C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x140 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x144 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x148 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x14C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x150 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x154 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x158 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x15C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x160 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x164 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x168 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x16C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x170 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x174 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x178 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x17C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x180 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x184 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x188 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x18C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x190 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x194 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x198 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x19C "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1A0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1A4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1A8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1AC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1B0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1B4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1B8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1BC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1C0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1C4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1C8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1CC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1D0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1D4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1D8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1DC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1E0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1E4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," line.long 0x1E8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_107," line.long 0x1EC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_108," line.long 0x1F0 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_109," line.long 0x1F4 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_110," line.long 0x1F8 "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_111," line.long 0x1FC "SDMMC_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_112," tree.end tree "SUBNOC_HSM_IN_IA_SDMMC_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B504400 group.long 0x0++0x3FF line.long 0x0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x14 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x34 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x3C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x4C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x50 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x54 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x58 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x5C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x60 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x64 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x68 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x6C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x70 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x74 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x78 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x7C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x80 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x90 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x98 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0x9C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xB8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xBC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xC8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xCC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xD8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xDC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xE8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xEC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xF8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0xFC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x100 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x104 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x108 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x10C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x110 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x114 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x118 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x11C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x120 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x124 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x128 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x12C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x130 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x134 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x138 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x13C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x140 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x144 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x148 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x14C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x150 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x154 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x158 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x15C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x160 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x164 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x168 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x16C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x170 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x174 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x178 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x17C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x180 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x184 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x188 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x18C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x190 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x194 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x198 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x19C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1A8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1AC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1B8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1BC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1C8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1CC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1D8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1DC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1E8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1EC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1F8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x1FC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x200 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x204 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x214 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x218 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x21C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x220 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x224 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x228 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x22C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x230 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x234 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x238 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x23C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x240 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x244 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x248 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x24C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x250 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x254 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x258 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x25C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x260 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x264 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x268 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x26C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x270 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x274 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x278 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x27C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x280 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x284 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x288 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x28C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x290 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x294 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x298 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x29C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2A4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2A8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2AC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2B4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2B8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2BC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2C4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2C8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2CC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2D4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2D8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2DC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2E4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2E8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2EC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2F4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x2F8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x2FC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x300 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x304 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x308 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x30C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x310 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x314 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x318 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x31C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x320 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x324 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x328 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x32C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x330 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x334 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x338 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x33C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x340 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x344 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x348 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x34C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x350 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x354 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x358 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x35C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x360 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x364 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x368 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x36C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x370 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x374 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x378 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x37C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x380 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x384 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x388 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x38C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x390 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x394 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x398 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x39C "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3A4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3A8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3AC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3B4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3B8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3BC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3C4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3C8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3CC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3D4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3D8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3DC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3E4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3E8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3EC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F0 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3F4 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," line.long 0x3F8 "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_228," line.long 0x3FC "SDMMC_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_229," tree.end tree "SUBNOC_HSM_IN_IA_SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000700 group.long 0x0++0x7F line.long 0x0 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "SUBNOC_DME_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_HSM_IN_IA_SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000780 group.long 0x0++0x7F line.long 0x0 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "SUBNOC_DSP_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_HSM_IN_IA_SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000800 group.long 0x0++0x7F line.long 0x0 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x14 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x18 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x20 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x24 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x28 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x2C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x30 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x34 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x38 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x3C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x40 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x44 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x48 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x4C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x50 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x54 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x58 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x5C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x60 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x64 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x68 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x6C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x70 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x74 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_24," line.long 0x78 "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_25," line.long 0x7C "SUBNOC_HSM_IN_IA_I_MAIN_QOSGENERATOR_RESERVED_26," tree.end tree "SUBNOC_HSM_IN_IA_SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B504800 group.long 0x0++0x3FF line.long 0x0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "SYSRAM0_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "SUBNOC_HSM_IN_IA_SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE" base ad:0x7B504C00 group.long 0x0++0x3FF line.long 0x0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_00," line.long 0x34 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_01," line.long 0x3C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_02," line.long 0x4C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_03," line.long 0x50 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_04," line.long 0x54 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_05," line.long 0x58 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_06," line.long 0x5C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_07," line.long 0x60 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_08," line.long 0x64 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_09," line.long 0x68 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_10," line.long 0x6C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_11," line.long 0x70 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_12," line.long 0x74 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_13," line.long 0x78 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_14," line.long 0x7C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_15," line.long 0x80 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_16," line.long 0x90 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_17," line.long 0x98 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_18," line.long 0x9C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_19," line.long 0xB0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_20," line.long 0xB4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_21," line.long 0xB8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_22," line.long 0xBC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_23," line.long 0xC0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_24," line.long 0xC4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_25," line.long 0xC8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_26," line.long 0xCC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_27," line.long 0xD0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_28," line.long 0xD4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_29," line.long 0xD8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_30," line.long 0xDC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_31," line.long 0xE0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_32," line.long 0xE4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_33," line.long 0xE8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_34," line.long 0xEC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_35," line.long 0xF0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_36," line.long 0xF4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_37," line.long 0xF8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_38," line.long 0xFC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_39," line.long 0x100 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_40," line.long 0x104 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_41," line.long 0x108 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_42," line.long 0x10C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_43," line.long 0x110 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_44," line.long 0x114 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_45," line.long 0x118 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_46," line.long 0x11C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_47," line.long 0x120 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_48," line.long 0x124 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_49," line.long 0x128 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_50," line.long 0x12C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_51," line.long 0x130 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_52," line.long 0x134 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_53," line.long 0x138 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_54," line.long 0x13C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_55," line.long 0x140 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_56," line.long 0x144 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_57," line.long 0x148 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_58," line.long 0x14C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_59," line.long 0x150 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_60," line.long 0x154 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_61," line.long 0x158 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_62," line.long 0x15C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_63," line.long 0x160 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_64," line.long 0x164 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_65," line.long 0x168 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_66," line.long 0x16C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_67," line.long 0x170 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_68," line.long 0x174 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_69," line.long 0x178 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_70," line.long 0x17C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_71," line.long 0x180 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_72," line.long 0x184 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_73," line.long 0x188 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_74," line.long 0x18C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_75," line.long 0x190 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_76," line.long 0x194 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_77," line.long 0x198 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_78," line.long 0x19C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_82," line.long 0x1AC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_86," line.long 0x1BC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_90," line.long 0x1CC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_94," line.long 0x1DC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_98," line.long 0x1EC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_102," line.long 0x1FC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_103," line.long 0x200 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_104," line.long 0x254 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_105," line.long 0x258 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_106," line.long 0x25C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_107," line.long 0x260 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_108," line.long 0x264 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_109," line.long 0x268 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_110," line.long 0x26C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_111," line.long 0x270 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_112," line.long 0x274 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_113," line.long 0x278 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_114," line.long 0x27C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_115," line.long 0x280 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_116," line.long 0x284 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_117," line.long 0x288 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_118," line.long 0x28C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_119," line.long 0x290 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_120," line.long 0x294 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_121," line.long 0x298 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_122," line.long 0x29C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_123," line.long 0x2A0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_124," line.long 0x2A4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_125," line.long 0x2A8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_126," line.long 0x2AC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_127," line.long 0x2B0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_128," line.long 0x2B4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_129," line.long 0x2B8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_130," line.long 0x2BC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_131," line.long 0x2C0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_132," line.long 0x2C4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_133," line.long 0x2C8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_134," line.long 0x2CC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_135," line.long 0x2D0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_136," line.long 0x2D4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_137," line.long 0x2D8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_138," line.long 0x2DC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_139," line.long 0x2E0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_140," line.long 0x2E4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_141," line.long 0x2E8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_142," line.long 0x2EC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_143," line.long 0x2F0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_144," line.long 0x2F4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_145," line.long 0x2F8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_146," line.long 0x2FC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_147," line.long 0x300 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_148," line.long 0x304 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_149," line.long 0x308 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_150," line.long 0x30C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_151," line.long 0x310 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_152," line.long 0x314 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_153," line.long 0x318 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_154," line.long 0x31C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_155," line.long 0x320 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_156," line.long 0x324 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_157," line.long 0x328 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_158," line.long 0x32C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_159," line.long 0x330 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_160," line.long 0x334 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_161," line.long 0x338 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_162," line.long 0x33C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_163," line.long 0x340 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_164," line.long 0x344 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_165," line.long 0x348 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_166," line.long 0x34C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_167," line.long 0x350 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_168," line.long 0x354 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_169," line.long 0x358 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_170," line.long 0x35C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_171," line.long 0x360 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_172," line.long 0x364 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_173," line.long 0x368 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_174," line.long 0x36C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_175," line.long 0x370 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_176," line.long 0x374 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_177," line.long 0x378 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_178," line.long 0x37C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_179," line.long 0x380 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_180," line.long 0x384 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_181," line.long 0x388 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_182," line.long 0x38C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_183," line.long 0x390 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_184," line.long 0x394 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_185," line.long 0x398 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_186," line.long 0x39C "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_187," line.long 0x3A0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_188," line.long 0x3A4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_189," line.long 0x3A8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_190," line.long 0x3AC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_191," line.long 0x3B0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_192," line.long 0x3B4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_193," line.long 0x3B8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_194," line.long 0x3BC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_195," line.long 0x3C0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_196," line.long 0x3C4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_197," line.long 0x3C8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_198," line.long 0x3CC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_199," line.long 0x3D0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_200," line.long 0x3D4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_201," line.long 0x3D8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_202," line.long 0x3DC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_203," line.long 0x3E0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_204," line.long 0x3E4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_205," line.long 0x3E8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_206," line.long 0x3EC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_207," line.long 0x3F0 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_208," line.long 0x3F4 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_209," line.long 0x3F8 "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_210," line.long 0x3FC "SYSRAM1_PACKET_PROBE_TA_MAIN_PROBE_RESERVED_211," tree.end tree "SUBNOC_HSM_IN_IA_ZIPW0_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000880 group.long 0x0++0x7F line.long 0x0 "ZIPW0_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW0_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW0_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ZIPW0_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ZIPW0_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ZIPW0_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ZIPW0_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ZIPW0_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_HSM_IN_IA_ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001080 group.long 0x0++0x7F line.long 0x0 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ZIPW0_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_HSM_IN_IA_ZIPW1_IA_I_MAIN_QOSGENERATOR" base ad:0x7B000900 group.long 0x0++0x7F line.long 0x0 "ZIPW1_IA_I_MAIN_QOSGENERATOR_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW1_IA_I_MAIN_QOSGENERATOR_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW1_IA_I_MAIN_QOSGENERATOR_PRIORITY," bitfld.long 0x8 31. "MARK,Backward compatibility marker when 0." "0,1" bitfld.long 0x8 8.--10. "P1,In Regulator mode defines the HIGH hurry level. In Fixed/Limiter mode defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "P0,In Regulator mode defines the LOW hurry level. In Fixed/Limiter mode defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7" line.long 0xC "ZIPW1_IA_I_MAIN_QOSGENERATOR_MODE," bitfld.long 0xC 0.--1. "MODE,Functional Mode: 0=Fixed 1=Limiter 2=Bypass 3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator" line.long 0x10 "ZIPW1_IA_I_MAIN_QOSGENERATOR_BANDWIDTH," hexmask.long.word 0x10 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words the desired rate in MBps is divided by frequency in MHz of the NIU and then multiplied by 256." line.long 0x14 "ZIPW1_IA_I_MAIN_QOSGENERATOR_SATURATION," hexmask.long.word 0x14 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter that is the measurement window in 16-byte units. In other words the desired number of bytes divided by 16." line.long 0x18 "ZIPW1_IA_I_MAIN_QOSGENERATOR_EXTCONTROL," bitfld.long 0x18 3. "EXTLIMITEN,When register field ExtLimitEn is set the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted the limiter is disabled: bandwidth is not limited and the counter is stuck to 0. When the bit is.." "0,1" bitfld.long 0x18 2. "INTCLKEN,When set to 1 register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0 and if configuration parameter useExternalReference is set to True an external reference clock at the socket is used.." "0,1" bitfld.long 0x18 1. "EXTTHREN,When register field ExtThrEn is set internal signals Urgency Press and Hurry are driven when input signal ExtThr is low by the value in register Priority field P0. When ExtThr is high they are drven by the value in register Priority field P1." "0,1" bitfld.long 0x18 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency Pressure and Hurry signals: When set to 0 the QoS generator drives the levels. When.." "0,1" line.long 0x1C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_00," line.long 0x20 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_01," line.long 0x24 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_02," line.long 0x28 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_03," line.long 0x2C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_04," line.long 0x30 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_05," line.long 0x34 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_06," line.long 0x38 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_07," line.long 0x3C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_08," line.long 0x40 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_09," line.long 0x44 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_10," line.long 0x48 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_11," line.long 0x4C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_12," line.long 0x50 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_13," line.long 0x54 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_14," line.long 0x58 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_15," line.long 0x5C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_16," line.long 0x60 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_17," line.long 0x64 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_18," line.long 0x68 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_19," line.long 0x6C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_20," line.long 0x70 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_21," line.long 0x74 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_22," line.long 0x78 "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_23," line.long 0x7C "ZIPW1_IA_I_MAIN_QOSGENERATOR_RESERVED_24," tree.end tree "SUBNOC_HSM_IN_IA_ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER" base ad:0x7B001100 group.long 0x0++0x7F line.long 0x0 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_MODE," bitfld.long 0x8 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1" line.long 0xC "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW," hexmask.long 0xC 0.--31. 1. "ADDRBASE_LOW,Address base LSB register." line.long 0x10 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_00," line.long 0x14 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE," hexmask.long.byte 0x14 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr and AddrMask = AddrBase and AddrMask." line.long 0x18 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_01," line.long 0x1C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_02," line.long 0x20 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_OPCODE," bitfld.long 0x20 1. "WREN,When set to 1 selects WR requests." "0,1" bitfld.long 0x20 0. "RDEN,When set to 1 selects RD requests." "0,1" line.long 0x24 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASE," hexmask.long 0x24 0.--31. 1. "USERBASE,This register contains the User base used to filter requests." line.long 0x28 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASK," hexmask.long 0x28 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests." line.long 0x2C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_03," line.long 0x30 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_04," line.long 0x34 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERBASEHIGH," hexmask.long.word 0x34 0.--13. 1. "USERBASEHIGH,This register contains the User base used to filter requests." line.long 0x38 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_USERMASKHIGH," hexmask.long.word 0x38 0.--13. 1. "USERMASKHIGH,This register contains the User mask used to filter requests." line.long 0x3C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_05," line.long 0x40 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_06," line.long 0x44 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_07," line.long 0x48 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_08," line.long 0x4C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_09," line.long 0x50 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_10," line.long 0x54 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_11," line.long 0x58 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_12," line.long 0x5C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_13," line.long 0x60 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_14," line.long 0x64 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_15," line.long 0x68 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_16," line.long 0x6C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_17," line.long 0x70 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_18," line.long 0x74 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_19," line.long 0x78 "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_20," line.long 0x7C "ZIPW1_IA_I_MAIN_TRANSACTIONSTATFILTER_RESERVED_21," tree.end tree "SUBNOC_HSM_IN_IA_ZIPW_PACKET_PROBE_REQ_MAIN_PROBE" base ad:0x7B505000 group.long 0x0++0x3FF line.long 0x0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_00," line.long 0x34 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_01," line.long 0x3C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_02," line.long 0x4C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_03," line.long 0x50 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_04," line.long 0x54 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_05," line.long 0x58 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_06," line.long 0x5C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_07," line.long 0x60 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_08," line.long 0x64 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_09," line.long 0x68 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_10," line.long 0x6C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_11," line.long 0x70 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_12," line.long 0x74 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_13," line.long 0x78 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_14," line.long 0x7C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_15," line.long 0x80 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_16," line.long 0x90 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_17," line.long 0x98 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_18," line.long 0x9C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_22," line.long 0xBC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_26," line.long 0xCC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_30," line.long 0xDC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_34," line.long 0xEC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_38," line.long 0xFC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_39," line.long 0x100 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_40," line.long 0x104 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_41," line.long 0x108 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_42," line.long 0x10C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_43," line.long 0x110 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_44," line.long 0x114 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_45," line.long 0x118 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_46," line.long 0x11C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_47," line.long 0x120 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_48," line.long 0x124 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_49," line.long 0x128 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_50," line.long 0x12C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_51," line.long 0x130 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_52," line.long 0x134 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_53," line.long 0x138 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_54," line.long 0x13C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_55," line.long 0x140 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_56," line.long 0x144 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_57," line.long 0x148 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_58," line.long 0x14C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_59," line.long 0x150 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_60," line.long 0x154 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_61," line.long 0x158 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_62," line.long 0x15C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_63," line.long 0x160 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_64," line.long 0x164 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_65," line.long 0x168 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_66," line.long 0x16C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_67," line.long 0x170 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_68," line.long 0x174 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_69," line.long 0x178 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_70," line.long 0x17C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_71," line.long 0x180 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_72," line.long 0x184 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_73," line.long 0x188 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_74," line.long 0x18C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_75," line.long 0x190 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_76," line.long 0x194 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_77," line.long 0x198 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_78," line.long 0x19C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_103," line.long 0x200 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_PORTSEL," bitfld.long 0x210 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x214 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_SRC," bitfld.long 0x214 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x214 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x218 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_ALARMMODE," bitfld.long 0x218 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x21C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_1_VAL," hexmask.long.word 0x21C 0.--13. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x220 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_PORTSEL," bitfld.long 0x220 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x224 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_SRC," bitfld.long 0x224 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x224 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x228 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_ALARMMODE," bitfld.long 0x228 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x22C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_2_VAL," hexmask.long.word 0x22C 0.--13. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x230 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_PORTSEL," bitfld.long 0x230 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x234 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_SRC," bitfld.long 0x234 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x234 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x238 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_ALARMMODE," bitfld.long 0x238 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x23C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_3_VAL," hexmask.long.word 0x23C 0.--13. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x240 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_PORTSEL," bitfld.long 0x240 0. "COUNTERS_4_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x244 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_SRC," bitfld.long 0x244 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x244 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x248 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_ALARMMODE," bitfld.long 0x248 0.--1. "COUNTERS_4_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x24C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_4_VAL," hexmask.long.word 0x24C 0.--13. 1. "COUNTERS_4_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x250 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_PORTSEL," bitfld.long 0x250 0. "COUNTERS_5_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x254 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_SRC," bitfld.long 0x254 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x254 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x258 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_ALARMMODE," bitfld.long 0x258 0.--1. "COUNTERS_5_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x25C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_COUNTERS_5_VAL," hexmask.long.word 0x25C 0.--13. 1. "COUNTERS_5_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x260 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_104," line.long 0x264 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_105," line.long 0x268 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_106," line.long 0x26C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_107," line.long 0x270 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_108," line.long 0x274 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_109," line.long 0x278 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_110," line.long 0x27C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_111," line.long 0x280 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_112," line.long 0x284 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_113," line.long 0x288 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_114," line.long 0x28C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_115," line.long 0x290 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_116," line.long 0x294 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_117," line.long 0x298 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_118," line.long 0x29C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_119," line.long 0x2A0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_120," line.long 0x2A4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_121," line.long 0x2A8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_122," line.long 0x2AC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_123," line.long 0x2B0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_124," line.long 0x2B4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_125," line.long 0x2B8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_126," line.long 0x2BC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_127," line.long 0x2C0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_128," line.long 0x2C4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_129," line.long 0x2C8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_130," line.long 0x2CC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_131," line.long 0x2D0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_132," line.long 0x2D4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_133," line.long 0x2D8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_134," line.long 0x2DC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_135," line.long 0x2E0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_136," line.long 0x2E4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_137," line.long 0x2E8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_138," line.long 0x2EC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_139," line.long 0x2F0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_140," line.long 0x2F4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_141," line.long 0x2F8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_142," line.long 0x2FC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_143," line.long 0x300 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_144," line.long 0x304 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_145," line.long 0x308 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_146," line.long 0x30C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_147," line.long 0x310 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_148," line.long 0x314 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_149," line.long 0x318 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_150," line.long 0x31C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_151," line.long 0x320 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_152," line.long 0x324 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_153," line.long 0x328 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_154," line.long 0x32C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_155," line.long 0x330 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_156," line.long 0x334 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_157," line.long 0x338 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_158," line.long 0x33C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_159," line.long 0x340 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_160," line.long 0x344 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_161," line.long 0x348 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_162," line.long 0x34C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_163," line.long 0x350 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_164," line.long 0x354 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_165," line.long 0x358 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_166," line.long 0x35C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_167," line.long 0x360 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_168," line.long 0x364 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_169," line.long 0x368 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_170," line.long 0x36C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_171," line.long 0x370 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_172," line.long 0x374 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_173," line.long 0x378 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_174," line.long 0x37C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_175," line.long 0x380 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_176," line.long 0x384 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_177," line.long 0x388 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_178," line.long 0x38C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_179," line.long 0x390 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_180," line.long 0x394 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_181," line.long 0x398 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_182," line.long 0x39C "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_183," line.long 0x3A0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_184," line.long 0x3A4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_185," line.long 0x3A8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_186," line.long 0x3AC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_187," line.long 0x3B0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_188," line.long 0x3B4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_189," line.long 0x3B8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_190," line.long 0x3BC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_191," line.long 0x3C0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_192," line.long 0x3C4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_193," line.long 0x3C8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_194," line.long 0x3CC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_195," line.long 0x3D0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_196," line.long 0x3D4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_197," line.long 0x3D8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_198," line.long 0x3DC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_199," line.long 0x3E0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_200," line.long 0x3E4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_201," line.long 0x3E8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_202," line.long 0x3EC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_203," line.long 0x3F0 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_204," line.long 0x3F4 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_205," line.long 0x3F8 "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_206," line.long 0x3FC "ZIPW_PACKET_PROBE_REQ_MAIN_PROBE_RESERVED_207," tree.end tree "SUBNOC_HSM_IN_IA_ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER" base ad:0x7B506600 group.long 0x0++0x1FF line.long 0x0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_EN," bitfld.long 0x8 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1" line.long 0xC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_MODE," bitfld.long 0xC 0.--1. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay Mode = 1 for Pending)" "0,1,2,3" line.long 0x10 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0," bitfld.long 0x10 0. "OBSERVEDSEL_0,Register ObservedSel_i selects the port to be observed: 0." "0,1" line.long 0x14 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1," bitfld.long 0x14 0. "OBSERVEDSEL_1,Register ObservedSel_i selects the port to be observed: 1." "0,1" line.long 0x18 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_00," line.long 0x1C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_01," line.long 0x20 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0," bitfld.long 0x20 0.--1. "NTENURELINES_0,Register nTenureLine_i indicates the number of transaction probe lines allocated to each observed port: 0." "0,1,2,3" line.long 0x24 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_02," line.long 0x28 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_03," line.long 0x2C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0," hexmask.long.byte 0x2C 0.--3. 1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x30 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1," hexmask.long.byte 0x30 0.--3. 1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x34 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2," hexmask.long.byte 0x34 0.--3. 1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x38 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3," hexmask.long.byte 0x38 0.--3. 1. "THRESHOLDS_0_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x3C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_4," hexmask.long.byte 0x3C 0.--3. 1. "THRESHOLDS_0_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x40 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_04," line.long 0x44 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_05," line.long 0x48 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_06," line.long 0x4C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_07," line.long 0x50 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_08," line.long 0x54 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_09," line.long 0x58 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_10," line.long 0x5C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_11," line.long 0x60 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_12," line.long 0x64 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_13," line.long 0x68 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0," hexmask.long.byte 0x68 0.--3. 1. "THRESHOLDS_1_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." line.long 0x6C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1," hexmask.long.byte 0x6C 0.--3. 1. "THRESHOLDS_1_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." line.long 0x70 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2," hexmask.long.byte 0x70 0.--3. 1. "THRESHOLDS_1_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." line.long 0x74 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3," hexmask.long.byte 0x74 0.--3. 1. "THRESHOLDS_1_3,Register Thresholds_i_j contains the threshold index '3' that allows computation of threshold values." line.long 0x78 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_4," hexmask.long.byte 0x78 0.--3. 1. "THRESHOLDS_1_4,Register Thresholds_i_j contains the threshold index '4' that allows computation of threshold values." line.long 0x7C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_14," line.long 0x80 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_15," line.long 0x84 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_16," line.long 0x88 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_17," line.long 0x8C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_18," line.long 0x90 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_19," line.long 0x94 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_20," line.long 0x98 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_21," line.long 0x9C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_22," line.long 0xA0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_23," line.long 0xA4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_24," line.long 0xA8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_25," line.long 0xAC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_26," line.long 0xB0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_27," line.long 0xB4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_28," line.long 0xB8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_29," line.long 0xBC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_30," line.long 0xC0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_31," line.long 0xC4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_32," line.long 0xC8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_33," line.long 0xCC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_34," line.long 0xD0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_35," line.long 0xD4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_36," line.long 0xD8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_37," line.long 0xDC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_38," line.long 0xE0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_39," line.long 0xE4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_40," line.long 0xE8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_41," line.long 0xEC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_42," line.long 0xF0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_43," line.long 0xF4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_44," line.long 0xF8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_45," line.long 0xFC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_46," line.long 0x100 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_47," line.long 0x104 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_48," line.long 0x108 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_49," line.long 0x10C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_50," line.long 0x110 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_51," line.long 0x114 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_52," line.long 0x118 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_53," line.long 0x11C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS," bitfld.long 0x11C 0.--1. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1,2,3" line.long 0x120 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET," bitfld.long 0x120 0.--1. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1,2,3" line.long 0x124 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE," bitfld.long 0x124 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE) and when register mode is set to PENDING the pending event is generated on each cycle when the counter is greater than.." "0,1" line.long 0x128 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_PRESCALER," hexmask.long.byte 0x128 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0 pre-scaling is disabled. If set to any other supported value 'n' the threshold counter value is divided by (n + 1)." line.long 0x12C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_54," line.long 0x130 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_55," line.long 0x134 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_56," line.long 0x138 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_57," line.long 0x13C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_58," line.long 0x140 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_59," line.long 0x144 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_60," line.long 0x148 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_61," line.long 0x14C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_62," line.long 0x150 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_63," line.long 0x154 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_64," line.long 0x158 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_65," line.long 0x15C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_66," line.long 0x160 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_67," line.long 0x164 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_68," line.long 0x168 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_69," line.long 0x16C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_70," line.long 0x170 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_71," line.long 0x174 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_72," line.long 0x178 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_73," line.long 0x17C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_74," line.long 0x180 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_75," line.long 0x184 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_76," line.long 0x188 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_77," line.long 0x18C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_78," line.long 0x190 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_79," line.long 0x194 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_80," line.long 0x198 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_81," line.long 0x19C "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_82," line.long 0x1A0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_83," line.long 0x1A4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_84," line.long 0x1A8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_85," line.long 0x1AC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_86," line.long 0x1B0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_87," line.long 0x1B4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_88," line.long 0x1B8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_89," line.long 0x1BC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_90," line.long 0x1C0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_91," line.long 0x1C4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_92," line.long 0x1C8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_93," line.long 0x1CC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_94," line.long 0x1D0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_95," line.long 0x1D4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_96," line.long 0x1D8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_97," line.long 0x1DC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_98," line.long 0x1E0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_99," line.long 0x1E4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_100," line.long 0x1E8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_101," line.long 0x1EC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_102," line.long 0x1F0 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_103," line.long 0x1F4 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_104," line.long 0x1F8 "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_105," line.long 0x1FC "ZIPW_PACKET_PROBE_REQ_MAIN_TRANSACTIONSTATPROFILER_RESERVED_106," tree.end tree "SUBNOC_HSM_IN_IA_ZIPW_PACKET_PROBE_RSP_MAIN_PROBE" base ad:0x7B505400 group.long 0x0++0x3FF line.long 0x0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_ID_COREID," hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP." newline hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP." line.long 0x4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_ID_REVISIONID," hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code." newline hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself." line.long 0x8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_MAINCTL," bitfld.long 0x8 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0 filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1 filters are.." "0,1" newline bitfld.long 0x8 6. "INTRUSIVEMODE,When set to 1 register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0 the register enables trace operation in Overflow flow-control mode" "0,1" newline bitfld.long 0x8 5. "STATCONDDUMP,When set register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin StatAlarmMax and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1" newline bitfld.long 0x8 4. "ALARMEN," "0,1" newline bitfld.long 0x8 3. "STATEN,When set to 1 register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0 counters are disabled." "0,1" newline bitfld.long 0x8 2. "PAYLOADEN,Register field PayloadEn when set to 1 enables traces to contain headers and payload. When set ot 0 only headers are reported." "0,1" newline bitfld.long 0x8 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1" newline bitfld.long 0x8 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status independently of filtering mechanisms thus constituting a simple supplementary global filter." "0,1" line.long 0xC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_CFGCTL," bitfld.long 0xC 1. "ACTIVE,Active status of the packet probe." "0,1" newline bitfld.long 0xC 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1" line.long 0x10 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEPORTSEL," bitfld.long 0x10 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1" line.long 0x14 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERLUT," bitfld.long 0x14 0.--1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.." "0,1,2,3" line.long 0x18 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMEN," bitfld.long 0x18 0.--1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3" line.long 0x1C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMSTATUS," bitfld.long 0x1C 0.--1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3" line.long 0x20 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_TRACEALARMCLR," bitfld.long 0x20 0.--1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0 TraceAlarmClr is reserved.NOTE The.." "0,1,2,3" line.long 0x24 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATPERIOD," hexmask.long.byte 0x24 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period within a range of 2 cycles to 2 gigacycles during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.." line.long 0x28 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATGO," bitfld.long 0x28 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode that is when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1" line.long 0x2C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMIN," hexmask.long 0x2C 0.--27. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x30 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_00," line.long 0x34 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMMAX," hexmask.long 0x34 0.--27. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .." line.long 0x38 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_01," line.long 0x3C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMSTATUS," bitfld.long 0x3C 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1" line.long 0x40 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMCLR," bitfld.long 0x40 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1" line.long 0x44 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_STATALARMEN," bitfld.long 0x44 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1" line.long 0x48 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_02," line.long 0x4C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_03," line.long 0x50 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_04," line.long 0x54 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_05," line.long 0x58 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_06," line.long 0x5C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_07," line.long 0x60 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_08," line.long 0x64 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_09," line.long 0x68 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_10," line.long 0x6C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_11," line.long 0x70 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_12," line.long 0x74 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_13," line.long 0x78 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_14," line.long 0x7C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_15," line.long 0x80 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDBASE," hexmask.long.tbyte 0x80 0.--19. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets." line.long 0x84 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ROUTEIDMASK," hexmask.long.tbyte 0x84 0.--19. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId and RouteIdMask = RouteIdBase and RouteIdMask." line.long 0x88 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW," hexmask.long 0x88 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register." line.long 0x8C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_16," line.long 0x90 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_WINDOWSIZE," hexmask.long.byte 0x90 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize packet.Len) - 1). A packet is a candidate when packet.Addr and Mask = AddrBase and Mask. This.." line.long 0x94 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_17," line.long 0x98 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_18," line.long 0x9C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_OPCODE," bitfld.long 0x9C 3. "URGEN,Selects URG packets (urgency)." "0,1" newline bitfld.long 0x9C 2. "LOCKEN,Selects RDX-WR RDL WRC and Linked sequence." "0,1" newline bitfld.long 0x9C 1. "WREN,Selects WR packets." "0,1" newline bitfld.long 0x9C 0. "RDEN,Selects RD packets." "0,1" line.long 0xA0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_STATUS," bitfld.long 0xA0 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1" newline bitfld.long 0xA0 0. "REQEN,Selects REQ status packets." "0,1" line.long 0xA4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_LENGTH," hexmask.long.byte 0xA4 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length." line.long 0xA8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_FILTERS_0_URGENCY," bitfld.long 0xA8 0.--2. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3,4,5,6,7" line.long 0xAC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_19," line.long 0xB0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_20," line.long 0xB4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_21," line.long 0xB8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_22," line.long 0xBC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_23," line.long 0xC0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_24," line.long 0xC4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_25," line.long 0xC8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_26," line.long 0xCC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_27," line.long 0xD0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_28," line.long 0xD4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_29," line.long 0xD8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_30," line.long 0xDC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_31," line.long 0xE0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_32," line.long 0xE4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_33," line.long 0xE8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_34," line.long 0xEC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_35," line.long 0xF0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_36," line.long 0xF4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_37," line.long 0xF8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_38," line.long 0xFC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_39," line.long 0x100 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_40," line.long 0x104 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_41," line.long 0x108 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_42," line.long 0x10C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_43," line.long 0x110 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_44," line.long 0x114 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_45," line.long 0x118 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_46," line.long 0x11C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_47," line.long 0x120 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_48," line.long 0x124 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_49," line.long 0x128 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_50," line.long 0x12C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_51," line.long 0x130 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_52," line.long 0x134 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_53," line.long 0x138 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_54," line.long 0x13C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_55," line.long 0x140 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_56," line.long 0x144 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_57," line.long 0x148 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_58," line.long 0x14C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_59," line.long 0x150 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_60," line.long 0x154 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_61," line.long 0x158 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_62," line.long 0x15C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_63," line.long 0x160 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_64," line.long 0x164 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_65," line.long 0x168 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_66," line.long 0x16C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_67," line.long 0x170 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_68," line.long 0x174 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_69," line.long 0x178 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_70," line.long 0x17C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_71," line.long 0x180 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_72," line.long 0x184 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_73," line.long 0x188 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_74," line.long 0x18C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_75," line.long 0x190 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_76," line.long 0x194 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_77," line.long 0x198 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_78," line.long 0x19C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_79," line.long 0x1A0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_80," line.long 0x1A4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_81," line.long 0x1A8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_82," line.long 0x1AC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_83," line.long 0x1B0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_84," line.long 0x1B4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_85," line.long 0x1B8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_86," line.long 0x1BC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_87," line.long 0x1C0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_88," line.long 0x1C4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_89," line.long 0x1C8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_90," line.long 0x1CC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_91," line.long 0x1D0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_92," line.long 0x1D4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_93," line.long 0x1D8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_94," line.long 0x1DC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_95," line.long 0x1E0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_96," line.long 0x1E4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_97," line.long 0x1E8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_98," line.long 0x1EC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_99," line.long 0x1F0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_100," line.long 0x1F4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_101," line.long 0x1F8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_102," line.long 0x1FC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_103," line.long 0x200 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_PORTSEL," bitfld.long 0x200 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1" line.long 0x204 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_SRC," bitfld.long 0x204 5. "EXTEVENT,When greater than 0 the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1" newline hexmask.long.byte 0x204 0.--4. 1. "INTEVENT,Internal packet event" line.long 0x208 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_ALARMMODE," bitfld.long 0x208 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.." line.long 0x20C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_COUNTERS_0_VAL," hexmask.long.word 0x20C 0.--13. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output or when statisticscollection is suspended subsequent to triggers or signal statSuspend." line.long 0x210 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_104," line.long 0x214 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_105," line.long 0x218 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_106," line.long 0x21C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_107," line.long 0x220 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_108," line.long 0x224 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_109," line.long 0x228 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_110," line.long 0x22C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_111," line.long 0x230 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_112," line.long 0x234 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_113," line.long 0x238 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_114," line.long 0x23C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_115," line.long 0x240 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_116," line.long 0x244 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_117," line.long 0x248 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_118," line.long 0x24C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_119," line.long 0x250 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_120," line.long 0x254 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_121," line.long 0x258 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_122," line.long 0x25C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_123," line.long 0x260 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_124," line.long 0x264 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_125," line.long 0x268 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_126," line.long 0x26C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_127," line.long 0x270 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_128," line.long 0x274 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_129," line.long 0x278 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_130," line.long 0x27C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_131," line.long 0x280 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_132," line.long 0x284 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_133," line.long 0x288 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_134," line.long 0x28C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_135," line.long 0x290 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_136," line.long 0x294 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_137," line.long 0x298 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_138," line.long 0x29C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_139," line.long 0x2A0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_140," line.long 0x2A4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_141," line.long 0x2A8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_142," line.long 0x2AC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_143," line.long 0x2B0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_144," line.long 0x2B4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_145," line.long 0x2B8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_146," line.long 0x2BC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_147," line.long 0x2C0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_148," line.long 0x2C4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_149," line.long 0x2C8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_150," line.long 0x2CC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_151," line.long 0x2D0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_152," line.long 0x2D4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_153," line.long 0x2D8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_154," line.long 0x2DC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_155," line.long 0x2E0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_156," line.long 0x2E4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_157," line.long 0x2E8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_158," line.long 0x2EC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_159," line.long 0x2F0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_160," line.long 0x2F4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_161," line.long 0x2F8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_162," line.long 0x2FC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_163," line.long 0x300 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_164," line.long 0x304 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_165," line.long 0x308 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_166," line.long 0x30C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_167," line.long 0x310 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_168," line.long 0x314 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_169," line.long 0x318 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_170," line.long 0x31C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_171," line.long 0x320 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_172," line.long 0x324 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_173," line.long 0x328 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_174," line.long 0x32C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_175," line.long 0x330 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_176," line.long 0x334 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_177," line.long 0x338 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_178," line.long 0x33C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_179," line.long 0x340 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_180," line.long 0x344 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_181," line.long 0x348 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_182," line.long 0x34C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_183," line.long 0x350 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_184," line.long 0x354 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_185," line.long 0x358 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_186," line.long 0x35C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_187," line.long 0x360 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_188," line.long 0x364 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_189," line.long 0x368 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_190," line.long 0x36C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_191," line.long 0x370 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_192," line.long 0x374 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_193," line.long 0x378 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_194," line.long 0x37C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_195," line.long 0x380 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_196," line.long 0x384 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_197," line.long 0x388 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_198," line.long 0x38C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_199," line.long 0x390 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_200," line.long 0x394 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_201," line.long 0x398 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_202," line.long 0x39C "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_203," line.long 0x3A0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_204," line.long 0x3A4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_205," line.long 0x3A8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_206," line.long 0x3AC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_207," line.long 0x3B0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_208," line.long 0x3B4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_209," line.long 0x3B8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_210," line.long 0x3BC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_211," line.long 0x3C0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_212," line.long 0x3C4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_213," line.long 0x3C8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_214," line.long 0x3CC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_215," line.long 0x3D0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_216," line.long 0x3D4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_217," line.long 0x3D8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_218," line.long 0x3DC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_219," line.long 0x3E0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_220," line.long 0x3E4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_221," line.long 0x3E8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_222," line.long 0x3EC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_223," line.long 0x3F0 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_224," line.long 0x3F4 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_225," line.long 0x3F8 "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_226," line.long 0x3FC "ZIPW_PACKET_PROBE_RSP_MAIN_PROBE_RESERVED_227," tree.end tree.end tree.end tree "NVM (Non Volatile Memory)" base ad:0x0 tree "NVM_0" base ad:0x711BC000 group.long 0x0++0x7 line.long 0x0 "MCR_C0,Module Configuration Register" bitfld.long 0x0 31. "DSBC,Data Double Bit Correction" "0: Reads are occurring normally,1: An ECC Double Error occurred and was corrected.." bitfld.long 0x0 30. "RRE,Read Reference Error" "0: Reads are occurring normally,1: A Read Reference Error occurred during a.." newline bitfld.long 0x0 29. "AEE,Code Address Encode Error" "0: Reads are occurring normally,1: An Address Encode Error occurred during a.." bitfld.long 0x0 28. "EEE,Code EDC after ECC Error" "0: Reads are occurring normally,1: A previous Read may have been corrupted" newline bitfld.long 0x0 27. "DSBC1,Data Single Bit Correction 1" "0: Reads are occurring normally,1: An ECC Single Error occurred and was corrected.." bitfld.long 0x0 26. "DWEE1,Code Quad Word 1 uncorrectable ECC Error" "0: Reads are occurring normally,1: An ECC Uncorrectable Error occurred in a.." newline bitfld.long 0x0 25. "DDWEE0,Data Quad Word 0 Uncorrectable ECC Error" "0,1" bitfld.long 0x0 24. "DWEE0,Code Quad Word 0 Uncorrectable ECC Error" "0: Reads are occurring normally,1: An ECC Uncorrectable Error occurred in a.." newline bitfld.long 0x0 23. "DAEE,Data Address Encode Error" "0: Reads are occurring normally,1: An Address Encode Error occurred during a.." bitfld.long 0x0 22. "DEEE,Data EDC after ECC Error" "0: Reads are occurring normally,1: A previous Read may have been corrupted" newline bitfld.long 0x0 21. "EXTWE,Extension Write Error" "0: No write protection errors,1: Write protection errors during extended command" bitfld.long 0x0 20. "SBC1,Code Single Bit Correction 1" "0: Reads are occurring normally,1: An ECC Single Error occurred and was corrected.." newline bitfld.long 0x0 19. "SAK,Suspend Acknowledge" "0: Operation has been completed prior that Suspend..,1: Suspend Acknowledged" bitfld.long 0x0 18. "LSW,Lock-Sel Write Error" "0: Lock and Sel write successful,1: Lock and Sel write not succeeded" newline bitfld.long 0x0 17. "PEP,Write and extended Protection Error" "0: Program and refresh protection errors do not exist,1: Previous program or refresh protection error.." bitfld.long 0x0 16. "PES,Program extended Sequence Error" "0: Program or extended phase accepted,1: Program or extended command encountered an error" newline bitfld.long 0x0 15. "EER,ECC uncorrectable Event Error" "0: Reads are occurring normally,1: An ECC uncorrectable Triple Error occurred.." bitfld.long 0x0 14. "RWE,Read-while-Write event Error" "0: Reads are occurring normally,1: A RWW Error occurred during a previous Read" newline bitfld.long 0x0 13. "SBC,Code double Bit Correction" "0: Reads are occurring normally,1: An ECC Double Error occurred and was corrected.." bitfld.long 0x0 12. "RE,Reset Error" "0: NVM Boot phase has occurred normally,1: A reset error has been encountered" newline bitfld.long 0x0 11. "PEAS,Write Access Space" "0: UTEST address space is disabled for program and..,1: UTEST address space is enabled for program and.." bitfld.long 0x0 10. "DONE,Modify operation DONE" "0: ,1: " newline bitfld.long 0x0 9. "PEG,Write/Extension Good" "0: Write extended operation failed or aborted,1: Write or Extended operation successful" bitfld.long 0x0 8. "PECIE,Write Complete Interrupt Enable" "0: An interrupt request is not generated when the..,1: An interrupt request is generated when the DONE.." newline bitfld.long 0x0 7. "FERS,Factory Mode" "0: Factory Mode is disabled,1: Factory Mode is enabled" bitfld.long 0x0 6. "BLK,BLK" "0,1" newline bitfld.long 0x0 5. "RSB,RSB" "0,1" bitfld.long 0x0 4. "PGM,Program" "0: NVM is not executing a write sequence,1: NVM is executing a write sequence" newline bitfld.long 0x0 3. "PSUS,Program Suspend" "0: Program sequence is not suspended,1: Program sequence is suspended" bitfld.long 0x0 2. "ERS,Extended operations" "0: NVM is not executing an extended command sequence,1: NVM is executing an extended command sequence" newline bitfld.long 0x0 1. "ESUS,Extended operation Suspend" "0: Extended sequence is not suspended,1: and DONE=1" bitfld.long 0x0 0. "EHV,Enable High Voltage" "0: NVM is not enabled to perform a high voltage..,1: NVM is enabled to perform a high voltage operation" line.long 0x4 "MCRX_C0,Module Configuration Extended" bitfld.long 0x4 29. "OTAE,Over-the-air RWW partition Error" "0: No RWW selection error is reported for assisted..,1: RWW selection error is reported for assisted.." bitfld.long 0x4 28. "OTAW,Over-the-air ready-to-write" "0: No RWW selection error is reported for assisted..,1: RWW selection error is reported for assisted.." newline bitfld.long 0x4 22. "AICVK,AIC/MR full Tile signature initialization" "0: compute signature values otherwise,1: Signature/parity calculation command enabled" bitfld.long 0x4 21. "RFSCR,Refresh Crash" "0: No crash has been reported,1: Crash has occurred during while executing.." newline bitfld.long 0x4 18.--20. "EXTSS,Refresh Successful sequence" "0: No fails during sequence,1: Timeout fails during PEC reading request to NVMC..,2: Fail due to triple error detection during target..,3: Fail due to triple error detection during spare..,4: PEC Spare module program fail,5: PEC target module program fail,6: PEC test flash marker program fail during spare..,?" bitfld.long 0x4 17. "EXTCR,EXTension CRash" "0: No crash has been reported,1: Crash has occurred while executing previous.." newline bitfld.long 0x4 12. "AOTA,Assisted over-the-air" "0: Assisted over-the-air end phase,1: Assisted over-the-air set-up phase" bitfld.long 0x4 10. "PARCK,AIC parity NVM writing." "0: Compute and write signature,1: Compute and write parity" newline bitfld.long 0x4 9. "COMP,Complementary" "0: Complementary Array is not selected for Extended..,1: Complementary Array is selected for Extended.." bitfld.long 0x4 8. "DIR,Direct" "0: Direct Array is not selected for Extended Command,1: Direct Array is selected for Extended Command" newline bitfld.long 0x4 4. "RFS,Refresh" "0: Refresh disabled,1: Refresh enabled" bitfld.long 0x4 1. "SWAP,Address Swap" "0: RWW partitions address swap is not altered,1: RWW partitions address swap is set by SELx values" newline bitfld.long 0x4 0. "EXT,Address EXTension" "0: RWW partitions address mode is not altered,1: RWW partitions address mode is set by SELx values" rgroup.long 0x8++0x3 line.long 0x0 "MCRE_C0,Extended Module Configuration Register" hexmask.long.byte 0x0 24.--30. 1. "N256K,Number of 128 KB and 256 KB blocks in the 256K space" bitfld.long 0x0 21.--23. "N64KH,Number of 64 KB blocks in high space" "0: Zero 64 KB blocks.,1: Two 64 KB blocks.,2: Four 64 KB blocks.,3: Six 64 KB blocks.,4: Eight 64 KB blocks.,?,?,?" newline bitfld.long 0x0 19.--20. "N32KH,Number of 32 KB blocks in high space" "0: Zero 32 KB blocks.,1: Two 32 KB blocks.,2: Four 32 KB blocks.,?" bitfld.long 0x0 16.--18. "N16KH,Number of 16 KB blocks in high space" "0: Zero 16 KB blocks.,1: Two 16 KB blocks.,2: Four 16 KB blocks.,3: Six 16 KB blocks.,4: Eight 16 KB blocks.,?,?,?" newline bitfld.long 0x0 13.--15. "N64KM,Number of 64 KB blocks in mid space" "0: Zero 64 KB blocks.,1: Two 64 KB blocks.,2: Four 64 KB blocks.,3: Six 64 KB blocks.,4: Eight 64 KB blocks.,?,?,?" bitfld.long 0x0 11.--12. "N32KM,Number of 32 KB blocks in mid space" "0: Zero 32 KB blocks.,1: Two 32 KB blocks.,2: Four 32 KB blocks.,?" newline bitfld.long 0x0 8.--10. "N16KM,Number of 16 KB blocks in mid space" "0: Zero 16 KB blocks.,1: Two 16 KB blocks.,2: Four 16 KB blocks.,3: Six 16 KB blocks.,4: Eight 16 KB blocks.,?,?,?" bitfld.long 0x0 5.--7. "N64KL,Number of 64 KB blocks in low space" "0: Zero 64 KB blocks.,1: Two 64 KB blocks.,2: Four 64 KB blocks.,3: Six 64 KB blocks.,4: Eight 64 KB blocks.,?,?,?" newline bitfld.long 0x0 3.--4. "N32KL,Number of 32 KB blocks in low space" "0: Zero 32 KB blocks.,1: Two 32 KB blocks.,2: Four 32 KB blocks.,3: Three 32 KB blocks." bitfld.long 0x0 0.--2. "N16KL,Number of 16 KB blocks in low space" "0: Zero 16 KB blocks.,1: Two 16 KB blocks.,2: Four 16 KB blocks.,3: Six 16 KB blocks.,4: Eight 16 KB blocks.,5: Three 16 KB blocks.,?,?" group.long 0x10++0xF line.long 0x0 "LOCK0_C0,Lock 0 register" bitfld.long 0x0 31. "TSLK,UTEST NVM block lock" "0: Test Address Space Block is unlocked and can be..,1: Test Address Space Block is locked and cannot be.." hexmask.long.word 0x0 16.--29. 1. "LOWLOCK,Low address space block lock" newline hexmask.long.word 0x0 0.--15. 1. "MIDLOCK,Mid address space block lock" line.long 0x4 "LOCK1_C0,Lock 1 register" hexmask.long.word 0x4 0.--15. 1. "HIGHLOCK,High address space block lock" line.long 0x8 "LOCK2_C0,Lock 2 Register" hexmask.long 0x8 0.--31. 1. "A256KLOCK,256K address space block lock A256KLOCK[31:0]" line.long 0xC "LOCK3_C0,Lock 3 Register" hexmask.long 0xC 0.--31. 1. "A256KLOCK,256K address space block lock A256KLOCK[63:32]" group.long 0x38++0x13 line.long 0x0 "SEL0_C0,Select 0 register" hexmask.long.word 0x0 16.--29. 1. "LOWSEL,Low address space block Select" hexmask.long.word 0x0 0.--15. 1. "MIDSEL,Mid address space block Select" line.long 0x4 "SEL1_C0,Select 1 register" hexmask.long.word 0x4 0.--15. 1. "HIGHSEL,High/Data address space block Select 1" line.long 0x8 "SEL2_C0,Select 2 register" hexmask.long 0x8 0.--31. 1. "A256KSEL,256K address space block select A256KSEL[31:0]" line.long 0xC "SEL3_C0,Select 3 register" hexmask.long 0xC 0.--31. 1. "A256KSEL,256K address space block select A256KSEL[63:32]" line.long 0x10 "MCR_P1R_C0,Module Configuration Register Port 1 Read" bitfld.long 0x10 30. "PRRE,Parallel Read Reference Error" "0: Reads are occurring normally,1: A Read Reference Error occurred during a.." bitfld.long 0x10 29. "PAEE,Parallel Address Encode Error" "0: Reads are occurring normally,1: An Address Encode Error occurred during a.." newline bitfld.long 0x10 28. "PEEE,Parallel EDC after ECC Error" "0: Reads are occurring normally,1: A previous Read may have been corrupted" hexmask.long.byte 0x10 24.--27. 1. "PDWEE,Parallel Double Word Uncorrectable ECC Error" newline bitfld.long 0x10 20. "PSBC1,Parallel Single Bit Correction 1" "0: Reads are occurring normally,1: An ECC Single Error occurred and was corrected.." bitfld.long 0x10 15. "PEER,Parallel ECC Event Error" "0: Reads are occurring normally,1: An ECC Double Error occurred during a previous.." newline bitfld.long 0x10 14. "PRWE,Parallel Read-while-Write event Error" "0: Reads are occurring normally,1: A RWW Error occurred during a previous Read" bitfld.long 0x10 13. "PSBC,Parallel Single Bit Correction" "0: Reads are occurring normally,1: An ECC Single Error occurred and was corrected.." rgroup.long 0x4C++0x7 line.long 0x0 "PAR_C0,Program Address register" hexmask.long 0x0 3.--29. 1. "PAR,Address" line.long 0x4 "ADR_C0,Address register" bitfld.long 0x4 31. "SAD,Test Address" "0,1" hexmask.long 0x4 3.--29. 1. "ADDR,Address" group.long 0x54++0x3 line.long 0x0 "UT0_C0,User Test 0 register" bitfld.long 0x0 31. "UTE,User Test Enable" "0,1" bitfld.long 0x0 30. "SBCE,Double Bit Correction Enable" "0,1" newline bitfld.long 0x0 29. "DAR,Direct ARray" "0,1" bitfld.long 0x0 28. "CLCK,It enables embedded column signature check and flagging during Full columns AIC or MR execution." "0: Check is enabled,1: Check is disabled" newline bitfld.long 0x0 24. "AICAP,Array Integrity Check Address Port" "0: AIC_ADR0_Cy is selected,1: AIC_ADR1_Cy is selected" bitfld.long 0x0 23. "SBCE1,Single Bit Correction Enable" "0,1" newline bitfld.long 0x0 22. "AICV,Vertical array integrity check enabled" "0: AIC single column processing enabled,1: AIC single column processing disabled whole Tile.." bitfld.long 0x0 20. "ECRC,Array integrity check self check signature error" "0: Signature check passed,1: Signature check failed" newline bitfld.long 0x0 19. "EDCDD,Disable Data memory EDC after ECC error reporting to FCCU" "0: Data memory EEE error reporting to FCCU is enabled,1: Data memory EEE error reporting to FCCU is.." bitfld.long 0x0 18. "CPR,Customer Programmable Read Voltage and Reference Detection" "0: Customer Programmable Read Voltage and Reference..,1: Customer Programmable Read Voltage and Reference.." newline bitfld.long 0x0 17. "CPA,Customer Programmable Address Encode Detection" "0: Customer Programmable Address Encode Detection..,1: Customer Programmable Address Encode Detection.." bitfld.long 0x0 16. "CPE,Customer Programmable EDC after ECC Detection" "0: Customer Programmable EDC after ECC Detection..,1: Customer Programmable EDC after ECC Detection.." newline bitfld.long 0x0 15. "AERE,AIC ECC error reporting" "0: AIC Ecc error reporting disabled,1: AIC Ecc error reporting enabled" bitfld.long 0x0 9. "NAIBP,Next Array Integrity Break Point" "0: Array Integrity s not currently at a break point,1: Array Integrity is at a break point" newline bitfld.long 0x0 8. "AIBPE,Array Integrity Break Point Enable" "0: Array Integrity breakpoints are not enabled,1: Array Integrity breakpoints are enabled during.." bitfld.long 0x0 6. "AISUS,Array Integrity Suspend" "0: Array Integrity sequence not suspended,1: Array Integrity sequence is suspended" newline bitfld.long 0x0 5. "MRE,Margin Read Enable" "0: Margin Read is not enabled,1: Margin Read is enabled" bitfld.long 0x0 4. "MRV,Margin Read Value" "0: Zero's margin reads are requested (if MRE=1),1: One's margin reads are requested (if MRE=1)" newline bitfld.long 0x0 3. "MRB,Blank Margin Read Value" "0: Margin reads qualified by MRV are requested (if..,1: Blank margin reads qualified by MRV are requested" bitfld.long 0x0 2. "AIS,Array Integrity Sequence" "0: Array Integrity sequence is proprietary sequence,1: Array Integrity sequence is sequential" newline bitfld.long 0x0 1. "AIE,Array Integrity Enable" "0: Array Integrity Check and Margin Read and are..,1: Array Integrity Check and Margin Read are enabled" bitfld.long 0x0 0. "AID,Array Integrity Done" "0: Array Integrity Check is on-going,1: Array Integrity Check is done" rgroup.long 0x58++0x1F line.long 0x0 "UM0_C0,User Multiple Input Signature 0 register" bitfld.long 0x0 31. "MISR31,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 30. "MISR30,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 29. "MISR29,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 28. "MISR28,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 27. "MISR27,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 26. "MISR26,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 25. "MISR25,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 24. "MISR24,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 23. "MISR23,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 22. "MISR22,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 21. "MISR21,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 20. "MISR20,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 19. "MISR19,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 18. "MISR18,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 17. "MISR17,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 16. "MISR16,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 15. "MISR15,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 14. "MISR14,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 13. "MISR13,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 12. "MISR12,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 11. "MISR11,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 10. "MISR10,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 9. "MISR9,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 8. "MISR8,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 7. "MISR7,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 6. "MISR6,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 5. "MISR5,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 4. "MISR4,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 3. "MISR3,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 2. "MISR2,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 1. "MISR1,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 0. "MISR0,Multiple input signature 310x0:" "0,1" line.long 0x4 "UM1_C0,User Multiple Input Signature 1 register" bitfld.long 0x4 31. "MISR63,Multiple input signature 6332" "0,1" bitfld.long 0x4 30. "MISR62,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 29. "MISR61,Multiple input signature 6332" "0,1" bitfld.long 0x4 28. "MISR60,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 27. "MISR59,Multiple input signature 6332" "0,1" bitfld.long 0x4 26. "MISR58,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 25. "MISR57,Multiple input signature 6332" "0,1" bitfld.long 0x4 24. "MISR56,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 23. "MISR55,Multiple input signature 6332" "0,1" bitfld.long 0x4 22. "MISR54,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 21. "MISR53,Multiple input signature 6332" "0,1" bitfld.long 0x4 20. "MISR52,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 19. "MISR51,Multiple input signature 6332" "0,1" bitfld.long 0x4 18. "MISR50,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 17. "MISR49,Multiple input signature 6332" "0,1" bitfld.long 0x4 16. "MISR48,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 15. "MISR47,Multiple input signature 6332" "0,1" bitfld.long 0x4 14. "MISR46,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 13. "MISR45,Multiple input signature 6332" "0,1" bitfld.long 0x4 12. "MISR44,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 11. "MISR43,Multiple input signature 6332" "0,1" bitfld.long 0x4 10. "MISR42,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 9. "MISR41,Multiple input signature 6332" "0,1" bitfld.long 0x4 8. "MISR40,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 7. "MISR39,Multiple input signature 6332" "0,1" bitfld.long 0x4 6. "MISR38,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 5. "MISR37,Multiple input signature 6332" "0,1" bitfld.long 0x4 4. "MISR36,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 3. "MISR35,Multiple input signature 6332" "0,1" bitfld.long 0x4 2. "MISR34,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 1. "MISR33,Multiple input signature 6332" "0,1" bitfld.long 0x4 0. "MISR32,Multiple input signature 6332" "0,1" line.long 0x8 "UM2_C0,User Multiple Input Signature 2 register" bitfld.long 0x8 31. "MISR95,Multiple input signature 9564" "0,1" bitfld.long 0x8 30. "MISR94,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 29. "MISR93,Multiple input signature 9564" "0,1" bitfld.long 0x8 28. "MISR92,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 27. "MISR91,Multiple input signature 9564" "0,1" bitfld.long 0x8 26. "MISR90,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 25. "MISR89,Multiple input signature 9564" "0,1" bitfld.long 0x8 24. "MISR88,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 23. "MISR87,Multiple input signature 9564" "0,1" bitfld.long 0x8 22. "MISR86,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 21. "MISR85,Multiple input signature 9564" "0,1" bitfld.long 0x8 20. "MISR84,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 19. "MISR83,Multiple input signature 9564" "0,1" bitfld.long 0x8 18. "MISR82,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 17. "MISR81,Multiple input signature 9564" "0,1" bitfld.long 0x8 16. "MISR80,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 15. "MISR79,Multiple input signature 9564" "0,1" bitfld.long 0x8 14. "MISR78,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 13. "MISR77,Multiple input signature 9564" "0,1" bitfld.long 0x8 12. "MISR76,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 11. "MISR75,Multiple input signature 9564" "0,1" bitfld.long 0x8 10. "MISR74,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 9. "MISR73,Multiple input signature 9564" "0,1" bitfld.long 0x8 8. "MISR72,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 7. "MISR71,Multiple input signature 9564" "0,1" bitfld.long 0x8 6. "MISR70,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 5. "MISR69,Multiple input signature 9564" "0,1" bitfld.long 0x8 4. "MISR68,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 3. "MISR67,Multiple input signature 9564" "0,1" bitfld.long 0x8 2. "MISR66,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 1. "MISR65,Multiple input signature 9564" "0,1" bitfld.long 0x8 0. "MISR64,Multiple input signature 9564" "0,1" line.long 0xC "UM3_C0,User Multiple Input Signature 3 register" bitfld.long 0xC 31. "MISR127,Multiple input signature 12796" "0,1" bitfld.long 0xC 30. "MISR126,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 29. "MISR125,Multiple input signature 12796" "0,1" bitfld.long 0xC 28. "MISR124,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 27. "MISR123,Multiple input signature 12796" "0,1" bitfld.long 0xC 26. "MISR122,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 25. "MISR121,Multiple input signature 12796" "0,1" bitfld.long 0xC 24. "MISR120,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 23. "MISR119,Multiple input signature 12796" "0,1" bitfld.long 0xC 22. "MISR118,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 21. "MISR117,Multiple input signature 12796" "0,1" bitfld.long 0xC 20. "MISR116,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 19. "MISR115,Multiple input signature 12796" "0,1" bitfld.long 0xC 18. "MISR114,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 17. "MISR113,Multiple input signature 12796" "0,1" bitfld.long 0xC 16. "MISR112,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 15. "MISR111,Multiple input signature 12796" "0,1" bitfld.long 0xC 14. "MISR110,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 13. "MISR109,Multiple input signature 12796" "0,1" bitfld.long 0xC 12. "MISR108,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 11. "MISR107,Multiple input signature 12796" "0,1" bitfld.long 0xC 10. "MISR106,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 9. "MISR105,Multiple input signature 12796" "0,1" bitfld.long 0xC 8. "MISR104,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 7. "MISR103,Multiple input signature 12796" "0,1" bitfld.long 0xC 6. "MISR102,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 5. "MISR101,Multiple input signature 12796" "0,1" bitfld.long 0xC 4. "MISR100,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 3. "MISR99,Multiple input signature 12796" "0,1" bitfld.long 0xC 2. "MISR98,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 1. "MISR97,Multiple input signature 12796" "0,1" bitfld.long 0xC 0. "MISR96,Multiple input signature 12796" "0,1" line.long 0x10 "UM4_C0,User Multiple Input Signature 4 register" bitfld.long 0x10 31. "MISR159,Multiple input signature 159128" "0,1" bitfld.long 0x10 30. "MISR158,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 29. "MISR157,Multiple input signature 159128" "0,1" bitfld.long 0x10 28. "MISR156,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 27. "MISR155,Multiple input signature 159128" "0,1" bitfld.long 0x10 26. "MISR154,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 25. "MISR153,Multiple input signature 159128" "0,1" bitfld.long 0x10 24. "MISR152,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 23. "MISR151,Multiple input signature 159128" "0,1" bitfld.long 0x10 22. "MISR150,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 21. "MISR149,Multiple input signature 159128" "0,1" bitfld.long 0x10 20. "MISR148,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 19. "MISR147,Multiple input signature 159128" "0,1" bitfld.long 0x10 18. "MISR146,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 17. "MISR145,Multiple input signature 159128" "0,1" bitfld.long 0x10 16. "MISR144,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 15. "MISR143,Multiple input signature 159128" "0,1" bitfld.long 0x10 14. "MISR142,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 13. "MISR141,Multiple input signature 159128" "0,1" bitfld.long 0x10 12. "MISR140,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 11. "MISR139,Multiple input signature 159128" "0,1" bitfld.long 0x10 10. "MISR138,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 9. "MISR137,Multiple input signature 159128" "0,1" bitfld.long 0x10 8. "MISR136,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 7. "MISR135,Multiple input signature 159128" "0,1" bitfld.long 0x10 6. "MISR134,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 5. "MISR133,Multiple input signature 159128" "0,1" bitfld.long 0x10 4. "MISR132,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 3. "MISR131,Multiple input signature 159128" "0,1" bitfld.long 0x10 2. "MISR130,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 1. "MISR129,Multiple input signature 159128" "0,1" bitfld.long 0x10 0. "MISR128,Multiple input signature 159128" "0,1" line.long 0x14 "UM5_C0,User Multiple Input Signature 5 register" bitfld.long 0x14 31. "MISR191,Multiple input signature 191160" "0,1" bitfld.long 0x14 30. "MISR190,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 29. "MISR189,Multiple input signature 191160" "0,1" bitfld.long 0x14 28. "MISR188,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 27. "MISR187,Multiple input signature 191160" "0,1" bitfld.long 0x14 26. "MISR186,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 25. "MISR185,Multiple input signature 191160" "0,1" bitfld.long 0x14 24. "MISR184,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 23. "MISR183,Multiple input signature 191160" "0,1" bitfld.long 0x14 22. "MISR182,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 21. "MISR181,Multiple input signature 191160" "0,1" bitfld.long 0x14 20. "MISR180,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 19. "MISR179,Multiple input signature 191160" "0,1" bitfld.long 0x14 18. "MISR178,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 17. "MISR177,Multiple input signature 191160" "0,1" bitfld.long 0x14 16. "MISR176,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 15. "MISR175,Multiple input signature 191160" "0,1" bitfld.long 0x14 14. "MISR174,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 13. "MISR173,Multiple input signature 191160" "0,1" bitfld.long 0x14 12. "MISR172,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 11. "MISR171,Multiple input signature 191160" "0,1" bitfld.long 0x14 10. "MISR170,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 9. "MISR169,Multiple input signature 191160" "0,1" bitfld.long 0x14 8. "MISR168,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 7. "MISR167,Multiple input signature 191160" "0,1" bitfld.long 0x14 6. "MISR166,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 5. "MISR165,Multiple input signature 191160" "0,1" bitfld.long 0x14 4. "MISR164,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 3. "MISR163,Multiple input signature 191160" "0,1" bitfld.long 0x14 2. "MISR162,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 1. "MISR161,Multiple input signature 191160" "0,1" bitfld.long 0x14 0. "MISR160,Multiple input signature 191160" "0,1" line.long 0x18 "UM6_C0,User Multiple Input Signature 6 register" bitfld.long 0x18 31. "MISR223,Multiple input signature 223192" "0,1" bitfld.long 0x18 30. "MISR222,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 29. "MISR221,Multiple input signature 223192" "0,1" bitfld.long 0x18 28. "MISR220,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 27. "MISR219,Multiple input signature 223192" "0,1" bitfld.long 0x18 26. "MISR218,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 25. "MISR217,Multiple input signature 223192" "0,1" bitfld.long 0x18 24. "MISR216,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 23. "MISR215,Multiple input signature 223192" "0,1" bitfld.long 0x18 22. "MISR214,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 21. "MISR213,Multiple input signature 223192" "0,1" bitfld.long 0x18 20. "MISR212,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 19. "MISR211,Multiple input signature 223192" "0,1" bitfld.long 0x18 18. "MISR210,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 17. "MISR209,Multiple input signature 223192" "0,1" bitfld.long 0x18 16. "MISR208,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 15. "MISR207,Multiple input signature 223192" "0,1" bitfld.long 0x18 14. "MISR206,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 13. "MISR205,Multiple input signature 223192" "0,1" bitfld.long 0x18 12. "MISR204,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 11. "MISR203,Multiple input signature 223192" "0,1" bitfld.long 0x18 10. "MISR202,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 9. "MISR201,Multiple input signature 223192" "0,1" bitfld.long 0x18 8. "MISR200,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 7. "MISR199,Multiple input signature 223192" "0,1" bitfld.long 0x18 6. "MISR198,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 5. "MISR197,Multiple input signature 223192" "0,1" bitfld.long 0x18 4. "MISR196,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 3. "MISR195,Multiple input signature 223192" "0,1" bitfld.long 0x18 2. "MISR194,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 1. "MISR193,Multiple input signature 223192" "0,1" bitfld.long 0x18 0. "MISR192,Multiple input signature 223192" "0,1" line.long 0x1C "UM7_C0,User Multiple Input Signature 7 register" bitfld.long 0x1C 31. "MISR255,Multiple input signature 255224" "0,1" bitfld.long 0x1C 30. "MISR254,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 29. "MISR253,Multiple input signature 255224" "0,1" bitfld.long 0x1C 28. "MISR252,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 27. "MISR251,Multiple input signature 255224" "0,1" bitfld.long 0x1C 26. "MISR250,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 25. "MISR249,Multiple input signature 255224" "0,1" bitfld.long 0x1C 24. "MISR248,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 23. "MISR247,Multiple input signature 255224" "0,1" bitfld.long 0x1C 22. "MISR246,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 21. "MISR245,Multiple input signature 255224" "0,1" bitfld.long 0x1C 20. "MISR244,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 19. "MISR243,Multiple input signature 255224" "0,1" bitfld.long 0x1C 18. "MISR242,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 17. "MISR241,Multiple input signature 255224" "0,1" bitfld.long 0x1C 16. "MISR240,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 15. "MISR239,Multiple input signature 255224" "0,1" bitfld.long 0x1C 14. "MISR238,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 13. "MISR237,Multiple input signature 255224" "0,1" bitfld.long 0x1C 12. "MISR236,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 11. "MISR235,Multiple input signature 255224" "0,1" bitfld.long 0x1C 10. "MISR234,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 9. "MISR233,Multiple input signature 255224" "0,1" bitfld.long 0x1C 8. "MISR232,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 7. "MISR231,Multiple input signature 255224" "0,1" bitfld.long 0x1C 6. "MISR230,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 5. "MISR229,Multiple input signature 255224" "0,1" bitfld.long 0x1C 4. "MISR228,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 3. "MISR227,Multiple input signature 255224" "0,1" bitfld.long 0x1C 2. "MISR226,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 1. "MISR225,Multiple input signature 255224" "0,1" bitfld.long 0x1C 0. "MISR224,Multiple input signature 255224" "0,1" rgroup.long 0x80++0xF line.long 0x0 "OPP0_C0,Over-program protection 0 register" hexmask.long.word 0x0 16.--29. 1. "LOWOPP,Low address space Over Program Protection" hexmask.long.word 0x0 0.--15. 1. "MIDOPP,Mid address space Over Program Protection" line.long 0x4 "OPP1_C0,Over-program protection 1 register" hexmask.long.word 0x4 0.--15. 1. "HIGHOPP,High address space Over Program Protection" line.long 0x8 "OPP2_C0,Over-program protection 2 register" hexmask.long 0x8 0.--31. 1. "A256KOPP,256K Address Space Block Over Program Protection A256KOPP[31:0]" line.long 0xC "OPP3_C0,Over-program protection 3 register" hexmask.long 0xC 0.--31. 1. "A256KOPP,256K Address space Over Program Protection A256KOPP[63:32]" group.long 0x94++0xB line.long 0x0 "AIC_ADR0_C0,Array integrity check port 0. cluster C0 Tile/column address selection register" hexmask.long 0x0 3.--29. 1. "AIC_ADR0,AIC Tile/column selection register on port 0 cluster C0" line.long 0x4 "AIC_ADR1_C0,Array integrity check port 1. cluster C0 Tile/column address selection register" hexmask.long 0x4 3.--29. 1. "AIC_ADR1,AIC Tile/column selection register on port 1 cluster C0" line.long 0x8 "AIC_RWR_C0,Array integrity check read while read configuration register" hexmask.long.word 0x8 16.--31. 1. "WT_CONF,It stores decimal to binary encoded format the number of fclk_C0 clock cycles in which AIC internal state machine remain on IDLE state." hexmask.long.word 0x8 0.--15. 1. "RD_CONF,It stores decimal to binary encoded format the number of consecutive internal reads to be executed by AIC internal state machine after flh_rlock_ack_Px_C0 signal assertion coming from PFC. After completion of this task PCM de-asserts.." rgroup.long 0x100++0x1F line.long 0x0 "EXTSTAT_C0,Extended Mode Status Register" hexmask.long.word 0x0 16.--31. 1. "SWAPSTAT,Extended Mode Status Register EXTSTAT" hexmask.long.word 0x0 0.--15. 1. "EXTSTAT,Extended Mode Status Register EXTSTAT" line.long 0x4 "RFSSTAT_C0,Refresh Status Register" hexmask.long.word 0x4 16.--31. 1. "RFSSTATCMP,Extended Mode Status Register RFSSTAT" hexmask.long.word 0x4 0.--15. 1. "RFSSTATDIR,Extended Mode Status Register EXTSTAT" line.long 0x8 "OTAWSTAT_C0,Over-The-Air Write Ready Status Register" hexmask.long.word 0x8 16.--31. 1. "OTAWSTATCMP,Over-the-air write Status Register OTAWSTAT" hexmask.long.word 0x8 0.--15. 1. "OTAWSTATDIR,Over-the-air write Status Register OTAWSTAT" line.long 0xC "CRSTAT_C0,Crash Status Register" hexmask.long.word 0xC 16.--31. 1. "CRSTATCMP,Crash Status Register CRSTAT" hexmask.long.word 0xC 0.--15. 1. "CRSTATDIR,Crash Status Register CRSTAT" line.long 0x10 "PLOCK0_C0,Program Lock Protection 0 register" hexmask.long.word 0x10 16.--31. 1. "LOWPLOCK,Low address space extended Lock Protection" hexmask.long.word 0x10 0.--15. 1. "MIDPLOCK,Mid address space extended Lock Protection" line.long 0x14 "PLOCK1_C0,Program Lock Protection 1 register" hexmask.long.word 0x14 0.--15. 1. "HIGHPLOCK,High address space Program Lock Protection" line.long 0x18 "PLOCK2_C0,Program Lock Protection 2 register" hexmask.long 0x18 0.--31. 1. "A256KPLOCK,256K High address space Program Lock Protection A256KPLOCK[31:0]" line.long 0x1C "PLOCK3_C0,Program Lock protection 3 register" hexmask.long 0x1C 0.--31. 1. "A256KPLOCK,256K High address space Program Lock Protection A256KPLOCK[63:32]" rgroup.long 0x134++0x3 line.long 0x0 "ADR_P1R_C0,Address register Port 1 read" hexmask.long.tbyte 0x0 3.--23. 1. "PADR,Parallel Address" tree.end tree "NVM_1" base ad:0x717BC000 group.long 0x0++0x3 line.long 0x0 "MCR_C1,Module Configuration Register" bitfld.long 0x0 30. "RRE,Read Reference Error" "0: Reads are occurring normally,1: A Read Reference Error occurred during a.." bitfld.long 0x0 29. "AEE,Address Encode Error" "0: Reads are occurring normally,1: An Address Encode Error occurred during a.." newline bitfld.long 0x0 28. "EEE,ECC after ECC Error" "0: Reads are occurring normally,1: A previous Read may have been corrupted." bitfld.long 0x0 26. "DWEE1,Quad Word Uncorrectable ECC Error" "0,1" newline bitfld.long 0x0 24. "DWEE0,Quad Word Uncorrectable ECC Error" "0,1" bitfld.long 0x0 20. "SBC1,Single Bit Correction 1" "0: Reads are occurring normally,1: An ECC Single Error occurred and was corrected.." newline bitfld.long 0x0 15. "EER,ECC uncorrectable Event Error" "0: Reads are occurring normally,1: An ECC uncorrectable Triple Error occurred.." bitfld.long 0x0 14. "RWE,Read-while-Write event Error" "0: Reads are occurring normally,1: A RWW Error occurred during a previous Read" newline bitfld.long 0x0 13. "SBC,double Bit Correction" "0: Reads are occurring normally,1: An ECC Double Error occurred and was corrected.." bitfld.long 0x0 12. "RE,Reset Error" "0: NVM Boot phase has occurred normally,1: A reset error has been encountered" rgroup.long 0x8++0x3 line.long 0x0 "MCRE_C1,Extended Module Configuration Register" hexmask.long.byte 0x0 24.--30. 1. "N256K,Number of 128 KB and 256 KB blocks in the 256K space" bitfld.long 0x0 21.--23. "N64KH,Number of 64 KB blocks in high space" "0: Zero 64 KB blocks.,1: Two 64 KB blocks.,2: Four 64 KB blocks.,3: Six 64 KB blocks.,4: Eight 64 KB blocks.,?,?,?" newline bitfld.long 0x0 19.--20. "N32KH,Number of 32 KB blocks in high space" "0: Zero 32 KB blocks.,1: Two 32 KB blocks.,2: Four 32 KB blocks.,?" bitfld.long 0x0 16.--18. "N16KH,Number of 16 KB blocks in high space" "0: Zero 16 KB blocks.,1: Two 16 KB blocks.,2: Four 16 KB blocks.,3: Six 16 KB blocks.,4: Eight 16 KB blocks.,?,?,?" newline bitfld.long 0x0 13.--15. "N64KM,Number of 64 KB blocks in mid space" "0: Zero 64 KB blocks.,1: Two 64 KB blocks.,2: Four 64 KB blocks.,3: Six 64 KB blocks.,4: Eight 64 KB blocks.,?,?,?" bitfld.long 0x0 11.--12. "N32KM,Number of 32 KB blocks in mid space" "0: Zero 32 KB blocks.,1: Two 32 KB blocks.,2: Four 32 KB blocks.,?" newline bitfld.long 0x0 8.--10. "N16KM,Number of 16 KB blocks in mid space" "0: Zero 16 KB blocks.,1: Two 16 KB blocks.,2: Four 16 KB blocks.,3: Six 16 KB blocks.,4: Eight 16 KB blocks.,?,?,?" bitfld.long 0x0 5.--7. "N64KL,Number of 64 KB blocks in low space" "0: Zero 64 KB blocks.,1: Two 64 KB blocks.,2: Four 64 KB blocks.,3: Six 64 KB blocks.,4: Eight 64 KB blocks.,?,?,?" newline bitfld.long 0x0 3.--4. "N32KL,Number of 32 KB blocks in low space" "0: Zero 32 KB blocks.,1: Two 32 KB blocks.,2: Four 32 KB blocks.,3: Three 32 KB blocks." bitfld.long 0x0 0.--2. "N16KL,Number of 16 KB blocks in low space" "0: Zero 16 KB blocks.,1: Two 16 KB blocks.,2: Four 16 KB blocks.,3: Six 16 KB blocks.,4: Eight 16 KB blocks.,5: Three 16 KB blocks.,?,?" group.long 0x10++0xF line.long 0x0 "LOCK0_C1,Lock 0 register" hexmask.long.word 0x0 16.--29. 1. "LOWLOCK,Low address space block lock" hexmask.long.word 0x0 0.--15. 1. "MIDLOCK,Mid address space block lock" line.long 0x4 "LOCK1_C1,Lock 1 register" hexmask.long.word 0x4 0.--15. 1. "HIGHLOCK,High address space block lock" line.long 0x8 "LOCK2_C1,Lock 2 Register" hexmask.long 0x8 0.--31. 1. "A256KLOCK,256K address space block lock A256KLOCK[31:0]" line.long 0xC "LOCK3_C1,Lock 3 Register" hexmask.long 0xC 0.--31. 1. "A256KLOCK,256K address space block lock A256KLOCK[63:32]" group.long 0x38++0x13 line.long 0x0 "SEL0_C1,Select 0 register" hexmask.long.word 0x0 16.--29. 1. "LOWSEL,Low address space block Select" hexmask.long.word 0x0 0.--15. 1. "MIDSEL,Mid address space block Select" line.long 0x4 "SEL1_C1,Select 1 register" hexmask.long.word 0x4 0.--15. 1. "HIGHSEL,High/Data address space block Select 1" line.long 0x8 "SEL2_C1,Select 2 register" hexmask.long 0x8 0.--31. 1. "A256KSEL,256K address space block select A256KSEL[31:0]" line.long 0xC "SEL3_C1,Select 3 register" hexmask.long 0xC 0.--31. 1. "A256KSEL,256K address space block select A256KSEL[63:32]" line.long 0x10 "MCR_P1R_C1,Module Configuration Register Port 1 read" bitfld.long 0x10 30. "PRRE,Parallel Read Reference Error" "0: Reads are occurring normally,1: A Read Reference Error occurred during a.." bitfld.long 0x10 29. "PAEE,Parallel Address Encode Error" "0: Reads are occurring normally,1: An Address Encode Error occurred during a.." newline bitfld.long 0x10 28. "PEEE,Parallel EDC after ECC Error" "0: Reads are occurring normally,1: A previous Read may have been corrupted" hexmask.long.byte 0x10 24.--27. 1. "PDWEE,Parallel Double Word Uncorrectable ECC Error" newline bitfld.long 0x10 20. "PSBC1,Parallel Single Bit Correction 1" "0: Reads are occurring normally,1: An ECC Single Error occurred and was corrected.." bitfld.long 0x10 15. "PEER,Parallel ECC Event Error" "0: Reads are occurring normally,1: An ECC Double Error occurred during a previous.." newline bitfld.long 0x10 14. "PRWE,Parallel Read-while-Write event Error" "0: Reads are occurring normally,1: A RWW Error occurred during a previous Read" bitfld.long 0x10 13. "PSBC,Parallel Single Bit Correction" "0: Reads are occurring normally,1: An ECC Single Error occurred and was corrected.." rgroup.long 0x50++0x3 line.long 0x0 "ADR_C1,Address register" bitfld.long 0x0 31. "SAD,Test Address" "0,1" hexmask.long.tbyte 0x0 3.--23. 1. "ADDR,Address" group.long 0x54++0x3 line.long 0x0 "UT0_C1,User Test 0 register" bitfld.long 0x0 31. "UTE,User Test Enable" "0,1" bitfld.long 0x0 30. "SBCE,Double Bit Correction Enable" "0,1" newline bitfld.long 0x0 28. "CLCK,It enables embedded column signature check and flagging during Full columns AIC or MR execution." "0: Check is enabled,1: Check is disabled" bitfld.long 0x0 23. "SBCE1,Single Bit Correction Enable" "0,1" newline bitfld.long 0x0 22. "AICV,Vertical array integrity check enabled" "0: AIC single column processing enabled,1: AIC single column processing disabled whole Tile.." bitfld.long 0x0 20. "ECRC,Array integrity check self check signature error" "0: Signature check passed,1: Signature check failed." newline bitfld.long 0x0 19. "AICV_ADR,Vertical array integrity check address register selection" "0: AIC on Tile/column selected by AIC_ADR0_C1,1: AIC on Tile/column selected by AIC_ADR1_C1" bitfld.long 0x0 18. "CPR,Customer Programmable Read Voltage and Reference Detection" "0: Customer Programmable Read Voltage and Reference..,1: Customer Programmable Read Voltage and Reference.." newline bitfld.long 0x0 17. "CPA,Customer Programmable Address Encode Detection" "0: Customer Programmable Address Encode Detection..,1: Customer Programmable Address Encode Detection.." bitfld.long 0x0 16. "CPE,Customer Programmable EDC after ECC Detection" "0: Customer Programmable EDC after ECC Detection..,1: Customer Programmable EDC after ECC Detection.." newline bitfld.long 0x0 15. "AERE,AIC ecc error reporting" "0: AIC Ecc error reporting disabled,1: AIC Ecc error reporting enabled" bitfld.long 0x0 9. "NAIBP,Next Array Integrity Break Point" "0: Array Integrity-Vth Distribution is not..,1: Array Integrity-Vth Distribution is at a break.." newline bitfld.long 0x0 8. "AIBPE,Array Integrity Break Point Enable" "0: Array Integrity breakpoints are not enabled,1: Array Integrity breakpoints are enabled during.." bitfld.long 0x0 6. "AISUS,Array Integrity Suspend" "0: Array Integrity sequence not suspended,1: Array Integrity sequence is suspended" newline bitfld.long 0x0 5. "MRE,Margin Read Enable" "0: Margin Read is not enabled,1: Margin Read is enabled" bitfld.long 0x0 4. "MRV,Margin Read Value" "0: Zero's margin reads are requested (if MRE=1),1: One's margin reads are requested (if MRE=1)" newline bitfld.long 0x0 3. "MRB,Blank Margin Read Value" "0: Margin reads qualified by MRV are requested (if..,1: Blank margin reads qualified by MRV are requested" bitfld.long 0x0 2. "AIS,Array Integrity Sequence" "0: Array Integrity sequence is proprietary sequence,1: Array Integrity sequence is sequential" newline bitfld.long 0x0 1. "AIE,Array Integrity Enable" "0: Array Integrity Check and Margin Read and are..,1: Array Integrity Check and Margin Read are enabled" bitfld.long 0x0 0. "AID,Array Integrity Done" "0: Array Integrity Check is on-going,1: Array Integrity Check is done" rgroup.long 0x58++0xF line.long 0x0 "UM0_C1,User Multiple Input Signature 0 register" bitfld.long 0x0 31. "MISR31,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 30. "MISR30,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 29. "MISR29,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 28. "MISR28,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 27. "MISR27,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 26. "MISR26,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 25. "MISR25,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 24. "MISR24,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 23. "MISR23,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 22. "MISR22,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 21. "MISR21,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 20. "MISR20,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 19. "MISR19,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 18. "MISR18,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 17. "MISR17,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 16. "MISR16,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 15. "MISR15,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 14. "MISR14,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 13. "MISR13,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 12. "MISR12,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 11. "MISR11,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 10. "MISR10,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 9. "MISR9,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 8. "MISR8,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 7. "MISR7,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 6. "MISR6,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 5. "MISR5,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 4. "MISR4,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 3. "MISR3,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 2. "MISR2,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 1. "MISR1,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 0. "MISR0,Multiple input signature 310x0:" "0,1" line.long 0x4 "UM1_C1,User Multiple Input Signature 1 register" bitfld.long 0x4 31. "MISR63,Multiple input signature 6332" "0,1" bitfld.long 0x4 30. "MISR62,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 29. "MISR61,Multiple input signature 6332" "0,1" bitfld.long 0x4 28. "MISR60,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 27. "MISR59,Multiple input signature 6332" "0,1" bitfld.long 0x4 26. "MISR58,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 25. "MISR57,Multiple input signature 6332" "0,1" bitfld.long 0x4 24. "MISR56,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 23. "MISR55,Multiple input signature 6332" "0,1" bitfld.long 0x4 22. "MISR54,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 21. "MISR53,Multiple input signature 6332" "0,1" bitfld.long 0x4 20. "MISR52,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 19. "MISR51,Multiple input signature 6332" "0,1" bitfld.long 0x4 18. "MISR50,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 17. "MISR49,Multiple input signature 6332" "0,1" bitfld.long 0x4 16. "MISR48,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 15. "MISR47,Multiple input signature 6332" "0,1" bitfld.long 0x4 14. "MISR46,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 13. "MISR45,Multiple input signature 6332" "0,1" bitfld.long 0x4 12. "MISR44,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 11. "MISR43,Multiple input signature 6332" "0,1" bitfld.long 0x4 10. "MISR42,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 9. "MISR41,Multiple input signature 6332" "0,1" bitfld.long 0x4 8. "MISR40,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 7. "MISR39,Multiple input signature 6332" "0,1" bitfld.long 0x4 6. "MISR38,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 5. "MISR37,Multiple input signature 6332" "0,1" bitfld.long 0x4 4. "MISR36,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 3. "MISR35,Multiple input signature 6332" "0,1" bitfld.long 0x4 2. "MISR34,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 1. "MISR33,Multiple input signature 6332" "0,1" bitfld.long 0x4 0. "MISR32,Multiple input signature 6332" "0,1" line.long 0x8 "UM2_C1,User Multiple Input Signature 2 register" bitfld.long 0x8 31. "MISR95,Multiple input signature 9564" "0,1" bitfld.long 0x8 30. "MISR94,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 29. "MISR93,Multiple input signature 9564" "0,1" bitfld.long 0x8 28. "MISR92,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 27. "MISR91,Multiple input signature 9564" "0,1" bitfld.long 0x8 26. "MISR90,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 25. "MISR89,Multiple input signature 9564" "0,1" bitfld.long 0x8 24. "MISR88,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 23. "MISR87,Multiple input signature 9564" "0,1" bitfld.long 0x8 22. "MISR86,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 21. "MISR85,Multiple input signature 9564" "0,1" bitfld.long 0x8 20. "MISR84,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 19. "MISR83,Multiple input signature 9564" "0,1" bitfld.long 0x8 18. "MISR82,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 17. "MISR81,Multiple input signature 9564" "0,1" bitfld.long 0x8 16. "MISR80,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 15. "MISR79,Multiple input signature 9564" "0,1" bitfld.long 0x8 14. "MISR78,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 13. "MISR77,Multiple input signature 9564" "0,1" bitfld.long 0x8 12. "MISR76,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 11. "MISR75,Multiple input signature 9564" "0,1" bitfld.long 0x8 10. "MISR74,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 9. "MISR73,Multiple input signature 9564" "0,1" bitfld.long 0x8 8. "MISR72,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 7. "MISR71,Multiple input signature 9564" "0,1" bitfld.long 0x8 6. "MISR70,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 5. "MISR69,Multiple input signature 9564" "0,1" bitfld.long 0x8 4. "MISR68,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 3. "MISR67,Multiple input signature 9564" "0,1" bitfld.long 0x8 2. "MISR66,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 1. "MISR65,Multiple input signature 9564" "0,1" bitfld.long 0x8 0. "MISR64,Multiple input signature 9564" "0,1" line.long 0xC "UM3_C1,User Multiple Input Signature 3 register" bitfld.long 0xC 31. "MISR127,Multiple input signature 12796" "0,1" bitfld.long 0xC 30. "MISR126,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 29. "MISR125,Multiple input signature 12796" "0,1" bitfld.long 0xC 28. "MISR124,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 27. "MISR123,Multiple input signature 12796" "0,1" bitfld.long 0xC 26. "MISR122,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 25. "MISR121,Multiple input signature 12796" "0,1" bitfld.long 0xC 24. "MISR120,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 23. "MISR119,Multiple input signature 12796" "0,1" bitfld.long 0xC 22. "MISR118,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 21. "MISR117,Multiple input signature 12796" "0,1" bitfld.long 0xC 20. "MISR116,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 19. "MISR115,Multiple input signature 12796" "0,1" bitfld.long 0xC 18. "MISR114,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 17. "MISR113,Multiple input signature 12796" "0,1" bitfld.long 0xC 16. "MISR112,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 15. "MISR111,Multiple input signature 12796" "0,1" bitfld.long 0xC 14. "MISR110,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 13. "MISR109,Multiple input signature 12796" "0,1" bitfld.long 0xC 12. "MISR108,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 11. "MISR107,Multiple input signature 12796" "0,1" bitfld.long 0xC 10. "MISR106,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 9. "MISR105,Multiple input signature 12796" "0,1" bitfld.long 0xC 8. "MISR104,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 7. "MISR103,Multiple input signature 12796" "0,1" bitfld.long 0xC 6. "MISR102,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 5. "MISR101,Multiple input signature 12796" "0,1" bitfld.long 0xC 4. "MISR100,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 3. "MISR99,Multiple input signature 12796" "0,1" bitfld.long 0xC 2. "MISR98,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 1. "MISR97,Multiple input signature 12796" "0,1" bitfld.long 0xC 0. "MISR96,Multiple input signature 12796" "0,1" rgroup.long 0x6C++0xB line.long 0x0 "UM5_C1,User Multiple Input Signature 5 register" bitfld.long 0x0 31. "MISR191,Multiple input signature 191160" "0,1" bitfld.long 0x0 30. "MISR190,Multiple input signature 191160" "0,1" newline bitfld.long 0x0 29. "MISR189,Multiple input signature 191160" "0,1" bitfld.long 0x0 28. "MISR188,Multiple input signature 191160" "0,1" newline bitfld.long 0x0 27. "MISR187,Multiple input signature 191160" "0,1" bitfld.long 0x0 26. "MISR186,Multiple input signature 191160" "0,1" newline bitfld.long 0x0 25. "MISR185,Multiple input signature 191160" "0,1" bitfld.long 0x0 24. "MISR184,Multiple input signature 191160" "0,1" newline bitfld.long 0x0 23. "MISR183,Multiple input signature 191160" "0,1" bitfld.long 0x0 22. "MISR182,Multiple input signature 191160" "0,1" newline bitfld.long 0x0 21. "MISR181,Multiple input signature 191160" "0,1" bitfld.long 0x0 20. "MISR180,Multiple input signature 191160" "0,1" newline bitfld.long 0x0 19. "MISR179,Multiple input signature 191160" "0,1" bitfld.long 0x0 18. "MISR178,Multiple input signature 191160" "0,1" newline bitfld.long 0x0 17. "MISR177,Multiple input signature 191160" "0,1" bitfld.long 0x0 16. "MISR176,Multiple input signature 191160" "0,1" newline bitfld.long 0x0 15. "MISR175,Multiple input signature 191160" "0,1" bitfld.long 0x0 14. "MISR174,Multiple input signature 191160" "0,1" newline bitfld.long 0x0 13. "MISR173,Multiple input signature 191160" "0,1" bitfld.long 0x0 12. "MISR172,Multiple input signature 191160" "0,1" newline bitfld.long 0x0 11. "MISR171,Multiple input signature 191160" "0,1" bitfld.long 0x0 10. "MISR170,Multiple input signature 191160" "0,1" newline bitfld.long 0x0 9. "MISR169,Multiple input signature 191160" "0,1" bitfld.long 0x0 8. "MISR168,Multiple input signature 191160" "0,1" newline bitfld.long 0x0 7. "MISR167,Multiple input signature 191160" "0,1" bitfld.long 0x0 6. "MISR166,Multiple input signature 191160" "0,1" newline bitfld.long 0x0 5. "MISR165,Multiple input signature 191160" "0,1" bitfld.long 0x0 4. "MISR164,Multiple input signature 191160" "0,1" newline bitfld.long 0x0 3. "MISR163,Multiple input signature 191160" "0,1" bitfld.long 0x0 2. "MISR162,Multiple input signature 191160" "0,1" newline bitfld.long 0x0 1. "MISR161,Multiple input signature 191160" "0,1" bitfld.long 0x0 0. "MISR160,Multiple input signature 191160" "0,1" line.long 0x4 "UM6_C1,User Multiple Input Signature 6 register" bitfld.long 0x4 31. "MISR223,Multiple input signature 223192" "0,1" bitfld.long 0x4 30. "MISR222,Multiple input signature 223192" "0,1" newline bitfld.long 0x4 29. "MISR221,Multiple input signature 223192" "0,1" bitfld.long 0x4 28. "MISR220,Multiple input signature 223192" "0,1" newline bitfld.long 0x4 27. "MISR219,Multiple input signature 223192" "0,1" bitfld.long 0x4 26. "MISR218,Multiple input signature 223192" "0,1" newline bitfld.long 0x4 25. "MISR217,Multiple input signature 223192" "0,1" bitfld.long 0x4 24. "MISR216,Multiple input signature 223192" "0,1" newline bitfld.long 0x4 23. "MISR215,Multiple input signature 223192" "0,1" bitfld.long 0x4 22. "MISR214,Multiple input signature 223192" "0,1" newline bitfld.long 0x4 21. "MISR213,Multiple input signature 223192" "0,1" bitfld.long 0x4 20. "MISR212,Multiple input signature 223192" "0,1" newline bitfld.long 0x4 19. "MISR211,Multiple input signature 223192" "0,1" bitfld.long 0x4 18. "MISR210,Multiple input signature 223192" "0,1" newline bitfld.long 0x4 17. "MISR209,Multiple input signature 223192" "0,1" bitfld.long 0x4 16. "MISR208,Multiple input signature 223192" "0,1" newline bitfld.long 0x4 15. "MISR207,Multiple input signature 223192" "0,1" bitfld.long 0x4 14. "MISR206,Multiple input signature 223192" "0,1" newline bitfld.long 0x4 13. "MISR205,Multiple input signature 223192" "0,1" bitfld.long 0x4 12. "MISR204,Multiple input signature 223192" "0,1" newline bitfld.long 0x4 11. "MISR203,Multiple input signature 223192" "0,1" bitfld.long 0x4 10. "MISR202,Multiple input signature 223192" "0,1" newline bitfld.long 0x4 9. "MISR201,Multiple input signature 223192" "0,1" bitfld.long 0x4 8. "MISR200,Multiple input signature 223192" "0,1" newline bitfld.long 0x4 7. "MISR199,Multiple input signature 223192" "0,1" bitfld.long 0x4 6. "MISR198,Multiple input signature 223192" "0,1" newline bitfld.long 0x4 5. "MISR197,Multiple input signature 223192" "0,1" bitfld.long 0x4 4. "MISR196,Multiple input signature 223192" "0,1" newline bitfld.long 0x4 3. "MISR195,Multiple input signature 223192" "0,1" bitfld.long 0x4 2. "MISR194,Multiple input signature 223192" "0,1" newline bitfld.long 0x4 1. "MISR193,Multiple input signature 223192" "0,1" bitfld.long 0x4 0. "MISR192,Multiple input signature 223192" "0,1" line.long 0x8 "UM7_C1,User Multiple Input Signature 7 register" bitfld.long 0x8 31. "MISR255,Multiple input signature 255224" "0,1" bitfld.long 0x8 30. "MISR254,Multiple input signature 255224" "0,1" newline bitfld.long 0x8 29. "MISR253,Multiple input signature 255224" "0,1" bitfld.long 0x8 28. "MISR252,Multiple input signature 255224" "0,1" newline bitfld.long 0x8 27. "MISR251,Multiple input signature 255224" "0,1" bitfld.long 0x8 26. "MISR250,Multiple input signature 255224" "0,1" newline bitfld.long 0x8 25. "MISR249,Multiple input signature 255224" "0,1" bitfld.long 0x8 24. "MISR248,Multiple input signature 255224" "0,1" newline bitfld.long 0x8 23. "MISR247,Multiple input signature 255224" "0,1" bitfld.long 0x8 22. "MISR246,Multiple input signature 255224" "0,1" newline bitfld.long 0x8 21. "MISR245,Multiple input signature 255224" "0,1" bitfld.long 0x8 20. "MISR244,Multiple input signature 255224" "0,1" newline bitfld.long 0x8 19. "MISR243,Multiple input signature 255224" "0,1" bitfld.long 0x8 18. "MISR242,Multiple input signature 255224" "0,1" newline bitfld.long 0x8 17. "MISR241,Multiple input signature 255224" "0,1" bitfld.long 0x8 16. "MISR240,Multiple input signature 255224" "0,1" newline bitfld.long 0x8 15. "MISR239,Multiple input signature 255224" "0,1" bitfld.long 0x8 14. "MISR238,Multiple input signature 255224" "0,1" newline bitfld.long 0x8 13. "MISR237,Multiple input signature 255224" "0,1" bitfld.long 0x8 12. "MISR236,Multiple input signature 255224" "0,1" newline bitfld.long 0x8 11. "MISR235,Multiple input signature 255224" "0,1" bitfld.long 0x8 10. "MISR234,Multiple input signature 255224" "0,1" newline bitfld.long 0x8 9. "MISR233,Multiple input signature 255224" "0,1" bitfld.long 0x8 8. "MISR232,Multiple input signature 255224" "0,1" newline bitfld.long 0x8 7. "MISR231,Multiple input signature 255224" "0,1" bitfld.long 0x8 6. "MISR230,Multiple input signature 255224" "0,1" newline bitfld.long 0x8 5. "MISR229,Multiple input signature 255224" "0,1" bitfld.long 0x8 4. "MISR228,Multiple input signature 255224" "0,1" newline bitfld.long 0x8 3. "MISR227,Multiple input signature 255224" "0,1" bitfld.long 0x8 2. "MISR226,Multiple input signature 255224" "0,1" newline bitfld.long 0x8 1. "MISR225,Multiple input signature 255224" "0,1" bitfld.long 0x8 0. "MISR224,Multiple input signature 255224" "0,1" rgroup.long 0x80++0xF line.long 0x0 "OPP0_C1,Over-program protection 0 register" hexmask.long.word 0x0 16.--29. 1. "LOWOPP,Low address space Over Program Protection" hexmask.long.word 0x0 0.--15. 1. "MIDOPP,Mid address space Over Program Protection" line.long 0x4 "OPP1_C1,Over-program protection 1 register" hexmask.long.word 0x4 0.--15. 1. "HIGHOPP,High address space Over Program Protection" line.long 0x8 "OPP2_C1,Over-program protection 2 register" hexmask.long 0x8 0.--31. 1. "A256KOPP,256K Address Space Block Over Program Protection A256KOPP[31:0]" line.long 0xC "OPP3_C1,Over-program protection 3 register" hexmask.long 0xC 0.--31. 1. "A256KOPP,256K Address space Over Program Protection A256KOPP[63:32]" group.long 0x94++0xB line.long 0x0 "AIC_ADR0_C1,Array integrity check port 0. cluster C1 Tile/column address selection register" hexmask.long 0x0 3.--29. 1. "AIC_ADR0,AIC Tile/column selection register on port 0 cluster C1" line.long 0x4 "AIC_ADR1_C1,Array integrity check port 1. cluster C1 Tile/column address selection register" hexmask.long 0x4 3.--29. 1. "AIC_ADR1,AIC Tile/column selection register on port 1 cluster C1" line.long 0x8 "AIC_RWR_C1,Array integrity check read while read configuration register" hexmask.long.word 0x8 16.--31. 1. "WT_CONF,It stores decimal to binary encoded format the number of fclk_C0 clock cycles in which AIC internal state machine remains on IDLE state ." hexmask.long.word 0x8 0.--15. 1. "RD_CONF,It stores decimal to binary encoded format the number of consecutive internal reads to be executed by AIC internal state machine after flh_rlock_ack_Px_C0 signal assertion coming from PFC. After completion of this task PCM de-asserts.." rgroup.long 0x110++0xF line.long 0x0 "PLOCK0_C1,Program Lock Protection 0 register" hexmask.long.word 0x0 16.--31. 1. "LOWPLOCK,Low address space extended Lock Protection" hexmask.long.word 0x0 0.--15. 1. "MIDPLOCK,Mid address space extended Lock Protection" line.long 0x4 "PLOCK1_C1,Program Lock Protection 1 register" hexmask.long.word 0x4 0.--15. 1. "HIGHPLOCK,High address space Program Lock Protection" line.long 0x8 "PLOCK2_C1,Program Lock Protection 2 register" hexmask.long 0x8 0.--31. 1. "A256KPLOCK,256K High address space Program Lock Protection A256KPLOCK[31:0]" line.long 0xC "PLOCK3_C1,Program Lock protection 3 register" hexmask.long 0xC 0.--31. 1. "A256KPLOCK,256K High address space Program Lock Protection A256KPLOCK[63:32]" rgroup.long 0x134++0x3 line.long 0x0 "ADR_P1R_C1,Address register Port 1 Read" hexmask.long.tbyte 0x0 3.--23. 1. "PADR,Parallel Address" tree.end tree "NVM_2" base ad:0x711C4000 rgroup.long 0x8++0x3 line.long 0x0 "MCRE_C2,Extended Module Configuration Register" hexmask.long.byte 0x0 24.--30. 1. "N256K,Number of 128 KB and 256 KB blocks in the 256K space" bitfld.long 0x0 21.--23. "N64KH,Number of 64 KB blocks in high space" "0: Zero 64 KB blocks.,1: Two 64 KB blocks.,2: Four 64 KB blocks.,3: Six 64 KB blocks.,4: Eight 64 KB blocks.,?,?,?" newline bitfld.long 0x0 19.--20. "N32KH,Number of 32 KB blocks in high space" "0: Zero 32 KB blocks.,1: Two 32 KB blocks.,2: Four 32 KB blocks.,?" bitfld.long 0x0 16.--18. "N16KH,Number of 16 KB blocks in high space" "0: Zero 16 KB blocks.,1: Two 16 KB blocks.,2: Four 16 KB blocks.,3: Six 16 KB blocks.,4: Eight 16 KB blocks.,?,?,?" newline bitfld.long 0x0 13.--15. "N64KM,Number of 64 KB blocks in mid space" "0: Zero 64 KB blocks.,1: Two 64 KB blocks.,2: Four 64 KB blocks.,3: Six 64 KB blocks.,4: Eight 64 KB blocks.,?,?,?" bitfld.long 0x0 11.--12. "N32KM,Number of 32 KB blocks in mid space" "0: Zero 32 KB blocks.,1: Two 32 KB blocks.,2: Four 32 KB blocks.,?" newline bitfld.long 0x0 8.--10. "N16KM,Number of 16 KB blocks in mid space" "0: Zero 16 KB blocks.,1: Two 16 KB blocks.,2: Four 16 KB blocks.,3: Six 16 KB blocks.,4: Eight 16 KB blocks.,?,?,?" bitfld.long 0x0 5.--7. "N64KL,Number of 64 KB blocks in low space" "0: Zero 64 KB blocks.,1: Two 64 KB blocks.,2: Four 64 KB blocks.,3: Six 64 KB blocks.,4: Eight 64 KB blocks.,?,?,?" newline bitfld.long 0x0 3.--4. "N32KL,Number of 32 KB blocks in low space" "0: Zero 32 KB blocks.,1: Two 32 KB blocks.,2: Four 32 KB blocks.,3: Three 32 KB blocks." bitfld.long 0x0 0.--2. "N16KL,Number of 16 KB blocks in low space" "0: Zero 16 KB blocks.,1: Two 16 KB blocks.,2: Four 16 KB blocks.,3: Six 16 KB blocks.,4: Eight 16 KB blocks.,5: Three 16 KB blocks.,?,?" group.long 0x10++0xF line.long 0x0 "LOCK0_C2,Lock 0 register" hexmask.long.word 0x0 16.--29. 1. "LOWLOCK,Low address space block lock" hexmask.long.word 0x0 0.--15. 1. "MIDLOCK,Mid address space block lock" line.long 0x4 "LOCK1_C2,Lock 1 register" hexmask.long.word 0x4 0.--15. 1. "HIGHLOCK,High address space block lock" line.long 0x8 "LOCK2_C2,Lock 2 Register" hexmask.long 0x8 0.--31. 1. "A256KLOCK,256K address space block lock A256KLOCK[31:0]" line.long 0xC "LOCK3_C2,Lock 3 Register" hexmask.long 0xC 0.--31. 1. "A256KLOCK,256K address space block lock A256KLOCK[63:32]" group.long 0x38++0x13 line.long 0x0 "SEL0_C2,Select 0 register" hexmask.long.word 0x0 16.--29. 1. "LOWSEL,Low address space block Select" hexmask.long.word 0x0 0.--15. 1. "MIDSEL,Mid address space block Select" line.long 0x4 "SEL1_C2,Select 1 register" hexmask.long.word 0x4 0.--15. 1. "HIGHSEL,High/Data address space block Select 1" line.long 0x8 "SEL2_C2,Select 2 register" hexmask.long 0x8 0.--31. 1. "A256KSEL,256K address space block select A256KSEL[31:0]" line.long 0xC "SEL3_C2,Select 3 register" hexmask.long 0xC 0.--31. 1. "A256KSEL,256K address space block select A256KSEL[63:32]" line.long 0x10 "MCR_P1R_C2,Module Configuration Register Port 1 Read" bitfld.long 0x10 30. "PRRE,Parallel Read Reference Error" "0: Reads are occurring normally,1: A Read Reference Error occurred during a.." bitfld.long 0x10 29. "PAEE,Parallel Address Encode Error" "0: Reads are occurring normally,1: An Address Encode Error occurred during a.." newline bitfld.long 0x10 28. "PEEE,Parallel EDC after ECC Error" "0: Reads are occurring normally,1: A previous Read may have been corrupted" hexmask.long.byte 0x10 24.--27. 1. "PDWEE,Parallel Double Word Uncorrectable ECC Error" newline bitfld.long 0x10 20. "PSBC1,Parallel Single Bit Correction 1" "0: Reads are occurring normally,1: An ECC Single Error occurred and was corrected.." bitfld.long 0x10 15. "PEER,Parallel ECC Event Error" "0: Reads are occurring normally,1: An ECC Double Error occurred during a previous.." newline bitfld.long 0x10 14. "PRWE,Parallel Read-while-Write event Error" "0: Reads are occurring normally,1: A RWW Error occurred during a previous Read" bitfld.long 0x10 13. "PSBC,Parallel Single Bit Correction" "0: Reads are occurring normally,1: An ECC Single Error occurred and was corrected.." rgroup.long 0x50++0x3 line.long 0x0 "ADR_C2,Address register" bitfld.long 0x0 31. "SAD,Test Address" "0,1" hexmask.long.tbyte 0x0 3.--23. 1. "ADDR,Address" group.long 0x54++0x3 line.long 0x0 "UT0_C2,User Test 0 register" bitfld.long 0x0 31. "UTE,User Test Enable" "0,1" bitfld.long 0x0 30. "SBCE,Double Bit Correction Enable" "0,1" newline bitfld.long 0x0 28. "CLCK,It enables embedded column signature check and flagging during Full columns AIC or MR execution." "0: Check is enabled,1: Check is disabled" bitfld.long 0x0 23. "SBCE1,Single Bit Correction Enable" "0,1" newline bitfld.long 0x0 22. "AICV,Vertical array integrity check enabled" "0: AIC single column processing enabled,1: AIC single column processing disabled whole Tile.." bitfld.long 0x0 20. "ECRC,Array integrity check self check signature error" "0: Signature check passed,1: Signature check failed" newline bitfld.long 0x0 19. "AICV_ADR,Vertical array integrity check address register selection" "0: AIC on Tile/column selected by AIC_ADR0_C2,1: AIC on Tile/column selected by AIC_ADR1_C2" bitfld.long 0x0 18. "CPR,Customer Programmable Read Voltage and Reference Detection" "0: Customer Programmable Read Voltage and Reference..,1: Customer Programmable Read Voltage and Reference.." newline bitfld.long 0x0 17. "CPA,Customer Programmable Address Encode Detection" "0: Customer Programmable Address Encode Detection..,1: Customer Programmable Address Encode Detection.." bitfld.long 0x0 16. "CPE,Customer Programmable EDC after ECC Detection" "0: Customer Programmable EDC after ECC Detection..,1: Customer Programmable EDC after ECC Detection.." newline bitfld.long 0x0 15. "AERE,AIC ecc error reporting" "0: AIC Ecc error reporting disabled,1: AIC Ecc error reporting enabled" bitfld.long 0x0 9. "NAIBP,Next Array Integrity Break Point" "0: Array Integrity-Vth Distribution is not..,1: Array Integrity-Vth Distribution is at a break.." newline bitfld.long 0x0 8. "AIBPE,Array Integrity Break Point Enable" "0: Array Integrity breakpoints are not enabled,1: Array Integrity breakpoints are enabled during.." bitfld.long 0x0 6. "AISUS,Array Integrity Suspend" "0: Array Integrity sequence not suspended,1: Array Integrity sequence is suspended" newline bitfld.long 0x0 5. "MRE,Margin Read Enable" "0: Margin Read is not enabled,1: Margin Read is enabled" bitfld.long 0x0 4. "MRV,Margin Read Value" "0: Zero's margin reads are requested (if MRE=1),1: One's margin reads are requested (if MRE=1)" newline bitfld.long 0x0 3. "MRB,Blank Margin Read Value" "0: Margin reads qualified by MRV are requested (if..,?" bitfld.long 0x0 2. "AIS,Array Integrity Sequence" "0: Array Integrity sequence is proprietary sequence,1: Array Integrity sequence is sequential" newline bitfld.long 0x0 1. "AIE,Array Integrity Enable" "0: Array Integrity Check and Margin Read and are..,1: Array Integrity Check and Margin Read are enabled" bitfld.long 0x0 0. "AID,Array Integrity Done" "0: Array Integrity Check is on-going,1: Array Integrity Check is done" rgroup.long 0x58++0x1F line.long 0x0 "UM0_C2,User Multiple Input Signature 0 register" bitfld.long 0x0 31. "MISR31,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 30. "MISR30,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 29. "MISR29,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 28. "MISR28,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 27. "MISR27,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 26. "MISR26,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 25. "MISR25,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 24. "MISR24,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 23. "MISR23,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 22. "MISR22,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 21. "MISR21,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 20. "MISR20,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 19. "MISR19,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 18. "MISR18,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 17. "MISR17,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 16. "MISR16,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 15. "MISR15,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 14. "MISR14,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 13. "MISR13,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 12. "MISR12,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 11. "MISR11,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 10. "MISR10,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 9. "MISR9,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 8. "MISR8,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 7. "MISR7,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 6. "MISR6,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 5. "MISR5,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 4. "MISR4,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 3. "MISR3,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 2. "MISR2,Multiple input signature 310x0:" "0,1" newline bitfld.long 0x0 1. "MISR1,Multiple input signature 310x0:" "0,1" bitfld.long 0x0 0. "MISR0,Multiple input signature 310x0:" "0,1" line.long 0x4 "UM1_C2,User Multiple Input Signature 1 register" bitfld.long 0x4 31. "MISR63,Multiple input signature 6332" "0,1" bitfld.long 0x4 30. "MISR62,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 29. "MISR61,Multiple input signature 6332" "0,1" bitfld.long 0x4 28. "MISR60,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 27. "MISR59,Multiple input signature 6332" "0,1" bitfld.long 0x4 26. "MISR58,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 25. "MISR57,Multiple input signature 6332" "0,1" bitfld.long 0x4 24. "MISR56,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 23. "MISR55,Multiple input signature 6332" "0,1" bitfld.long 0x4 22. "MISR54,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 21. "MISR53,Multiple input signature 6332" "0,1" bitfld.long 0x4 20. "MISR52,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 19. "MISR51,Multiple input signature 6332" "0,1" bitfld.long 0x4 18. "MISR50,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 17. "MISR49,Multiple input signature 6332" "0,1" bitfld.long 0x4 16. "MISR48,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 15. "MISR47,Multiple input signature 6332" "0,1" bitfld.long 0x4 14. "MISR46,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 13. "MISR45,Multiple input signature 6332" "0,1" bitfld.long 0x4 12. "MISR44,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 11. "MISR43,Multiple input signature 6332" "0,1" bitfld.long 0x4 10. "MISR42,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 9. "MISR41,Multiple input signature 6332" "0,1" bitfld.long 0x4 8. "MISR40,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 7. "MISR39,Multiple input signature 6332" "0,1" bitfld.long 0x4 6. "MISR38,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 5. "MISR37,Multiple input signature 6332" "0,1" bitfld.long 0x4 4. "MISR36,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 3. "MISR35,Multiple input signature 6332" "0,1" bitfld.long 0x4 2. "MISR34,Multiple input signature 6332" "0,1" newline bitfld.long 0x4 1. "MISR33,Multiple input signature 6332" "0,1" bitfld.long 0x4 0. "MISR32,Multiple input signature 6332" "0,1" line.long 0x8 "UM2_C2,User Multiple Input Signature 2 register" bitfld.long 0x8 31. "MISR95,Multiple input signature 9564" "0,1" bitfld.long 0x8 30. "MISR94,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 29. "MISR93,Multiple input signature 9564" "0,1" bitfld.long 0x8 28. "MISR92,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 27. "MISR91,Multiple input signature 9564" "0,1" bitfld.long 0x8 26. "MISR90,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 25. "MISR89,Multiple input signature 9564" "0,1" bitfld.long 0x8 24. "MISR88,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 23. "MISR87,Multiple input signature 9564" "0,1" bitfld.long 0x8 22. "MISR86,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 21. "MISR85,Multiple input signature 9564" "0,1" bitfld.long 0x8 20. "MISR84,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 19. "MISR83,Multiple input signature 9564" "0,1" bitfld.long 0x8 18. "MISR82,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 17. "MISR81,Multiple input signature 9564" "0,1" bitfld.long 0x8 16. "MISR80,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 15. "MISR79,Multiple input signature 9564" "0,1" bitfld.long 0x8 14. "MISR78,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 13. "MISR77,Multiple input signature 9564" "0,1" bitfld.long 0x8 12. "MISR76,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 11. "MISR75,Multiple input signature 9564" "0,1" bitfld.long 0x8 10. "MISR74,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 9. "MISR73,Multiple input signature 9564" "0,1" bitfld.long 0x8 8. "MISR72,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 7. "MISR71,Multiple input signature 9564" "0,1" bitfld.long 0x8 6. "MISR70,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 5. "MISR69,Multiple input signature 9564" "0,1" bitfld.long 0x8 4. "MISR68,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 3. "MISR67,Multiple input signature 9564" "0,1" bitfld.long 0x8 2. "MISR66,Multiple input signature 9564" "0,1" newline bitfld.long 0x8 1. "MISR65,Multiple input signature 9564" "0,1" bitfld.long 0x8 0. "MISR64,Multiple input signature 9564" "0,1" line.long 0xC "UM3_C2,User Multiple Input Signature 3 register" bitfld.long 0xC 31. "MISR127,Multiple input signature 12796" "0,1" bitfld.long 0xC 30. "MISR126,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 29. "MISR125,Multiple input signature 12796" "0,1" bitfld.long 0xC 28. "MISR124,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 27. "MISR123,Multiple input signature 12796" "0,1" bitfld.long 0xC 26. "MISR122,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 25. "MISR121,Multiple input signature 12796" "0,1" bitfld.long 0xC 24. "MISR120,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 23. "MISR119,Multiple input signature 12796" "0,1" bitfld.long 0xC 22. "MISR118,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 21. "MISR117,Multiple input signature 12796" "0,1" bitfld.long 0xC 20. "MISR116,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 19. "MISR115,Multiple input signature 12796" "0,1" bitfld.long 0xC 18. "MISR114,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 17. "MISR113,Multiple input signature 12796" "0,1" bitfld.long 0xC 16. "MISR112,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 15. "MISR111,Multiple input signature 12796" "0,1" bitfld.long 0xC 14. "MISR110,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 13. "MISR109,Multiple input signature 12796" "0,1" bitfld.long 0xC 12. "MISR108,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 11. "MISR107,Multiple input signature 12796" "0,1" bitfld.long 0xC 10. "MISR106,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 9. "MISR105,Multiple input signature 12796" "0,1" bitfld.long 0xC 8. "MISR104,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 7. "MISR103,Multiple input signature 12796" "0,1" bitfld.long 0xC 6. "MISR102,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 5. "MISR101,Multiple input signature 12796" "0,1" bitfld.long 0xC 4. "MISR100,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 3. "MISR99,Multiple input signature 12796" "0,1" bitfld.long 0xC 2. "MISR98,Multiple input signature 12796" "0,1" newline bitfld.long 0xC 1. "MISR97,Multiple input signature 12796" "0,1" bitfld.long 0xC 0. "MISR96,Multiple input signature 12796" "0,1" line.long 0x10 "UM4_C2,User Multiple Input Signature 4 register" bitfld.long 0x10 31. "MISR159,Multiple input signature 159128" "0,1" bitfld.long 0x10 30. "MISR158,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 29. "MISR157,Multiple input signature 159128" "0,1" bitfld.long 0x10 28. "MISR156,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 27. "MISR155,Multiple input signature 159128" "0,1" bitfld.long 0x10 26. "MISR154,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 25. "MISR153,Multiple input signature 159128" "0,1" bitfld.long 0x10 24. "MISR152,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 23. "MISR151,Multiple input signature 159128" "0,1" bitfld.long 0x10 22. "MISR150,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 21. "MISR149,Multiple input signature 159128" "0,1" bitfld.long 0x10 20. "MISR148,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 19. "MISR147,Multiple input signature 159128" "0,1" bitfld.long 0x10 18. "MISR146,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 17. "MISR145,Multiple input signature 159128" "0,1" bitfld.long 0x10 16. "MISR144,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 15. "MISR143,Multiple input signature 159128" "0,1" bitfld.long 0x10 14. "MISR142,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 13. "MISR141,Multiple input signature 159128" "0,1" bitfld.long 0x10 12. "MISR140,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 11. "MISR139,Multiple input signature 159128" "0,1" bitfld.long 0x10 10. "MISR138,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 9. "MISR137,Multiple input signature 159128" "0,1" bitfld.long 0x10 8. "MISR136,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 7. "MISR135,Multiple input signature 159128" "0,1" bitfld.long 0x10 6. "MISR134,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 5. "MISR133,Multiple input signature 159128" "0,1" bitfld.long 0x10 4. "MISR132,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 3. "MISR131,Multiple input signature 159128" "0,1" bitfld.long 0x10 2. "MISR130,Multiple input signature 159128" "0,1" newline bitfld.long 0x10 1. "MISR129,Multiple input signature 159128" "0,1" bitfld.long 0x10 0. "MISR128,Multiple input signature 159128" "0,1" line.long 0x14 "UM5_C2,User Multiple Input Signature 5 register" bitfld.long 0x14 31. "MISR191,Multiple input signature 191160" "0,1" bitfld.long 0x14 30. "MISR190,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 29. "MISR189,Multiple input signature 191160" "0,1" bitfld.long 0x14 28. "MISR188,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 27. "MISR187,Multiple input signature 191160" "0,1" bitfld.long 0x14 26. "MISR186,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 25. "MISR185,Multiple input signature 191160" "0,1" bitfld.long 0x14 24. "MISR184,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 23. "MISR183,Multiple input signature 191160" "0,1" bitfld.long 0x14 22. "MISR182,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 21. "MISR181,Multiple input signature 191160" "0,1" bitfld.long 0x14 20. "MISR180,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 19. "MISR179,Multiple input signature 191160" "0,1" bitfld.long 0x14 18. "MISR178,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 17. "MISR177,Multiple input signature 191160" "0,1" bitfld.long 0x14 16. "MISR176,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 15. "MISR175,Multiple input signature 191160" "0,1" bitfld.long 0x14 14. "MISR174,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 13. "MISR173,Multiple input signature 191160" "0,1" bitfld.long 0x14 12. "MISR172,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 11. "MISR171,Multiple input signature 191160" "0,1" bitfld.long 0x14 10. "MISR170,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 9. "MISR169,Multiple input signature 191160" "0,1" bitfld.long 0x14 8. "MISR168,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 7. "MISR167,Multiple input signature 191160" "0,1" bitfld.long 0x14 6. "MISR166,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 5. "MISR165,Multiple input signature 191160" "0,1" bitfld.long 0x14 4. "MISR164,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 3. "MISR163,Multiple input signature 191160" "0,1" bitfld.long 0x14 2. "MISR162,Multiple input signature 191160" "0,1" newline bitfld.long 0x14 1. "MISR161,Multiple input signature 191160" "0,1" bitfld.long 0x14 0. "MISR160,Multiple input signature 191160" "0,1" line.long 0x18 "UM6_C2,User Multiple Input Signature 6 register" bitfld.long 0x18 31. "MISR223,Multiple input signature 223192" "0,1" bitfld.long 0x18 30. "MISR222,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 29. "MISR221,Multiple input signature 223192" "0,1" bitfld.long 0x18 28. "MISR220,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 27. "MISR219,Multiple input signature 223192" "0,1" bitfld.long 0x18 26. "MISR218,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 25. "MISR217,Multiple input signature 223192" "0,1" bitfld.long 0x18 24. "MISR216,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 23. "MISR215,Multiple input signature 223192" "0,1" bitfld.long 0x18 22. "MISR214,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 21. "MISR213,Multiple input signature 223192" "0,1" bitfld.long 0x18 20. "MISR212,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 19. "MISR211,Multiple input signature 223192" "0,1" bitfld.long 0x18 18. "MISR210,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 17. "MISR209,Multiple input signature 223192" "0,1" bitfld.long 0x18 16. "MISR208,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 15. "MISR207,Multiple input signature 223192" "0,1" bitfld.long 0x18 14. "MISR206,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 13. "MISR205,Multiple input signature 223192" "0,1" bitfld.long 0x18 12. "MISR204,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 11. "MISR203,Multiple input signature 223192" "0,1" bitfld.long 0x18 10. "MISR202,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 9. "MISR201,Multiple input signature 223192" "0,1" bitfld.long 0x18 8. "MISR200,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 7. "MISR199,Multiple input signature 223192" "0,1" bitfld.long 0x18 6. "MISR198,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 5. "MISR197,Multiple input signature 223192" "0,1" bitfld.long 0x18 4. "MISR196,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 3. "MISR195,Multiple input signature 223192" "0,1" bitfld.long 0x18 2. "MISR194,Multiple input signature 223192" "0,1" newline bitfld.long 0x18 1. "MISR193,Multiple input signature 223192" "0,1" bitfld.long 0x18 0. "MISR192,Multiple input signature 223192" "0,1" line.long 0x1C "UM7_C2,User Multiple Input Signature 7 register" bitfld.long 0x1C 31. "MISR255,Multiple input signature 255224" "0,1" bitfld.long 0x1C 30. "MISR254,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 29. "MISR253,Multiple input signature 255224" "0,1" bitfld.long 0x1C 28. "MISR252,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 27. "MISR251,Multiple input signature 255224" "0,1" bitfld.long 0x1C 26. "MISR250,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 25. "MISR249,Multiple input signature 255224" "0,1" bitfld.long 0x1C 24. "MISR248,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 23. "MISR247,Multiple input signature 255224" "0,1" bitfld.long 0x1C 22. "MISR246,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 21. "MISR245,Multiple input signature 255224" "0,1" bitfld.long 0x1C 20. "MISR244,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 19. "MISR243,Multiple input signature 255224" "0,1" bitfld.long 0x1C 18. "MISR242,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 17. "MISR241,Multiple input signature 255224" "0,1" bitfld.long 0x1C 16. "MISR240,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 15. "MISR239,Multiple input signature 255224" "0,1" bitfld.long 0x1C 14. "MISR238,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 13. "MISR237,Multiple input signature 255224" "0,1" bitfld.long 0x1C 12. "MISR236,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 11. "MISR235,Multiple input signature 255224" "0,1" bitfld.long 0x1C 10. "MISR234,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 9. "MISR233,Multiple input signature 255224" "0,1" bitfld.long 0x1C 8. "MISR232,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 7. "MISR231,Multiple input signature 255224" "0,1" bitfld.long 0x1C 6. "MISR230,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 5. "MISR229,Multiple input signature 255224" "0,1" bitfld.long 0x1C 4. "MISR228,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 3. "MISR227,Multiple input signature 255224" "0,1" bitfld.long 0x1C 2. "MISR226,Multiple input signature 255224" "0,1" newline bitfld.long 0x1C 1. "MISR225,Multiple input signature 255224" "0,1" bitfld.long 0x1C 0. "MISR224,Multiple input signature 255224" "0,1" rgroup.long 0x80++0xF line.long 0x0 "OPP0_C2,Over-program protection 0 register" hexmask.long.word 0x0 16.--29. 1. "LOWOPP,Low address space Over Program Protection" hexmask.long.word 0x0 0.--15. 1. "MIDOPP,Mid address space Over Program Protection" line.long 0x4 "OPP1_C2,Over-program protection 1 register" hexmask.long.word 0x4 0.--15. 1. "HIGHOPP,High address space Over Program Protection" line.long 0x8 "OPP2_C2,Over-program protection 2 register" hexmask.long 0x8 0.--31. 1. "A256KOPP,256K Address Space Block Over Program Protection A256KOPP[31:0]" line.long 0xC "OPP3_C2,Over-program protection 3 register" hexmask.long 0xC 0.--31. 1. "A256KOPP,256K Address space Over Program Protection A256KOPP[63:32]" group.long 0x94++0xB line.long 0x0 "AIC_ADR0_C2,Array integrity check port 0. cluster C2 Tile/column address selection register" hexmask.long 0x0 3.--29. 1. "AIC_ADR0,AIC Tile/column selection register on port 0 cluster C1" line.long 0x4 "AIC_ADR1_C2,Array integrity check port 1. cluster C2 Tile/column address selection register" hexmask.long 0x4 3.--29. 1. "AIC_ADR1,AIC Tile/column selection register on port 1 cluster C1" line.long 0x8 "AIC_RWR_C2,Array integrity check read while read configuration register" hexmask.long.word 0x8 16.--31. 1. "WT_CONF,It stores decimal to binary encoded format the number of fclk_C0 clock cycles in which AIC internal state machine remains on IDLE state." hexmask.long.word 0x8 0.--15. 1. "RD_CONF,It stores decimal to binary encoded format the number of consecutive internal reads to be executed by AIC internal state machine after flh_rlock_ack_Px_C0 signal assertion coming from PFC. After completion of this task PCM de-asserts.." rgroup.long 0x110++0xF line.long 0x0 "PLOCK0_C2,Program Lock Protection 0 register" hexmask.long.word 0x0 16.--31. 1. "LOWPLOCK,Low address space extended Lock Protection" hexmask.long.word 0x0 0.--15. 1. "MIDPLOCK,Mid address space extended Lock Protection" line.long 0x4 "PLOCK1_C2,Program Lock Protection 1 register" hexmask.long.word 0x4 0.--15. 1. "HIGHPLOCK,High address space Program Lock Protection" line.long 0x8 "PLOCK2_C2,Program Lock Protection 2 register" hexmask.long 0x8 0.--31. 1. "A256KPLOCK,256K High address space Program Lock Protection A256KPLOCK[31:0]" line.long 0xC "PLOCK3_C2,Program Lock protection 3 register" hexmask.long 0xC 0.--31. 1. "A256KPLOCK,256K High address space Program Lock Protection A256KPLOCK[63:32]" rgroup.long 0x134++0x3 line.long 0x0 "ADR_P1R_C2,Address register Port 1 Read" hexmask.long.tbyte 0x0 3.--23. 1. "PADR,Parallel Address" tree.end tree "NVM_CTRL_0_0" base ad:0x71178000 group.long 0x0++0x3 line.long 0x0 "PFCR1,NVM PC configuration register 1" hexmask.long.byte 0x0 8.--12. 1. "RWSC,Read Wait State Control" group.long 0x8++0x3 line.long 0x0 "PFCR3,NVM PC configuration register 3" bitfld.long 0x0 15. "BCS_DIS,BCS_DIS" "0,1" rgroup.long 0xC++0x3 line.long 0x0 "PFSR,NVM PC Status register" bitfld.long 0x0 0. "NVMPCFLHBUSY,NVMPCFLHBUSY" "0,1" group.long 0x10++0xB line.long 0x0 "FLTENA,NVM PC fault latching enable register" bitfld.long 0x0 10. "NVMCTED,NVM Code triple ECC error" "0,1" bitfld.long 0x0 9. "NVMCDBC,NVM Code double ECC error" "0,1" bitfld.long 0x0 8. "NVMCSBC,NVM Code single ECC error" "0,1" bitfld.long 0x0 7. "NVMDTED,NVM Data triple ECC error" "0,1" bitfld.long 0x0 6. "NVMDDBC,NVM Data double ECC error" "0,1" bitfld.long 0x0 5. "NVMDSBC,NVM Data single ECC error" "0,1" bitfld.long 0x0 4. "NVMENCE,NVM Address encoding error" "0,1" newline bitfld.long 0x0 3. "NVMCEDC,NVM Code EDC error" "0,1" bitfld.long 0x0 2. "NVMDEDC,NVM Data EDC error" "0,1" bitfld.long 0x0 1. "NVMPCENC,NVMPC Address encoding error" "0,1" bitfld.long 0x0 0. "NVMPCENSWAP,NVMPC SWAP Address error" "0,1" line.long 0x4 "FLTFRC,NVM PC fault forcing register" bitfld.long 0x4 10. "NVMCTED,NVM Code triple ECC error" "0,1" bitfld.long 0x4 9. "NVMCDBC,NVM Code double ECC error" "0,1" bitfld.long 0x4 8. "NVMCSBC,NVM Code single ECC error" "0,1" bitfld.long 0x4 7. "NVMDTED,NVM Data triple ECC error" "0,1" bitfld.long 0x4 6. "NVMDDBC,NVM Data double ECC error" "0,1" bitfld.long 0x4 5. "NVMDSBC,NVM Data single ECC error" "0,1" bitfld.long 0x4 4. "NVMENCE,NVM Address encoding error" "0,1" newline bitfld.long 0x4 3. "NVMCEDC,NVM Code EDC error" "0,1" bitfld.long 0x4 2. "NVMDEDC,NVM Data EDC error" "0,1" bitfld.long 0x4 1. "NVMPCENC,NVMPC Address encoding error" "0,1" bitfld.long 0x4 0. "NVMPCENSWAP,NVMPC SWAP Address error" "0,1" line.long 0x8 "FLTSCR,NVM PC fault status and clear register" bitfld.long 0x8 10. "NVMCTED,NVM Code triple ECC error" "0,1" bitfld.long 0x8 9. "NVMCDBC,NVM Code double ECC error" "0,1" bitfld.long 0x8 8. "NVMCSBC,NVM Code triple ECC error" "0,1" bitfld.long 0x8 7. "NVMDTED,NVM Data triple ECC error" "0,1" bitfld.long 0x8 6. "NVMDDBC,NVM Data double ECC error" "0,1" bitfld.long 0x8 5. "NVMDSBC,NVM Data single ECC error" "0,1" bitfld.long 0x8 4. "NVMENCE,NVM Address encoding error" "0,1" newline bitfld.long 0x8 3. "NVMCEDC,NVM Code EDC error" "0,1" bitfld.long 0x8 2. "NVMDEDC,NVM Data EDC error" "0,1" bitfld.long 0x8 1. "NVMPCENC,NVMPC Address encoding error" "0,1" bitfld.long 0x8 0. "NVMPCENSWAP,NVMPC SWAP Address error" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "FLTADR,NVM PC fault address register" hexmask.long 0x0 0.--31. 1. "FADR,Fault Address" rgroup.long 0x310++0x17 line.long 0x0 "PFCMC,NVM PC cache miss count register" hexmask.long 0x0 0.--31. 1. "SCMCNT,Cache miss count [31:0]" line.long 0x4 "PFCMOC,NVM PC cache miss overflow counter register" hexmask.long 0x4 0.--31. 1. "SCMOCNT,Cache miss count [63:32]" line.long 0x8 "PFCHC,NVM PC cache hit counter register" hexmask.long 0x8 0.--31. 1. "SCHCNT,Cache hit count [31:0]" line.long 0xC "PFCHOC,NVM PC cache hit overflow counter register" hexmask.long 0xC 0.--31. 1. "SCHOCNT,Cache hit count [63:32]" line.long 0x10 "PFFHC,NVM PC FIFO hit counter" hexmask.long 0x10 0.--31. 1. "PFFHCNT,FIFO hit count [0:31]" line.long 0x14 "PFFHOC,NVM PC FIFO hit overflow counter register" hexmask.long 0x14 0.--31. 1. "PFFHOCNT,FIFO Hit Overflow Count [32:63]" rgroup.long 0x330++0xF line.long 0x0 "PFPFC,NVM PC Prefetch Buffer Counter register" hexmask.long 0x0 0.--31. 1. "PFPFCNT,Prefetch access count [31:0]" line.long 0x4 "PFPFOC,NVM PC Prefetch Buffer Overflow Counter register" hexmask.long 0x4 0.--31. 1. "PFPFOCNT,Prefetch access count [63:32]" line.long 0x8 "PFPFHC,NVM PC Prefetch Buffer Hit Counter register" hexmask.long 0x8 0.--31. 1. "PFPFHCCNT,Prefetch buffer hit count [31:0]" line.long 0xC "PFPFHOC,NVM PC Prefetch Buffer Hit Overflow Counter register" hexmask.long 0xC 0.--31. 1. "PFPFHOCCNT,Prefetch buffer hit count [63:32]" tree.end tree "NVM_CTRL_0_1" base ad:0x7117C000 group.long 0x0++0x3 line.long 0x0 "PFCR1,NVM PC configuration register 1" hexmask.long.byte 0x0 8.--12. 1. "RWSC,Read Wait State Control" group.long 0x8++0x3 line.long 0x0 "PFCR3,NVM PC configuration register 3" bitfld.long 0x0 15. "BCS_DIS,BCS_DIS" "0,1" rgroup.long 0xC++0x3 line.long 0x0 "PFSR,NVM PC Status register" bitfld.long 0x0 0. "NVMPCFLHBUSY,NVMPCFLHBUSY" "0,1" group.long 0x10++0xB line.long 0x0 "FLTENA,NVM PC fault latching enable register" bitfld.long 0x0 10. "NVMCTED,NVM Code triple ECC error" "0,1" bitfld.long 0x0 9. "NVMCDBC,NVM Code double ECC error" "0,1" bitfld.long 0x0 8. "NVMCSBC,NVM Code single ECC error" "0,1" bitfld.long 0x0 7. "NVMDTED,NVM Data triple ECC error" "0,1" bitfld.long 0x0 6. "NVMDDBC,NVM Data double ECC error" "0,1" bitfld.long 0x0 5. "NVMDSBC,NVM Data single ECC error" "0,1" bitfld.long 0x0 4. "NVMENCE,NVM Address encoding error" "0,1" newline bitfld.long 0x0 3. "NVMCEDC,NVM Code EDC error" "0,1" bitfld.long 0x0 2. "NVMDEDC,NVM Data EDC error" "0,1" bitfld.long 0x0 1. "NVMPCENC,NVMPC Address encoding error" "0,1" bitfld.long 0x0 0. "NVMPCENSWAP,NVMPC SWAP Address error" "0,1" line.long 0x4 "FLTFRC,NVM PC fault forcing register" bitfld.long 0x4 10. "NVMCTED,NVM Code triple ECC error" "0,1" bitfld.long 0x4 9. "NVMCDBC,NVM Code double ECC error" "0,1" bitfld.long 0x4 8. "NVMCSBC,NVM Code single ECC error" "0,1" bitfld.long 0x4 7. "NVMDTED,NVM Data triple ECC error" "0,1" bitfld.long 0x4 6. "NVMDDBC,NVM Data double ECC error" "0,1" bitfld.long 0x4 5. "NVMDSBC,NVM Data single ECC error" "0,1" bitfld.long 0x4 4. "NVMENCE,NVM Address encoding error" "0,1" newline bitfld.long 0x4 3. "NVMCEDC,NVM Code EDC error" "0,1" bitfld.long 0x4 2. "NVMDEDC,NVM Data EDC error" "0,1" bitfld.long 0x4 1. "NVMPCENC,NVMPC Address encoding error" "0,1" bitfld.long 0x4 0. "NVMPCENSWAP,NVMPC SWAP Address error" "0,1" line.long 0x8 "FLTSCR,NVM PC fault status and clear register" bitfld.long 0x8 10. "NVMCTED,NVM Code triple ECC error" "0,1" bitfld.long 0x8 9. "NVMCDBC,NVM Code double ECC error" "0,1" bitfld.long 0x8 8. "NVMCSBC,NVM Code triple ECC error" "0,1" bitfld.long 0x8 7. "NVMDTED,NVM Data triple ECC error" "0,1" bitfld.long 0x8 6. "NVMDDBC,NVM Data double ECC error" "0,1" bitfld.long 0x8 5. "NVMDSBC,NVM Data single ECC error" "0,1" bitfld.long 0x8 4. "NVMENCE,NVM Address encoding error" "0,1" newline bitfld.long 0x8 3. "NVMCEDC,NVM Code EDC error" "0,1" bitfld.long 0x8 2. "NVMDEDC,NVM Data EDC error" "0,1" bitfld.long 0x8 1. "NVMPCENC,NVMPC Address encoding error" "0,1" bitfld.long 0x8 0. "NVMPCENSWAP,NVMPC SWAP Address error" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "FLTADR,NVM PC fault address register" hexmask.long 0x0 0.--31. 1. "FADR,Fault Address" rgroup.long 0x310++0x17 line.long 0x0 "PFCMC,NVM PC cache miss count register" hexmask.long 0x0 0.--31. 1. "SCMCNT,Cache miss count [31:0]" line.long 0x4 "PFCMOC,NVM PC cache miss overflow counter register" hexmask.long 0x4 0.--31. 1. "SCMOCNT,Cache miss count [63:32]" line.long 0x8 "PFCHC,NVM PC cache hit counter register" hexmask.long 0x8 0.--31. 1. "SCHCNT,Cache hit count [31:0]" line.long 0xC "PFCHOC,NVM PC cache hit overflow counter register" hexmask.long 0xC 0.--31. 1. "SCHOCNT,Cache hit count [63:32]" line.long 0x10 "PFFHC,NVM PC FIFO hit counter" hexmask.long 0x10 0.--31. 1. "PFFHCNT,FIFO hit count [0:31]" line.long 0x14 "PFFHOC,NVM PC FIFO hit overflow counter register" hexmask.long 0x14 0.--31. 1. "PFFHOCNT,FIFO Hit Overflow Count [32:63]" rgroup.long 0x330++0xF line.long 0x0 "PFPFC,NVM PC Prefetch Buffer Counter register" hexmask.long 0x0 0.--31. 1. "PFPFCNT,Prefetch access count [31:0]" line.long 0x4 "PFPFOC,NVM PC Prefetch Buffer Overflow Counter register" hexmask.long 0x4 0.--31. 1. "PFPFOCNT,Prefetch access count [63:32]" line.long 0x8 "PFPFHC,NVM PC Prefetch Buffer Hit Counter register" hexmask.long 0x8 0.--31. 1. "PFPFHCCNT,Prefetch buffer hit count [31:0]" line.long 0xC "PFPFHOC,NVM PC Prefetch Buffer Hit Overflow Counter register" hexmask.long 0xC 0.--31. 1. "PFPFHOCCNT,Prefetch buffer hit count [63:32]" tree.end tree "NVM_CTRL_1_0" base ad:0x71778000 group.long 0x0++0x3 line.long 0x0 "PFCR1,NVM PC configuration register 1" hexmask.long.byte 0x0 8.--12. 1. "RWSC,Read Wait State Control" group.long 0x8++0x3 line.long 0x0 "PFCR3,NVM PC configuration register 3" bitfld.long 0x0 15. "BCS_DIS,BCS_DIS" "0,1" rgroup.long 0xC++0x3 line.long 0x0 "PFSR,NVM PC Status register" bitfld.long 0x0 0. "NVMPCFLHBUSY,NVMPCFLHBUSY" "0,1" group.long 0x10++0xB line.long 0x0 "FLTENA,NVM PC fault latching enable register" bitfld.long 0x0 10. "NVMCTED,NVM Code triple ECC error" "0,1" bitfld.long 0x0 9. "NVMCDBC,NVM Code double ECC error" "0,1" bitfld.long 0x0 8. "NVMCSBC,NVM Code single ECC error" "0,1" bitfld.long 0x0 7. "NVMDTED,NVM Data triple ECC error" "0,1" bitfld.long 0x0 6. "NVMDDBC,NVM Data double ECC error" "0,1" bitfld.long 0x0 5. "NVMDSBC,NVM Data single ECC error" "0,1" bitfld.long 0x0 4. "NVMENCE,NVM Address encoding error" "0,1" newline bitfld.long 0x0 3. "NVMCEDC,NVM Code EDC error" "0,1" bitfld.long 0x0 2. "NVMDEDC,NVM Data EDC error" "0,1" bitfld.long 0x0 1. "NVMPCENC,NVMPC Address encoding error" "0,1" bitfld.long 0x0 0. "NVMPCENSWAP,NVMPC SWAP Address error" "0,1" line.long 0x4 "FLTFRC,NVM PC fault forcing register" bitfld.long 0x4 10. "NVMCTED,NVM Code triple ECC error" "0,1" bitfld.long 0x4 9. "NVMCDBC,NVM Code double ECC error" "0,1" bitfld.long 0x4 8. "NVMCSBC,NVM Code single ECC error" "0,1" bitfld.long 0x4 7. "NVMDTED,NVM Data triple ECC error" "0,1" bitfld.long 0x4 6. "NVMDDBC,NVM Data double ECC error" "0,1" bitfld.long 0x4 5. "NVMDSBC,NVM Data single ECC error" "0,1" bitfld.long 0x4 4. "NVMENCE,NVM Address encoding error" "0,1" newline bitfld.long 0x4 3. "NVMCEDC,NVM Code EDC error" "0,1" bitfld.long 0x4 2. "NVMDEDC,NVM Data EDC error" "0,1" bitfld.long 0x4 1. "NVMPCENC,NVMPC Address encoding error" "0,1" bitfld.long 0x4 0. "NVMPCENSWAP,NVMPC SWAP Address error" "0,1" line.long 0x8 "FLTSCR,NVM PC fault status and clear register" bitfld.long 0x8 10. "NVMCTED,NVM Code triple ECC error" "0,1" bitfld.long 0x8 9. "NVMCDBC,NVM Code double ECC error" "0,1" bitfld.long 0x8 8. "NVMCSBC,NVM Code triple ECC error" "0,1" bitfld.long 0x8 7. "NVMDTED,NVM Data triple ECC error" "0,1" bitfld.long 0x8 6. "NVMDDBC,NVM Data double ECC error" "0,1" bitfld.long 0x8 5. "NVMDSBC,NVM Data single ECC error" "0,1" bitfld.long 0x8 4. "NVMENCE,NVM Address encoding error" "0,1" newline bitfld.long 0x8 3. "NVMCEDC,NVM Code EDC error" "0,1" bitfld.long 0x8 2. "NVMDEDC,NVM Data EDC error" "0,1" bitfld.long 0x8 1. "NVMPCENC,NVMPC Address encoding error" "0,1" bitfld.long 0x8 0. "NVMPCENSWAP,NVMPC SWAP Address error" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "FLTADR,NVM PC fault address register" hexmask.long 0x0 0.--31. 1. "FADR,Fault Address" rgroup.long 0x310++0x17 line.long 0x0 "PFCMC,NVM PC cache miss count register" hexmask.long 0x0 0.--31. 1. "SCMCNT,Cache miss count [31:0]" line.long 0x4 "PFCMOC,NVM PC cache miss overflow counter register" hexmask.long 0x4 0.--31. 1. "SCMOCNT,Cache miss count [63:32]" line.long 0x8 "PFCHC,NVM PC cache hit counter register" hexmask.long 0x8 0.--31. 1. "SCHCNT,Cache hit count [31:0]" line.long 0xC "PFCHOC,NVM PC cache hit overflow counter register" hexmask.long 0xC 0.--31. 1. "SCHOCNT,Cache hit count [63:32]" line.long 0x10 "PFFHC,NVM PC FIFO hit counter" hexmask.long 0x10 0.--31. 1. "PFFHCNT,FIFO hit count [0:31]" line.long 0x14 "PFFHOC,NVM PC FIFO hit overflow counter register" hexmask.long 0x14 0.--31. 1. "PFFHOCNT,FIFO Hit Overflow Count [32:63]" rgroup.long 0x330++0xF line.long 0x0 "PFPFC,NVM PC Prefetch Buffer Counter register" hexmask.long 0x0 0.--31. 1. "PFPFCNT,Prefetch access count [31:0]" line.long 0x4 "PFPFOC,NVM PC Prefetch Buffer Overflow Counter register" hexmask.long 0x4 0.--31. 1. "PFPFOCNT,Prefetch access count [63:32]" line.long 0x8 "PFPFHC,NVM PC Prefetch Buffer Hit Counter register" hexmask.long 0x8 0.--31. 1. "PFPFHCCNT,Prefetch buffer hit count [31:0]" line.long 0xC "PFPFHOC,NVM PC Prefetch Buffer Hit Overflow Counter register" hexmask.long 0xC 0.--31. 1. "PFPFHOCCNT,Prefetch buffer hit count [63:32]" tree.end tree "NVM_CTRL_1_1" base ad:0x7177C000 group.long 0x0++0x3 line.long 0x0 "PFCR1,NVM PC configuration register 1" hexmask.long.byte 0x0 8.--12. 1. "RWSC,Read Wait State Control" group.long 0x8++0x3 line.long 0x0 "PFCR3,NVM PC configuration register 3" bitfld.long 0x0 15. "BCS_DIS,BCS_DIS" "0,1" rgroup.long 0xC++0x3 line.long 0x0 "PFSR,NVM PC Status register" bitfld.long 0x0 0. "NVMPCFLHBUSY,NVMPCFLHBUSY" "0,1" group.long 0x10++0xB line.long 0x0 "FLTENA,NVM PC fault latching enable register" bitfld.long 0x0 10. "NVMCTED,NVM Code triple ECC error" "0,1" bitfld.long 0x0 9. "NVMCDBC,NVM Code double ECC error" "0,1" bitfld.long 0x0 8. "NVMCSBC,NVM Code single ECC error" "0,1" bitfld.long 0x0 7. "NVMDTED,NVM Data triple ECC error" "0,1" bitfld.long 0x0 6. "NVMDDBC,NVM Data double ECC error" "0,1" bitfld.long 0x0 5. "NVMDSBC,NVM Data single ECC error" "0,1" bitfld.long 0x0 4. "NVMENCE,NVM Address encoding error" "0,1" newline bitfld.long 0x0 3. "NVMCEDC,NVM Code EDC error" "0,1" bitfld.long 0x0 2. "NVMDEDC,NVM Data EDC error" "0,1" bitfld.long 0x0 1. "NVMPCENC,NVMPC Address encoding error" "0,1" bitfld.long 0x0 0. "NVMPCENSWAP,NVMPC SWAP Address error" "0,1" line.long 0x4 "FLTFRC,NVM PC fault forcing register" bitfld.long 0x4 10. "NVMCTED,NVM Code triple ECC error" "0,1" bitfld.long 0x4 9. "NVMCDBC,NVM Code double ECC error" "0,1" bitfld.long 0x4 8. "NVMCSBC,NVM Code single ECC error" "0,1" bitfld.long 0x4 7. "NVMDTED,NVM Data triple ECC error" "0,1" bitfld.long 0x4 6. "NVMDDBC,NVM Data double ECC error" "0,1" bitfld.long 0x4 5. "NVMDSBC,NVM Data single ECC error" "0,1" bitfld.long 0x4 4. "NVMENCE,NVM Address encoding error" "0,1" newline bitfld.long 0x4 3. "NVMCEDC,NVM Code EDC error" "0,1" bitfld.long 0x4 2. "NVMDEDC,NVM Data EDC error" "0,1" bitfld.long 0x4 1. "NVMPCENC,NVMPC Address encoding error" "0,1" bitfld.long 0x4 0. "NVMPCENSWAP,NVMPC SWAP Address error" "0,1" line.long 0x8 "FLTSCR,NVM PC fault status and clear register" bitfld.long 0x8 10. "NVMCTED,NVM Code triple ECC error" "0,1" bitfld.long 0x8 9. "NVMCDBC,NVM Code double ECC error" "0,1" bitfld.long 0x8 8. "NVMCSBC,NVM Code triple ECC error" "0,1" bitfld.long 0x8 7. "NVMDTED,NVM Data triple ECC error" "0,1" bitfld.long 0x8 6. "NVMDDBC,NVM Data double ECC error" "0,1" bitfld.long 0x8 5. "NVMDSBC,NVM Data single ECC error" "0,1" bitfld.long 0x8 4. "NVMENCE,NVM Address encoding error" "0,1" newline bitfld.long 0x8 3. "NVMCEDC,NVM Code EDC error" "0,1" bitfld.long 0x8 2. "NVMDEDC,NVM Data EDC error" "0,1" bitfld.long 0x8 1. "NVMPCENC,NVMPC Address encoding error" "0,1" bitfld.long 0x8 0. "NVMPCENSWAP,NVMPC SWAP Address error" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "FLTADR,NVM PC fault address register" hexmask.long 0x0 0.--31. 1. "FADR,Fault Address" rgroup.long 0x310++0x17 line.long 0x0 "PFCMC,NVM PC cache miss count register" hexmask.long 0x0 0.--31. 1. "SCMCNT,Cache miss count [31:0]" line.long 0x4 "PFCMOC,NVM PC cache miss overflow counter register" hexmask.long 0x4 0.--31. 1. "SCMOCNT,Cache miss count [63:32]" line.long 0x8 "PFCHC,NVM PC cache hit counter register" hexmask.long 0x8 0.--31. 1. "SCHCNT,Cache hit count [31:0]" line.long 0xC "PFCHOC,NVM PC cache hit overflow counter register" hexmask.long 0xC 0.--31. 1. "SCHOCNT,Cache hit count [63:32]" line.long 0x10 "PFFHC,NVM PC FIFO hit counter" hexmask.long 0x10 0.--31. 1. "PFFHCNT,FIFO hit count [0:31]" line.long 0x14 "PFFHOC,NVM PC FIFO hit overflow counter register" hexmask.long 0x14 0.--31. 1. "PFFHOCNT,FIFO Hit Overflow Count [32:63]" rgroup.long 0x330++0xF line.long 0x0 "PFPFC,NVM PC Prefetch Buffer Counter register" hexmask.long 0x0 0.--31. 1. "PFPFCNT,Prefetch access count [31:0]" line.long 0x4 "PFPFOC,NVM PC Prefetch Buffer Overflow Counter register" hexmask.long 0x4 0.--31. 1. "PFPFOCNT,Prefetch access count [63:32]" line.long 0x8 "PFPFHC,NVM PC Prefetch Buffer Hit Counter register" hexmask.long 0x8 0.--31. 1. "PFPFHCCNT,Prefetch buffer hit count [31:0]" line.long 0xC "PFPFHOC,NVM PC Prefetch Buffer Hit Overflow Counter register" hexmask.long 0xC 0.--31. 1. "PFPFHOCCNT,Prefetch buffer hit count [63:32]" tree.end tree "NVM_CTRL_2_0" base ad:0x71180000 group.long 0x0++0x3 line.long 0x0 "PFCR1,NVM PC configuration register 1" hexmask.long.byte 0x0 8.--12. 1. "RWSC,Read Wait State Control" group.long 0x8++0x3 line.long 0x0 "PFCR3,NVM PC configuration register 3" bitfld.long 0x0 15. "BCS_DIS,BCS_DIS" "0,1" rgroup.long 0xC++0x3 line.long 0x0 "PFSR,NVM PC Status register" bitfld.long 0x0 0. "NVMPCFLHBUSY,NVMPCFLHBUSY" "0,1" group.long 0x10++0xB line.long 0x0 "FLTENA,NVM PC fault latching enable register" bitfld.long 0x0 10. "NVMCTED,NVM Code triple ECC error" "0,1" bitfld.long 0x0 9. "NVMCDBC,NVM Code double ECC error" "0,1" bitfld.long 0x0 8. "NVMCSBC,NVM Code single ECC error" "0,1" bitfld.long 0x0 7. "NVMDTED,NVM Data triple ECC error" "0,1" bitfld.long 0x0 6. "NVMDDBC,NVM Data double ECC error" "0,1" bitfld.long 0x0 5. "NVMDSBC,NVM Data single ECC error" "0,1" bitfld.long 0x0 4. "NVMENCE,NVM Address encoding error" "0,1" newline bitfld.long 0x0 3. "NVMCEDC,NVM Code EDC error" "0,1" bitfld.long 0x0 2. "NVMDEDC,NVM Data EDC error" "0,1" bitfld.long 0x0 1. "NVMPCENC,NVMPC Address encoding error" "0,1" bitfld.long 0x0 0. "NVMPCENSWAP,NVMPC SWAP Address error" "0,1" line.long 0x4 "FLTFRC,NVM PC fault forcing register" bitfld.long 0x4 10. "NVMCTED,NVM Code triple ECC error" "0,1" bitfld.long 0x4 9. "NVMCDBC,NVM Code double ECC error" "0,1" bitfld.long 0x4 8. "NVMCSBC,NVM Code single ECC error" "0,1" bitfld.long 0x4 7. "NVMDTED,NVM Data triple ECC error" "0,1" bitfld.long 0x4 6. "NVMDDBC,NVM Data double ECC error" "0,1" bitfld.long 0x4 5. "NVMDSBC,NVM Data single ECC error" "0,1" bitfld.long 0x4 4. "NVMENCE,NVM Address encoding error" "0,1" newline bitfld.long 0x4 3. "NVMCEDC,NVM Code EDC error" "0,1" bitfld.long 0x4 2. "NVMDEDC,NVM Data EDC error" "0,1" bitfld.long 0x4 1. "NVMPCENC,NVMPC Address encoding error" "0,1" bitfld.long 0x4 0. "NVMPCENSWAP,NVMPC SWAP Address error" "0,1" line.long 0x8 "FLTSCR,NVM PC fault status and clear register" bitfld.long 0x8 10. "NVMCTED,NVM Code triple ECC error" "0,1" bitfld.long 0x8 9. "NVMCDBC,NVM Code double ECC error" "0,1" bitfld.long 0x8 8. "NVMCSBC,NVM Code triple ECC error" "0,1" bitfld.long 0x8 7. "NVMDTED,NVM Data triple ECC error" "0,1" bitfld.long 0x8 6. "NVMDDBC,NVM Data double ECC error" "0,1" bitfld.long 0x8 5. "NVMDSBC,NVM Data single ECC error" "0,1" bitfld.long 0x8 4. "NVMENCE,NVM Address encoding error" "0,1" newline bitfld.long 0x8 3. "NVMCEDC,NVM Code EDC error" "0,1" bitfld.long 0x8 2. "NVMDEDC,NVM Data EDC error" "0,1" bitfld.long 0x8 1. "NVMPCENC,NVMPC Address encoding error" "0,1" bitfld.long 0x8 0. "NVMPCENSWAP,NVMPC SWAP Address error" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "FLTADR,NVM PC fault address register" hexmask.long 0x0 0.--31. 1. "FADR,Fault Address" rgroup.long 0x310++0x17 line.long 0x0 "PFCMC,NVM PC cache miss count register" hexmask.long 0x0 0.--31. 1. "SCMCNT,Cache miss count [31:0]" line.long 0x4 "PFCMOC,NVM PC cache miss overflow counter register" hexmask.long 0x4 0.--31. 1. "SCMOCNT,Cache miss count [63:32]" line.long 0x8 "PFCHC,NVM PC cache hit counter register" hexmask.long 0x8 0.--31. 1. "SCHCNT,Cache hit count [31:0]" line.long 0xC "PFCHOC,NVM PC cache hit overflow counter register" hexmask.long 0xC 0.--31. 1. "SCHOCNT,Cache hit count [63:32]" line.long 0x10 "PFFHC,NVM PC FIFO hit counter" hexmask.long 0x10 0.--31. 1. "PFFHCNT,FIFO hit count [0:31]" line.long 0x14 "PFFHOC,NVM PC FIFO hit overflow counter register" hexmask.long 0x14 0.--31. 1. "PFFHOCNT,FIFO Hit Overflow Count [32:63]" rgroup.long 0x330++0xF line.long 0x0 "PFPFC,NVM PC Prefetch Buffer Counter register" hexmask.long 0x0 0.--31. 1. "PFPFCNT,Prefetch access count [31:0]" line.long 0x4 "PFPFOC,NVM PC Prefetch Buffer Overflow Counter register" hexmask.long 0x4 0.--31. 1. "PFPFOCNT,Prefetch access count [63:32]" line.long 0x8 "PFPFHC,NVM PC Prefetch Buffer Hit Counter register" hexmask.long 0x8 0.--31. 1. "PFPFHCCNT,Prefetch buffer hit count [31:0]" line.long 0xC "PFPFHOC,NVM PC Prefetch Buffer Hit Overflow Counter register" hexmask.long 0xC 0.--31. 1. "PFPFHOCCNT,Prefetch buffer hit count [63:32]" tree.end tree "NVM_CTRL_2_1" base ad:0x71184000 group.long 0x0++0x3 line.long 0x0 "PFCR1,NVM PC configuration register 1" hexmask.long.byte 0x0 8.--12. 1. "RWSC,Read Wait State Control" group.long 0x8++0x3 line.long 0x0 "PFCR3,NVM PC configuration register 3" bitfld.long 0x0 15. "BCS_DIS,BCS_DIS" "0,1" rgroup.long 0xC++0x3 line.long 0x0 "PFSR,NVM PC Status register" bitfld.long 0x0 0. "NVMPCFLHBUSY,NVMPCFLHBUSY" "0,1" group.long 0x10++0xB line.long 0x0 "FLTENA,NVM PC fault latching enable register" bitfld.long 0x0 10. "NVMCTED,NVM Code triple ECC error" "0,1" bitfld.long 0x0 9. "NVMCDBC,NVM Code double ECC error" "0,1" bitfld.long 0x0 8. "NVMCSBC,NVM Code single ECC error" "0,1" bitfld.long 0x0 7. "NVMDTED,NVM Data triple ECC error" "0,1" bitfld.long 0x0 6. "NVMDDBC,NVM Data double ECC error" "0,1" bitfld.long 0x0 5. "NVMDSBC,NVM Data single ECC error" "0,1" bitfld.long 0x0 4. "NVMENCE,NVM Address encoding error" "0,1" newline bitfld.long 0x0 3. "NVMCEDC,NVM Code EDC error" "0,1" bitfld.long 0x0 2. "NVMDEDC,NVM Data EDC error" "0,1" bitfld.long 0x0 1. "NVMPCENC,NVMPC Address encoding error" "0,1" bitfld.long 0x0 0. "NVMPCENSWAP,NVMPC SWAP Address error" "0,1" line.long 0x4 "FLTFRC,NVM PC fault forcing register" bitfld.long 0x4 10. "NVMCTED,NVM Code triple ECC error" "0,1" bitfld.long 0x4 9. "NVMCDBC,NVM Code double ECC error" "0,1" bitfld.long 0x4 8. "NVMCSBC,NVM Code single ECC error" "0,1" bitfld.long 0x4 7. "NVMDTED,NVM Data triple ECC error" "0,1" bitfld.long 0x4 6. "NVMDDBC,NVM Data double ECC error" "0,1" bitfld.long 0x4 5. "NVMDSBC,NVM Data single ECC error" "0,1" bitfld.long 0x4 4. "NVMENCE,NVM Address encoding error" "0,1" newline bitfld.long 0x4 3. "NVMCEDC,NVM Code EDC error" "0,1" bitfld.long 0x4 2. "NVMDEDC,NVM Data EDC error" "0,1" bitfld.long 0x4 1. "NVMPCENC,NVMPC Address encoding error" "0,1" bitfld.long 0x4 0. "NVMPCENSWAP,NVMPC SWAP Address error" "0,1" line.long 0x8 "FLTSCR,NVM PC fault status and clear register" bitfld.long 0x8 10. "NVMCTED,NVM Code triple ECC error" "0,1" bitfld.long 0x8 9. "NVMCDBC,NVM Code double ECC error" "0,1" bitfld.long 0x8 8. "NVMCSBC,NVM Code triple ECC error" "0,1" bitfld.long 0x8 7. "NVMDTED,NVM Data triple ECC error" "0,1" bitfld.long 0x8 6. "NVMDDBC,NVM Data double ECC error" "0,1" bitfld.long 0x8 5. "NVMDSBC,NVM Data single ECC error" "0,1" bitfld.long 0x8 4. "NVMENCE,NVM Address encoding error" "0,1" newline bitfld.long 0x8 3. "NVMCEDC,NVM Code EDC error" "0,1" bitfld.long 0x8 2. "NVMDEDC,NVM Data EDC error" "0,1" bitfld.long 0x8 1. "NVMPCENC,NVMPC Address encoding error" "0,1" bitfld.long 0x8 0. "NVMPCENSWAP,NVMPC SWAP Address error" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "FLTADR,NVM PC fault address register" hexmask.long 0x0 0.--31. 1. "FADR,Fault Address" rgroup.long 0x310++0x17 line.long 0x0 "PFCMC,NVM PC cache miss count register" hexmask.long 0x0 0.--31. 1. "SCMCNT,Cache miss count [31:0]" line.long 0x4 "PFCMOC,NVM PC cache miss overflow counter register" hexmask.long 0x4 0.--31. 1. "SCMOCNT,Cache miss count [63:32]" line.long 0x8 "PFCHC,NVM PC cache hit counter register" hexmask.long 0x8 0.--31. 1. "SCHCNT,Cache hit count [31:0]" line.long 0xC "PFCHOC,NVM PC cache hit overflow counter register" hexmask.long 0xC 0.--31. 1. "SCHOCNT,Cache hit count [63:32]" line.long 0x10 "PFFHC,NVM PC FIFO hit counter" hexmask.long 0x10 0.--31. 1. "PFFHCNT,FIFO hit count [0:31]" line.long 0x14 "PFFHOC,NVM PC FIFO hit overflow counter register" hexmask.long 0x14 0.--31. 1. "PFFHOCNT,FIFO Hit Overflow Count [32:63]" rgroup.long 0x330++0xF line.long 0x0 "PFPFC,NVM PC Prefetch Buffer Counter register" hexmask.long 0x0 0.--31. 1. "PFPFCNT,Prefetch access count [31:0]" line.long 0x4 "PFPFOC,NVM PC Prefetch Buffer Overflow Counter register" hexmask.long 0x4 0.--31. 1. "PFPFOCNT,Prefetch access count [63:32]" line.long 0x8 "PFPFHC,NVM PC Prefetch Buffer Hit Counter register" hexmask.long 0x8 0.--31. 1. "PFPFHCCNT,Prefetch buffer hit count [31:0]" line.long 0xC "PFPFHOC,NVM PC Prefetch Buffer Hit Overflow Counter register" hexmask.long 0xC 0.--31. 1. "PFPFHOCCNT,Prefetch buffer hit count [63:32]" tree.end tree.end tree "OCTOSPI (OctoSPI Interface)" base ad:0x0 tree "OCTOSPI_AHB_1_OCTOSPI_AHB_ADR" base ad:0x4FFFEC00 group.long 0x0++0x3 line.long 0x0 "OCTOSPI_CR,Octo SPI Control Register" bitfld.long 0x0 28.--29. "FMODE,This field defines the OctoSPI’s functional mode of operation.If DMAEN=1 already then the DMA controller for the corresponding channel must be" "0: Indirect write mode,1: Indirect read mode,2: Automatic polling mode,3: Memory-mapped mode" bitfld.long 0x0 23. "PMM,This bit indicates which method should be used for determining a “match” during automatic polling mode.This bit can be modified only when BUSY=0." "0: AND match mode- SMF is set if all the unmasked..,1: OR match mode- SMF is set if any one of the.." newline bitfld.long 0x0 22. "APMS,This bit determines if automatic polling is stopped after a match." "0: Automatic polling mode is stopped only by abort..,1: Automatic polling mode stops as soon as there is.." bitfld.long 0x0 20. "TOIE,This bit enables the TimeOut Interrupt." "0: Interrupt disable,1: Interrupt enabled" newline bitfld.long 0x0 19. "SMIE,This bit enables the Status Match Interrupt." "0: Interrupt disable,1: Interrupt enabled" bitfld.long 0x0 18. "FTIE,This bit enables the FIFO Threshold Interrupt." "0: Interrupt disable,1: Interrupt enabled" newline bitfld.long 0x0 17. "TCIE,This bit enables the Transfer Complete Interrupt." "0: Interrupt disable,1: Interrupt enabled" bitfld.long 0x0 16. "TEIE,This bit enables the Transfer Error Interrupt." "0: Interrupt disable,1: Interrupt enabled" newline hexmask.long.byte 0x0 8.--13. 1. "FTHRESH,Defines in indirect mode the threshold number of bytes in the FIFO which will cause the FIFO Threshold Flag (FTF OCTOSPI_SR[2]) to be set." bitfld.long 0x0 7. "FSEL,This bit selects the Flash memory to be addressed in single/dual/quad mode in single flash mode (when DFM = 0). This bit can be modified only when BUSY = 0." "0: FLASH 1 selected (data exchanged over IO[3:0]),1: FLASH 2 selected (data exchanged over IO[3:0])" newline bitfld.long 0x0 6. "DQM,This bit activates Dual-Quad mode where two external devices are used simultaneously to double throughput and capacity.This bit can be modified only when BUSY=0." "0: Dual-Quad mode disabled,1: Dual-Quad mode enabled" bitfld.long 0x0 3. "TCEN,This bit is valid only when memory-mapped mode (FMODE=11) is selected. Activating this bit causes the chip select (nCS) to be released (and thus reduce consumption) if there has not been an access after a certain amount of time where this time is.." "0: Timeout counter is disabled and thus the chip..,1: Timeout counter is enabled and thus the chip.." newline bitfld.long 0x0 2. "DMAEN,In indirect mode DMA can be used to input or output data via the OCTOSPI_DR register." "0: DMA is disabled for indirect mode,1: DMA is enabled for indirect mode" bitfld.long 0x0 1. "ABORT,This bit aborts the on-going command sequence. It is automatically reset once the abort is complete." "0: No abort requested,1: Abort requested" newline bitfld.long 0x0 0. "EN,Enable the OctoSPI." "0: OctoSPI is disabled,1: OctoSPI is enabled" group.long 0x8++0xF line.long 0x0 "OCTOSPI_DCR1,OctoSPI Device Configuration Register 1" bitfld.long 0x0 24.--26. "MTYP,This bit indicates type of memory to be supported." "0: Micron mode – D0/D1 ordering in DTR 8-data-bit..,1: Macronix mode – D1/D0 ordering in DTR..,?,?,4: HyperBusTM memory mode – Protocol follows..,5: HyperBusTM register mode – addressing register..,?,?" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,This field defines the size of external device using the following formula:" newline bitfld.long 0x0 8.--10. "CSHT,CSHT+1 defines the minimum number of CLK cycles where the chip-select (nCS) must remain high between commands issued to the external device." "0: nCS stays high for at least 1 cycle between..,1: nCS stays high for at least 2 cycles between..,?,?,?,?,?,?" bitfld.long 0x0 4.--6. "CKCSHT,CKCSHT+1 defines the number of CLK cycles provided on the CLK /nCLK pins when the chip select (nCS) is set to high at the end of a transaction." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "DLYBYP,This bit configure the free running clock." "0: Sampling clock is delayed by the delay block.,1: Delay block is bypassed so the sampling clock is.." bitfld.long 0x0 1. "FRCK,This bit configure the free running clock." "0: CLK is not free running.,1: CLK is free running (always provided)" newline bitfld.long 0x0 0. "CKMODE,This bit indicates the level that CLK takes between commands (when nCS=1)." "0: CLK must stay low while nCS is high (chip select..,1: CLK must stay high while nCS is high (chip.." line.long 0x4 "OCTOSPI_DCR2,OctoSPI Device Configuration Register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,This field indicates the wrap-size to which the memory is configured. For memories which" "0: wrapped reads are not supported by the memory.,1: reserved,2: external memory supports wrap size of 16 bytes..,3: external memory supports wrap size of 32 bytes..,4: external memory supports wrap size of 64 bytes..,5: external memory supports wrap size of 128 bytes,?,?" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,This field defines the scaler factor for generating CLK based on the AHB clock (value+1)." line.long 0x8 "OCTOSPI_DCR3,OctoSPI Device Configuration Register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,This bits enable the transaction boundary feature." hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,This bits enable the communication regulation feature." line.long 0xC "OCTOSPI_DCR4,OctoSPI Device Configuration Register 4" hexmask.long 0xC 0.--31. 1. "REFRESH,This bits enable the refresh rate feature." rgroup.long 0x20++0x3 line.long 0x0 "OCTOSPI_SR,OctoSPI Status Register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,This field gives the number of valid bytes which are being held in the FIFO. FLEVEL=0 when the FIFO is empty and 32 when it is full. In memory-mapped mode and in automatic" bitfld.long 0x0 5. "BUSY,This bit is set when an operation is on going. This bit clears automatically when the operation with the external device is finished and the FIFO is empty." "0,1" newline bitfld.long 0x0 4. "TOF,This bit is set when timeout occurs.It is cleared by writing 1 to CTOF." "0,1" bitfld.long 0x0 3. "SMF,This bit is set in automatic polling mode when the unmasked received data matches the corresponding bits in the match register (OCTOSPI_PSMAR). It is cleared by writing 1 to CSMF." "0,1" newline bitfld.long 0x0 2. "FTF,In indrect mode this bit is set when the FIFO threshold has been reached or if there is any data left in the FIFO after reads from the external device are complete. It is cleared" "0,1" bitfld.long 0x0 1. "TCF,This bit is set in indirect mode when the programmed number of data has been transferred or in any mode when the transfer has been aborted.It is cleared by writing 1 to" "0,1" newline bitfld.long 0x0 0. "TEF,This bit is set in indirect mode when an invalid address is being accessed in indirect mode. It is cleared by writing 1 to CTEF." "0,1" group.long 0x24++0x3 line.long 0x0 "OCTOSPI_FCR,OctoSPI Flag Clear Register" bitfld.long 0x0 4. "CTOF,Writing 1 clears the TOF flag in the OCTOSPI_SR register" "0,1" bitfld.long 0x0 3. "CSMF,Writing 1 clears the SMF flag in the OCTOSPI_SR register" "0,1" newline bitfld.long 0x0 1. "CTCF,Writing 1 clears the TCF flag in the OCTOSPI_SR register" "0,1" bitfld.long 0x0 0. "CTEF,Writing 1 clears the TEF flag in the OCTOSPI_SR register" "0,1" group.long 0x40++0x3 line.long 0x0 "OCTOSPI_DLR,OctoSPI Data Length Register" hexmask.long 0x0 0.--31. 1. "DL,Number of data to be retrieved (value+1) in indirect and status-polling modes. A value no greater than 3 (indicating 4 bytes) should be used for status-polling mode." group.long 0x48++0x3 line.long 0x0 "OCTOSPI_AR,OctoSPI Address Register" hexmask.long 0x0 0.--31. 1. "ADDRESS,Address to be send to the external device." group.long 0x50++0x3 line.long 0x0 "OCTOSPI_DR,OctoSPI Data Register" hexmask.long 0x0 0.--31. 1. "DATA,Data to be sent/received to/from the external SPI device." group.long 0x80++0x3 line.long 0x0 "OCTOSPI_PSMKR,OctoSPI Polling Status Mask Register" hexmask.long 0x0 0.--31. 1. "MASK,Mask to be applied to the status bytes received in polling mode." group.long 0x88++0x3 line.long 0x0 "OCTOSPI_PSMAR,OctoSPI Polling Status Match Register" hexmask.long 0x0 0.--31. 1. "MATCH,Value to be compared with the masked status register to get a match." group.long 0x90++0x3 line.long 0x0 "OCTOSPI_PIR,OctoSPI Polling Interval Register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,Number of CLK cycle between to read during automatic polling phases." group.long 0x100++0x3 line.long 0x0 "OCTOSPI_CCR,OctoSPI Communication Configuration Register" bitfld.long 0x0 31. "SIOO,See Section : Sending the instruction only once on page 28. This bit has no effect when IMODE=00." "0: Send instruction on every transaction,1: Send instruction only for the first command" bitfld.long 0x0 29. "DQSE,This bit enables the data strobe management." "0: DQS disabled,1: DQS enabled" newline bitfld.long 0x0 27. "DDTR,This bit sets the DTR Mode for the alternate bytes phase." "0: DTR Mode disabled for alternate bytes phase,1: DTR Mode enabled for alternate bytes phase" bitfld.long 0x0 24.--26. "DMODE,This field defines the data phase’s mode of operation." "0: No Instruction,1: Data on a single line,2: Data on two lines,3: Data on four lines,4: Data on eight lines,?,?,?" newline bitfld.long 0x0 20.--21. "ABSIZE,This bit defines alternate bytes size." "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" bitfld.long 0x0 19. "ABDTR,This bit sets the DTR Mode for the alternate bytes phase." "0: DTR Mode disabled for alternate bytes phase,1: DTR Mode enabled for alternate bytes phase" newline bitfld.long 0x0 16.--18. "ABMODE,This field defines the alternate byte phase’s mode of operation." "0: No instruction,1: Alternate bytes on a single line,2: Alternate bytes on two lines,3: Alternate bytes on four lines,4: Alternate bytes on eight lines,?,?,?" bitfld.long 0x0 12.--13. "ADSIZE,This bit defines address size." "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" newline bitfld.long 0x0 11. "ADDTR,This bit sets the DTR Mode for the address phase." "0: DTR Mode disabled for address phase,1: DTR Mode enabled for address phase" bitfld.long 0x0 8.--10. "ADMODE,This field defines the address phase’s mode of operation." "0: No Address,1: Address on a single line,2: Address on two lines,3: Address on four lines,4: Address on eight lines,?,?,?" newline bitfld.long 0x0 4.--5. "ISIZE,This bit defines instruction size." "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" bitfld.long 0x0 3. "IDTR,This bit sets the DTR Mode for the instruction phase." "0: DTR Mode disabled for instruction phase,1: DTR Mode enabled for instruction phase" newline bitfld.long 0x0 0.--2. "IMODE,This field defines the instruction phase’s mode of operation:" "0: No instruction,1: Instruction on a single line,2: Instruction on two lines,3: Instruction on four lines,4: Instruction on eight lines,?,?,?" group.long 0x108++0x3 line.long 0x0 "OCTOSPI_TCR,OctoSPI Timing Configuration Register" bitfld.long 0x0 30. "SSHIFT,By default the OctoSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data is to be sampled later in order to account for external signal delays." "0: No shift,1: 1/2 cycle shift" bitfld.long 0x0 28. "DHQC,This field defines the delay hold quarter cycle." "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "DCYC,This field defines the duration of the dummy phase. In both SDR and DTR modes it specifies a number of CLK cycles (0-31)." group.long 0x110++0x3 line.long 0x0 "OCTOSPI_IR,OctoSPI Instruction Register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction to be send to the external SPI device." group.long 0x120++0x3 line.long 0x0 "OCTOSPI_ABR,OctoSPI Alternate Bytes Register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Optional data to be send to the external SPI device right after the address." group.long 0x130++0x3 line.long 0x0 "OCTOSPI_LPTR,OctoSPI Low Power Timeout Register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,After each access in memory-mapped mode OctoSPI prefetches the subsequent bytes and holds these bytes in the FIFO. This field indicates how many CLK cycles OctoSPI waits after the FIFO becomes full until it raises nCS putting the external.." group.long 0x140++0x3 line.long 0x0 "OCTOSPI_WPCCR,OctoSPI Wrap Communication Configuration Register" bitfld.long 0x0 31. "SIOO,See Section : Sending the instruction only once on page 28. This bit has no effect when IMODE=00." "0: Send instruction on every transaction,1: Send instruction only for the first command" bitfld.long 0x0 29. "DQSE,This bit enables the data strobe management." "0: DQS disabled,1: DQS enabled" newline bitfld.long 0x0 27. "DDTR,This bit sets the DTR Mode for the alternate bytes phase." "0: DTR Mode disabled for alternate bytes phase,1: DTR Mode enabled for alternate bytes phase" bitfld.long 0x0 24.--26. "DMODE,This field defines the data phase’s mode of operation." "0: No Instruction,1: Data on a single line,2: Data on two lines,3: Data on four lines,4: Data on eight lines,?,?,?" newline bitfld.long 0x0 20.--21. "ABSIZE,This bit defines alternate bytes size." "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" bitfld.long 0x0 19. "ABDTR,This bit sets the DTR Mode for the alternate bytes phase." "0: DTR Mode disabled for alternate bytes phase,1: DTR Mode enabled for alternate bytes phase" newline bitfld.long 0x0 16.--18. "ABMODE,This field defines the alternate byte phase’s mode of operation." "0: No instruction,1: Alternate bytes on a single line,2: Alternate bytes on two lines,3: Alternate bytes on four lines,4: Alternate bytes on eight lines,?,?,?" bitfld.long 0x0 12.--13. "ADSIZE,This bit defines address size." "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" newline bitfld.long 0x0 11. "ADDTR,This bit sets the DTR Mode for the address phase." "0: DTR Mode disabled for address phase,1: DTR Mode enabled for address phase" bitfld.long 0x0 8.--10. "ADMODE,This field defines the address phase’s mode of operation." "0: No Address,1: Address on a single line,2: Address on two lines,3: Address on four lines,4: Address on eight lines,?,?,?" newline bitfld.long 0x0 4.--5. "ISIZE,This bit defines instruction size." "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" bitfld.long 0x0 3. "IDTR,This bit sets the DTR Mode for the instruction phase:" "0: DTR Mode disabled for instruction phase,1: DTR Mode enabled for instruction phase" newline bitfld.long 0x0 0.--2. "IMODE,This field defines the instruction phase’s mode of operation." "0: No instruction,1: Instruction on a single line,2: Instruction on two lines,3: Instruction on four lines,4: Instruction on eight lines,?,?,?" group.long 0x148++0x3 line.long 0x0 "OCTOSPI_WPTCR,OctoSPI Wrap Timing Configuration Register" bitfld.long 0x0 30. "SSHIFT,By default the OctoSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data is to be sampled later in order to account for external signal delays." "0: No shift,1: 1/2 cycle shift" bitfld.long 0x0 28. "DHQC,This field defines the delay hold quarter cycle." "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "DCYC,This field defines the duration of the dummy phase. In both SDR and DTR modes it specifies a number of CLK cycles (0-31)." group.long 0x150++0x3 line.long 0x0 "OCTOSPI_WPIR,OctoSPI Wrap Instruction Register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction to be send to the external SPI device." group.long 0x160++0x3 line.long 0x0 "OCTOSPI_WPABR,OctoSPI Wrap Alternate Bytes Register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Optional data to be send to the external SPI device right after the address." group.long 0x180++0x3 line.long 0x0 "OCTOSPI_WCCR,OctoSPI Write Communication Configuration Register" bitfld.long 0x0 31. "SIOO,See Section : Sending the instruction only once on page 28. This bit has no effect when IMODE=00." "0: Send instruction on every transaction,1: Send instruction only for the first command" bitfld.long 0x0 29. "DQSE,This bit enables the data strobe management." "0: DQS disabled,1: DQS enabled" newline bitfld.long 0x0 27. "DDTR,This bit sets the DTR Mode for the alternate bytes phase." "0: DTR Mode disabled for alternate bytes phase,1: DTR Mode enabled for alternate bytes phase" bitfld.long 0x0 24.--26. "DMODE,This field defines the data phase’s mode of operation." "0: No Instruction,1: Data on a single line,2: Data on two lines,3: Data on four lines,4: Data on eight lines,?,?,?" newline bitfld.long 0x0 20.--21. "ABSIZE,This bit defines alternate bytes size." "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" bitfld.long 0x0 19. "ABDTR,This bit sets the DTR Mode for the alternate bytes phase." "0: DTR Mode disabled for alternate bytes phase,1: DTR Mode enabled for alternate bytes phase" newline bitfld.long 0x0 16.--18. "ABMODE,This field defines the alternate byte phase’s mode of operation." "0: No instruction,1: Alternate bytes on a single line,2: Alternate bytes on two lines,3: Alternate bytes on four lines,4: Alternate bytes on eight lines,?,?,?" bitfld.long 0x0 12.--13. "ADSIZE,This bit defines address size." "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" newline bitfld.long 0x0 11. "ADDTR,This bit sets the DTR Mode for the address phase." "0: DTR Mode disabled for address phase,1: DTR Mode enabled for address phase" bitfld.long 0x0 8.--10. "ADMODE,This field defines the address phase’s mode of operation." "0: No Address,1: Address on a single line,2: Address on two lines,3: Address on four lines,4: Address on eight lines,?,?,?" newline bitfld.long 0x0 4.--5. "ISIZE,This bit defines instruction size." "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" bitfld.long 0x0 3. "IDTR,This bit sets the DTR Mode for the instruction phase." "0: DTR Mode disabled for instruction phase,1: DTR Mode enabled for instruction phase" newline bitfld.long 0x0 0.--2. "IMODE,This field defines the instruction phase’s mode of operation:" "0: No instruction,1: Instruction on a single line,2: Instruction on two lines,3: Instruction on four lines,4: Instruction on eight lines,?,?,?" group.long 0x188++0x3 line.long 0x0 "OCTOSPI_WTCR,OctoSPI Write Timing Configuration Register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,This field defines the duration of the dummy phase. In both SDR and DTR modes it" group.long 0x190++0x3 line.long 0x0 "OCTOSPI_WIR,OctoSPI Write Instruction Register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction to be send to the external SPI device." group.long 0x1A0++0x3 line.long 0x0 "OCTOSPI_WABR,OctoSPI Write Alternate Bytes Register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Optional data to be send to the external SPI device right after the address." group.long 0x200++0x3 line.long 0x0 "OCTOSPI_HLCR,OctoSPI Hyperbus Latency Configuration Register" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Device read write recovery time expressed in number of communication clock cycles." hexmask.long.byte 0x0 8.--15. 1. "TACC,Device access time expressed in number of communication clock cycles." newline bitfld.long 0x0 1. "WZL,This bit enables zero latency on write operations." "0: Latency on write accesses,1: No latency on write accesses" bitfld.long 0x0 0. "LM,This bit select the latency mode." "0: Variable initial latency,1: Fixed latency" rgroup.long 0x3F0++0xF line.long 0x0 "OCTOSPI_HWCFGR,OctoSPI HW Configuration Register" hexmask.long.byte 0x0 28.--31. 1. "ARB_MASTER,Defines the arbitration in the IP" hexmask.long.byte 0x0 24.--27. 1. "MMW_EN,Memory Mapped Write Enabled" newline hexmask.long.byte 0x0 20.--23. 1. "ID_LENGTH,ID Length used inside IP for AXI Interface" hexmask.long.byte 0x0 12.--19. 1. "PRESC_RST_VAL,Reset Value of Prescaler to be applied." newline hexmask.long.byte 0x0 4.--11. 1. "FIFO_DEPTH,TX and RX FIFO in Words to be instantiated inside the IP." hexmask.long.byte 0x0 0.--3. 1. "AXI_INTERFACE,The Bus Interface of IP is AXI or AHB." line.long 0x4 "OCTOSPI_VER,OctoSPI Version Register" hexmask.long.byte 0x4 0.--7. 1. "VER,This field returns the IP Version." line.long 0x8 "OCTOSPI_ID,OctoSPI Identification" hexmask.long 0x8 0.--31. 1. "ID,This field returns the Identification of the OctoSPI IP." line.long 0xC "OCTOSPI_MID,OctoSPI HW Magic ID" hexmask.long 0xC 0.--31. 1. "MID,This field returns the Magic ID of the OctoSPI IP." tree.end tree "OCTOSPI_AHB_ADR" base ad:0x4FFFE000 group.long 0x0++0x3 line.long 0x0 "OCTOSPI_CR,Octo SPI Control Register" bitfld.long 0x0 28.--29. "FMODE,This field defines the OctoSPI’s functional mode of operation.If DMAEN=1 already then the DMA controller for the corresponding channel must be" "0: Indirect write mode,1: Indirect read mode,2: Automatic polling mode,3: Memory-mapped mode" bitfld.long 0x0 23. "PMM,This bit indicates which method should be used for determining a “match” during automatic polling mode.This bit can be modified only when BUSY=0." "0: AND match mode- SMF is set if all the unmasked..,1: OR match mode- SMF is set if any one of the.." newline bitfld.long 0x0 22. "APMS,This bit determines if automatic polling is stopped after a match." "0: Automatic polling mode is stopped only by abort..,1: Automatic polling mode stops as soon as there is.." bitfld.long 0x0 20. "TOIE,This bit enables the TimeOut Interrupt." "0: Interrupt disable,1: Interrupt enabled" newline bitfld.long 0x0 19. "SMIE,This bit enables the Status Match Interrupt." "0: Interrupt disable,1: Interrupt enabled" bitfld.long 0x0 18. "FTIE,This bit enables the FIFO Threshold Interrupt." "0: Interrupt disable,1: Interrupt enabled" newline bitfld.long 0x0 17. "TCIE,This bit enables the Transfer Complete Interrupt." "0: Interrupt disable,1: Interrupt enabled" bitfld.long 0x0 16. "TEIE,This bit enables the Transfer Error Interrupt." "0: Interrupt disable,1: Interrupt enabled" newline hexmask.long.byte 0x0 8.--13. 1. "FTHRESH,Defines in indirect mode the threshold number of bytes in the FIFO which will cause the FIFO Threshold Flag (FTF OCTOSPI_SR[2]) to be set." bitfld.long 0x0 7. "FSEL,This bit selects the Flash memory to be addressed in single/dual/quad mode in single flash mode (when DFM = 0). This bit can be modified only when BUSY = 0." "0: FLASH 1 selected (data exchanged over IO[3:0]),1: FLASH 2 selected (data exchanged over IO[3:0])" newline bitfld.long 0x0 6. "DQM,This bit activates Dual-Quad mode where two external devices are used simultaneously to double throughput and capacity.This bit can be modified only when BUSY=0." "0: Dual-Quad mode disabled,1: Dual-Quad mode enabled" bitfld.long 0x0 3. "TCEN,This bit is valid only when memory-mapped mode (FMODE=11) is selected. Activating this bit causes the chip select (nCS) to be released (and thus reduce consumption) if there has not been an access after a certain amount of time where this time is.." "0: Timeout counter is disabled and thus the chip..,1: Timeout counter is enabled and thus the chip.." newline bitfld.long 0x0 2. "DMAEN,In indirect mode DMA can be used to input or output data via the OCTOSPI_DR register." "0: DMA is disabled for indirect mode,1: DMA is enabled for indirect mode" bitfld.long 0x0 1. "ABORT,This bit aborts the on-going command sequence. It is automatically reset once the abort is complete." "0: No abort requested,1: Abort requested" newline bitfld.long 0x0 0. "EN,Enable the OctoSPI." "0: OctoSPI is disabled,1: OctoSPI is enabled" group.long 0x8++0xF line.long 0x0 "OCTOSPI_DCR1,OctoSPI Device Configuration Register 1" bitfld.long 0x0 24.--26. "MTYP,This bit indicates type of memory to be supported." "0: Micron mode – D0/D1 ordering in DTR 8-data-bit..,1: Macronix mode – D1/D0 ordering in DTR..,?,?,4: HyperBusTM memory mode – Protocol follows..,5: HyperBusTM register mode – addressing register..,?,?" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,This field defines the size of external device using the following formula:" newline bitfld.long 0x0 8.--10. "CSHT,CSHT+1 defines the minimum number of CLK cycles where the chip-select (nCS) must remain high between commands issued to the external device." "0: nCS stays high for at least 1 cycle between..,1: nCS stays high for at least 2 cycles between..,?,?,?,?,?,?" bitfld.long 0x0 4.--6. "CKCSHT,CKCSHT+1 defines the number of CLK cycles provided on the CLK /nCLK pins when the chip select (nCS) is set to high at the end of a transaction." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "DLYBYP,This bit configure the free running clock." "0: Sampling clock is delayed by the delay block.,1: Delay block is bypassed so the sampling clock is.." bitfld.long 0x0 1. "FRCK,This bit configure the free running clock." "0: CLK is not free running.,1: CLK is free running (always provided)" newline bitfld.long 0x0 0. "CKMODE,This bit indicates the level that CLK takes between commands (when nCS=1)." "0: CLK must stay low while nCS is high (chip select..,1: CLK must stay high while nCS is high (chip.." line.long 0x4 "OCTOSPI_DCR2,OctoSPI Device Configuration Register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,This field indicates the wrap-size to which the memory is configured. For memories which" "0: wrapped reads are not supported by the memory.,1: reserved,2: external memory supports wrap size of 16 bytes..,3: external memory supports wrap size of 32 bytes..,4: external memory supports wrap size of 64 bytes..,5: external memory supports wrap size of 128 bytes,?,?" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,This field defines the scaler factor for generating CLK based on the AHB clock (value+1)." line.long 0x8 "OCTOSPI_DCR3,OctoSPI Device Configuration Register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,This bits enable the transaction boundary feature." hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,This bits enable the communication regulation feature." line.long 0xC "OCTOSPI_DCR4,OctoSPI Device Configuration Register 4" hexmask.long 0xC 0.--31. 1. "REFRESH,This bits enable the refresh rate feature." rgroup.long 0x20++0x3 line.long 0x0 "OCTOSPI_SR,OctoSPI Status Register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,This field gives the number of valid bytes which are being held in the FIFO. FLEVEL=0 when the FIFO is empty and 32 when it is full. In memory-mapped mode and in automatic" bitfld.long 0x0 5. "BUSY,This bit is set when an operation is on going. This bit clears automatically when the operation with the external device is finished and the FIFO is empty." "0,1" newline bitfld.long 0x0 4. "TOF,This bit is set when timeout occurs.It is cleared by writing 1 to CTOF." "0,1" bitfld.long 0x0 3. "SMF,This bit is set in automatic polling mode when the unmasked received data matches the corresponding bits in the match register (OCTOSPI_PSMAR). It is cleared by writing 1 to CSMF." "0,1" newline bitfld.long 0x0 2. "FTF,In indrect mode this bit is set when the FIFO threshold has been reached or if there is any data left in the FIFO after reads from the external device are complete. It is cleared" "0,1" bitfld.long 0x0 1. "TCF,This bit is set in indirect mode when the programmed number of data has been transferred or in any mode when the transfer has been aborted.It is cleared by writing 1 to" "0,1" newline bitfld.long 0x0 0. "TEF,This bit is set in indirect mode when an invalid address is being accessed in indirect mode. It is cleared by writing 1 to CTEF." "0,1" group.long 0x24++0x3 line.long 0x0 "OCTOSPI_FCR,OctoSPI Flag Clear Register" bitfld.long 0x0 4. "CTOF,Writing 1 clears the TOF flag in the OCTOSPI_SR register" "0,1" bitfld.long 0x0 3. "CSMF,Writing 1 clears the SMF flag in the OCTOSPI_SR register" "0,1" newline bitfld.long 0x0 1. "CTCF,Writing 1 clears the TCF flag in the OCTOSPI_SR register" "0,1" bitfld.long 0x0 0. "CTEF,Writing 1 clears the TEF flag in the OCTOSPI_SR register" "0,1" group.long 0x40++0x3 line.long 0x0 "OCTOSPI_DLR,OctoSPI Data Length Register" hexmask.long 0x0 0.--31. 1. "DL,Number of data to be retrieved (value+1) in indirect and status-polling modes. A value no greater than 3 (indicating 4 bytes) should be used for status-polling mode." group.long 0x48++0x3 line.long 0x0 "OCTOSPI_AR,OctoSPI Address Register" hexmask.long 0x0 0.--31. 1. "ADDRESS,Address to be send to the external device." group.long 0x50++0x3 line.long 0x0 "OCTOSPI_DR,OctoSPI Data Register" hexmask.long 0x0 0.--31. 1. "DATA,Data to be sent/received to/from the external SPI device." group.long 0x80++0x3 line.long 0x0 "OCTOSPI_PSMKR,OctoSPI Polling Status Mask Register" hexmask.long 0x0 0.--31. 1. "MASK,Mask to be applied to the status bytes received in polling mode." group.long 0x88++0x3 line.long 0x0 "OCTOSPI_PSMAR,OctoSPI Polling Status Match Register" hexmask.long 0x0 0.--31. 1. "MATCH,Value to be compared with the masked status register to get a match." group.long 0x90++0x3 line.long 0x0 "OCTOSPI_PIR,OctoSPI Polling Interval Register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,Number of CLK cycle between to read during automatic polling phases." group.long 0x100++0x3 line.long 0x0 "OCTOSPI_CCR,OctoSPI Communication Configuration Register" bitfld.long 0x0 31. "SIOO,See Section : Sending the instruction only once on page 28. This bit has no effect when IMODE=00." "0: Send instruction on every transaction,1: Send instruction only for the first command" bitfld.long 0x0 29. "DQSE,This bit enables the data strobe management." "0: DQS disabled,1: DQS enabled" newline bitfld.long 0x0 27. "DDTR,This bit sets the DTR Mode for the alternate bytes phase." "0: DTR Mode disabled for alternate bytes phase,1: DTR Mode enabled for alternate bytes phase" bitfld.long 0x0 24.--26. "DMODE,This field defines the data phase’s mode of operation." "0: No Instruction,1: Data on a single line,2: Data on two lines,3: Data on four lines,4: Data on eight lines,?,?,?" newline bitfld.long 0x0 20.--21. "ABSIZE,This bit defines alternate bytes size." "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" bitfld.long 0x0 19. "ABDTR,This bit sets the DTR Mode for the alternate bytes phase." "0: DTR Mode disabled for alternate bytes phase,1: DTR Mode enabled for alternate bytes phase" newline bitfld.long 0x0 16.--18. "ABMODE,This field defines the alternate byte phase’s mode of operation." "0: No instruction,1: Alternate bytes on a single line,2: Alternate bytes on two lines,3: Alternate bytes on four lines,4: Alternate bytes on eight lines,?,?,?" bitfld.long 0x0 12.--13. "ADSIZE,This bit defines address size." "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" newline bitfld.long 0x0 11. "ADDTR,This bit sets the DTR Mode for the address phase." "0: DTR Mode disabled for address phase,1: DTR Mode enabled for address phase" bitfld.long 0x0 8.--10. "ADMODE,This field defines the address phase’s mode of operation." "0: No Address,1: Address on a single line,2: Address on two lines,3: Address on four lines,4: Address on eight lines,?,?,?" newline bitfld.long 0x0 4.--5. "ISIZE,This bit defines instruction size." "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" bitfld.long 0x0 3. "IDTR,This bit sets the DTR Mode for the instruction phase." "0: DTR Mode disabled for instruction phase,1: DTR Mode enabled for instruction phase" newline bitfld.long 0x0 0.--2. "IMODE,This field defines the instruction phase’s mode of operation:" "0: No instruction,1: Instruction on a single line,2: Instruction on two lines,3: Instruction on four lines,4: Instruction on eight lines,?,?,?" group.long 0x108++0x3 line.long 0x0 "OCTOSPI_TCR,OctoSPI Timing Configuration Register" bitfld.long 0x0 30. "SSHIFT,By default the OctoSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data is to be sampled later in order to account for external signal delays." "0: No shift,1: 1/2 cycle shift" bitfld.long 0x0 28. "DHQC,This field defines the delay hold quarter cycle." "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "DCYC,This field defines the duration of the dummy phase. In both SDR and DTR modes it specifies a number of CLK cycles (0-31)." group.long 0x110++0x3 line.long 0x0 "OCTOSPI_IR,OctoSPI Instruction Register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction to be send to the external SPI device." group.long 0x120++0x3 line.long 0x0 "OCTOSPI_ABR,OctoSPI Alternate Bytes Register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Optional data to be send to the external SPI device right after the address." group.long 0x130++0x3 line.long 0x0 "OCTOSPI_LPTR,OctoSPI Low Power Timeout Register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,After each access in memory-mapped mode OctoSPI prefetches the subsequent bytes and holds these bytes in the FIFO. This field indicates how many CLK cycles OctoSPI waits after the FIFO becomes full until it raises nCS putting the external.." group.long 0x140++0x3 line.long 0x0 "OCTOSPI_WPCCR,OctoSPI Wrap Communication Configuration Register" bitfld.long 0x0 31. "SIOO,See Section : Sending the instruction only once on page 28. This bit has no effect when IMODE=00." "0: Send instruction on every transaction,1: Send instruction only for the first command" bitfld.long 0x0 29. "DQSE,This bit enables the data strobe management." "0: DQS disabled,1: DQS enabled" newline bitfld.long 0x0 27. "DDTR,This bit sets the DTR Mode for the alternate bytes phase." "0: DTR Mode disabled for alternate bytes phase,1: DTR Mode enabled for alternate bytes phase" bitfld.long 0x0 24.--26. "DMODE,This field defines the data phase’s mode of operation." "0: No Instruction,1: Data on a single line,2: Data on two lines,3: Data on four lines,4: Data on eight lines,?,?,?" newline bitfld.long 0x0 20.--21. "ABSIZE,This bit defines alternate bytes size." "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" bitfld.long 0x0 19. "ABDTR,This bit sets the DTR Mode for the alternate bytes phase." "0: DTR Mode disabled for alternate bytes phase,1: DTR Mode enabled for alternate bytes phase" newline bitfld.long 0x0 16.--18. "ABMODE,This field defines the alternate byte phase’s mode of operation." "0: No instruction,1: Alternate bytes on a single line,2: Alternate bytes on two lines,3: Alternate bytes on four lines,4: Alternate bytes on eight lines,?,?,?" bitfld.long 0x0 12.--13. "ADSIZE,This bit defines address size." "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" newline bitfld.long 0x0 11. "ADDTR,This bit sets the DTR Mode for the address phase." "0: DTR Mode disabled for address phase,1: DTR Mode enabled for address phase" bitfld.long 0x0 8.--10. "ADMODE,This field defines the address phase’s mode of operation." "0: No Address,1: Address on a single line,2: Address on two lines,3: Address on four lines,4: Address on eight lines,?,?,?" newline bitfld.long 0x0 4.--5. "ISIZE,This bit defines instruction size." "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" bitfld.long 0x0 3. "IDTR,This bit sets the DTR Mode for the instruction phase:" "0: DTR Mode disabled for instruction phase,1: DTR Mode enabled for instruction phase" newline bitfld.long 0x0 0.--2. "IMODE,This field defines the instruction phase’s mode of operation." "0: No instruction,1: Instruction on a single line,2: Instruction on two lines,3: Instruction on four lines,4: Instruction on eight lines,?,?,?" group.long 0x148++0x3 line.long 0x0 "OCTOSPI_WPTCR,OctoSPI Wrap Timing Configuration Register" bitfld.long 0x0 30. "SSHIFT,By default the OctoSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data is to be sampled later in order to account for external signal delays." "0: No shift,1: 1/2 cycle shift" bitfld.long 0x0 28. "DHQC,This field defines the delay hold quarter cycle." "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "DCYC,This field defines the duration of the dummy phase. In both SDR and DTR modes it specifies a number of CLK cycles (0-31)." group.long 0x150++0x3 line.long 0x0 "OCTOSPI_WPIR,OctoSPI Wrap Instruction Register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction to be send to the external SPI device." group.long 0x160++0x3 line.long 0x0 "OCTOSPI_WPABR,OctoSPI Wrap Alternate Bytes Register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Optional data to be send to the external SPI device right after the address." group.long 0x180++0x3 line.long 0x0 "OCTOSPI_WCCR,OctoSPI Write Communication Configuration Register" bitfld.long 0x0 31. "SIOO,See Section : Sending the instruction only once on page 28. This bit has no effect when IMODE=00." "0: Send instruction on every transaction,1: Send instruction only for the first command" bitfld.long 0x0 29. "DQSE,This bit enables the data strobe management." "0: DQS disabled,1: DQS enabled" newline bitfld.long 0x0 27. "DDTR,This bit sets the DTR Mode for the alternate bytes phase." "0: DTR Mode disabled for alternate bytes phase,1: DTR Mode enabled for alternate bytes phase" bitfld.long 0x0 24.--26. "DMODE,This field defines the data phase’s mode of operation." "0: No Instruction,1: Data on a single line,2: Data on two lines,3: Data on four lines,4: Data on eight lines,?,?,?" newline bitfld.long 0x0 20.--21. "ABSIZE,This bit defines alternate bytes size." "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" bitfld.long 0x0 19. "ABDTR,This bit sets the DTR Mode for the alternate bytes phase." "0: DTR Mode disabled for alternate bytes phase,1: DTR Mode enabled for alternate bytes phase" newline bitfld.long 0x0 16.--18. "ABMODE,This field defines the alternate byte phase’s mode of operation." "0: No instruction,1: Alternate bytes on a single line,2: Alternate bytes on two lines,3: Alternate bytes on four lines,4: Alternate bytes on eight lines,?,?,?" bitfld.long 0x0 12.--13. "ADSIZE,This bit defines address size." "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" newline bitfld.long 0x0 11. "ADDTR,This bit sets the DTR Mode for the address phase." "0: DTR Mode disabled for address phase,1: DTR Mode enabled for address phase" bitfld.long 0x0 8.--10. "ADMODE,This field defines the address phase’s mode of operation." "0: No Address,1: Address on a single line,2: Address on two lines,3: Address on four lines,4: Address on eight lines,?,?,?" newline bitfld.long 0x0 4.--5. "ISIZE,This bit defines instruction size." "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" bitfld.long 0x0 3. "IDTR,This bit sets the DTR Mode for the instruction phase." "0: DTR Mode disabled for instruction phase,1: DTR Mode enabled for instruction phase" newline bitfld.long 0x0 0.--2. "IMODE,This field defines the instruction phase’s mode of operation:" "0: No instruction,1: Instruction on a single line,2: Instruction on two lines,3: Instruction on four lines,4: Instruction on eight lines,?,?,?" group.long 0x188++0x3 line.long 0x0 "OCTOSPI_WTCR,OctoSPI Write Timing Configuration Register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,This field defines the duration of the dummy phase. In both SDR and DTR modes it" group.long 0x190++0x3 line.long 0x0 "OCTOSPI_WIR,OctoSPI Write Instruction Register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction to be send to the external SPI device." group.long 0x1A0++0x3 line.long 0x0 "OCTOSPI_WABR,OctoSPI Write Alternate Bytes Register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Optional data to be send to the external SPI device right after the address." group.long 0x200++0x3 line.long 0x0 "OCTOSPI_HLCR,OctoSPI Hyperbus Latency Configuration Register" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Device read write recovery time expressed in number of communication clock cycles." hexmask.long.byte 0x0 8.--15. 1. "TACC,Device access time expressed in number of communication clock cycles." newline bitfld.long 0x0 1. "WZL,This bit enables zero latency on write operations." "0: Latency on write accesses,1: No latency on write accesses" bitfld.long 0x0 0. "LM,This bit select the latency mode." "0: Variable initial latency,1: Fixed latency" rgroup.long 0x3F0++0xF line.long 0x0 "OCTOSPI_HWCFGR,OctoSPI HW Configuration Register" hexmask.long.byte 0x0 28.--31. 1. "ARB_MASTER,Defines the arbitration in the IP" hexmask.long.byte 0x0 24.--27. 1. "MMW_EN,Memory Mapped Write Enabled" newline hexmask.long.byte 0x0 20.--23. 1. "ID_LENGTH,ID Length used inside IP for AXI Interface" hexmask.long.byte 0x0 12.--19. 1. "PRESC_RST_VAL,Reset Value of Prescaler to be applied." newline hexmask.long.byte 0x0 4.--11. 1. "FIFO_DEPTH,TX and RX FIFO in Words to be instantiated inside the IP." hexmask.long.byte 0x0 0.--3. 1. "AXI_INTERFACE,The Bus Interface of IP is AXI or AHB." line.long 0x4 "OCTOSPI_VER,OctoSPI Version Register" hexmask.long.byte 0x4 0.--7. 1. "VER,This field returns the IP Version." line.long 0x8 "OCTOSPI_ID,OctoSPI Identification" hexmask.long 0x8 0.--31. 1. "ID,This field returns the Identification of the OctoSPI IP." line.long 0xC "OCTOSPI_MID,OctoSPI HW Magic ID" hexmask.long 0xC 0.--31. 1. "MID,This field returns the Magic ID of the OctoSPI IP." tree.end tree "OCTOSPIIOM_ADR" base ad:0x4FFFF800 group.long 0x0++0xB line.long 0x0 "OCTOSPIIOM_CR,OctoSPI IO Manager Control Register" hexmask.long.byte 0x0 16.--23. 1. "REQ2ACK_TIME,In multiplexed mode (MUXEN = 1) this field defines the time between two transaction." bitfld.long 0x0 0. "MUXEN,This bit enables the multiplexing of the two OctoSPI." "0: No multiplexing,1: OctoSPI1 and OctoSPI2 are multiplexed over the.." line.long 0x4 "OCTOSPIIOM_P1CR,OctoSPI IO Manager Control Register" bitfld.long 0x4 25.--26. "IOHSRC,This bits select the source of Port n IO[7:4]." "0: OCTOSPI1_IO[3:0] in non muxed mode /..,1: OCTOSPI1_IO[7:4] in non muxed mode /..,2: OCTOSPI2_IO[3:0] in non muxed mode / unused in..,3: OCTOSPI2_IO[7:4] in non muxed mode / unused in.." bitfld.long 0x4 24. "IOHEN,This bit enables the Port n IO[7:4]." "0: IO[7:4] for Port n is disabled,1: IO[7:4] for Port n is enabled" newline bitfld.long 0x4 17.--18. "IOLSRC,This bits select the source of Port n IO[3:0]." "0: OCTOSPI1_IO[3:0] in non muxed mode /..,1: OCTOSPI1_IO[7:4] in non muxed mode /..,2: OCTOSPI2_IO[3:0] in non muxed mode / unused in..,3: OCTOSPI2_IO[7:4] in non muxed mode / unused in.." bitfld.long 0x4 16. "IOLEN,This bit enables the Port n IO[3:0]." "0: IO[3:0] for Port n is disabled,1: IO[3:0] for Port n is enabled" newline bitfld.long 0x4 9. "NCSSRC,This bit selects the source of Port n nCS." "0: OCTOSPI1_nCS,1: OCTOSPI2_nCS" bitfld.long 0x4 8. "NCSEN,This bit enables the Port n nCS." "0: nCS for Port n is disabled,1: nCS for Port n is enabled" newline bitfld.long 0x4 5. "DQSSRC,This bit selects the source of Port n DQS." "0: OCTOSPI1_DQS in non muxed mode / MUXED_DQS in..,1: OCTOSPI2_DQS in non muxed mode / unused port in.." bitfld.long 0x4 4. "DQSEN,This bit enables the Port n DQS." "0: DQS for Port n is disabled,1: DQS for Port n is enabled" newline bitfld.long 0x4 1. "CLKSRC,This bit selects the source of Port n CLK/CLKn." "0: OCTOSPI1_CLK/CLKn in non muxed mode /..,1: OCTOSPI2_CLK/CLKn in non muxed mode / unused.." bitfld.long 0x4 0. "CLKEN,This bit enables the Port n CLK/CLKn." "0: CLK/CLKn for Port n is disabled,1: CLK/CLKn for Port n is enabled" line.long 0x8 "OCTOSPIIOM_P2CR,OctoSPI IO Manager Control Register" bitfld.long 0x8 25.--26. "IOHSRC,This bits select the source of Port n IO[7:4]." "0: OCTOSPI1_IO[3:0] in non muxed mode /..,1: OCTOSPI1_IO[7:4] in non muxed mode /..,2: OCTOSPI2_IO[3:0] in non muxed mode / unused in..,3: OCTOSPI2_IO[7:4] in non muxed mode / unused in.." bitfld.long 0x8 24. "IOHEN,This bit enables the Port n IO[7:4]." "0: IO[7:4] for Port n is disabled,1: IO[7:4] for Port n is enabled" newline bitfld.long 0x8 17.--18. "IOLSRC,This bits select the source of Port n IO[3:0]." "0: OCTOSPI1_IO[3:0] in non muxed mode /..,1: OCTOSPI1_IO[7:4] in non muxed mode /..,2: OCTOSPI2_IO[3:0] in non muxed mode / unused in..,3: OCTOSPI2_IO[7:4] in non muxed mode / unused in.." bitfld.long 0x8 16. "IOLEN,This bit enables the Port n IO[3:0]." "0: IO[3:0] for Port n is disabled,1: IO[3:0] for Port n is enabled" newline bitfld.long 0x8 9. "NCSSRC,This bit selects the source of Port n nCS." "0: OCTOSPI1_nCS,1: OCTOSPI2_nCS" bitfld.long 0x8 8. "NCSEN,This bit enables the Port n nCS." "0: nCS for Port n is disabled,1: nCS for Port n is enabled" newline bitfld.long 0x8 5. "DQSSRC,This bit selects the source of Port n DQS." "0: OCTOSPI1_DQS in non muxed mode / MUXED_DQS in..,1: OCTOSPI2_DQS in non muxed mode / unused port in.." bitfld.long 0x8 4. "DQSEN,This bit enables the Port n DQS." "0: DQS for Port n is disabled,1: DQS for Port n is enabled" newline bitfld.long 0x8 1. "CLKSRC,This bit selects the source of Port n CLK/CLKn." "0: OCTOSPI1_CLK/CLKn in non muxed mode /..,1: OCTOSPI2_CLK/CLKn in non muxed mode / unused.." bitfld.long 0x8 0. "CLKEN,This bit enables the Port n CLK/CLKn." "0: CLK/CLKn for Port n is disabled,1: CLK/CLKn for Port n is enabled" tree.end tree.end tree "OSC32K_DIG (OSC32K Digital Interface)" base ad:0x722C80C0 group.long 0x0++0x3 line.long 0x0 "SXOSC_CTL,OSC32K Control register" bitfld.long 0x0 31. "OSCBYP,Crystal Oscillator bypass" "0: Oscillator output is used as root clock,1: EXTAL is used as root clock" hexmask.long.byte 0x0 16.--23. 1. "EOCV,End of Count Value" newline bitfld.long 0x0 15. "M_OSC,Crystal oscillator clock interrupt mask" "0: Crystal oscillator clock interrupt is masked,1: Crystal oscillator clock interrupt is enabled" hexmask.long.byte 0x0 8.--12. 1. "OSCDIV,Crystal oscillator clock division factor" newline bitfld.long 0x0 7. "I_OSC,Crystal oscillator clock interrupt" "0: No oscillator clock interrupt occurred,1: Oscillator clock interrupt pending" bitfld.long 0x0 1. "S_OSC,Crystal oscillator status" "0: Crystal oscillator output clock is not stable,1: Crystal oscillator is providing a stable clock" newline bitfld.long 0x0 0. "OSCON,Crystal oscillator power-down control" "0: Crystal oscillator is switched off,1: Crystal oscillator is switched on" tree.end tree "OSC40M_DIG (OSC40M Digital Interface)" base ad:0x722C8080 group.long 0x0++0x3 line.long 0x0 "CTL,XOSC Control register" bitfld.long 0x0 31. "OSCBYP,Crystal Oscillator bypass" "0: Oscillator output is used as root clock.,1: EXTAL is used as root clock." hexmask.long.byte 0x0 16.--23. 1. "EOCV,End of Count Value" newline bitfld.long 0x0 15. "M_OSC,Crystal oscillator clock interrupt mask" "0: Crystal oscillator clock interrupt is masked.,1: Crystal oscillator clock interrupt is enabled." hexmask.long.byte 0x0 8.--12. 1. "OSCDIV,Crystal oscillator clock division factor" newline bitfld.long 0x0 7. "I_OSC,Crystal oscillator clock interrupt" "0: No oscillator clock interrupt occurred.,1: Oscillator clock interrupt pending." tree.end tree "OVLY_CTRL (Overlay Controller)" base ad:0x0 tree "OVLY_CTRL_0" base ad:0x71060000 group.long 0x0++0x7 line.long 0x0 "OVLY_CRCR,Overlay Calibration Remap Control Register" bitfld.long 0x0 31. "BUFFER_RDATA,Enable buffer on response data path" "0: Data from Overlay RAM available in same cycle as..,1: Data from Overlay RAM available earlier than NVM.." bitfld.long 0x0 0. "CR_EN,Calibration Remap Enable" "0: Calibration remap evaluation is not performed on..,1: Calibration remap evaluation is performed on all.." line.long 0x4 "OVLY_CRDE,Overlay Calibration Remap Descriptor Enable register" hexmask.long.word 0x4 0.--15. 1. "CRD_EN,Calibration Remap Descriptor Enable." group.long 0x10++0xB line.long 0x0 "CRD0_W0,Calibration Remap Descriptor 0 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD0_W1,Calibration Remap Descriptor 0 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD0_W2,Calibration Remap Descriptor 0 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x20++0xB line.long 0x0 "CRD1_W0,Calibration Remap Descriptor 1 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD1_W1,Calibration Remap Descriptor 1 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD1_W2,Calibration Remap Descriptor 1 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x30++0xB line.long 0x0 "CRD2_W0,Calibration Remap Descriptor 2 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD2_W1,Calibration Remap Descriptor 2 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD2_W2,Calibration Remap Descriptor 2 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x40++0xB line.long 0x0 "CRD3_W0,Calibration Remap Descriptor 3 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD3_W1,Calibration Remap Descriptor 3 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD3_W2,Calibration Remap Descriptor 3 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x50++0xB line.long 0x0 "CRD4_W0,Calibration Remap Descriptor 4 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD4_W1,Calibration Remap Descriptor 4 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD4_W2,Calibration Remap Descriptor 4 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x60++0xB line.long 0x0 "CRD5_W0,Calibration Remap Descriptor 5 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD5_W1,Calibration Remap Descriptor 5 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD5_W2,Calibration Remap Descriptor 5 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x70++0xB line.long 0x0 "CRD6_W0,Calibration Remap Descriptor 6 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD6_W1,Calibration Remap Descriptor 6 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD6_W2,Calibration Remap Descriptor 6 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x80++0xB line.long 0x0 "CRD7_W0,Calibration Remap Descriptor 7 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD7_W1,Calibration Remap Descriptor 7 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD7_W2,Calibration Remap Descriptor 7 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x90++0xB line.long 0x0 "CRD8_W0,Calibration Remap Descriptor 8 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD8_W1,Calibration Remap Descriptor 8 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD8_W2,Calibration Remap Descriptor 8 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xA0++0xB line.long 0x0 "CRD9_W0,Calibration Remap Descriptor 9 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD9_W1,Calibration Remap Descriptor 9 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD9_W2,Calibration Remap Descriptor 9 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xB0++0xB line.long 0x0 "CRD10_W0,Calibration Remap Descriptor 10 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD10_W1,Calibration Remap Descriptor 10 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD10_W2,Calibration Remap Descriptor 10 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xC0++0xB line.long 0x0 "CRD11_W0,Calibration Remap Descriptor 11 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD11_W1,Calibration Remap Descriptor 11 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD11_W2,Calibration Remap Descriptor 11 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xD0++0xB line.long 0x0 "CRD12_W0,Calibration Remap Descriptor 12 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD12_W1,Calibration Remap Descriptor 12 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD12_W2,Calibration Remap Descriptor 12 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xE0++0xB line.long 0x0 "CRD13_W0,Calibration Remap Descriptor 13 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD13_W1,Calibration Remap Descriptor 13 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD13_W2,Calibration Remap Descriptor 13 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xF0++0xB line.long 0x0 "CRD14_W0,Calibration Remap Descriptor 14 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD14_W1,Calibration Remap Descriptor 14 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD14_W2,Calibration Remap Descriptor 14 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x100++0xB line.long 0x0 "CRD15_W0,Calibration Remap Descriptor 15 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD15_W1,Calibration Remap Descriptor 15 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD15_W2,Calibration Remap Descriptor 15 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" tree.end tree "OVLY_CTRL_1" base ad:0x71660000 group.long 0x0++0x7 line.long 0x0 "OVLY_CRCR,Overlay Calibration Remap Control Register" bitfld.long 0x0 31. "BUFFER_RDATA,Enable buffer on response data path" "0: Data from Overlay RAM available in same cycle as..,1: Data from Overlay RAM available earlier than NVM.." bitfld.long 0x0 0. "CR_EN,Calibration Remap Enable" "0: Calibration remap evaluation is not performed on..,1: Calibration remap evaluation is performed on all.." line.long 0x4 "OVLY_CRDE,Overlay Calibration Remap Descriptor Enable register" hexmask.long.word 0x4 0.--15. 1. "CRD_EN,Calibration Remap Descriptor Enable." group.long 0x10++0xB line.long 0x0 "CRD0_W0,Calibration Remap Descriptor 0 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD0_W1,Calibration Remap Descriptor 0 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD0_W2,Calibration Remap Descriptor 0 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x20++0xB line.long 0x0 "CRD1_W0,Calibration Remap Descriptor 1 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD1_W1,Calibration Remap Descriptor 1 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD1_W2,Calibration Remap Descriptor 1 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x30++0xB line.long 0x0 "CRD2_W0,Calibration Remap Descriptor 2 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD2_W1,Calibration Remap Descriptor 2 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD2_W2,Calibration Remap Descriptor 2 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x40++0xB line.long 0x0 "CRD3_W0,Calibration Remap Descriptor 3 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD3_W1,Calibration Remap Descriptor 3 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD3_W2,Calibration Remap Descriptor 3 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x50++0xB line.long 0x0 "CRD4_W0,Calibration Remap Descriptor 4 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD4_W1,Calibration Remap Descriptor 4 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD4_W2,Calibration Remap Descriptor 4 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x60++0xB line.long 0x0 "CRD5_W0,Calibration Remap Descriptor 5 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD5_W1,Calibration Remap Descriptor 5 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD5_W2,Calibration Remap Descriptor 5 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x70++0xB line.long 0x0 "CRD6_W0,Calibration Remap Descriptor 6 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD6_W1,Calibration Remap Descriptor 6 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD6_W2,Calibration Remap Descriptor 6 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x80++0xB line.long 0x0 "CRD7_W0,Calibration Remap Descriptor 7 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD7_W1,Calibration Remap Descriptor 7 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD7_W2,Calibration Remap Descriptor 7 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x90++0xB line.long 0x0 "CRD8_W0,Calibration Remap Descriptor 8 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD8_W1,Calibration Remap Descriptor 8 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD8_W2,Calibration Remap Descriptor 8 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xA0++0xB line.long 0x0 "CRD9_W0,Calibration Remap Descriptor 9 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD9_W1,Calibration Remap Descriptor 9 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD9_W2,Calibration Remap Descriptor 9 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xB0++0xB line.long 0x0 "CRD10_W0,Calibration Remap Descriptor 10 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD10_W1,Calibration Remap Descriptor 10 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD10_W2,Calibration Remap Descriptor 10 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xC0++0xB line.long 0x0 "CRD11_W0,Calibration Remap Descriptor 11 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD11_W1,Calibration Remap Descriptor 11 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD11_W2,Calibration Remap Descriptor 11 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xD0++0xB line.long 0x0 "CRD12_W0,Calibration Remap Descriptor 12 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD12_W1,Calibration Remap Descriptor 12 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD12_W2,Calibration Remap Descriptor 12 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xE0++0xB line.long 0x0 "CRD13_W0,Calibration Remap Descriptor 13 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD13_W1,Calibration Remap Descriptor 13 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD13_W2,Calibration Remap Descriptor 13 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xF0++0xB line.long 0x0 "CRD14_W0,Calibration Remap Descriptor 14 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD14_W1,Calibration Remap Descriptor 14 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD14_W2,Calibration Remap Descriptor 14 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x100++0xB line.long 0x0 "CRD15_W0,Calibration Remap Descriptor 15 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD15_W1,Calibration Remap Descriptor 15 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD15_W2,Calibration Remap Descriptor 15 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" tree.end tree "OVLY_CTRL_2" base ad:0x71064000 group.long 0x0++0x7 line.long 0x0 "OVLY_CRCR,Overlay Calibration Remap Control Register" bitfld.long 0x0 31. "BUFFER_RDATA,Enable buffer on response data path" "0: Data from Overlay RAM available in same cycle as..,1: Data from Overlay RAM available earlier than NVM.." bitfld.long 0x0 0. "CR_EN,Calibration Remap Enable" "0: Calibration remap evaluation is not performed on..,1: Calibration remap evaluation is performed on all.." line.long 0x4 "OVLY_CRDE,Overlay Calibration Remap Descriptor Enable register" hexmask.long.word 0x4 0.--15. 1. "CRD_EN,Calibration Remap Descriptor Enable." group.long 0x10++0xB line.long 0x0 "CRD0_W0,Calibration Remap Descriptor 0 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD0_W1,Calibration Remap Descriptor 0 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD0_W2,Calibration Remap Descriptor 0 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x20++0xB line.long 0x0 "CRD1_W0,Calibration Remap Descriptor 1 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD1_W1,Calibration Remap Descriptor 1 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD1_W2,Calibration Remap Descriptor 1 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x30++0xB line.long 0x0 "CRD2_W0,Calibration Remap Descriptor 2 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD2_W1,Calibration Remap Descriptor 2 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD2_W2,Calibration Remap Descriptor 2 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x40++0xB line.long 0x0 "CRD3_W0,Calibration Remap Descriptor 3 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD3_W1,Calibration Remap Descriptor 3 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD3_W2,Calibration Remap Descriptor 3 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x50++0xB line.long 0x0 "CRD4_W0,Calibration Remap Descriptor 4 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD4_W1,Calibration Remap Descriptor 4 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD4_W2,Calibration Remap Descriptor 4 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x60++0xB line.long 0x0 "CRD5_W0,Calibration Remap Descriptor 5 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD5_W1,Calibration Remap Descriptor 5 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD5_W2,Calibration Remap Descriptor 5 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x70++0xB line.long 0x0 "CRD6_W0,Calibration Remap Descriptor 6 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD6_W1,Calibration Remap Descriptor 6 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD6_W2,Calibration Remap Descriptor 6 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x80++0xB line.long 0x0 "CRD7_W0,Calibration Remap Descriptor 7 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD7_W1,Calibration Remap Descriptor 7 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD7_W2,Calibration Remap Descriptor 7 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x90++0xB line.long 0x0 "CRD8_W0,Calibration Remap Descriptor 8 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD8_W1,Calibration Remap Descriptor 8 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD8_W2,Calibration Remap Descriptor 8 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xA0++0xB line.long 0x0 "CRD9_W0,Calibration Remap Descriptor 9 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD9_W1,Calibration Remap Descriptor 9 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD9_W2,Calibration Remap Descriptor 9 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xB0++0xB line.long 0x0 "CRD10_W0,Calibration Remap Descriptor 10 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD10_W1,Calibration Remap Descriptor 10 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD10_W2,Calibration Remap Descriptor 10 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xC0++0xB line.long 0x0 "CRD11_W0,Calibration Remap Descriptor 11 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD11_W1,Calibration Remap Descriptor 11 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD11_W2,Calibration Remap Descriptor 11 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xD0++0xB line.long 0x0 "CRD12_W0,Calibration Remap Descriptor 12 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD12_W1,Calibration Remap Descriptor 12 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD12_W2,Calibration Remap Descriptor 12 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xE0++0xB line.long 0x0 "CRD13_W0,Calibration Remap Descriptor 13 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD13_W1,Calibration Remap Descriptor 13 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD13_W2,Calibration Remap Descriptor 13 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xF0++0xB line.long 0x0 "CRD14_W0,Calibration Remap Descriptor 14 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD14_W1,Calibration Remap Descriptor 14 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD14_W2,Calibration Remap Descriptor 14 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x100++0xB line.long 0x0 "CRD15_W0,Calibration Remap Descriptor 15 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD15_W1,Calibration Remap Descriptor 15 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD15_W2,Calibration Remap Descriptor 15 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" tree.end tree "OVLY_CTRL_3" base ad:0x71664000 group.long 0x0++0x7 line.long 0x0 "OVLY_CRCR,Overlay Calibration Remap Control Register" bitfld.long 0x0 31. "BUFFER_RDATA,Enable buffer on response data path" "0: Data from Overlay RAM available in same cycle as..,1: Data from Overlay RAM available earlier than NVM.." bitfld.long 0x0 0. "CR_EN,Calibration Remap Enable" "0: Calibration remap evaluation is not performed on..,1: Calibration remap evaluation is performed on all.." line.long 0x4 "OVLY_CRDE,Overlay Calibration Remap Descriptor Enable register" hexmask.long.word 0x4 0.--15. 1. "CRD_EN,Calibration Remap Descriptor Enable." group.long 0x10++0xB line.long 0x0 "CRD0_W0,Calibration Remap Descriptor 0 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD0_W1,Calibration Remap Descriptor 0 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD0_W2,Calibration Remap Descriptor 0 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x20++0xB line.long 0x0 "CRD1_W0,Calibration Remap Descriptor 1 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD1_W1,Calibration Remap Descriptor 1 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD1_W2,Calibration Remap Descriptor 1 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x30++0xB line.long 0x0 "CRD2_W0,Calibration Remap Descriptor 2 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD2_W1,Calibration Remap Descriptor 2 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD2_W2,Calibration Remap Descriptor 2 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x40++0xB line.long 0x0 "CRD3_W0,Calibration Remap Descriptor 3 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD3_W1,Calibration Remap Descriptor 3 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD3_W2,Calibration Remap Descriptor 3 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x50++0xB line.long 0x0 "CRD4_W0,Calibration Remap Descriptor 4 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD4_W1,Calibration Remap Descriptor 4 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD4_W2,Calibration Remap Descriptor 4 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x60++0xB line.long 0x0 "CRD5_W0,Calibration Remap Descriptor 5 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD5_W1,Calibration Remap Descriptor 5 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD5_W2,Calibration Remap Descriptor 5 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x70++0xB line.long 0x0 "CRD6_W0,Calibration Remap Descriptor 6 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD6_W1,Calibration Remap Descriptor 6 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD6_W2,Calibration Remap Descriptor 6 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x80++0xB line.long 0x0 "CRD7_W0,Calibration Remap Descriptor 7 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD7_W1,Calibration Remap Descriptor 7 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD7_W2,Calibration Remap Descriptor 7 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x90++0xB line.long 0x0 "CRD8_W0,Calibration Remap Descriptor 8 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD8_W1,Calibration Remap Descriptor 8 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD8_W2,Calibration Remap Descriptor 8 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xA0++0xB line.long 0x0 "CRD9_W0,Calibration Remap Descriptor 9 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD9_W1,Calibration Remap Descriptor 9 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD9_W2,Calibration Remap Descriptor 9 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xB0++0xB line.long 0x0 "CRD10_W0,Calibration Remap Descriptor 10 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD10_W1,Calibration Remap Descriptor 10 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD10_W2,Calibration Remap Descriptor 10 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xC0++0xB line.long 0x0 "CRD11_W0,Calibration Remap Descriptor 11 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD11_W1,Calibration Remap Descriptor 11 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD11_W2,Calibration Remap Descriptor 11 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xD0++0xB line.long 0x0 "CRD12_W0,Calibration Remap Descriptor 12 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD12_W1,Calibration Remap Descriptor 12 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD12_W2,Calibration Remap Descriptor 12 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xE0++0xB line.long 0x0 "CRD13_W0,Calibration Remap Descriptor 13 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD13_W1,Calibration Remap Descriptor 13 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD13_W2,Calibration Remap Descriptor 13 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xF0++0xB line.long 0x0 "CRD14_W0,Calibration Remap Descriptor 14 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD14_W1,Calibration Remap Descriptor 14 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD14_W2,Calibration Remap Descriptor 14 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x100++0xB line.long 0x0 "CRD15_W0,Calibration Remap Descriptor 15 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD15_W1,Calibration Remap Descriptor 15 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD15_W2,Calibration Remap Descriptor 15 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" tree.end tree "OVLY_CTRL_4" base ad:0x71068000 group.long 0x0++0x7 line.long 0x0 "OVLY_CRCR,Overlay Calibration Remap Control Register" bitfld.long 0x0 31. "BUFFER_RDATA,Enable buffer on response data path" "0: Data from Overlay RAM available in same cycle as..,1: Data from Overlay RAM available earlier than NVM.." bitfld.long 0x0 0. "CR_EN,Calibration Remap Enable" "0: Calibration remap evaluation is not performed on..,1: Calibration remap evaluation is performed on all.." line.long 0x4 "OVLY_CRDE,Overlay Calibration Remap Descriptor Enable register" hexmask.long.word 0x4 0.--15. 1. "CRD_EN,Calibration Remap Descriptor Enable." group.long 0x10++0xB line.long 0x0 "CRD0_W0,Calibration Remap Descriptor 0 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD0_W1,Calibration Remap Descriptor 0 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD0_W2,Calibration Remap Descriptor 0 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x20++0xB line.long 0x0 "CRD1_W0,Calibration Remap Descriptor 1 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD1_W1,Calibration Remap Descriptor 1 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD1_W2,Calibration Remap Descriptor 1 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x30++0xB line.long 0x0 "CRD2_W0,Calibration Remap Descriptor 2 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD2_W1,Calibration Remap Descriptor 2 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD2_W2,Calibration Remap Descriptor 2 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x40++0xB line.long 0x0 "CRD3_W0,Calibration Remap Descriptor 3 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD3_W1,Calibration Remap Descriptor 3 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD3_W2,Calibration Remap Descriptor 3 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x50++0xB line.long 0x0 "CRD4_W0,Calibration Remap Descriptor 4 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD4_W1,Calibration Remap Descriptor 4 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD4_W2,Calibration Remap Descriptor 4 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x60++0xB line.long 0x0 "CRD5_W0,Calibration Remap Descriptor 5 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD5_W1,Calibration Remap Descriptor 5 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD5_W2,Calibration Remap Descriptor 5 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x70++0xB line.long 0x0 "CRD6_W0,Calibration Remap Descriptor 6 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD6_W1,Calibration Remap Descriptor 6 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD6_W2,Calibration Remap Descriptor 6 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x80++0xB line.long 0x0 "CRD7_W0,Calibration Remap Descriptor 7 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD7_W1,Calibration Remap Descriptor 7 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD7_W2,Calibration Remap Descriptor 7 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x90++0xB line.long 0x0 "CRD8_W0,Calibration Remap Descriptor 8 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD8_W1,Calibration Remap Descriptor 8 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD8_W2,Calibration Remap Descriptor 8 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xA0++0xB line.long 0x0 "CRD9_W0,Calibration Remap Descriptor 9 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD9_W1,Calibration Remap Descriptor 9 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD9_W2,Calibration Remap Descriptor 9 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xB0++0xB line.long 0x0 "CRD10_W0,Calibration Remap Descriptor 10 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD10_W1,Calibration Remap Descriptor 10 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD10_W2,Calibration Remap Descriptor 10 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xC0++0xB line.long 0x0 "CRD11_W0,Calibration Remap Descriptor 11 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD11_W1,Calibration Remap Descriptor 11 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD11_W2,Calibration Remap Descriptor 11 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xD0++0xB line.long 0x0 "CRD12_W0,Calibration Remap Descriptor 12 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD12_W1,Calibration Remap Descriptor 12 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD12_W2,Calibration Remap Descriptor 12 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xE0++0xB line.long 0x0 "CRD13_W0,Calibration Remap Descriptor 13 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD13_W1,Calibration Remap Descriptor 13 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD13_W2,Calibration Remap Descriptor 13 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xF0++0xB line.long 0x0 "CRD14_W0,Calibration Remap Descriptor 14 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD14_W1,Calibration Remap Descriptor 14 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD14_W2,Calibration Remap Descriptor 14 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x100++0xB line.long 0x0 "CRD15_W0,Calibration Remap Descriptor 15 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD15_W1,Calibration Remap Descriptor 15 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD15_W2,Calibration Remap Descriptor 15 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" tree.end tree "OVLY_CTRL_5" base ad:0x71668000 group.long 0x0++0x7 line.long 0x0 "OVLY_CRCR,Overlay Calibration Remap Control Register" bitfld.long 0x0 31. "BUFFER_RDATA,Enable buffer on response data path" "0: Data from Overlay RAM available in same cycle as..,1: Data from Overlay RAM available earlier than NVM.." bitfld.long 0x0 0. "CR_EN,Calibration Remap Enable" "0: Calibration remap evaluation is not performed on..,1: Calibration remap evaluation is performed on all.." line.long 0x4 "OVLY_CRDE,Overlay Calibration Remap Descriptor Enable register" hexmask.long.word 0x4 0.--15. 1. "CRD_EN,Calibration Remap Descriptor Enable." group.long 0x10++0xB line.long 0x0 "CRD0_W0,Calibration Remap Descriptor 0 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD0_W1,Calibration Remap Descriptor 0 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD0_W2,Calibration Remap Descriptor 0 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x20++0xB line.long 0x0 "CRD1_W0,Calibration Remap Descriptor 1 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD1_W1,Calibration Remap Descriptor 1 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD1_W2,Calibration Remap Descriptor 1 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x30++0xB line.long 0x0 "CRD2_W0,Calibration Remap Descriptor 2 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD2_W1,Calibration Remap Descriptor 2 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD2_W2,Calibration Remap Descriptor 2 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x40++0xB line.long 0x0 "CRD3_W0,Calibration Remap Descriptor 3 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD3_W1,Calibration Remap Descriptor 3 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD3_W2,Calibration Remap Descriptor 3 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x50++0xB line.long 0x0 "CRD4_W0,Calibration Remap Descriptor 4 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD4_W1,Calibration Remap Descriptor 4 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD4_W2,Calibration Remap Descriptor 4 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x60++0xB line.long 0x0 "CRD5_W0,Calibration Remap Descriptor 5 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD5_W1,Calibration Remap Descriptor 5 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD5_W2,Calibration Remap Descriptor 5 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x70++0xB line.long 0x0 "CRD6_W0,Calibration Remap Descriptor 6 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD6_W1,Calibration Remap Descriptor 6 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD6_W2,Calibration Remap Descriptor 6 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x80++0xB line.long 0x0 "CRD7_W0,Calibration Remap Descriptor 7 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD7_W1,Calibration Remap Descriptor 7 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD7_W2,Calibration Remap Descriptor 7 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x90++0xB line.long 0x0 "CRD8_W0,Calibration Remap Descriptor 8 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD8_W1,Calibration Remap Descriptor 8 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD8_W2,Calibration Remap Descriptor 8 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xA0++0xB line.long 0x0 "CRD9_W0,Calibration Remap Descriptor 9 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD9_W1,Calibration Remap Descriptor 9 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD9_W2,Calibration Remap Descriptor 9 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xB0++0xB line.long 0x0 "CRD10_W0,Calibration Remap Descriptor 10 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD10_W1,Calibration Remap Descriptor 10 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD10_W2,Calibration Remap Descriptor 10 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xC0++0xB line.long 0x0 "CRD11_W0,Calibration Remap Descriptor 11 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD11_W1,Calibration Remap Descriptor 11 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD11_W2,Calibration Remap Descriptor 11 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xD0++0xB line.long 0x0 "CRD12_W0,Calibration Remap Descriptor 12 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD12_W1,Calibration Remap Descriptor 12 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD12_W2,Calibration Remap Descriptor 12 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xE0++0xB line.long 0x0 "CRD13_W0,Calibration Remap Descriptor 13 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD13_W1,Calibration Remap Descriptor 13 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD13_W2,Calibration Remap Descriptor 13 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0xF0++0xB line.long 0x0 "CRD14_W0,Calibration Remap Descriptor 14 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD14_W1,Calibration Remap Descriptor 14 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD14_W2,Calibration Remap Descriptor 14 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" group.long 0x100++0xB line.long 0x0 "CRD15_W0,Calibration Remap Descriptor 15 Word0 register" hexmask.long 0x0 0.--31. 1. "LSTART_ADDR,Logical Start Address." line.long 0x4 "CRD15_W1,Calibration Remap Descriptor 15 Word1 register" hexmask.long 0x4 0.--31. 1. "PSTART_ADDR,Calibration Remap Descriptor n Physical Start Address" line.long 0x8 "CRD15_W2,Calibration Remap Descriptor 15 Word2 register" hexmask.long.byte 0x8 0.--3. 1. "CRD_SIZE,Calibration Remap Descriptor n Size" tree.end tree.end tree "OVLY_PRAM (Overlay Platform RAM)" base ad:0x0 tree "OVLY_PRAM_0" base ad:0x71044000 group.long 0x0++0x7 line.long 0x0 "CR,Platform RAM controller Configuration Register" bitfld.long 0x0 4. "WWS_EN,Wait State Enable for writes" "0: No extra wait state for Write operations,1: One extra wait state for Write operations" bitfld.long 0x0 3. "MEMACC_WAIT,Wait State Enable for ECC for RMW operations" "0: No extra wait state for RMW operations.,1: One extra wait state for RMW operations." newline bitfld.long 0x0 2. "RWS_EN,Wait State Enable for high memory access time" "0: RAM read takes 1 cycle.,1: RAM read takes 2 cycles." bitfld.long 0x0 1. "FIXED_BURST_EN,Fixed Burst Enable" "0: Fixed burst not supported. PRAMC will signal..,1: Fixed burst is supported by PRAMC." line.long 0x4 "MEM_SCRB,Platform RAM controller Memory Scrubbing" bitfld.long 0x4 31. "SCRB_STATUS,Error Repair Status" "0: Memory Scrubbing on RAM location is complete.,1: Memory Scrubbing on RAM location is pending." hexmask.long 0x4 0.--28. 1. "SCRB_ADDR,Memory Scrubbing Address" tree.end tree "OVLY_PRAM_1" base ad:0x71644000 group.long 0x0++0x7 line.long 0x0 "CR,Platform RAM controller Configuration Register" bitfld.long 0x0 4. "WWS_EN,Wait State Enable for writes" "0: No extra wait state for Write operations,1: One extra wait state for Write operations" bitfld.long 0x0 3. "MEMACC_WAIT,Wait State Enable for ECC for RMW operations" "0: No extra wait state for RMW operations.,1: One extra wait state for RMW operations." newline bitfld.long 0x0 2. "RWS_EN,Wait State Enable for high memory access time" "0: RAM read takes 1 cycle.,1: RAM read takes 2 cycles." bitfld.long 0x0 1. "FIXED_BURST_EN,Fixed Burst Enable" "0: Fixed burst not supported. PRAMC will signal..,1: Fixed burst is supported by PRAMC." line.long 0x4 "MEM_SCRB,Platform RAM controller Memory Scrubbing" bitfld.long 0x4 31. "SCRB_STATUS,Error Repair Status" "0: Memory Scrubbing on RAM location is complete.,1: Memory Scrubbing on RAM location is pending." hexmask.long 0x4 0.--28. 1. "SCRB_ADDR,Memory Scrubbing Address" tree.end tree "OVLY_PRAM_2" base ad:0x71048000 group.long 0x0++0x7 line.long 0x0 "CR,Platform RAM controller Configuration Register" bitfld.long 0x0 4. "WWS_EN,Wait State Enable for writes" "0: No extra wait state for Write operations,1: One extra wait state for Write operations" bitfld.long 0x0 3. "MEMACC_WAIT,Wait State Enable for ECC for RMW operations" "0: No extra wait state for RMW operations.,1: One extra wait state for RMW operations." newline bitfld.long 0x0 2. "RWS_EN,Wait State Enable for high memory access time" "0: RAM read takes 1 cycle.,1: RAM read takes 2 cycles." bitfld.long 0x0 1. "FIXED_BURST_EN,Fixed Burst Enable" "0: Fixed burst not supported. PRAMC will signal..,1: Fixed burst is supported by PRAMC." line.long 0x4 "MEM_SCRB,Platform RAM controller Memory Scrubbing" bitfld.long 0x4 31. "SCRB_STATUS,Error Repair Status" "0: Memory Scrubbing on RAM location is complete.,1: Memory Scrubbing on RAM location is pending." hexmask.long 0x4 0.--28. 1. "SCRB_ADDR,Memory Scrubbing Address" tree.end tree "OVLY_PRAM_3" base ad:0x71648000 group.long 0x0++0x7 line.long 0x0 "CR,Platform RAM controller Configuration Register" bitfld.long 0x0 4. "WWS_EN,Wait State Enable for writes" "0: No extra wait state for Write operations,1: One extra wait state for Write operations" bitfld.long 0x0 3. "MEMACC_WAIT,Wait State Enable for ECC for RMW operations" "0: No extra wait state for RMW operations.,1: One extra wait state for RMW operations." newline bitfld.long 0x0 2. "RWS_EN,Wait State Enable for high memory access time" "0: RAM read takes 1 cycle.,1: RAM read takes 2 cycles." bitfld.long 0x0 1. "FIXED_BURST_EN,Fixed Burst Enable" "0: Fixed burst not supported. PRAMC will signal..,1: Fixed burst is supported by PRAMC." line.long 0x4 "MEM_SCRB,Platform RAM controller Memory Scrubbing" bitfld.long 0x4 31. "SCRB_STATUS,Error Repair Status" "0: Memory Scrubbing on RAM location is complete.,1: Memory Scrubbing on RAM location is pending." hexmask.long 0x4 0.--28. 1. "SCRB_ADDR,Memory Scrubbing Address" tree.end tree "OVLY_PRAM_4" base ad:0x7104C000 group.long 0x0++0x7 line.long 0x0 "CR,Platform RAM controller Configuration Register" bitfld.long 0x0 4. "WWS_EN,Wait State Enable for writes" "0: No extra wait state for Write operations,1: One extra wait state for Write operations" bitfld.long 0x0 3. "MEMACC_WAIT,Wait State Enable for ECC for RMW operations" "0: No extra wait state for RMW operations.,1: One extra wait state for RMW operations." newline bitfld.long 0x0 2. "RWS_EN,Wait State Enable for high memory access time" "0: RAM read takes 1 cycle.,1: RAM read takes 2 cycles." bitfld.long 0x0 1. "FIXED_BURST_EN,Fixed Burst Enable" "0: Fixed burst not supported. PRAMC will signal..,1: Fixed burst is supported by PRAMC." line.long 0x4 "MEM_SCRB,Platform RAM controller Memory Scrubbing" bitfld.long 0x4 31. "SCRB_STATUS,Error Repair Status" "0: Memory Scrubbing on RAM location is complete.,1: Memory Scrubbing on RAM location is pending." hexmask.long 0x4 0.--28. 1. "SCRB_ADDR,Memory Scrubbing Address" tree.end tree "OVLY_PRAM_5" base ad:0x7164C000 group.long 0x0++0x7 line.long 0x0 "CR,Platform RAM controller Configuration Register" bitfld.long 0x0 4. "WWS_EN,Wait State Enable for writes" "0: No extra wait state for Write operations,1: One extra wait state for Write operations" bitfld.long 0x0 3. "MEMACC_WAIT,Wait State Enable for ECC for RMW operations" "0: No extra wait state for RMW operations.,1: One extra wait state for RMW operations." newline bitfld.long 0x0 2. "RWS_EN,Wait State Enable for high memory access time" "0: RAM read takes 1 cycle.,1: RAM read takes 2 cycles." bitfld.long 0x0 1. "FIXED_BURST_EN,Fixed Burst Enable" "0: Fixed burst not supported. PRAMC will signal..,1: Fixed burst is supported by PRAMC." line.long 0x4 "MEM_SCRB,Platform RAM controller Memory Scrubbing" bitfld.long 0x4 31. "SCRB_STATUS,Error Repair Status" "0: Memory Scrubbing on RAM location is complete.,1: Memory Scrubbing on RAM location is pending." hexmask.long 0x4 0.--28. 1. "SCRB_ADDR,Memory Scrubbing Address" tree.end tree.end tree "PBRIDGE (Peripheral Bridge)" base ad:0x0 tree "PBRIDGE_0" base ad:0x70000000 group.long 0x0++0x1F line.long 0x0 "MPRA,Master Privilege Register A" bitfld.long 0x0 28.--30. "MPROT0,Access privilege level associated with bus master 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "MPROT1,Access privilege level associated with bus master 1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "MPROT2,Access privilege level associated with bus master 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "MPROT3,Access privilege level associated with bus master 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "MPROT4,Access privilege level associated with bus master 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "MPROT5,Access privilege level associated with bus master 5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "MPROT6,Access privilege level associated with bus master 6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "MPROT7,Access privilege level associated with bus master 7" "0,1,2,3,4,5,6,7" line.long 0x4 "MPRB,Master Privilege Register B" bitfld.long 0x4 28.--30. "MPROT8,Access privilege level associated with bus master 8" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "MPROT9,Access privilege level associated with bus master 9" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "MPROT10,Access privilege level associated with bus master 10" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "MPROT11,Access privilege level associated with bus master 11" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "MPROT12,Access privilege level associated with bus master 12" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "MPROT13,Access privilege level associated with bus master 13" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "MPROT14,Access privilege level associated with bus master 14" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "MPROT15,Access privilege level associated with bus master 15" "0,1,2,3,4,5,6,7" line.long 0x8 "MPRC,Master Privilege Register C" bitfld.long 0x8 28.--30. "MPROT16,Access privilege level associated with bus master 16" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "MPROT17,Access privilege level associated with bus master 17" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "MPROT18,Access privilege level associated with bus master 18" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "MPROT19,Access privilege level associated with bus master 19" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "MPROT20,Access privilege level associated with bus master 20" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8.--10. "MPROT21,Access privilege level associated with bus master 21" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "MPROT22,Access privilege level associated with bus master 22" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "MPROT23,Access privilege level associated with bus master 23" "0,1,2,3,4,5,6,7" line.long 0xC "MPRD,Master Privilege Register D" bitfld.long 0xC 28.--30. "MPROT24,Access privilege level associated with bus master 24" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "MPROT25,Access privilege level associated with bus master 25" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "MPROT26,Access privilege level associated with bus master 26" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "MPROT27,Access privilege level associated with bus master 27" "0,1,2,3,4,5,6,7" bitfld.long 0xC 12.--14. "MPROT28,Access privilege level associated with bus master 28" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8.--10. "MPROT29,Access privilege level associated with bus master 29" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4.--6. "MPROT30,Access privilege level associated with bus master 30" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "MPROT31,Access privilege level associated with bus master 31" "0,1,2,3,4,5,6,7" line.long 0x10 "MPRE,Master Privilege Register E" bitfld.long 0x10 28.--30. "MPROT32,Access privilege level associated with bus master 32" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "MPROT33,Access privilege level associated with bus master 33" "0,1,2,3,4,5,6,7" bitfld.long 0x10 20.--22. "MPROT34,Access privilege level associated with bus master 34" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "MPROT35,Access privilege level associated with bus master 35" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "MPROT36,Access privilege level associated with bus master 36" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8.--10. "MPROT37,Access privilege level associated with bus master 37" "0,1,2,3,4,5,6,7" bitfld.long 0x10 4.--6. "MPROT38,Access privilege level associated with bus master 38" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "MPROT39,Access privilege level associated with bus master 39" "0,1,2,3,4,5,6,7" line.long 0x14 "MPRF,Master Privilege Register F" bitfld.long 0x14 28.--30. "MPROT40,Access privilege level associated with bus master 40" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "MPROT41,Access privilege level associated with bus master 41" "0,1,2,3,4,5,6,7" bitfld.long 0x14 20.--22. "MPROT42,Access privilege level associated with bus master 42" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "MPROT43,Access privilege level associated with bus master 43" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "MPROT44,Access privilege level associated with bus master 44" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8.--10. "MPROT45,Access privilege level associated with bus master 45" "0,1,2,3,4,5,6,7" bitfld.long 0x14 4.--6. "MPROT46,Access privilege level associated with bus master 46" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "MPROT47,Access privilege level associated with bus master 47" "0,1,2,3,4,5,6,7" line.long 0x18 "MPRG,Master Privilege Register G" bitfld.long 0x18 28.--30. "MPROT48,Access privilege level associated with bus master 48" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "MPROT49,Access privilege level associated with bus master 49" "0,1,2,3,4,5,6,7" bitfld.long 0x18 20.--22. "MPROT50,Access privilege level associated with bus master 50" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "MPROT51,Access privilege level associated with bus master 51" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "MPROT52,Access privilege level associated with bus master 52" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8.--10. "MPROT53,Access privilege level associated with bus master 53" "0,1,2,3,4,5,6,7" bitfld.long 0x18 4.--6. "MPROT54,Access privilege level associated with bus master 54" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "MPROT55,Access privilege level associated with bus master 55" "0,1,2,3,4,5,6,7" line.long 0x1C "MPRH,Master Privilege Register H" bitfld.long 0x1C 28.--30. "MPROT56,Access privilege level associated with bus master 56" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--26. "MPROT57,Access privilege level associated with bus master 57" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--22. "MPROT58,Access privilege level associated with bus master 58" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 16.--18. "MPROT59,Access privilege level associated with bus master 59" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 12.--14. "MPROT60,Access privilege level associated with bus master 60" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8.--10. "MPROT61,Access privilege level associated with bus master 61" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 4.--6. "MPROT62,Access privilege level associated with bus master 62" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "MPROT63,Access privilege level associated with bus master 63" "0,1,2,3,4,5,6,7" group.long 0x100++0x3 line.long 0x0 "PACRA,Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "PACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" group.long 0x160++0x3 line.long 0x0 "OPACRI,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x168++0x1F line.long 0x0 "OPACRK,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x4 "OPACRL,Off-Platform Peripheral Access Control Registers" bitfld.long 0x4 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x8 "OPACRM,Off-Platform Peripheral Access Control Registers" bitfld.long 0x8 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0xC "OPACRN,Off-Platform Peripheral Access Control Registers" bitfld.long 0xC 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0xC 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x10 "OPACRO,Off-Platform Peripheral Access Control Registers" bitfld.long 0x10 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x10 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x10 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x14 "OPACRP,Off-Platform Peripheral Access Control Registers" bitfld.long 0x14 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x14 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x14 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x18 "OPACRQ,Off-Platform Peripheral Access Control Registers" bitfld.long 0x18 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x18 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x18 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x1C "OPACRR,Off-Platform Peripheral Access Control Registers" bitfld.long 0x1C 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x18C++0x7 line.long 0x0 "OPACRT,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x4 "OPACRU,Off-Platform Peripheral Access Control Registers" bitfld.long 0x4 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x198++0x3 line.long 0x0 "OPACRW,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x1A8++0x13 line.long 0x0 "OPACRAA,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x4 "OPACRAB,Off-Platform Peripheral Access Control Registers" bitfld.long 0x4 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x8 "OPACRAC,Off-Platform Peripheral Access Control Registers" bitfld.long 0x8 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0xC "OPACRAD,Off-Platform Peripheral Access Control Registers" bitfld.long 0xC 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0xC 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x10 "OPACRAE,Off-Platform Peripheral Access Control Registers" bitfld.long 0x10 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x10 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x10 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x1E0++0x3 line.long 0x0 "VMIDA,Peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "VMIDA,VMID associated with module a" group.long 0x280++0x7 line.long 0x0 "OVMIDQ,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDR,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x290++0xB line.long 0x0 "OVMIDU,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDV,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x8 "OVMIDW,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x8 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x8 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x8 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x8 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x2A4++0x3 line.long 0x0 "OVMIDZ,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x2AC++0x7 line.long 0x0 "OVMIDAB,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDAC,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x2B8++0x17 line.long 0x0 "OVMIDAE,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDAF,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x8 "OVMIDAG,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x8 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x8 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x8 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x8 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0xC "OVMIDAH,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0xC 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0xC 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0xC 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0xC 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x10 "OVMIDAI,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x10 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x10 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x10 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x10 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x14 "OVMIDAJ,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x14 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x14 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x14 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x14 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x2DC++0x7 line.long 0x0 "OVMIDAN,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDAO,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x2F0++0x7 line.long 0x0 "OVMIDAS,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDAT,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x310++0x23 line.long 0x0 "OVMIDBA,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDBB,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x8 "OVMIDBC,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x8 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x8 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x8 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x8 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0xC "OVMIDBD,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0xC 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0xC 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0xC 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0xC 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x10 "OVMIDBE,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x10 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x10 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x10 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x10 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x14 "OVMIDBF,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x14 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x14 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x14 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x14 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x18 "OVMIDBG,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x18 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x18 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x18 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x18 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x1C "OVMIDBH,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x1C 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x1C 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x1C 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x1C 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x20 "OVMIDBI,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x20 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x20 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x20 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x20 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x360++0xB line.long 0x0 "VIRTFAULT0,Virtualisation Fault 0 register" bitfld.long 0x0 23. "SLOTID_TYPE,Slot ID associated with the visualization fault is an onpf or offpf slot." "0: indicates offpf slot,1: indicates onpf slot" hexmask.long.byte 0x0 15.--22. 1. "SLOTID,Slot ID associated with the virtualisation fault" hexmask.long.byte 0x0 9.--14. 1. "MASTERID,Master ID associated with the virtualisation fault" hexmask.long.byte 0x0 1.--8. 1. "VMID,VMID associated with the virtualisation fault" bitfld.long 0x0 0. "ERRPEND,virtualisation Error is pending" "0,1" line.long 0x4 "VIRTFAULT1,Virtualisation Fault 1 register" bitfld.long 0x4 8.--10. "HBURST,hburst attribute associated the transaction causing virtualisation error" "0,1,2,3,4,5,6,7" bitfld.long 0x4 5.--7. "HSIZE,hsize attribute associated the transaction causing virtualisation error" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3.--4. "HTRANS,htrans attribute associated the transaction causing virtualisation error" "0,1,2,3" bitfld.long 0x4 1.--2. "HPROT,hprot attribute associated the transaction causing virtualisation error" "0,1,2,3" bitfld.long 0x4 0. "HWRITE,hwrite attribute associated the transaction causing virtualisation error" "0,1" line.long 0x8 "EL2_DISABLE,Virtualisation Fault 1 register" bitfld.long 0x8 0. "EL2_DISABLE,This bit controls virtualisation checks in PBRIDGE." "0: All virtualisation checks in PBRIDGE are enabled,1: All virtualisation checks in PBRIDGE are disabled" tree.end tree "PBRIDGE_1" base ad:0x70600000 group.long 0x0++0x1F line.long 0x0 "MPRA,Master Privilege Register A" bitfld.long 0x0 28.--30. "MPROT0,Access privilege level associated with bus master 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "MPROT1,Access privilege level associated with bus master 1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "MPROT2,Access privilege level associated with bus master 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "MPROT3,Access privilege level associated with bus master 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "MPROT4,Access privilege level associated with bus master 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "MPROT5,Access privilege level associated with bus master 5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "MPROT6,Access privilege level associated with bus master 6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "MPROT7,Access privilege level associated with bus master 7" "0,1,2,3,4,5,6,7" line.long 0x4 "MPRB,Master Privilege Register B" bitfld.long 0x4 28.--30. "MPROT8,Access privilege level associated with bus master 8" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "MPROT9,Access privilege level associated with bus master 9" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "MPROT10,Access privilege level associated with bus master 10" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "MPROT11,Access privilege level associated with bus master 11" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "MPROT12,Access privilege level associated with bus master 12" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "MPROT13,Access privilege level associated with bus master 13" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "MPROT14,Access privilege level associated with bus master 14" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "MPROT15,Access privilege level associated with bus master 15" "0,1,2,3,4,5,6,7" line.long 0x8 "MPRC,Master Privilege Register C" bitfld.long 0x8 28.--30. "MPROT16,Access privilege level associated with bus master 16" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "MPROT17,Access privilege level associated with bus master 17" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "MPROT18,Access privilege level associated with bus master 18" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "MPROT19,Access privilege level associated with bus master 19" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "MPROT20,Access privilege level associated with bus master 20" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8.--10. "MPROT21,Access privilege level associated with bus master 21" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "MPROT22,Access privilege level associated with bus master 22" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "MPROT23,Access privilege level associated with bus master 23" "0,1,2,3,4,5,6,7" line.long 0xC "MPRD,Master Privilege Register D" bitfld.long 0xC 28.--30. "MPROT24,Access privilege level associated with bus master 24" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "MPROT25,Access privilege level associated with bus master 25" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "MPROT26,Access privilege level associated with bus master 26" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "MPROT27,Access privilege level associated with bus master 27" "0,1,2,3,4,5,6,7" bitfld.long 0xC 12.--14. "MPROT28,Access privilege level associated with bus master 28" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8.--10. "MPROT29,Access privilege level associated with bus master 29" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4.--6. "MPROT30,Access privilege level associated with bus master 30" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "MPROT31,Access privilege level associated with bus master 31" "0,1,2,3,4,5,6,7" line.long 0x10 "MPRE,Master Privilege Register E" bitfld.long 0x10 28.--30. "MPROT32,Access privilege level associated with bus master 32" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "MPROT33,Access privilege level associated with bus master 33" "0,1,2,3,4,5,6,7" bitfld.long 0x10 20.--22. "MPROT34,Access privilege level associated with bus master 34" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "MPROT35,Access privilege level associated with bus master 35" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "MPROT36,Access privilege level associated with bus master 36" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8.--10. "MPROT37,Access privilege level associated with bus master 37" "0,1,2,3,4,5,6,7" bitfld.long 0x10 4.--6. "MPROT38,Access privilege level associated with bus master 38" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "MPROT39,Access privilege level associated with bus master 39" "0,1,2,3,4,5,6,7" line.long 0x14 "MPRF,Master Privilege Register F" bitfld.long 0x14 28.--30. "MPROT40,Access privilege level associated with bus master 40" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "MPROT41,Access privilege level associated with bus master 41" "0,1,2,3,4,5,6,7" bitfld.long 0x14 20.--22. "MPROT42,Access privilege level associated with bus master 42" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "MPROT43,Access privilege level associated with bus master 43" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "MPROT44,Access privilege level associated with bus master 44" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8.--10. "MPROT45,Access privilege level associated with bus master 45" "0,1,2,3,4,5,6,7" bitfld.long 0x14 4.--6. "MPROT46,Access privilege level associated with bus master 46" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "MPROT47,Access privilege level associated with bus master 47" "0,1,2,3,4,5,6,7" line.long 0x18 "MPRG,Master Privilege Register G" bitfld.long 0x18 28.--30. "MPROT48,Access privilege level associated with bus master 48" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "MPROT49,Access privilege level associated with bus master 49" "0,1,2,3,4,5,6,7" bitfld.long 0x18 20.--22. "MPROT50,Access privilege level associated with bus master 50" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "MPROT51,Access privilege level associated with bus master 51" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "MPROT52,Access privilege level associated with bus master 52" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8.--10. "MPROT53,Access privilege level associated with bus master 53" "0,1,2,3,4,5,6,7" bitfld.long 0x18 4.--6. "MPROT54,Access privilege level associated with bus master 54" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "MPROT55,Access privilege level associated with bus master 55" "0,1,2,3,4,5,6,7" line.long 0x1C "MPRH,Master Privilege Register H" bitfld.long 0x1C 28.--30. "MPROT56,Access privilege level associated with bus master 56" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--26. "MPROT57,Access privilege level associated with bus master 57" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--22. "MPROT58,Access privilege level associated with bus master 58" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 16.--18. "MPROT59,Access privilege level associated with bus master 59" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 12.--14. "MPROT60,Access privilege level associated with bus master 60" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8.--10. "MPROT61,Access privilege level associated with bus master 61" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 4.--6. "MPROT62,Access privilege level associated with bus master 62" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "MPROT63,Access privilege level associated with bus master 63" "0,1,2,3,4,5,6,7" group.long 0x100++0x3 line.long 0x0 "PACRA,Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "PACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" group.long 0x140++0x1F line.long 0x0 "OPACRA,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x4 "OPACRB,Off-Platform Peripheral Access Control Registers" bitfld.long 0x4 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x8 "OPACRC,Off-Platform Peripheral Access Control Registers" bitfld.long 0x8 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0xC "OPACRD,Off-Platform Peripheral Access Control Registers" bitfld.long 0xC 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0xC 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x10 "OPACRE,Off-Platform Peripheral Access Control Registers" bitfld.long 0x10 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x10 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x10 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x14 "OPACRF,Off-Platform Peripheral Access Control Registers" bitfld.long 0x14 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x14 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x14 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x18 "OPACRG,Off-Platform Peripheral Access Control Registers" bitfld.long 0x18 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x18 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x18 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x1C "OPACRH,Off-Platform Peripheral Access Control Registers" bitfld.long 0x1C 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x168++0x7 line.long 0x0 "OPACRK,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x4 "OPACRL,Off-Platform Peripheral Access Control Registers" bitfld.long 0x4 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x178++0xF line.long 0x0 "OPACRO,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x4 "OPACRP,Off-Platform Peripheral Access Control Registers" bitfld.long 0x4 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x8 "OPACRQ,Off-Platform Peripheral Access Control Registers" bitfld.long 0x8 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0xC "OPACRR,Off-Platform Peripheral Access Control Registers" bitfld.long 0xC 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0xC 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x18C++0x7 line.long 0x0 "OPACRT,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x4 "OPACRU,Off-Platform Peripheral Access Control Registers" bitfld.long 0x4 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x198++0x3 line.long 0x0 "OPACRW,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x1A8++0x7 line.long 0x0 "OPACRAA,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x4 "OPACRAB,Off-Platform Peripheral Access Control Registers" bitfld.long 0x4 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x1B4++0xB line.long 0x0 "OPACRAD,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x4 "OPACRAE,Off-Platform Peripheral Access Control Registers" bitfld.long 0x4 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x8 "OPACRAF,Off-Platform Peripheral Access Control Registers" bitfld.long 0x8 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x1E0++0x3 line.long 0x0 "VMIDA,Peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "VMIDA,VMID associated with module a" group.long 0x240++0x3F line.long 0x0 "OVMIDA,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDB,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x8 "OVMIDC,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x8 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x8 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x8 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x8 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0xC "OVMIDD,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0xC 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0xC 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0xC 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0xC 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x10 "OVMIDE,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x10 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x10 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x10 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x10 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x14 "OVMIDF,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x14 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x14 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x14 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x14 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x18 "OVMIDG,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x18 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x18 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x18 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x18 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x1C "OVMIDH,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x1C 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x1C 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x1C 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x1C 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x20 "OVMIDI,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x20 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x20 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x20 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x20 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x24 "OVMIDJ,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x24 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x24 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x24 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x24 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x28 "OVMIDK,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x28 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x28 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x28 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x28 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x2C "OVMIDL,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x2C 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x2C 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x2C 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x2C 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x30 "OVMIDM,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x30 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x30 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x30 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x30 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x34 "OVMIDN,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x34 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x34 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x34 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x34 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x38 "OVMIDO,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x38 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x38 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x38 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x38 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x3C "OVMIDP,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x3C 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x3C 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x3C 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x3C 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x294++0x7 line.long 0x0 "OVMIDV,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDW,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x2B0++0x3 line.long 0x0 "OVMIDAC,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x2B8++0x17 line.long 0x0 "OVMIDAE,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDAF,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x8 "OVMIDAG,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x8 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x8 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x8 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x8 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0xC "OVMIDAH,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0xC 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0xC 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0xC 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0xC 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x10 "OVMIDAI,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x10 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x10 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x10 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x10 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x14 "OVMIDAJ,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x14 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x14 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x14 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x14 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x2DC++0x7 line.long 0x0 "OVMIDAN,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDAO,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x2F0++0x7 line.long 0x0 "OVMIDAS,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDAT,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x310++0xF line.long 0x0 "OVMIDBA,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDBB,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x8 "OVMIDBC,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x8 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x8 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x8 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x8 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0xC "OVMIDBD,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0xC 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0xC 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0xC 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0xC 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x32C++0x7 line.long 0x0 "OVMIDBH,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDBI,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x338++0x7 line.long 0x0 "OVMIDBK,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDBL,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x360++0xB line.long 0x0 "VIRTFAULT0,Virtualisation Fault 0 register" bitfld.long 0x0 23. "SLOTID_TYPE,Slot ID associated with the visualization fault is an onpf or offpf slot." "0: indicates offpf slot,1: indicates onpf slot" hexmask.long.byte 0x0 15.--22. 1. "SLOTID,Slot ID associated with the virtualisation fault" hexmask.long.byte 0x0 9.--14. 1. "MASTERID,Master ID associated with the virtualisation fault" hexmask.long.byte 0x0 1.--8. 1. "VMID,VMID associated with the virtualisation fault" bitfld.long 0x0 0. "ERRPEND,virtualisation Error is pending" "0,1" line.long 0x4 "VIRTFAULT1,Virtualisation Fault 1 register" bitfld.long 0x4 8.--10. "HBURST,hburst attribute associated the transaction causing virtualisation error" "0,1,2,3,4,5,6,7" bitfld.long 0x4 5.--7. "HSIZE,hsize attribute associated the transaction causing virtualisation error" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3.--4. "HTRANS,htrans attribute associated the transaction causing virtualisation error" "0,1,2,3" bitfld.long 0x4 1.--2. "HPROT,hprot attribute associated the transaction causing virtualisation error" "0,1,2,3" bitfld.long 0x4 0. "HWRITE,hwrite attribute associated the transaction causing virtualisation error" "0,1" line.long 0x8 "EL2_DISABLE,Virtualisation Fault 1 register" bitfld.long 0x8 0. "EL2_DISABLE,This bit controls virtualisation checks in PBRIDGE." "0: All virtualisation checks in PBRIDGE are enabled,1: All virtualisation checks in PBRIDGE are disabled" tree.end tree "PBRIDGE_2" base ad:0x70C00000 group.long 0x0++0x1F line.long 0x0 "MPRA,Master Privilege Register A" bitfld.long 0x0 28.--30. "MPROT0,Access privilege level associated with bus master 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "MPROT1,Access privilege level associated with bus master 1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "MPROT2,Access privilege level associated with bus master 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "MPROT3,Access privilege level associated with bus master 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "MPROT4,Access privilege level associated with bus master 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "MPROT5,Access privilege level associated with bus master 5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "MPROT6,Access privilege level associated with bus master 6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "MPROT7,Access privilege level associated with bus master 7" "0,1,2,3,4,5,6,7" line.long 0x4 "MPRB,Master Privilege Register B" bitfld.long 0x4 28.--30. "MPROT8,Access privilege level associated with bus master 8" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "MPROT9,Access privilege level associated with bus master 9" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "MPROT10,Access privilege level associated with bus master 10" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "MPROT11,Access privilege level associated with bus master 11" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "MPROT12,Access privilege level associated with bus master 12" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "MPROT13,Access privilege level associated with bus master 13" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "MPROT14,Access privilege level associated with bus master 14" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "MPROT15,Access privilege level associated with bus master 15" "0,1,2,3,4,5,6,7" line.long 0x8 "MPRC,Master Privilege Register C" bitfld.long 0x8 28.--30. "MPROT16,Access privilege level associated with bus master 16" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "MPROT17,Access privilege level associated with bus master 17" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "MPROT18,Access privilege level associated with bus master 18" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "MPROT19,Access privilege level associated with bus master 19" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "MPROT20,Access privilege level associated with bus master 20" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8.--10. "MPROT21,Access privilege level associated with bus master 21" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "MPROT22,Access privilege level associated with bus master 22" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "MPROT23,Access privilege level associated with bus master 23" "0,1,2,3,4,5,6,7" line.long 0xC "MPRD,Master Privilege Register D" bitfld.long 0xC 28.--30. "MPROT24,Access privilege level associated with bus master 24" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "MPROT25,Access privilege level associated with bus master 25" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "MPROT26,Access privilege level associated with bus master 26" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "MPROT27,Access privilege level associated with bus master 27" "0,1,2,3,4,5,6,7" bitfld.long 0xC 12.--14. "MPROT28,Access privilege level associated with bus master 28" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8.--10. "MPROT29,Access privilege level associated with bus master 29" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4.--6. "MPROT30,Access privilege level associated with bus master 30" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "MPROT31,Access privilege level associated with bus master 31" "0,1,2,3,4,5,6,7" line.long 0x10 "MPRE,Master Privilege Register E" bitfld.long 0x10 28.--30. "MPROT32,Access privilege level associated with bus master 32" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "MPROT33,Access privilege level associated with bus master 33" "0,1,2,3,4,5,6,7" bitfld.long 0x10 20.--22. "MPROT34,Access privilege level associated with bus master 34" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "MPROT35,Access privilege level associated with bus master 35" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "MPROT36,Access privilege level associated with bus master 36" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8.--10. "MPROT37,Access privilege level associated with bus master 37" "0,1,2,3,4,5,6,7" bitfld.long 0x10 4.--6. "MPROT38,Access privilege level associated with bus master 38" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "MPROT39,Access privilege level associated with bus master 39" "0,1,2,3,4,5,6,7" line.long 0x14 "MPRF,Master Privilege Register F" bitfld.long 0x14 28.--30. "MPROT40,Access privilege level associated with bus master 40" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "MPROT41,Access privilege level associated with bus master 41" "0,1,2,3,4,5,6,7" bitfld.long 0x14 20.--22. "MPROT42,Access privilege level associated with bus master 42" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "MPROT43,Access privilege level associated with bus master 43" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "MPROT44,Access privilege level associated with bus master 44" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8.--10. "MPROT45,Access privilege level associated with bus master 45" "0,1,2,3,4,5,6,7" bitfld.long 0x14 4.--6. "MPROT46,Access privilege level associated with bus master 46" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "MPROT47,Access privilege level associated with bus master 47" "0,1,2,3,4,5,6,7" line.long 0x18 "MPRG,Master Privilege Register G" bitfld.long 0x18 28.--30. "MPROT48,Access privilege level associated with bus master 48" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "MPROT49,Access privilege level associated with bus master 49" "0,1,2,3,4,5,6,7" bitfld.long 0x18 20.--22. "MPROT50,Access privilege level associated with bus master 50" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "MPROT51,Access privilege level associated with bus master 51" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "MPROT52,Access privilege level associated with bus master 52" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8.--10. "MPROT53,Access privilege level associated with bus master 53" "0,1,2,3,4,5,6,7" bitfld.long 0x18 4.--6. "MPROT54,Access privilege level associated with bus master 54" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "MPROT55,Access privilege level associated with bus master 55" "0,1,2,3,4,5,6,7" line.long 0x1C "MPRH,Master Privilege Register H" bitfld.long 0x1C 28.--30. "MPROT56,Access privilege level associated with bus master 56" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--26. "MPROT57,Access privilege level associated with bus master 57" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--22. "MPROT58,Access privilege level associated with bus master 58" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 16.--18. "MPROT59,Access privilege level associated with bus master 59" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 12.--14. "MPROT60,Access privilege level associated with bus master 60" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8.--10. "MPROT61,Access privilege level associated with bus master 61" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 4.--6. "MPROT62,Access privilege level associated with bus master 62" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "MPROT63,Access privilege level associated with bus master 63" "0,1,2,3,4,5,6,7" group.long 0x100++0x3 line.long 0x0 "PACRA,Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "PACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" group.long 0x140++0x1B line.long 0x0 "OPACRA,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x4 "OPACRB,Off-Platform Peripheral Access Control Registers" bitfld.long 0x4 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x8 "OPACRC,Off-Platform Peripheral Access Control Registers" bitfld.long 0x8 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0xC "OPACRD,Off-Platform Peripheral Access Control Registers" bitfld.long 0xC 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0xC 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x10 "OPACRE,Off-Platform Peripheral Access Control Registers" bitfld.long 0x10 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x10 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x10 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x14 "OPACRF,Off-Platform Peripheral Access Control Registers" bitfld.long 0x14 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x14 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x14 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x18 "OPACRG,Off-Platform Peripheral Access Control Registers" bitfld.long 0x18 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x18 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x18 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x160++0x17 line.long 0x0 "OPACRI,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x4 "OPACRJ,Off-Platform Peripheral Access Control Registers" bitfld.long 0x4 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x8 "OPACRK,Off-Platform Peripheral Access Control Registers" bitfld.long 0x8 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0xC "OPACRL,Off-Platform Peripheral Access Control Registers" bitfld.long 0xC 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0xC 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x10 "OPACRM,Off-Platform Peripheral Access Control Registers" bitfld.long 0x10 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x10 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x10 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x14 "OPACRN,Off-Platform Peripheral Access Control Registers" bitfld.long 0x14 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x14 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x14 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x17C++0xB line.long 0x0 "OPACRP,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x4 "OPACRQ,Off-Platform Peripheral Access Control Registers" bitfld.long 0x4 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x8 "OPACRR,Off-Platform Peripheral Access Control Registers" bitfld.long 0x8 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x194++0x3 line.long 0x0 "OPACRV,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x19C++0x1B line.long 0x0 "OPACRX,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x4 "OPACRY,Off-Platform Peripheral Access Control Registers" bitfld.long 0x4 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x8 "OPACRZ,Off-Platform Peripheral Access Control Registers" bitfld.long 0x8 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0xC "OPACRAA,Off-Platform Peripheral Access Control Registers" bitfld.long 0xC 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0xC 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x10 "OPACRAB,Off-Platform Peripheral Access Control Registers" bitfld.long 0x10 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x10 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x10 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x14 "OPACRAC,Off-Platform Peripheral Access Control Registers" bitfld.long 0x14 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x14 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x14 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x18 "OPACRAD,Off-Platform Peripheral Access Control Registers" bitfld.long 0x18 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x18 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x18 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x1BC++0x3 line.long 0x0 "OPACRAF,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x1E0++0x3 line.long 0x0 "VMIDA,Peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "VMIDA,VMID associated with module a" group.long 0x240++0x7 line.long 0x0 "OVMIDA,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDB,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x24C++0x1F line.long 0x0 "OVMIDD,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDE,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x8 "OVMIDF,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x8 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x8 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x8 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x8 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0xC "OVMIDG,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0xC 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0xC 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0xC 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0xC 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x10 "OVMIDH,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x10 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x10 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x10 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x10 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x14 "OVMIDI,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x14 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x14 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x14 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x14 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x18 "OVMIDJ,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x18 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x18 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x18 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x18 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x1C "OVMIDK,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x1C 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x1C 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x1C 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x1C 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x270++0x3 line.long 0x0 "OVMIDM,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x284++0xB line.long 0x0 "OVMIDR,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDS,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x8 "OVMIDT,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x8 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x8 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x8 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x8 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x294++0x13 line.long 0x0 "OVMIDV,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDW,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x8 "OVMIDX,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x8 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x8 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x8 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x8 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0xC "OVMIDY,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0xC 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0xC 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0xC 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0xC 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x10 "OVMIDZ,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x10 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x10 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x10 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x10 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x2AC++0x3 line.long 0x0 "OVMIDAB,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x2BC++0xB line.long 0x0 "OVMIDAF,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDAG,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x8 "OVMIDAH,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x8 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x8 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x8 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x8 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x2CC++0x3 line.long 0x0 "OVMIDAJ,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x2EC++0x3 line.long 0x0 "OVMIDAR,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x2FC++0x17 line.long 0x0 "OVMIDAV,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDAW,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x8 "OVMIDAX,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x8 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x8 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x8 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x8 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0xC "OVMIDAY,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0xC 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0xC 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0xC 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0xC 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x10 "OVMIDAZ,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x10 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x10 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x10 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x10 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x14 "OVMIDBA,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x14 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x14 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x14 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x14 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x318++0xB line.long 0x0 "OVMIDBC,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDBD,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x8 "OVMIDBE,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x8 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x8 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x8 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x8 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x328++0x3 line.long 0x0 "OVMIDBG,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x338++0x3 line.long 0x0 "OVMIDBK,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x360++0xB line.long 0x0 "VIRTFAULT0,Virtualisation Fault 0 register" bitfld.long 0x0 23. "SLOTID_TYPE,Slot ID associated with the visualization fault is an onpf or offpf slot." "0: indicates offpf slot,1: indicates onpf slot" hexmask.long.byte 0x0 15.--22. 1. "SLOTID,Slot ID associated with the virtualisation fault" hexmask.long.byte 0x0 9.--14. 1. "MASTERID,Master ID associated with the virtualisation fault" hexmask.long.byte 0x0 1.--8. 1. "VMID,VMID associated with the virtualisation fault" bitfld.long 0x0 0. "ERRPEND,virtualisation Error is pending" "0,1" line.long 0x4 "VIRTFAULT1,Virtualisation Fault 1 register" bitfld.long 0x4 8.--10. "HBURST,hburst attribute associated the transaction causing virtualisation error" "0,1,2,3,4,5,6,7" bitfld.long 0x4 5.--7. "HSIZE,hsize attribute associated the transaction causing virtualisation error" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3.--4. "HTRANS,htrans attribute associated the transaction causing virtualisation error" "0,1,2,3" bitfld.long 0x4 1.--2. "HPROT,hprot attribute associated the transaction causing virtualisation error" "0,1,2,3" bitfld.long 0x4 0. "HWRITE,hwrite attribute associated the transaction causing virtualisation error" "0,1" line.long 0x8 "EL2_DISABLE,Virtualisation Fault 1 register" bitfld.long 0x8 0. "EL2_DISABLE,This bit controls virtualisation checks in PBRIDGE." "0: All virtualisation checks in PBRIDGE are enabled,1: All virtualisation checks in PBRIDGE are disabled" tree.end tree "PBRIDGE_3" base ad:0x71200000 group.long 0x0++0x1F line.long 0x0 "MPRA,Master Privilege Register A" bitfld.long 0x0 28.--30. "MPROT0,Access privilege level associated with bus master 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "MPROT1,Access privilege level associated with bus master 1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "MPROT2,Access privilege level associated with bus master 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "MPROT3,Access privilege level associated with bus master 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "MPROT4,Access privilege level associated with bus master 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "MPROT5,Access privilege level associated with bus master 5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "MPROT6,Access privilege level associated with bus master 6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "MPROT7,Access privilege level associated with bus master 7" "0,1,2,3,4,5,6,7" line.long 0x4 "MPRB,Master Privilege Register B" bitfld.long 0x4 28.--30. "MPROT8,Access privilege level associated with bus master 8" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "MPROT9,Access privilege level associated with bus master 9" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "MPROT10,Access privilege level associated with bus master 10" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "MPROT11,Access privilege level associated with bus master 11" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "MPROT12,Access privilege level associated with bus master 12" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "MPROT13,Access privilege level associated with bus master 13" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "MPROT14,Access privilege level associated with bus master 14" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "MPROT15,Access privilege level associated with bus master 15" "0,1,2,3,4,5,6,7" line.long 0x8 "MPRC,Master Privilege Register C" bitfld.long 0x8 28.--30. "MPROT16,Access privilege level associated with bus master 16" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "MPROT17,Access privilege level associated with bus master 17" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "MPROT18,Access privilege level associated with bus master 18" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "MPROT19,Access privilege level associated with bus master 19" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "MPROT20,Access privilege level associated with bus master 20" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8.--10. "MPROT21,Access privilege level associated with bus master 21" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "MPROT22,Access privilege level associated with bus master 22" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "MPROT23,Access privilege level associated with bus master 23" "0,1,2,3,4,5,6,7" line.long 0xC "MPRD,Master Privilege Register D" bitfld.long 0xC 28.--30. "MPROT24,Access privilege level associated with bus master 24" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "MPROT25,Access privilege level associated with bus master 25" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "MPROT26,Access privilege level associated with bus master 26" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "MPROT27,Access privilege level associated with bus master 27" "0,1,2,3,4,5,6,7" bitfld.long 0xC 12.--14. "MPROT28,Access privilege level associated with bus master 28" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8.--10. "MPROT29,Access privilege level associated with bus master 29" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4.--6. "MPROT30,Access privilege level associated with bus master 30" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "MPROT31,Access privilege level associated with bus master 31" "0,1,2,3,4,5,6,7" line.long 0x10 "MPRE,Master Privilege Register E" bitfld.long 0x10 28.--30. "MPROT32,Access privilege level associated with bus master 32" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "MPROT33,Access privilege level associated with bus master 33" "0,1,2,3,4,5,6,7" bitfld.long 0x10 20.--22. "MPROT34,Access privilege level associated with bus master 34" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "MPROT35,Access privilege level associated with bus master 35" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "MPROT36,Access privilege level associated with bus master 36" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8.--10. "MPROT37,Access privilege level associated with bus master 37" "0,1,2,3,4,5,6,7" bitfld.long 0x10 4.--6. "MPROT38,Access privilege level associated with bus master 38" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "MPROT39,Access privilege level associated with bus master 39" "0,1,2,3,4,5,6,7" line.long 0x14 "MPRF,Master Privilege Register F" bitfld.long 0x14 28.--30. "MPROT40,Access privilege level associated with bus master 40" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "MPROT41,Access privilege level associated with bus master 41" "0,1,2,3,4,5,6,7" bitfld.long 0x14 20.--22. "MPROT42,Access privilege level associated with bus master 42" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "MPROT43,Access privilege level associated with bus master 43" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "MPROT44,Access privilege level associated with bus master 44" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8.--10. "MPROT45,Access privilege level associated with bus master 45" "0,1,2,3,4,5,6,7" bitfld.long 0x14 4.--6. "MPROT46,Access privilege level associated with bus master 46" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "MPROT47,Access privilege level associated with bus master 47" "0,1,2,3,4,5,6,7" line.long 0x18 "MPRG,Master Privilege Register G" bitfld.long 0x18 28.--30. "MPROT48,Access privilege level associated with bus master 48" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "MPROT49,Access privilege level associated with bus master 49" "0,1,2,3,4,5,6,7" bitfld.long 0x18 20.--22. "MPROT50,Access privilege level associated with bus master 50" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "MPROT51,Access privilege level associated with bus master 51" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "MPROT52,Access privilege level associated with bus master 52" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8.--10. "MPROT53,Access privilege level associated with bus master 53" "0,1,2,3,4,5,6,7" bitfld.long 0x18 4.--6. "MPROT54,Access privilege level associated with bus master 54" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "MPROT55,Access privilege level associated with bus master 55" "0,1,2,3,4,5,6,7" line.long 0x1C "MPRH,Master Privilege Register H" bitfld.long 0x1C 28.--30. "MPROT56,Access privilege level associated with bus master 56" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--26. "MPROT57,Access privilege level associated with bus master 57" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--22. "MPROT58,Access privilege level associated with bus master 58" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 16.--18. "MPROT59,Access privilege level associated with bus master 59" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 12.--14. "MPROT60,Access privilege level associated with bus master 60" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8.--10. "MPROT61,Access privilege level associated with bus master 61" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 4.--6. "MPROT62,Access privilege level associated with bus master 62" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "MPROT63,Access privilege level associated with bus master 63" "0,1,2,3,4,5,6,7" group.long 0x100++0x3 line.long 0x0 "PACRA,Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "PACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" group.long 0x140++0x1B line.long 0x0 "OPACRA,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x4 "OPACRB,Off-Platform Peripheral Access Control Registers" bitfld.long 0x4 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x8 "OPACRC,Off-Platform Peripheral Access Control Registers" bitfld.long 0x8 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0xC "OPACRD,Off-Platform Peripheral Access Control Registers" bitfld.long 0xC 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0xC 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x10 "OPACRE,Off-Platform Peripheral Access Control Registers" bitfld.long 0x10 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x10 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x10 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x14 "OPACRF,Off-Platform Peripheral Access Control Registers" bitfld.long 0x14 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x14 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x14 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x18 "OPACRG,Off-Platform Peripheral Access Control Registers" bitfld.long 0x18 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x18 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x18 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x164++0x13 line.long 0x0 "OPACRJ,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x4 "OPACRK,Off-Platform Peripheral Access Control Registers" bitfld.long 0x4 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x8 "OPACRL,Off-Platform Peripheral Access Control Registers" bitfld.long 0x8 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0xC "OPACRM,Off-Platform Peripheral Access Control Registers" bitfld.long 0xC 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0xC 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x10 "OPACRN,Off-Platform Peripheral Access Control Registers" bitfld.long 0x10 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x10 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x10 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x190++0x3 line.long 0x0 "OPACRU,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x19C++0x13 line.long 0x0 "OPACRX,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x4 "OPACRY,Off-Platform Peripheral Access Control Registers" bitfld.long 0x4 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x8 "OPACRZ,Off-Platform Peripheral Access Control Registers" bitfld.long 0x8 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0xC "OPACRAA,Off-Platform Peripheral Access Control Registers" bitfld.long 0xC 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0xC 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x10 "OPACRAB,Off-Platform Peripheral Access Control Registers" bitfld.long 0x10 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x10 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x10 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x1B4++0xB line.long 0x0 "OPACRAD,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x4 "OPACRAE,Off-Platform Peripheral Access Control Registers" bitfld.long 0x4 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x8 "OPACRAF,Off-Platform Peripheral Access Control Registers" bitfld.long 0x8 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x1E0++0x3 line.long 0x0 "VMIDA,Peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "VMIDA,VMID associated with module a" group.long 0x244++0x17 line.long 0x0 "OVMIDB,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDC,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x8 "OVMIDD,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x8 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x8 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x8 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x8 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0xC "OVMIDE,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0xC 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0xC 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0xC 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0xC 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x10 "OVMIDF,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x10 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x10 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x10 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x10 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x14 "OVMIDG,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x14 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x14 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x14 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x14 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x260++0x3 line.long 0x0 "OVMIDI,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x268++0x3 line.long 0x0 "OVMIDK,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x270++0x3 line.long 0x0 "OVMIDM,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x288++0x7 line.long 0x0 "OVMIDS,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDT,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x294++0x13 line.long 0x0 "OVMIDV,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDW,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x8 "OVMIDX,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x8 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x8 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x8 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x8 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0xC "OVMIDY,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0xC 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0xC 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0xC 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0xC 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x10 "OVMIDZ,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x10 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x10 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x10 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x10 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x2AC++0x3 line.long 0x0 "OVMIDAB,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x2E0++0x3 line.long 0x0 "OVMIDAO,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x2F8++0x1B line.long 0x0 "OVMIDAU,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDAV,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x8 "OVMIDAW,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x8 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x8 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x8 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x8 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0xC "OVMIDAX,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0xC 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0xC 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0xC 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0xC 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x10 "OVMIDAY,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x10 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x10 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x10 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x10 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x14 "OVMIDAZ,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x14 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x14 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x14 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x14 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x18 "OVMIDBA,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x18 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x18 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x18 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x18 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x318++0x3 line.long 0x0 "OVMIDBC,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x328++0x3 line.long 0x0 "OVMIDBG,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x330++0x3 line.long 0x0 "OVMIDBI,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x338++0x3 line.long 0x0 "OVMIDBK,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x360++0xB line.long 0x0 "VIRTFAULT0,Virtualisation Fault 0 register" bitfld.long 0x0 23. "SLOTID_TYPE,Slot ID associated with the visualization fault is an onpf or offpf slot." "0: indicates offpf slot,1: indicates onpf slot" hexmask.long.byte 0x0 15.--22. 1. "SLOTID,Slot ID associated with the virtualisation fault" hexmask.long.byte 0x0 9.--14. 1. "MASTERID,Master ID associated with the virtualisation fault" hexmask.long.byte 0x0 1.--8. 1. "VMID,VMID associated with the virtualisation fault" bitfld.long 0x0 0. "ERRPEND,virtualisation Error is pending" "0,1" line.long 0x4 "VIRTFAULT1,Virtualisation Fault 1 register" bitfld.long 0x4 8.--10. "HBURST,hburst attribute associated the transaction causing virtualisation error" "0,1,2,3,4,5,6,7" bitfld.long 0x4 5.--7. "HSIZE,hsize attribute associated the transaction causing virtualisation error" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3.--4. "HTRANS,htrans attribute associated the transaction causing virtualisation error" "0,1,2,3" bitfld.long 0x4 1.--2. "HPROT,hprot attribute associated the transaction causing virtualisation error" "0,1,2,3" bitfld.long 0x4 0. "HWRITE,hwrite attribute associated the transaction causing virtualisation error" "0,1" line.long 0x8 "EL2_DISABLE,Virtualisation Fault 1 register" bitfld.long 0x8 0. "EL2_DISABLE,This bit controls virtualisation checks in PBRIDGE." "0: All virtualisation checks in PBRIDGE are enabled,1: All virtualisation checks in PBRIDGE are disabled" tree.end tree "PBRIDGE_4" base ad:0x71800000 group.long 0x0++0x1F line.long 0x0 "MPRA,Master Privilege Register A" bitfld.long 0x0 28.--30. "MPROT0,Access privilege level associated with bus master 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "MPROT1,Access privilege level associated with bus master 1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "MPROT2,Access privilege level associated with bus master 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "MPROT3,Access privilege level associated with bus master 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "MPROT4,Access privilege level associated with bus master 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "MPROT5,Access privilege level associated with bus master 5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "MPROT6,Access privilege level associated with bus master 6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "MPROT7,Access privilege level associated with bus master 7" "0,1,2,3,4,5,6,7" line.long 0x4 "MPRB,Master Privilege Register B" bitfld.long 0x4 28.--30. "MPROT8,Access privilege level associated with bus master 8" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "MPROT9,Access privilege level associated with bus master 9" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "MPROT10,Access privilege level associated with bus master 10" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "MPROT11,Access privilege level associated with bus master 11" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "MPROT12,Access privilege level associated with bus master 12" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "MPROT13,Access privilege level associated with bus master 13" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "MPROT14,Access privilege level associated with bus master 14" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "MPROT15,Access privilege level associated with bus master 15" "0,1,2,3,4,5,6,7" line.long 0x8 "MPRC,Master Privilege Register C" bitfld.long 0x8 28.--30. "MPROT16,Access privilege level associated with bus master 16" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "MPROT17,Access privilege level associated with bus master 17" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "MPROT18,Access privilege level associated with bus master 18" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "MPROT19,Access privilege level associated with bus master 19" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "MPROT20,Access privilege level associated with bus master 20" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8.--10. "MPROT21,Access privilege level associated with bus master 21" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "MPROT22,Access privilege level associated with bus master 22" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "MPROT23,Access privilege level associated with bus master 23" "0,1,2,3,4,5,6,7" line.long 0xC "MPRD,Master Privilege Register D" bitfld.long 0xC 28.--30. "MPROT24,Access privilege level associated with bus master 24" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "MPROT25,Access privilege level associated with bus master 25" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "MPROT26,Access privilege level associated with bus master 26" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "MPROT27,Access privilege level associated with bus master 27" "0,1,2,3,4,5,6,7" bitfld.long 0xC 12.--14. "MPROT28,Access privilege level associated with bus master 28" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8.--10. "MPROT29,Access privilege level associated with bus master 29" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4.--6. "MPROT30,Access privilege level associated with bus master 30" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "MPROT31,Access privilege level associated with bus master 31" "0,1,2,3,4,5,6,7" line.long 0x10 "MPRE,Master Privilege Register E" bitfld.long 0x10 28.--30. "MPROT32,Access privilege level associated with bus master 32" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "MPROT33,Access privilege level associated with bus master 33" "0,1,2,3,4,5,6,7" bitfld.long 0x10 20.--22. "MPROT34,Access privilege level associated with bus master 34" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "MPROT35,Access privilege level associated with bus master 35" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "MPROT36,Access privilege level associated with bus master 36" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8.--10. "MPROT37,Access privilege level associated with bus master 37" "0,1,2,3,4,5,6,7" bitfld.long 0x10 4.--6. "MPROT38,Access privilege level associated with bus master 38" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "MPROT39,Access privilege level associated with bus master 39" "0,1,2,3,4,5,6,7" line.long 0x14 "MPRF,Master Privilege Register F" bitfld.long 0x14 28.--30. "MPROT40,Access privilege level associated with bus master 40" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "MPROT41,Access privilege level associated with bus master 41" "0,1,2,3,4,5,6,7" bitfld.long 0x14 20.--22. "MPROT42,Access privilege level associated with bus master 42" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "MPROT43,Access privilege level associated with bus master 43" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "MPROT44,Access privilege level associated with bus master 44" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8.--10. "MPROT45,Access privilege level associated with bus master 45" "0,1,2,3,4,5,6,7" bitfld.long 0x14 4.--6. "MPROT46,Access privilege level associated with bus master 46" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "MPROT47,Access privilege level associated with bus master 47" "0,1,2,3,4,5,6,7" line.long 0x18 "MPRG,Master Privilege Register G" bitfld.long 0x18 28.--30. "MPROT48,Access privilege level associated with bus master 48" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "MPROT49,Access privilege level associated with bus master 49" "0,1,2,3,4,5,6,7" bitfld.long 0x18 20.--22. "MPROT50,Access privilege level associated with bus master 50" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "MPROT51,Access privilege level associated with bus master 51" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "MPROT52,Access privilege level associated with bus master 52" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8.--10. "MPROT53,Access privilege level associated with bus master 53" "0,1,2,3,4,5,6,7" bitfld.long 0x18 4.--6. "MPROT54,Access privilege level associated with bus master 54" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "MPROT55,Access privilege level associated with bus master 55" "0,1,2,3,4,5,6,7" line.long 0x1C "MPRH,Master Privilege Register H" bitfld.long 0x1C 28.--30. "MPROT56,Access privilege level associated with bus master 56" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--26. "MPROT57,Access privilege level associated with bus master 57" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--22. "MPROT58,Access privilege level associated with bus master 58" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 16.--18. "MPROT59,Access privilege level associated with bus master 59" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 12.--14. "MPROT60,Access privilege level associated with bus master 60" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8.--10. "MPROT61,Access privilege level associated with bus master 61" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 4.--6. "MPROT62,Access privilege level associated with bus master 62" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "MPROT63,Access privilege level associated with bus master 63" "0,1,2,3,4,5,6,7" group.long 0x100++0x3 line.long 0x0 "PACRA,Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "PACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" group.long 0x160++0x3 line.long 0x0 "OPACRI,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x1A8++0x17 line.long 0x0 "OPACRAA,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x4 "OPACRAB,Off-Platform Peripheral Access Control Registers" bitfld.long 0x4 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x8 "OPACRAC,Off-Platform Peripheral Access Control Registers" bitfld.long 0x8 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0xC "OPACRAD,Off-Platform Peripheral Access Control Registers" bitfld.long 0xC 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0xC 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x10 "OPACRAE,Off-Platform Peripheral Access Control Registers" bitfld.long 0x10 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x10 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x10 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x14 "OPACRAF,Off-Platform Peripheral Access Control Registers" bitfld.long 0x14 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x14 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x14 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x1E0++0x3 line.long 0x0 "VMIDA,Peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "VMIDA,VMID associated with module a" group.long 0x280++0x3 line.long 0x0 "OVMIDQ,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x314++0x13 line.long 0x0 "OVMIDBB,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDBC,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x8 "OVMIDBD,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x8 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x8 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x8 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x8 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0xC "OVMIDBE,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0xC 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0xC 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0xC 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0xC 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x10 "OVMIDBF,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x10 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x10 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x10 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x10 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x32C++0x13 line.long 0x0 "OVMIDBH,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x0 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x0 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x0 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x0 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x4 "OVMIDBI,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x4 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x4 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x4 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x4 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x8 "OVMIDBJ,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x8 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x8 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x8 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x8 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0xC "OVMIDBK,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0xC 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0xC 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0xC 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0xC 0.--7. 1. "OVMIDD,VMID associated with module d" line.long 0x10 "OVMIDBL,Off-Platform peripheral VMID memory protection registers" hexmask.long.byte 0x10 24.--31. 1. "OVMIDA,VMID associated with module a" hexmask.long.byte 0x10 16.--23. 1. "OVMIDB,VMID associated with module b" hexmask.long.byte 0x10 8.--15. 1. "OVMIDC,VMID associated with module c" hexmask.long.byte 0x10 0.--7. 1. "OVMIDD,VMID associated with module d" group.long 0x360++0xB line.long 0x0 "VIRTFAULT0,Virtualisation Fault 0 register" bitfld.long 0x0 23. "SLOTID_TYPE,Slot ID associated with the visualization fault is an onpf or offpf slot." "0: indicates offpf slot,1: indicates onpf slot" hexmask.long.byte 0x0 15.--22. 1. "SLOTID,Slot ID associated with the virtualisation fault" hexmask.long.byte 0x0 9.--14. 1. "MASTERID,Master ID associated with the virtualisation fault" hexmask.long.byte 0x0 1.--8. 1. "VMID,VMID associated with the virtualisation fault" bitfld.long 0x0 0. "ERRPEND,virtualisation Error is pending" "0,1" line.long 0x4 "VIRTFAULT1,Virtualisation Fault 1 register" bitfld.long 0x4 8.--10. "HBURST,hburst attribute associated the transaction causing virtualisation error" "0,1,2,3,4,5,6,7" bitfld.long 0x4 5.--7. "HSIZE,hsize attribute associated the transaction causing virtualisation error" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3.--4. "HTRANS,htrans attribute associated the transaction causing virtualisation error" "0,1,2,3" bitfld.long 0x4 1.--2. "HPROT,hprot attribute associated the transaction causing virtualisation error" "0,1,2,3" bitfld.long 0x4 0. "HWRITE,hwrite attribute associated the transaction causing virtualisation error" "0,1" line.long 0x8 "EL2_DISABLE,Virtualisation Fault 1 register" bitfld.long 0x8 0. "EL2_DISABLE,This bit controls virtualisation checks in PBRIDGE." "0: All virtualisation checks in PBRIDGE are enabled,1: All virtualisation checks in PBRIDGE are disabled" tree.end tree "PBRIDGE_5" base ad:0x71E00000 group.long 0x0++0x1F line.long 0x0 "MPRA,Master Privilege Register A" bitfld.long 0x0 28.--30. "MPROT0,Access privilege level associated with bus master 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "MPROT1,Access privilege level associated with bus master 1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "MPROT2,Access privilege level associated with bus master 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "MPROT3,Access privilege level associated with bus master 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "MPROT4,Access privilege level associated with bus master 4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "MPROT5,Access privilege level associated with bus master 5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "MPROT6,Access privilege level associated with bus master 6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "MPROT7,Access privilege level associated with bus master 7" "0,1,2,3,4,5,6,7" line.long 0x4 "MPRB,Master Privilege Register B" bitfld.long 0x4 28.--30. "MPROT8,Access privilege level associated with bus master 8" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "MPROT9,Access privilege level associated with bus master 9" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "MPROT10,Access privilege level associated with bus master 10" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "MPROT11,Access privilege level associated with bus master 11" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "MPROT12,Access privilege level associated with bus master 12" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "MPROT13,Access privilege level associated with bus master 13" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "MPROT14,Access privilege level associated with bus master 14" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "MPROT15,Access privilege level associated with bus master 15" "0,1,2,3,4,5,6,7" line.long 0x8 "MPRC,Master Privilege Register C" bitfld.long 0x8 28.--30. "MPROT16,Access privilege level associated with bus master 16" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "MPROT17,Access privilege level associated with bus master 17" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "MPROT18,Access privilege level associated with bus master 18" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "MPROT19,Access privilege level associated with bus master 19" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "MPROT20,Access privilege level associated with bus master 20" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "MPROT21,Access privilege level associated with bus master 21" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "MPROT22,Access privilege level associated with bus master 22" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "MPROT23,Access privilege level associated with bus master 23" "0,1,2,3,4,5,6,7" line.long 0xC "MPRD,Master Privilege Register D" bitfld.long 0xC 28.--30. "MPROT24,Access privilege level associated with bus master 24" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "MPROT25,Access privilege level associated with bus master 25" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "MPROT26,Access privilege level associated with bus master 26" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "MPROT27,Access privilege level associated with bus master 27" "0,1,2,3,4,5,6,7" bitfld.long 0xC 12.--14. "MPROT28,Access privilege level associated with bus master 28" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--10. "MPROT29,Access privilege level associated with bus master 29" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4.--6. "MPROT30,Access privilege level associated with bus master 30" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "MPROT31,Access privilege level associated with bus master 31" "0,1,2,3,4,5,6,7" line.long 0x10 "MPRE,Master Privilege Register E" bitfld.long 0x10 28.--30. "MPROT32,Access privilege level associated with bus master 32" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "MPROT33,Access privilege level associated with bus master 33" "0,1,2,3,4,5,6,7" bitfld.long 0x10 20.--22. "MPROT34,Access privilege level associated with bus master 34" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "MPROT35,Access privilege level associated with bus master 35" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "MPROT36,Access privilege level associated with bus master 36" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8.--10. "MPROT37,Access privilege level associated with bus master 37" "0,1,2,3,4,5,6,7" bitfld.long 0x10 4.--6. "MPROT38,Access privilege level associated with bus master 38" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "MPROT39,Access privilege level associated with bus master 39" "0,1,2,3,4,5,6,7" line.long 0x14 "MPRF,Master Privilege Register F" bitfld.long 0x14 28.--30. "MPROT40,Access privilege level associated with bus master 40" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "MPROT41,Access privilege level associated with bus master 41" "0,1,2,3,4,5,6,7" bitfld.long 0x14 20.--22. "MPROT42,Access privilege level associated with bus master 42" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "MPROT43,Access privilege level associated with bus master 43" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "MPROT44,Access privilege level associated with bus master 44" "0,1,2,3,4,5,6,7" bitfld.long 0x14 8.--10. "MPROT45,Access privilege level associated with bus master 45" "0,1,2,3,4,5,6,7" bitfld.long 0x14 4.--6. "MPROT46,Access privilege level associated with bus master 46" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "MPROT47,Access privilege level associated with bus master 47" "0,1,2,3,4,5,6,7" line.long 0x18 "MPRG,Master Privilege Register G" bitfld.long 0x18 28.--30. "MPROT48,Access privilege level associated with bus master 48" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "MPROT49,Access privilege level associated with bus master 49" "0,1,2,3,4,5,6,7" bitfld.long 0x18 20.--22. "MPROT50,Access privilege level associated with bus master 50" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "MPROT51,Access privilege level associated with bus master 51" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "MPROT52,Access privilege level associated with bus master 52" "0,1,2,3,4,5,6,7" bitfld.long 0x18 8.--10. "MPROT53,Access privilege level associated with bus master 53" "0,1,2,3,4,5,6,7" bitfld.long 0x18 4.--6. "MPROT54,Access privilege level associated with bus master 54" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "MPROT55,Access privilege level associated with bus master 55" "0,1,2,3,4,5,6,7" line.long 0x1C "MPRH,Master Privilege Register H" bitfld.long 0x1C 28.--30. "MPROT56,Access privilege level associated with bus master 56" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--26. "MPROT57,Access privilege level associated with bus master 57" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--22. "MPROT58,Access privilege level associated with bus master 58" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 16.--18. "MPROT59,Access privilege level associated with bus master 59" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 12.--14. "MPROT60,Access privilege level associated with bus master 60" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 8.--10. "MPROT61,Access privilege level associated with bus master 61" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 4.--6. "MPROT62,Access privilege level associated with bus master 62" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "MPROT63,Access privilege level associated with bus master 63" "0,1,2,3,4,5,6,7" group.long 0x100++0x3 line.long 0x0 "PACRA,Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "PACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" group.long 0x140++0xB line.long 0x0 "OPACRA,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x4 "OPACRB,Off-Platform Peripheral Access Control Registers" bitfld.long 0x4 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x8 "OPACRC,Off-Platform Peripheral Access Control Registers" bitfld.long 0x8 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x154++0x3 line.long 0x0 "OPACRF,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x160++0xF line.long 0x0 "OPACRI,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x4 "OPACRJ,Off-Platform Peripheral Access Control Registers" bitfld.long 0x4 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x8 "OPACRK,Off-Platform Peripheral Access Control Registers" bitfld.long 0x8 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0xC "OPACRL,Off-Platform Peripheral Access Control Registers" bitfld.long 0xC 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0xC 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x178++0x3 line.long 0x0 "OPACRO,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x194++0x3 line.long 0x0 "OPACRV,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x19C++0x3 line.long 0x0 "OPACRX,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x1A8++0x3 line.long 0x0 "OPACRAA,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" group.long 0x1B8++0x7 line.long 0x0 "OPACRAE,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" line.long 0x4 "OPACRAF,Off-Platform Peripheral Access Control Registers" bitfld.long 0x4 28.--30. "OPACRA,Access level associated with module a" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "OPACRB,Access level associated with module b" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "OPACRC,Access level associated with module c" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "OPACRD,Access level associated with module d" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "OPACRE,Access level associated with module e" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "OPACRF,Access level associated with module f" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "OPACRG,Access level associated with module g" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "OPACRH,Access level associated with module h" "0,1,2,3,4,5,6,7" tree.end tree.end tree "PLLDIG (Dual PLL Digital Interface)" base ad:0x0 tree "PLLDIG_DOMAIN_0" base ad:0x710C0100 group.long 0x20++0x13 line.long 0x0 "PLL1CR,PLL1 control register" bitfld.long 0x0 8.--9. "CLKCFG,Clock configuration" "0: PLL off,?,?,3: Normal mode with PLL running" bitfld.long 0x0 7. "EXPDIE,External power down cycle complete indication interrupt enable" "0: Ignore interrupt. Interrupt not requested,1: Enable interrupt request on power down cycle.." newline bitfld.long 0x0 3. "LOLIE,Loss of lock interrupt enable" "0: or PLL1CR[LOLIE]=0,1: Enable interrupt request upon loss of lock and.." line.long 0x4 "PLL1SR,PLL1 status register" bitfld.long 0x4 7. "EXTPDF,External power down cycle complete indication interrupt flag" "0: PLLs not power cycled. Interrupt not requested,1: PLLs power down cycle is complete. Interrupt is.." bitfld.long 0x4 3. "LOLF,Loss of lock flag" "0: No loss of lock detected. Interrupt service not..,1: or asserting reset" newline bitfld.long 0x4 2. "LOCK,Lock status bit" "0: PLL is unlocked,1: PLL is locked" line.long 0x8 "PLL1DV,PLL1 divider register" hexmask.long.byte 0x8 24.--29. 1. "RFDPHI_LC,PHI_LC reduced frequency divider" hexmask.long.byte 0x8 16.--21. 1. "RFDPHI_HP,PHI_HP reduced frequency divider" newline hexmask.long.byte 0x8 0.--6. 1. "MFD,Loop multiplication factor divider" line.long 0xC "PLL1FM,PLL1 frequency modulation register" bitfld.long 0xC 30. "MODEN,Modulation enable" "0: Frequency modulation disabled,1: Frequency modulation enabled" bitfld.long 0xC 29. "MODSEL,Modulation selection" "0: Modulation centered around nominal frequency,1: Modulation spread below nominal frequency" newline hexmask.long.word 0xC 16.--28. 1. "MODPRD,Modulation period" hexmask.long.word 0xC 0.--14. 1. "INCSTP,Increment step" line.long 0x10 "PLL1FD,PLL1 fractional divider register" bitfld.long 0x10 30. "FDEN,Fractional divide enable" "0: Fractional divide disabled,1: Fractional divide enabled" bitfld.long 0x10 16.--17. "DTHDIS,Dither disable" "0: Increase PLL multiplication factor by 1/2^13 and..,1: Increase PLL multiplication factor by 1/2^13 and..,2: No influence on PLL multiplication factor and..,3: No influence on PLL multiplication factor and no.." newline hexmask.long.word 0x10 0.--11. 1. "FRCDIV,Fractional divide input" tree.end tree "PLLDIG_DOMAIN_1" base ad:0x716C0100 group.long 0x20++0x13 line.long 0x0 "PLL1CR,PLL1 control register" bitfld.long 0x0 8.--9. "CLKCFG,Clock configuration" "0: PLL off,?,?,3: Normal mode with PLL running" bitfld.long 0x0 7. "EXPDIE,External power down cycle complete indication interrupt enable" "0: Ignore interrupt. Interrupt not requested,1: Enable interrupt request on power down cycle.." newline bitfld.long 0x0 3. "LOLIE,Loss of lock interrupt enable" "0: or PLL1CR[LOLIE]=0,1: Enable interrupt request upon loss of lock and.." line.long 0x4 "PLL1SR,PLL1 status register" bitfld.long 0x4 7. "EXTPDF,External power down cycle complete indication interrupt flag" "0: PLLs not power cycled. Interrupt not requested,1: PLLs power down cycle is complete. Interrupt is.." bitfld.long 0x4 3. "LOLF,Loss of lock flag" "0: No loss of lock detected. Interrupt service not..,1: or asserting reset" newline bitfld.long 0x4 2. "LOCK,Lock status bit" "0: PLL is unlocked,1: PLL is locked" line.long 0x8 "PLL1DV,PLL1 divider register" hexmask.long.byte 0x8 24.--29. 1. "RFDPHI_LC,PHI_LC reduced frequency divider" hexmask.long.byte 0x8 16.--21. 1. "RFDPHI_HP,PHI_HP reduced frequency divider" newline hexmask.long.byte 0x8 0.--6. 1. "MFD,Loop multiplication factor divider" line.long 0xC "PLL1FM,PLL1 frequency modulation register" bitfld.long 0xC 30. "MODEN,Modulation enable" "0: Frequency modulation disabled,1: Frequency modulation enabled" bitfld.long 0xC 29. "MODSEL,Modulation selection" "0: Modulation centered around nominal frequency,1: Modulation spread below nominal frequency" newline hexmask.long.word 0xC 16.--28. 1. "MODPRD,Modulation period" hexmask.long.word 0xC 0.--14. 1. "INCSTP,Increment step" line.long 0x10 "PLL1FD,PLL1 fractional divider register" bitfld.long 0x10 30. "FDEN,Fractional divide enable" "0: Fractional divide disabled,1: Fractional divide enabled" bitfld.long 0x10 16.--17. "DTHDIS,Dither disable" "0: Increase PLL multiplication factor by 1/2^13 and..,1: Increase PLL multiplication factor by 1/2^13 and..,2: No influence on PLL multiplication factor and..,3: No influence on PLL multiplication factor and no.." newline hexmask.long.word 0x10 0.--11. 1. "FRCDIV,Fractional divide input" tree.end tree "PLLDIG_DOMAIN_2" base ad:0x710C4100 group.long 0x20++0x13 line.long 0x0 "PLL1CR,PLL1 control register" bitfld.long 0x0 8.--9. "CLKCFG,Clock configuration" "0: PLL off,?,?,3: Normal mode with PLL running" bitfld.long 0x0 7. "EXPDIE,External power down cycle complete indication interrupt enable" "0: Ignore interrupt. Interrupt not requested,1: Enable interrupt request on power down cycle.." newline bitfld.long 0x0 3. "LOLIE,Loss of lock interrupt enable" "0: or PLL1CR[LOLIE]=0,1: Enable interrupt request upon loss of lock and.." line.long 0x4 "PLL1SR,PLL1 status register" bitfld.long 0x4 7. "EXTPDF,External power down cycle complete indication interrupt flag" "0: PLLs not power cycled. Interrupt not requested,1: PLLs power down cycle is complete. Interrupt is.." bitfld.long 0x4 3. "LOLF,Loss of lock flag" "0: No loss of lock detected. Interrupt service not..,1: or asserting reset" newline bitfld.long 0x4 2. "LOCK,Lock status bit" "0: PLL is unlocked,1: PLL is locked" line.long 0x8 "PLL1DV,PLL1 divider register" hexmask.long.byte 0x8 24.--29. 1. "RFDPHI_LC,PHI_LC reduced frequency divider" hexmask.long.byte 0x8 16.--21. 1. "RFDPHI_HP,PHI_HP reduced frequency divider" newline hexmask.long.byte 0x8 0.--6. 1. "MFD,Loop multiplication factor divider" line.long 0xC "PLL1FM,PLL1 frequency modulation register" bitfld.long 0xC 30. "MODEN,Modulation enable" "0: Frequency modulation disabled,1: Frequency modulation enabled" bitfld.long 0xC 29. "MODSEL,Modulation selection" "0: Modulation centered around nominal frequency,1: Modulation spread below nominal frequency" newline hexmask.long.word 0xC 16.--28. 1. "MODPRD,Modulation period" hexmask.long.word 0xC 0.--14. 1. "INCSTP,Increment step" line.long 0x10 "PLL1FD,PLL1 fractional divider register" bitfld.long 0x10 30. "FDEN,Fractional divide enable" "0: Fractional divide disabled,1: Fractional divide enabled" bitfld.long 0x10 16.--17. "DTHDIS,Dither disable" "0: Increase PLL multiplication factor by 1/2^13 and..,1: Increase PLL multiplication factor by 1/2^13 and..,2: No influence on PLL multiplication factor and..,3: No influence on PLL multiplication factor and no.." newline hexmask.long.word 0x10 0.--11. 1. "FRCDIV,Fractional divide input" tree.end tree "PLLDIG_PERIPHERAL_DOMAIN" base ad:0x722C8100 group.long 0x0++0xB line.long 0x0 "PLL0CR,PLL0 control register" bitfld.long 0x0 8.--9. "CLKCFG,Clock configuration" "0: PLL off.,?,?,3: Normal mode with PLL running" bitfld.long 0x0 7. "EXPDIE,External power down cycle complete indication interrupt enable" "0: Ignore interrupt. Interrupt not requested,1: Enable interrupt request on power down cycle.." newline bitfld.long 0x0 3. "LOLIE,Loss of lock interrupt enable" "0: or PLL0x0:CR[LOLIE]=0,1: Enable interrupt request upon loss of lock" line.long 0x4 "PLL0SR,PLL0 status register" bitfld.long 0x4 7. "EXTPDF,External power down cycle complete indication interrupt flag" "0: PLLs not power cycled. Interrupt not requested,1: PLLs power down cycle is complete. Interrupt is.." bitfld.long 0x4 3. "LOLF,Loss of lock flag" "0: No loss of lock detected. Interrupt service not..,1: Loss of lock detected. Interrupt service requested" newline bitfld.long 0x4 2. "LOCK,Lock status bit" "0: PLL is unlocked,1: PLL is locked" line.long 0x8 "PLL0DV,PLL0 divider register" hexmask.long.byte 0x8 27.--30. 1. "RFDPHI1,PHI1 reduced frequency divider" hexmask.long.byte 0x8 16.--21. 1. "RFDPHI,PHI reduced frequency divider" newline bitfld.long 0x8 12.--14. "PREDIV,Input clock pre-divider" "0: causes the input clock to be inhibited,1: Divide by 1,2: Divide by 2,?,?,?,6: Divide by 6,7: Divide by 7" hexmask.long.byte 0x8 0.--6. 1. "MFD,Loop multiplication factor divider" group.long 0x24++0xB line.long 0x0 "PLL1SR,PLL0 status register for FM output" bitfld.long 0x0 2. "LOCK_JM,Lock_JM status bit indicates whether PLL_JM has acquired lock." "0: PLL_JM is unlocked,1: PLL_JM is locked" line.long 0x4 "PLL1DV,PLL0 divider register for FM output" hexmask.long.byte 0x4 16.--21. 1. "RFDPHI_JM,PHI_JM reduced frequency divider" line.long 0x8 "PLL1FM,PLL0 frequency modulation register" bitfld.long 0x8 30. "MODEN,Modulation enable" "0: Frequency modulation disabled,1: Frequency modulation enabled" bitfld.long 0x8 29. "MODSEL,Modulation selection" "0: Modulation depth = +/-2% centered around nominal..,1: Modulation depth = +/-1% centered around nominal.." newline hexmask.long.byte 0x8 16.--20. 1. "MODPRD,Modulation period division factor (MPDIV)" tree.end tree.end tree "PMC_DIG (Power Management Controller Digital Interface)" base ad:0x0 tree "PMC_DIG_PERIPHERAL_DOMAIN" base ad:0x722B0400 group.long 0x0++0x13 line.long 0x0 "EPR_LV0,Event Pending LV0 register" bitfld.long 0x0 27. "LVD3_TD,LVD3_TD flag" "0,1" newline bitfld.long 0x0 18. "LVD2_C_MD,LVD2_C_MD flag" "0,1" newline bitfld.long 0x0 17. "LVD2_C_LP,LVD2_C_LP flag" "0,1" newline bitfld.long 0x0 2. "MVD0_C_MD,MVD0_C_MD flag" "0,1" newline bitfld.long 0x0 1. "MVD0_C_LP,MVD0_C_LP flag" "0,1" newline bitfld.long 0x0 0. "MVD0_C_ULP,MVD0_C_ULP flag" "0,1" line.long 0x4 "REE_LV0,Reset Event Enable LV0 register" bitfld.long 0x4 27. "REE3_TD,LVD3_TD reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 18. "REE2_C_MD,LVD2_C_MD reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 17. "REE2_C_LP,LVD2_C_LP reset enable" "0: Reset disabled,1: Reset enabled" line.long 0x8 "RES_LV0,Reset Event Select LV0 register" bitfld.long 0x8 27. "RES3_TD,LVD3_TD reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 18. "RES2_C_MD,LVD2_C_MD reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 17. "RES2_C_LP,LVD2_C_LP reset event select" "0: Destructive reset,1: Functional reset" line.long 0xC "IEE_LV0,Interrupt Enable LV0 register" bitfld.long 0xC 27. "IEE3_TD,LVD3_TD interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 18. "IEE2_C_MD,LVD2_C_MD interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 17. "IEE2_C_LP,LVD2_C_LP interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x10 "FEE_LV0,FCCU Event Enable LV0 register" bitfld.long 0x10 27. "FEE3_TD,LVD3_TD FCCU event enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x10 18. "FEE2_C_MD,LVD2_C_MD FCCU event enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x10 17. "FEE2_C_LP,LVD2_C_LP FCCU event enable" "0: Reset disabled,1: Reset enabled" group.long 0x20++0x13 line.long 0x0 "EPR_LV1,Event Pending LV1 register" bitfld.long 0x0 15. "LVD5_ED,LVD5_ED flag" "0,1" line.long 0x4 "REE_LV1,Reset Event Enable LV1 register" bitfld.long 0x4 15. "REE5_ED,LVD5_ED reset enable" "0: Reset disabled,1: Reset enabled" line.long 0x8 "RES_LV1,Reset Event Select LV1 register" bitfld.long 0x8 15. "RES5_ED,LVD5_ED reset event select" "0: Destructive reset,1: Functional reset" line.long 0xC "IEE_LV1,Interrupt Enable LV1 register" bitfld.long 0xC 15. "IEE5_ED,LVD5_ED interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x10 "FEE_LV1,FCCU Event Enable LV1 register" bitfld.long 0x10 15. "FEE5_ED,LVD5_ED FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" group.long 0x40++0x13 line.long 0x0 "EPR_LV2,Event Pending LV2 register" bitfld.long 0x0 24. "UVD11_C_MD,UVD11_C_MD flag" "0,1" newline bitfld.long 0x0 18. "UVD10_C_MD,UVD10_C_MD flag" "0,1" newline bitfld.long 0x0 16. "UVD10_C_ULP,UVD10_C_ULP flag" "0,1" line.long 0x4 "REE_LV2,Reset Event Enable LV2 register" bitfld.long 0x4 24. "REE11_C_MD,UVD11_C_MD reset enable" "0: Reset disabled,1: Reset enabled" line.long 0x8 "RES_LV2,Reset Event Select LV2 register" bitfld.long 0x8 24. "RES11_C_MD,UVD11_C_MD reset event select" "0: Destructive reset,1: Functional reset" line.long 0xC "IEE_LV2,Interrupt Enable LV2 register" bitfld.long 0xC 24. "IEE11_C_MD,UVD11_C_MD interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x10 "FEE_LV2,FCCU Event Enable LV2 register" bitfld.long 0x10 24. "FEE11_C_MD,UVD11_C_MD FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" group.long 0x60++0x13 line.long 0x0 "EPR_HV0,Event Pending HV0 register" bitfld.long 0x0 30. "LVD15_A,LVD15_A flag" "0,1" newline bitfld.long 0x0 28. "LVD15_S,LVD15_S flag" "0,1" newline bitfld.long 0x0 18. "LVD14_C_MD,LVD14_C_MD flag" "0,1" newline bitfld.long 0x0 16. "LVD14_C,LVD14_C flag" "0,1" newline bitfld.long 0x0 12. "MVD13_S,MVD13_S flag" "0,1" newline bitfld.long 0x0 2. "MVD12_C_MD,MVD12_C_MD flag" "0,1" newline bitfld.long 0x0 0. "MVD12_C,MVD12_C flag" "0,1" line.long 0x4 "REE_HV0,Reset Event Enable HV0 register" bitfld.long 0x4 30. "REE15_A,LVD15_A reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 28. "REE15_S,LVD15_S reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 18. "REE14_C_MD,LVD14_C_MD reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 16. "REE14_C,LVD14_C reset enable" "0: Reset disabled,1: Reset enabled" line.long 0x8 "RES_HV0,Reset Event Select HV0 register" bitfld.long 0x8 30. "RES15_A,LVD15_A reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 28. "RES15_S,LVD15_S reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 18. "RES14_C_MD,LVD14_C_MD reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 16. "RES14_C,LVD14_C reset event select" "0: Destructive reset,1: Functional reset" line.long 0xC "IEE_HV0,Interrupt Enable HV0 register" bitfld.long 0xC 30. "IEE15_A,LVD15_A interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 28. "IEE15_S,LVD15_S interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 18. "IEE14_C_MD,LVD14_C_MD interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 16. "IEE14_C,LVD14_C interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x10 "FEE_HV0,FCCU Event Enable HV0 register" bitfld.long 0x10 30. "FEE15_A,LVD15_A FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" newline bitfld.long 0x10 28. "FEE15_S,LVD15_S FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" newline bitfld.long 0x10 18. "FEE14_C_MD,LVD14_C_MD FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" newline bitfld.long 0x10 16. "FEE14_C,LVD14_C FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" group.long 0x80++0x13 line.long 0x0 "EPR_HV1,Event Pending HV1 register" bitfld.long 0x0 30. "LVD19_A,LVD19_A flag" "0,1" newline bitfld.long 0x0 29. "LVD19_S1,LVD19_S1 flag" "0,1" newline bitfld.long 0x0 28. "LVD19_S0,LVD19_S0 flag" "0,1" newline bitfld.long 0x0 26. "LVD19_NP,LVD19_NP flag" "0,1" newline bitfld.long 0x0 18. "LVD18_C_MD,LVD18_C_MD flag" "0,1" newline bitfld.long 0x0 14. "LVD17_IX1,LVD17_IX1 flag" "0,1" newline bitfld.long 0x0 13. "LVD17_IX0,LVD17_IX0 flag" "0,1" line.long 0x4 "REE_HV1,Reset Event Enable HV1 register" bitfld.long 0x4 30. "REE19_A,LVD19_A reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 29. "REE19_S1,LVD19_S1 reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 28. "REE19_S0,LVD19_S0 reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 26. "REE19_NP,LVD19_NP reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 18. "REE18_C_MD,LVD18_C_MD reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 14. "REE17_IX1,LVD17_IX1 reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 13. "REE17_IX0,LVD17_IX0 reset enable" "0: Reset disabled,1: Reset enabled" line.long 0x8 "RES_HV1,Reset Event Select HV1 register" bitfld.long 0x8 30. "RES19_A,LVD19_A reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 29. "RES19_S1,LVD19_S1 reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 28. "RES19_S0,LVD19_S0 reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 26. "RES19_NP,LVD19_NP reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 18. "RES18_C_MD,LVD18_C_MD reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 14. "RES17_IX1,LVD17_IX1 reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 13. "RES17_IX0,LVD17_IX0 reset event select" "0: Destructive reset,1: Functional reset" line.long 0xC "IEE_HV1,Interrupt Enable HV1 register" bitfld.long 0xC 30. "IEE19_A,LVD19_A interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 29. "IEE19_S1,LVD19_S1 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 28. "IEE19_S0,LVD19_S0 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 26. "IEE19_NP,LVD19_NP interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 18. "IEE18_C_MD,LVD18_C_MD interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 14. "IEE17_IX1,LVD17_IX1 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 13. "IEE17_IX0,LVD17_IX0 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x10 "FEE_HV1,FCCU Event Enable HV1 register" bitfld.long 0x10 30. "FEE19_A,LVD19_A FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" newline bitfld.long 0x10 29. "FEE19_S1,LVD19_S1 FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" newline bitfld.long 0x10 28. "FEE19_S0,LVD19_S0 FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" newline bitfld.long 0x10 26. "FEE19_NP,LVD19_NP FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" newline bitfld.long 0x10 18. "FEE18_C_MD,LVD18_C_MD FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" newline bitfld.long 0x10 14. "FEE17_IX1,LVD17_IX1 FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" newline bitfld.long 0x10 13. "FEE17_IX0,LVD17_IX0 FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" group.long 0xA0++0x13 line.long 0x0 "EPR_HV2,Event Pending HV2 register" bitfld.long 0x0 30. "UVD23_A,UVD23_A flag" "0,1" newline bitfld.long 0x0 28. "UVD23_S,UVD23_S flag" "0,1" newline bitfld.long 0x0 18. "UVD22_C_MD,UVD22_C_MD flag" "0,1" newline bitfld.long 0x0 16. "UVD22_C,UVD22_C flag" "0,1" newline bitfld.long 0x0 14. "HVD21_IX1,HVD21_IX1 flag" "0,1" newline bitfld.long 0x0 13. "HVD21_IX0,HVD21_IX0 flag" "0,1" newline bitfld.long 0x0 2. "HVD20_C_MD,HVD20_C_MD flag" "0,1" line.long 0x4 "REE_HV2,Reset Event Enable HV2 register" bitfld.long 0x4 30. "REE23_A,UVD23_A reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 14. "REE21_IX1,HVD21_IX1 reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 13. "REE21_IX0,HVD21_IX0 reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 2. "REE20_C_MD,HVD20_C_MD reset enable" "0: Reset disabled,1: Reset enabled" line.long 0x8 "RES_HV2,Reset Event Select HV2 register" bitfld.long 0x8 30. "RES23_A,UVD23_A reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 14. "RES21_IX1,HVD21_IX1 reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 13. "RES21_IX0,HVD21_IX0 reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 2. "RES20_C_MD,HVD20_C_MD reset event select" "0: Destructive reset,1: Functional reset" line.long 0xC "IEE_HV2,Interrupt Enable HV2 register" bitfld.long 0xC 30. "IEE23_A,UVD23_A interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 14. "IEE21_IX1,HVD21_IX1 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 13. "IEE21_IX0,HVD21_IX0 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 2. "IEE20_C_MD,HVD20_C_MD interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x10 "FEE_HV2,FCCU Event Enable HV2 register" bitfld.long 0x10 30. "FEE23_A,UVD23_A FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" newline bitfld.long 0x10 14. "FEE21_IX1,HVD21_IX1 FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" newline bitfld.long 0x10 13. "FEE21_IX0,HVD21_IX0 FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" newline bitfld.long 0x10 2. "FEE20_C_MD,HVD20_C_MD FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" group.long 0xC0++0x13 line.long 0x0 "EPR_MV0,Event Pending MV0 register" bitfld.long 0x0 31. "LVD29_Y,LVD29_Y flag" "0,1" newline bitfld.long 0x0 30. "LVD29_A,LVD29_A flag" "0,1" newline bitfld.long 0x0 26. "LVD29_N,LVD29_N flag" "0,1" newline bitfld.long 0x0 25. "LVD29_P,LVD29_P flag" "0,1" newline bitfld.long 0x0 17. "LVD26_C_LP,LVD26_C_LP flag" "0,1" newline bitfld.long 0x0 16. "LVD26_C_ULP,LVD26_C_ULP flag" "0,1" newline bitfld.long 0x0 10. "MVD25_N,MVD25_N flag" "0,1" newline bitfld.long 0x0 1. "MVD24_C_LP,MVD24_C_LP flag" "0,1" newline bitfld.long 0x0 0. "MVD24_C_ULP,MVD24_C_ULP flag" "0,1" line.long 0x4 "REE_MV0,Reset Event Enable MV0 register" bitfld.long 0x4 31. "REE29_Y,LVD29_Y reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 30. "REE29_A,LVD29_A reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 26. "REE29_N,LVD29_N reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 25. "REE29_P,LVD29_P reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 17. "REE26_C_LP,LVD26_C_LP reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 16. "REE26_C_ULP,LVD26_C_ULP reset enable" "0: Reset disabled,1: Reset enabled" line.long 0x8 "RES_MV0,Reset Event Select MV0 register" bitfld.long 0x8 31. "RES29_Y,LVD29_Y reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 30. "RES29_A,LVD29_A reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 26. "RES29_N,LVD29_N reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 25. "RES29_P,LVD29_P reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 17. "RES26_C_LP,LVD26_C_LP reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 16. "RES26_C_ULP,LVD26_C_ULP reset event select" "0: Destructive reset,1: Functional reset" line.long 0xC "IEE_MV0,Interrupt Enable MV0 register" bitfld.long 0xC 31. "IEE29_Y,LVD29_Y interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 30. "IEE29_A,LVD29_A interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 26. "IEE29_N,LVD29_N interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 25. "IEE29_P,LVD29_P interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 17. "IEE26_C_LP,LVD26_C_LP interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 16. "IEE26_C_ULP,LVD26_C_ULP interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x10 "FEE_MV0,FCCU Event Enable MV0 register" bitfld.long 0x10 31. "FEE29_Y,LVD29_Y FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" newline bitfld.long 0x10 30. "FEE29_A,LVD29_A FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" newline bitfld.long 0x10 26. "FEE29_N,LVD29_N FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" newline bitfld.long 0x10 25. "FEE29_P,LVD29_P FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" newline bitfld.long 0x10 17. "FEE26_C_LP,LVD26_C_LP FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" newline bitfld.long 0x10 16. "FEE26_C_ULP,LVD26_C_ULP FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" group.long 0x100++0x13 line.long 0x0 "EPR_MV2,Event Pending MV2 register" bitfld.long 0x0 31. "UVD35_Y,UVD35_Y flag" "0,1" newline bitfld.long 0x0 30. "UVD35_A,UVD35_A flag" "0,1" newline bitfld.long 0x0 26. "UVD35_N,UVD35_N flag" "0,1" newline bitfld.long 0x0 25. "UVD35_P,UVD35_P flag" "0,1" newline bitfld.long 0x0 17. "UVD34_C_LP,UVD34_C_LP flag" "0,1" newline bitfld.long 0x0 16. "UVD34_C_ULP,UVD34_C_ULP flag" "0,1" line.long 0x4 "REE_MV2,Reset Event Enable MV2 register" bitfld.long 0x4 31. "REE35_Y,UVD35_Y reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 30. "REE35_A,UVD35_A reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 25. "REE35_P,UVD35_P reset enable" "0: Reset disabled,1: Reset enabled" line.long 0x8 "RES_MV2,Reset Event Select MV2 register" bitfld.long 0x8 31. "RES35_Y,UVD35_Y reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 30. "RES35_A,UVD35_A reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 25. "RES35_P,UVD35_P reset event select" "0: Destructive reset,1: Functional reset" line.long 0xC "IEE_MV2,Interrupt Enable MV2 register" bitfld.long 0xC 31. "IEE35_Y,UVD35_Y interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 30. "IEE35_A,UVD35_A interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 25. "IEE35_P,UVD35_P interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x10 "FEE_MV2,FCCU Event Enable MV2 register" bitfld.long 0x10 31. "FEE35_Y,UVD35_Y FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" newline bitfld.long 0x10 30. "FEE35_A,UVD35_A FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" newline bitfld.long 0x10 25. "FEE35_P,UVD35_P FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" group.long 0x120++0x13 line.long 0x0 "EPR_BV,Event Pending BV register" bitfld.long 0x0 28. "HVD39_FB,HVD39_FB flag" "0,1" newline bitfld.long 0x0 8. "LVD37_FB,LVD37_FB flag" "0,1" line.long 0x4 "REE_BV,Reset Event Enable BV register" bitfld.long 0x4 28. "REE39_FB,HVD39_FB reset enable" "0: Reset disabled,1: Reset enabled" newline bitfld.long 0x4 8. "REE37_FB,LVD37_FB reset enable" "0: Reset disabled,1: Reset enabled" line.long 0x8 "RES_BV,Reset Event Select BV register" bitfld.long 0x8 28. "RES39_FB,HVD39_FB reset event select" "0: Destructive reset,1: Functional reset" newline bitfld.long 0x8 8. "RES37_FB,LVD37_FB reset event select" "0: Destructive reset,1: Functional reset" line.long 0xC "IEE_BV,Interrupt Enable BV register" bitfld.long 0xC 28. "IEE39_FB,HVD39_FB interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0xC 8. "IEE37_FB,LVD37_FB interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x10 "FEE_BV,FCCU Event Enable BV register" bitfld.long 0x10 28. "FEE39_FB,HVD39_FB FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" newline bitfld.long 0x10 8. "FEE37_FB,LVD37_FB FCCU event enable" "0: FCCU event disabled,1: FCCU event enabled" rgroup.long 0x200++0x1B line.long 0x0 "GR_LV0,Supply Gauge Status LV0 register" bitfld.long 0x0 27. "LVD3_TD,LVD3_TD detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0x0 18. "LVD2_C_MD,LVD2_C_MD detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0x0 17. "LVD2_C_LP,LVD2_C_LP detect flag" "0: Event not occurring,1: Event occurring" line.long 0x4 "GR_LV1,Supply Gauge Status LV1 register" bitfld.long 0x4 15. "LVD5_ED,LVD5_ED detect flag" "0: Event not occurring,1: Event occurring" line.long 0x8 "GR_LV2,Supply Gauge Status LV2 register" bitfld.long 0x8 24. "UVD11_C_MD,UVD11_C_MD detect flag" "0: Event not occurring,1: Event occurring" line.long 0xC "GR_HV0,Supply Gauge Status HV0 register" bitfld.long 0xC 30. "LVD15_A,LVD15_A detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0xC 28. "LVD15_S,LVD15_S detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0xC 18. "LVD14_C_MD,LVD14_C_MD detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0xC 16. "LVD14_C,LVD14_C detect flag" "0: Event not occurring,1: Event occurring" line.long 0x10 "GR_HV1,Supply Gauge Status HV1 register" bitfld.long 0x10 30. "LVD19_A,LVD19_A detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0x10 29. "LVD19_S1,LVD19_S1 detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0x10 28. "LVD19_S0,LVD19_S0 detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0x10 26. "LVD19_NP,LVD19_NP detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0x10 18. "LVD18_C_MD,LVD18_C_MD detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0x10 14. "LVD17_IX1,LVD17_IX1 detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0x10 13. "LVD17_IX0,LVD17_IX0 detect flag" "0: Event not occurring,1: Event occurring" line.long 0x14 "GR_HV2,Supply Gauge Status HV2 register" bitfld.long 0x14 30. "UVD23_A,UVD23_A detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0x14 14. "HVD21_IX1,HVD21_IX1 detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0x14 13. "HVD21_IX0,HVD21_IX0 detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0x14 2. "HVD20_C_MD,HVD20_C_MD detect flag" "0: Event not occurring,1: Event occurring" line.long 0x18 "GR_MV0,Supply Gauge Status MV0 register" bitfld.long 0x18 31. "LVD27_Y,LVD27_Y detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0x18 30. "LVD27_A,LVD27_A detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0x18 26. "LVD27_N,LVD27_N detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0x18 25. "LVD27_P,LVD27_P detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0x18 17. "LVD26_C_LP,LVD26_C_LP detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0x18 16. "LVD26_C_ULP,LVD26_C_ULP detect flag" "0: Event not occurring,1: Event occurring" rgroup.long 0x220++0x7 line.long 0x0 "GR_MV2,Supply Gauge Status MV2 register" bitfld.long 0x0 31. "UVD35_Y,UVD35_Y detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0x0 30. "UVD35_A,UVD35_A detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0x0 25. "UVD35_P,UVD35_P detect flag" "0: Event not occurring,1: Event occurring" line.long 0x4 "GR_BV,Supply Gauge Status BV register" bitfld.long 0x4 28. "HVD39_FB,HVD39_FB detect flag" "0: Event not occurring,1: Event occurring" newline bitfld.long 0x4 8. "LVD37_FB,LVD37_FB detect flag" "0: Event not occurring,1: Event occurring" rgroup.long 0x230++0xB line.long 0x0 "GR_P0,Pending Gauge Status P0 register" bitfld.long 0x0 27. "LVD27_BYTE3,LVD27_BYTE3 pending monitor" "0,1" newline bitfld.long 0x0 26. "LVD26_BYTE2,LVD26_BYTE2 pending monitor" "0,1" newline bitfld.long 0x0 23. "UVD23_BYTE3,UVD23_BYTE3 pending monitor" "0,1" newline bitfld.long 0x0 22. "UVD22_BYTE2,UVD22_BYTE2 pending monitor" "0,1" newline bitfld.long 0x0 21. "HVD21_BYTE1,HVD21_BYTE1 pending monitor" "0,1" newline bitfld.long 0x0 20. "HVD20_BYTE0,HVD20_BYTE0 pending monitor" "0,1" newline bitfld.long 0x0 19. "LVD19_BYTE3,LVD19_BYTE3 pending monitor" "0,1" newline bitfld.long 0x0 18. "LVD18_BYTE2,LVD18_BYTE2 pending monitor" "0,1" newline bitfld.long 0x0 17. "LVD17_BYTE1,LVD17_BYTE1 pending monitor" "0,1" newline bitfld.long 0x0 15. "LVD15_BYTE3,LVD15_BYTE3 pending monitor" "0,1" newline bitfld.long 0x0 14. "LVD14_BYTE2,LVD14_BYTE2 pending monitor" "0,1" newline bitfld.long 0x0 11. "UVD11_BYTE3,UVD11_BYTE3 pending monitor" "0,1" newline bitfld.long 0x0 10. "UVD10_BYTE2,UVD10_BYTE2 pending monitor" "0,1" newline bitfld.long 0x0 5. "LVD5_BYTE1,LVD5_BYTE1 pending monitor" "0,1" newline bitfld.long 0x0 3. "LVD3_BYTE3,LVD3_BYTE3 pending monitor" "0,1" newline bitfld.long 0x0 2. "LVD2_BYTE2,LVD2_BYTE2 pending monitor" "0,1" line.long 0x4 "GR_P1,Pending Gauge Status P1 register" bitfld.long 0x4 7. "HVD39_BYTE3,HVD39_BYTE3 pending monitor" "0,1" newline bitfld.long 0x4 5. "LVD37_BYTE1,LVD37_BYTE1 pending monitor" "0,1" newline bitfld.long 0x4 3. "UVD35_BYTE3,UVD35_BYTE3 pending monitor" "0,1" newline bitfld.long 0x4 2. "UVD34_BYTE2,UVD34_BYTE2 pending monitor" "0,1" line.long 0x8 "IE_G0,Interrupt Enable Pending G0 register" bitfld.long 0x8 27. "LVD27_BYTE3,LVD27_BYTE3 enable interrupt monitor" "0,1" newline bitfld.long 0x8 26. "LVD26_BYTE2,LVD26_BYTE2 enable interrupt monitor" "0,1" newline bitfld.long 0x8 23. "UVD23_BYTE3,UVD23_BYTE3 enable interrupt monitor" "0,1" newline bitfld.long 0x8 21. "HVD21_BYTE1,HVD21_BYTE1enable interrupt monitor" "0,1" newline bitfld.long 0x8 20. "HVD20_BYTE0,HVD20_BYTE0 enable interrupt monitor" "0,1" newline bitfld.long 0x8 19. "LVD19_BYTE3,LVD19_BYTE3 enable interrupt monitor" "0,1" newline bitfld.long 0x8 18. "LVD18_BYTE2,LVD18_BYTE2 enable interrupt monitor" "0,1" newline bitfld.long 0x8 17. "LVD17_BYTE1,LVD17_BYTE1 enable interrupt monitor" "0,1" newline bitfld.long 0x8 15. "LVD15_BYTE3,LVD15_BYTE3 enable interrupt monitor" "0,1" newline bitfld.long 0x8 14. "LVD14_BYTE2,LVD14_BYTE2 enable interrupt monitor" "0,1" newline bitfld.long 0x8 11. "UVD11_BYTE3,UVD11_BYTE3 enable interrupt monitor" "0,1" newline bitfld.long 0x8 5. "LVD5_BYTE1,LVD5_BYTE1 enable interrupt monitor" "0,1" newline bitfld.long 0x8 3. "LVD3_BYTE3,LVD3_BYTE3 enable interrupt monitor" "0,1" newline bitfld.long 0x8 2. "LVD2_BYTE2,LVD2_BYTE2 enable interrupt monitor" "0,1" group.long 0x23C++0x3 line.long 0x0 "IE_G1,Interrupt Enable Pending G1 register" bitfld.long 0x0 31. "IE_EN,Interrupt Enable" "0: No interrupt enables can be written.,1: Any interrupt enable can be written." newline bitfld.long 0x0 30. "IRQ_EN,IRQ_EN user BIST enable interrupt monitor" "0,1" newline bitfld.long 0x0 7. "HVD39_BYTE3,HVD39_BYTE3 enable interrupt monitor" "0,1" newline bitfld.long 0x0 5. "LVD37_BYTE1,LVD37_BYTE1 enable interrupt monitor" "0,1" newline bitfld.long 0x0 3. "UVD35_BYTE3,UVD35_BYTE3 enable interrupt monitor" "0,1" rgroup.long 0x240++0x7 line.long 0x0 "EXTREG_S,Internal/External Regulator Status register" bitfld.long 0x0 4. "REG_MODE,This bit indicates internal or external regulator mode." "0: Internal regulator mode,1: External regulator mode" line.long 0x4 "HPREG_SMPS_SEL_S,HPREG SMPS Select Status register" bitfld.long 0x4 0. "SMPS_ENB,SMPS enable/disable status" "0: SMPS enabled,1: SMPS disabled" group.long 0x250++0x7 line.long 0x0 "CAPLESS_CTRL_AND_STATUS_REG,CAPLESS Control and Status Register" bitfld.long 0x0 17. "CLK_CLUSTER_CAPLESS_TRIM_READY,Power down control of clk cluster capless" "0: Capless trimming not done,1: Capless trimming done" newline bitfld.long 0x0 16. "SAR_ADC_CAPLESS_TRIM_READY,Power down control of SAR ADC cluster capless" "0: Capless trimming not done,1: Capless trimming done" newline bitfld.long 0x0 1. "CLK_CLUSTER_CAPLESS,Power down control of clk cluster capless" "0: Capless on,1: Capless off" newline bitfld.long 0x0 0. "SAR_ADC_CAPLESS,Power down control of SAR ADC cluster capless" "0: Capless on,1: Capless off" line.long 0x4 "CLK_CTRL_REG,Clock Control Register" bitfld.long 0x4 0. "RCOSC_1M_ENB,It enables/disables the RC OSC 1MHz clock." "0: RC OSC 1M clock is enabled,1: RC OSC 1M clock is disabled" rgroup.long 0x258++0x3 line.long 0x0 "FBB_TEMP_COMPENSATE_VALUE,FBB_TEMP_COMPENSATE_VALUE register" hexmask.long.byte 0x0 8.--12. 1. "FBB_PWELL_OFFSET,FBB pwell codes" newline hexmask.long.byte 0x0 0.--4. 1. "FBB_NWELL_CODE,FBB nwell codes" rgroup.long 0x260++0x3 line.long 0x0 "SMPS_LDO_CAPLESS_PD_STATUS,SMPS. LDO and Capless Power On/Off Status register" bitfld.long 0x0 5. "PCM_CAPLESS_PD,This bit indicates PCM capless on/off status." "0: PCM capless on,1: PCM capless off" newline bitfld.long 0x0 4. "CLK_CLUSTER_CAPLESS_PD,This bit indicates clk cluster capless on/off status." "0: clk cluster capless on,1: clk cluster capless off" newline bitfld.long 0x0 3. "SAR_ADC_CAPLESS_PD,This bit indicates SARADC capless on/off status." "0: SARADC capless on,1: SARADC capless off" newline bitfld.long 0x0 2. "LPREG_PD,This bit indicates LREG on/off status." "0: LPREG on,1: LPREG off" newline bitfld.long 0x0 1. "ULPREG_PD,This bit indicates ULREG on/off status." "0: ULPREG on,1: ULPREG off" newline bitfld.long 0x0 0. "SMPS_PD,This bit indicates SMPS on/off status." "0: SMPS on,1: SMPS off" group.long 0x264++0x3 line.long 0x0 "ED_STATUS,Emulation Domain Status register" bitfld.long 0x0 0. "ED_RAM_STATUS,The flag indicates whether ED RAM contents is valid or not." "0: ED RAM content is not valid,1: ED RAM content is valid" rgroup.long 0x268++0xF line.long 0x0 "SMPS_AND_LDO_TRIM_VALUE,SMPS. LDO Trim Values register" hexmask.long.byte 0x0 20.--24. 1. "LPREG_TRIM,This indicates the LPREG Trim Value." newline hexmask.long.byte 0x0 15.--19. 1. "ULPREG_TRIM,This indicates the ULPREG Trim Value." newline hexmask.long.byte 0x0 10.--14. 1. "PGATE_SLOPE_TRIM,This indicates the PGATE Slope Trim Value." newline hexmask.long.byte 0x0 5.--9. 1. "VLXRISE_DEADTIME_TRIM,This indicates the VLXRISE Deadtime Trim Value." newline hexmask.long.byte 0x0 0.--4. 1. "VLXFALL_DEADTIME_TRIM,This indicates the VLXFALL Deadtime Trim Value." line.long 0x4 "CAPLESS_TRIM_VALUE1,Capless Regulator Trim Value 1 register" hexmask.long.byte 0x4 15.--18. 1. "PMC_CAPLESS_LP_COARSE_TRIM,This indicates the PMC Capless LP Coarse Trim Value." newline hexmask.long.byte 0x4 10.--14. 1. "PMC_CAPLESS_LP_FINE_TRIM,This indicates the PMC Capless LP Fine Trim Value." newline hexmask.long.byte 0x4 5.--9. 1. "PMC_CAPLESS_ULP_COARSE_TRIM,This indicates the PMC Capless ULP Coarse Trim Value." newline hexmask.long.byte 0x4 0.--4. 1. "PMC_CAPLESS_ULP_FINE_TRIM,This indicates the PMC Capless ULP Fine Trim Value." line.long 0x8 "CAPLESS_TRIM_VALUE2,Capless Regulator Trim Value 2 register" hexmask.long.byte 0x8 25.--28. 1. "PCM_CAPLESS_COARSE_TRIM,This indicates the PCM Capless Coarse Trim Value." newline hexmask.long.byte 0x8 20.--24. 1. "PCM_CAPLESS_FINE_TRIM,This indicates the PCM Capless Fine Trim Value." newline hexmask.long.byte 0x8 15.--18. 1. "CLK_CLUSTER_CAPLESS_COARSE_TRIM,This indicates the CLK Cluster Capless Coarse Trim Value." newline hexmask.long.byte 0x8 10.--14. 1. "CLK_CLUSTER_CAPLESS_FINE_TRIM,This indicates the CLK Cluster Capless Fine Trim Value." newline hexmask.long.byte 0x8 5.--8. 1. "SAR_ADC_CAPLESS_COARSE_TRIM,This indicates the SARADC Capless Coarse Trim Value." newline hexmask.long.byte 0x8 0.--4. 1. "SAR_ADC_CAPLESS_FINE_TRIM,This indicates the SARADC Capless Fine Trim Value." line.long 0xC "CAPLESS_TRIM_VALUE3,Capless Regulator Trim Value 3 register" hexmask.long.byte 0xC 15.--18. 1. "SGMII1_COARSE_TRIM,This indicates the SGMII1 Capless Coarse Trim Value." newline hexmask.long.byte 0xC 10.--14. 1. "SGMII1_FINE_TRIM,This indicates the SGMII1 Capless Fine Trim Value." newline hexmask.long.byte 0xC 5.--8. 1. "SGMII_COARSE_TRIM,This indicates the SGMII Capless Coarse Trim Value." newline hexmask.long.byte 0xC 0.--4. 1. "SGMII_FINE_TRIM,This indicates the SGMII Capless Fine Trim Value." group.long 0x278++0x3 line.long 0x0 "VSIO,Voltage Selection of IO register" bitfld.long 0x0 6. "VSIO_LP,VSIO_LP" "0: Ring operates at 3.3V.,1: Ring operates at 5V." newline bitfld.long 0x0 5. "VSIO_IF1,VSIO_IF1" "0: Ring operates at 3.3V.,1: Ring operates at 5V." newline bitfld.long 0x0 4. "VSIO_IF0,VSIO_IF0" "0: Ring operates at 3.3V.,1: Ring operates at 5V." newline bitfld.long 0x0 3. "VSIO_ADC,VSIO_ADC" "0: Ring operates at 3.3V.,1: Ring operates at 5V." newline bitfld.long 0x0 0. "VSIO_IM,VSIO_IM" "0: Ring operates at 3.3V.,1: Ring operates at 5V." rgroup.long 0x280++0x3 line.long 0x0 "TEMP0_VALUE,Temperature Sensor 0 Value register" hexmask.long.word 0x0 16.--31. 1. "INACCURATE_TEMPERATURE,INACCURATE_TEMPERATURE" newline hexmask.long.word 0x0 0.--15. 1. "ACCURATE_TEMPERATURE,ACCURATE_TEMPERATURE" group.long 0x284++0xB line.long 0x0 "TEMP0_COMPARATOR0,Temperature 0 Comparator 0 register" bitfld.long 0x0 31. "FEE,FCCU Event Enable" "0: FCCU Event is disabled,1: FCCU Event is enabled" newline bitfld.long 0x0 30. "IEE,Interrupt Event Enable" "0: Interrupt Event is disabled,1: Interrupt Event is enabled" newline bitfld.long 0x0 29. "RES,Reset Event Selection" "0: Reset event trigger a destructive reset,1: Reset event trigger a functional reset" newline bitfld.long 0x0 28. "REE,Reset Event Enable" "0: Reset Event generation is disabled,1: Reset Event generation is enabled" newline bitfld.long 0x0 27. "GREATER_THAN_OR_LESS_THAN,GREATER_THAN_OR_LESS_THAN comparator selection" "0: Event is trigger when temperature is equal or..,1: Event is trigger when temperature is strictly.." newline hexmask.long.word 0x0 0.--15. 1. "THRESHOLD,THRESHOLD value of the temperature in 2 and apos;s compliment." line.long 0x4 "TEMP0_COMPARATOR1,Temperature 0 Comparator 1 register" bitfld.long 0x4 31. "FEE,FCCU Event Enable" "0: FCCU Event is disabled,1: FCCU Event is enabled" newline bitfld.long 0x4 30. "IEE,Interrupt Event Enable" "0: Interrupt Event is disabled,1: Interrupt Event is enabled" newline bitfld.long 0x4 29. "RES,Reset Event Selection" "0: Reset event trigger a destructive reset,1: Reset event trigger a functional reset" newline bitfld.long 0x4 28. "REE,Reset Event Enable" "0: Reset Event generation is disabled,1: Reset Event generation is enabled" newline bitfld.long 0x4 27. "GREATER_THAN_OR_LESS_THAN,GREATER_THAN_OR_LESS_THAN comparator selection" "0: Event is trigger when temperature is equal or..,1: Event is trigger when temperature is strictly.." newline hexmask.long.word 0x4 0.--15. 1. "THRESHOLD,THRESHOLD value of the temperature in 2 and apos;s compliment." line.long 0x8 "TEMP0_COMPARATOR2,Temperature 0 Comparator 2 register" bitfld.long 0x8 31. "FEE,FCCU Event Enable" "0: FCCU Event is disabled,1: FCCU Event is enabled" newline bitfld.long 0x8 30. "IEE,Interrupt Event Enable" "0: Interrupt Event is disabled,1: Interrupt Event is enabled" newline bitfld.long 0x8 29. "RES,Reset Event Selection" "0: Reset event trigger a destructive reset,1: Reset event trigger a functional reset" newline bitfld.long 0x8 28. "REE,Reset Event Enable" "0: Reset Event generation is disabled,1: Reset Event generation is enabled" newline bitfld.long 0x8 27. "GREATER_THAN_OR_LESS_THAN,GREATER_THAN_OR_LESS_THAN comparator selection" "0: Event is trigger when temperature is equal or..,1: Event is trigger when temperature is strictly.." newline hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,THRESHOLD value of the temperature in 2 and apos;s compliment." rgroup.long 0x2A0++0x3 line.long 0x0 "VREF0_VALUE,Voltage Reference 0 Value register" hexmask.long.word 0x0 0.--15. 1. "VOLTAGE_REFERENCE,Sensor 0 Voltage Reference value" group.long 0x2A4++0x3 line.long 0x0 "VREF0_COMPARATOR0,Voltage Reference 0 Comparator 0 register" bitfld.long 0x0 31. "FEE,FCCU Event Enable" "0: FCCU Event is disabled,1: FCCU Event is enabled" newline bitfld.long 0x0 30. "IEE,Interrupt Event Enable" "0: Interrupt Event is disabled,1: Interrupt Event is enabled" newline bitfld.long 0x0 29. "RES,Reset Event Selection" "0: Reset event trigger a destructive reset,1: Reset event trigger a functional reset" newline bitfld.long 0x0 28. "REE,Reset Event Enable" "0: Reset Event generation is disabled,1: Reset Event generation is enabled" newline bitfld.long 0x0 27. "GREATER_THAN_OR_LESS_THAN,GREATER_THAN_OR_LESS_THAN comparator selection" "0: Event is triggered when voltage is equal or..,1: Event is triggered when voltage is strictly.." newline hexmask.long.word 0x0 0.--15. 1. "THRESHOLD,THRESHOLD value" rgroup.long 0x2A8++0x3 line.long 0x0 "VREF1_VALUE,Voltage Reference 1 Value register" hexmask.long.word 0x0 0.--15. 1. "VOLTAGE_REFERENCE,Sensor 1 Voltage Reference value" group.long 0x2AC++0x3 line.long 0x0 "VREF1_COMPARATOR0,Voltage Reference 1 Comparator 0 register" bitfld.long 0x0 31. "FEE,FCCU Event Enable" "0: FCCU Event is disabled,1: FCCU Event is enabled" newline bitfld.long 0x0 30. "IEE,Interrupt Event Enable" "0: Interrupt Event is disabled,1: Interrupt Event is enabled" newline bitfld.long 0x0 29. "RES,Reset Event Selection" "0: Reset event trigger a destructive reset,1: Reset event trigger a functional reset" newline bitfld.long 0x0 28. "REE,Reset Event Enable" "0: Reset Event generation is disabled,1: Reset Event generation is enabled" newline bitfld.long 0x0 27. "GREATER_THAN_OR_LESS_THAN,GREATER_THAN_OR_LESS_THAN comparator selection" "0: Event is trigger when voltage is equal or below..,1: Event is trigger when voltage is strictly above.." newline hexmask.long.word 0x0 0.--15. 1. "THRESHOLD,THRESHOLD value" rgroup.long 0x2B0++0x3 line.long 0x0 "VREF2_VALUE,Voltage Reference 2 Value register" hexmask.long.word 0x0 0.--15. 1. "VOLTAGE_REFERENCE,Sensor 2 Voltage Reference value" group.long 0x2B4++0x3 line.long 0x0 "VREF2_COMPARATOR0,Voltage Reference 2 Comparator 0 register" bitfld.long 0x0 31. "FEE,FCCU Event Enable" "0: FCCU Event is disabled,1: FCCU Event is enabled" newline bitfld.long 0x0 30. "IEE,Interrupt Event Enable" "0: Interrupt Event is disabled,1: Interrupt Event is enabled" newline bitfld.long 0x0 29. "RES,Reset Event Selection" "0: Reset event trigger a destructive reset,1: Reset event trigger a functional reset" newline bitfld.long 0x0 28. "REE,Reset Event Enable" "0: Reset Event generation is disabled,1: Reset Event generation is enabled" newline bitfld.long 0x0 27. "GREATER_THAN_OR_LESS_THAN,GREATER_THAN_OR_LESS_THAN comparator selection" "0: Event is trigger when voltage is equal or below..,1: Event is trigger when voltage is strictly above.." newline hexmask.long.word 0x0 0.--15. 1. "THRESHOLD,THRESHOLD value" rgroup.long 0x2B8++0x3 line.long 0x0 "VREF3_VALUE,Voltage Reference 3 Value register" hexmask.long.word 0x0 0.--15. 1. "VOLTAGE_REFERENCE,Sensor 3 Voltage Reference value" group.long 0x2BC++0x3 line.long 0x0 "VREF3_COMPARATOR0,Voltage Reference 3 Comparator 0 register" bitfld.long 0x0 31. "FEE,FCCU Event Enable" "0: FCCU Event is disabled,1: FCCU Event is enabled" newline bitfld.long 0x0 30. "IEE,Interrupt Event Enable" "0: Interrupt Event is disabled,1: Interrupt Event is enabled" newline bitfld.long 0x0 29. "RES,Reset Event Selection" "0: Reset event trigger a destructive reset,1: Reset event trigger a functional reset" newline bitfld.long 0x0 28. "REE,Reset Event Enable" "0: Reset Event generation is disabled,1: Reset Event generation is enabled" newline bitfld.long 0x0 27. "GREATER_THAN_OR_LESS_THAN,GREATER_THAN_OR_LESS_THAN comparator selection" "0: Event is trigger when voltage is equal or below..,1: Event is trigger when voltage is strictly above.." newline hexmask.long.word 0x0 0.--15. 1. "THRESHOLD,THRESHOLD value" rgroup.long 0x2D0++0x7 line.long 0x0 "VTSENSE_PARAMETER,VTSENSE Parameter register" bitfld.long 0x0 19.--21. "ETA_CAL,ETA_CAL value" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 10.--18. 1. "B_IN,B_IN value" newline hexmask.long.word 0x0 0.--9. 1. "A_IN,A_IN value" line.long 0x4 "VTSENSE_CALIB_VALUE,VTSENSE Calibration register" hexmask.long.word 0x4 16.--24. 1. "CALIB_MODE_CALIB_VALUE,Calibration value obtained during calibration mode." newline hexmask.long.word 0x4 0.--8. 1. "DCF_CALIB_VALUE,Calibration value read from DCF." group.long 0x2D8++0xF line.long 0x0 "VTSENSE_STATUS,VTSENSE Status register" bitfld.long 0x0 31. "VREF3_PROBE_ERROR,VREF3_PROBE_ERROR" "0,1" newline bitfld.long 0x0 30. "VREF3_MODE_ERROR,VREF3_MODE_ERROR" "0,1" newline bitfld.long 0x0 29. "VREF3_OVERFLOW,Indicates overflow corresponding to Vref3." "0,1" newline bitfld.long 0x0 28. "EPR_VREF3,Indicates occurrence of Vref3 event" "0: Vref3 is within threshold,1: Vref3 threshold crossed" newline bitfld.long 0x0 27. "VREF2_PROBE_ERROR,VREF2_PROBE_ERROR" "0,1" newline bitfld.long 0x0 26. "VREF2_MODE_ERROR,VREF2_MODE_ERROR" "0,1" newline bitfld.long 0x0 25. "VREF2_OVERFLOW,Indicates overflow corresponding to Vref2." "0,1" newline bitfld.long 0x0 24. "EPR_VREF2,Indicates occurrence of Vref2 event" "0: Vref2 is within threshold,1: Vref2 threshold crossed" newline bitfld.long 0x0 23. "VREF1_PROBE_ERROR,VREF1_PROBE_ERROR" "0,1" newline bitfld.long 0x0 22. "VREF1_MODE_ERROR,VREF1_MODE_ERROR" "0,1" newline bitfld.long 0x0 21. "VREF1_OVERFLOW,Indicates overflow corresponding to Vref1." "0,1" newline bitfld.long 0x0 20. "EPR_VREF1,Indicates occurrence of Vref1 event" "0: Vref1 is within threshold,1: Vref1 threshold crossed" newline bitfld.long 0x0 19. "VREF0_PROBE_ERROR,VREF0_PROBE_ERROR" "0,1" newline bitfld.long 0x0 18. "VREF0_MODE_ERROR,VREF0_MODE_ERROR" "0,1" newline bitfld.long 0x0 17. "VREF0_OVERFLOW,VREF0_OVERFLOW" "0,1" newline bitfld.long 0x0 16. "EPR_VREF0,EPR_VREF0" "0: Vref0 is within threshold,1: Vref0 threshold crossed" newline bitfld.long 0x0 15. "TEMP0_MODE_ERROR,TEMP0_MODE_ERROR" "0,1" newline bitfld.long 0x0 14. "TEMP0_OVERFLOW,TEMP0_OVERFLOW" "0,1" newline bitfld.long 0x0 13. "EPR_TEMP0_COMPARATOR2,EPR_TEMP0_COMPARATOR2" "0,1" newline bitfld.long 0x0 12. "EPR_TEMP0_COMPARATOR1,EPR_TEMP0_COMPARATOR1" "0,1" newline bitfld.long 0x0 11. "EPR_TEMP0_COMPARATOR0,EPR_TEMP0_COMPARATOR0" "0,1" newline bitfld.long 0x0 8. "FD_OUT_FLAG,Fail Detect Status" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "NEXT_STATE,Next state of VTsense" newline hexmask.long.byte 0x0 0.--3. 1. "CURRENT_STATE,Present state of VTsense" line.long 0x4 "VTSENSE_CONFIG,VTSENSE Configuration register" bitfld.long 0x4 24. "FAIL_DETECT,To check fail detect state" "0: Fail detect state check disable,1: Fail detect state check enable" newline bitfld.long 0x4 20. "STANDBY,Standby state triggering" "0: Standby state disable,1: Standby state enable" newline bitfld.long 0x4 16. "VREF3_CAL,Enabling for measuring of remote ADC reference voltage between 4V to 6V" "0: Vref3 measurement disable,1: Vref3 measurement enable" newline bitfld.long 0x4 12. "VREF2_CAL,Enabling for measuring of remote ADC reference voltage between 2.7V to 4V" "0: Vref2 measurement disable,1: Vref2 measurement enable" newline bitfld.long 0x4 8. "VREF1_CAL,Enabling for measuring of remote low voltage" "0: Vref1 measurement disable,1: Vref1 measurement enable" newline bitfld.long 0x4 4. "VREF0_CAL,Enabling for measuring of local low voltage" "0,1" newline bitfld.long 0x4 0. "TEMP0_CAL,Temperature Measurement" "0,1" line.long 0x8 "VTSENSE_STBY_TIME,Standby Duration register" hexmask.long 0x8 0.--31. 1. "STANDBY_DURATION,Standby duration value." line.long 0xC "VTSENSE_STATE_REPEAT_COUNT,VTsense State Repeat Count register" hexmask.long.byte 0xC 16.--19. 1. "VREF3_STATE,Voltage measurement state is repeated based upon the value. If the value is \q0\q voltage is measured once and then it moves to the next state. If the value is \q15\q voltage is measured 16 times and then it moves to the next state." newline hexmask.long.byte 0xC 12.--15. 1. "VREF2_STATE,Voltage measurement state is repeated based upon the value. If the value is \q0\q voltage is measured once and then it moves to the next state. If the value is \q15\q voltage is measured 16 times and then it moves to the next state." newline hexmask.long.byte 0xC 8.--11. 1. "VREF1_STATE,Voltage measurement state is repeated based upon the value. If the value is \q0\q voltage is measured once and then it moves to the next state. If the value is \q15\q voltage is measured 16 times and then it moves to the next state." newline hexmask.long.byte 0xC 4.--7. 1. "VREF0_STATE,Voltage measurement state is repeated based upon the value. If the value is \q0\q voltage is measured once and then it moves to the next state. If the value is \q15\q voltage is measured 16 times and then it moves to the next state." newline hexmask.long.byte 0xC 0.--3. 1. "TEMP0_STATE,Temperature measurement state is repeated based upon the value. If the value is \q0\q temperature is measured once and then it moves to the next state. If the value is \q15\q temperature is measured 16 times and then it moves to the next state." group.long 0x2EC++0x13 line.long 0x0 "EPR_TEMP,Event Pending Temperature register" bitfld.long 0x0 2. "TEMP_2,TEMP_2 flag." "0: Currently no occurrence,1: Temperature occurrence detected" newline bitfld.long 0x0 1. "TEMP_1,TEMP_1 flag." "0: Currently no occurrence,1: Temperature occurrence detected" newline bitfld.long 0x0 0. "TEMP_0,TEMP_0 flag." "0: Currently no occurrence,1: Temperature occurrence detected" line.long 0x4 "REE_TEMP,Reset Event Enable Temperature register" bitfld.long 0x4 2. "TEMP_2,TEMP_2 flag." "0: Temperature Sensor 2 Reset event Disable,1: Temperature Sensor 2 Reset event Enable" newline bitfld.long 0x4 1. "TEMP_1,TEMP_1 flag." "0: Temperature Sensor 1 Reset event Disable,1: Temperature Sensor 1 Reset event Enable" newline bitfld.long 0x4 0. "TEMP_0,TEMP_0 flag." "0: Temperature Sensor 0 Reset event Disable,1: Temperature Sensor 0 Reset event Enable" line.long 0x8 "RES_TEMP,Reset Event Select Temperature register" bitfld.long 0x8 2. "TEMP_2,TEMP_2 flag." "0: Temperature Sensor 2 destructive reset is..,1: Temperature Sensor 2 functional reset is generated" newline bitfld.long 0x8 1. "TEMP_1,TEMP_1 flag." "0: Temperature Sensor 1 destructive reset is..,1: Temperature Sensor 1 functional reset is generated" newline bitfld.long 0x8 0. "TEMP_0,TEMP_0 flag." "0: Temperature Sensor 0 destructive reset is..,1: Temperature Sensor 0 functional reset is generated" line.long 0xC "CTL_TEMP,Control Temperature register" bitfld.long 0xC 20. "PMC_AOUT_EN,Temperature Sensor Enable for PMU" "0: Temperature threshold detector disable,1: Temperature threshold detector enable" newline hexmask.long.byte 0xC 16.--19. 1. "TRIM_ADJ_OVER1,Customer adjustable over trim register for PMU" newline bitfld.long 0xC 15. "IEE_TEMP2,This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. The MSB in IE_G0 must be set to access this bit." "0,1" newline bitfld.long 0xC 14. "IEE_TEMP1,This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. The MSB in IE_G0 must be set to access this bit." "0,1" newline bitfld.long 0xC 13. "IEE_TEMP0,This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. The MSB in IE_G0 must be set to access this bit." "0,1" newline hexmask.long.byte 0xC 8.--11. 1. "TRIM_ADJ_OVER,Customer adjustable over trim register" newline hexmask.long.byte 0xC 2.--5. 1. "TRIM_ADJ_UNDER,Customer adjustable under trim register" line.long 0x10 "FEE_TEMP,FCCU Event Enable Temperature register" bitfld.long 0x10 2. "TEMP_2,TEMP_2 flag" "0: Temperature Sensor 2 FCCU fault Disable,1: Temperature Sensor 2 FCCU fault Enable" newline bitfld.long 0x10 1. "TEMP_1,TEMP_1 flag" "0: Temperature Sensor 1 FCCU fault Disable,1: Temperature Sensor 1 FCCU fault Enable" newline bitfld.long 0x10 0. "TEMP_0,TEMP_0 flag" "0: Temperature Sensor 0 FCCU fault Disable,1: Temperature Sensor 0 FCCU fault Enable" rgroup.long 0x300++0x1B line.long 0x0 "BIST_MASK_STATUS_LV0,BIST Mask Status LV0 register" bitfld.long 0x0 27. "LVD3_TD,LVD3_TD" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x0 18. "LVD2_C_MD,LVD2_C_MD" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x0 17. "LVD2_C_LP,LVD2_C_LP" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x0 2. "MVD0_C_MD,MVD0_C_MD" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x0 1. "MVD0_C_LP,MVD0_C_LP" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x0 0. "MVD0_C_ULP,MVD0_C_ULP" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" line.long 0x4 "BIST_MASK_STATUS_LV1,BIST Mask Status LV1 register" bitfld.long 0x4 15. "LVD5_ED,Note: Avoid reading this register while PMC BIST is running. It always shows status as 1. After destructive reset it comes again to reset value." "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" line.long 0x8 "BIST_MASK_STATUS_LV2,BIST Mask Status LV2 register" bitfld.long 0x8 24. "UVD11_C_MD,UVD11_C_MD" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x8 18. "UVD10_C_MD,UVD10_C_MD" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x8 16. "UVD10_C_ULP,UVD10_C_ULP" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" line.long 0xC "BIST_MASK_STATUS_HV0,BIST Mask Status HV0 register" bitfld.long 0xC 30. "LVD15_A,LVD15_A" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0xC 28. "LVD15_S,LVD15_S" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0xC 18. "LVD14_C_MD,LVD14_C_MD" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0xC 16. "LVD14_C,LVD14_C" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0xC 12. "MVD13_S,MVD13_S" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0xC 2. "MVD12_C_MD,MVD12_C_MD" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0xC 0. "MVD12_C,MVD12_C" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" line.long 0x10 "BIST_MASK_STATUS_HV1,BIST Mask Status HV1 register" bitfld.long 0x10 30. "LVD19_A,LVD19_A" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x10 29. "LVD19_S1,LVD19_S1" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x10 28. "LVD19_S0,LVD19_S0" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x10 26. "LVD19_NP,LVD19_NP" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x10 18. "LVD18_C_MD,LVD18_C_MD" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x10 14. "LVD17_IX1,LVD17_IX1" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x10 13. "LVD17_IX0,LVD17_IX0" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" line.long 0x14 "BIST_MASK_STATUS_HV2,BIST Mask Status HV2 register" bitfld.long 0x14 30. "UVD23_A,UVD23_A" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x14 28. "UVD23_S,UVD23_S" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x14 18. "UVD22_C_MD,UVD22_C_MD" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x14 16. "UVD22_C,UVD22_C" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x14 14. "HVD21_IX1,HVD21_IX1" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x14 13. "HVD21_IX0,HVD21_IX0" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x14 2. "HVD20_C_MD,HVD20_C_MD" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" line.long 0x18 "BIST_MASK_STATUS_MV0,BIST Mask Status MV0 register" bitfld.long 0x18 31. "LVD29_Y,LVD29_Y" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x18 30. "LVD29_A,LVD29_A" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x18 26. "LVD29_N,LVD29_N" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x18 25. "LVD29_P,LVD29_P" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x18 17. "LVD26_C_LP,LVD26_C_LP" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x18 16. "LVD26_C_ULP,LVD26_C_ULP" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" rgroup.long 0x320++0x7 line.long 0x0 "BIST_MASK_STATUS_MV2,BIST Mask Status MV2 register" bitfld.long 0x0 31. "UVD35_Y,UVD35_Y" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x0 30. "UVD35_A,UVD35_A" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x0 26. "UVD35_N,UVD35_N" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x0 25. "UVD35_P,UVD35_P" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x0 17. "UVD34_C_LP,UVD34_C_LP" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x0 16. "UVD34_C_ULP,UVD34_C_ULP" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" line.long 0x4 "BIST_MASK_STATUS_BV,BIST Mask Status BV register" bitfld.long 0x4 28. "HVD39_FB,HVD39_FB" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" newline bitfld.long 0x4 8. "LVD37_FB,LVD37_FB" "0: Monitor bist is not running hence not masked,1: Monitor bist is running hence masked" group.long 0x328++0x1B line.long 0x0 "BIST_RUN_EN_LV0,BIST Run Enable LV0 register" bitfld.long 0x0 27. "LVD3_TD,LVD3_TD" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x0 18. "LVD2_C_MD,LVD2_C_MD" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x0 17. "LVD2_C_LP,LVD2_C_LP" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x0 2. "MVD0_C_MD,MVD0_C_MD" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x0 1. "MVD0_C_LP,MVD0_C_LP" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x0 0. "MVD0_C_ULP,MVD0_C_ULP" "0: BIST run disabled,1: BIST run enabled" line.long 0x4 "BIST_RUN_EN_LV1,BIST Run Enable LV1 register" bitfld.long 0x4 15. "LVD5_ED,LVD5_ED" "0: BIST run disabled,1: BIST run enabled" line.long 0x8 "BIST_RUN_EN_LV2,BIST Run Enable LV2 register" bitfld.long 0x8 24. "UVD11_C_MD,UVD11_C_MD" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x8 18. "UVD10_C_MD,UVD10_C_MD" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x8 16. "UVD10_C_ULP,UVD10_C_ULP" "0: BIST run disabled,1: BIST run enabled" line.long 0xC "BIST_RUN_EN_HV0,BIST Run Enable HV0 register" bitfld.long 0xC 30. "LVD15_A,LVD15_A" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0xC 28. "LVD15_S,LVD15_S" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0xC 18. "LVD14_C_MD,LVD14_C_MD" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0xC 16. "LVD14_C,LVD14_C" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0xC 12. "MVD13_S,MVD13_S" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0xC 2. "MVD12_C_MD,MVD12_C_MD" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0xC 0. "MVD12_C,MVD12_C" "0: BIST run disabled,1: BIST run enabled" line.long 0x10 "BIST_RUN_EN_HV1,BIST Run Enable HV1 register" bitfld.long 0x10 30. "LVD19_A,LVD19_A" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x10 29. "LVD19_S1,LVD19_S1" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x10 28. "LVD19_S0,LVD19_S0" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x10 26. "LVD19_NP,LVD19_NP" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x10 18. "LVD18_C_MD,LVD18_C_MD" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x10 14. "LVD17_IX1,LVD17_IX1" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x10 13. "LVD17_IX0,LVD17_IX0" "0: BIST run disabled,1: BIST run enabled" line.long 0x14 "BIST_RUN_EN_HV2,BIST Run Enable HV2 register" bitfld.long 0x14 30. "UVD23_A,UVD23_A" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x14 28. "UVD23_S,UVD23_S" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x14 18. "UVD22_C_MD,UVD22_C_MD" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x14 16. "UVD22_C,UVD22_C" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x14 14. "HVD21_IX1,HVD21_IX1" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x14 13. "HVD21_IX0,HVD21_IX0" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x14 2. "HVD20_C_MD,HVD20_C_MD" "0: BIST run disabled,1: BIST run enabled" line.long 0x18 "BIST_RUN_EN_MV0,BIST Run Enable MV0 register" bitfld.long 0x18 31. "LVD29_Y,LVD29_Y" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x18 30. "LVD29_A,LVD29_A" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x18 26. "LVD29_N,LVD29_N" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x18 25. "LVD29_P,LVD29_P" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x18 17. "LVD26_C_LP,LVD26_C_LP" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x18 16. "LVD26_C_ULP,LVD26_C_ULP" "0: BIST run disabled,1: BIST run enabled" group.long 0x348++0x7 line.long 0x0 "BIST_RUN_EN_MV2,BIST Run Enable MV2 register" bitfld.long 0x0 31. "UVD35_Y,UVD35_Y" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x0 30. "UVD35_A,UVD35_A" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x0 26. "UVD35_N,UVD35_N" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x0 25. "UVD35_P,UVD35_P" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x0 17. "UVD34_C_LP,UVD34_C_LP" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x0 16. "UVD34_C_ULP,UVD34_C_ULP" "0: BIST run disabled,1: BIST run enabled" line.long 0x4 "BIST_RUN_EN_BV,BIST Run Enable BV register" bitfld.long 0x4 28. "HVD39_FB,HVD39_FB" "0: BIST run disabled,1: BIST run enabled" newline bitfld.long 0x4 8. "LVD37_FB,LVD37_FB" "0: BIST run disabled,1: BIST run enabled" rgroup.long 0x350++0x37 line.long 0x0 "BIST_FLAGS_PHASE1_LV0,User BIST Flags Phase1 LV0 register" bitfld.long 0x0 27. "LVD3_TD,LVD3_TD user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x0 18. "LVD2_C_MD,LVD2_C_MD user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x0 17. "LVD2_C_LP,LVD2_C_LP user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x0 2. "MVD0_C_MD,MVD0_C_MD user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x0 1. "MVD0_C_LP,MVD0_C_LP user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x0 0. "MVD0_C_ULP,MVD0_C_ULP user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" line.long 0x4 "BIST_FLAGS_PHASE2_LV0,User BIST Flags Phase2 LV0 register" bitfld.long 0x4 27. "LVD3_TD,LVD3_TD user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x4 18. "LVD2_C_MD,LVD2_C_MD user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x4 17. "LVD2_C_LP,LVD2_C_LP user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x4 2. "MVD0_C_MD,MVD0_C_MD user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x4 1. "MVD0_C_LP,MVD0_C_LP user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x4 0. "MVD0_C_ULP,MVD0_C_ULP user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" line.long 0x8 "BIST_FLAGS_PHASE1_LV1,User BIST Flags Phase1 LV1 register" bitfld.long 0x8 15. "LVD5_ED,LVD5_ED user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" line.long 0xC "BIST_FLAGS_PHASE2_LV1,User BIST Flags Phase2 LV1 register" bitfld.long 0xC 15. "LVD5_ED,LVD5_ED user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" line.long 0x10 "BIST_FLAGS_PHASE1_LV2,User BIST Flags Phase1 LV2 register" bitfld.long 0x10 24. "UVD11_C_MD,UVD11_C_MD user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x10 18. "UVD10_C_MD,UVD10_C_MD user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x10 16. "UVD10_C_ULP,UVD10_C_ULP user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" line.long 0x14 "BIST_FLAGS_PHASE2_LV2,User BIST Flags Phase2 LV2 register" bitfld.long 0x14 24. "UVD11_C_MD,UVD11_C_MD user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x14 18. "UVD10_C_MD,UVD10_C_MD user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x14 16. "UVD10_C_ULP,UVD10_C_ULP user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" line.long 0x18 "BIST_FLAGS_PHASE1_HV0,User BIST Flags Phase1 HV0 register" bitfld.long 0x18 30. "LVD15_A,LVD15_A user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x18 28. "LVD15_S,LVD15_S user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x18 18. "LVD14_C_MD,LVD14_C_MD user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x18 16. "LVD14_C,LVD14_C user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x18 12. "MVD13_S,MVD13_S user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x18 2. "MVD12_C_MD,MVD12_C_MD user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x18 0. "MVD12_C,MVD12_C user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" line.long 0x1C "BIST_FLAGS_PHASE2_HV0,User BIST Flags Phase2 HV0 register" bitfld.long 0x1C 30. "LVD15_A,LVD15_A user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x1C 28. "LVD15_S,LVD15_S user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x1C 18. "LVD14_C_MD,LVD14_C_MD user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x1C 16. "LVD14_C,LVD14_C user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x1C 12. "MVD13_S,MVD13_S user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x1C 2. "MVD12_C_MD,MVD12_C_MD user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x1C 0. "MVD12_C,MVD12_C user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" line.long 0x20 "BIST_FLAGS_PHASE1_HV1,User BIST Flags Phase1 HV1 register" bitfld.long 0x20 30. "LVD19_A,LVD19_A user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x20 29. "LVD19_S1,LVD19_S1 user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x20 28. "LVD19_S0,LVD19_S0 user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x20 26. "LVD19_NP,LVD19_NP user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x20 18. "LVD18_C_MD,LVD18_C_MD user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x20 14. "LVD17_IX1,LVD17_IX1 user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x20 13. "LVD17_IX0,LVD17_IX0 user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" line.long 0x24 "BIST_FLAGS_PHASE2_HV1,User BIST Flags Phase2 HV1 register" bitfld.long 0x24 30. "LVD19_A,LVD19_A user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x24 29. "LVD19_S1,LVD19_S1 user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x24 28. "LVD19_S0,LVD19_S0 user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x24 26. "LVD19_NP,LVD19_NP user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x24 18. "LVD18_C_MD,LVD18_C_MD user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x24 14. "LVD17_IX1,LVD17_IX1 user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x24 13. "LVD17_IX0,LVD17_IX0 user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" line.long 0x28 "BIST_FLAGS_PHASE1_HV2,User BIST Flags Phase1 HV2 register" bitfld.long 0x28 30. "UVD23_A,UVD23_A user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x28 28. "UVD23_S,UVD23_S user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x28 18. "UVD22_C_MD,UVD22_C_MD user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x28 16. "UVD22_C,UVD22_C user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x28 14. "HVD21_IX1,HVD21_IX1 user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x28 13. "HVD21_IX0,HVD21_IX0 user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x28 2. "HVD20_C_MD,HVD20_C_MD user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" line.long 0x2C "BIST_FLAGS_PHASE2_HV2,User BIST Flags Phase2 HV2 register" bitfld.long 0x2C 30. "UVD23_A,UVD23_A user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x2C 28. "UVD23_S,UVD23_S user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x2C 18. "UVD22_C_MD,UVD22_C_MD user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x2C 16. "UVD22_C,UVD22_C user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x2C 14. "HVD21_IX1,HVD21_IX1 user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x2C 13. "HVD21_IX0,HVD21_IX0 user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x2C 2. "HVD20_C_MD,HVD20_C_MD user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" line.long 0x30 "BIST_FLAGS_PHASE1_MV0,User BIST Flags Phase1 MV0 register" bitfld.long 0x30 31. "LVD29_Y,LVD29_Y user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x30 30. "LVD29_A,LVD29_A user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x30 26. "LVD29_N,LVD29_N user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x30 25. "LVD29_P,LVD29_P user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x30 17. "LVD26_C_LP,LVD26_C_LP user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x30 16. "LVD26_C_ULP,LVD26_C_ULP user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" line.long 0x34 "BIST_FLAGS_PHASE2_MV0,User BIST Flags Phase2 MV0 register" bitfld.long 0x34 31. "LVD29_Y,LVD29_Y user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x34 30. "LVD29_A,LVD29_A user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x34 26. "LVD29_N,LVD29_N user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x34 25. "LVD29_P,LVD29_P user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x34 17. "LVD26_C_LP,LVD26_C_LP user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x34 16. "LVD26_C_ULP,LVD26_C_ULP user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" rgroup.long 0x390++0xF line.long 0x0 "BIST_FLAGS_PHASE1_MV2,User BIST Flags Phase1 MV2 register" bitfld.long 0x0 31. "UVD35_Y,UVD35_Y user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x0 30. "UVD35_A,UVD35_A user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x0 26. "UVD35_N,UVD35_N user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x0 25. "UVD35_P,UVD35_P user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x0 17. "UVD34_C_LP,UVD34_C_LP user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x0 16. "UVD34_C_ULP,UVD34_C_ULP user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" line.long 0x4 "BIST_FLAGS_PHASE2_MV2,User BIST Flags Phase2 MV2 register" bitfld.long 0x4 31. "UVD35_Y,UVD35_Y user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x4 30. "UVD35_A,UVD35_A user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x4 26. "UVD35_N,UVD35_N user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x4 25. "UVD35_P,UVD35_P user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x4 17. "UVD34_C_LP,UVD34_C_LP user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0x4 16. "UVD34_C_ULP,UVD34_C_ULP user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" line.long 0x8 "BIST_FLAGS_PHASE1_BV,User BIST Flags Phase1 BV register" bitfld.long 0x8 28. "HVD39_FB,HVD39_FB user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" newline bitfld.long 0x8 8. "LVD37_FB,LVD37_FB user BIST flag" "0: Monitor tripped condition OK,1: Monitor tripped condition not OK" line.long 0xC "BIST_FLAGS_PHASE2_BV,User BIST Flags Phase2 BV register" bitfld.long 0xC 28. "HVD39_FB,HVD39_FB user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" newline bitfld.long 0xC 8. "LVD37_FB,LVD37_FB user BIST flag" "0: Monitor lifted condition not OK,1: Monitor lifted condition OK" group.long 0x3D4++0xF line.long 0x0 "BIST_CTRL,User BIST Control register" bitfld.long 0x0 20. "IRQST,IRQST is the Interrupt reQuest pending STatus bit to generate a User BIST Interrupt. It is a R/W0 register. That means Set by HW and Cleared by SW. The destructive reset resets this bit." "0: No interrupt occurred,1: An interrupt occurred" newline bitfld.long 0x0 16. "IRQEN,IRQEN is the Interrupt reQuest ENable bit to permit a User BIST Interrupt. It is a R/W register. The destructive reset resets this bit." "0: Interrupt is disabled,1: Interrupt enabled" newline bitfld.long 0x0 12. "NCFST,NCFST is the Not Critical Fault bit. The assertion of this bit generates FCCU event once user BIST fails. It is set by HW and Cleared by SW. The destructive reset resets this bit." "0: No User BIST NCF occurred,1: A User BIST NCF occurred" newline bitfld.long 0x0 8. "NCFEN,NCFEN is the Not Critical Fault Enable bit to permit a User BIST Not Critical Fault. It is a R/W register. The destructive reset resets these bits." "0: No User BIST NCF enabled,1: A User BIST NCF enabled" newline bitfld.long 0x0 4.--6. "STATUS,STATUS is a three read-only bit bitfield that according to the value has a own meaning." "0: BIST_IDLE,1: BIST_RUN,2: BIST_PASSED,3: BIST_FAILED,4: BIST_ABORT,?,?,?" newline bitfld.long 0x0 0. "START,START User BIST bit. If set by SW a 1 is present in the START bit for a System clock cycle only then the START bit register is clear by HW. The destructive reset resets this bit." "0: No start pulse.,1: A start pulse occurs of a 1 System clock cycle.." line.long 0x4 "BIST_TIME10,User BIST Time1 and Time0 register" hexmask.long.word 0x4 16.--28. 1. "TIME_1,TIME_1 is the IRC clock cycles number required by the TIMER 1 in the User BIST management. The destructive reset resets these bits." newline hexmask.long.word 0x4 0.--12. 1. "TIME_0,TIME_0 is the IRC clock cycles number required by the TIMER 0 in the User BIST management. The destructive reset resets these bits." line.long 0x8 "BIST_TIME32,User BIST Time3 and Time2 register" hexmask.long.word 0x8 16.--28. 1. "TIME_3,TIME_3 is the IRC clock cycles number required by the TIMER 3 in the User BIST management. The destructive reset resets these bits." newline hexmask.long.word 0x8 0.--12. 1. "TIME_2,TIME_2 is the IRC clock cycles number required by the TIMER 2 in the User BIST management. The destructive reset resets these bits." line.long 0xC "BIST_TIME65,User BIST Time6 and Time5 register" hexmask.long.word 0xC 16.--28. 1. "TIME_6,TIME_6 is the IRC clock cycles number required by the TIMER 6 in the User BIST management. The destructive reset resets these bits." newline hexmask.long.word 0xC 0.--12. 1. "TIME_5,TIME_6 is the IRC clock cycles number required by the TIMER 6 in the User BIST management. The destructive reset resets these bits." rgroup.long 0x3E4++0x3 line.long 0x0 "BIST_DEBUG,User BIST VD Under Test Monitor register" hexmask.long.byte 0x0 0.--6. 1. "VD_MON,The seven read only bits of field VD_MON give the current VD Under Test of the User BIST unit among 45 VDs available according to the following values:" tree.end tree.end tree "PRAM (Platform RAM Controller)" base ad:0x0 tree "PRAM_0" base ad:0x71198000 group.long 0x0++0x7 line.long 0x0 "CR,Platform RAM controller Configuration Register" bitfld.long 0x0 4. "WWS_EN,Wait State Enable for writes" "0: No extra wait state for Write operations,1: One extra wait state for Write operations" bitfld.long 0x0 3. "MEMACC_WAIT,Wait State Enable for ECC for RMW operations" "0: No extra wait state for RMW operations.,1: One extra wait state for RMW operations." newline bitfld.long 0x0 2. "RWS_EN,Wait State Enable for high memory access time" "0: RAM read takes 1 cycle.,1: RAM read takes 2 cycles." bitfld.long 0x0 1. "FIXED_BURST_EN,Fixed Burst Enable" "0: Fixed burst not supported. PRAMC will signal..,1: Fixed burst is supported by PRAMC." line.long 0x4 "MEM_SCRB,Platform RAM controller Memory Scrubbing" bitfld.long 0x4 31. "SCRB_STATUS,Error Repair Status" "0: Memory Scrubbing on RAM location is complete.,1: Memory Scrubbing on RAM location is pending." hexmask.long 0x4 0.--28. 1. "SCRB_ADDR,Memory Scrubbing Address" tree.end tree "PRAM_1" base ad:0x71798000 group.long 0x0++0x7 line.long 0x0 "CR,Platform RAM controller Configuration Register" bitfld.long 0x0 4. "WWS_EN,Wait State Enable for writes" "0: No extra wait state for Write operations,1: One extra wait state for Write operations" bitfld.long 0x0 3. "MEMACC_WAIT,Wait State Enable for ECC for RMW operations" "0: No extra wait state for RMW operations.,1: One extra wait state for RMW operations." newline bitfld.long 0x0 2. "RWS_EN,Wait State Enable for high memory access time" "0: RAM read takes 1 cycle.,1: RAM read takes 2 cycles." bitfld.long 0x0 1. "FIXED_BURST_EN,Fixed Burst Enable" "0: Fixed burst not supported. PRAMC will signal..,1: Fixed burst is supported by PRAMC." line.long 0x4 "MEM_SCRB,Platform RAM controller Memory Scrubbing" bitfld.long 0x4 31. "SCRB_STATUS,Error Repair Status" "0: Memory Scrubbing on RAM location is complete.,1: Memory Scrubbing on RAM location is pending." hexmask.long 0x4 0.--28. 1. "SCRB_ADDR,Memory Scrubbing Address" tree.end tree "PRAM_2" base ad:0x7119C000 group.long 0x0++0x7 line.long 0x0 "CR,Platform RAM controller Configuration Register" bitfld.long 0x0 4. "WWS_EN,Wait State Enable for writes" "0: No extra wait state for Write operations,1: One extra wait state for Write operations" bitfld.long 0x0 3. "MEMACC_WAIT,Wait State Enable for ECC for RMW operations" "0: No extra wait state for RMW operations.,1: One extra wait state for RMW operations." newline bitfld.long 0x0 2. "RWS_EN,Wait State Enable for high memory access time" "0: RAM read takes 1 cycle.,1: RAM read takes 2 cycles." bitfld.long 0x0 1. "FIXED_BURST_EN,Fixed Burst Enable" "0: Fixed burst not supported. PRAMC will signal..,1: Fixed burst is supported by PRAMC." line.long 0x4 "MEM_SCRB,Platform RAM controller Memory Scrubbing" bitfld.long 0x4 31. "SCRB_STATUS,Error Repair Status" "0: Memory Scrubbing on RAM location is complete.,1: Memory Scrubbing on RAM location is pending." hexmask.long 0x4 0.--28. 1. "SCRB_ADDR,Memory Scrubbing Address" tree.end tree "PRAM_3" base ad:0x7179C000 group.long 0x0++0x7 line.long 0x0 "CR,Platform RAM controller Configuration Register" bitfld.long 0x0 4. "WWS_EN,Wait State Enable for writes" "0: No extra wait state for Write operations,1: One extra wait state for Write operations" bitfld.long 0x0 3. "MEMACC_WAIT,Wait State Enable for ECC for RMW operations" "0: No extra wait state for RMW operations.,1: One extra wait state for RMW operations." newline bitfld.long 0x0 2. "RWS_EN,Wait State Enable for high memory access time" "0: RAM read takes 1 cycle.,1: RAM read takes 2 cycles." bitfld.long 0x0 1. "FIXED_BURST_EN,Fixed Burst Enable" "0: Fixed burst not supported. PRAMC will signal..,1: Fixed burst is supported by PRAMC." line.long 0x4 "MEM_SCRB,Platform RAM controller Memory Scrubbing" bitfld.long 0x4 31. "SCRB_STATUS,Error Repair Status" "0: Memory Scrubbing on RAM location is complete.,1: Memory Scrubbing on RAM location is pending." hexmask.long 0x4 0.--28. 1. "SCRB_ADDR,Memory Scrubbing Address" tree.end tree "PRAM_4" base ad:0x711A0000 group.long 0x0++0x7 line.long 0x0 "CR,Platform RAM controller Configuration Register" bitfld.long 0x0 4. "WWS_EN,Wait State Enable for writes" "0: No extra wait state for Write operations,1: One extra wait state for Write operations" bitfld.long 0x0 3. "MEMACC_WAIT,Wait State Enable for ECC for RMW operations" "0: No extra wait state for RMW operations.,1: One extra wait state for RMW operations." newline bitfld.long 0x0 2. "RWS_EN,Wait State Enable for high memory access time" "0: RAM read takes 1 cycle.,1: RAM read takes 2 cycles." bitfld.long 0x0 1. "FIXED_BURST_EN,Fixed Burst Enable" "0: Fixed burst not supported. PRAMC will signal..,1: Fixed burst is supported by PRAMC." line.long 0x4 "MEM_SCRB,Platform RAM controller Memory Scrubbing" bitfld.long 0x4 31. "SCRB_STATUS,Error Repair Status" "0: Memory Scrubbing on RAM location is complete.,1: Memory Scrubbing on RAM location is pending." hexmask.long 0x4 0.--28. 1. "SCRB_ADDR,Memory Scrubbing Address" tree.end tree "PRAM_5" base ad:0x723A0000 group.long 0x0++0x3 line.long 0x0 "PRCR1,Platform RAM configuration register 1" bitfld.long 0x0 9. "PRI1,Not used since port 1 is not used. This bit can be written by software." "0,1" bitfld.long 0x0 8. "PRI0,Not used since port 1 is not used. This bit can be written by software." "0,1" bitfld.long 0x0 7. "P1_BO_DIS,Not used since port 1 is not used. This bit can be written by software." "0,1" bitfld.long 0x0 6. "P0_BO_DIS,Port p0 read burst optimization disable" "0: 32-bit WRP4 read bursts are optimized such that..,1: 32-bit WRP4 read bursts are not optimized; the.." newline bitfld.long 0x0 0. "FT_DIS,Flow through disabled" "0: RAM read data is passed directly to the system..,1: RAM read data is registered prior to returning.." tree.end tree "PRAM_6" base ad:0x723A4000 group.long 0x0++0x3 line.long 0x0 "PRCR1,Platform RAM configuration register 1" bitfld.long 0x0 9. "PRI1,Not used since port 1 is not used. This bit can be written by software." "0,1" bitfld.long 0x0 8. "PRI0,Not used since port 1 is not used. This bit can be written by software." "0,1" bitfld.long 0x0 7. "P1_BO_DIS,Not used since port 1 is not used. This bit can be written by software." "0,1" bitfld.long 0x0 6. "P0_BO_DIS,Port p0 read burst optimization disable" "0: 32-bit WRP4 read bursts are optimized such that..,1: 32-bit WRP4 read bursts are not optimized; the.." newline bitfld.long 0x0 0. "FT_DIS,Flow through disabled" "0: RAM read data is passed directly to the system..,1: RAM read data is registered prior to returning.." tree.end tree "PRAM_7" base ad:0x717A4000 group.long 0x0++0x3 line.long 0x0 "PRCR1,Platform RAM configuration register 1" bitfld.long 0x0 9. "PRI1,Not used since port 1 is not used. This bit can be written by software." "0,1" bitfld.long 0x0 8. "PRI0,Not used since port 1 is not used. This bit can be written by software." "0,1" bitfld.long 0x0 7. "P1_BO_DIS,Not used since port 1 is not used. This bit can be written by software." "0,1" bitfld.long 0x0 6. "P0_BO_DIS,Port p0 read burst optimization disable" "0: 32-bit WRP4 read bursts are optimized such that..,1: 32-bit WRP4 read bursts are not optimized; the.." newline bitfld.long 0x0 0. "FT_DIS,Flow through disabled" "0: RAM read data is passed directly to the system..,1: RAM read data is registered prior to returning.." tree.end tree "PRAM_8" base ad:0x711A8000 group.long 0x0++0x3 line.long 0x0 "PRCR1,Platform RAM configuration register 1" bitfld.long 0x0 9. "PRI1,Not used since port 1 is not used. This bit can be written by software." "0,1" bitfld.long 0x0 8. "PRI0,Not used since port 1 is not used. This bit can be written by software." "0,1" bitfld.long 0x0 7. "P1_BO_DIS,Not used since port 1 is not used. This bit can be written by software." "0,1" bitfld.long 0x0 6. "P0_BO_DIS,Port p0 read burst optimization disable" "0: 32-bit WRP4 read bursts are optimized such that..,1: 32-bit WRP4 read bursts are not optimized; the.." newline bitfld.long 0x0 0. "FT_DIS,Flow through disabled" "0: RAM read data is passed directly to the system..,1: RAM read data is registered prior to returning.." tree.end tree "PRAM_9" base ad:0x717A8000 group.long 0x0++0x7 line.long 0x0 "CR,Platform RAM controller Configuration Register" bitfld.long 0x0 4. "WWS_EN,Wait State Enable for writes" "0: No extra wait state for Write operations,1: One extra wait state for Write operations" bitfld.long 0x0 3. "MEMACC_WAIT,Wait State Enable for ECC for RMW operations" "0: No extra wait state for RMW operations.,1: One extra wait state for RMW operations." newline bitfld.long 0x0 2. "RWS_EN,Wait State Enable for high memory access time" "0: RAM read takes 1 cycle.,1: RAM read takes 2 cycles." bitfld.long 0x0 1. "FIXED_BURST_EN,Fixed Burst Enable" "0: Fixed burst not supported. PRAMC will signal..,1: Fixed burst is supported by PRAMC." line.long 0x4 "MEM_SCRB,Platform RAM controller Memory Scrubbing" bitfld.long 0x4 31. "SCRB_STATUS,Error Repair Status" "0: Memory Scrubbing on RAM location is complete.,1: Memory Scrubbing on RAM location is pending." hexmask.long 0x4 0.--28. 1. "SCRB_ADDR,Memory Scrubbing Address" tree.end tree "PRAM_10" base ad:0x711AC000 group.long 0x0++0x7 line.long 0x0 "CR,Platform RAM controller Configuration Register" bitfld.long 0x0 4. "WWS_EN,Wait State Enable for writes" "0: No extra wait state for Write operations,1: One extra wait state for Write operations" bitfld.long 0x0 3. "MEMACC_WAIT,Wait State Enable for ECC for RMW operations" "0: No extra wait state for RMW operations.,1: One extra wait state for RMW operations." newline bitfld.long 0x0 2. "RWS_EN,Wait State Enable for high memory access time" "0: RAM read takes 1 cycle.,1: RAM read takes 2 cycles." bitfld.long 0x0 1. "FIXED_BURST_EN,Fixed Burst Enable" "0: Fixed burst not supported. PRAMC will signal..,1: Fixed burst is supported by PRAMC." line.long 0x4 "MEM_SCRB,Platform RAM controller Memory Scrubbing" bitfld.long 0x4 31. "SCRB_STATUS,Error Repair Status" "0: Memory Scrubbing on RAM location is complete.,1: Memory Scrubbing on RAM location is pending." hexmask.long 0x4 0.--28. 1. "SCRB_ADDR,Memory Scrubbing Address" tree.end tree "PRAM_12" base ad:0x711B0000 group.long 0x0++0x7 line.long 0x0 "CR,Platform RAM controller Configuration Register" bitfld.long 0x0 4. "WWS_EN,Wait State Enable for writes" "0: No extra wait state for Write operations,1: One extra wait state for Write operations" bitfld.long 0x0 3. "MEMACC_WAIT,Wait State Enable for ECC for RMW operations" "0: No extra wait state for RMW operations.,1: One extra wait state for RMW operations." newline bitfld.long 0x0 2. "RWS_EN,Wait State Enable for high memory access time" "0: RAM read takes 1 cycle.,1: RAM read takes 2 cycles." bitfld.long 0x0 1. "FIXED_BURST_EN,Fixed Burst Enable" "0: Fixed burst not supported. PRAMC will signal..,1: Fixed burst is supported by PRAMC." line.long 0x4 "MEM_SCRB,Platform RAM controller Memory Scrubbing" bitfld.long 0x4 31. "SCRB_STATUS,Error Repair Status" "0: Memory Scrubbing on RAM location is complete.,1: Memory Scrubbing on RAM location is pending." hexmask.long 0x4 0.--28. 1. "SCRB_ADDR,Memory Scrubbing Address" tree.end tree.end tree "PSI5 (Peripheral Sensor Interface)" base ad:0x0 tree "PSI5_0" base ad:0x70EF8000 group.word 0x2++0x1 line.word 0x0 "GCR,Global Control Register" bitfld.word 0x0 1. "CTC_GED,Channel Target Counter (CTC) Global Enable/Disable." "0: All the CTC counters having..,1: Simultaneously starts the CTC of all the.." newline bitfld.word 0x0 0. "GLOBAL_DISABLE_REQ,PSI5 Receive Global disable request. When set all PSI5 channels enter Disable mode (from individual Normal or Config modes) regardless of the settings of the PCCR[PSI5_CH_CONFIG] and PCCR[PSI5_CH_EN] bits." "0: PSI5 channel(s) enters Normal or Config mode..,1: All PSI5 Channels are in Disable mode." group.long 0x8++0x1F line.long 0x0 "CH0_PCCR,PSI5 Channel Control Register" bitfld.long 0x0 31. "CTC_GED_SEL,Channel Target Counter Global Enable/Disable Select" "0: CTC enabled disabled by CTC_ED.,1: CTC enabled/disabled by CTC_GED." newline bitfld.long 0x0 30. "CTC_ED,Channel Target Counter Enable/Disable" "0: The CTC counters is disabled and reset.,1: The CTC counter is enabled and start counting." newline hexmask.long.byte 0x0 24.--28. 1. "MEM_DEPTH,Can be programmed from 0 to 31 and denotes the size of the memory that should be used for storing the PSI5 messages. Area above the MEM_DEPTH is treated as being unavailable for message storage." newline bitfld.long 0x0 20. "ERROR_SELECT4,The ERROR_SELECT bitfield indicates which of the C E EM T or F error conditions generate an interrupt when the EICR Interrupt Enable bit is set. The individual bits are mapped as {C E EM T F}. The corresponding error is also latched in.." "0: The C bit does not generate an interrupt.,1: The C bit generates an interrupt." newline bitfld.long 0x0 19. "ERROR_SELECT3,Error_Select[3] or E_INT_SEL" "0: The E bit does not generate an interrupt.,1: The E bit generates an interrupt." newline bitfld.long 0x0 18. "ERROR_SELECT2,Error_Select[2] or EM_INT_SEL" "0: The EM bit does not generate an interrupt.,1: The EM bit generates an interrupt." newline bitfld.long 0x0 17. "ERROR_SELECT1,Error_Select[1] or T_INT_SEL" "0: The T bit does not generate an interrupt.,1: The T bit generates an interrupt." newline bitfld.long 0x0 16. "ERROR_SELECT0,Error_Select[0] or F_INT_SEL" "0: The F bit does not generate an interrupt.,1: The F bit generates an interrupt." newline bitfld.long 0x0 14. "GTM_RESET_ASYNC_EN,GTM_RESET_ASYNC_EN" "0: Both the assertion and the deassertion of the..,1: Assertion of the GTM reset is treated.." newline bitfld.long 0x0 10. "DEBUG_EN,This bit allows/prevents the IP from entering the debug mode whenever the debugger is connected and a breakpoint is encountered by the debugger:" "0: The IP never enters the debug mode even if the..,1: Whenever the debugger is connected and a.." newline bitfld.long 0x0 9. "DEBUG_FREEZE_CTRL,Note: In the above configuration the status of registers read through the debugger may be different when entering debug mode and when actually accessing registers at some later point of time." "0: When the IP enters the Debug mode then it goes..,1: When the IP enters the Debug mode then it goes.." newline bitfld.long 0x0 8. "SP_TS_CLK_SEL,This bit controls which clock goes to the Sync Pulse and Time Stamp Generator Unit." "0: The 1MHz clock generated from the CGM goes for..,1: The clock generated from the GTM goes for.." newline bitfld.long 0x0 5. "FAST_CLR_SMC,This bit controls the clearing mechanism of the IS_NVSM[x] IS_CESM[x] and IS_OWSM[x] bits in the GISR." "0: Fast clearing is disabled (clear when written to..,1: Fast clearing is enabled." newline bitfld.long 0x0 4. "FAST_CLR_PSI5,This bit controls the clearing mechanism of bits in NDSR (in conf2 conf3 and conf4 modes) EISR (in conf2 conf3 and conf4 modes) and OWSR (in conf2 and conf3 modes)." "0: Fast Clearing Disables (clear when written to 1),1: Fast Clearing Enabled" newline bitfld.long 0x0 3. "BIT_RATE,This bit selects the receive message bit rate (T bit) for this particular PSI5 Channel that is it selects one of the two driven clocks (4MHz or 6.048MHz) in CGM." "0: 125Kbit/s bit rate selected (4MHz clock).,1: 189Kbit/s bit rate selected (6.048MHz clock)." newline bitfld.long 0x0 2. "MODE,This bit selects the operating modes." "0: Asynchronous operating mode (Integrated sync..,1: Synchronous operating modes (Integrated sync.." newline bitfld.long 0x0 1. "PSI5_CH_CONFIG,PSI5 Channel Config mode request" "0: (If PCCR[PSI5_CH_EN] =0x1: and..,1: (If PCCR[PSI5_CH_EN]=0x1: and.." newline bitfld.long 0x0 0. "PSI5_CH_EN,PSI5 Channel Enable. If this bit is cleared this particular psi5 channel continues to stay in Disable mode even if GCR[GLOBAL_DISABLE_REQ] = 0. If set it enters Configuration mode from Disable mode (based on PCCR[PSI5_CH_CONFIG]). Default.." "0: PSI5 channel continues in Disable mode.,1: PSI5 channel enabled to enter Config/Normal mode." line.long 0x4 "CH0_DCR,DMA Control Register" hexmask.long.byte 0x4 24.--28. 1. "DMA_PM_DS_WM,Value fixed by user software." newline bitfld.long 0x4 18. "IE_DMA_TF_SF,Enable for interrupt which is generated when DMA transfer finishes for DMA SMC Frame register." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x4 17. "IE_DMA_TF_PM_DS,Enable for Interrupt which is generated when DMA transfer finishes for PSI5 messages/DMA Diagnostic Status register depending on the DMA_PM_DS_CONFIG bits of the DCR." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x4 11. "IE_DMA_PM_DS_FIFO_FULL,This bit is effective only when the DMA_PM_DS_CONFIG = conf2 conf3 or conf4. It enables the FIFO FULL condition generation interrupt. For the cases that generate these FIFO FULL conditions refer to the description of.." "0,1" newline bitfld.long 0x4 10. "IE_DMA_SFUF,Enables interrupt when there is underflow in DMA SMC Frame register when DMA is enabled. It is set when the DSFR is read without a valid DMA request that is it is empty." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x4 8. "IE_DMA_PM_DS_UF,Enables interrupt when there is underflow in DMA PSI5 message register when DMA is enabled. Default value is 0. For the details as to when this underflow occurs refer to the details of IS_DMA_PM_DS_UF bit details of the DSR." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x4 2. "DMA_EN_SF,Enable DMA request for SMC Frame Data" "0: DMA for SMC frame is disabled. The six dedicated..,1: DMA for SMC frame is enabled. The six dedicated.." newline bitfld.long 0x4 0.--1. "DMA_PM_DS_CONFIG,These bits define how the PSI5 messages are stored in the MEM_DEPTH memory area and the associated diagnostic bits (EISR NDSR) are transferred." "0: conf1 The DMA request is disabled. In this mode..,1: conf2 After transferring the dma_pm_ds_wm number..,2: conf3 dma_pm_ds_wm number of PSI5 messages is..,3: conf4 Only the diagnostic bits are transferred.." line.long 0x8 "CH0_DSR,DMA Status Register" bitfld.long 0x8 18. "IS_DMA_TF_SF,This flag is set when DMA transfer finishes for DMA SMC Frame register." "0,1" newline bitfld.long 0x8 17. "IS_DMA_TF_PM_DS,This flag is set when DMA transfer finishes. For the various configurations of this request refer to the descriptions of the DMA_PM_DS_CONFIG bits in the DCR. This flag is cleared by w1c." "0,1" newline bitfld.long 0x8 11. "IS_DMA_PM_DS_FIFO_FULL,Interrupt Status when there is FIFO FULL corresponding to the DMA request ipd_psi5_dma_req_pm_ds." "0: No FIFO full.,1: FIFO full has occurred" newline bitfld.long 0x8 10. "IS_DMA_SFUF,SMC Frame DMA underflow: This happens when the DSFR has been read without a proper DMA request being asserted. The DSFR is empty and it is read. This bit is cleared by a w1c." "0: No underflow has occurred.,1: Underflow has occurred." newline bitfld.long 0x8 8. "IS_DMA_PM_DS_UF,Depending on the DMA_PM_DS_CONFIG bits following is the underflow conditions:" "0: No underflow has occurred.,1: Underflow has occurred." line.long 0xC "CH0_GICR,General Interrupt Control Register" hexmask.long.byte 0xC 24.--29. 1. "IE_CESM,Interrupt request when received SMC frame in corresponding slot has CRC failure (CRC recalculation on SMC)." newline bitfld.long 0xC 23. "IE_STS,Interrupt request enabled when the Sync Pulse Triggered Time Stamp value is refreshed on STSRR." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 22. "IE_DTS,Interrupt request enabled when the Data Start sequence Triggered Time Stamp value is refreshed on DTSRR." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 21. "IE_DSROW,Interrupt request enabled when system tries to overwrite on Data Shift register when it is not ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 20. "IE_BROW,Interrupt request enabled when system tries to overwrite on buffer register when it is not ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 19. "IE_PROW,Interrupt request enabled when system tries to overwrite on Preparation register when it is not ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 18. "IE_DSRR,Interrupt request enabled when Data Shift Register is ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 17. "IE_BRR,Interrupt request enabled when buffer Register is ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 16. "IE_PRR,Interrupt request enabled when Preparation Register ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline hexmask.long.byte 0xC 8.--13. 1. "IE_OWSM,Interrupt request enable for the SMC message Overwrite bits." newline hexmask.long.byte 0xC 0.--5. 1. "IE_NVSM,Interrupt request enabled when any new valid SMC message (fault free) is received in SFR[i]{i:0 to 5} that is during slot1 to slot6. This interrupt is generated only when corresponding IS_NVSMS[5:0] is set." line.long 0x10 "CH0_NDICR,New Data Interrupt Control Register" hexmask.long 0x10 0.--31. 1. "IE_ND,Interrupt request enabled when any new message (fault-free/with fault) is received in the RAM buffer Registerx location [x: 0 to 31] This interrupt is generated only when corresponding RAM buffer Ready with new data." line.long 0x14 "CH0_OWICR,Overwrite Interrupt Control Register" hexmask.long 0x14 0.--31. 1. "IE_OW,Interrupt request enabled when any new message overwrites the old unread PSI5 message in the RAM buffer Registerx location [x: 0 to 31] This interrupt generated only when corresponding RAM buffer Ready with new data." line.long 0x18 "CH0_EICR,Error Interrupt Control Register" hexmask.long 0x18 0.--31. 1. "IE_ERROR,Interrupt request enabled when any/all of the error conditions C E EM T or F is observed in a PSI5 message in the RAM buffer Registerx location [x: 0 to 31]. This interrupt is generated only when the corresponding RAM buffer is Ready with.." line.long 0x1C "CH0_GISR,General Interrupt Status Register" bitfld.long 0x1C 31. "IS_DEBUG_FREEZE,This flag is set to 1 when the IP enters the debug freeze mode. Please see Section1.1.3.5: Debug mode for details about the debug mode. This bit is auto cleared by the hardware when the IP exits the debug freeze mode." "0: IP not in debug freeze mode,1: IP in debug freeze mode" newline bitfld.long 0x1C 29. "IS_CESM6,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 28. "IS_CESM5,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 27. "IS_CESM4,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 26. "IS_CESM3,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 25. "IS_CESM2,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 24. "IS_CESM1,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 23. "IS_STS,This Interrupt flag is set when the Sync Pulse Triggered Time Stamp value is refreshed on STSRR." "0,1" newline bitfld.long 0x1C 22. "IS_DTS,This Interrupt flag is set when the Data Start sequence Triggered Time Stamp value is refreshed on DTSRR." "0,1" newline bitfld.long 0x1C 21. "IS_DSROW,This flag is set when the system tries to overwrite on Data Shift register when it is not ready to accept new data." "0,1" newline bitfld.long 0x1C 20. "IS_BROW,This flag is set when the system tries to overwrite on buffer register when it is not ready to accept new data." "0,1" newline bitfld.long 0x1C 19. "IS_PROW,This flag is set when the system tries to overwrite on Preparation register when it is not ready to accept new data." "0,1" newline bitfld.long 0x1C 18. "DSR_RDY,This bit acts both as a status and a control bit." "0,1" newline bitfld.long 0x1C 17. "DBR_RDY,This bit acts both as a status and a control bit." "0,1" newline bitfld.long 0x1C 16. "DPR_RDY,This bit acts both as a status and a control bit." "0,1" newline bitfld.long 0x1C 13. "IS_OWSM6,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 12. "IS_OWSM5,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 11. "IS_OWSM4,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 10. "IS_OWSM3,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 9. "IS_OWSM2,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 8. "IS_OWSM1,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 5. "IS_NVSM6,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" newline bitfld.long 0x1C 4. "IS_NVSM5,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" newline bitfld.long 0x1C 3. "IS_NVSM4,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" newline bitfld.long 0x1C 2. "IS_NVSM3,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" newline bitfld.long 0x1C 1. "IS_NVSM2,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" newline bitfld.long 0x1C 0. "IS_NVSM1,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" rgroup.long 0x28++0x13 line.long 0x0 "CH0_DPMR,DMA PSI5 Message Register" hexmask.long 0x0 0.--31. 1. "PSI5_RXDATA,PSI5_RXDATA[31:0]" line.long 0x4 "CH0_DSFR,DMA SMC Frame Register" hexmask.long 0x4 0.--31. 1. "SMC_RXDATA,When the DMA_EN_SF = 1 then the six SFR registers are searched in a round robin fashion for the reception of the complete SMC data. The DMA request is asserted as soon as the first encountered SFR has a complete SMC frame. This request.." line.long 0x8 "CH0_DDSR,DMA Diagnostic Status Register" hexmask.long 0x8 0.--31. 1. "DDS,This register maps each of the individual Diagnostic registers (in the order NDSR EISR) depending on the configuration of the DMA_PM_DS_CONFIG bits in the DCR. This register is a reflection of the location pointed to by the DMA read pointer." line.long 0xC "CH0_PMRRL,PSI5 Message Receive Register Low" hexmask.long 0xC 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xC 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRC[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "C,This bit will be set if CRC/P recalculation return an Error." "0,1" line.long 0x10 "CH0_PMRRH,PSI5 Message Receive Register High" bitfld.long 0x10 30. "F,This represents that NO frame was received in the corresponding configured slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error)." newline bitfld.long 0x10 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the T bit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields." newline bitfld.long 0x10 28. "E,This bit indicates electrical error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x10 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot spread across two slots started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot." newline bitfld.long 0x10 24.--26. "SLOTCOUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x10 0.--23. 1. "T0MESTAMPVALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed by.." group.long 0x3C++0x123 line.long 0x0 "CH0_PMRL0,PSI5 Message Register Low 0" hexmask.long 0x0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x4 "CH0_PMRH0,PSI5 Message Register High 0" bitfld.long 0x4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x4 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x8 "CH0_PMRL1,PSI5 Message Register Low 1" hexmask.long 0x8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xC "CH0_PMRH1,PSI5 Message Register High 1" bitfld.long 0xC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xC 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x10 "CH0_PMRL2,PSI5 Message Register Low 2" hexmask.long 0x10 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x10 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x14 "CH0_PMRH2,PSI5 Message Register High 2" bitfld.long 0x14 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x14 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x14 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x14 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x14 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x14 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x14 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x18 "CH0_PMRL3,PSI5 Message Register Low 3" hexmask.long 0x18 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x18 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x1C "CH0_PMRH3,PSI5 Message Register High 3" bitfld.long 0x1C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x1C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x1C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x1C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x1C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x1C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x1C 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x20 "CH0_PMRL4,PSI5 Message Register Low 4" hexmask.long 0x20 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x20 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x24 "CH0_PMRH4,PSI5 Message Register High 4" bitfld.long 0x24 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x24 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x24 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x24 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x24 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x24 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x24 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x28 "CH0_PMRL5,PSI5 Message Register Low 5" hexmask.long 0x28 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x28 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x2C "CH0_PMRH5,PSI5 Message Register High 5" bitfld.long 0x2C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x2C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x2C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x2C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x2C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x2C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x2C 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x30 "CH0_PMRL6,PSI5 Message Register Low 6" hexmask.long 0x30 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x30 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x34 "CH0_PMRH6,PSI5 Message Register High 6" bitfld.long 0x34 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x34 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x34 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x34 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x34 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x34 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x34 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x38 "CH0_PMRL7,PSI5 Message Register Low 7" hexmask.long 0x38 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x38 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x3C "CH0_PMRH7,PSI5 Message Register High 7" bitfld.long 0x3C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x3C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x3C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x3C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x3C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x3C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x3C 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x40 "CH0_PMRL8,PSI5 Message Register Low 8" hexmask.long 0x40 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x40 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x44 "CH0_PMRH8,PSI5 Message Register High 8" bitfld.long 0x44 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x44 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x44 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x44 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x44 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x44 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x44 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x48 "CH0_PMRL9,PSI5 Message Register Low 9" hexmask.long 0x48 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x48 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x4C "CH0_PMRH9,PSI5 Message Register High 9" bitfld.long 0x4C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x4C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x4C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x4C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x4C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x4C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x4C 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x50 "CH0_PMRL10,PSI5 Message Register Low 10" hexmask.long 0x50 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x50 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x54 "CH0_PMRH10,PSI5 Message Register High 10" bitfld.long 0x54 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x54 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x54 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x54 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x54 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x54 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x54 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x58 "CH0_PMRL11,PSI5 Message Register Low 11" hexmask.long 0x58 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x58 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x5C "CH0_PMRH11,PSI5 Message Register High 11" bitfld.long 0x5C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x5C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x5C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x5C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x5C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x5C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x5C 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x60 "CH0_PMRL12,PSI5 Message Register Low 12" hexmask.long 0x60 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x60 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x64 "CH0_PMRH12,PSI5 Message Register High 12" bitfld.long 0x64 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x64 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x64 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x64 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x64 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x64 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x64 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x68 "CH0_PMRL13,PSI5 Message Register Low 13" hexmask.long 0x68 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x68 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x6C "CH0_PMRH13,PSI5 Message Register High 13" bitfld.long 0x6C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x6C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x6C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x6C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x6C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x6C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x6C 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x70 "CH0_PMRL14,PSI5 Message Register Low 14" hexmask.long 0x70 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x70 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x74 "CH0_PMRH14,PSI5 Message Register High 14" bitfld.long 0x74 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x74 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x74 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x74 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x74 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x74 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x74 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x78 "CH0_PMRL15,PSI5 Message Register Low 15" hexmask.long 0x78 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x78 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x7C "CH0_PMRH15,PSI5 Message Register High 15" bitfld.long 0x7C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x7C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x7C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x7C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x7C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x7C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x7C 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x80 "CH0_PMRL16,PSI5 Message Register Low 16" hexmask.long 0x80 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x80 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x84 "CH0_PMRH16,PSI5 Message Register High 16" bitfld.long 0x84 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x84 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x84 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x84 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x84 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x84 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x84 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x88 "CH0_PMRL17,PSI5 Message Register Low 17" hexmask.long 0x88 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x88 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x8C "CH0_PMRH17,PSI5 Message Register High 17" bitfld.long 0x8C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x8C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x8C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x8C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x8C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x8C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x8C 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x90 "CH0_PMRL18,PSI5 Message Register Low 18" hexmask.long 0x90 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x90 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x94 "CH0_PMRH18,PSI5 Message Register High 18" bitfld.long 0x94 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x94 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x94 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x94 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x94 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x94 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x94 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x98 "CH0_PMRL19,PSI5 Message Register Low 19" hexmask.long 0x98 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x98 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x9C "CH0_PMRH19,PSI5 Message Register High 19" bitfld.long 0x9C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x9C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x9C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x9C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x9C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x9C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x9C 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xA0 "CH0_PMRL20,PSI5 Message Register Low 20" hexmask.long 0xA0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xA0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xA4 "CH0_PMRH20,PSI5 Message Register High 20" bitfld.long 0xA4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xA4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xA4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xA4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xA4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xA4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xA4 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xA8 "CH0_PMRL21,PSI5 Message Register Low 21" hexmask.long 0xA8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xA8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xAC "CH0_PMRH21,PSI5 Message Register High 21" bitfld.long 0xAC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xAC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xAC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xAC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xAC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xAC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xAC 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xB0 "CH0_PMRL22,PSI5 Message Register Low 22" hexmask.long 0xB0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data framesfor more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the PSI5.." newline bitfld.long 0xB0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xB4 "CH0_PMRH22,PSI5 Message Register High 22" bitfld.long 0xB4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xB4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xB4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xB4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xB4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xB4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xB4 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xB8 "CH0_PMRL23,PSI5 Message Register Low 23" hexmask.long 0xB8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data framesfor more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the PSI5.." newline bitfld.long 0xB8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xBC "CH0_PMRH23,PSI5 Message Register High 23" bitfld.long 0xBC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xBC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xBC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xBC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xBC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xBC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xBC 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xC0 "CH0_PMRL24,PSI5 Message Register Low 24" hexmask.long 0xC0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xC0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xC4 "CH0_PMRH24,PSI5 Message Register High 24" bitfld.long 0xC4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xC4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xC4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xC4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xC4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xC4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xC4 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xC8 "CH0_PMRL25,PSI5 Message Register Low 25" hexmask.long 0xC8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xC8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xCC "CH0_PMRH25,PSI5 Message Register High 25" bitfld.long 0xCC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xCC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xCC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xCC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xCC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xCC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xCC 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xD0 "CH0_PMRL26,PSI5 Message Register Low 26" hexmask.long 0xD0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xD0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xD4 "CH0_PMRH26,PSI5 Message Register High 26" bitfld.long 0xD4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xD4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xD4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xD4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xD4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xD4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xD4 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xD8 "CH0_PMRL27,PSI5 Message Register Low 27" hexmask.long 0xD8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xD8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xDC "CH0_PMRH27,PSI5 Message Register High 27" bitfld.long 0xDC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xDC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xDC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xDC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xDC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xDC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xDC 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xE0 "CH0_PMRL28,PSI5 Message Register Low 28" hexmask.long 0xE0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xE0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xE4 "CH0_PMRH28,PSI5 Message Register High 28" bitfld.long 0xE4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xE4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xE4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xE4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xE4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xE4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xE4 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xE8 "CH0_PMRL29,PSI5 Message Register Low 29" hexmask.long 0xE8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xE8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xEC "CH0_PMRH29,PSI5 Message Register High 29" bitfld.long 0xEC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xEC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xEC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xEC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xEC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xEC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xEC 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xF0 "CH0_PMRL30,PSI5 Message Register Low 30" hexmask.long 0xF0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xF0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xF4 "CH0_PMRH30,PSI5 Message Register High 30" bitfld.long 0xF4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xF4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xF4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xF4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xF4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xF4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xF4 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xF8 "CH0_PMRL31,PSI5 Message Register Low 31" hexmask.long 0xF8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xF8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xFC "CH0_PMRH31,PSI5 Message Register High 31" bitfld.long 0xFC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xFC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xFC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xFC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xFC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xFC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xFC 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x100 "CH0_SFR1,SMC Frame Register 1" bitfld.long 0x100 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the correct.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x100 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x100 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x100 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x100 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x100 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x100 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x100 0.--11. 1. "DATA,DATA payload" line.long 0x104 "CH0_SFR2,SMC Frame Register 2" bitfld.long 0x104 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the correct.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x104 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x104 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x104 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x104 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x104 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x104 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x104 0.--11. 1. "DATA,DATA payload" line.long 0x108 "CH0_SFR3,SMC Frame Register 3" bitfld.long 0x108 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the correct.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x108 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x108 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x108 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x108 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x108 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x108 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x108 0.--11. 1. "DATA,DATA payload" line.long 0x10C "CH0_SFR4,SMC Frame Register 4" bitfld.long 0x10C 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the correct.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10C 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x10C 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x10C 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x10C 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x10C 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x10C 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x10C 0.--11. 1. "DATA,DATA payload" line.long 0x110 "CH0_SFR5,SMC Frame Register 5" bitfld.long 0x110 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x110 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x110 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x110 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x110 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x110 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x110 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x110 0.--11. 1. "DATA,DATA payload" line.long 0x114 "CH0_SFR6,SMC Frame Register 6" bitfld.long 0x114 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the correct.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x114 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x114 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x114 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x114 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x114 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x114 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x114 0.--11. 1. "DATA,DATA payload" line.long 0x118 "CH0_NDSR,New Data Status Register" hexmask.long 0x118 0.--31. 1. "NDS,New Data Status flags for PSI5 Messages corresponding to each PSI5 MB locations." line.long 0x11C "CH0_OWSR,Overwrite Status Register" hexmask.long 0x11C 0.--31. 1. "OWS,Over Write Status flags for PSI5 Messages corresponding to each PSI5 location in the RAM registers." line.long 0x120 "CH0_EISR,Error Indication Status Register" hexmask.long 0x120 0.--31. 1. "ERROR,Error Status flags for PSI5 Messages corresponding to each PSI5 MB locations." wgroup.long 0x160++0x3 line.long 0x0 "CH0_SNDSR,Set New Data Status Register" hexmask.long 0x0 0.--31. 1. "SNDS,Sets New Data Status flags for PSI5 Messages corresponding to each PSI5 MB locations." group.long 0x164++0x3 line.long 0x0 "CH0_SOWSR,Set Overwrite Status Register" hexmask.long 0x0 0.--31. 1. "SOWS,Sets overwrite status flags for PSI5 messages corresponding to each PSI5 MB locations." wgroup.long 0x168++0x7 line.long 0x0 "CH0_SEISR,Set Error Status Register" hexmask.long 0x0 0.--31. 1. "SERROR,Sets Error Status flags for PSI5 messages corresponding to each PSI5 MB locations." line.long 0x4 "CH0_SSESR,Set SMC Error Status Register" hexmask.long.byte 0x4 24.--29. 1. "SCESM,Sets IS_CESM Status flags for SMC Messages corresponding to each SMC MB locations." newline hexmask.long.byte 0x4 8.--13. 1. "SOWSM,Sets IS_OWSM Status flags for SMC Messages corresponding to each SMC MB locations." newline hexmask.long.byte 0x4 0.--5. 1. "SNVSM,Sets IS_NVSM Status flags for SMC Messages corresponding to each SMC MB locations." rgroup.long 0x170++0x7 line.long 0x0 "CH0_STSRR,Sync Time Stamp Read Register" hexmask.long.tbyte 0x0 0.--23. 1. "STSV,Sync Time Stamp Value[23:0]" line.long 0x4 "CH0_DTSRR,Data Time Stamp Read Register" bitfld.long 0x4 24.--26. "SLOT_COUNTER,3-bit Slot Counter which corresponds to the slot for which the DTSRR contains the Time Stamp. The slot_counter contains the slot in which the start bits of this frame was captured (after successful detection of S1). If the start bits get.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x4 0.--23. 1. "DTSV,Data Time Stamp Value[23:0]" group.long 0x178++0x17 line.long 0x0 "CH0_S1FCR,Slot 1 Frame Configuration Register" bitfld.long 0x0 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0x0 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0x0 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0x0 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0x0 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." line.long 0x4 "CH0_S2FCR,Slot 2 Frame Configuration Register" bitfld.long 0x4 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0x4 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0x4 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0x4 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0x4 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." line.long 0x8 "CH0_S3FCR,Slot 3 Frame Configuration Register" bitfld.long 0x8 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0x8 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0x8 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0x8 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0x8 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." line.long 0xC "CH0_S4FCR,Slot 4 Frame Configuration Register" bitfld.long 0xC 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0xC 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0xC 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0xC 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0xC 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." line.long 0x10 "CH0_S5FCR,Slot 5 Frame Configuration Register" bitfld.long 0x10 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0x10 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0x10 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0x10 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0x10 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." line.long 0x14 "CH0_S6FCR,Slot 6 Frame Configuration Register" bitfld.long 0x14 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0x14 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0x14 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0x14 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0x14 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." rgroup.word 0x190++0xB line.word 0x0 "CH0_S2SBR,Slot 2 Start Boundary Register" hexmask.word 0x0 0.--14. 1. "S2SBT,Slot 2 Start Boundary Time" line.word 0x2 "CH0_S1SBR,Slot 1 Start Boundary Register" hexmask.word 0x2 0.--14. 1. "S1SBT,Slot 0x1: Start Boundary Time" line.word 0x4 "CH0_S4SBR,Slot 4 Start Boundary Register" hexmask.word 0x4 0.--14. 1. "S4SBT,Slot 4 Start Boundary Time" line.word 0x6 "CH0_S3SBR,Slot 3 Start Boundary Register" hexmask.word 0x6 0.--14. 1. "S3SBT,Slot 3 Start Boundary Time" line.word 0x8 "CH0_S6SBR,Slot 6 Start Boundary Register" hexmask.word 0x8 0.--14. 1. "S6SBT,Slot 6 Start Boundary Time" line.word 0xA "CH0_S5SBR,Slot 5 Start Boundary Register" hexmask.word 0xA 0.--14. 1. "S5SBT,Slot 5 Start Boundary Time" group.long 0x19C++0x3 line.long 0x0 "CH0_SNEBR,Slot n End Boundary Register" bitfld.long 0x0 16.--18. "SLOT_NO,The field indicates the Slot number{16} for which Slot End Boundary Time is defined." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--14. 1. "SNEBT,Slot n End Boundary Time" group.word 0x1A0++0xB line.word 0x0 "CH0_MDDIS_OFF,Manchester Decoder Disable Offset Register" hexmask.word.byte 0x0 0.--6. 1. "MDDIS_OFF,These 7 bits can be used to program the time for which the Manchester decoder remains disabled. This offset is added AFTER the falling edge of the sync pulse. Thus the total time for which the Manchester decoder remains disabled = TsyncH +.." line.word 0x2 "CH0_DOBCR,Data Output Block Configuration Register" hexmask.word.byte 0x2 10.--15. 1. "DATA_LENGTH,Can take on values from 0 to 63 corresponding to 1 bit to 64 bit non standard length commands." newline bitfld.word 0x2 9. "DBR_RST,This is to reset and reject current content to Data Buffer Register. When this bit is written as 1 then the contents of the DBR are reset to all 0s (if DEFAULT_SYNC= = 0) or all 1s (if DEFAULT_SYNC == 1). As soon as content is reset the DBR would.." "0,1" newline bitfld.word 0x2 8. "DSR_RST,This is to reset and reject current content to Data Shift Register.When this bit is written as 1 then the contents of the DSR are reset to all 0s (if DEFAULT_SYNC= = 0) or all 1s (if DEFAULT_SYNC == 1). As soon as content is reset the DSR would.." "0,1" newline bitfld.word 0x2 5.--7. "CMD_TYPE,These 3 bits indicate the type of command that needs to be transmitted during the ECU to sensor communication. Table2061 is a brief description of the same." "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 4. "DEFAULT_SYNC,When this bit is set to 0 then the default value of DSR and DBR registers are all 0s; when this bit is set to 1 then the default value of DBR and DSR registers are all 1s." "0,1" newline bitfld.word 0x2 3. "GTM_TRIG_SEL,GTM event triggered/internal sync pulse generator selection as shift clock for the DSR." "0: Internal sync pulse generator shift triggered,1: GTM event shift triggered" newline bitfld.word 0x2 2. "SP_PULSE_SEL,Selects the source for the short pulse PWM module:" "0: SP module gets the data from the DSR,1: SP module directly gets input from the.." newline bitfld.word 0x2 1. "OP_SEL,This bit selects the driving source of the ipp_do_psi5_sdout port." "0: The sync pulse generator select as per the..,1: PWM output" newline bitfld.word 0x2 0. "SW_READY,When this bit is written to 1 the transfer from DBR to DSR automatically happens as soon as DSR_RDY becomes 1. When this bit is kept to 0 then the transfer from DBR to DSR will remain pending. Once the software makes this bit as 1 and DSR_RDY.." "0,1" line.word 0x4 "CH0_PW1D,Pulse Width for Data Bit 1 Register" hexmask.word.byte 0x4 0.--6. 1. "PULSE_W0DTH1,This defines the width (in microsesc) of data value0x1: to be sent from Data Output Register. It is the number of clock cycles (1 microsesc clock) counted up to width Pulse_Width1; starting as soon as trigger appears from the ISPG(Internal.." line.word 0x6 "CH0_PW0D,Pulse Width for Data Bit 0 Register" hexmask.word.byte 0x6 0.--6. 1. "PULSE_W0DTH0,This defines the width (in microsesc) of data value0x0: to be sent from Data Output Register. It is the number of clock cycles (1 microsesc clock) counted up to width Pulse_Width0; starting as soon as trigger appears from the ISPG (Internal.." line.word 0x8 "CH0_CIPR,Counter Initialize Pulse Register" hexmask.word 0x8 0.--15. 1. "CIPR,Counter initialization pulse register" line.word 0xA "CH0_CTPR,Counter Target Pulse Register" hexmask.word 0xA 0.--15. 1. "CTPR,Counter Target Pulse Register" group.long 0x1AC++0x3 line.long 0x0 "CH0_DPRL,Data Preparation Register Low" hexmask.long.tbyte 0x0 0.--23. 1. "DPR,DPR[23:0] are the 24-bits of the DPR register used for writing the variable length standard ECU-to-Sensor commands comprising of the address data and other fields. Note that the IP is transparent to the arrangement of the address data and other.." rgroup.long 0x1B0++0x3 line.long 0x0 "CH0_DPRH,Data Preparation Register High" group.long 0x1B4++0xF line.long 0x0 "CH0_DBRL,Data Buffer Register Low" hexmask.long 0x0 0.--31. 1. "DBR,This register contains the Lower 32 bits(DBR[31:0]) of the max-64 bit length command (DBR[63:0]). The higher bits DBR[63:32] are contained in the DBRH register." line.long 0x4 "CH0_DBRH,Data Buffer Register High" hexmask.long 0x4 0.--31. 1. "DBR,This register contains the Upper 32 bits(DBR[63:32]) of the max-64 bit length command (DBR[63:0]). The lower bits DBR[31:0] are contained in the DBRL register." line.long 0x8 "CH0_DSRL,Data Shift Register Low" hexmask.long 0x8 0.--31. 1. "DSR,These bits can be updated by the hardware or can be written by the CPU. The number of accessible bits in DSR are always equal to the number of accessible bits in DBR which in turn depend on the value of PSI5_DOBCR[CMD_TYPE] register bits.When these.." line.long 0xC "CH0_DSRH,Data Shift Register High" hexmask.long 0xC 0.--31. 1. "DSR,These bits can be updated by the hardware or can be written by the CPU. The number of accessible bits in DSR are always equal to the number of accessible bits in DBR which in turn depend on the value of PSI5_DOBCR[CMD_TYPE] register bits. When these.." group.long 0x1C8++0x1F line.long 0x0 "CH1_PCCR,PSI5 Channel Control Register" bitfld.long 0x0 31. "CTC_GED_SEL,Channel Target Counter Global Enable/Disable Select" "0: CTC enabled disabled by CTC_ED.,1: CTC enabled/disabled by CTC_GED." newline bitfld.long 0x0 30. "CTC_ED,Channel Target Counter Enable/Disable" "0: The CTC counters is disabled and reset.,1: The CTC counter is enabled and start counting." newline hexmask.long.byte 0x0 24.--28. 1. "MEM_DEPTH,Can be programmed from 0 to 31 and denotes the size of the memory that should be used for storing the PSI5 messages. Area above the MEM_DEPTH is treated as being unavailable for message storage." newline bitfld.long 0x0 20. "ERROR_SELECT4,The ERROR_SELECT bitfield indicates which of the C E EM T or F error conditions generate an interrupt when the EICR Interrupt Enable bit is set. The individual bits are mapped as {C E EM T F}. The corresponding error is also latched in.." "0: The C bit does not generate an interrupt.,1: The C bit generates an interrupt." newline bitfld.long 0x0 19. "ERROR_SELECT3,Error_Select[3] or E_INT_SEL" "0: The E bit does not generate an interrupt.,1: The E bit generates an interrupt." newline bitfld.long 0x0 18. "ERROR_SELECT2,Error_Select[2] or EM_INT_SEL" "0: The EM bit does not generate an interrupt.,1: The EM bit generates an interrupt." newline bitfld.long 0x0 17. "ERROR_SELECT1,Error_Select[1] or T_INT_SEL" "0: The T bit does not generate an interrupt.,1: The T bit generates an interrupt." newline bitfld.long 0x0 16. "ERROR_SELECT0,Error_Select[0] or F_INT_SEL" "0: The F bit does not generate an interrupt.,1: The F bit generates an interrupt." newline bitfld.long 0x0 14. "GTM_RESET_ASYNC_EN,GTM_RESET_ASYNC_EN" "0: Both the assertion and the deassertion of the..,1: Assertion of the GTM reset is treated.." newline bitfld.long 0x0 10. "DEBUG_EN,This bit allows/prevents the IP from entering the debug mode whenever the debugger is connected and a breakpoint is encountered by the debugger:" "0: The IP never enters the debug mode even if the..,1: Whenever the debugger is connected and a.." newline bitfld.long 0x0 9. "DEBUG_FREEZE_CTRL,Note: In the above configuration the status of registers read through the debugger may be different when entering debug mode and when actually accessing registers at some later point of time." "0: When the IP enters the Debug mode then it goes..,1: When the IP enters the Debug mode then it goes.." newline bitfld.long 0x0 8. "SP_TS_CLK_SEL,This bit controls which clock goes to the Sync Pulse and Time Stamp Generator Unit." "0: The 1MHz clock generated from the CGM goes for..,1: The clock generated from the GTM goes for.." newline bitfld.long 0x0 5. "FAST_CLR_SMC,This bit controls the clearing mechanism of the IS_NVSM[x] IS_CESM[x] and IS_OWSM[x] bits in the GISR." "0: Fast clearing is disabled (clear when written to..,1: Fast clearing is enabled." newline bitfld.long 0x0 4. "FAST_CLR_PSI5,This bit controls the clearing mechanism of bits in NDSR (in conf2 conf3 and conf4 modes) EISR (in conf2 conf3 and conf4 modes) and OWSR (in conf2 and conf3 modes)." "0: Fast Clearing Disables (clear when written to 1),1: Fast Clearing Enabled" newline bitfld.long 0x0 3. "BIT_RATE,This bit selects the receive message bit rate (T bit) for this particular PSI5 Channel that is it selects one of the two driven clocks (4MHz or 6.048MHz) in CGM." "0: 125Kbit/s bit rate selected (4MHz clock).,1: 189Kbit/s bit rate selected (6.048MHz clock)." newline bitfld.long 0x0 2. "MODE,This bit selects the operating modes." "0: Asynchronous operating mode (Integrated sync..,1: Synchronous operating modes (Integrated sync.." newline bitfld.long 0x0 1. "PSI5_CH_CONFIG,PSI5 Channel Config mode request" "0: (If PCCR[PSI5_CH_EN] =0x1: and..,1: (If PCCR[PSI5_CH_EN]=0x1: and.." newline bitfld.long 0x0 0. "PSI5_CH_EN,PSI5 Channel Enable. If this bit is cleared this particular psi5 channel continues to stay in Disable mode even if GCR[GLOBAL_DISABLE_REQ] = 0. If set it enters Configuration mode from Disable mode (based on PCCR[PSI5_CH_CONFIG]). Default.." "0: PSI5 channel continues in Disable mode.,1: PSI5 channel enabled to enter Config/Normal mode." line.long 0x4 "CH1_DCR,DMA Control Register" hexmask.long.byte 0x4 24.--28. 1. "DMA_PM_DS_WM,Value fixed by user software." newline bitfld.long 0x4 18. "IE_DMA_TF_SF,Enable for interrupt which is generated when DMA transfer finishes for DMA SMC Frame register." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x4 17. "IE_DMA_TF_PM_DS,Enable for Interrupt which is generated when DMA transfer finishes for PSI5 messages/DMA Diagnostic Status register depending on the DMA_PM_DS_CONFIG bits of the DCR." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x4 11. "IE_DMA_PM_DS_FIFO_FULL,This bit is effective only when the DMA_PM_DS_CONFIG = conf2 conf3 or conf4. It enables the FIFO FULL condition generation interrupt. For the cases that generate these FIFO FULL conditions refer to the description of.." "0,1" newline bitfld.long 0x4 10. "IE_DMA_SFUF,Enables interrupt when there is underflow in DMA SMC Frame register when DMA is enabled. It is set when the DSFR is read without a valid DMA request that is it is empty." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x4 8. "IE_DMA_PM_DS_UF,Enables interrupt when there is underflow in DMA PSI5 message register when DMA is enabled. Default value is 0. For the details as to when this underflow occurs refer to the details of IS_DMA_PM_DS_UF bit details of the DSR." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x4 2. "DMA_EN_SF,Enable DMA request for SMC Frame Data" "0: DMA for SMC frame is disabled. The six dedicated..,1: DMA for SMC frame is enabled. The six dedicated.." newline bitfld.long 0x4 0.--1. "DMA_PM_DS_CONFIG,These bits define how the PSI5 messages are stored in the MEM_DEPTH memory area and the associated diagnostic bits (EISR NDSR) are transferred." "0: conf1 The DMA request is disabled. In this mode..,1: conf2 After transferring the dma_pm_ds_wm number..,2: conf3 dma_pm_ds_wm number of PSI5 messages is..,3: conf4 Only the diagnostic bits are transferred.." line.long 0x8 "CH1_DSR,DMA Status Register" bitfld.long 0x8 18. "IS_DMA_TF_SF,This flag is set when DMA transfer finishes for DMA SMC Frame register." "0,1" newline bitfld.long 0x8 17. "IS_DMA_TF_PM_DS,This flag is set when DMA transfer finishes. For the various configurations of this request refer to the descriptions of the DMA_PM_DS_CONFIG bits in the DCR. This flag is cleared by w1c." "0,1" newline bitfld.long 0x8 11. "IS_DMA_PM_DS_FIFO_FULL,Interrupt Status when there is FIFO FULL corresponding to the DMA request ipd_psi5_dma_req_pm_ds." "0: No FIFO full.,1: FIFO full has occurred" newline bitfld.long 0x8 10. "IS_DMA_SFUF,SMC Frame DMA underflow: This happens when the DSFR has been read without a proper DMA request being asserted. The DSFR is empty and it is read. This bit is cleared by a w1c." "0: No underflow has occurred.,1: Underflow has occurred." newline bitfld.long 0x8 8. "IS_DMA_PM_DS_UF,Depending on the DMA_PM_DS_CONFIG bits following is the underflow conditions:" "0: No underflow has occurred.,1: Underflow has occurred." line.long 0xC "CH1_GICR,General Interrupt Control Register" hexmask.long.byte 0xC 24.--29. 1. "IE_CESM,Interrupt request when received SMC frame in corresponding slot has CRC failure (CRC recalculation on SMC)." newline bitfld.long 0xC 23. "IE_STS,Interrupt request enabled when the Sync Pulse Triggered Time Stamp value is refreshed on STSRR." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 22. "IE_DTS,Interrupt request enabled when the Data Start sequence Triggered Time Stamp value is refreshed on DTSRR." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 21. "IE_DSROW,Interrupt request enabled when system tries to overwrite on Data Shift register when it is not ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 20. "IE_BROW,Interrupt request enabled when system tries to overwrite on buffer register when it is not ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 19. "IE_PROW,Interrupt request enabled when system tries to overwrite on Preparation register when it is not ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 18. "IE_DSRR,Interrupt request enabled when Data Shift Register is ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 17. "IE_BRR,Interrupt request enabled when buffer Register is ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 16. "IE_PRR,Interrupt request enabled when Preparation Register ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline hexmask.long.byte 0xC 8.--13. 1. "IE_OWSM,Interrupt request enable for the SMC message Overwrite bits." newline hexmask.long.byte 0xC 0.--5. 1. "IE_NVSM,Interrupt request enabled when any new valid SMC message (fault free) is received in SFR[i]{i:0 to 5} that is during slot1 to slot6. This interrupt is generated only when corresponding IS_NVSMS[5:0] is set." line.long 0x10 "CH1_NDICR,New Data Interrupt Control Register" hexmask.long 0x10 0.--31. 1. "IE_ND,Interrupt request enabled when any new message (fault-free/with fault) is received in the RAM buffer Registerx location [x: 0 to 31] This interrupt is generated only when corresponding RAM buffer Ready with new data." line.long 0x14 "CH1_OWICR,Overwrite Interrupt Control Register" hexmask.long 0x14 0.--31. 1. "IE_OW,Interrupt request enabled when any new message overwrites the old unread PSI5 message in the RAM buffer Registerx location [x: 0 to 31] This interrupt generated only when corresponding RAM buffer Ready with new data." line.long 0x18 "CH1_EICR,Error Interrupt Control Register" hexmask.long 0x18 0.--31. 1. "IE_ERROR,Interrupt request enabled when any/all of the error conditions C E EM T or F is observed in a PSI5 message in the RAM buffer Registerx location [x: 0 to 31]. This interrupt is generated only when the corresponding RAM buffer is Ready with.." line.long 0x1C "CH1_GISR,General Interrupt Status Register" bitfld.long 0x1C 31. "IS_DEBUG_FREEZE,This flag is set to 1 when the IP enters the debug freeze mode. Please see Section1.1.3.5: Debug mode for details about the debug mode. This bit is auto cleared by the hardware when the IP exits the debug freeze mode." "0: IP not in debug freeze mode,1: IP in debug freeze mode" newline bitfld.long 0x1C 29. "IS_CESM6,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 28. "IS_CESM5,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 27. "IS_CESM4,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 26. "IS_CESM3,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 25. "IS_CESM2,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 24. "IS_CESM1,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 23. "IS_STS,This Interrupt flag is set when the Sync Pulse Triggered Time Stamp value is refreshed on STSRR." "0,1" newline bitfld.long 0x1C 22. "IS_DTS,This Interrupt flag is set when the Data Start sequence Triggered Time Stamp value is refreshed on DTSRR." "0,1" newline bitfld.long 0x1C 21. "IS_DSROW,This flag is set when the system tries to overwrite on Data Shift register when it is not ready to accept new data." "0,1" newline bitfld.long 0x1C 20. "IS_BROW,This flag is set when the system tries to overwrite on buffer register when it is not ready to accept new data." "0,1" newline bitfld.long 0x1C 19. "IS_PROW,This flag is set when the system tries to overwrite on Preparation register when it is not ready to accept new data." "0,1" newline bitfld.long 0x1C 18. "DSR_RDY,This bit acts both as a status and a control bit." "0,1" newline bitfld.long 0x1C 17. "DBR_RDY,This bit acts both as a status and a control bit." "0,1" newline bitfld.long 0x1C 16. "DPR_RDY,This bit acts both as a status and a control bit." "0,1" newline bitfld.long 0x1C 13. "IS_OWSM6,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 12. "IS_OWSM5,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 11. "IS_OWSM4,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 10. "IS_OWSM3,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 9. "IS_OWSM2,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 8. "IS_OWSM1,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 5. "IS_NVSM6,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" newline bitfld.long 0x1C 4. "IS_NVSM5,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" newline bitfld.long 0x1C 3. "IS_NVSM4,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" newline bitfld.long 0x1C 2. "IS_NVSM3,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" newline bitfld.long 0x1C 1. "IS_NVSM2,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" newline bitfld.long 0x1C 0. "IS_NVSM1,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" rgroup.long 0x1E8++0x13 line.long 0x0 "CH1_DPMR,DMA PSI5 Message Register" hexmask.long 0x0 0.--31. 1. "PSI5_RXDATA,PSI5_RXDATA[31:0]" line.long 0x4 "CH1_DSFR,DMA SMC Frame Register" hexmask.long 0x4 0.--31. 1. "SMC_RXDATA,When the DMA_EN_SF = 1 then the six SFR registers are searched in a round robin fashion for the reception of the complete SMC data. The DMA request is asserted as soon as the first encountered SFR has a complete SMC frame. This request.." line.long 0x8 "CH1_DDSR,DMA Diagnostic Status Register" hexmask.long 0x8 0.--31. 1. "DDS,This register maps each of the individual Diagnostic registers (in the order NDSR EISR) depending on the configuration of the DMA_PM_DS_CONFIG bits in the DCR. This register is a reflection of the location pointed to by the DMA read pointer." line.long 0xC "CH1_PMRRL,PSI5 Message Receive Register Low" hexmask.long 0xC 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xC 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRC[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "C,This bit will be set if CRC/P recalculation return an Error." "0,1" line.long 0x10 "CH1_PMRRH,PSI5 Message Receive Register High" bitfld.long 0x10 30. "F,This represents that NO frame was received in the corresponding configured slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error)." newline bitfld.long 0x10 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the T bit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields." newline bitfld.long 0x10 28. "E,This bit indicates electrical error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x10 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot spread across two slots started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot." newline bitfld.long 0x10 24.--26. "SLOTCOUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x10 0.--23. 1. "T1MESTAMPVALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed by.." group.long 0x1FC++0x123 line.long 0x0 "CH1_PMRL0,PSI5 Message Register Low 0" hexmask.long 0x0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x4 "CH1_PMRH0,PSI5 Message Register High 0" bitfld.long 0x4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x4 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x8 "CH1_PMRL1,PSI5 Message Register Low 1" hexmask.long 0x8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xC "CH1_PMRH1,PSI5 Message Register High 1" bitfld.long 0xC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xC 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x10 "CH1_PMRL2,PSI5 Message Register Low 2" hexmask.long 0x10 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x10 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x14 "CH1_PMRH2,PSI5 Message Register High 2" bitfld.long 0x14 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x14 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x14 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x14 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x14 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x14 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x14 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x18 "CH1_PMRL3,PSI5 Message Register Low 3" hexmask.long 0x18 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x18 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x1C "CH1_PMRH3,PSI5 Message Register High 3" bitfld.long 0x1C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x1C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x1C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x1C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x1C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x1C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x1C 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x20 "CH1_PMRL4,PSI5 Message Register Low 4" hexmask.long 0x20 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x20 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x24 "CH1_PMRH4,PSI5 Message Register High 4" bitfld.long 0x24 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x24 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x24 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x24 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x24 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x24 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x24 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x28 "CH1_PMRL5,PSI5 Message Register Low 5" hexmask.long 0x28 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x28 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x2C "CH1_PMRH5,PSI5 Message Register High 5" bitfld.long 0x2C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x2C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x2C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x2C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x2C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x2C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x2C 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x30 "CH1_PMRL6,PSI5 Message Register Low 6" hexmask.long 0x30 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x30 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x34 "CH1_PMRH6,PSI5 Message Register High 6" bitfld.long 0x34 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x34 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x34 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x34 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x34 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x34 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x34 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x38 "CH1_PMRL7,PSI5 Message Register Low 7" hexmask.long 0x38 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x38 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x3C "CH1_PMRH7,PSI5 Message Register High 7" bitfld.long 0x3C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x3C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x3C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x3C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x3C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x3C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x3C 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x40 "CH1_PMRL8,PSI5 Message Register Low 8" hexmask.long 0x40 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x40 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x44 "CH1_PMRH8,PSI5 Message Register High 8" bitfld.long 0x44 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x44 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x44 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x44 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x44 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x44 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x44 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x48 "CH1_PMRL9,PSI5 Message Register Low 9" hexmask.long 0x48 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x48 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x4C "CH1_PMRH9,PSI5 Message Register High 9" bitfld.long 0x4C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x4C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x4C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x4C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x4C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x4C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x4C 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x50 "CH1_PMRL10,PSI5 Message Register Low 10" hexmask.long 0x50 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x50 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x54 "CH1_PMRH10,PSI5 Message Register High 10" bitfld.long 0x54 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x54 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x54 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x54 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x54 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x54 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x54 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x58 "CH1_PMRL11,PSI5 Message Register Low 11" hexmask.long 0x58 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x58 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x5C "CH1_PMRH11,PSI5 Message Register High 11" bitfld.long 0x5C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x5C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x5C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x5C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x5C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x5C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x5C 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x60 "CH1_PMRL12,PSI5 Message Register Low 12" hexmask.long 0x60 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x60 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x64 "CH1_PMRH12,PSI5 Message Register High 12" bitfld.long 0x64 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x64 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x64 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x64 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x64 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x64 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x64 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x68 "CH1_PMRL13,PSI5 Message Register Low 13" hexmask.long 0x68 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x68 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x6C "CH1_PMRH13,PSI5 Message Register High 13" bitfld.long 0x6C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x6C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x6C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x6C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x6C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x6C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x6C 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x70 "CH1_PMRL14,PSI5 Message Register Low 14" hexmask.long 0x70 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x70 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x74 "CH1_PMRH14,PSI5 Message Register High 14" bitfld.long 0x74 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x74 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x74 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x74 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x74 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x74 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x74 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x78 "CH1_PMRL15,PSI5 Message Register Low 15" hexmask.long 0x78 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x78 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x7C "CH1_PMRH15,PSI5 Message Register High 15" bitfld.long 0x7C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x7C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x7C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x7C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x7C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x7C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x7C 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x80 "CH1_PMRL16,PSI5 Message Register Low 16" hexmask.long 0x80 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x80 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x84 "CH1_PMRH16,PSI5 Message Register High 16" bitfld.long 0x84 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x84 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x84 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x84 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x84 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x84 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x84 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x88 "CH1_PMRL17,PSI5 Message Register Low 17" hexmask.long 0x88 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x88 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x8C "CH1_PMRH17,PSI5 Message Register High 17" bitfld.long 0x8C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x8C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x8C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x8C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x8C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x8C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x8C 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x90 "CH1_PMRL18,PSI5 Message Register Low 18" hexmask.long 0x90 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x90 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x94 "CH1_PMRH18,PSI5 Message Register High 18" bitfld.long 0x94 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x94 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x94 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x94 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x94 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x94 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x94 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x98 "CH1_PMRL19,PSI5 Message Register Low 19" hexmask.long 0x98 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x98 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x9C "CH1_PMRH19,PSI5 Message Register High 19" bitfld.long 0x9C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x9C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x9C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x9C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x9C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x9C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x9C 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xA0 "CH1_PMRL20,PSI5 Message Register Low 20" hexmask.long 0xA0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xA0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xA4 "CH1_PMRH20,PSI5 Message Register High 20" bitfld.long 0xA4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xA4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xA4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xA4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xA4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xA4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xA4 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xA8 "CH1_PMRL21,PSI5 Message Register Low 21" hexmask.long 0xA8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xA8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xAC "CH1_PMRH21,PSI5 Message Register High 21" bitfld.long 0xAC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xAC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xAC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xAC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xAC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xAC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xAC 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xB0 "CH1_PMRL22,PSI5 Message Register Low 22" hexmask.long 0xB0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data framesfor more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the PSI5.." newline bitfld.long 0xB0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xB4 "CH1_PMRH22,PSI5 Message Register High 22" bitfld.long 0xB4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xB4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xB4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xB4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xB4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xB4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xB4 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xB8 "CH1_PMRL23,PSI5 Message Register Low 23" hexmask.long 0xB8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data framesfor more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the PSI5.." newline bitfld.long 0xB8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xBC "CH1_PMRH23,PSI5 Message Register High 23" bitfld.long 0xBC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xBC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xBC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xBC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xBC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xBC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xBC 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xC0 "CH1_PMRL24,PSI5 Message Register Low 24" hexmask.long 0xC0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xC0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xC4 "CH1_PMRH24,PSI5 Message Register High 24" bitfld.long 0xC4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xC4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xC4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xC4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xC4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xC4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xC4 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xC8 "CH1_PMRL25,PSI5 Message Register Low 25" hexmask.long 0xC8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xC8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xCC "CH1_PMRH25,PSI5 Message Register High 25" bitfld.long 0xCC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xCC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xCC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xCC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xCC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xCC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xCC 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xD0 "CH1_PMRL26,PSI5 Message Register Low 26" hexmask.long 0xD0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xD0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xD4 "CH1_PMRH26,PSI5 Message Register High 26" bitfld.long 0xD4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xD4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xD4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xD4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xD4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xD4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xD4 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xD8 "CH1_PMRL27,PSI5 Message Register Low 27" hexmask.long 0xD8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xD8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xDC "CH1_PMRH27,PSI5 Message Register High 27" bitfld.long 0xDC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xDC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xDC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xDC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xDC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xDC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xDC 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xE0 "CH1_PMRL28,PSI5 Message Register Low 28" hexmask.long 0xE0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xE0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xE4 "CH1_PMRH28,PSI5 Message Register High 28" bitfld.long 0xE4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xE4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xE4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xE4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xE4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xE4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xE4 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xE8 "CH1_PMRL29,PSI5 Message Register Low 29" hexmask.long 0xE8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xE8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xEC "CH1_PMRH29,PSI5 Message Register High 29" bitfld.long 0xEC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xEC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xEC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xEC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xEC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xEC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xEC 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xF0 "CH1_PMRL30,PSI5 Message Register Low 30" hexmask.long 0xF0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xF0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xF4 "CH1_PMRH30,PSI5 Message Register High 30" bitfld.long 0xF4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xF4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xF4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xF4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xF4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xF4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xF4 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xF8 "CH1_PMRL31,PSI5 Message Register Low 31" hexmask.long 0xF8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xF8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xFC "CH1_PMRH31,PSI5 Message Register High 31" bitfld.long 0xFC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xFC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xFC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xFC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xFC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xFC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xFC 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x100 "CH1_SFR1,SMC Frame Register 1" bitfld.long 0x100 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the correct.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x100 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x100 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x100 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x100 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x100 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x100 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x100 0.--11. 1. "DATA,DATA payload" line.long 0x104 "CH1_SFR2,SMC Frame Register 2" bitfld.long 0x104 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the correct.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x104 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x104 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x104 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x104 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x104 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x104 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x104 0.--11. 1. "DATA,DATA payload" line.long 0x108 "CH1_SFR3,SMC Frame Register 3" bitfld.long 0x108 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the correct.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x108 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x108 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x108 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x108 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x108 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x108 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x108 0.--11. 1. "DATA,DATA payload" line.long 0x10C "CH1_SFR4,SMC Frame Register 4" bitfld.long 0x10C 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the correct.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10C 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x10C 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x10C 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x10C 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x10C 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x10C 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x10C 0.--11. 1. "DATA,DATA payload" line.long 0x110 "CH1_SFR5,SMC Frame Register 5" bitfld.long 0x110 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x110 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x110 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x110 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x110 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x110 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x110 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x110 0.--11. 1. "DATA,DATA payload" line.long 0x114 "CH1_SFR6,SMC Frame Register 6" bitfld.long 0x114 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the correct.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x114 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x114 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x114 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x114 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x114 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x114 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x114 0.--11. 1. "DATA,DATA payload" line.long 0x118 "CH1_NDSR,New Data Status Register" hexmask.long 0x118 0.--31. 1. "NDS,New Data Status flags for PSI5 Messages corresponding to each PSI5 MB locations." line.long 0x11C "CH1_OWSR,Overwrite Status Register" hexmask.long 0x11C 0.--31. 1. "OWS,Over Write Status flags for PSI5 Messages corresponding to each PSI5 location in the RAM registers." line.long 0x120 "CH1_EISR,Error Indication Status Register" hexmask.long 0x120 0.--31. 1. "ERROR,Error Status flags for PSI5 Messages corresponding to each PSI5 MB locations." wgroup.long 0x320++0x3 line.long 0x0 "CH1_SNDSR,Set New Data Status Register" hexmask.long 0x0 0.--31. 1. "SNDS,Sets New Data Status flags for PSI5 Messages corresponding to each PSI5 MB locations." group.long 0x324++0x3 line.long 0x0 "CH1_SOWSR,Set Overwrite Status Register" hexmask.long 0x0 0.--31. 1. "SOWS,Sets overwrite status flags for PSI5 messages corresponding to each PSI5 MB locations." wgroup.long 0x328++0x7 line.long 0x0 "CH1_SEISR,Set Error Status Register" hexmask.long 0x0 0.--31. 1. "SERROR,Sets Error Status flags for PSI5 messages corresponding to each PSI5 MB locations." line.long 0x4 "CH1_SSESR,Set SMC Error Status Register" hexmask.long.byte 0x4 24.--29. 1. "SCESM,Sets IS_CESM Status flags for SMC Messages corresponding to each SMC MB locations." newline hexmask.long.byte 0x4 8.--13. 1. "SOWSM,Sets IS_OWSM Status flags for SMC Messages corresponding to each SMC MB locations." newline hexmask.long.byte 0x4 0.--5. 1. "SNVSM,Sets IS_NVSM Status flags for SMC Messages corresponding to each SMC MB locations." rgroup.long 0x330++0x7 line.long 0x0 "CH1_STSRR,Sync Time Stamp Read Register" hexmask.long.tbyte 0x0 0.--23. 1. "STSV,Sync Time Stamp Value[23:0]" line.long 0x4 "CH1_DTSRR,Data Time Stamp Read Register" bitfld.long 0x4 24.--26. "SLOT_COUNTER,3-bit Slot Counter which corresponds to the slot for which the DTSRR contains the Time Stamp. The slot_counter contains the slot in which the start bits of this frame was captured (after successful detection of S1). If the start bits get.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x4 0.--23. 1. "DTSV,Data Time Stamp Value[23:0]" group.long 0x338++0x17 line.long 0x0 "CH1_S1FCR,Slot 1 Frame Configuration Register" bitfld.long 0x0 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0x0 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0x0 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0x0 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0x0 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." line.long 0x4 "CH1_S2FCR,Slot 2 Frame Configuration Register" bitfld.long 0x4 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0x4 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0x4 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0x4 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0x4 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." line.long 0x8 "CH1_S3FCR,Slot 3 Frame Configuration Register" bitfld.long 0x8 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0x8 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0x8 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0x8 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0x8 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." line.long 0xC "CH1_S4FCR,Slot 4 Frame Configuration Register" bitfld.long 0xC 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0xC 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0xC 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0xC 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0xC 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." line.long 0x10 "CH1_S5FCR,Slot 5 Frame Configuration Register" bitfld.long 0x10 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0x10 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0x10 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0x10 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0x10 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." line.long 0x14 "CH1_S6FCR,Slot 6 Frame Configuration Register" bitfld.long 0x14 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0x14 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0x14 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0x14 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0x14 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." rgroup.word 0x350++0xB line.word 0x0 "CH1_S2SBR,Slot 2 Start Boundary Register" hexmask.word 0x0 0.--14. 1. "S2SBT,Slot 2 Start Boundary Time" line.word 0x2 "CH1_S1SBR,Slot 1 Start Boundary Register" hexmask.word 0x2 0.--14. 1. "S1SBT,Slot 0x1: Start Boundary Time" line.word 0x4 "CH1_S4SBR,Slot 4 Start Boundary Register" hexmask.word 0x4 0.--14. 1. "S4SBT,Slot 4 Start Boundary Time" line.word 0x6 "CH1_S3SBR,Slot 3 Start Boundary Register" hexmask.word 0x6 0.--14. 1. "S3SBT,Slot 3 Start Boundary Time" line.word 0x8 "CH1_S6SBR,Slot 6 Start Boundary Register" hexmask.word 0x8 0.--14. 1. "S6SBT,Slot 6 Start Boundary Time" line.word 0xA "CH1_S5SBR,Slot 5 Start Boundary Register" hexmask.word 0xA 0.--14. 1. "S5SBT,Slot 5 Start Boundary Time" group.long 0x35C++0x3 line.long 0x0 "CH1_SNEBR,Slot n End Boundary Register" bitfld.long 0x0 16.--18. "SLOT_NO,The field indicates the Slot number{16} for which Slot End Boundary Time is defined." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--14. 1. "SNEBT,Slot n End Boundary Time" group.word 0x360++0xB line.word 0x0 "CH1_MDDIS_OFF,Manchester Decoder Disable Offset Register" hexmask.word.byte 0x0 0.--6. 1. "MDDIS_OFF,These 7 bits can be used to program the time for which the Manchester decoder remains disabled. This offset is added AFTER the falling edge of the sync pulse. Thus the total time for which the Manchester decoder remains disabled = TsyncH +.." line.word 0x2 "CH1_DOBCR,Data Output Block Configuration Register" hexmask.word.byte 0x2 10.--15. 1. "DATA_LENGTH,Can take on values from 0 to 63 corresponding to 1 bit to 64 bit non standard length commands." newline bitfld.word 0x2 9. "DBR_RST,This is to reset and reject current content to Data Buffer Register. When this bit is written as 1 then the contents of the DBR are reset to all 0s (if DEFAULT_SYNC= = 0) or all 1s (if DEFAULT_SYNC == 1). As soon as content is reset the DBR would.." "0,1" newline bitfld.word 0x2 8. "DSR_RST,This is to reset and reject current content to Data Shift Register.When this bit is written as 1 then the contents of the DSR are reset to all 0s (if DEFAULT_SYNC= = 0) or all 1s (if DEFAULT_SYNC == 1). As soon as content is reset the DSR would.." "0,1" newline bitfld.word 0x2 5.--7. "CMD_TYPE,These 3 bits indicate the type of command that needs to be transmitted during the ECU to sensor communication. Table2061 is a brief description of the same." "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 4. "DEFAULT_SYNC,When this bit is set to 0 then the default value of DSR and DBR registers are all 0s; when this bit is set to 1 then the default value of DBR and DSR registers are all 1s." "0,1" newline bitfld.word 0x2 3. "GTM_TRIG_SEL,GTM event triggered/internal sync pulse generator selection as shift clock for the DSR." "0: Internal sync pulse generator shift triggered,1: GTM event shift triggered" newline bitfld.word 0x2 2. "SP_PULSE_SEL,Selects the source for the short pulse PWM module:" "0: SP module gets the data from the DSR,1: SP module directly gets input from the.." newline bitfld.word 0x2 1. "OP_SEL,This bit selects the driving source of the ipp_do_psi5_sdout port." "0: The sync pulse generator select as per the..,1: PWM output" newline bitfld.word 0x2 0. "SW_READY,When this bit is written to 1 the transfer from DBR to DSR automatically happens as soon as DSR_RDY becomes 1. When this bit is kept to 0 then the transfer from DBR to DSR will remain pending. Once the software makes this bit as 1 and DSR_RDY.." "0,1" line.word 0x4 "CH1_PW1D,Pulse Width for Data Bit 1 Register" hexmask.word.byte 0x4 0.--6. 1. "PULSE_W1DTH1,This defines the width (in microsesc) of data value0x1: to be sent from Data Output Register. It is the number of clock cycles (1 microsesc clock) counted up to width Pulse_Width1; starting as soon as trigger appears from the ISPG(Internal.." line.word 0x6 "CH1_PW0D,Pulse Width for Data Bit 0 Register" hexmask.word.byte 0x6 0.--6. 1. "PULSE_W1DTH0,This defines the width (in microsesc) of data value0x0: to be sent from Data Output Register. It is the number of clock cycles (1 microsesc clock) counted up to width Pulse_Width0; starting as soon as trigger appears from the ISPG (Internal.." line.word 0x8 "CH1_CIPR,Counter Initialize Pulse Register" hexmask.word 0x8 0.--15. 1. "CIPR,Counter initialization pulse register" line.word 0xA "CH1_CTPR,Counter Target Pulse Register" hexmask.word 0xA 0.--15. 1. "CTPR,Counter Target Pulse Register" group.long 0x36C++0x3 line.long 0x0 "CH1_DPRL,Data Preparation Register Low" hexmask.long.tbyte 0x0 0.--23. 1. "DPR,DPR[23:0] are the 24-bits of the DPR register used for writing the variable length standard ECU-to-Sensor commands comprising of the address data and other fields. Note that the IP is transparent to the arrangement of the address data and other.." rgroup.long 0x370++0x3 line.long 0x0 "CH1_DPRH,Data Preparation Register High" group.long 0x374++0xF line.long 0x0 "CH1_DBRL,Data Buffer Register Low" hexmask.long 0x0 0.--31. 1. "DBR,This register contains the Lower 32 bits(DBR[31:0]) of the max-64 bit length command (DBR[63:0]). The higher bits DBR[63:32] are contained in the DBRH register." line.long 0x4 "CH1_DBRH,Data Buffer Register High" hexmask.long 0x4 0.--31. 1. "DBR,This register contains the Upper 32 bits(DBR[63:32]) of the max-64 bit length command (DBR[63:0]). The lower bits DBR[31:0] are contained in the DBRL register." line.long 0x8 "CH1_DSRL,Data Shift Register Low" hexmask.long 0x8 0.--31. 1. "DSR,These bits can be updated by the hardware or can be written by the CPU. The number of accessible bits in DSR are always equal to the number of accessible bits in DBR which in turn depend on the value of PSI5_DOBCR[CMD_TYPE] register bits.When these.." line.long 0xC "CH1_DSRH,Data Shift Register High" hexmask.long 0xC 0.--31. 1. "DSR,These bits can be updated by the hardware or can be written by the CPU. The number of accessible bits in DSR are always equal to the number of accessible bits in DBR which in turn depend on the value of PSI5_DOBCR[CMD_TYPE] register bits. When these.." tree.end tree "PSI5_1" base ad:0x714F8000 group.long 0x8++0x1F line.long 0x0 "CH0_PCCR,PSI5 Channel Control Register" bitfld.long 0x0 31. "CTC_GED_SEL,Channel Target Counter Global Enable/Disable Select" "0: CTC enabled disabled by CTC_ED.,1: CTC enabled/disabled by CTC_GED." newline bitfld.long 0x0 30. "CTC_ED,Channel Target Counter Enable/Disable" "0: The CTC counters is disabled and reset.,1: The CTC counter is enabled and start counting." newline hexmask.long.byte 0x0 24.--28. 1. "MEM_DEPTH,Can be programmed from 0 to 31 and denotes the size of the memory that should be used for storing the PSI5 messages. Area above the MEM_DEPTH is treated as being unavailable for message storage." newline bitfld.long 0x0 20. "ERROR_SELECT4,The ERROR_SELECT bitfield indicates which of the C E EM T or F error conditions generate an interrupt when the EICR Interrupt Enable bit is set. The individual bits are mapped as {C E EM T F}. The corresponding error is also latched in.." "0: The C bit does not generate an interrupt.,1: The C bit generates an interrupt." newline bitfld.long 0x0 19. "ERROR_SELECT3,Error_Select[3] or E_INT_SEL" "0: The E bit does not generate an interrupt.,1: The E bit generates an interrupt." newline bitfld.long 0x0 18. "ERROR_SELECT2,Error_Select[2] or EM_INT_SEL" "0: The EM bit does not generate an interrupt.,1: The EM bit generates an interrupt." newline bitfld.long 0x0 17. "ERROR_SELECT1,Error_Select[1] or T_INT_SEL" "0: The T bit does not generate an interrupt.,1: The T bit generates an interrupt." newline bitfld.long 0x0 16. "ERROR_SELECT0,Error_Select[0] or F_INT_SEL" "0: The F bit does not generate an interrupt.,1: The F bit generates an interrupt." newline bitfld.long 0x0 14. "GTM_RESET_ASYNC_EN,GTM_RESET_ASYNC_EN" "0: Both the assertion and the deassertion of the..,1: Assertion of the GTM reset is treated.." newline bitfld.long 0x0 10. "DEBUG_EN,This bit allows/prevents the IP from entering the debug mode whenever the debugger is connected and a breakpoint is encountered by the debugger:" "0: The IP never enters the debug mode even if the..,1: Whenever the debugger is connected and a.." newline bitfld.long 0x0 9. "DEBUG_FREEZE_CTRL,Note: In the above configuration the status of registers read through the debugger may be different when entering debug mode and when actually accessing registers at some later point of time." "0: When the IP enters the Debug mode then it goes..,1: When the IP enters the Debug mode then it goes.." newline bitfld.long 0x0 8. "SP_TS_CLK_SEL,This bit controls which clock goes to the Sync Pulse and Time Stamp Generator Unit." "0: The 1MHz clock generated from the CGM goes for..,1: The clock generated from the GTM goes for.." newline bitfld.long 0x0 5. "FAST_CLR_SMC,This bit controls the clearing mechanism of the IS_NVSM[x] IS_CESM[x] and IS_OWSM[x] bits in the GISR." "0: Fast clearing is disabled (clear when written to..,1: Fast clearing is enabled." newline bitfld.long 0x0 4. "FAST_CLR_PSI5,This bit controls the clearing mechanism of bits in NDSR (in conf2 conf3 and conf4 modes) EISR (in conf2 conf3 and conf4 modes) and OWSR (in conf2 and conf3 modes)." "0: Fast Clearing Disables (clear when written to 1),1: Fast Clearing Enabled" newline bitfld.long 0x0 3. "BIT_RATE,This bit selects the receive message bit rate (T bit) for this particular PSI5 Channel that is it selects one of the two driven clocks (4MHz or 6.048MHz) in CGM." "0: 125Kbit/s bit rate selected (4MHz clock).,1: 189Kbit/s bit rate selected (6.048MHz clock)." newline bitfld.long 0x0 2. "MODE,This bit selects the operating modes." "0: Asynchronous operating mode (Integrated sync..,1: Synchronous operating modes (Integrated sync.." newline bitfld.long 0x0 1. "PSI5_CH_CONFIG,PSI5 Channel Config mode request" "0: (If PCCR[PSI5_CH_EN] =0x1: and..,1: (If PCCR[PSI5_CH_EN]=0x1: and.." newline bitfld.long 0x0 0. "PSI5_CH_EN,PSI5 Channel Enable. If this bit is cleared this particular psi5 channel continues to stay in Disable mode even if GCR[GLOBAL_DISABLE_REQ] = 0. If set it enters Configuration mode from Disable mode (based on PCCR[PSI5_CH_CONFIG]). Default.." "0: PSI5 channel continues in Disable mode.,1: PSI5 channel enabled to enter Config/Normal mode." line.long 0x4 "CH0_DCR,DMA Control Register" hexmask.long.byte 0x4 24.--28. 1. "DMA_PM_DS_WM,Value fixed by user software." newline bitfld.long 0x4 18. "IE_DMA_TF_SF,Enable for interrupt which is generated when DMA transfer finishes for DMA SMC Frame register." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x4 17. "IE_DMA_TF_PM_DS,Enable for Interrupt which is generated when DMA transfer finishes for PSI5 messages/DMA Diagnostic Status register depending on the DMA_PM_DS_CONFIG bits of the DCR." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x4 11. "IE_DMA_PM_DS_FIFO_FULL,This bit is effective only when the DMA_PM_DS_CONFIG = conf2 conf3 or conf4. It enables the FIFO FULL condition generation interrupt. For the cases that generate these FIFO FULL conditions refer to the description of.." "0,1" newline bitfld.long 0x4 10. "IE_DMA_SFUF,Enables interrupt when there is underflow in DMA SMC Frame register when DMA is enabled. It is set when the DSFR is read without a valid DMA request that is it is empty." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x4 8. "IE_DMA_PM_DS_UF,Enables interrupt when there is underflow in DMA PSI5 message register when DMA is enabled. Default value is 0. For the details as to when this underflow occurs refer to the details of IS_DMA_PM_DS_UF bit details of the DSR." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x4 2. "DMA_EN_SF,Enable DMA request for SMC Frame Data" "0: DMA for SMC frame is disabled. The six dedicated..,1: DMA for SMC frame is enabled. The six dedicated.." newline bitfld.long 0x4 0.--1. "DMA_PM_DS_CONFIG,These bits define how the PSI5 messages are stored in the MEM_DEPTH memory area and the associated diagnostic bits (EISR NDSR) are transferred." "0: conf1 The DMA request is disabled. In this mode..,1: conf2 After transferring the dma_pm_ds_wm number..,2: conf3 dma_pm_ds_wm number of PSI5 messages is..,3: conf4 Only the diagnostic bits are transferred.." line.long 0x8 "CH0_DSR,DMA Status Register" bitfld.long 0x8 18. "IS_DMA_TF_SF,This flag is set when DMA transfer finishes for DMA SMC Frame register." "0,1" newline bitfld.long 0x8 17. "IS_DMA_TF_PM_DS,This flag is set when DMA transfer finishes. For the various configurations of this request refer to the descriptions of the DMA_PM_DS_CONFIG bits in the DCR. This flag is cleared by w1c." "0,1" newline bitfld.long 0x8 11. "IS_DMA_PM_DS_FIFO_FULL,Interrupt Status when there is FIFO FULL corresponding to the DMA request ipd_psi5_dma_req_pm_ds." "0: No FIFO full.,1: FIFO full has occurred" newline bitfld.long 0x8 10. "IS_DMA_SFUF,SMC Frame DMA underflow: This happens when the DSFR has been read without a proper DMA request being asserted. The DSFR is empty and it is read. This bit is cleared by a w1c." "0: No underflow has occurred.,1: Underflow has occurred." newline bitfld.long 0x8 8. "IS_DMA_PM_DS_UF,Depending on the DMA_PM_DS_CONFIG bits following is the underflow conditions:" "0: No underflow has occurred.,1: Underflow has occurred." line.long 0xC "CH0_GICR,General Interrupt Control Register" hexmask.long.byte 0xC 24.--29. 1. "IE_CESM,Interrupt request when received SMC frame in corresponding slot has CRC failure (CRC recalculation on SMC)." newline bitfld.long 0xC 23. "IE_STS,Interrupt request enabled when the Sync Pulse Triggered Time Stamp value is refreshed on STSRR." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 22. "IE_DTS,Interrupt request enabled when the Data Start sequence Triggered Time Stamp value is refreshed on DTSRR." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 21. "IE_DSROW,Interrupt request enabled when system tries to overwrite on Data Shift register when it is not ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 20. "IE_BROW,Interrupt request enabled when system tries to overwrite on buffer register when it is not ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 19. "IE_PROW,Interrupt request enabled when system tries to overwrite on Preparation register when it is not ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 18. "IE_DSRR,Interrupt request enabled when Data Shift Register is ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 17. "IE_BRR,Interrupt request enabled when buffer Register is ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 16. "IE_PRR,Interrupt request enabled when Preparation Register ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline hexmask.long.byte 0xC 8.--13. 1. "IE_OWSM,Interrupt request enable for the SMC message Overwrite bits." newline hexmask.long.byte 0xC 0.--5. 1. "IE_NVSM,Interrupt request enabled when any new valid SMC message (fault free) is received in SFR[i]{i:0 to 5} that is during slot1 to slot6. This interrupt is generated only when corresponding IS_NVSMS[5:0] is set." line.long 0x10 "CH0_NDICR,New Data Interrupt Control Register" hexmask.long 0x10 0.--31. 1. "IE_ND,Interrupt request enabled when any new message (fault-free/with fault) is received in the RAM buffer Registerx location [x: 0 to 31] This interrupt is generated only when corresponding RAM buffer Ready with new data." line.long 0x14 "CH0_OWICR,Overwrite Interrupt Control Register" hexmask.long 0x14 0.--31. 1. "IE_OW,Interrupt request enabled when any new message overwrites the old unread PSI5 message in the RAM buffer Registerx location [x: 0 to 31] This interrupt generated only when corresponding RAM buffer Ready with new data." line.long 0x18 "CH0_EICR,Error Interrupt Control Register" hexmask.long 0x18 0.--31. 1. "IE_ERROR,Interrupt request enabled when any/all of the error conditions C E EM T or F is observed in a PSI5 message in the RAM buffer Registerx location [x: 0 to 31]. This interrupt is generated only when the corresponding RAM buffer is Ready with.." line.long 0x1C "CH0_GISR,General Interrupt Status Register" bitfld.long 0x1C 31. "IS_DEBUG_FREEZE,This flag is set to 1 when the IP enters the debug freeze mode. Please see Section1.1.3.5: Debug mode for details about the debug mode. This bit is auto cleared by the hardware when the IP exits the debug freeze mode." "0: IP not in debug freeze mode,1: IP in debug freeze mode" newline bitfld.long 0x1C 29. "IS_CESM6,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 28. "IS_CESM5,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 27. "IS_CESM4,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 26. "IS_CESM3,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 25. "IS_CESM2,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 24. "IS_CESM1,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 23. "IS_STS,This Interrupt flag is set when the Sync Pulse Triggered Time Stamp value is refreshed on STSRR." "0,1" newline bitfld.long 0x1C 22. "IS_DTS,This Interrupt flag is set when the Data Start sequence Triggered Time Stamp value is refreshed on DTSRR." "0,1" newline bitfld.long 0x1C 21. "IS_DSROW,This flag is set when the system tries to overwrite on Data Shift register when it is not ready to accept new data." "0,1" newline bitfld.long 0x1C 20. "IS_BROW,This flag is set when the system tries to overwrite on buffer register when it is not ready to accept new data." "0,1" newline bitfld.long 0x1C 19. "IS_PROW,This flag is set when the system tries to overwrite on Preparation register when it is not ready to accept new data." "0,1" newline bitfld.long 0x1C 18. "DSR_RDY,This bit acts both as a status and a control bit." "0,1" newline bitfld.long 0x1C 17. "DBR_RDY,This bit acts both as a status and a control bit." "0,1" newline bitfld.long 0x1C 16. "DPR_RDY,This bit acts both as a status and a control bit." "0,1" newline bitfld.long 0x1C 13. "IS_OWSM6,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 12. "IS_OWSM5,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 11. "IS_OWSM4,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 10. "IS_OWSM3,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 9. "IS_OWSM2,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 8. "IS_OWSM1,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 5. "IS_NVSM6,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" newline bitfld.long 0x1C 4. "IS_NVSM5,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" newline bitfld.long 0x1C 3. "IS_NVSM4,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" newline bitfld.long 0x1C 2. "IS_NVSM3,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" newline bitfld.long 0x1C 1. "IS_NVSM2,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" newline bitfld.long 0x1C 0. "IS_NVSM1,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" rgroup.long 0x28++0x13 line.long 0x0 "CH0_DPMR,DMA PSI5 Message Register" hexmask.long 0x0 0.--31. 1. "PSI5_RXDATA,PSI5_RXDATA[31:0]" line.long 0x4 "CH0_DSFR,DMA SMC Frame Register" hexmask.long 0x4 0.--31. 1. "SMC_RXDATA,When the DMA_EN_SF = 1 then the six SFR registers are searched in a round robin fashion for the reception of the complete SMC data. The DMA request is asserted as soon as the first encountered SFR has a complete SMC frame. This request.." line.long 0x8 "CH0_DDSR,DMA Diagnostic Status Register" hexmask.long 0x8 0.--31. 1. "DDS,This register maps each of the individual Diagnostic registers (in the order NDSR EISR) depending on the configuration of the DMA_PM_DS_CONFIG bits in the DCR. This register is a reflection of the location pointed to by the DMA read pointer." line.long 0xC "CH0_PMRRL,PSI5 Message Receive Register Low" hexmask.long 0xC 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xC 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRC[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "C,This bit will be set if CRC/P recalculation return an Error." "0,1" line.long 0x10 "CH0_PMRRH,PSI5 Message Receive Register High" bitfld.long 0x10 30. "F,This represents that NO frame was received in the corresponding configured slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error)." newline bitfld.long 0x10 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the T bit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields." newline bitfld.long 0x10 28. "E,This bit indicates electrical error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x10 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot spread across two slots started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot." newline bitfld.long 0x10 24.--26. "SLOTCOUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x10 0.--23. 1. "T0MESTAMPVALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed by.." group.long 0x3C++0x123 line.long 0x0 "CH0_PMRL0,PSI5 Message Register Low 0" hexmask.long 0x0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x4 "CH0_PMRH0,PSI5 Message Register High 0" bitfld.long 0x4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x4 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x8 "CH0_PMRL1,PSI5 Message Register Low 1" hexmask.long 0x8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xC "CH0_PMRH1,PSI5 Message Register High 1" bitfld.long 0xC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xC 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x10 "CH0_PMRL2,PSI5 Message Register Low 2" hexmask.long 0x10 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x10 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x14 "CH0_PMRH2,PSI5 Message Register High 2" bitfld.long 0x14 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x14 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x14 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x14 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x14 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x14 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x14 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x18 "CH0_PMRL3,PSI5 Message Register Low 3" hexmask.long 0x18 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x18 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x1C "CH0_PMRH3,PSI5 Message Register High 3" bitfld.long 0x1C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x1C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x1C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x1C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x1C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x1C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x1C 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x20 "CH0_PMRL4,PSI5 Message Register Low 4" hexmask.long 0x20 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x20 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x24 "CH0_PMRH4,PSI5 Message Register High 4" bitfld.long 0x24 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x24 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x24 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x24 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x24 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x24 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x24 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x28 "CH0_PMRL5,PSI5 Message Register Low 5" hexmask.long 0x28 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x28 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x2C "CH0_PMRH5,PSI5 Message Register High 5" bitfld.long 0x2C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x2C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x2C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x2C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x2C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x2C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x2C 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x30 "CH0_PMRL6,PSI5 Message Register Low 6" hexmask.long 0x30 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x30 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x34 "CH0_PMRH6,PSI5 Message Register High 6" bitfld.long 0x34 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x34 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x34 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x34 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x34 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x34 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x34 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x38 "CH0_PMRL7,PSI5 Message Register Low 7" hexmask.long 0x38 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x38 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x3C "CH0_PMRH7,PSI5 Message Register High 7" bitfld.long 0x3C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x3C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x3C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x3C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x3C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x3C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x3C 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x40 "CH0_PMRL8,PSI5 Message Register Low 8" hexmask.long 0x40 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x40 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x44 "CH0_PMRH8,PSI5 Message Register High 8" bitfld.long 0x44 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x44 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x44 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x44 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x44 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x44 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x44 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x48 "CH0_PMRL9,PSI5 Message Register Low 9" hexmask.long 0x48 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x48 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x4C "CH0_PMRH9,PSI5 Message Register High 9" bitfld.long 0x4C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x4C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x4C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x4C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x4C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x4C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x4C 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x50 "CH0_PMRL10,PSI5 Message Register Low 10" hexmask.long 0x50 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x50 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x54 "CH0_PMRH10,PSI5 Message Register High 10" bitfld.long 0x54 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x54 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x54 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x54 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x54 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x54 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x54 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x58 "CH0_PMRL11,PSI5 Message Register Low 11" hexmask.long 0x58 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x58 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x5C "CH0_PMRH11,PSI5 Message Register High 11" bitfld.long 0x5C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x5C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x5C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x5C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x5C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x5C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x5C 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x60 "CH0_PMRL12,PSI5 Message Register Low 12" hexmask.long 0x60 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x60 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x64 "CH0_PMRH12,PSI5 Message Register High 12" bitfld.long 0x64 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x64 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x64 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x64 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x64 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x64 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x64 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x68 "CH0_PMRL13,PSI5 Message Register Low 13" hexmask.long 0x68 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x68 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x6C "CH0_PMRH13,PSI5 Message Register High 13" bitfld.long 0x6C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x6C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x6C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x6C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x6C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x6C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x6C 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x70 "CH0_PMRL14,PSI5 Message Register Low 14" hexmask.long 0x70 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x70 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x74 "CH0_PMRH14,PSI5 Message Register High 14" bitfld.long 0x74 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x74 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x74 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x74 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x74 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x74 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x74 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x78 "CH0_PMRL15,PSI5 Message Register Low 15" hexmask.long 0x78 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x78 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x7C "CH0_PMRH15,PSI5 Message Register High 15" bitfld.long 0x7C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x7C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x7C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x7C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x7C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x7C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x7C 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x80 "CH0_PMRL16,PSI5 Message Register Low 16" hexmask.long 0x80 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x80 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x84 "CH0_PMRH16,PSI5 Message Register High 16" bitfld.long 0x84 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x84 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x84 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x84 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x84 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x84 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x84 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x88 "CH0_PMRL17,PSI5 Message Register Low 17" hexmask.long 0x88 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x88 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x8C "CH0_PMRH17,PSI5 Message Register High 17" bitfld.long 0x8C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x8C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x8C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x8C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x8C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x8C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x8C 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x90 "CH0_PMRL18,PSI5 Message Register Low 18" hexmask.long 0x90 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x90 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x94 "CH0_PMRH18,PSI5 Message Register High 18" bitfld.long 0x94 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x94 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x94 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x94 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x94 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x94 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x94 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x98 "CH0_PMRL19,PSI5 Message Register Low 19" hexmask.long 0x98 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x98 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x9C "CH0_PMRH19,PSI5 Message Register High 19" bitfld.long 0x9C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x9C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x9C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x9C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x9C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x9C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x9C 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xA0 "CH0_PMRL20,PSI5 Message Register Low 20" hexmask.long 0xA0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xA0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xA4 "CH0_PMRH20,PSI5 Message Register High 20" bitfld.long 0xA4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xA4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xA4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xA4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xA4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xA4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xA4 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xA8 "CH0_PMRL21,PSI5 Message Register Low 21" hexmask.long 0xA8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xA8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xAC "CH0_PMRH21,PSI5 Message Register High 21" bitfld.long 0xAC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xAC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xAC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xAC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xAC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xAC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xAC 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xB0 "CH0_PMRL22,PSI5 Message Register Low 22" hexmask.long 0xB0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data framesfor more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the PSI5.." newline bitfld.long 0xB0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xB4 "CH0_PMRH22,PSI5 Message Register High 22" bitfld.long 0xB4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xB4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xB4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xB4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xB4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xB4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xB4 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xB8 "CH0_PMRL23,PSI5 Message Register Low 23" hexmask.long 0xB8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data framesfor more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the PSI5.." newline bitfld.long 0xB8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xBC "CH0_PMRH23,PSI5 Message Register High 23" bitfld.long 0xBC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xBC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xBC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xBC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xBC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xBC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xBC 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xC0 "CH0_PMRL24,PSI5 Message Register Low 24" hexmask.long 0xC0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xC0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xC4 "CH0_PMRH24,PSI5 Message Register High 24" bitfld.long 0xC4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xC4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xC4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xC4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xC4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xC4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xC4 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xC8 "CH0_PMRL25,PSI5 Message Register Low 25" hexmask.long 0xC8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xC8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xCC "CH0_PMRH25,PSI5 Message Register High 25" bitfld.long 0xCC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xCC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xCC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xCC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xCC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xCC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xCC 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xD0 "CH0_PMRL26,PSI5 Message Register Low 26" hexmask.long 0xD0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xD0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xD4 "CH0_PMRH26,PSI5 Message Register High 26" bitfld.long 0xD4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xD4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xD4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xD4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xD4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xD4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xD4 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xD8 "CH0_PMRL27,PSI5 Message Register Low 27" hexmask.long 0xD8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xD8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xDC "CH0_PMRH27,PSI5 Message Register High 27" bitfld.long 0xDC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xDC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xDC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xDC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xDC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xDC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xDC 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xE0 "CH0_PMRL28,PSI5 Message Register Low 28" hexmask.long 0xE0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xE0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xE4 "CH0_PMRH28,PSI5 Message Register High 28" bitfld.long 0xE4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xE4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xE4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xE4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xE4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xE4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xE4 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xE8 "CH0_PMRL29,PSI5 Message Register Low 29" hexmask.long 0xE8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xE8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xEC "CH0_PMRH29,PSI5 Message Register High 29" bitfld.long 0xEC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xEC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xEC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xEC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xEC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xEC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xEC 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xF0 "CH0_PMRL30,PSI5 Message Register Low 30" hexmask.long 0xF0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xF0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xF4 "CH0_PMRH30,PSI5 Message Register High 30" bitfld.long 0xF4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xF4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xF4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xF4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xF4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xF4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xF4 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xF8 "CH0_PMRL31,PSI5 Message Register Low 31" hexmask.long 0xF8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xF8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xFC "CH0_PMRH31,PSI5 Message Register High 31" bitfld.long 0xFC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xFC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xFC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xFC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xFC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xFC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xFC 0.--23. 1. "T0ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x100 "CH0_SFR1,SMC Frame Register 1" bitfld.long 0x100 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the correct.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x100 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x100 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x100 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x100 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x100 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x100 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x100 0.--11. 1. "DATA,DATA payload" line.long 0x104 "CH0_SFR2,SMC Frame Register 2" bitfld.long 0x104 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the correct.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x104 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x104 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x104 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x104 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x104 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x104 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x104 0.--11. 1. "DATA,DATA payload" line.long 0x108 "CH0_SFR3,SMC Frame Register 3" bitfld.long 0x108 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the correct.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x108 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x108 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x108 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x108 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x108 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x108 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x108 0.--11. 1. "DATA,DATA payload" line.long 0x10C "CH0_SFR4,SMC Frame Register 4" bitfld.long 0x10C 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the correct.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10C 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x10C 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x10C 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x10C 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x10C 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x10C 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x10C 0.--11. 1. "DATA,DATA payload" line.long 0x110 "CH0_SFR5,SMC Frame Register 5" bitfld.long 0x110 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x110 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x110 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x110 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x110 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x110 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x110 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x110 0.--11. 1. "DATA,DATA payload" line.long 0x114 "CH0_SFR6,SMC Frame Register 6" bitfld.long 0x114 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the correct.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x114 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x114 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x114 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x114 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x114 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x114 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x114 0.--11. 1. "DATA,DATA payload" line.long 0x118 "CH0_NDSR,New Data Status Register" hexmask.long 0x118 0.--31. 1. "NDS,New Data Status flags for PSI5 Messages corresponding to each PSI5 MB locations." line.long 0x11C "CH0_OWSR,Overwrite Status Register" hexmask.long 0x11C 0.--31. 1. "OWS,Over Write Status flags for PSI5 Messages corresponding to each PSI5 location in the RAM registers." line.long 0x120 "CH0_EISR,Error Indication Status Register" hexmask.long 0x120 0.--31. 1. "ERROR,Error Status flags for PSI5 Messages corresponding to each PSI5 MB locations." wgroup.long 0x160++0x3 line.long 0x0 "CH0_SNDSR,Set New Data Status Register" hexmask.long 0x0 0.--31. 1. "SNDS,Sets New Data Status flags for PSI5 Messages corresponding to each PSI5 MB locations." group.long 0x164++0x3 line.long 0x0 "CH0_SOWSR,Set Overwrite Status Register" hexmask.long 0x0 0.--31. 1. "SOWS,Sets overwrite status flags for PSI5 messages corresponding to each PSI5 MB locations." wgroup.long 0x168++0x7 line.long 0x0 "CH0_SEISR,Set Error Status Register" hexmask.long 0x0 0.--31. 1. "SERROR,Sets Error Status flags for PSI5 messages corresponding to each PSI5 MB locations." line.long 0x4 "CH0_SSESR,Set SMC Error Status Register" hexmask.long.byte 0x4 24.--29. 1. "SCESM,Sets IS_CESM Status flags for SMC Messages corresponding to each SMC MB locations." newline hexmask.long.byte 0x4 8.--13. 1. "SOWSM,Sets IS_OWSM Status flags for SMC Messages corresponding to each SMC MB locations." newline hexmask.long.byte 0x4 0.--5. 1. "SNVSM,Sets IS_NVSM Status flags for SMC Messages corresponding to each SMC MB locations." rgroup.long 0x170++0x7 line.long 0x0 "CH0_STSRR,Sync Time Stamp Read Register" hexmask.long.tbyte 0x0 0.--23. 1. "STSV,Sync Time Stamp Value[23:0]" line.long 0x4 "CH0_DTSRR,Data Time Stamp Read Register" bitfld.long 0x4 24.--26. "SLOT_COUNTER,3-bit Slot Counter which corresponds to the slot for which the DTSRR contains the Time Stamp. The slot_counter contains the slot in which the start bits of this frame was captured (after successful detection of S1). If the start bits get.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x4 0.--23. 1. "DTSV,Data Time Stamp Value[23:0]" group.long 0x178++0x17 line.long 0x0 "CH0_S1FCR,Slot 1 Frame Configuration Register" bitfld.long 0x0 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0x0 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0x0 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0x0 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0x0 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." line.long 0x4 "CH0_S2FCR,Slot 2 Frame Configuration Register" bitfld.long 0x4 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0x4 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0x4 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0x4 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0x4 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." line.long 0x8 "CH0_S3FCR,Slot 3 Frame Configuration Register" bitfld.long 0x8 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0x8 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0x8 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0x8 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0x8 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." line.long 0xC "CH0_S4FCR,Slot 4 Frame Configuration Register" bitfld.long 0xC 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0xC 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0xC 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0xC 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0xC 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." line.long 0x10 "CH0_S5FCR,Slot 5 Frame Configuration Register" bitfld.long 0x10 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0x10 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0x10 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0x10 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0x10 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." line.long 0x14 "CH0_S6FCR,Slot 6 Frame Configuration Register" bitfld.long 0x14 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0x14 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0x14 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0x14 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0x14 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." rgroup.word 0x190++0xB line.word 0x0 "CH0_S2SBR,Slot 2 Start Boundary Register" hexmask.word 0x0 0.--14. 1. "S2SBT,Slot 2 Start Boundary Time" line.word 0x2 "CH0_S1SBR,Slot 1 Start Boundary Register" hexmask.word 0x2 0.--14. 1. "S1SBT,Slot 0x1: Start Boundary Time" line.word 0x4 "CH0_S4SBR,Slot 4 Start Boundary Register" hexmask.word 0x4 0.--14. 1. "S4SBT,Slot 4 Start Boundary Time" line.word 0x6 "CH0_S3SBR,Slot 3 Start Boundary Register" hexmask.word 0x6 0.--14. 1. "S3SBT,Slot 3 Start Boundary Time" line.word 0x8 "CH0_S6SBR,Slot 6 Start Boundary Register" hexmask.word 0x8 0.--14. 1. "S6SBT,Slot 6 Start Boundary Time" line.word 0xA "CH0_S5SBR,Slot 5 Start Boundary Register" hexmask.word 0xA 0.--14. 1. "S5SBT,Slot 5 Start Boundary Time" group.long 0x19C++0x3 line.long 0x0 "CH0_SNEBR,Slot n End Boundary Register" bitfld.long 0x0 16.--18. "SLOT_NO,The field indicates the Slot number{16} for which Slot End Boundary Time is defined." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--14. 1. "SNEBT,Slot n End Boundary Time" group.word 0x1A0++0xB line.word 0x0 "CH0_MDDIS_OFF,Manchester Decoder Disable Offset Register" hexmask.word.byte 0x0 0.--6. 1. "MDDIS_OFF,These 7 bits can be used to program the time for which the Manchester decoder remains disabled. This offset is added AFTER the falling edge of the sync pulse. Thus the total time for which the Manchester decoder remains disabled = TsyncH +.." line.word 0x2 "CH0_DOBCR,Data Output Block Configuration Register" hexmask.word.byte 0x2 10.--15. 1. "DATA_LENGTH,Can take on values from 0 to 63 corresponding to 1 bit to 64 bit non standard length commands." newline bitfld.word 0x2 9. "DBR_RST,This is to reset and reject current content to Data Buffer Register. When this bit is written as 1 then the contents of the DBR are reset to all 0s (if DEFAULT_SYNC= = 0) or all 1s (if DEFAULT_SYNC == 1). As soon as content is reset the DBR would.." "0,1" newline bitfld.word 0x2 8. "DSR_RST,This is to reset and reject current content to Data Shift Register.When this bit is written as 1 then the contents of the DSR are reset to all 0s (if DEFAULT_SYNC= = 0) or all 1s (if DEFAULT_SYNC == 1). As soon as content is reset the DSR would.." "0,1" newline bitfld.word 0x2 5.--7. "CMD_TYPE,These 3 bits indicate the type of command that needs to be transmitted during the ECU to sensor communication. Table2061 is a brief description of the same." "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 4. "DEFAULT_SYNC,When this bit is set to 0 then the default value of DSR and DBR registers are all 0s; when this bit is set to 1 then the default value of DBR and DSR registers are all 1s." "0,1" newline bitfld.word 0x2 3. "GTM_TRIG_SEL,GTM event triggered/internal sync pulse generator selection as shift clock for the DSR." "0: Internal sync pulse generator shift triggered,1: GTM event shift triggered" newline bitfld.word 0x2 2. "SP_PULSE_SEL,Selects the source for the short pulse PWM module:" "0: SP module gets the data from the DSR,1: SP module directly gets input from the.." newline bitfld.word 0x2 1. "OP_SEL,This bit selects the driving source of the ipp_do_psi5_sdout port." "0: The sync pulse generator select as per the..,1: PWM output" newline bitfld.word 0x2 0. "SW_READY,When this bit is written to 1 the transfer from DBR to DSR automatically happens as soon as DSR_RDY becomes 1. When this bit is kept to 0 then the transfer from DBR to DSR will remain pending. Once the software makes this bit as 1 and DSR_RDY.." "0,1" line.word 0x4 "CH0_PW1D,Pulse Width for Data Bit 1 Register" hexmask.word.byte 0x4 0.--6. 1. "PULSE_W0DTH1,This defines the width (in microsesc) of data value0x1: to be sent from Data Output Register. It is the number of clock cycles (1 microsesc clock) counted up to width Pulse_Width1; starting as soon as trigger appears from the ISPG(Internal.." line.word 0x6 "CH0_PW0D,Pulse Width for Data Bit 0 Register" hexmask.word.byte 0x6 0.--6. 1. "PULSE_W0DTH0,This defines the width (in microsesc) of data value0x0: to be sent from Data Output Register. It is the number of clock cycles (1 microsesc clock) counted up to width Pulse_Width0; starting as soon as trigger appears from the ISPG (Internal.." line.word 0x8 "CH0_CIPR,Counter Initialize Pulse Register" hexmask.word 0x8 0.--15. 1. "CIPR,Counter initialization pulse register" line.word 0xA "CH0_CTPR,Counter Target Pulse Register" hexmask.word 0xA 0.--15. 1. "CTPR,Counter Target Pulse Register" group.long 0x1AC++0x3 line.long 0x0 "CH0_DPRL,Data Preparation Register Low" hexmask.long.tbyte 0x0 0.--23. 1. "DPR,DPR[23:0] are the 24-bits of the DPR register used for writing the variable length standard ECU-to-Sensor commands comprising of the address data and other fields. Note that the IP is transparent to the arrangement of the address data and other.." rgroup.long 0x1B0++0x3 line.long 0x0 "CH0_DPRH,Data Preparation Register High" group.long 0x1B4++0xF line.long 0x0 "CH0_DBRL,Data Buffer Register Low" hexmask.long 0x0 0.--31. 1. "DBR,This register contains the Lower 32 bits(DBR[31:0]) of the max-64 bit length command (DBR[63:0]). The higher bits DBR[63:32] are contained in the DBRH register." line.long 0x4 "CH0_DBRH,Data Buffer Register High" hexmask.long 0x4 0.--31. 1. "DBR,This register contains the Upper 32 bits(DBR[63:32]) of the max-64 bit length command (DBR[63:0]). The lower bits DBR[31:0] are contained in the DBRL register." line.long 0x8 "CH0_DSRL,Data Shift Register Low" hexmask.long 0x8 0.--31. 1. "DSR,These bits can be updated by the hardware or can be written by the CPU. The number of accessible bits in DSR are always equal to the number of accessible bits in DBR which in turn depend on the value of PSI5_DOBCR[CMD_TYPE] register bits.When these.." line.long 0xC "CH0_DSRH,Data Shift Register High" hexmask.long 0xC 0.--31. 1. "DSR,These bits can be updated by the hardware or can be written by the CPU. The number of accessible bits in DSR are always equal to the number of accessible bits in DBR which in turn depend on the value of PSI5_DOBCR[CMD_TYPE] register bits. When these.." group.long 0x1C8++0x1F line.long 0x0 "CH1_PCCR,PSI5 Channel Control Register" bitfld.long 0x0 31. "CTC_GED_SEL,Channel Target Counter Global Enable/Disable Select" "0: CTC enabled disabled by CTC_ED.,1: CTC enabled/disabled by CTC_GED." newline bitfld.long 0x0 30. "CTC_ED,Channel Target Counter Enable/Disable" "0: The CTC counters is disabled and reset.,1: The CTC counter is enabled and start counting." newline hexmask.long.byte 0x0 24.--28. 1. "MEM_DEPTH,Can be programmed from 0 to 31 and denotes the size of the memory that should be used for storing the PSI5 messages. Area above the MEM_DEPTH is treated as being unavailable for message storage." newline bitfld.long 0x0 20. "ERROR_SELECT4,The ERROR_SELECT bitfield indicates which of the C E EM T or F error conditions generate an interrupt when the EICR Interrupt Enable bit is set. The individual bits are mapped as {C E EM T F}. The corresponding error is also latched in.." "0: The C bit does not generate an interrupt.,1: The C bit generates an interrupt." newline bitfld.long 0x0 19. "ERROR_SELECT3,Error_Select[3] or E_INT_SEL" "0: The E bit does not generate an interrupt.,1: The E bit generates an interrupt." newline bitfld.long 0x0 18. "ERROR_SELECT2,Error_Select[2] or EM_INT_SEL" "0: The EM bit does not generate an interrupt.,1: The EM bit generates an interrupt." newline bitfld.long 0x0 17. "ERROR_SELECT1,Error_Select[1] or T_INT_SEL" "0: The T bit does not generate an interrupt.,1: The T bit generates an interrupt." newline bitfld.long 0x0 16. "ERROR_SELECT0,Error_Select[0] or F_INT_SEL" "0: The F bit does not generate an interrupt.,1: The F bit generates an interrupt." newline bitfld.long 0x0 14. "GTM_RESET_ASYNC_EN,GTM_RESET_ASYNC_EN" "0: Both the assertion and the deassertion of the..,1: Assertion of the GTM reset is treated.." newline bitfld.long 0x0 10. "DEBUG_EN,This bit allows/prevents the IP from entering the debug mode whenever the debugger is connected and a breakpoint is encountered by the debugger:" "0: The IP never enters the debug mode even if the..,1: Whenever the debugger is connected and a.." newline bitfld.long 0x0 9. "DEBUG_FREEZE_CTRL,Note: In the above configuration the status of registers read through the debugger may be different when entering debug mode and when actually accessing registers at some later point of time." "0: When the IP enters the Debug mode then it goes..,1: When the IP enters the Debug mode then it goes.." newline bitfld.long 0x0 8. "SP_TS_CLK_SEL,This bit controls which clock goes to the Sync Pulse and Time Stamp Generator Unit." "0: The 1MHz clock generated from the CGM goes for..,1: The clock generated from the GTM goes for.." newline bitfld.long 0x0 5. "FAST_CLR_SMC,This bit controls the clearing mechanism of the IS_NVSM[x] IS_CESM[x] and IS_OWSM[x] bits in the GISR." "0: Fast clearing is disabled (clear when written to..,1: Fast clearing is enabled." newline bitfld.long 0x0 4. "FAST_CLR_PSI5,This bit controls the clearing mechanism of bits in NDSR (in conf2 conf3 and conf4 modes) EISR (in conf2 conf3 and conf4 modes) and OWSR (in conf2 and conf3 modes)." "0: Fast Clearing Disables (clear when written to 1),1: Fast Clearing Enabled" newline bitfld.long 0x0 3. "BIT_RATE,This bit selects the receive message bit rate (T bit) for this particular PSI5 Channel that is it selects one of the two driven clocks (4MHz or 6.048MHz) in CGM." "0: 125Kbit/s bit rate selected (4MHz clock).,1: 189Kbit/s bit rate selected (6.048MHz clock)." newline bitfld.long 0x0 2. "MODE,This bit selects the operating modes." "0: Asynchronous operating mode (Integrated sync..,1: Synchronous operating modes (Integrated sync.." newline bitfld.long 0x0 1. "PSI5_CH_CONFIG,PSI5 Channel Config mode request" "0: (If PCCR[PSI5_CH_EN] =0x1: and..,1: (If PCCR[PSI5_CH_EN]=0x1: and.." newline bitfld.long 0x0 0. "PSI5_CH_EN,PSI5 Channel Enable. If this bit is cleared this particular psi5 channel continues to stay in Disable mode even if GCR[GLOBAL_DISABLE_REQ] = 0. If set it enters Configuration mode from Disable mode (based on PCCR[PSI5_CH_CONFIG]). Default.." "0: PSI5 channel continues in Disable mode.,1: PSI5 channel enabled to enter Config/Normal mode." line.long 0x4 "CH1_DCR,DMA Control Register" hexmask.long.byte 0x4 24.--28. 1. "DMA_PM_DS_WM,Value fixed by user software." newline bitfld.long 0x4 18. "IE_DMA_TF_SF,Enable for interrupt which is generated when DMA transfer finishes for DMA SMC Frame register." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x4 17. "IE_DMA_TF_PM_DS,Enable for Interrupt which is generated when DMA transfer finishes for PSI5 messages/DMA Diagnostic Status register depending on the DMA_PM_DS_CONFIG bits of the DCR." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x4 11. "IE_DMA_PM_DS_FIFO_FULL,This bit is effective only when the DMA_PM_DS_CONFIG = conf2 conf3 or conf4. It enables the FIFO FULL condition generation interrupt. For the cases that generate these FIFO FULL conditions refer to the description of.." "0,1" newline bitfld.long 0x4 10. "IE_DMA_SFUF,Enables interrupt when there is underflow in DMA SMC Frame register when DMA is enabled. It is set when the DSFR is read without a valid DMA request that is it is empty." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x4 8. "IE_DMA_PM_DS_UF,Enables interrupt when there is underflow in DMA PSI5 message register when DMA is enabled. Default value is 0. For the details as to when this underflow occurs refer to the details of IS_DMA_PM_DS_UF bit details of the DSR." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x4 2. "DMA_EN_SF,Enable DMA request for SMC Frame Data" "0: DMA for SMC frame is disabled. The six dedicated..,1: DMA for SMC frame is enabled. The six dedicated.." newline bitfld.long 0x4 0.--1. "DMA_PM_DS_CONFIG,These bits define how the PSI5 messages are stored in the MEM_DEPTH memory area and the associated diagnostic bits (EISR NDSR) are transferred." "0: conf1 The DMA request is disabled. In this mode..,1: conf2 After transferring the dma_pm_ds_wm number..,2: conf3 dma_pm_ds_wm number of PSI5 messages is..,3: conf4 Only the diagnostic bits are transferred.." line.long 0x8 "CH1_DSR,DMA Status Register" bitfld.long 0x8 18. "IS_DMA_TF_SF,This flag is set when DMA transfer finishes for DMA SMC Frame register." "0,1" newline bitfld.long 0x8 17. "IS_DMA_TF_PM_DS,This flag is set when DMA transfer finishes. For the various configurations of this request refer to the descriptions of the DMA_PM_DS_CONFIG bits in the DCR. This flag is cleared by w1c." "0,1" newline bitfld.long 0x8 11. "IS_DMA_PM_DS_FIFO_FULL,Interrupt Status when there is FIFO FULL corresponding to the DMA request ipd_psi5_dma_req_pm_ds." "0: No FIFO full.,1: FIFO full has occurred" newline bitfld.long 0x8 10. "IS_DMA_SFUF,SMC Frame DMA underflow: This happens when the DSFR has been read without a proper DMA request being asserted. The DSFR is empty and it is read. This bit is cleared by a w1c." "0: No underflow has occurred.,1: Underflow has occurred." newline bitfld.long 0x8 8. "IS_DMA_PM_DS_UF,Depending on the DMA_PM_DS_CONFIG bits following is the underflow conditions:" "0: No underflow has occurred.,1: Underflow has occurred." line.long 0xC "CH1_GICR,General Interrupt Control Register" hexmask.long.byte 0xC 24.--29. 1. "IE_CESM,Interrupt request when received SMC frame in corresponding slot has CRC failure (CRC recalculation on SMC)." newline bitfld.long 0xC 23. "IE_STS,Interrupt request enabled when the Sync Pulse Triggered Time Stamp value is refreshed on STSRR." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 22. "IE_DTS,Interrupt request enabled when the Data Start sequence Triggered Time Stamp value is refreshed on DTSRR." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 21. "IE_DSROW,Interrupt request enabled when system tries to overwrite on Data Shift register when it is not ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 20. "IE_BROW,Interrupt request enabled when system tries to overwrite on buffer register when it is not ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 19. "IE_PROW,Interrupt request enabled when system tries to overwrite on Preparation register when it is not ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 18. "IE_DSRR,Interrupt request enabled when Data Shift Register is ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 17. "IE_BRR,Interrupt request enabled when buffer Register is ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0xC 16. "IE_PRR,Interrupt request enabled when Preparation Register ready to accept new data." "0: Interrupt is disabled.,1: Interrupt is enabled." newline hexmask.long.byte 0xC 8.--13. 1. "IE_OWSM,Interrupt request enable for the SMC message Overwrite bits." newline hexmask.long.byte 0xC 0.--5. 1. "IE_NVSM,Interrupt request enabled when any new valid SMC message (fault free) is received in SFR[i]{i:0 to 5} that is during slot1 to slot6. This interrupt is generated only when corresponding IS_NVSMS[5:0] is set." line.long 0x10 "CH1_NDICR,New Data Interrupt Control Register" hexmask.long 0x10 0.--31. 1. "IE_ND,Interrupt request enabled when any new message (fault-free/with fault) is received in the RAM buffer Registerx location [x: 0 to 31] This interrupt is generated only when corresponding RAM buffer Ready with new data." line.long 0x14 "CH1_OWICR,Overwrite Interrupt Control Register" hexmask.long 0x14 0.--31. 1. "IE_OW,Interrupt request enabled when any new message overwrites the old unread PSI5 message in the RAM buffer Registerx location [x: 0 to 31] This interrupt generated only when corresponding RAM buffer Ready with new data." line.long 0x18 "CH1_EICR,Error Interrupt Control Register" hexmask.long 0x18 0.--31. 1. "IE_ERROR,Interrupt request enabled when any/all of the error conditions C E EM T or F is observed in a PSI5 message in the RAM buffer Registerx location [x: 0 to 31]. This interrupt is generated only when the corresponding RAM buffer is Ready with.." line.long 0x1C "CH1_GISR,General Interrupt Status Register" bitfld.long 0x1C 31. "IS_DEBUG_FREEZE,This flag is set to 1 when the IP enters the debug freeze mode. Please see Section1.1.3.5: Debug mode for details about the debug mode. This bit is auto cleared by the hardware when the IP exits the debug freeze mode." "0: IP not in debug freeze mode,1: IP in debug freeze mode" newline bitfld.long 0x1C 29. "IS_CESM6,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 28. "IS_CESM5,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 27. "IS_CESM4,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 26. "IS_CESM3,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 25. "IS_CESM2,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 24. "IS_CESM1,These flags are set when the received SMC frame in the corresponding slot has a CRC failure (CRC recalculation on SMC). These bits are automatically cleared upon message read when the FAST_CLR_SMC =1 and the DMA_EN_SF = 1 or by w1c." "0,1" newline bitfld.long 0x1C 23. "IS_STS,This Interrupt flag is set when the Sync Pulse Triggered Time Stamp value is refreshed on STSRR." "0,1" newline bitfld.long 0x1C 22. "IS_DTS,This Interrupt flag is set when the Data Start sequence Triggered Time Stamp value is refreshed on DTSRR." "0,1" newline bitfld.long 0x1C 21. "IS_DSROW,This flag is set when the system tries to overwrite on Data Shift register when it is not ready to accept new data." "0,1" newline bitfld.long 0x1C 20. "IS_BROW,This flag is set when the system tries to overwrite on buffer register when it is not ready to accept new data." "0,1" newline bitfld.long 0x1C 19. "IS_PROW,This flag is set when the system tries to overwrite on Preparation register when it is not ready to accept new data." "0,1" newline bitfld.long 0x1C 18. "DSR_RDY,This bit acts both as a status and a control bit." "0,1" newline bitfld.long 0x1C 17. "DBR_RDY,This bit acts both as a status and a control bit." "0,1" newline bitfld.long 0x1C 16. "DPR_RDY,This bit acts both as a status and a control bit." "0,1" newline bitfld.long 0x1C 13. "IS_OWSM6,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 12. "IS_OWSM5,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 11. "IS_OWSM4,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 10. "IS_OWSM3,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 9. "IS_OWSM2,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 8. "IS_OWSM1,Status for the SMC message overwrite bits. Each of the 6 locations correspond to the SMC message pertaining to each SFR[x] register x=0x1: to 6. These bits are cleared automatically upon message read when the FAST_CLR_SMC = 1 and the DMA_EN_SF.." "?,1: to 6" newline bitfld.long 0x1C 5. "IS_NVSM6,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" newline bitfld.long 0x1C 4. "IS_NVSM5,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" newline bitfld.long 0x1C 3. "IS_NVSM4,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" newline bitfld.long 0x1C 2. "IS_NVSM3,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" newline bitfld.long 0x1C 1. "IS_NVSM2,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" newline bitfld.long 0x1C 0. "IS_NVSM1,These flags are set when corresponding SFR[i] receives and is ready (to read) with new valid SMC message. These bits are cleared automatically upon message read when the FAST_CLR_SMC=0x1: and the DMA_EN_SF = 1 or by w1c." "?,1: and the DMA_EN_SF = 1 or by w1c" rgroup.long 0x1E8++0x13 line.long 0x0 "CH1_DPMR,DMA PSI5 Message Register" hexmask.long 0x0 0.--31. 1. "PSI5_RXDATA,PSI5_RXDATA[31:0]" line.long 0x4 "CH1_DSFR,DMA SMC Frame Register" hexmask.long 0x4 0.--31. 1. "SMC_RXDATA,When the DMA_EN_SF = 1 then the six SFR registers are searched in a round robin fashion for the reception of the complete SMC data. The DMA request is asserted as soon as the first encountered SFR has a complete SMC frame. This request.." line.long 0x8 "CH1_DDSR,DMA Diagnostic Status Register" hexmask.long 0x8 0.--31. 1. "DDS,This register maps each of the individual Diagnostic registers (in the order NDSR EISR) depending on the configuration of the DMA_PM_DS_CONFIG bits in the DCR. This register is a reflection of the location pointed to by the DMA read pointer." line.long 0xC "CH1_PMRRL,PSI5 Message Receive Register Low" hexmask.long 0xC 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xC 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRC[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "C,This bit will be set if CRC/P recalculation return an Error." "0,1" line.long 0x10 "CH1_PMRRH,PSI5 Message Receive Register High" bitfld.long 0x10 30. "F,This represents that NO frame was received in the corresponding configured slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error)." newline bitfld.long 0x10 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the T bit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields." newline bitfld.long 0x10 28. "E,This bit indicates electrical error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x10 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot spread across two slots started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot." newline bitfld.long 0x10 24.--26. "SLOTCOUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x10 0.--23. 1. "T1MESTAMPVALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed by.." group.long 0x1FC++0x123 line.long 0x0 "CH1_PMRL0,PSI5 Message Register Low 0" hexmask.long 0x0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x4 "CH1_PMRH0,PSI5 Message Register High 0" bitfld.long 0x4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x4 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x8 "CH1_PMRL1,PSI5 Message Register Low 1" hexmask.long 0x8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xC "CH1_PMRH1,PSI5 Message Register High 1" bitfld.long 0xC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xC 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x10 "CH1_PMRL2,PSI5 Message Register Low 2" hexmask.long 0x10 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x10 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x14 "CH1_PMRH2,PSI5 Message Register High 2" bitfld.long 0x14 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x14 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x14 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x14 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x14 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x14 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x14 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x18 "CH1_PMRL3,PSI5 Message Register Low 3" hexmask.long 0x18 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x18 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x1C "CH1_PMRH3,PSI5 Message Register High 3" bitfld.long 0x1C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x1C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x1C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x1C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x1C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x1C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x1C 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x20 "CH1_PMRL4,PSI5 Message Register Low 4" hexmask.long 0x20 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x20 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x24 "CH1_PMRH4,PSI5 Message Register High 4" bitfld.long 0x24 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x24 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x24 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x24 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x24 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x24 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x24 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x28 "CH1_PMRL5,PSI5 Message Register Low 5" hexmask.long 0x28 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x28 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x2C "CH1_PMRH5,PSI5 Message Register High 5" bitfld.long 0x2C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x2C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x2C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x2C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x2C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x2C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x2C 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x30 "CH1_PMRL6,PSI5 Message Register Low 6" hexmask.long 0x30 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x30 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x34 "CH1_PMRH6,PSI5 Message Register High 6" bitfld.long 0x34 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x34 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x34 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x34 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x34 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x34 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x34 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x38 "CH1_PMRL7,PSI5 Message Register Low 7" hexmask.long 0x38 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x38 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x3C "CH1_PMRH7,PSI5 Message Register High 7" bitfld.long 0x3C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x3C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x3C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x3C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x3C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x3C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x3C 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x40 "CH1_PMRL8,PSI5 Message Register Low 8" hexmask.long 0x40 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x40 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x44 "CH1_PMRH8,PSI5 Message Register High 8" bitfld.long 0x44 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x44 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x44 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x44 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x44 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x44 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x44 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x48 "CH1_PMRL9,PSI5 Message Register Low 9" hexmask.long 0x48 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x48 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x4C "CH1_PMRH9,PSI5 Message Register High 9" bitfld.long 0x4C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x4C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x4C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x4C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x4C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x4C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x4C 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x50 "CH1_PMRL10,PSI5 Message Register Low 10" hexmask.long 0x50 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x50 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x54 "CH1_PMRH10,PSI5 Message Register High 10" bitfld.long 0x54 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x54 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x54 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x54 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x54 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x54 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x54 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x58 "CH1_PMRL11,PSI5 Message Register Low 11" hexmask.long 0x58 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x58 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x5C "CH1_PMRH11,PSI5 Message Register High 11" bitfld.long 0x5C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x5C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x5C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x5C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x5C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x5C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x5C 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x60 "CH1_PMRL12,PSI5 Message Register Low 12" hexmask.long 0x60 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x60 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x64 "CH1_PMRH12,PSI5 Message Register High 12" bitfld.long 0x64 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x64 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x64 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x64 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x64 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x64 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x64 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x68 "CH1_PMRL13,PSI5 Message Register Low 13" hexmask.long 0x68 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x68 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x6C "CH1_PMRH13,PSI5 Message Register High 13" bitfld.long 0x6C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x6C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x6C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x6C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x6C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x6C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x6C 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x70 "CH1_PMRL14,PSI5 Message Register Low 14" hexmask.long 0x70 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x70 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x74 "CH1_PMRH14,PSI5 Message Register High 14" bitfld.long 0x74 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x74 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x74 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x74 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x74 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x74 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x74 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x78 "CH1_PMRL15,PSI5 Message Register Low 15" hexmask.long 0x78 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x78 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x7C "CH1_PMRH15,PSI5 Message Register High 15" bitfld.long 0x7C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x7C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x7C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x7C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x7C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x7C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x7C 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x80 "CH1_PMRL16,PSI5 Message Register Low 16" hexmask.long 0x80 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x80 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x84 "CH1_PMRH16,PSI5 Message Register High 16" bitfld.long 0x84 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x84 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x84 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x84 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x84 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x84 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x84 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x88 "CH1_PMRL17,PSI5 Message Register Low 17" hexmask.long 0x88 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x88 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x8C "CH1_PMRH17,PSI5 Message Register High 17" bitfld.long 0x8C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x8C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x8C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x8C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x8C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x8C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x8C 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x90 "CH1_PMRL18,PSI5 Message Register Low 18" hexmask.long 0x90 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x90 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x94 "CH1_PMRH18,PSI5 Message Register High 18" bitfld.long 0x94 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x94 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x94 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x94 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x94 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x94 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x94 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x98 "CH1_PMRL19,PSI5 Message Register Low 19" hexmask.long 0x98 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0x98 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0x9C "CH1_PMRH19,PSI5 Message Register High 19" bitfld.long 0x9C 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0x9C 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0x9C 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0x9C 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0x9C 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0x9C 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x9C 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xA0 "CH1_PMRL20,PSI5 Message Register Low 20" hexmask.long 0xA0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xA0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xA4 "CH1_PMRH20,PSI5 Message Register High 20" bitfld.long 0xA4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xA4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xA4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xA4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xA4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xA4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xA4 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xA8 "CH1_PMRL21,PSI5 Message Register Low 21" hexmask.long 0xA8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xA8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xAC "CH1_PMRH21,PSI5 Message Register High 21" bitfld.long 0xAC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xAC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xAC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xAC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xAC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xAC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xAC 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xB0 "CH1_PMRL22,PSI5 Message Register Low 22" hexmask.long 0xB0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data framesfor more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the PSI5.." newline bitfld.long 0xB0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xB4 "CH1_PMRH22,PSI5 Message Register High 22" bitfld.long 0xB4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xB4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xB4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xB4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xB4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xB4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xB4 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xB8 "CH1_PMRL23,PSI5 Message Register Low 23" hexmask.long 0xB8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data framesfor more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the PSI5.." newline bitfld.long 0xB8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xBC "CH1_PMRH23,PSI5 Message Register High 23" bitfld.long 0xBC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xBC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xBC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xBC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xBC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xBC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xBC 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xC0 "CH1_PMRL24,PSI5 Message Register Low 24" hexmask.long 0xC0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xC0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xC4 "CH1_PMRH24,PSI5 Message Register High 24" bitfld.long 0xC4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xC4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xC4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xC4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xC4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xC4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xC4 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xC8 "CH1_PMRL25,PSI5 Message Register Low 25" hexmask.long 0xC8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xC8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xCC "CH1_PMRH25,PSI5 Message Register High 25" bitfld.long 0xCC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xCC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xCC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xCC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xCC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xCC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xCC 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xD0 "CH1_PMRL26,PSI5 Message Register Low 26" hexmask.long 0xD0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xD0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xD4 "CH1_PMRH26,PSI5 Message Register High 26" bitfld.long 0xD4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xD4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xD4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xD4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xD4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xD4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xD4 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xD8 "CH1_PMRL27,PSI5 Message Register Low 27" hexmask.long 0xD8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xD8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xDC "CH1_PMRH27,PSI5 Message Register High 27" bitfld.long 0xDC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xDC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xDC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xDC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xDC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xDC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xDC 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xE0 "CH1_PMRL28,PSI5 Message Register Low 28" hexmask.long 0xE0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xE0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xE4 "CH1_PMRH28,PSI5 Message Register High 28" bitfld.long 0xE4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xE4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xE4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xE4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xE4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xE4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xE4 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xE8 "CH1_PMRL29,PSI5 Message Register Low 29" hexmask.long 0xE8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xE8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xEC "CH1_PMRH29,PSI5 Message Register High 29" bitfld.long 0xEC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xEC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xEC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xEC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xEC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xEC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xEC 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xF0 "CH1_PMRL30,PSI5 Message Register Low 30" hexmask.long 0xF0 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xF0 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xF4 "CH1_PMRH30,PSI5 Message Register High 30" bitfld.long 0xF4 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xF4 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xF4 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xF4 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xF4 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xF4 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xF4 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0xF8 "CH1_PMRL31,PSI5 Message Register Low 31" hexmask.long 0xF8 4.--31. 1. "DATA_REGION,These are application-specific optional bits + data payload of received message. See Section71.4.2.1: Reception of data frames for more details. The data is left-aligned that is Data Region[0]/D0 corresponds to first received bit of the.." newline bitfld.long 0xF8 1.--3. "CRCP,This field represents CRC/Parity value of the data. When parity configuration is selected in the S[1-6]FCR registers the CRCP[2] bits denotes the parity." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 0. "C,This bit will be set if CRC/Parity recalculation return an Error. It is writable in configuration mode (for test purposes)." "0,1" line.long 0xFC "CH1_PMRH31,PSI5 Message Register High 31" bitfld.long 0xFC 31. "O,This bit carries the same information as OWSR but appended here for each message separately. This bit is set when the current message (which is being read) has overwritten some previous unread message. Note that if the corresponding location in the.." "0,1" newline bitfld.long 0xFC 30. "F,This represents that NO frame was received in corresponding configured Slot." "0: Frame was received in the corresponding..,1: No frame was received (F bit error). In the.." newline bitfld.long 0xFC 29. "EM,This bit indicates electrical error in the PSI5 Message at bits corresponding to Serial Messaging Channel (M0 M1) that is at least one bit is absent during the Tbit period." "0: No electrical error in M0 M1 fields.,1: Electrical error in M0 M1 fields. In the normal.." newline bitfld.long 0xFC 28. "E,This Bit Indicates Electrical Error that is at least one bit is absent during the Tbit period (except M0 and M1 bits and the start bits)." "0: No electrical error in fields other than M0 M1..,1: Electrical error in fields other than M0 M1 and.." newline bitfld.long 0xFC 27. "T,This bit indicates timing error that is frame has started in an unconfigured slot or it has spread across two slots or it has started before the first configured slot." "0: No timing error in the corresponding slot.,1: Timing error in the corresponding slot. In the.." newline bitfld.long 0xFC 24.--26. "SLOT_COUNTER,This value indicates the slot number in which this frame was received. More specifically it indicates in which slot the start bits of the frame have been detected. If the start bits get detected before the start boundary of Slot1 then the.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0xFC 0.--23. 1. "T1ME_STAMP_VALUE,This is 24-bit Time Stamp value appended to Received message as soon as start bits are detected. This time stamp is captured at rising edge of S0 and stored at the rising edge of S1. The specific value that is appended can be programmed.." line.long 0x100 "CH1_SFR1,SMC Frame Register 1" bitfld.long 0x100 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the correct.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x100 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x100 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x100 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x100 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x100 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x100 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x100 0.--11. 1. "DATA,DATA payload" line.long 0x104 "CH1_SFR2,SMC Frame Register 2" bitfld.long 0x104 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the correct.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x104 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x104 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x104 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x104 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x104 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x104 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x104 0.--11. 1. "DATA,DATA payload" line.long 0x108 "CH1_SFR3,SMC Frame Register 3" bitfld.long 0x108 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the correct.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x108 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x108 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x108 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x108 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x108 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x108 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x108 0.--11. 1. "DATA,DATA payload" line.long 0x10C "CH1_SFR4,SMC Frame Register 4" bitfld.long 0x10C 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the correct.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10C 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x10C 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x10C 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x10C 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x10C 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x10C 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x10C 0.--11. 1. "DATA,DATA payload" line.long 0x110 "CH1_SFR5,SMC Frame Register 5" bitfld.long 0x110 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x110 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x110 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x110 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x110 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x110 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x110 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x110 0.--11. 1. "DATA,DATA payload" line.long 0x114 "CH1_SFR6,SMC Frame Register 6" bitfld.long 0x114 29.--31. "SLOT_NO,This indicates in which slot this SMC frame was received. Note that here the slot number refers to the slot in which all the re-arranged PSI5 messages (from which the M0 M1 bits have been extracted) are supposed to have occurred after the correct.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x114 28. "CER,CRC Error" "0: The present data has no CRC error.,1: The present data has a CRC error." newline bitfld.long 0x114 27. "OW,Overwrite status" "0: The present data was already read when new..,1: New message has overwritten the previous unread.." newline hexmask.long.byte 0x114 21.--26. 1. "CRC,6-bit CRC for slow serial message" newline bitfld.long 0x114 20. "C,Configuration bit" "0: 12-bit data and 8-bit message ID.,1: 16-bit data and 4-bit message ID." newline hexmask.long.byte 0x114 16.--19. 1. "ID,Message ID: If C =0x0: indicates ID[7:4] if C =0x1: indicates ID[3:0]." newline hexmask.long.byte 0x114 12.--15. 1. "IDDATA,Message ID/DATA: If C =0x0: indicates ID[3:0] if C =0x1: indicates DATA[15:12]." newline hexmask.long.word 0x114 0.--11. 1. "DATA,DATA payload" line.long 0x118 "CH1_NDSR,New Data Status Register" hexmask.long 0x118 0.--31. 1. "NDS,New Data Status flags for PSI5 Messages corresponding to each PSI5 MB locations." line.long 0x11C "CH1_OWSR,Overwrite Status Register" hexmask.long 0x11C 0.--31. 1. "OWS,Over Write Status flags for PSI5 Messages corresponding to each PSI5 location in the RAM registers." line.long 0x120 "CH1_EISR,Error Indication Status Register" hexmask.long 0x120 0.--31. 1. "ERROR,Error Status flags for PSI5 Messages corresponding to each PSI5 MB locations." wgroup.long 0x320++0x3 line.long 0x0 "CH1_SNDSR,Set New Data Status Register" hexmask.long 0x0 0.--31. 1. "SNDS,Sets New Data Status flags for PSI5 Messages corresponding to each PSI5 MB locations." group.long 0x324++0x3 line.long 0x0 "CH1_SOWSR,Set Overwrite Status Register" hexmask.long 0x0 0.--31. 1. "SOWS,Sets overwrite status flags for PSI5 messages corresponding to each PSI5 MB locations." wgroup.long 0x328++0x7 line.long 0x0 "CH1_SEISR,Set Error Status Register" hexmask.long 0x0 0.--31. 1. "SERROR,Sets Error Status flags for PSI5 messages corresponding to each PSI5 MB locations." line.long 0x4 "CH1_SSESR,Set SMC Error Status Register" hexmask.long.byte 0x4 24.--29. 1. "SCESM,Sets IS_CESM Status flags for SMC Messages corresponding to each SMC MB locations." newline hexmask.long.byte 0x4 8.--13. 1. "SOWSM,Sets IS_OWSM Status flags for SMC Messages corresponding to each SMC MB locations." newline hexmask.long.byte 0x4 0.--5. 1. "SNVSM,Sets IS_NVSM Status flags for SMC Messages corresponding to each SMC MB locations." rgroup.long 0x330++0x7 line.long 0x0 "CH1_STSRR,Sync Time Stamp Read Register" hexmask.long.tbyte 0x0 0.--23. 1. "STSV,Sync Time Stamp Value[23:0]" line.long 0x4 "CH1_DTSRR,Data Time Stamp Read Register" bitfld.long 0x4 24.--26. "SLOT_COUNTER,3-bit Slot Counter which corresponds to the slot for which the DTSRR contains the Time Stamp. The slot_counter contains the slot in which the start bits of this frame was captured (after successful detection of S1). If the start bits get.." "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x4 0.--23. 1. "DTSV,Data Time Stamp Value[23:0]" group.long 0x338++0x17 line.long 0x0 "CH1_S1FCR,Slot 1 Frame Configuration Register" bitfld.long 0x0 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0x0 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0x0 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0x0 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0x0 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." line.long 0x4 "CH1_S2FCR,Slot 2 Frame Configuration Register" bitfld.long 0x4 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0x4 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0x4 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0x4 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0x4 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." line.long 0x8 "CH1_S3FCR,Slot 3 Frame Configuration Register" bitfld.long 0x8 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0x8 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0x8 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0x8 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0x8 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." line.long 0xC "CH1_S4FCR,Slot 4 Frame Configuration Register" bitfld.long 0xC 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0xC 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0xC 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0xC 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0xC 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." line.long 0x10 "CH1_S5FCR,Slot 5 Frame Configuration Register" bitfld.long 0x10 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0x10 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0x10 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0x10 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0x10 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." line.long 0x14 "CH1_S6FCR,Slot 6 Frame Configuration Register" bitfld.long 0x14 18. "SLOT_EN,SLOT_EN" "0: This particular slot is disabled that is not in..,1: This particular slot is enabled that is in use.." newline bitfld.long 0x14 17. "TS_CAPT,TS_CAPT" "0: Time stamp value captured at rising edge of S0..,1: Time stamp value captured at corresponding Tsync.." newline bitfld.long 0x14 15. "SMCL,Serial Messaging Channel field" "0: Serial Messaging Channel (optional) not present..,1: 2-bit{M1 M0} Serial Messaging Channel present on.." newline hexmask.long.byte 0x14 1.--5. 1. "DRL,Data Region Length[4:0]" newline bitfld.long 0x14 0. "CRCP,CRCP" "0: 3 bit CRC[2:0] present on Rx Message during Time..,1: 1 bit Parity field present on Rx Message during.." rgroup.word 0x350++0xB line.word 0x0 "CH1_S2SBR,Slot 2 Start Boundary Register" hexmask.word 0x0 0.--14. 1. "S2SBT,Slot 2 Start Boundary Time" line.word 0x2 "CH1_S1SBR,Slot 1 Start Boundary Register" hexmask.word 0x2 0.--14. 1. "S1SBT,Slot 0x1: Start Boundary Time" line.word 0x4 "CH1_S4SBR,Slot 4 Start Boundary Register" hexmask.word 0x4 0.--14. 1. "S4SBT,Slot 4 Start Boundary Time" line.word 0x6 "CH1_S3SBR,Slot 3 Start Boundary Register" hexmask.word 0x6 0.--14. 1. "S3SBT,Slot 3 Start Boundary Time" line.word 0x8 "CH1_S6SBR,Slot 6 Start Boundary Register" hexmask.word 0x8 0.--14. 1. "S6SBT,Slot 6 Start Boundary Time" line.word 0xA "CH1_S5SBR,Slot 5 Start Boundary Register" hexmask.word 0xA 0.--14. 1. "S5SBT,Slot 5 Start Boundary Time" group.long 0x35C++0x3 line.long 0x0 "CH1_SNEBR,Slot n End Boundary Register" bitfld.long 0x0 16.--18. "SLOT_NO,The field indicates the Slot number{16} for which Slot End Boundary Time is defined." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--14. 1. "SNEBT,Slot n End Boundary Time" group.word 0x360++0xB line.word 0x0 "CH1_MDDIS_OFF,Manchester Decoder Disable Offset Register" hexmask.word.byte 0x0 0.--6. 1. "MDDIS_OFF,These 7 bits can be used to program the time for which the Manchester decoder remains disabled. This offset is added AFTER the falling edge of the sync pulse. Thus the total time for which the Manchester decoder remains disabled = TsyncH +.." line.word 0x2 "CH1_DOBCR,Data Output Block Configuration Register" hexmask.word.byte 0x2 10.--15. 1. "DATA_LENGTH,Can take on values from 0 to 63 corresponding to 1 bit to 64 bit non standard length commands." newline bitfld.word 0x2 9. "DBR_RST,This is to reset and reject current content to Data Buffer Register. When this bit is written as 1 then the contents of the DBR are reset to all 0s (if DEFAULT_SYNC= = 0) or all 1s (if DEFAULT_SYNC == 1). As soon as content is reset the DBR would.." "0,1" newline bitfld.word 0x2 8. "DSR_RST,This is to reset and reject current content to Data Shift Register.When this bit is written as 1 then the contents of the DSR are reset to all 0s (if DEFAULT_SYNC= = 0) or all 1s (if DEFAULT_SYNC == 1). As soon as content is reset the DSR would.." "0,1" newline bitfld.word 0x2 5.--7. "CMD_TYPE,These 3 bits indicate the type of command that needs to be transmitted during the ECU to sensor communication. Table2061 is a brief description of the same." "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 4. "DEFAULT_SYNC,When this bit is set to 0 then the default value of DSR and DBR registers are all 0s; when this bit is set to 1 then the default value of DBR and DSR registers are all 1s." "0,1" newline bitfld.word 0x2 3. "GTM_TRIG_SEL,GTM event triggered/internal sync pulse generator selection as shift clock for the DSR." "0: Internal sync pulse generator shift triggered,1: GTM event shift triggered" newline bitfld.word 0x2 2. "SP_PULSE_SEL,Selects the source for the short pulse PWM module:" "0: SP module gets the data from the DSR,1: SP module directly gets input from the.." newline bitfld.word 0x2 1. "OP_SEL,This bit selects the driving source of the ipp_do_psi5_sdout port." "0: The sync pulse generator select as per the..,1: PWM output" newline bitfld.word 0x2 0. "SW_READY,When this bit is written to 1 the transfer from DBR to DSR automatically happens as soon as DSR_RDY becomes 1. When this bit is kept to 0 then the transfer from DBR to DSR will remain pending. Once the software makes this bit as 1 and DSR_RDY.." "0,1" line.word 0x4 "CH1_PW1D,Pulse Width for Data Bit 1 Register" hexmask.word.byte 0x4 0.--6. 1. "PULSE_W1DTH1,This defines the width (in microsesc) of data value0x1: to be sent from Data Output Register. It is the number of clock cycles (1 microsesc clock) counted up to width Pulse_Width1; starting as soon as trigger appears from the ISPG(Internal.." line.word 0x6 "CH1_PW0D,Pulse Width for Data Bit 0 Register" hexmask.word.byte 0x6 0.--6. 1. "PULSE_W1DTH0,This defines the width (in microsesc) of data value0x0: to be sent from Data Output Register. It is the number of clock cycles (1 microsesc clock) counted up to width Pulse_Width0; starting as soon as trigger appears from the ISPG (Internal.." line.word 0x8 "CH1_CIPR,Counter Initialize Pulse Register" hexmask.word 0x8 0.--15. 1. "CIPR,Counter initialization pulse register" line.word 0xA "CH1_CTPR,Counter Target Pulse Register" hexmask.word 0xA 0.--15. 1. "CTPR,Counter Target Pulse Register" group.long 0x36C++0x3 line.long 0x0 "CH1_DPRL,Data Preparation Register Low" hexmask.long.tbyte 0x0 0.--23. 1. "DPR,DPR[23:0] are the 24-bits of the DPR register used for writing the variable length standard ECU-to-Sensor commands comprising of the address data and other fields. Note that the IP is transparent to the arrangement of the address data and other.." rgroup.long 0x370++0x3 line.long 0x0 "CH1_DPRH,Data Preparation Register High" group.long 0x374++0xF line.long 0x0 "CH1_DBRL,Data Buffer Register Low" hexmask.long 0x0 0.--31. 1. "DBR,This register contains the Lower 32 bits(DBR[31:0]) of the max-64 bit length command (DBR[63:0]). The higher bits DBR[63:32] are contained in the DBRH register." line.long 0x4 "CH1_DBRH,Data Buffer Register High" hexmask.long 0x4 0.--31. 1. "DBR,This register contains the Upper 32 bits(DBR[63:32]) of the max-64 bit length command (DBR[63:0]). The lower bits DBR[31:0] are contained in the DBRL register." line.long 0x8 "CH1_DSRL,Data Shift Register Low" hexmask.long 0x8 0.--31. 1. "DSR,These bits can be updated by the hardware or can be written by the CPU. The number of accessible bits in DSR are always equal to the number of accessible bits in DBR which in turn depend on the value of PSI5_DOBCR[CMD_TYPE] register bits.When these.." line.long 0xC "CH1_DSRH,Data Shift Register High" hexmask.long 0xC 0.--31. 1. "DSR,These bits can be updated by the hardware or can be written by the CPU. The number of accessible bits in DSR are always equal to the number of accessible bits in DBR which in turn depend on the value of PSI5_DOBCR[CMD_TYPE] register bits. When these.." tree.end tree.end tree "PSI5S (Peripheral Sensor Interface with Serial PHY)" base ad:0x0 tree "PSI5S_0" base ad:0x70F08000 group.long 0x0++0xB line.long 0x0 "LINCR1,PSI5-S LIN control register 1" bitfld.long 0x0 12. "AUTOWU,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x0 6. "SLFM,Self test mode" "0: Self test mode disabled,1: Self test mode enabled" newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" newline bitfld.long 0x0 2. "RBLM,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x0 1. "SLEEP,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x0 0. "INIT,PS_NOUSE_BIT" "0,1" line.long 0x4 "LINIER,PSI5-S LIN interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt generation enabled" newline bitfld.long 0x4 14. "OCIE,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generation enabled" newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt generation enabled" newline bitfld.long 0x4 5. "WUIE,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x4 3. "TOIE,Timeout Interrupt Enable" "0: No interrupt,1: Interrupt generation enabled." newline bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt generation enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt generation enabled" line.long 0x8 "LINSR,PSI5-S LIN status register" bitfld.long 0x8 15. "LINS3,PS_NOUSE_BITS" "0,1" newline bitfld.long 0x8 14. "LINS2,PS_NOUSE_BITS" "0,1" newline bitfld.long 0x8 13. "LINS1,PS_NOUSE_BITS" "0,1" newline bitfld.long 0x8 12. "LINS0,PS_NOUSE_BITS" "0,1" group.long 0x10++0x7 line.long 0x0 "UARTCR,PSI5-S UART mode control register" bitfld.long 0x0 31. "MIS,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x0 28.--30. "CSP,Configurable Sample Point" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--27. 1. "OSR,Over Sampling Rate" newline bitfld.long 0x0 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x0 20.--22. "NEF,PS_NOUSE_BIT" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "PCE_TX_DTU,In PSI5-S mode Parity Control Enable for Tx path (In UART STANDLONE mode used to disable UART timeout refer to Chapter56) LINFlexD for more details):" "0: Parity generation for Tx path disabled.,1: Parity generation for Tx path enabled." newline bitfld.long 0x0 17.--18. "SBUR,PS_NOUSE_BIT" "0,1,2,3" newline bitfld.long 0x0 16. "WLS,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x0 13.--15. "TDFL_TFC,PS_NOUSE_BIT" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10.--12. "RDFL_RFC,PS_NOUSE_BIT" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9. "RFBM,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x0 8. "TFBM,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x0 7. "WL1,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x0 6. "PC1,Parity Control {PC1 PC0}" "0: Parity is Even for both the Rx/Tx paths.,1: Parity is Odd for both the Rx/Tx paths." newline bitfld.long 0x0 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" newline bitfld.long 0x0 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x0 3. "PC0,Parity Control {PC1 PC0}" "0: Parity is Even for both the Rx/Tx paths,1: Parity is Odd for both the Rx/Tx paths." newline bitfld.long 0x0 2. "PCE_RX,Receive Parity check enable." "0: Disable the parity checking on the Rx path,1: Enable the parity checking on the Rx path" newline bitfld.long 0x0 1. "WL0,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x0 0. "UART,PS_NOUSE_BIT" "0,1" line.long 0x4 "UARTSR,PSI5-S UART mode status register" bitfld.long 0x4 15. "SZF,Stuck at Zero flag" "0,1" newline bitfld.long 0x4 14. "OCF,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x4 13. "PE3,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x4 12. "PE2,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x4 11. "PE1,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x4 10. "PE0,Parity Error flag for Data0 byte" "0: No parity error,1: Parity error in the corresponding received byte" newline bitfld.long 0x4 9. "RMB,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x4 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0x4 7. "BOF,Buffer overrun flag" "0,1" newline bitfld.long 0x4 6. "RDI,Receiver Data Input signal" "0,1" newline bitfld.long 0x4 5. "WUF,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x4 4. "RFNE,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x4 3. "TO,Timeout" "0,1" newline bitfld.long 0x4 2. "DRF,Data Reception Completed Flag" "0,1" newline bitfld.long 0x4 1. "DTF,Data Transmission Completed Flag" "0,1" newline bitfld.long 0x4 0. "NF,Noise flag" "0,1" group.long 0x24++0x7 line.long 0x0 "LINFBRR,PSI5-S LIN fractional baud rate register" bitfld.long 0x0 3. "FBR3,Fractional Baud rates. Refer to the Note: on page 2541." "0,1" newline bitfld.long 0x0 2. "FBR2,Fractional Baud rates. Refer to the Note: on page 2541." "0,1" newline bitfld.long 0x0 1. "FBR1,Fractional Baud rates. Refer to the Note: on page 2541." "0,1" newline bitfld.long 0x0 0. "FBR0,Fractional Baud rates. Refer to the Note: on page 2541." "0,1" line.long 0x4 "LINIBRR,LIN integer baud rate register" bitfld.long 0x4 19. "IBR19,Integer Baud rates" "0,1" newline bitfld.long 0x4 18. "IBR18,Integer Baud rates" "0,1" newline bitfld.long 0x4 17. "IBR17,Integer Baud rates" "0,1" newline bitfld.long 0x4 16. "IBR16,Integer Baud rates" "0,1" newline bitfld.long 0x4 15. "IBR15,Integer Baud rates" "0,1" newline bitfld.long 0x4 14. "IBR14,Integer Baud rates" "0,1" newline bitfld.long 0x4 13. "IBR13,Integer Baud rates" "0,1" newline bitfld.long 0x4 12. "IBR12,Integer Baud rates" "0,1" newline bitfld.long 0x4 11. "IBR11,Integer Baud rates" "0,1" newline bitfld.long 0x4 10. "IBR10,Integer Baud rates" "0,1" newline bitfld.long 0x4 9. "IBR9,Integer Baud rates" "0,1" newline bitfld.long 0x4 8. "IBR8,Integer Baud rates" "0,1" newline bitfld.long 0x4 7. "IBR7,Integer Baud rates" "0,1" newline bitfld.long 0x4 6. "IBR6,Integer Baud rates" "0,1" newline bitfld.long 0x4 5. "IBR5,Integer Baud rates" "0,1" newline bitfld.long 0x4 4. "IBR4,Integer Baud rates" "0,1" newline bitfld.long 0x4 3. "IBR3,Integer Baud rates" "0,1" newline bitfld.long 0x4 2. "IBR2,Integer Baud rates" "0,1" newline bitfld.long 0x4 1. "IBR1,Integer Baud rates" "0,1" newline bitfld.long 0x4 0. "IBR0,Integer Baud rates" "0,1" group.long 0x30++0x3 line.long 0x0 "LINCR2,PSI5-S LIN control register 2" bitfld.long 0x0 9. "ABRQ,Abort Request" "0,1" group.long 0x38++0x7 line.long 0x0 "BDRL,PSI5-S buffer data register least significant" hexmask.long.byte 0x0 24.--31. 1. "DATA_TX3,PS_NOUSE_BIT" newline hexmask.long.byte 0x0 16.--23. 1. "DATA_TX2,PS_NOUSE_BIT" newline hexmask.long.byte 0x0 8.--15. 1. "DATA_TX1,PS_NOUSE_BIT" newline hexmask.long.byte 0x0 0.--7. 1. "DATA_TX0,Data Byte for Tx." line.long 0x4 "BDRM,PSI5-S buffer data register most significant" hexmask.long.byte 0x4 24.--31. 1. "DATA_RX3,PS_NOUSE_BIT" newline hexmask.long.byte 0x4 16.--23. 1. "DATA_RX2,PS_NOUSE_BIT" newline hexmask.long.byte 0x4 8.--15. 1. "DATA_RX1,PS_NOUSE_BIT" newline hexmask.long.byte 0x4 0.--7. 1. "DATA_RX0,Receive data byte for Rx" group.long 0x4C++0x7 line.long 0x0 "GCR,PSI5-S global control register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." newline bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" newline bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,PSI5-S UART preset timeout register" bitfld.long 0x4 11. "PTO11,Preset Timeout" "0,1" newline bitfld.long 0x4 10. "PTO10,Preset Timeout" "0,1" newline bitfld.long 0x4 9. "PTO9,Preset Timeout" "0,1" newline bitfld.long 0x4 8. "PTO8,Preset Timeout" "0,1" newline bitfld.long 0x4 7. "PTO7,Preset Timeout" "0,1" newline bitfld.long 0x4 6. "PTO6,Preset Timeout" "0,1" newline bitfld.long 0x4 5. "PTO5,Preset Timeout" "0,1" newline bitfld.long 0x4 4. "PTO4,Preset Timeout" "0,1" newline bitfld.long 0x4 3. "PTO3,Preset Timeout" "0,1" newline bitfld.long 0x4 2. "PTO2,Preset Timeout" "0,1" newline bitfld.long 0x4 1. "PTO1,Preset Timeout" "0,1" newline bitfld.long 0x4 0. "PTO0,Preset Timeout" "0,1" rgroup.long 0x54++0x3 line.long 0x0 "UARTCTO,PSI5-S UART current timeout register" bitfld.long 0x0 11. "CTO11,Current Timeout" "0,1" newline bitfld.long 0x0 10. "CTO10,Current Timeout" "0,1" newline bitfld.long 0x0 9. "CTO9,Current Timeout" "0,1" newline bitfld.long 0x0 8. "CTO8,Current Timeout" "0,1" newline bitfld.long 0x0 7. "CTO7,Current Timeout" "0,1" newline bitfld.long 0x0 6. "CTO6,Current Timeout" "0,1" newline bitfld.long 0x0 5. "CTO5,Current Timeout" "0,1" newline bitfld.long 0x0 4. "CTO4,Current Timeout" "0,1" newline bitfld.long 0x0 3. "CTO3,Current Timeout" "0,1" newline bitfld.long 0x0 2. "CTO2,Current Timeout" "0,1" newline bitfld.long 0x0 1. "CTO1,Current Timeout" "0,1" newline bitfld.long 0x0 0. "CTO0,Current Timeout" "0,1" group.long 0x58++0xB line.long 0x0 "DMATXE,DMA Tx enable register" bitfld.long 0x0 0. "DTE0,PS_NOUSE_BIT" "0,1" line.long 0x4 "DMARXE,DMA Rx enable register" bitfld.long 0x4 0. "DRE0,PS_NOUSE_BIT" "0,1" line.long 0x8 "PTD,PSI5-S UART Tx idle delay time" hexmask.long.byte 0x8 1.--4. 1. "IFD,Interframe Delay" newline bitfld.long 0x8 0. "EN,IFD Enable" "0: The IFD is active in the UART Tx path,1: The IFD is inactive" group.long 0xB4++0x1B line.long 0x0 "GLCR,PSI5-S global control register" bitfld.long 0x0 22.--23. "DIRCMD_LEN,Direct Command Length Register" "0: 1 byte command: 1 byte {DIRCMD_BYTE0} of the..,1: 2 byte command: 2 bytes {DIRCMD_BYTE1..,2: 4 byte command: 4 bytes,3: 4 byte command: 4 bytes {DIRCMD_BYTE3.." newline bitfld.long 0x0 20. "IE_DIRCMD_RDY,Interrupt enable bit for DIRCMD_RDY" "0: PS_GLCR[DIRCMD_RDY] when goes as '1' does not..,1: PS_GLCR[DIRCMD_RDY] when goes as '1' generates.." newline bitfld.long 0x0 18. "DEBUG_EN,Debug enable bit" "0: The IP does not enter the debug mode when a..,1: The IP enters the debug mode immediately as soon.." newline bitfld.long 0x0 15. "GL_DDSR_TRIG,This is the global shift trigger of all the DDSRs of each channel. When the corresponding PS_E2SCR_CH[n][GL_TRIG_SEL]==1 only then is this bit effective else this bit has no effect." "0: Shift triggers of all the DDSR registers are..,1: The shift triggers of all the DDSR's start.." newline bitfld.long 0x0 14. "GL_MODETR_DONE_EN,Interrupt enable for PS_GLSR[GL_MODETR_DONE] bit" "0: No interrupt is generated on setting of the..,1: Generates the interrupt when.." newline bitfld.long 0x0 13. "MRU_ERR_EN,Enables the interrupt for MRU overwrite when the unread contents of MRU Buffer1 are overwritten by a new message." "0: MRU overwrite error is not enabled.,1: MRU overwrite error is enabled." newline bitfld.long 0x0 12. "TSCS_B,This bit controls the selection of clock input to timestamp counter B either by the external periodic clock or by the GTM module." "0: External clock (ipg_clk_ps_ts) is selected.,1: gtm_trig is selected as the clock." newline bitfld.long 0x0 11. "TSCS_A,This bit controls the selection of clock input to timestamp counter A either by the external periodic clock or by the GTM module." "0: External clock (ipg_clk_ps_ts) is selected.,1: gtm_trig is selected as the clock." newline bitfld.long 0x0 10. "CLR_CNTR_B,This bit resets timestamp counter B when PS_GLCR[CLRTSCNT_G_L] is NOT set." "?,1: Timestamp counter B is reset." newline bitfld.long 0x0 9. "CLR_CNTR_A,This bit resets timestamp counter A when PS_GLCR[CLRTSCNT_G_L] is NOT set." "?,1: Timestamp counter A is reset." newline bitfld.long 0x0 8. "CLRTSCNT_G,This bit controls the global clearing of the timestamp counters A and B when CLRTSCNT_G_L==1. When CLRTSCNT_G_L == 0 then this bit has no effect." "?,1: Both timestamp counters are cleared at the same.." newline bitfld.long 0x0 7. "CLRTSCNT_G_L,This bit control whether the timestamp counters counter A and B are cleared simultaneously or independently:" "0: Timestamp counters A and B are cleared..,1: Both timestamp counters are cleared.." newline bitfld.long 0x0 6. "TSCNT_EN_B,This bit controls enabling of timestamp counter A when PS_GLCR[TSCNTEN_G_L] is not set." "0: Timestamp counter A not enabled.,1: Timestamp counter B is enabled." newline bitfld.long 0x0 5. "TSCNT_EN_A,This bit controls enabling of timestamp counter A when PS_GLCR[TSCNTEN_G_L] is not set." "0: Timestamp counter A not enabled.,1: Timestamp counter A is enabled." newline bitfld.long 0x0 4. "TSCNTEN_G,This bit controls the global trigger of the timestamp counters A and B when TSCNTEN_G_L==1. When TSCNTEN_G_L==0x0: then this bit has no effect." "0: then this bit has no effect,1: Both timestamp counters start simultaneously." newline bitfld.long 0x0 3. "TSCNTEN_G_L,This bit control whether the timestamp counters counter A and B are started simultaneously or independently." "0: Timestamp counters A and B are started..,1: Both timestamp counters are triggered.." newline bitfld.long 0x0 0.--2. "GLOBAL_MODE,These are the bits which decide Global Mode of the IP. There are 4 modes UART_STDALONE PS_DISABLE PS_CONFIG and PS_NORMAL. For details of modes related to GLOBAL_MODE bit setting refer to Table1619) State transition." "0,1,2,3,4,5,6,7" line.long 0x4 "GLSR,PSI5-S global status register" bitfld.long 0x4 20. "DIRCMD_RDY,Bit used to indicate the 'Ready for Direct Command write' status:" "0: Direct Command that is written to the PS_DIRCMD..,1: The PS_DIRCMD register is empty and the.." newline bitfld.long 0x4 14. "GL_MODETR_DONE,This bit indicates as to when the global mode transitions as programmed by PS_GLCR[GLOBAL_MODE] have actually been accomplished:" "0: The intended global mode as programmed in the..,1: The global mode as programmed in the.." newline bitfld.long 0x4 13. "MRU_ERR,This bit shows whether unread MRU buffer1 contents have been overwritten by a new message:" "0: No overwrite occurred.,1: Overwrite occurred." newline bitfld.long 0x4 3.--5. "FID,Points to the frame whose data in MRU buffer 1 was overwritten." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "CHID,Points to the channel whose data in MRU buffer 1 was overwritten." "0,1,2,3,4,5,6,7" line.long 0x8 "CH_BASE_ADDR,PSI5-S channel base address register" hexmask.long 0x8 0.--31. 1. "MAILBOX_BASE_ADDR,This register provides the base address of the mailbox in the system RAM.This value needs to be programmed by the software." line.long 0xC "MRU_BUF2_REG0,PSI5-S MRU output buffer 2 register 0" hexmask.long 0xC 0.--31. 1. "CHANNEL_SPECIFIC_MAILBOX_ADDR,This register provides the channel specific mailbox address corresponding to channel and slot for which data has been received.This value is computed by the IP based on the PS_CH_BASE_ADDR[MAILBOX_BASE_ADDR] and FID CID." line.long 0x10 "MRU_BUF2_REG1,PSI5-S MRU output buffer 2 register 1" hexmask.long.byte 0x10 28.--31. 1. "DCI,To ensure that the Application reads the PSI5 message and its timestamp consistently Data Consistency Indicator (DCI) is added to each word of the Message Reconstruction Unit Output buffer and subsequently is transferred to the PSI5 Mailbox in.." newline bitfld.long 0x10 26. "R_UVL_ERR,Message underflow" "0: No error occurred,1: PSI5 message extraction" newline bitfld.long 0x10 25. "N_ERR,Indicates that the number of UART bytes in the received UART packet does not match the number specified in Channel Configuration Register A indicated by CID and FID that is the number of UART bytes does not match the value programmed in.." "0: No error occurred,1: PSI5 message extraction" newline bitfld.long 0x10 22.--24. "CHID,Indicates Channel id of PSI5 message present in the UART header byte." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 19.--21. "FID,Indicates Frame ID of PSI5 message present in the UART header byte." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 18. "R_OVL_ERR,Message overflow.It is set when more than six UART bytes are received in the UART packet.The message may be recoverable (XCRC_ERR == 0) or unrecoverable (XCRC_ERR==1). Refer to Section54.4.2.1: PSI5 message extraction for more details." "0: No error occurred,1: PSI5 message extraction" newline bitfld.long 0x10 17. "F_WD_ERR,Frame watchdog error in the received PSI5 message" "0: No error occurred,1: Error occurred" newline bitfld.long 0x10 16. "SCI_O_ERR,UART overrun error has occurred in at least one UART byte of the received UART packet due to which some UART byte has been lost." "0: No error occurred,1: Error occurred" newline bitfld.long 0x10 15. "SCI_F_ERR,UART framing error has occurred in the current received UART packet." "0: No error occurred,1: Error occurred" newline bitfld.long 0x10 14. "SCI_P_ERR,UART message parity error has occurred in at least one UART byte of the received UART packet." "0: No error occurred,1: Error occurred" newline bitfld.long 0x10 13. "HD_ERR,This bit is set when any of the ERR[1:0] is '1' and indicates a transceiver error." "0: No error occurred,1: Error occurred" newline bitfld.long 0x10 11.--12. "ERR,Transceiver error flags received in the Message header byte of the UART packet indicated by CID and FID." "0,1,2,3" newline bitfld.long 0x10 10. "CRC_ERR_P_ERR,Indicates whether 'PSI5 message' crc_err or the parity error in the PSI5 message indicated by CID and FID has occurred. The Parity is taken as even for PSI5 calculation:" "0: No crc_error/parity error has occurred,1: Indicates crc_error/Parity Error has occurred" newline bitfld.long 0x10 7.--9. "CRC,Contains the received CRC or Parity Bits of the PSI5 message of indicated by CID and FID." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 6. "XCRC_ERR,Indicates xcrc_err in the received UART packet:" "0: No xcrc_error occurred,1: Indicates xcrc_error occurred" newline hexmask.long.byte 0x10 0.--5. 1. "XCRC,This is the value of XCRC received in the last six bits of the UART byte which occurs just before the information of a 'new UART packet received' has been generated. Refer to Section54.4.1: PSI5-S UART message structure and Section54.4.2.5: PSI5-S.." line.long 0x14 "MRU_BUF2_REG2,PSI5-S MRU output buffer 2 register 2" hexmask.long.byte 0x14 28.--31. 1. "DCI,To ensure that the Application reads the PSI5 message and its timestamp consistently Data Consistency Indicator (DCI) is added to each word of the Message Reconstruction Unit Output buffer and subsequently is transferred to the PSI5 Mailbox in.." newline hexmask.long 0x14 0.--27. 1. "PS_DATA,PSI5 data bits extracted from the received UART bytes." line.long 0x18 "MRU_BUF2_REG3,PSI5-S MRU output buffer 2 register 3" hexmask.long.byte 0x18 28.--31. 1. "DCI,To ensure that the Application reads the PSI5 message and its timestamp consistently Data Consistency Indicator (DCI) is added to each word of the Message Reconstruction Unit Output buffer and subsequently is transferred to the PSI5 Mailbox in.." newline hexmask.long.tbyte 0x18 0.--23. 1. "TIMESTAMP,Time stamp value appended based on the various timestamp bit settings in the PS_GLCR register PS_PCCR_CH[n] register and the errors occurred. Refer to Section54.4.4: Timestamp for more details." group.long 0xE0++0x4F line.long 0x0 "MBOX_SR_IRQ,PSI5-S mbox status IRQ" bitfld.long 0x0 7. "MBOX_CH7,When set it Indicates at least one message in mailbox 7 is pending for read by the application." "0,1" newline bitfld.long 0x0 6. "MBOX_CH6,When set it Indicates at least one message in mailbox 6 is pending for read by the application." "0,1" newline bitfld.long 0x0 5. "MBOX_CH5,When set it Indicates at least one message in mailbox 5 is pending for read by the application." "0,1" newline bitfld.long 0x0 4. "MBOX_CH4,When set it Indicates at least one message in mailbox 4 is pending for read by the application." "0,1" newline bitfld.long 0x0 3. "MBOX_CH3,When set it Indicates at least one message in mailbox 3 is pending for read by the application." "0,1" newline bitfld.long 0x0 2. "MBOX_CH2,When set it Indicates at least one message in mailbox 2 is pending for read by the application." "0,1" newline bitfld.long 0x0 1. "MBOX_CH1,When set it Indicates at least one message in mailbox 1is pending for read by the application." "0,1" newline bitfld.long 0x0 0. "MBOX_CH0,When set it Indicates at least one message in mailbox 0is pending for read by the application." "0,1" line.long 0x4 "ERR_SR_IRQ,PSI5-S error status IRQ" bitfld.long 0x4 9. "R_UVL_ERR,When set indicates that message underflow error (number of UART bytes received are less than 3) is present in the message currently present in MRU buf2." "0,1" newline bitfld.long 0x4 8. "N_ERR,When set indicates that N_ERR (Number of UART bytes are not equal to PS_MSGA_CHn[Fn_byte]) is present in the message currently present in MRU buf2." "0,1" newline bitfld.long 0x4 7. "R_OVL_ERR,When set indicates that message Overflow error (number of UART bytes received have exceeded 6) is present in the message currently present in MRU buf2." "0,1" newline bitfld.long 0x4 6. "F_WD_ERR,When set indicates that Frame Watchdog error is present in the message currently present in MRU buf2." "0,1" newline bitfld.long 0x4 5. "SCI_O_ERR,When set indicates that UART Overrun error (from the UART side) is present in the message currently present in MRU buf2. When '1' then this bit indicates that some UART byte belonging to the concerned UART packet has been overwritten by.." "0,1" newline bitfld.long 0x4 4. "SCI_F_ERR,When set indicates that UART Framing error is present in the message currently present in MRU buf2. If this bit is set then it indicates to the application that the synchronization of the UART module is lost and any subsequent UART bytes.." "0,1" newline bitfld.long 0x4 3. "SCI_P_ERR,When set indicates that UART parity error is present in the message currently present in MRU buf2. This bit is set when there is a parity error in any UART byte using which the concerned UART packet was formed." "0,1" newline bitfld.long 0x4 2. "HD_ERR,When set indicates that Header error (E0/E1) is present in the message currently present in MRU buf2." "0,1" newline bitfld.long 0x4 1. "CRC_ERR_P_ERR,When set indicates that PSI5 CRC/Parity error is present in the message currently present in MRU buf2." "0,1" newline bitfld.long 0x4 0. "XCRC_ERR,When set indicates that XCRC error is present in the message currently present in MRU buf2." "0,1" line.long 0x8 "MBOX_SEL_IRQ0,PSI5-S mailbox select IRQ0" bitfld.long 0x8 7. "MBOX_CH7_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH7] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH7] contributes to.." newline bitfld.long 0x8 6. "MBOX_CH6_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH6] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH6] contributes to.." newline bitfld.long 0x8 5. "MBOX_CH5_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH5] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH5] contributes to.." newline bitfld.long 0x8 4. "MBOX_CH4_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH4] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH4] contributes to.." newline bitfld.long 0x8 3. "MBOX_CH3_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH3] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH3] contributes to.." newline bitfld.long 0x8 2. "MBOX_CH2_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH2] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH2] contributes to.." newline bitfld.long 0x8 1. "MBOX_CH1_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH1] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH1] contributes to.." newline bitfld.long 0x8 0. "MBOX_CH0_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH0] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH0] contributes to.." line.long 0xC "ERR_SEL_IRQ0,PSI5-S error select IRQ0" bitfld.long 0xC 9. "R_UVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] contributes to.." newline bitfld.long 0xC 8. "N_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[N_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[N_ERR_SEL] contributes to.." newline bitfld.long 0xC 7. "R_OVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] contributes to.." newline bitfld.long 0xC 6. "F_WD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[F_WD_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[F_WD_ERR_SEL] contributes to.." newline bitfld.long 0xC 5. "SCI_O_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] contributes to.." newline bitfld.long 0xC 4. "SCI_F_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] contributes to.." newline bitfld.long 0xC 3. "SCI_P_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] contributes to.." newline bitfld.long 0xC 2. "HD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[HD_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[HD_ERR_SEL] contributes to.." newline bitfld.long 0xC 1. "CRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[CRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[CRC_ERR_SEL] contributes to.." newline bitfld.long 0xC 0. "XCRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[XCRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[XCRC_ERR_SEL] contributes to.." line.long 0x10 "MBOX_SEL_IRQ1,PSI5-S mailbox select IRQ1" bitfld.long 0x10 7. "MBOX_CH7_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH7] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH7] contributes to.." newline bitfld.long 0x10 6. "MBOX_CH6_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH6] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH6] contributes to.." newline bitfld.long 0x10 5. "MBOX_CH5_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH5] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH5] contributes to.." newline bitfld.long 0x10 4. "MBOX_CH4_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH4] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH4] contributes to.." newline bitfld.long 0x10 3. "MBOX_CH3_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH3] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH3] contributes to.." newline bitfld.long 0x10 2. "MBOX_CH2_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH2] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH2] contributes to.." newline bitfld.long 0x10 1. "MBOX_CH1_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH1] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH1] contributes to.." newline bitfld.long 0x10 0. "MBOX_CH0_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH0] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH0] contributes to.." line.long 0x14 "ERR_SEL_IRQ1,PSI5-S error select IRQ1" bitfld.long 0x14 9. "R_UVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] contributes to.." newline bitfld.long 0x14 8. "N_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[N_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[N_ERR_SEL] contributes to.." newline bitfld.long 0x14 7. "R_OVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] contributes to.." newline bitfld.long 0x14 6. "F_WD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[F_WD_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[F_WD_ERR_SEL] contributes to.." newline bitfld.long 0x14 5. "SCI_O_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] contributes to.." newline bitfld.long 0x14 4. "SCI_F_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] contributes to.." newline bitfld.long 0x14 3. "SCI_P_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] contributes to.." newline bitfld.long 0x14 2. "HD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[HD_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[HD_ERR_SEL] contributes to.." newline bitfld.long 0x14 1. "CRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[CRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[CRC_ERR_SEL] contributes to.." newline bitfld.long 0x14 0. "XCRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[XCRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[XCRC_ERR_SEL] contributes to.." line.long 0x18 "MBOX_SEL_IRQ2,PSI5-S mailbox select IRQ2" bitfld.long 0x18 7. "MBOX_CH7_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH7] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH7] contributes to.." newline bitfld.long 0x18 6. "MBOX_CH6_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH6] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH6] contributes to.." newline bitfld.long 0x18 5. "MBOX_CH5_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH5] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH5] contributes to.." newline bitfld.long 0x18 4. "MBOX_CH4_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH4] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH4] contributes to.." newline bitfld.long 0x18 3. "MBOX_CH3_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH3] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH3] contributes to.." newline bitfld.long 0x18 2. "MBOX_CH2_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH2] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH2] contributes to.." newline bitfld.long 0x18 1. "MBOX_CH1_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH1] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH1] contributes to.." newline bitfld.long 0x18 0. "MBOX_CH0_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH0] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH0] contributes to.." line.long 0x1C "ERR_SEL_IRQ2,PSI5-S error select IRQ2" bitfld.long 0x1C 9. "R_UVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] contributes to.." newline bitfld.long 0x1C 8. "N_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[N_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[N_ERR_SEL] contributes to.." newline bitfld.long 0x1C 7. "R_OVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] contributes to.." newline bitfld.long 0x1C 6. "F_WD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[F_WD_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[F_WD_ERR_SEL] contributes to.." newline bitfld.long 0x1C 5. "SCI_O_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] contributes to.." newline bitfld.long 0x1C 4. "SCI_F_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] contributes to.." newline bitfld.long 0x1C 3. "SCI_P_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] contributes to.." newline bitfld.long 0x1C 2. "HD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[HD_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[HD_ERR_SEL] contributes to.." newline bitfld.long 0x1C 1. "CRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[CRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[CRC_ERR_SEL] contributes to.." newline bitfld.long 0x1C 0. "XCRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[XCRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[XCRC_ERR_SEL] contributes to.." line.long 0x20 "MBOX_SEL_IRQ3,PSI5-S mailbox select IRQ3" bitfld.long 0x20 7. "MBOX_CH7_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH7] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH7] contributes to.." newline bitfld.long 0x20 6. "MBOX_CH6_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH6] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH6] contributes to.." newline bitfld.long 0x20 5. "MBOX_CH5_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH5] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH5] contributes to.." newline bitfld.long 0x20 4. "MBOX_CH4_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH4] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH4] contributes to.." newline bitfld.long 0x20 3. "MBOX_CH3_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH3] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH3] contributes to.." newline bitfld.long 0x20 2. "MBOX_CH2_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH2] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH2] contributes to.." newline bitfld.long 0x20 1. "MBOX_CH1_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH1] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH1] contributes to.." newline bitfld.long 0x20 0. "MBOX_CH0_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH0] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH0] contributes to.." line.long 0x24 "ERR_SEL_IRQ3,PSI5-S error select IRQ3" bitfld.long 0x24 9. "R_UVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] contributes to.." newline bitfld.long 0x24 8. "N_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[N_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[N_ERR_SEL] contributes to.." newline bitfld.long 0x24 7. "R_OVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] contributes to.." newline bitfld.long 0x24 6. "F_WD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[F_WD_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[F_WD_ERR_SEL] contributes to.." newline bitfld.long 0x24 5. "SCI_O_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] contributes to.." newline bitfld.long 0x24 4. "SCI_F_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] contributes to.." newline bitfld.long 0x24 3. "SCI_P_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] contributes to.." newline bitfld.long 0x24 2. "HD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[HD_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[HD_ERR_SEL] contributes to.." newline bitfld.long 0x24 1. "CRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[CRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[CRC_ERR_SEL] contributes to.." newline bitfld.long 0x24 0. "XCRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[XCRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[XCRC_ERR_SEL] contributes to.." line.long 0x28 "MBOX_SEL_IRQ4,PSI5-S mailbox select IRQ4" bitfld.long 0x28 7. "MBOX_CH7_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH7] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH7] contributes to.." newline bitfld.long 0x28 6. "MBOX_CH6_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH6] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH6] contributes to.." newline bitfld.long 0x28 5. "MBOX_CH5_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH5] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH5] contributes to.." newline bitfld.long 0x28 4. "MBOX_CH4_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH4] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH4] contributes to.." newline bitfld.long 0x28 3. "MBOX_CH3_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH3] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH3] contributes to.." newline bitfld.long 0x28 2. "MBOX_CH2_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH2] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH2] contributes to.." newline bitfld.long 0x28 1. "MBOX_CH1_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH1] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH1] contributes to.." newline bitfld.long 0x28 0. "MBOX_CH0_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH0] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH0] contributes to.." line.long 0x2C "ERR_SEL_IRQ4,PSI5-S error select IRQ4" bitfld.long 0x2C 9. "R_UVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] contributes to.." newline bitfld.long 0x2C 8. "N_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[N_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[N_ERR_SEL] contributes to.." newline bitfld.long 0x2C 7. "R_OVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] contributes to.." newline bitfld.long 0x2C 6. "F_WD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[F_WD_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[F_WD_ERR_SEL] contributes to.." newline bitfld.long 0x2C 5. "SCI_O_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] contributes to.." newline bitfld.long 0x2C 4. "SCI_F_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] contributes to.." newline bitfld.long 0x2C 3. "SCI_P_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] contributes to.." newline bitfld.long 0x2C 2. "HD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[HD_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[HD_ERR_SEL] contributes to.." newline bitfld.long 0x2C 1. "CRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[CRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[CRC_ERR_SEL] contributes to.." newline bitfld.long 0x2C 0. "XCRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[XCRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[XCRC_ERR_SEL] contributes to.." line.long 0x30 "MBOX_SEL_IRQ5,PSI5-S mailbox select IRQ5" bitfld.long 0x30 7. "MBOX_CH7_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH7] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH7] contributes to.." newline bitfld.long 0x30 6. "MBOX_CH6_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH6] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH6] contributes to.." newline bitfld.long 0x30 5. "MBOX_CH5_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH5] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH5] contributes to.." newline bitfld.long 0x30 4. "MBOX_CH4_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH4] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH4] contributes to.." newline bitfld.long 0x30 3. "MBOX_CH3_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH3] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH3] contributes to.." newline bitfld.long 0x30 2. "MBOX_CH2_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH2] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH2] contributes to.." newline bitfld.long 0x30 1. "MBOX_CH1_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH1] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH1] contributes to.." newline bitfld.long 0x30 0. "MBOX_CH0_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH0] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH0] contributes to.." line.long 0x34 "ERR_SEL_IRQ5,PSI5-S error select IRQ5" bitfld.long 0x34 9. "R_UVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] contributes to.." newline bitfld.long 0x34 8. "N_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[N_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[N_ERR_SEL] contributes to.." newline bitfld.long 0x34 7. "R_OVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] contributes to.." newline bitfld.long 0x34 6. "F_WD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[F_WD_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[F_WD_ERR_SEL] contributes to.." newline bitfld.long 0x34 5. "SCI_O_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] contributes to.." newline bitfld.long 0x34 4. "SCI_F_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] contributes to.." newline bitfld.long 0x34 3. "SCI_P_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] contributes to.." newline bitfld.long 0x34 2. "HD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[HD_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[HD_ERR_SEL] contributes to.." newline bitfld.long 0x34 1. "CRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[CRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[CRC_ERR_SEL] contributes to.." newline bitfld.long 0x34 0. "XCRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[XCRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[XCRC_ERR_SEL] contributes to.." line.long 0x38 "MBOX_SEL_IRQ6,PSI5-S mailbox select IRQ6" bitfld.long 0x38 7. "MBOX_CH7_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH7] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH7] contributes to.." newline bitfld.long 0x38 6. "MBOX_CH6_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH6] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH6] contributes to.." newline bitfld.long 0x38 5. "MBOX_CH5_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH5] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH5] contributes to.." newline bitfld.long 0x38 4. "MBOX_CH4_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH4] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH4] contributes to.." newline bitfld.long 0x38 3. "MBOX_CH3_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH3] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH3] contributes to.." newline bitfld.long 0x38 2. "MBOX_CH2_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH2] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH2] contributes to.." newline bitfld.long 0x38 1. "MBOX_CH1_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH1] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH1] contributes to.." newline bitfld.long 0x38 0. "MBOX_CH0_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH0] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH0] contributes to.." line.long 0x3C "ERR_SEL_IRQ6,PSI5-S error select IRQ6" bitfld.long 0x3C 9. "R_UVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] contributes to.." newline bitfld.long 0x3C 8. "N_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[N_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[N_ERR_SEL] contributes to.." newline bitfld.long 0x3C 7. "R_OVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] contributes to.." newline bitfld.long 0x3C 6. "F_WD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[F_WD_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[F_WD_ERR_SEL] contributes to.." newline bitfld.long 0x3C 5. "SCI_O_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] contributes to.." newline bitfld.long 0x3C 4. "SCI_F_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] contributes to.." newline bitfld.long 0x3C 3. "SCI_P_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] contributes to.." newline bitfld.long 0x3C 2. "HD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[HD_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[HD_ERR_SEL] contributes to.." newline bitfld.long 0x3C 1. "CRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[CRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[CRC_ERR_SEL] contributes to.." newline bitfld.long 0x3C 0. "XCRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[XCRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[XCRC_ERR_SEL] contributes to.." line.long 0x40 "MBOX_SEL_IRQ7,PSI5-S mailbox select IRQ7" bitfld.long 0x40 7. "MBOX_CH7_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH7] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH7] contributes to.." newline bitfld.long 0x40 6. "MBOX_CH6_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH6] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH6] contributes to.." newline bitfld.long 0x40 5. "MBOX_CH5_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH5] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH5] contributes to.." newline bitfld.long 0x40 4. "MBOX_CH4_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH4] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH4] contributes to.." newline bitfld.long 0x40 3. "MBOX_CH3_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH3] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH3] contributes to.." newline bitfld.long 0x40 2. "MBOX_CH2_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH2] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH2] contributes to.." newline bitfld.long 0x40 1. "MBOX_CH1_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH1] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH1] contributes to.." newline bitfld.long 0x40 0. "MBOX_CH0_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH0] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH0] contributes to.." line.long 0x44 "ERR_SEL_IRQ7,PSI5-S error select IRQ7" bitfld.long 0x44 9. "R_UVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] contributes to.." newline bitfld.long 0x44 8. "N_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[N_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[N_ERR_SEL] contributes to.." newline bitfld.long 0x44 7. "R_OVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] contributes to.." newline bitfld.long 0x44 6. "F_WD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[F_WD_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[F_WD_ERR_SEL] contributes to.." newline bitfld.long 0x44 5. "SCI_O_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] contributes to.." newline bitfld.long 0x44 4. "SCI_F_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] contributes to.." newline bitfld.long 0x44 3. "SCI_P_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] contributes to.." newline bitfld.long 0x44 2. "HD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[HD_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[HD_ERR_SEL] contributes to.." newline bitfld.long 0x44 1. "CRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[CRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[CRC_ERR_SEL] contributes to.." newline bitfld.long 0x44 0. "XCRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[XCRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[XCRC_ERR_SEL] contributes to.." line.long 0x48 "WDGTSSR,PSI5-S watchdog error status and watchdog timestamp status register" hexmask.long.byte 0x48 25.--31. 1. "F_WD_ERR_STATUS,F_WD_ERR_STATUS[7:1]" newline hexmask.long.tbyte 0x48 0.--23. 1. "WDGTS_STATUS,Timestamp value of that specific channel the timestamp of which is captured when the watchdog error of that specific channel has occurred." line.long 0x4C "DIRCMD,PSI5-S ECU to sensor direct command write register" hexmask.long.byte 0x4C 24.--31. 1. "DIRCMD_BYTE3,Byte3 of the Direct Command" newline hexmask.long.byte 0x4C 16.--23. 1. "DIRCMD_BYTE2,Byte2 of the Direct Command" newline hexmask.long.byte 0x4C 8.--15. 1. "DIRCMD_BYTE1,Byte1 of the Direct Command" newline hexmask.long.byte 0x4C 0.--7. 1. "DIRCMD_BYTE0,Byte0 of the Direct Command" group.long 0x16C++0x7 line.long 0x0 "MSGA_CH0,PSI5-S channel 0 message configuration register A" bitfld.long 0x0 8.--10. "F0_BYTE,Number of UART bytes comprising one UART packet. Applicable only to special messages having CID = 0 in their Message Header." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "TIME_STAMP_A_B_SEL,Whether the Timestamp corresponding to timestamp counter A or B is appended to messages targeted for Channel0." "0: Timestamp counter A,1: Timestamp counter B" newline bitfld.long 0x0 3. "TSBUF_CLR,This bit is used to clear the local timestamp buffer for the respective channel.Once cleared the buffer remains clear till the event to capture time stamp is triggered." "?,1: Timestamp buffer is cleared." newline bitfld.long 0x0 2. "TSBUF_EN,This bit controls whether timestamp buffer maintains a value '0' or is refreshed on a timestamp 'capture event'." "0: Timestamp buffer maintains value '0'.,1: Timestamp buffer responds to a 'capture event'.." line.long 0x4 "MSGB_CH0,PSI5-S channel 0 message configuration register B" hexmask.long.byte 0x4 0.--4. 1. "F0_PAYLOAD,Number of bits in payload region of the message (only for channels having CID as '0' in the message header). This channel is always asynchronous." group.long 0x178++0x3 line.long 0x0 "MBOX_SR_CH0,PSI5-S mailbox status register channel 0" bitfld.long 0x0 5. "F1_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when an unrecoverable message (with the CID = 0 and FID=1) is read from the MRU_BUF2." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 4. "F1_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX0 LOC1." "0: No overwrite of unread message in MBOX0 LOC1.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 3. "F1_READ,MBOX0 LOC1 is reserved for any unrecoverable message (XCRC_ERR has occurred or it is an 'illegal message'). It can correspond to any channel from 1 to 7." "0: No unread message in MBOX0.LOC1.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 2. "F0_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when a transceiver message (with the CID = 0 and FID=0) is read from the MRU_BUF2." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 1. "F0_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX0 LOC0." "0: No overwrite of unread message in MBOX0 LOC0.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 0. "F0_READ,MBOX0 LOC0 is reserved for a transceiver message." "0: No unread message in MBOX0 LOC0.,1: It indicates that the message that has just been.." group.long 0x190++0x7 line.long 0x0 "MSGA_CH1,PSI5-S channel message configuration register A" bitfld.long 0x0 31. "L_PC_EN,Selects whether the parity/CRC selection for a PSI5 message is to be controlled globally on a channel basis (through the G_PC bits) or locally on a per frame basis (through the L_PC[frame] bits)." "0: Parity/CRC option controlled globally through..,1: Parity/CRC option controlled locally through the.." newline bitfld.long 0x0 28.--30. "F5_BYTE,Number of bytes in UART packet for message corresponding to frame 5." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "L_PC5,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame5.,1: CRC selected for PSI5 message for frame5." newline bitfld.long 0x0 24.--26. "F4_BYTE,Number of bytes in UART packet for message corresponding to frame 4." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "L_PC4,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame4.,1: CRC selected for PSI5 message for frame4." newline bitfld.long 0x0 20.--22. "F3_BYTE,Number of bytes in UART packet for message corresponding to frame 3." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "L_PC3,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame3.,1: CRC selected for PSI5 message for frame3." newline bitfld.long 0x0 16.--18. "F2_BYTE,Number of bytes in UART packet for message corresponding to frame 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "L_PC2,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame2.,1: CRC selected for PSI5 message for frame2." newline bitfld.long 0x0 12.--14. "F1_BYTE,Number of bytes in UART packet for message corresponding to frame 1." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "L_PC1,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame1.,1: CRC selected for PSI5 message for frame1." newline bitfld.long 0x0 8.--10. "F0_BYTE,Number of bytes in UART packet for message corresponding to frame 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "L_PC0,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame0.,1: CRC selected for PSI5 message for frame0." newline bitfld.long 0x0 6. "MODE,This bit selects the operating modes between sync and async for the channel." "0: Synchronous.,1: Asynchronous." newline bitfld.long 0x0 5. "TIME_STAMP_A_B_SEL,Decides whether timestamp counter A or B value is captured in the local timestamp buffer whenever a 'capture event' occurs." "0: Timestamp counter A.,1: Timestamp counter B." newline bitfld.long 0x0 4. "TMSG_TCMD,Whether the timestamp is recorded when the message is received or when the channel command is moved from the TxFIFO to the UART Tx register (emulates a sync pulse)" "0: Timestamp recorded based on 'emulated' sync pulse.,1: Timestamp recorded based on message header byte.." newline bitfld.long 0x0 3. "TSBUF_CLR,This bit is used to clear the local timestamp buffer for the respective channel.Once cleared the buffer remains clear till the event to capture time stamp is triggered." "?,1: Timestamp buffer is cleared." newline bitfld.long 0x0 2. "TSBUF_EN,This bit controls whether timestamp buffer maintains a value '0' or is refreshed on a timestamp 'capture event'." "0: Timestamp buffer maintains value '0'.,1: Timestamp buffer responds to a 'capture event'.." newline bitfld.long 0x0 1. "G_PC,This bit globally selects the Parity or the CRC option for all the Frames of that particular channel" "0: Parity option selected globally for messages of..,1: CRC option selected globally for messages of all.." newline bitfld.long 0x0 0. "CH_EN,PSI5 Channel Enable. This bit decides if the IP takes the data belonging to the specific channel as 'legal' or 'illegal'." "0: Concerned PSI5 channel is disabled. Any data..,1: PSI5 message extraction for the definition of.." line.long 0x4 "MSGB_CH1,PSI5-S channel message configuration register B" hexmask.long.byte 0x4 25.--29. 1. "F5_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 5." newline hexmask.long.byte 0x4 20.--24. 1. "F4_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 4." newline hexmask.long.byte 0x4 15.--19. 1. "F3_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 3." newline hexmask.long.byte 0x4 10.--14. 1. "F2_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 2." newline hexmask.long.byte 0x4 5.--9. 1. "F1_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 1." newline hexmask.long.byte 0x4 0.--4. 1. "F0_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 0." group.long 0x19C++0x1F line.long 0x0 "MBOX_SR_CH1,PSI5-S mailbox status register channel" bitfld.long 0x0 17. "F5_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=5) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 16. "F5_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No overwrite of unread message in MBOX[n] LOC5.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 15. "F5_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No unread message in MBOX[n] LOC5.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 14. "F4_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=4) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 13. "F4_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No overwrite of unread message in MBOX[n] LOC4.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 12. "F4_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No unread message in MBOX[n] LOC4.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 11. "F3_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=3) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 10. "F3_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No overwrite of unread message in MBOX[n] LOC3.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 9. "F3_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No unread message in MBOX[n] LOC3.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 8. "F2_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=2) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 7. "F2_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No overwrite of unread message in MBOX[n] LOC2.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 6. "F2_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No unread message in MBOX[n] LOC2.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 5. "F1_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=1) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 4. "F1_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No overwrite of unread message in MBOX[n] LOC1.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 3. "F1_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No unread message in MBOX[n] LOC1.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 2. "F0_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=0) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 1. "F0_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No overwrite of unread message in MBOX[n] LOC0.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 0. "F0_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No unread message in MBOX[n] LOC0.,1: It indicates that the message that has just been.." line.long 0x4 "WD_CFGR_CH1,PSI5-S channel watchdog configuration register" bitfld.long 0x4 27. "WDRST,Resets watchdog counter for the channel" "0,1" newline bitfld.long 0x4 26. "WDCS,This selects either GTM or the module clock for watchdog counter of the channel. See Figure1629) Clock distribution in PSI5-S." "0: ipg_clk_ps_wd clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x4 25. "WDEN,The watchdog counter for each channel can be started stopped." "0: Watchdog counter stopped. It maintains its value.,1: Watchdog counter started." newline hexmask.long.tbyte 0x4 0.--23. 1. "WD_TO,This indicates the watchdog time out value. The watchdog generates an overrun error in case the watchdog is not refreshed before the watchdog counter reached the WD_TO value." line.long 0x8 "DDTRIG_OFFR_CH1,PSI5-S DDSR trigger offset register channel" hexmask.long.word 0x8 0.--15. 1. "DDTRIG_OFFR,These bits configure the delay between the 'shift trigger' of the various DDSRs across different channels. The value in this register governs the delay after which the specific DDSR is triggered once the Global Shift trigger.." line.long 0xC "DDTRIG_PERR_CH1,PSI5-S DDSR trigger period register channel" hexmask.long.word 0xC 0.--15. 1. "DDTRIG_PERR,These bits configure the 'shift trigger' period for the DDSR of that specific channel. The value in this register governs the period with which the data for the DDSR of that particular channel is shifted out." line.long 0x10 "E2SCR_CH1,PSI5-S ECU to sensor control register" hexmask.long.byte 0x10 26.--30. 1. "CMD,Bits for the ECU-to-sensor 'CMD' format. They refer to the command send to the UART Tx logic when a '1' is shifted from the DDSR register." newline hexmask.long.byte 0x10 20.--24. 1. "ACMD,Bits for the ECU-to-sensor 'ACMD' format. They refer to the command send to the UART Tx logic when a '0' is shifted from the DDSR register." newline bitfld.long 0x10 17. "CH_TRIG,This controls that the DDSR of the specific channel is triggered locally. This bit controls the shifting when PS_E2SCR_CHn[GL_TRIG_SEL] is 0." "0: Stop the DDSR from shifting the commands. The..,1: Start the 'shift trigger' of the DDSR." newline bitfld.long 0x10 16. "GL_TRIG_SEL,This bit controls whether the DDSR shift trigger is a global trigger or a local channel trigger." "0: The DDSR shift trigger is a local channel..,1: The DDSR shift trigger is a global trigger.." newline bitfld.long 0x10 15. "DEFAULT_SYNC,Decides the value to which the DDSR has to default to when PS_E2SSR_CHn[DDSR_RDY] == 1." "0,1" newline bitfld.long 0x10 14. "DDSR_SHIFT_SEL,DDSR Shift Selection" "0: The shift trigger is from internal DDSR counters..,1: The input signal gtm_trig directly acts as the.." newline bitfld.long 0x10 13. "DDSR_CLR,Used for rejecting the contents of the DDSR register." "0,1" newline bitfld.long 0x10 12. "DDSR_CLK_SEL,Selects which clock clocks shift logic of the DDSR for shifting the bits for command transmission." "0: ipg_clk_ps_ddtrig clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x10 11. "CMDTR_SW_CTRL,Once the command is ready for transmission (indicated by the setting PS_E2SSR_CHn[CMDPR_BZY] to 1) this bit decides when the actual transmission has to start:" "0: The actual transmission of command remains..,1: The command transmission starts once the.." newline bitfld.long 0x10 9. "SYNCHRO_OVF_IE,Synchro overflow interrupt enable" "0: No interrupt is generated when..,1: Generate an interrupt when.." newline bitfld.long 0x10 7. "CMDTR_NWRT_IE,Interrupt Enable for DDSR being attempted to be written when it is still not empty that is PS_E2SSR_CHn[DDSR_RDY] == 0 yet an attempt to write to DDSR is made." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 6. "CMDPR_BZY_IE,Interrupt Enable for DDSR getting updated with the internally processed complete command (with CRC stuff bits start bits getting appended)." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 5. "DDSR_RDY_IE,Interrupt Enable for DDSR getting empty and ready for receiving new command." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 0.--2. "CMD_TYPE," "0,1,2,3,4,5,6,7" line.long 0x14 "E2SSR_CH1,PSI5-S ECU to sensor status register" bitfld.long 0x14 9. "SYNCHRO_OVF,This bit gets set whenever due to any reason (like too less DDTRIG period) sync pulse of a channel comes before the previous sync pulse of the same channel has actually shifted its data." "0: No synch pulse overflow has occurred in the..,1: Synch Pulse overflow has occurred for the.." newline bitfld.long 0x14 7. "CMDTR_NWRT,Status of Command written to the DDSR:" "0: Command written to the DDSR has been accepted..,1: Command written to the DDSR is rejected as an.." newline bitfld.long 0x14 6. "CMDPR_BZY,Command Processing Busy Status" "0: DDSR is busy with command processing. For this..,1: DDSR is ready with the processed command.." newline bitfld.long 0x14 5. "DDSR_RDY,Status for DDSR getting empty and ready for receiving new command." "0: DDSR is not ready and is busy with either the..,1: DDSR is empty and ready for receiving a new.." line.long 0x18 "DDSR_H_CH1,PSI5-S channel1 ECU to sensor downstream data shift register high" hexmask.long.word 0x18 0.--10. 1. "DDSR_H,Upper High bits of the 43 bit complete DDSR register. These bits are updated by the hardware and software cannot write to these bits." line.long 0x1C "DDSR_L_CH1,PSI5-S channel1 ECU to sensor downstream data shift register low" hexmask.long.byte 0x1C 24.--31. 1. "DDSR_L1,8 bits of the DDSR_L that can only be read by the Application. These 8 bits are automatically updated by the hardware. They can be read by the software to check for the processed command after the command is written to the DDSR by the.." newline hexmask.long.tbyte 0x1C 0.--23. 1. "DDSR_L0,Lower 24 bits of the DDSR register that are written by the Application as well as updated by the hardware once the command processing is over." group.long 0x1CC++0x7 line.long 0x0 "MSGA_CH2,PSI5-S channel message configuration register A" bitfld.long 0x0 31. "L_PC_EN,Selects whether the parity/CRC selection for a PSI5 message is to be controlled globally on a channel basis (through the G_PC bits) or locally on a per frame basis (through the L_PC[frame] bits)." "0: Parity/CRC option controlled globally through..,1: Parity/CRC option controlled locally through the.." newline bitfld.long 0x0 28.--30. "F5_BYTE,Number of bytes in UART packet for message corresponding to frame 5." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "L_PC5,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame5.,1: CRC selected for PSI5 message for frame5." newline bitfld.long 0x0 24.--26. "F4_BYTE,Number of bytes in UART packet for message corresponding to frame 4." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "L_PC4,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame4.,1: CRC selected for PSI5 message for frame4." newline bitfld.long 0x0 20.--22. "F3_BYTE,Number of bytes in UART packet for message corresponding to frame 3." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "L_PC3,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame3.,1: CRC selected for PSI5 message for frame3." newline bitfld.long 0x0 16.--18. "F2_BYTE,Number of bytes in UART packet for message corresponding to frame 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "L_PC2,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame2.,1: CRC selected for PSI5 message for frame2." newline bitfld.long 0x0 12.--14. "F1_BYTE,Number of bytes in UART packet for message corresponding to frame 1." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "L_PC1,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame1.,1: CRC selected for PSI5 message for frame1." newline bitfld.long 0x0 8.--10. "F0_BYTE,Number of bytes in UART packet for message corresponding to frame 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "L_PC0,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame0.,1: CRC selected for PSI5 message for frame0." newline bitfld.long 0x0 6. "MODE,This bit selects the operating modes between sync and async for the channel." "0: Synchronous.,1: Asynchronous." newline bitfld.long 0x0 5. "TIME_STAMP_A_B_SEL,Decides whether timestamp counter A or B value is captured in the local timestamp buffer whenever a 'capture event' occurs." "0: Timestamp counter A.,1: Timestamp counter B." newline bitfld.long 0x0 4. "TMSG_TCMD,Whether the timestamp is recorded when the message is received or when the channel command is moved from the TxFIFO to the UART Tx register (emulates a sync pulse)" "0: Timestamp recorded based on 'emulated' sync pulse.,1: Timestamp recorded based on message header byte.." newline bitfld.long 0x0 3. "TSBUF_CLR,This bit is used to clear the local timestamp buffer for the respective channel.Once cleared the buffer remains clear till the event to capture time stamp is triggered." "?,1: Timestamp buffer is cleared." newline bitfld.long 0x0 2. "TSBUF_EN,This bit controls whether timestamp buffer maintains a value '0' or is refreshed on a timestamp 'capture event'." "0: Timestamp buffer maintains value '0'.,1: Timestamp buffer responds to a 'capture event'.." newline bitfld.long 0x0 1. "G_PC,This bit globally selects the Parity or the CRC option for all the Frames of that particular channel" "0: Parity option selected globally for messages of..,1: CRC option selected globally for messages of all.." newline bitfld.long 0x0 0. "CH_EN,PSI5 Channel Enable. This bit decides if the IP takes the data belonging to the specific channel as 'legal' or 'illegal'." "0: Concerned PSI5 channel is disabled. Any data..,1: PSI5 message extraction for the definition of.." line.long 0x4 "MSGB_CH2,PSI5-S channel message configuration register B" hexmask.long.byte 0x4 25.--29. 1. "F5_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 5." newline hexmask.long.byte 0x4 20.--24. 1. "F4_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 4." newline hexmask.long.byte 0x4 15.--19. 1. "F3_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 3." newline hexmask.long.byte 0x4 10.--14. 1. "F2_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 2." newline hexmask.long.byte 0x4 5.--9. 1. "F1_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 1." newline hexmask.long.byte 0x4 0.--4. 1. "F0_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 0." group.long 0x1D8++0x1F line.long 0x0 "MBOX_SR_CH2,PSI5-S mailbox status register channel" bitfld.long 0x0 17. "F5_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=5) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 16. "F5_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No overwrite of unread message in MBOX[n] LOC5.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 15. "F5_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No unread message in MBOX[n] LOC5.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 14. "F4_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=4) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 13. "F4_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No overwrite of unread message in MBOX[n] LOC4.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 12. "F4_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No unread message in MBOX[n] LOC4.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 11. "F3_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=3) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 10. "F3_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No overwrite of unread message in MBOX[n] LOC3.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 9. "F3_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No unread message in MBOX[n] LOC3.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 8. "F2_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=2) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 7. "F2_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No overwrite of unread message in MBOX[n] LOC2.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 6. "F2_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No unread message in MBOX[n] LOC2.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 5. "F1_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=1) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 4. "F1_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No overwrite of unread message in MBOX[n] LOC1.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 3. "F1_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No unread message in MBOX[n] LOC1.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 2. "F0_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=0) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 1. "F0_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No overwrite of unread message in MBOX[n] LOC0.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 0. "F0_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No unread message in MBOX[n] LOC0.,1: It indicates that the message that has just been.." line.long 0x4 "WD_CFGR_CH2,PSI5-S channel watchdog configuration register" bitfld.long 0x4 27. "WDRST,Resets watchdog counter for the channel" "0,1" newline bitfld.long 0x4 26. "WDCS,This selects either GTM or the module clock for watchdog counter of the channel. See Figure1629) Clock distribution in PSI5-S." "0: ipg_clk_ps_wd clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x4 25. "WDEN,The watchdog counter for each channel can be started stopped." "0: Watchdog counter stopped. It maintains its value.,1: Watchdog counter started." newline hexmask.long.tbyte 0x4 0.--23. 1. "WD_TO,This indicates the watchdog time out value. The watchdog generates an overrun error in case the watchdog is not refreshed before the watchdog counter reached the WD_TO value." line.long 0x8 "DDTRIG_OFFR_CH2,PSI5-S DDSR trigger offset register channel" hexmask.long.word 0x8 0.--15. 1. "DDTRIG_OFFR,These bits configure the delay between the 'shift trigger' of the various DDSRs across different channels. The value in this register governs the delay after which the specific DDSR is triggered once the Global Shift trigger.." line.long 0xC "DDTRIG_PERR_CH2,PSI5-S DDSR trigger period register channel" hexmask.long.word 0xC 0.--15. 1. "DDTRIG_PERR,These bits configure the 'shift trigger' period for the DDSR of that specific channel. The value in this register governs the period with which the data for the DDSR of that particular channel is shifted out." line.long 0x10 "E2SCR_CH2,PSI5-S ECU to sensor control register" hexmask.long.byte 0x10 26.--30. 1. "CMD,Bits for the ECU-to-sensor 'CMD' format. They refer to the command send to the UART Tx logic when a '1' is shifted from the DDSR register." newline hexmask.long.byte 0x10 20.--24. 1. "ACMD,Bits for the ECU-to-sensor 'ACMD' format. They refer to the command send to the UART Tx logic when a '0' is shifted from the DDSR register." newline bitfld.long 0x10 17. "CH_TRIG,This controls that the DDSR of the specific channel is triggered locally. This bit controls the shifting when PS_E2SCR_CHn[GL_TRIG_SEL] is 0." "0: Stop the DDSR from shifting the commands. The..,1: Start the 'shift trigger' of the DDSR." newline bitfld.long 0x10 16. "GL_TRIG_SEL,This bit controls whether the DDSR shift trigger is a global trigger or a local channel trigger." "0: The DDSR shift trigger is a local channel..,1: The DDSR shift trigger is a global trigger.." newline bitfld.long 0x10 15. "DEFAULT_SYNC,Decides the value to which the DDSR has to default to when PS_E2SSR_CHn[DDSR_RDY] == 1." "0,1" newline bitfld.long 0x10 14. "DDSR_SHIFT_SEL,DDSR Shift Selection" "0: The shift trigger is from internal DDSR counters..,1: The input signal gtm_trig directly acts as the.." newline bitfld.long 0x10 13. "DDSR_CLR,Used for rejecting the contents of the DDSR register." "0,1" newline bitfld.long 0x10 12. "DDSR_CLK_SEL,Selects which clock clocks shift logic of the DDSR for shifting the bits for command transmission." "0: ipg_clk_ps_ddtrig clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x10 11. "CMDTR_SW_CTRL,Once the command is ready for transmission (indicated by the setting PS_E2SSR_CHn[CMDPR_BZY] to 1) this bit decides when the actual transmission has to start:" "0: The actual transmission of command remains..,1: The command transmission starts once the.." newline bitfld.long 0x10 9. "SYNCHRO_OVF_IE,Synchro overflow interrupt enable" "0: No interrupt is generated when..,1: Generate an interrupt when.." newline bitfld.long 0x10 7. "CMDTR_NWRT_IE,Interrupt Enable for DDSR being attempted to be written when it is still not empty that is PS_E2SSR_CHn[DDSR_RDY] == 0 yet an attempt to write to DDSR is made." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 6. "CMDPR_BZY_IE,Interrupt Enable for DDSR getting updated with the internally processed complete command (with CRC stuff bits start bits getting appended)." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 5. "DDSR_RDY_IE,Interrupt Enable for DDSR getting empty and ready for receiving new command." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 0.--2. "CMD_TYPE," "0,1,2,3,4,5,6,7" line.long 0x14 "E2SSR_CH2,PSI5-S ECU to sensor status register" bitfld.long 0x14 9. "SYNCHRO_OVF,This bit gets set whenever due to any reason (like too less DDTRIG period) sync pulse of a channel comes before the previous sync pulse of the same channel has actually shifted its data." "0: No synch pulse overflow has occurred in the..,1: Synch Pulse overflow has occurred for the.." newline bitfld.long 0x14 7. "CMDTR_NWRT,Status of Command written to the DDSR:" "0: Command written to the DDSR has been accepted..,1: Command written to the DDSR is rejected as an.." newline bitfld.long 0x14 6. "CMDPR_BZY,Command Processing Busy Status" "0: DDSR is busy with command processing. For this..,1: DDSR is ready with the processed command.." newline bitfld.long 0x14 5. "DDSR_RDY,Status for DDSR getting empty and ready for receiving new command." "0: DDSR is not ready and is busy with either the..,1: DDSR is empty and ready for receiving a new.." line.long 0x18 "DDSR_H_CH2,PSI5-S channel1 ECU to sensor downstream data shift register high" hexmask.long.word 0x18 0.--10. 1. "DDSR_H,Upper High bits of the 43 bit complete DDSR register. These bits are updated by the hardware and software cannot write to these bits." line.long 0x1C "DDSR_L_CH2,PSI5-S channel1 ECU to sensor downstream data shift register low" hexmask.long.byte 0x1C 24.--31. 1. "DDSR_L1,8 bits of the DDSR_L that can only be read by the Application. These 8 bits are automatically updated by the hardware. They can be read by the software to check for the processed command after the command is written to the DDSR by the.." newline hexmask.long.tbyte 0x1C 0.--23. 1. "DDSR_L0,Lower 24 bits of the DDSR register that are written by the Application as well as updated by the hardware once the command processing is over." group.long 0x208++0x7 line.long 0x0 "MSGA_CH3,PSI5-S channel message configuration register A" bitfld.long 0x0 31. "L_PC_EN,Selects whether the parity/CRC selection for a PSI5 message is to be controlled globally on a channel basis (through the G_PC bits) or locally on a per frame basis (through the L_PC[frame] bits)." "0: Parity/CRC option controlled globally through..,1: Parity/CRC option controlled locally through the.." newline bitfld.long 0x0 28.--30. "F5_BYTE,Number of bytes in UART packet for message corresponding to frame 5." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "L_PC5,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame5.,1: CRC selected for PSI5 message for frame5." newline bitfld.long 0x0 24.--26. "F4_BYTE,Number of bytes in UART packet for message corresponding to frame 4." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "L_PC4,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame4.,1: CRC selected for PSI5 message for frame4." newline bitfld.long 0x0 20.--22. "F3_BYTE,Number of bytes in UART packet for message corresponding to frame 3." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "L_PC3,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame3.,1: CRC selected for PSI5 message for frame3." newline bitfld.long 0x0 16.--18. "F2_BYTE,Number of bytes in UART packet for message corresponding to frame 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "L_PC2,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame2.,1: CRC selected for PSI5 message for frame2." newline bitfld.long 0x0 12.--14. "F1_BYTE,Number of bytes in UART packet for message corresponding to frame 1." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "L_PC1,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame1.,1: CRC selected for PSI5 message for frame1." newline bitfld.long 0x0 8.--10. "F0_BYTE,Number of bytes in UART packet for message corresponding to frame 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "L_PC0,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame0.,1: CRC selected for PSI5 message for frame0." newline bitfld.long 0x0 6. "MODE,This bit selects the operating modes between sync and async for the channel." "0: Synchronous.,1: Asynchronous." newline bitfld.long 0x0 5. "TIME_STAMP_A_B_SEL,Decides whether timestamp counter A or B value is captured in the local timestamp buffer whenever a 'capture event' occurs." "0: Timestamp counter A.,1: Timestamp counter B." newline bitfld.long 0x0 4. "TMSG_TCMD,Whether the timestamp is recorded when the message is received or when the channel command is moved from the TxFIFO to the UART Tx register (emulates a sync pulse)" "0: Timestamp recorded based on 'emulated' sync pulse.,1: Timestamp recorded based on message header byte.." newline bitfld.long 0x0 3. "TSBUF_CLR,This bit is used to clear the local timestamp buffer for the respective channel.Once cleared the buffer remains clear till the event to capture time stamp is triggered." "?,1: Timestamp buffer is cleared." newline bitfld.long 0x0 2. "TSBUF_EN,This bit controls whether timestamp buffer maintains a value '0' or is refreshed on a timestamp 'capture event'." "0: Timestamp buffer maintains value '0'.,1: Timestamp buffer responds to a 'capture event'.." newline bitfld.long 0x0 1. "G_PC,This bit globally selects the Parity or the CRC option for all the Frames of that particular channel" "0: Parity option selected globally for messages of..,1: CRC option selected globally for messages of all.." newline bitfld.long 0x0 0. "CH_EN,PSI5 Channel Enable. This bit decides if the IP takes the data belonging to the specific channel as 'legal' or 'illegal'." "0: Concerned PSI5 channel is disabled. Any data..,1: PSI5 message extraction for the definition of.." line.long 0x4 "MSGB_CH3,PSI5-S channel message configuration register B" hexmask.long.byte 0x4 25.--29. 1. "F5_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 5." newline hexmask.long.byte 0x4 20.--24. 1. "F4_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 4." newline hexmask.long.byte 0x4 15.--19. 1. "F3_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 3." newline hexmask.long.byte 0x4 10.--14. 1. "F2_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 2." newline hexmask.long.byte 0x4 5.--9. 1. "F1_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 1." newline hexmask.long.byte 0x4 0.--4. 1. "F0_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 0." group.long 0x214++0x1F line.long 0x0 "MBOX_SR_CH3,PSI5-S mailbox status register channel" bitfld.long 0x0 17. "F5_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=5) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 16. "F5_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No overwrite of unread message in MBOX[n] LOC5.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 15. "F5_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No unread message in MBOX[n] LOC5.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 14. "F4_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=4) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 13. "F4_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No overwrite of unread message in MBOX[n] LOC4.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 12. "F4_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No unread message in MBOX[n] LOC4.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 11. "F3_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=3) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 10. "F3_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No overwrite of unread message in MBOX[n] LOC3.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 9. "F3_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No unread message in MBOX[n] LOC3.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 8. "F2_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=2) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 7. "F2_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No overwrite of unread message in MBOX[n] LOC2.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 6. "F2_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No unread message in MBOX[n] LOC2.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 5. "F1_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=1) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 4. "F1_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No overwrite of unread message in MBOX[n] LOC1.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 3. "F1_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No unread message in MBOX[n] LOC1.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 2. "F0_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=0) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 1. "F0_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No overwrite of unread message in MBOX[n] LOC0.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 0. "F0_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No unread message in MBOX[n] LOC0.,1: It indicates that the message that has just been.." line.long 0x4 "WD_CFGR_CH3,PSI5-S channel watchdog configuration register" bitfld.long 0x4 27. "WDRST,Resets watchdog counter for the channel" "0,1" newline bitfld.long 0x4 26. "WDCS,This selects either GTM or the module clock for watchdog counter of the channel. See Figure1629) Clock distribution in PSI5-S." "0: ipg_clk_ps_wd clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x4 25. "WDEN,The watchdog counter for each channel can be started stopped." "0: Watchdog counter stopped. It maintains its value.,1: Watchdog counter started." newline hexmask.long.tbyte 0x4 0.--23. 1. "WD_TO,This indicates the watchdog time out value. The watchdog generates an overrun error in case the watchdog is not refreshed before the watchdog counter reached the WD_TO value." line.long 0x8 "DDTRIG_OFFR_CH3,PSI5-S DDSR trigger offset register channel" hexmask.long.word 0x8 0.--15. 1. "DDTRIG_OFFR,These bits configure the delay between the 'shift trigger' of the various DDSRs across different channels. The value in this register governs the delay after which the specific DDSR is triggered once the Global Shift trigger.." line.long 0xC "DDTRIG_PERR_CH3,PSI5-S DDSR trigger period register channel" hexmask.long.word 0xC 0.--15. 1. "DDTRIG_PERR,These bits configure the 'shift trigger' period for the DDSR of that specific channel. The value in this register governs the period with which the data for the DDSR of that particular channel is shifted out." line.long 0x10 "E2SCR_CH3,PSI5-S ECU to sensor control register" hexmask.long.byte 0x10 26.--30. 1. "CMD,Bits for the ECU-to-sensor 'CMD' format. They refer to the command send to the UART Tx logic when a '1' is shifted from the DDSR register." newline hexmask.long.byte 0x10 20.--24. 1. "ACMD,Bits for the ECU-to-sensor 'ACMD' format. They refer to the command send to the UART Tx logic when a '0' is shifted from the DDSR register." newline bitfld.long 0x10 17. "CH_TRIG,This controls that the DDSR of the specific channel is triggered locally. This bit controls the shifting when PS_E2SCR_CHn[GL_TRIG_SEL] is 0." "0: Stop the DDSR from shifting the commands. The..,1: Start the 'shift trigger' of the DDSR." newline bitfld.long 0x10 16. "GL_TRIG_SEL,This bit controls whether the DDSR shift trigger is a global trigger or a local channel trigger." "0: The DDSR shift trigger is a local channel..,1: The DDSR shift trigger is a global trigger.." newline bitfld.long 0x10 15. "DEFAULT_SYNC,Decides the value to which the DDSR has to default to when PS_E2SSR_CHn[DDSR_RDY] == 1." "0,1" newline bitfld.long 0x10 14. "DDSR_SHIFT_SEL,DDSR Shift Selection" "0: The shift trigger is from internal DDSR counters..,1: The input signal gtm_trig directly acts as the.." newline bitfld.long 0x10 13. "DDSR_CLR,Used for rejecting the contents of the DDSR register." "0,1" newline bitfld.long 0x10 12. "DDSR_CLK_SEL,Selects which clock clocks shift logic of the DDSR for shifting the bits for command transmission." "0: ipg_clk_ps_ddtrig clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x10 11. "CMDTR_SW_CTRL,Once the command is ready for transmission (indicated by the setting PS_E2SSR_CHn[CMDPR_BZY] to 1) this bit decides when the actual transmission has to start:" "0: The actual transmission of command remains..,1: The command transmission starts once the.." newline bitfld.long 0x10 9. "SYNCHRO_OVF_IE,Synchro overflow interrupt enable" "0: No interrupt is generated when..,1: Generate an interrupt when.." newline bitfld.long 0x10 7. "CMDTR_NWRT_IE,Interrupt Enable for DDSR being attempted to be written when it is still not empty that is PS_E2SSR_CHn[DDSR_RDY] == 0 yet an attempt to write to DDSR is made." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 6. "CMDPR_BZY_IE,Interrupt Enable for DDSR getting updated with the internally processed complete command (with CRC stuff bits start bits getting appended)." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 5. "DDSR_RDY_IE,Interrupt Enable for DDSR getting empty and ready for receiving new command." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 0.--2. "CMD_TYPE," "0,1,2,3,4,5,6,7" line.long 0x14 "E2SSR_CH3,PSI5-S ECU to sensor status register" bitfld.long 0x14 9. "SYNCHRO_OVF,This bit gets set whenever due to any reason (like too less DDTRIG period) sync pulse of a channel comes before the previous sync pulse of the same channel has actually shifted its data." "0: No synch pulse overflow has occurred in the..,1: Synch Pulse overflow has occurred for the.." newline bitfld.long 0x14 7. "CMDTR_NWRT,Status of Command written to the DDSR:" "0: Command written to the DDSR has been accepted..,1: Command written to the DDSR is rejected as an.." newline bitfld.long 0x14 6. "CMDPR_BZY,Command Processing Busy Status" "0: DDSR is busy with command processing. For this..,1: DDSR is ready with the processed command.." newline bitfld.long 0x14 5. "DDSR_RDY,Status for DDSR getting empty and ready for receiving new command." "0: DDSR is not ready and is busy with either the..,1: DDSR is empty and ready for receiving a new.." line.long 0x18 "DDSR_H_CH3,PSI5-S channel1 ECU to sensor downstream data shift register high" hexmask.long.word 0x18 0.--10. 1. "DDSR_H,Upper High bits of the 43 bit complete DDSR register. These bits are updated by the hardware and software cannot write to these bits." line.long 0x1C "DDSR_L_CH3,PSI5-S channel1 ECU to sensor downstream data shift register low" hexmask.long.byte 0x1C 24.--31. 1. "DDSR_L1,8 bits of the DDSR_L that can only be read by the Application. These 8 bits are automatically updated by the hardware. They can be read by the software to check for the processed command after the command is written to the DDSR by the.." newline hexmask.long.tbyte 0x1C 0.--23. 1. "DDSR_L0,Lower 24 bits of the DDSR register that are written by the Application as well as updated by the hardware once the command processing is over." group.long 0x244++0x7 line.long 0x0 "MSGA_CH4,PSI5-S channel message configuration register A" bitfld.long 0x0 31. "L_PC_EN,Selects whether the parity/CRC selection for a PSI5 message is to be controlled globally on a channel basis (through the G_PC bits) or locally on a per frame basis (through the L_PC[frame] bits)." "0: Parity/CRC option controlled globally through..,1: Parity/CRC option controlled locally through the.." newline bitfld.long 0x0 28.--30. "F5_BYTE,Number of bytes in UART packet for message corresponding to frame 5." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "L_PC5,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame5.,1: CRC selected for PSI5 message for frame5." newline bitfld.long 0x0 24.--26. "F4_BYTE,Number of bytes in UART packet for message corresponding to frame 4." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "L_PC4,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame4.,1: CRC selected for PSI5 message for frame4." newline bitfld.long 0x0 20.--22. "F3_BYTE,Number of bytes in UART packet for message corresponding to frame 3." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "L_PC3,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame3.,1: CRC selected for PSI5 message for frame3." newline bitfld.long 0x0 16.--18. "F2_BYTE,Number of bytes in UART packet for message corresponding to frame 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "L_PC2,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame2.,1: CRC selected for PSI5 message for frame2." newline bitfld.long 0x0 12.--14. "F1_BYTE,Number of bytes in UART packet for message corresponding to frame 1." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "L_PC1,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame1.,1: CRC selected for PSI5 message for frame1." newline bitfld.long 0x0 8.--10. "F0_BYTE,Number of bytes in UART packet for message corresponding to frame 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "L_PC0,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame0.,1: CRC selected for PSI5 message for frame0." newline bitfld.long 0x0 6. "MODE,This bit selects the operating modes between sync and async for the channel." "0: Synchronous.,1: Asynchronous." newline bitfld.long 0x0 5. "TIME_STAMP_A_B_SEL,Decides whether timestamp counter A or B value is captured in the local timestamp buffer whenever a 'capture event' occurs." "0: Timestamp counter A.,1: Timestamp counter B." newline bitfld.long 0x0 4. "TMSG_TCMD,Whether the timestamp is recorded when the message is received or when the channel command is moved from the TxFIFO to the UART Tx register (emulates a sync pulse)" "0: Timestamp recorded based on 'emulated' sync pulse.,1: Timestamp recorded based on message header byte.." newline bitfld.long 0x0 3. "TSBUF_CLR,This bit is used to clear the local timestamp buffer for the respective channel.Once cleared the buffer remains clear till the event to capture time stamp is triggered." "?,1: Timestamp buffer is cleared." newline bitfld.long 0x0 2. "TSBUF_EN,This bit controls whether timestamp buffer maintains a value '0' or is refreshed on a timestamp 'capture event'." "0: Timestamp buffer maintains value '0'.,1: Timestamp buffer responds to a 'capture event'.." newline bitfld.long 0x0 1. "G_PC,This bit globally selects the Parity or the CRC option for all the Frames of that particular channel" "0: Parity option selected globally for messages of..,1: CRC option selected globally for messages of all.." newline bitfld.long 0x0 0. "CH_EN,PSI5 Channel Enable. This bit decides if the IP takes the data belonging to the specific channel as 'legal' or 'illegal'." "0: Concerned PSI5 channel is disabled. Any data..,1: PSI5 message extraction for the definition of.." line.long 0x4 "MSGB_CH4,PSI5-S channel message configuration register B" hexmask.long.byte 0x4 25.--29. 1. "F5_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 5." newline hexmask.long.byte 0x4 20.--24. 1. "F4_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 4." newline hexmask.long.byte 0x4 15.--19. 1. "F3_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 3." newline hexmask.long.byte 0x4 10.--14. 1. "F2_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 2." newline hexmask.long.byte 0x4 5.--9. 1. "F1_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 1." newline hexmask.long.byte 0x4 0.--4. 1. "F0_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 0." group.long 0x250++0x1F line.long 0x0 "MBOX_SR_CH4,PSI5-S mailbox status register channel" bitfld.long 0x0 17. "F5_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=5) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 16. "F5_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No overwrite of unread message in MBOX[n] LOC5.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 15. "F5_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No unread message in MBOX[n] LOC5.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 14. "F4_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=4) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 13. "F4_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No overwrite of unread message in MBOX[n] LOC4.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 12. "F4_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No unread message in MBOX[n] LOC4.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 11. "F3_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=3) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 10. "F3_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No overwrite of unread message in MBOX[n] LOC3.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 9. "F3_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No unread message in MBOX[n] LOC3.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 8. "F2_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=2) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 7. "F2_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No overwrite of unread message in MBOX[n] LOC2.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 6. "F2_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No unread message in MBOX[n] LOC2.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 5. "F1_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=1) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 4. "F1_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No overwrite of unread message in MBOX[n] LOC1.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 3. "F1_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No unread message in MBOX[n] LOC1.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 2. "F0_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=0) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 1. "F0_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No overwrite of unread message in MBOX[n] LOC0.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 0. "F0_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No unread message in MBOX[n] LOC0.,1: It indicates that the message that has just been.." line.long 0x4 "WD_CFGR_CH4,PSI5-S channel watchdog configuration register" bitfld.long 0x4 27. "WDRST,Resets watchdog counter for the channel" "0,1" newline bitfld.long 0x4 26. "WDCS,This selects either GTM or the module clock for watchdog counter of the channel. See Figure1629) Clock distribution in PSI5-S." "0: ipg_clk_ps_wd clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x4 25. "WDEN,The watchdog counter for each channel can be started stopped." "0: Watchdog counter stopped. It maintains its value.,1: Watchdog counter started." newline hexmask.long.tbyte 0x4 0.--23. 1. "WD_TO,This indicates the watchdog time out value. The watchdog generates an overrun error in case the watchdog is not refreshed before the watchdog counter reached the WD_TO value." line.long 0x8 "DDTRIG_OFFR_CH4,PSI5-S DDSR trigger offset register channel" hexmask.long.word 0x8 0.--15. 1. "DDTRIG_OFFR,These bits configure the delay between the 'shift trigger' of the various DDSRs across different channels. The value in this register governs the delay after which the specific DDSR is triggered once the Global Shift trigger.." line.long 0xC "DDTRIG_PERR_CH4,PSI5-S DDSR trigger period register channel" hexmask.long.word 0xC 0.--15. 1. "DDTRIG_PERR,These bits configure the 'shift trigger' period for the DDSR of that specific channel. The value in this register governs the period with which the data for the DDSR of that particular channel is shifted out." line.long 0x10 "E2SCR_CH4,PSI5-S ECU to sensor control register" hexmask.long.byte 0x10 26.--30. 1. "CMD,Bits for the ECU-to-sensor 'CMD' format. They refer to the command send to the UART Tx logic when a '1' is shifted from the DDSR register." newline hexmask.long.byte 0x10 20.--24. 1. "ACMD,Bits for the ECU-to-sensor 'ACMD' format. They refer to the command send to the UART Tx logic when a '0' is shifted from the DDSR register." newline bitfld.long 0x10 17. "CH_TRIG,This controls that the DDSR of the specific channel is triggered locally. This bit controls the shifting when PS_E2SCR_CHn[GL_TRIG_SEL] is 0." "0: Stop the DDSR from shifting the commands. The..,1: Start the 'shift trigger' of the DDSR." newline bitfld.long 0x10 16. "GL_TRIG_SEL,This bit controls whether the DDSR shift trigger is a global trigger or a local channel trigger." "0: The DDSR shift trigger is a local channel..,1: The DDSR shift trigger is a global trigger.." newline bitfld.long 0x10 15. "DEFAULT_SYNC,Decides the value to which the DDSR has to default to when PS_E2SSR_CHn[DDSR_RDY] == 1." "0,1" newline bitfld.long 0x10 14. "DDSR_SHIFT_SEL,DDSR Shift Selection" "0: The shift trigger is from internal DDSR counters..,1: The input signal gtm_trig directly acts as the.." newline bitfld.long 0x10 13. "DDSR_CLR,Used for rejecting the contents of the DDSR register." "0,1" newline bitfld.long 0x10 12. "DDSR_CLK_SEL,Selects which clock clocks shift logic of the DDSR for shifting the bits for command transmission." "0: ipg_clk_ps_ddtrig clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x10 11. "CMDTR_SW_CTRL,Once the command is ready for transmission (indicated by the setting PS_E2SSR_CHn[CMDPR_BZY] to 1) this bit decides when the actual transmission has to start:" "0: The actual transmission of command remains..,1: The command transmission starts once the.." newline bitfld.long 0x10 9. "SYNCHRO_OVF_IE,Synchro overflow interrupt enable" "0: No interrupt is generated when..,1: Generate an interrupt when.." newline bitfld.long 0x10 7. "CMDTR_NWRT_IE,Interrupt Enable for DDSR being attempted to be written when it is still not empty that is PS_E2SSR_CHn[DDSR_RDY] == 0 yet an attempt to write to DDSR is made." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 6. "CMDPR_BZY_IE,Interrupt Enable for DDSR getting updated with the internally processed complete command (with CRC stuff bits start bits getting appended)." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 5. "DDSR_RDY_IE,Interrupt Enable for DDSR getting empty and ready for receiving new command." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 0.--2. "CMD_TYPE," "0,1,2,3,4,5,6,7" line.long 0x14 "E2SSR_CH4,PSI5-S ECU to sensor status register" bitfld.long 0x14 9. "SYNCHRO_OVF,This bit gets set whenever due to any reason (like too less DDTRIG period) sync pulse of a channel comes before the previous sync pulse of the same channel has actually shifted its data." "0: No synch pulse overflow has occurred in the..,1: Synch Pulse overflow has occurred for the.." newline bitfld.long 0x14 7. "CMDTR_NWRT,Status of Command written to the DDSR:" "0: Command written to the DDSR has been accepted..,1: Command written to the DDSR is rejected as an.." newline bitfld.long 0x14 6. "CMDPR_BZY,Command Processing Busy Status" "0: DDSR is busy with command processing. For this..,1: DDSR is ready with the processed command.." newline bitfld.long 0x14 5. "DDSR_RDY,Status for DDSR getting empty and ready for receiving new command." "0: DDSR is not ready and is busy with either the..,1: DDSR is empty and ready for receiving a new.." line.long 0x18 "DDSR_H_CH4,PSI5-S channel1 ECU to sensor downstream data shift register high" hexmask.long.word 0x18 0.--10. 1. "DDSR_H,Upper High bits of the 43 bit complete DDSR register. These bits are updated by the hardware and software cannot write to these bits." line.long 0x1C "DDSR_L_CH4,PSI5-S channel1 ECU to sensor downstream data shift register low" hexmask.long.byte 0x1C 24.--31. 1. "DDSR_L1,8 bits of the DDSR_L that can only be read by the Application. These 8 bits are automatically updated by the hardware. They can be read by the software to check for the processed command after the command is written to the DDSR by the.." newline hexmask.long.tbyte 0x1C 0.--23. 1. "DDSR_L0,Lower 24 bits of the DDSR register that are written by the Application as well as updated by the hardware once the command processing is over." group.long 0x280++0x7 line.long 0x0 "MSGA_CH5,PSI5-S channel message configuration register A" bitfld.long 0x0 31. "L_PC_EN,Selects whether the parity/CRC selection for a PSI5 message is to be controlled globally on a channel basis (through the G_PC bits) or locally on a per frame basis (through the L_PC[frame] bits)." "0: Parity/CRC option controlled globally through..,1: Parity/CRC option controlled locally through the.." newline bitfld.long 0x0 28.--30. "F5_BYTE,Number of bytes in UART packet for message corresponding to frame 5." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "L_PC5,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame5.,1: CRC selected for PSI5 message for frame5." newline bitfld.long 0x0 24.--26. "F4_BYTE,Number of bytes in UART packet for message corresponding to frame 4." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "L_PC4,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame4.,1: CRC selected for PSI5 message for frame4." newline bitfld.long 0x0 20.--22. "F3_BYTE,Number of bytes in UART packet for message corresponding to frame 3." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "L_PC3,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame3.,1: CRC selected for PSI5 message for frame3." newline bitfld.long 0x0 16.--18. "F2_BYTE,Number of bytes in UART packet for message corresponding to frame 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "L_PC2,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame2.,1: CRC selected for PSI5 message for frame2." newline bitfld.long 0x0 12.--14. "F1_BYTE,Number of bytes in UART packet for message corresponding to frame 1." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "L_PC1,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame1.,1: CRC selected for PSI5 message for frame1." newline bitfld.long 0x0 8.--10. "F0_BYTE,Number of bytes in UART packet for message corresponding to frame 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "L_PC0,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame0.,1: CRC selected for PSI5 message for frame0." newline bitfld.long 0x0 6. "MODE,This bit selects the operating modes between sync and async for the channel." "0: Synchronous.,1: Asynchronous." newline bitfld.long 0x0 5. "TIME_STAMP_A_B_SEL,Decides whether timestamp counter A or B value is captured in the local timestamp buffer whenever a 'capture event' occurs." "0: Timestamp counter A.,1: Timestamp counter B." newline bitfld.long 0x0 4. "TMSG_TCMD,Whether the timestamp is recorded when the message is received or when the channel command is moved from the TxFIFO to the UART Tx register (emulates a sync pulse)" "0: Timestamp recorded based on 'emulated' sync pulse.,1: Timestamp recorded based on message header byte.." newline bitfld.long 0x0 3. "TSBUF_CLR,This bit is used to clear the local timestamp buffer for the respective channel.Once cleared the buffer remains clear till the event to capture time stamp is triggered." "?,1: Timestamp buffer is cleared." newline bitfld.long 0x0 2. "TSBUF_EN,This bit controls whether timestamp buffer maintains a value '0' or is refreshed on a timestamp 'capture event'." "0: Timestamp buffer maintains value '0'.,1: Timestamp buffer responds to a 'capture event'.." newline bitfld.long 0x0 1. "G_PC,This bit globally selects the Parity or the CRC option for all the Frames of that particular channel" "0: Parity option selected globally for messages of..,1: CRC option selected globally for messages of all.." newline bitfld.long 0x0 0. "CH_EN,PSI5 Channel Enable. This bit decides if the IP takes the data belonging to the specific channel as 'legal' or 'illegal'." "0: Concerned PSI5 channel is disabled. Any data..,1: PSI5 message extraction for the definition of.." line.long 0x4 "MSGB_CH5,PSI5-S channel message configuration register B" hexmask.long.byte 0x4 25.--29. 1. "F5_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 5." newline hexmask.long.byte 0x4 20.--24. 1. "F4_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 4." newline hexmask.long.byte 0x4 15.--19. 1. "F3_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 3." newline hexmask.long.byte 0x4 10.--14. 1. "F2_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 2." newline hexmask.long.byte 0x4 5.--9. 1. "F1_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 1." newline hexmask.long.byte 0x4 0.--4. 1. "F0_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 0." group.long 0x28C++0x1F line.long 0x0 "MBOX_SR_CH5,PSI5-S mailbox status register channel" bitfld.long 0x0 17. "F5_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=5) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 16. "F5_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No overwrite of unread message in MBOX[n] LOC5.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 15. "F5_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No unread message in MBOX[n] LOC5.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 14. "F4_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=4) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 13. "F4_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No overwrite of unread message in MBOX[n] LOC4.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 12. "F4_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No unread message in MBOX[n] LOC4.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 11. "F3_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=3) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 10. "F3_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No overwrite of unread message in MBOX[n] LOC3.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 9. "F3_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No unread message in MBOX[n] LOC3.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 8. "F2_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=2) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 7. "F2_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No overwrite of unread message in MBOX[n] LOC2.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 6. "F2_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No unread message in MBOX[n] LOC2.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 5. "F1_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=1) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 4. "F1_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No overwrite of unread message in MBOX[n] LOC1.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 3. "F1_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No unread message in MBOX[n] LOC1.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 2. "F0_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=0) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 1. "F0_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No overwrite of unread message in MBOX[n] LOC0.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 0. "F0_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No unread message in MBOX[n] LOC0.,1: It indicates that the message that has just been.." line.long 0x4 "WD_CFGR_CH5,PSI5-S channel watchdog configuration register" bitfld.long 0x4 27. "WDRST,Resets watchdog counter for the channel" "0,1" newline bitfld.long 0x4 26. "WDCS,This selects either GTM or the module clock for watchdog counter of the channel. See Figure1629) Clock distribution in PSI5-S." "0: ipg_clk_ps_wd clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x4 25. "WDEN,The watchdog counter for each channel can be started stopped." "0: Watchdog counter stopped. It maintains its value.,1: Watchdog counter started." newline hexmask.long.tbyte 0x4 0.--23. 1. "WD_TO,This indicates the watchdog time out value. The watchdog generates an overrun error in case the watchdog is not refreshed before the watchdog counter reached the WD_TO value." line.long 0x8 "DDTRIG_OFFR_CH5,PSI5-S DDSR trigger offset register channel" hexmask.long.word 0x8 0.--15. 1. "DDTRIG_OFFR,These bits configure the delay between the 'shift trigger' of the various DDSRs across different channels. The value in this register governs the delay after which the specific DDSR is triggered once the Global Shift trigger.." line.long 0xC "DDTRIG_PERR_CH5,PSI5-S DDSR trigger period register channel" hexmask.long.word 0xC 0.--15. 1. "DDTRIG_PERR,These bits configure the 'shift trigger' period for the DDSR of that specific channel. The value in this register governs the period with which the data for the DDSR of that particular channel is shifted out." line.long 0x10 "E2SCR_CH5,PSI5-S ECU to sensor control register" hexmask.long.byte 0x10 26.--30. 1. "CMD,Bits for the ECU-to-sensor 'CMD' format. They refer to the command send to the UART Tx logic when a '1' is shifted from the DDSR register." newline hexmask.long.byte 0x10 20.--24. 1. "ACMD,Bits for the ECU-to-sensor 'ACMD' format. They refer to the command send to the UART Tx logic when a '0' is shifted from the DDSR register." newline bitfld.long 0x10 17. "CH_TRIG,This controls that the DDSR of the specific channel is triggered locally. This bit controls the shifting when PS_E2SCR_CHn[GL_TRIG_SEL] is 0." "0: Stop the DDSR from shifting the commands. The..,1: Start the 'shift trigger' of the DDSR." newline bitfld.long 0x10 16. "GL_TRIG_SEL,This bit controls whether the DDSR shift trigger is a global trigger or a local channel trigger." "0: The DDSR shift trigger is a local channel..,1: The DDSR shift trigger is a global trigger.." newline bitfld.long 0x10 15. "DEFAULT_SYNC,Decides the value to which the DDSR has to default to when PS_E2SSR_CHn[DDSR_RDY] == 1." "0,1" newline bitfld.long 0x10 14. "DDSR_SHIFT_SEL,DDSR Shift Selection" "0: The shift trigger is from internal DDSR counters..,1: The input signal gtm_trig directly acts as the.." newline bitfld.long 0x10 13. "DDSR_CLR,Used for rejecting the contents of the DDSR register." "0,1" newline bitfld.long 0x10 12. "DDSR_CLK_SEL,Selects which clock clocks shift logic of the DDSR for shifting the bits for command transmission." "0: ipg_clk_ps_ddtrig clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x10 11. "CMDTR_SW_CTRL,Once the command is ready for transmission (indicated by the setting PS_E2SSR_CHn[CMDPR_BZY] to 1) this bit decides when the actual transmission has to start:" "0: The actual transmission of command remains..,1: The command transmission starts once the.." newline bitfld.long 0x10 9. "SYNCHRO_OVF_IE,Synchro overflow interrupt enable" "0: No interrupt is generated when..,1: Generate an interrupt when.." newline bitfld.long 0x10 7. "CMDTR_NWRT_IE,Interrupt Enable for DDSR being attempted to be written when it is still not empty that is PS_E2SSR_CHn[DDSR_RDY] == 0 yet an attempt to write to DDSR is made." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 6. "CMDPR_BZY_IE,Interrupt Enable for DDSR getting updated with the internally processed complete command (with CRC stuff bits start bits getting appended)." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 5. "DDSR_RDY_IE,Interrupt Enable for DDSR getting empty and ready for receiving new command." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 0.--2. "CMD_TYPE," "0,1,2,3,4,5,6,7" line.long 0x14 "E2SSR_CH5,PSI5-S ECU to sensor status register" bitfld.long 0x14 9. "SYNCHRO_OVF,This bit gets set whenever due to any reason (like too less DDTRIG period) sync pulse of a channel comes before the previous sync pulse of the same channel has actually shifted its data." "0: No synch pulse overflow has occurred in the..,1: Synch Pulse overflow has occurred for the.." newline bitfld.long 0x14 7. "CMDTR_NWRT,Status of Command written to the DDSR:" "0: Command written to the DDSR has been accepted..,1: Command written to the DDSR is rejected as an.." newline bitfld.long 0x14 6. "CMDPR_BZY,Command Processing Busy Status" "0: DDSR is busy with command processing. For this..,1: DDSR is ready with the processed command.." newline bitfld.long 0x14 5. "DDSR_RDY,Status for DDSR getting empty and ready for receiving new command." "0: DDSR is not ready and is busy with either the..,1: DDSR is empty and ready for receiving a new.." line.long 0x18 "DDSR_H_CH5,PSI5-S channel1 ECU to sensor downstream data shift register high" hexmask.long.word 0x18 0.--10. 1. "DDSR_H,Upper High bits of the 43 bit complete DDSR register. These bits are updated by the hardware and software cannot write to these bits." line.long 0x1C "DDSR_L_CH5,PSI5-S channel1 ECU to sensor downstream data shift register low" hexmask.long.byte 0x1C 24.--31. 1. "DDSR_L1,8 bits of the DDSR_L that can only be read by the Application. These 8 bits are automatically updated by the hardware. They can be read by the software to check for the processed command after the command is written to the DDSR by the.." newline hexmask.long.tbyte 0x1C 0.--23. 1. "DDSR_L0,Lower 24 bits of the DDSR register that are written by the Application as well as updated by the hardware once the command processing is over." group.long 0x2BC++0x7 line.long 0x0 "MSGA_CH6,PSI5-S channel message configuration register A" bitfld.long 0x0 31. "L_PC_EN,Selects whether the parity/CRC selection for a PSI5 message is to be controlled globally on a channel basis (through the G_PC bits) or locally on a per frame basis (through the L_PC[frame] bits)." "0: Parity/CRC option controlled globally through..,1: Parity/CRC option controlled locally through the.." newline bitfld.long 0x0 28.--30. "F5_BYTE,Number of bytes in UART packet for message corresponding to frame 5." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "L_PC5,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame5.,1: CRC selected for PSI5 message for frame5." newline bitfld.long 0x0 24.--26. "F4_BYTE,Number of bytes in UART packet for message corresponding to frame 4." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "L_PC4,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame4.,1: CRC selected for PSI5 message for frame4." newline bitfld.long 0x0 20.--22. "F3_BYTE,Number of bytes in UART packet for message corresponding to frame 3." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "L_PC3,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame3.,1: CRC selected for PSI5 message for frame3." newline bitfld.long 0x0 16.--18. "F2_BYTE,Number of bytes in UART packet for message corresponding to frame 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "L_PC2,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame2.,1: CRC selected for PSI5 message for frame2." newline bitfld.long 0x0 12.--14. "F1_BYTE,Number of bytes in UART packet for message corresponding to frame 1." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "L_PC1,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame1.,1: CRC selected for PSI5 message for frame1." newline bitfld.long 0x0 8.--10. "F0_BYTE,Number of bytes in UART packet for message corresponding to frame 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "L_PC0,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame0.,1: CRC selected for PSI5 message for frame0." newline bitfld.long 0x0 6. "MODE,This bit selects the operating modes between sync and async for the channel." "0: Synchronous.,1: Asynchronous." newline bitfld.long 0x0 5. "TIME_STAMP_A_B_SEL,Decides whether timestamp counter A or B value is captured in the local timestamp buffer whenever a 'capture event' occurs." "0: Timestamp counter A.,1: Timestamp counter B." newline bitfld.long 0x0 4. "TMSG_TCMD,Whether the timestamp is recorded when the message is received or when the channel command is moved from the TxFIFO to the UART Tx register (emulates a sync pulse)" "0: Timestamp recorded based on 'emulated' sync pulse.,1: Timestamp recorded based on message header byte.." newline bitfld.long 0x0 3. "TSBUF_CLR,This bit is used to clear the local timestamp buffer for the respective channel.Once cleared the buffer remains clear till the event to capture time stamp is triggered." "?,1: Timestamp buffer is cleared." newline bitfld.long 0x0 2. "TSBUF_EN,This bit controls whether timestamp buffer maintains a value '0' or is refreshed on a timestamp 'capture event'." "0: Timestamp buffer maintains value '0'.,1: Timestamp buffer responds to a 'capture event'.." newline bitfld.long 0x0 1. "G_PC,This bit globally selects the Parity or the CRC option for all the Frames of that particular channel" "0: Parity option selected globally for messages of..,1: CRC option selected globally for messages of all.." newline bitfld.long 0x0 0. "CH_EN,PSI5 Channel Enable. This bit decides if the IP takes the data belonging to the specific channel as 'legal' or 'illegal'." "0: Concerned PSI5 channel is disabled. Any data..,1: PSI5 message extraction for the definition of.." line.long 0x4 "MSGB_CH6,PSI5-S channel message configuration register B" hexmask.long.byte 0x4 25.--29. 1. "F5_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 5." newline hexmask.long.byte 0x4 20.--24. 1. "F4_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 4." newline hexmask.long.byte 0x4 15.--19. 1. "F3_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 3." newline hexmask.long.byte 0x4 10.--14. 1. "F2_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 2." newline hexmask.long.byte 0x4 5.--9. 1. "F1_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 1." newline hexmask.long.byte 0x4 0.--4. 1. "F0_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 0." group.long 0x2C8++0x1F line.long 0x0 "MBOX_SR_CH6,PSI5-S mailbox status register channel" bitfld.long 0x0 17. "F5_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=5) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 16. "F5_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No overwrite of unread message in MBOX[n] LOC5.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 15. "F5_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No unread message in MBOX[n] LOC5.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 14. "F4_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=4) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 13. "F4_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No overwrite of unread message in MBOX[n] LOC4.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 12. "F4_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No unread message in MBOX[n] LOC4.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 11. "F3_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=3) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 10. "F3_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No overwrite of unread message in MBOX[n] LOC3.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 9. "F3_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No unread message in MBOX[n] LOC3.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 8. "F2_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=2) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 7. "F2_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No overwrite of unread message in MBOX[n] LOC2.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 6. "F2_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No unread message in MBOX[n] LOC2.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 5. "F1_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=1) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 4. "F1_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No overwrite of unread message in MBOX[n] LOC1.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 3. "F1_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No unread message in MBOX[n] LOC1.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 2. "F0_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=0) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 1. "F0_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No overwrite of unread message in MBOX[n] LOC0.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 0. "F0_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No unread message in MBOX[n] LOC0.,1: It indicates that the message that has just been.." line.long 0x4 "WD_CFGR_CH6,PSI5-S channel watchdog configuration register" bitfld.long 0x4 27. "WDRST,Resets watchdog counter for the channel" "0,1" newline bitfld.long 0x4 26. "WDCS,This selects either GTM or the module clock for watchdog counter of the channel. See Figure1629) Clock distribution in PSI5-S." "0: ipg_clk_ps_wd clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x4 25. "WDEN,The watchdog counter for each channel can be started stopped." "0: Watchdog counter stopped. It maintains its value.,1: Watchdog counter started." newline hexmask.long.tbyte 0x4 0.--23. 1. "WD_TO,This indicates the watchdog time out value. The watchdog generates an overrun error in case the watchdog is not refreshed before the watchdog counter reached the WD_TO value." line.long 0x8 "DDTRIG_OFFR_CH6,PSI5-S DDSR trigger offset register channel" hexmask.long.word 0x8 0.--15. 1. "DDTRIG_OFFR,These bits configure the delay between the 'shift trigger' of the various DDSRs across different channels. The value in this register governs the delay after which the specific DDSR is triggered once the Global Shift trigger.." line.long 0xC "DDTRIG_PERR_CH6,PSI5-S DDSR trigger period register channel" hexmask.long.word 0xC 0.--15. 1. "DDTRIG_PERR,These bits configure the 'shift trigger' period for the DDSR of that specific channel. The value in this register governs the period with which the data for the DDSR of that particular channel is shifted out." line.long 0x10 "E2SCR_CH6,PSI5-S ECU to sensor control register" hexmask.long.byte 0x10 26.--30. 1. "CMD,Bits for the ECU-to-sensor 'CMD' format. They refer to the command send to the UART Tx logic when a '1' is shifted from the DDSR register." newline hexmask.long.byte 0x10 20.--24. 1. "ACMD,Bits for the ECU-to-sensor 'ACMD' format. They refer to the command send to the UART Tx logic when a '0' is shifted from the DDSR register." newline bitfld.long 0x10 17. "CH_TRIG,This controls that the DDSR of the specific channel is triggered locally. This bit controls the shifting when PS_E2SCR_CHn[GL_TRIG_SEL] is 0." "0: Stop the DDSR from shifting the commands. The..,1: Start the 'shift trigger' of the DDSR." newline bitfld.long 0x10 16. "GL_TRIG_SEL,This bit controls whether the DDSR shift trigger is a global trigger or a local channel trigger." "0: The DDSR shift trigger is a local channel..,1: The DDSR shift trigger is a global trigger.." newline bitfld.long 0x10 15. "DEFAULT_SYNC,Decides the value to which the DDSR has to default to when PS_E2SSR_CHn[DDSR_RDY] == 1." "0,1" newline bitfld.long 0x10 14. "DDSR_SHIFT_SEL,DDSR Shift Selection" "0: The shift trigger is from internal DDSR counters..,1: The input signal gtm_trig directly acts as the.." newline bitfld.long 0x10 13. "DDSR_CLR,Used for rejecting the contents of the DDSR register." "0,1" newline bitfld.long 0x10 12. "DDSR_CLK_SEL,Selects which clock clocks shift logic of the DDSR for shifting the bits for command transmission." "0: ipg_clk_ps_ddtrig clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x10 11. "CMDTR_SW_CTRL,Once the command is ready for transmission (indicated by the setting PS_E2SSR_CHn[CMDPR_BZY] to 1) this bit decides when the actual transmission has to start:" "0: The actual transmission of command remains..,1: The command transmission starts once the.." newline bitfld.long 0x10 9. "SYNCHRO_OVF_IE,Synchro overflow interrupt enable" "0: No interrupt is generated when..,1: Generate an interrupt when.." newline bitfld.long 0x10 7. "CMDTR_NWRT_IE,Interrupt Enable for DDSR being attempted to be written when it is still not empty that is PS_E2SSR_CHn[DDSR_RDY] == 0 yet an attempt to write to DDSR is made." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 6. "CMDPR_BZY_IE,Interrupt Enable for DDSR getting updated with the internally processed complete command (with CRC stuff bits start bits getting appended)." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 5. "DDSR_RDY_IE,Interrupt Enable for DDSR getting empty and ready for receiving new command." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 0.--2. "CMD_TYPE," "0,1,2,3,4,5,6,7" line.long 0x14 "E2SSR_CH6,PSI5-S ECU to sensor status register" bitfld.long 0x14 9. "SYNCHRO_OVF,This bit gets set whenever due to any reason (like too less DDTRIG period) sync pulse of a channel comes before the previous sync pulse of the same channel has actually shifted its data." "0: No synch pulse overflow has occurred in the..,1: Synch Pulse overflow has occurred for the.." newline bitfld.long 0x14 7. "CMDTR_NWRT,Status of Command written to the DDSR:" "0: Command written to the DDSR has been accepted..,1: Command written to the DDSR is rejected as an.." newline bitfld.long 0x14 6. "CMDPR_BZY,Command Processing Busy Status" "0: DDSR is busy with command processing. For this..,1: DDSR is ready with the processed command.." newline bitfld.long 0x14 5. "DDSR_RDY,Status for DDSR getting empty and ready for receiving new command." "0: DDSR is not ready and is busy with either the..,1: DDSR is empty and ready for receiving a new.." line.long 0x18 "DDSR_H_CH6,PSI5-S channel1 ECU to sensor downstream data shift register high" hexmask.long.word 0x18 0.--10. 1. "DDSR_H,Upper High bits of the 43 bit complete DDSR register. These bits are updated by the hardware and software cannot write to these bits." line.long 0x1C "DDSR_L_CH6,PSI5-S channel1 ECU to sensor downstream data shift register low" hexmask.long.byte 0x1C 24.--31. 1. "DDSR_L1,8 bits of the DDSR_L that can only be read by the Application. These 8 bits are automatically updated by the hardware. They can be read by the software to check for the processed command after the command is written to the DDSR by the.." newline hexmask.long.tbyte 0x1C 0.--23. 1. "DDSR_L0,Lower 24 bits of the DDSR register that are written by the Application as well as updated by the hardware once the command processing is over." group.long 0x2F8++0x7 line.long 0x0 "MSGA_CH7,PSI5-S channel message configuration register A" bitfld.long 0x0 31. "L_PC_EN,Selects whether the parity/CRC selection for a PSI5 message is to be controlled globally on a channel basis (through the G_PC bits) or locally on a per frame basis (through the L_PC[frame] bits)." "0: Parity/CRC option controlled globally through..,1: Parity/CRC option controlled locally through the.." newline bitfld.long 0x0 28.--30. "F5_BYTE,Number of bytes in UART packet for message corresponding to frame 5." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "L_PC5,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame5.,1: CRC selected for PSI5 message for frame5." newline bitfld.long 0x0 24.--26. "F4_BYTE,Number of bytes in UART packet for message corresponding to frame 4." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "L_PC4,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame4.,1: CRC selected for PSI5 message for frame4." newline bitfld.long 0x0 20.--22. "F3_BYTE,Number of bytes in UART packet for message corresponding to frame 3." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "L_PC3,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame3.,1: CRC selected for PSI5 message for frame3." newline bitfld.long 0x0 16.--18. "F2_BYTE,Number of bytes in UART packet for message corresponding to frame 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "L_PC2,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame2.,1: CRC selected for PSI5 message for frame2." newline bitfld.long 0x0 12.--14. "F1_BYTE,Number of bytes in UART packet for message corresponding to frame 1." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "L_PC1,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame1.,1: CRC selected for PSI5 message for frame1." newline bitfld.long 0x0 8.--10. "F0_BYTE,Number of bytes in UART packet for message corresponding to frame 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "L_PC0,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame0.,1: CRC selected for PSI5 message for frame0." newline bitfld.long 0x0 6. "MODE,This bit selects the operating modes between sync and async for the channel." "0: Synchronous.,1: Asynchronous." newline bitfld.long 0x0 5. "TIME_STAMP_A_B_SEL,Decides whether timestamp counter A or B value is captured in the local timestamp buffer whenever a 'capture event' occurs." "0: Timestamp counter A.,1: Timestamp counter B." newline bitfld.long 0x0 4. "TMSG_TCMD,Whether the timestamp is recorded when the message is received or when the channel command is moved from the TxFIFO to the UART Tx register (emulates a sync pulse)" "0: Timestamp recorded based on 'emulated' sync pulse.,1: Timestamp recorded based on message header byte.." newline bitfld.long 0x0 3. "TSBUF_CLR,This bit is used to clear the local timestamp buffer for the respective channel.Once cleared the buffer remains clear till the event to capture time stamp is triggered." "?,1: Timestamp buffer is cleared." newline bitfld.long 0x0 2. "TSBUF_EN,This bit controls whether timestamp buffer maintains a value '0' or is refreshed on a timestamp 'capture event'." "0: Timestamp buffer maintains value '0'.,1: Timestamp buffer responds to a 'capture event'.." newline bitfld.long 0x0 1. "G_PC,This bit globally selects the Parity or the CRC option for all the Frames of that particular channel" "0: Parity option selected globally for messages of..,1: CRC option selected globally for messages of all.." newline bitfld.long 0x0 0. "CH_EN,PSI5 Channel Enable. This bit decides if the IP takes the data belonging to the specific channel as 'legal' or 'illegal'." "0: Concerned PSI5 channel is disabled. Any data..,1: PSI5 message extraction for the definition of.." line.long 0x4 "MSGB_CH7,PSI5-S channel message configuration register B" hexmask.long.byte 0x4 25.--29. 1. "F5_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 5." newline hexmask.long.byte 0x4 20.--24. 1. "F4_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 4." newline hexmask.long.byte 0x4 15.--19. 1. "F3_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 3." newline hexmask.long.byte 0x4 10.--14. 1. "F2_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 2." newline hexmask.long.byte 0x4 5.--9. 1. "F1_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 1." newline hexmask.long.byte 0x4 0.--4. 1. "F0_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 0." group.long 0x304++0x1F line.long 0x0 "MBOX_SR_CH7,PSI5-S mailbox status register channel" bitfld.long 0x0 17. "F5_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=5) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 16. "F5_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No overwrite of unread message in MBOX[n] LOC5.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 15. "F5_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No unread message in MBOX[n] LOC5.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 14. "F4_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=4) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 13. "F4_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No overwrite of unread message in MBOX[n] LOC4.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 12. "F4_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No unread message in MBOX[n] LOC4.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 11. "F3_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=3) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 10. "F3_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No overwrite of unread message in MBOX[n] LOC3.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 9. "F3_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No unread message in MBOX[n] LOC3.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 8. "F2_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=2) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 7. "F2_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No overwrite of unread message in MBOX[n] LOC2.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 6. "F2_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No unread message in MBOX[n] LOC2.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 5. "F1_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=1) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 4. "F1_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No overwrite of unread message in MBOX[n] LOC1.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 3. "F1_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No unread message in MBOX[n] LOC1.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 2. "F0_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=0) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 1. "F0_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No overwrite of unread message in MBOX[n] LOC0.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 0. "F0_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No unread message in MBOX[n] LOC0.,1: It indicates that the message that has just been.." line.long 0x4 "WD_CFGR_CH7,PSI5-S channel watchdog configuration register" bitfld.long 0x4 27. "WDRST,Resets watchdog counter for the channel" "0,1" newline bitfld.long 0x4 26. "WDCS,This selects either GTM or the module clock for watchdog counter of the channel. See Figure1629) Clock distribution in PSI5-S." "0: ipg_clk_ps_wd clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x4 25. "WDEN,The watchdog counter for each channel can be started stopped." "0: Watchdog counter stopped. It maintains its value.,1: Watchdog counter started." newline hexmask.long.tbyte 0x4 0.--23. 1. "WD_TO,This indicates the watchdog time out value. The watchdog generates an overrun error in case the watchdog is not refreshed before the watchdog counter reached the WD_TO value." line.long 0x8 "DDTRIG_OFFR_CH7,PSI5-S DDSR trigger offset register channel" hexmask.long.word 0x8 0.--15. 1. "DDTRIG_OFFR,These bits configure the delay between the 'shift trigger' of the various DDSRs across different channels. The value in this register governs the delay after which the specific DDSR is triggered once the Global Shift trigger.." line.long 0xC "DDTRIG_PERR_CH7,PSI5-S DDSR trigger period register channel" hexmask.long.word 0xC 0.--15. 1. "DDTRIG_PERR,These bits configure the 'shift trigger' period for the DDSR of that specific channel. The value in this register governs the period with which the data for the DDSR of that particular channel is shifted out." line.long 0x10 "E2SCR_CH7,PSI5-S ECU to sensor control register" hexmask.long.byte 0x10 26.--30. 1. "CMD,Bits for the ECU-to-sensor 'CMD' format. They refer to the command send to the UART Tx logic when a '1' is shifted from the DDSR register." newline hexmask.long.byte 0x10 20.--24. 1. "ACMD,Bits for the ECU-to-sensor 'ACMD' format. They refer to the command send to the UART Tx logic when a '0' is shifted from the DDSR register." newline bitfld.long 0x10 17. "CH_TRIG,This controls that the DDSR of the specific channel is triggered locally. This bit controls the shifting when PS_E2SCR_CHn[GL_TRIG_SEL] is 0." "0: Stop the DDSR from shifting the commands. The..,1: Start the 'shift trigger' of the DDSR." newline bitfld.long 0x10 16. "GL_TRIG_SEL,This bit controls whether the DDSR shift trigger is a global trigger or a local channel trigger." "0: The DDSR shift trigger is a local channel..,1: The DDSR shift trigger is a global trigger.." newline bitfld.long 0x10 15. "DEFAULT_SYNC,Decides the value to which the DDSR has to default to when PS_E2SSR_CHn[DDSR_RDY] == 1." "0,1" newline bitfld.long 0x10 14. "DDSR_SHIFT_SEL,DDSR Shift Selection" "0: The shift trigger is from internal DDSR counters..,1: The input signal gtm_trig directly acts as the.." newline bitfld.long 0x10 13. "DDSR_CLR,Used for rejecting the contents of the DDSR register." "0,1" newline bitfld.long 0x10 12. "DDSR_CLK_SEL,Selects which clock clocks shift logic of the DDSR for shifting the bits for command transmission." "0: ipg_clk_ps_ddtrig clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x10 11. "CMDTR_SW_CTRL,Once the command is ready for transmission (indicated by the setting PS_E2SSR_CHn[CMDPR_BZY] to 1) this bit decides when the actual transmission has to start:" "0: The actual transmission of command remains..,1: The command transmission starts once the.." newline bitfld.long 0x10 9. "SYNCHRO_OVF_IE,Synchro overflow interrupt enable" "0: No interrupt is generated when..,1: Generate an interrupt when.." newline bitfld.long 0x10 7. "CMDTR_NWRT_IE,Interrupt Enable for DDSR being attempted to be written when it is still not empty that is PS_E2SSR_CHn[DDSR_RDY] == 0 yet an attempt to write to DDSR is made." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 6. "CMDPR_BZY_IE,Interrupt Enable for DDSR getting updated with the internally processed complete command (with CRC stuff bits start bits getting appended)." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 5. "DDSR_RDY_IE,Interrupt Enable for DDSR getting empty and ready for receiving new command." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 0.--2. "CMD_TYPE," "0,1,2,3,4,5,6,7" line.long 0x14 "E2SSR_CH7,PSI5-S ECU to sensor status register" bitfld.long 0x14 9. "SYNCHRO_OVF,This bit gets set whenever due to any reason (like too less DDTRIG period) sync pulse of a channel comes before the previous sync pulse of the same channel has actually shifted its data." "0: No synch pulse overflow has occurred in the..,1: Synch Pulse overflow has occurred for the.." newline bitfld.long 0x14 7. "CMDTR_NWRT,Status of Command written to the DDSR:" "0: Command written to the DDSR has been accepted..,1: Command written to the DDSR is rejected as an.." newline bitfld.long 0x14 6. "CMDPR_BZY,Command Processing Busy Status" "0: DDSR is busy with command processing. For this..,1: DDSR is ready with the processed command.." newline bitfld.long 0x14 5. "DDSR_RDY,Status for DDSR getting empty and ready for receiving new command." "0: DDSR is not ready and is busy with either the..,1: DDSR is empty and ready for receiving a new.." line.long 0x18 "DDSR_H_CH7,PSI5-S channel1 ECU to sensor downstream data shift register high" hexmask.long.word 0x18 0.--10. 1. "DDSR_H,Upper High bits of the 43 bit complete DDSR register. These bits are updated by the hardware and software cannot write to these bits." line.long 0x1C "DDSR_L_CH7,PSI5-S channel1 ECU to sensor downstream data shift register low" hexmask.long.byte 0x1C 24.--31. 1. "DDSR_L1,8 bits of the DDSR_L that can only be read by the Application. These 8 bits are automatically updated by the hardware. They can be read by the software to check for the processed command after the command is written to the DDSR by the.." newline hexmask.long.tbyte 0x1C 0.--23. 1. "DDSR_L0,Lower 24 bits of the DDSR register that are written by the Application as well as updated by the hardware once the command processing is over." tree.end tree "PSI5S_1" base ad:0x71508000 group.long 0x0++0xB line.long 0x0 "LINCR1,PSI5-S LIN control register 1" bitfld.long 0x0 12. "AUTOWU,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x0 6. "SLFM,Self test mode" "0: Self test mode disabled,1: Self test mode enabled" newline bitfld.long 0x0 5. "LBKM,Loop Back mode" "0: Loop Back Mode disabled,1: Loop Back mode enabled" newline bitfld.long 0x0 2. "RBLM,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x0 1. "SLEEP,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x0 0. "INIT,PS_NOUSE_BIT" "0,1" line.long 0x4 "LINIER,PSI5-S LIN interrupt enable register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable" "0: No interrupt,1: Interrupt generation enabled" newline bitfld.long 0x4 14. "OCIE,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generation enabled" newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable" "0: No interrupt,1: Interrupt generation enabled" newline bitfld.long 0x4 5. "WUIE,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x4 3. "TOIE,Timeout Interrupt Enable" "0: No interrupt,1: Interrupt generation enabled." newline bitfld.long 0x4 2. "DRIE,Data Reception complete Interrupt enable" "0: No interrupt,1: Interrupt generation enabled" newline bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable" "0: No interrupt,1: Interrupt generation enabled" line.long 0x8 "LINSR,PSI5-S LIN status register" bitfld.long 0x8 15. "LINS3,PS_NOUSE_BITS" "0,1" newline bitfld.long 0x8 14. "LINS2,PS_NOUSE_BITS" "0,1" newline bitfld.long 0x8 13. "LINS1,PS_NOUSE_BITS" "0,1" newline bitfld.long 0x8 12. "LINS0,PS_NOUSE_BITS" "0,1" group.long 0x10++0x7 line.long 0x0 "UARTCR,PSI5-S UART mode control register" bitfld.long 0x0 31. "MIS,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x0 28.--30. "CSP,Configurable Sample Point" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--27. 1. "OSR,Over Sampling Rate" newline bitfld.long 0x0 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR bits decide the over sampling rate." newline bitfld.long 0x0 20.--22. "NEF,PS_NOUSE_BIT" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "PCE_TX_DTU,In PSI5-S mode Parity Control Enable for Tx path (In UART STANDLONE mode used to disable UART timeout refer to Chapter56) LINFlexD for more details):" "0: Parity generation for Tx path disabled.,1: Parity generation for Tx path enabled." newline bitfld.long 0x0 17.--18. "SBUR,PS_NOUSE_BIT" "0,1,2,3" newline bitfld.long 0x0 16. "WLS,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x0 13.--15. "TDFL_TFC,PS_NOUSE_BIT" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10.--12. "RDFL_RFC,PS_NOUSE_BIT" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9. "RFBM,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x0 8. "TFBM,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x0 7. "WL1,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x0 6. "PC1,Parity Control {PC1 PC0}" "0: Parity is Even for both the Rx/Tx paths.,1: Parity is Odd for both the Rx/Tx paths." newline bitfld.long 0x0 5. "RXEN,Receiver Enable" "0: Receiver disabled,1: Receiver enabled" newline bitfld.long 0x0 4. "TXEN,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." newline bitfld.long 0x0 3. "PC0,Parity Control {PC1 PC0}" "0: Parity is Even for both the Rx/Tx paths,1: Parity is Odd for both the Rx/Tx paths." newline bitfld.long 0x0 2. "PCE_RX,Receive Parity check enable." "0: Disable the parity checking on the Rx path,1: Enable the parity checking on the Rx path" newline bitfld.long 0x0 1. "WL0,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x0 0. "UART,PS_NOUSE_BIT" "0,1" line.long 0x4 "UARTSR,PSI5-S UART mode status register" bitfld.long 0x4 15. "SZF,Stuck at Zero flag" "0,1" newline bitfld.long 0x4 14. "OCF,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x4 13. "PE3,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x4 12. "PE2,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x4 11. "PE1,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x4 10. "PE0,Parity Error flag for Data0 byte" "0: No parity error,1: Parity error in the corresponding received byte" newline bitfld.long 0x4 9. "RMB,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x4 8. "FEF,Framing Error flag" "0,1" newline bitfld.long 0x4 7. "BOF,Buffer overrun flag" "0,1" newline bitfld.long 0x4 6. "RDI,Receiver Data Input signal" "0,1" newline bitfld.long 0x4 5. "WUF,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x4 4. "RFNE,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x4 3. "TO,Timeout" "0,1" newline bitfld.long 0x4 2. "DRF,Data Reception Completed Flag" "0,1" newline bitfld.long 0x4 1. "DTF,Data Transmission Completed Flag" "0,1" newline bitfld.long 0x4 0. "NF,Noise flag" "0,1" group.long 0x24++0x7 line.long 0x0 "LINFBRR,PSI5-S LIN fractional baud rate register" bitfld.long 0x0 3. "FBR3,Fractional Baud rates. Refer to the Note: on page 2541." "0,1" newline bitfld.long 0x0 2. "FBR2,Fractional Baud rates. Refer to the Note: on page 2541." "0,1" newline bitfld.long 0x0 1. "FBR1,Fractional Baud rates. Refer to the Note: on page 2541." "0,1" newline bitfld.long 0x0 0. "FBR0,Fractional Baud rates. Refer to the Note: on page 2541." "0,1" line.long 0x4 "LINIBRR,LIN integer baud rate register" bitfld.long 0x4 19. "IBR19,Integer Baud rates" "0,1" newline bitfld.long 0x4 18. "IBR18,Integer Baud rates" "0,1" newline bitfld.long 0x4 17. "IBR17,Integer Baud rates" "0,1" newline bitfld.long 0x4 16. "IBR16,Integer Baud rates" "0,1" newline bitfld.long 0x4 15. "IBR15,Integer Baud rates" "0,1" newline bitfld.long 0x4 14. "IBR14,Integer Baud rates" "0,1" newline bitfld.long 0x4 13. "IBR13,Integer Baud rates" "0,1" newline bitfld.long 0x4 12. "IBR12,Integer Baud rates" "0,1" newline bitfld.long 0x4 11. "IBR11,Integer Baud rates" "0,1" newline bitfld.long 0x4 10. "IBR10,Integer Baud rates" "0,1" newline bitfld.long 0x4 9. "IBR9,Integer Baud rates" "0,1" newline bitfld.long 0x4 8. "IBR8,Integer Baud rates" "0,1" newline bitfld.long 0x4 7. "IBR7,Integer Baud rates" "0,1" newline bitfld.long 0x4 6. "IBR6,Integer Baud rates" "0,1" newline bitfld.long 0x4 5. "IBR5,Integer Baud rates" "0,1" newline bitfld.long 0x4 4. "IBR4,Integer Baud rates" "0,1" newline bitfld.long 0x4 3. "IBR3,Integer Baud rates" "0,1" newline bitfld.long 0x4 2. "IBR2,Integer Baud rates" "0,1" newline bitfld.long 0x4 1. "IBR1,Integer Baud rates" "0,1" newline bitfld.long 0x4 0. "IBR0,Integer Baud rates" "0,1" group.long 0x30++0x3 line.long 0x0 "LINCR2,PSI5-S LIN control register 2" bitfld.long 0x0 9. "ABRQ,Abort Request" "0,1" group.long 0x38++0x7 line.long 0x0 "BDRL,PSI5-S buffer data register least significant" hexmask.long.byte 0x0 24.--31. 1. "DATA_TX3,PS_NOUSE_BIT" newline hexmask.long.byte 0x0 16.--23. 1. "DATA_TX2,PS_NOUSE_BIT" newline hexmask.long.byte 0x0 8.--15. 1. "DATA_TX1,PS_NOUSE_BIT" newline hexmask.long.byte 0x0 0.--7. 1. "DATA_TX0,Data Byte for Tx." line.long 0x4 "BDRM,PSI5-S buffer data register most significant" hexmask.long.byte 0x4 24.--31. 1. "DATA_RX3,PS_NOUSE_BIT" newline hexmask.long.byte 0x4 16.--23. 1. "DATA_RX2,PS_NOUSE_BIT" newline hexmask.long.byte 0x4 8.--15. 1. "DATA_RX1,PS_NOUSE_BIT" newline hexmask.long.byte 0x4 0.--7. 1. "DATA_RX0,Receive data byte for Rx" group.long 0x4C++0x7 line.long 0x0 "GCR,PSI5-S global control register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB" "0: The first bit of transmitted data is LSB in..,1: The first bit of transmitted data is MSB in.." newline bitfld.long 0x0 4. "RDFBM,Received data first bit MSB" "0: The first bit of received data is LSB in other..,1: The first bit of received data is MSB in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection" "0: Transmitted data is not inverted,1: Transmitted data is inverted" newline bitfld.long 0x0 2. "RDLIS,Received data level inversion selection" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,PS_NOUSE_BIT" "0,1" newline bitfld.long 0x0 0. "SR,Soft reset" "0,1" line.long 0x4 "UARTPTO,PSI5-S UART preset timeout register" bitfld.long 0x4 11. "PTO11,Preset Timeout" "0,1" newline bitfld.long 0x4 10. "PTO10,Preset Timeout" "0,1" newline bitfld.long 0x4 9. "PTO9,Preset Timeout" "0,1" newline bitfld.long 0x4 8. "PTO8,Preset Timeout" "0,1" newline bitfld.long 0x4 7. "PTO7,Preset Timeout" "0,1" newline bitfld.long 0x4 6. "PTO6,Preset Timeout" "0,1" newline bitfld.long 0x4 5. "PTO5,Preset Timeout" "0,1" newline bitfld.long 0x4 4. "PTO4,Preset Timeout" "0,1" newline bitfld.long 0x4 3. "PTO3,Preset Timeout" "0,1" newline bitfld.long 0x4 2. "PTO2,Preset Timeout" "0,1" newline bitfld.long 0x4 1. "PTO1,Preset Timeout" "0,1" newline bitfld.long 0x4 0. "PTO0,Preset Timeout" "0,1" rgroup.long 0x54++0x3 line.long 0x0 "UARTCTO,PSI5-S UART current timeout register" bitfld.long 0x0 11. "CTO11,Current Timeout" "0,1" newline bitfld.long 0x0 10. "CTO10,Current Timeout" "0,1" newline bitfld.long 0x0 9. "CTO9,Current Timeout" "0,1" newline bitfld.long 0x0 8. "CTO8,Current Timeout" "0,1" newline bitfld.long 0x0 7. "CTO7,Current Timeout" "0,1" newline bitfld.long 0x0 6. "CTO6,Current Timeout" "0,1" newline bitfld.long 0x0 5. "CTO5,Current Timeout" "0,1" newline bitfld.long 0x0 4. "CTO4,Current Timeout" "0,1" newline bitfld.long 0x0 3. "CTO3,Current Timeout" "0,1" newline bitfld.long 0x0 2. "CTO2,Current Timeout" "0,1" newline bitfld.long 0x0 1. "CTO1,Current Timeout" "0,1" newline bitfld.long 0x0 0. "CTO0,Current Timeout" "0,1" group.long 0x58++0xB line.long 0x0 "DMATXE,DMA Tx enable register" bitfld.long 0x0 0. "DTE0,PS_NOUSE_BIT" "0,1" line.long 0x4 "DMARXE,DMA Rx enable register" bitfld.long 0x4 0. "DRE0,PS_NOUSE_BIT" "0,1" line.long 0x8 "PTD,PSI5-S UART Tx idle delay time" hexmask.long.byte 0x8 1.--4. 1. "IFD,Interframe Delay" newline bitfld.long 0x8 0. "EN,IFD Enable" "0: The IFD is active in the UART Tx path,1: The IFD is inactive" group.long 0xB4++0x1B line.long 0x0 "GLCR,PSI5-S global control register" bitfld.long 0x0 22.--23. "DIRCMD_LEN,Direct Command Length Register" "0: 1 byte command: 1 byte {DIRCMD_BYTE0} of the..,1: 2 byte command: 2 bytes {DIRCMD_BYTE1..,2: 4 byte command: 4 bytes,3: 4 byte command: 4 bytes {DIRCMD_BYTE3.." newline bitfld.long 0x0 20. "IE_DIRCMD_RDY,Interrupt enable bit for DIRCMD_RDY" "0: PS_GLCR[DIRCMD_RDY] when goes as '1' does not..,1: PS_GLCR[DIRCMD_RDY] when goes as '1' generates.." newline bitfld.long 0x0 18. "DEBUG_EN,Debug enable bit" "0: The IP does not enter the debug mode when a..,1: The IP enters the debug mode immediately as soon.." newline bitfld.long 0x0 15. "GL_DDSR_TRIG,This is the global shift trigger of all the DDSRs of each channel. When the corresponding PS_E2SCR_CH[n][GL_TRIG_SEL]==1 only then is this bit effective else this bit has no effect." "0: Shift triggers of all the DDSR registers are..,1: The shift triggers of all the DDSR's start.." newline bitfld.long 0x0 14. "GL_MODETR_DONE_EN,Interrupt enable for PS_GLSR[GL_MODETR_DONE] bit" "0: No interrupt is generated on setting of the..,1: Generates the interrupt when.." newline bitfld.long 0x0 13. "MRU_ERR_EN,Enables the interrupt for MRU overwrite when the unread contents of MRU Buffer1 are overwritten by a new message." "0: MRU overwrite error is not enabled.,1: MRU overwrite error is enabled." newline bitfld.long 0x0 12. "TSCS_B,This bit controls the selection of clock input to timestamp counter B either by the external periodic clock or by the GTM module." "0: External clock (ipg_clk_ps_ts) is selected.,1: gtm_trig is selected as the clock." newline bitfld.long 0x0 11. "TSCS_A,This bit controls the selection of clock input to timestamp counter A either by the external periodic clock or by the GTM module." "0: External clock (ipg_clk_ps_ts) is selected.,1: gtm_trig is selected as the clock." newline bitfld.long 0x0 10. "CLR_CNTR_B,This bit resets timestamp counter B when PS_GLCR[CLRTSCNT_G_L] is NOT set." "?,1: Timestamp counter B is reset." newline bitfld.long 0x0 9. "CLR_CNTR_A,This bit resets timestamp counter A when PS_GLCR[CLRTSCNT_G_L] is NOT set." "?,1: Timestamp counter A is reset." newline bitfld.long 0x0 8. "CLRTSCNT_G,This bit controls the global clearing of the timestamp counters A and B when CLRTSCNT_G_L==1. When CLRTSCNT_G_L == 0 then this bit has no effect." "?,1: Both timestamp counters are cleared at the same.." newline bitfld.long 0x0 7. "CLRTSCNT_G_L,This bit control whether the timestamp counters counter A and B are cleared simultaneously or independently:" "0: Timestamp counters A and B are cleared..,1: Both timestamp counters are cleared.." newline bitfld.long 0x0 6. "TSCNT_EN_B,This bit controls enabling of timestamp counter A when PS_GLCR[TSCNTEN_G_L] is not set." "0: Timestamp counter A not enabled.,1: Timestamp counter B is enabled." newline bitfld.long 0x0 5. "TSCNT_EN_A,This bit controls enabling of timestamp counter A when PS_GLCR[TSCNTEN_G_L] is not set." "0: Timestamp counter A not enabled.,1: Timestamp counter A is enabled." newline bitfld.long 0x0 4. "TSCNTEN_G,This bit controls the global trigger of the timestamp counters A and B when TSCNTEN_G_L==1. When TSCNTEN_G_L==0x0: then this bit has no effect." "0: then this bit has no effect,1: Both timestamp counters start simultaneously." newline bitfld.long 0x0 3. "TSCNTEN_G_L,This bit control whether the timestamp counters counter A and B are started simultaneously or independently." "0: Timestamp counters A and B are started..,1: Both timestamp counters are triggered.." newline bitfld.long 0x0 0.--2. "GLOBAL_MODE,These are the bits which decide Global Mode of the IP. There are 4 modes UART_STDALONE PS_DISABLE PS_CONFIG and PS_NORMAL. For details of modes related to GLOBAL_MODE bit setting refer to Table1619) State transition." "0,1,2,3,4,5,6,7" line.long 0x4 "GLSR,PSI5-S global status register" bitfld.long 0x4 20. "DIRCMD_RDY,Bit used to indicate the 'Ready for Direct Command write' status:" "0: Direct Command that is written to the PS_DIRCMD..,1: The PS_DIRCMD register is empty and the.." newline bitfld.long 0x4 14. "GL_MODETR_DONE,This bit indicates as to when the global mode transitions as programmed by PS_GLCR[GLOBAL_MODE] have actually been accomplished:" "0: The intended global mode as programmed in the..,1: The global mode as programmed in the.." newline bitfld.long 0x4 13. "MRU_ERR,This bit shows whether unread MRU buffer1 contents have been overwritten by a new message:" "0: No overwrite occurred.,1: Overwrite occurred." newline bitfld.long 0x4 3.--5. "FID,Points to the frame whose data in MRU buffer 1 was overwritten." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "CHID,Points to the channel whose data in MRU buffer 1 was overwritten." "0,1,2,3,4,5,6,7" line.long 0x8 "CH_BASE_ADDR,PSI5-S channel base address register" hexmask.long 0x8 0.--31. 1. "MAILBOX_BASE_ADDR,This register provides the base address of the mailbox in the system RAM.This value needs to be programmed by the software." line.long 0xC "MRU_BUF2_REG0,PSI5-S MRU output buffer 2 register 0" hexmask.long 0xC 0.--31. 1. "CHANNEL_SPECIFIC_MAILBOX_ADDR,This register provides the channel specific mailbox address corresponding to channel and slot for which data has been received.This value is computed by the IP based on the PS_CH_BASE_ADDR[MAILBOX_BASE_ADDR] and FID CID." line.long 0x10 "MRU_BUF2_REG1,PSI5-S MRU output buffer 2 register 1" hexmask.long.byte 0x10 28.--31. 1. "DCI,To ensure that the Application reads the PSI5 message and its timestamp consistently Data Consistency Indicator (DCI) is added to each word of the Message Reconstruction Unit Output buffer and subsequently is transferred to the PSI5 Mailbox in.." newline bitfld.long 0x10 26. "R_UVL_ERR,Message underflow" "0: No error occurred,1: PSI5 message extraction" newline bitfld.long 0x10 25. "N_ERR,Indicates that the number of UART bytes in the received UART packet does not match the number specified in Channel Configuration Register A indicated by CID and FID that is the number of UART bytes does not match the value programmed in.." "0: No error occurred,1: PSI5 message extraction" newline bitfld.long 0x10 22.--24. "CHID,Indicates Channel id of PSI5 message present in the UART header byte." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 19.--21. "FID,Indicates Frame ID of PSI5 message present in the UART header byte." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 18. "R_OVL_ERR,Message overflow.It is set when more than six UART bytes are received in the UART packet.The message may be recoverable (XCRC_ERR == 0) or unrecoverable (XCRC_ERR==1). Refer to Section54.4.2.1: PSI5 message extraction for more details." "0: No error occurred,1: PSI5 message extraction" newline bitfld.long 0x10 17. "F_WD_ERR,Frame watchdog error in the received PSI5 message" "0: No error occurred,1: Error occurred" newline bitfld.long 0x10 16. "SCI_O_ERR,UART overrun error has occurred in at least one UART byte of the received UART packet due to which some UART byte has been lost." "0: No error occurred,1: Error occurred" newline bitfld.long 0x10 15. "SCI_F_ERR,UART framing error has occurred in the current received UART packet." "0: No error occurred,1: Error occurred" newline bitfld.long 0x10 14. "SCI_P_ERR,UART message parity error has occurred in at least one UART byte of the received UART packet." "0: No error occurred,1: Error occurred" newline bitfld.long 0x10 13. "HD_ERR,This bit is set when any of the ERR[1:0] is '1' and indicates a transceiver error." "0: No error occurred,1: Error occurred" newline bitfld.long 0x10 11.--12. "ERR,Transceiver error flags received in the Message header byte of the UART packet indicated by CID and FID." "0,1,2,3" newline bitfld.long 0x10 10. "CRC_ERR_P_ERR,Indicates whether 'PSI5 message' crc_err or the parity error in the PSI5 message indicated by CID and FID has occurred. The Parity is taken as even for PSI5 calculation:" "0: No crc_error/parity error has occurred,1: Indicates crc_error/Parity Error has occurred" newline bitfld.long 0x10 7.--9. "CRC,Contains the received CRC or Parity Bits of the PSI5 message of indicated by CID and FID." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 6. "XCRC_ERR,Indicates xcrc_err in the received UART packet:" "0: No xcrc_error occurred,1: Indicates xcrc_error occurred" newline hexmask.long.byte 0x10 0.--5. 1. "XCRC,This is the value of XCRC received in the last six bits of the UART byte which occurs just before the information of a 'new UART packet received' has been generated. Refer to Section54.4.1: PSI5-S UART message structure and Section54.4.2.5: PSI5-S.." line.long 0x14 "MRU_BUF2_REG2,PSI5-S MRU output buffer 2 register 2" hexmask.long.byte 0x14 28.--31. 1. "DCI,To ensure that the Application reads the PSI5 message and its timestamp consistently Data Consistency Indicator (DCI) is added to each word of the Message Reconstruction Unit Output buffer and subsequently is transferred to the PSI5 Mailbox in.." newline hexmask.long 0x14 0.--27. 1. "PS_DATA,PSI5 data bits extracted from the received UART bytes." line.long 0x18 "MRU_BUF2_REG3,PSI5-S MRU output buffer 2 register 3" hexmask.long.byte 0x18 28.--31. 1. "DCI,To ensure that the Application reads the PSI5 message and its timestamp consistently Data Consistency Indicator (DCI) is added to each word of the Message Reconstruction Unit Output buffer and subsequently is transferred to the PSI5 Mailbox in.." newline hexmask.long.tbyte 0x18 0.--23. 1. "TIMESTAMP,Time stamp value appended based on the various timestamp bit settings in the PS_GLCR register PS_PCCR_CH[n] register and the errors occurred. Refer to Section54.4.4: Timestamp for more details." group.long 0xE0++0x4F line.long 0x0 "MBOX_SR_IRQ,PSI5-S mbox status IRQ" bitfld.long 0x0 7. "MBOX_CH7,When set it Indicates at least one message in mailbox 7 is pending for read by the application." "0,1" newline bitfld.long 0x0 6. "MBOX_CH6,When set it Indicates at least one message in mailbox 6 is pending for read by the application." "0,1" newline bitfld.long 0x0 5. "MBOX_CH5,When set it Indicates at least one message in mailbox 5 is pending for read by the application." "0,1" newline bitfld.long 0x0 4. "MBOX_CH4,When set it Indicates at least one message in mailbox 4 is pending for read by the application." "0,1" newline bitfld.long 0x0 3. "MBOX_CH3,When set it Indicates at least one message in mailbox 3 is pending for read by the application." "0,1" newline bitfld.long 0x0 2. "MBOX_CH2,When set it Indicates at least one message in mailbox 2 is pending for read by the application." "0,1" newline bitfld.long 0x0 1. "MBOX_CH1,When set it Indicates at least one message in mailbox 1is pending for read by the application." "0,1" newline bitfld.long 0x0 0. "MBOX_CH0,When set it Indicates at least one message in mailbox 0is pending for read by the application." "0,1" line.long 0x4 "ERR_SR_IRQ,PSI5-S error status IRQ" bitfld.long 0x4 9. "R_UVL_ERR,When set indicates that message underflow error (number of UART bytes received are less than 3) is present in the message currently present in MRU buf2." "0,1" newline bitfld.long 0x4 8. "N_ERR,When set indicates that N_ERR (Number of UART bytes are not equal to PS_MSGA_CHn[Fn_byte]) is present in the message currently present in MRU buf2." "0,1" newline bitfld.long 0x4 7. "R_OVL_ERR,When set indicates that message Overflow error (number of UART bytes received have exceeded 6) is present in the message currently present in MRU buf2." "0,1" newline bitfld.long 0x4 6. "F_WD_ERR,When set indicates that Frame Watchdog error is present in the message currently present in MRU buf2." "0,1" newline bitfld.long 0x4 5. "SCI_O_ERR,When set indicates that UART Overrun error (from the UART side) is present in the message currently present in MRU buf2. When '1' then this bit indicates that some UART byte belonging to the concerned UART packet has been overwritten by.." "0,1" newline bitfld.long 0x4 4. "SCI_F_ERR,When set indicates that UART Framing error is present in the message currently present in MRU buf2. If this bit is set then it indicates to the application that the synchronization of the UART module is lost and any subsequent UART bytes.." "0,1" newline bitfld.long 0x4 3. "SCI_P_ERR,When set indicates that UART parity error is present in the message currently present in MRU buf2. This bit is set when there is a parity error in any UART byte using which the concerned UART packet was formed." "0,1" newline bitfld.long 0x4 2. "HD_ERR,When set indicates that Header error (E0/E1) is present in the message currently present in MRU buf2." "0,1" newline bitfld.long 0x4 1. "CRC_ERR_P_ERR,When set indicates that PSI5 CRC/Parity error is present in the message currently present in MRU buf2." "0,1" newline bitfld.long 0x4 0. "XCRC_ERR,When set indicates that XCRC error is present in the message currently present in MRU buf2." "0,1" line.long 0x8 "MBOX_SEL_IRQ0,PSI5-S mailbox select IRQ0" bitfld.long 0x8 7. "MBOX_CH7_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH7] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH7] contributes to.." newline bitfld.long 0x8 6. "MBOX_CH6_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH6] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH6] contributes to.." newline bitfld.long 0x8 5. "MBOX_CH5_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH5] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH5] contributes to.." newline bitfld.long 0x8 4. "MBOX_CH4_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH4] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH4] contributes to.." newline bitfld.long 0x8 3. "MBOX_CH3_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH3] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH3] contributes to.." newline bitfld.long 0x8 2. "MBOX_CH2_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH2] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH2] contributes to.." newline bitfld.long 0x8 1. "MBOX_CH1_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH1] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH1] contributes to.." newline bitfld.long 0x8 0. "MBOX_CH0_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH0] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH0] contributes to.." line.long 0xC "ERR_SEL_IRQ0,PSI5-S error select IRQ0" bitfld.long 0xC 9. "R_UVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] contributes to.." newline bitfld.long 0xC 8. "N_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[N_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[N_ERR_SEL] contributes to.." newline bitfld.long 0xC 7. "R_OVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] contributes to.." newline bitfld.long 0xC 6. "F_WD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[F_WD_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[F_WD_ERR_SEL] contributes to.." newline bitfld.long 0xC 5. "SCI_O_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] contributes to.." newline bitfld.long 0xC 4. "SCI_F_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] contributes to.." newline bitfld.long 0xC 3. "SCI_P_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] contributes to.." newline bitfld.long 0xC 2. "HD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[HD_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[HD_ERR_SEL] contributes to.." newline bitfld.long 0xC 1. "CRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[CRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[CRC_ERR_SEL] contributes to.." newline bitfld.long 0xC 0. "XCRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[XCRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[XCRC_ERR_SEL] contributes to.." line.long 0x10 "MBOX_SEL_IRQ1,PSI5-S mailbox select IRQ1" bitfld.long 0x10 7. "MBOX_CH7_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH7] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH7] contributes to.." newline bitfld.long 0x10 6. "MBOX_CH6_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH6] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH6] contributes to.." newline bitfld.long 0x10 5. "MBOX_CH5_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH5] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH5] contributes to.." newline bitfld.long 0x10 4. "MBOX_CH4_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH4] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH4] contributes to.." newline bitfld.long 0x10 3. "MBOX_CH3_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH3] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH3] contributes to.." newline bitfld.long 0x10 2. "MBOX_CH2_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH2] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH2] contributes to.." newline bitfld.long 0x10 1. "MBOX_CH1_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH1] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH1] contributes to.." newline bitfld.long 0x10 0. "MBOX_CH0_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH0] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH0] contributes to.." line.long 0x14 "ERR_SEL_IRQ1,PSI5-S error select IRQ1" bitfld.long 0x14 9. "R_UVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] contributes to.." newline bitfld.long 0x14 8. "N_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[N_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[N_ERR_SEL] contributes to.." newline bitfld.long 0x14 7. "R_OVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] contributes to.." newline bitfld.long 0x14 6. "F_WD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[F_WD_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[F_WD_ERR_SEL] contributes to.." newline bitfld.long 0x14 5. "SCI_O_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] contributes to.." newline bitfld.long 0x14 4. "SCI_F_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] contributes to.." newline bitfld.long 0x14 3. "SCI_P_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] contributes to.." newline bitfld.long 0x14 2. "HD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[HD_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[HD_ERR_SEL] contributes to.." newline bitfld.long 0x14 1. "CRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[CRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[CRC_ERR_SEL] contributes to.." newline bitfld.long 0x14 0. "XCRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[XCRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[XCRC_ERR_SEL] contributes to.." line.long 0x18 "MBOX_SEL_IRQ2,PSI5-S mailbox select IRQ2" bitfld.long 0x18 7. "MBOX_CH7_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH7] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH7] contributes to.." newline bitfld.long 0x18 6. "MBOX_CH6_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH6] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH6] contributes to.." newline bitfld.long 0x18 5. "MBOX_CH5_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH5] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH5] contributes to.." newline bitfld.long 0x18 4. "MBOX_CH4_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH4] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH4] contributes to.." newline bitfld.long 0x18 3. "MBOX_CH3_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH3] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH3] contributes to.." newline bitfld.long 0x18 2. "MBOX_CH2_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH2] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH2] contributes to.." newline bitfld.long 0x18 1. "MBOX_CH1_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH1] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH1] contributes to.." newline bitfld.long 0x18 0. "MBOX_CH0_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH0] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH0] contributes to.." line.long 0x1C "ERR_SEL_IRQ2,PSI5-S error select IRQ2" bitfld.long 0x1C 9. "R_UVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] contributes to.." newline bitfld.long 0x1C 8. "N_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[N_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[N_ERR_SEL] contributes to.." newline bitfld.long 0x1C 7. "R_OVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] contributes to.." newline bitfld.long 0x1C 6. "F_WD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[F_WD_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[F_WD_ERR_SEL] contributes to.." newline bitfld.long 0x1C 5. "SCI_O_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] contributes to.." newline bitfld.long 0x1C 4. "SCI_F_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] contributes to.." newline bitfld.long 0x1C 3. "SCI_P_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] contributes to.." newline bitfld.long 0x1C 2. "HD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[HD_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[HD_ERR_SEL] contributes to.." newline bitfld.long 0x1C 1. "CRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[CRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[CRC_ERR_SEL] contributes to.." newline bitfld.long 0x1C 0. "XCRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[XCRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[XCRC_ERR_SEL] contributes to.." line.long 0x20 "MBOX_SEL_IRQ3,PSI5-S mailbox select IRQ3" bitfld.long 0x20 7. "MBOX_CH7_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH7] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH7] contributes to.." newline bitfld.long 0x20 6. "MBOX_CH6_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH6] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH6] contributes to.." newline bitfld.long 0x20 5. "MBOX_CH5_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH5] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH5] contributes to.." newline bitfld.long 0x20 4. "MBOX_CH4_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH4] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH4] contributes to.." newline bitfld.long 0x20 3. "MBOX_CH3_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH3] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH3] contributes to.." newline bitfld.long 0x20 2. "MBOX_CH2_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH2] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH2] contributes to.." newline bitfld.long 0x20 1. "MBOX_CH1_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH1] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH1] contributes to.." newline bitfld.long 0x20 0. "MBOX_CH0_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH0] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH0] contributes to.." line.long 0x24 "ERR_SEL_IRQ3,PSI5-S error select IRQ3" bitfld.long 0x24 9. "R_UVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] contributes to.." newline bitfld.long 0x24 8. "N_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[N_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[N_ERR_SEL] contributes to.." newline bitfld.long 0x24 7. "R_OVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] contributes to.." newline bitfld.long 0x24 6. "F_WD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[F_WD_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[F_WD_ERR_SEL] contributes to.." newline bitfld.long 0x24 5. "SCI_O_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] contributes to.." newline bitfld.long 0x24 4. "SCI_F_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] contributes to.." newline bitfld.long 0x24 3. "SCI_P_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] contributes to.." newline bitfld.long 0x24 2. "HD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[HD_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[HD_ERR_SEL] contributes to.." newline bitfld.long 0x24 1. "CRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[CRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[CRC_ERR_SEL] contributes to.." newline bitfld.long 0x24 0. "XCRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[XCRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[XCRC_ERR_SEL] contributes to.." line.long 0x28 "MBOX_SEL_IRQ4,PSI5-S mailbox select IRQ4" bitfld.long 0x28 7. "MBOX_CH7_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH7] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH7] contributes to.." newline bitfld.long 0x28 6. "MBOX_CH6_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH6] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH6] contributes to.." newline bitfld.long 0x28 5. "MBOX_CH5_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH5] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH5] contributes to.." newline bitfld.long 0x28 4. "MBOX_CH4_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH4] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH4] contributes to.." newline bitfld.long 0x28 3. "MBOX_CH3_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH3] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH3] contributes to.." newline bitfld.long 0x28 2. "MBOX_CH2_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH2] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH2] contributes to.." newline bitfld.long 0x28 1. "MBOX_CH1_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH1] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH1] contributes to.." newline bitfld.long 0x28 0. "MBOX_CH0_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH0] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH0] contributes to.." line.long 0x2C "ERR_SEL_IRQ4,PSI5-S error select IRQ4" bitfld.long 0x2C 9. "R_UVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] contributes to.." newline bitfld.long 0x2C 8. "N_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[N_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[N_ERR_SEL] contributes to.." newline bitfld.long 0x2C 7. "R_OVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] contributes to.." newline bitfld.long 0x2C 6. "F_WD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[F_WD_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[F_WD_ERR_SEL] contributes to.." newline bitfld.long 0x2C 5. "SCI_O_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] contributes to.." newline bitfld.long 0x2C 4. "SCI_F_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] contributes to.." newline bitfld.long 0x2C 3. "SCI_P_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] contributes to.." newline bitfld.long 0x2C 2. "HD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[HD_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[HD_ERR_SEL] contributes to.." newline bitfld.long 0x2C 1. "CRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[CRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[CRC_ERR_SEL] contributes to.." newline bitfld.long 0x2C 0. "XCRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[XCRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[XCRC_ERR_SEL] contributes to.." line.long 0x30 "MBOX_SEL_IRQ5,PSI5-S mailbox select IRQ5" bitfld.long 0x30 7. "MBOX_CH7_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH7] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH7] contributes to.." newline bitfld.long 0x30 6. "MBOX_CH6_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH6] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH6] contributes to.." newline bitfld.long 0x30 5. "MBOX_CH5_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH5] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH5] contributes to.." newline bitfld.long 0x30 4. "MBOX_CH4_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH4] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH4] contributes to.." newline bitfld.long 0x30 3. "MBOX_CH3_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH3] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH3] contributes to.." newline bitfld.long 0x30 2. "MBOX_CH2_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH2] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH2] contributes to.." newline bitfld.long 0x30 1. "MBOX_CH1_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH1] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH1] contributes to.." newline bitfld.long 0x30 0. "MBOX_CH0_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH0] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH0] contributes to.." line.long 0x34 "ERR_SEL_IRQ5,PSI5-S error select IRQ5" bitfld.long 0x34 9. "R_UVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] contributes to.." newline bitfld.long 0x34 8. "N_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[N_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[N_ERR_SEL] contributes to.." newline bitfld.long 0x34 7. "R_OVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] contributes to.." newline bitfld.long 0x34 6. "F_WD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[F_WD_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[F_WD_ERR_SEL] contributes to.." newline bitfld.long 0x34 5. "SCI_O_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] contributes to.." newline bitfld.long 0x34 4. "SCI_F_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] contributes to.." newline bitfld.long 0x34 3. "SCI_P_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] contributes to.." newline bitfld.long 0x34 2. "HD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[HD_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[HD_ERR_SEL] contributes to.." newline bitfld.long 0x34 1. "CRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[CRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[CRC_ERR_SEL] contributes to.." newline bitfld.long 0x34 0. "XCRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[XCRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[XCRC_ERR_SEL] contributes to.." line.long 0x38 "MBOX_SEL_IRQ6,PSI5-S mailbox select IRQ6" bitfld.long 0x38 7. "MBOX_CH7_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH7] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH7] contributes to.." newline bitfld.long 0x38 6. "MBOX_CH6_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH6] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH6] contributes to.." newline bitfld.long 0x38 5. "MBOX_CH5_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH5] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH5] contributes to.." newline bitfld.long 0x38 4. "MBOX_CH4_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH4] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH4] contributes to.." newline bitfld.long 0x38 3. "MBOX_CH3_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH3] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH3] contributes to.." newline bitfld.long 0x38 2. "MBOX_CH2_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH2] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH2] contributes to.." newline bitfld.long 0x38 1. "MBOX_CH1_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH1] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH1] contributes to.." newline bitfld.long 0x38 0. "MBOX_CH0_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH0] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH0] contributes to.." line.long 0x3C "ERR_SEL_IRQ6,PSI5-S error select IRQ6" bitfld.long 0x3C 9. "R_UVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] contributes to.." newline bitfld.long 0x3C 8. "N_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[N_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[N_ERR_SEL] contributes to.." newline bitfld.long 0x3C 7. "R_OVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] contributes to.." newline bitfld.long 0x3C 6. "F_WD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[F_WD_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[F_WD_ERR_SEL] contributes to.." newline bitfld.long 0x3C 5. "SCI_O_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] contributes to.." newline bitfld.long 0x3C 4. "SCI_F_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] contributes to.." newline bitfld.long 0x3C 3. "SCI_P_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] contributes to.." newline bitfld.long 0x3C 2. "HD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[HD_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[HD_ERR_SEL] contributes to.." newline bitfld.long 0x3C 1. "CRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[CRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[CRC_ERR_SEL] contributes to.." newline bitfld.long 0x3C 0. "XCRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[XCRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[XCRC_ERR_SEL] contributes to.." line.long 0x40 "MBOX_SEL_IRQ7,PSI5-S mailbox select IRQ7" bitfld.long 0x40 7. "MBOX_CH7_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH7] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH7] contributes to.." newline bitfld.long 0x40 6. "MBOX_CH6_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH6] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH6] contributes to.." newline bitfld.long 0x40 5. "MBOX_CH5_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH5] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH5] contributes to.." newline bitfld.long 0x40 4. "MBOX_CH4_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH4] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH4] contributes to.." newline bitfld.long 0x40 3. "MBOX_CH3_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH3] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH3] contributes to.." newline bitfld.long 0x40 2. "MBOX_CH2_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH2] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH2] contributes to.." newline bitfld.long 0x40 1. "MBOX_CH1_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH1] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH1] contributes to.." newline bitfld.long 0x40 0. "MBOX_CH0_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_MBOX_SR_IRQ[MBOX_CH0] does not contribute to..,1: PS_MBOX_SR_IRQ[MBOX_CH0] contributes to.." line.long 0x44 "ERR_SEL_IRQ7,PSI5-S error select IRQ7" bitfld.long 0x44 9. "R_UVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_UVL_ERR_SEL] contributes to.." newline bitfld.long 0x44 8. "N_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[N_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[N_ERR_SEL] contributes to.." newline bitfld.long 0x44 7. "R_OVL_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[R_OVL_ERR_SEL] contributes to.." newline bitfld.long 0x44 6. "F_WD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[F_WD_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[F_WD_ERR_SEL] contributes to.." newline bitfld.long 0x44 5. "SCI_O_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_O_ERR_SEL] contributes to.." newline bitfld.long 0x44 4. "SCI_F_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_F_ERR_SEL] contributes to.." newline bitfld.long 0x44 3. "SCI_P_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[SCI_P_ERR_SEL] contributes to.." newline bitfld.long 0x44 2. "HD_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[HD_ERR_SEL] does not contribute to..,1: PS_ERR_SR_IRQ[HD_ERR_SEL] contributes to.." newline bitfld.long 0x44 1. "CRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[CRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[CRC_ERR_SEL] contributes to.." newline bitfld.long 0x44 0. "XCRC_ERR_SEL,Interrupt Selection source for irq[irq_n] interrupt" "0: PS_ERR_SR_IRQ[XCRC_ERR_SEL] does not contribute..,1: PS_ERR_SR_IRQ[XCRC_ERR_SEL] contributes to.." line.long 0x48 "WDGTSSR,PSI5-S watchdog error status and watchdog timestamp status register" hexmask.long.byte 0x48 25.--31. 1. "F_WD_ERR_STATUS,F_WD_ERR_STATUS[7:1]" newline hexmask.long.tbyte 0x48 0.--23. 1. "WDGTS_STATUS,Timestamp value of that specific channel the timestamp of which is captured when the watchdog error of that specific channel has occurred." line.long 0x4C "DIRCMD,PSI5-S ECU to sensor direct command write register" hexmask.long.byte 0x4C 24.--31. 1. "DIRCMD_BYTE3,Byte3 of the Direct Command" newline hexmask.long.byte 0x4C 16.--23. 1. "DIRCMD_BYTE2,Byte2 of the Direct Command" newline hexmask.long.byte 0x4C 8.--15. 1. "DIRCMD_BYTE1,Byte1 of the Direct Command" newline hexmask.long.byte 0x4C 0.--7. 1. "DIRCMD_BYTE0,Byte0 of the Direct Command" group.long 0x16C++0x7 line.long 0x0 "MSGA_CH0,PSI5-S channel 0 message configuration register A" bitfld.long 0x0 8.--10. "F0_BYTE,Number of UART bytes comprising one UART packet. Applicable only to special messages having CID = 0 in their Message Header." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "TIME_STAMP_A_B_SEL,Whether the Timestamp corresponding to timestamp counter A or B is appended to messages targeted for Channel0." "0: Timestamp counter A,1: Timestamp counter B" newline bitfld.long 0x0 3. "TSBUF_CLR,This bit is used to clear the local timestamp buffer for the respective channel.Once cleared the buffer remains clear till the event to capture time stamp is triggered." "?,1: Timestamp buffer is cleared." newline bitfld.long 0x0 2. "TSBUF_EN,This bit controls whether timestamp buffer maintains a value '0' or is refreshed on a timestamp 'capture event'." "0: Timestamp buffer maintains value '0'.,1: Timestamp buffer responds to a 'capture event'.." line.long 0x4 "MSGB_CH0,PSI5-S channel 0 message configuration register B" hexmask.long.byte 0x4 0.--4. 1. "F0_PAYLOAD,Number of bits in payload region of the message (only for channels having CID as '0' in the message header). This channel is always asynchronous." group.long 0x178++0x3 line.long 0x0 "MBOX_SR_CH0,PSI5-S mailbox status register channel 0" bitfld.long 0x0 5. "F1_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when an unrecoverable message (with the CID = 0 and FID=1) is read from the MRU_BUF2." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 4. "F1_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX0 LOC1." "0: No overwrite of unread message in MBOX0 LOC1.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 3. "F1_READ,MBOX0 LOC1 is reserved for any unrecoverable message (XCRC_ERR has occurred or it is an 'illegal message'). It can correspond to any channel from 1 to 7." "0: No unread message in MBOX0.LOC1.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 2. "F0_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when a transceiver message (with the CID = 0 and FID=0) is read from the MRU_BUF2." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 1. "F0_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX0 LOC0." "0: No overwrite of unread message in MBOX0 LOC0.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 0. "F0_READ,MBOX0 LOC0 is reserved for a transceiver message." "0: No unread message in MBOX0 LOC0.,1: It indicates that the message that has just been.." group.long 0x190++0x7 line.long 0x0 "MSGA_CH1,PSI5-S channel message configuration register A" bitfld.long 0x0 31. "L_PC_EN,Selects whether the parity/CRC selection for a PSI5 message is to be controlled globally on a channel basis (through the G_PC bits) or locally on a per frame basis (through the L_PC[frame] bits)." "0: Parity/CRC option controlled globally through..,1: Parity/CRC option controlled locally through the.." newline bitfld.long 0x0 28.--30. "F5_BYTE,Number of bytes in UART packet for message corresponding to frame 5." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "L_PC5,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame5.,1: CRC selected for PSI5 message for frame5." newline bitfld.long 0x0 24.--26. "F4_BYTE,Number of bytes in UART packet for message corresponding to frame 4." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "L_PC4,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame4.,1: CRC selected for PSI5 message for frame4." newline bitfld.long 0x0 20.--22. "F3_BYTE,Number of bytes in UART packet for message corresponding to frame 3." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "L_PC3,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame3.,1: CRC selected for PSI5 message for frame3." newline bitfld.long 0x0 16.--18. "F2_BYTE,Number of bytes in UART packet for message corresponding to frame 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "L_PC2,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame2.,1: CRC selected for PSI5 message for frame2." newline bitfld.long 0x0 12.--14. "F1_BYTE,Number of bytes in UART packet for message corresponding to frame 1." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "L_PC1,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame1.,1: CRC selected for PSI5 message for frame1." newline bitfld.long 0x0 8.--10. "F0_BYTE,Number of bytes in UART packet for message corresponding to frame 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "L_PC0,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame0.,1: CRC selected for PSI5 message for frame0." newline bitfld.long 0x0 6. "MODE,This bit selects the operating modes between sync and async for the channel." "0: Synchronous.,1: Asynchronous." newline bitfld.long 0x0 5. "TIME_STAMP_A_B_SEL,Decides whether timestamp counter A or B value is captured in the local timestamp buffer whenever a 'capture event' occurs." "0: Timestamp counter A.,1: Timestamp counter B." newline bitfld.long 0x0 4. "TMSG_TCMD,Whether the timestamp is recorded when the message is received or when the channel command is moved from the TxFIFO to the UART Tx register (emulates a sync pulse)" "0: Timestamp recorded based on 'emulated' sync pulse.,1: Timestamp recorded based on message header byte.." newline bitfld.long 0x0 3. "TSBUF_CLR,This bit is used to clear the local timestamp buffer for the respective channel.Once cleared the buffer remains clear till the event to capture time stamp is triggered." "?,1: Timestamp buffer is cleared." newline bitfld.long 0x0 2. "TSBUF_EN,This bit controls whether timestamp buffer maintains a value '0' or is refreshed on a timestamp 'capture event'." "0: Timestamp buffer maintains value '0'.,1: Timestamp buffer responds to a 'capture event'.." newline bitfld.long 0x0 1. "G_PC,This bit globally selects the Parity or the CRC option for all the Frames of that particular channel" "0: Parity option selected globally for messages of..,1: CRC option selected globally for messages of all.." newline bitfld.long 0x0 0. "CH_EN,PSI5 Channel Enable. This bit decides if the IP takes the data belonging to the specific channel as 'legal' or 'illegal'." "0: Concerned PSI5 channel is disabled. Any data..,1: PSI5 message extraction for the definition of.." line.long 0x4 "MSGB_CH1,PSI5-S channel message configuration register B" hexmask.long.byte 0x4 25.--29. 1. "F5_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 5." newline hexmask.long.byte 0x4 20.--24. 1. "F4_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 4." newline hexmask.long.byte 0x4 15.--19. 1. "F3_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 3." newline hexmask.long.byte 0x4 10.--14. 1. "F2_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 2." newline hexmask.long.byte 0x4 5.--9. 1. "F1_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 1." newline hexmask.long.byte 0x4 0.--4. 1. "F0_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 0." group.long 0x19C++0x1F line.long 0x0 "MBOX_SR_CH1,PSI5-S mailbox status register channel" bitfld.long 0x0 17. "F5_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=5) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 16. "F5_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No overwrite of unread message in MBOX[n] LOC5.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 15. "F5_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No unread message in MBOX[n] LOC5.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 14. "F4_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=4) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 13. "F4_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No overwrite of unread message in MBOX[n] LOC4.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 12. "F4_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No unread message in MBOX[n] LOC4.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 11. "F3_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=3) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 10. "F3_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No overwrite of unread message in MBOX[n] LOC3.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 9. "F3_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No unread message in MBOX[n] LOC3.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 8. "F2_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=2) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 7. "F2_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No overwrite of unread message in MBOX[n] LOC2.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 6. "F2_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No unread message in MBOX[n] LOC2.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 5. "F1_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=1) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 4. "F1_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No overwrite of unread message in MBOX[n] LOC1.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 3. "F1_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No unread message in MBOX[n] LOC1.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 2. "F0_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=0) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 1. "F0_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No overwrite of unread message in MBOX[n] LOC0.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 0. "F0_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No unread message in MBOX[n] LOC0.,1: It indicates that the message that has just been.." line.long 0x4 "WD_CFGR_CH1,PSI5-S channel watchdog configuration register" bitfld.long 0x4 27. "WDRST,Resets watchdog counter for the channel" "0,1" newline bitfld.long 0x4 26. "WDCS,This selects either GTM or the module clock for watchdog counter of the channel. See Figure1629) Clock distribution in PSI5-S." "0: ipg_clk_ps_wd clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x4 25. "WDEN,The watchdog counter for each channel can be started stopped." "0: Watchdog counter stopped. It maintains its value.,1: Watchdog counter started." newline hexmask.long.tbyte 0x4 0.--23. 1. "WD_TO,This indicates the watchdog time out value. The watchdog generates an overrun error in case the watchdog is not refreshed before the watchdog counter reached the WD_TO value." line.long 0x8 "DDTRIG_OFFR_CH1,PSI5-S DDSR trigger offset register channel" hexmask.long.word 0x8 0.--15. 1. "DDTRIG_OFFR,These bits configure the delay between the 'shift trigger' of the various DDSRs across different channels. The value in this register governs the delay after which the specific DDSR is triggered once the Global Shift trigger.." line.long 0xC "DDTRIG_PERR_CH1,PSI5-S DDSR trigger period register channel" hexmask.long.word 0xC 0.--15. 1. "DDTRIG_PERR,These bits configure the 'shift trigger' period for the DDSR of that specific channel. The value in this register governs the period with which the data for the DDSR of that particular channel is shifted out." line.long 0x10 "E2SCR_CH1,PSI5-S ECU to sensor control register" hexmask.long.byte 0x10 26.--30. 1. "CMD,Bits for the ECU-to-sensor 'CMD' format. They refer to the command send to the UART Tx logic when a '1' is shifted from the DDSR register." newline hexmask.long.byte 0x10 20.--24. 1. "ACMD,Bits for the ECU-to-sensor 'ACMD' format. They refer to the command send to the UART Tx logic when a '0' is shifted from the DDSR register." newline bitfld.long 0x10 17. "CH_TRIG,This controls that the DDSR of the specific channel is triggered locally. This bit controls the shifting when PS_E2SCR_CHn[GL_TRIG_SEL] is 0." "0: Stop the DDSR from shifting the commands. The..,1: Start the 'shift trigger' of the DDSR." newline bitfld.long 0x10 16. "GL_TRIG_SEL,This bit controls whether the DDSR shift trigger is a global trigger or a local channel trigger." "0: The DDSR shift trigger is a local channel..,1: The DDSR shift trigger is a global trigger.." newline bitfld.long 0x10 15. "DEFAULT_SYNC,Decides the value to which the DDSR has to default to when PS_E2SSR_CHn[DDSR_RDY] == 1." "0,1" newline bitfld.long 0x10 14. "DDSR_SHIFT_SEL,DDSR Shift Selection" "0: The shift trigger is from internal DDSR counters..,1: The input signal gtm_trig directly acts as the.." newline bitfld.long 0x10 13. "DDSR_CLR,Used for rejecting the contents of the DDSR register." "0,1" newline bitfld.long 0x10 12. "DDSR_CLK_SEL,Selects which clock clocks shift logic of the DDSR for shifting the bits for command transmission." "0: ipg_clk_ps_ddtrig clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x10 11. "CMDTR_SW_CTRL,Once the command is ready for transmission (indicated by the setting PS_E2SSR_CHn[CMDPR_BZY] to 1) this bit decides when the actual transmission has to start:" "0: The actual transmission of command remains..,1: The command transmission starts once the.." newline bitfld.long 0x10 9. "SYNCHRO_OVF_IE,Synchro overflow interrupt enable" "0: No interrupt is generated when..,1: Generate an interrupt when.." newline bitfld.long 0x10 7. "CMDTR_NWRT_IE,Interrupt Enable for DDSR being attempted to be written when it is still not empty that is PS_E2SSR_CHn[DDSR_RDY] == 0 yet an attempt to write to DDSR is made." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 6. "CMDPR_BZY_IE,Interrupt Enable for DDSR getting updated with the internally processed complete command (with CRC stuff bits start bits getting appended)." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 5. "DDSR_RDY_IE,Interrupt Enable for DDSR getting empty and ready for receiving new command." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 0.--2. "CMD_TYPE," "0,1,2,3,4,5,6,7" line.long 0x14 "E2SSR_CH1,PSI5-S ECU to sensor status register" bitfld.long 0x14 9. "SYNCHRO_OVF,This bit gets set whenever due to any reason (like too less DDTRIG period) sync pulse of a channel comes before the previous sync pulse of the same channel has actually shifted its data." "0: No synch pulse overflow has occurred in the..,1: Synch Pulse overflow has occurred for the.." newline bitfld.long 0x14 7. "CMDTR_NWRT,Status of Command written to the DDSR:" "0: Command written to the DDSR has been accepted..,1: Command written to the DDSR is rejected as an.." newline bitfld.long 0x14 6. "CMDPR_BZY,Command Processing Busy Status" "0: DDSR is busy with command processing. For this..,1: DDSR is ready with the processed command.." newline bitfld.long 0x14 5. "DDSR_RDY,Status for DDSR getting empty and ready for receiving new command." "0: DDSR is not ready and is busy with either the..,1: DDSR is empty and ready for receiving a new.." line.long 0x18 "DDSR_H_CH1,PSI5-S channel1 ECU to sensor downstream data shift register high" hexmask.long.word 0x18 0.--10. 1. "DDSR_H,Upper High bits of the 43 bit complete DDSR register. These bits are updated by the hardware and software cannot write to these bits." line.long 0x1C "DDSR_L_CH1,PSI5-S channel1 ECU to sensor downstream data shift register low" hexmask.long.byte 0x1C 24.--31. 1. "DDSR_L1,8 bits of the DDSR_L that can only be read by the Application. These 8 bits are automatically updated by the hardware. They can be read by the software to check for the processed command after the command is written to the DDSR by the.." newline hexmask.long.tbyte 0x1C 0.--23. 1. "DDSR_L0,Lower 24 bits of the DDSR register that are written by the Application as well as updated by the hardware once the command processing is over." group.long 0x1CC++0x7 line.long 0x0 "MSGA_CH2,PSI5-S channel message configuration register A" bitfld.long 0x0 31. "L_PC_EN,Selects whether the parity/CRC selection for a PSI5 message is to be controlled globally on a channel basis (through the G_PC bits) or locally on a per frame basis (through the L_PC[frame] bits)." "0: Parity/CRC option controlled globally through..,1: Parity/CRC option controlled locally through the.." newline bitfld.long 0x0 28.--30. "F5_BYTE,Number of bytes in UART packet for message corresponding to frame 5." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "L_PC5,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame5.,1: CRC selected for PSI5 message for frame5." newline bitfld.long 0x0 24.--26. "F4_BYTE,Number of bytes in UART packet for message corresponding to frame 4." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "L_PC4,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame4.,1: CRC selected for PSI5 message for frame4." newline bitfld.long 0x0 20.--22. "F3_BYTE,Number of bytes in UART packet for message corresponding to frame 3." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "L_PC3,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame3.,1: CRC selected for PSI5 message for frame3." newline bitfld.long 0x0 16.--18. "F2_BYTE,Number of bytes in UART packet for message corresponding to frame 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "L_PC2,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame2.,1: CRC selected for PSI5 message for frame2." newline bitfld.long 0x0 12.--14. "F1_BYTE,Number of bytes in UART packet for message corresponding to frame 1." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "L_PC1,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame1.,1: CRC selected for PSI5 message for frame1." newline bitfld.long 0x0 8.--10. "F0_BYTE,Number of bytes in UART packet for message corresponding to frame 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "L_PC0,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame0.,1: CRC selected for PSI5 message for frame0." newline bitfld.long 0x0 6. "MODE,This bit selects the operating modes between sync and async for the channel." "0: Synchronous.,1: Asynchronous." newline bitfld.long 0x0 5. "TIME_STAMP_A_B_SEL,Decides whether timestamp counter A or B value is captured in the local timestamp buffer whenever a 'capture event' occurs." "0: Timestamp counter A.,1: Timestamp counter B." newline bitfld.long 0x0 4. "TMSG_TCMD,Whether the timestamp is recorded when the message is received or when the channel command is moved from the TxFIFO to the UART Tx register (emulates a sync pulse)" "0: Timestamp recorded based on 'emulated' sync pulse.,1: Timestamp recorded based on message header byte.." newline bitfld.long 0x0 3. "TSBUF_CLR,This bit is used to clear the local timestamp buffer for the respective channel.Once cleared the buffer remains clear till the event to capture time stamp is triggered." "?,1: Timestamp buffer is cleared." newline bitfld.long 0x0 2. "TSBUF_EN,This bit controls whether timestamp buffer maintains a value '0' or is refreshed on a timestamp 'capture event'." "0: Timestamp buffer maintains value '0'.,1: Timestamp buffer responds to a 'capture event'.." newline bitfld.long 0x0 1. "G_PC,This bit globally selects the Parity or the CRC option for all the Frames of that particular channel" "0: Parity option selected globally for messages of..,1: CRC option selected globally for messages of all.." newline bitfld.long 0x0 0. "CH_EN,PSI5 Channel Enable. This bit decides if the IP takes the data belonging to the specific channel as 'legal' or 'illegal'." "0: Concerned PSI5 channel is disabled. Any data..,1: PSI5 message extraction for the definition of.." line.long 0x4 "MSGB_CH2,PSI5-S channel message configuration register B" hexmask.long.byte 0x4 25.--29. 1. "F5_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 5." newline hexmask.long.byte 0x4 20.--24. 1. "F4_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 4." newline hexmask.long.byte 0x4 15.--19. 1. "F3_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 3." newline hexmask.long.byte 0x4 10.--14. 1. "F2_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 2." newline hexmask.long.byte 0x4 5.--9. 1. "F1_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 1." newline hexmask.long.byte 0x4 0.--4. 1. "F0_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 0." group.long 0x1D8++0x1F line.long 0x0 "MBOX_SR_CH2,PSI5-S mailbox status register channel" bitfld.long 0x0 17. "F5_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=5) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 16. "F5_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No overwrite of unread message in MBOX[n] LOC5.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 15. "F5_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No unread message in MBOX[n] LOC5.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 14. "F4_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=4) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 13. "F4_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No overwrite of unread message in MBOX[n] LOC4.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 12. "F4_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No unread message in MBOX[n] LOC4.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 11. "F3_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=3) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 10. "F3_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No overwrite of unread message in MBOX[n] LOC3.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 9. "F3_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No unread message in MBOX[n] LOC3.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 8. "F2_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=2) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 7. "F2_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No overwrite of unread message in MBOX[n] LOC2.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 6. "F2_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No unread message in MBOX[n] LOC2.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 5. "F1_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=1) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 4. "F1_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No overwrite of unread message in MBOX[n] LOC1.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 3. "F1_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No unread message in MBOX[n] LOC1.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 2. "F0_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=0) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 1. "F0_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No overwrite of unread message in MBOX[n] LOC0.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 0. "F0_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No unread message in MBOX[n] LOC0.,1: It indicates that the message that has just been.." line.long 0x4 "WD_CFGR_CH2,PSI5-S channel watchdog configuration register" bitfld.long 0x4 27. "WDRST,Resets watchdog counter for the channel" "0,1" newline bitfld.long 0x4 26. "WDCS,This selects either GTM or the module clock for watchdog counter of the channel. See Figure1629) Clock distribution in PSI5-S." "0: ipg_clk_ps_wd clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x4 25. "WDEN,The watchdog counter for each channel can be started stopped." "0: Watchdog counter stopped. It maintains its value.,1: Watchdog counter started." newline hexmask.long.tbyte 0x4 0.--23. 1. "WD_TO,This indicates the watchdog time out value. The watchdog generates an overrun error in case the watchdog is not refreshed before the watchdog counter reached the WD_TO value." line.long 0x8 "DDTRIG_OFFR_CH2,PSI5-S DDSR trigger offset register channel" hexmask.long.word 0x8 0.--15. 1. "DDTRIG_OFFR,These bits configure the delay between the 'shift trigger' of the various DDSRs across different channels. The value in this register governs the delay after which the specific DDSR is triggered once the Global Shift trigger.." line.long 0xC "DDTRIG_PERR_CH2,PSI5-S DDSR trigger period register channel" hexmask.long.word 0xC 0.--15. 1. "DDTRIG_PERR,These bits configure the 'shift trigger' period for the DDSR of that specific channel. The value in this register governs the period with which the data for the DDSR of that particular channel is shifted out." line.long 0x10 "E2SCR_CH2,PSI5-S ECU to sensor control register" hexmask.long.byte 0x10 26.--30. 1. "CMD,Bits for the ECU-to-sensor 'CMD' format. They refer to the command send to the UART Tx logic when a '1' is shifted from the DDSR register." newline hexmask.long.byte 0x10 20.--24. 1. "ACMD,Bits for the ECU-to-sensor 'ACMD' format. They refer to the command send to the UART Tx logic when a '0' is shifted from the DDSR register." newline bitfld.long 0x10 17. "CH_TRIG,This controls that the DDSR of the specific channel is triggered locally. This bit controls the shifting when PS_E2SCR_CHn[GL_TRIG_SEL] is 0." "0: Stop the DDSR from shifting the commands. The..,1: Start the 'shift trigger' of the DDSR." newline bitfld.long 0x10 16. "GL_TRIG_SEL,This bit controls whether the DDSR shift trigger is a global trigger or a local channel trigger." "0: The DDSR shift trigger is a local channel..,1: The DDSR shift trigger is a global trigger.." newline bitfld.long 0x10 15. "DEFAULT_SYNC,Decides the value to which the DDSR has to default to when PS_E2SSR_CHn[DDSR_RDY] == 1." "0,1" newline bitfld.long 0x10 14. "DDSR_SHIFT_SEL,DDSR Shift Selection" "0: The shift trigger is from internal DDSR counters..,1: The input signal gtm_trig directly acts as the.." newline bitfld.long 0x10 13. "DDSR_CLR,Used for rejecting the contents of the DDSR register." "0,1" newline bitfld.long 0x10 12. "DDSR_CLK_SEL,Selects which clock clocks shift logic of the DDSR for shifting the bits for command transmission." "0: ipg_clk_ps_ddtrig clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x10 11. "CMDTR_SW_CTRL,Once the command is ready for transmission (indicated by the setting PS_E2SSR_CHn[CMDPR_BZY] to 1) this bit decides when the actual transmission has to start:" "0: The actual transmission of command remains..,1: The command transmission starts once the.." newline bitfld.long 0x10 9. "SYNCHRO_OVF_IE,Synchro overflow interrupt enable" "0: No interrupt is generated when..,1: Generate an interrupt when.." newline bitfld.long 0x10 7. "CMDTR_NWRT_IE,Interrupt Enable for DDSR being attempted to be written when it is still not empty that is PS_E2SSR_CHn[DDSR_RDY] == 0 yet an attempt to write to DDSR is made." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 6. "CMDPR_BZY_IE,Interrupt Enable for DDSR getting updated with the internally processed complete command (with CRC stuff bits start bits getting appended)." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 5. "DDSR_RDY_IE,Interrupt Enable for DDSR getting empty and ready for receiving new command." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 0.--2. "CMD_TYPE," "0,1,2,3,4,5,6,7" line.long 0x14 "E2SSR_CH2,PSI5-S ECU to sensor status register" bitfld.long 0x14 9. "SYNCHRO_OVF,This bit gets set whenever due to any reason (like too less DDTRIG period) sync pulse of a channel comes before the previous sync pulse of the same channel has actually shifted its data." "0: No synch pulse overflow has occurred in the..,1: Synch Pulse overflow has occurred for the.." newline bitfld.long 0x14 7. "CMDTR_NWRT,Status of Command written to the DDSR:" "0: Command written to the DDSR has been accepted..,1: Command written to the DDSR is rejected as an.." newline bitfld.long 0x14 6. "CMDPR_BZY,Command Processing Busy Status" "0: DDSR is busy with command processing. For this..,1: DDSR is ready with the processed command.." newline bitfld.long 0x14 5. "DDSR_RDY,Status for DDSR getting empty and ready for receiving new command." "0: DDSR is not ready and is busy with either the..,1: DDSR is empty and ready for receiving a new.." line.long 0x18 "DDSR_H_CH2,PSI5-S channel1 ECU to sensor downstream data shift register high" hexmask.long.word 0x18 0.--10. 1. "DDSR_H,Upper High bits of the 43 bit complete DDSR register. These bits are updated by the hardware and software cannot write to these bits." line.long 0x1C "DDSR_L_CH2,PSI5-S channel1 ECU to sensor downstream data shift register low" hexmask.long.byte 0x1C 24.--31. 1. "DDSR_L1,8 bits of the DDSR_L that can only be read by the Application. These 8 bits are automatically updated by the hardware. They can be read by the software to check for the processed command after the command is written to the DDSR by the.." newline hexmask.long.tbyte 0x1C 0.--23. 1. "DDSR_L0,Lower 24 bits of the DDSR register that are written by the Application as well as updated by the hardware once the command processing is over." group.long 0x208++0x7 line.long 0x0 "MSGA_CH3,PSI5-S channel message configuration register A" bitfld.long 0x0 31. "L_PC_EN,Selects whether the parity/CRC selection for a PSI5 message is to be controlled globally on a channel basis (through the G_PC bits) or locally on a per frame basis (through the L_PC[frame] bits)." "0: Parity/CRC option controlled globally through..,1: Parity/CRC option controlled locally through the.." newline bitfld.long 0x0 28.--30. "F5_BYTE,Number of bytes in UART packet for message corresponding to frame 5." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "L_PC5,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame5.,1: CRC selected for PSI5 message for frame5." newline bitfld.long 0x0 24.--26. "F4_BYTE,Number of bytes in UART packet for message corresponding to frame 4." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "L_PC4,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame4.,1: CRC selected for PSI5 message for frame4." newline bitfld.long 0x0 20.--22. "F3_BYTE,Number of bytes in UART packet for message corresponding to frame 3." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "L_PC3,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame3.,1: CRC selected for PSI5 message for frame3." newline bitfld.long 0x0 16.--18. "F2_BYTE,Number of bytes in UART packet for message corresponding to frame 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "L_PC2,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame2.,1: CRC selected for PSI5 message for frame2." newline bitfld.long 0x0 12.--14. "F1_BYTE,Number of bytes in UART packet for message corresponding to frame 1." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "L_PC1,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame1.,1: CRC selected for PSI5 message for frame1." newline bitfld.long 0x0 8.--10. "F0_BYTE,Number of bytes in UART packet for message corresponding to frame 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "L_PC0,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame0.,1: CRC selected for PSI5 message for frame0." newline bitfld.long 0x0 6. "MODE,This bit selects the operating modes between sync and async for the channel." "0: Synchronous.,1: Asynchronous." newline bitfld.long 0x0 5. "TIME_STAMP_A_B_SEL,Decides whether timestamp counter A or B value is captured in the local timestamp buffer whenever a 'capture event' occurs." "0: Timestamp counter A.,1: Timestamp counter B." newline bitfld.long 0x0 4. "TMSG_TCMD,Whether the timestamp is recorded when the message is received or when the channel command is moved from the TxFIFO to the UART Tx register (emulates a sync pulse)" "0: Timestamp recorded based on 'emulated' sync pulse.,1: Timestamp recorded based on message header byte.." newline bitfld.long 0x0 3. "TSBUF_CLR,This bit is used to clear the local timestamp buffer for the respective channel.Once cleared the buffer remains clear till the event to capture time stamp is triggered." "?,1: Timestamp buffer is cleared." newline bitfld.long 0x0 2. "TSBUF_EN,This bit controls whether timestamp buffer maintains a value '0' or is refreshed on a timestamp 'capture event'." "0: Timestamp buffer maintains value '0'.,1: Timestamp buffer responds to a 'capture event'.." newline bitfld.long 0x0 1. "G_PC,This bit globally selects the Parity or the CRC option for all the Frames of that particular channel" "0: Parity option selected globally for messages of..,1: CRC option selected globally for messages of all.." newline bitfld.long 0x0 0. "CH_EN,PSI5 Channel Enable. This bit decides if the IP takes the data belonging to the specific channel as 'legal' or 'illegal'." "0: Concerned PSI5 channel is disabled. Any data..,1: PSI5 message extraction for the definition of.." line.long 0x4 "MSGB_CH3,PSI5-S channel message configuration register B" hexmask.long.byte 0x4 25.--29. 1. "F5_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 5." newline hexmask.long.byte 0x4 20.--24. 1. "F4_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 4." newline hexmask.long.byte 0x4 15.--19. 1. "F3_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 3." newline hexmask.long.byte 0x4 10.--14. 1. "F2_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 2." newline hexmask.long.byte 0x4 5.--9. 1. "F1_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 1." newline hexmask.long.byte 0x4 0.--4. 1. "F0_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 0." group.long 0x214++0x1F line.long 0x0 "MBOX_SR_CH3,PSI5-S mailbox status register channel" bitfld.long 0x0 17. "F5_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=5) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 16. "F5_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No overwrite of unread message in MBOX[n] LOC5.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 15. "F5_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No unread message in MBOX[n] LOC5.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 14. "F4_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=4) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 13. "F4_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No overwrite of unread message in MBOX[n] LOC4.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 12. "F4_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No unread message in MBOX[n] LOC4.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 11. "F3_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=3) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 10. "F3_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No overwrite of unread message in MBOX[n] LOC3.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 9. "F3_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No unread message in MBOX[n] LOC3.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 8. "F2_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=2) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 7. "F2_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No overwrite of unread message in MBOX[n] LOC2.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 6. "F2_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No unread message in MBOX[n] LOC2.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 5. "F1_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=1) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 4. "F1_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No overwrite of unread message in MBOX[n] LOC1.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 3. "F1_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No unread message in MBOX[n] LOC1.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 2. "F0_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=0) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 1. "F0_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No overwrite of unread message in MBOX[n] LOC0.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 0. "F0_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No unread message in MBOX[n] LOC0.,1: It indicates that the message that has just been.." line.long 0x4 "WD_CFGR_CH3,PSI5-S channel watchdog configuration register" bitfld.long 0x4 27. "WDRST,Resets watchdog counter for the channel" "0,1" newline bitfld.long 0x4 26. "WDCS,This selects either GTM or the module clock for watchdog counter of the channel. See Figure1629) Clock distribution in PSI5-S." "0: ipg_clk_ps_wd clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x4 25. "WDEN,The watchdog counter for each channel can be started stopped." "0: Watchdog counter stopped. It maintains its value.,1: Watchdog counter started." newline hexmask.long.tbyte 0x4 0.--23. 1. "WD_TO,This indicates the watchdog time out value. The watchdog generates an overrun error in case the watchdog is not refreshed before the watchdog counter reached the WD_TO value." line.long 0x8 "DDTRIG_OFFR_CH3,PSI5-S DDSR trigger offset register channel" hexmask.long.word 0x8 0.--15. 1. "DDTRIG_OFFR,These bits configure the delay between the 'shift trigger' of the various DDSRs across different channels. The value in this register governs the delay after which the specific DDSR is triggered once the Global Shift trigger.." line.long 0xC "DDTRIG_PERR_CH3,PSI5-S DDSR trigger period register channel" hexmask.long.word 0xC 0.--15. 1. "DDTRIG_PERR,These bits configure the 'shift trigger' period for the DDSR of that specific channel. The value in this register governs the period with which the data for the DDSR of that particular channel is shifted out." line.long 0x10 "E2SCR_CH3,PSI5-S ECU to sensor control register" hexmask.long.byte 0x10 26.--30. 1. "CMD,Bits for the ECU-to-sensor 'CMD' format. They refer to the command send to the UART Tx logic when a '1' is shifted from the DDSR register." newline hexmask.long.byte 0x10 20.--24. 1. "ACMD,Bits for the ECU-to-sensor 'ACMD' format. They refer to the command send to the UART Tx logic when a '0' is shifted from the DDSR register." newline bitfld.long 0x10 17. "CH_TRIG,This controls that the DDSR of the specific channel is triggered locally. This bit controls the shifting when PS_E2SCR_CHn[GL_TRIG_SEL] is 0." "0: Stop the DDSR from shifting the commands. The..,1: Start the 'shift trigger' of the DDSR." newline bitfld.long 0x10 16. "GL_TRIG_SEL,This bit controls whether the DDSR shift trigger is a global trigger or a local channel trigger." "0: The DDSR shift trigger is a local channel..,1: The DDSR shift trigger is a global trigger.." newline bitfld.long 0x10 15. "DEFAULT_SYNC,Decides the value to which the DDSR has to default to when PS_E2SSR_CHn[DDSR_RDY] == 1." "0,1" newline bitfld.long 0x10 14. "DDSR_SHIFT_SEL,DDSR Shift Selection" "0: The shift trigger is from internal DDSR counters..,1: The input signal gtm_trig directly acts as the.." newline bitfld.long 0x10 13. "DDSR_CLR,Used for rejecting the contents of the DDSR register." "0,1" newline bitfld.long 0x10 12. "DDSR_CLK_SEL,Selects which clock clocks shift logic of the DDSR for shifting the bits for command transmission." "0: ipg_clk_ps_ddtrig clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x10 11. "CMDTR_SW_CTRL,Once the command is ready for transmission (indicated by the setting PS_E2SSR_CHn[CMDPR_BZY] to 1) this bit decides when the actual transmission has to start:" "0: The actual transmission of command remains..,1: The command transmission starts once the.." newline bitfld.long 0x10 9. "SYNCHRO_OVF_IE,Synchro overflow interrupt enable" "0: No interrupt is generated when..,1: Generate an interrupt when.." newline bitfld.long 0x10 7. "CMDTR_NWRT_IE,Interrupt Enable for DDSR being attempted to be written when it is still not empty that is PS_E2SSR_CHn[DDSR_RDY] == 0 yet an attempt to write to DDSR is made." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 6. "CMDPR_BZY_IE,Interrupt Enable for DDSR getting updated with the internally processed complete command (with CRC stuff bits start bits getting appended)." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 5. "DDSR_RDY_IE,Interrupt Enable for DDSR getting empty and ready for receiving new command." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 0.--2. "CMD_TYPE," "0,1,2,3,4,5,6,7" line.long 0x14 "E2SSR_CH3,PSI5-S ECU to sensor status register" bitfld.long 0x14 9. "SYNCHRO_OVF,This bit gets set whenever due to any reason (like too less DDTRIG period) sync pulse of a channel comes before the previous sync pulse of the same channel has actually shifted its data." "0: No synch pulse overflow has occurred in the..,1: Synch Pulse overflow has occurred for the.." newline bitfld.long 0x14 7. "CMDTR_NWRT,Status of Command written to the DDSR:" "0: Command written to the DDSR has been accepted..,1: Command written to the DDSR is rejected as an.." newline bitfld.long 0x14 6. "CMDPR_BZY,Command Processing Busy Status" "0: DDSR is busy with command processing. For this..,1: DDSR is ready with the processed command.." newline bitfld.long 0x14 5. "DDSR_RDY,Status for DDSR getting empty and ready for receiving new command." "0: DDSR is not ready and is busy with either the..,1: DDSR is empty and ready for receiving a new.." line.long 0x18 "DDSR_H_CH3,PSI5-S channel1 ECU to sensor downstream data shift register high" hexmask.long.word 0x18 0.--10. 1. "DDSR_H,Upper High bits of the 43 bit complete DDSR register. These bits are updated by the hardware and software cannot write to these bits." line.long 0x1C "DDSR_L_CH3,PSI5-S channel1 ECU to sensor downstream data shift register low" hexmask.long.byte 0x1C 24.--31. 1. "DDSR_L1,8 bits of the DDSR_L that can only be read by the Application. These 8 bits are automatically updated by the hardware. They can be read by the software to check for the processed command after the command is written to the DDSR by the.." newline hexmask.long.tbyte 0x1C 0.--23. 1. "DDSR_L0,Lower 24 bits of the DDSR register that are written by the Application as well as updated by the hardware once the command processing is over." group.long 0x244++0x7 line.long 0x0 "MSGA_CH4,PSI5-S channel message configuration register A" bitfld.long 0x0 31. "L_PC_EN,Selects whether the parity/CRC selection for a PSI5 message is to be controlled globally on a channel basis (through the G_PC bits) or locally on a per frame basis (through the L_PC[frame] bits)." "0: Parity/CRC option controlled globally through..,1: Parity/CRC option controlled locally through the.." newline bitfld.long 0x0 28.--30. "F5_BYTE,Number of bytes in UART packet for message corresponding to frame 5." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "L_PC5,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame5.,1: CRC selected for PSI5 message for frame5." newline bitfld.long 0x0 24.--26. "F4_BYTE,Number of bytes in UART packet for message corresponding to frame 4." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "L_PC4,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame4.,1: CRC selected for PSI5 message for frame4." newline bitfld.long 0x0 20.--22. "F3_BYTE,Number of bytes in UART packet for message corresponding to frame 3." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "L_PC3,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame3.,1: CRC selected for PSI5 message for frame3." newline bitfld.long 0x0 16.--18. "F2_BYTE,Number of bytes in UART packet for message corresponding to frame 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "L_PC2,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame2.,1: CRC selected for PSI5 message for frame2." newline bitfld.long 0x0 12.--14. "F1_BYTE,Number of bytes in UART packet for message corresponding to frame 1." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "L_PC1,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame1.,1: CRC selected for PSI5 message for frame1." newline bitfld.long 0x0 8.--10. "F0_BYTE,Number of bytes in UART packet for message corresponding to frame 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "L_PC0,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame0.,1: CRC selected for PSI5 message for frame0." newline bitfld.long 0x0 6. "MODE,This bit selects the operating modes between sync and async for the channel." "0: Synchronous.,1: Asynchronous." newline bitfld.long 0x0 5. "TIME_STAMP_A_B_SEL,Decides whether timestamp counter A or B value is captured in the local timestamp buffer whenever a 'capture event' occurs." "0: Timestamp counter A.,1: Timestamp counter B." newline bitfld.long 0x0 4. "TMSG_TCMD,Whether the timestamp is recorded when the message is received or when the channel command is moved from the TxFIFO to the UART Tx register (emulates a sync pulse)" "0: Timestamp recorded based on 'emulated' sync pulse.,1: Timestamp recorded based on message header byte.." newline bitfld.long 0x0 3. "TSBUF_CLR,This bit is used to clear the local timestamp buffer for the respective channel.Once cleared the buffer remains clear till the event to capture time stamp is triggered." "?,1: Timestamp buffer is cleared." newline bitfld.long 0x0 2. "TSBUF_EN,This bit controls whether timestamp buffer maintains a value '0' or is refreshed on a timestamp 'capture event'." "0: Timestamp buffer maintains value '0'.,1: Timestamp buffer responds to a 'capture event'.." newline bitfld.long 0x0 1. "G_PC,This bit globally selects the Parity or the CRC option for all the Frames of that particular channel" "0: Parity option selected globally for messages of..,1: CRC option selected globally for messages of all.." newline bitfld.long 0x0 0. "CH_EN,PSI5 Channel Enable. This bit decides if the IP takes the data belonging to the specific channel as 'legal' or 'illegal'." "0: Concerned PSI5 channel is disabled. Any data..,1: PSI5 message extraction for the definition of.." line.long 0x4 "MSGB_CH4,PSI5-S channel message configuration register B" hexmask.long.byte 0x4 25.--29. 1. "F5_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 5." newline hexmask.long.byte 0x4 20.--24. 1. "F4_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 4." newline hexmask.long.byte 0x4 15.--19. 1. "F3_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 3." newline hexmask.long.byte 0x4 10.--14. 1. "F2_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 2." newline hexmask.long.byte 0x4 5.--9. 1. "F1_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 1." newline hexmask.long.byte 0x4 0.--4. 1. "F0_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 0." group.long 0x250++0x1F line.long 0x0 "MBOX_SR_CH4,PSI5-S mailbox status register channel" bitfld.long 0x0 17. "F5_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=5) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 16. "F5_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No overwrite of unread message in MBOX[n] LOC5.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 15. "F5_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No unread message in MBOX[n] LOC5.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 14. "F4_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=4) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 13. "F4_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No overwrite of unread message in MBOX[n] LOC4.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 12. "F4_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No unread message in MBOX[n] LOC4.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 11. "F3_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=3) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 10. "F3_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No overwrite of unread message in MBOX[n] LOC3.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 9. "F3_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No unread message in MBOX[n] LOC3.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 8. "F2_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=2) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 7. "F2_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No overwrite of unread message in MBOX[n] LOC2.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 6. "F2_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No unread message in MBOX[n] LOC2.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 5. "F1_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=1) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 4. "F1_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No overwrite of unread message in MBOX[n] LOC1.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 3. "F1_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No unread message in MBOX[n] LOC1.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 2. "F0_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=0) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 1. "F0_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No overwrite of unread message in MBOX[n] LOC0.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 0. "F0_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No unread message in MBOX[n] LOC0.,1: It indicates that the message that has just been.." line.long 0x4 "WD_CFGR_CH4,PSI5-S channel watchdog configuration register" bitfld.long 0x4 27. "WDRST,Resets watchdog counter for the channel" "0,1" newline bitfld.long 0x4 26. "WDCS,This selects either GTM or the module clock for watchdog counter of the channel. See Figure1629) Clock distribution in PSI5-S." "0: ipg_clk_ps_wd clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x4 25. "WDEN,The watchdog counter for each channel can be started stopped." "0: Watchdog counter stopped. It maintains its value.,1: Watchdog counter started." newline hexmask.long.tbyte 0x4 0.--23. 1. "WD_TO,This indicates the watchdog time out value. The watchdog generates an overrun error in case the watchdog is not refreshed before the watchdog counter reached the WD_TO value." line.long 0x8 "DDTRIG_OFFR_CH4,PSI5-S DDSR trigger offset register channel" hexmask.long.word 0x8 0.--15. 1. "DDTRIG_OFFR,These bits configure the delay between the 'shift trigger' of the various DDSRs across different channels. The value in this register governs the delay after which the specific DDSR is triggered once the Global Shift trigger.." line.long 0xC "DDTRIG_PERR_CH4,PSI5-S DDSR trigger period register channel" hexmask.long.word 0xC 0.--15. 1. "DDTRIG_PERR,These bits configure the 'shift trigger' period for the DDSR of that specific channel. The value in this register governs the period with which the data for the DDSR of that particular channel is shifted out." line.long 0x10 "E2SCR_CH4,PSI5-S ECU to sensor control register" hexmask.long.byte 0x10 26.--30. 1. "CMD,Bits for the ECU-to-sensor 'CMD' format. They refer to the command send to the UART Tx logic when a '1' is shifted from the DDSR register." newline hexmask.long.byte 0x10 20.--24. 1. "ACMD,Bits for the ECU-to-sensor 'ACMD' format. They refer to the command send to the UART Tx logic when a '0' is shifted from the DDSR register." newline bitfld.long 0x10 17. "CH_TRIG,This controls that the DDSR of the specific channel is triggered locally. This bit controls the shifting when PS_E2SCR_CHn[GL_TRIG_SEL] is 0." "0: Stop the DDSR from shifting the commands. The..,1: Start the 'shift trigger' of the DDSR." newline bitfld.long 0x10 16. "GL_TRIG_SEL,This bit controls whether the DDSR shift trigger is a global trigger or a local channel trigger." "0: The DDSR shift trigger is a local channel..,1: The DDSR shift trigger is a global trigger.." newline bitfld.long 0x10 15. "DEFAULT_SYNC,Decides the value to which the DDSR has to default to when PS_E2SSR_CHn[DDSR_RDY] == 1." "0,1" newline bitfld.long 0x10 14. "DDSR_SHIFT_SEL,DDSR Shift Selection" "0: The shift trigger is from internal DDSR counters..,1: The input signal gtm_trig directly acts as the.." newline bitfld.long 0x10 13. "DDSR_CLR,Used for rejecting the contents of the DDSR register." "0,1" newline bitfld.long 0x10 12. "DDSR_CLK_SEL,Selects which clock clocks shift logic of the DDSR for shifting the bits for command transmission." "0: ipg_clk_ps_ddtrig clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x10 11. "CMDTR_SW_CTRL,Once the command is ready for transmission (indicated by the setting PS_E2SSR_CHn[CMDPR_BZY] to 1) this bit decides when the actual transmission has to start:" "0: The actual transmission of command remains..,1: The command transmission starts once the.." newline bitfld.long 0x10 9. "SYNCHRO_OVF_IE,Synchro overflow interrupt enable" "0: No interrupt is generated when..,1: Generate an interrupt when.." newline bitfld.long 0x10 7. "CMDTR_NWRT_IE,Interrupt Enable for DDSR being attempted to be written when it is still not empty that is PS_E2SSR_CHn[DDSR_RDY] == 0 yet an attempt to write to DDSR is made." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 6. "CMDPR_BZY_IE,Interrupt Enable for DDSR getting updated with the internally processed complete command (with CRC stuff bits start bits getting appended)." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 5. "DDSR_RDY_IE,Interrupt Enable for DDSR getting empty and ready for receiving new command." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 0.--2. "CMD_TYPE," "0,1,2,3,4,5,6,7" line.long 0x14 "E2SSR_CH4,PSI5-S ECU to sensor status register" bitfld.long 0x14 9. "SYNCHRO_OVF,This bit gets set whenever due to any reason (like too less DDTRIG period) sync pulse of a channel comes before the previous sync pulse of the same channel has actually shifted its data." "0: No synch pulse overflow has occurred in the..,1: Synch Pulse overflow has occurred for the.." newline bitfld.long 0x14 7. "CMDTR_NWRT,Status of Command written to the DDSR:" "0: Command written to the DDSR has been accepted..,1: Command written to the DDSR is rejected as an.." newline bitfld.long 0x14 6. "CMDPR_BZY,Command Processing Busy Status" "0: DDSR is busy with command processing. For this..,1: DDSR is ready with the processed command.." newline bitfld.long 0x14 5. "DDSR_RDY,Status for DDSR getting empty and ready for receiving new command." "0: DDSR is not ready and is busy with either the..,1: DDSR is empty and ready for receiving a new.." line.long 0x18 "DDSR_H_CH4,PSI5-S channel1 ECU to sensor downstream data shift register high" hexmask.long.word 0x18 0.--10. 1. "DDSR_H,Upper High bits of the 43 bit complete DDSR register. These bits are updated by the hardware and software cannot write to these bits." line.long 0x1C "DDSR_L_CH4,PSI5-S channel1 ECU to sensor downstream data shift register low" hexmask.long.byte 0x1C 24.--31. 1. "DDSR_L1,8 bits of the DDSR_L that can only be read by the Application. These 8 bits are automatically updated by the hardware. They can be read by the software to check for the processed command after the command is written to the DDSR by the.." newline hexmask.long.tbyte 0x1C 0.--23. 1. "DDSR_L0,Lower 24 bits of the DDSR register that are written by the Application as well as updated by the hardware once the command processing is over." group.long 0x280++0x7 line.long 0x0 "MSGA_CH5,PSI5-S channel message configuration register A" bitfld.long 0x0 31. "L_PC_EN,Selects whether the parity/CRC selection for a PSI5 message is to be controlled globally on a channel basis (through the G_PC bits) or locally on a per frame basis (through the L_PC[frame] bits)." "0: Parity/CRC option controlled globally through..,1: Parity/CRC option controlled locally through the.." newline bitfld.long 0x0 28.--30. "F5_BYTE,Number of bytes in UART packet for message corresponding to frame 5." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "L_PC5,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame5.,1: CRC selected for PSI5 message for frame5." newline bitfld.long 0x0 24.--26. "F4_BYTE,Number of bytes in UART packet for message corresponding to frame 4." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "L_PC4,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame4.,1: CRC selected for PSI5 message for frame4." newline bitfld.long 0x0 20.--22. "F3_BYTE,Number of bytes in UART packet for message corresponding to frame 3." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "L_PC3,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame3.,1: CRC selected for PSI5 message for frame3." newline bitfld.long 0x0 16.--18. "F2_BYTE,Number of bytes in UART packet for message corresponding to frame 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "L_PC2,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame2.,1: CRC selected for PSI5 message for frame2." newline bitfld.long 0x0 12.--14. "F1_BYTE,Number of bytes in UART packet for message corresponding to frame 1." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "L_PC1,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame1.,1: CRC selected for PSI5 message for frame1." newline bitfld.long 0x0 8.--10. "F0_BYTE,Number of bytes in UART packet for message corresponding to frame 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "L_PC0,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame0.,1: CRC selected for PSI5 message for frame0." newline bitfld.long 0x0 6. "MODE,This bit selects the operating modes between sync and async for the channel." "0: Synchronous.,1: Asynchronous." newline bitfld.long 0x0 5. "TIME_STAMP_A_B_SEL,Decides whether timestamp counter A or B value is captured in the local timestamp buffer whenever a 'capture event' occurs." "0: Timestamp counter A.,1: Timestamp counter B." newline bitfld.long 0x0 4. "TMSG_TCMD,Whether the timestamp is recorded when the message is received or when the channel command is moved from the TxFIFO to the UART Tx register (emulates a sync pulse)" "0: Timestamp recorded based on 'emulated' sync pulse.,1: Timestamp recorded based on message header byte.." newline bitfld.long 0x0 3. "TSBUF_CLR,This bit is used to clear the local timestamp buffer for the respective channel.Once cleared the buffer remains clear till the event to capture time stamp is triggered." "?,1: Timestamp buffer is cleared." newline bitfld.long 0x0 2. "TSBUF_EN,This bit controls whether timestamp buffer maintains a value '0' or is refreshed on a timestamp 'capture event'." "0: Timestamp buffer maintains value '0'.,1: Timestamp buffer responds to a 'capture event'.." newline bitfld.long 0x0 1. "G_PC,This bit globally selects the Parity or the CRC option for all the Frames of that particular channel" "0: Parity option selected globally for messages of..,1: CRC option selected globally for messages of all.." newline bitfld.long 0x0 0. "CH_EN,PSI5 Channel Enable. This bit decides if the IP takes the data belonging to the specific channel as 'legal' or 'illegal'." "0: Concerned PSI5 channel is disabled. Any data..,1: PSI5 message extraction for the definition of.." line.long 0x4 "MSGB_CH5,PSI5-S channel message configuration register B" hexmask.long.byte 0x4 25.--29. 1. "F5_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 5." newline hexmask.long.byte 0x4 20.--24. 1. "F4_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 4." newline hexmask.long.byte 0x4 15.--19. 1. "F3_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 3." newline hexmask.long.byte 0x4 10.--14. 1. "F2_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 2." newline hexmask.long.byte 0x4 5.--9. 1. "F1_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 1." newline hexmask.long.byte 0x4 0.--4. 1. "F0_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 0." group.long 0x28C++0x1F line.long 0x0 "MBOX_SR_CH5,PSI5-S mailbox status register channel" bitfld.long 0x0 17. "F5_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=5) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 16. "F5_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No overwrite of unread message in MBOX[n] LOC5.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 15. "F5_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No unread message in MBOX[n] LOC5.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 14. "F4_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=4) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 13. "F4_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No overwrite of unread message in MBOX[n] LOC4.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 12. "F4_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No unread message in MBOX[n] LOC4.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 11. "F3_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=3) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 10. "F3_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No overwrite of unread message in MBOX[n] LOC3.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 9. "F3_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No unread message in MBOX[n] LOC3.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 8. "F2_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=2) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 7. "F2_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No overwrite of unread message in MBOX[n] LOC2.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 6. "F2_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No unread message in MBOX[n] LOC2.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 5. "F1_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=1) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 4. "F1_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No overwrite of unread message in MBOX[n] LOC1.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 3. "F1_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No unread message in MBOX[n] LOC1.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 2. "F0_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=0) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 1. "F0_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No overwrite of unread message in MBOX[n] LOC0.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 0. "F0_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No unread message in MBOX[n] LOC0.,1: It indicates that the message that has just been.." line.long 0x4 "WD_CFGR_CH5,PSI5-S channel watchdog configuration register" bitfld.long 0x4 27. "WDRST,Resets watchdog counter for the channel" "0,1" newline bitfld.long 0x4 26. "WDCS,This selects either GTM or the module clock for watchdog counter of the channel. See Figure1629) Clock distribution in PSI5-S." "0: ipg_clk_ps_wd clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x4 25. "WDEN,The watchdog counter for each channel can be started stopped." "0: Watchdog counter stopped. It maintains its value.,1: Watchdog counter started." newline hexmask.long.tbyte 0x4 0.--23. 1. "WD_TO,This indicates the watchdog time out value. The watchdog generates an overrun error in case the watchdog is not refreshed before the watchdog counter reached the WD_TO value." line.long 0x8 "DDTRIG_OFFR_CH5,PSI5-S DDSR trigger offset register channel" hexmask.long.word 0x8 0.--15. 1. "DDTRIG_OFFR,These bits configure the delay between the 'shift trigger' of the various DDSRs across different channels. The value in this register governs the delay after which the specific DDSR is triggered once the Global Shift trigger.." line.long 0xC "DDTRIG_PERR_CH5,PSI5-S DDSR trigger period register channel" hexmask.long.word 0xC 0.--15. 1. "DDTRIG_PERR,These bits configure the 'shift trigger' period for the DDSR of that specific channel. The value in this register governs the period with which the data for the DDSR of that particular channel is shifted out." line.long 0x10 "E2SCR_CH5,PSI5-S ECU to sensor control register" hexmask.long.byte 0x10 26.--30. 1. "CMD,Bits for the ECU-to-sensor 'CMD' format. They refer to the command send to the UART Tx logic when a '1' is shifted from the DDSR register." newline hexmask.long.byte 0x10 20.--24. 1. "ACMD,Bits for the ECU-to-sensor 'ACMD' format. They refer to the command send to the UART Tx logic when a '0' is shifted from the DDSR register." newline bitfld.long 0x10 17. "CH_TRIG,This controls that the DDSR of the specific channel is triggered locally. This bit controls the shifting when PS_E2SCR_CHn[GL_TRIG_SEL] is 0." "0: Stop the DDSR from shifting the commands. The..,1: Start the 'shift trigger' of the DDSR." newline bitfld.long 0x10 16. "GL_TRIG_SEL,This bit controls whether the DDSR shift trigger is a global trigger or a local channel trigger." "0: The DDSR shift trigger is a local channel..,1: The DDSR shift trigger is a global trigger.." newline bitfld.long 0x10 15. "DEFAULT_SYNC,Decides the value to which the DDSR has to default to when PS_E2SSR_CHn[DDSR_RDY] == 1." "0,1" newline bitfld.long 0x10 14. "DDSR_SHIFT_SEL,DDSR Shift Selection" "0: The shift trigger is from internal DDSR counters..,1: The input signal gtm_trig directly acts as the.." newline bitfld.long 0x10 13. "DDSR_CLR,Used for rejecting the contents of the DDSR register." "0,1" newline bitfld.long 0x10 12. "DDSR_CLK_SEL,Selects which clock clocks shift logic of the DDSR for shifting the bits for command transmission." "0: ipg_clk_ps_ddtrig clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x10 11. "CMDTR_SW_CTRL,Once the command is ready for transmission (indicated by the setting PS_E2SSR_CHn[CMDPR_BZY] to 1) this bit decides when the actual transmission has to start:" "0: The actual transmission of command remains..,1: The command transmission starts once the.." newline bitfld.long 0x10 9. "SYNCHRO_OVF_IE,Synchro overflow interrupt enable" "0: No interrupt is generated when..,1: Generate an interrupt when.." newline bitfld.long 0x10 7. "CMDTR_NWRT_IE,Interrupt Enable for DDSR being attempted to be written when it is still not empty that is PS_E2SSR_CHn[DDSR_RDY] == 0 yet an attempt to write to DDSR is made." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 6. "CMDPR_BZY_IE,Interrupt Enable for DDSR getting updated with the internally processed complete command (with CRC stuff bits start bits getting appended)." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 5. "DDSR_RDY_IE,Interrupt Enable for DDSR getting empty and ready for receiving new command." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 0.--2. "CMD_TYPE," "0,1,2,3,4,5,6,7" line.long 0x14 "E2SSR_CH5,PSI5-S ECU to sensor status register" bitfld.long 0x14 9. "SYNCHRO_OVF,This bit gets set whenever due to any reason (like too less DDTRIG period) sync pulse of a channel comes before the previous sync pulse of the same channel has actually shifted its data." "0: No synch pulse overflow has occurred in the..,1: Synch Pulse overflow has occurred for the.." newline bitfld.long 0x14 7. "CMDTR_NWRT,Status of Command written to the DDSR:" "0: Command written to the DDSR has been accepted..,1: Command written to the DDSR is rejected as an.." newline bitfld.long 0x14 6. "CMDPR_BZY,Command Processing Busy Status" "0: DDSR is busy with command processing. For this..,1: DDSR is ready with the processed command.." newline bitfld.long 0x14 5. "DDSR_RDY,Status for DDSR getting empty and ready for receiving new command." "0: DDSR is not ready and is busy with either the..,1: DDSR is empty and ready for receiving a new.." line.long 0x18 "DDSR_H_CH5,PSI5-S channel1 ECU to sensor downstream data shift register high" hexmask.long.word 0x18 0.--10. 1. "DDSR_H,Upper High bits of the 43 bit complete DDSR register. These bits are updated by the hardware and software cannot write to these bits." line.long 0x1C "DDSR_L_CH5,PSI5-S channel1 ECU to sensor downstream data shift register low" hexmask.long.byte 0x1C 24.--31. 1. "DDSR_L1,8 bits of the DDSR_L that can only be read by the Application. These 8 bits are automatically updated by the hardware. They can be read by the software to check for the processed command after the command is written to the DDSR by the.." newline hexmask.long.tbyte 0x1C 0.--23. 1. "DDSR_L0,Lower 24 bits of the DDSR register that are written by the Application as well as updated by the hardware once the command processing is over." group.long 0x2BC++0x7 line.long 0x0 "MSGA_CH6,PSI5-S channel message configuration register A" bitfld.long 0x0 31. "L_PC_EN,Selects whether the parity/CRC selection for a PSI5 message is to be controlled globally on a channel basis (through the G_PC bits) or locally on a per frame basis (through the L_PC[frame] bits)." "0: Parity/CRC option controlled globally through..,1: Parity/CRC option controlled locally through the.." newline bitfld.long 0x0 28.--30. "F5_BYTE,Number of bytes in UART packet for message corresponding to frame 5." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "L_PC5,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame5.,1: CRC selected for PSI5 message for frame5." newline bitfld.long 0x0 24.--26. "F4_BYTE,Number of bytes in UART packet for message corresponding to frame 4." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "L_PC4,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame4.,1: CRC selected for PSI5 message for frame4." newline bitfld.long 0x0 20.--22. "F3_BYTE,Number of bytes in UART packet for message corresponding to frame 3." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "L_PC3,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame3.,1: CRC selected for PSI5 message for frame3." newline bitfld.long 0x0 16.--18. "F2_BYTE,Number of bytes in UART packet for message corresponding to frame 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "L_PC2,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame2.,1: CRC selected for PSI5 message for frame2." newline bitfld.long 0x0 12.--14. "F1_BYTE,Number of bytes in UART packet for message corresponding to frame 1." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "L_PC1,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame1.,1: CRC selected for PSI5 message for frame1." newline bitfld.long 0x0 8.--10. "F0_BYTE,Number of bytes in UART packet for message corresponding to frame 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "L_PC0,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame0.,1: CRC selected for PSI5 message for frame0." newline bitfld.long 0x0 6. "MODE,This bit selects the operating modes between sync and async for the channel." "0: Synchronous.,1: Asynchronous." newline bitfld.long 0x0 5. "TIME_STAMP_A_B_SEL,Decides whether timestamp counter A or B value is captured in the local timestamp buffer whenever a 'capture event' occurs." "0: Timestamp counter A.,1: Timestamp counter B." newline bitfld.long 0x0 4. "TMSG_TCMD,Whether the timestamp is recorded when the message is received or when the channel command is moved from the TxFIFO to the UART Tx register (emulates a sync pulse)" "0: Timestamp recorded based on 'emulated' sync pulse.,1: Timestamp recorded based on message header byte.." newline bitfld.long 0x0 3. "TSBUF_CLR,This bit is used to clear the local timestamp buffer for the respective channel.Once cleared the buffer remains clear till the event to capture time stamp is triggered." "?,1: Timestamp buffer is cleared." newline bitfld.long 0x0 2. "TSBUF_EN,This bit controls whether timestamp buffer maintains a value '0' or is refreshed on a timestamp 'capture event'." "0: Timestamp buffer maintains value '0'.,1: Timestamp buffer responds to a 'capture event'.." newline bitfld.long 0x0 1. "G_PC,This bit globally selects the Parity or the CRC option for all the Frames of that particular channel" "0: Parity option selected globally for messages of..,1: CRC option selected globally for messages of all.." newline bitfld.long 0x0 0. "CH_EN,PSI5 Channel Enable. This bit decides if the IP takes the data belonging to the specific channel as 'legal' or 'illegal'." "0: Concerned PSI5 channel is disabled. Any data..,1: PSI5 message extraction for the definition of.." line.long 0x4 "MSGB_CH6,PSI5-S channel message configuration register B" hexmask.long.byte 0x4 25.--29. 1. "F5_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 5." newline hexmask.long.byte 0x4 20.--24. 1. "F4_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 4." newline hexmask.long.byte 0x4 15.--19. 1. "F3_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 3." newline hexmask.long.byte 0x4 10.--14. 1. "F2_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 2." newline hexmask.long.byte 0x4 5.--9. 1. "F1_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 1." newline hexmask.long.byte 0x4 0.--4. 1. "F0_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 0." group.long 0x2C8++0x1F line.long 0x0 "MBOX_SR_CH6,PSI5-S mailbox status register channel" bitfld.long 0x0 17. "F5_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=5) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 16. "F5_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No overwrite of unread message in MBOX[n] LOC5.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 15. "F5_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No unread message in MBOX[n] LOC5.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 14. "F4_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=4) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 13. "F4_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No overwrite of unread message in MBOX[n] LOC4.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 12. "F4_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No unread message in MBOX[n] LOC4.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 11. "F3_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=3) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 10. "F3_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No overwrite of unread message in MBOX[n] LOC3.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 9. "F3_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No unread message in MBOX[n] LOC3.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 8. "F2_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=2) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 7. "F2_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No overwrite of unread message in MBOX[n] LOC2.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 6. "F2_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No unread message in MBOX[n] LOC2.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 5. "F1_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=1) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 4. "F1_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No overwrite of unread message in MBOX[n] LOC1.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 3. "F1_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No unread message in MBOX[n] LOC1.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 2. "F0_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=0) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 1. "F0_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No overwrite of unread message in MBOX[n] LOC0.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 0. "F0_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No unread message in MBOX[n] LOC0.,1: It indicates that the message that has just been.." line.long 0x4 "WD_CFGR_CH6,PSI5-S channel watchdog configuration register" bitfld.long 0x4 27. "WDRST,Resets watchdog counter for the channel" "0,1" newline bitfld.long 0x4 26. "WDCS,This selects either GTM or the module clock for watchdog counter of the channel. See Figure1629) Clock distribution in PSI5-S." "0: ipg_clk_ps_wd clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x4 25. "WDEN,The watchdog counter for each channel can be started stopped." "0: Watchdog counter stopped. It maintains its value.,1: Watchdog counter started." newline hexmask.long.tbyte 0x4 0.--23. 1. "WD_TO,This indicates the watchdog time out value. The watchdog generates an overrun error in case the watchdog is not refreshed before the watchdog counter reached the WD_TO value." line.long 0x8 "DDTRIG_OFFR_CH6,PSI5-S DDSR trigger offset register channel" hexmask.long.word 0x8 0.--15. 1. "DDTRIG_OFFR,These bits configure the delay between the 'shift trigger' of the various DDSRs across different channels. The value in this register governs the delay after which the specific DDSR is triggered once the Global Shift trigger.." line.long 0xC "DDTRIG_PERR_CH6,PSI5-S DDSR trigger period register channel" hexmask.long.word 0xC 0.--15. 1. "DDTRIG_PERR,These bits configure the 'shift trigger' period for the DDSR of that specific channel. The value in this register governs the period with which the data for the DDSR of that particular channel is shifted out." line.long 0x10 "E2SCR_CH6,PSI5-S ECU to sensor control register" hexmask.long.byte 0x10 26.--30. 1. "CMD,Bits for the ECU-to-sensor 'CMD' format. They refer to the command send to the UART Tx logic when a '1' is shifted from the DDSR register." newline hexmask.long.byte 0x10 20.--24. 1. "ACMD,Bits for the ECU-to-sensor 'ACMD' format. They refer to the command send to the UART Tx logic when a '0' is shifted from the DDSR register." newline bitfld.long 0x10 17. "CH_TRIG,This controls that the DDSR of the specific channel is triggered locally. This bit controls the shifting when PS_E2SCR_CHn[GL_TRIG_SEL] is 0." "0: Stop the DDSR from shifting the commands. The..,1: Start the 'shift trigger' of the DDSR." newline bitfld.long 0x10 16. "GL_TRIG_SEL,This bit controls whether the DDSR shift trigger is a global trigger or a local channel trigger." "0: The DDSR shift trigger is a local channel..,1: The DDSR shift trigger is a global trigger.." newline bitfld.long 0x10 15. "DEFAULT_SYNC,Decides the value to which the DDSR has to default to when PS_E2SSR_CHn[DDSR_RDY] == 1." "0,1" newline bitfld.long 0x10 14. "DDSR_SHIFT_SEL,DDSR Shift Selection" "0: The shift trigger is from internal DDSR counters..,1: The input signal gtm_trig directly acts as the.." newline bitfld.long 0x10 13. "DDSR_CLR,Used for rejecting the contents of the DDSR register." "0,1" newline bitfld.long 0x10 12. "DDSR_CLK_SEL,Selects which clock clocks shift logic of the DDSR for shifting the bits for command transmission." "0: ipg_clk_ps_ddtrig clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x10 11. "CMDTR_SW_CTRL,Once the command is ready for transmission (indicated by the setting PS_E2SSR_CHn[CMDPR_BZY] to 1) this bit decides when the actual transmission has to start:" "0: The actual transmission of command remains..,1: The command transmission starts once the.." newline bitfld.long 0x10 9. "SYNCHRO_OVF_IE,Synchro overflow interrupt enable" "0: No interrupt is generated when..,1: Generate an interrupt when.." newline bitfld.long 0x10 7. "CMDTR_NWRT_IE,Interrupt Enable for DDSR being attempted to be written when it is still not empty that is PS_E2SSR_CHn[DDSR_RDY] == 0 yet an attempt to write to DDSR is made." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 6. "CMDPR_BZY_IE,Interrupt Enable for DDSR getting updated with the internally processed complete command (with CRC stuff bits start bits getting appended)." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 5. "DDSR_RDY_IE,Interrupt Enable for DDSR getting empty and ready for receiving new command." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 0.--2. "CMD_TYPE," "0,1,2,3,4,5,6,7" line.long 0x14 "E2SSR_CH6,PSI5-S ECU to sensor status register" bitfld.long 0x14 9. "SYNCHRO_OVF,This bit gets set whenever due to any reason (like too less DDTRIG period) sync pulse of a channel comes before the previous sync pulse of the same channel has actually shifted its data." "0: No synch pulse overflow has occurred in the..,1: Synch Pulse overflow has occurred for the.." newline bitfld.long 0x14 7. "CMDTR_NWRT,Status of Command written to the DDSR:" "0: Command written to the DDSR has been accepted..,1: Command written to the DDSR is rejected as an.." newline bitfld.long 0x14 6. "CMDPR_BZY,Command Processing Busy Status" "0: DDSR is busy with command processing. For this..,1: DDSR is ready with the processed command.." newline bitfld.long 0x14 5. "DDSR_RDY,Status for DDSR getting empty and ready for receiving new command." "0: DDSR is not ready and is busy with either the..,1: DDSR is empty and ready for receiving a new.." line.long 0x18 "DDSR_H_CH6,PSI5-S channel1 ECU to sensor downstream data shift register high" hexmask.long.word 0x18 0.--10. 1. "DDSR_H,Upper High bits of the 43 bit complete DDSR register. These bits are updated by the hardware and software cannot write to these bits." line.long 0x1C "DDSR_L_CH6,PSI5-S channel1 ECU to sensor downstream data shift register low" hexmask.long.byte 0x1C 24.--31. 1. "DDSR_L1,8 bits of the DDSR_L that can only be read by the Application. These 8 bits are automatically updated by the hardware. They can be read by the software to check for the processed command after the command is written to the DDSR by the.." newline hexmask.long.tbyte 0x1C 0.--23. 1. "DDSR_L0,Lower 24 bits of the DDSR register that are written by the Application as well as updated by the hardware once the command processing is over." group.long 0x2F8++0x7 line.long 0x0 "MSGA_CH7,PSI5-S channel message configuration register A" bitfld.long 0x0 31. "L_PC_EN,Selects whether the parity/CRC selection for a PSI5 message is to be controlled globally on a channel basis (through the G_PC bits) or locally on a per frame basis (through the L_PC[frame] bits)." "0: Parity/CRC option controlled globally through..,1: Parity/CRC option controlled locally through the.." newline bitfld.long 0x0 28.--30. "F5_BYTE,Number of bytes in UART packet for message corresponding to frame 5." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "L_PC5,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame5.,1: CRC selected for PSI5 message for frame5." newline bitfld.long 0x0 24.--26. "F4_BYTE,Number of bytes in UART packet for message corresponding to frame 4." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "L_PC4,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame4.,1: CRC selected for PSI5 message for frame4." newline bitfld.long 0x0 20.--22. "F3_BYTE,Number of bytes in UART packet for message corresponding to frame 3." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "L_PC3,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame3.,1: CRC selected for PSI5 message for frame3." newline bitfld.long 0x0 16.--18. "F2_BYTE,Number of bytes in UART packet for message corresponding to frame 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "L_PC2,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message" "0: Parity selected for message for frame2.,1: CRC selected for PSI5 message for frame2." newline bitfld.long 0x0 12.--14. "F1_BYTE,Number of bytes in UART packet for message corresponding to frame 1." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "L_PC1,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame1.,1: CRC selected for PSI5 message for frame1." newline bitfld.long 0x0 8.--10. "F0_BYTE,Number of bytes in UART packet for message corresponding to frame 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "L_PC0,Effective when L_PC_EN == 1. Controls the local parity/CRC option for the message." "0: Parity selected for message for frame0.,1: CRC selected for PSI5 message for frame0." newline bitfld.long 0x0 6. "MODE,This bit selects the operating modes between sync and async for the channel." "0: Synchronous.,1: Asynchronous." newline bitfld.long 0x0 5. "TIME_STAMP_A_B_SEL,Decides whether timestamp counter A or B value is captured in the local timestamp buffer whenever a 'capture event' occurs." "0: Timestamp counter A.,1: Timestamp counter B." newline bitfld.long 0x0 4. "TMSG_TCMD,Whether the timestamp is recorded when the message is received or when the channel command is moved from the TxFIFO to the UART Tx register (emulates a sync pulse)" "0: Timestamp recorded based on 'emulated' sync pulse.,1: Timestamp recorded based on message header byte.." newline bitfld.long 0x0 3. "TSBUF_CLR,This bit is used to clear the local timestamp buffer for the respective channel.Once cleared the buffer remains clear till the event to capture time stamp is triggered." "?,1: Timestamp buffer is cleared." newline bitfld.long 0x0 2. "TSBUF_EN,This bit controls whether timestamp buffer maintains a value '0' or is refreshed on a timestamp 'capture event'." "0: Timestamp buffer maintains value '0'.,1: Timestamp buffer responds to a 'capture event'.." newline bitfld.long 0x0 1. "G_PC,This bit globally selects the Parity or the CRC option for all the Frames of that particular channel" "0: Parity option selected globally for messages of..,1: CRC option selected globally for messages of all.." newline bitfld.long 0x0 0. "CH_EN,PSI5 Channel Enable. This bit decides if the IP takes the data belonging to the specific channel as 'legal' or 'illegal'." "0: Concerned PSI5 channel is disabled. Any data..,1: PSI5 message extraction for the definition of.." line.long 0x4 "MSGB_CH7,PSI5-S channel message configuration register B" hexmask.long.byte 0x4 25.--29. 1. "F5_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 5." newline hexmask.long.byte 0x4 20.--24. 1. "F4_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 4." newline hexmask.long.byte 0x4 15.--19. 1. "F3_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 3." newline hexmask.long.byte 0x4 10.--14. 1. "F2_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 2." newline hexmask.long.byte 0x4 5.--9. 1. "F1_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 1." newline hexmask.long.byte 0x4 0.--4. 1. "F0_PAYLOAD,Number of bits in the payload region of the PSI5 message corresponding to frame 0." group.long 0x304++0x1F line.long 0x0 "MBOX_SR_CH7,PSI5-S mailbox status register channel" bitfld.long 0x0 17. "F5_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=5) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 16. "F5_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No overwrite of unread message in MBOX[n] LOC5.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 15. "F5_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC5." "0: No unread message in MBOX[n] LOC5.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 14. "F4_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=4) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 13. "F4_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No overwrite of unread message in MBOX[n] LOC4.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 12. "F4_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC4." "0: No unread message in MBOX[n] LOC4.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 11. "F3_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=3) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 10. "F3_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No overwrite of unread message in MBOX[n] LOC3.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 9. "F3_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC3." "0: No unread message in MBOX[n] LOC3.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 8. "F2_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=2) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 7. "F2_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No overwrite of unread message in MBOX[n] LOC2.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 6. "F2_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC2." "0: No unread message in MBOX[n] LOC2.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 5. "F1_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=1) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 4. "F1_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No overwrite of unread message in MBOX[n] LOC1.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 3. "F1_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC1." "0: No unread message in MBOX[n] LOC1.,1: It indicates that the message that has just been.." newline bitfld.long 0x0 2. "F0_ERR,This bit is the 'OR' of the contents of the PS_MBOX_SR_IRQ register. It is updated when the corresponding message (with the CID = n and FID=0) is read from the MRU_BUF2 by the DMA." "0: Indicates that the message that has just been..,1: Indicates that the message that has just been.." newline bitfld.long 0x0 1. "F0_OV,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No overwrite of unread message in MBOX[n] LOC0.,1: Indicates that there is an unread message stored.." newline bitfld.long 0x0 0. "F0_READ,It is a w1c and software has to clear it whenever it reads the message from the MBOX[n] LOC0." "0: No unread message in MBOX[n] LOC0.,1: It indicates that the message that has just been.." line.long 0x4 "WD_CFGR_CH7,PSI5-S channel watchdog configuration register" bitfld.long 0x4 27. "WDRST,Resets watchdog counter for the channel" "0,1" newline bitfld.long 0x4 26. "WDCS,This selects either GTM or the module clock for watchdog counter of the channel. See Figure1629) Clock distribution in PSI5-S." "0: ipg_clk_ps_wd clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x4 25. "WDEN,The watchdog counter for each channel can be started stopped." "0: Watchdog counter stopped. It maintains its value.,1: Watchdog counter started." newline hexmask.long.tbyte 0x4 0.--23. 1. "WD_TO,This indicates the watchdog time out value. The watchdog generates an overrun error in case the watchdog is not refreshed before the watchdog counter reached the WD_TO value." line.long 0x8 "DDTRIG_OFFR_CH7,PSI5-S DDSR trigger offset register channel" hexmask.long.word 0x8 0.--15. 1. "DDTRIG_OFFR,These bits configure the delay between the 'shift trigger' of the various DDSRs across different channels. The value in this register governs the delay after which the specific DDSR is triggered once the Global Shift trigger.." line.long 0xC "DDTRIG_PERR_CH7,PSI5-S DDSR trigger period register channel" hexmask.long.word 0xC 0.--15. 1. "DDTRIG_PERR,These bits configure the 'shift trigger' period for the DDSR of that specific channel. The value in this register governs the period with which the data for the DDSR of that particular channel is shifted out." line.long 0x10 "E2SCR_CH7,PSI5-S ECU to sensor control register" hexmask.long.byte 0x10 26.--30. 1. "CMD,Bits for the ECU-to-sensor 'CMD' format. They refer to the command send to the UART Tx logic when a '1' is shifted from the DDSR register." newline hexmask.long.byte 0x10 20.--24. 1. "ACMD,Bits for the ECU-to-sensor 'ACMD' format. They refer to the command send to the UART Tx logic when a '0' is shifted from the DDSR register." newline bitfld.long 0x10 17. "CH_TRIG,This controls that the DDSR of the specific channel is triggered locally. This bit controls the shifting when PS_E2SCR_CHn[GL_TRIG_SEL] is 0." "0: Stop the DDSR from shifting the commands. The..,1: Start the 'shift trigger' of the DDSR." newline bitfld.long 0x10 16. "GL_TRIG_SEL,This bit controls whether the DDSR shift trigger is a global trigger or a local channel trigger." "0: The DDSR shift trigger is a local channel..,1: The DDSR shift trigger is a global trigger.." newline bitfld.long 0x10 15. "DEFAULT_SYNC,Decides the value to which the DDSR has to default to when PS_E2SSR_CHn[DDSR_RDY] == 1." "0,1" newline bitfld.long 0x10 14. "DDSR_SHIFT_SEL,DDSR Shift Selection" "0: The shift trigger is from internal DDSR counters..,1: The input signal gtm_trig directly acts as the.." newline bitfld.long 0x10 13. "DDSR_CLR,Used for rejecting the contents of the DDSR register." "0,1" newline bitfld.long 0x10 12. "DDSR_CLK_SEL,Selects which clock clocks shift logic of the DDSR for shifting the bits for command transmission." "0: ipg_clk_ps_ddtrig clock.,1: gtm_trig is selected as the clock." newline bitfld.long 0x10 11. "CMDTR_SW_CTRL,Once the command is ready for transmission (indicated by the setting PS_E2SSR_CHn[CMDPR_BZY] to 1) this bit decides when the actual transmission has to start:" "0: The actual transmission of command remains..,1: The command transmission starts once the.." newline bitfld.long 0x10 9. "SYNCHRO_OVF_IE,Synchro overflow interrupt enable" "0: No interrupt is generated when..,1: Generate an interrupt when.." newline bitfld.long 0x10 7. "CMDTR_NWRT_IE,Interrupt Enable for DDSR being attempted to be written when it is still not empty that is PS_E2SSR_CHn[DDSR_RDY] == 0 yet an attempt to write to DDSR is made." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 6. "CMDPR_BZY_IE,Interrupt Enable for DDSR getting updated with the internally processed complete command (with CRC stuff bits start bits getting appended)." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 5. "DDSR_RDY_IE,Interrupt Enable for DDSR getting empty and ready for receiving new command." "0: Disable the interrupt.,1: Enable the interrupt." newline bitfld.long 0x10 0.--2. "CMD_TYPE," "0,1,2,3,4,5,6,7" line.long 0x14 "E2SSR_CH7,PSI5-S ECU to sensor status register" bitfld.long 0x14 9. "SYNCHRO_OVF,This bit gets set whenever due to any reason (like too less DDTRIG period) sync pulse of a channel comes before the previous sync pulse of the same channel has actually shifted its data." "0: No synch pulse overflow has occurred in the..,1: Synch Pulse overflow has occurred for the.." newline bitfld.long 0x14 7. "CMDTR_NWRT,Status of Command written to the DDSR:" "0: Command written to the DDSR has been accepted..,1: Command written to the DDSR is rejected as an.." newline bitfld.long 0x14 6. "CMDPR_BZY,Command Processing Busy Status" "0: DDSR is busy with command processing. For this..,1: DDSR is ready with the processed command.." newline bitfld.long 0x14 5. "DDSR_RDY,Status for DDSR getting empty and ready for receiving new command." "0: DDSR is not ready and is busy with either the..,1: DDSR is empty and ready for receiving a new.." line.long 0x18 "DDSR_H_CH7,PSI5-S channel1 ECU to sensor downstream data shift register high" hexmask.long.word 0x18 0.--10. 1. "DDSR_H,Upper High bits of the 43 bit complete DDSR register. These bits are updated by the hardware and software cannot write to these bits." line.long 0x1C "DDSR_L_CH7,PSI5-S channel1 ECU to sensor downstream data shift register low" hexmask.long.byte 0x1C 24.--31. 1. "DDSR_L1,8 bits of the DDSR_L that can only be read by the Application. These 8 bits are automatically updated by the hardware. They can be read by the software to check for the processed command after the command is written to the DDSR by the.." newline hexmask.long.tbyte 0x1C 0.--23. 1. "DDSR_L0,Lower 24 bits of the DDSR register that are written by the Application as well as updated by the hardware once the command processing is over." tree.end tree.end tree "RC1024K_DIG (RC1024K Digital Interface)" base ad:0x0 tree "RC1024K_DIG_PERIPHERAL_DOMAIN" base ad:0x722C8040 group.long 0x0++0x3 line.long 0x0 "CTL,Low Power RC Control register" hexmask.long.byte 0x0 16.--20. 1. "LPRCTRIM,Low power RC trimming bits" hexmask.long.byte 0x0 8.--12. 1. "LPRCDIV,Low Power RC clock division factor" bitfld.long 0x0 4. "S_LPRC,Low Power RC clock status" "0: LPRC is not providing a stable clock,1: LPRC is providing a stable clock" tree.end tree.end tree "RCMAIN_DIG (RCMAIN Digital Interface)" base ad:0x722C8000 group.long 0x0++0x3 line.long 0x0 "CTL,IRCOSC control register" hexmask.long.byte 0x0 16.--21. 1. "USER_TRIM,User trimming bits TRIM_BIT_USER[5:0] with respect to nominal factory frequency" hexmask.long.byte 0x0 8.--12. 1. "RCDIV,Main IRCOSC clock division factor" rgroup.long 0x4++0x3 line.long 0x0 "NT,IRCOSC Native Trimming register" hexmask.long.byte 0x0 24.--29. 1. "FT_CODE,This bitfield indicates the trimming code applied to RCOSC analog macro based on temperature measured by vtsense" hexmask.long.byte 0x0 0.--7. 1. "RCTRIM,IRCOSC trimming value: this bitfield reflects the coarse trim and fine trim applied to RC analog macro read from DCF clients." tree.end tree "REMAPDEFAULT" base ad:0x0 tree "REMAPDEFAULT_AXIM_0_IA_RD" tree "NIC400_LOCALKITE1_REMAPDEFAULT_AXIM_0_IA_RD" base ad:0x7B200000 wgroup.long 0x0++0x3 line.long 0x0 "REMAP," bitfld.long 0x0 0. "REMAP,REMAP" "0,1" rgroup.long 0x1FD0++0x2F line.long 0x0 "PERIPH_ID_4," hexmask.long.byte 0x0 0.--7. 1. "PERIPH_ID_4,PERIPH_ID_4" line.long 0x4 "PERIPH_ID_5," hexmask.long.byte 0x4 0.--7. 1. "PERIPH_ID_5,PERIPH_ID_5" line.long 0x8 "PERIPH_ID_6," hexmask.long.byte 0x8 0.--7. 1. "PERIPH_ID_6,PERIPH_ID_6" line.long 0xC "PERIPH_ID_7," hexmask.long.byte 0xC 0.--7. 1. "PERIPH_ID_7,PERIPH_ID_7" line.long 0x10 "PERIPH_ID_0," hexmask.long.byte 0x10 0.--7. 1. "PERIPH_ID_0,PERIPH_ID_0" line.long 0x14 "PERIPH_ID_1," hexmask.long.byte 0x14 0.--7. 1. "PERIPH_ID_1,PERIPH_ID_1" line.long 0x18 "PERIPH_ID_2," hexmask.long.byte 0x18 0.--7. 1. "PERIPH_ID_2,PERIPH_ID_2" line.long 0x1C "PERIPH_ID_3," hexmask.long.byte 0x1C 4.--7. 1. "REV_AND,REV_AND" hexmask.long.byte 0x1C 0.--3. 1. "CUST_MOD_NUM,CUST_MOD_NUM" line.long 0x20 "COMP_ID_0," hexmask.long.byte 0x20 0.--7. 1. "COMP_ID_0,COMP_ID_0" line.long 0x24 "COMP_ID_1," hexmask.long.byte 0x24 0.--7. 1. "COMP_ID_1,COMP_ID_1" line.long 0x28 "COMP_ID_2," hexmask.long.byte 0x28 0.--7. 1. "COMP_ID_2,COMP_ID_2" line.long 0x2C "COMP_ID_3," hexmask.long.byte 0x2C 0.--7. 1. "COMP_ID_3,COMP_ID_3" group.long 0x42108++0x3 line.long 0x0 "AXIM_0_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x43108++0x3 line.long 0x0 "AXIM_1_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x44108++0x3 line.long 0x0 "AXIF_0_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x45108++0x3 line.long 0x0 "AXIF_1_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x46108++0x7 line.long 0x0 "IN_NOC_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" line.long 0x4 "IN_NOC_IA_QOS_CNTL," bitfld.long 0x4 20. "MODE_AR_FC,MODE_AR_FC" "0,1" bitfld.long 0x4 16. "MODE_AW_FC,MODE_AW_FC" "0,1" bitfld.long 0x4 4. "EN_AR_FC,EN_AR_FC" "0,1" bitfld.long 0x4 3. "EN_AW_FC,EN_AW_FC" "0,1" bitfld.long 0x4 2. "EN_AWAR_RATE,EN_AWAR_RATE" "0,1" bitfld.long 0x4 1. "EN_AR_RATE,EN_AR_RATE" "0,1" newline bitfld.long 0x4 0. "EN_AW_RATE,EN_AW_RATE" "0,1" group.long 0x46118++0x23 line.long 0x0 "IN_NOC_IA_AW_P," hexmask.long.byte 0x0 24.--31. 1. "AW_P,AW_P" line.long 0x4 "IN_NOC_IA_AW_B," hexmask.long.word 0x4 0.--15. 1. "AW_B,AW_B" line.long 0x8 "IN_NOC_IA_AW_R," hexmask.long.word 0x8 20.--31. 1. "AW_R,AW_R" line.long 0xC "IN_NOC_IA_AR_P," hexmask.long.byte 0xC 24.--31. 1. "AR_P,AR_P" line.long 0x10 "IN_NOC_IA_AR_B," hexmask.long.word 0x10 0.--15. 1. "AR_B,AR_B" line.long 0x14 "IN_NOC_IA_AR_R," hexmask.long.word 0x14 20.--31. 1. "AR_R,AR_R" line.long 0x18 "IN_NOC_IA_TARGET_FC," hexmask.long.word 0x18 16.--27. 1. "AR_TARGET_FC,AR_TARGET_FC" hexmask.long.word 0x18 0.--11. 1. "AW_TARGET_FC,AW_TARGET_FC" line.long 0x1C "IN_NOC_IA_KI_FC," bitfld.long 0x1C 8.--10. "AR_KI_FC,AR_KI_FC" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "AW_KI_FC,AW_KI_FC" "0,1,2,3,4,5,6,7" line.long 0x20 "IN_NOC_IA_QOS_RANGE," hexmask.long.byte 0x20 24.--27. 1. "AR_MAX_QOS,AR_MAX_QOS" hexmask.long.byte 0x20 16.--19. 1. "AR_MIN_QOS,AR_MIN_QOS" hexmask.long.byte 0x20 8.--11. 1. "AW_MAX_QOS,AW_MAX_QOS" hexmask.long.byte 0x20 0.--3. 1. "AW_MIN_QOS,AW_MIN_QOS" group.long 0xC2008++0x3 line.long 0x0 "AXIM_0_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC2108++0x3 line.long 0x0 "AXIM_0_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC3008++0x3 line.long 0x0 "AXIM_1_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC3108++0x3 line.long 0x0 "AXIM_1_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC4008++0x3 line.long 0x0 "IN_NOC_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC4108++0x3 line.long 0x0 "IN_NOC_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC5008++0x3 line.long 0x0 "AXIM_0_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC5108++0x3 line.long 0x0 "AXIM_0_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC6008++0x3 line.long 0x0 "AXIM_1_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC6108++0x3 line.long 0x0 "AXIM_1_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC7008++0x3 line.long 0x0 "AXIM_0_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC7108++0x3 line.long 0x0 "AXIM_0_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC8008++0x3 line.long 0x0 "AXIM_1_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC8108++0x3 line.long 0x0 "AXIM_1_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC9008++0x3 line.long 0x0 "AXIF_0_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC9108++0x3 line.long 0x0 "AXIF_0_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCA008++0x3 line.long 0x0 "IB17_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCA108++0x3 line.long 0x0 "IB17_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCB008++0x3 line.long 0x0 "AXIM_0_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCB108++0x3 line.long 0x0 "AXIM_0_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCC008++0x3 line.long 0x0 "IB18_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCC108++0x3 line.long 0x0 "IB18_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCD008++0x3 line.long 0x0 "AXIF_1_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCD108++0x3 line.long 0x0 "AXIF_1_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCE008++0x3 line.long 0x0 "AXIF_0_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCE108++0x3 line.long 0x0 "AXIF_0_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCF008++0x3 line.long 0x0 "IN_NOC_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCF108++0x3 line.long 0x0 "IN_NOC_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD0008++0x3 line.long 0x0 "AXIM_1_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD0108++0x3 line.long 0x0 "AXIM_1_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD1008++0x3 line.long 0x0 "IB21_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD1108++0x3 line.long 0x0 "IB21_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD2008++0x3 line.long 0x0 "AXIF_1_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD2108++0x3 line.long 0x0 "AXIF_1_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD3008++0x3 line.long 0x0 "IN_NOC_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD3108++0x3 line.long 0x0 "IN_NOC_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD4008++0x3 line.long 0x0 "IB20_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD4108++0x3 line.long 0x0 "IB20_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD5008++0x3 line.long 0x0 "IB22_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD5108++0x3 line.long 0x0 "IB22_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD6008++0x3 line.long 0x0 "IB19_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD6108++0x3 line.long 0x0 "IB19_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD7008++0x3 line.long 0x0 "IN_NOC_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD7108++0x3 line.long 0x0 "IN_NOC_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" tree.end tree "NIC400_LOCALKITE2_REMAPDEFAULT_AXIM_0_IA_RD" base ad:0x7B300000 wgroup.long 0x0++0x3 line.long 0x0 "REMAP," bitfld.long 0x0 0. "REMAP,REMAP" "0,1" rgroup.long 0x1FD0++0x2F line.long 0x0 "PERIPH_ID_4," hexmask.long.byte 0x0 0.--7. 1. "PERIPH_ID_4,PERIPH_ID_4" line.long 0x4 "PERIPH_ID_5," hexmask.long.byte 0x4 0.--7. 1. "PERIPH_ID_5,PERIPH_ID_5" line.long 0x8 "PERIPH_ID_6," hexmask.long.byte 0x8 0.--7. 1. "PERIPH_ID_6,PERIPH_ID_6" line.long 0xC "PERIPH_ID_7," hexmask.long.byte 0xC 0.--7. 1. "PERIPH_ID_7,PERIPH_ID_7" line.long 0x10 "PERIPH_ID_0," hexmask.long.byte 0x10 0.--7. 1. "PERIPH_ID_0,PERIPH_ID_0" line.long 0x14 "PERIPH_ID_1," hexmask.long.byte 0x14 0.--7. 1. "PERIPH_ID_1,PERIPH_ID_1" line.long 0x18 "PERIPH_ID_2," hexmask.long.byte 0x18 0.--7. 1. "PERIPH_ID_2,PERIPH_ID_2" line.long 0x1C "PERIPH_ID_3," hexmask.long.byte 0x1C 4.--7. 1. "REV_AND,REV_AND" hexmask.long.byte 0x1C 0.--3. 1. "CUST_MOD_NUM,CUST_MOD_NUM" line.long 0x20 "COMP_ID_0," hexmask.long.byte 0x20 0.--7. 1. "COMP_ID_0,COMP_ID_0" line.long 0x24 "COMP_ID_1," hexmask.long.byte 0x24 0.--7. 1. "COMP_ID_1,COMP_ID_1" line.long 0x28 "COMP_ID_2," hexmask.long.byte 0x28 0.--7. 1. "COMP_ID_2,COMP_ID_2" line.long 0x2C "COMP_ID_3," hexmask.long.byte 0x2C 0.--7. 1. "COMP_ID_3,COMP_ID_3" group.long 0x42108++0x3 line.long 0x0 "AXIM_0_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x43108++0x3 line.long 0x0 "AXIM_1_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x44108++0x3 line.long 0x0 "AXIF_0_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x45108++0x3 line.long 0x0 "AXIF_1_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x46108++0x7 line.long 0x0 "IN_NOC_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" line.long 0x4 "IN_NOC_IA_QOS_CNTL," bitfld.long 0x4 20. "MODE_AR_FC,MODE_AR_FC" "0,1" bitfld.long 0x4 16. "MODE_AW_FC,MODE_AW_FC" "0,1" bitfld.long 0x4 4. "EN_AR_FC,EN_AR_FC" "0,1" bitfld.long 0x4 3. "EN_AW_FC,EN_AW_FC" "0,1" bitfld.long 0x4 2. "EN_AWAR_RATE,EN_AWAR_RATE" "0,1" bitfld.long 0x4 1. "EN_AR_RATE,EN_AR_RATE" "0,1" newline bitfld.long 0x4 0. "EN_AW_RATE,EN_AW_RATE" "0,1" group.long 0x46118++0x23 line.long 0x0 "IN_NOC_IA_AW_P," hexmask.long.byte 0x0 24.--31. 1. "AW_P,AW_P" line.long 0x4 "IN_NOC_IA_AW_B," hexmask.long.word 0x4 0.--15. 1. "AW_B,AW_B" line.long 0x8 "IN_NOC_IA_AW_R," hexmask.long.word 0x8 20.--31. 1. "AW_R,AW_R" line.long 0xC "IN_NOC_IA_AR_P," hexmask.long.byte 0xC 24.--31. 1. "AR_P,AR_P" line.long 0x10 "IN_NOC_IA_AR_B," hexmask.long.word 0x10 0.--15. 1. "AR_B,AR_B" line.long 0x14 "IN_NOC_IA_AR_R," hexmask.long.word 0x14 20.--31. 1. "AR_R,AR_R" line.long 0x18 "IN_NOC_IA_TARGET_FC," hexmask.long.word 0x18 16.--27. 1. "AR_TARGET_FC,AR_TARGET_FC" hexmask.long.word 0x18 0.--11. 1. "AW_TARGET_FC,AW_TARGET_FC" line.long 0x1C "IN_NOC_IA_KI_FC," bitfld.long 0x1C 8.--10. "AR_KI_FC,AR_KI_FC" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "AW_KI_FC,AW_KI_FC" "0,1,2,3,4,5,6,7" line.long 0x20 "IN_NOC_IA_QOS_RANGE," hexmask.long.byte 0x20 24.--27. 1. "AR_MAX_QOS,AR_MAX_QOS" hexmask.long.byte 0x20 16.--19. 1. "AR_MIN_QOS,AR_MIN_QOS" hexmask.long.byte 0x20 8.--11. 1. "AW_MAX_QOS,AW_MAX_QOS" hexmask.long.byte 0x20 0.--3. 1. "AW_MIN_QOS,AW_MIN_QOS" group.long 0xC2008++0x3 line.long 0x0 "AXIM_0_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC2108++0x3 line.long 0x0 "AXIM_0_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC3008++0x3 line.long 0x0 "AXIM_1_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC3108++0x3 line.long 0x0 "AXIM_1_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC4008++0x3 line.long 0x0 "IN_NOC_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC4108++0x3 line.long 0x0 "IN_NOC_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC5008++0x3 line.long 0x0 "AXIM_0_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC5108++0x3 line.long 0x0 "AXIM_0_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC6008++0x3 line.long 0x0 "AXIM_1_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC6108++0x3 line.long 0x0 "AXIM_1_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC7008++0x3 line.long 0x0 "AXIM_0_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC7108++0x3 line.long 0x0 "AXIM_0_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC8008++0x3 line.long 0x0 "AXIM_1_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC8108++0x3 line.long 0x0 "AXIM_1_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC9008++0x3 line.long 0x0 "AXIF_0_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC9108++0x3 line.long 0x0 "AXIF_0_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCA008++0x3 line.long 0x0 "IB17_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCA108++0x3 line.long 0x0 "IB17_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCB008++0x3 line.long 0x0 "AXIM_0_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCB108++0x3 line.long 0x0 "AXIM_0_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCC008++0x3 line.long 0x0 "IB18_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCC108++0x3 line.long 0x0 "IB18_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCD008++0x3 line.long 0x0 "AXIF_1_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCD108++0x3 line.long 0x0 "AXIF_1_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCE008++0x3 line.long 0x0 "AXIF_0_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCE108++0x3 line.long 0x0 "AXIF_0_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCF008++0x3 line.long 0x0 "IN_NOC_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCF108++0x3 line.long 0x0 "IN_NOC_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD0008++0x3 line.long 0x0 "AXIM_1_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD0108++0x3 line.long 0x0 "AXIM_1_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD1008++0x3 line.long 0x0 "IB21_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD1108++0x3 line.long 0x0 "IB21_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD2008++0x3 line.long 0x0 "AXIF_1_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD2108++0x3 line.long 0x0 "AXIF_1_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD3008++0x3 line.long 0x0 "IN_NOC_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD3108++0x3 line.long 0x0 "IN_NOC_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD4008++0x3 line.long 0x0 "IB20_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD4108++0x3 line.long 0x0 "IB20_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD5008++0x3 line.long 0x0 "IB22_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD5108++0x3 line.long 0x0 "IB22_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD6008++0x3 line.long 0x0 "IB19_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD6108++0x3 line.long 0x0 "IB19_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD7008++0x3 line.long 0x0 "IN_NOC_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD7108++0x3 line.long 0x0 "IN_NOC_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" tree.end tree "REMAPDEFAULT_AXIM_0_IA_RD" base ad:0x7B100000 wgroup.long 0x0++0x3 line.long 0x0 "REMAP," bitfld.long 0x0 0. "REMAP,REMAP" "0,1" rgroup.long 0x1FD0++0x2F line.long 0x0 "PERIPH_ID_4," hexmask.long.byte 0x0 0.--7. 1. "PERIPH_ID_4,PERIPH_ID_4" line.long 0x4 "PERIPH_ID_5," hexmask.long.byte 0x4 0.--7. 1. "PERIPH_ID_5,PERIPH_ID_5" line.long 0x8 "PERIPH_ID_6," hexmask.long.byte 0x8 0.--7. 1. "PERIPH_ID_6,PERIPH_ID_6" line.long 0xC "PERIPH_ID_7," hexmask.long.byte 0xC 0.--7. 1. "PERIPH_ID_7,PERIPH_ID_7" line.long 0x10 "PERIPH_ID_0," hexmask.long.byte 0x10 0.--7. 1. "PERIPH_ID_0,PERIPH_ID_0" line.long 0x14 "PERIPH_ID_1," hexmask.long.byte 0x14 0.--7. 1. "PERIPH_ID_1,PERIPH_ID_1" line.long 0x18 "PERIPH_ID_2," hexmask.long.byte 0x18 0.--7. 1. "PERIPH_ID_2,PERIPH_ID_2" line.long 0x1C "PERIPH_ID_3," hexmask.long.byte 0x1C 4.--7. 1. "REV_AND,REV_AND" hexmask.long.byte 0x1C 0.--3. 1. "CUST_MOD_NUM,CUST_MOD_NUM" line.long 0x20 "COMP_ID_0," hexmask.long.byte 0x20 0.--7. 1. "COMP_ID_0,COMP_ID_0" line.long 0x24 "COMP_ID_1," hexmask.long.byte 0x24 0.--7. 1. "COMP_ID_1,COMP_ID_1" line.long 0x28 "COMP_ID_2," hexmask.long.byte 0x28 0.--7. 1. "COMP_ID_2,COMP_ID_2" line.long 0x2C "COMP_ID_3," hexmask.long.byte 0x2C 0.--7. 1. "COMP_ID_3,COMP_ID_3" group.long 0x42108++0x3 line.long 0x0 "AXIM_0_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x43108++0x3 line.long 0x0 "AXIM_1_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x44108++0x3 line.long 0x0 "AXIF_0_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x45108++0x3 line.long 0x0 "AXIF_1_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x46108++0x7 line.long 0x0 "IN_NOC_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" line.long 0x4 "IN_NOC_IA_QOS_CNTL," bitfld.long 0x4 20. "MODE_AR_FC,MODE_AR_FC" "0,1" bitfld.long 0x4 16. "MODE_AW_FC,MODE_AW_FC" "0,1" bitfld.long 0x4 4. "EN_AR_FC,EN_AR_FC" "0,1" bitfld.long 0x4 3. "EN_AW_FC,EN_AW_FC" "0,1" bitfld.long 0x4 2. "EN_AWAR_RATE,EN_AWAR_RATE" "0,1" bitfld.long 0x4 1. "EN_AR_RATE,EN_AR_RATE" "0,1" newline bitfld.long 0x4 0. "EN_AW_RATE,EN_AW_RATE" "0,1" group.long 0x46118++0x23 line.long 0x0 "IN_NOC_IA_AW_P," hexmask.long.byte 0x0 24.--31. 1. "AW_P,AW_P" line.long 0x4 "IN_NOC_IA_AW_B," hexmask.long.word 0x4 0.--15. 1. "AW_B,AW_B" line.long 0x8 "IN_NOC_IA_AW_R," hexmask.long.word 0x8 20.--31. 1. "AW_R,AW_R" line.long 0xC "IN_NOC_IA_AR_P," hexmask.long.byte 0xC 24.--31. 1. "AR_P,AR_P" line.long 0x10 "IN_NOC_IA_AR_B," hexmask.long.word 0x10 0.--15. 1. "AR_B,AR_B" line.long 0x14 "IN_NOC_IA_AR_R," hexmask.long.word 0x14 20.--31. 1. "AR_R,AR_R" line.long 0x18 "IN_NOC_IA_TARGET_FC," hexmask.long.word 0x18 16.--27. 1. "AR_TARGET_FC,AR_TARGET_FC" hexmask.long.word 0x18 0.--11. 1. "AW_TARGET_FC,AW_TARGET_FC" line.long 0x1C "IN_NOC_IA_KI_FC," bitfld.long 0x1C 8.--10. "AR_KI_FC,AR_KI_FC" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "AW_KI_FC,AW_KI_FC" "0,1,2,3,4,5,6,7" line.long 0x20 "IN_NOC_IA_QOS_RANGE," hexmask.long.byte 0x20 24.--27. 1. "AR_MAX_QOS,AR_MAX_QOS" hexmask.long.byte 0x20 16.--19. 1. "AR_MIN_QOS,AR_MIN_QOS" hexmask.long.byte 0x20 8.--11. 1. "AW_MAX_QOS,AW_MAX_QOS" hexmask.long.byte 0x20 0.--3. 1. "AW_MIN_QOS,AW_MIN_QOS" group.long 0xC2008++0x3 line.long 0x0 "AXIM_0_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC2108++0x3 line.long 0x0 "AXIM_0_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC3008++0x3 line.long 0x0 "AXIM_1_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC3108++0x3 line.long 0x0 "AXIM_1_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC4008++0x3 line.long 0x0 "IN_NOC_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC4108++0x3 line.long 0x0 "IN_NOC_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC5008++0x3 line.long 0x0 "AXIM_0_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC5108++0x3 line.long 0x0 "AXIM_0_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC6008++0x3 line.long 0x0 "AXIM_1_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC6108++0x3 line.long 0x0 "AXIM_1_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC7008++0x3 line.long 0x0 "AXIM_0_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC7108++0x3 line.long 0x0 "AXIM_0_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC8008++0x3 line.long 0x0 "AXIM_1_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC8108++0x3 line.long 0x0 "AXIM_1_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC9008++0x3 line.long 0x0 "AXIF_0_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC9108++0x3 line.long 0x0 "AXIF_0_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCA008++0x3 line.long 0x0 "IB17_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCA108++0x3 line.long 0x0 "IB17_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCB008++0x3 line.long 0x0 "AXIM_0_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCB108++0x3 line.long 0x0 "AXIM_0_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCC008++0x3 line.long 0x0 "IB18_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCC108++0x3 line.long 0x0 "IB18_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCD008++0x3 line.long 0x0 "AXIF_1_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCD108++0x3 line.long 0x0 "AXIF_1_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCE008++0x3 line.long 0x0 "AXIF_0_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCE108++0x3 line.long 0x0 "AXIF_0_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCF008++0x3 line.long 0x0 "IN_NOC_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCF108++0x3 line.long 0x0 "IN_NOC_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD0008++0x3 line.long 0x0 "AXIM_1_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD0108++0x3 line.long 0x0 "AXIM_1_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD1008++0x3 line.long 0x0 "IB21_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD1108++0x3 line.long 0x0 "IB21_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD2008++0x3 line.long 0x0 "AXIF_1_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD2108++0x3 line.long 0x0 "AXIF_1_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD3008++0x3 line.long 0x0 "IN_NOC_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD3108++0x3 line.long 0x0 "IN_NOC_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD4008++0x3 line.long 0x0 "IB20_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD4108++0x3 line.long 0x0 "IB20_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD5008++0x3 line.long 0x0 "IB22_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD5108++0x3 line.long 0x0 "IB22_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD6008++0x3 line.long 0x0 "IB19_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD6108++0x3 line.long 0x0 "IB19_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD7008++0x3 line.long 0x0 "IN_NOC_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD7108++0x3 line.long 0x0 "IN_NOC_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" tree.end tree.end tree "REMAPDEFAULT_AXIM_1_IA_RD" tree "NIC400_LOCALKITE1_REMAPDEFAULT_AXIM_1_IA_RD" base ad:0x7B200000 wgroup.long 0x0++0x3 line.long 0x0 "REMAP," bitfld.long 0x0 0. "REMAP,REMAP" "0,1" rgroup.long 0x1FD0++0x2F line.long 0x0 "PERIPH_ID_4," hexmask.long.byte 0x0 0.--7. 1. "PERIPH_ID_4,PERIPH_ID_4" line.long 0x4 "PERIPH_ID_5," hexmask.long.byte 0x4 0.--7. 1. "PERIPH_ID_5,PERIPH_ID_5" line.long 0x8 "PERIPH_ID_6," hexmask.long.byte 0x8 0.--7. 1. "PERIPH_ID_6,PERIPH_ID_6" line.long 0xC "PERIPH_ID_7," hexmask.long.byte 0xC 0.--7. 1. "PERIPH_ID_7,PERIPH_ID_7" line.long 0x10 "PERIPH_ID_0," hexmask.long.byte 0x10 0.--7. 1. "PERIPH_ID_0,PERIPH_ID_0" line.long 0x14 "PERIPH_ID_1," hexmask.long.byte 0x14 0.--7. 1. "PERIPH_ID_1,PERIPH_ID_1" line.long 0x18 "PERIPH_ID_2," hexmask.long.byte 0x18 0.--7. 1. "PERIPH_ID_2,PERIPH_ID_2" line.long 0x1C "PERIPH_ID_3," hexmask.long.byte 0x1C 4.--7. 1. "REV_AND,REV_AND" hexmask.long.byte 0x1C 0.--3. 1. "CUST_MOD_NUM,CUST_MOD_NUM" line.long 0x20 "COMP_ID_0," hexmask.long.byte 0x20 0.--7. 1. "COMP_ID_0,COMP_ID_0" line.long 0x24 "COMP_ID_1," hexmask.long.byte 0x24 0.--7. 1. "COMP_ID_1,COMP_ID_1" line.long 0x28 "COMP_ID_2," hexmask.long.byte 0x28 0.--7. 1. "COMP_ID_2,COMP_ID_2" line.long 0x2C "COMP_ID_3," hexmask.long.byte 0x2C 0.--7. 1. "COMP_ID_3,COMP_ID_3" group.long 0x42108++0x3 line.long 0x0 "AXIM_0_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x43108++0x3 line.long 0x0 "AXIM_1_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x44108++0x3 line.long 0x0 "AXIF_0_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x45108++0x3 line.long 0x0 "AXIF_1_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x46108++0x7 line.long 0x0 "IN_NOC_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" line.long 0x4 "IN_NOC_IA_QOS_CNTL," bitfld.long 0x4 20. "MODE_AR_FC,MODE_AR_FC" "0,1" bitfld.long 0x4 16. "MODE_AW_FC,MODE_AW_FC" "0,1" bitfld.long 0x4 4. "EN_AR_FC,EN_AR_FC" "0,1" bitfld.long 0x4 3. "EN_AW_FC,EN_AW_FC" "0,1" bitfld.long 0x4 2. "EN_AWAR_RATE,EN_AWAR_RATE" "0,1" bitfld.long 0x4 1. "EN_AR_RATE,EN_AR_RATE" "0,1" newline bitfld.long 0x4 0. "EN_AW_RATE,EN_AW_RATE" "0,1" group.long 0x46118++0x23 line.long 0x0 "IN_NOC_IA_AW_P," hexmask.long.byte 0x0 24.--31. 1. "AW_P,AW_P" line.long 0x4 "IN_NOC_IA_AW_B," hexmask.long.word 0x4 0.--15. 1. "AW_B,AW_B" line.long 0x8 "IN_NOC_IA_AW_R," hexmask.long.word 0x8 20.--31. 1. "AW_R,AW_R" line.long 0xC "IN_NOC_IA_AR_P," hexmask.long.byte 0xC 24.--31. 1. "AR_P,AR_P" line.long 0x10 "IN_NOC_IA_AR_B," hexmask.long.word 0x10 0.--15. 1. "AR_B,AR_B" line.long 0x14 "IN_NOC_IA_AR_R," hexmask.long.word 0x14 20.--31. 1. "AR_R,AR_R" line.long 0x18 "IN_NOC_IA_TARGET_FC," hexmask.long.word 0x18 16.--27. 1. "AR_TARGET_FC,AR_TARGET_FC" hexmask.long.word 0x18 0.--11. 1. "AW_TARGET_FC,AW_TARGET_FC" line.long 0x1C "IN_NOC_IA_KI_FC," bitfld.long 0x1C 8.--10. "AR_KI_FC,AR_KI_FC" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "AW_KI_FC,AW_KI_FC" "0,1,2,3,4,5,6,7" line.long 0x20 "IN_NOC_IA_QOS_RANGE," hexmask.long.byte 0x20 24.--27. 1. "AR_MAX_QOS,AR_MAX_QOS" hexmask.long.byte 0x20 16.--19. 1. "AR_MIN_QOS,AR_MIN_QOS" hexmask.long.byte 0x20 8.--11. 1. "AW_MAX_QOS,AW_MAX_QOS" hexmask.long.byte 0x20 0.--3. 1. "AW_MIN_QOS,AW_MIN_QOS" group.long 0xC2008++0x3 line.long 0x0 "AXIM_0_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC2108++0x3 line.long 0x0 "AXIM_0_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC3008++0x3 line.long 0x0 "AXIM_1_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC3108++0x3 line.long 0x0 "AXIM_1_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC4008++0x3 line.long 0x0 "IN_NOC_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC4108++0x3 line.long 0x0 "IN_NOC_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC5008++0x3 line.long 0x0 "AXIM_0_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC5108++0x3 line.long 0x0 "AXIM_0_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC6008++0x3 line.long 0x0 "AXIM_1_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC6108++0x3 line.long 0x0 "AXIM_1_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC7008++0x3 line.long 0x0 "AXIM_0_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC7108++0x3 line.long 0x0 "AXIM_0_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC8008++0x3 line.long 0x0 "AXIM_1_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC8108++0x3 line.long 0x0 "AXIM_1_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC9008++0x3 line.long 0x0 "AXIF_0_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC9108++0x3 line.long 0x0 "AXIF_0_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCA008++0x3 line.long 0x0 "IB17_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCA108++0x3 line.long 0x0 "IB17_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCB008++0x3 line.long 0x0 "AXIM_0_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCB108++0x3 line.long 0x0 "AXIM_0_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCC008++0x3 line.long 0x0 "IB18_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCC108++0x3 line.long 0x0 "IB18_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCD008++0x3 line.long 0x0 "AXIF_1_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCD108++0x3 line.long 0x0 "AXIF_1_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCE008++0x3 line.long 0x0 "AXIF_0_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCE108++0x3 line.long 0x0 "AXIF_0_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCF008++0x3 line.long 0x0 "IN_NOC_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCF108++0x3 line.long 0x0 "IN_NOC_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD0008++0x3 line.long 0x0 "AXIM_1_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD0108++0x3 line.long 0x0 "AXIM_1_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD1008++0x3 line.long 0x0 "IB21_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD1108++0x3 line.long 0x0 "IB21_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD2008++0x3 line.long 0x0 "AXIF_1_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD2108++0x3 line.long 0x0 "AXIF_1_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD3008++0x3 line.long 0x0 "IN_NOC_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD3108++0x3 line.long 0x0 "IN_NOC_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD4008++0x3 line.long 0x0 "IB20_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD4108++0x3 line.long 0x0 "IB20_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD5008++0x3 line.long 0x0 "IB22_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD5108++0x3 line.long 0x0 "IB22_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD6008++0x3 line.long 0x0 "IB19_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD6108++0x3 line.long 0x0 "IB19_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD7008++0x3 line.long 0x0 "IN_NOC_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD7108++0x3 line.long 0x0 "IN_NOC_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" tree.end tree "NIC400_LOCALKITE2_REMAPDEFAULT_AXIM_1_IA_RD" base ad:0x7B300000 wgroup.long 0x0++0x3 line.long 0x0 "REMAP," bitfld.long 0x0 0. "REMAP,REMAP" "0,1" rgroup.long 0x1FD0++0x2F line.long 0x0 "PERIPH_ID_4," hexmask.long.byte 0x0 0.--7. 1. "PERIPH_ID_4,PERIPH_ID_4" line.long 0x4 "PERIPH_ID_5," hexmask.long.byte 0x4 0.--7. 1. "PERIPH_ID_5,PERIPH_ID_5" line.long 0x8 "PERIPH_ID_6," hexmask.long.byte 0x8 0.--7. 1. "PERIPH_ID_6,PERIPH_ID_6" line.long 0xC "PERIPH_ID_7," hexmask.long.byte 0xC 0.--7. 1. "PERIPH_ID_7,PERIPH_ID_7" line.long 0x10 "PERIPH_ID_0," hexmask.long.byte 0x10 0.--7. 1. "PERIPH_ID_0,PERIPH_ID_0" line.long 0x14 "PERIPH_ID_1," hexmask.long.byte 0x14 0.--7. 1. "PERIPH_ID_1,PERIPH_ID_1" line.long 0x18 "PERIPH_ID_2," hexmask.long.byte 0x18 0.--7. 1. "PERIPH_ID_2,PERIPH_ID_2" line.long 0x1C "PERIPH_ID_3," hexmask.long.byte 0x1C 4.--7. 1. "REV_AND,REV_AND" hexmask.long.byte 0x1C 0.--3. 1. "CUST_MOD_NUM,CUST_MOD_NUM" line.long 0x20 "COMP_ID_0," hexmask.long.byte 0x20 0.--7. 1. "COMP_ID_0,COMP_ID_0" line.long 0x24 "COMP_ID_1," hexmask.long.byte 0x24 0.--7. 1. "COMP_ID_1,COMP_ID_1" line.long 0x28 "COMP_ID_2," hexmask.long.byte 0x28 0.--7. 1. "COMP_ID_2,COMP_ID_2" line.long 0x2C "COMP_ID_3," hexmask.long.byte 0x2C 0.--7. 1. "COMP_ID_3,COMP_ID_3" group.long 0x42108++0x3 line.long 0x0 "AXIM_0_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x43108++0x3 line.long 0x0 "AXIM_1_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x44108++0x3 line.long 0x0 "AXIF_0_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x45108++0x3 line.long 0x0 "AXIF_1_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x46108++0x7 line.long 0x0 "IN_NOC_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" line.long 0x4 "IN_NOC_IA_QOS_CNTL," bitfld.long 0x4 20. "MODE_AR_FC,MODE_AR_FC" "0,1" bitfld.long 0x4 16. "MODE_AW_FC,MODE_AW_FC" "0,1" bitfld.long 0x4 4. "EN_AR_FC,EN_AR_FC" "0,1" bitfld.long 0x4 3. "EN_AW_FC,EN_AW_FC" "0,1" bitfld.long 0x4 2. "EN_AWAR_RATE,EN_AWAR_RATE" "0,1" bitfld.long 0x4 1. "EN_AR_RATE,EN_AR_RATE" "0,1" newline bitfld.long 0x4 0. "EN_AW_RATE,EN_AW_RATE" "0,1" group.long 0x46118++0x23 line.long 0x0 "IN_NOC_IA_AW_P," hexmask.long.byte 0x0 24.--31. 1. "AW_P,AW_P" line.long 0x4 "IN_NOC_IA_AW_B," hexmask.long.word 0x4 0.--15. 1. "AW_B,AW_B" line.long 0x8 "IN_NOC_IA_AW_R," hexmask.long.word 0x8 20.--31. 1. "AW_R,AW_R" line.long 0xC "IN_NOC_IA_AR_P," hexmask.long.byte 0xC 24.--31. 1. "AR_P,AR_P" line.long 0x10 "IN_NOC_IA_AR_B," hexmask.long.word 0x10 0.--15. 1. "AR_B,AR_B" line.long 0x14 "IN_NOC_IA_AR_R," hexmask.long.word 0x14 20.--31. 1. "AR_R,AR_R" line.long 0x18 "IN_NOC_IA_TARGET_FC," hexmask.long.word 0x18 16.--27. 1. "AR_TARGET_FC,AR_TARGET_FC" hexmask.long.word 0x18 0.--11. 1. "AW_TARGET_FC,AW_TARGET_FC" line.long 0x1C "IN_NOC_IA_KI_FC," bitfld.long 0x1C 8.--10. "AR_KI_FC,AR_KI_FC" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "AW_KI_FC,AW_KI_FC" "0,1,2,3,4,5,6,7" line.long 0x20 "IN_NOC_IA_QOS_RANGE," hexmask.long.byte 0x20 24.--27. 1. "AR_MAX_QOS,AR_MAX_QOS" hexmask.long.byte 0x20 16.--19. 1. "AR_MIN_QOS,AR_MIN_QOS" hexmask.long.byte 0x20 8.--11. 1. "AW_MAX_QOS,AW_MAX_QOS" hexmask.long.byte 0x20 0.--3. 1. "AW_MIN_QOS,AW_MIN_QOS" group.long 0xC2008++0x3 line.long 0x0 "AXIM_0_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC2108++0x3 line.long 0x0 "AXIM_0_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC3008++0x3 line.long 0x0 "AXIM_1_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC3108++0x3 line.long 0x0 "AXIM_1_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC4008++0x3 line.long 0x0 "IN_NOC_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC4108++0x3 line.long 0x0 "IN_NOC_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC5008++0x3 line.long 0x0 "AXIM_0_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC5108++0x3 line.long 0x0 "AXIM_0_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC6008++0x3 line.long 0x0 "AXIM_1_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC6108++0x3 line.long 0x0 "AXIM_1_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC7008++0x3 line.long 0x0 "AXIM_0_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC7108++0x3 line.long 0x0 "AXIM_0_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC8008++0x3 line.long 0x0 "AXIM_1_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC8108++0x3 line.long 0x0 "AXIM_1_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC9008++0x3 line.long 0x0 "AXIF_0_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC9108++0x3 line.long 0x0 "AXIF_0_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCA008++0x3 line.long 0x0 "IB17_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCA108++0x3 line.long 0x0 "IB17_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCB008++0x3 line.long 0x0 "AXIM_0_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCB108++0x3 line.long 0x0 "AXIM_0_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCC008++0x3 line.long 0x0 "IB18_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCC108++0x3 line.long 0x0 "IB18_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCD008++0x3 line.long 0x0 "AXIF_1_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCD108++0x3 line.long 0x0 "AXIF_1_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCE008++0x3 line.long 0x0 "AXIF_0_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCE108++0x3 line.long 0x0 "AXIF_0_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCF008++0x3 line.long 0x0 "IN_NOC_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCF108++0x3 line.long 0x0 "IN_NOC_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD0008++0x3 line.long 0x0 "AXIM_1_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD0108++0x3 line.long 0x0 "AXIM_1_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD1008++0x3 line.long 0x0 "IB21_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD1108++0x3 line.long 0x0 "IB21_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD2008++0x3 line.long 0x0 "AXIF_1_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD2108++0x3 line.long 0x0 "AXIF_1_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD3008++0x3 line.long 0x0 "IN_NOC_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD3108++0x3 line.long 0x0 "IN_NOC_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD4008++0x3 line.long 0x0 "IB20_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD4108++0x3 line.long 0x0 "IB20_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD5008++0x3 line.long 0x0 "IB22_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD5108++0x3 line.long 0x0 "IB22_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD6008++0x3 line.long 0x0 "IB19_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD6108++0x3 line.long 0x0 "IB19_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD7008++0x3 line.long 0x0 "IN_NOC_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD7108++0x3 line.long 0x0 "IN_NOC_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" tree.end tree "REMAPDEFAULT_AXIM_1_IA_RD" base ad:0x7B100000 wgroup.long 0x0++0x3 line.long 0x0 "REMAP," bitfld.long 0x0 0. "REMAP,REMAP" "0,1" rgroup.long 0x1FD0++0x2F line.long 0x0 "PERIPH_ID_4," hexmask.long.byte 0x0 0.--7. 1. "PERIPH_ID_4,PERIPH_ID_4" line.long 0x4 "PERIPH_ID_5," hexmask.long.byte 0x4 0.--7. 1. "PERIPH_ID_5,PERIPH_ID_5" line.long 0x8 "PERIPH_ID_6," hexmask.long.byte 0x8 0.--7. 1. "PERIPH_ID_6,PERIPH_ID_6" line.long 0xC "PERIPH_ID_7," hexmask.long.byte 0xC 0.--7. 1. "PERIPH_ID_7,PERIPH_ID_7" line.long 0x10 "PERIPH_ID_0," hexmask.long.byte 0x10 0.--7. 1. "PERIPH_ID_0,PERIPH_ID_0" line.long 0x14 "PERIPH_ID_1," hexmask.long.byte 0x14 0.--7. 1. "PERIPH_ID_1,PERIPH_ID_1" line.long 0x18 "PERIPH_ID_2," hexmask.long.byte 0x18 0.--7. 1. "PERIPH_ID_2,PERIPH_ID_2" line.long 0x1C "PERIPH_ID_3," hexmask.long.byte 0x1C 4.--7. 1. "REV_AND,REV_AND" hexmask.long.byte 0x1C 0.--3. 1. "CUST_MOD_NUM,CUST_MOD_NUM" line.long 0x20 "COMP_ID_0," hexmask.long.byte 0x20 0.--7. 1. "COMP_ID_0,COMP_ID_0" line.long 0x24 "COMP_ID_1," hexmask.long.byte 0x24 0.--7. 1. "COMP_ID_1,COMP_ID_1" line.long 0x28 "COMP_ID_2," hexmask.long.byte 0x28 0.--7. 1. "COMP_ID_2,COMP_ID_2" line.long 0x2C "COMP_ID_3," hexmask.long.byte 0x2C 0.--7. 1. "COMP_ID_3,COMP_ID_3" group.long 0x42108++0x3 line.long 0x0 "AXIM_0_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x43108++0x3 line.long 0x0 "AXIM_1_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x44108++0x3 line.long 0x0 "AXIF_0_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x45108++0x3 line.long 0x0 "AXIF_1_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x46108++0x7 line.long 0x0 "IN_NOC_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" line.long 0x4 "IN_NOC_IA_QOS_CNTL," bitfld.long 0x4 20. "MODE_AR_FC,MODE_AR_FC" "0,1" bitfld.long 0x4 16. "MODE_AW_FC,MODE_AW_FC" "0,1" bitfld.long 0x4 4. "EN_AR_FC,EN_AR_FC" "0,1" bitfld.long 0x4 3. "EN_AW_FC,EN_AW_FC" "0,1" bitfld.long 0x4 2. "EN_AWAR_RATE,EN_AWAR_RATE" "0,1" bitfld.long 0x4 1. "EN_AR_RATE,EN_AR_RATE" "0,1" newline bitfld.long 0x4 0. "EN_AW_RATE,EN_AW_RATE" "0,1" group.long 0x46118++0x23 line.long 0x0 "IN_NOC_IA_AW_P," hexmask.long.byte 0x0 24.--31. 1. "AW_P,AW_P" line.long 0x4 "IN_NOC_IA_AW_B," hexmask.long.word 0x4 0.--15. 1. "AW_B,AW_B" line.long 0x8 "IN_NOC_IA_AW_R," hexmask.long.word 0x8 20.--31. 1. "AW_R,AW_R" line.long 0xC "IN_NOC_IA_AR_P," hexmask.long.byte 0xC 24.--31. 1. "AR_P,AR_P" line.long 0x10 "IN_NOC_IA_AR_B," hexmask.long.word 0x10 0.--15. 1. "AR_B,AR_B" line.long 0x14 "IN_NOC_IA_AR_R," hexmask.long.word 0x14 20.--31. 1. "AR_R,AR_R" line.long 0x18 "IN_NOC_IA_TARGET_FC," hexmask.long.word 0x18 16.--27. 1. "AR_TARGET_FC,AR_TARGET_FC" hexmask.long.word 0x18 0.--11. 1. "AW_TARGET_FC,AW_TARGET_FC" line.long 0x1C "IN_NOC_IA_KI_FC," bitfld.long 0x1C 8.--10. "AR_KI_FC,AR_KI_FC" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "AW_KI_FC,AW_KI_FC" "0,1,2,3,4,5,6,7" line.long 0x20 "IN_NOC_IA_QOS_RANGE," hexmask.long.byte 0x20 24.--27. 1. "AR_MAX_QOS,AR_MAX_QOS" hexmask.long.byte 0x20 16.--19. 1. "AR_MIN_QOS,AR_MIN_QOS" hexmask.long.byte 0x20 8.--11. 1. "AW_MAX_QOS,AW_MAX_QOS" hexmask.long.byte 0x20 0.--3. 1. "AW_MIN_QOS,AW_MIN_QOS" group.long 0xC2008++0x3 line.long 0x0 "AXIM_0_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC2108++0x3 line.long 0x0 "AXIM_0_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC3008++0x3 line.long 0x0 "AXIM_1_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC3108++0x3 line.long 0x0 "AXIM_1_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC4008++0x3 line.long 0x0 "IN_NOC_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC4108++0x3 line.long 0x0 "IN_NOC_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC5008++0x3 line.long 0x0 "AXIM_0_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC5108++0x3 line.long 0x0 "AXIM_0_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC6008++0x3 line.long 0x0 "AXIM_1_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC6108++0x3 line.long 0x0 "AXIM_1_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC7008++0x3 line.long 0x0 "AXIM_0_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC7108++0x3 line.long 0x0 "AXIM_0_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC8008++0x3 line.long 0x0 "AXIM_1_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC8108++0x3 line.long 0x0 "AXIM_1_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC9008++0x3 line.long 0x0 "AXIF_0_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC9108++0x3 line.long 0x0 "AXIF_0_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCA008++0x3 line.long 0x0 "IB17_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCA108++0x3 line.long 0x0 "IB17_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCB008++0x3 line.long 0x0 "AXIM_0_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCB108++0x3 line.long 0x0 "AXIM_0_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCC008++0x3 line.long 0x0 "IB18_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCC108++0x3 line.long 0x0 "IB18_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCD008++0x3 line.long 0x0 "AXIF_1_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCD108++0x3 line.long 0x0 "AXIF_1_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCE008++0x3 line.long 0x0 "AXIF_0_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCE108++0x3 line.long 0x0 "AXIF_0_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCF008++0x3 line.long 0x0 "IN_NOC_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCF108++0x3 line.long 0x0 "IN_NOC_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD0008++0x3 line.long 0x0 "AXIM_1_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD0108++0x3 line.long 0x0 "AXIM_1_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD1008++0x3 line.long 0x0 "IB21_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD1108++0x3 line.long 0x0 "IB21_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD2008++0x3 line.long 0x0 "AXIF_1_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD2108++0x3 line.long 0x0 "AXIF_1_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD3008++0x3 line.long 0x0 "IN_NOC_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD3108++0x3 line.long 0x0 "IN_NOC_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD4008++0x3 line.long 0x0 "IB20_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD4108++0x3 line.long 0x0 "IB20_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD5008++0x3 line.long 0x0 "IB22_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD5108++0x3 line.long 0x0 "IB22_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD6008++0x3 line.long 0x0 "IB19_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD6108++0x3 line.long 0x0 "IB19_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD7008++0x3 line.long 0x0 "IN_NOC_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD7108++0x3 line.long 0x0 "IN_NOC_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" tree.end tree.end tree "REMAPDEFAULT_IN_NOC_IA_RD" tree "NIC400_LOCALKITE1_REMAPDEFAULT_IN_NOC_IA_RD" base ad:0x7B200000 wgroup.long 0x0++0x3 line.long 0x0 "REMAP," bitfld.long 0x0 0. "REMAP,REMAP" "0,1" rgroup.long 0x1FD0++0x2F line.long 0x0 "PERIPH_ID_4," hexmask.long.byte 0x0 0.--7. 1. "PERIPH_ID_4,PERIPH_ID_4" line.long 0x4 "PERIPH_ID_5," hexmask.long.byte 0x4 0.--7. 1. "PERIPH_ID_5,PERIPH_ID_5" line.long 0x8 "PERIPH_ID_6," hexmask.long.byte 0x8 0.--7. 1. "PERIPH_ID_6,PERIPH_ID_6" line.long 0xC "PERIPH_ID_7," hexmask.long.byte 0xC 0.--7. 1. "PERIPH_ID_7,PERIPH_ID_7" line.long 0x10 "PERIPH_ID_0," hexmask.long.byte 0x10 0.--7. 1. "PERIPH_ID_0,PERIPH_ID_0" line.long 0x14 "PERIPH_ID_1," hexmask.long.byte 0x14 0.--7. 1. "PERIPH_ID_1,PERIPH_ID_1" line.long 0x18 "PERIPH_ID_2," hexmask.long.byte 0x18 0.--7. 1. "PERIPH_ID_2,PERIPH_ID_2" line.long 0x1C "PERIPH_ID_3," hexmask.long.byte 0x1C 4.--7. 1. "REV_AND,REV_AND" hexmask.long.byte 0x1C 0.--3. 1. "CUST_MOD_NUM,CUST_MOD_NUM" line.long 0x20 "COMP_ID_0," hexmask.long.byte 0x20 0.--7. 1. "COMP_ID_0,COMP_ID_0" line.long 0x24 "COMP_ID_1," hexmask.long.byte 0x24 0.--7. 1. "COMP_ID_1,COMP_ID_1" line.long 0x28 "COMP_ID_2," hexmask.long.byte 0x28 0.--7. 1. "COMP_ID_2,COMP_ID_2" line.long 0x2C "COMP_ID_3," hexmask.long.byte 0x2C 0.--7. 1. "COMP_ID_3,COMP_ID_3" group.long 0x42108++0x3 line.long 0x0 "AXIM_0_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x43108++0x3 line.long 0x0 "AXIM_1_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x44108++0x3 line.long 0x0 "AXIF_0_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x45108++0x3 line.long 0x0 "AXIF_1_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x46108++0x7 line.long 0x0 "IN_NOC_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" line.long 0x4 "IN_NOC_IA_QOS_CNTL," bitfld.long 0x4 20. "MODE_AR_FC,MODE_AR_FC" "0,1" bitfld.long 0x4 16. "MODE_AW_FC,MODE_AW_FC" "0,1" bitfld.long 0x4 4. "EN_AR_FC,EN_AR_FC" "0,1" bitfld.long 0x4 3. "EN_AW_FC,EN_AW_FC" "0,1" bitfld.long 0x4 2. "EN_AWAR_RATE,EN_AWAR_RATE" "0,1" bitfld.long 0x4 1. "EN_AR_RATE,EN_AR_RATE" "0,1" newline bitfld.long 0x4 0. "EN_AW_RATE,EN_AW_RATE" "0,1" group.long 0x46118++0x23 line.long 0x0 "IN_NOC_IA_AW_P," hexmask.long.byte 0x0 24.--31. 1. "AW_P,AW_P" line.long 0x4 "IN_NOC_IA_AW_B," hexmask.long.word 0x4 0.--15. 1. "AW_B,AW_B" line.long 0x8 "IN_NOC_IA_AW_R," hexmask.long.word 0x8 20.--31. 1. "AW_R,AW_R" line.long 0xC "IN_NOC_IA_AR_P," hexmask.long.byte 0xC 24.--31. 1. "AR_P,AR_P" line.long 0x10 "IN_NOC_IA_AR_B," hexmask.long.word 0x10 0.--15. 1. "AR_B,AR_B" line.long 0x14 "IN_NOC_IA_AR_R," hexmask.long.word 0x14 20.--31. 1. "AR_R,AR_R" line.long 0x18 "IN_NOC_IA_TARGET_FC," hexmask.long.word 0x18 16.--27. 1. "AR_TARGET_FC,AR_TARGET_FC" hexmask.long.word 0x18 0.--11. 1. "AW_TARGET_FC,AW_TARGET_FC" line.long 0x1C "IN_NOC_IA_KI_FC," bitfld.long 0x1C 8.--10. "AR_KI_FC,AR_KI_FC" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "AW_KI_FC,AW_KI_FC" "0,1,2,3,4,5,6,7" line.long 0x20 "IN_NOC_IA_QOS_RANGE," hexmask.long.byte 0x20 24.--27. 1. "AR_MAX_QOS,AR_MAX_QOS" hexmask.long.byte 0x20 16.--19. 1. "AR_MIN_QOS,AR_MIN_QOS" hexmask.long.byte 0x20 8.--11. 1. "AW_MAX_QOS,AW_MAX_QOS" hexmask.long.byte 0x20 0.--3. 1. "AW_MIN_QOS,AW_MIN_QOS" group.long 0xC2008++0x3 line.long 0x0 "AXIM_0_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC2108++0x3 line.long 0x0 "AXIM_0_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC3008++0x3 line.long 0x0 "AXIM_1_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC3108++0x3 line.long 0x0 "AXIM_1_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC4008++0x3 line.long 0x0 "IN_NOC_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC4108++0x3 line.long 0x0 "IN_NOC_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC5008++0x3 line.long 0x0 "AXIM_0_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC5108++0x3 line.long 0x0 "AXIM_0_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC6008++0x3 line.long 0x0 "AXIM_1_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC6108++0x3 line.long 0x0 "AXIM_1_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC7008++0x3 line.long 0x0 "AXIM_0_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC7108++0x3 line.long 0x0 "AXIM_0_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC8008++0x3 line.long 0x0 "AXIM_1_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC8108++0x3 line.long 0x0 "AXIM_1_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC9008++0x3 line.long 0x0 "AXIF_0_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC9108++0x3 line.long 0x0 "AXIF_0_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCA008++0x3 line.long 0x0 "IB17_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCA108++0x3 line.long 0x0 "IB17_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCB008++0x3 line.long 0x0 "AXIM_0_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCB108++0x3 line.long 0x0 "AXIM_0_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCC008++0x3 line.long 0x0 "IB18_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCC108++0x3 line.long 0x0 "IB18_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCD008++0x3 line.long 0x0 "AXIF_1_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCD108++0x3 line.long 0x0 "AXIF_1_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCE008++0x3 line.long 0x0 "AXIF_0_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCE108++0x3 line.long 0x0 "AXIF_0_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCF008++0x3 line.long 0x0 "IN_NOC_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCF108++0x3 line.long 0x0 "IN_NOC_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD0008++0x3 line.long 0x0 "AXIM_1_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD0108++0x3 line.long 0x0 "AXIM_1_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD1008++0x3 line.long 0x0 "IB21_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD1108++0x3 line.long 0x0 "IB21_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD2008++0x3 line.long 0x0 "AXIF_1_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD2108++0x3 line.long 0x0 "AXIF_1_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD3008++0x3 line.long 0x0 "IN_NOC_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD3108++0x3 line.long 0x0 "IN_NOC_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD4008++0x3 line.long 0x0 "IB20_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD4108++0x3 line.long 0x0 "IB20_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD5008++0x3 line.long 0x0 "IB22_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD5108++0x3 line.long 0x0 "IB22_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD6008++0x3 line.long 0x0 "IB19_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD6108++0x3 line.long 0x0 "IB19_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD7008++0x3 line.long 0x0 "IN_NOC_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD7108++0x3 line.long 0x0 "IN_NOC_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" tree.end tree "NIC400_LOCALKITE2_REMAPDEFAULT_IN_NOC_IA_RD" base ad:0x7B300000 wgroup.long 0x0++0x3 line.long 0x0 "REMAP," bitfld.long 0x0 0. "REMAP,REMAP" "0,1" rgroup.long 0x1FD0++0x2F line.long 0x0 "PERIPH_ID_4," hexmask.long.byte 0x0 0.--7. 1. "PERIPH_ID_4,PERIPH_ID_4" line.long 0x4 "PERIPH_ID_5," hexmask.long.byte 0x4 0.--7. 1. "PERIPH_ID_5,PERIPH_ID_5" line.long 0x8 "PERIPH_ID_6," hexmask.long.byte 0x8 0.--7. 1. "PERIPH_ID_6,PERIPH_ID_6" line.long 0xC "PERIPH_ID_7," hexmask.long.byte 0xC 0.--7. 1. "PERIPH_ID_7,PERIPH_ID_7" line.long 0x10 "PERIPH_ID_0," hexmask.long.byte 0x10 0.--7. 1. "PERIPH_ID_0,PERIPH_ID_0" line.long 0x14 "PERIPH_ID_1," hexmask.long.byte 0x14 0.--7. 1. "PERIPH_ID_1,PERIPH_ID_1" line.long 0x18 "PERIPH_ID_2," hexmask.long.byte 0x18 0.--7. 1. "PERIPH_ID_2,PERIPH_ID_2" line.long 0x1C "PERIPH_ID_3," hexmask.long.byte 0x1C 4.--7. 1. "REV_AND,REV_AND" hexmask.long.byte 0x1C 0.--3. 1. "CUST_MOD_NUM,CUST_MOD_NUM" line.long 0x20 "COMP_ID_0," hexmask.long.byte 0x20 0.--7. 1. "COMP_ID_0,COMP_ID_0" line.long 0x24 "COMP_ID_1," hexmask.long.byte 0x24 0.--7. 1. "COMP_ID_1,COMP_ID_1" line.long 0x28 "COMP_ID_2," hexmask.long.byte 0x28 0.--7. 1. "COMP_ID_2,COMP_ID_2" line.long 0x2C "COMP_ID_3," hexmask.long.byte 0x2C 0.--7. 1. "COMP_ID_3,COMP_ID_3" group.long 0x42108++0x3 line.long 0x0 "AXIM_0_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x43108++0x3 line.long 0x0 "AXIM_1_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x44108++0x3 line.long 0x0 "AXIF_0_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x45108++0x3 line.long 0x0 "AXIF_1_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x46108++0x7 line.long 0x0 "IN_NOC_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" line.long 0x4 "IN_NOC_IA_QOS_CNTL," bitfld.long 0x4 20. "MODE_AR_FC,MODE_AR_FC" "0,1" bitfld.long 0x4 16. "MODE_AW_FC,MODE_AW_FC" "0,1" bitfld.long 0x4 4. "EN_AR_FC,EN_AR_FC" "0,1" bitfld.long 0x4 3. "EN_AW_FC,EN_AW_FC" "0,1" bitfld.long 0x4 2. "EN_AWAR_RATE,EN_AWAR_RATE" "0,1" bitfld.long 0x4 1. "EN_AR_RATE,EN_AR_RATE" "0,1" newline bitfld.long 0x4 0. "EN_AW_RATE,EN_AW_RATE" "0,1" group.long 0x46118++0x23 line.long 0x0 "IN_NOC_IA_AW_P," hexmask.long.byte 0x0 24.--31. 1. "AW_P,AW_P" line.long 0x4 "IN_NOC_IA_AW_B," hexmask.long.word 0x4 0.--15. 1. "AW_B,AW_B" line.long 0x8 "IN_NOC_IA_AW_R," hexmask.long.word 0x8 20.--31. 1. "AW_R,AW_R" line.long 0xC "IN_NOC_IA_AR_P," hexmask.long.byte 0xC 24.--31. 1. "AR_P,AR_P" line.long 0x10 "IN_NOC_IA_AR_B," hexmask.long.word 0x10 0.--15. 1. "AR_B,AR_B" line.long 0x14 "IN_NOC_IA_AR_R," hexmask.long.word 0x14 20.--31. 1. "AR_R,AR_R" line.long 0x18 "IN_NOC_IA_TARGET_FC," hexmask.long.word 0x18 16.--27. 1. "AR_TARGET_FC,AR_TARGET_FC" hexmask.long.word 0x18 0.--11. 1. "AW_TARGET_FC,AW_TARGET_FC" line.long 0x1C "IN_NOC_IA_KI_FC," bitfld.long 0x1C 8.--10. "AR_KI_FC,AR_KI_FC" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "AW_KI_FC,AW_KI_FC" "0,1,2,3,4,5,6,7" line.long 0x20 "IN_NOC_IA_QOS_RANGE," hexmask.long.byte 0x20 24.--27. 1. "AR_MAX_QOS,AR_MAX_QOS" hexmask.long.byte 0x20 16.--19. 1. "AR_MIN_QOS,AR_MIN_QOS" hexmask.long.byte 0x20 8.--11. 1. "AW_MAX_QOS,AW_MAX_QOS" hexmask.long.byte 0x20 0.--3. 1. "AW_MIN_QOS,AW_MIN_QOS" group.long 0xC2008++0x3 line.long 0x0 "AXIM_0_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC2108++0x3 line.long 0x0 "AXIM_0_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC3008++0x3 line.long 0x0 "AXIM_1_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC3108++0x3 line.long 0x0 "AXIM_1_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC4008++0x3 line.long 0x0 "IN_NOC_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC4108++0x3 line.long 0x0 "IN_NOC_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC5008++0x3 line.long 0x0 "AXIM_0_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC5108++0x3 line.long 0x0 "AXIM_0_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC6008++0x3 line.long 0x0 "AXIM_1_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC6108++0x3 line.long 0x0 "AXIM_1_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC7008++0x3 line.long 0x0 "AXIM_0_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC7108++0x3 line.long 0x0 "AXIM_0_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC8008++0x3 line.long 0x0 "AXIM_1_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC8108++0x3 line.long 0x0 "AXIM_1_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC9008++0x3 line.long 0x0 "AXIF_0_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC9108++0x3 line.long 0x0 "AXIF_0_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCA008++0x3 line.long 0x0 "IB17_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCA108++0x3 line.long 0x0 "IB17_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCB008++0x3 line.long 0x0 "AXIM_0_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCB108++0x3 line.long 0x0 "AXIM_0_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCC008++0x3 line.long 0x0 "IB18_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCC108++0x3 line.long 0x0 "IB18_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCD008++0x3 line.long 0x0 "AXIF_1_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCD108++0x3 line.long 0x0 "AXIF_1_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCE008++0x3 line.long 0x0 "AXIF_0_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCE108++0x3 line.long 0x0 "AXIF_0_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCF008++0x3 line.long 0x0 "IN_NOC_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCF108++0x3 line.long 0x0 "IN_NOC_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD0008++0x3 line.long 0x0 "AXIM_1_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD0108++0x3 line.long 0x0 "AXIM_1_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD1008++0x3 line.long 0x0 "IB21_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD1108++0x3 line.long 0x0 "IB21_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD2008++0x3 line.long 0x0 "AXIF_1_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD2108++0x3 line.long 0x0 "AXIF_1_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD3008++0x3 line.long 0x0 "IN_NOC_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD3108++0x3 line.long 0x0 "IN_NOC_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD4008++0x3 line.long 0x0 "IB20_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD4108++0x3 line.long 0x0 "IB20_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD5008++0x3 line.long 0x0 "IB22_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD5108++0x3 line.long 0x0 "IB22_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD6008++0x3 line.long 0x0 "IB19_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD6108++0x3 line.long 0x0 "IB19_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD7008++0x3 line.long 0x0 "IN_NOC_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD7108++0x3 line.long 0x0 "IN_NOC_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" tree.end tree "REMAPDEFAULT_IN_NOC_IA_RD" base ad:0x7B100000 wgroup.long 0x0++0x3 line.long 0x0 "REMAP," bitfld.long 0x0 0. "REMAP,REMAP" "0,1" rgroup.long 0x1FD0++0x2F line.long 0x0 "PERIPH_ID_4," hexmask.long.byte 0x0 0.--7. 1. "PERIPH_ID_4,PERIPH_ID_4" line.long 0x4 "PERIPH_ID_5," hexmask.long.byte 0x4 0.--7. 1. "PERIPH_ID_5,PERIPH_ID_5" line.long 0x8 "PERIPH_ID_6," hexmask.long.byte 0x8 0.--7. 1. "PERIPH_ID_6,PERIPH_ID_6" line.long 0xC "PERIPH_ID_7," hexmask.long.byte 0xC 0.--7. 1. "PERIPH_ID_7,PERIPH_ID_7" line.long 0x10 "PERIPH_ID_0," hexmask.long.byte 0x10 0.--7. 1. "PERIPH_ID_0,PERIPH_ID_0" line.long 0x14 "PERIPH_ID_1," hexmask.long.byte 0x14 0.--7. 1. "PERIPH_ID_1,PERIPH_ID_1" line.long 0x18 "PERIPH_ID_2," hexmask.long.byte 0x18 0.--7. 1. "PERIPH_ID_2,PERIPH_ID_2" line.long 0x1C "PERIPH_ID_3," hexmask.long.byte 0x1C 4.--7. 1. "REV_AND,REV_AND" hexmask.long.byte 0x1C 0.--3. 1. "CUST_MOD_NUM,CUST_MOD_NUM" line.long 0x20 "COMP_ID_0," hexmask.long.byte 0x20 0.--7. 1. "COMP_ID_0,COMP_ID_0" line.long 0x24 "COMP_ID_1," hexmask.long.byte 0x24 0.--7. 1. "COMP_ID_1,COMP_ID_1" line.long 0x28 "COMP_ID_2," hexmask.long.byte 0x28 0.--7. 1. "COMP_ID_2,COMP_ID_2" line.long 0x2C "COMP_ID_3," hexmask.long.byte 0x2C 0.--7. 1. "COMP_ID_3,COMP_ID_3" group.long 0x42108++0x3 line.long 0x0 "AXIM_0_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x43108++0x3 line.long 0x0 "AXIM_1_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x44108++0x3 line.long 0x0 "AXIF_0_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x45108++0x3 line.long 0x0 "AXIF_1_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0x46108++0x7 line.long 0x0 "IN_NOC_IA_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" line.long 0x4 "IN_NOC_IA_QOS_CNTL," bitfld.long 0x4 20. "MODE_AR_FC,MODE_AR_FC" "0,1" bitfld.long 0x4 16. "MODE_AW_FC,MODE_AW_FC" "0,1" bitfld.long 0x4 4. "EN_AR_FC,EN_AR_FC" "0,1" bitfld.long 0x4 3. "EN_AW_FC,EN_AW_FC" "0,1" bitfld.long 0x4 2. "EN_AWAR_RATE,EN_AWAR_RATE" "0,1" bitfld.long 0x4 1. "EN_AR_RATE,EN_AR_RATE" "0,1" newline bitfld.long 0x4 0. "EN_AW_RATE,EN_AW_RATE" "0,1" group.long 0x46118++0x23 line.long 0x0 "IN_NOC_IA_AW_P," hexmask.long.byte 0x0 24.--31. 1. "AW_P,AW_P" line.long 0x4 "IN_NOC_IA_AW_B," hexmask.long.word 0x4 0.--15. 1. "AW_B,AW_B" line.long 0x8 "IN_NOC_IA_AW_R," hexmask.long.word 0x8 20.--31. 1. "AW_R,AW_R" line.long 0xC "IN_NOC_IA_AR_P," hexmask.long.byte 0xC 24.--31. 1. "AR_P,AR_P" line.long 0x10 "IN_NOC_IA_AR_B," hexmask.long.word 0x10 0.--15. 1. "AR_B,AR_B" line.long 0x14 "IN_NOC_IA_AR_R," hexmask.long.word 0x14 20.--31. 1. "AR_R,AR_R" line.long 0x18 "IN_NOC_IA_TARGET_FC," hexmask.long.word 0x18 16.--27. 1. "AR_TARGET_FC,AR_TARGET_FC" hexmask.long.word 0x18 0.--11. 1. "AW_TARGET_FC,AW_TARGET_FC" line.long 0x1C "IN_NOC_IA_KI_FC," bitfld.long 0x1C 8.--10. "AR_KI_FC,AR_KI_FC" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "AW_KI_FC,AW_KI_FC" "0,1,2,3,4,5,6,7" line.long 0x20 "IN_NOC_IA_QOS_RANGE," hexmask.long.byte 0x20 24.--27. 1. "AR_MAX_QOS,AR_MAX_QOS" hexmask.long.byte 0x20 16.--19. 1. "AR_MIN_QOS,AR_MIN_QOS" hexmask.long.byte 0x20 8.--11. 1. "AW_MAX_QOS,AW_MAX_QOS" hexmask.long.byte 0x20 0.--3. 1. "AW_MIN_QOS,AW_MIN_QOS" group.long 0xC2008++0x3 line.long 0x0 "AXIM_0_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC2108++0x3 line.long 0x0 "AXIM_0_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC3008++0x3 line.long 0x0 "AXIM_1_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC3108++0x3 line.long 0x0 "AXIM_1_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC4008++0x3 line.long 0x0 "IN_NOC_TO_RAM_0_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC4108++0x3 line.long 0x0 "IN_NOC_TO_RAM_0_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC5008++0x3 line.long 0x0 "AXIM_0_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC5108++0x3 line.long 0x0 "AXIM_0_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC6008++0x3 line.long 0x0 "AXIM_1_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC6108++0x3 line.long 0x0 "AXIM_1_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC7008++0x3 line.long 0x0 "AXIM_0_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC7108++0x3 line.long 0x0 "AXIM_0_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC8008++0x3 line.long 0x0 "AXIM_1_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC8108++0x3 line.long 0x0 "AXIM_1_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xC9008++0x3 line.long 0x0 "AXIF_0_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xC9108++0x3 line.long 0x0 "AXIF_0_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCA008++0x3 line.long 0x0 "IB17_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCA108++0x3 line.long 0x0 "IB17_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCB008++0x3 line.long 0x0 "AXIM_0_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCB108++0x3 line.long 0x0 "AXIM_0_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCC008++0x3 line.long 0x0 "IB18_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCC108++0x3 line.long 0x0 "IB18_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCD008++0x3 line.long 0x0 "AXIF_1_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCD108++0x3 line.long 0x0 "AXIF_1_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCE008++0x3 line.long 0x0 "AXIF_0_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCE108++0x3 line.long 0x0 "AXIF_0_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xCF008++0x3 line.long 0x0 "IN_NOC_TO_RAM_1_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xCF108++0x3 line.long 0x0 "IN_NOC_TO_RAM_1_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD0008++0x3 line.long 0x0 "AXIM_1_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD0108++0x3 line.long 0x0 "AXIM_1_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD1008++0x3 line.long 0x0 "IB21_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD1108++0x3 line.long 0x0 "IB21_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD2008++0x3 line.long 0x0 "AXIF_1_TO_OUT_NOC_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD2108++0x3 line.long 0x0 "AXIF_1_TO_OUT_NOC_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD3008++0x3 line.long 0x0 "IN_NOC_TO_FLASH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD3108++0x3 line.long 0x0 "IN_NOC_TO_FLASH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD4008++0x3 line.long 0x0 "IB20_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD4108++0x3 line.long 0x0 "IB20_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD5008++0x3 line.long 0x0 "IB22_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD5108++0x3 line.long 0x0 "IB22_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD6008++0x3 line.long 0x0 "IB19_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD6108++0x3 line.long 0x0 "IB19_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" group.long 0xD7008++0x3 line.long 0x0 "IN_NOC_TO_GPV_SWITCH_FN_MOD_ISS_BM," bitfld.long 0x0 0.--1. "FN_MOD_ISS_BM,FN_MOD_ISS_BM" "0,1,2,3" group.long 0xD7108++0x3 line.long 0x0 "IN_NOC_TO_GPV_SWITCH_FN_MOD," bitfld.long 0x0 0.--1. "FN_MOD,FN_MOD" "0,1,2,3" tree.end tree.end tree.end tree "RTC_API (Real Time Clock / Autonomous Periodic Interrupt)" base ad:0x72340000 group.long 0x0++0xB line.long 0x0 "RTCSUPV,RTC Supervisor Control register" bitfld.long 0x0 31. "SUPV,RTC Supervisor Bit" "0: All registers are accessible in both user as..,1: All other registers are accessible in supervisor.." line.long 0x4 "RTCC,RTC Control register" bitfld.long 0x4 31. "CNTEN,Counter Enable" "0: Counter disabled and reset,1: Counter enabled" bitfld.long 0x4 30. "RTCIE,RTC Interrupt Enable" "0: RTC interrupts disabled,1: RTC interrupts enabled" newline bitfld.long 0x4 29. "FRZEN,Freeze Enable Bit" "0: Counter running in debug mode,1: Counter stops (freezes) in debug mode" bitfld.long 0x4 28. "ROVREN,Counter Roll Over Interrupt Enable" "0: RTC rollover interrupt disabled,1: RTC rollover interrupt enabled" newline bitfld.long 0x4 15. "APIEN,Autonomous Periodic Interrupt Enable" "0: API disabled,1: API enabled" bitfld.long 0x4 14. "APIIE,API Interrupt Enable" "0: API interrupts disabled,1: API interrupts enabled" newline bitfld.long 0x4 12.--13. "CLKSEL,Clock Select" "0: SXOSC,1: LPRC prescaled by 8,2: IRCOSC,?" bitfld.long 0x4 11. "DIV512EN,Divide by 512 enable" "0: Divide by 512 is disabled,1: Divide by 512 is enabled" newline bitfld.long 0x4 10. "DIV32EN,Divide by 32 enable" "0: Divide by 32 is disabled,1: Divide by 32 is enabled" bitfld.long 0x4 0. "TRIG_EN,Trigger enable" "0: Trigger enable is disabled,1: Trigger enable is enabled" line.long 0x8 "RTCS,RTC Status register" bitfld.long 0x8 29. "RTCF,RTC Interrupt Flag" "0: RTC counter is not equal to RTCVAL,1: RTC counter matches RTCVAL" bitfld.long 0x8 18. "INV_RTC,Invalid RTC write" "0,1" newline bitfld.long 0x8 17. "INV_API,Invalid APIVAL write" "0,1" bitfld.long 0x8 16. "INV_ANL,Invalid ANLCMP write" "0,1" newline bitfld.long 0x8 13. "APIF,API Interrupt Flag" "0: No API interrupt,1: API interrupt" bitfld.long 0x8 10. "ROVRF,Counter Roll Over Interrupt Flag" "0: RTC has not rolled over,1: RTC has rolled over" rgroup.long 0xC++0x3 line.long 0x0 "RTCCNT,RTC Counter register" hexmask.long 0x0 0.--31. 1. "RTCCNT,RTC Counter Value" group.long 0x10++0xB line.long 0x0 "RTC_APIVAL,API Compare Value register" hexmask.long 0x0 0.--31. 1. "APIVAL,API Compare Value" line.long 0x4 "RTC_RTCVAL,RTC Compare Value register" hexmask.long 0x4 0.--31. 1. "RTCVAL,RTC Compare Value" line.long 0x8 "RTC_ANLCMP_CNT,RTC Analogue Comparator Count register" hexmask.long 0x8 0.--31. 1. "ANLCMP,The trigger_en_out pulse is generated (after the generation of wakeup_api signal) as per the number of API clocks programmed into this register." tree.end tree "SAR_ADC (Successive Approximation Register Analog-to-Digital Converter)" base ad:0x0 tree "SAR_ADC_9BIT_0" base ad:0x70430000 group.long 0x0++0x3 line.long 0x0 "MCR,Main Configuration Register" bitfld.long 0x0 31. "OWREN,This bit enables or disables the functionality to overwrite unread converted data in ICDR TCDR ECDR registers." "0: Prevents overwrite of unread converted data new..,1: Enables converted data to be overwritten by a.." bitfld.long 0x0 30. "WLSIDE,Write left/right-aligned" "0: The conversion data in ICDR TCDR ECDR registers..,1: Conversion data is left-aligned (from 15 to (15.." newline bitfld.long 0x0 29. "MODE,One Shot/Scan" "0: One Shot Mode: Configures the normal conversion..,1: Scan Mode: Configures continuous chain.." bitfld.long 0x0 28. "XSTRTEN,This bit enables or disables the external start signal to initial a normal conversion. This can be used to synchronize multiple SARADCs concurrently." "0: External start signal is disabled,1: External start signal high level will start a.." newline bitfld.long 0x0 27. "NSTART,Setting this bit starts the chain or scan conversion. Resetting this bit during scan mode causes the current chain conversion to finish then stops the operation." "0: Cause the current chain conversion to finish and..,1: Starts the chain or scan conversion" bitfld.long 0x0 26. "NTRGEN,NTRGEN" "0: Normal trigger disabled to start a normal..,1: Normal trigger enabled to start a normal.." newline bitfld.long 0x0 24.--25. "NEDGESEL,NEDGESEL" "0: Falling edge of normal trigger is selected,1: Rising edge of normal trigger is selected,2: Both rising and falling edges of normal trigger..,3: Both rising and falling edges of normal trigger.." bitfld.long 0x0 23. "JSTART,Setting this bit will start the configured injected analog channels to be converted by software. Resetting this bit has no effect as the injected chain conversion cannot be interrupted." "0: Writting '0' has not effect,1: Starts the injected chain conversion" newline bitfld.long 0x0 22. "JTRGEN,JTRGEN" "0: Injection trigger disabled for channel injection..,1: Injection trigger enabled for channel injection" bitfld.long 0x0 20.--21. "JEDGESEL,JEDGESEL" "0: Falling edge of injection trigger is selected,1: Rising edge of injection trigger is selected,?,3: Both rising and falling edges of injection.." newline bitfld.long 0x0 19. "JTRGSEQ,JTRGSEQ" "0: Injection trigger sequence mode is disabled,1: Injection trigger sequence mode is enabled" bitfld.long 0x0 15. "WTRIGOUT,This control bit enables the Trigger on every threshold crossover event (crossing of Lower/Upper thresholds) of each WDG monitor to external trigger port (up to 16 ports for up to 16 WDGs)." "0: Trigger outputs disabled,1: Trigger ouputs enabled" newline bitfld.long 0x0 7. "ABORTCHAIN,When this bit is set the ongoing Chain Conversion is aborted. This bit is reset by hardware as soon as a new conversion is requested." "0: Conversion is not affected,1: Aborts the ongoing chain conversion" bitfld.long 0x0 6. "ABORT,When this bit is set the ongoing conversion is aborted and a new conversion is invoked. This bit is reset by hardware as soon as a new conversion is invoked." "0: Conversion is not affected,1: Aborts the ongoing conversion" newline bitfld.long 0x0 4. "FRZ,This bit enables to stop the SARADC conversions at the end of current channel conversion when SoC enters debug mode." "0: Conversions are not stopped,1: When SoC enters debug mode further conversions.." bitfld.long 0x0 2. "FCE,This bit enables the fast comparison mode for upcoming channel conversions." "0: Fast comparision mode disabled,1: Fast comparision mode enabled" newline bitfld.long 0x0 1. "EDCSELF,This bit selects the format for 3-bit output port ipp_decode_extch used as select line for external decode channel 8:1 muxes. The last three bits of external channel number are passed as is (if value 0) or converted to gray code (if value 1) and.." "0: Binary format,1: Gray code format" bitfld.long 0x0 0. "PWDN,When this bit is set the analog module is requested to enter Power Down mode." "0: SARADC is in normal mode,1: SARADC has been requested to power down" rgroup.long 0x4++0x3 line.long 0x0 "MSR,Main Status Register" bitfld.long 0x0 27. "NSTART,This status bit is used to signal that a normal conversion is ongoing." "0: Normal conversion is not taking place,1: Normal conversion is ongoing or the normal.." bitfld.long 0x0 23. "JSTART,This status bit is used to signal that an injected conversion is ongoing." "0: Injected conversion is not taking place,1: Injected conversion is ongoing" newline bitfld.long 0x0 18. "JABORTCHAIN,This status bit is used to signal that an Injected conversion chain has been aborted. This bit is reset when a new conversion starts." "0: Last injected conversion chain has not been..,1: Last injected conversion chain has been aborted" hexmask.long.byte 0x0 8.--15. 1. "CHADDR,Channel under measure address" newline bitfld.long 0x0 0.--2. "ADCSTATUS,The value of this parameter depends on ADC status. While requesting an external channel conversion SARADC digital interface needs to wait for a fixed time determined by DSD bitfield of DSDR before proceeding to actual sampling phase." "0: IDLE,1: Power-down,2: Wait state,?,4: Sample,?,6: Conversion,?" group.long 0x10++0x7 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 3. "JEOC,This bit indicates the end of conversion for an injected channel." "0: End of conversion of injected channel has not..,1: End of conversion of injected channel has.." bitfld.long 0x0 2. "JECH,This bit indicates the end of conversion for an injected chain." "0: End of conversion of injected chain has not..,1: End of conversion of injected chain has occurred.." newline bitfld.long 0x0 1. "NEOC,This bit indicates the end of conversion for a normal channel." "0: End of conversion of normal channel has not..,1: End of conversion of normal channel has occurred.." bitfld.long 0x0 0. "NECH,This bit indicates the end of conversion for an normal chain." "0: End of conversion of normal chain has not..,1: End of conversion of normal chain has occurred.." line.long 0x4 "ICIPR0,Internal Channel Interrupt Pending Register 0" bitfld.long 0x4 8. "EOC_CH8,End of conversion interrupt pending bit for channel 8" "0: End of conversion for CH[8] has not occured,1: End of conversion for CH[8] has occured" bitfld.long 0x4 7. "EOC_CH7,End of conversion interrupt pending bit for channel 7" "0: End of conversion for CH[7] has not occured,1: End of conversion for CH[7] has occured" group.long 0x20++0x7 line.long 0x0 "IMR,Interrupt Mask Register" bitfld.long 0x0 3. "MSKJEOC,Mask bit for JEOC" "0: JEOC interrupt is disabled,1: JEOC interrupt is enabled" bitfld.long 0x0 2. "MSKJECH,Mask bit for JECH" "0: JECH interrupt is disabled,1: JECH interrupt is enabled" newline bitfld.long 0x0 1. "MSKNEOC,Mask bit for NEOC" "0: NEOC interrupt is disabled,1: NEOC interrupt is enabled" bitfld.long 0x0 0. "MSKNECH,Mask bit for NECH" "0: NECH interrupt is disabled,1: NECH interrupt is enabled" line.long 0x4 "ICIMR0,Internal Channel Interrupt Mask Register 0" bitfld.long 0x4 8. "IM_CH8,Interrupt mask bit for channel 8" "0: Interupt for CH[8] is disabled,1: Interupt for CH[8] is enabled" bitfld.long 0x4 7. "IM_CH7,Interrupt mask bit for channel 7" "0: Interupt for CH[7] is disabled,1: Interupt for CH[7] is enabled" group.long 0x30++0xB line.long 0x0 "WTISR,Watchdog Threshold Interrupt Status Register" bitfld.long 0x0 3. "WDG1H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 1." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 2. "WDG1L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 1." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x0 1. "WDG0H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 0." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 0. "WDG0L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 0." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." line.long 0x4 "WTIMR,Watchdog Threshold Interrupt Mask Register" bitfld.long 0x4 3. "MSKWDG1H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG1H is disabled.,1: Inetrupt for WDG1H is enabled." bitfld.long 0x4 2. "MSKWDG1L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG1L is disabled.,1: Inetrupt for WDG1L is enabled." newline bitfld.long 0x4 1. "MSKWDG0H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG0H is disabled.,1: Inetrupt for WDG0H is enabled." bitfld.long 0x4 0. "MSKWDG0L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG0L is disabled.,1: Inetrupt for WDG0L is enabled." line.long 0x8 "WLTCR,Watchdog Level Trigger Configuration Register" bitfld.long 0x8 1. "LTMW1,LTMW1" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0x8 0. "LTMW0,LTMW0" "0: Level Trigger Mode,1: Hysteresis Mode" group.long 0x60++0x7 line.long 0x0 "WTHRHLR0,Watchdog Threshold Register 0" hexmask.long.word 0x0 16.--25. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x0 0.--9. 1. "THRL,Low threshold value for channel x" line.long 0x4 "WTHRHLR1,Watchdog Threshold Register 1" hexmask.long.word 0x4 16.--25. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x4 0.--9. 1. "THRL,Low threshold value for channel x" group.long 0x94++0x13 line.long 0x0 "CTR0,Conversion Timing Register 0" bitfld.long 0x0 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x0 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x4 "CTR1,Conversion Timing Register 1" bitfld.long 0x4 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x4 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x4 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x8 "CTR2,Conversion Timing Register 2" bitfld.long 0x8 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x8 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x8 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0xC "CTR3,Conversion Timing Register 3" bitfld.long 0xC 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0xC 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0xC 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x10 "ICNCMR0,Internal Channel Normal Conversion Mask Register 0" bitfld.long 0x10 8. "NCE_CH8,NCE_CH8" "0: Normal conversion is disabled for CH[8].,1: Normal conversion is enabled for CH[8]." bitfld.long 0x10 7. "NCE_CH7,NCE_CH7" "0: Normal conversion is disabled for CH[7].,1: Normal conversion is enabled for CH[7]." group.long 0xB4++0x3 line.long 0x0 "ICJCMR0,Internal Channel Injected Conversion Mask Register 0" bitfld.long 0x0 8. "JCE_CH8,JCE_CH8" "0: Injected conversion is disabled for CH[8].,1: Injected conversion is enabled for CH[8]." bitfld.long 0x0 7. "JCE_CH7,JCE_CH7" "0: Injected conversion is disabled for CH[7].,1: Injected conversion is enabled for CH[7]." group.long 0xC8++0x3 line.long 0x0 "PDEDR,Power Down Exit Delay Register" hexmask.long.byte 0x0 0.--7. 1. "PDED,Defines the delay between the power-down bit reset and the starting of conversion." group.long 0x11C++0x7 line.long 0x0 "ICDR7,Internal Channel Data Register 7" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4 "ICDR8,Internal Channel Data Register 8" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" group.long 0x2B0++0x7 line.long 0x0 "ICWSELR0,Internal Channel Watchdog Select Register 0" bitfld.long 0x0 28. "WSEL_CH7,0000 THRHLR0 register is selected" "0,1" line.long 0x4 "ICWSELR1,Internal Channel Watchdog Select Register 1" bitfld.long 0x4 0. "WSEL_CH8,0000 THRHLR0 register is selected" "0,1" group.long 0x2E0++0x3 line.long 0x0 "ICWENR0,Internal Channel Watchdog Enable Register 0" bitfld.long 0x0 8. "WEN_CH8,WEN_CH8" "0: Watchdog feature is disabled for CH[8],1: Watchdog feature is enabled fir CH[8]" bitfld.long 0x0 7. "WEN_CH7,WEN_CH7" "0: Watchdog feature is disabled for CH[7],1: Watchdog feature is enabled fir CH[7]" group.long 0x2F0++0x3 line.long 0x0 "ICAWORR0,Internal Channel Analog Watchdog Out of Range Register 0" bitfld.long 0x0 8. "AWOR_CH8,Analog watchdog out of range status for channel 8 provided corresponding WEN_CH8 bit is set." "0: CH[8] converted data is not out of range..,1: CH[8] converted data is out of range determined.." bitfld.long 0x0 7. "AWOR_CH7,Analog watchdog out of range status for channel 7 provided corresponding WEN_CH7 bit is set." "0: CH[7] converted data is not out of range..,1: CH[7] converted data is out of range determined.." tree.end tree "SAR_ADC_9BIT_2" base ad:0x70438000 group.long 0x0++0x3 line.long 0x0 "MCR,Main Configuration Register" bitfld.long 0x0 31. "OWREN,This bit enables or disables the functionality to overwrite unread converted data in ICDR TCDR ECDR registers." "0: Prevents overwrite of unread converted data new..,1: Enables converted data to be overwritten by a.." bitfld.long 0x0 30. "WLSIDE,Write left/right-aligned" "0: The conversion data in ICDR TCDR ECDR registers..,1: Conversion data is left-aligned (from 15 to (15.." newline bitfld.long 0x0 29. "MODE,One Shot/Scan" "0: One Shot Mode: Configures the normal conversion..,1: Scan Mode: Configures continuous chain.." bitfld.long 0x0 28. "XSTRTEN,This bit enables or disables the external start signal to initial a normal conversion. This can be used to synchronize multiple SARADCs concurrently." "0: External start signal is disabled,1: External start signal high level will start a.." newline bitfld.long 0x0 27. "NSTART,Setting this bit starts the chain or scan conversion. Resetting this bit during scan mode causes the current chain conversion to finish then stops the operation." "0: Cause the current chain conversion to finish and..,1: Starts the chain or scan conversion" bitfld.long 0x0 26. "NTRGEN,NTRGEN" "0: Normal trigger disabled to start a normal..,1: Normal trigger enabled to start a normal.." newline bitfld.long 0x0 24.--25. "NEDGESEL,NEDGESEL" "0: Falling edge of normal trigger is selected,1: Rising edge of normal trigger is selected,2: Both rising and falling edges of normal trigger..,3: Both rising and falling edges of normal trigger.." bitfld.long 0x0 23. "JSTART,Setting this bit will start the configured injected analog channels to be converted by software. Resetting this bit has no effect as the injected chain conversion cannot be interrupted." "0: Writting '0' has not effect,1: Starts the injected chain conversion" newline bitfld.long 0x0 22. "JTRGEN,JTRGEN" "0: Injection trigger disabled for channel injection..,1: Injection trigger enabled for channel injection" bitfld.long 0x0 20.--21. "JEDGESEL,JEDGESEL" "0: Falling edge of injection trigger is selected,1: Rising edge of injection trigger is selected,?,3: Both rising and falling edges of injection.." newline bitfld.long 0x0 19. "JTRGSEQ,JTRGSEQ" "0: Injection trigger sequence mode is disabled,1: Injection trigger sequence mode is enabled" bitfld.long 0x0 15. "WTRIGOUT,This control bit enables the Trigger on every threshold crossover event (crossing of Lower/Upper thresholds) of each WDG monitor to external trigger port (up to 16 ports for up to 16 WDGs)." "0: Trigger outputs disabled,1: Trigger ouputs enabled" newline bitfld.long 0x0 7. "ABORTCHAIN,When this bit is set the ongoing Chain Conversion is aborted. This bit is reset by hardware as soon as a new conversion is requested." "0: Conversion is not affected,1: Aborts the ongoing chain conversion" bitfld.long 0x0 6. "ABORT,When this bit is set the ongoing conversion is aborted and a new conversion is invoked. This bit is reset by hardware as soon as a new conversion is invoked." "0: Conversion is not affected,1: Aborts the ongoing conversion" newline bitfld.long 0x0 4. "FRZ,This bit enables to stop the SARADC conversions at the end of current channel conversion when SoC enters debug mode." "0: Conversions are not stopped,1: When SoC enters debug mode further conversions.." bitfld.long 0x0 2. "FCE,This bit enables the fast comparison mode for upcoming channel conversions." "0: Fast comparision mode disabled,1: Fast comparision mode enabled" newline bitfld.long 0x0 1. "EDCSELF,This bit selects the format for 3-bit output port ipp_decode_extch used as select line for external decode channel 8:1 muxes. The last three bits of external channel number are passed as is (if value 0) or converted to gray code (if value 1) and.." "0: Binary format,1: Gray code format" bitfld.long 0x0 0. "PWDN,When this bit is set the analog module is requested to enter Power Down mode." "0: SARADC is in normal mode,1: SARADC has been requested to power down" rgroup.long 0x4++0x3 line.long 0x0 "MSR,Main Status Register" bitfld.long 0x0 27. "NSTART,This status bit is used to signal that a normal conversion is ongoing." "0: Normal conversion is not taking place,1: Normal conversion is ongoing or the normal.." bitfld.long 0x0 23. "JSTART,This status bit is used to signal that an injected conversion is ongoing." "0: Injected conversion is not taking place,1: Injected conversion is ongoing" newline bitfld.long 0x0 18. "JABORTCHAIN,This status bit is used to signal that an Injected conversion chain has been aborted. This bit is reset when a new conversion starts." "0: Last injected conversion chain has not been..,1: Last injected conversion chain has been aborted" hexmask.long.byte 0x0 8.--15. 1. "CHADDR,Channel under measure address" newline bitfld.long 0x0 0.--2. "ADCSTATUS,The value of this parameter depends on ADC status. While requesting an external channel conversion SARADC digital interface needs to wait for a fixed time determined by DSD bitfield of DSDR before proceeding to actual sampling phase." "0: IDLE,1: Power-down,2: Wait state,?,4: Sample,?,6: Conversion,?" group.long 0x10++0x7 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 3. "JEOC,This bit indicates the end of conversion for an injected channel." "0: End of conversion of injected channel has not..,1: End of conversion of injected channel has.." bitfld.long 0x0 2. "JECH,This bit indicates the end of conversion for an injected chain." "0: End of conversion of injected chain has not..,1: End of conversion of injected chain has occurred.." newline bitfld.long 0x0 1. "NEOC,This bit indicates the end of conversion for a normal channel." "0: End of conversion of normal channel has not..,1: End of conversion of normal channel has occurred.." bitfld.long 0x0 0. "NECH,This bit indicates the end of conversion for an normal chain." "0: End of conversion of normal chain has not..,1: End of conversion of normal chain has occurred.." line.long 0x4 "ICIPR0,Internal Channel Interrupt Pending Register 0" bitfld.long 0x4 17. "EOC_CH17,End of conversion interrupt pending bit for channel 17" "0: End of conversion for CH[17] has not occured,1: End of conversion for CH[17] has occured" bitfld.long 0x4 16. "EOC_CH16,End of conversion interrupt pending bit for channel 16" "0: End of conversion for CH[16] has not occured,1: End of conversion for CH[16] has occured" group.long 0x20++0x7 line.long 0x0 "IMR,Interrupt Mask Register" bitfld.long 0x0 3. "MSKJEOC,Mask bit for JEOC" "0: JEOC interrupt is disabled,1: JEOC interrupt is enabled" bitfld.long 0x0 2. "MSKJECH,Mask bit for JECH" "0: JECH interrupt is disabled,1: JECH interrupt is enabled" newline bitfld.long 0x0 1. "MSKNEOC,Mask bit for NEOC" "0: NEOC interrupt is disabled,1: NEOC interrupt is enabled" bitfld.long 0x0 0. "MSKNECH,Mask bit for NECH" "0: NECH interrupt is disabled,1: NECH interrupt is enabled" line.long 0x4 "ICIMR0,Internal Channel Interrupt Mask Register 0" bitfld.long 0x4 17. "IM_CH17,Interrupt mask bit for channel 17" "0: Interupt for CH[17] is disabled,1: Interupt for CH[17] is enabled" bitfld.long 0x4 16. "IM_CH16,Interrupt mask bit for channel 16" "0: Interupt for CH[16] is disabled,1: Interupt for CH[16] is enabled" group.long 0x30++0xB line.long 0x0 "WTISR,Watchdog Threshold Interrupt Status Register" bitfld.long 0x0 3. "WDG1H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 1." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 2. "WDG1L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 1." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x0 1. "WDG0H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 0." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 0. "WDG0L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 0." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." line.long 0x4 "WTIMR,Watchdog Threshold Interrupt Mask Register" bitfld.long 0x4 3. "MSKWDG1H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG1H is disabled.,1: Inetrupt for WDG1H is enabled." bitfld.long 0x4 2. "MSKWDG1L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG1L is disabled.,1: Inetrupt for WDG1L is enabled." newline bitfld.long 0x4 1. "MSKWDG0H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG0H is disabled.,1: Inetrupt for WDG0H is enabled." bitfld.long 0x4 0. "MSKWDG0L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG0L is disabled.,1: Inetrupt for WDG0L is enabled." line.long 0x8 "WLTCR,Watchdog Level Trigger Configuration Register" bitfld.long 0x8 1. "LTMW1,LTMW1" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0x8 0. "LTMW0,LTMW0" "0: Level Trigger Mode,1: Hysteresis Mode" group.long 0x60++0x7 line.long 0x0 "WTHRHLR0,Watchdog Threshold Register 0" hexmask.long.word 0x0 16.--25. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x0 0.--9. 1. "THRL,Low threshold value for channel x" line.long 0x4 "WTHRHLR1,Watchdog Threshold Register 1" hexmask.long.word 0x4 16.--25. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x4 0.--9. 1. "THRL,Low threshold value for channel x" group.long 0x94++0x13 line.long 0x0 "CTR0,Conversion Timing Register 0" bitfld.long 0x0 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x0 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x4 "CTR1,Conversion Timing Register 1" bitfld.long 0x4 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x4 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x4 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x8 "CTR2,Conversion Timing Register 2" bitfld.long 0x8 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x8 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x8 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0xC "CTR3,Conversion Timing Register 3" bitfld.long 0xC 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0xC 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0xC 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x10 "ICNCMR0,Internal Channel Normal Conversion Mask Register 0" bitfld.long 0x10 17. "NCE_CH17,NCE_CH17" "0: Normal conversion is disabled for CH[17].,1: Normal conversion is enabled for CH[17]." bitfld.long 0x10 16. "NCE_CH16,NCE_CH16" "0: Normal conversion is disabled for CH[16].,1: Normal conversion is enabled for CH[16]." group.long 0xB4++0x3 line.long 0x0 "ICJCMR0,Internal Channel Injected Conversion Mask Register 0" bitfld.long 0x0 17. "JCE_CH17,JCE_CH17" "0: Injected conversion is disabled for CH[17].,1: Injected conversion is enabled for CH[17]." bitfld.long 0x0 16. "JCE_CH16,JCE_CH16" "0: Injected conversion is disabled for CH[16].,1: Injected conversion is enabled for CH[16]." group.long 0xC8++0x3 line.long 0x0 "PDEDR,Power Down Exit Delay Register" hexmask.long.byte 0x0 0.--7. 1. "PDED,Defines the delay between the power-down bit reset and the starting of conversion." group.long 0x140++0x7 line.long 0x0 "ICDR16,Internal Channel Data Register 16" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4 "ICDR17,Internal Channel Data Register 17" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" group.long 0x2B8++0x3 line.long 0x0 "ICWSELR2,Internal Channel Watchdog Select Register 2" bitfld.long 0x0 4. "WSEL_CH17,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x0 0. "WSEL_CH16,0000 THRHLR0 register is selected" "0,1" group.long 0x2E0++0x3 line.long 0x0 "ICWENR0,Internal Channel Watchdog Enable Register 0" bitfld.long 0x0 17. "WEN_CH17,WEN_CH17" "0: Watchdog feature is disabled for CH[17],1: Watchdog feature is enabled fir CH[17]" bitfld.long 0x0 16. "WEN_CH16,WEN_CH16" "0: Watchdog feature is disabled for CH[16],1: Watchdog feature is enabled fir CH[16]" group.long 0x2F0++0x3 line.long 0x0 "ICAWORR0,Internal Channel Analog Watchdog Out of Range Register 0" bitfld.long 0x0 17. "AWOR_CH17,Analog watchdog out of range status for channel 17 provided corresponding WEN_CH17 bit is set." "0: CH[17] converted data is not out of range..,1: CH[17] converted data is out of range determined.." bitfld.long 0x0 16. "AWOR_CH16,Analog watchdog out of range status for channel 16 provided corresponding WEN_CH16 bit is set." "0: CH[16] converted data is not out of range..,1: CH[16] converted data is out of range determined.." tree.end tree "SAR_ADC_9BIT_3" base ad:0x70A38000 group.long 0x0++0x3 line.long 0x0 "MCR,Main Configuration Register" bitfld.long 0x0 31. "OWREN,This bit enables or disables the functionality to overwrite unread converted data in ICDR TCDR ECDR registers." "0: Prevents overwrite of unread converted data new..,1: Enables converted data to be overwritten by a.." bitfld.long 0x0 30. "WLSIDE,Write left/right-aligned" "0: The conversion data in ICDR TCDR ECDR registers..,1: Conversion data is left-aligned (from 15 to (15.." newline bitfld.long 0x0 29. "MODE,One Shot/Scan" "0: One Shot Mode: Configures the normal conversion..,1: Scan Mode: Configures continuous chain.." bitfld.long 0x0 28. "XSTRTEN,This bit enables or disables the external start signal to initial a normal conversion. This can be used to synchronize multiple SARADCs concurrently." "0: External start signal is disabled,1: External start signal high level will start a.." newline bitfld.long 0x0 27. "NSTART,Setting this bit starts the chain or scan conversion. Resetting this bit during scan mode causes the current chain conversion to finish then stops the operation." "0: Cause the current chain conversion to finish and..,1: Starts the chain or scan conversion" bitfld.long 0x0 26. "NTRGEN,NTRGEN" "0: Normal trigger disabled to start a normal..,1: Normal trigger enabled to start a normal.." newline bitfld.long 0x0 24.--25. "NEDGESEL,NEDGESEL" "0: Falling edge of normal trigger is selected,1: Rising edge of normal trigger is selected,2: Both rising and falling edges of normal trigger..,3: Both rising and falling edges of normal trigger.." bitfld.long 0x0 23. "JSTART,Setting this bit will start the configured injected analog channels to be converted by software. Resetting this bit has no effect as the injected chain conversion cannot be interrupted." "0: Writting '0' has not effect,1: Starts the injected chain conversion" newline bitfld.long 0x0 22. "JTRGEN,JTRGEN" "0: Injection trigger disabled for channel injection..,1: Injection trigger enabled for channel injection" bitfld.long 0x0 20.--21. "JEDGESEL,JEDGESEL" "0: Falling edge of injection trigger is selected,1: Rising edge of injection trigger is selected,?,3: Both rising and falling edges of injection.." newline bitfld.long 0x0 19. "JTRGSEQ,JTRGSEQ" "0: Injection trigger sequence mode is disabled,1: Injection trigger sequence mode is enabled" bitfld.long 0x0 15. "WTRIGOUT,This control bit enables the Trigger on every threshold crossover event (crossing of Lower/Upper thresholds) of each WDG monitor to external trigger port (up to 16 ports for up to 16 WDGs)." "0: Trigger outputs disabled,1: Trigger ouputs enabled" newline bitfld.long 0x0 7. "ABORTCHAIN,When this bit is set the ongoing Chain Conversion is aborted. This bit is reset by hardware as soon as a new conversion is requested." "0: Conversion is not affected,1: Aborts the ongoing chain conversion" bitfld.long 0x0 6. "ABORT,When this bit is set the ongoing conversion is aborted and a new conversion is invoked. This bit is reset by hardware as soon as a new conversion is invoked." "0: Conversion is not affected,1: Aborts the ongoing conversion" newline bitfld.long 0x0 4. "FRZ,This bit enables to stop the SARADC conversions at the end of current channel conversion when SoC enters debug mode." "0: Conversions are not stopped,1: When SoC enters debug mode further conversions.." bitfld.long 0x0 2. "FCE,This bit enables the fast comparison mode for upcoming channel conversions." "0: Fast comparision mode disabled,1: Fast comparision mode enabled" newline bitfld.long 0x0 1. "EDCSELF,This bit selects the format for 3-bit output port ipp_decode_extch used as select line for external decode channel 8:1 muxes. The last three bits of external channel number are passed as is (if value 0) or converted to gray code (if value 1) and.." "0: Binary format,1: Gray code format" bitfld.long 0x0 0. "PWDN,When this bit is set the analog module is requested to enter Power Down mode." "0: SARADC is in normal mode,1: SARADC has been requested to power down" rgroup.long 0x4++0x3 line.long 0x0 "MSR,Main Status Register" bitfld.long 0x0 27. "NSTART,This status bit is used to signal that a normal conversion is ongoing." "0: Normal conversion is not taking place,1: Normal conversion is ongoing or the normal.." bitfld.long 0x0 23. "JSTART,This status bit is used to signal that an injected conversion is ongoing." "0: Injected conversion is not taking place,1: Injected conversion is ongoing" newline bitfld.long 0x0 18. "JABORTCHAIN,This status bit is used to signal that an Injected conversion chain has been aborted. This bit is reset when a new conversion starts." "0: Last injected conversion chain has not been..,1: Last injected conversion chain has been aborted" hexmask.long.byte 0x0 8.--15. 1. "CHADDR,Channel under measure address" newline bitfld.long 0x0 0.--2. "ADCSTATUS,The value of this parameter depends on ADC status. While requesting an external channel conversion SARADC digital interface needs to wait for a fixed time determined by DSD bitfield of DSDR before proceeding to actual sampling phase." "0: IDLE,1: Power-down,2: Wait state,?,4: Sample,?,6: Conversion,?" group.long 0x10++0xB line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 3. "JEOC,This bit indicates the end of conversion for an injected channel." "0: End of conversion of injected channel has not..,1: End of conversion of injected channel has.." bitfld.long 0x0 2. "JECH,This bit indicates the end of conversion for an injected chain." "0: End of conversion of injected chain has not..,1: End of conversion of injected chain has occurred.." newline bitfld.long 0x0 1. "NEOC,This bit indicates the end of conversion for a normal channel." "0: End of conversion of normal channel has not..,1: End of conversion of normal channel has occurred.." bitfld.long 0x0 0. "NECH,This bit indicates the end of conversion for an normal chain." "0: End of conversion of normal chain has not..,1: End of conversion of normal chain has occurred.." line.long 0x4 "ICIPR0,Internal Channel Interrupt Pending Register 0" bitfld.long 0x4 29. "EOC_CH29,End of conversion interrupt pending bit for channel 29" "0: End of conversion for CH[29] has not occured,1: End of conversion for CH[29] has occured" line.long 0x8 "ICIPR1,Internal Channel Interrupt Pending Register 1" bitfld.long 0x8 0. "EOC_CH32,End of conversion interrupt pending bit for channel 32" "0: End of conversion for CH[32] has not occured,1: End of conversion for CH[32] has occured" group.long 0x20++0xB line.long 0x0 "IMR,Interrupt Mask Register" bitfld.long 0x0 3. "MSKJEOC,Mask bit for JEOC" "0: JEOC interrupt is disabled,1: JEOC interrupt is enabled" bitfld.long 0x0 2. "MSKJECH,Mask bit for JECH" "0: JECH interrupt is disabled,1: JECH interrupt is enabled" newline bitfld.long 0x0 1. "MSKNEOC,Mask bit for NEOC" "0: NEOC interrupt is disabled,1: NEOC interrupt is enabled" bitfld.long 0x0 0. "MSKNECH,Mask bit for NECH" "0: NECH interrupt is disabled,1: NECH interrupt is enabled" line.long 0x4 "ICIMR0,Internal Channel Interrupt Mask Register 0" bitfld.long 0x4 29. "IM_CH29,Interrupt mask bit for channel 29" "0: Interupt for CH[29] is disabled,1: Interupt for CH[29] is enabled" line.long 0x8 "ICIMR1,Internal Channel Interrupt Mask Register 1" bitfld.long 0x8 0. "IM_CH32,Interrupt mask bit for channel 32" "0: Interupt for CH[32] is disabled,1: Interupt for CH[32] is enabled" group.long 0x30++0xB line.long 0x0 "WTISR,Watchdog Threshold Interrupt Status Register" bitfld.long 0x0 3. "WDG1H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 1." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 2. "WDG1L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 1." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x0 1. "WDG0H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 0." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 0. "WDG0L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 0." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." line.long 0x4 "WTIMR,Watchdog Threshold Interrupt Mask Register" bitfld.long 0x4 3. "MSKWDG1H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG1H is disabled.,1: Inetrupt for WDG1H is enabled." bitfld.long 0x4 2. "MSKWDG1L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG1L is disabled.,1: Inetrupt for WDG1L is enabled." newline bitfld.long 0x4 1. "MSKWDG0H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG0H is disabled.,1: Inetrupt for WDG0H is enabled." bitfld.long 0x4 0. "MSKWDG0L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG0L is disabled.,1: Inetrupt for WDG0L is enabled." line.long 0x8 "WLTCR,Watchdog Level Trigger Configuration Register" bitfld.long 0x8 1. "LTMW1,LTMW1" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0x8 0. "LTMW0,LTMW0" "0: Level Trigger Mode,1: Hysteresis Mode" group.long 0x60++0x7 line.long 0x0 "WTHRHLR0,Watchdog Threshold Register 0" hexmask.long.word 0x0 16.--25. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x0 0.--9. 1. "THRL,Low threshold value for channel x" line.long 0x4 "WTHRHLR1,Watchdog Threshold Register 1" hexmask.long.word 0x4 16.--25. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x4 0.--9. 1. "THRL,Low threshold value for channel x" group.long 0x94++0x17 line.long 0x0 "CTR0,Conversion Timing Register 0" bitfld.long 0x0 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x0 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x4 "CTR1,Conversion Timing Register 1" bitfld.long 0x4 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x4 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x4 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x8 "CTR2,Conversion Timing Register 2" bitfld.long 0x8 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x8 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x8 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0xC "CTR3,Conversion Timing Register 3" bitfld.long 0xC 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0xC 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0xC 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x10 "ICNCMR0,Internal Channel Normal Conversion Mask Register 0" bitfld.long 0x10 29. "NCE_CH29,NCE_CH29" "0: Normal conversion is disabled for CH[29].,1: Normal conversion is enabled for CH[29]." line.long 0x14 "ICNCMR1,Internal Channel Normal Conversion Mask Register 1" bitfld.long 0x14 0. "NCE_CH32,NCE_CH32" "0: Normal conversion is disabled for CH[32].,1: Normal conversion is enabled for CH[32]." group.long 0xB4++0x7 line.long 0x0 "ICJCMR0,Internal Channel Injected Conversion Mask Register 0" bitfld.long 0x0 29. "JCE_CH29,JCE_CH29" "0: Injected conversion is disabled for CH[29].,1: Injected conversion is enabled for CH[29]." line.long 0x4 "ICJCMR1,Internal Channel Injected Conversion Mask Register 1" bitfld.long 0x4 0. "JCE_CH32,JCE_CH32" "0: Injected conversion is disabled for CH[32].,1: Injected conversion is enabled for CH[32]." group.long 0xC8++0x3 line.long 0x0 "PDEDR,Power Down Exit Delay Register" hexmask.long.byte 0x0 0.--7. 1. "PDED,Defines the delay between the power-down bit reset and the starting of conversion." group.long 0x174++0x3 line.long 0x0 "ICDR29,Internal Channel Data Register 29" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" group.long 0x180++0x3 line.long 0x0 "ICDR32,Internal Channel Data Register 32" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" group.long 0x2BC++0x7 line.long 0x0 "ICWSELR3,Internal Channel Watchdog Select Register 3" bitfld.long 0x0 20. "WSEL_CH29,0000 THRHLR0 register is selected" "0,1" line.long 0x4 "ICWSELR4,Internal Channel Watchdog Select Register 4" bitfld.long 0x4 0. "WSEL_CH32,0000 THRHLR0 register is selected" "0,1" group.long 0x2E0++0x7 line.long 0x0 "ICWENR0,Internal Channel Watchdog Enable Register 0" bitfld.long 0x0 29. "WEN_CH29,WEN_CH29" "0: Watchdog feature is disabled for CH[29],1: Watchdog feature is enabled fir CH[29]" line.long 0x4 "ICWENR1,Internal Channel Watchdog Enable Register 1" bitfld.long 0x4 0. "WEN_CH32,WEN_CH32" "0: Watchdog feature is disabled for CH[32],1: Watchdog feature is enabled fir CH[32]" group.long 0x2F0++0x7 line.long 0x0 "ICAWORR0,Internal Channel Analog Watchdog Out of Range Register 0" bitfld.long 0x0 29. "AWOR_CH29,Analog watchdog out of range status for channel 29 provided corresponding WEN_CH29 bit is set." "0: CH[29] converted data is not out of range..,1: CH[29] converted data is out of range determined.." line.long 0x4 "ICAWORR1,Internal Channel Analog Watchdog Out of Range Register 1" bitfld.long 0x4 0. "AWOR_CH32,Analog watchdog out of range status for channel 32 provided corresponding WEN_CH32 bit is set." "0: CH[32] converted data is not out of range..,1: CH[32] converted data is out of range determined.." tree.end tree "SAR_ADC_9BIT_6" base ad:0x70448000 group.long 0x0++0x3 line.long 0x0 "MCR,Main Configuration Register" bitfld.long 0x0 31. "OWREN,This bit enables or disables the functionality to overwrite unread converted data in ICDR TCDR ECDR registers." "0: Prevents overwrite of unread converted data new..,1: Enables converted data to be overwritten by a.." bitfld.long 0x0 30. "WLSIDE,Write left/right-aligned" "0: The conversion data in ICDR TCDR ECDR registers..,1: Conversion data is left-aligned (from 15 to (15.." newline bitfld.long 0x0 29. "MODE,One Shot/Scan" "0: One Shot Mode: Configures the normal conversion..,1: Scan Mode: Configures continuous chain.." bitfld.long 0x0 28. "XSTRTEN,This bit enables or disables the external start signal to initial a normal conversion. This can be used to synchronize multiple SARADCs concurrently." "0: External start signal is disabled,1: External start signal high level will start a.." newline bitfld.long 0x0 27. "NSTART,Setting this bit starts the chain or scan conversion. Resetting this bit during scan mode causes the current chain conversion to finish then stops the operation." "0: Cause the current chain conversion to finish and..,1: Starts the chain or scan conversion" bitfld.long 0x0 26. "NTRGEN,NTRGEN" "0: Normal trigger disabled to start a normal..,1: Normal trigger enabled to start a normal.." newline bitfld.long 0x0 24.--25. "NEDGESEL,NEDGESEL" "0: Falling edge of normal trigger is selected,1: Rising edge of normal trigger is selected,2: Both rising and falling edges of normal trigger..,3: Both rising and falling edges of normal trigger.." bitfld.long 0x0 23. "JSTART,Setting this bit will start the configured injected analog channels to be converted by software. Resetting this bit has no effect as the injected chain conversion cannot be interrupted." "0: Writting '0' has not effect,1: Starts the injected chain conversion" newline bitfld.long 0x0 22. "JTRGEN,JTRGEN" "0: Injection trigger disabled for channel injection..,1: Injection trigger enabled for channel injection" bitfld.long 0x0 20.--21. "JEDGESEL,JEDGESEL" "0: Falling edge of injection trigger is selected,1: Rising edge of injection trigger is selected,?,3: Both rising and falling edges of injection.." newline bitfld.long 0x0 19. "JTRGSEQ,JTRGSEQ" "0: Injection trigger sequence mode is disabled,1: Injection trigger sequence mode is enabled" bitfld.long 0x0 15. "WTRIGOUT,This control bit enables the Trigger on every threshold crossover event (crossing of Lower/Upper thresholds) of each WDG monitor to external trigger port (up to 16 ports for up to 16 WDGs)." "0: Trigger outputs disabled,1: Trigger ouputs enabled" newline bitfld.long 0x0 7. "ABORTCHAIN,When this bit is set the ongoing Chain Conversion is aborted. This bit is reset by hardware as soon as a new conversion is requested." "0: Conversion is not affected,1: Aborts the ongoing chain conversion" bitfld.long 0x0 6. "ABORT,When this bit is set the ongoing conversion is aborted and a new conversion is invoked. This bit is reset by hardware as soon as a new conversion is invoked." "0: Conversion is not affected,1: Aborts the ongoing conversion" newline bitfld.long 0x0 4. "FRZ,This bit enables to stop the SARADC conversions at the end of current channel conversion when SoC enters debug mode." "0: Conversions are not stopped,1: When SoC enters debug mode further conversions.." bitfld.long 0x0 2. "FCE,This bit enables the fast comparison mode for upcoming channel conversions." "0: Fast comparision mode disabled,1: Fast comparision mode enabled" newline bitfld.long 0x0 1. "EDCSELF,This bit selects the format for 3-bit output port ipp_decode_extch used as select line for external decode channel 8:1 muxes. The last three bits of external channel number are passed as is (if value 0) or converted to gray code (if value 1) and.." "0: Binary format,1: Gray code format" bitfld.long 0x0 0. "PWDN,When this bit is set the analog module is requested to enter Power Down mode." "0: SARADC is in normal mode,1: SARADC has been requested to power down" rgroup.long 0x4++0x3 line.long 0x0 "MSR,Main Status Register" bitfld.long 0x0 27. "NSTART,This status bit is used to signal that a normal conversion is ongoing." "0: Normal conversion is not taking place,1: Normal conversion is ongoing or the normal.." bitfld.long 0x0 23. "JSTART,This status bit is used to signal that an injected conversion is ongoing." "0: Injected conversion is not taking place,1: Injected conversion is ongoing" newline bitfld.long 0x0 18. "JABORTCHAIN,This status bit is used to signal that an Injected conversion chain has been aborted. This bit is reset when a new conversion starts." "0: Last injected conversion chain has not been..,1: Last injected conversion chain has been aborted" hexmask.long.byte 0x0 8.--15. 1. "CHADDR,Channel under measure address" newline bitfld.long 0x0 0.--2. "ADCSTATUS,The value of this parameter depends on ADC status. While requesting an external channel conversion SARADC digital interface needs to wait for a fixed time determined by DSD bitfield of DSDR before proceeding to actual sampling phase." "0: IDLE,1: Power-down,2: Wait state,?,4: Sample,?,6: Conversion,?" group.long 0x10++0x3 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 3. "JEOC,This bit indicates the end of conversion for an injected channel." "0: End of conversion of injected channel has not..,1: End of conversion of injected channel has.." bitfld.long 0x0 2. "JECH,This bit indicates the end of conversion for an injected chain." "0: End of conversion of injected chain has not..,1: End of conversion of injected chain has occurred.." newline bitfld.long 0x0 1. "NEOC,This bit indicates the end of conversion for a normal channel." "0: End of conversion of normal channel has not..,1: End of conversion of normal channel has occurred.." bitfld.long 0x0 0. "NECH,This bit indicates the end of conversion for an normal chain." "0: End of conversion of normal chain has not..,1: End of conversion of normal chain has occurred.." group.long 0x18++0x3 line.long 0x0 "ICIPR1,Internal Channel Interrupt Pending Register 1" bitfld.long 0x0 17. "EOC_CH49,End of conversion interrupt pending bit for channel 49" "0: End of conversion for CH[49] has not occured,1: End of conversion for CH[49] has occured" bitfld.long 0x0 16. "EOC_CH48,End of conversion interrupt pending bit for channel 48" "0: End of conversion for CH[48] has not occured,1: End of conversion for CH[48] has occured" group.long 0x20++0x3 line.long 0x0 "IMR,Interrupt Mask Register" bitfld.long 0x0 3. "MSKJEOC,Mask bit for JEOC" "0: JEOC interrupt is disabled,1: JEOC interrupt is enabled" bitfld.long 0x0 2. "MSKJECH,Mask bit for JECH" "0: JECH interrupt is disabled,1: JECH interrupt is enabled" newline bitfld.long 0x0 1. "MSKNEOC,Mask bit for NEOC" "0: NEOC interrupt is disabled,1: NEOC interrupt is enabled" bitfld.long 0x0 0. "MSKNECH,Mask bit for NECH" "0: NECH interrupt is disabled,1: NECH interrupt is enabled" group.long 0x28++0x3 line.long 0x0 "ICIMR1,Internal Channel Interrupt Mask Register 1" bitfld.long 0x0 17. "IM_CH49,Interrupt mask bit for channel 49" "0: Interupt for CH[49] is disabled,1: Interupt for CH[49] is enabled" bitfld.long 0x0 16. "IM_CH48,Interrupt mask bit for channel 48" "0: Interupt for CH[48] is disabled,1: Interupt for CH[48] is enabled" group.long 0x30++0xB line.long 0x0 "WTISR,Watchdog Threshold Interrupt Status Register" bitfld.long 0x0 3. "WDG1H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 1." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 2. "WDG1L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 1." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x0 1. "WDG0H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 0." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 0. "WDG0L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 0." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." line.long 0x4 "WTIMR,Watchdog Threshold Interrupt Mask Register" bitfld.long 0x4 3. "MSKWDG1H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG1H is disabled.,1: Inetrupt for WDG1H is enabled." bitfld.long 0x4 2. "MSKWDG1L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG1L is disabled.,1: Inetrupt for WDG1L is enabled." newline bitfld.long 0x4 1. "MSKWDG0H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG0H is disabled.,1: Inetrupt for WDG0H is enabled." bitfld.long 0x4 0. "MSKWDG0L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG0L is disabled.,1: Inetrupt for WDG0L is enabled." line.long 0x8 "WLTCR,Watchdog Level Trigger Configuration Register" bitfld.long 0x8 1. "LTMW1,LTMW1" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0x8 0. "LTMW0,LTMW0" "0: Level Trigger Mode,1: Hysteresis Mode" group.long 0x60++0x7 line.long 0x0 "WTHRHLR0,Watchdog Threshold Register 0" hexmask.long.word 0x0 16.--25. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x0 0.--9. 1. "THRL,Low threshold value for channel x" line.long 0x4 "WTHRHLR1,Watchdog Threshold Register 1" hexmask.long.word 0x4 16.--25. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x4 0.--9. 1. "THRL,Low threshold value for channel x" group.long 0x94++0xF line.long 0x0 "CTR0,Conversion Timing Register 0" bitfld.long 0x0 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x0 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x4 "CTR1,Conversion Timing Register 1" bitfld.long 0x4 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x4 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x4 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x8 "CTR2,Conversion Timing Register 2" bitfld.long 0x8 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x8 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x8 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0xC "CTR3,Conversion Timing Register 3" bitfld.long 0xC 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0xC 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0xC 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." group.long 0xA8++0x3 line.long 0x0 "ICNCMR1,Internal Channel Normal Conversion Mask Register 1" bitfld.long 0x0 17. "NCE_CH49,NCE_CH49" "0: Normal conversion is disabled for CH[49].,1: Normal conversion is enabled for CH[49]." bitfld.long 0x0 16. "NCE_CH48,NCE_CH48" "0: Normal conversion is disabled for CH[48].,1: Normal conversion is enabled for CH[48]." group.long 0xB8++0x3 line.long 0x0 "ICJCMR1,Internal Channel Injected Conversion Mask Register 1" bitfld.long 0x0 17. "JCE_CH49,JCE_CH49" "0: Injected conversion is disabled for CH[49].,1: Injected conversion is enabled for CH[49]." bitfld.long 0x0 16. "JCE_CH48,JCE_CH48" "0: Injected conversion is disabled for CH[48].,1: Injected conversion is enabled for CH[48]." group.long 0xC8++0x3 line.long 0x0 "PDEDR,Power Down Exit Delay Register" hexmask.long.byte 0x0 0.--7. 1. "PDED,Defines the delay between the power-down bit reset and the starting of conversion." group.long 0x1C0++0x7 line.long 0x0 "ICDR48,Internal Channel Data Register 48" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4 "ICDR49,Internal Channel Data Register 49" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" group.long 0x2C8++0x3 line.long 0x0 "ICWSELR6,Internal Channel Watchdog Select Register 6" bitfld.long 0x0 4. "WSEL_CH49,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x0 0. "WSEL_CH48,0000 THRHLR0 register is selected" "0,1" group.long 0x2E4++0x3 line.long 0x0 "ICWENR1,Internal Channel Watchdog Enable Register 1" bitfld.long 0x0 17. "WEN_CH49,WEN_CH49" "0: Watchdog feature is disabled for CH[49],1: Watchdog feature is enabled fir CH[49]" bitfld.long 0x0 16. "WEN_CH48,WEN_CH48" "0: Watchdog feature is disabled for CH[48],1: Watchdog feature is enabled fir CH[48]" group.long 0x2F4++0x3 line.long 0x0 "ICAWORR1,Internal Channel Analog Watchdog Out of Range Register 1" bitfld.long 0x0 17. "AWOR_CH49,Analog watchdog out of range status for channel 49 provided corresponding WEN_CH49 bit is set." "0: CH[49] converted data is not out of range..,1: CH[49] converted data is out of range determined.." bitfld.long 0x0 16. "AWOR_CH48,Analog watchdog out of range status for channel 48 provided corresponding WEN_CH48 bit is set." "0: CH[48] converted data is not out of range..,1: CH[48] converted data is out of range determined.." tree.end tree "SAR_ADC_12BIT_0" base ad:0x7028C000 group.long 0x0++0x3 line.long 0x0 "MCR,Main Configuration Register" bitfld.long 0x0 31. "OWREN,This bit enables or disables the functionality to overwrite unread converted data in ICDR TCDR ECDR registers." "0: Prevents overwrite of unread converted data new..,1: Enables converted data to be overwritten by a.." bitfld.long 0x0 30. "WLSIDE,Write left/right-aligned" "0: The conversion data in ICDR TCDR ECDR registers..,1: Conversion data is left-aligned (from 15 to (15.." newline bitfld.long 0x0 29. "MODE,One Shot/Scan" "0: One Shot Mode: Configures the normal conversion..,1: Scan Mode: Configures continuous chain.." bitfld.long 0x0 28. "XSTRTEN,This bit enables or disables the external start signal to initial a normal conversion. This can be used to synchronize multiple SARADCs concurrently." "0: External start signal is disabled,1: External start signal high level will start a.." newline bitfld.long 0x0 27. "NSTART,Setting this bit starts the chain or scan conversion. Resetting this bit during scan mode causes the current chain conversion to finish then stops the operation." "0: Cause the current chain conversion to finish and..,1: Starts the chain or scan conversion" bitfld.long 0x0 26. "NTRGEN,NTRGEN" "0: Normal trigger disabled to start a normal..,1: Normal trigger enabled to start a normal.." newline bitfld.long 0x0 24.--25. "NEDGESEL,NEDGESEL" "0: Falling edge of normal trigger is selected,1: Rising edge of normal trigger is selected,2: Both rising and falling edges of normal trigger..,3: Both rising and falling edges of normal trigger.." bitfld.long 0x0 23. "JSTART,Setting this bit will start the configured injected analog channels to be converted by software. Resetting this bit has no effect as the injected chain conversion cannot be interrupted." "0: Writting '0' has not effect,1: Starts the injected chain conversion" newline bitfld.long 0x0 22. "JTRGEN,JTRGEN" "0: Injection trigger disabled for channel injection..,1: Injection trigger enabled for channel injection" bitfld.long 0x0 20.--21. "JEDGESEL,JEDGESEL" "0: Falling edge of injection trigger is selected,1: Rising edge of injection trigger is selected,?,3: Both rising and falling edges of injection.." newline bitfld.long 0x0 19. "JTRGSEQ,JTRGSEQ" "0: Injection trigger sequence mode is disabled,1: Injection trigger sequence mode is enabled" bitfld.long 0x0 17. "CTUEN,Can be set or cleared anytime with some restriction mentioned in CTU trigger/control mode section." "0: The cross triggering unit is disabled and the..,1: The cross triggering unit is enabled and the.." newline bitfld.long 0x0 16. "CTU_MODE,This bit is present only if generic parameter CTSEN = 2 otherwise this bit is a reserved bit and always read as 0. This should be set only when ADC Digital is in powerdown mode." "0: CTU control mode is selected,1: CTU trigger mode is selected" bitfld.long 0x0 15. "WTRIGOUT,This control bit enables the Trigger on every threshold crossover event (crossing of Lower/Upper thresholds) of each WDG monitor to external trigger port (up to 16 ports for up to 16 WDGs)." "0: Trigger outputs disabled,1: Trigger ouputs enabled" newline bitfld.long 0x0 7. "ABORTCHAIN,When this bit is set the ongoing Chain Conversion is aborted. This bit is reset by hardware as soon as a new conversion is requested." "0: Conversion is not affected,1: Aborts the ongoing chain conversion" bitfld.long 0x0 6. "ABORT,When this bit is set the ongoing conversion is aborted and a new conversion is invoked. This bit is reset by hardware as soon as a new conversion is invoked." "0: Conversion is not affected,1: Aborts the ongoing conversion" newline bitfld.long 0x0 4. "FRZ,This bit enables to stop the SARADC conversions at the end of current channel conversion when SoC enters debug mode." "0: Conversions are not stopped,1: When SoC enters debug mode further conversions.." bitfld.long 0x0 2. "FCE,This bit enables the fast comparison mode for upcoming channel conversions." "0: Fast comparision mode disabled,1: Fast comparision mode enabled" newline bitfld.long 0x0 1. "EDCSELF,This bit selects the format for 3-bit output port ipp_decode_extch used as select line for external decode channel 8:1 muxes. The last three bits of external channel number are passed as is (if value 0) or converted to gray code (if value 1) and.." "0: Binary format,1: Gray code format" bitfld.long 0x0 0. "PWDN,When this bit is set the analog module is requested to enter Power Down mode." "0: SARADC is in normal mode,1: SARADC has been requested to power down" rgroup.long 0x4++0x3 line.long 0x0 "MSR,Main Status Register" bitfld.long 0x0 27. "NSTART,This status bit is used to signal that a normal conversion is ongoing." "0: Normal conversion is not taking place,1: Normal conversion is ongoing or the normal.." bitfld.long 0x0 23. "JSTART,This status bit is used to signal that an injected conversion is ongoing." "0: Injected conversion is not taking place,1: Injected conversion is ongoing" newline bitfld.long 0x0 18. "JABORTCHAIN,This status bit is used to signal that an Injected conversion chain has been aborted. This bit is reset when a new conversion starts." "0: Last injected conversion chain has not been..,1: Last injected conversion chain has been aborted" bitfld.long 0x0 16. "CTUSTART,This status bit is used to signal that a CTU conversion is ongoing. This bit is set when a CTU trigger pulse is received and the CTU conversion starts. When CTU trigger mode is enabled this bit is automatically reset when the conversion is.." "0: CTU triggered injected conversion is not taking..,1: CTU triggered injected conversion is ongoing" newline hexmask.long.byte 0x0 8.--15. 1. "CHADDR,Channel under measure address" bitfld.long 0x0 0.--2. "ADCSTATUS,The value of this parameter depends on ADC status. While requesting an external channel conversion SARADC digital interface needs to wait for a fixed time determined by DSD bitfield of DSDR before proceeding to actual sampling phase." "0: IDLE,1: Power-down,2: Wait state,?,4: Sample,?,6: Conversion,?" group.long 0x10++0x7 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CTUTRGERR,This Error Flag indicates that the next CTU trigger has been discarded as it overlapped during execution of current CTU conversion. This indicated that CTU sampling duration is less than programmed conversion time of ADC." "0: No CTU trigger overlap error condition since..,1: CTU trigger overlap error has occurred." bitfld.long 0x0 4. "EOCTU,This bit indicates the end of conversion for a CTU injected channel." "0: End of conversion of CTU triggered channel has..,1: End of conversion of CTU triggered channel has.." newline bitfld.long 0x0 3. "JEOC,This bit indicates the end of conversion for an injected channel." "0: End of conversion of injected channel has not..,1: End of conversion of injected channel has.." bitfld.long 0x0 2. "JECH,This bit indicates the end of conversion for an injected chain." "0: End of conversion of injected chain has not..,1: End of conversion of injected chain has occurred.." newline bitfld.long 0x0 1. "NEOC,This bit indicates the end of conversion for a normal channel." "0: End of conversion of normal channel has not..,1: End of conversion of normal channel has occurred.." bitfld.long 0x0 0. "NECH,This bit indicates the end of conversion for an normal chain." "0: End of conversion of normal chain has not..,1: End of conversion of normal chain has occurred.." line.long 0x4 "ICIPR0,Internal Channel Interrupt Pending Register 0" bitfld.long 0x4 7. "EOC_CH7,End of conversion interrupt pending bit for channel 7" "0: End of conversion for CH[7] has not occured,1: End of conversion for CH[7] has occured" bitfld.long 0x4 6. "EOC_CH6,End of conversion interrupt pending bit for channel 6" "0: End of conversion for CH[6] has not occured,1: End of conversion for CH[6] has occured" newline bitfld.long 0x4 5. "EOC_CH5,End of conversion interrupt pending bit for channel 5" "0: End of conversion for CH[5] has not occured,1: End of conversion for CH[5] has occured" bitfld.long 0x4 4. "EOC_CH4,End of conversion interrupt pending bit for channel 4" "0: End of conversion for CH[4] has not occured,1: End of conversion for CH[4] has occured" newline bitfld.long 0x4 3. "EOC_CH3,End of conversion interrupt pending bit for channel 3" "0: End of conversion for CH[3] has not occured,1: End of conversion for CH[3] has occured" bitfld.long 0x4 2. "EOC_CH2,End of conversion interrupt pending bit for channel 2" "0: End of conversion for CH[2] has not occured,1: End of conversion for CH[2] has occured" newline bitfld.long 0x4 1. "EOC_CH1,End of conversion interrupt pending bit for channel 1" "0: End of conversion for CH[1] has not occured,1: End of conversion for CH[1] has occured" bitfld.long 0x4 0. "EOC_CH0,End of conversion interrupt pending bit for channel 0" "0: End of conversion for CH[0] has not occured,1: End of conversion for CH[0] has occured" group.long 0x20++0x7 line.long 0x0 "IMR,Interrupt Mask Register" bitfld.long 0x0 5. "MSKCTUTRGERR,Mask bit for CTU Trigger" "0: CTUTRGERR interrupt is disabled,1: CTUTRGERR interrupt is enabled" bitfld.long 0x0 4. "MSKEOCTU,Mask bit for EOCTU" "0: EOCTU interrupt is disabled,1: EOCTU interrupt is enabled" newline bitfld.long 0x0 3. "MSKJEOC,Mask bit for JEOC" "0: JEOC interrupt is disabled,1: JEOC interrupt is enabled" bitfld.long 0x0 2. "MSKJECH,Mask bit for JECH" "0: JECH interrupt is disabled,1: JECH interrupt is enabled" newline bitfld.long 0x0 1. "MSKNEOC,Mask bit for NEOC" "0: NEOC interrupt is disabled,1: NEOC interrupt is enabled" bitfld.long 0x0 0. "MSKNECH,Mask bit for NECH" "0: NECH interrupt is disabled,1: NECH interrupt is enabled" line.long 0x4 "ICIMR0,Internal Channel Interrupt Mask Register 0" bitfld.long 0x4 7. "IM_CH7,Interrupt mask bit for channel 7" "0: Interupt for CH[7] is disabled,1: Interupt for CH[7] is enabled" bitfld.long 0x4 6. "IM_CH6,Interrupt mask bit for channel 6" "0: Interupt for CH[6] is disabled,1: Interupt for CH[6] is enabled" newline bitfld.long 0x4 5. "IM_CH5,Interrupt mask bit for channel 5" "0: Interupt for CH[5] is disabled,1: Interupt for CH[5] is enabled" bitfld.long 0x4 4. "IM_CH4,Interrupt mask bit for channel 4" "0: Interupt for CH[4] is disabled,1: Interupt for CH[4] is enabled" newline bitfld.long 0x4 3. "IM_CH3,Interrupt mask bit for channel 3" "0: Interupt for CH[3] is disabled,1: Interupt for CH[3] is enabled" bitfld.long 0x4 2. "IM_CH2,Interrupt mask bit for channel 2" "0: Interupt for CH[2] is disabled,1: Interupt for CH[2] is enabled" newline bitfld.long 0x4 1. "IM_CH1,Interrupt mask bit for channel 1" "0: Interupt for CH[1] is disabled,1: Interupt for CH[1] is enabled" bitfld.long 0x4 0. "IM_CH0,Interrupt mask bit for channel 0" "0: Interupt for CH[0] is disabled,1: Interupt for CH[0] is enabled" group.long 0x30++0xB line.long 0x0 "WTISR,Watchdog Threshold Interrupt Status Register" bitfld.long 0x0 7. "WDG3H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 3." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 6. "WDG3L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 3." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x0 5. "WDG2H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 2." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 4. "WDG2L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 2." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x0 3. "WDG1H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 1." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 2. "WDG1L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 1." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x0 1. "WDG0H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 0." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 0. "WDG0L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 0." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." line.long 0x4 "WTIMR,Watchdog Threshold Interrupt Mask Register" bitfld.long 0x4 7. "MSKWDG3H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG3H is disabled.,1: Inetrupt for WDG3H is enabled." bitfld.long 0x4 6. "MSKWDG3L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG3L is disabled.,1: Inetrupt for WDG3L is enabled." newline bitfld.long 0x4 5. "MSKWDG2H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG2H is disabled.,1: Inetrupt for WDG2H is enabled." bitfld.long 0x4 4. "MSKWDG2L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG2L is disabled.,1: Inetrupt for WDG2L is enabled." newline bitfld.long 0x4 3. "MSKWDG1H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG1H is disabled.,1: Inetrupt for WDG1H is enabled." bitfld.long 0x4 2. "MSKWDG1L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG1L is disabled.,1: Inetrupt for WDG1L is enabled." newline bitfld.long 0x4 1. "MSKWDG0H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG0H is disabled.,1: Inetrupt for WDG0H is enabled." bitfld.long 0x4 0. "MSKWDG0L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG0L is disabled.,1: Inetrupt for WDG0L is enabled." line.long 0x8 "WLTCR,Watchdog Level Trigger Configuration Register" bitfld.long 0x8 3. "LTMW3,LTMW3" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0x8 2. "LTMW2,LTMW2" "0: Level Trigger Mode,1: Hysteresis Mode" newline bitfld.long 0x8 1. "LTMW1,LTMW1" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0x8 0. "LTMW0,LTMW0" "0: Level Trigger Mode,1: Hysteresis Mode" group.long 0x40++0x7 line.long 0x0 "DMAE,DMA Enable Register" bitfld.long 0x0 1. "DCLR,DMA clear sequence enable" "0: DMA request cleared by Acknowledge from DMA..,1: DMA request cleared on read of data registers" bitfld.long 0x0 0. "DMAEN,DMA global enable" "0: DMA feature disabled,1: DMA feature enabled" line.long 0x4 "ICDSR0,Internal Channel DMA Select Register 0" bitfld.long 0x4 7. "DS_CH7,DS_CH7" "0: CH[7] is disabled to transfer data in DMA mode.,1: CH[7] is enabled to transfer data in DMA mode." bitfld.long 0x4 6. "DS_CH6,DS_CH6" "0: CH[6] is disabled to transfer data in DMA mode.,1: CH[6] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 5. "DS_CH5,DS_CH5" "0: CH[5] is disabled to transfer data in DMA mode.,1: CH[5] is enabled to transfer data in DMA mode." bitfld.long 0x4 4. "DS_CH4,DS_CH4" "0: CH[4] is disabled to transfer data in DMA mode.,1: CH[4] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 3. "DS_CH3,DS_CH3" "0: CH[3] is disabled to transfer data in DMA mode.,1: CH[3] is enabled to transfer data in DMA mode." bitfld.long 0x4 2. "DS_CH2,DS_CH2" "0: CH[2] is disabled to transfer data in DMA mode.,1: CH[2] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 1. "DS_CH1,DS_CH1" "0: CH[1] is disabled to transfer data in DMA mode.,1: CH[1] is enabled to transfer data in DMA mode." bitfld.long 0x4 0. "DS_CH0,DS_CH0" "0: CH[0] is disabled to transfer data in DMA mode.,1: CH[0] is enabled to transfer data in DMA mode." group.long 0x60++0xF line.long 0x0 "WTHRHLR0,Watchdog Threshold Register 0" hexmask.long.word 0x0 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x0 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x4 "WTHRHLR1,Watchdog Threshold Register 1" hexmask.long.word 0x4 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x4 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x8 "WTHRHLR2,Watchdog Threshold Register 2" hexmask.long.word 0x8 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x8 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0xC "WTHRHLR3,Watchdog Threshold Register 3" hexmask.long.word 0xC 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0xC 0.--11. 1. "THRL,Low threshold value for channel x" group.long 0x94++0x13 line.long 0x0 "CTR0,Conversion Timing Register 0" bitfld.long 0x0 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x0 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x4 "CTR1,Conversion Timing Register 1" bitfld.long 0x4 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x4 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x4 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x8 "CTR2,Conversion Timing Register 2" bitfld.long 0x8 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x8 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x8 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0xC "CTR3,Conversion Timing Register 3" bitfld.long 0xC 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0xC 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0xC 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x10 "ICNCMR0,Internal Channel Normal Conversion Mask Register 0" bitfld.long 0x10 7. "NCE_CH7,NCE_CH7" "0: Normal conversion is disabled for CH[7].,1: Normal conversion is enabled for CH[7]." bitfld.long 0x10 6. "NCE_CH6,NCE_CH6" "0: Normal conversion is disabled for CH[6].,1: Normal conversion is enabled for CH[6]." newline bitfld.long 0x10 5. "NCE_CH5,NCE_CH5" "0: Normal conversion is disabled for CH[5].,1: Normal conversion is enabled for CH[5]." bitfld.long 0x10 4. "NCE_CH4,NCE_CH4" "0: Normal conversion is disabled for CH[4].,1: Normal conversion is enabled for CH[4]." newline bitfld.long 0x10 3. "NCE_CH3,NCE_CH3" "0: Normal conversion is disabled for CH[3].,1: Normal conversion is enabled for CH[3]." bitfld.long 0x10 2. "NCE_CH2,NCE_CH2" "0: Normal conversion is disabled for CH[2].,1: Normal conversion is enabled for CH[2]." newline bitfld.long 0x10 1. "NCE_CH1,NCE_CH1" "0: Normal conversion is disabled for CH[1].,1: Normal conversion is enabled for CH[1]." bitfld.long 0x10 0. "NCE_CH0,NCE_CH0" "0: Normal conversion is disabled for CH[0].,1: Normal conversion is enabled for CH[0]." group.long 0xB4++0x3 line.long 0x0 "ICJCMR0,Internal Channel Injected Conversion Mask Register 0" bitfld.long 0x0 7. "JCE_CH7,JCE_CH7" "0: Injected conversion is disabled for CH[7].,1: Injected conversion is enabled for CH[7]." bitfld.long 0x0 6. "JCE_CH6,JCE_CH6" "0: Injected conversion is disabled for CH[6].,1: Injected conversion is enabled for CH[6]." newline bitfld.long 0x0 5. "JCE_CH5,JCE_CH5" "0: Injected conversion is disabled for CH[5].,1: Injected conversion is enabled for CH[5]." bitfld.long 0x0 4. "JCE_CH4,JCE_CH4" "0: Injected conversion is disabled for CH[4].,1: Injected conversion is enabled for CH[4]." newline bitfld.long 0x0 3. "JCE_CH3,JCE_CH3" "0: Injected conversion is disabled for CH[3].,1: Injected conversion is enabled for CH[3]." bitfld.long 0x0 2. "JCE_CH2,JCE_CH2" "0: Injected conversion is disabled for CH[2].,1: Injected conversion is enabled for CH[2]." newline bitfld.long 0x0 1. "JCE_CH1,JCE_CH1" "0: Injected conversion is disabled for CH[1].,1: Injected conversion is enabled for CH[1]." bitfld.long 0x0 0. "JCE_CH0,JCE_CH0" "0: Injected conversion is disabled for CH[0].,1: Injected conversion is enabled for CH[0]." group.long 0xC8++0x3 line.long 0x0 "PDEDR,Power Down Exit Delay Register" hexmask.long.byte 0x0 0.--7. 1. "PDED,Defines the delay between the power-down bit reset and the starting of conversion." group.long 0x100++0x1F line.long 0x0 "ICDR0,Internal Channel Data Register 0" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4 "ICDR1,Internal Channel Data Register 1" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x8 "ICDR2,Internal Channel Data Register 2" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x8 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xC "ICDR3,Internal Channel Data Register 3" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xC 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x10 "ICDR4,Internal Channel Data Register 4" bitfld.long 0x10 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x10 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x10 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x10 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x10 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x10 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x10 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x14 "ICDR5,Internal Channel Data Register 5" bitfld.long 0x14 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x14 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x14 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x14 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x14 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x14 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x14 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x18 "ICDR6,Internal Channel Data Register 6" bitfld.long 0x18 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x18 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x18 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x18 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x18 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x18 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x18 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x1C "ICDR7,Internal Channel Data Register 7" bitfld.long 0x1C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x1C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x1C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x1C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x1C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x1C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x1C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" group.long 0x2B0++0x3 line.long 0x0 "ICWSELR0,Internal Channel Watchdog Select Register 0" bitfld.long 0x0 28.--29. "WSEL_CH7,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH6,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH5,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH4,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 12.--13. "WSEL_CH3,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 8.--9. "WSEL_CH2,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 4.--5. "WSEL_CH1,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 0.--1. "WSEL_CH0,0000 THRHLR0 register is selected" "0,1,2,3" group.long 0x2E0++0x3 line.long 0x0 "ICWENR0,Internal Channel Watchdog Enable Register 0" bitfld.long 0x0 7. "WEN_CH7,WEN_CH7" "0: Watchdog feature is disabled for CH[7],1: Watchdog feature is enabled fir CH[7]" bitfld.long 0x0 6. "WEN_CH6,WEN_CH6" "0: Watchdog feature is disabled for CH[6],1: Watchdog feature is enabled fir CH[6]" newline bitfld.long 0x0 5. "WEN_CH5,WEN_CH5" "0: Watchdog feature is disabled for CH[5],1: Watchdog feature is enabled fir CH[5]" bitfld.long 0x0 4. "WEN_CH4,WEN_CH4" "0: Watchdog feature is disabled for CH[4],1: Watchdog feature is enabled fir CH[4]" newline bitfld.long 0x0 3. "WEN_CH3,WEN_CH3" "0: Watchdog feature is disabled for CH[3],1: Watchdog feature is enabled fir CH[3]" bitfld.long 0x0 2. "WEN_CH2,WEN_CH2" "0: Watchdog feature is disabled for CH[2],1: Watchdog feature is enabled fir CH[2]" newline bitfld.long 0x0 1. "WEN_CH1,WEN_CH1" "0: Watchdog feature is disabled for CH[1],1: Watchdog feature is enabled fir CH[1]" bitfld.long 0x0 0. "WEN_CH0,WEN_CH0" "0: Watchdog feature is disabled for CH[0],1: Watchdog feature is enabled fir CH[0]" group.long 0x2F0++0x3 line.long 0x0 "ICAWORR0,Internal Channel Analog Watchdog Out of Range Register 0" bitfld.long 0x0 7. "AWOR_CH7,Analog watchdog out of range status for channel 7 provided corresponding WEN_CH7 bit is set." "0: CH[7] converted data is not out of range..,1: CH[7] converted data is out of range determined.." bitfld.long 0x0 6. "AWOR_CH6,Analog watchdog out of range status for channel 6 provided corresponding WEN_CH6 bit is set." "0: CH[6] converted data is not out of range..,1: CH[6] converted data is out of range determined.." newline bitfld.long 0x0 5. "AWOR_CH5,Analog watchdog out of range status for channel 5 provided corresponding WEN_CH5 bit is set." "0: CH[5] converted data is not out of range..,1: CH[5] converted data is out of range determined.." bitfld.long 0x0 4. "AWOR_CH4,Analog watchdog out of range status for channel 4 provided corresponding WEN_CH4 bit is set." "0: CH[4] converted data is not out of range..,1: CH[4] converted data is out of range determined.." newline bitfld.long 0x0 3. "AWOR_CH3,Analog watchdog out of range status for channel 3 provided corresponding WEN_CH3 bit is set." "0: CH[3] converted data is not out of range..,1: CH[3] converted data is out of range determined.." bitfld.long 0x0 2. "AWOR_CH2,Analog watchdog out of range status for channel 2 provided corresponding WEN_CH2 bit is set." "0: CH[2] converted data is not out of range..,1: CH[2] converted data is out of range determined.." newline bitfld.long 0x0 1. "AWOR_CH1,Analog watchdog out of range status for channel 1 provided corresponding WEN_CH1 bit is set." "0: CH[1] converted data is not out of range..,1: CH[1] converted data is out of range determined.." bitfld.long 0x0 0. "AWOR_CH0,Analog watchdog out of range status for channel 0 provided corresponding WEN_CH0 bit is set." "0: CH[0] converted data is not out of range..,1: CH[0] converted data is out of range determined.." group.long 0x400++0x13 line.long 0x0 "TCIPR,Test Channel Interrupt Pending Register" bitfld.long 0x0 31. "EOC_CH127,End of conversion interrupt pending bit for channel 127" "0: End of conversion for CH[127] has not occurred.,1: End of conversion for CH[127] has occurred" bitfld.long 0x0 30. "EOC_CH126,End of conversion interrupt pending bit for channel 126" "0: End of conversion for CH[126] has not occurred.,1: End of conversion for CH[126] has occurred" newline bitfld.long 0x0 29. "EOC_CH125,End of conversion interrupt pending bit for channel 125" "0: End of conversion for CH[125] has not occurred.,1: End of conversion for CH[125] has occurred" bitfld.long 0x0 28. "EOC_CH124,End of conversion interrupt pending bit for channel 124" "0: End of conversion for CH[124] has not occurred.,1: End of conversion for CH[124] has occurred" line.long 0x4 "TCIMR,Test Channel Interrupt Mask Register" bitfld.long 0x4 31. "IM_CH127,IM_CH127" "0: Interrupt for CH[127] is disabled.,1: Interrupt for CH[127] is enabled." bitfld.long 0x4 30. "IM_CH126,IM_CH126" "0: Interrupt for CH[126] is disabled.,1: Interrupt for CH[126] is enabled." newline bitfld.long 0x4 29. "IM_CH125,IM_CH125" "0: Interrupt for CH[125] is disabled.,1: Interrupt for CH[125] is enabled." bitfld.long 0x4 28. "IM_CH124,IM_CH124" "0: Interrupt for CH[124] is disabled.,1: Interrupt for CH[124] is enabled." line.long 0x8 "TCDSR,Test Channel DMA Select Register" bitfld.long 0x8 31. "DS_CH127,DS_CH127" "0: CH[127] is disabled to transfer data in DMA mode.,1: CH[127] is enabled to transfer data in DMA mode." bitfld.long 0x8 30. "DS_CH126,DS_CH126" "0: CH[126] is disabled to transfer data in DMA mode.,1: CH[126] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 29. "DS_CH125,DS_CH125" "0: CH[125] is disabled to transfer data in DMA mode.,1: CH[125] is enabled to transfer data in DMA mode." bitfld.long 0x8 28. "DS_CH124,DS_CH124" "0: CH[124] is disabled to transfer data in DMA mode.,1: CH[124] is enabled to transfer data in DMA mode." line.long 0xC "TCNCMR,Test Channel Normal Conversion Mask Register" bitfld.long 0xC 31. "NCE_CH127,NCE_CH127" "0: Normal conversion is disabled for CH[127].,1: Normal conversion is enabled for CH[127]." bitfld.long 0xC 30. "NCE_CH126,NCE_CH126" "0: Normal conversion is disabled for CH[126].,1: Normal conversion is enabled for CH[126]." newline bitfld.long 0xC 29. "NCE_CH125,NCE_CH125" "0: Normal conversion is disabled for CH[125].,1: Normal conversion is enabled for CH[125]." bitfld.long 0xC 28. "NCE_CH124,NCE_CH124" "0: Normal conversion is disabled for CH[124].,1: Normal conversion is enabled for CH[124]." line.long 0x10 "TCJCMR,Test Channel Injected Conversion Mask Register" bitfld.long 0x10 31. "JCE_CH127,JCE_CH127" "0: Injected conversion is disabled for CH[127].,1: Injected conversion is enabled for CH[127]." bitfld.long 0x10 30. "JCE_CH126,JCE_CH126" "0: Injected conversion is disabled for CH[126].,1: Injected conversion is enabled for CH[126]." newline bitfld.long 0x10 29. "JCE_CH125,JCE_CH125" "0: Injected conversion is disabled for CH[125].,1: Injected conversion is enabled for CH[125]." bitfld.long 0x10 28. "JCE_CH124,JCE_CH124" "0: Injected conversion is disabled for CH[124].,1: Injected conversion is enabled for CH[124]." group.long 0x420++0xB line.long 0x0 "TCWSELR3,Test Channel Watchdog Select Register 3" bitfld.long 0x0 28.--29. "WSEL_CH127,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH126,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH125,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH124,0000 THRHLR0 register is selected" "0,1,2,3" line.long 0x4 "TCWENR,Test Channel Watchdog Enable Register" bitfld.long 0x4 31. "WEN_CH127,WEN_CH127" "0: Watchdog feature is disabled for CH[127].,1: Watchdog feature is enabled for CH[127]." bitfld.long 0x4 30. "WEN_CH126,WEN_CH126" "0: Watchdog feature is disabled for CH[126].,1: Watchdog feature is enabled for CH[126]." newline bitfld.long 0x4 29. "WEN_CH125,WEN_CH125" "0: Watchdog feature is disabled for CH[125].,1: Watchdog feature is enabled for CH[125]." bitfld.long 0x4 28. "WEN_CH124,WEN_CH124" "0: Watchdog feature is disabled for CH[124].,1: Watchdog feature is enabled for CH[124]." line.long 0x8 "TCAWORR,Test Channel Analog Watchdog Out of Range Register" bitfld.long 0x8 31. "AWOR_CH127,Analog watchdog out of range status for channel 127 provided corresponding WEN_CH127 bit is set." "0: CH[127] converted data is not out of range..,1: CH[127] converted data is out of range.." bitfld.long 0x8 30. "AWOR_CH126,Analog watchdog out of range status for channel 126 provided corresponding WEN_CH126 bit is set." "0: CH[126] converted data is not out of range..,1: CH[126] converted data is out of range.." newline bitfld.long 0x8 29. "AWOR_CH125,Analog watchdog out of range status for channel 125 provided corresponding WEN_CH125 bit is set." "0: CH[125] converted data is not out of range..,1: CH[125] converted data is out of range.." bitfld.long 0x8 28. "AWOR_CH124,Analog watchdog out of range status for channel 124 provided corresponding WEN_CH124 bit is set." "0: CH[124] converted data is not out of range..,1: CH[124] converted data is out of range.." group.long 0x44C++0x3 line.long 0x0 "TCCAPR7,Test Channel Connection with Analog Pin Register 7" bitfld.long 0x0 31. "ESIC_TCH31,Enable short with internal channel for test channel 31" "0: Test channel 31 cannot be shorted with internal..,1: Test channel 31 can be shorted with internal.." hexmask.long.byte 0x0 24.--30. 1. "ICSEL_TCH31,Internal channel selection for short with test channel 31" newline bitfld.long 0x0 23. "ESIC_TCH30,Enable short with internal channel for test channel 30" "0: Test channel 30 cannot be shorted with internal..,1: Test channel 30 can be shorted with internal.." hexmask.long.byte 0x0 16.--22. 1. "ICSEL_TCH30,Internal channel selection for short with test channel 30" newline bitfld.long 0x0 15. "ESIC_TCH29,Enable short with internal channel for test channel 29" "0: Test channel 29 cannot be shorted with internal..,1: Test channel 29 can be shorted with internal.." hexmask.long.byte 0x0 8.--14. 1. "ICSEL_TCH29,Internal channel selection for short with test channel 29" newline bitfld.long 0x0 7. "ESIC_TCH28,Enable short with internal channel for test channel 28" "0: Test channel 28 cannot be shorted with internal..,1: Test channel 28 can be shorted with internal.." hexmask.long.byte 0x0 0.--6. 1. "ICSEL_TCH28,Internal channel selection for short with test channel 28" group.long 0x4C0++0xF line.long 0x0 "TCDR124,Test Channel Data Register 124" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x4 "TCDR125,Test Channel Data Register 125" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x8 "TCDR126,Test Channel Data Register 126" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xC "TCDR127,Test Channel Data Register 127" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." tree.end tree "SAR_ADC_12BIT_1" base ad:0x7088C000 group.long 0x0++0x3 line.long 0x0 "MCR,Main Configuration Register" bitfld.long 0x0 31. "OWREN,This bit enables or disables the functionality to overwrite unread converted data in ICDR TCDR ECDR registers." "0: Prevents overwrite of unread converted data new..,1: Enables converted data to be overwritten by a.." bitfld.long 0x0 30. "WLSIDE,Write left/right-aligned" "0: The conversion data in ICDR TCDR ECDR registers..,1: Conversion data is left-aligned (from 15 to (15.." newline bitfld.long 0x0 29. "MODE,One Shot/Scan" "0: One Shot Mode: Configures the normal conversion..,1: Scan Mode: Configures continuous chain.." bitfld.long 0x0 28. "XSTRTEN,This bit enables or disables the external start signal to initial a normal conversion. This can be used to synchronize multiple SARADCs concurrently." "0: External start signal is disabled,1: External start signal high level will start a.." newline bitfld.long 0x0 27. "NSTART,Setting this bit starts the chain or scan conversion. Resetting this bit during scan mode causes the current chain conversion to finish then stops the operation." "0: Cause the current chain conversion to finish and..,1: Starts the chain or scan conversion" bitfld.long 0x0 26. "NTRGEN,NTRGEN" "0: Normal trigger disabled to start a normal..,1: Normal trigger enabled to start a normal.." newline bitfld.long 0x0 24.--25. "NEDGESEL,NEDGESEL" "0: Falling edge of normal trigger is selected,1: Rising edge of normal trigger is selected,2: Both rising and falling edges of normal trigger..,3: Both rising and falling edges of normal trigger.." bitfld.long 0x0 23. "JSTART,Setting this bit will start the configured injected analog channels to be converted by software. Resetting this bit has no effect as the injected chain conversion cannot be interrupted." "0: Writting '0' has not effect,1: Starts the injected chain conversion" newline bitfld.long 0x0 22. "JTRGEN,JTRGEN" "0: Injection trigger disabled for channel injection..,1: Injection trigger enabled for channel injection" bitfld.long 0x0 20.--21. "JEDGESEL,JEDGESEL" "0: Falling edge of injection trigger is selected,1: Rising edge of injection trigger is selected,?,3: Both rising and falling edges of injection.." newline bitfld.long 0x0 19. "JTRGSEQ,JTRGSEQ" "0: Injection trigger sequence mode is disabled,1: Injection trigger sequence mode is enabled" bitfld.long 0x0 17. "CTUEN,Can be set or cleared anytime with some restriction mentioned in CTU trigger/control mode section." "0: The cross triggering unit is disabled and the..,1: The cross triggering unit is enabled and the.." newline bitfld.long 0x0 16. "CTU_MODE,This bit is present only if generic parameter CTSEN = 2 otherwise this bit is a reserved bit and always read as 0. This should be set only when ADC Digital is in powerdown mode." "0: CTU control mode is selected,1: CTU trigger mode is selected" bitfld.long 0x0 15. "WTRIGOUT,This control bit enables the Trigger on every threshold crossover event (crossing of Lower/Upper thresholds) of each WDG monitor to external trigger port (up to 16 ports for up to 16 WDGs)." "0: Trigger outputs disabled,1: Trigger ouputs enabled" newline bitfld.long 0x0 7. "ABORTCHAIN,When this bit is set the ongoing Chain Conversion is aborted. This bit is reset by hardware as soon as a new conversion is requested." "0: Conversion is not affected,1: Aborts the ongoing chain conversion" bitfld.long 0x0 6. "ABORT,When this bit is set the ongoing conversion is aborted and a new conversion is invoked. This bit is reset by hardware as soon as a new conversion is invoked." "0: Conversion is not affected,1: Aborts the ongoing conversion" newline bitfld.long 0x0 4. "FRZ,This bit enables to stop the SARADC conversions at the end of current channel conversion when SoC enters debug mode." "0: Conversions are not stopped,1: When SoC enters debug mode further conversions.." bitfld.long 0x0 2. "FCE,This bit enables the fast comparison mode for upcoming channel conversions." "0: Fast comparision mode disabled,1: Fast comparision mode enabled" newline bitfld.long 0x0 1. "EDCSELF,This bit selects the format for 3-bit output port ipp_decode_extch used as select line for external decode channel 8:1 muxes. The last three bits of external channel number are passed as is (if value 0) or converted to gray code (if value 1) and.." "0: Binary format,1: Gray code format" bitfld.long 0x0 0. "PWDN,When this bit is set the analog module is requested to enter Power Down mode." "0: SARADC is in normal mode,1: SARADC has been requested to power down" rgroup.long 0x4++0x3 line.long 0x0 "MSR,Main Status Register" bitfld.long 0x0 27. "NSTART,This status bit is used to signal that a normal conversion is ongoing." "0: Normal conversion is not taking place,1: Normal conversion is ongoing or the normal.." bitfld.long 0x0 23. "JSTART,This status bit is used to signal that an injected conversion is ongoing." "0: Injected conversion is not taking place,1: Injected conversion is ongoing" newline bitfld.long 0x0 18. "JABORTCHAIN,This status bit is used to signal that an Injected conversion chain has been aborted. This bit is reset when a new conversion starts." "0: Last injected conversion chain has not been..,1: Last injected conversion chain has been aborted" bitfld.long 0x0 16. "CTUSTART,This status bit is used to signal that a CTU conversion is ongoing. This bit is set when a CTU trigger pulse is received and the CTU conversion starts. When CTU trigger mode is enabled this bit is automatically reset when the conversion is.." "0: CTU triggered injected conversion is not taking..,1: CTU triggered injected conversion is ongoing" newline hexmask.long.byte 0x0 8.--15. 1. "CHADDR,Channel under measure address" bitfld.long 0x0 0.--2. "ADCSTATUS,The value of this parameter depends on ADC status. While requesting an external channel conversion SARADC digital interface needs to wait for a fixed time determined by DSD bitfield of DSDR before proceeding to actual sampling phase." "0: IDLE,1: Power-down,2: Wait state,?,4: Sample,?,6: Conversion,?" group.long 0x10++0x7 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CTUTRGERR,This Error Flag indicates that the next CTU trigger has been discarded as it overlapped during execution of current CTU conversion. This indicated that CTU sampling duration is less than programmed conversion time of ADC." "0: No CTU trigger overlap error condition since..,1: CTU trigger overlap error has occurred." bitfld.long 0x0 4. "EOCTU,This bit indicates the end of conversion for a CTU injected channel." "0: End of conversion of CTU triggered channel has..,1: End of conversion of CTU triggered channel has.." newline bitfld.long 0x0 3. "JEOC,This bit indicates the end of conversion for an injected channel." "0: End of conversion of injected channel has not..,1: End of conversion of injected channel has.." bitfld.long 0x0 2. "JECH,This bit indicates the end of conversion for an injected chain." "0: End of conversion of injected chain has not..,1: End of conversion of injected chain has occurred.." newline bitfld.long 0x0 1. "NEOC,This bit indicates the end of conversion for a normal channel." "0: End of conversion of normal channel has not..,1: End of conversion of normal channel has occurred.." bitfld.long 0x0 0. "NECH,This bit indicates the end of conversion for an normal chain." "0: End of conversion of normal chain has not..,1: End of conversion of normal chain has occurred.." line.long 0x4 "ICIPR0,Internal Channel Interrupt Pending Register 0" bitfld.long 0x4 15. "EOC_CH15,End of conversion interrupt pending bit for channel 15" "0: End of conversion for CH[15] has not occured,1: End of conversion for CH[15] has occured" bitfld.long 0x4 14. "EOC_CH14,End of conversion interrupt pending bit for channel 14" "0: End of conversion for CH[14] has not occured,1: End of conversion for CH[14] has occured" newline bitfld.long 0x4 13. "EOC_CH13,End of conversion interrupt pending bit for channel 13" "0: End of conversion for CH[13] has not occured,1: End of conversion for CH[13] has occured" bitfld.long 0x4 12. "EOC_CH12,End of conversion interrupt pending bit for channel 12" "0: End of conversion for CH[12] has not occured,1: End of conversion for CH[12] has occured" newline bitfld.long 0x4 11. "EOC_CH11,End of conversion interrupt pending bit for channel 11" "0: End of conversion for CH[11] has not occured,1: End of conversion for CH[11] has occured" bitfld.long 0x4 10. "EOC_CH10,End of conversion interrupt pending bit for channel 10" "0: End of conversion for CH[10] has not occured,1: End of conversion for CH[10] has occured" newline bitfld.long 0x4 9. "EOC_CH9,End of conversion interrupt pending bit for channel 9" "0: End of conversion for CH[9] has not occured,1: End of conversion for CH[9] has occured" bitfld.long 0x4 8. "EOC_CH8,End of conversion interrupt pending bit for channel 8" "0: End of conversion for CH[8] has not occured,1: End of conversion for CH[8] has occured" group.long 0x20++0x7 line.long 0x0 "IMR,Interrupt Mask Register" bitfld.long 0x0 5. "MSKCTUTRGERR,Mask bit for CTU Trigger" "0: CTUTRGERR interrupt is disabled,1: CTUTRGERR interrupt is enabled" bitfld.long 0x0 4. "MSKEOCTU,Mask bit for EOCTU" "0: EOCTU interrupt is disabled,1: EOCTU interrupt is enabled" newline bitfld.long 0x0 3. "MSKJEOC,Mask bit for JEOC" "0: JEOC interrupt is disabled,1: JEOC interrupt is enabled" bitfld.long 0x0 2. "MSKJECH,Mask bit for JECH" "0: JECH interrupt is disabled,1: JECH interrupt is enabled" newline bitfld.long 0x0 1. "MSKNEOC,Mask bit for NEOC" "0: NEOC interrupt is disabled,1: NEOC interrupt is enabled" bitfld.long 0x0 0. "MSKNECH,Mask bit for NECH" "0: NECH interrupt is disabled,1: NECH interrupt is enabled" line.long 0x4 "ICIMR0,Internal Channel Interrupt Mask Register 0" bitfld.long 0x4 15. "IM_CH15,Interrupt mask bit for channel 15" "0: Interupt for CH[15] is disabled,1: Interupt for CH[15] is enabled" bitfld.long 0x4 14. "IM_CH14,Interrupt mask bit for channel 14" "0: Interupt for CH[14] is disabled,1: Interupt for CH[14] is enabled" newline bitfld.long 0x4 13. "IM_CH13,Interrupt mask bit for channel 13" "0: Interupt for CH[13] is disabled,1: Interupt for CH[13] is enabled" bitfld.long 0x4 12. "IM_CH12,Interrupt mask bit for channel 12" "0: Interupt for CH[12] is disabled,1: Interupt for CH[12] is enabled" newline bitfld.long 0x4 11. "IM_CH11,Interrupt mask bit for channel 11" "0: Interupt for CH[11] is disabled,1: Interupt for CH[11] is enabled" bitfld.long 0x4 10. "IM_CH10,Interrupt mask bit for channel 10" "0: Interupt for CH[10] is disabled,1: Interupt for CH[10] is enabled" newline bitfld.long 0x4 9. "IM_CH9,Interrupt mask bit for channel 9" "0: Interupt for CH[9] is disabled,1: Interupt for CH[9] is enabled" bitfld.long 0x4 8. "IM_CH8,Interrupt mask bit for channel 8" "0: Interupt for CH[8] is disabled,1: Interupt for CH[8] is enabled" group.long 0x30++0xB line.long 0x0 "WTISR,Watchdog Threshold Interrupt Status Register" bitfld.long 0x0 7. "WDG3H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 3." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 6. "WDG3L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 3." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x0 5. "WDG2H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 2." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 4. "WDG2L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 2." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x0 3. "WDG1H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 1." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 2. "WDG1L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 1." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x0 1. "WDG0H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 0." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 0. "WDG0L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 0." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." line.long 0x4 "WTIMR,Watchdog Threshold Interrupt Mask Register" bitfld.long 0x4 7. "MSKWDG3H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG3H is disabled.,1: Inetrupt for WDG3H is enabled." bitfld.long 0x4 6. "MSKWDG3L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG3L is disabled.,1: Inetrupt for WDG3L is enabled." newline bitfld.long 0x4 5. "MSKWDG2H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG2H is disabled.,1: Inetrupt for WDG2H is enabled." bitfld.long 0x4 4. "MSKWDG2L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG2L is disabled.,1: Inetrupt for WDG2L is enabled." newline bitfld.long 0x4 3. "MSKWDG1H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG1H is disabled.,1: Inetrupt for WDG1H is enabled." bitfld.long 0x4 2. "MSKWDG1L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG1L is disabled.,1: Inetrupt for WDG1L is enabled." newline bitfld.long 0x4 1. "MSKWDG0H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG0H is disabled.,1: Inetrupt for WDG0H is enabled." bitfld.long 0x4 0. "MSKWDG0L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG0L is disabled.,1: Inetrupt for WDG0L is enabled." line.long 0x8 "WLTCR,Watchdog Level Trigger Configuration Register" bitfld.long 0x8 3. "LTMW3,LTMW3" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0x8 2. "LTMW2,LTMW2" "0: Level Trigger Mode,1: Hysteresis Mode" newline bitfld.long 0x8 1. "LTMW1,LTMW1" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0x8 0. "LTMW0,LTMW0" "0: Level Trigger Mode,1: Hysteresis Mode" group.long 0x40++0x7 line.long 0x0 "DMAE,DMA Enable Register" bitfld.long 0x0 1. "DCLR,DMA clear sequence enable" "0: DMA request cleared by Acknowledge from DMA..,1: DMA request cleared on read of data registers" bitfld.long 0x0 0. "DMAEN,DMA global enable" "0: DMA feature disabled,1: DMA feature enabled" line.long 0x4 "ICDSR0,Internal Channel DMA Select Register 0" bitfld.long 0x4 15. "DS_CH15,DS_CH15" "0: CH[15] is disabled to transfer data in DMA mode.,1: CH[15] is enabled to transfer data in DMA mode." bitfld.long 0x4 14. "DS_CH14,DS_CH14" "0: CH[14] is disabled to transfer data in DMA mode.,1: CH[14] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 13. "DS_CH13,DS_CH13" "0: CH[13] is disabled to transfer data in DMA mode.,1: CH[13] is enabled to transfer data in DMA mode." bitfld.long 0x4 12. "DS_CH12,DS_CH12" "0: CH[12] is disabled to transfer data in DMA mode.,1: CH[12] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 11. "DS_CH11,DS_CH11" "0: CH[11] is disabled to transfer data in DMA mode.,1: CH[11] is enabled to transfer data in DMA mode." bitfld.long 0x4 10. "DS_CH10,DS_CH10" "0: CH[10] is disabled to transfer data in DMA mode.,1: CH[10] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 9. "DS_CH9,DS_CH9" "0: CH[9] is disabled to transfer data in DMA mode.,1: CH[9] is enabled to transfer data in DMA mode." bitfld.long 0x4 8. "DS_CH8,DS_CH8" "0: CH[8] is disabled to transfer data in DMA mode.,1: CH[8] is enabled to transfer data in DMA mode." group.long 0x60++0xF line.long 0x0 "WTHRHLR0,Watchdog Threshold Register 0" hexmask.long.word 0x0 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x0 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x4 "WTHRHLR1,Watchdog Threshold Register 1" hexmask.long.word 0x4 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x4 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x8 "WTHRHLR2,Watchdog Threshold Register 2" hexmask.long.word 0x8 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x8 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0xC "WTHRHLR3,Watchdog Threshold Register 3" hexmask.long.word 0xC 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0xC 0.--11. 1. "THRL,Low threshold value for channel x" group.long 0x94++0x13 line.long 0x0 "CTR0,Conversion Timing Register 0" bitfld.long 0x0 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x0 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x4 "CTR1,Conversion Timing Register 1" bitfld.long 0x4 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x4 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x4 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x8 "CTR2,Conversion Timing Register 2" bitfld.long 0x8 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x8 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x8 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0xC "CTR3,Conversion Timing Register 3" bitfld.long 0xC 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0xC 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0xC 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x10 "ICNCMR0,Internal Channel Normal Conversion Mask Register 0" bitfld.long 0x10 15. "NCE_CH15,NCE_CH15" "0: Normal conversion is disabled for CH[15].,1: Normal conversion is enabled for CH[15]." bitfld.long 0x10 14. "NCE_CH14,NCE_CH14" "0: Normal conversion is disabled for CH[14].,1: Normal conversion is enabled for CH[14]." newline bitfld.long 0x10 13. "NCE_CH13,NCE_CH13" "0: Normal conversion is disabled for CH[13].,1: Normal conversion is enabled for CH[13]." bitfld.long 0x10 12. "NCE_CH12,NCE_CH12" "0: Normal conversion is disabled for CH[12].,1: Normal conversion is enabled for CH[12]." newline bitfld.long 0x10 11. "NCE_CH11,NCE_CH11" "0: Normal conversion is disabled for CH[11].,1: Normal conversion is enabled for CH[11]." bitfld.long 0x10 10. "NCE_CH10,NCE_CH10" "0: Normal conversion is disabled for CH[10].,1: Normal conversion is enabled for CH[10]." newline bitfld.long 0x10 9. "NCE_CH9,NCE_CH9" "0: Normal conversion is disabled for CH[9].,1: Normal conversion is enabled for CH[9]." bitfld.long 0x10 8. "NCE_CH8,NCE_CH8" "0: Normal conversion is disabled for CH[8].,1: Normal conversion is enabled for CH[8]." group.long 0xB4++0x3 line.long 0x0 "ICJCMR0,Internal Channel Injected Conversion Mask Register 0" bitfld.long 0x0 15. "JCE_CH15,JCE_CH15" "0: Injected conversion is disabled for CH[15].,1: Injected conversion is enabled for CH[15]." bitfld.long 0x0 14. "JCE_CH14,JCE_CH14" "0: Injected conversion is disabled for CH[14].,1: Injected conversion is enabled for CH[14]." newline bitfld.long 0x0 13. "JCE_CH13,JCE_CH13" "0: Injected conversion is disabled for CH[13].,1: Injected conversion is enabled for CH[13]." bitfld.long 0x0 12. "JCE_CH12,JCE_CH12" "0: Injected conversion is disabled for CH[12].,1: Injected conversion is enabled for CH[12]." newline bitfld.long 0x0 11. "JCE_CH11,JCE_CH11" "0: Injected conversion is disabled for CH[11].,1: Injected conversion is enabled for CH[11]." bitfld.long 0x0 10. "JCE_CH10,JCE_CH10" "0: Injected conversion is disabled for CH[10].,1: Injected conversion is enabled for CH[10]." newline bitfld.long 0x0 9. "JCE_CH9,JCE_CH9" "0: Injected conversion is disabled for CH[9].,1: Injected conversion is enabled for CH[9]." bitfld.long 0x0 8. "JCE_CH8,JCE_CH8" "0: Injected conversion is disabled for CH[8].,1: Injected conversion is enabled for CH[8]." group.long 0xC8++0x3 line.long 0x0 "PDEDR,Power Down Exit Delay Register" hexmask.long.byte 0x0 0.--7. 1. "PDED,Defines the delay between the power-down bit reset and the starting of conversion." group.long 0x120++0x1F line.long 0x0 "ICDR8,Internal Channel Data Register 8" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4 "ICDR9,Internal Channel Data Register 9" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x8 "ICDR10,Internal Channel Data Register 10" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x8 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xC "ICDR11,Internal Channel Data Register 11" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xC 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x10 "ICDR12,Internal Channel Data Register 12" bitfld.long 0x10 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x10 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x10 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x10 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x10 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x10 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x10 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x14 "ICDR13,Internal Channel Data Register 13" bitfld.long 0x14 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x14 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x14 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x14 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x14 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x14 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x14 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x18 "ICDR14,Internal Channel Data Register 14" bitfld.long 0x18 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x18 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x18 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x18 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x18 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x18 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x18 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x1C "ICDR15,Internal Channel Data Register 15" bitfld.long 0x1C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x1C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x1C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x1C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x1C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x1C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x1C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" group.long 0x2B4++0x3 line.long 0x0 "ICWSELR1,Internal Channel Watchdog Select Register 1" bitfld.long 0x0 28.--29. "WSEL_CH15,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH14,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH13,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH12,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 12.--13. "WSEL_CH11,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 8.--9. "WSEL_CH10,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 4.--5. "WSEL_CH9,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 0.--1. "WSEL_CH8,0000 THRHLR0 register is selected" "0,1,2,3" group.long 0x2E0++0x3 line.long 0x0 "ICWENR0,Internal Channel Watchdog Enable Register 0" bitfld.long 0x0 15. "WEN_CH15,WEN_CH15" "0: Watchdog feature is disabled for CH[15],1: Watchdog feature is enabled fir CH[15]" bitfld.long 0x0 14. "WEN_CH14,WEN_CH14" "0: Watchdog feature is disabled for CH[14],1: Watchdog feature is enabled fir CH[14]" newline bitfld.long 0x0 13. "WEN_CH13,WEN_CH13" "0: Watchdog feature is disabled for CH[13],1: Watchdog feature is enabled fir CH[13]" bitfld.long 0x0 12. "WEN_CH12,WEN_CH12" "0: Watchdog feature is disabled for CH[12],1: Watchdog feature is enabled fir CH[12]" newline bitfld.long 0x0 11. "WEN_CH11,WEN_CH11" "0: Watchdog feature is disabled for CH[11],1: Watchdog feature is enabled fir CH[11]" bitfld.long 0x0 10. "WEN_CH10,WEN_CH10" "0: Watchdog feature is disabled for CH[10],1: Watchdog feature is enabled fir CH[10]" newline bitfld.long 0x0 9. "WEN_CH9,WEN_CH9" "0: Watchdog feature is disabled for CH[9],1: Watchdog feature is enabled fir CH[9]" bitfld.long 0x0 8. "WEN_CH8,WEN_CH8" "0: Watchdog feature is disabled for CH[8],1: Watchdog feature is enabled fir CH[8]" group.long 0x2F0++0x3 line.long 0x0 "ICAWORR0,Internal Channel Analog Watchdog Out of Range Register 0" bitfld.long 0x0 15. "AWOR_CH15,Analog watchdog out of range status for channel 15 provided corresponding WEN_CH15 bit is set." "0: CH[15] converted data is not out of range..,1: CH[15] converted data is out of range determined.." bitfld.long 0x0 14. "AWOR_CH14,Analog watchdog out of range status for channel 14 provided corresponding WEN_CH14 bit is set." "0: CH[14] converted data is not out of range..,1: CH[14] converted data is out of range determined.." newline bitfld.long 0x0 13. "AWOR_CH13,Analog watchdog out of range status for channel 13 provided corresponding WEN_CH13 bit is set." "0: CH[13] converted data is not out of range..,1: CH[13] converted data is out of range determined.." bitfld.long 0x0 12. "AWOR_CH12,Analog watchdog out of range status for channel 12 provided corresponding WEN_CH12 bit is set." "0: CH[12] converted data is not out of range..,1: CH[12] converted data is out of range determined.." newline bitfld.long 0x0 11. "AWOR_CH11,Analog watchdog out of range status for channel 11 provided corresponding WEN_CH11 bit is set." "0: CH[11] converted data is not out of range..,1: CH[11] converted data is out of range determined.." bitfld.long 0x0 10. "AWOR_CH10,Analog watchdog out of range status for channel 10 provided corresponding WEN_CH10 bit is set." "0: CH[10] converted data is not out of range..,1: CH[10] converted data is out of range determined.." newline bitfld.long 0x0 9. "AWOR_CH9,Analog watchdog out of range status for channel 9 provided corresponding WEN_CH9 bit is set." "0: CH[9] converted data is not out of range..,1: CH[9] converted data is out of range determined.." bitfld.long 0x0 8. "AWOR_CH8,Analog watchdog out of range status for channel 8 provided corresponding WEN_CH8 bit is set." "0: CH[8] converted data is not out of range..,1: CH[8] converted data is out of range determined.." group.long 0x400++0x13 line.long 0x0 "TCIPR,Test Channel Interrupt Pending Register" bitfld.long 0x0 31. "EOC_CH127,End of conversion interrupt pending bit for channel 127" "0: End of conversion for CH[127] has not occurred.,1: End of conversion for CH[127] has occurred" bitfld.long 0x0 30. "EOC_CH126,End of conversion interrupt pending bit for channel 126" "0: End of conversion for CH[126] has not occurred.,1: End of conversion for CH[126] has occurred" newline bitfld.long 0x0 29. "EOC_CH125,End of conversion interrupt pending bit for channel 125" "0: End of conversion for CH[125] has not occurred.,1: End of conversion for CH[125] has occurred" bitfld.long 0x0 28. "EOC_CH124,End of conversion interrupt pending bit for channel 124" "0: End of conversion for CH[124] has not occurred.,1: End of conversion for CH[124] has occurred" line.long 0x4 "TCIMR,Test Channel Interrupt Mask Register" bitfld.long 0x4 31. "IM_CH127,IM_CH127" "0: Interrupt for CH[127] is disabled.,1: Interrupt for CH[127] is enabled." bitfld.long 0x4 30. "IM_CH126,IM_CH126" "0: Interrupt for CH[126] is disabled.,1: Interrupt for CH[126] is enabled." newline bitfld.long 0x4 29. "IM_CH125,IM_CH125" "0: Interrupt for CH[125] is disabled.,1: Interrupt for CH[125] is enabled." bitfld.long 0x4 28. "IM_CH124,IM_CH124" "0: Interrupt for CH[124] is disabled.,1: Interrupt for CH[124] is enabled." line.long 0x8 "TCDSR,Test Channel DMA Select Register" bitfld.long 0x8 31. "DS_CH127,DS_CH127" "0: CH[127] is disabled to transfer data in DMA mode.,1: CH[127] is enabled to transfer data in DMA mode." bitfld.long 0x8 30. "DS_CH126,DS_CH126" "0: CH[126] is disabled to transfer data in DMA mode.,1: CH[126] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 29. "DS_CH125,DS_CH125" "0: CH[125] is disabled to transfer data in DMA mode.,1: CH[125] is enabled to transfer data in DMA mode." bitfld.long 0x8 28. "DS_CH124,DS_CH124" "0: CH[124] is disabled to transfer data in DMA mode.,1: CH[124] is enabled to transfer data in DMA mode." line.long 0xC "TCNCMR,Test Channel Normal Conversion Mask Register" bitfld.long 0xC 31. "NCE_CH127,NCE_CH127" "0: Normal conversion is disabled for CH[127].,1: Normal conversion is enabled for CH[127]." bitfld.long 0xC 30. "NCE_CH126,NCE_CH126" "0: Normal conversion is disabled for CH[126].,1: Normal conversion is enabled for CH[126]." newline bitfld.long 0xC 29. "NCE_CH125,NCE_CH125" "0: Normal conversion is disabled for CH[125].,1: Normal conversion is enabled for CH[125]." bitfld.long 0xC 28. "NCE_CH124,NCE_CH124" "0: Normal conversion is disabled for CH[124].,1: Normal conversion is enabled for CH[124]." line.long 0x10 "TCJCMR,Test Channel Injected Conversion Mask Register" bitfld.long 0x10 31. "JCE_CH127,JCE_CH127" "0: Injected conversion is disabled for CH[127].,1: Injected conversion is enabled for CH[127]." bitfld.long 0x10 30. "JCE_CH126,JCE_CH126" "0: Injected conversion is disabled for CH[126].,1: Injected conversion is enabled for CH[126]." newline bitfld.long 0x10 29. "JCE_CH125,JCE_CH125" "0: Injected conversion is disabled for CH[125].,1: Injected conversion is enabled for CH[125]." bitfld.long 0x10 28. "JCE_CH124,JCE_CH124" "0: Injected conversion is disabled for CH[124].,1: Injected conversion is enabled for CH[124]." group.long 0x420++0xB line.long 0x0 "TCWSELR3,Test Channel Watchdog Select Register 3" bitfld.long 0x0 28.--29. "WSEL_CH127,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH126,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH125,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH124,0000 THRHLR0 register is selected" "0,1,2,3" line.long 0x4 "TCWENR,Test Channel Watchdog Enable Register" bitfld.long 0x4 31. "WEN_CH127,WEN_CH127" "0: Watchdog feature is disabled for CH[127].,1: Watchdog feature is enabled for CH[127]." bitfld.long 0x4 30. "WEN_CH126,WEN_CH126" "0: Watchdog feature is disabled for CH[126].,1: Watchdog feature is enabled for CH[126]." newline bitfld.long 0x4 29. "WEN_CH125,WEN_CH125" "0: Watchdog feature is disabled for CH[125].,1: Watchdog feature is enabled for CH[125]." bitfld.long 0x4 28. "WEN_CH124,WEN_CH124" "0: Watchdog feature is disabled for CH[124].,1: Watchdog feature is enabled for CH[124]." line.long 0x8 "TCAWORR,Test Channel Analog Watchdog Out of Range Register" bitfld.long 0x8 31. "AWOR_CH127,Analog watchdog out of range status for channel 127 provided corresponding WEN_CH127 bit is set." "0: CH[127] converted data is not out of range..,1: CH[127] converted data is out of range.." bitfld.long 0x8 30. "AWOR_CH126,Analog watchdog out of range status for channel 126 provided corresponding WEN_CH126 bit is set." "0: CH[126] converted data is not out of range..,1: CH[126] converted data is out of range.." newline bitfld.long 0x8 29. "AWOR_CH125,Analog watchdog out of range status for channel 125 provided corresponding WEN_CH125 bit is set." "0: CH[125] converted data is not out of range..,1: CH[125] converted data is out of range.." bitfld.long 0x8 28. "AWOR_CH124,Analog watchdog out of range status for channel 124 provided corresponding WEN_CH124 bit is set." "0: CH[124] converted data is not out of range..,1: CH[124] converted data is out of range.." group.long 0x44C++0x3 line.long 0x0 "TCCAPR7,Test Channel Connection with Analog Pin Register 7" bitfld.long 0x0 31. "ESIC_TCH31,Enable short with internal channel for test channel 31" "0: Test channel 31 cannot be shorted with internal..,1: Test channel 31 can be shorted with internal.." hexmask.long.byte 0x0 24.--30. 1. "ICSEL_TCH31,Internal channel selection for short with test channel 31" newline bitfld.long 0x0 23. "ESIC_TCH30,Enable short with internal channel for test channel 30" "0: Test channel 30 cannot be shorted with internal..,1: Test channel 30 can be shorted with internal.." hexmask.long.byte 0x0 16.--22. 1. "ICSEL_TCH30,Internal channel selection for short with test channel 30" newline bitfld.long 0x0 15. "ESIC_TCH29,Enable short with internal channel for test channel 29" "0: Test channel 29 cannot be shorted with internal..,1: Test channel 29 can be shorted with internal.." hexmask.long.byte 0x0 8.--14. 1. "ICSEL_TCH29,Internal channel selection for short with test channel 29" newline bitfld.long 0x0 7. "ESIC_TCH28,Enable short with internal channel for test channel 28" "0: Test channel 28 cannot be shorted with internal..,1: Test channel 28 can be shorted with internal.." hexmask.long.byte 0x0 0.--6. 1. "ICSEL_TCH28,Internal channel selection for short with test channel 28" group.long 0x4C0++0xF line.long 0x0 "TCDR124,Test Channel Data Register 124" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x4 "TCDR125,Test Channel Data Register 125" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x8 "TCDR126,Test Channel Data Register 126" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xC "TCDR127,Test Channel Data Register 127" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." tree.end tree "SAR_ADC_12BIT_2" base ad:0x70294000 group.long 0x0++0x3 line.long 0x0 "MCR,Main Configuration Register" bitfld.long 0x0 31. "OWREN,This bit enables or disables the functionality to overwrite unread converted data in ICDR TCDR ECDR registers." "0: Prevents overwrite of unread converted data new..,1: Enables converted data to be overwritten by a.." bitfld.long 0x0 30. "WLSIDE,Write left/right-aligned" "0: The conversion data in ICDR TCDR ECDR registers..,1: Conversion data is left-aligned (from 15 to (15.." newline bitfld.long 0x0 29. "MODE,One Shot/Scan" "0: One Shot Mode: Configures the normal conversion..,1: Scan Mode: Configures continuous chain.." bitfld.long 0x0 28. "XSTRTEN,This bit enables or disables the external start signal to initial a normal conversion. This can be used to synchronize multiple SARADCs concurrently." "0: External start signal is disabled,1: External start signal high level will start a.." newline bitfld.long 0x0 27. "NSTART,Setting this bit starts the chain or scan conversion. Resetting this bit during scan mode causes the current chain conversion to finish then stops the operation." "0: Cause the current chain conversion to finish and..,1: Starts the chain or scan conversion" bitfld.long 0x0 26. "NTRGEN,NTRGEN" "0: Normal trigger disabled to start a normal..,1: Normal trigger enabled to start a normal.." newline bitfld.long 0x0 24.--25. "NEDGESEL,NEDGESEL" "0: Falling edge of normal trigger is selected,1: Rising edge of normal trigger is selected,2: Both rising and falling edges of normal trigger..,3: Both rising and falling edges of normal trigger.." bitfld.long 0x0 23. "JSTART,Setting this bit will start the configured injected analog channels to be converted by software. Resetting this bit has no effect as the injected chain conversion cannot be interrupted." "0: Writting '0' has not effect,1: Starts the injected chain conversion" newline bitfld.long 0x0 22. "JTRGEN,JTRGEN" "0: Injection trigger disabled for channel injection..,1: Injection trigger enabled for channel injection" bitfld.long 0x0 20.--21. "JEDGESEL,JEDGESEL" "0: Falling edge of injection trigger is selected,1: Rising edge of injection trigger is selected,?,3: Both rising and falling edges of injection.." newline bitfld.long 0x0 19. "JTRGSEQ,JTRGSEQ" "0: Injection trigger sequence mode is disabled,1: Injection trigger sequence mode is enabled" bitfld.long 0x0 17. "CTUEN,Can be set or cleared anytime with some restriction mentioned in CTU trigger/control mode section." "0: The cross triggering unit is disabled and the..,1: The cross triggering unit is enabled and the.." newline bitfld.long 0x0 16. "CTU_MODE,This bit is present only if generic parameter CTSEN = 2 otherwise this bit is a reserved bit and always read as 0. This should be set only when ADC Digital is in powerdown mode." "0: CTU control mode is selected,1: CTU trigger mode is selected" bitfld.long 0x0 15. "WTRIGOUT,This control bit enables the Trigger on every threshold crossover event (crossing of Lower/Upper thresholds) of each WDG monitor to external trigger port (up to 16 ports for up to 16 WDGs)." "0: Trigger outputs disabled,1: Trigger ouputs enabled" newline bitfld.long 0x0 7. "ABORTCHAIN,When this bit is set the ongoing Chain Conversion is aborted. This bit is reset by hardware as soon as a new conversion is requested." "0: Conversion is not affected,1: Aborts the ongoing chain conversion" bitfld.long 0x0 6. "ABORT,When this bit is set the ongoing conversion is aborted and a new conversion is invoked. This bit is reset by hardware as soon as a new conversion is invoked." "0: Conversion is not affected,1: Aborts the ongoing conversion" newline bitfld.long 0x0 4. "FRZ,This bit enables to stop the SARADC conversions at the end of current channel conversion when SoC enters debug mode." "0: Conversions are not stopped,1: When SoC enters debug mode further conversions.." bitfld.long 0x0 2. "FCE,This bit enables the fast comparison mode for upcoming channel conversions." "0: Fast comparision mode disabled,1: Fast comparision mode enabled" newline bitfld.long 0x0 1. "EDCSELF,This bit selects the format for 3-bit output port ipp_decode_extch used as select line for external decode channel 8:1 muxes. The last three bits of external channel number are passed as is (if value 0) or converted to gray code (if value 1) and.." "0: Binary format,1: Gray code format" bitfld.long 0x0 0. "PWDN,When this bit is set the analog module is requested to enter Power Down mode." "0: SARADC is in normal mode,1: SARADC has been requested to power down" rgroup.long 0x4++0x3 line.long 0x0 "MSR,Main Status Register" bitfld.long 0x0 27. "NSTART,This status bit is used to signal that a normal conversion is ongoing." "0: Normal conversion is not taking place,1: Normal conversion is ongoing or the normal.." bitfld.long 0x0 23. "JSTART,This status bit is used to signal that an injected conversion is ongoing." "0: Injected conversion is not taking place,1: Injected conversion is ongoing" newline bitfld.long 0x0 18. "JABORTCHAIN,This status bit is used to signal that an Injected conversion chain has been aborted. This bit is reset when a new conversion starts." "0: Last injected conversion chain has not been..,1: Last injected conversion chain has been aborted" bitfld.long 0x0 16. "CTUSTART,This status bit is used to signal that a CTU conversion is ongoing. This bit is set when a CTU trigger pulse is received and the CTU conversion starts. When CTU trigger mode is enabled this bit is automatically reset when the conversion is.." "0: CTU triggered injected conversion is not taking..,1: CTU triggered injected conversion is ongoing" newline hexmask.long.byte 0x0 8.--15. 1. "CHADDR,Channel under measure address" bitfld.long 0x0 0.--2. "ADCSTATUS,The value of this parameter depends on ADC status. While requesting an external channel conversion SARADC digital interface needs to wait for a fixed time determined by DSD bitfield of DSDR before proceeding to actual sampling phase." "0: IDLE,1: Power-down,2: Wait state,?,4: Sample,?,6: Conversion,?" group.long 0x10++0x7 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CTUTRGERR,This Error Flag indicates that the next CTU trigger has been discarded as it overlapped during execution of current CTU conversion. This indicated that CTU sampling duration is less than programmed conversion time of ADC." "0: No CTU trigger overlap error condition since..,1: CTU trigger overlap error has occurred." bitfld.long 0x0 4. "EOCTU,This bit indicates the end of conversion for a CTU injected channel." "0: End of conversion of CTU triggered channel has..,1: End of conversion of CTU triggered channel has.." newline bitfld.long 0x0 3. "JEOC,This bit indicates the end of conversion for an injected channel." "0: End of conversion of injected channel has not..,1: End of conversion of injected channel has.." bitfld.long 0x0 2. "JECH,This bit indicates the end of conversion for an injected chain." "0: End of conversion of injected chain has not..,1: End of conversion of injected chain has occurred.." newline bitfld.long 0x0 1. "NEOC,This bit indicates the end of conversion for a normal channel." "0: End of conversion of normal channel has not..,1: End of conversion of normal channel has occurred.." bitfld.long 0x0 0. "NECH,This bit indicates the end of conversion for an normal chain." "0: End of conversion of normal chain has not..,1: End of conversion of normal chain has occurred.." line.long 0x4 "ICIPR0,Internal Channel Interrupt Pending Register 0" bitfld.long 0x4 23. "EOC_CH23,End of conversion interrupt pending bit for channel 23" "0: End of conversion for CH[23] has not occured,1: End of conversion for CH[23] has occured" bitfld.long 0x4 22. "EOC_CH22,End of conversion interrupt pending bit for channel 22" "0: End of conversion for CH[22] has not occured,1: End of conversion for CH[22] has occured" newline bitfld.long 0x4 21. "EOC_CH21,End of conversion interrupt pending bit for channel 21" "0: End of conversion for CH[21] has not occured,1: End of conversion for CH[21] has occured" bitfld.long 0x4 20. "EOC_CH20,End of conversion interrupt pending bit for channel 20" "0: End of conversion for CH[20] has not occured,1: End of conversion for CH[20] has occured" newline bitfld.long 0x4 19. "EOC_CH19,End of conversion interrupt pending bit for channel 19" "0: End of conversion for CH[19] has not occured,1: End of conversion for CH[19] has occured" bitfld.long 0x4 18. "EOC_CH18,End of conversion interrupt pending bit for channel 18" "0: End of conversion for CH[18] has not occured,1: End of conversion for CH[18] has occured" newline bitfld.long 0x4 17. "EOC_CH17,End of conversion interrupt pending bit for channel 17" "0: End of conversion for CH[17] has not occured,1: End of conversion for CH[17] has occured" bitfld.long 0x4 16. "EOC_CH16,End of conversion interrupt pending bit for channel 16" "0: End of conversion for CH[16] has not occured,1: End of conversion for CH[16] has occured" group.long 0x1C++0xB line.long 0x0 "ICIPR2,Internal Channel Interrupt Pending Register 2" bitfld.long 0x0 25. "EOC_CH89,End of conversion interrupt pending bit for channel 89" "0: End of conversion for CH[89] has not occured,1: End of conversion for CH[89] has occured" bitfld.long 0x0 24. "EOC_CH88,End of conversion interrupt pending bit for channel 88" "0: End of conversion for CH[88] has not occured,1: End of conversion for CH[88] has occured" line.long 0x4 "IMR,Interrupt Mask Register" bitfld.long 0x4 5. "MSKCTUTRGERR,Mask bit for CTU Trigger" "0: CTUTRGERR interrupt is disabled,1: CTUTRGERR interrupt is enabled" bitfld.long 0x4 4. "MSKEOCTU,Mask bit for EOCTU" "0: EOCTU interrupt is disabled,1: EOCTU interrupt is enabled" newline bitfld.long 0x4 3. "MSKJEOC,Mask bit for JEOC" "0: JEOC interrupt is disabled,1: JEOC interrupt is enabled" bitfld.long 0x4 2. "MSKJECH,Mask bit for JECH" "0: JECH interrupt is disabled,1: JECH interrupt is enabled" newline bitfld.long 0x4 1. "MSKNEOC,Mask bit for NEOC" "0: NEOC interrupt is disabled,1: NEOC interrupt is enabled" bitfld.long 0x4 0. "MSKNECH,Mask bit for NECH" "0: NECH interrupt is disabled,1: NECH interrupt is enabled" line.long 0x8 "ICIMR0,Internal Channel Interrupt Mask Register 0" bitfld.long 0x8 23. "IM_CH23,Interrupt mask bit for channel 23" "0: Interupt for CH[23] is disabled,1: Interupt for CH[23] is enabled" bitfld.long 0x8 22. "IM_CH22,Interrupt mask bit for channel 22" "0: Interupt for CH[22] is disabled,1: Interupt for CH[22] is enabled" newline bitfld.long 0x8 21. "IM_CH21,Interrupt mask bit for channel 21" "0: Interupt for CH[21] is disabled,1: Interupt for CH[21] is enabled" bitfld.long 0x8 20. "IM_CH20,Interrupt mask bit for channel 20" "0: Interupt for CH[20] is disabled,1: Interupt for CH[20] is enabled" newline bitfld.long 0x8 19. "IM_CH19,Interrupt mask bit for channel 19" "0: Interupt for CH[19] is disabled,1: Interupt for CH[19] is enabled" bitfld.long 0x8 18. "IM_CH18,Interrupt mask bit for channel 18" "0: Interupt for CH[18] is disabled,1: Interupt for CH[18] is enabled" newline bitfld.long 0x8 17. "IM_CH17,Interrupt mask bit for channel 17" "0: Interupt for CH[17] is disabled,1: Interupt for CH[17] is enabled" bitfld.long 0x8 16. "IM_CH16,Interrupt mask bit for channel 16" "0: Interupt for CH[16] is disabled,1: Interupt for CH[16] is enabled" group.long 0x2C++0xF line.long 0x0 "ICIMR2,Internal Channel Interrupt Mask Register 2" bitfld.long 0x0 25. "IM_CH89,Interrupt mask bit for channel 89" "0: Interupt for CH[89] is disabled,1: Interupt for CH[89] is enabled" bitfld.long 0x0 24. "IM_CH88,Interrupt mask bit for channel 88" "0: Interupt for CH[88] is disabled,1: Interupt for CH[88] is enabled" line.long 0x4 "WTISR,Watchdog Threshold Interrupt Status Register" bitfld.long 0x4 7. "WDG3H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 3." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x4 6. "WDG3L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 3." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x4 5. "WDG2H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 2." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x4 4. "WDG2L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 2." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x4 3. "WDG1H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 1." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x4 2. "WDG1L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 1." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x4 1. "WDG0H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 0." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x4 0. "WDG0L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 0." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." line.long 0x8 "WTIMR,Watchdog Threshold Interrupt Mask Register" bitfld.long 0x8 7. "MSKWDG3H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG3H is disabled.,1: Inetrupt for WDG3H is enabled." bitfld.long 0x8 6. "MSKWDG3L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG3L is disabled.,1: Inetrupt for WDG3L is enabled." newline bitfld.long 0x8 5. "MSKWDG2H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG2H is disabled.,1: Inetrupt for WDG2H is enabled." bitfld.long 0x8 4. "MSKWDG2L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG2L is disabled.,1: Inetrupt for WDG2L is enabled." newline bitfld.long 0x8 3. "MSKWDG1H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG1H is disabled.,1: Inetrupt for WDG1H is enabled." bitfld.long 0x8 2. "MSKWDG1L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG1L is disabled.,1: Inetrupt for WDG1L is enabled." newline bitfld.long 0x8 1. "MSKWDG0H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG0H is disabled.,1: Inetrupt for WDG0H is enabled." bitfld.long 0x8 0. "MSKWDG0L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG0L is disabled.,1: Inetrupt for WDG0L is enabled." line.long 0xC "WLTCR,Watchdog Level Trigger Configuration Register" bitfld.long 0xC 3. "LTMW3,LTMW3" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0xC 2. "LTMW2,LTMW2" "0: Level Trigger Mode,1: Hysteresis Mode" newline bitfld.long 0xC 1. "LTMW1,LTMW1" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0xC 0. "LTMW0,LTMW0" "0: Level Trigger Mode,1: Hysteresis Mode" group.long 0x40++0x7 line.long 0x0 "DMAE,DMA Enable Register" bitfld.long 0x0 1. "DCLR,DMA clear sequence enable" "0: DMA request cleared by Acknowledge from DMA..,1: DMA request cleared on read of data registers" bitfld.long 0x0 0. "DMAEN,DMA global enable" "0: DMA feature disabled,1: DMA feature enabled" line.long 0x4 "ICDSR0,Internal Channel DMA Select Register 0" bitfld.long 0x4 23. "DS_CH23,DS_CH23" "0: CH[23] is disabled to transfer data in DMA mode.,1: CH[23] is enabled to transfer data in DMA mode." bitfld.long 0x4 22. "DS_CH22,DS_CH22" "0: CH[22] is disabled to transfer data in DMA mode.,1: CH[22] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 21. "DS_CH21,DS_CH21" "0: CH[21] is disabled to transfer data in DMA mode.,1: CH[21] is enabled to transfer data in DMA mode." bitfld.long 0x4 20. "DS_CH20,DS_CH20" "0: CH[20] is disabled to transfer data in DMA mode.,1: CH[20] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 19. "DS_CH19,DS_CH19" "0: CH[19] is disabled to transfer data in DMA mode.,1: CH[19] is enabled to transfer data in DMA mode." bitfld.long 0x4 18. "DS_CH18,DS_CH18" "0: CH[18] is disabled to transfer data in DMA mode.,1: CH[18] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 17. "DS_CH17,DS_CH17" "0: CH[17] is disabled to transfer data in DMA mode.,1: CH[17] is enabled to transfer data in DMA mode." bitfld.long 0x4 16. "DS_CH16,DS_CH16" "0: CH[16] is disabled to transfer data in DMA mode.,1: CH[16] is enabled to transfer data in DMA mode." group.long 0x4C++0x3 line.long 0x0 "ICDSR2,Internal Channel DMA Select Register 2" bitfld.long 0x0 25. "DS_CH89,DS_CH89" "0: CH[89] is disabled to transfer data in DMA mode.,1: CH[89] is enabled to transfer data in DMA mode." bitfld.long 0x0 24. "DS_CH88,DS_CH88" "0: CH[88] is disabled to transfer data in DMA mode.,1: CH[88] is enabled to transfer data in DMA mode." group.long 0x60++0xF line.long 0x0 "WTHRHLR0,Watchdog Threshold Register 0" hexmask.long.word 0x0 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x0 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x4 "WTHRHLR1,Watchdog Threshold Register 1" hexmask.long.word 0x4 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x4 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x8 "WTHRHLR2,Watchdog Threshold Register 2" hexmask.long.word 0x8 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x8 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0xC "WTHRHLR3,Watchdog Threshold Register 3" hexmask.long.word 0xC 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0xC 0.--11. 1. "THRL,Low threshold value for channel x" group.long 0x94++0x13 line.long 0x0 "CTR0,Conversion Timing Register 0" bitfld.long 0x0 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x0 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x4 "CTR1,Conversion Timing Register 1" bitfld.long 0x4 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x4 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x4 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x8 "CTR2,Conversion Timing Register 2" bitfld.long 0x8 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x8 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x8 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0xC "CTR3,Conversion Timing Register 3" bitfld.long 0xC 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0xC 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0xC 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x10 "ICNCMR0,Internal Channel Normal Conversion Mask Register 0" bitfld.long 0x10 23. "NCE_CH23,NCE_CH23" "0: Normal conversion is disabled for CH[23].,1: Normal conversion is enabled for CH[23]." bitfld.long 0x10 22. "NCE_CH22,NCE_CH22" "0: Normal conversion is disabled for CH[22].,1: Normal conversion is enabled for CH[22]." newline bitfld.long 0x10 21. "NCE_CH21,NCE_CH21" "0: Normal conversion is disabled for CH[21].,1: Normal conversion is enabled for CH[21]." bitfld.long 0x10 20. "NCE_CH20,NCE_CH20" "0: Normal conversion is disabled for CH[20].,1: Normal conversion is enabled for CH[20]." newline bitfld.long 0x10 19. "NCE_CH19,NCE_CH19" "0: Normal conversion is disabled for CH[19].,1: Normal conversion is enabled for CH[19]." bitfld.long 0x10 18. "NCE_CH18,NCE_CH18" "0: Normal conversion is disabled for CH[18].,1: Normal conversion is enabled for CH[18]." newline bitfld.long 0x10 17. "NCE_CH17,NCE_CH17" "0: Normal conversion is disabled for CH[17].,1: Normal conversion is enabled for CH[17]." bitfld.long 0x10 16. "NCE_CH16,NCE_CH16" "0: Normal conversion is disabled for CH[16].,1: Normal conversion is enabled for CH[16]." group.long 0xAC++0x3 line.long 0x0 "ICNCMR2,Internal Channel Normal Conversion Mask Register 2" bitfld.long 0x0 25. "NCE_CH89,NCE_CH89" "0: Normal conversion is disabled for CH[89].,1: Normal conversion is enabled for CH[89]." bitfld.long 0x0 24. "NCE_CH88,NCE_CH88" "0: Normal conversion is disabled for CH[88].,1: Normal conversion is enabled for CH[88]." group.long 0xB4++0x3 line.long 0x0 "ICJCMR0,Internal Channel Injected Conversion Mask Register 0" bitfld.long 0x0 23. "JCE_CH23,JCE_CH23" "0: Injected conversion is disabled for CH[23].,1: Injected conversion is enabled for CH[23]." bitfld.long 0x0 22. "JCE_CH22,JCE_CH22" "0: Injected conversion is disabled for CH[22].,1: Injected conversion is enabled for CH[22]." newline bitfld.long 0x0 21. "JCE_CH21,JCE_CH21" "0: Injected conversion is disabled for CH[21].,1: Injected conversion is enabled for CH[21]." bitfld.long 0x0 20. "JCE_CH20,JCE_CH20" "0: Injected conversion is disabled for CH[20].,1: Injected conversion is enabled for CH[20]." newline bitfld.long 0x0 19. "JCE_CH19,JCE_CH19" "0: Injected conversion is disabled for CH[19].,1: Injected conversion is enabled for CH[19]." bitfld.long 0x0 18. "JCE_CH18,JCE_CH18" "0: Injected conversion is disabled for CH[18].,1: Injected conversion is enabled for CH[18]." newline bitfld.long 0x0 17. "JCE_CH17,JCE_CH17" "0: Injected conversion is disabled for CH[17].,1: Injected conversion is enabled for CH[17]." bitfld.long 0x0 16. "JCE_CH16,JCE_CH16" "0: Injected conversion is disabled for CH[16].,1: Injected conversion is enabled for CH[16]." group.long 0xBC++0x3 line.long 0x0 "ICJCMR2,Internal Channel Injected Conversion Mask Register 2" bitfld.long 0x0 25. "JCE_CH89,JCE_CH89" "0: Injected conversion is disabled for CH[89].,1: Injected conversion is enabled for CH[89]." bitfld.long 0x0 24. "JCE_CH88,JCE_CH88" "0: Injected conversion is disabled for CH[88].,1: Injected conversion is enabled for CH[88]." group.long 0xC8++0x3 line.long 0x0 "PDEDR,Power Down Exit Delay Register" hexmask.long.byte 0x0 0.--7. 1. "PDED,Defines the delay between the power-down bit reset and the starting of conversion." group.long 0x140++0x1F line.long 0x0 "ICDR16,Internal Channel Data Register 16" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4 "ICDR17,Internal Channel Data Register 17" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x8 "ICDR18,Internal Channel Data Register 18" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x8 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xC "ICDR19,Internal Channel Data Register 19" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xC 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x10 "ICDR20,Internal Channel Data Register 20" bitfld.long 0x10 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x10 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x10 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x10 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x10 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x10 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x10 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x14 "ICDR21,Internal Channel Data Register 21" bitfld.long 0x14 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x14 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x14 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x14 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x14 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x14 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x14 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x18 "ICDR22,Internal Channel Data Register 22" bitfld.long 0x18 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x18 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x18 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x18 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x18 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x18 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x18 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x1C "ICDR23,Internal Channel Data Register 23" bitfld.long 0x1C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x1C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x1C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x1C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x1C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x1C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x1C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" group.long 0x260++0x7 line.long 0x0 "ICDR88,Internal Channel Data Register 88" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4 "ICDR89,Internal Channel Data Register 89" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" group.long 0x2B8++0x3 line.long 0x0 "ICWSELR2,Internal Channel Watchdog Select Register 2" bitfld.long 0x0 28.--29. "WSEL_CH23,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH22,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH21,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH20,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 12.--13. "WSEL_CH19,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 8.--9. "WSEL_CH18,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 4.--5. "WSEL_CH17,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 0.--1. "WSEL_CH16,0000 THRHLR0 register is selected" "0,1,2,3" group.long 0x2DC++0x7 line.long 0x0 "ICWSELR11,Internal Channel Watchdog Select Register 11" bitfld.long 0x0 4.--5. "WSEL_CH89,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 0.--1. "WSEL_CH88,0000 THRHLR0 register is selected" "0,1,2,3" line.long 0x4 "ICWENR0,Internal Channel Watchdog Enable Register 0" bitfld.long 0x4 23. "WEN_CH23,WEN_CH23" "0: Watchdog feature is disabled for CH[23],1: Watchdog feature is enabled fir CH[23]" bitfld.long 0x4 22. "WEN_CH22,WEN_CH22" "0: Watchdog feature is disabled for CH[22],1: Watchdog feature is enabled fir CH[22]" newline bitfld.long 0x4 21. "WEN_CH21,WEN_CH21" "0: Watchdog feature is disabled for CH[21],1: Watchdog feature is enabled fir CH[21]" bitfld.long 0x4 20. "WEN_CH20,WEN_CH20" "0: Watchdog feature is disabled for CH[20],1: Watchdog feature is enabled fir CH[20]" newline bitfld.long 0x4 19. "WEN_CH19,WEN_CH19" "0: Watchdog feature is disabled for CH[19],1: Watchdog feature is enabled fir CH[19]" bitfld.long 0x4 18. "WEN_CH18,WEN_CH18" "0: Watchdog feature is disabled for CH[18],1: Watchdog feature is enabled fir CH[18]" newline bitfld.long 0x4 17. "WEN_CH17,WEN_CH17" "0: Watchdog feature is disabled for CH[17],1: Watchdog feature is enabled fir CH[17]" bitfld.long 0x4 16. "WEN_CH16,WEN_CH16" "0: Watchdog feature is disabled for CH[16],1: Watchdog feature is enabled fir CH[16]" group.long 0x2E8++0x3 line.long 0x0 "ICWENR2,Internal Channel Watchdog Enable Register 2" bitfld.long 0x0 25. "WEN_CH89,WEN_CH89" "0: Watchdog feature is disabled for CH[89],1: Watchdog feature is enabled fir CH[89]" bitfld.long 0x0 24. "WEN_CH88,WEN_CH88" "0: Watchdog feature is disabled for CH[88],1: Watchdog feature is enabled fir CH[88]" group.long 0x2F0++0x3 line.long 0x0 "ICAWORR0,Internal Channel Analog Watchdog Out of Range Register 0" bitfld.long 0x0 23. "AWOR_CH23,Analog watchdog out of range status for channel 23 provided corresponding WEN_CH23 bit is set." "0: CH[23] converted data is not out of range..,1: CH[23] converted data is out of range determined.." bitfld.long 0x0 22. "AWOR_CH22,Analog watchdog out of range status for channel 22 provided corresponding WEN_CH22 bit is set." "0: CH[22] converted data is not out of range..,1: CH[22] converted data is out of range determined.." newline bitfld.long 0x0 21. "AWOR_CH21,Analog watchdog out of range status for channel 21 provided corresponding WEN_CH21 bit is set." "0: CH[21] converted data is not out of range..,1: CH[21] converted data is out of range determined.." bitfld.long 0x0 20. "AWOR_CH20,Analog watchdog out of range status for channel 20 provided corresponding WEN_CH20 bit is set." "0: CH[20] converted data is not out of range..,1: CH[20] converted data is out of range determined.." newline bitfld.long 0x0 19. "AWOR_CH19,Analog watchdog out of range status for channel 19 provided corresponding WEN_CH19 bit is set." "0: CH[19] converted data is not out of range..,1: CH[19] converted data is out of range determined.." bitfld.long 0x0 18. "AWOR_CH18,Analog watchdog out of range status for channel 18 provided corresponding WEN_CH18 bit is set." "0: CH[18] converted data is not out of range..,1: CH[18] converted data is out of range determined.." newline bitfld.long 0x0 17. "AWOR_CH17,Analog watchdog out of range status for channel 17 provided corresponding WEN_CH17 bit is set." "0: CH[17] converted data is not out of range..,1: CH[17] converted data is out of range determined.." bitfld.long 0x0 16. "AWOR_CH16,Analog watchdog out of range status for channel 16 provided corresponding WEN_CH16 bit is set." "0: CH[16] converted data is not out of range..,1: CH[16] converted data is out of range determined.." group.long 0x2F8++0x3 line.long 0x0 "ICAWORR2,Internal Channel Analog Watchdog Out of Range Register 2" bitfld.long 0x0 25. "AWOR_CH89,Analog watchdog out of range status for channel 89 provided corresponding WEN_CH89 bit is set." "0: CH[89] converted data is not out of range..,1: CH[89] converted data is out of range determined.." bitfld.long 0x0 24. "AWOR_CH88,Analog watchdog out of range status for channel 88 provided corresponding WEN_CH88 bit is set." "0: CH[88] converted data is not out of range..,1: CH[88] converted data is out of range determined.." group.long 0x400++0x13 line.long 0x0 "TCIPR,Test Channel Interrupt Pending Register" bitfld.long 0x0 31. "EOC_CH127,End of conversion interrupt pending bit for channel 127" "0: End of conversion for CH[127] has not occurred.,1: End of conversion for CH[127] has occurred" bitfld.long 0x0 30. "EOC_CH126,End of conversion interrupt pending bit for channel 126" "0: End of conversion for CH[126] has not occurred.,1: End of conversion for CH[126] has occurred" newline bitfld.long 0x0 29. "EOC_CH125,End of conversion interrupt pending bit for channel 125" "0: End of conversion for CH[125] has not occurred.,1: End of conversion for CH[125] has occurred" bitfld.long 0x0 28. "EOC_CH124,End of conversion interrupt pending bit for channel 124" "0: End of conversion for CH[124] has not occurred.,1: End of conversion for CH[124] has occurred" line.long 0x4 "TCIMR,Test Channel Interrupt Mask Register" bitfld.long 0x4 31. "IM_CH127,IM_CH127" "0: Interrupt for CH[127] is disabled.,1: Interrupt for CH[127] is enabled." bitfld.long 0x4 30. "IM_CH126,IM_CH126" "0: Interrupt for CH[126] is disabled.,1: Interrupt for CH[126] is enabled." newline bitfld.long 0x4 29. "IM_CH125,IM_CH125" "0: Interrupt for CH[125] is disabled.,1: Interrupt for CH[125] is enabled." bitfld.long 0x4 28. "IM_CH124,IM_CH124" "0: Interrupt for CH[124] is disabled.,1: Interrupt for CH[124] is enabled." line.long 0x8 "TCDSR,Test Channel DMA Select Register" bitfld.long 0x8 31. "DS_CH127,DS_CH127" "0: CH[127] is disabled to transfer data in DMA mode.,1: CH[127] is enabled to transfer data in DMA mode." bitfld.long 0x8 30. "DS_CH126,DS_CH126" "0: CH[126] is disabled to transfer data in DMA mode.,1: CH[126] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 29. "DS_CH125,DS_CH125" "0: CH[125] is disabled to transfer data in DMA mode.,1: CH[125] is enabled to transfer data in DMA mode." bitfld.long 0x8 28. "DS_CH124,DS_CH124" "0: CH[124] is disabled to transfer data in DMA mode.,1: CH[124] is enabled to transfer data in DMA mode." line.long 0xC "TCNCMR,Test Channel Normal Conversion Mask Register" bitfld.long 0xC 31. "NCE_CH127,NCE_CH127" "0: Normal conversion is disabled for CH[127].,1: Normal conversion is enabled for CH[127]." bitfld.long 0xC 30. "NCE_CH126,NCE_CH126" "0: Normal conversion is disabled for CH[126].,1: Normal conversion is enabled for CH[126]." newline bitfld.long 0xC 29. "NCE_CH125,NCE_CH125" "0: Normal conversion is disabled for CH[125].,1: Normal conversion is enabled for CH[125]." bitfld.long 0xC 28. "NCE_CH124,NCE_CH124" "0: Normal conversion is disabled for CH[124].,1: Normal conversion is enabled for CH[124]." line.long 0x10 "TCJCMR,Test Channel Injected Conversion Mask Register" bitfld.long 0x10 31. "JCE_CH127,JCE_CH127" "0: Injected conversion is disabled for CH[127].,1: Injected conversion is enabled for CH[127]." bitfld.long 0x10 30. "JCE_CH126,JCE_CH126" "0: Injected conversion is disabled for CH[126].,1: Injected conversion is enabled for CH[126]." newline bitfld.long 0x10 29. "JCE_CH125,JCE_CH125" "0: Injected conversion is disabled for CH[125].,1: Injected conversion is enabled for CH[125]." bitfld.long 0x10 28. "JCE_CH124,JCE_CH124" "0: Injected conversion is disabled for CH[124].,1: Injected conversion is enabled for CH[124]." group.long 0x420++0xB line.long 0x0 "TCWSELR3,Test Channel Watchdog Select Register 3" bitfld.long 0x0 28.--29. "WSEL_CH127,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH126,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH125,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH124,0000 THRHLR0 register is selected" "0,1,2,3" line.long 0x4 "TCWENR,Test Channel Watchdog Enable Register" bitfld.long 0x4 31. "WEN_CH127,WEN_CH127" "0: Watchdog feature is disabled for CH[127].,1: Watchdog feature is enabled for CH[127]." bitfld.long 0x4 30. "WEN_CH126,WEN_CH126" "0: Watchdog feature is disabled for CH[126].,1: Watchdog feature is enabled for CH[126]." newline bitfld.long 0x4 29. "WEN_CH125,WEN_CH125" "0: Watchdog feature is disabled for CH[125].,1: Watchdog feature is enabled for CH[125]." bitfld.long 0x4 28. "WEN_CH124,WEN_CH124" "0: Watchdog feature is disabled for CH[124].,1: Watchdog feature is enabled for CH[124]." line.long 0x8 "TCAWORR,Test Channel Analog Watchdog Out of Range Register" bitfld.long 0x8 31. "AWOR_CH127,Analog watchdog out of range status for channel 127 provided corresponding WEN_CH127 bit is set." "0: CH[127] converted data is not out of range..,1: CH[127] converted data is out of range.." bitfld.long 0x8 30. "AWOR_CH126,Analog watchdog out of range status for channel 126 provided corresponding WEN_CH126 bit is set." "0: CH[126] converted data is not out of range..,1: CH[126] converted data is out of range.." newline bitfld.long 0x8 29. "AWOR_CH125,Analog watchdog out of range status for channel 125 provided corresponding WEN_CH125 bit is set." "0: CH[125] converted data is not out of range..,1: CH[125] converted data is out of range.." bitfld.long 0x8 28. "AWOR_CH124,Analog watchdog out of range status for channel 124 provided corresponding WEN_CH124 bit is set." "0: CH[124] converted data is not out of range..,1: CH[124] converted data is out of range.." group.long 0x44C++0x3 line.long 0x0 "TCCAPR7,Test Channel Connection with Analog Pin Register 7" bitfld.long 0x0 31. "ESIC_TCH31,Enable short with internal channel for test channel 31" "0: Test channel 31 cannot be shorted with internal..,1: Test channel 31 can be shorted with internal.." hexmask.long.byte 0x0 24.--30. 1. "ICSEL_TCH31,Internal channel selection for short with test channel 31" newline bitfld.long 0x0 23. "ESIC_TCH30,Enable short with internal channel for test channel 30" "0: Test channel 30 cannot be shorted with internal..,1: Test channel 30 can be shorted with internal.." hexmask.long.byte 0x0 16.--22. 1. "ICSEL_TCH30,Internal channel selection for short with test channel 30" newline bitfld.long 0x0 15. "ESIC_TCH29,Enable short with internal channel for test channel 29" "0: Test channel 29 cannot be shorted with internal..,1: Test channel 29 can be shorted with internal.." hexmask.long.byte 0x0 8.--14. 1. "ICSEL_TCH29,Internal channel selection for short with test channel 29" newline bitfld.long 0x0 7. "ESIC_TCH28,Enable short with internal channel for test channel 28" "0: Test channel 28 cannot be shorted with internal..,1: Test channel 28 can be shorted with internal.." hexmask.long.byte 0x0 0.--6. 1. "ICSEL_TCH28,Internal channel selection for short with test channel 28" group.long 0x4C0++0xF line.long 0x0 "TCDR124,Test Channel Data Register 124" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x4 "TCDR125,Test Channel Data Register 125" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x8 "TCDR126,Test Channel Data Register 126" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xC "TCDR127,Test Channel Data Register 127" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." tree.end tree "SAR_ADC_12BIT_3" base ad:0x70894000 group.long 0x0++0x3 line.long 0x0 "MCR,Main Configuration Register" bitfld.long 0x0 31. "OWREN,This bit enables or disables the functionality to overwrite unread converted data in ICDR TCDR ECDR registers." "0: Prevents overwrite of unread converted data new..,1: Enables converted data to be overwritten by a.." bitfld.long 0x0 30. "WLSIDE,Write left/right-aligned" "0: The conversion data in ICDR TCDR ECDR registers..,1: Conversion data is left-aligned (from 15 to (15.." newline bitfld.long 0x0 29. "MODE,One Shot/Scan" "0: One Shot Mode: Configures the normal conversion..,1: Scan Mode: Configures continuous chain.." bitfld.long 0x0 28. "XSTRTEN,This bit enables or disables the external start signal to initial a normal conversion. This can be used to synchronize multiple SARADCs concurrently." "0: External start signal is disabled,1: External start signal high level will start a.." newline bitfld.long 0x0 27. "NSTART,Setting this bit starts the chain or scan conversion. Resetting this bit during scan mode causes the current chain conversion to finish then stops the operation." "0: Cause the current chain conversion to finish and..,1: Starts the chain or scan conversion" bitfld.long 0x0 26. "NTRGEN,NTRGEN" "0: Normal trigger disabled to start a normal..,1: Normal trigger enabled to start a normal.." newline bitfld.long 0x0 24.--25. "NEDGESEL,NEDGESEL" "0: Falling edge of normal trigger is selected,1: Rising edge of normal trigger is selected,2: Both rising and falling edges of normal trigger..,3: Both rising and falling edges of normal trigger.." bitfld.long 0x0 23. "JSTART,Setting this bit will start the configured injected analog channels to be converted by software. Resetting this bit has no effect as the injected chain conversion cannot be interrupted." "0: Writting '0' has not effect,1: Starts the injected chain conversion" newline bitfld.long 0x0 22. "JTRGEN,JTRGEN" "0: Injection trigger disabled for channel injection..,1: Injection trigger enabled for channel injection" bitfld.long 0x0 20.--21. "JEDGESEL,JEDGESEL" "0: Falling edge of injection trigger is selected,1: Rising edge of injection trigger is selected,?,3: Both rising and falling edges of injection.." newline bitfld.long 0x0 19. "JTRGSEQ,JTRGSEQ" "0: Injection trigger sequence mode is disabled,1: Injection trigger sequence mode is enabled" bitfld.long 0x0 17. "CTUEN,Can be set or cleared anytime with some restriction mentioned in CTU trigger/control mode section." "0: The cross triggering unit is disabled and the..,1: The cross triggering unit is enabled and the.." newline bitfld.long 0x0 16. "CTU_MODE,This bit is present only if generic parameter CTSEN = 2 otherwise this bit is a reserved bit and always read as 0. This should be set only when ADC Digital is in powerdown mode." "0: CTU control mode is selected,1: CTU trigger mode is selected" bitfld.long 0x0 15. "WTRIGOUT,This control bit enables the Trigger on every threshold crossover event (crossing of Lower/Upper thresholds) of each WDG monitor to external trigger port (up to 16 ports for up to 16 WDGs)." "0: Trigger outputs disabled,1: Trigger ouputs enabled" newline bitfld.long 0x0 7. "ABORTCHAIN,When this bit is set the ongoing Chain Conversion is aborted. This bit is reset by hardware as soon as a new conversion is requested." "0: Conversion is not affected,1: Aborts the ongoing chain conversion" bitfld.long 0x0 6. "ABORT,When this bit is set the ongoing conversion is aborted and a new conversion is invoked. This bit is reset by hardware as soon as a new conversion is invoked." "0: Conversion is not affected,1: Aborts the ongoing conversion" newline bitfld.long 0x0 4. "FRZ,This bit enables to stop the SARADC conversions at the end of current channel conversion when SoC enters debug mode." "0: Conversions are not stopped,1: When SoC enters debug mode further conversions.." bitfld.long 0x0 2. "FCE,This bit enables the fast comparison mode for upcoming channel conversions." "0: Fast comparision mode disabled,1: Fast comparision mode enabled" newline bitfld.long 0x0 1. "EDCSELF,This bit selects the format for 3-bit output port ipp_decode_extch used as select line for external decode channel 8:1 muxes. The last three bits of external channel number are passed as is (if value 0) or converted to gray code (if value 1) and.." "0: Binary format,1: Gray code format" bitfld.long 0x0 0. "PWDN,When this bit is set the analog module is requested to enter Power Down mode." "0: SARADC is in normal mode,1: SARADC has been requested to power down" rgroup.long 0x4++0x3 line.long 0x0 "MSR,Main Status Register" bitfld.long 0x0 27. "NSTART,This status bit is used to signal that a normal conversion is ongoing." "0: Normal conversion is not taking place,1: Normal conversion is ongoing or the normal.." bitfld.long 0x0 23. "JSTART,This status bit is used to signal that an injected conversion is ongoing." "0: Injected conversion is not taking place,1: Injected conversion is ongoing" newline bitfld.long 0x0 18. "JABORTCHAIN,This status bit is used to signal that an Injected conversion chain has been aborted. This bit is reset when a new conversion starts." "0: Last injected conversion chain has not been..,1: Last injected conversion chain has been aborted" bitfld.long 0x0 16. "CTUSTART,This status bit is used to signal that a CTU conversion is ongoing. This bit is set when a CTU trigger pulse is received and the CTU conversion starts. When CTU trigger mode is enabled this bit is automatically reset when the conversion is.." "0: CTU triggered injected conversion is not taking..,1: CTU triggered injected conversion is ongoing" newline hexmask.long.byte 0x0 8.--15. 1. "CHADDR,Channel under measure address" bitfld.long 0x0 0.--2. "ADCSTATUS,The value of this parameter depends on ADC status. While requesting an external channel conversion SARADC digital interface needs to wait for a fixed time determined by DSD bitfield of DSDR before proceeding to actual sampling phase." "0: IDLE,1: Power-down,2: Wait state,?,4: Sample,?,6: Conversion,?" group.long 0x10++0x7 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CTUTRGERR,This Error Flag indicates that the next CTU trigger has been discarded as it overlapped during execution of current CTU conversion. This indicated that CTU sampling duration is less than programmed conversion time of ADC." "0: No CTU trigger overlap error condition since..,1: CTU trigger overlap error has occurred." bitfld.long 0x0 4. "EOCTU,This bit indicates the end of conversion for a CTU injected channel." "0: End of conversion of CTU triggered channel has..,1: End of conversion of CTU triggered channel has.." newline bitfld.long 0x0 3. "JEOC,This bit indicates the end of conversion for an injected channel." "0: End of conversion of injected channel has not..,1: End of conversion of injected channel has.." bitfld.long 0x0 2. "JECH,This bit indicates the end of conversion for an injected chain." "0: End of conversion of injected chain has not..,1: End of conversion of injected chain has occurred.." newline bitfld.long 0x0 1. "NEOC,This bit indicates the end of conversion for a normal channel." "0: End of conversion of normal channel has not..,1: End of conversion of normal channel has occurred.." bitfld.long 0x0 0. "NECH,This bit indicates the end of conversion for an normal chain." "0: End of conversion of normal chain has not..,1: End of conversion of normal chain has occurred.." line.long 0x4 "ICIPR0,Internal Channel Interrupt Pending Register 0" bitfld.long 0x4 31. "EOC_CH31,End of conversion interrupt pending bit for channel 31" "0: End of conversion for CH[31] has not occured,1: End of conversion for CH[31] has occured" bitfld.long 0x4 30. "EOC_CH30,End of conversion interrupt pending bit for channel 30" "0: End of conversion for CH[30] has not occured,1: End of conversion for CH[30] has occured" newline bitfld.long 0x4 29. "EOC_CH29,End of conversion interrupt pending bit for channel 29" "0: End of conversion for CH[29] has not occured,1: End of conversion for CH[29] has occured" bitfld.long 0x4 28. "EOC_CH28,End of conversion interrupt pending bit for channel 28" "0: End of conversion for CH[28] has not occured,1: End of conversion for CH[28] has occured" newline bitfld.long 0x4 27. "EOC_CH27,End of conversion interrupt pending bit for channel 27" "0: End of conversion for CH[27] has not occured,1: End of conversion for CH[27] has occured" bitfld.long 0x4 26. "EOC_CH26,End of conversion interrupt pending bit for channel 26" "0: End of conversion for CH[26] has not occured,1: End of conversion for CH[26] has occured" newline bitfld.long 0x4 25. "EOC_CH25,End of conversion interrupt pending bit for channel 25" "0: End of conversion for CH[25] has not occured,1: End of conversion for CH[25] has occured" bitfld.long 0x4 24. "EOC_CH24,End of conversion interrupt pending bit for channel 24" "0: End of conversion for CH[24] has not occured,1: End of conversion for CH[24] has occured" group.long 0x1C++0xB line.long 0x0 "ICIPR2,Internal Channel Interrupt Pending Register 2" bitfld.long 0x0 27. "EOC_CH91,End of conversion interrupt pending bit for channel 91" "0: End of conversion for CH[91] has not occured,1: End of conversion for CH[91] has occured" bitfld.long 0x0 26. "EOC_CH90,End of conversion interrupt pending bit for channel 90" "0: End of conversion for CH[90] has not occured,1: End of conversion for CH[90] has occured" line.long 0x4 "IMR,Interrupt Mask Register" bitfld.long 0x4 5. "MSKCTUTRGERR,Mask bit for CTU Trigger" "0: CTUTRGERR interrupt is disabled,1: CTUTRGERR interrupt is enabled" bitfld.long 0x4 4. "MSKEOCTU,Mask bit for EOCTU" "0: EOCTU interrupt is disabled,1: EOCTU interrupt is enabled" newline bitfld.long 0x4 3. "MSKJEOC,Mask bit for JEOC" "0: JEOC interrupt is disabled,1: JEOC interrupt is enabled" bitfld.long 0x4 2. "MSKJECH,Mask bit for JECH" "0: JECH interrupt is disabled,1: JECH interrupt is enabled" newline bitfld.long 0x4 1. "MSKNEOC,Mask bit for NEOC" "0: NEOC interrupt is disabled,1: NEOC interrupt is enabled" bitfld.long 0x4 0. "MSKNECH,Mask bit for NECH" "0: NECH interrupt is disabled,1: NECH interrupt is enabled" line.long 0x8 "ICIMR0,Internal Channel Interrupt Mask Register 0" bitfld.long 0x8 31. "IM_CH31,Interrupt mask bit for channel 31" "0: Interupt for CH[31] is disabled,1: Interupt for CH[31] is enabled" bitfld.long 0x8 30. "IM_CH30,Interrupt mask bit for channel 30" "0: Interupt for CH[30] is disabled,1: Interupt for CH[30] is enabled" newline bitfld.long 0x8 29. "IM_CH29,Interrupt mask bit for channel 29" "0: Interupt for CH[29] is disabled,1: Interupt for CH[29] is enabled" bitfld.long 0x8 28. "IM_CH28,Interrupt mask bit for channel 28" "0: Interupt for CH[28] is disabled,1: Interupt for CH[28] is enabled" newline bitfld.long 0x8 27. "IM_CH27,Interrupt mask bit for channel 27" "0: Interupt for CH[27] is disabled,1: Interupt for CH[27] is enabled" bitfld.long 0x8 26. "IM_CH26,Interrupt mask bit for channel 26" "0: Interupt for CH[26] is disabled,1: Interupt for CH[26] is enabled" newline bitfld.long 0x8 25. "IM_CH25,Interrupt mask bit for channel 25" "0: Interupt for CH[25] is disabled,1: Interupt for CH[25] is enabled" bitfld.long 0x8 24. "IM_CH24,Interrupt mask bit for channel 24" "0: Interupt for CH[24] is disabled,1: Interupt for CH[24] is enabled" group.long 0x2C++0xF line.long 0x0 "ICIMR2,Internal Channel Interrupt Mask Register 2" bitfld.long 0x0 27. "IM_CH91,Interrupt mask bit for channel 91" "0: Interupt for CH[91] is disabled,1: Interupt for CH[91] is enabled" bitfld.long 0x0 26. "IM_CH90,Interrupt mask bit for channel 90" "0: Interupt for CH[90] is disabled,1: Interupt for CH[90] is enabled" line.long 0x4 "WTISR,Watchdog Threshold Interrupt Status Register" bitfld.long 0x4 7. "WDG3H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 3." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x4 6. "WDG3L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 3." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x4 5. "WDG2H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 2." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x4 4. "WDG2L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 2." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x4 3. "WDG1H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 1." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x4 2. "WDG1L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 1." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x4 1. "WDG0H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 0." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x4 0. "WDG0L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 0." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." line.long 0x8 "WTIMR,Watchdog Threshold Interrupt Mask Register" bitfld.long 0x8 7. "MSKWDG3H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG3H is disabled.,1: Inetrupt for WDG3H is enabled." bitfld.long 0x8 6. "MSKWDG3L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG3L is disabled.,1: Inetrupt for WDG3L is enabled." newline bitfld.long 0x8 5. "MSKWDG2H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG2H is disabled.,1: Inetrupt for WDG2H is enabled." bitfld.long 0x8 4. "MSKWDG2L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG2L is disabled.,1: Inetrupt for WDG2L is enabled." newline bitfld.long 0x8 3. "MSKWDG1H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG1H is disabled.,1: Inetrupt for WDG1H is enabled." bitfld.long 0x8 2. "MSKWDG1L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG1L is disabled.,1: Inetrupt for WDG1L is enabled." newline bitfld.long 0x8 1. "MSKWDG0H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG0H is disabled.,1: Inetrupt for WDG0H is enabled." bitfld.long 0x8 0. "MSKWDG0L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG0L is disabled.,1: Inetrupt for WDG0L is enabled." line.long 0xC "WLTCR,Watchdog Level Trigger Configuration Register" bitfld.long 0xC 3. "LTMW3,LTMW3" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0xC 2. "LTMW2,LTMW2" "0: Level Trigger Mode,1: Hysteresis Mode" newline bitfld.long 0xC 1. "LTMW1,LTMW1" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0xC 0. "LTMW0,LTMW0" "0: Level Trigger Mode,1: Hysteresis Mode" group.long 0x40++0x7 line.long 0x0 "DMAE,DMA Enable Register" bitfld.long 0x0 1. "DCLR,DMA clear sequence enable" "0: DMA request cleared by Acknowledge from DMA..,1: DMA request cleared on read of data registers" bitfld.long 0x0 0. "DMAEN,DMA global enable" "0: DMA feature disabled,1: DMA feature enabled" line.long 0x4 "ICDSR0,Internal Channel DMA Select Register 0" bitfld.long 0x4 31. "DS_CH31,DS_CH31" "0: CH[31] is disabled to transfer data in DMA mode.,1: CH[31] is enabled to transfer data in DMA mode." bitfld.long 0x4 30. "DS_CH30,DS_CH30" "0: CH[30] is disabled to transfer data in DMA mode.,1: CH[30] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 29. "DS_CH29,DS_CH29" "0: CH[29] is disabled to transfer data in DMA mode.,1: CH[29] is enabled to transfer data in DMA mode." bitfld.long 0x4 28. "DS_CH28,DS_CH28" "0: CH[28] is disabled to transfer data in DMA mode.,1: CH[28] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 27. "DS_CH27,DS_CH27" "0: CH[27] is disabled to transfer data in DMA mode.,1: CH[27] is enabled to transfer data in DMA mode." bitfld.long 0x4 26. "DS_CH26,DS_CH26" "0: CH[26] is disabled to transfer data in DMA mode.,1: CH[26] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 25. "DS_CH25,DS_CH25" "0: CH[25] is disabled to transfer data in DMA mode.,1: CH[25] is enabled to transfer data in DMA mode." bitfld.long 0x4 24. "DS_CH24,DS_CH24" "0: CH[24] is disabled to transfer data in DMA mode.,1: CH[24] is enabled to transfer data in DMA mode." group.long 0x4C++0x3 line.long 0x0 "ICDSR2,Internal Channel DMA Select Register 2" bitfld.long 0x0 27. "DS_CH91,DS_CH91" "0: CH[91] is disabled to transfer data in DMA mode.,1: CH[91] is enabled to transfer data in DMA mode." bitfld.long 0x0 26. "DS_CH90,DS_CH90" "0: CH[90] is disabled to transfer data in DMA mode.,1: CH[90] is enabled to transfer data in DMA mode." group.long 0x60++0xF line.long 0x0 "WTHRHLR0,Watchdog Threshold Register 0" hexmask.long.word 0x0 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x0 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x4 "WTHRHLR1,Watchdog Threshold Register 1" hexmask.long.word 0x4 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x4 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x8 "WTHRHLR2,Watchdog Threshold Register 2" hexmask.long.word 0x8 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x8 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0xC "WTHRHLR3,Watchdog Threshold Register 3" hexmask.long.word 0xC 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0xC 0.--11. 1. "THRL,Low threshold value for channel x" group.long 0x94++0x13 line.long 0x0 "CTR0,Conversion Timing Register 0" bitfld.long 0x0 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x0 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x4 "CTR1,Conversion Timing Register 1" bitfld.long 0x4 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x4 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x4 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x8 "CTR2,Conversion Timing Register 2" bitfld.long 0x8 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x8 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x8 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0xC "CTR3,Conversion Timing Register 3" bitfld.long 0xC 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0xC 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0xC 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x10 "ICNCMR0,Internal Channel Normal Conversion Mask Register 0" bitfld.long 0x10 31. "NCE_CH31,NCE_CH31" "0: Normal conversion is disabled for CH[31].,1: Normal conversion is enabled for CH[31]." bitfld.long 0x10 30. "NCE_CH30,NCE_CH30" "0: Normal conversion is disabled for CH[30].,1: Normal conversion is enabled for CH[30]." newline bitfld.long 0x10 29. "NCE_CH29,NCE_CH29" "0: Normal conversion is disabled for CH[29].,1: Normal conversion is enabled for CH[29]." bitfld.long 0x10 28. "NCE_CH28,NCE_CH28" "0: Normal conversion is disabled for CH[28].,1: Normal conversion is enabled for CH[28]." newline bitfld.long 0x10 27. "NCE_CH27,NCE_CH27" "0: Normal conversion is disabled for CH[27].,1: Normal conversion is enabled for CH[27]." bitfld.long 0x10 26. "NCE_CH26,NCE_CH26" "0: Normal conversion is disabled for CH[26].,1: Normal conversion is enabled for CH[26]." newline bitfld.long 0x10 25. "NCE_CH25,NCE_CH25" "0: Normal conversion is disabled for CH[25].,1: Normal conversion is enabled for CH[25]." bitfld.long 0x10 24. "NCE_CH24,NCE_CH24" "0: Normal conversion is disabled for CH[24].,1: Normal conversion is enabled for CH[24]." group.long 0xAC++0x3 line.long 0x0 "ICNCMR2,Internal Channel Normal Conversion Mask Register 2" bitfld.long 0x0 27. "NCE_CH91,NCE_CH91" "0: Normal conversion is disabled for CH[91].,1: Normal conversion is enabled for CH[91]." bitfld.long 0x0 26. "NCE_CH90,NCE_CH90" "0: Normal conversion is disabled for CH[90].,1: Normal conversion is enabled for CH[90]." group.long 0xB4++0x3 line.long 0x0 "ICJCMR0,Internal Channel Injected Conversion Mask Register 0" bitfld.long 0x0 31. "JCE_CH31,JCE_CH31" "0: Injected conversion is disabled for CH[31].,1: Injected conversion is enabled for CH[31]." bitfld.long 0x0 30. "JCE_CH30,JCE_CH30" "0: Injected conversion is disabled for CH[30].,1: Injected conversion is enabled for CH[30]." newline bitfld.long 0x0 29. "JCE_CH29,JCE_CH29" "0: Injected conversion is disabled for CH[29].,1: Injected conversion is enabled for CH[29]." bitfld.long 0x0 28. "JCE_CH28,JCE_CH28" "0: Injected conversion is disabled for CH[28].,1: Injected conversion is enabled for CH[28]." newline bitfld.long 0x0 27. "JCE_CH27,JCE_CH27" "0: Injected conversion is disabled for CH[27].,1: Injected conversion is enabled for CH[27]." bitfld.long 0x0 26. "JCE_CH26,JCE_CH26" "0: Injected conversion is disabled for CH[26].,1: Injected conversion is enabled for CH[26]." newline bitfld.long 0x0 25. "JCE_CH25,JCE_CH25" "0: Injected conversion is disabled for CH[25].,1: Injected conversion is enabled for CH[25]." bitfld.long 0x0 24. "JCE_CH24,JCE_CH24" "0: Injected conversion is disabled for CH[24].,1: Injected conversion is enabled for CH[24]." group.long 0xBC++0x3 line.long 0x0 "ICJCMR2,Internal Channel Injected Conversion Mask Register 2" bitfld.long 0x0 27. "JCE_CH91,JCE_CH91" "0: Injected conversion is disabled for CH[91].,1: Injected conversion is enabled for CH[91]." bitfld.long 0x0 26. "JCE_CH90,JCE_CH90" "0: Injected conversion is disabled for CH[90].,1: Injected conversion is enabled for CH[90]." group.long 0xC8++0x3 line.long 0x0 "PDEDR,Power Down Exit Delay Register" hexmask.long.byte 0x0 0.--7. 1. "PDED,Defines the delay between the power-down bit reset and the starting of conversion." group.long 0x160++0x1F line.long 0x0 "ICDR24,Internal Channel Data Register 24" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4 "ICDR25,Internal Channel Data Register 25" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x8 "ICDR26,Internal Channel Data Register 26" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x8 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xC "ICDR27,Internal Channel Data Register 27" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xC 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x10 "ICDR28,Internal Channel Data Register 28" bitfld.long 0x10 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x10 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x10 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x10 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x10 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x10 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x10 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x14 "ICDR29,Internal Channel Data Register 29" bitfld.long 0x14 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x14 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x14 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x14 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x14 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x14 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x14 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x18 "ICDR30,Internal Channel Data Register 30" bitfld.long 0x18 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x18 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x18 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x18 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x18 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x18 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x18 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x1C "ICDR31,Internal Channel Data Register 31" bitfld.long 0x1C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x1C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x1C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x1C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x1C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x1C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x1C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" group.long 0x268++0x7 line.long 0x0 "ICDR90,Internal Channel Data Register 90" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4 "ICDR91,Internal Channel Data Register 91" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" group.long 0x2BC++0x3 line.long 0x0 "ICWSELR3,Internal Channel Watchdog Select Register 3" bitfld.long 0x0 28.--29. "WSEL_CH31,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH30,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH29,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH28,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 12.--13. "WSEL_CH27,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 8.--9. "WSEL_CH26,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 4.--5. "WSEL_CH25,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 0.--1. "WSEL_CH24,0000 THRHLR0 register is selected" "0,1,2,3" group.long 0x2DC++0x7 line.long 0x0 "ICWSELR11,Internal Channel Watchdog Select Register 11" bitfld.long 0x0 12.--13. "WSEL_CH91,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 8.--9. "WSEL_CH90,0000 THRHLR0 register is selected" "0,1,2,3" line.long 0x4 "ICWENR0,Internal Channel Watchdog Enable Register 0" bitfld.long 0x4 31. "WEN_CH31,WEN_CH31" "0: Watchdog feature is disabled for CH[31],1: Watchdog feature is enabled fir CH[31]" bitfld.long 0x4 30. "WEN_CH30,WEN_CH30" "0: Watchdog feature is disabled for CH[30],1: Watchdog feature is enabled fir CH[30]" newline bitfld.long 0x4 29. "WEN_CH29,WEN_CH29" "0: Watchdog feature is disabled for CH[29],1: Watchdog feature is enabled fir CH[29]" bitfld.long 0x4 28. "WEN_CH28,WEN_CH28" "0: Watchdog feature is disabled for CH[28],1: Watchdog feature is enabled fir CH[28]" newline bitfld.long 0x4 27. "WEN_CH27,WEN_CH27" "0: Watchdog feature is disabled for CH[27],1: Watchdog feature is enabled fir CH[27]" bitfld.long 0x4 26. "WEN_CH26,WEN_CH26" "0: Watchdog feature is disabled for CH[26],1: Watchdog feature is enabled fir CH[26]" newline bitfld.long 0x4 25. "WEN_CH25,WEN_CH25" "0: Watchdog feature is disabled for CH[25],1: Watchdog feature is enabled fir CH[25]" bitfld.long 0x4 24. "WEN_CH24,WEN_CH24" "0: Watchdog feature is disabled for CH[24],1: Watchdog feature is enabled fir CH[24]" group.long 0x2E8++0x3 line.long 0x0 "ICWENR2,Internal Channel Watchdog Enable Register 2" bitfld.long 0x0 27. "WEN_CH91,WEN_CH91" "0: Watchdog feature is disabled for CH[91],1: Watchdog feature is enabled fir CH[91]" bitfld.long 0x0 26. "WEN_CH90,WEN_CH90" "0: Watchdog feature is disabled for CH[90],1: Watchdog feature is enabled fir CH[90]" group.long 0x2F0++0x3 line.long 0x0 "ICAWORR0,Internal Channel Analog Watchdog Out of Range Register 0" bitfld.long 0x0 31. "AWOR_CH31,Analog watchdog out of range status for channel 31 provided corresponding WEN_CH31 bit is set." "0: CH[31] converted data is not out of range..,1: CH[31] converted data is out of range determined.." bitfld.long 0x0 30. "AWOR_CH30,Analog watchdog out of range status for channel 30 provided corresponding WEN_CH30 bit is set." "0: CH[30] converted data is not out of range..,1: CH[30] converted data is out of range determined.." newline bitfld.long 0x0 29. "AWOR_CH29,Analog watchdog out of range status for channel 29 provided corresponding WEN_CH29 bit is set." "0: CH[29] converted data is not out of range..,1: CH[29] converted data is out of range determined.." bitfld.long 0x0 28. "AWOR_CH28,Analog watchdog out of range status for channel 28 provided corresponding WEN_CH28 bit is set." "0: CH[28] converted data is not out of range..,1: CH[28] converted data is out of range determined.." newline bitfld.long 0x0 27. "AWOR_CH27,Analog watchdog out of range status for channel 27 provided corresponding WEN_CH27 bit is set." "0: CH[27] converted data is not out of range..,1: CH[27] converted data is out of range determined.." bitfld.long 0x0 26. "AWOR_CH26,Analog watchdog out of range status for channel 26 provided corresponding WEN_CH26 bit is set." "0: CH[26] converted data is not out of range..,1: CH[26] converted data is out of range determined.." newline bitfld.long 0x0 25. "AWOR_CH25,Analog watchdog out of range status for channel 25 provided corresponding WEN_CH25 bit is set." "0: CH[25] converted data is not out of range..,1: CH[25] converted data is out of range determined.." bitfld.long 0x0 24. "AWOR_CH24,Analog watchdog out of range status for channel 24 provided corresponding WEN_CH24 bit is set." "0: CH[24] converted data is not out of range..,1: CH[24] converted data is out of range determined.." group.long 0x2F8++0x3 line.long 0x0 "ICAWORR2,Internal Channel Analog Watchdog Out of Range Register 2" bitfld.long 0x0 27. "AWOR_CH91,Analog watchdog out of range status for channel 91 provided corresponding WEN_CH91 bit is set." "0: CH[91] converted data is not out of range..,1: CH[91] converted data is out of range determined.." bitfld.long 0x0 26. "AWOR_CH90,Analog watchdog out of range status for channel 90 provided corresponding WEN_CH90 bit is set." "0: CH[90] converted data is not out of range..,1: CH[90] converted data is out of range determined.." group.long 0x400++0x13 line.long 0x0 "TCIPR,Test Channel Interrupt Pending Register" bitfld.long 0x0 31. "EOC_CH127,End of conversion interrupt pending bit for channel 127" "0: End of conversion for CH[127] has not occurred.,1: End of conversion for CH[127] has occurred" bitfld.long 0x0 30. "EOC_CH126,End of conversion interrupt pending bit for channel 126" "0: End of conversion for CH[126] has not occurred.,1: End of conversion for CH[126] has occurred" newline bitfld.long 0x0 29. "EOC_CH125,End of conversion interrupt pending bit for channel 125" "0: End of conversion for CH[125] has not occurred.,1: End of conversion for CH[125] has occurred" bitfld.long 0x0 28. "EOC_CH124,End of conversion interrupt pending bit for channel 124" "0: End of conversion for CH[124] has not occurred.,1: End of conversion for CH[124] has occurred" line.long 0x4 "TCIMR,Test Channel Interrupt Mask Register" bitfld.long 0x4 31. "IM_CH127,IM_CH127" "0: Interrupt for CH[127] is disabled.,1: Interrupt for CH[127] is enabled." bitfld.long 0x4 30. "IM_CH126,IM_CH126" "0: Interrupt for CH[126] is disabled.,1: Interrupt for CH[126] is enabled." newline bitfld.long 0x4 29. "IM_CH125,IM_CH125" "0: Interrupt for CH[125] is disabled.,1: Interrupt for CH[125] is enabled." bitfld.long 0x4 28. "IM_CH124,IM_CH124" "0: Interrupt for CH[124] is disabled.,1: Interrupt for CH[124] is enabled." line.long 0x8 "TCDSR,Test Channel DMA Select Register" bitfld.long 0x8 31. "DS_CH127,DS_CH127" "0: CH[127] is disabled to transfer data in DMA mode.,1: CH[127] is enabled to transfer data in DMA mode." bitfld.long 0x8 30. "DS_CH126,DS_CH126" "0: CH[126] is disabled to transfer data in DMA mode.,1: CH[126] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 29. "DS_CH125,DS_CH125" "0: CH[125] is disabled to transfer data in DMA mode.,1: CH[125] is enabled to transfer data in DMA mode." bitfld.long 0x8 28. "DS_CH124,DS_CH124" "0: CH[124] is disabled to transfer data in DMA mode.,1: CH[124] is enabled to transfer data in DMA mode." line.long 0xC "TCNCMR,Test Channel Normal Conversion Mask Register" bitfld.long 0xC 31. "NCE_CH127,NCE_CH127" "0: Normal conversion is disabled for CH[127].,1: Normal conversion is enabled for CH[127]." bitfld.long 0xC 30. "NCE_CH126,NCE_CH126" "0: Normal conversion is disabled for CH[126].,1: Normal conversion is enabled for CH[126]." newline bitfld.long 0xC 29. "NCE_CH125,NCE_CH125" "0: Normal conversion is disabled for CH[125].,1: Normal conversion is enabled for CH[125]." bitfld.long 0xC 28. "NCE_CH124,NCE_CH124" "0: Normal conversion is disabled for CH[124].,1: Normal conversion is enabled for CH[124]." line.long 0x10 "TCJCMR,Test Channel Injected Conversion Mask Register" bitfld.long 0x10 31. "JCE_CH127,JCE_CH127" "0: Injected conversion is disabled for CH[127].,1: Injected conversion is enabled for CH[127]." bitfld.long 0x10 30. "JCE_CH126,JCE_CH126" "0: Injected conversion is disabled for CH[126].,1: Injected conversion is enabled for CH[126]." newline bitfld.long 0x10 29. "JCE_CH125,JCE_CH125" "0: Injected conversion is disabled for CH[125].,1: Injected conversion is enabled for CH[125]." bitfld.long 0x10 28. "JCE_CH124,JCE_CH124" "0: Injected conversion is disabled for CH[124].,1: Injected conversion is enabled for CH[124]." group.long 0x420++0xB line.long 0x0 "TCWSELR3,Test Channel Watchdog Select Register 3" bitfld.long 0x0 28.--29. "WSEL_CH127,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH126,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH125,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH124,0000 THRHLR0 register is selected" "0,1,2,3" line.long 0x4 "TCWENR,Test Channel Watchdog Enable Register" bitfld.long 0x4 31. "WEN_CH127,WEN_CH127" "0: Watchdog feature is disabled for CH[127].,1: Watchdog feature is enabled for CH[127]." bitfld.long 0x4 30. "WEN_CH126,WEN_CH126" "0: Watchdog feature is disabled for CH[126].,1: Watchdog feature is enabled for CH[126]." newline bitfld.long 0x4 29. "WEN_CH125,WEN_CH125" "0: Watchdog feature is disabled for CH[125].,1: Watchdog feature is enabled for CH[125]." bitfld.long 0x4 28. "WEN_CH124,WEN_CH124" "0: Watchdog feature is disabled for CH[124].,1: Watchdog feature is enabled for CH[124]." line.long 0x8 "TCAWORR,Test Channel Analog Watchdog Out of Range Register" bitfld.long 0x8 31. "AWOR_CH127,Analog watchdog out of range status for channel 127 provided corresponding WEN_CH127 bit is set." "0: CH[127] converted data is not out of range..,1: CH[127] converted data is out of range.." bitfld.long 0x8 30. "AWOR_CH126,Analog watchdog out of range status for channel 126 provided corresponding WEN_CH126 bit is set." "0: CH[126] converted data is not out of range..,1: CH[126] converted data is out of range.." newline bitfld.long 0x8 29. "AWOR_CH125,Analog watchdog out of range status for channel 125 provided corresponding WEN_CH125 bit is set." "0: CH[125] converted data is not out of range..,1: CH[125] converted data is out of range.." bitfld.long 0x8 28. "AWOR_CH124,Analog watchdog out of range status for channel 124 provided corresponding WEN_CH124 bit is set." "0: CH[124] converted data is not out of range..,1: CH[124] converted data is out of range.." group.long 0x44C++0x3 line.long 0x0 "TCCAPR7,Test Channel Connection with Analog Pin Register 7" bitfld.long 0x0 31. "ESIC_TCH31,Enable short with internal channel for test channel 31" "0: Test channel 31 cannot be shorted with internal..,1: Test channel 31 can be shorted with internal.." hexmask.long.byte 0x0 24.--30. 1. "ICSEL_TCH31,Internal channel selection for short with test channel 31" newline bitfld.long 0x0 23. "ESIC_TCH30,Enable short with internal channel for test channel 30" "0: Test channel 30 cannot be shorted with internal..,1: Test channel 30 can be shorted with internal.." hexmask.long.byte 0x0 16.--22. 1. "ICSEL_TCH30,Internal channel selection for short with test channel 30" newline bitfld.long 0x0 15. "ESIC_TCH29,Enable short with internal channel for test channel 29" "0: Test channel 29 cannot be shorted with internal..,1: Test channel 29 can be shorted with internal.." hexmask.long.byte 0x0 8.--14. 1. "ICSEL_TCH29,Internal channel selection for short with test channel 29" newline bitfld.long 0x0 7. "ESIC_TCH28,Enable short with internal channel for test channel 28" "0: Test channel 28 cannot be shorted with internal..,1: Test channel 28 can be shorted with internal.." hexmask.long.byte 0x0 0.--6. 1. "ICSEL_TCH28,Internal channel selection for short with test channel 28" group.long 0x4C0++0xF line.long 0x0 "TCDR124,Test Channel Data Register 124" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x4 "TCDR125,Test Channel Data Register 125" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x8 "TCDR126,Test Channel Data Register 126" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xC "TCDR127,Test Channel Data Register 127" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." tree.end tree "SAR_ADC_12BIT_4" base ad:0x7029C000 group.long 0x0++0x3 line.long 0x0 "MCR,Main Configuration Register" bitfld.long 0x0 31. "OWREN,This bit enables or disables the functionality to overwrite unread converted data in ICDR TCDR ECDR registers." "0: Prevents overwrite of unread converted data new..,1: Enables converted data to be overwritten by a.." bitfld.long 0x0 30. "WLSIDE,Write left/right-aligned" "0: The conversion data in ICDR TCDR ECDR registers..,1: Conversion data is left-aligned (from 15 to (15.." newline bitfld.long 0x0 29. "MODE,One Shot/Scan" "0: One Shot Mode: Configures the normal conversion..,1: Scan Mode: Configures continuous chain.." bitfld.long 0x0 28. "XSTRTEN,This bit enables or disables the external start signal to initial a normal conversion. This can be used to synchronize multiple SARADCs concurrently." "0: External start signal is disabled,1: External start signal high level will start a.." newline bitfld.long 0x0 27. "NSTART,Setting this bit starts the chain or scan conversion. Resetting this bit during scan mode causes the current chain conversion to finish then stops the operation." "0: Cause the current chain conversion to finish and..,1: Starts the chain or scan conversion" bitfld.long 0x0 26. "NTRGEN,NTRGEN" "0: Normal trigger disabled to start a normal..,1: Normal trigger enabled to start a normal.." newline bitfld.long 0x0 24.--25. "NEDGESEL,NEDGESEL" "0: Falling edge of normal trigger is selected,1: Rising edge of normal trigger is selected,2: Both rising and falling edges of normal trigger..,3: Both rising and falling edges of normal trigger.." bitfld.long 0x0 23. "JSTART,Setting this bit will start the configured injected analog channels to be converted by software. Resetting this bit has no effect as the injected chain conversion cannot be interrupted." "0: Writting '0' has not effect,1: Starts the injected chain conversion" newline bitfld.long 0x0 22. "JTRGEN,JTRGEN" "0: Injection trigger disabled for channel injection..,1: Injection trigger enabled for channel injection" bitfld.long 0x0 20.--21. "JEDGESEL,JEDGESEL" "0: Falling edge of injection trigger is selected,1: Rising edge of injection trigger is selected,?,3: Both rising and falling edges of injection.." newline bitfld.long 0x0 19. "JTRGSEQ,JTRGSEQ" "0: Injection trigger sequence mode is disabled,1: Injection trigger sequence mode is enabled" bitfld.long 0x0 17. "CTUEN,Can be set or cleared anytime with some restriction mentioned in CTU trigger/control mode section." "0: The cross triggering unit is disabled and the..,1: The cross triggering unit is enabled and the.." newline bitfld.long 0x0 16. "CTU_MODE,This bit is present only if generic parameter CTSEN = 2 otherwise this bit is a reserved bit and always read as 0. This should be set only when ADC Digital is in powerdown mode." "0: CTU control mode is selected,1: CTU trigger mode is selected" bitfld.long 0x0 15. "WTRIGOUT,This control bit enables the Trigger on every threshold crossover event (crossing of Lower/Upper thresholds) of each WDG monitor to external trigger port (up to 16 ports for up to 16 WDGs)." "0: Trigger outputs disabled,1: Trigger ouputs enabled" newline bitfld.long 0x0 7. "ABORTCHAIN,When this bit is set the ongoing Chain Conversion is aborted. This bit is reset by hardware as soon as a new conversion is requested." "0: Conversion is not affected,1: Aborts the ongoing chain conversion" bitfld.long 0x0 6. "ABORT,When this bit is set the ongoing conversion is aborted and a new conversion is invoked. This bit is reset by hardware as soon as a new conversion is invoked." "0: Conversion is not affected,1: Aborts the ongoing conversion" newline bitfld.long 0x0 4. "FRZ,This bit enables to stop the SARADC conversions at the end of current channel conversion when SoC enters debug mode." "0: Conversions are not stopped,1: When SoC enters debug mode further conversions.." bitfld.long 0x0 2. "FCE,This bit enables the fast comparison mode for upcoming channel conversions." "0: Fast comparision mode disabled,1: Fast comparision mode enabled" newline bitfld.long 0x0 1. "EDCSELF,This bit selects the format for 3-bit output port ipp_decode_extch used as select line for external decode channel 8:1 muxes. The last three bits of external channel number are passed as is (if value 0) or converted to gray code (if value 1) and.." "0: Binary format,1: Gray code format" bitfld.long 0x0 0. "PWDN,When this bit is set the analog module is requested to enter Power Down mode." "0: SARADC is in normal mode,1: SARADC has been requested to power down" rgroup.long 0x4++0x3 line.long 0x0 "MSR,Main Status Register" bitfld.long 0x0 27. "NSTART,This status bit is used to signal that a normal conversion is ongoing." "0: Normal conversion is not taking place,1: Normal conversion is ongoing or the normal.." bitfld.long 0x0 23. "JSTART,This status bit is used to signal that an injected conversion is ongoing." "0: Injected conversion is not taking place,1: Injected conversion is ongoing" newline bitfld.long 0x0 18. "JABORTCHAIN,This status bit is used to signal that an Injected conversion chain has been aborted. This bit is reset when a new conversion starts." "0: Last injected conversion chain has not been..,1: Last injected conversion chain has been aborted" bitfld.long 0x0 16. "CTUSTART,This status bit is used to signal that a CTU conversion is ongoing. This bit is set when a CTU trigger pulse is received and the CTU conversion starts. When CTU trigger mode is enabled this bit is automatically reset when the conversion is.." "0: CTU triggered injected conversion is not taking..,1: CTU triggered injected conversion is ongoing" newline hexmask.long.byte 0x0 8.--15. 1. "CHADDR,Channel under measure address" bitfld.long 0x0 0.--2. "ADCSTATUS,The value of this parameter depends on ADC status. While requesting an external channel conversion SARADC digital interface needs to wait for a fixed time determined by DSD bitfield of DSDR before proceeding to actual sampling phase." "0: IDLE,1: Power-down,2: Wait state,?,4: Sample,?,6: Conversion,?" group.long 0x10++0x3 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CTUTRGERR,This Error Flag indicates that the next CTU trigger has been discarded as it overlapped during execution of current CTU conversion. This indicated that CTU sampling duration is less than programmed conversion time of ADC." "0: No CTU trigger overlap error condition since..,1: CTU trigger overlap error has occurred." bitfld.long 0x0 4. "EOCTU,This bit indicates the end of conversion for a CTU injected channel." "0: End of conversion of CTU triggered channel has..,1: End of conversion of CTU triggered channel has.." newline bitfld.long 0x0 3. "JEOC,This bit indicates the end of conversion for an injected channel." "0: End of conversion of injected channel has not..,1: End of conversion of injected channel has.." bitfld.long 0x0 2. "JECH,This bit indicates the end of conversion for an injected chain." "0: End of conversion of injected chain has not..,1: End of conversion of injected chain has occurred.." newline bitfld.long 0x0 1. "NEOC,This bit indicates the end of conversion for a normal channel." "0: End of conversion of normal channel has not..,1: End of conversion of normal channel has occurred.." bitfld.long 0x0 0. "NECH,This bit indicates the end of conversion for an normal chain." "0: End of conversion of normal chain has not..,1: End of conversion of normal chain has occurred.." group.long 0x18++0xB line.long 0x0 "ICIPR1,Internal Channel Interrupt Pending Register 1" bitfld.long 0x0 7. "EOC_CH39,End of conversion interrupt pending bit for channel 39" "0: End of conversion for CH[39] has not occured,1: End of conversion for CH[39] has occured" bitfld.long 0x0 6. "EOC_CH38,End of conversion interrupt pending bit for channel 38" "0: End of conversion for CH[38] has not occured,1: End of conversion for CH[38] has occured" newline bitfld.long 0x0 5. "EOC_CH37,End of conversion interrupt pending bit for channel 37" "0: End of conversion for CH[37] has not occured,1: End of conversion for CH[37] has occured" bitfld.long 0x0 4. "EOC_CH36,End of conversion interrupt pending bit for channel 36" "0: End of conversion for CH[36] has not occured,1: End of conversion for CH[36] has occured" newline bitfld.long 0x0 3. "EOC_CH35,End of conversion interrupt pending bit for channel 35" "0: End of conversion for CH[35] has not occured,1: End of conversion for CH[35] has occured" bitfld.long 0x0 2. "EOC_CH34,End of conversion interrupt pending bit for channel 34" "0: End of conversion for CH[34] has not occured,1: End of conversion for CH[34] has occured" newline bitfld.long 0x0 1. "EOC_CH33,End of conversion interrupt pending bit for channel 33" "0: End of conversion for CH[33] has not occured,1: End of conversion for CH[33] has occured" bitfld.long 0x0 0. "EOC_CH32,End of conversion interrupt pending bit for channel 32" "0: End of conversion for CH[32] has not occured,1: End of conversion for CH[32] has occured" line.long 0x4 "ICIPR2,Internal Channel Interrupt Pending Register 2" bitfld.long 0x4 29. "EOC_CH93,End of conversion interrupt pending bit for channel 93" "0: End of conversion for CH[93] has not occured,1: End of conversion for CH[93] has occured" bitfld.long 0x4 28. "EOC_CH92,End of conversion interrupt pending bit for channel 92" "0: End of conversion for CH[92] has not occured,1: End of conversion for CH[92] has occured" line.long 0x8 "IMR,Interrupt Mask Register" bitfld.long 0x8 5. "MSKCTUTRGERR,Mask bit for CTU Trigger" "0: CTUTRGERR interrupt is disabled,1: CTUTRGERR interrupt is enabled" bitfld.long 0x8 4. "MSKEOCTU,Mask bit for EOCTU" "0: EOCTU interrupt is disabled,1: EOCTU interrupt is enabled" newline bitfld.long 0x8 3. "MSKJEOC,Mask bit for JEOC" "0: JEOC interrupt is disabled,1: JEOC interrupt is enabled" bitfld.long 0x8 2. "MSKJECH,Mask bit for JECH" "0: JECH interrupt is disabled,1: JECH interrupt is enabled" newline bitfld.long 0x8 1. "MSKNEOC,Mask bit for NEOC" "0: NEOC interrupt is disabled,1: NEOC interrupt is enabled" bitfld.long 0x8 0. "MSKNECH,Mask bit for NECH" "0: NECH interrupt is disabled,1: NECH interrupt is enabled" group.long 0x28++0x13 line.long 0x0 "ICIMR1,Internal Channel Interrupt Mask Register 1" bitfld.long 0x0 7. "IM_CH39,Interrupt mask bit for channel 39" "0: Interupt for CH[39] is disabled,1: Interupt for CH[39] is enabled" bitfld.long 0x0 6. "IM_CH38,Interrupt mask bit for channel 38" "0: Interupt for CH[38] is disabled,1: Interupt for CH[38] is enabled" newline bitfld.long 0x0 5. "IM_CH37,Interrupt mask bit for channel 37" "0: Interupt for CH[37] is disabled,1: Interupt for CH[37] is enabled" bitfld.long 0x0 4. "IM_CH36,Interrupt mask bit for channel 36" "0: Interupt for CH[36] is disabled,1: Interupt for CH[36] is enabled" newline bitfld.long 0x0 3. "IM_CH35,Interrupt mask bit for channel 35" "0: Interupt for CH[35] is disabled,1: Interupt for CH[35] is enabled" bitfld.long 0x0 2. "IM_CH34,Interrupt mask bit for channel 34" "0: Interupt for CH[34] is disabled,1: Interupt for CH[34] is enabled" newline bitfld.long 0x0 1. "IM_CH33,Interrupt mask bit for channel 33" "0: Interupt for CH[33] is disabled,1: Interupt for CH[33] is enabled" bitfld.long 0x0 0. "IM_CH32,Interrupt mask bit for channel 32" "0: Interupt for CH[32] is disabled,1: Interupt for CH[32] is enabled" line.long 0x4 "ICIMR2,Internal Channel Interrupt Mask Register 2" bitfld.long 0x4 29. "IM_CH93,Interrupt mask bit for channel 93" "0: Interupt for CH[93] is disabled,1: Interupt for CH[93] is enabled" bitfld.long 0x4 28. "IM_CH92,Interrupt mask bit for channel 92" "0: Interupt for CH[92] is disabled,1: Interupt for CH[92] is enabled" line.long 0x8 "WTISR,Watchdog Threshold Interrupt Status Register" bitfld.long 0x8 7. "WDG3H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 3." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x8 6. "WDG3L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 3." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x8 5. "WDG2H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 2." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x8 4. "WDG2L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 2." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x8 3. "WDG1H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 1." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x8 2. "WDG1L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 1." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x8 1. "WDG0H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 0." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x8 0. "WDG0L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 0." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." line.long 0xC "WTIMR,Watchdog Threshold Interrupt Mask Register" bitfld.long 0xC 7. "MSKWDG3H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG3H is disabled.,1: Inetrupt for WDG3H is enabled." bitfld.long 0xC 6. "MSKWDG3L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG3L is disabled.,1: Inetrupt for WDG3L is enabled." newline bitfld.long 0xC 5. "MSKWDG2H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG2H is disabled.,1: Inetrupt for WDG2H is enabled." bitfld.long 0xC 4. "MSKWDG2L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG2L is disabled.,1: Inetrupt for WDG2L is enabled." newline bitfld.long 0xC 3. "MSKWDG1H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG1H is disabled.,1: Inetrupt for WDG1H is enabled." bitfld.long 0xC 2. "MSKWDG1L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG1L is disabled.,1: Inetrupt for WDG1L is enabled." newline bitfld.long 0xC 1. "MSKWDG0H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG0H is disabled.,1: Inetrupt for WDG0H is enabled." bitfld.long 0xC 0. "MSKWDG0L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG0L is disabled.,1: Inetrupt for WDG0L is enabled." line.long 0x10 "WLTCR,Watchdog Level Trigger Configuration Register" bitfld.long 0x10 3. "LTMW3,LTMW3" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0x10 2. "LTMW2,LTMW2" "0: Level Trigger Mode,1: Hysteresis Mode" newline bitfld.long 0x10 1. "LTMW1,LTMW1" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0x10 0. "LTMW0,LTMW0" "0: Level Trigger Mode,1: Hysteresis Mode" group.long 0x40++0x3 line.long 0x0 "DMAE,DMA Enable Register" bitfld.long 0x0 1. "DCLR,DMA clear sequence enable" "0: DMA request cleared by Acknowledge from DMA..,1: DMA request cleared on read of data registers" bitfld.long 0x0 0. "DMAEN,DMA global enable" "0: DMA feature disabled,1: DMA feature enabled" group.long 0x48++0x7 line.long 0x0 "ICDSR1,Internal Channel DMA Select Register 1" bitfld.long 0x0 7. "DS_CH39,DS_CH39" "0: CH[39] is disabled to transfer data in DMA mode.,1: CH[39] is enabled to transfer data in DMA mode." bitfld.long 0x0 6. "DS_CH38,DS_CH38" "0: CH[38] is disabled to transfer data in DMA mode.,1: CH[38] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 5. "DS_CH37,DS_CH37" "0: CH[37] is disabled to transfer data in DMA mode.,1: CH[37] is enabled to transfer data in DMA mode." bitfld.long 0x0 4. "DS_CH36,DS_CH36" "0: CH[36] is disabled to transfer data in DMA mode.,1: CH[36] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 3. "DS_CH35,DS_CH35" "0: CH[35] is disabled to transfer data in DMA mode.,1: CH[35] is enabled to transfer data in DMA mode." bitfld.long 0x0 2. "DS_CH34,DS_CH34" "0: CH[34] is disabled to transfer data in DMA mode.,1: CH[34] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 1. "DS_CH33,DS_CH33" "0: CH[33] is disabled to transfer data in DMA mode.,1: CH[33] is enabled to transfer data in DMA mode." bitfld.long 0x0 0. "DS_CH32,DS_CH32" "0: CH[32] is disabled to transfer data in DMA mode.,1: CH[32] is enabled to transfer data in DMA mode." line.long 0x4 "ICDSR2,Internal Channel DMA Select Register 2" bitfld.long 0x4 29. "DS_CH93,DS_CH93" "0: CH[93] is disabled to transfer data in DMA mode.,1: CH[93] is enabled to transfer data in DMA mode." bitfld.long 0x4 28. "DS_CH92,DS_CH92" "0: CH[92] is disabled to transfer data in DMA mode.,1: CH[92] is enabled to transfer data in DMA mode." group.long 0x60++0xF line.long 0x0 "WTHRHLR0,Watchdog Threshold Register 0" hexmask.long.word 0x0 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x0 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x4 "WTHRHLR1,Watchdog Threshold Register 1" hexmask.long.word 0x4 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x4 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x8 "WTHRHLR2,Watchdog Threshold Register 2" hexmask.long.word 0x8 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x8 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0xC "WTHRHLR3,Watchdog Threshold Register 3" hexmask.long.word 0xC 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0xC 0.--11. 1. "THRL,Low threshold value for channel x" group.long 0x94++0xF line.long 0x0 "CTR0,Conversion Timing Register 0" bitfld.long 0x0 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x0 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x4 "CTR1,Conversion Timing Register 1" bitfld.long 0x4 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x4 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x4 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x8 "CTR2,Conversion Timing Register 2" bitfld.long 0x8 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x8 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x8 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0xC "CTR3,Conversion Timing Register 3" bitfld.long 0xC 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0xC 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0xC 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." group.long 0xA8++0x7 line.long 0x0 "ICNCMR1,Internal Channel Normal Conversion Mask Register 1" bitfld.long 0x0 7. "NCE_CH39,NCE_CH39" "0: Normal conversion is disabled for CH[39].,1: Normal conversion is enabled for CH[39]." bitfld.long 0x0 6. "NCE_CH38,NCE_CH38" "0: Normal conversion is disabled for CH[38].,1: Normal conversion is enabled for CH[38]." newline bitfld.long 0x0 5. "NCE_CH37,NCE_CH37" "0: Normal conversion is disabled for CH[37].,1: Normal conversion is enabled for CH[37]." bitfld.long 0x0 4. "NCE_CH36,NCE_CH36" "0: Normal conversion is disabled for CH[36].,1: Normal conversion is enabled for CH[36]." newline bitfld.long 0x0 3. "NCE_CH35,NCE_CH35" "0: Normal conversion is disabled for CH[35].,1: Normal conversion is enabled for CH[35]." bitfld.long 0x0 2. "NCE_CH34,NCE_CH34" "0: Normal conversion is disabled for CH[34].,1: Normal conversion is enabled for CH[34]." newline bitfld.long 0x0 1. "NCE_CH33,NCE_CH33" "0: Normal conversion is disabled for CH[33].,1: Normal conversion is enabled for CH[33]." bitfld.long 0x0 0. "NCE_CH32,NCE_CH32" "0: Normal conversion is disabled for CH[32].,1: Normal conversion is enabled for CH[32]." line.long 0x4 "ICNCMR2,Internal Channel Normal Conversion Mask Register 2" bitfld.long 0x4 29. "NCE_CH93,NCE_CH93" "0: Normal conversion is disabled for CH[93].,1: Normal conversion is enabled for CH[93]." bitfld.long 0x4 28. "NCE_CH92,NCE_CH92" "0: Normal conversion is disabled for CH[92].,1: Normal conversion is enabled for CH[92]." group.long 0xB8++0x7 line.long 0x0 "ICJCMR1,Internal Channel Injected Conversion Mask Register 1" bitfld.long 0x0 7. "JCE_CH39,JCE_CH39" "0: Injected conversion is disabled for CH[39].,1: Injected conversion is enabled for CH[39]." bitfld.long 0x0 6. "JCE_CH38,JCE_CH38" "0: Injected conversion is disabled for CH[38].,1: Injected conversion is enabled for CH[38]." newline bitfld.long 0x0 5. "JCE_CH37,JCE_CH37" "0: Injected conversion is disabled for CH[37].,1: Injected conversion is enabled for CH[37]." bitfld.long 0x0 4. "JCE_CH36,JCE_CH36" "0: Injected conversion is disabled for CH[36].,1: Injected conversion is enabled for CH[36]." newline bitfld.long 0x0 3. "JCE_CH35,JCE_CH35" "0: Injected conversion is disabled for CH[35].,1: Injected conversion is enabled for CH[35]." bitfld.long 0x0 2. "JCE_CH34,JCE_CH34" "0: Injected conversion is disabled for CH[34].,1: Injected conversion is enabled for CH[34]." newline bitfld.long 0x0 1. "JCE_CH33,JCE_CH33" "0: Injected conversion is disabled for CH[33].,1: Injected conversion is enabled for CH[33]." bitfld.long 0x0 0. "JCE_CH32,JCE_CH32" "0: Injected conversion is disabled for CH[32].,1: Injected conversion is enabled for CH[32]." line.long 0x4 "ICJCMR2,Internal Channel Injected Conversion Mask Register 2" bitfld.long 0x4 29. "JCE_CH93,JCE_CH93" "0: Injected conversion is disabled for CH[93].,1: Injected conversion is enabled for CH[93]." bitfld.long 0x4 28. "JCE_CH92,JCE_CH92" "0: Injected conversion is disabled for CH[92].,1: Injected conversion is enabled for CH[92]." group.long 0xC8++0x3 line.long 0x0 "PDEDR,Power Down Exit Delay Register" hexmask.long.byte 0x0 0.--7. 1. "PDED,Defines the delay between the power-down bit reset and the starting of conversion." group.long 0x180++0x1F line.long 0x0 "ICDR32,Internal Channel Data Register 32" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4 "ICDR33,Internal Channel Data Register 33" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x8 "ICDR34,Internal Channel Data Register 34" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x8 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xC "ICDR35,Internal Channel Data Register 35" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xC 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x10 "ICDR36,Internal Channel Data Register 36" bitfld.long 0x10 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x10 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x10 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x10 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x10 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x10 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x10 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x14 "ICDR37,Internal Channel Data Register 37" bitfld.long 0x14 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x14 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x14 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x14 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x14 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x14 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x14 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x18 "ICDR38,Internal Channel Data Register 38" bitfld.long 0x18 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x18 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x18 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x18 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x18 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x18 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x18 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x1C "ICDR39,Internal Channel Data Register 39" bitfld.long 0x1C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x1C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x1C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x1C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x1C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x1C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x1C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" group.long 0x270++0x7 line.long 0x0 "ICDR92,Internal Channel Data Register 92" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4 "ICDR93,Internal Channel Data Register 93" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" group.long 0x2C0++0x3 line.long 0x0 "ICWSELR4,Internal Channel Watchdog Select Register 4" bitfld.long 0x0 28.--29. "WSEL_CH39,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH38,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH37,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH36,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 12.--13. "WSEL_CH35,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 8.--9. "WSEL_CH34,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 4.--5. "WSEL_CH33,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 0.--1. "WSEL_CH32,0000 THRHLR0 register is selected" "0,1,2,3" group.long 0x2DC++0x3 line.long 0x0 "ICWSELR11,Internal Channel Watchdog Select Register 11" bitfld.long 0x0 20.--21. "WSEL_CH93,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH92,0000 THRHLR0 register is selected" "0,1,2,3" group.long 0x2E4++0x7 line.long 0x0 "ICWENR1,Internal Channel Watchdog Enable Register 1" bitfld.long 0x0 7. "WEN_CH39,WEN_CH39" "0: Watchdog feature is disabled for CH[39],1: Watchdog feature is enabled fir CH[39]" bitfld.long 0x0 6. "WEN_CH38,WEN_CH38" "0: Watchdog feature is disabled for CH[38],1: Watchdog feature is enabled fir CH[38]" newline bitfld.long 0x0 5. "WEN_CH37,WEN_CH37" "0: Watchdog feature is disabled for CH[37],1: Watchdog feature is enabled fir CH[37]" bitfld.long 0x0 4. "WEN_CH36,WEN_CH36" "0: Watchdog feature is disabled for CH[36],1: Watchdog feature is enabled fir CH[36]" newline bitfld.long 0x0 3. "WEN_CH35,WEN_CH35" "0: Watchdog feature is disabled for CH[35],1: Watchdog feature is enabled fir CH[35]" bitfld.long 0x0 2. "WEN_CH34,WEN_CH34" "0: Watchdog feature is disabled for CH[34],1: Watchdog feature is enabled fir CH[34]" newline bitfld.long 0x0 1. "WEN_CH33,WEN_CH33" "0: Watchdog feature is disabled for CH[33],1: Watchdog feature is enabled fir CH[33]" bitfld.long 0x0 0. "WEN_CH32,WEN_CH32" "0: Watchdog feature is disabled for CH[32],1: Watchdog feature is enabled fir CH[32]" line.long 0x4 "ICWENR2,Internal Channel Watchdog Enable Register 2" bitfld.long 0x4 29. "WEN_CH93,WEN_CH93" "0: Watchdog feature is disabled for CH[93],1: Watchdog feature is enabled fir CH[93]" bitfld.long 0x4 28. "WEN_CH92,WEN_CH92" "0: Watchdog feature is disabled for CH[92],1: Watchdog feature is enabled fir CH[92]" group.long 0x2F4++0x7 line.long 0x0 "ICAWORR1,Internal Channel Analog Watchdog Out of Range Register 1" bitfld.long 0x0 7. "AWOR_CH39,Analog watchdog out of range status for channel 39 provided corresponding WEN_CH39 bit is set." "0: CH[39] converted data is not out of range..,1: CH[39] converted data is out of range determined.." bitfld.long 0x0 6. "AWOR_CH38,Analog watchdog out of range status for channel 38 provided corresponding WEN_CH38 bit is set." "0: CH[38] converted data is not out of range..,1: CH[38] converted data is out of range determined.." newline bitfld.long 0x0 5. "AWOR_CH37,Analog watchdog out of range status for channel 37 provided corresponding WEN_CH37 bit is set." "0: CH[37] converted data is not out of range..,1: CH[37] converted data is out of range determined.." bitfld.long 0x0 4. "AWOR_CH36,Analog watchdog out of range status for channel 36 provided corresponding WEN_CH36 bit is set." "0: CH[36] converted data is not out of range..,1: CH[36] converted data is out of range determined.." newline bitfld.long 0x0 3. "AWOR_CH35,Analog watchdog out of range status for channel 35 provided corresponding WEN_CH35 bit is set." "0: CH[35] converted data is not out of range..,1: CH[35] converted data is out of range determined.." bitfld.long 0x0 2. "AWOR_CH34,Analog watchdog out of range status for channel 34 provided corresponding WEN_CH34 bit is set." "0: CH[34] converted data is not out of range..,1: CH[34] converted data is out of range determined.." newline bitfld.long 0x0 1. "AWOR_CH33,Analog watchdog out of range status for channel 33 provided corresponding WEN_CH33 bit is set." "0: CH[33] converted data is not out of range..,1: CH[33] converted data is out of range determined.." bitfld.long 0x0 0. "AWOR_CH32,Analog watchdog out of range status for channel 32 provided corresponding WEN_CH32 bit is set." "0: CH[32] converted data is not out of range..,1: CH[32] converted data is out of range determined.." line.long 0x4 "ICAWORR2,Internal Channel Analog Watchdog Out of Range Register 2" bitfld.long 0x4 29. "AWOR_CH93,Analog watchdog out of range status for channel 93 provided corresponding WEN_CH93 bit is set." "0: CH[93] converted data is not out of range..,1: CH[93] converted data is out of range determined.." bitfld.long 0x4 28. "AWOR_CH92,Analog watchdog out of range status for channel 92 provided corresponding WEN_CH92 bit is set." "0: CH[92] converted data is not out of range..,1: CH[92] converted data is out of range determined.." group.long 0x400++0x13 line.long 0x0 "TCIPR,Test Channel Interrupt Pending Register" bitfld.long 0x0 31. "EOC_CH127,End of conversion interrupt pending bit for channel 127" "0: End of conversion for CH[127] has not occurred.,1: End of conversion for CH[127] has occurred" bitfld.long 0x0 30. "EOC_CH126,End of conversion interrupt pending bit for channel 126" "0: End of conversion for CH[126] has not occurred.,1: End of conversion for CH[126] has occurred" newline bitfld.long 0x0 29. "EOC_CH125,End of conversion interrupt pending bit for channel 125" "0: End of conversion for CH[125] has not occurred.,1: End of conversion for CH[125] has occurred" bitfld.long 0x0 28. "EOC_CH124,End of conversion interrupt pending bit for channel 124" "0: End of conversion for CH[124] has not occurred.,1: End of conversion for CH[124] has occurred" line.long 0x4 "TCIMR,Test Channel Interrupt Mask Register" bitfld.long 0x4 31. "IM_CH127,IM_CH127" "0: Interrupt for CH[127] is disabled.,1: Interrupt for CH[127] is enabled." bitfld.long 0x4 30. "IM_CH126,IM_CH126" "0: Interrupt for CH[126] is disabled.,1: Interrupt for CH[126] is enabled." newline bitfld.long 0x4 29. "IM_CH125,IM_CH125" "0: Interrupt for CH[125] is disabled.,1: Interrupt for CH[125] is enabled." bitfld.long 0x4 28. "IM_CH124,IM_CH124" "0: Interrupt for CH[124] is disabled.,1: Interrupt for CH[124] is enabled." line.long 0x8 "TCDSR,Test Channel DMA Select Register" bitfld.long 0x8 31. "DS_CH127,DS_CH127" "0: CH[127] is disabled to transfer data in DMA mode.,1: CH[127] is enabled to transfer data in DMA mode." bitfld.long 0x8 30. "DS_CH126,DS_CH126" "0: CH[126] is disabled to transfer data in DMA mode.,1: CH[126] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 29. "DS_CH125,DS_CH125" "0: CH[125] is disabled to transfer data in DMA mode.,1: CH[125] is enabled to transfer data in DMA mode." bitfld.long 0x8 28. "DS_CH124,DS_CH124" "0: CH[124] is disabled to transfer data in DMA mode.,1: CH[124] is enabled to transfer data in DMA mode." line.long 0xC "TCNCMR,Test Channel Normal Conversion Mask Register" bitfld.long 0xC 31. "NCE_CH127,NCE_CH127" "0: Normal conversion is disabled for CH[127].,1: Normal conversion is enabled for CH[127]." bitfld.long 0xC 30. "NCE_CH126,NCE_CH126" "0: Normal conversion is disabled for CH[126].,1: Normal conversion is enabled for CH[126]." newline bitfld.long 0xC 29. "NCE_CH125,NCE_CH125" "0: Normal conversion is disabled for CH[125].,1: Normal conversion is enabled for CH[125]." bitfld.long 0xC 28. "NCE_CH124,NCE_CH124" "0: Normal conversion is disabled for CH[124].,1: Normal conversion is enabled for CH[124]." line.long 0x10 "TCJCMR,Test Channel Injected Conversion Mask Register" bitfld.long 0x10 31. "JCE_CH127,JCE_CH127" "0: Injected conversion is disabled for CH[127].,1: Injected conversion is enabled for CH[127]." bitfld.long 0x10 30. "JCE_CH126,JCE_CH126" "0: Injected conversion is disabled for CH[126].,1: Injected conversion is enabled for CH[126]." newline bitfld.long 0x10 29. "JCE_CH125,JCE_CH125" "0: Injected conversion is disabled for CH[125].,1: Injected conversion is enabled for CH[125]." bitfld.long 0x10 28. "JCE_CH124,JCE_CH124" "0: Injected conversion is disabled for CH[124].,1: Injected conversion is enabled for CH[124]." group.long 0x420++0xB line.long 0x0 "TCWSELR3,Test Channel Watchdog Select Register 3" bitfld.long 0x0 28.--29. "WSEL_CH127,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH126,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH125,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH124,0000 THRHLR0 register is selected" "0,1,2,3" line.long 0x4 "TCWENR,Test Channel Watchdog Enable Register" bitfld.long 0x4 31. "WEN_CH127,WEN_CH127" "0: Watchdog feature is disabled for CH[127].,1: Watchdog feature is enabled for CH[127]." bitfld.long 0x4 30. "WEN_CH126,WEN_CH126" "0: Watchdog feature is disabled for CH[126].,1: Watchdog feature is enabled for CH[126]." newline bitfld.long 0x4 29. "WEN_CH125,WEN_CH125" "0: Watchdog feature is disabled for CH[125].,1: Watchdog feature is enabled for CH[125]." bitfld.long 0x4 28. "WEN_CH124,WEN_CH124" "0: Watchdog feature is disabled for CH[124].,1: Watchdog feature is enabled for CH[124]." line.long 0x8 "TCAWORR,Test Channel Analog Watchdog Out of Range Register" bitfld.long 0x8 31. "AWOR_CH127,Analog watchdog out of range status for channel 127 provided corresponding WEN_CH127 bit is set." "0: CH[127] converted data is not out of range..,1: CH[127] converted data is out of range.." bitfld.long 0x8 30. "AWOR_CH126,Analog watchdog out of range status for channel 126 provided corresponding WEN_CH126 bit is set." "0: CH[126] converted data is not out of range..,1: CH[126] converted data is out of range.." newline bitfld.long 0x8 29. "AWOR_CH125,Analog watchdog out of range status for channel 125 provided corresponding WEN_CH125 bit is set." "0: CH[125] converted data is not out of range..,1: CH[125] converted data is out of range.." bitfld.long 0x8 28. "AWOR_CH124,Analog watchdog out of range status for channel 124 provided corresponding WEN_CH124 bit is set." "0: CH[124] converted data is not out of range..,1: CH[124] converted data is out of range.." group.long 0x44C++0x3 line.long 0x0 "TCCAPR7,Test Channel Connection with Analog Pin Register 7" bitfld.long 0x0 31. "ESIC_TCH31,Enable short with internal channel for test channel 31" "0: Test channel 31 cannot be shorted with internal..,1: Test channel 31 can be shorted with internal.." hexmask.long.byte 0x0 24.--30. 1. "ICSEL_TCH31,Internal channel selection for short with test channel 31" newline bitfld.long 0x0 23. "ESIC_TCH30,Enable short with internal channel for test channel 30" "0: Test channel 30 cannot be shorted with internal..,1: Test channel 30 can be shorted with internal.." hexmask.long.byte 0x0 16.--22. 1. "ICSEL_TCH30,Internal channel selection for short with test channel 30" newline bitfld.long 0x0 15. "ESIC_TCH29,Enable short with internal channel for test channel 29" "0: Test channel 29 cannot be shorted with internal..,1: Test channel 29 can be shorted with internal.." hexmask.long.byte 0x0 8.--14. 1. "ICSEL_TCH29,Internal channel selection for short with test channel 29" newline bitfld.long 0x0 7. "ESIC_TCH28,Enable short with internal channel for test channel 28" "0: Test channel 28 cannot be shorted with internal..,1: Test channel 28 can be shorted with internal.." hexmask.long.byte 0x0 0.--6. 1. "ICSEL_TCH28,Internal channel selection for short with test channel 28" group.long 0x4C0++0xF line.long 0x0 "TCDR124,Test Channel Data Register 124" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x4 "TCDR125,Test Channel Data Register 125" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x8 "TCDR126,Test Channel Data Register 126" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xC "TCDR127,Test Channel Data Register 127" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." tree.end tree "SAR_ADC_12BIT_5" base ad:0x7089C000 group.long 0x0++0x3 line.long 0x0 "MCR,Main Configuration Register" bitfld.long 0x0 31. "OWREN,This bit enables or disables the functionality to overwrite unread converted data in ICDR TCDR ECDR registers." "0: Prevents overwrite of unread converted data new..,1: Enables converted data to be overwritten by a.." bitfld.long 0x0 30. "WLSIDE,Write left/right-aligned" "0: The conversion data in ICDR TCDR ECDR registers..,1: Conversion data is left-aligned (from 15 to (15.." newline bitfld.long 0x0 29. "MODE,One Shot/Scan" "0: One Shot Mode: Configures the normal conversion..,1: Scan Mode: Configures continuous chain.." bitfld.long 0x0 28. "XSTRTEN,This bit enables or disables the external start signal to initial a normal conversion. This can be used to synchronize multiple SARADCs concurrently." "0: External start signal is disabled,1: External start signal high level will start a.." newline bitfld.long 0x0 27. "NSTART,Setting this bit starts the chain or scan conversion. Resetting this bit during scan mode causes the current chain conversion to finish then stops the operation." "0: Cause the current chain conversion to finish and..,1: Starts the chain or scan conversion" bitfld.long 0x0 26. "NTRGEN,NTRGEN" "0: Normal trigger disabled to start a normal..,1: Normal trigger enabled to start a normal.." newline bitfld.long 0x0 24.--25. "NEDGESEL,NEDGESEL" "0: Falling edge of normal trigger is selected,1: Rising edge of normal trigger is selected,2: Both rising and falling edges of normal trigger..,3: Both rising and falling edges of normal trigger.." bitfld.long 0x0 23. "JSTART,Setting this bit will start the configured injected analog channels to be converted by software. Resetting this bit has no effect as the injected chain conversion cannot be interrupted." "0: Writting '0' has not effect,1: Starts the injected chain conversion" newline bitfld.long 0x0 22. "JTRGEN,JTRGEN" "0: Injection trigger disabled for channel injection..,1: Injection trigger enabled for channel injection" bitfld.long 0x0 20.--21. "JEDGESEL,JEDGESEL" "0: Falling edge of injection trigger is selected,1: Rising edge of injection trigger is selected,?,3: Both rising and falling edges of injection.." newline bitfld.long 0x0 19. "JTRGSEQ,JTRGSEQ" "0: Injection trigger sequence mode is disabled,1: Injection trigger sequence mode is enabled" bitfld.long 0x0 17. "CTUEN,Can be set or cleared anytime with some restriction mentioned in CTU trigger/control mode section." "0: The cross triggering unit is disabled and the..,1: The cross triggering unit is enabled and the.." newline bitfld.long 0x0 16. "CTU_MODE,This bit is present only if generic parameter CTSEN = 2 otherwise this bit is a reserved bit and always read as 0. This should be set only when ADC Digital is in powerdown mode." "0: CTU control mode is selected,1: CTU trigger mode is selected" bitfld.long 0x0 15. "WTRIGOUT,This control bit enables the Trigger on every threshold crossover event (crossing of Lower/Upper thresholds) of each WDG monitor to external trigger port (up to 16 ports for up to 16 WDGs)." "0: Trigger outputs disabled,1: Trigger ouputs enabled" newline bitfld.long 0x0 7. "ABORTCHAIN,When this bit is set the ongoing Chain Conversion is aborted. This bit is reset by hardware as soon as a new conversion is requested." "0: Conversion is not affected,1: Aborts the ongoing chain conversion" bitfld.long 0x0 6. "ABORT,When this bit is set the ongoing conversion is aborted and a new conversion is invoked. This bit is reset by hardware as soon as a new conversion is invoked." "0: Conversion is not affected,1: Aborts the ongoing conversion" newline bitfld.long 0x0 4. "FRZ,This bit enables to stop the SARADC conversions at the end of current channel conversion when SoC enters debug mode." "0: Conversions are not stopped,1: When SoC enters debug mode further conversions.." bitfld.long 0x0 2. "FCE,This bit enables the fast comparison mode for upcoming channel conversions." "0: Fast comparision mode disabled,1: Fast comparision mode enabled" newline bitfld.long 0x0 1. "EDCSELF,This bit selects the format for 3-bit output port ipp_decode_extch used as select line for external decode channel 8:1 muxes. The last three bits of external channel number are passed as is (if value 0) or converted to gray code (if value 1) and.." "0: Binary format,1: Gray code format" bitfld.long 0x0 0. "PWDN,When this bit is set the analog module is requested to enter Power Down mode." "0: SARADC is in normal mode,1: SARADC has been requested to power down" rgroup.long 0x4++0x3 line.long 0x0 "MSR,Main Status Register" bitfld.long 0x0 27. "NSTART,This status bit is used to signal that a normal conversion is ongoing." "0: Normal conversion is not taking place,1: Normal conversion is ongoing or the normal.." bitfld.long 0x0 23. "JSTART,This status bit is used to signal that an injected conversion is ongoing." "0: Injected conversion is not taking place,1: Injected conversion is ongoing" newline bitfld.long 0x0 18. "JABORTCHAIN,This status bit is used to signal that an Injected conversion chain has been aborted. This bit is reset when a new conversion starts." "0: Last injected conversion chain has not been..,1: Last injected conversion chain has been aborted" bitfld.long 0x0 16. "CTUSTART,This status bit is used to signal that a CTU conversion is ongoing. This bit is set when a CTU trigger pulse is received and the CTU conversion starts. When CTU trigger mode is enabled this bit is automatically reset when the conversion is.." "0: CTU triggered injected conversion is not taking..,1: CTU triggered injected conversion is ongoing" newline hexmask.long.byte 0x0 8.--15. 1. "CHADDR,Channel under measure address" bitfld.long 0x0 0.--2. "ADCSTATUS,The value of this parameter depends on ADC status. While requesting an external channel conversion SARADC digital interface needs to wait for a fixed time determined by DSD bitfield of DSDR before proceeding to actual sampling phase." "0: IDLE,1: Power-down,2: Wait state,?,4: Sample,?,6: Conversion,?" group.long 0x10++0x3 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CTUTRGERR,This Error Flag indicates that the next CTU trigger has been discarded as it overlapped during execution of current CTU conversion. This indicated that CTU sampling duration is less than programmed conversion time of ADC." "0: No CTU trigger overlap error condition since..,1: CTU trigger overlap error has occurred." bitfld.long 0x0 4. "EOCTU,This bit indicates the end of conversion for a CTU injected channel." "0: End of conversion of CTU triggered channel has..,1: End of conversion of CTU triggered channel has.." newline bitfld.long 0x0 3. "JEOC,This bit indicates the end of conversion for an injected channel." "0: End of conversion of injected channel has not..,1: End of conversion of injected channel has.." bitfld.long 0x0 2. "JECH,This bit indicates the end of conversion for an injected chain." "0: End of conversion of injected chain has not..,1: End of conversion of injected chain has occurred.." newline bitfld.long 0x0 1. "NEOC,This bit indicates the end of conversion for a normal channel." "0: End of conversion of normal channel has not..,1: End of conversion of normal channel has occurred.." bitfld.long 0x0 0. "NECH,This bit indicates the end of conversion for an normal chain." "0: End of conversion of normal chain has not..,1: End of conversion of normal chain has occurred.." group.long 0x18++0x3 line.long 0x0 "ICIPR1,Internal Channel Interrupt Pending Register 1" bitfld.long 0x0 15. "EOC_CH47,End of conversion interrupt pending bit for channel 47" "0: End of conversion for CH[47] has not occured,1: End of conversion for CH[47] has occured" bitfld.long 0x0 14. "EOC_CH46,End of conversion interrupt pending bit for channel 46" "0: End of conversion for CH[46] has not occured,1: End of conversion for CH[46] has occured" newline bitfld.long 0x0 13. "EOC_CH45,End of conversion interrupt pending bit for channel 45" "0: End of conversion for CH[45] has not occured,1: End of conversion for CH[45] has occured" bitfld.long 0x0 12. "EOC_CH44,End of conversion interrupt pending bit for channel 44" "0: End of conversion for CH[44] has not occured,1: End of conversion for CH[44] has occured" newline bitfld.long 0x0 11. "EOC_CH43,End of conversion interrupt pending bit for channel 43" "0: End of conversion for CH[43] has not occured,1: End of conversion for CH[43] has occured" bitfld.long 0x0 10. "EOC_CH42,End of conversion interrupt pending bit for channel 42" "0: End of conversion for CH[42] has not occured,1: End of conversion for CH[42] has occured" newline bitfld.long 0x0 9. "EOC_CH41,End of conversion interrupt pending bit for channel 41" "0: End of conversion for CH[41] has not occured,1: End of conversion for CH[41] has occured" bitfld.long 0x0 8. "EOC_CH40,End of conversion interrupt pending bit for channel 40" "0: End of conversion for CH[40] has not occured,1: End of conversion for CH[40] has occured" group.long 0x20++0x3 line.long 0x0 "IMR,Interrupt Mask Register" bitfld.long 0x0 5. "MSKCTUTRGERR,Mask bit for CTU Trigger" "0: CTUTRGERR interrupt is disabled,1: CTUTRGERR interrupt is enabled" bitfld.long 0x0 4. "MSKEOCTU,Mask bit for EOCTU" "0: EOCTU interrupt is disabled,1: EOCTU interrupt is enabled" newline bitfld.long 0x0 3. "MSKJEOC,Mask bit for JEOC" "0: JEOC interrupt is disabled,1: JEOC interrupt is enabled" bitfld.long 0x0 2. "MSKJECH,Mask bit for JECH" "0: JECH interrupt is disabled,1: JECH interrupt is enabled" newline bitfld.long 0x0 1. "MSKNEOC,Mask bit for NEOC" "0: NEOC interrupt is disabled,1: NEOC interrupt is enabled" bitfld.long 0x0 0. "MSKNECH,Mask bit for NECH" "0: NECH interrupt is disabled,1: NECH interrupt is enabled" group.long 0x28++0x3 line.long 0x0 "ICIMR1,Internal Channel Interrupt Mask Register 1" bitfld.long 0x0 15. "IM_CH47,Interrupt mask bit for channel 47" "0: Interupt for CH[47] is disabled,1: Interupt for CH[47] is enabled" bitfld.long 0x0 14. "IM_CH46,Interrupt mask bit for channel 46" "0: Interupt for CH[46] is disabled,1: Interupt for CH[46] is enabled" newline bitfld.long 0x0 13. "IM_CH45,Interrupt mask bit for channel 45" "0: Interupt for CH[45] is disabled,1: Interupt for CH[45] is enabled" bitfld.long 0x0 12. "IM_CH44,Interrupt mask bit for channel 44" "0: Interupt for CH[44] is disabled,1: Interupt for CH[44] is enabled" newline bitfld.long 0x0 11. "IM_CH43,Interrupt mask bit for channel 43" "0: Interupt for CH[43] is disabled,1: Interupt for CH[43] is enabled" bitfld.long 0x0 10. "IM_CH42,Interrupt mask bit for channel 42" "0: Interupt for CH[42] is disabled,1: Interupt for CH[42] is enabled" newline bitfld.long 0x0 9. "IM_CH41,Interrupt mask bit for channel 41" "0: Interupt for CH[41] is disabled,1: Interupt for CH[41] is enabled" bitfld.long 0x0 8. "IM_CH40,Interrupt mask bit for channel 40" "0: Interupt for CH[40] is disabled,1: Interupt for CH[40] is enabled" group.long 0x30++0xB line.long 0x0 "WTISR,Watchdog Threshold Interrupt Status Register" bitfld.long 0x0 7. "WDG3H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 3." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 6. "WDG3L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 3." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x0 5. "WDG2H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 2." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 4. "WDG2L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 2." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x0 3. "WDG1H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 1." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 2. "WDG1L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 1." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x0 1. "WDG0H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 0." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 0. "WDG0L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 0." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." line.long 0x4 "WTIMR,Watchdog Threshold Interrupt Mask Register" bitfld.long 0x4 7. "MSKWDG3H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG3H is disabled.,1: Inetrupt for WDG3H is enabled." bitfld.long 0x4 6. "MSKWDG3L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG3L is disabled.,1: Inetrupt for WDG3L is enabled." newline bitfld.long 0x4 5. "MSKWDG2H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG2H is disabled.,1: Inetrupt for WDG2H is enabled." bitfld.long 0x4 4. "MSKWDG2L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG2L is disabled.,1: Inetrupt for WDG2L is enabled." newline bitfld.long 0x4 3. "MSKWDG1H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG1H is disabled.,1: Inetrupt for WDG1H is enabled." bitfld.long 0x4 2. "MSKWDG1L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG1L is disabled.,1: Inetrupt for WDG1L is enabled." newline bitfld.long 0x4 1. "MSKWDG0H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG0H is disabled.,1: Inetrupt for WDG0H is enabled." bitfld.long 0x4 0. "MSKWDG0L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG0L is disabled.,1: Inetrupt for WDG0L is enabled." line.long 0x8 "WLTCR,Watchdog Level Trigger Configuration Register" bitfld.long 0x8 3. "LTMW3,LTMW3" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0x8 2. "LTMW2,LTMW2" "0: Level Trigger Mode,1: Hysteresis Mode" newline bitfld.long 0x8 1. "LTMW1,LTMW1" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0x8 0. "LTMW0,LTMW0" "0: Level Trigger Mode,1: Hysteresis Mode" group.long 0x40++0x3 line.long 0x0 "DMAE,DMA Enable Register" bitfld.long 0x0 1. "DCLR,DMA clear sequence enable" "0: DMA request cleared by Acknowledge from DMA..,1: DMA request cleared on read of data registers" bitfld.long 0x0 0. "DMAEN,DMA global enable" "0: DMA feature disabled,1: DMA feature enabled" group.long 0x48++0x3 line.long 0x0 "ICDSR1,Internal Channel DMA Select Register 1" bitfld.long 0x0 15. "DS_CH47,DS_CH47" "0: CH[47] is disabled to transfer data in DMA mode.,1: CH[47] is enabled to transfer data in DMA mode." bitfld.long 0x0 14. "DS_CH46,DS_CH46" "0: CH[46] is disabled to transfer data in DMA mode.,1: CH[46] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 13. "DS_CH45,DS_CH45" "0: CH[45] is disabled to transfer data in DMA mode.,1: CH[45] is enabled to transfer data in DMA mode." bitfld.long 0x0 12. "DS_CH44,DS_CH44" "0: CH[44] is disabled to transfer data in DMA mode.,1: CH[44] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 11. "DS_CH43,DS_CH43" "0: CH[43] is disabled to transfer data in DMA mode.,1: CH[43] is enabled to transfer data in DMA mode." bitfld.long 0x0 10. "DS_CH42,DS_CH42" "0: CH[42] is disabled to transfer data in DMA mode.,1: CH[42] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 9. "DS_CH41,DS_CH41" "0: CH[41] is disabled to transfer data in DMA mode.,1: CH[41] is enabled to transfer data in DMA mode." bitfld.long 0x0 8. "DS_CH40,DS_CH40" "0: CH[40] is disabled to transfer data in DMA mode.,1: CH[40] is enabled to transfer data in DMA mode." group.long 0x60++0xF line.long 0x0 "WTHRHLR0,Watchdog Threshold Register 0" hexmask.long.word 0x0 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x0 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x4 "WTHRHLR1,Watchdog Threshold Register 1" hexmask.long.word 0x4 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x4 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x8 "WTHRHLR2,Watchdog Threshold Register 2" hexmask.long.word 0x8 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x8 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0xC "WTHRHLR3,Watchdog Threshold Register 3" hexmask.long.word 0xC 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0xC 0.--11. 1. "THRL,Low threshold value for channel x" group.long 0x94++0xF line.long 0x0 "CTR0,Conversion Timing Register 0" bitfld.long 0x0 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x0 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x4 "CTR1,Conversion Timing Register 1" bitfld.long 0x4 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x4 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x4 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x8 "CTR2,Conversion Timing Register 2" bitfld.long 0x8 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x8 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x8 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0xC "CTR3,Conversion Timing Register 3" bitfld.long 0xC 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0xC 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0xC 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." group.long 0xA8++0x3 line.long 0x0 "ICNCMR1,Internal Channel Normal Conversion Mask Register 1" bitfld.long 0x0 15. "NCE_CH47,NCE_CH47" "0: Normal conversion is disabled for CH[47].,1: Normal conversion is enabled for CH[47]." bitfld.long 0x0 14. "NCE_CH46,NCE_CH46" "0: Normal conversion is disabled for CH[46].,1: Normal conversion is enabled for CH[46]." newline bitfld.long 0x0 13. "NCE_CH45,NCE_CH45" "0: Normal conversion is disabled for CH[45].,1: Normal conversion is enabled for CH[45]." bitfld.long 0x0 12. "NCE_CH44,NCE_CH44" "0: Normal conversion is disabled for CH[44].,1: Normal conversion is enabled for CH[44]." newline bitfld.long 0x0 11. "NCE_CH43,NCE_CH43" "0: Normal conversion is disabled for CH[43].,1: Normal conversion is enabled for CH[43]." bitfld.long 0x0 10. "NCE_CH42,NCE_CH42" "0: Normal conversion is disabled for CH[42].,1: Normal conversion is enabled for CH[42]." newline bitfld.long 0x0 9. "NCE_CH41,NCE_CH41" "0: Normal conversion is disabled for CH[41].,1: Normal conversion is enabled for CH[41]." bitfld.long 0x0 8. "NCE_CH40,NCE_CH40" "0: Normal conversion is disabled for CH[40].,1: Normal conversion is enabled for CH[40]." group.long 0xB8++0x3 line.long 0x0 "ICJCMR1,Internal Channel Injected Conversion Mask Register 1" bitfld.long 0x0 15. "JCE_CH47,JCE_CH47" "0: Injected conversion is disabled for CH[47].,1: Injected conversion is enabled for CH[47]." bitfld.long 0x0 14. "JCE_CH46,JCE_CH46" "0: Injected conversion is disabled for CH[46].,1: Injected conversion is enabled for CH[46]." newline bitfld.long 0x0 13. "JCE_CH45,JCE_CH45" "0: Injected conversion is disabled for CH[45].,1: Injected conversion is enabled for CH[45]." bitfld.long 0x0 12. "JCE_CH44,JCE_CH44" "0: Injected conversion is disabled for CH[44].,1: Injected conversion is enabled for CH[44]." newline bitfld.long 0x0 11. "JCE_CH43,JCE_CH43" "0: Injected conversion is disabled for CH[43].,1: Injected conversion is enabled for CH[43]." bitfld.long 0x0 10. "JCE_CH42,JCE_CH42" "0: Injected conversion is disabled for CH[42].,1: Injected conversion is enabled for CH[42]." newline bitfld.long 0x0 9. "JCE_CH41,JCE_CH41" "0: Injected conversion is disabled for CH[41].,1: Injected conversion is enabled for CH[41]." bitfld.long 0x0 8. "JCE_CH40,JCE_CH40" "0: Injected conversion is disabled for CH[40].,1: Injected conversion is enabled for CH[40]." group.long 0xC8++0x3 line.long 0x0 "PDEDR,Power Down Exit Delay Register" hexmask.long.byte 0x0 0.--7. 1. "PDED,Defines the delay between the power-down bit reset and the starting of conversion." group.long 0x1A0++0x1F line.long 0x0 "ICDR40,Internal Channel Data Register 40" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4 "ICDR41,Internal Channel Data Register 41" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x8 "ICDR42,Internal Channel Data Register 42" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x8 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xC "ICDR43,Internal Channel Data Register 43" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xC 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x10 "ICDR44,Internal Channel Data Register 44" bitfld.long 0x10 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x10 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x10 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x10 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x10 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x10 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x10 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x14 "ICDR45,Internal Channel Data Register 45" bitfld.long 0x14 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x14 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x14 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x14 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x14 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x14 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x14 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x18 "ICDR46,Internal Channel Data Register 46" bitfld.long 0x18 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x18 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x18 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x18 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x18 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x18 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x18 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x1C "ICDR47,Internal Channel Data Register 47" bitfld.long 0x1C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x1C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x1C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x1C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x1C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x1C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x1C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" group.long 0x2C4++0x3 line.long 0x0 "ICWSELR5,Internal Channel Watchdog Select Register 5" bitfld.long 0x0 28.--29. "WSEL_CH47,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH46,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH45,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH44,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 12.--13. "WSEL_CH43,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 8.--9. "WSEL_CH42,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 4.--5. "WSEL_CH41,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 0.--1. "WSEL_CH40,0000 THRHLR0 register is selected" "0,1,2,3" group.long 0x2E4++0x3 line.long 0x0 "ICWENR1,Internal Channel Watchdog Enable Register 1" bitfld.long 0x0 15. "WEN_CH47,WEN_CH47" "0: Watchdog feature is disabled for CH[47],1: Watchdog feature is enabled fir CH[47]" bitfld.long 0x0 14. "WEN_CH46,WEN_CH46" "0: Watchdog feature is disabled for CH[46],1: Watchdog feature is enabled fir CH[46]" newline bitfld.long 0x0 13. "WEN_CH45,WEN_CH45" "0: Watchdog feature is disabled for CH[45],1: Watchdog feature is enabled fir CH[45]" bitfld.long 0x0 12. "WEN_CH44,WEN_CH44" "0: Watchdog feature is disabled for CH[44],1: Watchdog feature is enabled fir CH[44]" newline bitfld.long 0x0 11. "WEN_CH43,WEN_CH43" "0: Watchdog feature is disabled for CH[43],1: Watchdog feature is enabled fir CH[43]" bitfld.long 0x0 10. "WEN_CH42,WEN_CH42" "0: Watchdog feature is disabled for CH[42],1: Watchdog feature is enabled fir CH[42]" newline bitfld.long 0x0 9. "WEN_CH41,WEN_CH41" "0: Watchdog feature is disabled for CH[41],1: Watchdog feature is enabled fir CH[41]" bitfld.long 0x0 8. "WEN_CH40,WEN_CH40" "0: Watchdog feature is disabled for CH[40],1: Watchdog feature is enabled fir CH[40]" group.long 0x2F4++0x3 line.long 0x0 "ICAWORR1,Internal Channel Analog Watchdog Out of Range Register 1" bitfld.long 0x0 15. "AWOR_CH47,Analog watchdog out of range status for channel 47 provided corresponding WEN_CH47 bit is set." "0: CH[47] converted data is not out of range..,1: CH[47] converted data is out of range determined.." bitfld.long 0x0 14. "AWOR_CH46,Analog watchdog out of range status for channel 46 provided corresponding WEN_CH46 bit is set." "0: CH[46] converted data is not out of range..,1: CH[46] converted data is out of range determined.." newline bitfld.long 0x0 13. "AWOR_CH45,Analog watchdog out of range status for channel 45 provided corresponding WEN_CH45 bit is set." "0: CH[45] converted data is not out of range..,1: CH[45] converted data is out of range determined.." bitfld.long 0x0 12. "AWOR_CH44,Analog watchdog out of range status for channel 44 provided corresponding WEN_CH44 bit is set." "0: CH[44] converted data is not out of range..,1: CH[44] converted data is out of range determined.." newline bitfld.long 0x0 11. "AWOR_CH43,Analog watchdog out of range status for channel 43 provided corresponding WEN_CH43 bit is set." "0: CH[43] converted data is not out of range..,1: CH[43] converted data is out of range determined.." bitfld.long 0x0 10. "AWOR_CH42,Analog watchdog out of range status for channel 42 provided corresponding WEN_CH42 bit is set." "0: CH[42] converted data is not out of range..,1: CH[42] converted data is out of range determined.." newline bitfld.long 0x0 9. "AWOR_CH41,Analog watchdog out of range status for channel 41 provided corresponding WEN_CH41 bit is set." "0: CH[41] converted data is not out of range..,1: CH[41] converted data is out of range determined.." bitfld.long 0x0 8. "AWOR_CH40,Analog watchdog out of range status for channel 40 provided corresponding WEN_CH40 bit is set." "0: CH[40] converted data is not out of range..,1: CH[40] converted data is out of range determined.." group.long 0x400++0x13 line.long 0x0 "TCIPR,Test Channel Interrupt Pending Register" bitfld.long 0x0 31. "EOC_CH127,End of conversion interrupt pending bit for channel 127" "0: End of conversion for CH[127] has not occurred.,1: End of conversion for CH[127] has occurred" bitfld.long 0x0 30. "EOC_CH126,End of conversion interrupt pending bit for channel 126" "0: End of conversion for CH[126] has not occurred.,1: End of conversion for CH[126] has occurred" newline bitfld.long 0x0 29. "EOC_CH125,End of conversion interrupt pending bit for channel 125" "0: End of conversion for CH[125] has not occurred.,1: End of conversion for CH[125] has occurred" bitfld.long 0x0 28. "EOC_CH124,End of conversion interrupt pending bit for channel 124" "0: End of conversion for CH[124] has not occurred.,1: End of conversion for CH[124] has occurred" line.long 0x4 "TCIMR,Test Channel Interrupt Mask Register" bitfld.long 0x4 31. "IM_CH127,IM_CH127" "0: Interrupt for CH[127] is disabled.,1: Interrupt for CH[127] is enabled." bitfld.long 0x4 30. "IM_CH126,IM_CH126" "0: Interrupt for CH[126] is disabled.,1: Interrupt for CH[126] is enabled." newline bitfld.long 0x4 29. "IM_CH125,IM_CH125" "0: Interrupt for CH[125] is disabled.,1: Interrupt for CH[125] is enabled." bitfld.long 0x4 28. "IM_CH124,IM_CH124" "0: Interrupt for CH[124] is disabled.,1: Interrupt for CH[124] is enabled." line.long 0x8 "TCDSR,Test Channel DMA Select Register" bitfld.long 0x8 31. "DS_CH127,DS_CH127" "0: CH[127] is disabled to transfer data in DMA mode.,1: CH[127] is enabled to transfer data in DMA mode." bitfld.long 0x8 30. "DS_CH126,DS_CH126" "0: CH[126] is disabled to transfer data in DMA mode.,1: CH[126] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 29. "DS_CH125,DS_CH125" "0: CH[125] is disabled to transfer data in DMA mode.,1: CH[125] is enabled to transfer data in DMA mode." bitfld.long 0x8 28. "DS_CH124,DS_CH124" "0: CH[124] is disabled to transfer data in DMA mode.,1: CH[124] is enabled to transfer data in DMA mode." line.long 0xC "TCNCMR,Test Channel Normal Conversion Mask Register" bitfld.long 0xC 31. "NCE_CH127,NCE_CH127" "0: Normal conversion is disabled for CH[127].,1: Normal conversion is enabled for CH[127]." bitfld.long 0xC 30. "NCE_CH126,NCE_CH126" "0: Normal conversion is disabled for CH[126].,1: Normal conversion is enabled for CH[126]." newline bitfld.long 0xC 29. "NCE_CH125,NCE_CH125" "0: Normal conversion is disabled for CH[125].,1: Normal conversion is enabled for CH[125]." bitfld.long 0xC 28. "NCE_CH124,NCE_CH124" "0: Normal conversion is disabled for CH[124].,1: Normal conversion is enabled for CH[124]." line.long 0x10 "TCJCMR,Test Channel Injected Conversion Mask Register" bitfld.long 0x10 31. "JCE_CH127,JCE_CH127" "0: Injected conversion is disabled for CH[127].,1: Injected conversion is enabled for CH[127]." bitfld.long 0x10 30. "JCE_CH126,JCE_CH126" "0: Injected conversion is disabled for CH[126].,1: Injected conversion is enabled for CH[126]." newline bitfld.long 0x10 29. "JCE_CH125,JCE_CH125" "0: Injected conversion is disabled for CH[125].,1: Injected conversion is enabled for CH[125]." bitfld.long 0x10 28. "JCE_CH124,JCE_CH124" "0: Injected conversion is disabled for CH[124].,1: Injected conversion is enabled for CH[124]." group.long 0x420++0xB line.long 0x0 "TCWSELR3,Test Channel Watchdog Select Register 3" bitfld.long 0x0 28.--29. "WSEL_CH127,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH126,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH125,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH124,0000 THRHLR0 register is selected" "0,1,2,3" line.long 0x4 "TCWENR,Test Channel Watchdog Enable Register" bitfld.long 0x4 31. "WEN_CH127,WEN_CH127" "0: Watchdog feature is disabled for CH[127].,1: Watchdog feature is enabled for CH[127]." bitfld.long 0x4 30. "WEN_CH126,WEN_CH126" "0: Watchdog feature is disabled for CH[126].,1: Watchdog feature is enabled for CH[126]." newline bitfld.long 0x4 29. "WEN_CH125,WEN_CH125" "0: Watchdog feature is disabled for CH[125].,1: Watchdog feature is enabled for CH[125]." bitfld.long 0x4 28. "WEN_CH124,WEN_CH124" "0: Watchdog feature is disabled for CH[124].,1: Watchdog feature is enabled for CH[124]." line.long 0x8 "TCAWORR,Test Channel Analog Watchdog Out of Range Register" bitfld.long 0x8 31. "AWOR_CH127,Analog watchdog out of range status for channel 127 provided corresponding WEN_CH127 bit is set." "0: CH[127] converted data is not out of range..,1: CH[127] converted data is out of range.." bitfld.long 0x8 30. "AWOR_CH126,Analog watchdog out of range status for channel 126 provided corresponding WEN_CH126 bit is set." "0: CH[126] converted data is not out of range..,1: CH[126] converted data is out of range.." newline bitfld.long 0x8 29. "AWOR_CH125,Analog watchdog out of range status for channel 125 provided corresponding WEN_CH125 bit is set." "0: CH[125] converted data is not out of range..,1: CH[125] converted data is out of range.." bitfld.long 0x8 28. "AWOR_CH124,Analog watchdog out of range status for channel 124 provided corresponding WEN_CH124 bit is set." "0: CH[124] converted data is not out of range..,1: CH[124] converted data is out of range.." group.long 0x44C++0x3 line.long 0x0 "TCCAPR7,Test Channel Connection with Analog Pin Register 7" bitfld.long 0x0 31. "ESIC_TCH31,Enable short with internal channel for test channel 31" "0: Test channel 31 cannot be shorted with internal..,1: Test channel 31 can be shorted with internal.." hexmask.long.byte 0x0 24.--30. 1. "ICSEL_TCH31,Internal channel selection for short with test channel 31" newline bitfld.long 0x0 23. "ESIC_TCH30,Enable short with internal channel for test channel 30" "0: Test channel 30 cannot be shorted with internal..,1: Test channel 30 can be shorted with internal.." hexmask.long.byte 0x0 16.--22. 1. "ICSEL_TCH30,Internal channel selection for short with test channel 30" newline bitfld.long 0x0 15. "ESIC_TCH29,Enable short with internal channel for test channel 29" "0: Test channel 29 cannot be shorted with internal..,1: Test channel 29 can be shorted with internal.." hexmask.long.byte 0x0 8.--14. 1. "ICSEL_TCH29,Internal channel selection for short with test channel 29" newline bitfld.long 0x0 7. "ESIC_TCH28,Enable short with internal channel for test channel 28" "0: Test channel 28 cannot be shorted with internal..,1: Test channel 28 can be shorted with internal.." hexmask.long.byte 0x0 0.--6. 1. "ICSEL_TCH28,Internal channel selection for short with test channel 28" group.long 0x4C0++0xF line.long 0x0 "TCDR124,Test Channel Data Register 124" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x4 "TCDR125,Test Channel Data Register 125" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x8 "TCDR126,Test Channel Data Register 126" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xC "TCDR127,Test Channel Data Register 127" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." tree.end tree "SAR_ADC_12BIT_6" base ad:0x702A4000 group.long 0x0++0x3 line.long 0x0 "MCR,Main Configuration Register" bitfld.long 0x0 31. "OWREN,This bit enables or disables the functionality to overwrite unread converted data in ICDR TCDR ECDR registers." "0: Prevents overwrite of unread converted data new..,1: Enables converted data to be overwritten by a.." bitfld.long 0x0 30. "WLSIDE,Write left/right-aligned" "0: The conversion data in ICDR TCDR ECDR registers..,1: Conversion data is left-aligned (from 15 to (15.." newline bitfld.long 0x0 29. "MODE,One Shot/Scan" "0: One Shot Mode: Configures the normal conversion..,1: Scan Mode: Configures continuous chain.." bitfld.long 0x0 28. "XSTRTEN,This bit enables or disables the external start signal to initial a normal conversion. This can be used to synchronize multiple SARADCs concurrently." "0: External start signal is disabled,1: External start signal high level will start a.." newline bitfld.long 0x0 27. "NSTART,Setting this bit starts the chain or scan conversion. Resetting this bit during scan mode causes the current chain conversion to finish then stops the operation." "0: Cause the current chain conversion to finish and..,1: Starts the chain or scan conversion" bitfld.long 0x0 26. "NTRGEN,NTRGEN" "0: Normal trigger disabled to start a normal..,1: Normal trigger enabled to start a normal.." newline bitfld.long 0x0 24.--25. "NEDGESEL,NEDGESEL" "0: Falling edge of normal trigger is selected,1: Rising edge of normal trigger is selected,2: Both rising and falling edges of normal trigger..,3: Both rising and falling edges of normal trigger.." bitfld.long 0x0 23. "JSTART,Setting this bit will start the configured injected analog channels to be converted by software. Resetting this bit has no effect as the injected chain conversion cannot be interrupted." "0: Writting '0' has not effect,1: Starts the injected chain conversion" newline bitfld.long 0x0 22. "JTRGEN,JTRGEN" "0: Injection trigger disabled for channel injection..,1: Injection trigger enabled for channel injection" bitfld.long 0x0 20.--21. "JEDGESEL,JEDGESEL" "0: Falling edge of injection trigger is selected,1: Rising edge of injection trigger is selected,?,3: Both rising and falling edges of injection.." newline bitfld.long 0x0 19. "JTRGSEQ,JTRGSEQ" "0: Injection trigger sequence mode is disabled,1: Injection trigger sequence mode is enabled" bitfld.long 0x0 17. "CTUEN,Can be set or cleared anytime with some restriction mentioned in CTU trigger/control mode section." "0: The cross triggering unit is disabled and the..,1: The cross triggering unit is enabled and the.." newline bitfld.long 0x0 16. "CTU_MODE,This bit is present only if generic parameter CTSEN = 2 otherwise this bit is a reserved bit and always read as 0. This should be set only when ADC Digital is in powerdown mode." "0: CTU control mode is selected,1: CTU trigger mode is selected" bitfld.long 0x0 15. "WTRIGOUT,This control bit enables the Trigger on every threshold crossover event (crossing of Lower/Upper thresholds) of each WDG monitor to external trigger port (up to 16 ports for up to 16 WDGs)." "0: Trigger outputs disabled,1: Trigger ouputs enabled" newline bitfld.long 0x0 7. "ABORTCHAIN,When this bit is set the ongoing Chain Conversion is aborted. This bit is reset by hardware as soon as a new conversion is requested." "0: Conversion is not affected,1: Aborts the ongoing chain conversion" bitfld.long 0x0 6. "ABORT,When this bit is set the ongoing conversion is aborted and a new conversion is invoked. This bit is reset by hardware as soon as a new conversion is invoked." "0: Conversion is not affected,1: Aborts the ongoing conversion" newline bitfld.long 0x0 4. "FRZ,This bit enables to stop the SARADC conversions at the end of current channel conversion when SoC enters debug mode." "0: Conversions are not stopped,1: When SoC enters debug mode further conversions.." bitfld.long 0x0 2. "FCE,This bit enables the fast comparison mode for upcoming channel conversions." "0: Fast comparision mode disabled,1: Fast comparision mode enabled" newline bitfld.long 0x0 1. "EDCSELF,This bit selects the format for 3-bit output port ipp_decode_extch used as select line for external decode channel 8:1 muxes. The last three bits of external channel number are passed as is (if value 0) or converted to gray code (if value 1) and.." "0: Binary format,1: Gray code format" bitfld.long 0x0 0. "PWDN,When this bit is set the analog module is requested to enter Power Down mode." "0: SARADC is in normal mode,1: SARADC has been requested to power down" rgroup.long 0x4++0x3 line.long 0x0 "MSR,Main Status Register" bitfld.long 0x0 27. "NSTART,This status bit is used to signal that a normal conversion is ongoing." "0: Normal conversion is not taking place,1: Normal conversion is ongoing or the normal.." bitfld.long 0x0 23. "JSTART,This status bit is used to signal that an injected conversion is ongoing." "0: Injected conversion is not taking place,1: Injected conversion is ongoing" newline bitfld.long 0x0 18. "JABORTCHAIN,This status bit is used to signal that an Injected conversion chain has been aborted. This bit is reset when a new conversion starts." "0: Last injected conversion chain has not been..,1: Last injected conversion chain has been aborted" bitfld.long 0x0 16. "CTUSTART,This status bit is used to signal that a CTU conversion is ongoing. This bit is set when a CTU trigger pulse is received and the CTU conversion starts. When CTU trigger mode is enabled this bit is automatically reset when the conversion is.." "0: CTU triggered injected conversion is not taking..,1: CTU triggered injected conversion is ongoing" newline hexmask.long.byte 0x0 8.--15. 1. "CHADDR,Channel under measure address" bitfld.long 0x0 0.--2. "ADCSTATUS,The value of this parameter depends on ADC status. While requesting an external channel conversion SARADC digital interface needs to wait for a fixed time determined by DSD bitfield of DSDR before proceeding to actual sampling phase." "0: IDLE,1: Power-down,2: Wait state,?,4: Sample,?,6: Conversion,?" group.long 0x10++0x3 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CTUTRGERR,This Error Flag indicates that the next CTU trigger has been discarded as it overlapped during execution of current CTU conversion. This indicated that CTU sampling duration is less than programmed conversion time of ADC." "0: No CTU trigger overlap error condition since..,1: CTU trigger overlap error has occurred." bitfld.long 0x0 4. "EOCTU,This bit indicates the end of conversion for a CTU injected channel." "0: End of conversion of CTU triggered channel has..,1: End of conversion of CTU triggered channel has.." newline bitfld.long 0x0 3. "JEOC,This bit indicates the end of conversion for an injected channel." "0: End of conversion of injected channel has not..,1: End of conversion of injected channel has.." bitfld.long 0x0 2. "JECH,This bit indicates the end of conversion for an injected chain." "0: End of conversion of injected chain has not..,1: End of conversion of injected chain has occurred.." newline bitfld.long 0x0 1. "NEOC,This bit indicates the end of conversion for a normal channel." "0: End of conversion of normal channel has not..,1: End of conversion of normal channel has occurred.." bitfld.long 0x0 0. "NECH,This bit indicates the end of conversion for an normal chain." "0: End of conversion of normal chain has not..,1: End of conversion of normal chain has occurred.." group.long 0x18++0x3 line.long 0x0 "ICIPR1,Internal Channel Interrupt Pending Register 1" bitfld.long 0x0 23. "EOC_CH55,End of conversion interrupt pending bit for channel 55" "0: End of conversion for CH[55] has not occured,1: End of conversion for CH[55] has occured" bitfld.long 0x0 22. "EOC_CH54,End of conversion interrupt pending bit for channel 54" "0: End of conversion for CH[54] has not occured,1: End of conversion for CH[54] has occured" newline bitfld.long 0x0 21. "EOC_CH53,End of conversion interrupt pending bit for channel 53" "0: End of conversion for CH[53] has not occured,1: End of conversion for CH[53] has occured" bitfld.long 0x0 20. "EOC_CH52,End of conversion interrupt pending bit for channel 52" "0: End of conversion for CH[52] has not occured,1: End of conversion for CH[52] has occured" newline bitfld.long 0x0 19. "EOC_CH51,End of conversion interrupt pending bit for channel 51" "0: End of conversion for CH[51] has not occured,1: End of conversion for CH[51] has occured" bitfld.long 0x0 18. "EOC_CH50,End of conversion interrupt pending bit for channel 50" "0: End of conversion for CH[50] has not occured,1: End of conversion for CH[50] has occured" newline bitfld.long 0x0 17. "EOC_CH49,End of conversion interrupt pending bit for channel 49" "0: End of conversion for CH[49] has not occured,1: End of conversion for CH[49] has occured" bitfld.long 0x0 16. "EOC_CH48,End of conversion interrupt pending bit for channel 48" "0: End of conversion for CH[48] has not occured,1: End of conversion for CH[48] has occured" group.long 0x20++0x3 line.long 0x0 "IMR,Interrupt Mask Register" bitfld.long 0x0 5. "MSKCTUTRGERR,Mask bit for CTU Trigger" "0: CTUTRGERR interrupt is disabled,1: CTUTRGERR interrupt is enabled" bitfld.long 0x0 4. "MSKEOCTU,Mask bit for EOCTU" "0: EOCTU interrupt is disabled,1: EOCTU interrupt is enabled" newline bitfld.long 0x0 3. "MSKJEOC,Mask bit for JEOC" "0: JEOC interrupt is disabled,1: JEOC interrupt is enabled" bitfld.long 0x0 2. "MSKJECH,Mask bit for JECH" "0: JECH interrupt is disabled,1: JECH interrupt is enabled" newline bitfld.long 0x0 1. "MSKNEOC,Mask bit for NEOC" "0: NEOC interrupt is disabled,1: NEOC interrupt is enabled" bitfld.long 0x0 0. "MSKNECH,Mask bit for NECH" "0: NECH interrupt is disabled,1: NECH interrupt is enabled" group.long 0x28++0x3 line.long 0x0 "ICIMR1,Internal Channel Interrupt Mask Register 1" bitfld.long 0x0 23. "IM_CH55,Interrupt mask bit for channel 55" "0: Interupt for CH[55] is disabled,1: Interupt for CH[55] is enabled" bitfld.long 0x0 22. "IM_CH54,Interrupt mask bit for channel 54" "0: Interupt for CH[54] is disabled,1: Interupt for CH[54] is enabled" newline bitfld.long 0x0 21. "IM_CH53,Interrupt mask bit for channel 53" "0: Interupt for CH[53] is disabled,1: Interupt for CH[53] is enabled" bitfld.long 0x0 20. "IM_CH52,Interrupt mask bit for channel 52" "0: Interupt for CH[52] is disabled,1: Interupt for CH[52] is enabled" newline bitfld.long 0x0 19. "IM_CH51,Interrupt mask bit for channel 51" "0: Interupt for CH[51] is disabled,1: Interupt for CH[51] is enabled" bitfld.long 0x0 18. "IM_CH50,Interrupt mask bit for channel 50" "0: Interupt for CH[50] is disabled,1: Interupt for CH[50] is enabled" newline bitfld.long 0x0 17. "IM_CH49,Interrupt mask bit for channel 49" "0: Interupt for CH[49] is disabled,1: Interupt for CH[49] is enabled" bitfld.long 0x0 16. "IM_CH48,Interrupt mask bit for channel 48" "0: Interupt for CH[48] is disabled,1: Interupt for CH[48] is enabled" group.long 0x30++0xB line.long 0x0 "WTISR,Watchdog Threshold Interrupt Status Register" bitfld.long 0x0 7. "WDG3H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 3." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 6. "WDG3L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 3." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x0 5. "WDG2H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 2." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 4. "WDG2L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 2." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x0 3. "WDG1H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 1." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 2. "WDG1L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 1." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x0 1. "WDG0H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 0." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 0. "WDG0L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 0." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." line.long 0x4 "WTIMR,Watchdog Threshold Interrupt Mask Register" bitfld.long 0x4 7. "MSKWDG3H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG3H is disabled.,1: Inetrupt for WDG3H is enabled." bitfld.long 0x4 6. "MSKWDG3L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG3L is disabled.,1: Inetrupt for WDG3L is enabled." newline bitfld.long 0x4 5. "MSKWDG2H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG2H is disabled.,1: Inetrupt for WDG2H is enabled." bitfld.long 0x4 4. "MSKWDG2L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG2L is disabled.,1: Inetrupt for WDG2L is enabled." newline bitfld.long 0x4 3. "MSKWDG1H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG1H is disabled.,1: Inetrupt for WDG1H is enabled." bitfld.long 0x4 2. "MSKWDG1L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG1L is disabled.,1: Inetrupt for WDG1L is enabled." newline bitfld.long 0x4 1. "MSKWDG0H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG0H is disabled.,1: Inetrupt for WDG0H is enabled." bitfld.long 0x4 0. "MSKWDG0L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG0L is disabled.,1: Inetrupt for WDG0L is enabled." line.long 0x8 "WLTCR,Watchdog Level Trigger Configuration Register" bitfld.long 0x8 3. "LTMW3,LTMW3" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0x8 2. "LTMW2,LTMW2" "0: Level Trigger Mode,1: Hysteresis Mode" newline bitfld.long 0x8 1. "LTMW1,LTMW1" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0x8 0. "LTMW0,LTMW0" "0: Level Trigger Mode,1: Hysteresis Mode" group.long 0x40++0x3 line.long 0x0 "DMAE,DMA Enable Register" bitfld.long 0x0 1. "DCLR,DMA clear sequence enable" "0: DMA request cleared by Acknowledge from DMA..,1: DMA request cleared on read of data registers" bitfld.long 0x0 0. "DMAEN,DMA global enable" "0: DMA feature disabled,1: DMA feature enabled" group.long 0x48++0x3 line.long 0x0 "ICDSR1,Internal Channel DMA Select Register 1" bitfld.long 0x0 23. "DS_CH55,DS_CH55" "0: CH[55] is disabled to transfer data in DMA mode.,1: CH[55] is enabled to transfer data in DMA mode." bitfld.long 0x0 22. "DS_CH54,DS_CH54" "0: CH[54] is disabled to transfer data in DMA mode.,1: CH[54] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 21. "DS_CH53,DS_CH53" "0: CH[53] is disabled to transfer data in DMA mode.,1: CH[53] is enabled to transfer data in DMA mode." bitfld.long 0x0 20. "DS_CH52,DS_CH52" "0: CH[52] is disabled to transfer data in DMA mode.,1: CH[52] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 19. "DS_CH51,DS_CH51" "0: CH[51] is disabled to transfer data in DMA mode.,1: CH[51] is enabled to transfer data in DMA mode." bitfld.long 0x0 18. "DS_CH50,DS_CH50" "0: CH[50] is disabled to transfer data in DMA mode.,1: CH[50] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 17. "DS_CH49,DS_CH49" "0: CH[49] is disabled to transfer data in DMA mode.,1: CH[49] is enabled to transfer data in DMA mode." bitfld.long 0x0 16. "DS_CH48,DS_CH48" "0: CH[48] is disabled to transfer data in DMA mode.,1: CH[48] is enabled to transfer data in DMA mode." group.long 0x60++0xF line.long 0x0 "WTHRHLR0,Watchdog Threshold Register 0" hexmask.long.word 0x0 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x0 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x4 "WTHRHLR1,Watchdog Threshold Register 1" hexmask.long.word 0x4 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x4 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x8 "WTHRHLR2,Watchdog Threshold Register 2" hexmask.long.word 0x8 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x8 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0xC "WTHRHLR3,Watchdog Threshold Register 3" hexmask.long.word 0xC 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0xC 0.--11. 1. "THRL,Low threshold value for channel x" group.long 0x94++0xF line.long 0x0 "CTR0,Conversion Timing Register 0" bitfld.long 0x0 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x0 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x4 "CTR1,Conversion Timing Register 1" bitfld.long 0x4 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x4 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x4 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x8 "CTR2,Conversion Timing Register 2" bitfld.long 0x8 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x8 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x8 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0xC "CTR3,Conversion Timing Register 3" bitfld.long 0xC 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0xC 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0xC 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." group.long 0xA8++0x3 line.long 0x0 "ICNCMR1,Internal Channel Normal Conversion Mask Register 1" bitfld.long 0x0 23. "NCE_CH55,NCE_CH55" "0: Normal conversion is disabled for CH[55].,1: Normal conversion is enabled for CH[55]." bitfld.long 0x0 22. "NCE_CH54,NCE_CH54" "0: Normal conversion is disabled for CH[54].,1: Normal conversion is enabled for CH[54]." newline bitfld.long 0x0 21. "NCE_CH53,NCE_CH53" "0: Normal conversion is disabled for CH[53].,1: Normal conversion is enabled for CH[53]." bitfld.long 0x0 20. "NCE_CH52,NCE_CH52" "0: Normal conversion is disabled for CH[52].,1: Normal conversion is enabled for CH[52]." newline bitfld.long 0x0 19. "NCE_CH51,NCE_CH51" "0: Normal conversion is disabled for CH[51].,1: Normal conversion is enabled for CH[51]." bitfld.long 0x0 18. "NCE_CH50,NCE_CH50" "0: Normal conversion is disabled for CH[50].,1: Normal conversion is enabled for CH[50]." newline bitfld.long 0x0 17. "NCE_CH49,NCE_CH49" "0: Normal conversion is disabled for CH[49].,1: Normal conversion is enabled for CH[49]." bitfld.long 0x0 16. "NCE_CH48,NCE_CH48" "0: Normal conversion is disabled for CH[48].,1: Normal conversion is enabled for CH[48]." group.long 0xB8++0x3 line.long 0x0 "ICJCMR1,Internal Channel Injected Conversion Mask Register 1" bitfld.long 0x0 23. "JCE_CH55,JCE_CH55" "0: Injected conversion is disabled for CH[55].,1: Injected conversion is enabled for CH[55]." bitfld.long 0x0 22. "JCE_CH54,JCE_CH54" "0: Injected conversion is disabled for CH[54].,1: Injected conversion is enabled for CH[54]." newline bitfld.long 0x0 21. "JCE_CH53,JCE_CH53" "0: Injected conversion is disabled for CH[53].,1: Injected conversion is enabled for CH[53]." bitfld.long 0x0 20. "JCE_CH52,JCE_CH52" "0: Injected conversion is disabled for CH[52].,1: Injected conversion is enabled for CH[52]." newline bitfld.long 0x0 19. "JCE_CH51,JCE_CH51" "0: Injected conversion is disabled for CH[51].,1: Injected conversion is enabled for CH[51]." bitfld.long 0x0 18. "JCE_CH50,JCE_CH50" "0: Injected conversion is disabled for CH[50].,1: Injected conversion is enabled for CH[50]." newline bitfld.long 0x0 17. "JCE_CH49,JCE_CH49" "0: Injected conversion is disabled for CH[49].,1: Injected conversion is enabled for CH[49]." bitfld.long 0x0 16. "JCE_CH48,JCE_CH48" "0: Injected conversion is disabled for CH[48].,1: Injected conversion is enabled for CH[48]." group.long 0xC8++0x3 line.long 0x0 "PDEDR,Power Down Exit Delay Register" hexmask.long.byte 0x0 0.--7. 1. "PDED,Defines the delay between the power-down bit reset and the starting of conversion." group.long 0x1C0++0x1F line.long 0x0 "ICDR48,Internal Channel Data Register 48" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4 "ICDR49,Internal Channel Data Register 49" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x8 "ICDR50,Internal Channel Data Register 50" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x8 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xC "ICDR51,Internal Channel Data Register 51" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xC 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x10 "ICDR52,Internal Channel Data Register 52" bitfld.long 0x10 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x10 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x10 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x10 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x10 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x10 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x10 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x14 "ICDR53,Internal Channel Data Register 53" bitfld.long 0x14 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x14 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x14 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x14 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x14 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x14 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x14 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x18 "ICDR54,Internal Channel Data Register 54" bitfld.long 0x18 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x18 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x18 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x18 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x18 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x18 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x18 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x1C "ICDR55,Internal Channel Data Register 55" bitfld.long 0x1C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x1C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x1C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x1C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x1C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x1C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x1C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" group.long 0x2C8++0x3 line.long 0x0 "ICWSELR6,Internal Channel Watchdog Select Register 6" bitfld.long 0x0 28.--29. "WSEL_CH55,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH54,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH53,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH52,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 12.--13. "WSEL_CH51,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 8.--9. "WSEL_CH50,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 4.--5. "WSEL_CH49,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 0.--1. "WSEL_CH48,0000 THRHLR0 register is selected" "0,1,2,3" group.long 0x2E4++0x3 line.long 0x0 "ICWENR1,Internal Channel Watchdog Enable Register 1" bitfld.long 0x0 23. "WEN_CH55,WEN_CH55" "0: Watchdog feature is disabled for CH[55],1: Watchdog feature is enabled fir CH[55]" bitfld.long 0x0 22. "WEN_CH54,WEN_CH54" "0: Watchdog feature is disabled for CH[54],1: Watchdog feature is enabled fir CH[54]" newline bitfld.long 0x0 21. "WEN_CH53,WEN_CH53" "0: Watchdog feature is disabled for CH[53],1: Watchdog feature is enabled fir CH[53]" bitfld.long 0x0 20. "WEN_CH52,WEN_CH52" "0: Watchdog feature is disabled for CH[52],1: Watchdog feature is enabled fir CH[52]" newline bitfld.long 0x0 19. "WEN_CH51,WEN_CH51" "0: Watchdog feature is disabled for CH[51],1: Watchdog feature is enabled fir CH[51]" bitfld.long 0x0 18. "WEN_CH50,WEN_CH50" "0: Watchdog feature is disabled for CH[50],1: Watchdog feature is enabled fir CH[50]" newline bitfld.long 0x0 17. "WEN_CH49,WEN_CH49" "0: Watchdog feature is disabled for CH[49],1: Watchdog feature is enabled fir CH[49]" bitfld.long 0x0 16. "WEN_CH48,WEN_CH48" "0: Watchdog feature is disabled for CH[48],1: Watchdog feature is enabled fir CH[48]" group.long 0x2F4++0x3 line.long 0x0 "ICAWORR1,Internal Channel Analog Watchdog Out of Range Register 1" bitfld.long 0x0 23. "AWOR_CH55,Analog watchdog out of range status for channel 55 provided corresponding WEN_CH55 bit is set." "0: CH[55] converted data is not out of range..,1: CH[55] converted data is out of range determined.." bitfld.long 0x0 22. "AWOR_CH54,Analog watchdog out of range status for channel 54 provided corresponding WEN_CH54 bit is set." "0: CH[54] converted data is not out of range..,1: CH[54] converted data is out of range determined.." newline bitfld.long 0x0 21. "AWOR_CH53,Analog watchdog out of range status for channel 53 provided corresponding WEN_CH53 bit is set." "0: CH[53] converted data is not out of range..,1: CH[53] converted data is out of range determined.." bitfld.long 0x0 20. "AWOR_CH52,Analog watchdog out of range status for channel 52 provided corresponding WEN_CH52 bit is set." "0: CH[52] converted data is not out of range..,1: CH[52] converted data is out of range determined.." newline bitfld.long 0x0 19. "AWOR_CH51,Analog watchdog out of range status for channel 51 provided corresponding WEN_CH51 bit is set." "0: CH[51] converted data is not out of range..,1: CH[51] converted data is out of range determined.." bitfld.long 0x0 18. "AWOR_CH50,Analog watchdog out of range status for channel 50 provided corresponding WEN_CH50 bit is set." "0: CH[50] converted data is not out of range..,1: CH[50] converted data is out of range determined.." newline bitfld.long 0x0 17. "AWOR_CH49,Analog watchdog out of range status for channel 49 provided corresponding WEN_CH49 bit is set." "0: CH[49] converted data is not out of range..,1: CH[49] converted data is out of range determined.." bitfld.long 0x0 16. "AWOR_CH48,Analog watchdog out of range status for channel 48 provided corresponding WEN_CH48 bit is set." "0: CH[48] converted data is not out of range..,1: CH[48] converted data is out of range determined.." group.long 0x400++0x13 line.long 0x0 "TCIPR,Test Channel Interrupt Pending Register" bitfld.long 0x0 31. "EOC_CH127,End of conversion interrupt pending bit for channel 127" "0: End of conversion for CH[127] has not occurred.,1: End of conversion for CH[127] has occurred" bitfld.long 0x0 30. "EOC_CH126,End of conversion interrupt pending bit for channel 126" "0: End of conversion for CH[126] has not occurred.,1: End of conversion for CH[126] has occurred" newline bitfld.long 0x0 29. "EOC_CH125,End of conversion interrupt pending bit for channel 125" "0: End of conversion for CH[125] has not occurred.,1: End of conversion for CH[125] has occurred" bitfld.long 0x0 28. "EOC_CH124,End of conversion interrupt pending bit for channel 124" "0: End of conversion for CH[124] has not occurred.,1: End of conversion for CH[124] has occurred" line.long 0x4 "TCIMR,Test Channel Interrupt Mask Register" bitfld.long 0x4 31. "IM_CH127,IM_CH127" "0: Interrupt for CH[127] is disabled.,1: Interrupt for CH[127] is enabled." bitfld.long 0x4 30. "IM_CH126,IM_CH126" "0: Interrupt for CH[126] is disabled.,1: Interrupt for CH[126] is enabled." newline bitfld.long 0x4 29. "IM_CH125,IM_CH125" "0: Interrupt for CH[125] is disabled.,1: Interrupt for CH[125] is enabled." bitfld.long 0x4 28. "IM_CH124,IM_CH124" "0: Interrupt for CH[124] is disabled.,1: Interrupt for CH[124] is enabled." line.long 0x8 "TCDSR,Test Channel DMA Select Register" bitfld.long 0x8 31. "DS_CH127,DS_CH127" "0: CH[127] is disabled to transfer data in DMA mode.,1: CH[127] is enabled to transfer data in DMA mode." bitfld.long 0x8 30. "DS_CH126,DS_CH126" "0: CH[126] is disabled to transfer data in DMA mode.,1: CH[126] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 29. "DS_CH125,DS_CH125" "0: CH[125] is disabled to transfer data in DMA mode.,1: CH[125] is enabled to transfer data in DMA mode." bitfld.long 0x8 28. "DS_CH124,DS_CH124" "0: CH[124] is disabled to transfer data in DMA mode.,1: CH[124] is enabled to transfer data in DMA mode." line.long 0xC "TCNCMR,Test Channel Normal Conversion Mask Register" bitfld.long 0xC 31. "NCE_CH127,NCE_CH127" "0: Normal conversion is disabled for CH[127].,1: Normal conversion is enabled for CH[127]." bitfld.long 0xC 30. "NCE_CH126,NCE_CH126" "0: Normal conversion is disabled for CH[126].,1: Normal conversion is enabled for CH[126]." newline bitfld.long 0xC 29. "NCE_CH125,NCE_CH125" "0: Normal conversion is disabled for CH[125].,1: Normal conversion is enabled for CH[125]." bitfld.long 0xC 28. "NCE_CH124,NCE_CH124" "0: Normal conversion is disabled for CH[124].,1: Normal conversion is enabled for CH[124]." line.long 0x10 "TCJCMR,Test Channel Injected Conversion Mask Register" bitfld.long 0x10 31. "JCE_CH127,JCE_CH127" "0: Injected conversion is disabled for CH[127].,1: Injected conversion is enabled for CH[127]." bitfld.long 0x10 30. "JCE_CH126,JCE_CH126" "0: Injected conversion is disabled for CH[126].,1: Injected conversion is enabled for CH[126]." newline bitfld.long 0x10 29. "JCE_CH125,JCE_CH125" "0: Injected conversion is disabled for CH[125].,1: Injected conversion is enabled for CH[125]." bitfld.long 0x10 28. "JCE_CH124,JCE_CH124" "0: Injected conversion is disabled for CH[124].,1: Injected conversion is enabled for CH[124]." group.long 0x420++0xB line.long 0x0 "TCWSELR3,Test Channel Watchdog Select Register 3" bitfld.long 0x0 28.--29. "WSEL_CH127,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH126,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH125,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH124,0000 THRHLR0 register is selected" "0,1,2,3" line.long 0x4 "TCWENR,Test Channel Watchdog Enable Register" bitfld.long 0x4 31. "WEN_CH127,WEN_CH127" "0: Watchdog feature is disabled for CH[127].,1: Watchdog feature is enabled for CH[127]." bitfld.long 0x4 30. "WEN_CH126,WEN_CH126" "0: Watchdog feature is disabled for CH[126].,1: Watchdog feature is enabled for CH[126]." newline bitfld.long 0x4 29. "WEN_CH125,WEN_CH125" "0: Watchdog feature is disabled for CH[125].,1: Watchdog feature is enabled for CH[125]." bitfld.long 0x4 28. "WEN_CH124,WEN_CH124" "0: Watchdog feature is disabled for CH[124].,1: Watchdog feature is enabled for CH[124]." line.long 0x8 "TCAWORR,Test Channel Analog Watchdog Out of Range Register" bitfld.long 0x8 31. "AWOR_CH127,Analog watchdog out of range status for channel 127 provided corresponding WEN_CH127 bit is set." "0: CH[127] converted data is not out of range..,1: CH[127] converted data is out of range.." bitfld.long 0x8 30. "AWOR_CH126,Analog watchdog out of range status for channel 126 provided corresponding WEN_CH126 bit is set." "0: CH[126] converted data is not out of range..,1: CH[126] converted data is out of range.." newline bitfld.long 0x8 29. "AWOR_CH125,Analog watchdog out of range status for channel 125 provided corresponding WEN_CH125 bit is set." "0: CH[125] converted data is not out of range..,1: CH[125] converted data is out of range.." bitfld.long 0x8 28. "AWOR_CH124,Analog watchdog out of range status for channel 124 provided corresponding WEN_CH124 bit is set." "0: CH[124] converted data is not out of range..,1: CH[124] converted data is out of range.." group.long 0x44C++0x3 line.long 0x0 "TCCAPR7,Test Channel Connection with Analog Pin Register 7" bitfld.long 0x0 31. "ESIC_TCH31,Enable short with internal channel for test channel 31" "0: Test channel 31 cannot be shorted with internal..,1: Test channel 31 can be shorted with internal.." hexmask.long.byte 0x0 24.--30. 1. "ICSEL_TCH31,Internal channel selection for short with test channel 31" newline bitfld.long 0x0 23. "ESIC_TCH30,Enable short with internal channel for test channel 30" "0: Test channel 30 cannot be shorted with internal..,1: Test channel 30 can be shorted with internal.." hexmask.long.byte 0x0 16.--22. 1. "ICSEL_TCH30,Internal channel selection for short with test channel 30" newline bitfld.long 0x0 15. "ESIC_TCH29,Enable short with internal channel for test channel 29" "0: Test channel 29 cannot be shorted with internal..,1: Test channel 29 can be shorted with internal.." hexmask.long.byte 0x0 8.--14. 1. "ICSEL_TCH29,Internal channel selection for short with test channel 29" newline bitfld.long 0x0 7. "ESIC_TCH28,Enable short with internal channel for test channel 28" "0: Test channel 28 cannot be shorted with internal..,1: Test channel 28 can be shorted with internal.." hexmask.long.byte 0x0 0.--6. 1. "ICSEL_TCH28,Internal channel selection for short with test channel 28" group.long 0x4C0++0xF line.long 0x0 "TCDR124,Test Channel Data Register 124" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x4 "TCDR125,Test Channel Data Register 125" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x8 "TCDR126,Test Channel Data Register 126" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xC "TCDR127,Test Channel Data Register 127" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." tree.end tree "SAR_ADC_12BIT_7" base ad:0x708A4000 group.long 0x0++0x3 line.long 0x0 "MCR,Main Configuration Register" bitfld.long 0x0 31. "OWREN,This bit enables or disables the functionality to overwrite unread converted data in ICDR TCDR ECDR registers." "0: Prevents overwrite of unread converted data new..,1: Enables converted data to be overwritten by a.." bitfld.long 0x0 30. "WLSIDE,Write left/right-aligned" "0: The conversion data in ICDR TCDR ECDR registers..,1: Conversion data is left-aligned (from 15 to (15.." newline bitfld.long 0x0 29. "MODE,One Shot/Scan" "0: One Shot Mode: Configures the normal conversion..,1: Scan Mode: Configures continuous chain.." bitfld.long 0x0 28. "XSTRTEN,This bit enables or disables the external start signal to initial a normal conversion. This can be used to synchronize multiple SARADCs concurrently." "0: External start signal is disabled,1: External start signal high level will start a.." newline bitfld.long 0x0 27. "NSTART,Setting this bit starts the chain or scan conversion. Resetting this bit during scan mode causes the current chain conversion to finish then stops the operation." "0: Cause the current chain conversion to finish and..,1: Starts the chain or scan conversion" bitfld.long 0x0 26. "NTRGEN,NTRGEN" "0: Normal trigger disabled to start a normal..,1: Normal trigger enabled to start a normal.." newline bitfld.long 0x0 24.--25. "NEDGESEL,NEDGESEL" "0: Falling edge of normal trigger is selected,1: Rising edge of normal trigger is selected,2: Both rising and falling edges of normal trigger..,3: Both rising and falling edges of normal trigger.." bitfld.long 0x0 23. "JSTART,Setting this bit will start the configured injected analog channels to be converted by software. Resetting this bit has no effect as the injected chain conversion cannot be interrupted." "0: Writting '0' has not effect,1: Starts the injected chain conversion" newline bitfld.long 0x0 22. "JTRGEN,JTRGEN" "0: Injection trigger disabled for channel injection..,1: Injection trigger enabled for channel injection" bitfld.long 0x0 20.--21. "JEDGESEL,JEDGESEL" "0: Falling edge of injection trigger is selected,1: Rising edge of injection trigger is selected,?,3: Both rising and falling edges of injection.." newline bitfld.long 0x0 19. "JTRGSEQ,JTRGSEQ" "0: Injection trigger sequence mode is disabled,1: Injection trigger sequence mode is enabled" bitfld.long 0x0 17. "CTUEN,Can be set or cleared anytime with some restriction mentioned in CTU trigger/control mode section." "0: The cross triggering unit is disabled and the..,1: The cross triggering unit is enabled and the.." newline bitfld.long 0x0 16. "CTU_MODE,This bit is present only if generic parameter CTSEN = 2 otherwise this bit is a reserved bit and always read as 0. This should be set only when ADC Digital is in powerdown mode." "0: CTU control mode is selected,1: CTU trigger mode is selected" bitfld.long 0x0 15. "WTRIGOUT,This control bit enables the Trigger on every threshold crossover event (crossing of Lower/Upper thresholds) of each WDG monitor to external trigger port (up to 16 ports for up to 16 WDGs)." "0: Trigger outputs disabled,1: Trigger ouputs enabled" newline bitfld.long 0x0 7. "ABORTCHAIN,When this bit is set the ongoing Chain Conversion is aborted. This bit is reset by hardware as soon as a new conversion is requested." "0: Conversion is not affected,1: Aborts the ongoing chain conversion" bitfld.long 0x0 6. "ABORT,When this bit is set the ongoing conversion is aborted and a new conversion is invoked. This bit is reset by hardware as soon as a new conversion is invoked." "0: Conversion is not affected,1: Aborts the ongoing conversion" newline bitfld.long 0x0 4. "FRZ,This bit enables to stop the SARADC conversions at the end of current channel conversion when SoC enters debug mode." "0: Conversions are not stopped,1: When SoC enters debug mode further conversions.." bitfld.long 0x0 2. "FCE,This bit enables the fast comparison mode for upcoming channel conversions." "0: Fast comparision mode disabled,1: Fast comparision mode enabled" newline bitfld.long 0x0 1. "EDCSELF,This bit selects the format for 3-bit output port ipp_decode_extch used as select line for external decode channel 8:1 muxes. The last three bits of external channel number are passed as is (if value 0) or converted to gray code (if value 1) and.." "0: Binary format,1: Gray code format" bitfld.long 0x0 0. "PWDN,When this bit is set the analog module is requested to enter Power Down mode." "0: SARADC is in normal mode,1: SARADC has been requested to power down" rgroup.long 0x4++0x3 line.long 0x0 "MSR,Main Status Register" bitfld.long 0x0 27. "NSTART,This status bit is used to signal that a normal conversion is ongoing." "0: Normal conversion is not taking place,1: Normal conversion is ongoing or the normal.." bitfld.long 0x0 23. "JSTART,This status bit is used to signal that an injected conversion is ongoing." "0: Injected conversion is not taking place,1: Injected conversion is ongoing" newline bitfld.long 0x0 18. "JABORTCHAIN,This status bit is used to signal that an Injected conversion chain has been aborted. This bit is reset when a new conversion starts." "0: Last injected conversion chain has not been..,1: Last injected conversion chain has been aborted" bitfld.long 0x0 16. "CTUSTART,This status bit is used to signal that a CTU conversion is ongoing. This bit is set when a CTU trigger pulse is received and the CTU conversion starts. When CTU trigger mode is enabled this bit is automatically reset when the conversion is.." "0: CTU triggered injected conversion is not taking..,1: CTU triggered injected conversion is ongoing" newline hexmask.long.byte 0x0 8.--15. 1. "CHADDR,Channel under measure address" bitfld.long 0x0 0.--2. "ADCSTATUS,The value of this parameter depends on ADC status. While requesting an external channel conversion SARADC digital interface needs to wait for a fixed time determined by DSD bitfield of DSDR before proceeding to actual sampling phase." "0: IDLE,1: Power-down,2: Wait state,?,4: Sample,?,6: Conversion,?" group.long 0x10++0x3 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CTUTRGERR,This Error Flag indicates that the next CTU trigger has been discarded as it overlapped during execution of current CTU conversion. This indicated that CTU sampling duration is less than programmed conversion time of ADC." "0: No CTU trigger overlap error condition since..,1: CTU trigger overlap error has occurred." bitfld.long 0x0 4. "EOCTU,This bit indicates the end of conversion for a CTU injected channel." "0: End of conversion of CTU triggered channel has..,1: End of conversion of CTU triggered channel has.." newline bitfld.long 0x0 3. "JEOC,This bit indicates the end of conversion for an injected channel." "0: End of conversion of injected channel has not..,1: End of conversion of injected channel has.." bitfld.long 0x0 2. "JECH,This bit indicates the end of conversion for an injected chain." "0: End of conversion of injected chain has not..,1: End of conversion of injected chain has occurred.." newline bitfld.long 0x0 1. "NEOC,This bit indicates the end of conversion for a normal channel." "0: End of conversion of normal channel has not..,1: End of conversion of normal channel has occurred.." bitfld.long 0x0 0. "NECH,This bit indicates the end of conversion for an normal chain." "0: End of conversion of normal chain has not..,1: End of conversion of normal chain has occurred.." group.long 0x18++0xB line.long 0x0 "ICIPR1,Internal Channel Interrupt Pending Register 1" bitfld.long 0x0 31. "EOC_CH63,End of conversion interrupt pending bit for channel 63" "0: End of conversion for CH[63] has not occured,1: End of conversion for CH[63] has occured" bitfld.long 0x0 30. "EOC_CH62,End of conversion interrupt pending bit for channel 62" "0: End of conversion for CH[62] has not occured,1: End of conversion for CH[62] has occured" newline bitfld.long 0x0 29. "EOC_CH61,End of conversion interrupt pending bit for channel 61" "0: End of conversion for CH[61] has not occured,1: End of conversion for CH[61] has occured" bitfld.long 0x0 28. "EOC_CH60,End of conversion interrupt pending bit for channel 60" "0: End of conversion for CH[60] has not occured,1: End of conversion for CH[60] has occured" newline bitfld.long 0x0 27. "EOC_CH59,End of conversion interrupt pending bit for channel 59" "0: End of conversion for CH[59] has not occured,1: End of conversion for CH[59] has occured" bitfld.long 0x0 26. "EOC_CH58,End of conversion interrupt pending bit for channel 58" "0: End of conversion for CH[58] has not occured,1: End of conversion for CH[58] has occured" newline bitfld.long 0x0 25. "EOC_CH57,End of conversion interrupt pending bit for channel 57" "0: End of conversion for CH[57] has not occured,1: End of conversion for CH[57] has occured" bitfld.long 0x0 24. "EOC_CH56,End of conversion interrupt pending bit for channel 56" "0: End of conversion for CH[56] has not occured,1: End of conversion for CH[56] has occured" line.long 0x4 "ICIPR2,Internal Channel Interrupt Pending Register 2" bitfld.long 0x4 1. "EOC_CH65,End of conversion interrupt pending bit for channel 65" "0: End of conversion for CH[65] has not occured,1: End of conversion for CH[65] has occured" bitfld.long 0x4 0. "EOC_CH64,End of conversion interrupt pending bit for channel 64" "0: End of conversion for CH[64] has not occured,1: End of conversion for CH[64] has occured" line.long 0x8 "IMR,Interrupt Mask Register" bitfld.long 0x8 5. "MSKCTUTRGERR,Mask bit for CTU Trigger" "0: CTUTRGERR interrupt is disabled,1: CTUTRGERR interrupt is enabled" bitfld.long 0x8 4. "MSKEOCTU,Mask bit for EOCTU" "0: EOCTU interrupt is disabled,1: EOCTU interrupt is enabled" newline bitfld.long 0x8 3. "MSKJEOC,Mask bit for JEOC" "0: JEOC interrupt is disabled,1: JEOC interrupt is enabled" bitfld.long 0x8 2. "MSKJECH,Mask bit for JECH" "0: JECH interrupt is disabled,1: JECH interrupt is enabled" newline bitfld.long 0x8 1. "MSKNEOC,Mask bit for NEOC" "0: NEOC interrupt is disabled,1: NEOC interrupt is enabled" bitfld.long 0x8 0. "MSKNECH,Mask bit for NECH" "0: NECH interrupt is disabled,1: NECH interrupt is enabled" group.long 0x28++0x13 line.long 0x0 "ICIMR1,Internal Channel Interrupt Mask Register 1" bitfld.long 0x0 31. "IM_CH63,Interrupt mask bit for channel 63" "0: Interupt for CH[63] is disabled,1: Interupt for CH[63] is enabled" bitfld.long 0x0 30. "IM_CH62,Interrupt mask bit for channel 62" "0: Interupt for CH[62] is disabled,1: Interupt for CH[62] is enabled" newline bitfld.long 0x0 29. "IM_CH61,Interrupt mask bit for channel 61" "0: Interupt for CH[61] is disabled,1: Interupt for CH[61] is enabled" bitfld.long 0x0 28. "IM_CH60,Interrupt mask bit for channel 60" "0: Interupt for CH[60] is disabled,1: Interupt for CH[60] is enabled" newline bitfld.long 0x0 27. "IM_CH59,Interrupt mask bit for channel 59" "0: Interupt for CH[59] is disabled,1: Interupt for CH[59] is enabled" bitfld.long 0x0 26. "IM_CH58,Interrupt mask bit for channel 58" "0: Interupt for CH[58] is disabled,1: Interupt for CH[58] is enabled" newline bitfld.long 0x0 25. "IM_CH57,Interrupt mask bit for channel 57" "0: Interupt for CH[57] is disabled,1: Interupt for CH[57] is enabled" bitfld.long 0x0 24. "IM_CH56,Interrupt mask bit for channel 56" "0: Interupt for CH[56] is disabled,1: Interupt for CH[56] is enabled" line.long 0x4 "ICIMR2,Internal Channel Interrupt Mask Register 2" bitfld.long 0x4 1. "IM_CH65,Interrupt mask bit for channel 65" "0: Interupt for CH[65] is disabled,1: Interupt for CH[65] is enabled" bitfld.long 0x4 0. "IM_CH64,Interrupt mask bit for channel 64" "0: Interupt for CH[64] is disabled,1: Interupt for CH[64] is enabled" line.long 0x8 "WTISR,Watchdog Threshold Interrupt Status Register" bitfld.long 0x8 7. "WDG3H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 3." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x8 6. "WDG3L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 3." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x8 5. "WDG2H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 2." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x8 4. "WDG2L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 2." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x8 3. "WDG1H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 1." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x8 2. "WDG1L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 1." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x8 1. "WDG0H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 0." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x8 0. "WDG0L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 0." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." line.long 0xC "WTIMR,Watchdog Threshold Interrupt Mask Register" bitfld.long 0xC 7. "MSKWDG3H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG3H is disabled.,1: Inetrupt for WDG3H is enabled." bitfld.long 0xC 6. "MSKWDG3L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG3L is disabled.,1: Inetrupt for WDG3L is enabled." newline bitfld.long 0xC 5. "MSKWDG2H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG2H is disabled.,1: Inetrupt for WDG2H is enabled." bitfld.long 0xC 4. "MSKWDG2L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG2L is disabled.,1: Inetrupt for WDG2L is enabled." newline bitfld.long 0xC 3. "MSKWDG1H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG1H is disabled.,1: Inetrupt for WDG1H is enabled." bitfld.long 0xC 2. "MSKWDG1L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG1L is disabled.,1: Inetrupt for WDG1L is enabled." newline bitfld.long 0xC 1. "MSKWDG0H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG0H is disabled.,1: Inetrupt for WDG0H is enabled." bitfld.long 0xC 0. "MSKWDG0L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG0L is disabled.,1: Inetrupt for WDG0L is enabled." line.long 0x10 "WLTCR,Watchdog Level Trigger Configuration Register" bitfld.long 0x10 3. "LTMW3,LTMW3" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0x10 2. "LTMW2,LTMW2" "0: Level Trigger Mode,1: Hysteresis Mode" newline bitfld.long 0x10 1. "LTMW1,LTMW1" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0x10 0. "LTMW0,LTMW0" "0: Level Trigger Mode,1: Hysteresis Mode" group.long 0x40++0x3 line.long 0x0 "DMAE,DMA Enable Register" bitfld.long 0x0 1. "DCLR,DMA clear sequence enable" "0: DMA request cleared by Acknowledge from DMA..,1: DMA request cleared on read of data registers" bitfld.long 0x0 0. "DMAEN,DMA global enable" "0: DMA feature disabled,1: DMA feature enabled" group.long 0x48++0x7 line.long 0x0 "ICDSR1,Internal Channel DMA Select Register 1" bitfld.long 0x0 31. "DS_CH63,DS_CH63" "0: CH[63] is disabled to transfer data in DMA mode.,1: CH[63] is enabled to transfer data in DMA mode." bitfld.long 0x0 30. "DS_CH62,DS_CH62" "0: CH[62] is disabled to transfer data in DMA mode.,1: CH[62] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 29. "DS_CH61,DS_CH61" "0: CH[61] is disabled to transfer data in DMA mode.,1: CH[61] is enabled to transfer data in DMA mode." bitfld.long 0x0 28. "DS_CH60,DS_CH60" "0: CH[60] is disabled to transfer data in DMA mode.,1: CH[60] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 27. "DS_CH59,DS_CH59" "0: CH[59] is disabled to transfer data in DMA mode.,1: CH[59] is enabled to transfer data in DMA mode." bitfld.long 0x0 26. "DS_CH58,DS_CH58" "0: CH[58] is disabled to transfer data in DMA mode.,1: CH[58] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 25. "DS_CH57,DS_CH57" "0: CH[57] is disabled to transfer data in DMA mode.,1: CH[57] is enabled to transfer data in DMA mode." bitfld.long 0x0 24. "DS_CH56,DS_CH56" "0: CH[56] is disabled to transfer data in DMA mode.,1: CH[56] is enabled to transfer data in DMA mode." line.long 0x4 "ICDSR2,Internal Channel DMA Select Register 2" bitfld.long 0x4 1. "DS_CH65,DS_CH65" "0: CH[65] is disabled to transfer data in DMA mode.,1: CH[65] is enabled to transfer data in DMA mode." bitfld.long 0x4 0. "DS_CH64,DS_CH64" "0: CH[64] is disabled to transfer data in DMA mode.,1: CH[64] is enabled to transfer data in DMA mode." group.long 0x60++0xF line.long 0x0 "WTHRHLR0,Watchdog Threshold Register 0" hexmask.long.word 0x0 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x0 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x4 "WTHRHLR1,Watchdog Threshold Register 1" hexmask.long.word 0x4 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x4 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x8 "WTHRHLR2,Watchdog Threshold Register 2" hexmask.long.word 0x8 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x8 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0xC "WTHRHLR3,Watchdog Threshold Register 3" hexmask.long.word 0xC 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0xC 0.--11. 1. "THRL,Low threshold value for channel x" group.long 0x94++0xF line.long 0x0 "CTR0,Conversion Timing Register 0" bitfld.long 0x0 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x0 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x4 "CTR1,Conversion Timing Register 1" bitfld.long 0x4 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x4 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x4 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x8 "CTR2,Conversion Timing Register 2" bitfld.long 0x8 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x8 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x8 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0xC "CTR3,Conversion Timing Register 3" bitfld.long 0xC 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0xC 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0xC 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." group.long 0xA8++0x7 line.long 0x0 "ICNCMR1,Internal Channel Normal Conversion Mask Register 1" bitfld.long 0x0 31. "NCE_CH63,NCE_CH63" "0: Normal conversion is disabled for CH[63].,1: Normal conversion is enabled for CH[63]." bitfld.long 0x0 30. "NCE_CH62,NCE_CH62" "0: Normal conversion is disabled for CH[62].,1: Normal conversion is enabled for CH[62]." newline bitfld.long 0x0 29. "NCE_CH61,NCE_CH61" "0: Normal conversion is disabled for CH[61].,1: Normal conversion is enabled for CH[61]." bitfld.long 0x0 28. "NCE_CH60,NCE_CH60" "0: Normal conversion is disabled for CH[60].,1: Normal conversion is enabled for CH[60]." newline bitfld.long 0x0 27. "NCE_CH59,NCE_CH59" "0: Normal conversion is disabled for CH[59].,1: Normal conversion is enabled for CH[59]." bitfld.long 0x0 26. "NCE_CH58,NCE_CH58" "0: Normal conversion is disabled for CH[58].,1: Normal conversion is enabled for CH[58]." newline bitfld.long 0x0 25. "NCE_CH57,NCE_CH57" "0: Normal conversion is disabled for CH[57].,1: Normal conversion is enabled for CH[57]." bitfld.long 0x0 24. "NCE_CH56,NCE_CH56" "0: Normal conversion is disabled for CH[56].,1: Normal conversion is enabled for CH[56]." line.long 0x4 "ICNCMR2,Internal Channel Normal Conversion Mask Register 2" bitfld.long 0x4 1. "NCE_CH65,NCE_CH65" "0: Normal conversion is disabled for CH[65].,1: Normal conversion is enabled for CH[65]." bitfld.long 0x4 0. "NCE_CH64,NCE_CH64" "0: Normal conversion is disabled for CH[64].,1: Normal conversion is enabled for CH[64]." group.long 0xB8++0x7 line.long 0x0 "ICJCMR1,Internal Channel Injected Conversion Mask Register 1" bitfld.long 0x0 31. "JCE_CH63,JCE_CH63" "0: Injected conversion is disabled for CH[63].,1: Injected conversion is enabled for CH[63]." bitfld.long 0x0 30. "JCE_CH62,JCE_CH62" "0: Injected conversion is disabled for CH[62].,1: Injected conversion is enabled for CH[62]." newline bitfld.long 0x0 29. "JCE_CH61,JCE_CH61" "0: Injected conversion is disabled for CH[61].,1: Injected conversion is enabled for CH[61]." bitfld.long 0x0 28. "JCE_CH60,JCE_CH60" "0: Injected conversion is disabled for CH[60].,1: Injected conversion is enabled for CH[60]." newline bitfld.long 0x0 27. "JCE_CH59,JCE_CH59" "0: Injected conversion is disabled for CH[59].,1: Injected conversion is enabled for CH[59]." bitfld.long 0x0 26. "JCE_CH58,JCE_CH58" "0: Injected conversion is disabled for CH[58].,1: Injected conversion is enabled for CH[58]." newline bitfld.long 0x0 25. "JCE_CH57,JCE_CH57" "0: Injected conversion is disabled for CH[57].,1: Injected conversion is enabled for CH[57]." bitfld.long 0x0 24. "JCE_CH56,JCE_CH56" "0: Injected conversion is disabled for CH[56].,1: Injected conversion is enabled for CH[56]." line.long 0x4 "ICJCMR2,Internal Channel Injected Conversion Mask Register 2" bitfld.long 0x4 1. "JCE_CH65,JCE_CH65" "0: Injected conversion is disabled for CH[65].,1: Injected conversion is enabled for CH[65]." bitfld.long 0x4 0. "JCE_CH64,JCE_CH64" "0: Injected conversion is disabled for CH[64].,1: Injected conversion is enabled for CH[64]." group.long 0xC8++0x3 line.long 0x0 "PDEDR,Power Down Exit Delay Register" hexmask.long.byte 0x0 0.--7. 1. "PDED,Defines the delay between the power-down bit reset and the starting of conversion." group.long 0x1E0++0x27 line.long 0x0 "ICDR56,Internal Channel Data Register 56" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4 "ICDR57,Internal Channel Data Register 57" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x8 "ICDR58,Internal Channel Data Register 58" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x8 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xC "ICDR59,Internal Channel Data Register 59" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xC 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x10 "ICDR60,Internal Channel Data Register 60" bitfld.long 0x10 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x10 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x10 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x10 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x10 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x10 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x10 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x14 "ICDR61,Internal Channel Data Register 61" bitfld.long 0x14 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x14 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x14 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x14 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x14 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x14 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x14 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x18 "ICDR62,Internal Channel Data Register 62" bitfld.long 0x18 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x18 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x18 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x18 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x18 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x18 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x18 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x1C "ICDR63,Internal Channel Data Register 63" bitfld.long 0x1C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x1C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x1C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x1C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x1C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x1C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x1C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x20 "ICDR64,Internal Channel Data Register 64" bitfld.long 0x20 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x20 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x20 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x20 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x20 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x20 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x20 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x24 "ICDR65,Internal Channel Data Register 65" bitfld.long 0x24 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x24 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x24 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x24 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x24 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x24 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x24 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" group.long 0x2CC++0x7 line.long 0x0 "ICWSELR7,Internal Channel Watchdog Select Register 7" bitfld.long 0x0 28.--29. "WSEL_CH63,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH62,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH61,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH60,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 12.--13. "WSEL_CH59,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 8.--9. "WSEL_CH58,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 4.--5. "WSEL_CH57,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 0.--1. "WSEL_CH56,0000 THRHLR0 register is selected" "0,1,2,3" line.long 0x4 "ICWSELR8,Internal Channel Watchdog Select Register 8" bitfld.long 0x4 4.--5. "WSEL_CH65,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x4 0.--1. "WSEL_CH64,0000 THRHLR0 register is selected" "0,1,2,3" group.long 0x2E4++0x7 line.long 0x0 "ICWENR1,Internal Channel Watchdog Enable Register 1" bitfld.long 0x0 31. "WEN_CH63,WEN_CH63" "0: Watchdog feature is disabled for CH[63],1: Watchdog feature is enabled fir CH[63]" bitfld.long 0x0 30. "WEN_CH62,WEN_CH62" "0: Watchdog feature is disabled for CH[62],1: Watchdog feature is enabled fir CH[62]" newline bitfld.long 0x0 29. "WEN_CH61,WEN_CH61" "0: Watchdog feature is disabled for CH[61],1: Watchdog feature is enabled fir CH[61]" bitfld.long 0x0 28. "WEN_CH60,WEN_CH60" "0: Watchdog feature is disabled for CH[60],1: Watchdog feature is enabled fir CH[60]" newline bitfld.long 0x0 27. "WEN_CH59,WEN_CH59" "0: Watchdog feature is disabled for CH[59],1: Watchdog feature is enabled fir CH[59]" bitfld.long 0x0 26. "WEN_CH58,WEN_CH58" "0: Watchdog feature is disabled for CH[58],1: Watchdog feature is enabled fir CH[58]" newline bitfld.long 0x0 25. "WEN_CH57,WEN_CH57" "0: Watchdog feature is disabled for CH[57],1: Watchdog feature is enabled fir CH[57]" bitfld.long 0x0 24. "WEN_CH56,WEN_CH56" "0: Watchdog feature is disabled for CH[56],1: Watchdog feature is enabled fir CH[56]" line.long 0x4 "ICWENR2,Internal Channel Watchdog Enable Register 2" bitfld.long 0x4 1. "WEN_CH65,WEN_CH65" "0: Watchdog feature is disabled for CH[65],1: Watchdog feature is enabled fir CH[65]" bitfld.long 0x4 0. "WEN_CH64,WEN_CH64" "0: Watchdog feature is disabled for CH[64],1: Watchdog feature is enabled fir CH[64]" group.long 0x2F4++0x7 line.long 0x0 "ICAWORR1,Internal Channel Analog Watchdog Out of Range Register 1" bitfld.long 0x0 31. "AWOR_CH63,Analog watchdog out of range status for channel 63 provided corresponding WEN_CH63 bit is set." "0: CH[63] converted data is not out of range..,1: CH[63] converted data is out of range determined.." bitfld.long 0x0 30. "AWOR_CH62,Analog watchdog out of range status for channel 62 provided corresponding WEN_CH62 bit is set." "0: CH[62] converted data is not out of range..,1: CH[62] converted data is out of range determined.." newline bitfld.long 0x0 29. "AWOR_CH61,Analog watchdog out of range status for channel 61 provided corresponding WEN_CH61 bit is set." "0: CH[61] converted data is not out of range..,1: CH[61] converted data is out of range determined.." bitfld.long 0x0 28. "AWOR_CH60,Analog watchdog out of range status for channel 60 provided corresponding WEN_CH60 bit is set." "0: CH[60] converted data is not out of range..,1: CH[60] converted data is out of range determined.." newline bitfld.long 0x0 27. "AWOR_CH59,Analog watchdog out of range status for channel 59 provided corresponding WEN_CH59 bit is set." "0: CH[59] converted data is not out of range..,1: CH[59] converted data is out of range determined.." bitfld.long 0x0 26. "AWOR_CH58,Analog watchdog out of range status for channel 58 provided corresponding WEN_CH58 bit is set." "0: CH[58] converted data is not out of range..,1: CH[58] converted data is out of range determined.." newline bitfld.long 0x0 25. "AWOR_CH57,Analog watchdog out of range status for channel 57 provided corresponding WEN_CH57 bit is set." "0: CH[57] converted data is not out of range..,1: CH[57] converted data is out of range determined.." bitfld.long 0x0 24. "AWOR_CH56,Analog watchdog out of range status for channel 56 provided corresponding WEN_CH56 bit is set." "0: CH[56] converted data is not out of range..,1: CH[56] converted data is out of range determined.." line.long 0x4 "ICAWORR2,Internal Channel Analog Watchdog Out of Range Register 2" bitfld.long 0x4 1. "AWOR_CH65,Analog watchdog out of range status for channel 65 provided corresponding WEN_CH65 bit is set." "0: CH[65] converted data is not out of range..,1: CH[65] converted data is out of range determined.." bitfld.long 0x4 0. "AWOR_CH64,Analog watchdog out of range status for channel 64 provided corresponding WEN_CH64 bit is set." "0: CH[64] converted data is not out of range..,1: CH[64] converted data is out of range determined.." group.long 0x400++0x13 line.long 0x0 "TCIPR,Test Channel Interrupt Pending Register" bitfld.long 0x0 31. "EOC_CH127,End of conversion interrupt pending bit for channel 127" "0: End of conversion for CH[127] has not occurred.,1: End of conversion for CH[127] has occurred" bitfld.long 0x0 30. "EOC_CH126,End of conversion interrupt pending bit for channel 126" "0: End of conversion for CH[126] has not occurred.,1: End of conversion for CH[126] has occurred" newline bitfld.long 0x0 29. "EOC_CH125,End of conversion interrupt pending bit for channel 125" "0: End of conversion for CH[125] has not occurred.,1: End of conversion for CH[125] has occurred" bitfld.long 0x0 28. "EOC_CH124,End of conversion interrupt pending bit for channel 124" "0: End of conversion for CH[124] has not occurred.,1: End of conversion for CH[124] has occurred" line.long 0x4 "TCIMR,Test Channel Interrupt Mask Register" bitfld.long 0x4 31. "IM_CH127,IM_CH127" "0: Interrupt for CH[127] is disabled.,1: Interrupt for CH[127] is enabled." bitfld.long 0x4 30. "IM_CH126,IM_CH126" "0: Interrupt for CH[126] is disabled.,1: Interrupt for CH[126] is enabled." newline bitfld.long 0x4 29. "IM_CH125,IM_CH125" "0: Interrupt for CH[125] is disabled.,1: Interrupt for CH[125] is enabled." bitfld.long 0x4 28. "IM_CH124,IM_CH124" "0: Interrupt for CH[124] is disabled.,1: Interrupt for CH[124] is enabled." line.long 0x8 "TCDSR,Test Channel DMA Select Register" bitfld.long 0x8 31. "DS_CH127,DS_CH127" "0: CH[127] is disabled to transfer data in DMA mode.,1: CH[127] is enabled to transfer data in DMA mode." bitfld.long 0x8 30. "DS_CH126,DS_CH126" "0: CH[126] is disabled to transfer data in DMA mode.,1: CH[126] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 29. "DS_CH125,DS_CH125" "0: CH[125] is disabled to transfer data in DMA mode.,1: CH[125] is enabled to transfer data in DMA mode." bitfld.long 0x8 28. "DS_CH124,DS_CH124" "0: CH[124] is disabled to transfer data in DMA mode.,1: CH[124] is enabled to transfer data in DMA mode." line.long 0xC "TCNCMR,Test Channel Normal Conversion Mask Register" bitfld.long 0xC 31. "NCE_CH127,NCE_CH127" "0: Normal conversion is disabled for CH[127].,1: Normal conversion is enabled for CH[127]." bitfld.long 0xC 30. "NCE_CH126,NCE_CH126" "0: Normal conversion is disabled for CH[126].,1: Normal conversion is enabled for CH[126]." newline bitfld.long 0xC 29. "NCE_CH125,NCE_CH125" "0: Normal conversion is disabled for CH[125].,1: Normal conversion is enabled for CH[125]." bitfld.long 0xC 28. "NCE_CH124,NCE_CH124" "0: Normal conversion is disabled for CH[124].,1: Normal conversion is enabled for CH[124]." line.long 0x10 "TCJCMR,Test Channel Injected Conversion Mask Register" bitfld.long 0x10 31. "JCE_CH127,JCE_CH127" "0: Injected conversion is disabled for CH[127].,1: Injected conversion is enabled for CH[127]." bitfld.long 0x10 30. "JCE_CH126,JCE_CH126" "0: Injected conversion is disabled for CH[126].,1: Injected conversion is enabled for CH[126]." newline bitfld.long 0x10 29. "JCE_CH125,JCE_CH125" "0: Injected conversion is disabled for CH[125].,1: Injected conversion is enabled for CH[125]." bitfld.long 0x10 28. "JCE_CH124,JCE_CH124" "0: Injected conversion is disabled for CH[124].,1: Injected conversion is enabled for CH[124]." group.long 0x420++0xB line.long 0x0 "TCWSELR3,Test Channel Watchdog Select Register 3" bitfld.long 0x0 28.--29. "WSEL_CH127,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH126,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH125,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH124,0000 THRHLR0 register is selected" "0,1,2,3" line.long 0x4 "TCWENR,Test Channel Watchdog Enable Register" bitfld.long 0x4 31. "WEN_CH127,WEN_CH127" "0: Watchdog feature is disabled for CH[127].,1: Watchdog feature is enabled for CH[127]." bitfld.long 0x4 30. "WEN_CH126,WEN_CH126" "0: Watchdog feature is disabled for CH[126].,1: Watchdog feature is enabled for CH[126]." newline bitfld.long 0x4 29. "WEN_CH125,WEN_CH125" "0: Watchdog feature is disabled for CH[125].,1: Watchdog feature is enabled for CH[125]." bitfld.long 0x4 28. "WEN_CH124,WEN_CH124" "0: Watchdog feature is disabled for CH[124].,1: Watchdog feature is enabled for CH[124]." line.long 0x8 "TCAWORR,Test Channel Analog Watchdog Out of Range Register" bitfld.long 0x8 31. "AWOR_CH127,Analog watchdog out of range status for channel 127 provided corresponding WEN_CH127 bit is set." "0: CH[127] converted data is not out of range..,1: CH[127] converted data is out of range.." bitfld.long 0x8 30. "AWOR_CH126,Analog watchdog out of range status for channel 126 provided corresponding WEN_CH126 bit is set." "0: CH[126] converted data is not out of range..,1: CH[126] converted data is out of range.." newline bitfld.long 0x8 29. "AWOR_CH125,Analog watchdog out of range status for channel 125 provided corresponding WEN_CH125 bit is set." "0: CH[125] converted data is not out of range..,1: CH[125] converted data is out of range.." bitfld.long 0x8 28. "AWOR_CH124,Analog watchdog out of range status for channel 124 provided corresponding WEN_CH124 bit is set." "0: CH[124] converted data is not out of range..,1: CH[124] converted data is out of range.." group.long 0x44C++0x3 line.long 0x0 "TCCAPR7,Test Channel Connection with Analog Pin Register 7" bitfld.long 0x0 31. "ESIC_TCH31,Enable short with internal channel for test channel 31" "0: Test channel 31 cannot be shorted with internal..,1: Test channel 31 can be shorted with internal.." hexmask.long.byte 0x0 24.--30. 1. "ICSEL_TCH31,Internal channel selection for short with test channel 31" newline bitfld.long 0x0 23. "ESIC_TCH30,Enable short with internal channel for test channel 30" "0: Test channel 30 cannot be shorted with internal..,1: Test channel 30 can be shorted with internal.." hexmask.long.byte 0x0 16.--22. 1. "ICSEL_TCH30,Internal channel selection for short with test channel 30" newline bitfld.long 0x0 15. "ESIC_TCH29,Enable short with internal channel for test channel 29" "0: Test channel 29 cannot be shorted with internal..,1: Test channel 29 can be shorted with internal.." hexmask.long.byte 0x0 8.--14. 1. "ICSEL_TCH29,Internal channel selection for short with test channel 29" newline bitfld.long 0x0 7. "ESIC_TCH28,Enable short with internal channel for test channel 28" "0: Test channel 28 cannot be shorted with internal..,1: Test channel 28 can be shorted with internal.." hexmask.long.byte 0x0 0.--6. 1. "ICSEL_TCH28,Internal channel selection for short with test channel 28" group.long 0x4C0++0xF line.long 0x0 "TCDR124,Test Channel Data Register 124" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x4 "TCDR125,Test Channel Data Register 125" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x8 "TCDR126,Test Channel Data Register 126" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xC "TCDR127,Test Channel Data Register 127" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." tree.end tree "SAR_ADC_12BIT_8" base ad:0x702AC000 group.long 0x0++0x3 line.long 0x0 "MCR,Main Configuration Register" bitfld.long 0x0 31. "OWREN,This bit enables or disables the functionality to overwrite unread converted data in ICDR TCDR ECDR registers." "0: Prevents overwrite of unread converted data new..,1: Enables converted data to be overwritten by a.." bitfld.long 0x0 30. "WLSIDE,Write left/right-aligned" "0: The conversion data in ICDR TCDR ECDR registers..,1: Conversion data is left-aligned (from 15 to (15.." newline bitfld.long 0x0 29. "MODE,One Shot/Scan" "0: One Shot Mode: Configures the normal conversion..,1: Scan Mode: Configures continuous chain.." bitfld.long 0x0 28. "XSTRTEN,This bit enables or disables the external start signal to initial a normal conversion. This can be used to synchronize multiple SARADCs concurrently." "0: External start signal is disabled,1: External start signal high level will start a.." newline bitfld.long 0x0 27. "NSTART,Setting this bit starts the chain or scan conversion. Resetting this bit during scan mode causes the current chain conversion to finish then stops the operation." "0: Cause the current chain conversion to finish and..,1: Starts the chain or scan conversion" bitfld.long 0x0 26. "NTRGEN,NTRGEN" "0: Normal trigger disabled to start a normal..,1: Normal trigger enabled to start a normal.." newline bitfld.long 0x0 24.--25. "NEDGESEL,NEDGESEL" "0: Falling edge of normal trigger is selected,1: Rising edge of normal trigger is selected,2: Both rising and falling edges of normal trigger..,3: Both rising and falling edges of normal trigger.." bitfld.long 0x0 23. "JSTART,Setting this bit will start the configured injected analog channels to be converted by software. Resetting this bit has no effect as the injected chain conversion cannot be interrupted." "0: Writting '0' has not effect,1: Starts the injected chain conversion" newline bitfld.long 0x0 22. "JTRGEN,JTRGEN" "0: Injection trigger disabled for channel injection..,1: Injection trigger enabled for channel injection" bitfld.long 0x0 20.--21. "JEDGESEL,JEDGESEL" "0: Falling edge of injection trigger is selected,1: Rising edge of injection trigger is selected,?,3: Both rising and falling edges of injection.." newline bitfld.long 0x0 19. "JTRGSEQ,JTRGSEQ" "0: Injection trigger sequence mode is disabled,1: Injection trigger sequence mode is enabled" bitfld.long 0x0 17. "CTUEN,Can be set or cleared anytime with some restriction mentioned in CTU trigger/control mode section." "0: The cross triggering unit is disabled and the..,1: The cross triggering unit is enabled and the.." newline bitfld.long 0x0 16. "CTU_MODE,This bit is present only if generic parameter CTSEN = 2 otherwise this bit is a reserved bit and always read as 0. This should be set only when ADC Digital is in powerdown mode." "0: CTU control mode is selected,1: CTU trigger mode is selected" bitfld.long 0x0 15. "WTRIGOUT,This control bit enables the Trigger on every threshold crossover event (crossing of Lower/Upper thresholds) of each WDG monitor to external trigger port (up to 16 ports for up to 16 WDGs)." "0: Trigger outputs disabled,1: Trigger ouputs enabled" newline bitfld.long 0x0 7. "ABORTCHAIN,When this bit is set the ongoing Chain Conversion is aborted. This bit is reset by hardware as soon as a new conversion is requested." "0: Conversion is not affected,1: Aborts the ongoing chain conversion" bitfld.long 0x0 6. "ABORT,When this bit is set the ongoing conversion is aborted and a new conversion is invoked. This bit is reset by hardware as soon as a new conversion is invoked." "0: Conversion is not affected,1: Aborts the ongoing conversion" newline bitfld.long 0x0 4. "FRZ,This bit enables to stop the SARADC conversions at the end of current channel conversion when SoC enters debug mode." "0: Conversions are not stopped,1: When SoC enters debug mode further conversions.." bitfld.long 0x0 2. "FCE,This bit enables the fast comparison mode for upcoming channel conversions." "0: Fast comparision mode disabled,1: Fast comparision mode enabled" newline bitfld.long 0x0 1. "EDCSELF,This bit selects the format for 3-bit output port ipp_decode_extch used as select line for external decode channel 8:1 muxes. The last three bits of external channel number are passed as is (if value 0) or converted to gray code (if value 1) and.." "0: Binary format,1: Gray code format" bitfld.long 0x0 0. "PWDN,When this bit is set the analog module is requested to enter Power Down mode." "0: SARADC is in normal mode,1: SARADC has been requested to power down" rgroup.long 0x4++0x3 line.long 0x0 "MSR,Main Status Register" bitfld.long 0x0 27. "NSTART,This status bit is used to signal that a normal conversion is ongoing." "0: Normal conversion is not taking place,1: Normal conversion is ongoing or the normal.." bitfld.long 0x0 23. "JSTART,This status bit is used to signal that an injected conversion is ongoing." "0: Injected conversion is not taking place,1: Injected conversion is ongoing" newline bitfld.long 0x0 18. "JABORTCHAIN,This status bit is used to signal that an Injected conversion chain has been aborted. This bit is reset when a new conversion starts." "0: Last injected conversion chain has not been..,1: Last injected conversion chain has been aborted" bitfld.long 0x0 16. "CTUSTART,This status bit is used to signal that a CTU conversion is ongoing. This bit is set when a CTU trigger pulse is received and the CTU conversion starts. When CTU trigger mode is enabled this bit is automatically reset when the conversion is.." "0: CTU triggered injected conversion is not taking..,1: CTU triggered injected conversion is ongoing" newline hexmask.long.byte 0x0 8.--15. 1. "CHADDR,Channel under measure address" bitfld.long 0x0 0.--2. "ADCSTATUS,The value of this parameter depends on ADC status. While requesting an external channel conversion SARADC digital interface needs to wait for a fixed time determined by DSD bitfield of DSDR before proceeding to actual sampling phase." "0: IDLE,1: Power-down,2: Wait state,?,4: Sample,?,6: Conversion,?" group.long 0x10++0x3 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CTUTRGERR,This Error Flag indicates that the next CTU trigger has been discarded as it overlapped during execution of current CTU conversion. This indicated that CTU sampling duration is less than programmed conversion time of ADC." "0: No CTU trigger overlap error condition since..,1: CTU trigger overlap error has occurred." bitfld.long 0x0 4. "EOCTU,This bit indicates the end of conversion for a CTU injected channel." "0: End of conversion of CTU triggered channel has..,1: End of conversion of CTU triggered channel has.." newline bitfld.long 0x0 3. "JEOC,This bit indicates the end of conversion for an injected channel." "0: End of conversion of injected channel has not..,1: End of conversion of injected channel has.." bitfld.long 0x0 2. "JECH,This bit indicates the end of conversion for an injected chain." "0: End of conversion of injected chain has not..,1: End of conversion of injected chain has occurred.." newline bitfld.long 0x0 1. "NEOC,This bit indicates the end of conversion for a normal channel." "0: End of conversion of normal channel has not..,1: End of conversion of normal channel has occurred.." bitfld.long 0x0 0. "NECH,This bit indicates the end of conversion for an normal chain." "0: End of conversion of normal chain has not..,1: End of conversion of normal chain has occurred.." group.long 0x1C++0x7 line.long 0x0 "ICIPR2,Internal Channel Interrupt Pending Register 2" bitfld.long 0x0 31. "EOC_CH95,End of conversion interrupt pending bit for channel 95" "0: End of conversion for CH[95] has not occured,1: End of conversion for CH[95] has occured" bitfld.long 0x0 30. "EOC_CH94,End of conversion interrupt pending bit for channel 94" "0: End of conversion for CH[94] has not occured,1: End of conversion for CH[94] has occured" newline bitfld.long 0x0 7. "EOC_CH71,End of conversion interrupt pending bit for channel 71" "0: End of conversion for CH[71] has not occured,1: End of conversion for CH[71] has occured" bitfld.long 0x0 6. "EOC_CH70,End of conversion interrupt pending bit for channel 70" "0: End of conversion for CH[70] has not occured,1: End of conversion for CH[70] has occured" newline bitfld.long 0x0 5. "EOC_CH69,End of conversion interrupt pending bit for channel 69" "0: End of conversion for CH[69] has not occured,1: End of conversion for CH[69] has occured" bitfld.long 0x0 4. "EOC_CH68,End of conversion interrupt pending bit for channel 68" "0: End of conversion for CH[68] has not occured,1: End of conversion for CH[68] has occured" newline bitfld.long 0x0 3. "EOC_CH67,End of conversion interrupt pending bit for channel 67" "0: End of conversion for CH[67] has not occured,1: End of conversion for CH[67] has occured" bitfld.long 0x0 2. "EOC_CH66,End of conversion interrupt pending bit for channel 66" "0: End of conversion for CH[66] has not occured,1: End of conversion for CH[66] has occured" newline bitfld.long 0x0 1. "EOC_CH65,End of conversion interrupt pending bit for channel 65" "0: End of conversion for CH[65] has not occured,1: End of conversion for CH[65] has occured" bitfld.long 0x0 0. "EOC_CH64,End of conversion interrupt pending bit for channel 64" "0: End of conversion for CH[64] has not occured,1: End of conversion for CH[64] has occured" line.long 0x4 "IMR,Interrupt Mask Register" bitfld.long 0x4 5. "MSKCTUTRGERR,Mask bit for CTU Trigger" "0: CTUTRGERR interrupt is disabled,1: CTUTRGERR interrupt is enabled" bitfld.long 0x4 4. "MSKEOCTU,Mask bit for EOCTU" "0: EOCTU interrupt is disabled,1: EOCTU interrupt is enabled" newline bitfld.long 0x4 3. "MSKJEOC,Mask bit for JEOC" "0: JEOC interrupt is disabled,1: JEOC interrupt is enabled" bitfld.long 0x4 2. "MSKJECH,Mask bit for JECH" "0: JECH interrupt is disabled,1: JECH interrupt is enabled" newline bitfld.long 0x4 1. "MSKNEOC,Mask bit for NEOC" "0: NEOC interrupt is disabled,1: NEOC interrupt is enabled" bitfld.long 0x4 0. "MSKNECH,Mask bit for NECH" "0: NECH interrupt is disabled,1: NECH interrupt is enabled" group.long 0x2C++0xF line.long 0x0 "ICIMR2,Internal Channel Interrupt Mask Register 2" bitfld.long 0x0 31. "IM_CH95,Interrupt mask bit for channel 95" "0: Interupt for CH[95] is disabled,1: Interupt for CH[95] is enabled" bitfld.long 0x0 30. "IM_CH94,Interrupt mask bit for channel 94" "0: Interupt for CH[94] is disabled,1: Interupt for CH[94] is enabled" newline bitfld.long 0x0 7. "IM_CH71,Interrupt mask bit for channel 71" "0: Interupt for CH[71] is disabled,1: Interupt for CH[71] is enabled" bitfld.long 0x0 6. "IM_CH70,Interrupt mask bit for channel 70" "0: Interupt for CH[70] is disabled,1: Interupt for CH[70] is enabled" newline bitfld.long 0x0 5. "IM_CH69,Interrupt mask bit for channel 69" "0: Interupt for CH[69] is disabled,1: Interupt for CH[69] is enabled" bitfld.long 0x0 4. "IM_CH68,Interrupt mask bit for channel 68" "0: Interupt for CH[68] is disabled,1: Interupt for CH[68] is enabled" newline bitfld.long 0x0 3. "IM_CH67,Interrupt mask bit for channel 67" "0: Interupt for CH[67] is disabled,1: Interupt for CH[67] is enabled" bitfld.long 0x0 2. "IM_CH66,Interrupt mask bit for channel 66" "0: Interupt for CH[66] is disabled,1: Interupt for CH[66] is enabled" newline bitfld.long 0x0 1. "IM_CH65,Interrupt mask bit for channel 65" "0: Interupt for CH[65] is disabled,1: Interupt for CH[65] is enabled" bitfld.long 0x0 0. "IM_CH64,Interrupt mask bit for channel 64" "0: Interupt for CH[64] is disabled,1: Interupt for CH[64] is enabled" line.long 0x4 "WTISR,Watchdog Threshold Interrupt Status Register" bitfld.long 0x4 7. "WDG3H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 3." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x4 6. "WDG3L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 3." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x4 5. "WDG2H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 2." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x4 4. "WDG2L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 2." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x4 3. "WDG1H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 1." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x4 2. "WDG1L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 1." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x4 1. "WDG0H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 0." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x4 0. "WDG0L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 0." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." line.long 0x8 "WTIMR,Watchdog Threshold Interrupt Mask Register" bitfld.long 0x8 7. "MSKWDG3H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG3H is disabled.,1: Inetrupt for WDG3H is enabled." bitfld.long 0x8 6. "MSKWDG3L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG3L is disabled.,1: Inetrupt for WDG3L is enabled." newline bitfld.long 0x8 5. "MSKWDG2H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG2H is disabled.,1: Inetrupt for WDG2H is enabled." bitfld.long 0x8 4. "MSKWDG2L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG2L is disabled.,1: Inetrupt for WDG2L is enabled." newline bitfld.long 0x8 3. "MSKWDG1H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG1H is disabled.,1: Inetrupt for WDG1H is enabled." bitfld.long 0x8 2. "MSKWDG1L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG1L is disabled.,1: Inetrupt for WDG1L is enabled." newline bitfld.long 0x8 1. "MSKWDG0H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG0H is disabled.,1: Inetrupt for WDG0H is enabled." bitfld.long 0x8 0. "MSKWDG0L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG0L is disabled.,1: Inetrupt for WDG0L is enabled." line.long 0xC "WLTCR,Watchdog Level Trigger Configuration Register" bitfld.long 0xC 3. "LTMW3,LTMW3" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0xC 2. "LTMW2,LTMW2" "0: Level Trigger Mode,1: Hysteresis Mode" newline bitfld.long 0xC 1. "LTMW1,LTMW1" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0xC 0. "LTMW0,LTMW0" "0: Level Trigger Mode,1: Hysteresis Mode" group.long 0x40++0x3 line.long 0x0 "DMAE,DMA Enable Register" bitfld.long 0x0 1. "DCLR,DMA clear sequence enable" "0: DMA request cleared by Acknowledge from DMA..,1: DMA request cleared on read of data registers" bitfld.long 0x0 0. "DMAEN,DMA global enable" "0: DMA feature disabled,1: DMA feature enabled" group.long 0x4C++0x3 line.long 0x0 "ICDSR2,Internal Channel DMA Select Register 2" bitfld.long 0x0 31. "DS_CH95,DS_CH95" "0: CH[95] is disabled to transfer data in DMA mode.,1: CH[95] is enabled to transfer data in DMA mode." bitfld.long 0x0 30. "DS_CH94,DS_CH94" "0: CH[94] is disabled to transfer data in DMA mode.,1: CH[94] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 7. "DS_CH71,DS_CH71" "0: CH[71] is disabled to transfer data in DMA mode.,1: CH[71] is enabled to transfer data in DMA mode." bitfld.long 0x0 6. "DS_CH70,DS_CH70" "0: CH[70] is disabled to transfer data in DMA mode.,1: CH[70] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 5. "DS_CH69,DS_CH69" "0: CH[69] is disabled to transfer data in DMA mode.,1: CH[69] is enabled to transfer data in DMA mode." bitfld.long 0x0 4. "DS_CH68,DS_CH68" "0: CH[68] is disabled to transfer data in DMA mode.,1: CH[68] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 3. "DS_CH67,DS_CH67" "0: CH[67] is disabled to transfer data in DMA mode.,1: CH[67] is enabled to transfer data in DMA mode." bitfld.long 0x0 2. "DS_CH66,DS_CH66" "0: CH[66] is disabled to transfer data in DMA mode.,1: CH[66] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 1. "DS_CH65,DS_CH65" "0: CH[65] is disabled to transfer data in DMA mode.,1: CH[65] is enabled to transfer data in DMA mode." bitfld.long 0x0 0. "DS_CH64,DS_CH64" "0: CH[64] is disabled to transfer data in DMA mode.,1: CH[64] is enabled to transfer data in DMA mode." group.long 0x60++0xF line.long 0x0 "WTHRHLR0,Watchdog Threshold Register 0" hexmask.long.word 0x0 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x0 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x4 "WTHRHLR1,Watchdog Threshold Register 1" hexmask.long.word 0x4 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x4 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x8 "WTHRHLR2,Watchdog Threshold Register 2" hexmask.long.word 0x8 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x8 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0xC "WTHRHLR3,Watchdog Threshold Register 3" hexmask.long.word 0xC 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0xC 0.--11. 1. "THRL,Low threshold value for channel x" group.long 0x94++0xF line.long 0x0 "CTR0,Conversion Timing Register 0" bitfld.long 0x0 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x0 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x4 "CTR1,Conversion Timing Register 1" bitfld.long 0x4 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x4 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x4 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x8 "CTR2,Conversion Timing Register 2" bitfld.long 0x8 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x8 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x8 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0xC "CTR3,Conversion Timing Register 3" bitfld.long 0xC 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0xC 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0xC 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." group.long 0xAC++0x3 line.long 0x0 "ICNCMR2,Internal Channel Normal Conversion Mask Register 2" bitfld.long 0x0 31. "NCE_CH95,NCE_CH95" "0: Normal conversion is disabled for CH[95].,1: Normal conversion is enabled for CH[95]." bitfld.long 0x0 30. "NCE_CH94,NCE_CH94" "0: Normal conversion is disabled for CH[94].,1: Normal conversion is enabled for CH[94]." newline bitfld.long 0x0 7. "NCE_CH71,NCE_CH71" "0: Normal conversion is disabled for CH[71].,1: Normal conversion is enabled for CH[71]." bitfld.long 0x0 6. "NCE_CH70,NCE_CH70" "0: Normal conversion is disabled for CH[70].,1: Normal conversion is enabled for CH[70]." newline bitfld.long 0x0 5. "NCE_CH69,NCE_CH69" "0: Normal conversion is disabled for CH[69].,1: Normal conversion is enabled for CH[69]." bitfld.long 0x0 4. "NCE_CH68,NCE_CH68" "0: Normal conversion is disabled for CH[68].,1: Normal conversion is enabled for CH[68]." newline bitfld.long 0x0 3. "NCE_CH67,NCE_CH67" "0: Normal conversion is disabled for CH[67].,1: Normal conversion is enabled for CH[67]." bitfld.long 0x0 2. "NCE_CH66,NCE_CH66" "0: Normal conversion is disabled for CH[66].,1: Normal conversion is enabled for CH[66]." newline bitfld.long 0x0 1. "NCE_CH65,NCE_CH65" "0: Normal conversion is disabled for CH[65].,1: Normal conversion is enabled for CH[65]." bitfld.long 0x0 0. "NCE_CH64,NCE_CH64" "0: Normal conversion is disabled for CH[64].,1: Normal conversion is enabled for CH[64]." group.long 0xBC++0x3 line.long 0x0 "ICJCMR2,Internal Channel Injected Conversion Mask Register 2" bitfld.long 0x0 31. "JCE_CH95,JCE_CH95" "0: Injected conversion is disabled for CH[95].,1: Injected conversion is enabled for CH[95]." bitfld.long 0x0 30. "JCE_CH94,JCE_CH94" "0: Injected conversion is disabled for CH[94].,1: Injected conversion is enabled for CH[94]." newline bitfld.long 0x0 7. "JCE_CH71,JCE_CH71" "0: Injected conversion is disabled for CH[71].,1: Injected conversion is enabled for CH[71]." bitfld.long 0x0 6. "JCE_CH70,JCE_CH70" "0: Injected conversion is disabled for CH[70].,1: Injected conversion is enabled for CH[70]." newline bitfld.long 0x0 5. "JCE_CH69,JCE_CH69" "0: Injected conversion is disabled for CH[69].,1: Injected conversion is enabled for CH[69]." bitfld.long 0x0 4. "JCE_CH68,JCE_CH68" "0: Injected conversion is disabled for CH[68].,1: Injected conversion is enabled for CH[68]." newline bitfld.long 0x0 3. "JCE_CH67,JCE_CH67" "0: Injected conversion is disabled for CH[67].,1: Injected conversion is enabled for CH[67]." bitfld.long 0x0 2. "JCE_CH66,JCE_CH66" "0: Injected conversion is disabled for CH[66].,1: Injected conversion is enabled for CH[66]." newline bitfld.long 0x0 1. "JCE_CH65,JCE_CH65" "0: Injected conversion is disabled for CH[65].,1: Injected conversion is enabled for CH[65]." bitfld.long 0x0 0. "JCE_CH64,JCE_CH64" "0: Injected conversion is disabled for CH[64].,1: Injected conversion is enabled for CH[64]." group.long 0xC8++0x3 line.long 0x0 "PDEDR,Power Down Exit Delay Register" hexmask.long.byte 0x0 0.--7. 1. "PDED,Defines the delay between the power-down bit reset and the starting of conversion." group.long 0x200++0x1F line.long 0x0 "ICDR64,Internal Channel Data Register 64" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4 "ICDR65,Internal Channel Data Register 65" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x8 "ICDR66,Internal Channel Data Register 66" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x8 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xC "ICDR67,Internal Channel Data Register 67" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xC 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x10 "ICDR68,Internal Channel Data Register 68" bitfld.long 0x10 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x10 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x10 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x10 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x10 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x10 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x10 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x14 "ICDR69,Internal Channel Data Register 69" bitfld.long 0x14 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x14 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x14 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x14 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x14 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x14 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x14 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x18 "ICDR70,Internal Channel Data Register 70" bitfld.long 0x18 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x18 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x18 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x18 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x18 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x18 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x18 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x1C "ICDR71,Internal Channel Data Register 71" bitfld.long 0x1C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x1C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x1C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x1C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x1C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x1C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x1C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" group.long 0x278++0x7 line.long 0x0 "ICDR94,Internal Channel Data Register 94" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4 "ICDR95,Internal Channel Data Register 95" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" group.long 0x2D0++0x3 line.long 0x0 "ICWSELR8,Internal Channel Watchdog Select Register 8" bitfld.long 0x0 28.--29. "WSEL_CH71,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH70,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH69,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH68,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 12.--13. "WSEL_CH67,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 8.--9. "WSEL_CH66,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 4.--5. "WSEL_CH65,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 0.--1. "WSEL_CH64,0000 THRHLR0 register is selected" "0,1,2,3" group.long 0x2DC++0x3 line.long 0x0 "ICWSELR11,Internal Channel Watchdog Select Register 11" bitfld.long 0x0 28.--29. "WSEL_CH95,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH94,0000 THRHLR0 register is selected" "0,1,2,3" group.long 0x2E8++0x3 line.long 0x0 "ICWENR2,Internal Channel Watchdog Enable Register 2" bitfld.long 0x0 31. "WEN_CH95,WEN_CH95" "0: Watchdog feature is disabled for CH[95],1: Watchdog feature is enabled fir CH[95]" bitfld.long 0x0 30. "WEN_CH94,WEN_CH94" "0: Watchdog feature is disabled for CH[94],1: Watchdog feature is enabled fir CH[94]" newline bitfld.long 0x0 7. "WEN_CH71,WEN_CH71" "0: Watchdog feature is disabled for CH[71],1: Watchdog feature is enabled fir CH[71]" bitfld.long 0x0 6. "WEN_CH70,WEN_CH70" "0: Watchdog feature is disabled for CH[70],1: Watchdog feature is enabled fir CH[70]" newline bitfld.long 0x0 5. "WEN_CH69,WEN_CH69" "0: Watchdog feature is disabled for CH[69],1: Watchdog feature is enabled fir CH[69]" bitfld.long 0x0 4. "WEN_CH68,WEN_CH68" "0: Watchdog feature is disabled for CH[68],1: Watchdog feature is enabled fir CH[68]" newline bitfld.long 0x0 3. "WEN_CH67,WEN_CH67" "0: Watchdog feature is disabled for CH[67],1: Watchdog feature is enabled fir CH[67]" bitfld.long 0x0 2. "WEN_CH66,WEN_CH66" "0: Watchdog feature is disabled for CH[66],1: Watchdog feature is enabled fir CH[66]" newline bitfld.long 0x0 1. "WEN_CH65,WEN_CH65" "0: Watchdog feature is disabled for CH[65],1: Watchdog feature is enabled fir CH[65]" bitfld.long 0x0 0. "WEN_CH64,WEN_CH64" "0: Watchdog feature is disabled for CH[64],1: Watchdog feature is enabled fir CH[64]" group.long 0x2F8++0x3 line.long 0x0 "ICAWORR2,Internal Channel Analog Watchdog Out of Range Register 2" bitfld.long 0x0 31. "AWOR_CH95,Analog watchdog out of range status for channel 95 provided corresponding WEN_CH95 bit is set." "0: CH[95] converted data is not out of range..,1: CH[95] converted data is out of range determined.." bitfld.long 0x0 30. "AWOR_CH94,Analog watchdog out of range status for channel 94 provided corresponding WEN_CH94 bit is set." "0: CH[94] converted data is not out of range..,1: CH[94] converted data is out of range determined.." newline bitfld.long 0x0 7. "AWOR_CH71,Analog watchdog out of range status for channel 71 provided corresponding WEN_CH71 bit is set." "0: CH[71] converted data is not out of range..,1: CH[71] converted data is out of range determined.." bitfld.long 0x0 6. "AWOR_CH70,Analog watchdog out of range status for channel 70 provided corresponding WEN_CH70 bit is set." "0: CH[70] converted data is not out of range..,1: CH[70] converted data is out of range determined.." newline bitfld.long 0x0 5. "AWOR_CH69,Analog watchdog out of range status for channel 69 provided corresponding WEN_CH69 bit is set." "0: CH[69] converted data is not out of range..,1: CH[69] converted data is out of range determined.." bitfld.long 0x0 4. "AWOR_CH68,Analog watchdog out of range status for channel 68 provided corresponding WEN_CH68 bit is set." "0: CH[68] converted data is not out of range..,1: CH[68] converted data is out of range determined.." newline bitfld.long 0x0 3. "AWOR_CH67,Analog watchdog out of range status for channel 67 provided corresponding WEN_CH67 bit is set." "0: CH[67] converted data is not out of range..,1: CH[67] converted data is out of range determined.." bitfld.long 0x0 2. "AWOR_CH66,Analog watchdog out of range status for channel 66 provided corresponding WEN_CH66 bit is set." "0: CH[66] converted data is not out of range..,1: CH[66] converted data is out of range determined.." newline bitfld.long 0x0 1. "AWOR_CH65,Analog watchdog out of range status for channel 65 provided corresponding WEN_CH65 bit is set." "0: CH[65] converted data is not out of range..,1: CH[65] converted data is out of range determined.." bitfld.long 0x0 0. "AWOR_CH64,Analog watchdog out of range status for channel 64 provided corresponding WEN_CH64 bit is set." "0: CH[64] converted data is not out of range..,1: CH[64] converted data is out of range determined.." group.long 0x400++0x13 line.long 0x0 "TCIPR,Test Channel Interrupt Pending Register" bitfld.long 0x0 31. "EOC_CH127,End of conversion interrupt pending bit for channel 127" "0: End of conversion for CH[127] has not occurred.,1: End of conversion for CH[127] has occurred" bitfld.long 0x0 30. "EOC_CH126,End of conversion interrupt pending bit for channel 126" "0: End of conversion for CH[126] has not occurred.,1: End of conversion for CH[126] has occurred" newline bitfld.long 0x0 29. "EOC_CH125,End of conversion interrupt pending bit for channel 125" "0: End of conversion for CH[125] has not occurred.,1: End of conversion for CH[125] has occurred" bitfld.long 0x0 28. "EOC_CH124,End of conversion interrupt pending bit for channel 124" "0: End of conversion for CH[124] has not occurred.,1: End of conversion for CH[124] has occurred" line.long 0x4 "TCIMR,Test Channel Interrupt Mask Register" bitfld.long 0x4 31. "IM_CH127,IM_CH127" "0: Interrupt for CH[127] is disabled.,1: Interrupt for CH[127] is enabled." bitfld.long 0x4 30. "IM_CH126,IM_CH126" "0: Interrupt for CH[126] is disabled.,1: Interrupt for CH[126] is enabled." newline bitfld.long 0x4 29. "IM_CH125,IM_CH125" "0: Interrupt for CH[125] is disabled.,1: Interrupt for CH[125] is enabled." bitfld.long 0x4 28. "IM_CH124,IM_CH124" "0: Interrupt for CH[124] is disabled.,1: Interrupt for CH[124] is enabled." line.long 0x8 "TCDSR,Test Channel DMA Select Register" bitfld.long 0x8 31. "DS_CH127,DS_CH127" "0: CH[127] is disabled to transfer data in DMA mode.,1: CH[127] is enabled to transfer data in DMA mode." bitfld.long 0x8 30. "DS_CH126,DS_CH126" "0: CH[126] is disabled to transfer data in DMA mode.,1: CH[126] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 29. "DS_CH125,DS_CH125" "0: CH[125] is disabled to transfer data in DMA mode.,1: CH[125] is enabled to transfer data in DMA mode." bitfld.long 0x8 28. "DS_CH124,DS_CH124" "0: CH[124] is disabled to transfer data in DMA mode.,1: CH[124] is enabled to transfer data in DMA mode." line.long 0xC "TCNCMR,Test Channel Normal Conversion Mask Register" bitfld.long 0xC 31. "NCE_CH127,NCE_CH127" "0: Normal conversion is disabled for CH[127].,1: Normal conversion is enabled for CH[127]." bitfld.long 0xC 30. "NCE_CH126,NCE_CH126" "0: Normal conversion is disabled for CH[126].,1: Normal conversion is enabled for CH[126]." newline bitfld.long 0xC 29. "NCE_CH125,NCE_CH125" "0: Normal conversion is disabled for CH[125].,1: Normal conversion is enabled for CH[125]." bitfld.long 0xC 28. "NCE_CH124,NCE_CH124" "0: Normal conversion is disabled for CH[124].,1: Normal conversion is enabled for CH[124]." line.long 0x10 "TCJCMR,Test Channel Injected Conversion Mask Register" bitfld.long 0x10 31. "JCE_CH127,JCE_CH127" "0: Injected conversion is disabled for CH[127].,1: Injected conversion is enabled for CH[127]." bitfld.long 0x10 30. "JCE_CH126,JCE_CH126" "0: Injected conversion is disabled for CH[126].,1: Injected conversion is enabled for CH[126]." newline bitfld.long 0x10 29. "JCE_CH125,JCE_CH125" "0: Injected conversion is disabled for CH[125].,1: Injected conversion is enabled for CH[125]." bitfld.long 0x10 28. "JCE_CH124,JCE_CH124" "0: Injected conversion is disabled for CH[124].,1: Injected conversion is enabled for CH[124]." group.long 0x420++0xB line.long 0x0 "TCWSELR3,Test Channel Watchdog Select Register 3" bitfld.long 0x0 28.--29. "WSEL_CH127,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH126,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH125,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH124,0000 THRHLR0 register is selected" "0,1,2,3" line.long 0x4 "TCWENR,Test Channel Watchdog Enable Register" bitfld.long 0x4 31. "WEN_CH127,WEN_CH127" "0: Watchdog feature is disabled for CH[127].,1: Watchdog feature is enabled for CH[127]." bitfld.long 0x4 30. "WEN_CH126,WEN_CH126" "0: Watchdog feature is disabled for CH[126].,1: Watchdog feature is enabled for CH[126]." newline bitfld.long 0x4 29. "WEN_CH125,WEN_CH125" "0: Watchdog feature is disabled for CH[125].,1: Watchdog feature is enabled for CH[125]." bitfld.long 0x4 28. "WEN_CH124,WEN_CH124" "0: Watchdog feature is disabled for CH[124].,1: Watchdog feature is enabled for CH[124]." line.long 0x8 "TCAWORR,Test Channel Analog Watchdog Out of Range Register" bitfld.long 0x8 31. "AWOR_CH127,Analog watchdog out of range status for channel 127 provided corresponding WEN_CH127 bit is set." "0: CH[127] converted data is not out of range..,1: CH[127] converted data is out of range.." bitfld.long 0x8 30. "AWOR_CH126,Analog watchdog out of range status for channel 126 provided corresponding WEN_CH126 bit is set." "0: CH[126] converted data is not out of range..,1: CH[126] converted data is out of range.." newline bitfld.long 0x8 29. "AWOR_CH125,Analog watchdog out of range status for channel 125 provided corresponding WEN_CH125 bit is set." "0: CH[125] converted data is not out of range..,1: CH[125] converted data is out of range.." bitfld.long 0x8 28. "AWOR_CH124,Analog watchdog out of range status for channel 124 provided corresponding WEN_CH124 bit is set." "0: CH[124] converted data is not out of range..,1: CH[124] converted data is out of range.." group.long 0x44C++0x3 line.long 0x0 "TCCAPR7,Test Channel Connection with Analog Pin Register 7" bitfld.long 0x0 31. "ESIC_TCH31,Enable short with internal channel for test channel 31" "0: Test channel 31 cannot be shorted with internal..,1: Test channel 31 can be shorted with internal.." hexmask.long.byte 0x0 24.--30. 1. "ICSEL_TCH31,Internal channel selection for short with test channel 31" newline bitfld.long 0x0 23. "ESIC_TCH30,Enable short with internal channel for test channel 30" "0: Test channel 30 cannot be shorted with internal..,1: Test channel 30 can be shorted with internal.." hexmask.long.byte 0x0 16.--22. 1. "ICSEL_TCH30,Internal channel selection for short with test channel 30" newline bitfld.long 0x0 15. "ESIC_TCH29,Enable short with internal channel for test channel 29" "0: Test channel 29 cannot be shorted with internal..,1: Test channel 29 can be shorted with internal.." hexmask.long.byte 0x0 8.--14. 1. "ICSEL_TCH29,Internal channel selection for short with test channel 29" newline bitfld.long 0x0 7. "ESIC_TCH28,Enable short with internal channel for test channel 28" "0: Test channel 28 cannot be shorted with internal..,1: Test channel 28 can be shorted with internal.." hexmask.long.byte 0x0 0.--6. 1. "ICSEL_TCH28,Internal channel selection for short with test channel 28" group.long 0x4C0++0xF line.long 0x0 "TCDR124,Test Channel Data Register 124" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x4 "TCDR125,Test Channel Data Register 125" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x8 "TCDR126,Test Channel Data Register 126" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xC "TCDR127,Test Channel Data Register 127" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." tree.end tree "SAR_ADC_12BIT_9" base ad:0x708AC000 group.long 0x0++0x3 line.long 0x0 "MCR,Main Configuration Register" bitfld.long 0x0 31. "OWREN,This bit enables or disables the functionality to overwrite unread converted data in ICDR TCDR ECDR registers." "0: Prevents overwrite of unread converted data new..,1: Enables converted data to be overwritten by a.." bitfld.long 0x0 30. "WLSIDE,Write left/right-aligned" "0: The conversion data in ICDR TCDR ECDR registers..,1: Conversion data is left-aligned (from 15 to (15.." newline bitfld.long 0x0 29. "MODE,One Shot/Scan" "0: One Shot Mode: Configures the normal conversion..,1: Scan Mode: Configures continuous chain.." bitfld.long 0x0 28. "XSTRTEN,This bit enables or disables the external start signal to initial a normal conversion. This can be used to synchronize multiple SARADCs concurrently." "0: External start signal is disabled,1: External start signal high level will start a.." newline bitfld.long 0x0 27. "NSTART,Setting this bit starts the chain or scan conversion. Resetting this bit during scan mode causes the current chain conversion to finish then stops the operation." "0: Cause the current chain conversion to finish and..,1: Starts the chain or scan conversion" bitfld.long 0x0 26. "NTRGEN,NTRGEN" "0: Normal trigger disabled to start a normal..,1: Normal trigger enabled to start a normal.." newline bitfld.long 0x0 24.--25. "NEDGESEL,NEDGESEL" "0: Falling edge of normal trigger is selected,1: Rising edge of normal trigger is selected,2: Both rising and falling edges of normal trigger..,3: Both rising and falling edges of normal trigger.." bitfld.long 0x0 23. "JSTART,Setting this bit will start the configured injected analog channels to be converted by software. Resetting this bit has no effect as the injected chain conversion cannot be interrupted." "0: Writting '0' has not effect,1: Starts the injected chain conversion" newline bitfld.long 0x0 22. "JTRGEN,JTRGEN" "0: Injection trigger disabled for channel injection..,1: Injection trigger enabled for channel injection" bitfld.long 0x0 20.--21. "JEDGESEL,JEDGESEL" "0: Falling edge of injection trigger is selected,1: Rising edge of injection trigger is selected,?,3: Both rising and falling edges of injection.." newline bitfld.long 0x0 19. "JTRGSEQ,JTRGSEQ" "0: Injection trigger sequence mode is disabled,1: Injection trigger sequence mode is enabled" bitfld.long 0x0 17. "CTUEN,Can be set or cleared anytime with some restriction mentioned in CTU trigger/control mode section." "0: The cross triggering unit is disabled and the..,1: The cross triggering unit is enabled and the.." newline bitfld.long 0x0 16. "CTU_MODE,This bit is present only if generic parameter CTSEN = 2 otherwise this bit is a reserved bit and always read as 0. This should be set only when ADC Digital is in powerdown mode." "0: CTU control mode is selected,1: CTU trigger mode is selected" bitfld.long 0x0 15. "WTRIGOUT,This control bit enables the Trigger on every threshold crossover event (crossing of Lower/Upper thresholds) of each WDG monitor to external trigger port (up to 16 ports for up to 16 WDGs)." "0: Trigger outputs disabled,1: Trigger ouputs enabled" newline bitfld.long 0x0 7. "ABORTCHAIN,When this bit is set the ongoing Chain Conversion is aborted. This bit is reset by hardware as soon as a new conversion is requested." "0: Conversion is not affected,1: Aborts the ongoing chain conversion" bitfld.long 0x0 6. "ABORT,When this bit is set the ongoing conversion is aborted and a new conversion is invoked. This bit is reset by hardware as soon as a new conversion is invoked." "0: Conversion is not affected,1: Aborts the ongoing conversion" newline bitfld.long 0x0 4. "FRZ,This bit enables to stop the SARADC conversions at the end of current channel conversion when SoC enters debug mode." "0: Conversions are not stopped,1: When SoC enters debug mode further conversions.." bitfld.long 0x0 2. "FCE,This bit enables the fast comparison mode for upcoming channel conversions." "0: Fast comparision mode disabled,1: Fast comparision mode enabled" newline bitfld.long 0x0 1. "EDCSELF,This bit selects the format for 3-bit output port ipp_decode_extch used as select line for external decode channel 8:1 muxes. The last three bits of external channel number are passed as is (if value 0) or converted to gray code (if value 1) and.." "0: Binary format,1: Gray code format" bitfld.long 0x0 0. "PWDN,When this bit is set the analog module is requested to enter Power Down mode." "0: SARADC is in normal mode,1: SARADC has been requested to power down" rgroup.long 0x4++0x3 line.long 0x0 "MSR,Main Status Register" bitfld.long 0x0 27. "NSTART,This status bit is used to signal that a normal conversion is ongoing." "0: Normal conversion is not taking place,1: Normal conversion is ongoing or the normal.." bitfld.long 0x0 23. "JSTART,This status bit is used to signal that an injected conversion is ongoing." "0: Injected conversion is not taking place,1: Injected conversion is ongoing" newline bitfld.long 0x0 18. "JABORTCHAIN,This status bit is used to signal that an Injected conversion chain has been aborted. This bit is reset when a new conversion starts." "0: Last injected conversion chain has not been..,1: Last injected conversion chain has been aborted" bitfld.long 0x0 16. "CTUSTART,This status bit is used to signal that a CTU conversion is ongoing. This bit is set when a CTU trigger pulse is received and the CTU conversion starts. When CTU trigger mode is enabled this bit is automatically reset when the conversion is.." "0: CTU triggered injected conversion is not taking..,1: CTU triggered injected conversion is ongoing" newline hexmask.long.byte 0x0 8.--15. 1. "CHADDR,Channel under measure address" bitfld.long 0x0 0.--2. "ADCSTATUS,The value of this parameter depends on ADC status. While requesting an external channel conversion SARADC digital interface needs to wait for a fixed time determined by DSD bitfield of DSDR before proceeding to actual sampling phase." "0: IDLE,1: Power-down,2: Wait state,?,4: Sample,?,6: Conversion,?" group.long 0x10++0x3 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CTUTRGERR,This Error Flag indicates that the next CTU trigger has been discarded as it overlapped during execution of current CTU conversion. This indicated that CTU sampling duration is less than programmed conversion time of ADC." "0: No CTU trigger overlap error condition since..,1: CTU trigger overlap error has occurred." bitfld.long 0x0 4. "EOCTU,This bit indicates the end of conversion for a CTU injected channel." "0: End of conversion of CTU triggered channel has..,1: End of conversion of CTU triggered channel has.." newline bitfld.long 0x0 3. "JEOC,This bit indicates the end of conversion for an injected channel." "0: End of conversion of injected channel has not..,1: End of conversion of injected channel has.." bitfld.long 0x0 2. "JECH,This bit indicates the end of conversion for an injected chain." "0: End of conversion of injected chain has not..,1: End of conversion of injected chain has occurred.." newline bitfld.long 0x0 1. "NEOC,This bit indicates the end of conversion for a normal channel." "0: End of conversion of normal channel has not..,1: End of conversion of normal channel has occurred.." bitfld.long 0x0 0. "NECH,This bit indicates the end of conversion for an normal chain." "0: End of conversion of normal chain has not..,1: End of conversion of normal chain has occurred.." group.long 0x1C++0x7 line.long 0x0 "ICIPR2,Internal Channel Interrupt Pending Register 2" bitfld.long 0x0 15. "EOC_CH79,End of conversion interrupt pending bit for channel 79" "0: End of conversion for CH[79] has not occured,1: End of conversion for CH[79] has occured" bitfld.long 0x0 14. "EOC_CH78,End of conversion interrupt pending bit for channel 78" "0: End of conversion for CH[78] has not occured,1: End of conversion for CH[78] has occured" newline bitfld.long 0x0 13. "EOC_CH77,End of conversion interrupt pending bit for channel 77" "0: End of conversion for CH[77] has not occured,1: End of conversion for CH[77] has occured" bitfld.long 0x0 12. "EOC_CH76,End of conversion interrupt pending bit for channel 76" "0: End of conversion for CH[76] has not occured,1: End of conversion for CH[76] has occured" newline bitfld.long 0x0 11. "EOC_CH75,End of conversion interrupt pending bit for channel 75" "0: End of conversion for CH[75] has not occured,1: End of conversion for CH[75] has occured" bitfld.long 0x0 10. "EOC_CH74,End of conversion interrupt pending bit for channel 74" "0: End of conversion for CH[74] has not occured,1: End of conversion for CH[74] has occured" newline bitfld.long 0x0 9. "EOC_CH73,End of conversion interrupt pending bit for channel 73" "0: End of conversion for CH[73] has not occured,1: End of conversion for CH[73] has occured" bitfld.long 0x0 8. "EOC_CH72,End of conversion interrupt pending bit for channel 72" "0: End of conversion for CH[72] has not occured,1: End of conversion for CH[72] has occured" line.long 0x4 "IMR,Interrupt Mask Register" bitfld.long 0x4 5. "MSKCTUTRGERR,Mask bit for CTU Trigger" "0: CTUTRGERR interrupt is disabled,1: CTUTRGERR interrupt is enabled" bitfld.long 0x4 4. "MSKEOCTU,Mask bit for EOCTU" "0: EOCTU interrupt is disabled,1: EOCTU interrupt is enabled" newline bitfld.long 0x4 3. "MSKJEOC,Mask bit for JEOC" "0: JEOC interrupt is disabled,1: JEOC interrupt is enabled" bitfld.long 0x4 2. "MSKJECH,Mask bit for JECH" "0: JECH interrupt is disabled,1: JECH interrupt is enabled" newline bitfld.long 0x4 1. "MSKNEOC,Mask bit for NEOC" "0: NEOC interrupt is disabled,1: NEOC interrupt is enabled" bitfld.long 0x4 0. "MSKNECH,Mask bit for NECH" "0: NECH interrupt is disabled,1: NECH interrupt is enabled" group.long 0x2C++0xF line.long 0x0 "ICIMR2,Internal Channel Interrupt Mask Register 2" bitfld.long 0x0 15. "IM_CH79,Interrupt mask bit for channel 79" "0: Interupt for CH[79] is disabled,1: Interupt for CH[79] is enabled" bitfld.long 0x0 14. "IM_CH78,Interrupt mask bit for channel 78" "0: Interupt for CH[78] is disabled,1: Interupt for CH[78] is enabled" newline bitfld.long 0x0 13. "IM_CH77,Interrupt mask bit for channel 77" "0: Interupt for CH[77] is disabled,1: Interupt for CH[77] is enabled" bitfld.long 0x0 12. "IM_CH76,Interrupt mask bit for channel 76" "0: Interupt for CH[76] is disabled,1: Interupt for CH[76] is enabled" newline bitfld.long 0x0 11. "IM_CH75,Interrupt mask bit for channel 75" "0: Interupt for CH[75] is disabled,1: Interupt for CH[75] is enabled" bitfld.long 0x0 10. "IM_CH74,Interrupt mask bit for channel 74" "0: Interupt for CH[74] is disabled,1: Interupt for CH[74] is enabled" newline bitfld.long 0x0 9. "IM_CH73,Interrupt mask bit for channel 73" "0: Interupt for CH[73] is disabled,1: Interupt for CH[73] is enabled" bitfld.long 0x0 8. "IM_CH72,Interrupt mask bit for channel 72" "0: Interupt for CH[72] is disabled,1: Interupt for CH[72] is enabled" line.long 0x4 "WTISR,Watchdog Threshold Interrupt Status Register" bitfld.long 0x4 7. "WDG3H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 3." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x4 6. "WDG3L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 3." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x4 5. "WDG2H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 2." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x4 4. "WDG2L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 2." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x4 3. "WDG1H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 1." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x4 2. "WDG1L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 1." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x4 1. "WDG0H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 0." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x4 0. "WDG0L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 0." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." line.long 0x8 "WTIMR,Watchdog Threshold Interrupt Mask Register" bitfld.long 0x8 7. "MSKWDG3H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG3H is disabled.,1: Inetrupt for WDG3H is enabled." bitfld.long 0x8 6. "MSKWDG3L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG3L is disabled.,1: Inetrupt for WDG3L is enabled." newline bitfld.long 0x8 5. "MSKWDG2H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG2H is disabled.,1: Inetrupt for WDG2H is enabled." bitfld.long 0x8 4. "MSKWDG2L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG2L is disabled.,1: Inetrupt for WDG2L is enabled." newline bitfld.long 0x8 3. "MSKWDG1H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG1H is disabled.,1: Inetrupt for WDG1H is enabled." bitfld.long 0x8 2. "MSKWDG1L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG1L is disabled.,1: Inetrupt for WDG1L is enabled." newline bitfld.long 0x8 1. "MSKWDG0H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG0H is disabled.,1: Inetrupt for WDG0H is enabled." bitfld.long 0x8 0. "MSKWDG0L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG0L is disabled.,1: Inetrupt for WDG0L is enabled." line.long 0xC "WLTCR,Watchdog Level Trigger Configuration Register" bitfld.long 0xC 3. "LTMW3,LTMW3" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0xC 2. "LTMW2,LTMW2" "0: Level Trigger Mode,1: Hysteresis Mode" newline bitfld.long 0xC 1. "LTMW1,LTMW1" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0xC 0. "LTMW0,LTMW0" "0: Level Trigger Mode,1: Hysteresis Mode" group.long 0x40++0x3 line.long 0x0 "DMAE,DMA Enable Register" bitfld.long 0x0 1. "DCLR,DMA clear sequence enable" "0: DMA request cleared by Acknowledge from DMA..,1: DMA request cleared on read of data registers" bitfld.long 0x0 0. "DMAEN,DMA global enable" "0: DMA feature disabled,1: DMA feature enabled" group.long 0x4C++0x3 line.long 0x0 "ICDSR2,Internal Channel DMA Select Register 2" bitfld.long 0x0 15. "DS_CH79,DS_CH79" "0: CH[79] is disabled to transfer data in DMA mode.,1: CH[79] is enabled to transfer data in DMA mode." bitfld.long 0x0 14. "DS_CH78,DS_CH78" "0: CH[78] is disabled to transfer data in DMA mode.,1: CH[78] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 13. "DS_CH77,DS_CH77" "0: CH[77] is disabled to transfer data in DMA mode.,1: CH[77] is enabled to transfer data in DMA mode." bitfld.long 0x0 12. "DS_CH76,DS_CH76" "0: CH[76] is disabled to transfer data in DMA mode.,1: CH[76] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 11. "DS_CH75,DS_CH75" "0: CH[75] is disabled to transfer data in DMA mode.,1: CH[75] is enabled to transfer data in DMA mode." bitfld.long 0x0 10. "DS_CH74,DS_CH74" "0: CH[74] is disabled to transfer data in DMA mode.,1: CH[74] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 9. "DS_CH73,DS_CH73" "0: CH[73] is disabled to transfer data in DMA mode.,1: CH[73] is enabled to transfer data in DMA mode." bitfld.long 0x0 8. "DS_CH72,DS_CH72" "0: CH[72] is disabled to transfer data in DMA mode.,1: CH[72] is enabled to transfer data in DMA mode." group.long 0x60++0xF line.long 0x0 "WTHRHLR0,Watchdog Threshold Register 0" hexmask.long.word 0x0 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x0 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x4 "WTHRHLR1,Watchdog Threshold Register 1" hexmask.long.word 0x4 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x4 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x8 "WTHRHLR2,Watchdog Threshold Register 2" hexmask.long.word 0x8 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x8 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0xC "WTHRHLR3,Watchdog Threshold Register 3" hexmask.long.word 0xC 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0xC 0.--11. 1. "THRL,Low threshold value for channel x" group.long 0x94++0xF line.long 0x0 "CTR0,Conversion Timing Register 0" bitfld.long 0x0 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x0 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x4 "CTR1,Conversion Timing Register 1" bitfld.long 0x4 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x4 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x4 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x8 "CTR2,Conversion Timing Register 2" bitfld.long 0x8 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x8 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x8 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0xC "CTR3,Conversion Timing Register 3" bitfld.long 0xC 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0xC 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0xC 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." group.long 0xAC++0x3 line.long 0x0 "ICNCMR2,Internal Channel Normal Conversion Mask Register 2" bitfld.long 0x0 15. "NCE_CH79,NCE_CH79" "0: Normal conversion is disabled for CH[79].,1: Normal conversion is enabled for CH[79]." bitfld.long 0x0 14. "NCE_CH78,NCE_CH78" "0: Normal conversion is disabled for CH[78].,1: Normal conversion is enabled for CH[78]." newline bitfld.long 0x0 13. "NCE_CH77,NCE_CH77" "0: Normal conversion is disabled for CH[77].,1: Normal conversion is enabled for CH[77]." bitfld.long 0x0 12. "NCE_CH76,NCE_CH76" "0: Normal conversion is disabled for CH[76].,1: Normal conversion is enabled for CH[76]." newline bitfld.long 0x0 11. "NCE_CH75,NCE_CH75" "0: Normal conversion is disabled for CH[75].,1: Normal conversion is enabled for CH[75]." bitfld.long 0x0 10. "NCE_CH74,NCE_CH74" "0: Normal conversion is disabled for CH[74].,1: Normal conversion is enabled for CH[74]." newline bitfld.long 0x0 9. "NCE_CH73,NCE_CH73" "0: Normal conversion is disabled for CH[73].,1: Normal conversion is enabled for CH[73]." bitfld.long 0x0 8. "NCE_CH72,NCE_CH72" "0: Normal conversion is disabled for CH[72].,1: Normal conversion is enabled for CH[72]." group.long 0xBC++0x3 line.long 0x0 "ICJCMR2,Internal Channel Injected Conversion Mask Register 2" bitfld.long 0x0 15. "JCE_CH79,JCE_CH79" "0: Injected conversion is disabled for CH[79].,1: Injected conversion is enabled for CH[79]." bitfld.long 0x0 14. "JCE_CH78,JCE_CH78" "0: Injected conversion is disabled for CH[78].,1: Injected conversion is enabled for CH[78]." newline bitfld.long 0x0 13. "JCE_CH77,JCE_CH77" "0: Injected conversion is disabled for CH[77].,1: Injected conversion is enabled for CH[77]." bitfld.long 0x0 12. "JCE_CH76,JCE_CH76" "0: Injected conversion is disabled for CH[76].,1: Injected conversion is enabled for CH[76]." newline bitfld.long 0x0 11. "JCE_CH75,JCE_CH75" "0: Injected conversion is disabled for CH[75].,1: Injected conversion is enabled for CH[75]." bitfld.long 0x0 10. "JCE_CH74,JCE_CH74" "0: Injected conversion is disabled for CH[74].,1: Injected conversion is enabled for CH[74]." newline bitfld.long 0x0 9. "JCE_CH73,JCE_CH73" "0: Injected conversion is disabled for CH[73].,1: Injected conversion is enabled for CH[73]." bitfld.long 0x0 8. "JCE_CH72,JCE_CH72" "0: Injected conversion is disabled for CH[72].,1: Injected conversion is enabled for CH[72]." group.long 0xC8++0x3 line.long 0x0 "PDEDR,Power Down Exit Delay Register" hexmask.long.byte 0x0 0.--7. 1. "PDED,Defines the delay between the power-down bit reset and the starting of conversion." group.long 0x220++0x1F line.long 0x0 "ICDR72,Internal Channel Data Register 72" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4 "ICDR73,Internal Channel Data Register 73" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x8 "ICDR74,Internal Channel Data Register 74" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x8 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xC "ICDR75,Internal Channel Data Register 75" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xC 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x10 "ICDR76,Internal Channel Data Register 76" bitfld.long 0x10 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x10 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x10 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x10 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x10 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x10 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x10 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x14 "ICDR77,Internal Channel Data Register 77" bitfld.long 0x14 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x14 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x14 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x14 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x14 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x14 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x14 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x18 "ICDR78,Internal Channel Data Register 78" bitfld.long 0x18 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x18 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x18 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x18 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x18 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x18 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x18 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x1C "ICDR79,Internal Channel Data Register 79" bitfld.long 0x1C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x1C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x1C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x1C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x1C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x1C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x1C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" group.long 0x2D4++0x3 line.long 0x0 "ICWSELR9,Internal Channel Watchdog Select Register 9" bitfld.long 0x0 28.--29. "WSEL_CH79,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH78,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH77,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH76,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 12.--13. "WSEL_CH75,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 8.--9. "WSEL_CH74,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 4.--5. "WSEL_CH73,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 0.--1. "WSEL_CH72,0000 THRHLR0 register is selected" "0,1,2,3" group.long 0x2E8++0x3 line.long 0x0 "ICWENR2,Internal Channel Watchdog Enable Register 2" bitfld.long 0x0 15. "WEN_CH79,WEN_CH79" "0: Watchdog feature is disabled for CH[79],1: Watchdog feature is enabled fir CH[79]" bitfld.long 0x0 14. "WEN_CH78,WEN_CH78" "0: Watchdog feature is disabled for CH[78],1: Watchdog feature is enabled fir CH[78]" newline bitfld.long 0x0 13. "WEN_CH77,WEN_CH77" "0: Watchdog feature is disabled for CH[77],1: Watchdog feature is enabled fir CH[77]" bitfld.long 0x0 12. "WEN_CH76,WEN_CH76" "0: Watchdog feature is disabled for CH[76],1: Watchdog feature is enabled fir CH[76]" newline bitfld.long 0x0 11. "WEN_CH75,WEN_CH75" "0: Watchdog feature is disabled for CH[75],1: Watchdog feature is enabled fir CH[75]" bitfld.long 0x0 10. "WEN_CH74,WEN_CH74" "0: Watchdog feature is disabled for CH[74],1: Watchdog feature is enabled fir CH[74]" newline bitfld.long 0x0 9. "WEN_CH73,WEN_CH73" "0: Watchdog feature is disabled for CH[73],1: Watchdog feature is enabled fir CH[73]" bitfld.long 0x0 8. "WEN_CH72,WEN_CH72" "0: Watchdog feature is disabled for CH[72],1: Watchdog feature is enabled fir CH[72]" group.long 0x2F8++0x3 line.long 0x0 "ICAWORR2,Internal Channel Analog Watchdog Out of Range Register 2" bitfld.long 0x0 15. "AWOR_CH79,Analog watchdog out of range status for channel 79 provided corresponding WEN_CH79 bit is set." "0: CH[79] converted data is not out of range..,1: CH[79] converted data is out of range determined.." bitfld.long 0x0 14. "AWOR_CH78,Analog watchdog out of range status for channel 78 provided corresponding WEN_CH78 bit is set." "0: CH[78] converted data is not out of range..,1: CH[78] converted data is out of range determined.." newline bitfld.long 0x0 13. "AWOR_CH77,Analog watchdog out of range status for channel 77 provided corresponding WEN_CH77 bit is set." "0: CH[77] converted data is not out of range..,1: CH[77] converted data is out of range determined.." bitfld.long 0x0 12. "AWOR_CH76,Analog watchdog out of range status for channel 76 provided corresponding WEN_CH76 bit is set." "0: CH[76] converted data is not out of range..,1: CH[76] converted data is out of range determined.." newline bitfld.long 0x0 11. "AWOR_CH75,Analog watchdog out of range status for channel 75 provided corresponding WEN_CH75 bit is set." "0: CH[75] converted data is not out of range..,1: CH[75] converted data is out of range determined.." bitfld.long 0x0 10. "AWOR_CH74,Analog watchdog out of range status for channel 74 provided corresponding WEN_CH74 bit is set." "0: CH[74] converted data is not out of range..,1: CH[74] converted data is out of range determined.." newline bitfld.long 0x0 9. "AWOR_CH73,Analog watchdog out of range status for channel 73 provided corresponding WEN_CH73 bit is set." "0: CH[73] converted data is not out of range..,1: CH[73] converted data is out of range determined.." bitfld.long 0x0 8. "AWOR_CH72,Analog watchdog out of range status for channel 72 provided corresponding WEN_CH72 bit is set." "0: CH[72] converted data is not out of range..,1: CH[72] converted data is out of range determined.." group.long 0x400++0x13 line.long 0x0 "TCIPR,Test Channel Interrupt Pending Register" bitfld.long 0x0 31. "EOC_CH127,End of conversion interrupt pending bit for channel 127" "0: End of conversion for CH[127] has not occurred.,1: End of conversion for CH[127] has occurred" bitfld.long 0x0 30. "EOC_CH126,End of conversion interrupt pending bit for channel 126" "0: End of conversion for CH[126] has not occurred.,1: End of conversion for CH[126] has occurred" newline bitfld.long 0x0 29. "EOC_CH125,End of conversion interrupt pending bit for channel 125" "0: End of conversion for CH[125] has not occurred.,1: End of conversion for CH[125] has occurred" bitfld.long 0x0 28. "EOC_CH124,End of conversion interrupt pending bit for channel 124" "0: End of conversion for CH[124] has not occurred.,1: End of conversion for CH[124] has occurred" line.long 0x4 "TCIMR,Test Channel Interrupt Mask Register" bitfld.long 0x4 31. "IM_CH127,IM_CH127" "0: Interrupt for CH[127] is disabled.,1: Interrupt for CH[127] is enabled." bitfld.long 0x4 30. "IM_CH126,IM_CH126" "0: Interrupt for CH[126] is disabled.,1: Interrupt for CH[126] is enabled." newline bitfld.long 0x4 29. "IM_CH125,IM_CH125" "0: Interrupt for CH[125] is disabled.,1: Interrupt for CH[125] is enabled." bitfld.long 0x4 28. "IM_CH124,IM_CH124" "0: Interrupt for CH[124] is disabled.,1: Interrupt for CH[124] is enabled." line.long 0x8 "TCDSR,Test Channel DMA Select Register" bitfld.long 0x8 31. "DS_CH127,DS_CH127" "0: CH[127] is disabled to transfer data in DMA mode.,1: CH[127] is enabled to transfer data in DMA mode." bitfld.long 0x8 30. "DS_CH126,DS_CH126" "0: CH[126] is disabled to transfer data in DMA mode.,1: CH[126] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 29. "DS_CH125,DS_CH125" "0: CH[125] is disabled to transfer data in DMA mode.,1: CH[125] is enabled to transfer data in DMA mode." bitfld.long 0x8 28. "DS_CH124,DS_CH124" "0: CH[124] is disabled to transfer data in DMA mode.,1: CH[124] is enabled to transfer data in DMA mode." line.long 0xC "TCNCMR,Test Channel Normal Conversion Mask Register" bitfld.long 0xC 31. "NCE_CH127,NCE_CH127" "0: Normal conversion is disabled for CH[127].,1: Normal conversion is enabled for CH[127]." bitfld.long 0xC 30. "NCE_CH126,NCE_CH126" "0: Normal conversion is disabled for CH[126].,1: Normal conversion is enabled for CH[126]." newline bitfld.long 0xC 29. "NCE_CH125,NCE_CH125" "0: Normal conversion is disabled for CH[125].,1: Normal conversion is enabled for CH[125]." bitfld.long 0xC 28. "NCE_CH124,NCE_CH124" "0: Normal conversion is disabled for CH[124].,1: Normal conversion is enabled for CH[124]." line.long 0x10 "TCJCMR,Test Channel Injected Conversion Mask Register" bitfld.long 0x10 31. "JCE_CH127,JCE_CH127" "0: Injected conversion is disabled for CH[127].,1: Injected conversion is enabled for CH[127]." bitfld.long 0x10 30. "JCE_CH126,JCE_CH126" "0: Injected conversion is disabled for CH[126].,1: Injected conversion is enabled for CH[126]." newline bitfld.long 0x10 29. "JCE_CH125,JCE_CH125" "0: Injected conversion is disabled for CH[125].,1: Injected conversion is enabled for CH[125]." bitfld.long 0x10 28. "JCE_CH124,JCE_CH124" "0: Injected conversion is disabled for CH[124].,1: Injected conversion is enabled for CH[124]." group.long 0x420++0xB line.long 0x0 "TCWSELR3,Test Channel Watchdog Select Register 3" bitfld.long 0x0 28.--29. "WSEL_CH127,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH126,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH125,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH124,0000 THRHLR0 register is selected" "0,1,2,3" line.long 0x4 "TCWENR,Test Channel Watchdog Enable Register" bitfld.long 0x4 31. "WEN_CH127,WEN_CH127" "0: Watchdog feature is disabled for CH[127].,1: Watchdog feature is enabled for CH[127]." bitfld.long 0x4 30. "WEN_CH126,WEN_CH126" "0: Watchdog feature is disabled for CH[126].,1: Watchdog feature is enabled for CH[126]." newline bitfld.long 0x4 29. "WEN_CH125,WEN_CH125" "0: Watchdog feature is disabled for CH[125].,1: Watchdog feature is enabled for CH[125]." bitfld.long 0x4 28. "WEN_CH124,WEN_CH124" "0: Watchdog feature is disabled for CH[124].,1: Watchdog feature is enabled for CH[124]." line.long 0x8 "TCAWORR,Test Channel Analog Watchdog Out of Range Register" bitfld.long 0x8 31. "AWOR_CH127,Analog watchdog out of range status for channel 127 provided corresponding WEN_CH127 bit is set." "0: CH[127] converted data is not out of range..,1: CH[127] converted data is out of range.." bitfld.long 0x8 30. "AWOR_CH126,Analog watchdog out of range status for channel 126 provided corresponding WEN_CH126 bit is set." "0: CH[126] converted data is not out of range..,1: CH[126] converted data is out of range.." newline bitfld.long 0x8 29. "AWOR_CH125,Analog watchdog out of range status for channel 125 provided corresponding WEN_CH125 bit is set." "0: CH[125] converted data is not out of range..,1: CH[125] converted data is out of range.." bitfld.long 0x8 28. "AWOR_CH124,Analog watchdog out of range status for channel 124 provided corresponding WEN_CH124 bit is set." "0: CH[124] converted data is not out of range..,1: CH[124] converted data is out of range.." group.long 0x44C++0x3 line.long 0x0 "TCCAPR7,Test Channel Connection with Analog Pin Register 7" bitfld.long 0x0 31. "ESIC_TCH31,Enable short with internal channel for test channel 31" "0: Test channel 31 cannot be shorted with internal..,1: Test channel 31 can be shorted with internal.." hexmask.long.byte 0x0 24.--30. 1. "ICSEL_TCH31,Internal channel selection for short with test channel 31" newline bitfld.long 0x0 23. "ESIC_TCH30,Enable short with internal channel for test channel 30" "0: Test channel 30 cannot be shorted with internal..,1: Test channel 30 can be shorted with internal.." hexmask.long.byte 0x0 16.--22. 1. "ICSEL_TCH30,Internal channel selection for short with test channel 30" newline bitfld.long 0x0 15. "ESIC_TCH29,Enable short with internal channel for test channel 29" "0: Test channel 29 cannot be shorted with internal..,1: Test channel 29 can be shorted with internal.." hexmask.long.byte 0x0 8.--14. 1. "ICSEL_TCH29,Internal channel selection for short with test channel 29" newline bitfld.long 0x0 7. "ESIC_TCH28,Enable short with internal channel for test channel 28" "0: Test channel 28 cannot be shorted with internal..,1: Test channel 28 can be shorted with internal.." hexmask.long.byte 0x0 0.--6. 1. "ICSEL_TCH28,Internal channel selection for short with test channel 28" group.long 0x4C0++0xF line.long 0x0 "TCDR124,Test Channel Data Register 124" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x4 "TCDR125,Test Channel Data Register 125" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x8 "TCDR126,Test Channel Data Register 126" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xC "TCDR127,Test Channel Data Register 127" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." tree.end tree "SAR_ADC_12BIT_10" base ad:0x702B4000 group.long 0x0++0x3 line.long 0x0 "MCR,Main Configuration Register" bitfld.long 0x0 31. "OWREN,This bit enables or disables the functionality to overwrite unread converted data in ICDR TCDR ECDR registers." "0: Prevents overwrite of unread converted data new..,1: Enables converted data to be overwritten by a.." bitfld.long 0x0 30. "WLSIDE,Write left/right-aligned" "0: The conversion data in ICDR TCDR ECDR registers..,1: Conversion data is left-aligned (from 15 to (15.." newline bitfld.long 0x0 29. "MODE,One Shot/Scan" "0: One Shot Mode: Configures the normal conversion..,1: Scan Mode: Configures continuous chain.." bitfld.long 0x0 28. "XSTRTEN,This bit enables or disables the external start signal to initial a normal conversion. This can be used to synchronize multiple SARADCs concurrently." "0: External start signal is disabled,1: External start signal high level will start a.." newline bitfld.long 0x0 27. "NSTART,Setting this bit starts the chain or scan conversion. Resetting this bit during scan mode causes the current chain conversion to finish then stops the operation." "0: Cause the current chain conversion to finish and..,1: Starts the chain or scan conversion" bitfld.long 0x0 26. "NTRGEN,NTRGEN" "0: Normal trigger disabled to start a normal..,1: Normal trigger enabled to start a normal.." newline bitfld.long 0x0 24.--25. "NEDGESEL,NEDGESEL" "0: Falling edge of normal trigger is selected,1: Rising edge of normal trigger is selected,2: Both rising and falling edges of normal trigger..,3: Both rising and falling edges of normal trigger.." bitfld.long 0x0 23. "JSTART,Setting this bit will start the configured injected analog channels to be converted by software. Resetting this bit has no effect as the injected chain conversion cannot be interrupted." "0: Writting '0' has not effect,1: Starts the injected chain conversion" newline bitfld.long 0x0 22. "JTRGEN,JTRGEN" "0: Injection trigger disabled for channel injection..,1: Injection trigger enabled for channel injection" bitfld.long 0x0 20.--21. "JEDGESEL,JEDGESEL" "0: Falling edge of injection trigger is selected,1: Rising edge of injection trigger is selected,?,3: Both rising and falling edges of injection.." newline bitfld.long 0x0 19. "JTRGSEQ,JTRGSEQ" "0: Injection trigger sequence mode is disabled,1: Injection trigger sequence mode is enabled" bitfld.long 0x0 17. "CTUEN,Can be set or cleared anytime with some restriction mentioned in CTU trigger/control mode section." "0: The cross triggering unit is disabled and the..,1: The cross triggering unit is enabled and the.." newline bitfld.long 0x0 16. "CTU_MODE,This bit is present only if generic parameter CTSEN = 2 otherwise this bit is a reserved bit and always read as 0. This should be set only when ADC Digital is in powerdown mode." "0: CTU control mode is selected,1: CTU trigger mode is selected" bitfld.long 0x0 15. "WTRIGOUT,This control bit enables the Trigger on every threshold crossover event (crossing of Lower/Upper thresholds) of each WDG monitor to external trigger port (up to 16 ports for up to 16 WDGs)." "0: Trigger outputs disabled,1: Trigger ouputs enabled" newline bitfld.long 0x0 7. "ABORTCHAIN,When this bit is set the ongoing Chain Conversion is aborted. This bit is reset by hardware as soon as a new conversion is requested." "0: Conversion is not affected,1: Aborts the ongoing chain conversion" bitfld.long 0x0 6. "ABORT,When this bit is set the ongoing conversion is aborted and a new conversion is invoked. This bit is reset by hardware as soon as a new conversion is invoked." "0: Conversion is not affected,1: Aborts the ongoing conversion" newline bitfld.long 0x0 4. "FRZ,This bit enables to stop the SARADC conversions at the end of current channel conversion when SoC enters debug mode." "0: Conversions are not stopped,1: When SoC enters debug mode further conversions.." bitfld.long 0x0 2. "FCE,This bit enables the fast comparison mode for upcoming channel conversions." "0: Fast comparision mode disabled,1: Fast comparision mode enabled" newline bitfld.long 0x0 1. "EDCSELF,This bit selects the format for 3-bit output port ipp_decode_extch used as select line for external decode channel 8:1 muxes. The last three bits of external channel number are passed as is (if value 0) or converted to gray code (if value 1) and.." "0: Binary format,1: Gray code format" bitfld.long 0x0 0. "PWDN,When this bit is set the analog module is requested to enter Power Down mode." "0: SARADC is in normal mode,1: SARADC has been requested to power down" rgroup.long 0x4++0x3 line.long 0x0 "MSR,Main Status Register" bitfld.long 0x0 27. "NSTART,This status bit is used to signal that a normal conversion is ongoing." "0: Normal conversion is not taking place,1: Normal conversion is ongoing or the normal.." bitfld.long 0x0 23. "JSTART,This status bit is used to signal that an injected conversion is ongoing." "0: Injected conversion is not taking place,1: Injected conversion is ongoing" newline bitfld.long 0x0 18. "JABORTCHAIN,This status bit is used to signal that an Injected conversion chain has been aborted. This bit is reset when a new conversion starts." "0: Last injected conversion chain has not been..,1: Last injected conversion chain has been aborted" bitfld.long 0x0 16. "CTUSTART,This status bit is used to signal that a CTU conversion is ongoing. This bit is set when a CTU trigger pulse is received and the CTU conversion starts. When CTU trigger mode is enabled this bit is automatically reset when the conversion is.." "0: CTU triggered injected conversion is not taking..,1: CTU triggered injected conversion is ongoing" newline hexmask.long.byte 0x0 8.--15. 1. "CHADDR,Channel under measure address" bitfld.long 0x0 0.--2. "ADCSTATUS,The value of this parameter depends on ADC status. While requesting an external channel conversion SARADC digital interface needs to wait for a fixed time determined by DSD bitfield of DSDR before proceeding to actual sampling phase." "0: IDLE,1: Power-down,2: Wait state,?,4: Sample,?,6: Conversion,?" group.long 0x10++0x3 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CTUTRGERR,This Error Flag indicates that the next CTU trigger has been discarded as it overlapped during execution of current CTU conversion. This indicated that CTU sampling duration is less than programmed conversion time of ADC." "0: No CTU trigger overlap error condition since..,1: CTU trigger overlap error has occurred." bitfld.long 0x0 4. "EOCTU,This bit indicates the end of conversion for a CTU injected channel." "0: End of conversion of CTU triggered channel has..,1: End of conversion of CTU triggered channel has.." newline bitfld.long 0x0 3. "JEOC,This bit indicates the end of conversion for an injected channel." "0: End of conversion of injected channel has not..,1: End of conversion of injected channel has.." bitfld.long 0x0 2. "JECH,This bit indicates the end of conversion for an injected chain." "0: End of conversion of injected chain has not..,1: End of conversion of injected chain has occurred.." newline bitfld.long 0x0 1. "NEOC,This bit indicates the end of conversion for a normal channel." "0: End of conversion of normal channel has not..,1: End of conversion of normal channel has occurred.." bitfld.long 0x0 0. "NECH,This bit indicates the end of conversion for an normal chain." "0: End of conversion of normal chain has not..,1: End of conversion of normal chain has occurred.." group.long 0x1C++0x7 line.long 0x0 "ICIPR2,Internal Channel Interrupt Pending Register 2" bitfld.long 0x0 23. "EOC_CH87,End of conversion interrupt pending bit for channel 87" "0: End of conversion for CH[87] has not occured,1: End of conversion for CH[87] has occured" bitfld.long 0x0 22. "EOC_CH86,End of conversion interrupt pending bit for channel 86" "0: End of conversion for CH[86] has not occured,1: End of conversion for CH[86] has occured" newline bitfld.long 0x0 21. "EOC_CH85,End of conversion interrupt pending bit for channel 85" "0: End of conversion for CH[85] has not occured,1: End of conversion for CH[85] has occured" bitfld.long 0x0 20. "EOC_CH84,End of conversion interrupt pending bit for channel 84" "0: End of conversion for CH[84] has not occured,1: End of conversion for CH[84] has occured" newline bitfld.long 0x0 19. "EOC_CH83,End of conversion interrupt pending bit for channel 83" "0: End of conversion for CH[83] has not occured,1: End of conversion for CH[83] has occured" bitfld.long 0x0 18. "EOC_CH82,End of conversion interrupt pending bit for channel 82" "0: End of conversion for CH[82] has not occured,1: End of conversion for CH[82] has occured" newline bitfld.long 0x0 17. "EOC_CH81,End of conversion interrupt pending bit for channel 81" "0: End of conversion for CH[81] has not occured,1: End of conversion for CH[81] has occured" bitfld.long 0x0 16. "EOC_CH80,End of conversion interrupt pending bit for channel 80" "0: End of conversion for CH[80] has not occured,1: End of conversion for CH[80] has occured" line.long 0x4 "IMR,Interrupt Mask Register" bitfld.long 0x4 5. "MSKCTUTRGERR,Mask bit for CTU Trigger" "0: CTUTRGERR interrupt is disabled,1: CTUTRGERR interrupt is enabled" bitfld.long 0x4 4. "MSKEOCTU,Mask bit for EOCTU" "0: EOCTU interrupt is disabled,1: EOCTU interrupt is enabled" newline bitfld.long 0x4 3. "MSKJEOC,Mask bit for JEOC" "0: JEOC interrupt is disabled,1: JEOC interrupt is enabled" bitfld.long 0x4 2. "MSKJECH,Mask bit for JECH" "0: JECH interrupt is disabled,1: JECH interrupt is enabled" newline bitfld.long 0x4 1. "MSKNEOC,Mask bit for NEOC" "0: NEOC interrupt is disabled,1: NEOC interrupt is enabled" bitfld.long 0x4 0. "MSKNECH,Mask bit for NECH" "0: NECH interrupt is disabled,1: NECH interrupt is enabled" group.long 0x2C++0xF line.long 0x0 "ICIMR2,Internal Channel Interrupt Mask Register 2" bitfld.long 0x0 23. "IM_CH87,Interrupt mask bit for channel 87" "0: Interupt for CH[87] is disabled,1: Interupt for CH[87] is enabled" bitfld.long 0x0 22. "IM_CH86,Interrupt mask bit for channel 86" "0: Interupt for CH[86] is disabled,1: Interupt for CH[86] is enabled" newline bitfld.long 0x0 21. "IM_CH85,Interrupt mask bit for channel 85" "0: Interupt for CH[85] is disabled,1: Interupt for CH[85] is enabled" bitfld.long 0x0 20. "IM_CH84,Interrupt mask bit for channel 84" "0: Interupt for CH[84] is disabled,1: Interupt for CH[84] is enabled" newline bitfld.long 0x0 19. "IM_CH83,Interrupt mask bit for channel 83" "0: Interupt for CH[83] is disabled,1: Interupt for CH[83] is enabled" bitfld.long 0x0 18. "IM_CH82,Interrupt mask bit for channel 82" "0: Interupt for CH[82] is disabled,1: Interupt for CH[82] is enabled" newline bitfld.long 0x0 17. "IM_CH81,Interrupt mask bit for channel 81" "0: Interupt for CH[81] is disabled,1: Interupt for CH[81] is enabled" bitfld.long 0x0 16. "IM_CH80,Interrupt mask bit for channel 80" "0: Interupt for CH[80] is disabled,1: Interupt for CH[80] is enabled" line.long 0x4 "WTISR,Watchdog Threshold Interrupt Status Register" bitfld.long 0x4 7. "WDG3H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 3." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x4 6. "WDG3L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 3." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x4 5. "WDG2H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 2." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x4 4. "WDG2L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 2." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x4 3. "WDG1H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 1." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x4 2. "WDG1L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 1." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x4 1. "WDG0H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 0." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x4 0. "WDG0L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 0." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." line.long 0x8 "WTIMR,Watchdog Threshold Interrupt Mask Register" bitfld.long 0x8 7. "MSKWDG3H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG3H is disabled.,1: Inetrupt for WDG3H is enabled." bitfld.long 0x8 6. "MSKWDG3L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG3L is disabled.,1: Inetrupt for WDG3L is enabled." newline bitfld.long 0x8 5. "MSKWDG2H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG2H is disabled.,1: Inetrupt for WDG2H is enabled." bitfld.long 0x8 4. "MSKWDG2L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG2L is disabled.,1: Inetrupt for WDG2L is enabled." newline bitfld.long 0x8 3. "MSKWDG1H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG1H is disabled.,1: Inetrupt for WDG1H is enabled." bitfld.long 0x8 2. "MSKWDG1L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG1L is disabled.,1: Inetrupt for WDG1L is enabled." newline bitfld.long 0x8 1. "MSKWDG0H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG0H is disabled.,1: Inetrupt for WDG0H is enabled." bitfld.long 0x8 0. "MSKWDG0L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG0L is disabled.,1: Inetrupt for WDG0L is enabled." line.long 0xC "WLTCR,Watchdog Level Trigger Configuration Register" bitfld.long 0xC 3. "LTMW3,LTMW3" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0xC 2. "LTMW2,LTMW2" "0: Level Trigger Mode,1: Hysteresis Mode" newline bitfld.long 0xC 1. "LTMW1,LTMW1" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0xC 0. "LTMW0,LTMW0" "0: Level Trigger Mode,1: Hysteresis Mode" group.long 0x40++0x3 line.long 0x0 "DMAE,DMA Enable Register" bitfld.long 0x0 1. "DCLR,DMA clear sequence enable" "0: DMA request cleared by Acknowledge from DMA..,1: DMA request cleared on read of data registers" bitfld.long 0x0 0. "DMAEN,DMA global enable" "0: DMA feature disabled,1: DMA feature enabled" group.long 0x4C++0x3 line.long 0x0 "ICDSR2,Internal Channel DMA Select Register 2" bitfld.long 0x0 23. "DS_CH87,DS_CH87" "0: CH[87] is disabled to transfer data in DMA mode.,1: CH[87] is enabled to transfer data in DMA mode." bitfld.long 0x0 22. "DS_CH86,DS_CH86" "0: CH[86] is disabled to transfer data in DMA mode.,1: CH[86] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 21. "DS_CH85,DS_CH85" "0: CH[85] is disabled to transfer data in DMA mode.,1: CH[85] is enabled to transfer data in DMA mode." bitfld.long 0x0 20. "DS_CH84,DS_CH84" "0: CH[84] is disabled to transfer data in DMA mode.,1: CH[84] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 19. "DS_CH83,DS_CH83" "0: CH[83] is disabled to transfer data in DMA mode.,1: CH[83] is enabled to transfer data in DMA mode." bitfld.long 0x0 18. "DS_CH82,DS_CH82" "0: CH[82] is disabled to transfer data in DMA mode.,1: CH[82] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 17. "DS_CH81,DS_CH81" "0: CH[81] is disabled to transfer data in DMA mode.,1: CH[81] is enabled to transfer data in DMA mode." bitfld.long 0x0 16. "DS_CH80,DS_CH80" "0: CH[80] is disabled to transfer data in DMA mode.,1: CH[80] is enabled to transfer data in DMA mode." group.long 0x60++0xF line.long 0x0 "WTHRHLR0,Watchdog Threshold Register 0" hexmask.long.word 0x0 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x0 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x4 "WTHRHLR1,Watchdog Threshold Register 1" hexmask.long.word 0x4 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x4 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x8 "WTHRHLR2,Watchdog Threshold Register 2" hexmask.long.word 0x8 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x8 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0xC "WTHRHLR3,Watchdog Threshold Register 3" hexmask.long.word 0xC 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0xC 0.--11. 1. "THRL,Low threshold value for channel x" group.long 0x94++0xF line.long 0x0 "CTR0,Conversion Timing Register 0" bitfld.long 0x0 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x0 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x4 "CTR1,Conversion Timing Register 1" bitfld.long 0x4 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x4 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x4 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x8 "CTR2,Conversion Timing Register 2" bitfld.long 0x8 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x8 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x8 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0xC "CTR3,Conversion Timing Register 3" bitfld.long 0xC 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0xC 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0xC 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." group.long 0xAC++0x3 line.long 0x0 "ICNCMR2,Internal Channel Normal Conversion Mask Register 2" bitfld.long 0x0 23. "NCE_CH87,NCE_CH87" "0: Normal conversion is disabled for CH[87].,1: Normal conversion is enabled for CH[87]." bitfld.long 0x0 22. "NCE_CH86,NCE_CH86" "0: Normal conversion is disabled for CH[86].,1: Normal conversion is enabled for CH[86]." newline bitfld.long 0x0 21. "NCE_CH85,NCE_CH85" "0: Normal conversion is disabled for CH[85].,1: Normal conversion is enabled for CH[85]." bitfld.long 0x0 20. "NCE_CH84,NCE_CH84" "0: Normal conversion is disabled for CH[84].,1: Normal conversion is enabled for CH[84]." newline bitfld.long 0x0 19. "NCE_CH83,NCE_CH83" "0: Normal conversion is disabled for CH[83].,1: Normal conversion is enabled for CH[83]." bitfld.long 0x0 18. "NCE_CH82,NCE_CH82" "0: Normal conversion is disabled for CH[82].,1: Normal conversion is enabled for CH[82]." newline bitfld.long 0x0 17. "NCE_CH81,NCE_CH81" "0: Normal conversion is disabled for CH[81].,1: Normal conversion is enabled for CH[81]." bitfld.long 0x0 16. "NCE_CH80,NCE_CH80" "0: Normal conversion is disabled for CH[80].,1: Normal conversion is enabled for CH[80]." group.long 0xBC++0x3 line.long 0x0 "ICJCMR2,Internal Channel Injected Conversion Mask Register 2" bitfld.long 0x0 23. "JCE_CH87,JCE_CH87" "0: Injected conversion is disabled for CH[87].,1: Injected conversion is enabled for CH[87]." bitfld.long 0x0 22. "JCE_CH86,JCE_CH86" "0: Injected conversion is disabled for CH[86].,1: Injected conversion is enabled for CH[86]." newline bitfld.long 0x0 21. "JCE_CH85,JCE_CH85" "0: Injected conversion is disabled for CH[85].,1: Injected conversion is enabled for CH[85]." bitfld.long 0x0 20. "JCE_CH84,JCE_CH84" "0: Injected conversion is disabled for CH[84].,1: Injected conversion is enabled for CH[84]." newline bitfld.long 0x0 19. "JCE_CH83,JCE_CH83" "0: Injected conversion is disabled for CH[83].,1: Injected conversion is enabled for CH[83]." bitfld.long 0x0 18. "JCE_CH82,JCE_CH82" "0: Injected conversion is disabled for CH[82].,1: Injected conversion is enabled for CH[82]." newline bitfld.long 0x0 17. "JCE_CH81,JCE_CH81" "0: Injected conversion is disabled for CH[81].,1: Injected conversion is enabled for CH[81]." bitfld.long 0x0 16. "JCE_CH80,JCE_CH80" "0: Injected conversion is disabled for CH[80].,1: Injected conversion is enabled for CH[80]." group.long 0xC8++0x3 line.long 0x0 "PDEDR,Power Down Exit Delay Register" hexmask.long.byte 0x0 0.--7. 1. "PDED,Defines the delay between the power-down bit reset and the starting of conversion." group.long 0x240++0x1F line.long 0x0 "ICDR80,Internal Channel Data Register 80" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4 "ICDR81,Internal Channel Data Register 81" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x8 "ICDR82,Internal Channel Data Register 82" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x8 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xC "ICDR83,Internal Channel Data Register 83" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xC 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x10 "ICDR84,Internal Channel Data Register 84" bitfld.long 0x10 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x10 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x10 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x10 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x10 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x10 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x10 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x14 "ICDR85,Internal Channel Data Register 85" bitfld.long 0x14 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x14 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x14 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x14 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x14 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x14 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x14 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x18 "ICDR86,Internal Channel Data Register 86" bitfld.long 0x18 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x18 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x18 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x18 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x18 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x18 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x18 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x1C "ICDR87,Internal Channel Data Register 87" bitfld.long 0x1C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x1C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x1C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x1C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x1C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x1C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x1C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" group.long 0x2D8++0x3 line.long 0x0 "ICWSELR10,Internal Channel Watchdog Select Register 10" bitfld.long 0x0 28.--29. "WSEL_CH87,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH86,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH85,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH84,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 12.--13. "WSEL_CH83,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 8.--9. "WSEL_CH82,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 4.--5. "WSEL_CH81,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 0.--1. "WSEL_CH80,0000 THRHLR0 register is selected" "0,1,2,3" group.long 0x2E8++0x3 line.long 0x0 "ICWENR2,Internal Channel Watchdog Enable Register 2" bitfld.long 0x0 23. "WEN_CH87,WEN_CH87" "0: Watchdog feature is disabled for CH[87],1: Watchdog feature is enabled fir CH[87]" bitfld.long 0x0 22. "WEN_CH86,WEN_CH86" "0: Watchdog feature is disabled for CH[86],1: Watchdog feature is enabled fir CH[86]" newline bitfld.long 0x0 21. "WEN_CH85,WEN_CH85" "0: Watchdog feature is disabled for CH[85],1: Watchdog feature is enabled fir CH[85]" bitfld.long 0x0 20. "WEN_CH84,WEN_CH84" "0: Watchdog feature is disabled for CH[84],1: Watchdog feature is enabled fir CH[84]" newline bitfld.long 0x0 19. "WEN_CH83,WEN_CH83" "0: Watchdog feature is disabled for CH[83],1: Watchdog feature is enabled fir CH[83]" bitfld.long 0x0 18. "WEN_CH82,WEN_CH82" "0: Watchdog feature is disabled for CH[82],1: Watchdog feature is enabled fir CH[82]" newline bitfld.long 0x0 17. "WEN_CH81,WEN_CH81" "0: Watchdog feature is disabled for CH[81],1: Watchdog feature is enabled fir CH[81]" bitfld.long 0x0 16. "WEN_CH80,WEN_CH80" "0: Watchdog feature is disabled for CH[80],1: Watchdog feature is enabled fir CH[80]" group.long 0x2F8++0x3 line.long 0x0 "ICAWORR2,Internal Channel Analog Watchdog Out of Range Register 2" bitfld.long 0x0 23. "AWOR_CH87,Analog watchdog out of range status for channel 87 provided corresponding WEN_CH87 bit is set." "0: CH[87] converted data is not out of range..,1: CH[87] converted data is out of range determined.." bitfld.long 0x0 22. "AWOR_CH86,Analog watchdog out of range status for channel 86 provided corresponding WEN_CH86 bit is set." "0: CH[86] converted data is not out of range..,1: CH[86] converted data is out of range determined.." newline bitfld.long 0x0 21. "AWOR_CH85,Analog watchdog out of range status for channel 85 provided corresponding WEN_CH85 bit is set." "0: CH[85] converted data is not out of range..,1: CH[85] converted data is out of range determined.." bitfld.long 0x0 20. "AWOR_CH84,Analog watchdog out of range status for channel 84 provided corresponding WEN_CH84 bit is set." "0: CH[84] converted data is not out of range..,1: CH[84] converted data is out of range determined.." newline bitfld.long 0x0 19. "AWOR_CH83,Analog watchdog out of range status for channel 83 provided corresponding WEN_CH83 bit is set." "0: CH[83] converted data is not out of range..,1: CH[83] converted data is out of range determined.." bitfld.long 0x0 18. "AWOR_CH82,Analog watchdog out of range status for channel 82 provided corresponding WEN_CH82 bit is set." "0: CH[82] converted data is not out of range..,1: CH[82] converted data is out of range determined.." newline bitfld.long 0x0 17. "AWOR_CH81,Analog watchdog out of range status for channel 81 provided corresponding WEN_CH81 bit is set." "0: CH[81] converted data is not out of range..,1: CH[81] converted data is out of range determined.." bitfld.long 0x0 16. "AWOR_CH80,Analog watchdog out of range status for channel 80 provided corresponding WEN_CH80 bit is set." "0: CH[80] converted data is not out of range..,1: CH[80] converted data is out of range determined.." group.long 0x400++0x13 line.long 0x0 "TCIPR,Test Channel Interrupt Pending Register" bitfld.long 0x0 31. "EOC_CH127,End of conversion interrupt pending bit for channel 127" "0: End of conversion for CH[127] has not occurred.,1: End of conversion for CH[127] has occurred" bitfld.long 0x0 30. "EOC_CH126,End of conversion interrupt pending bit for channel 126" "0: End of conversion for CH[126] has not occurred.,1: End of conversion for CH[126] has occurred" newline bitfld.long 0x0 29. "EOC_CH125,End of conversion interrupt pending bit for channel 125" "0: End of conversion for CH[125] has not occurred.,1: End of conversion for CH[125] has occurred" bitfld.long 0x0 28. "EOC_CH124,End of conversion interrupt pending bit for channel 124" "0: End of conversion for CH[124] has not occurred.,1: End of conversion for CH[124] has occurred" line.long 0x4 "TCIMR,Test Channel Interrupt Mask Register" bitfld.long 0x4 31. "IM_CH127,IM_CH127" "0: Interrupt for CH[127] is disabled.,1: Interrupt for CH[127] is enabled." bitfld.long 0x4 30. "IM_CH126,IM_CH126" "0: Interrupt for CH[126] is disabled.,1: Interrupt for CH[126] is enabled." newline bitfld.long 0x4 29. "IM_CH125,IM_CH125" "0: Interrupt for CH[125] is disabled.,1: Interrupt for CH[125] is enabled." bitfld.long 0x4 28. "IM_CH124,IM_CH124" "0: Interrupt for CH[124] is disabled.,1: Interrupt for CH[124] is enabled." line.long 0x8 "TCDSR,Test Channel DMA Select Register" bitfld.long 0x8 31. "DS_CH127,DS_CH127" "0: CH[127] is disabled to transfer data in DMA mode.,1: CH[127] is enabled to transfer data in DMA mode." bitfld.long 0x8 30. "DS_CH126,DS_CH126" "0: CH[126] is disabled to transfer data in DMA mode.,1: CH[126] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 29. "DS_CH125,DS_CH125" "0: CH[125] is disabled to transfer data in DMA mode.,1: CH[125] is enabled to transfer data in DMA mode." bitfld.long 0x8 28. "DS_CH124,DS_CH124" "0: CH[124] is disabled to transfer data in DMA mode.,1: CH[124] is enabled to transfer data in DMA mode." line.long 0xC "TCNCMR,Test Channel Normal Conversion Mask Register" bitfld.long 0xC 31. "NCE_CH127,NCE_CH127" "0: Normal conversion is disabled for CH[127].,1: Normal conversion is enabled for CH[127]." bitfld.long 0xC 30. "NCE_CH126,NCE_CH126" "0: Normal conversion is disabled for CH[126].,1: Normal conversion is enabled for CH[126]." newline bitfld.long 0xC 29. "NCE_CH125,NCE_CH125" "0: Normal conversion is disabled for CH[125].,1: Normal conversion is enabled for CH[125]." bitfld.long 0xC 28. "NCE_CH124,NCE_CH124" "0: Normal conversion is disabled for CH[124].,1: Normal conversion is enabled for CH[124]." line.long 0x10 "TCJCMR,Test Channel Injected Conversion Mask Register" bitfld.long 0x10 31. "JCE_CH127,JCE_CH127" "0: Injected conversion is disabled for CH[127].,1: Injected conversion is enabled for CH[127]." bitfld.long 0x10 30. "JCE_CH126,JCE_CH126" "0: Injected conversion is disabled for CH[126].,1: Injected conversion is enabled for CH[126]." newline bitfld.long 0x10 29. "JCE_CH125,JCE_CH125" "0: Injected conversion is disabled for CH[125].,1: Injected conversion is enabled for CH[125]." bitfld.long 0x10 28. "JCE_CH124,JCE_CH124" "0: Injected conversion is disabled for CH[124].,1: Injected conversion is enabled for CH[124]." group.long 0x420++0xB line.long 0x0 "TCWSELR3,Test Channel Watchdog Select Register 3" bitfld.long 0x0 28.--29. "WSEL_CH127,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 24.--25. "WSEL_CH126,0000 THRHLR0 register is selected" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WSEL_CH125,0000 THRHLR0 register is selected" "0,1,2,3" bitfld.long 0x0 16.--17. "WSEL_CH124,0000 THRHLR0 register is selected" "0,1,2,3" line.long 0x4 "TCWENR,Test Channel Watchdog Enable Register" bitfld.long 0x4 31. "WEN_CH127,WEN_CH127" "0: Watchdog feature is disabled for CH[127].,1: Watchdog feature is enabled for CH[127]." bitfld.long 0x4 30. "WEN_CH126,WEN_CH126" "0: Watchdog feature is disabled for CH[126].,1: Watchdog feature is enabled for CH[126]." newline bitfld.long 0x4 29. "WEN_CH125,WEN_CH125" "0: Watchdog feature is disabled for CH[125].,1: Watchdog feature is enabled for CH[125]." bitfld.long 0x4 28. "WEN_CH124,WEN_CH124" "0: Watchdog feature is disabled for CH[124].,1: Watchdog feature is enabled for CH[124]." line.long 0x8 "TCAWORR,Test Channel Analog Watchdog Out of Range Register" bitfld.long 0x8 31. "AWOR_CH127,Analog watchdog out of range status for channel 127 provided corresponding WEN_CH127 bit is set." "0: CH[127] converted data is not out of range..,1: CH[127] converted data is out of range.." bitfld.long 0x8 30. "AWOR_CH126,Analog watchdog out of range status for channel 126 provided corresponding WEN_CH126 bit is set." "0: CH[126] converted data is not out of range..,1: CH[126] converted data is out of range.." newline bitfld.long 0x8 29. "AWOR_CH125,Analog watchdog out of range status for channel 125 provided corresponding WEN_CH125 bit is set." "0: CH[125] converted data is not out of range..,1: CH[125] converted data is out of range.." bitfld.long 0x8 28. "AWOR_CH124,Analog watchdog out of range status for channel 124 provided corresponding WEN_CH124 bit is set." "0: CH[124] converted data is not out of range..,1: CH[124] converted data is out of range.." group.long 0x44C++0x3 line.long 0x0 "TCCAPR7,Test Channel Connection with Analog Pin Register 7" bitfld.long 0x0 31. "ESIC_TCH31,Enable short with internal channel for test channel 31" "0: Test channel 31 cannot be shorted with internal..,1: Test channel 31 can be shorted with internal.." hexmask.long.byte 0x0 24.--30. 1. "ICSEL_TCH31,Internal channel selection for short with test channel 31" newline bitfld.long 0x0 23. "ESIC_TCH30,Enable short with internal channel for test channel 30" "0: Test channel 30 cannot be shorted with internal..,1: Test channel 30 can be shorted with internal.." hexmask.long.byte 0x0 16.--22. 1. "ICSEL_TCH30,Internal channel selection for short with test channel 30" newline bitfld.long 0x0 15. "ESIC_TCH29,Enable short with internal channel for test channel 29" "0: Test channel 29 cannot be shorted with internal..,1: Test channel 29 can be shorted with internal.." hexmask.long.byte 0x0 8.--14. 1. "ICSEL_TCH29,Internal channel selection for short with test channel 29" newline bitfld.long 0x0 7. "ESIC_TCH28,Enable short with internal channel for test channel 28" "0: Test channel 28 cannot be shorted with internal..,1: Test channel 28 can be shorted with internal.." hexmask.long.byte 0x0 0.--6. 1. "ICSEL_TCH28,Internal channel selection for short with test channel 28" group.long 0x4C0++0xF line.long 0x0 "TCDR124,Test Channel Data Register 124" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x4 "TCDR125,Test Channel Data Register 125" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x8 "TCDR126,Test Channel Data Register 126" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xC "TCDR127,Test Channel Data Register 127" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." tree.end tree "SAR_ADC_12BIT_SV_0" base ad:0x70284000 group.long 0x0++0x3 line.long 0x0 "MCR,Main Configuration Register" bitfld.long 0x0 31. "OWREN,This bit enables or disables the functionality to overwrite unread converted data in ICDR TCDR ECDR registers." "0: Prevents overwrite of unread converted data new..,1: Enables converted data to be overwritten by a.." bitfld.long 0x0 30. "WLSIDE,Write left/right-aligned" "0: The conversion data in ICDR TCDR ECDR registers..,1: Conversion data is left-aligned (from 15 to (15.." newline bitfld.long 0x0 29. "MODE,One Shot/Scan" "0: One Shot Mode: Configures the normal conversion..,1: Scan Mode: Configures continuous chain.." bitfld.long 0x0 28. "XSTRTEN,This bit enables or disables the external start signal to initial a normal conversion. This can be used to synchronize multiple SARADCs concurrently." "0: External start signal is disabled,1: External start signal high level will start a.." newline bitfld.long 0x0 27. "NSTART,Setting this bit starts the chain or scan conversion. Resetting this bit during scan mode causes the current chain conversion to finish then stops the operation." "0: Cause the current chain conversion to finish and..,1: Starts the chain or scan conversion" bitfld.long 0x0 26. "NTRGEN,NTRGEN" "0: Normal trigger disabled to start a normal..,1: Normal trigger enabled to start a normal.." newline bitfld.long 0x0 24.--25. "NEDGESEL,NEDGESEL" "0: Falling edge of normal trigger is selected,1: Rising edge of normal trigger is selected,2: Both rising and falling edges of normal trigger..,3: Both rising and falling edges of normal trigger.." bitfld.long 0x0 23. "JSTART,Setting this bit will start the configured injected analog channels to be converted by software. Resetting this bit has no effect as the injected chain conversion cannot be interrupted." "0: Writting '0' has not effect,1: Starts the injected chain conversion" newline bitfld.long 0x0 22. "JTRGEN,JTRGEN" "0: Injection trigger disabled for channel injection..,1: Injection trigger enabled for channel injection" bitfld.long 0x0 20.--21. "JEDGESEL,JEDGESEL" "0: Falling edge of injection trigger is selected,1: Rising edge of injection trigger is selected,?,3: Both rising and falling edges of injection.." newline bitfld.long 0x0 19. "JTRGSEQ,JTRGSEQ" "0: Injection trigger sequence mode is disabled,1: Injection trigger sequence mode is enabled" bitfld.long 0x0 17. "CTUEN,Can be set or cleared anytime with some restriction mentioned in CTU trigger/control mode section." "0: The cross triggering unit is disabled and the..,1: The cross triggering unit is enabled and the.." newline bitfld.long 0x0 16. "CTU_MODE,This bit is present only if generic parameter CTSEN = 2 otherwise this bit is a reserved bit and always read as 0. This should be set only when ADC Digital is in powerdown mode." "0: CTU control mode is selected,1: CTU trigger mode is selected" bitfld.long 0x0 15. "WTRIGOUT,This control bit enables the Trigger on every threshold crossover event (crossing of Lower/Upper thresholds) of each WDG monitor to external trigger port (up to 16 ports for up to 16 WDGs)." "0: Trigger outputs disabled,1: Trigger ouputs enabled" newline bitfld.long 0x0 7. "ABORTCHAIN,When this bit is set the ongoing Chain Conversion is aborted. This bit is reset by hardware as soon as a new conversion is requested." "0: Conversion is not affected,1: Aborts the ongoing chain conversion" bitfld.long 0x0 6. "ABORT,When this bit is set the ongoing conversion is aborted and a new conversion is invoked. This bit is reset by hardware as soon as a new conversion is invoked." "0: Conversion is not affected,1: Aborts the ongoing conversion" newline bitfld.long 0x0 4. "FRZ,This bit enables to stop the SARADC conversions at the end of current channel conversion when SoC enters debug mode." "0: Conversions are not stopped,1: When SoC enters debug mode further conversions.." bitfld.long 0x0 2. "FCE,This bit enables the fast comparison mode for upcoming channel conversions." "0: Fast comparision mode disabled,1: Fast comparision mode enabled" newline bitfld.long 0x0 1. "EDCSELF,This bit selects the format for 3-bit output port ipp_decode_extch used as select line for external decode channel 8:1 muxes. The last three bits of external channel number are passed as is (if value 0) or converted to gray code (if value 1) and.." "0: Binary format,1: Gray code format" bitfld.long 0x0 0. "PWDN,When this bit is set the analog module is requested to enter Power Down mode." "0: SARADC is in normal mode,1: SARADC has been requested to power down" rgroup.long 0x4++0x3 line.long 0x0 "MSR,Main Status Register" bitfld.long 0x0 27. "NSTART,This status bit is used to signal that a normal conversion is ongoing." "0: Normal conversion is not taking place,1: Normal conversion is ongoing or the normal.." bitfld.long 0x0 23. "JSTART,This status bit is used to signal that an injected conversion is ongoing." "0: Injected conversion is not taking place,1: Injected conversion is ongoing" newline bitfld.long 0x0 18. "JABORTCHAIN,This status bit is used to signal that an Injected conversion chain has been aborted. This bit is reset when a new conversion starts." "0: Last injected conversion chain has not been..,1: Last injected conversion chain has been aborted" bitfld.long 0x0 16. "CTUSTART,This status bit is used to signal that a CTU conversion is ongoing. This bit is set when a CTU trigger pulse is received and the CTU conversion starts. When CTU trigger mode is enabled this bit is automatically reset when the conversion is.." "0: CTU triggered injected conversion is not taking..,1: CTU triggered injected conversion is ongoing" newline hexmask.long.byte 0x0 8.--15. 1. "CHADDR,Channel under measure address" bitfld.long 0x0 0.--2. "ADCSTATUS,The value of this parameter depends on ADC status. While requesting an external channel conversion SARADC digital interface needs to wait for a fixed time determined by DSD bitfield of DSDR before proceeding to actual sampling phase." "0: IDLE,1: Power-down,2: Wait state,?,4: Sample,?,6: Conversion,?" group.long 0x10++0x2B line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 5. "CTUTRGERR,This Error Flag indicates that the next CTU trigger has been discarded as it overlapped during execution of current CTU conversion. This indicated that CTU sampling duration is less than programmed conversion time of ADC." "0: No CTU trigger overlap error condition since..,1: CTU trigger overlap error has occurred." bitfld.long 0x0 4. "EOCTU,This bit indicates the end of conversion for a CTU injected channel." "0: End of conversion of CTU triggered channel has..,1: End of conversion of CTU triggered channel has.." newline bitfld.long 0x0 3. "JEOC,This bit indicates the end of conversion for an injected channel." "0: End of conversion of injected channel has not..,1: End of conversion of injected channel has.." bitfld.long 0x0 2. "JECH,This bit indicates the end of conversion for an injected chain." "0: End of conversion of injected chain has not..,1: End of conversion of injected chain has occurred.." newline bitfld.long 0x0 1. "NEOC,This bit indicates the end of conversion for a normal channel." "0: End of conversion of normal channel has not..,1: End of conversion of normal channel has occurred.." bitfld.long 0x0 0. "NECH,This bit indicates the end of conversion for an normal chain." "0: End of conversion of normal chain has not..,1: End of conversion of normal chain has occurred.." line.long 0x4 "ICIPR0,Internal Channel Interrupt Pending Register 0" bitfld.long 0x4 31. "EOC_CH31,End of conversion interrupt pending bit for channel 31" "0: End of conversion for CH[31] has not occured,1: End of conversion for CH[31] has occured" bitfld.long 0x4 30. "EOC_CH30,End of conversion interrupt pending bit for channel 30" "0: End of conversion for CH[30] has not occured,1: End of conversion for CH[30] has occured" newline bitfld.long 0x4 29. "EOC_CH29,End of conversion interrupt pending bit for channel 29" "0: End of conversion for CH[29] has not occured,1: End of conversion for CH[29] has occured" bitfld.long 0x4 28. "EOC_CH28,End of conversion interrupt pending bit for channel 28" "0: End of conversion for CH[28] has not occured,1: End of conversion for CH[28] has occured" newline bitfld.long 0x4 27. "EOC_CH27,End of conversion interrupt pending bit for channel 27" "0: End of conversion for CH[27] has not occured,1: End of conversion for CH[27] has occured" bitfld.long 0x4 26. "EOC_CH26,End of conversion interrupt pending bit for channel 26" "0: End of conversion for CH[26] has not occured,1: End of conversion for CH[26] has occured" newline bitfld.long 0x4 25. "EOC_CH25,End of conversion interrupt pending bit for channel 25" "0: End of conversion for CH[25] has not occured,1: End of conversion for CH[25] has occured" bitfld.long 0x4 24. "EOC_CH24,End of conversion interrupt pending bit for channel 24" "0: End of conversion for CH[24] has not occured,1: End of conversion for CH[24] has occured" newline bitfld.long 0x4 23. "EOC_CH23,End of conversion interrupt pending bit for channel 23" "0: End of conversion for CH[23] has not occured,1: End of conversion for CH[23] has occured" bitfld.long 0x4 22. "EOC_CH22,End of conversion interrupt pending bit for channel 22" "0: End of conversion for CH[22] has not occured,1: End of conversion for CH[22] has occured" newline bitfld.long 0x4 21. "EOC_CH21,End of conversion interrupt pending bit for channel 21" "0: End of conversion for CH[21] has not occured,1: End of conversion for CH[21] has occured" bitfld.long 0x4 20. "EOC_CH20,End of conversion interrupt pending bit for channel 20" "0: End of conversion for CH[20] has not occured,1: End of conversion for CH[20] has occured" newline bitfld.long 0x4 19. "EOC_CH19,End of conversion interrupt pending bit for channel 19" "0: End of conversion for CH[19] has not occured,1: End of conversion for CH[19] has occured" bitfld.long 0x4 18. "EOC_CH18,End of conversion interrupt pending bit for channel 18" "0: End of conversion for CH[18] has not occured,1: End of conversion for CH[18] has occured" newline bitfld.long 0x4 17. "EOC_CH17,End of conversion interrupt pending bit for channel 17" "0: End of conversion for CH[17] has not occured,1: End of conversion for CH[17] has occured" bitfld.long 0x4 16. "EOC_CH16,End of conversion interrupt pending bit for channel 16" "0: End of conversion for CH[16] has not occured,1: End of conversion for CH[16] has occured" newline bitfld.long 0x4 15. "EOC_CH15,End of conversion interrupt pending bit for channel 15" "0: End of conversion for CH[15] has not occured,1: End of conversion for CH[15] has occured" bitfld.long 0x4 14. "EOC_CH14,End of conversion interrupt pending bit for channel 14" "0: End of conversion for CH[14] has not occured,1: End of conversion for CH[14] has occured" newline bitfld.long 0x4 13. "EOC_CH13,End of conversion interrupt pending bit for channel 13" "0: End of conversion for CH[13] has not occured,1: End of conversion for CH[13] has occured" bitfld.long 0x4 12. "EOC_CH12,End of conversion interrupt pending bit for channel 12" "0: End of conversion for CH[12] has not occured,1: End of conversion for CH[12] has occured" newline bitfld.long 0x4 11. "EOC_CH11,End of conversion interrupt pending bit for channel 11" "0: End of conversion for CH[11] has not occured,1: End of conversion for CH[11] has occured" bitfld.long 0x4 10. "EOC_CH10,End of conversion interrupt pending bit for channel 10" "0: End of conversion for CH[10] has not occured,1: End of conversion for CH[10] has occured" newline bitfld.long 0x4 9. "EOC_CH9,End of conversion interrupt pending bit for channel 9" "0: End of conversion for CH[9] has not occured,1: End of conversion for CH[9] has occured" bitfld.long 0x4 8. "EOC_CH8,End of conversion interrupt pending bit for channel 8" "0: End of conversion for CH[8] has not occured,1: End of conversion for CH[8] has occured" newline bitfld.long 0x4 7. "EOC_CH7,End of conversion interrupt pending bit for channel 7" "0: End of conversion for CH[7] has not occured,1: End of conversion for CH[7] has occured" bitfld.long 0x4 6. "EOC_CH6,End of conversion interrupt pending bit for channel 6" "0: End of conversion for CH[6] has not occured,1: End of conversion for CH[6] has occured" newline bitfld.long 0x4 5. "EOC_CH5,End of conversion interrupt pending bit for channel 5" "0: End of conversion for CH[5] has not occured,1: End of conversion for CH[5] has occured" bitfld.long 0x4 4. "EOC_CH4,End of conversion interrupt pending bit for channel 4" "0: End of conversion for CH[4] has not occured,1: End of conversion for CH[4] has occured" newline bitfld.long 0x4 3. "EOC_CH3,End of conversion interrupt pending bit for channel 3" "0: End of conversion for CH[3] has not occured,1: End of conversion for CH[3] has occured" bitfld.long 0x4 2. "EOC_CH2,End of conversion interrupt pending bit for channel 2" "0: End of conversion for CH[2] has not occured,1: End of conversion for CH[2] has occured" newline bitfld.long 0x4 1. "EOC_CH1,End of conversion interrupt pending bit for channel 1" "0: End of conversion for CH[1] has not occured,1: End of conversion for CH[1] has occured" bitfld.long 0x4 0. "EOC_CH0,End of conversion interrupt pending bit for channel 0" "0: End of conversion for CH[0] has not occured,1: End of conversion for CH[0] has occured" line.long 0x8 "ICIPR1,Internal Channel Interrupt Pending Register 1" bitfld.long 0x8 31. "EOC_CH63,End of conversion interrupt pending bit for channel 63" "0: End of conversion for CH[63] has not occured,1: End of conversion for CH[63] has occured" bitfld.long 0x8 30. "EOC_CH62,End of conversion interrupt pending bit for channel 62" "0: End of conversion for CH[62] has not occured,1: End of conversion for CH[62] has occured" newline bitfld.long 0x8 29. "EOC_CH61,End of conversion interrupt pending bit for channel 61" "0: End of conversion for CH[61] has not occured,1: End of conversion for CH[61] has occured" bitfld.long 0x8 28. "EOC_CH60,End of conversion interrupt pending bit for channel 60" "0: End of conversion for CH[60] has not occured,1: End of conversion for CH[60] has occured" newline bitfld.long 0x8 27. "EOC_CH59,End of conversion interrupt pending bit for channel 59" "0: End of conversion for CH[59] has not occured,1: End of conversion for CH[59] has occured" bitfld.long 0x8 26. "EOC_CH58,End of conversion interrupt pending bit for channel 58" "0: End of conversion for CH[58] has not occured,1: End of conversion for CH[58] has occured" newline bitfld.long 0x8 25. "EOC_CH57,End of conversion interrupt pending bit for channel 57" "0: End of conversion for CH[57] has not occured,1: End of conversion for CH[57] has occured" bitfld.long 0x8 24. "EOC_CH56,End of conversion interrupt pending bit for channel 56" "0: End of conversion for CH[56] has not occured,1: End of conversion for CH[56] has occured" newline bitfld.long 0x8 23. "EOC_CH55,End of conversion interrupt pending bit for channel 55" "0: End of conversion for CH[55] has not occured,1: End of conversion for CH[55] has occured" bitfld.long 0x8 22. "EOC_CH54,End of conversion interrupt pending bit for channel 54" "0: End of conversion for CH[54] has not occured,1: End of conversion for CH[54] has occured" newline bitfld.long 0x8 21. "EOC_CH53,End of conversion interrupt pending bit for channel 53" "0: End of conversion for CH[53] has not occured,1: End of conversion for CH[53] has occured" bitfld.long 0x8 20. "EOC_CH52,End of conversion interrupt pending bit for channel 52" "0: End of conversion for CH[52] has not occured,1: End of conversion for CH[52] has occured" newline bitfld.long 0x8 19. "EOC_CH51,End of conversion interrupt pending bit for channel 51" "0: End of conversion for CH[51] has not occured,1: End of conversion for CH[51] has occured" bitfld.long 0x8 18. "EOC_CH50,End of conversion interrupt pending bit for channel 50" "0: End of conversion for CH[50] has not occured,1: End of conversion for CH[50] has occured" newline bitfld.long 0x8 17. "EOC_CH49,End of conversion interrupt pending bit for channel 49" "0: End of conversion for CH[49] has not occured,1: End of conversion for CH[49] has occured" bitfld.long 0x8 16. "EOC_CH48,End of conversion interrupt pending bit for channel 48" "0: End of conversion for CH[48] has not occured,1: End of conversion for CH[48] has occured" newline bitfld.long 0x8 15. "EOC_CH47,End of conversion interrupt pending bit for channel 47" "0: End of conversion for CH[47] has not occured,1: End of conversion for CH[47] has occured" bitfld.long 0x8 14. "EOC_CH46,End of conversion interrupt pending bit for channel 46" "0: End of conversion for CH[46] has not occured,1: End of conversion for CH[46] has occured" newline bitfld.long 0x8 13. "EOC_CH45,End of conversion interrupt pending bit for channel 45" "0: End of conversion for CH[45] has not occured,1: End of conversion for CH[45] has occured" bitfld.long 0x8 12. "EOC_CH44,End of conversion interrupt pending bit for channel 44" "0: End of conversion for CH[44] has not occured,1: End of conversion for CH[44] has occured" newline bitfld.long 0x8 11. "EOC_CH43,End of conversion interrupt pending bit for channel 43" "0: End of conversion for CH[43] has not occured,1: End of conversion for CH[43] has occured" bitfld.long 0x8 10. "EOC_CH42,End of conversion interrupt pending bit for channel 42" "0: End of conversion for CH[42] has not occured,1: End of conversion for CH[42] has occured" newline bitfld.long 0x8 9. "EOC_CH41,End of conversion interrupt pending bit for channel 41" "0: End of conversion for CH[41] has not occured,1: End of conversion for CH[41] has occured" bitfld.long 0x8 8. "EOC_CH40,End of conversion interrupt pending bit for channel 40" "0: End of conversion for CH[40] has not occured,1: End of conversion for CH[40] has occured" newline bitfld.long 0x8 7. "EOC_CH39,End of conversion interrupt pending bit for channel 39" "0: End of conversion for CH[39] has not occured,1: End of conversion for CH[39] has occured" bitfld.long 0x8 6. "EOC_CH38,End of conversion interrupt pending bit for channel 38" "0: End of conversion for CH[38] has not occured,1: End of conversion for CH[38] has occured" newline bitfld.long 0x8 5. "EOC_CH37,End of conversion interrupt pending bit for channel 37" "0: End of conversion for CH[37] has not occured,1: End of conversion for CH[37] has occured" bitfld.long 0x8 4. "EOC_CH36,End of conversion interrupt pending bit for channel 36" "0: End of conversion for CH[36] has not occured,1: End of conversion for CH[36] has occured" newline bitfld.long 0x8 3. "EOC_CH35,End of conversion interrupt pending bit for channel 35" "0: End of conversion for CH[35] has not occured,1: End of conversion for CH[35] has occured" bitfld.long 0x8 2. "EOC_CH34,End of conversion interrupt pending bit for channel 34" "0: End of conversion for CH[34] has not occured,1: End of conversion for CH[34] has occured" newline bitfld.long 0x8 1. "EOC_CH33,End of conversion interrupt pending bit for channel 33" "0: End of conversion for CH[33] has not occured,1: End of conversion for CH[33] has occured" bitfld.long 0x8 0. "EOC_CH32,End of conversion interrupt pending bit for channel 32" "0: End of conversion for CH[32] has not occured,1: End of conversion for CH[32] has occured" line.long 0xC "ICIPR2,Internal Channel Interrupt Pending Register 2" bitfld.long 0xC 31. "EOC_CH95,End of conversion interrupt pending bit for channel 95" "0: End of conversion for CH[95] has not occured,1: End of conversion for CH[95] has occured" bitfld.long 0xC 30. "EOC_CH94,End of conversion interrupt pending bit for channel 94" "0: End of conversion for CH[94] has not occured,1: End of conversion for CH[94] has occured" newline bitfld.long 0xC 29. "EOC_CH93,End of conversion interrupt pending bit for channel 93" "0: End of conversion for CH[93] has not occured,1: End of conversion for CH[93] has occured" bitfld.long 0xC 28. "EOC_CH92,End of conversion interrupt pending bit for channel 92" "0: End of conversion for CH[92] has not occured,1: End of conversion for CH[92] has occured" newline bitfld.long 0xC 27. "EOC_CH91,End of conversion interrupt pending bit for channel 91" "0: End of conversion for CH[91] has not occured,1: End of conversion for CH[91] has occured" bitfld.long 0xC 26. "EOC_CH90,End of conversion interrupt pending bit for channel 90" "0: End of conversion for CH[90] has not occured,1: End of conversion for CH[90] has occured" newline bitfld.long 0xC 25. "EOC_CH89,End of conversion interrupt pending bit for channel 89" "0: End of conversion for CH[89] has not occured,1: End of conversion for CH[89] has occured" bitfld.long 0xC 24. "EOC_CH88,End of conversion interrupt pending bit for channel 88" "0: End of conversion for CH[88] has not occured,1: End of conversion for CH[88] has occured" newline bitfld.long 0xC 23. "EOC_CH87,End of conversion interrupt pending bit for channel 87" "0: End of conversion for CH[87] has not occured,1: End of conversion for CH[87] has occured" bitfld.long 0xC 22. "EOC_CH86,End of conversion interrupt pending bit for channel 86" "0: End of conversion for CH[86] has not occured,1: End of conversion for CH[86] has occured" newline bitfld.long 0xC 21. "EOC_CH85,End of conversion interrupt pending bit for channel 85" "0: End of conversion for CH[85] has not occured,1: End of conversion for CH[85] has occured" bitfld.long 0xC 20. "EOC_CH84,End of conversion interrupt pending bit for channel 84" "0: End of conversion for CH[84] has not occured,1: End of conversion for CH[84] has occured" newline bitfld.long 0xC 19. "EOC_CH83,End of conversion interrupt pending bit for channel 83" "0: End of conversion for CH[83] has not occured,1: End of conversion for CH[83] has occured" bitfld.long 0xC 18. "EOC_CH82,End of conversion interrupt pending bit for channel 82" "0: End of conversion for CH[82] has not occured,1: End of conversion for CH[82] has occured" newline bitfld.long 0xC 17. "EOC_CH81,End of conversion interrupt pending bit for channel 81" "0: End of conversion for CH[81] has not occured,1: End of conversion for CH[81] has occured" bitfld.long 0xC 16. "EOC_CH80,End of conversion interrupt pending bit for channel 80" "0: End of conversion for CH[80] has not occured,1: End of conversion for CH[80] has occured" newline bitfld.long 0xC 15. "EOC_CH79,End of conversion interrupt pending bit for channel 79" "0: End of conversion for CH[79] has not occured,1: End of conversion for CH[79] has occured" bitfld.long 0xC 14. "EOC_CH78,End of conversion interrupt pending bit for channel 78" "0: End of conversion for CH[78] has not occured,1: End of conversion for CH[78] has occured" newline bitfld.long 0xC 13. "EOC_CH77,End of conversion interrupt pending bit for channel 77" "0: End of conversion for CH[77] has not occured,1: End of conversion for CH[77] has occured" bitfld.long 0xC 12. "EOC_CH76,End of conversion interrupt pending bit for channel 76" "0: End of conversion for CH[76] has not occured,1: End of conversion for CH[76] has occured" newline bitfld.long 0xC 11. "EOC_CH75,End of conversion interrupt pending bit for channel 75" "0: End of conversion for CH[75] has not occured,1: End of conversion for CH[75] has occured" bitfld.long 0xC 10. "EOC_CH74,End of conversion interrupt pending bit for channel 74" "0: End of conversion for CH[74] has not occured,1: End of conversion for CH[74] has occured" newline bitfld.long 0xC 9. "EOC_CH73,End of conversion interrupt pending bit for channel 73" "0: End of conversion for CH[73] has not occured,1: End of conversion for CH[73] has occured" bitfld.long 0xC 8. "EOC_CH72,End of conversion interrupt pending bit for channel 72" "0: End of conversion for CH[72] has not occured,1: End of conversion for CH[72] has occured" newline bitfld.long 0xC 7. "EOC_CH71,End of conversion interrupt pending bit for channel 71" "0: End of conversion for CH[71] has not occured,1: End of conversion for CH[71] has occured" bitfld.long 0xC 6. "EOC_CH70,End of conversion interrupt pending bit for channel 70" "0: End of conversion for CH[70] has not occured,1: End of conversion for CH[70] has occured" newline bitfld.long 0xC 5. "EOC_CH69,End of conversion interrupt pending bit for channel 69" "0: End of conversion for CH[69] has not occured,1: End of conversion for CH[69] has occured" bitfld.long 0xC 4. "EOC_CH68,End of conversion interrupt pending bit for channel 68" "0: End of conversion for CH[68] has not occured,1: End of conversion for CH[68] has occured" newline bitfld.long 0xC 3. "EOC_CH67,End of conversion interrupt pending bit for channel 67" "0: End of conversion for CH[67] has not occured,1: End of conversion for CH[67] has occured" bitfld.long 0xC 2. "EOC_CH66,End of conversion interrupt pending bit for channel 66" "0: End of conversion for CH[66] has not occured,1: End of conversion for CH[66] has occured" newline bitfld.long 0xC 1. "EOC_CH65,End of conversion interrupt pending bit for channel 65" "0: End of conversion for CH[65] has not occured,1: End of conversion for CH[65] has occured" bitfld.long 0xC 0. "EOC_CH64,End of conversion interrupt pending bit for channel 64" "0: End of conversion for CH[64] has not occured,1: End of conversion for CH[64] has occured" line.long 0x10 "IMR,Interrupt Mask Register" bitfld.long 0x10 5. "MSKCTUTRGERR,Mask bit for CTU Trigger" "0: CTUTRGERR interrupt is disabled,1: CTUTRGERR interrupt is enabled" bitfld.long 0x10 4. "MSKEOCTU,Mask bit for EOCTU" "0: EOCTU interrupt is disabled,1: EOCTU interrupt is enabled" newline bitfld.long 0x10 3. "MSKJEOC,Mask bit for JEOC" "0: JEOC interrupt is disabled,1: JEOC interrupt is enabled" bitfld.long 0x10 2. "MSKJECH,Mask bit for JECH" "0: JECH interrupt is disabled,1: JECH interrupt is enabled" newline bitfld.long 0x10 1. "MSKNEOC,Mask bit for NEOC" "0: NEOC interrupt is disabled,1: NEOC interrupt is enabled" bitfld.long 0x10 0. "MSKNECH,Mask bit for NECH" "0: NECH interrupt is disabled,1: NECH interrupt is enabled" line.long 0x14 "ICIMR0,Internal Channel Interrupt Mask Register 0" bitfld.long 0x14 31. "IM_CH31,Interrupt mask bit for channel 31" "0: Interupt for CH[31] is disabled,1: Interupt for CH[31] is enabled" bitfld.long 0x14 30. "IM_CH30,Interrupt mask bit for channel 30" "0: Interupt for CH[30] is disabled,1: Interupt for CH[30] is enabled" newline bitfld.long 0x14 29. "IM_CH29,Interrupt mask bit for channel 29" "0: Interupt for CH[29] is disabled,1: Interupt for CH[29] is enabled" bitfld.long 0x14 28. "IM_CH28,Interrupt mask bit for channel 28" "0: Interupt for CH[28] is disabled,1: Interupt for CH[28] is enabled" newline bitfld.long 0x14 27. "IM_CH27,Interrupt mask bit for channel 27" "0: Interupt for CH[27] is disabled,1: Interupt for CH[27] is enabled" bitfld.long 0x14 26. "IM_CH26,Interrupt mask bit for channel 26" "0: Interupt for CH[26] is disabled,1: Interupt for CH[26] is enabled" newline bitfld.long 0x14 25. "IM_CH25,Interrupt mask bit for channel 25" "0: Interupt for CH[25] is disabled,1: Interupt for CH[25] is enabled" bitfld.long 0x14 24. "IM_CH24,Interrupt mask bit for channel 24" "0: Interupt for CH[24] is disabled,1: Interupt for CH[24] is enabled" newline bitfld.long 0x14 23. "IM_CH23,Interrupt mask bit for channel 23" "0: Interupt for CH[23] is disabled,1: Interupt for CH[23] is enabled" bitfld.long 0x14 22. "IM_CH22,Interrupt mask bit for channel 22" "0: Interupt for CH[22] is disabled,1: Interupt for CH[22] is enabled" newline bitfld.long 0x14 21. "IM_CH21,Interrupt mask bit for channel 21" "0: Interupt for CH[21] is disabled,1: Interupt for CH[21] is enabled" bitfld.long 0x14 20. "IM_CH20,Interrupt mask bit for channel 20" "0: Interupt for CH[20] is disabled,1: Interupt for CH[20] is enabled" newline bitfld.long 0x14 19. "IM_CH19,Interrupt mask bit for channel 19" "0: Interupt for CH[19] is disabled,1: Interupt for CH[19] is enabled" bitfld.long 0x14 18. "IM_CH18,Interrupt mask bit for channel 18" "0: Interupt for CH[18] is disabled,1: Interupt for CH[18] is enabled" newline bitfld.long 0x14 17. "IM_CH17,Interrupt mask bit for channel 17" "0: Interupt for CH[17] is disabled,1: Interupt for CH[17] is enabled" bitfld.long 0x14 16. "IM_CH16,Interrupt mask bit for channel 16" "0: Interupt for CH[16] is disabled,1: Interupt for CH[16] is enabled" newline bitfld.long 0x14 15. "IM_CH15,Interrupt mask bit for channel 15" "0: Interupt for CH[15] is disabled,1: Interupt for CH[15] is enabled" bitfld.long 0x14 14. "IM_CH14,Interrupt mask bit for channel 14" "0: Interupt for CH[14] is disabled,1: Interupt for CH[14] is enabled" newline bitfld.long 0x14 13. "IM_CH13,Interrupt mask bit for channel 13" "0: Interupt for CH[13] is disabled,1: Interupt for CH[13] is enabled" bitfld.long 0x14 12. "IM_CH12,Interrupt mask bit for channel 12" "0: Interupt for CH[12] is disabled,1: Interupt for CH[12] is enabled" newline bitfld.long 0x14 11. "IM_CH11,Interrupt mask bit for channel 11" "0: Interupt for CH[11] is disabled,1: Interupt for CH[11] is enabled" bitfld.long 0x14 10. "IM_CH10,Interrupt mask bit for channel 10" "0: Interupt for CH[10] is disabled,1: Interupt for CH[10] is enabled" newline bitfld.long 0x14 9. "IM_CH9,Interrupt mask bit for channel 9" "0: Interupt for CH[9] is disabled,1: Interupt for CH[9] is enabled" bitfld.long 0x14 8. "IM_CH8,Interrupt mask bit for channel 8" "0: Interupt for CH[8] is disabled,1: Interupt for CH[8] is enabled" newline bitfld.long 0x14 7. "IM_CH7,Interrupt mask bit for channel 7" "0: Interupt for CH[7] is disabled,1: Interupt for CH[7] is enabled" bitfld.long 0x14 6. "IM_CH6,Interrupt mask bit for channel 6" "0: Interupt for CH[6] is disabled,1: Interupt for CH[6] is enabled" newline bitfld.long 0x14 5. "IM_CH5,Interrupt mask bit for channel 5" "0: Interupt for CH[5] is disabled,1: Interupt for CH[5] is enabled" bitfld.long 0x14 4. "IM_CH4,Interrupt mask bit for channel 4" "0: Interupt for CH[4] is disabled,1: Interupt for CH[4] is enabled" newline bitfld.long 0x14 3. "IM_CH3,Interrupt mask bit for channel 3" "0: Interupt for CH[3] is disabled,1: Interupt for CH[3] is enabled" bitfld.long 0x14 2. "IM_CH2,Interrupt mask bit for channel 2" "0: Interupt for CH[2] is disabled,1: Interupt for CH[2] is enabled" newline bitfld.long 0x14 1. "IM_CH1,Interrupt mask bit for channel 1" "0: Interupt for CH[1] is disabled,1: Interupt for CH[1] is enabled" bitfld.long 0x14 0. "IM_CH0,Interrupt mask bit for channel 0" "0: Interupt for CH[0] is disabled,1: Interupt for CH[0] is enabled" line.long 0x18 "ICIMR1,Internal Channel Interrupt Mask Register 1" bitfld.long 0x18 31. "IM_CH63,Interrupt mask bit for channel 63" "0: Interupt for CH[63] is disabled,1: Interupt for CH[63] is enabled" bitfld.long 0x18 30. "IM_CH62,Interrupt mask bit for channel 62" "0: Interupt for CH[62] is disabled,1: Interupt for CH[62] is enabled" newline bitfld.long 0x18 29. "IM_CH61,Interrupt mask bit for channel 61" "0: Interupt for CH[61] is disabled,1: Interupt for CH[61] is enabled" bitfld.long 0x18 28. "IM_CH60,Interrupt mask bit for channel 60" "0: Interupt for CH[60] is disabled,1: Interupt for CH[60] is enabled" newline bitfld.long 0x18 27. "IM_CH59,Interrupt mask bit for channel 59" "0: Interupt for CH[59] is disabled,1: Interupt for CH[59] is enabled" bitfld.long 0x18 26. "IM_CH58,Interrupt mask bit for channel 58" "0: Interupt for CH[58] is disabled,1: Interupt for CH[58] is enabled" newline bitfld.long 0x18 25. "IM_CH57,Interrupt mask bit for channel 57" "0: Interupt for CH[57] is disabled,1: Interupt for CH[57] is enabled" bitfld.long 0x18 24. "IM_CH56,Interrupt mask bit for channel 56" "0: Interupt for CH[56] is disabled,1: Interupt for CH[56] is enabled" newline bitfld.long 0x18 23. "IM_CH55,Interrupt mask bit for channel 55" "0: Interupt for CH[55] is disabled,1: Interupt for CH[55] is enabled" bitfld.long 0x18 22. "IM_CH54,Interrupt mask bit for channel 54" "0: Interupt for CH[54] is disabled,1: Interupt for CH[54] is enabled" newline bitfld.long 0x18 21. "IM_CH53,Interrupt mask bit for channel 53" "0: Interupt for CH[53] is disabled,1: Interupt for CH[53] is enabled" bitfld.long 0x18 20. "IM_CH52,Interrupt mask bit for channel 52" "0: Interupt for CH[52] is disabled,1: Interupt for CH[52] is enabled" newline bitfld.long 0x18 19. "IM_CH51,Interrupt mask bit for channel 51" "0: Interupt for CH[51] is disabled,1: Interupt for CH[51] is enabled" bitfld.long 0x18 18. "IM_CH50,Interrupt mask bit for channel 50" "0: Interupt for CH[50] is disabled,1: Interupt for CH[50] is enabled" newline bitfld.long 0x18 17. "IM_CH49,Interrupt mask bit for channel 49" "0: Interupt for CH[49] is disabled,1: Interupt for CH[49] is enabled" bitfld.long 0x18 16. "IM_CH48,Interrupt mask bit for channel 48" "0: Interupt for CH[48] is disabled,1: Interupt for CH[48] is enabled" newline bitfld.long 0x18 15. "IM_CH47,Interrupt mask bit for channel 47" "0: Interupt for CH[47] is disabled,1: Interupt for CH[47] is enabled" bitfld.long 0x18 14. "IM_CH46,Interrupt mask bit for channel 46" "0: Interupt for CH[46] is disabled,1: Interupt for CH[46] is enabled" newline bitfld.long 0x18 13. "IM_CH45,Interrupt mask bit for channel 45" "0: Interupt for CH[45] is disabled,1: Interupt for CH[45] is enabled" bitfld.long 0x18 12. "IM_CH44,Interrupt mask bit for channel 44" "0: Interupt for CH[44] is disabled,1: Interupt for CH[44] is enabled" newline bitfld.long 0x18 11. "IM_CH43,Interrupt mask bit for channel 43" "0: Interupt for CH[43] is disabled,1: Interupt for CH[43] is enabled" bitfld.long 0x18 10. "IM_CH42,Interrupt mask bit for channel 42" "0: Interupt for CH[42] is disabled,1: Interupt for CH[42] is enabled" newline bitfld.long 0x18 9. "IM_CH41,Interrupt mask bit for channel 41" "0: Interupt for CH[41] is disabled,1: Interupt for CH[41] is enabled" bitfld.long 0x18 8. "IM_CH40,Interrupt mask bit for channel 40" "0: Interupt for CH[40] is disabled,1: Interupt for CH[40] is enabled" newline bitfld.long 0x18 7. "IM_CH39,Interrupt mask bit for channel 39" "0: Interupt for CH[39] is disabled,1: Interupt for CH[39] is enabled" bitfld.long 0x18 6. "IM_CH38,Interrupt mask bit for channel 38" "0: Interupt for CH[38] is disabled,1: Interupt for CH[38] is enabled" newline bitfld.long 0x18 5. "IM_CH37,Interrupt mask bit for channel 37" "0: Interupt for CH[37] is disabled,1: Interupt for CH[37] is enabled" bitfld.long 0x18 4. "IM_CH36,Interrupt mask bit for channel 36" "0: Interupt for CH[36] is disabled,1: Interupt for CH[36] is enabled" newline bitfld.long 0x18 3. "IM_CH35,Interrupt mask bit for channel 35" "0: Interupt for CH[35] is disabled,1: Interupt for CH[35] is enabled" bitfld.long 0x18 2. "IM_CH34,Interrupt mask bit for channel 34" "0: Interupt for CH[34] is disabled,1: Interupt for CH[34] is enabled" newline bitfld.long 0x18 1. "IM_CH33,Interrupt mask bit for channel 33" "0: Interupt for CH[33] is disabled,1: Interupt for CH[33] is enabled" bitfld.long 0x18 0. "IM_CH32,Interrupt mask bit for channel 32" "0: Interupt for CH[32] is disabled,1: Interupt for CH[32] is enabled" line.long 0x1C "ICIMR2,Internal Channel Interrupt Mask Register 2" bitfld.long 0x1C 31. "IM_CH95,Interrupt mask bit for channel 95" "0: Interupt for CH[95] is disabled,1: Interupt for CH[95] is enabled" bitfld.long 0x1C 30. "IM_CH94,Interrupt mask bit for channel 94" "0: Interupt for CH[94] is disabled,1: Interupt for CH[94] is enabled" newline bitfld.long 0x1C 29. "IM_CH93,Interrupt mask bit for channel 93" "0: Interupt for CH[93] is disabled,1: Interupt for CH[93] is enabled" bitfld.long 0x1C 28. "IM_CH92,Interrupt mask bit for channel 92" "0: Interupt for CH[92] is disabled,1: Interupt for CH[92] is enabled" newline bitfld.long 0x1C 27. "IM_CH91,Interrupt mask bit for channel 91" "0: Interupt for CH[91] is disabled,1: Interupt for CH[91] is enabled" bitfld.long 0x1C 26. "IM_CH90,Interrupt mask bit for channel 90" "0: Interupt for CH[90] is disabled,1: Interupt for CH[90] is enabled" newline bitfld.long 0x1C 25. "IM_CH89,Interrupt mask bit for channel 89" "0: Interupt for CH[89] is disabled,1: Interupt for CH[89] is enabled" bitfld.long 0x1C 24. "IM_CH88,Interrupt mask bit for channel 88" "0: Interupt for CH[88] is disabled,1: Interupt for CH[88] is enabled" newline bitfld.long 0x1C 23. "IM_CH87,Interrupt mask bit for channel 87" "0: Interupt for CH[87] is disabled,1: Interupt for CH[87] is enabled" bitfld.long 0x1C 22. "IM_CH86,Interrupt mask bit for channel 86" "0: Interupt for CH[86] is disabled,1: Interupt for CH[86] is enabled" newline bitfld.long 0x1C 21. "IM_CH85,Interrupt mask bit for channel 85" "0: Interupt for CH[85] is disabled,1: Interupt for CH[85] is enabled" bitfld.long 0x1C 20. "IM_CH84,Interrupt mask bit for channel 84" "0: Interupt for CH[84] is disabled,1: Interupt for CH[84] is enabled" newline bitfld.long 0x1C 19. "IM_CH83,Interrupt mask bit for channel 83" "0: Interupt for CH[83] is disabled,1: Interupt for CH[83] is enabled" bitfld.long 0x1C 18. "IM_CH82,Interrupt mask bit for channel 82" "0: Interupt for CH[82] is disabled,1: Interupt for CH[82] is enabled" newline bitfld.long 0x1C 17. "IM_CH81,Interrupt mask bit for channel 81" "0: Interupt for CH[81] is disabled,1: Interupt for CH[81] is enabled" bitfld.long 0x1C 16. "IM_CH80,Interrupt mask bit for channel 80" "0: Interupt for CH[80] is disabled,1: Interupt for CH[80] is enabled" newline bitfld.long 0x1C 15. "IM_CH79,Interrupt mask bit for channel 79" "0: Interupt for CH[79] is disabled,1: Interupt for CH[79] is enabled" bitfld.long 0x1C 14. "IM_CH78,Interrupt mask bit for channel 78" "0: Interupt for CH[78] is disabled,1: Interupt for CH[78] is enabled" newline bitfld.long 0x1C 13. "IM_CH77,Interrupt mask bit for channel 77" "0: Interupt for CH[77] is disabled,1: Interupt for CH[77] is enabled" bitfld.long 0x1C 12. "IM_CH76,Interrupt mask bit for channel 76" "0: Interupt for CH[76] is disabled,1: Interupt for CH[76] is enabled" newline bitfld.long 0x1C 11. "IM_CH75,Interrupt mask bit for channel 75" "0: Interupt for CH[75] is disabled,1: Interupt for CH[75] is enabled" bitfld.long 0x1C 10. "IM_CH74,Interrupt mask bit for channel 74" "0: Interupt for CH[74] is disabled,1: Interupt for CH[74] is enabled" newline bitfld.long 0x1C 9. "IM_CH73,Interrupt mask bit for channel 73" "0: Interupt for CH[73] is disabled,1: Interupt for CH[73] is enabled" bitfld.long 0x1C 8. "IM_CH72,Interrupt mask bit for channel 72" "0: Interupt for CH[72] is disabled,1: Interupt for CH[72] is enabled" newline bitfld.long 0x1C 7. "IM_CH71,Interrupt mask bit for channel 71" "0: Interupt for CH[71] is disabled,1: Interupt for CH[71] is enabled" bitfld.long 0x1C 6. "IM_CH70,Interrupt mask bit for channel 70" "0: Interupt for CH[70] is disabled,1: Interupt for CH[70] is enabled" newline bitfld.long 0x1C 5. "IM_CH69,Interrupt mask bit for channel 69" "0: Interupt for CH[69] is disabled,1: Interupt for CH[69] is enabled" bitfld.long 0x1C 4. "IM_CH68,Interrupt mask bit for channel 68" "0: Interupt for CH[68] is disabled,1: Interupt for CH[68] is enabled" newline bitfld.long 0x1C 3. "IM_CH67,Interrupt mask bit for channel 67" "0: Interupt for CH[67] is disabled,1: Interupt for CH[67] is enabled" bitfld.long 0x1C 2. "IM_CH66,Interrupt mask bit for channel 66" "0: Interupt for CH[66] is disabled,1: Interupt for CH[66] is enabled" newline bitfld.long 0x1C 1. "IM_CH65,Interrupt mask bit for channel 65" "0: Interupt for CH[65] is disabled,1: Interupt for CH[65] is enabled" bitfld.long 0x1C 0. "IM_CH64,Interrupt mask bit for channel 64" "0: Interupt for CH[64] is disabled,1: Interupt for CH[64] is enabled" line.long 0x20 "WTISR,Watchdog Threshold Interrupt Status Register" bitfld.long 0x20 15. "WDG7H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 7." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x20 14. "WDG7L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 7." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x20 13. "WDG6H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 6." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x20 12. "WDG6L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 6." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x20 11. "WDG5H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 5." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x20 10. "WDG5L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 5." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x20 9. "WDG4H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 4." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x20 8. "WDG4L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 4." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x20 7. "WDG3H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 3." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x20 6. "WDG3L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 3." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x20 5. "WDG2H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 2." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x20 4. "WDG2L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 2." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x20 3. "WDG1H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 1." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x20 2. "WDG1L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 1." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x20 1. "WDG0H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 0." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x20 0. "WDG0L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 0." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." line.long 0x24 "WTIMR,Watchdog Threshold Interrupt Mask Register" bitfld.long 0x24 15. "MSKWDG7H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG7H is disabled.,1: Inetrupt for WDG7H is enabled." bitfld.long 0x24 14. "MSKWDG7L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG7L is disabled.,1: Inetrupt for WDG7L is enabled." newline bitfld.long 0x24 13. "MSKWDG6H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG6H is disabled.,1: Inetrupt for WDG6H is enabled." bitfld.long 0x24 12. "MSKWDG6L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG6L is disabled.,1: Inetrupt for WDG6L is enabled." newline bitfld.long 0x24 11. "MSKWDG5H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG5H is disabled.,1: Inetrupt for WDG5H is enabled." bitfld.long 0x24 10. "MSKWDG5L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG5L is disabled.,1: Inetrupt for WDG5L is enabled." newline bitfld.long 0x24 9. "MSKWDG4H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG4H is disabled.,1: Inetrupt for WDG4H is enabled." bitfld.long 0x24 8. "MSKWDG4L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG4L is disabled.,1: Inetrupt for WDG4L is enabled." newline bitfld.long 0x24 7. "MSKWDG3H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG3H is disabled.,1: Inetrupt for WDG3H is enabled." bitfld.long 0x24 6. "MSKWDG3L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG3L is disabled.,1: Inetrupt for WDG3L is enabled." newline bitfld.long 0x24 5. "MSKWDG2H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG2H is disabled.,1: Inetrupt for WDG2H is enabled." bitfld.long 0x24 4. "MSKWDG2L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG2L is disabled.,1: Inetrupt for WDG2L is enabled." newline bitfld.long 0x24 3. "MSKWDG1H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG1H is disabled.,1: Inetrupt for WDG1H is enabled." bitfld.long 0x24 2. "MSKWDG1L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG1L is disabled.,1: Inetrupt for WDG1L is enabled." newline bitfld.long 0x24 1. "MSKWDG0H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG0H is disabled.,1: Inetrupt for WDG0H is enabled." bitfld.long 0x24 0. "MSKWDG0L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG0L is disabled.,1: Inetrupt for WDG0L is enabled." line.long 0x28 "WLTCR,Watchdog Level Trigger Configuration Register" bitfld.long 0x28 7. "LTMW7,LTMW7" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0x28 6. "LTMW6,LTMW6" "0: Level Trigger Mode,1: Hysteresis Mode" newline bitfld.long 0x28 5. "LTMW5,LTMW5" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0x28 4. "LTMW4,LTMW4" "0: Level Trigger Mode,1: Hysteresis Mode" newline bitfld.long 0x28 3. "LTMW3,LTMW3" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0x28 2. "LTMW2,LTMW2" "0: Level Trigger Mode,1: Hysteresis Mode" newline bitfld.long 0x28 1. "LTMW1,LTMW1" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0x28 0. "LTMW0,LTMW0" "0: Level Trigger Mode,1: Hysteresis Mode" group.long 0x40++0xF line.long 0x0 "DMAE,DMA Enable Register" bitfld.long 0x0 1. "DCLR,DMA clear sequence enable" "0: DMA request cleared by Acknowledge from DMA..,1: DMA request cleared on read of data registers" bitfld.long 0x0 0. "DMAEN,DMA global enable" "0: DMA feature disabled,1: DMA feature enabled" line.long 0x4 "ICDSR0,Internal Channel DMA Select Register 0" bitfld.long 0x4 31. "DS_CH31,DS_CH31" "0: CH[31] is disabled to transfer data in DMA mode.,1: CH[31] is enabled to transfer data in DMA mode." bitfld.long 0x4 30. "DS_CH30,DS_CH30" "0: CH[30] is disabled to transfer data in DMA mode.,1: CH[30] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 29. "DS_CH29,DS_CH29" "0: CH[29] is disabled to transfer data in DMA mode.,1: CH[29] is enabled to transfer data in DMA mode." bitfld.long 0x4 28. "DS_CH28,DS_CH28" "0: CH[28] is disabled to transfer data in DMA mode.,1: CH[28] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 27. "DS_CH27,DS_CH27" "0: CH[27] is disabled to transfer data in DMA mode.,1: CH[27] is enabled to transfer data in DMA mode." bitfld.long 0x4 26. "DS_CH26,DS_CH26" "0: CH[26] is disabled to transfer data in DMA mode.,1: CH[26] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 25. "DS_CH25,DS_CH25" "0: CH[25] is disabled to transfer data in DMA mode.,1: CH[25] is enabled to transfer data in DMA mode." bitfld.long 0x4 24. "DS_CH24,DS_CH24" "0: CH[24] is disabled to transfer data in DMA mode.,1: CH[24] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 23. "DS_CH23,DS_CH23" "0: CH[23] is disabled to transfer data in DMA mode.,1: CH[23] is enabled to transfer data in DMA mode." bitfld.long 0x4 22. "DS_CH22,DS_CH22" "0: CH[22] is disabled to transfer data in DMA mode.,1: CH[22] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 21. "DS_CH21,DS_CH21" "0: CH[21] is disabled to transfer data in DMA mode.,1: CH[21] is enabled to transfer data in DMA mode." bitfld.long 0x4 20. "DS_CH20,DS_CH20" "0: CH[20] is disabled to transfer data in DMA mode.,1: CH[20] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 19. "DS_CH19,DS_CH19" "0: CH[19] is disabled to transfer data in DMA mode.,1: CH[19] is enabled to transfer data in DMA mode." bitfld.long 0x4 18. "DS_CH18,DS_CH18" "0: CH[18] is disabled to transfer data in DMA mode.,1: CH[18] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 17. "DS_CH17,DS_CH17" "0: CH[17] is disabled to transfer data in DMA mode.,1: CH[17] is enabled to transfer data in DMA mode." bitfld.long 0x4 16. "DS_CH16,DS_CH16" "0: CH[16] is disabled to transfer data in DMA mode.,1: CH[16] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 15. "DS_CH15,DS_CH15" "0: CH[15] is disabled to transfer data in DMA mode.,1: CH[15] is enabled to transfer data in DMA mode." bitfld.long 0x4 14. "DS_CH14,DS_CH14" "0: CH[14] is disabled to transfer data in DMA mode.,1: CH[14] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 13. "DS_CH13,DS_CH13" "0: CH[13] is disabled to transfer data in DMA mode.,1: CH[13] is enabled to transfer data in DMA mode." bitfld.long 0x4 12. "DS_CH12,DS_CH12" "0: CH[12] is disabled to transfer data in DMA mode.,1: CH[12] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 11. "DS_CH11,DS_CH11" "0: CH[11] is disabled to transfer data in DMA mode.,1: CH[11] is enabled to transfer data in DMA mode." bitfld.long 0x4 10. "DS_CH10,DS_CH10" "0: CH[10] is disabled to transfer data in DMA mode.,1: CH[10] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 9. "DS_CH9,DS_CH9" "0: CH[9] is disabled to transfer data in DMA mode.,1: CH[9] is enabled to transfer data in DMA mode." bitfld.long 0x4 8. "DS_CH8,DS_CH8" "0: CH[8] is disabled to transfer data in DMA mode.,1: CH[8] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 7. "DS_CH7,DS_CH7" "0: CH[7] is disabled to transfer data in DMA mode.,1: CH[7] is enabled to transfer data in DMA mode." bitfld.long 0x4 6. "DS_CH6,DS_CH6" "0: CH[6] is disabled to transfer data in DMA mode.,1: CH[6] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 5. "DS_CH5,DS_CH5" "0: CH[5] is disabled to transfer data in DMA mode.,1: CH[5] is enabled to transfer data in DMA mode." bitfld.long 0x4 4. "DS_CH4,DS_CH4" "0: CH[4] is disabled to transfer data in DMA mode.,1: CH[4] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 3. "DS_CH3,DS_CH3" "0: CH[3] is disabled to transfer data in DMA mode.,1: CH[3] is enabled to transfer data in DMA mode." bitfld.long 0x4 2. "DS_CH2,DS_CH2" "0: CH[2] is disabled to transfer data in DMA mode.,1: CH[2] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 1. "DS_CH1,DS_CH1" "0: CH[1] is disabled to transfer data in DMA mode.,1: CH[1] is enabled to transfer data in DMA mode." bitfld.long 0x4 0. "DS_CH0,DS_CH0" "0: CH[0] is disabled to transfer data in DMA mode.,1: CH[0] is enabled to transfer data in DMA mode." line.long 0x8 "ICDSR1,Internal Channel DMA Select Register 1" bitfld.long 0x8 31. "DS_CH63,DS_CH63" "0: CH[63] is disabled to transfer data in DMA mode.,1: CH[63] is enabled to transfer data in DMA mode." bitfld.long 0x8 30. "DS_CH62,DS_CH62" "0: CH[62] is disabled to transfer data in DMA mode.,1: CH[62] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 29. "DS_CH61,DS_CH61" "0: CH[61] is disabled to transfer data in DMA mode.,1: CH[61] is enabled to transfer data in DMA mode." bitfld.long 0x8 28. "DS_CH60,DS_CH60" "0: CH[60] is disabled to transfer data in DMA mode.,1: CH[60] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 27. "DS_CH59,DS_CH59" "0: CH[59] is disabled to transfer data in DMA mode.,1: CH[59] is enabled to transfer data in DMA mode." bitfld.long 0x8 26. "DS_CH58,DS_CH58" "0: CH[58] is disabled to transfer data in DMA mode.,1: CH[58] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 25. "DS_CH57,DS_CH57" "0: CH[57] is disabled to transfer data in DMA mode.,1: CH[57] is enabled to transfer data in DMA mode." bitfld.long 0x8 24. "DS_CH56,DS_CH56" "0: CH[56] is disabled to transfer data in DMA mode.,1: CH[56] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 23. "DS_CH55,DS_CH55" "0: CH[55] is disabled to transfer data in DMA mode.,1: CH[55] is enabled to transfer data in DMA mode." bitfld.long 0x8 22. "DS_CH54,DS_CH54" "0: CH[54] is disabled to transfer data in DMA mode.,1: CH[54] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 21. "DS_CH53,DS_CH53" "0: CH[53] is disabled to transfer data in DMA mode.,1: CH[53] is enabled to transfer data in DMA mode." bitfld.long 0x8 20. "DS_CH52,DS_CH52" "0: CH[52] is disabled to transfer data in DMA mode.,1: CH[52] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 19. "DS_CH51,DS_CH51" "0: CH[51] is disabled to transfer data in DMA mode.,1: CH[51] is enabled to transfer data in DMA mode." bitfld.long 0x8 18. "DS_CH50,DS_CH50" "0: CH[50] is disabled to transfer data in DMA mode.,1: CH[50] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 17. "DS_CH49,DS_CH49" "0: CH[49] is disabled to transfer data in DMA mode.,1: CH[49] is enabled to transfer data in DMA mode." bitfld.long 0x8 16. "DS_CH48,DS_CH48" "0: CH[48] is disabled to transfer data in DMA mode.,1: CH[48] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 15. "DS_CH47,DS_CH47" "0: CH[47] is disabled to transfer data in DMA mode.,1: CH[47] is enabled to transfer data in DMA mode." bitfld.long 0x8 14. "DS_CH46,DS_CH46" "0: CH[46] is disabled to transfer data in DMA mode.,1: CH[46] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 13. "DS_CH45,DS_CH45" "0: CH[45] is disabled to transfer data in DMA mode.,1: CH[45] is enabled to transfer data in DMA mode." bitfld.long 0x8 12. "DS_CH44,DS_CH44" "0: CH[44] is disabled to transfer data in DMA mode.,1: CH[44] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 11. "DS_CH43,DS_CH43" "0: CH[43] is disabled to transfer data in DMA mode.,1: CH[43] is enabled to transfer data in DMA mode." bitfld.long 0x8 10. "DS_CH42,DS_CH42" "0: CH[42] is disabled to transfer data in DMA mode.,1: CH[42] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 9. "DS_CH41,DS_CH41" "0: CH[41] is disabled to transfer data in DMA mode.,1: CH[41] is enabled to transfer data in DMA mode." bitfld.long 0x8 8. "DS_CH40,DS_CH40" "0: CH[40] is disabled to transfer data in DMA mode.,1: CH[40] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 7. "DS_CH39,DS_CH39" "0: CH[39] is disabled to transfer data in DMA mode.,1: CH[39] is enabled to transfer data in DMA mode." bitfld.long 0x8 6. "DS_CH38,DS_CH38" "0: CH[38] is disabled to transfer data in DMA mode.,1: CH[38] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 5. "DS_CH37,DS_CH37" "0: CH[37] is disabled to transfer data in DMA mode.,1: CH[37] is enabled to transfer data in DMA mode." bitfld.long 0x8 4. "DS_CH36,DS_CH36" "0: CH[36] is disabled to transfer data in DMA mode.,1: CH[36] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 3. "DS_CH35,DS_CH35" "0: CH[35] is disabled to transfer data in DMA mode.,1: CH[35] is enabled to transfer data in DMA mode." bitfld.long 0x8 2. "DS_CH34,DS_CH34" "0: CH[34] is disabled to transfer data in DMA mode.,1: CH[34] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 1. "DS_CH33,DS_CH33" "0: CH[33] is disabled to transfer data in DMA mode.,1: CH[33] is enabled to transfer data in DMA mode." bitfld.long 0x8 0. "DS_CH32,DS_CH32" "0: CH[32] is disabled to transfer data in DMA mode.,1: CH[32] is enabled to transfer data in DMA mode." line.long 0xC "ICDSR2,Internal Channel DMA Select Register 2" bitfld.long 0xC 31. "DS_CH95,DS_CH95" "0: CH[95] is disabled to transfer data in DMA mode.,1: CH[95] is enabled to transfer data in DMA mode." bitfld.long 0xC 30. "DS_CH94,DS_CH94" "0: CH[94] is disabled to transfer data in DMA mode.,1: CH[94] is enabled to transfer data in DMA mode." newline bitfld.long 0xC 29. "DS_CH93,DS_CH93" "0: CH[93] is disabled to transfer data in DMA mode.,1: CH[93] is enabled to transfer data in DMA mode." bitfld.long 0xC 28. "DS_CH92,DS_CH92" "0: CH[92] is disabled to transfer data in DMA mode.,1: CH[92] is enabled to transfer data in DMA mode." newline bitfld.long 0xC 27. "DS_CH91,DS_CH91" "0: CH[91] is disabled to transfer data in DMA mode.,1: CH[91] is enabled to transfer data in DMA mode." bitfld.long 0xC 26. "DS_CH90,DS_CH90" "0: CH[90] is disabled to transfer data in DMA mode.,1: CH[90] is enabled to transfer data in DMA mode." newline bitfld.long 0xC 25. "DS_CH89,DS_CH89" "0: CH[89] is disabled to transfer data in DMA mode.,1: CH[89] is enabled to transfer data in DMA mode." bitfld.long 0xC 24. "DS_CH88,DS_CH88" "0: CH[88] is disabled to transfer data in DMA mode.,1: CH[88] is enabled to transfer data in DMA mode." newline bitfld.long 0xC 23. "DS_CH87,DS_CH87" "0: CH[87] is disabled to transfer data in DMA mode.,1: CH[87] is enabled to transfer data in DMA mode." bitfld.long 0xC 22. "DS_CH86,DS_CH86" "0: CH[86] is disabled to transfer data in DMA mode.,1: CH[86] is enabled to transfer data in DMA mode." newline bitfld.long 0xC 21. "DS_CH85,DS_CH85" "0: CH[85] is disabled to transfer data in DMA mode.,1: CH[85] is enabled to transfer data in DMA mode." bitfld.long 0xC 20. "DS_CH84,DS_CH84" "0: CH[84] is disabled to transfer data in DMA mode.,1: CH[84] is enabled to transfer data in DMA mode." newline bitfld.long 0xC 19. "DS_CH83,DS_CH83" "0: CH[83] is disabled to transfer data in DMA mode.,1: CH[83] is enabled to transfer data in DMA mode." bitfld.long 0xC 18. "DS_CH82,DS_CH82" "0: CH[82] is disabled to transfer data in DMA mode.,1: CH[82] is enabled to transfer data in DMA mode." newline bitfld.long 0xC 17. "DS_CH81,DS_CH81" "0: CH[81] is disabled to transfer data in DMA mode.,1: CH[81] is enabled to transfer data in DMA mode." bitfld.long 0xC 16. "DS_CH80,DS_CH80" "0: CH[80] is disabled to transfer data in DMA mode.,1: CH[80] is enabled to transfer data in DMA mode." newline bitfld.long 0xC 15. "DS_CH79,DS_CH79" "0: CH[79] is disabled to transfer data in DMA mode.,1: CH[79] is enabled to transfer data in DMA mode." bitfld.long 0xC 14. "DS_CH78,DS_CH78" "0: CH[78] is disabled to transfer data in DMA mode.,1: CH[78] is enabled to transfer data in DMA mode." newline bitfld.long 0xC 13. "DS_CH77,DS_CH77" "0: CH[77] is disabled to transfer data in DMA mode.,1: CH[77] is enabled to transfer data in DMA mode." bitfld.long 0xC 12. "DS_CH76,DS_CH76" "0: CH[76] is disabled to transfer data in DMA mode.,1: CH[76] is enabled to transfer data in DMA mode." newline bitfld.long 0xC 11. "DS_CH75,DS_CH75" "0: CH[75] is disabled to transfer data in DMA mode.,1: CH[75] is enabled to transfer data in DMA mode." bitfld.long 0xC 10. "DS_CH74,DS_CH74" "0: CH[74] is disabled to transfer data in DMA mode.,1: CH[74] is enabled to transfer data in DMA mode." newline bitfld.long 0xC 9. "DS_CH73,DS_CH73" "0: CH[73] is disabled to transfer data in DMA mode.,1: CH[73] is enabled to transfer data in DMA mode." bitfld.long 0xC 8. "DS_CH72,DS_CH72" "0: CH[72] is disabled to transfer data in DMA mode.,1: CH[72] is enabled to transfer data in DMA mode." newline bitfld.long 0xC 7. "DS_CH71,DS_CH71" "0: CH[71] is disabled to transfer data in DMA mode.,1: CH[71] is enabled to transfer data in DMA mode." bitfld.long 0xC 6. "DS_CH70,DS_CH70" "0: CH[70] is disabled to transfer data in DMA mode.,1: CH[70] is enabled to transfer data in DMA mode." newline bitfld.long 0xC 5. "DS_CH69,DS_CH69" "0: CH[69] is disabled to transfer data in DMA mode.,1: CH[69] is enabled to transfer data in DMA mode." bitfld.long 0xC 4. "DS_CH68,DS_CH68" "0: CH[68] is disabled to transfer data in DMA mode.,1: CH[68] is enabled to transfer data in DMA mode." newline bitfld.long 0xC 3. "DS_CH67,DS_CH67" "0: CH[67] is disabled to transfer data in DMA mode.,1: CH[67] is enabled to transfer data in DMA mode." bitfld.long 0xC 2. "DS_CH66,DS_CH66" "0: CH[66] is disabled to transfer data in DMA mode.,1: CH[66] is enabled to transfer data in DMA mode." newline bitfld.long 0xC 1. "DS_CH65,DS_CH65" "0: CH[65] is disabled to transfer data in DMA mode.,1: CH[65] is enabled to transfer data in DMA mode." bitfld.long 0xC 0. "DS_CH64,DS_CH64" "0: CH[64] is disabled to transfer data in DMA mode.,1: CH[64] is enabled to transfer data in DMA mode." group.long 0x60++0xF line.long 0x0 "WTHRHLR0,Watchdog Threshold Register 0" hexmask.long.word 0x0 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x0 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x4 "WTHRHLR1,Watchdog Threshold Register 1" hexmask.long.word 0x4 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x4 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x8 "WTHRHLR2,Watchdog Threshold Register 2" hexmask.long.word 0x8 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x8 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0xC "WTHRHLR3,Watchdog Threshold Register 3" hexmask.long.word 0xC 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0xC 0.--11. 1. "THRL,Low threshold value for channel x" group.long 0x94++0x1B line.long 0x0 "CTR0,Conversion Timing Register 0" bitfld.long 0x0 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x0 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x4 "CTR1,Conversion Timing Register 1" bitfld.long 0x4 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x4 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x4 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x8 "CTR2,Conversion Timing Register 2" bitfld.long 0x8 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x8 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x8 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0xC "CTR3,Conversion Timing Register 3" bitfld.long 0xC 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0xC 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0xC 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x10 "ICNCMR0,Internal Channel Normal Conversion Mask Register 0" bitfld.long 0x10 31. "NCE_CH31,NCE_CH31" "0: Normal conversion is disabled for CH[31].,1: Normal conversion is enabled for CH[31]." bitfld.long 0x10 30. "NCE_CH30,NCE_CH30" "0: Normal conversion is disabled for CH[30].,1: Normal conversion is enabled for CH[30]." newline bitfld.long 0x10 29. "NCE_CH29,NCE_CH29" "0: Normal conversion is disabled for CH[29].,1: Normal conversion is enabled for CH[29]." bitfld.long 0x10 28. "NCE_CH28,NCE_CH28" "0: Normal conversion is disabled for CH[28].,1: Normal conversion is enabled for CH[28]." newline bitfld.long 0x10 27. "NCE_CH27,NCE_CH27" "0: Normal conversion is disabled for CH[27].,1: Normal conversion is enabled for CH[27]." bitfld.long 0x10 26. "NCE_CH26,NCE_CH26" "0: Normal conversion is disabled for CH[26].,1: Normal conversion is enabled for CH[26]." newline bitfld.long 0x10 25. "NCE_CH25,NCE_CH25" "0: Normal conversion is disabled for CH[25].,1: Normal conversion is enabled for CH[25]." bitfld.long 0x10 24. "NCE_CH24,NCE_CH24" "0: Normal conversion is disabled for CH[24].,1: Normal conversion is enabled for CH[24]." newline bitfld.long 0x10 23. "NCE_CH23,NCE_CH23" "0: Normal conversion is disabled for CH[23].,1: Normal conversion is enabled for CH[23]." bitfld.long 0x10 22. "NCE_CH22,NCE_CH22" "0: Normal conversion is disabled for CH[22].,1: Normal conversion is enabled for CH[22]." newline bitfld.long 0x10 21. "NCE_CH21,NCE_CH21" "0: Normal conversion is disabled for CH[21].,1: Normal conversion is enabled for CH[21]." bitfld.long 0x10 20. "NCE_CH20,NCE_CH20" "0: Normal conversion is disabled for CH[20].,1: Normal conversion is enabled for CH[20]." newline bitfld.long 0x10 19. "NCE_CH19,NCE_CH19" "0: Normal conversion is disabled for CH[19].,1: Normal conversion is enabled for CH[19]." bitfld.long 0x10 18. "NCE_CH18,NCE_CH18" "0: Normal conversion is disabled for CH[18].,1: Normal conversion is enabled for CH[18]." newline bitfld.long 0x10 17. "NCE_CH17,NCE_CH17" "0: Normal conversion is disabled for CH[17].,1: Normal conversion is enabled for CH[17]." bitfld.long 0x10 16. "NCE_CH16,NCE_CH16" "0: Normal conversion is disabled for CH[16].,1: Normal conversion is enabled for CH[16]." newline bitfld.long 0x10 15. "NCE_CH15,NCE_CH15" "0: Normal conversion is disabled for CH[15].,1: Normal conversion is enabled for CH[15]." bitfld.long 0x10 14. "NCE_CH14,NCE_CH14" "0: Normal conversion is disabled for CH[14].,1: Normal conversion is enabled for CH[14]." newline bitfld.long 0x10 13. "NCE_CH13,NCE_CH13" "0: Normal conversion is disabled for CH[13].,1: Normal conversion is enabled for CH[13]." bitfld.long 0x10 12. "NCE_CH12,NCE_CH12" "0: Normal conversion is disabled for CH[12].,1: Normal conversion is enabled for CH[12]." newline bitfld.long 0x10 11. "NCE_CH11,NCE_CH11" "0: Normal conversion is disabled for CH[11].,1: Normal conversion is enabled for CH[11]." bitfld.long 0x10 10. "NCE_CH10,NCE_CH10" "0: Normal conversion is disabled for CH[10].,1: Normal conversion is enabled for CH[10]." newline bitfld.long 0x10 9. "NCE_CH9,NCE_CH9" "0: Normal conversion is disabled for CH[9].,1: Normal conversion is enabled for CH[9]." bitfld.long 0x10 8. "NCE_CH8,NCE_CH8" "0: Normal conversion is disabled for CH[8].,1: Normal conversion is enabled for CH[8]." newline bitfld.long 0x10 7. "NCE_CH7,NCE_CH7" "0: Normal conversion is disabled for CH[7].,1: Normal conversion is enabled for CH[7]." bitfld.long 0x10 6. "NCE_CH6,NCE_CH6" "0: Normal conversion is disabled for CH[6].,1: Normal conversion is enabled for CH[6]." newline bitfld.long 0x10 5. "NCE_CH5,NCE_CH5" "0: Normal conversion is disabled for CH[5].,1: Normal conversion is enabled for CH[5]." bitfld.long 0x10 4. "NCE_CH4,NCE_CH4" "0: Normal conversion is disabled for CH[4].,1: Normal conversion is enabled for CH[4]." newline bitfld.long 0x10 3. "NCE_CH3,NCE_CH3" "0: Normal conversion is disabled for CH[3].,1: Normal conversion is enabled for CH[3]." bitfld.long 0x10 2. "NCE_CH2,NCE_CH2" "0: Normal conversion is disabled for CH[2].,1: Normal conversion is enabled for CH[2]." newline bitfld.long 0x10 1. "NCE_CH1,NCE_CH1" "0: Normal conversion is disabled for CH[1].,1: Normal conversion is enabled for CH[1]." bitfld.long 0x10 0. "NCE_CH0,NCE_CH0" "0: Normal conversion is disabled for CH[0].,1: Normal conversion is enabled for CH[0]." line.long 0x14 "ICNCMR1,Internal Channel Normal Conversion Mask Register 1" bitfld.long 0x14 31. "NCE_CH63,NCE_CH63" "0: Normal conversion is disabled for CH[63].,1: Normal conversion is enabled for CH[63]." bitfld.long 0x14 30. "NCE_CH62,NCE_CH62" "0: Normal conversion is disabled for CH[62].,1: Normal conversion is enabled for CH[62]." newline bitfld.long 0x14 29. "NCE_CH61,NCE_CH61" "0: Normal conversion is disabled for CH[61].,1: Normal conversion is enabled for CH[61]." bitfld.long 0x14 28. "NCE_CH60,NCE_CH60" "0: Normal conversion is disabled for CH[60].,1: Normal conversion is enabled for CH[60]." newline bitfld.long 0x14 27. "NCE_CH59,NCE_CH59" "0: Normal conversion is disabled for CH[59].,1: Normal conversion is enabled for CH[59]." bitfld.long 0x14 26. "NCE_CH58,NCE_CH58" "0: Normal conversion is disabled for CH[58].,1: Normal conversion is enabled for CH[58]." newline bitfld.long 0x14 25. "NCE_CH57,NCE_CH57" "0: Normal conversion is disabled for CH[57].,1: Normal conversion is enabled for CH[57]." bitfld.long 0x14 24. "NCE_CH56,NCE_CH56" "0: Normal conversion is disabled for CH[56].,1: Normal conversion is enabled for CH[56]." newline bitfld.long 0x14 23. "NCE_CH55,NCE_CH55" "0: Normal conversion is disabled for CH[55].,1: Normal conversion is enabled for CH[55]." bitfld.long 0x14 22. "NCE_CH54,NCE_CH54" "0: Normal conversion is disabled for CH[54].,1: Normal conversion is enabled for CH[54]." newline bitfld.long 0x14 21. "NCE_CH53,NCE_CH53" "0: Normal conversion is disabled for CH[53].,1: Normal conversion is enabled for CH[53]." bitfld.long 0x14 20. "NCE_CH52,NCE_CH52" "0: Normal conversion is disabled for CH[52].,1: Normal conversion is enabled for CH[52]." newline bitfld.long 0x14 19. "NCE_CH51,NCE_CH51" "0: Normal conversion is disabled for CH[51].,1: Normal conversion is enabled for CH[51]." bitfld.long 0x14 18. "NCE_CH50,NCE_CH50" "0: Normal conversion is disabled for CH[50].,1: Normal conversion is enabled for CH[50]." newline bitfld.long 0x14 17. "NCE_CH49,NCE_CH49" "0: Normal conversion is disabled for CH[49].,1: Normal conversion is enabled for CH[49]." bitfld.long 0x14 16. "NCE_CH48,NCE_CH48" "0: Normal conversion is disabled for CH[48].,1: Normal conversion is enabled for CH[48]." newline bitfld.long 0x14 15. "NCE_CH47,NCE_CH47" "0: Normal conversion is disabled for CH[47].,1: Normal conversion is enabled for CH[47]." bitfld.long 0x14 14. "NCE_CH46,NCE_CH46" "0: Normal conversion is disabled for CH[46].,1: Normal conversion is enabled for CH[46]." newline bitfld.long 0x14 13. "NCE_CH45,NCE_CH45" "0: Normal conversion is disabled for CH[45].,1: Normal conversion is enabled for CH[45]." bitfld.long 0x14 12. "NCE_CH44,NCE_CH44" "0: Normal conversion is disabled for CH[44].,1: Normal conversion is enabled for CH[44]." newline bitfld.long 0x14 11. "NCE_CH43,NCE_CH43" "0: Normal conversion is disabled for CH[43].,1: Normal conversion is enabled for CH[43]." bitfld.long 0x14 10. "NCE_CH42,NCE_CH42" "0: Normal conversion is disabled for CH[42].,1: Normal conversion is enabled for CH[42]." newline bitfld.long 0x14 9. "NCE_CH41,NCE_CH41" "0: Normal conversion is disabled for CH[41].,1: Normal conversion is enabled for CH[41]." bitfld.long 0x14 8. "NCE_CH40,NCE_CH40" "0: Normal conversion is disabled for CH[40].,1: Normal conversion is enabled for CH[40]." newline bitfld.long 0x14 7. "NCE_CH39,NCE_CH39" "0: Normal conversion is disabled for CH[39].,1: Normal conversion is enabled for CH[39]." bitfld.long 0x14 6. "NCE_CH38,NCE_CH38" "0: Normal conversion is disabled for CH[38].,1: Normal conversion is enabled for CH[38]." newline bitfld.long 0x14 5. "NCE_CH37,NCE_CH37" "0: Normal conversion is disabled for CH[37].,1: Normal conversion is enabled for CH[37]." bitfld.long 0x14 4. "NCE_CH36,NCE_CH36" "0: Normal conversion is disabled for CH[36].,1: Normal conversion is enabled for CH[36]." newline bitfld.long 0x14 3. "NCE_CH35,NCE_CH35" "0: Normal conversion is disabled for CH[35].,1: Normal conversion is enabled for CH[35]." bitfld.long 0x14 2. "NCE_CH34,NCE_CH34" "0: Normal conversion is disabled for CH[34].,1: Normal conversion is enabled for CH[34]." newline bitfld.long 0x14 1. "NCE_CH33,NCE_CH33" "0: Normal conversion is disabled for CH[33].,1: Normal conversion is enabled for CH[33]." bitfld.long 0x14 0. "NCE_CH32,NCE_CH32" "0: Normal conversion is disabled for CH[32].,1: Normal conversion is enabled for CH[32]." line.long 0x18 "ICNCMR2,Internal Channel Normal Conversion Mask Register 2" bitfld.long 0x18 31. "NCE_CH95,NCE_CH95" "0: Normal conversion is disabled for CH[95].,1: Normal conversion is enabled for CH[95]." bitfld.long 0x18 30. "NCE_CH94,NCE_CH94" "0: Normal conversion is disabled for CH[94].,1: Normal conversion is enabled for CH[94]." newline bitfld.long 0x18 29. "NCE_CH93,NCE_CH93" "0: Normal conversion is disabled for CH[93].,1: Normal conversion is enabled for CH[93]." bitfld.long 0x18 28. "NCE_CH92,NCE_CH92" "0: Normal conversion is disabled for CH[92].,1: Normal conversion is enabled for CH[92]." newline bitfld.long 0x18 27. "NCE_CH91,NCE_CH91" "0: Normal conversion is disabled for CH[91].,1: Normal conversion is enabled for CH[91]." bitfld.long 0x18 26. "NCE_CH90,NCE_CH90" "0: Normal conversion is disabled for CH[90].,1: Normal conversion is enabled for CH[90]." newline bitfld.long 0x18 25. "NCE_CH89,NCE_CH89" "0: Normal conversion is disabled for CH[89].,1: Normal conversion is enabled for CH[89]." bitfld.long 0x18 24. "NCE_CH88,NCE_CH88" "0: Normal conversion is disabled for CH[88].,1: Normal conversion is enabled for CH[88]." newline bitfld.long 0x18 23. "NCE_CH87,NCE_CH87" "0: Normal conversion is disabled for CH[87].,1: Normal conversion is enabled for CH[87]." bitfld.long 0x18 22. "NCE_CH86,NCE_CH86" "0: Normal conversion is disabled for CH[86].,1: Normal conversion is enabled for CH[86]." newline bitfld.long 0x18 21. "NCE_CH85,NCE_CH85" "0: Normal conversion is disabled for CH[85].,1: Normal conversion is enabled for CH[85]." bitfld.long 0x18 20. "NCE_CH84,NCE_CH84" "0: Normal conversion is disabled for CH[84].,1: Normal conversion is enabled for CH[84]." newline bitfld.long 0x18 19. "NCE_CH83,NCE_CH83" "0: Normal conversion is disabled for CH[83].,1: Normal conversion is enabled for CH[83]." bitfld.long 0x18 18. "NCE_CH82,NCE_CH82" "0: Normal conversion is disabled for CH[82].,1: Normal conversion is enabled for CH[82]." newline bitfld.long 0x18 17. "NCE_CH81,NCE_CH81" "0: Normal conversion is disabled for CH[81].,1: Normal conversion is enabled for CH[81]." bitfld.long 0x18 16. "NCE_CH80,NCE_CH80" "0: Normal conversion is disabled for CH[80].,1: Normal conversion is enabled for CH[80]." newline bitfld.long 0x18 15. "NCE_CH79,NCE_CH79" "0: Normal conversion is disabled for CH[79].,1: Normal conversion is enabled for CH[79]." bitfld.long 0x18 14. "NCE_CH78,NCE_CH78" "0: Normal conversion is disabled for CH[78].,1: Normal conversion is enabled for CH[78]." newline bitfld.long 0x18 13. "NCE_CH77,NCE_CH77" "0: Normal conversion is disabled for CH[77].,1: Normal conversion is enabled for CH[77]." bitfld.long 0x18 12. "NCE_CH76,NCE_CH76" "0: Normal conversion is disabled for CH[76].,1: Normal conversion is enabled for CH[76]." newline bitfld.long 0x18 11. "NCE_CH75,NCE_CH75" "0: Normal conversion is disabled for CH[75].,1: Normal conversion is enabled for CH[75]." bitfld.long 0x18 10. "NCE_CH74,NCE_CH74" "0: Normal conversion is disabled for CH[74].,1: Normal conversion is enabled for CH[74]." newline bitfld.long 0x18 9. "NCE_CH73,NCE_CH73" "0: Normal conversion is disabled for CH[73].,1: Normal conversion is enabled for CH[73]." bitfld.long 0x18 8. "NCE_CH72,NCE_CH72" "0: Normal conversion is disabled for CH[72].,1: Normal conversion is enabled for CH[72]." newline bitfld.long 0x18 7. "NCE_CH71,NCE_CH71" "0: Normal conversion is disabled for CH[71].,1: Normal conversion is enabled for CH[71]." bitfld.long 0x18 6. "NCE_CH70,NCE_CH70" "0: Normal conversion is disabled for CH[70].,1: Normal conversion is enabled for CH[70]." newline bitfld.long 0x18 5. "NCE_CH69,NCE_CH69" "0: Normal conversion is disabled for CH[69].,1: Normal conversion is enabled for CH[69]." bitfld.long 0x18 4. "NCE_CH68,NCE_CH68" "0: Normal conversion is disabled for CH[68].,1: Normal conversion is enabled for CH[68]." newline bitfld.long 0x18 3. "NCE_CH67,NCE_CH67" "0: Normal conversion is disabled for CH[67].,1: Normal conversion is enabled for CH[67]." bitfld.long 0x18 2. "NCE_CH66,NCE_CH66" "0: Normal conversion is disabled for CH[66].,1: Normal conversion is enabled for CH[66]." newline bitfld.long 0x18 1. "NCE_CH65,NCE_CH65" "0: Normal conversion is disabled for CH[65].,1: Normal conversion is enabled for CH[65]." bitfld.long 0x18 0. "NCE_CH64,NCE_CH64" "0: Normal conversion is disabled for CH[64].,1: Normal conversion is enabled for CH[64]." group.long 0xB4++0xB line.long 0x0 "ICJCMR0,Internal Channel Injected Conversion Mask Register 0" bitfld.long 0x0 31. "JCE_CH31,JCE_CH31" "0: Injected conversion is disabled for CH[31].,1: Injected conversion is enabled for CH[31]." bitfld.long 0x0 30. "JCE_CH30,JCE_CH30" "0: Injected conversion is disabled for CH[30].,1: Injected conversion is enabled for CH[30]." newline bitfld.long 0x0 29. "JCE_CH29,JCE_CH29" "0: Injected conversion is disabled for CH[29].,1: Injected conversion is enabled for CH[29]." bitfld.long 0x0 28. "JCE_CH28,JCE_CH28" "0: Injected conversion is disabled for CH[28].,1: Injected conversion is enabled for CH[28]." newline bitfld.long 0x0 27. "JCE_CH27,JCE_CH27" "0: Injected conversion is disabled for CH[27].,1: Injected conversion is enabled for CH[27]." bitfld.long 0x0 26. "JCE_CH26,JCE_CH26" "0: Injected conversion is disabled for CH[26].,1: Injected conversion is enabled for CH[26]." newline bitfld.long 0x0 25. "JCE_CH25,JCE_CH25" "0: Injected conversion is disabled for CH[25].,1: Injected conversion is enabled for CH[25]." bitfld.long 0x0 24. "JCE_CH24,JCE_CH24" "0: Injected conversion is disabled for CH[24].,1: Injected conversion is enabled for CH[24]." newline bitfld.long 0x0 23. "JCE_CH23,JCE_CH23" "0: Injected conversion is disabled for CH[23].,1: Injected conversion is enabled for CH[23]." bitfld.long 0x0 22. "JCE_CH22,JCE_CH22" "0: Injected conversion is disabled for CH[22].,1: Injected conversion is enabled for CH[22]." newline bitfld.long 0x0 21. "JCE_CH21,JCE_CH21" "0: Injected conversion is disabled for CH[21].,1: Injected conversion is enabled for CH[21]." bitfld.long 0x0 20. "JCE_CH20,JCE_CH20" "0: Injected conversion is disabled for CH[20].,1: Injected conversion is enabled for CH[20]." newline bitfld.long 0x0 19. "JCE_CH19,JCE_CH19" "0: Injected conversion is disabled for CH[19].,1: Injected conversion is enabled for CH[19]." bitfld.long 0x0 18. "JCE_CH18,JCE_CH18" "0: Injected conversion is disabled for CH[18].,1: Injected conversion is enabled for CH[18]." newline bitfld.long 0x0 17. "JCE_CH17,JCE_CH17" "0: Injected conversion is disabled for CH[17].,1: Injected conversion is enabled for CH[17]." bitfld.long 0x0 16. "JCE_CH16,JCE_CH16" "0: Injected conversion is disabled for CH[16].,1: Injected conversion is enabled for CH[16]." newline bitfld.long 0x0 15. "JCE_CH15,JCE_CH15" "0: Injected conversion is disabled for CH[15].,1: Injected conversion is enabled for CH[15]." bitfld.long 0x0 14. "JCE_CH14,JCE_CH14" "0: Injected conversion is disabled for CH[14].,1: Injected conversion is enabled for CH[14]." newline bitfld.long 0x0 13. "JCE_CH13,JCE_CH13" "0: Injected conversion is disabled for CH[13].,1: Injected conversion is enabled for CH[13]." bitfld.long 0x0 12. "JCE_CH12,JCE_CH12" "0: Injected conversion is disabled for CH[12].,1: Injected conversion is enabled for CH[12]." newline bitfld.long 0x0 11. "JCE_CH11,JCE_CH11" "0: Injected conversion is disabled for CH[11].,1: Injected conversion is enabled for CH[11]." bitfld.long 0x0 10. "JCE_CH10,JCE_CH10" "0: Injected conversion is disabled for CH[10].,1: Injected conversion is enabled for CH[10]." newline bitfld.long 0x0 9. "JCE_CH9,JCE_CH9" "0: Injected conversion is disabled for CH[9].,1: Injected conversion is enabled for CH[9]." bitfld.long 0x0 8. "JCE_CH8,JCE_CH8" "0: Injected conversion is disabled for CH[8].,1: Injected conversion is enabled for CH[8]." newline bitfld.long 0x0 7. "JCE_CH7,JCE_CH7" "0: Injected conversion is disabled for CH[7].,1: Injected conversion is enabled for CH[7]." bitfld.long 0x0 6. "JCE_CH6,JCE_CH6" "0: Injected conversion is disabled for CH[6].,1: Injected conversion is enabled for CH[6]." newline bitfld.long 0x0 5. "JCE_CH5,JCE_CH5" "0: Injected conversion is disabled for CH[5].,1: Injected conversion is enabled for CH[5]." bitfld.long 0x0 4. "JCE_CH4,JCE_CH4" "0: Injected conversion is disabled for CH[4].,1: Injected conversion is enabled for CH[4]." newline bitfld.long 0x0 3. "JCE_CH3,JCE_CH3" "0: Injected conversion is disabled for CH[3].,1: Injected conversion is enabled for CH[3]." bitfld.long 0x0 2. "JCE_CH2,JCE_CH2" "0: Injected conversion is disabled for CH[2].,1: Injected conversion is enabled for CH[2]." newline bitfld.long 0x0 1. "JCE_CH1,JCE_CH1" "0: Injected conversion is disabled for CH[1].,1: Injected conversion is enabled for CH[1]." bitfld.long 0x0 0. "JCE_CH0,JCE_CH0" "0: Injected conversion is disabled for CH[0].,1: Injected conversion is enabled for CH[0]." line.long 0x4 "ICJCMR1,Internal Channel Injected Conversion Mask Register 1" bitfld.long 0x4 31. "JCE_CH63,JCE_CH63" "0: Injected conversion is disabled for CH[63].,1: Injected conversion is enabled for CH[63]." bitfld.long 0x4 30. "JCE_CH62,JCE_CH62" "0: Injected conversion is disabled for CH[62].,1: Injected conversion is enabled for CH[62]." newline bitfld.long 0x4 29. "JCE_CH61,JCE_CH61" "0: Injected conversion is disabled for CH[61].,1: Injected conversion is enabled for CH[61]." bitfld.long 0x4 28. "JCE_CH60,JCE_CH60" "0: Injected conversion is disabled for CH[60].,1: Injected conversion is enabled for CH[60]." newline bitfld.long 0x4 27. "JCE_CH59,JCE_CH59" "0: Injected conversion is disabled for CH[59].,1: Injected conversion is enabled for CH[59]." bitfld.long 0x4 26. "JCE_CH58,JCE_CH58" "0: Injected conversion is disabled for CH[58].,1: Injected conversion is enabled for CH[58]." newline bitfld.long 0x4 25. "JCE_CH57,JCE_CH57" "0: Injected conversion is disabled for CH[57].,1: Injected conversion is enabled for CH[57]." bitfld.long 0x4 24. "JCE_CH56,JCE_CH56" "0: Injected conversion is disabled for CH[56].,1: Injected conversion is enabled for CH[56]." newline bitfld.long 0x4 23. "JCE_CH55,JCE_CH55" "0: Injected conversion is disabled for CH[55].,1: Injected conversion is enabled for CH[55]." bitfld.long 0x4 22. "JCE_CH54,JCE_CH54" "0: Injected conversion is disabled for CH[54].,1: Injected conversion is enabled for CH[54]." newline bitfld.long 0x4 21. "JCE_CH53,JCE_CH53" "0: Injected conversion is disabled for CH[53].,1: Injected conversion is enabled for CH[53]." bitfld.long 0x4 20. "JCE_CH52,JCE_CH52" "0: Injected conversion is disabled for CH[52].,1: Injected conversion is enabled for CH[52]." newline bitfld.long 0x4 19. "JCE_CH51,JCE_CH51" "0: Injected conversion is disabled for CH[51].,1: Injected conversion is enabled for CH[51]." bitfld.long 0x4 18. "JCE_CH50,JCE_CH50" "0: Injected conversion is disabled for CH[50].,1: Injected conversion is enabled for CH[50]." newline bitfld.long 0x4 17. "JCE_CH49,JCE_CH49" "0: Injected conversion is disabled for CH[49].,1: Injected conversion is enabled for CH[49]." bitfld.long 0x4 16. "JCE_CH48,JCE_CH48" "0: Injected conversion is disabled for CH[48].,1: Injected conversion is enabled for CH[48]." newline bitfld.long 0x4 15. "JCE_CH47,JCE_CH47" "0: Injected conversion is disabled for CH[47].,1: Injected conversion is enabled for CH[47]." bitfld.long 0x4 14. "JCE_CH46,JCE_CH46" "0: Injected conversion is disabled for CH[46].,1: Injected conversion is enabled for CH[46]." newline bitfld.long 0x4 13. "JCE_CH45,JCE_CH45" "0: Injected conversion is disabled for CH[45].,1: Injected conversion is enabled for CH[45]." bitfld.long 0x4 12. "JCE_CH44,JCE_CH44" "0: Injected conversion is disabled for CH[44].,1: Injected conversion is enabled for CH[44]." newline bitfld.long 0x4 11. "JCE_CH43,JCE_CH43" "0: Injected conversion is disabled for CH[43].,1: Injected conversion is enabled for CH[43]." bitfld.long 0x4 10. "JCE_CH42,JCE_CH42" "0: Injected conversion is disabled for CH[42].,1: Injected conversion is enabled for CH[42]." newline bitfld.long 0x4 9. "JCE_CH41,JCE_CH41" "0: Injected conversion is disabled for CH[41].,1: Injected conversion is enabled for CH[41]." bitfld.long 0x4 8. "JCE_CH40,JCE_CH40" "0: Injected conversion is disabled for CH[40].,1: Injected conversion is enabled for CH[40]." newline bitfld.long 0x4 7. "JCE_CH39,JCE_CH39" "0: Injected conversion is disabled for CH[39].,1: Injected conversion is enabled for CH[39]." bitfld.long 0x4 6. "JCE_CH38,JCE_CH38" "0: Injected conversion is disabled for CH[38].,1: Injected conversion is enabled for CH[38]." newline bitfld.long 0x4 5. "JCE_CH37,JCE_CH37" "0: Injected conversion is disabled for CH[37].,1: Injected conversion is enabled for CH[37]." bitfld.long 0x4 4. "JCE_CH36,JCE_CH36" "0: Injected conversion is disabled for CH[36].,1: Injected conversion is enabled for CH[36]." newline bitfld.long 0x4 3. "JCE_CH35,JCE_CH35" "0: Injected conversion is disabled for CH[35].,1: Injected conversion is enabled for CH[35]." bitfld.long 0x4 2. "JCE_CH34,JCE_CH34" "0: Injected conversion is disabled for CH[34].,1: Injected conversion is enabled for CH[34]." newline bitfld.long 0x4 1. "JCE_CH33,JCE_CH33" "0: Injected conversion is disabled for CH[33].,1: Injected conversion is enabled for CH[33]." bitfld.long 0x4 0. "JCE_CH32,JCE_CH32" "0: Injected conversion is disabled for CH[32].,1: Injected conversion is enabled for CH[32]." line.long 0x8 "ICJCMR2,Internal Channel Injected Conversion Mask Register 2" bitfld.long 0x8 31. "JCE_CH95,JCE_CH95" "0: Injected conversion is disabled for CH[95].,1: Injected conversion is enabled for CH[95]." bitfld.long 0x8 30. "JCE_CH94,JCE_CH94" "0: Injected conversion is disabled for CH[94].,1: Injected conversion is enabled for CH[94]." newline bitfld.long 0x8 29. "JCE_CH93,JCE_CH93" "0: Injected conversion is disabled for CH[93].,1: Injected conversion is enabled for CH[93]." bitfld.long 0x8 28. "JCE_CH92,JCE_CH92" "0: Injected conversion is disabled for CH[92].,1: Injected conversion is enabled for CH[92]." newline bitfld.long 0x8 27. "JCE_CH91,JCE_CH91" "0: Injected conversion is disabled for CH[91].,1: Injected conversion is enabled for CH[91]." bitfld.long 0x8 26. "JCE_CH90,JCE_CH90" "0: Injected conversion is disabled for CH[90].,1: Injected conversion is enabled for CH[90]." newline bitfld.long 0x8 25. "JCE_CH89,JCE_CH89" "0: Injected conversion is disabled for CH[89].,1: Injected conversion is enabled for CH[89]." bitfld.long 0x8 24. "JCE_CH88,JCE_CH88" "0: Injected conversion is disabled for CH[88].,1: Injected conversion is enabled for CH[88]." newline bitfld.long 0x8 23. "JCE_CH87,JCE_CH87" "0: Injected conversion is disabled for CH[87].,1: Injected conversion is enabled for CH[87]." bitfld.long 0x8 22. "JCE_CH86,JCE_CH86" "0: Injected conversion is disabled for CH[86].,1: Injected conversion is enabled for CH[86]." newline bitfld.long 0x8 21. "JCE_CH85,JCE_CH85" "0: Injected conversion is disabled for CH[85].,1: Injected conversion is enabled for CH[85]." bitfld.long 0x8 20. "JCE_CH84,JCE_CH84" "0: Injected conversion is disabled for CH[84].,1: Injected conversion is enabled for CH[84]." newline bitfld.long 0x8 19. "JCE_CH83,JCE_CH83" "0: Injected conversion is disabled for CH[83].,1: Injected conversion is enabled for CH[83]." bitfld.long 0x8 18. "JCE_CH82,JCE_CH82" "0: Injected conversion is disabled for CH[82].,1: Injected conversion is enabled for CH[82]." newline bitfld.long 0x8 17. "JCE_CH81,JCE_CH81" "0: Injected conversion is disabled for CH[81].,1: Injected conversion is enabled for CH[81]." bitfld.long 0x8 16. "JCE_CH80,JCE_CH80" "0: Injected conversion is disabled for CH[80].,1: Injected conversion is enabled for CH[80]." newline bitfld.long 0x8 15. "JCE_CH79,JCE_CH79" "0: Injected conversion is disabled for CH[79].,1: Injected conversion is enabled for CH[79]." bitfld.long 0x8 14. "JCE_CH78,JCE_CH78" "0: Injected conversion is disabled for CH[78].,1: Injected conversion is enabled for CH[78]." newline bitfld.long 0x8 13. "JCE_CH77,JCE_CH77" "0: Injected conversion is disabled for CH[77].,1: Injected conversion is enabled for CH[77]." bitfld.long 0x8 12. "JCE_CH76,JCE_CH76" "0: Injected conversion is disabled for CH[76].,1: Injected conversion is enabled for CH[76]." newline bitfld.long 0x8 11. "JCE_CH75,JCE_CH75" "0: Injected conversion is disabled for CH[75].,1: Injected conversion is enabled for CH[75]." bitfld.long 0x8 10. "JCE_CH74,JCE_CH74" "0: Injected conversion is disabled for CH[74].,1: Injected conversion is enabled for CH[74]." newline bitfld.long 0x8 9. "JCE_CH73,JCE_CH73" "0: Injected conversion is disabled for CH[73].,1: Injected conversion is enabled for CH[73]." bitfld.long 0x8 8. "JCE_CH72,JCE_CH72" "0: Injected conversion is disabled for CH[72].,1: Injected conversion is enabled for CH[72]." newline bitfld.long 0x8 7. "JCE_CH71,JCE_CH71" "0: Injected conversion is disabled for CH[71].,1: Injected conversion is enabled for CH[71]." bitfld.long 0x8 6. "JCE_CH70,JCE_CH70" "0: Injected conversion is disabled for CH[70].,1: Injected conversion is enabled for CH[70]." newline bitfld.long 0x8 5. "JCE_CH69,JCE_CH69" "0: Injected conversion is disabled for CH[69].,1: Injected conversion is enabled for CH[69]." bitfld.long 0x8 4. "JCE_CH68,JCE_CH68" "0: Injected conversion is disabled for CH[68].,1: Injected conversion is enabled for CH[68]." newline bitfld.long 0x8 3. "JCE_CH67,JCE_CH67" "0: Injected conversion is disabled for CH[67].,1: Injected conversion is enabled for CH[67]." bitfld.long 0x8 2. "JCE_CH66,JCE_CH66" "0: Injected conversion is disabled for CH[66].,1: Injected conversion is enabled for CH[66]." newline bitfld.long 0x8 1. "JCE_CH65,JCE_CH65" "0: Injected conversion is disabled for CH[65].,1: Injected conversion is enabled for CH[65]." bitfld.long 0x8 0. "JCE_CH64,JCE_CH64" "0: Injected conversion is disabled for CH[64].,1: Injected conversion is enabled for CH[64]." group.long 0xC8++0x3 line.long 0x0 "PDEDR,Power Down Exit Delay Register" hexmask.long.byte 0x0 0.--7. 1. "PDED,Defines the delay between the power-down bit reset and the starting of conversion." group.long 0x100++0x18F line.long 0x0 "ICDR0,Internal Channel Data Register 0" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4 "ICDR1,Internal Channel Data Register 1" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x8 "ICDR2,Internal Channel Data Register 2" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x8 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xC "ICDR3,Internal Channel Data Register 3" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xC 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x10 "ICDR4,Internal Channel Data Register 4" bitfld.long 0x10 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x10 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x10 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x10 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x10 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x10 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x10 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x14 "ICDR5,Internal Channel Data Register 5" bitfld.long 0x14 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x14 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x14 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x14 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x14 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x14 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x14 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x18 "ICDR6,Internal Channel Data Register 6" bitfld.long 0x18 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x18 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x18 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x18 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x18 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x18 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x18 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x1C "ICDR7,Internal Channel Data Register 7" bitfld.long 0x1C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x1C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x1C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x1C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x1C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x1C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x1C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x20 "ICDR8,Internal Channel Data Register 8" bitfld.long 0x20 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x20 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x20 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x20 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x20 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x20 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x20 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x24 "ICDR9,Internal Channel Data Register 9" bitfld.long 0x24 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x24 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x24 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x24 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x24 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x24 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x24 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x28 "ICDR10,Internal Channel Data Register 10" bitfld.long 0x28 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x28 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x28 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x28 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x28 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x28 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x28 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x2C "ICDR11,Internal Channel Data Register 11" bitfld.long 0x2C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x2C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x2C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x2C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x2C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x2C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x2C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x30 "ICDR12,Internal Channel Data Register 12" bitfld.long 0x30 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x30 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x30 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x30 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x30 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x30 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x30 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x34 "ICDR13,Internal Channel Data Register 13" bitfld.long 0x34 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x34 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x34 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x34 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x34 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x34 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x34 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x38 "ICDR14,Internal Channel Data Register 14" bitfld.long 0x38 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x38 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x38 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x38 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x38 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x38 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x38 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x3C "ICDR15,Internal Channel Data Register 15" bitfld.long 0x3C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x3C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x3C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x3C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x3C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x3C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x3C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x40 "ICDR16,Internal Channel Data Register 16" bitfld.long 0x40 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x40 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x40 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x40 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x40 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x40 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x40 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x44 "ICDR17,Internal Channel Data Register 17" bitfld.long 0x44 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x44 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x44 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x44 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x44 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x44 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x44 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x48 "ICDR18,Internal Channel Data Register 18" bitfld.long 0x48 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x48 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x48 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x48 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x48 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x48 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x48 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4C "ICDR19,Internal Channel Data Register 19" bitfld.long 0x4C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x50 "ICDR20,Internal Channel Data Register 20" bitfld.long 0x50 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x50 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x50 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x50 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x50 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x50 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x50 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x54 "ICDR21,Internal Channel Data Register 21" bitfld.long 0x54 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x54 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x54 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x54 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x54 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x54 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x54 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x58 "ICDR22,Internal Channel Data Register 22" bitfld.long 0x58 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x58 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x58 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x58 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x58 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x58 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x58 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x5C "ICDR23,Internal Channel Data Register 23" bitfld.long 0x5C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x5C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x5C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x5C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x5C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x5C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x5C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x60 "ICDR24,Internal Channel Data Register 24" bitfld.long 0x60 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x60 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x60 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x60 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x60 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x60 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x60 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x64 "ICDR25,Internal Channel Data Register 25" bitfld.long 0x64 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x64 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x64 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x64 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x64 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x64 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x64 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x68 "ICDR26,Internal Channel Data Register 26" bitfld.long 0x68 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x68 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x68 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x68 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x68 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x68 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x68 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x6C "ICDR27,Internal Channel Data Register 27" bitfld.long 0x6C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x6C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x6C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x6C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x6C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x6C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x6C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x70 "ICDR28,Internal Channel Data Register 28" bitfld.long 0x70 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x70 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x70 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x70 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x70 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x70 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x70 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x74 "ICDR29,Internal Channel Data Register 29" bitfld.long 0x74 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x74 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x74 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x74 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x74 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x74 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x74 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x78 "ICDR30,Internal Channel Data Register 30" bitfld.long 0x78 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x78 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x78 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x78 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x78 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x78 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x78 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x7C "ICDR31,Internal Channel Data Register 31" bitfld.long 0x7C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x7C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x7C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x7C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x7C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x7C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x7C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x80 "ICDR32,Internal Channel Data Register 32" bitfld.long 0x80 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x80 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x80 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x80 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x80 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x80 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x80 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x84 "ICDR33,Internal Channel Data Register 33" bitfld.long 0x84 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x84 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x84 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x84 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x84 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x84 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x84 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x88 "ICDR34,Internal Channel Data Register 34" bitfld.long 0x88 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x88 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x88 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x88 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x88 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x88 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x88 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x8C "ICDR35,Internal Channel Data Register 35" bitfld.long 0x8C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x8C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x8C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x8C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x8C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x90 "ICDR36,Internal Channel Data Register 36" bitfld.long 0x90 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x90 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x90 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x90 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x90 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x90 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x90 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x94 "ICDR37,Internal Channel Data Register 37" bitfld.long 0x94 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x94 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x94 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x94 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x94 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x94 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x94 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x98 "ICDR38,Internal Channel Data Register 38" bitfld.long 0x98 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x98 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x98 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x98 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x98 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x98 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x98 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x9C "ICDR39,Internal Channel Data Register 39" bitfld.long 0x9C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x9C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x9C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x9C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x9C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x9C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x9C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xA0 "ICDR40,Internal Channel Data Register 40" bitfld.long 0xA0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xA0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xA0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xA0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xA0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xA0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xA0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xA4 "ICDR41,Internal Channel Data Register 41" bitfld.long 0xA4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xA4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xA4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xA4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xA4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xA4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xA4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xA8 "ICDR42,Internal Channel Data Register 42" bitfld.long 0xA8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xA8 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xA8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xA8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xA8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xA8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xA8 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xAC "ICDR43,Internal Channel Data Register 43" bitfld.long 0xAC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xAC 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xAC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xAC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xAC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xAC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xAC 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xB0 "ICDR44,Internal Channel Data Register 44" bitfld.long 0xB0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xB0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xB0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xB0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xB0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xB0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xB0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xB4 "ICDR45,Internal Channel Data Register 45" bitfld.long 0xB4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xB4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xB4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xB4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xB4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xB4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xB4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xB8 "ICDR46,Internal Channel Data Register 46" bitfld.long 0xB8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xB8 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xB8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xB8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xB8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xB8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xB8 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xBC "ICDR47,Internal Channel Data Register 47" bitfld.long 0xBC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xBC 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xBC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xBC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xBC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xBC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xBC 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xC0 "ICDR48,Internal Channel Data Register 48" bitfld.long 0xC0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xC0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xC0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xC0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xC0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xC4 "ICDR49,Internal Channel Data Register 49" bitfld.long 0xC4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xC4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xC4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xC4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xC4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xC8 "ICDR50,Internal Channel Data Register 50" bitfld.long 0xC8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xC8 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xC8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xC8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xC8 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xCC "ICDR51,Internal Channel Data Register 51" bitfld.long 0xCC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xCC 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xCC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xCC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xCC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xCC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xCC 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xD0 "ICDR52,Internal Channel Data Register 52" bitfld.long 0xD0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xD0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xD0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xD0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xD0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xD0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xD0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xD4 "ICDR53,Internal Channel Data Register 53" bitfld.long 0xD4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xD4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xD4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xD4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xD4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xD4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xD4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xD8 "ICDR54,Internal Channel Data Register 54" bitfld.long 0xD8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xD8 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xD8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xD8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xD8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xD8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xD8 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xDC "ICDR55,Internal Channel Data Register 55" bitfld.long 0xDC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xDC 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xDC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xDC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xDC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xDC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xDC 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xE0 "ICDR56,Internal Channel Data Register 56" bitfld.long 0xE0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xE0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xE0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xE0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xE0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xE0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xE0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xE4 "ICDR57,Internal Channel Data Register 57" bitfld.long 0xE4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xE4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xE4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xE4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xE4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xE4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xE4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xE8 "ICDR58,Internal Channel Data Register 58" bitfld.long 0xE8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xE8 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xE8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xE8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xE8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xE8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xE8 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xEC "ICDR59,Internal Channel Data Register 59" bitfld.long 0xEC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xEC 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xEC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xEC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xEC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xEC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xEC 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xF0 "ICDR60,Internal Channel Data Register 60" bitfld.long 0xF0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xF0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xF0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xF0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xF0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xF0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xF0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xF4 "ICDR61,Internal Channel Data Register 61" bitfld.long 0xF4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xF4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xF4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xF4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xF4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xF4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xF4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xF8 "ICDR62,Internal Channel Data Register 62" bitfld.long 0xF8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xF8 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xF8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xF8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xF8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xF8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xF8 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xFC "ICDR63,Internal Channel Data Register 63" bitfld.long 0xFC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xFC 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xFC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xFC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xFC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xFC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xFC 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x100 "ICDR64,Internal Channel Data Register 64" bitfld.long 0x100 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x100 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x100 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x100 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x100 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x100 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x100 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x104 "ICDR65,Internal Channel Data Register 65" bitfld.long 0x104 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x104 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x104 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x104 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x104 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x104 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x104 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x108 "ICDR66,Internal Channel Data Register 66" bitfld.long 0x108 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x108 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x108 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x108 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x108 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x108 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x108 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x10C "ICDR67,Internal Channel Data Register 67" bitfld.long 0x10C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x10C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x10C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x10C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x10C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x10C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x10C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x110 "ICDR68,Internal Channel Data Register 68" bitfld.long 0x110 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x110 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x110 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x110 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x110 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x110 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x110 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x114 "ICDR69,Internal Channel Data Register 69" bitfld.long 0x114 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x114 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x114 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x114 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x114 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x114 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x114 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x118 "ICDR70,Internal Channel Data Register 70" bitfld.long 0x118 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x118 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x118 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x118 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x118 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x118 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x118 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x11C "ICDR71,Internal Channel Data Register 71" bitfld.long 0x11C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x11C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x11C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x11C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x11C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x11C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x11C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x120 "ICDR72,Internal Channel Data Register 72" bitfld.long 0x120 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x120 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x120 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x120 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x120 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x120 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x120 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x124 "ICDR73,Internal Channel Data Register 73" bitfld.long 0x124 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x124 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x124 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x124 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x124 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x124 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x124 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x128 "ICDR74,Internal Channel Data Register 74" bitfld.long 0x128 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x128 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x128 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x128 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x128 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x128 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x128 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x12C "ICDR75,Internal Channel Data Register 75" bitfld.long 0x12C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x12C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x12C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x12C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x12C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x12C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x12C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x130 "ICDR76,Internal Channel Data Register 76" bitfld.long 0x130 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x130 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x130 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x130 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x130 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x130 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x130 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x134 "ICDR77,Internal Channel Data Register 77" bitfld.long 0x134 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x134 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x134 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x134 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x134 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x134 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x134 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x138 "ICDR78,Internal Channel Data Register 78" bitfld.long 0x138 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x138 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x138 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x138 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x138 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x138 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x138 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x13C "ICDR79,Internal Channel Data Register 79" bitfld.long 0x13C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x13C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x13C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x13C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x13C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x13C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x13C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x140 "ICDR80,Internal Channel Data Register 80" bitfld.long 0x140 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x140 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x140 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x140 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x140 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x140 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x140 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x144 "ICDR81,Internal Channel Data Register 81" bitfld.long 0x144 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x144 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x144 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x144 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x144 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x144 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x144 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x148 "ICDR82,Internal Channel Data Register 82" bitfld.long 0x148 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x148 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x148 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x148 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x148 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x148 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x148 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x14C "ICDR83,Internal Channel Data Register 83" bitfld.long 0x14C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x14C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x14C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x14C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x14C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x14C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x14C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x150 "ICDR84,Internal Channel Data Register 84" bitfld.long 0x150 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x150 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x150 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x150 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x150 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x150 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x150 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x154 "ICDR85,Internal Channel Data Register 85" bitfld.long 0x154 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x154 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x154 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x154 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x154 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x154 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x154 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x158 "ICDR86,Internal Channel Data Register 86" bitfld.long 0x158 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x158 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x158 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x158 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x158 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x158 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x158 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x15C "ICDR87,Internal Channel Data Register 87" bitfld.long 0x15C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x15C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x15C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x15C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x15C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x15C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x15C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x160 "ICDR88,Internal Channel Data Register 88" bitfld.long 0x160 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x160 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x160 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x160 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x160 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x160 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x160 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x164 "ICDR89,Internal Channel Data Register 89" bitfld.long 0x164 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x164 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x164 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x164 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x164 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x164 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x164 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x168 "ICDR90,Internal Channel Data Register 90" bitfld.long 0x168 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x168 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x168 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x168 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x168 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x168 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x168 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x16C "ICDR91,Internal Channel Data Register 91" bitfld.long 0x16C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x16C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x16C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x16C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x16C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x16C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x16C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x170 "ICDR92,Internal Channel Data Register 92" bitfld.long 0x170 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x170 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x170 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x170 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x170 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x170 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x170 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x174 "ICDR93,Internal Channel Data Register 93" bitfld.long 0x174 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x174 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x174 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x174 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x174 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x174 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x174 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x178 "ICDR94,Internal Channel Data Register 94" bitfld.long 0x178 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x178 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x178 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x178 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x178 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x178 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x178 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x17C "ICDR95,Internal Channel Data Register 95" bitfld.long 0x17C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x17C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x17C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x17C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x17C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x17C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x17C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x180 "WTHRHLR4,Watchdog Threshold Register _m_" hexmask.long.word 0x180 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x180 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x184 "WTHRHLR5,Watchdog Threshold Register _m_" hexmask.long.word 0x184 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x184 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x188 "WTHRHLR6,Watchdog Threshold Register _m_" hexmask.long.word 0x188 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x188 0.--11. 1. "THRL,Low threshold value for channel x" line.long 0x18C "WTHRHLR7,Watchdog Threshold Register _m_" hexmask.long.word 0x18C 16.--27. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x18C 0.--11. 1. "THRL,Low threshold value for channel x" group.long 0x2B0++0x3B line.long 0x0 "ICWSELR0,Internal Channel Watchdog Select Register 0" bitfld.long 0x0 28.--30. "WSEL_CH7,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "WSEL_CH6,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "WSEL_CH5,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "WSEL_CH4,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "WSEL_CH3,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "WSEL_CH2,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "WSEL_CH1,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "WSEL_CH0,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" line.long 0x4 "ICWSELR1,Internal Channel Watchdog Select Register 1" bitfld.long 0x4 28.--30. "WSEL_CH15,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "WSEL_CH14,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20.--22. "WSEL_CH13,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "WSEL_CH12,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12.--14. "WSEL_CH11,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "WSEL_CH10,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "WSEL_CH9,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "WSEL_CH8,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" line.long 0x8 "ICWSELR2,Internal Channel Watchdog Select Register 2" bitfld.long 0x8 28.--30. "WSEL_CH23,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "WSEL_CH22,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20.--22. "WSEL_CH21,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "WSEL_CH20,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 12.--14. "WSEL_CH19,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "WSEL_CH18,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4.--6. "WSEL_CH17,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "WSEL_CH16,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" line.long 0xC "ICWSELR3,Internal Channel Watchdog Select Register 3" bitfld.long 0xC 28.--30. "WSEL_CH31,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "WSEL_CH30,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 20.--22. "WSEL_CH29,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "WSEL_CH28,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "WSEL_CH27,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--10. "WSEL_CH26,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4.--6. "WSEL_CH25,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "WSEL_CH24,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" line.long 0x10 "ICWSELR4,Internal Channel Watchdog Select Register 4" bitfld.long 0x10 28.--30. "WSEL_CH39,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "WSEL_CH38,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 20.--22. "WSEL_CH37,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "WSEL_CH36,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 12.--14. "WSEL_CH35,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8.--10. "WSEL_CH34,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 4.--6. "WSEL_CH33,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "WSEL_CH32,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" line.long 0x14 "ICWSELR5,Internal Channel Watchdog Select Register 5" bitfld.long 0x14 28.--30. "WSEL_CH47,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "WSEL_CH46,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 20.--22. "WSEL_CH45,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "WSEL_CH44,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "WSEL_CH43,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x14 8.--10. "WSEL_CH42,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 4.--6. "WSEL_CH41,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "WSEL_CH40,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" line.long 0x18 "ICWSELR6,Internal Channel Watchdog Select Register 6" bitfld.long 0x18 28.--30. "WSEL_CH55,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "WSEL_CH54,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 20.--22. "WSEL_CH53,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "WSEL_CH52,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "WSEL_CH51,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x18 8.--10. "WSEL_CH50,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 4.--6. "WSEL_CH49,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "WSEL_CH48,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" line.long 0x1C "ICWSELR7,Internal Channel Watchdog Select Register 7" bitfld.long 0x1C 28.--30. "WSEL_CH63,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--26. "WSEL_CH62,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 20.--22. "WSEL_CH61,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 16.--18. "WSEL_CH60,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 12.--14. "WSEL_CH59,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 8.--10. "WSEL_CH58,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 4.--6. "WSEL_CH57,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "WSEL_CH56,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" line.long 0x20 "ICWSELR8,Internal Channel Watchdog Select Register 8" bitfld.long 0x20 28.--30. "WSEL_CH71,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x20 24.--26. "WSEL_CH70,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 20.--22. "WSEL_CH69,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x20 16.--18. "WSEL_CH68,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 12.--14. "WSEL_CH67,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x20 8.--10. "WSEL_CH66,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 4.--6. "WSEL_CH65,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x20 0.--2. "WSEL_CH64,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" line.long 0x24 "ICWSELR9,Internal Channel Watchdog Select Register 9" bitfld.long 0x24 28.--30. "WSEL_CH79,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x24 24.--26. "WSEL_CH78,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 20.--22. "WSEL_CH77,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x24 16.--18. "WSEL_CH76,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 12.--14. "WSEL_CH75,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x24 8.--10. "WSEL_CH74,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 4.--6. "WSEL_CH73,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--2. "WSEL_CH72,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" line.long 0x28 "ICWSELR10,Internal Channel Watchdog Select Register 10" bitfld.long 0x28 28.--30. "WSEL_CH87,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x28 24.--26. "WSEL_CH86,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 20.--22. "WSEL_CH85,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x28 16.--18. "WSEL_CH84,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 12.--14. "WSEL_CH83,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x28 8.--10. "WSEL_CH82,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 4.--6. "WSEL_CH81,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x28 0.--2. "WSEL_CH80,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" line.long 0x2C "ICWSELR11,Internal Channel Watchdog Select Register 11" bitfld.long 0x2C 28.--30. "WSEL_CH95,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 24.--26. "WSEL_CH94,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 20.--22. "WSEL_CH93,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 16.--18. "WSEL_CH92,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 12.--14. "WSEL_CH91,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 8.--10. "WSEL_CH90,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 4.--6. "WSEL_CH89,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 0.--2. "WSEL_CH88,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" line.long 0x30 "ICWENR0,Internal Channel Watchdog Enable Register 0" bitfld.long 0x30 31. "WEN_CH31,WEN_CH31" "0: Watchdog feature is disabled for CH[31],1: Watchdog feature is enabled fir CH[31]" bitfld.long 0x30 30. "WEN_CH30,WEN_CH30" "0: Watchdog feature is disabled for CH[30],1: Watchdog feature is enabled fir CH[30]" newline bitfld.long 0x30 29. "WEN_CH29,WEN_CH29" "0: Watchdog feature is disabled for CH[29],1: Watchdog feature is enabled fir CH[29]" bitfld.long 0x30 28. "WEN_CH28,WEN_CH28" "0: Watchdog feature is disabled for CH[28],1: Watchdog feature is enabled fir CH[28]" newline bitfld.long 0x30 27. "WEN_CH27,WEN_CH27" "0: Watchdog feature is disabled for CH[27],1: Watchdog feature is enabled fir CH[27]" bitfld.long 0x30 26. "WEN_CH26,WEN_CH26" "0: Watchdog feature is disabled for CH[26],1: Watchdog feature is enabled fir CH[26]" newline bitfld.long 0x30 25. "WEN_CH25,WEN_CH25" "0: Watchdog feature is disabled for CH[25],1: Watchdog feature is enabled fir CH[25]" bitfld.long 0x30 24. "WEN_CH24,WEN_CH24" "0: Watchdog feature is disabled for CH[24],1: Watchdog feature is enabled fir CH[24]" newline bitfld.long 0x30 23. "WEN_CH23,WEN_CH23" "0: Watchdog feature is disabled for CH[23],1: Watchdog feature is enabled fir CH[23]" bitfld.long 0x30 22. "WEN_CH22,WEN_CH22" "0: Watchdog feature is disabled for CH[22],1: Watchdog feature is enabled fir CH[22]" newline bitfld.long 0x30 21. "WEN_CH21,WEN_CH21" "0: Watchdog feature is disabled for CH[21],1: Watchdog feature is enabled fir CH[21]" bitfld.long 0x30 20. "WEN_CH20,WEN_CH20" "0: Watchdog feature is disabled for CH[20],1: Watchdog feature is enabled fir CH[20]" newline bitfld.long 0x30 19. "WEN_CH19,WEN_CH19" "0: Watchdog feature is disabled for CH[19],1: Watchdog feature is enabled fir CH[19]" bitfld.long 0x30 18. "WEN_CH18,WEN_CH18" "0: Watchdog feature is disabled for CH[18],1: Watchdog feature is enabled fir CH[18]" newline bitfld.long 0x30 17. "WEN_CH17,WEN_CH17" "0: Watchdog feature is disabled for CH[17],1: Watchdog feature is enabled fir CH[17]" bitfld.long 0x30 16. "WEN_CH16,WEN_CH16" "0: Watchdog feature is disabled for CH[16],1: Watchdog feature is enabled fir CH[16]" newline bitfld.long 0x30 15. "WEN_CH15,WEN_CH15" "0: Watchdog feature is disabled for CH[15],1: Watchdog feature is enabled fir CH[15]" bitfld.long 0x30 14. "WEN_CH14,WEN_CH14" "0: Watchdog feature is disabled for CH[14],1: Watchdog feature is enabled fir CH[14]" newline bitfld.long 0x30 13. "WEN_CH13,WEN_CH13" "0: Watchdog feature is disabled for CH[13],1: Watchdog feature is enabled fir CH[13]" bitfld.long 0x30 12. "WEN_CH12,WEN_CH12" "0: Watchdog feature is disabled for CH[12],1: Watchdog feature is enabled fir CH[12]" newline bitfld.long 0x30 11. "WEN_CH11,WEN_CH11" "0: Watchdog feature is disabled for CH[11],1: Watchdog feature is enabled fir CH[11]" bitfld.long 0x30 10. "WEN_CH10,WEN_CH10" "0: Watchdog feature is disabled for CH[10],1: Watchdog feature is enabled fir CH[10]" newline bitfld.long 0x30 9. "WEN_CH9,WEN_CH9" "0: Watchdog feature is disabled for CH[9],1: Watchdog feature is enabled fir CH[9]" bitfld.long 0x30 8. "WEN_CH8,WEN_CH8" "0: Watchdog feature is disabled for CH[8],1: Watchdog feature is enabled fir CH[8]" newline bitfld.long 0x30 7. "WEN_CH7,WEN_CH7" "0: Watchdog feature is disabled for CH[7],1: Watchdog feature is enabled fir CH[7]" bitfld.long 0x30 6. "WEN_CH6,WEN_CH6" "0: Watchdog feature is disabled for CH[6],1: Watchdog feature is enabled fir CH[6]" newline bitfld.long 0x30 5. "WEN_CH5,WEN_CH5" "0: Watchdog feature is disabled for CH[5],1: Watchdog feature is enabled fir CH[5]" bitfld.long 0x30 4. "WEN_CH4,WEN_CH4" "0: Watchdog feature is disabled for CH[4],1: Watchdog feature is enabled fir CH[4]" newline bitfld.long 0x30 3. "WEN_CH3,WEN_CH3" "0: Watchdog feature is disabled for CH[3],1: Watchdog feature is enabled fir CH[3]" bitfld.long 0x30 2. "WEN_CH2,WEN_CH2" "0: Watchdog feature is disabled for CH[2],1: Watchdog feature is enabled fir CH[2]" newline bitfld.long 0x30 1. "WEN_CH1,WEN_CH1" "0: Watchdog feature is disabled for CH[1],1: Watchdog feature is enabled fir CH[1]" bitfld.long 0x30 0. "WEN_CH0,WEN_CH0" "0: Watchdog feature is disabled for CH[0],1: Watchdog feature is enabled fir CH[0]" line.long 0x34 "ICWENR1,Internal Channel Watchdog Enable Register 1" bitfld.long 0x34 31. "WEN_CH63,WEN_CH63" "0: Watchdog feature is disabled for CH[63],1: Watchdog feature is enabled fir CH[63]" bitfld.long 0x34 30. "WEN_CH62,WEN_CH62" "0: Watchdog feature is disabled for CH[62],1: Watchdog feature is enabled fir CH[62]" newline bitfld.long 0x34 29. "WEN_CH61,WEN_CH61" "0: Watchdog feature is disabled for CH[61],1: Watchdog feature is enabled fir CH[61]" bitfld.long 0x34 28. "WEN_CH60,WEN_CH60" "0: Watchdog feature is disabled for CH[60],1: Watchdog feature is enabled fir CH[60]" newline bitfld.long 0x34 27. "WEN_CH59,WEN_CH59" "0: Watchdog feature is disabled for CH[59],1: Watchdog feature is enabled fir CH[59]" bitfld.long 0x34 26. "WEN_CH58,WEN_CH58" "0: Watchdog feature is disabled for CH[58],1: Watchdog feature is enabled fir CH[58]" newline bitfld.long 0x34 25. "WEN_CH57,WEN_CH57" "0: Watchdog feature is disabled for CH[57],1: Watchdog feature is enabled fir CH[57]" bitfld.long 0x34 24. "WEN_CH56,WEN_CH56" "0: Watchdog feature is disabled for CH[56],1: Watchdog feature is enabled fir CH[56]" newline bitfld.long 0x34 23. "WEN_CH55,WEN_CH55" "0: Watchdog feature is disabled for CH[55],1: Watchdog feature is enabled fir CH[55]" bitfld.long 0x34 22. "WEN_CH54,WEN_CH54" "0: Watchdog feature is disabled for CH[54],1: Watchdog feature is enabled fir CH[54]" newline bitfld.long 0x34 21. "WEN_CH53,WEN_CH53" "0: Watchdog feature is disabled for CH[53],1: Watchdog feature is enabled fir CH[53]" bitfld.long 0x34 20. "WEN_CH52,WEN_CH52" "0: Watchdog feature is disabled for CH[52],1: Watchdog feature is enabled fir CH[52]" newline bitfld.long 0x34 19. "WEN_CH51,WEN_CH51" "0: Watchdog feature is disabled for CH[51],1: Watchdog feature is enabled fir CH[51]" bitfld.long 0x34 18. "WEN_CH50,WEN_CH50" "0: Watchdog feature is disabled for CH[50],1: Watchdog feature is enabled fir CH[50]" newline bitfld.long 0x34 17. "WEN_CH49,WEN_CH49" "0: Watchdog feature is disabled for CH[49],1: Watchdog feature is enabled fir CH[49]" bitfld.long 0x34 16. "WEN_CH48,WEN_CH48" "0: Watchdog feature is disabled for CH[48],1: Watchdog feature is enabled fir CH[48]" newline bitfld.long 0x34 15. "WEN_CH47,WEN_CH47" "0: Watchdog feature is disabled for CH[47],1: Watchdog feature is enabled fir CH[47]" bitfld.long 0x34 14. "WEN_CH46,WEN_CH46" "0: Watchdog feature is disabled for CH[46],1: Watchdog feature is enabled fir CH[46]" newline bitfld.long 0x34 13. "WEN_CH45,WEN_CH45" "0: Watchdog feature is disabled for CH[45],1: Watchdog feature is enabled fir CH[45]" bitfld.long 0x34 12. "WEN_CH44,WEN_CH44" "0: Watchdog feature is disabled for CH[44],1: Watchdog feature is enabled fir CH[44]" newline bitfld.long 0x34 11. "WEN_CH43,WEN_CH43" "0: Watchdog feature is disabled for CH[43],1: Watchdog feature is enabled fir CH[43]" bitfld.long 0x34 10. "WEN_CH42,WEN_CH42" "0: Watchdog feature is disabled for CH[42],1: Watchdog feature is enabled fir CH[42]" newline bitfld.long 0x34 9. "WEN_CH41,WEN_CH41" "0: Watchdog feature is disabled for CH[41],1: Watchdog feature is enabled fir CH[41]" bitfld.long 0x34 8. "WEN_CH40,WEN_CH40" "0: Watchdog feature is disabled for CH[40],1: Watchdog feature is enabled fir CH[40]" newline bitfld.long 0x34 7. "WEN_CH39,WEN_CH39" "0: Watchdog feature is disabled for CH[39],1: Watchdog feature is enabled fir CH[39]" bitfld.long 0x34 6. "WEN_CH38,WEN_CH38" "0: Watchdog feature is disabled for CH[38],1: Watchdog feature is enabled fir CH[38]" newline bitfld.long 0x34 5. "WEN_CH37,WEN_CH37" "0: Watchdog feature is disabled for CH[37],1: Watchdog feature is enabled fir CH[37]" bitfld.long 0x34 4. "WEN_CH36,WEN_CH36" "0: Watchdog feature is disabled for CH[36],1: Watchdog feature is enabled fir CH[36]" newline bitfld.long 0x34 3. "WEN_CH35,WEN_CH35" "0: Watchdog feature is disabled for CH[35],1: Watchdog feature is enabled fir CH[35]" bitfld.long 0x34 2. "WEN_CH34,WEN_CH34" "0: Watchdog feature is disabled for CH[34],1: Watchdog feature is enabled fir CH[34]" newline bitfld.long 0x34 1. "WEN_CH33,WEN_CH33" "0: Watchdog feature is disabled for CH[33],1: Watchdog feature is enabled fir CH[33]" bitfld.long 0x34 0. "WEN_CH32,WEN_CH32" "0: Watchdog feature is disabled for CH[32],1: Watchdog feature is enabled fir CH[32]" line.long 0x38 "ICWENR2,Internal Channel Watchdog Enable Register 2" bitfld.long 0x38 31. "WEN_CH95,WEN_CH95" "0: Watchdog feature is disabled for CH[95],1: Watchdog feature is enabled fir CH[95]" bitfld.long 0x38 30. "WEN_CH94,WEN_CH94" "0: Watchdog feature is disabled for CH[94],1: Watchdog feature is enabled fir CH[94]" newline bitfld.long 0x38 29. "WEN_CH93,WEN_CH93" "0: Watchdog feature is disabled for CH[93],1: Watchdog feature is enabled fir CH[93]" bitfld.long 0x38 28. "WEN_CH92,WEN_CH92" "0: Watchdog feature is disabled for CH[92],1: Watchdog feature is enabled fir CH[92]" newline bitfld.long 0x38 27. "WEN_CH91,WEN_CH91" "0: Watchdog feature is disabled for CH[91],1: Watchdog feature is enabled fir CH[91]" bitfld.long 0x38 26. "WEN_CH90,WEN_CH90" "0: Watchdog feature is disabled for CH[90],1: Watchdog feature is enabled fir CH[90]" newline bitfld.long 0x38 25. "WEN_CH89,WEN_CH89" "0: Watchdog feature is disabled for CH[89],1: Watchdog feature is enabled fir CH[89]" bitfld.long 0x38 24. "WEN_CH88,WEN_CH88" "0: Watchdog feature is disabled for CH[88],1: Watchdog feature is enabled fir CH[88]" newline bitfld.long 0x38 23. "WEN_CH87,WEN_CH87" "0: Watchdog feature is disabled for CH[87],1: Watchdog feature is enabled fir CH[87]" bitfld.long 0x38 22. "WEN_CH86,WEN_CH86" "0: Watchdog feature is disabled for CH[86],1: Watchdog feature is enabled fir CH[86]" newline bitfld.long 0x38 21. "WEN_CH85,WEN_CH85" "0: Watchdog feature is disabled for CH[85],1: Watchdog feature is enabled fir CH[85]" bitfld.long 0x38 20. "WEN_CH84,WEN_CH84" "0: Watchdog feature is disabled for CH[84],1: Watchdog feature is enabled fir CH[84]" newline bitfld.long 0x38 19. "WEN_CH83,WEN_CH83" "0: Watchdog feature is disabled for CH[83],1: Watchdog feature is enabled fir CH[83]" bitfld.long 0x38 18. "WEN_CH82,WEN_CH82" "0: Watchdog feature is disabled for CH[82],1: Watchdog feature is enabled fir CH[82]" newline bitfld.long 0x38 17. "WEN_CH81,WEN_CH81" "0: Watchdog feature is disabled for CH[81],1: Watchdog feature is enabled fir CH[81]" bitfld.long 0x38 16. "WEN_CH80,WEN_CH80" "0: Watchdog feature is disabled for CH[80],1: Watchdog feature is enabled fir CH[80]" newline bitfld.long 0x38 15. "WEN_CH79,WEN_CH79" "0: Watchdog feature is disabled for CH[79],1: Watchdog feature is enabled fir CH[79]" bitfld.long 0x38 14. "WEN_CH78,WEN_CH78" "0: Watchdog feature is disabled for CH[78],1: Watchdog feature is enabled fir CH[78]" newline bitfld.long 0x38 13. "WEN_CH77,WEN_CH77" "0: Watchdog feature is disabled for CH[77],1: Watchdog feature is enabled fir CH[77]" bitfld.long 0x38 12. "WEN_CH76,WEN_CH76" "0: Watchdog feature is disabled for CH[76],1: Watchdog feature is enabled fir CH[76]" newline bitfld.long 0x38 11. "WEN_CH75,WEN_CH75" "0: Watchdog feature is disabled for CH[75],1: Watchdog feature is enabled fir CH[75]" bitfld.long 0x38 10. "WEN_CH74,WEN_CH74" "0: Watchdog feature is disabled for CH[74],1: Watchdog feature is enabled fir CH[74]" newline bitfld.long 0x38 9. "WEN_CH73,WEN_CH73" "0: Watchdog feature is disabled for CH[73],1: Watchdog feature is enabled fir CH[73]" bitfld.long 0x38 8. "WEN_CH72,WEN_CH72" "0: Watchdog feature is disabled for CH[72],1: Watchdog feature is enabled fir CH[72]" newline bitfld.long 0x38 7. "WEN_CH71,WEN_CH71" "0: Watchdog feature is disabled for CH[71],1: Watchdog feature is enabled fir CH[71]" bitfld.long 0x38 6. "WEN_CH70,WEN_CH70" "0: Watchdog feature is disabled for CH[70],1: Watchdog feature is enabled fir CH[70]" newline bitfld.long 0x38 5. "WEN_CH69,WEN_CH69" "0: Watchdog feature is disabled for CH[69],1: Watchdog feature is enabled fir CH[69]" bitfld.long 0x38 4. "WEN_CH68,WEN_CH68" "0: Watchdog feature is disabled for CH[68],1: Watchdog feature is enabled fir CH[68]" newline bitfld.long 0x38 3. "WEN_CH67,WEN_CH67" "0: Watchdog feature is disabled for CH[67],1: Watchdog feature is enabled fir CH[67]" bitfld.long 0x38 2. "WEN_CH66,WEN_CH66" "0: Watchdog feature is disabled for CH[66],1: Watchdog feature is enabled fir CH[66]" newline bitfld.long 0x38 1. "WEN_CH65,WEN_CH65" "0: Watchdog feature is disabled for CH[65],1: Watchdog feature is enabled fir CH[65]" bitfld.long 0x38 0. "WEN_CH64,WEN_CH64" "0: Watchdog feature is disabled for CH[64],1: Watchdog feature is enabled fir CH[64]" group.long 0x2F0++0xB line.long 0x0 "ICAWORR0,Internal Channel Analog Watchdog Out of Range Register 0" bitfld.long 0x0 31. "AWOR_CH31,Analog watchdog out of range status for channel 31 provided corresponding WEN_CH31 bit is set." "0: CH[31] converted data is not out of range..,1: CH[31] converted data is out of range determined.." bitfld.long 0x0 30. "AWOR_CH30,Analog watchdog out of range status for channel 30 provided corresponding WEN_CH30 bit is set." "0: CH[30] converted data is not out of range..,1: CH[30] converted data is out of range determined.." newline bitfld.long 0x0 29. "AWOR_CH29,Analog watchdog out of range status for channel 29 provided corresponding WEN_CH29 bit is set." "0: CH[29] converted data is not out of range..,1: CH[29] converted data is out of range determined.." bitfld.long 0x0 28. "AWOR_CH28,Analog watchdog out of range status for channel 28 provided corresponding WEN_CH28 bit is set." "0: CH[28] converted data is not out of range..,1: CH[28] converted data is out of range determined.." newline bitfld.long 0x0 27. "AWOR_CH27,Analog watchdog out of range status for channel 27 provided corresponding WEN_CH27 bit is set." "0: CH[27] converted data is not out of range..,1: CH[27] converted data is out of range determined.." bitfld.long 0x0 26. "AWOR_CH26,Analog watchdog out of range status for channel 26 provided corresponding WEN_CH26 bit is set." "0: CH[26] converted data is not out of range..,1: CH[26] converted data is out of range determined.." newline bitfld.long 0x0 25. "AWOR_CH25,Analog watchdog out of range status for channel 25 provided corresponding WEN_CH25 bit is set." "0: CH[25] converted data is not out of range..,1: CH[25] converted data is out of range determined.." bitfld.long 0x0 24. "AWOR_CH24,Analog watchdog out of range status for channel 24 provided corresponding WEN_CH24 bit is set." "0: CH[24] converted data is not out of range..,1: CH[24] converted data is out of range determined.." newline bitfld.long 0x0 23. "AWOR_CH23,Analog watchdog out of range status for channel 23 provided corresponding WEN_CH23 bit is set." "0: CH[23] converted data is not out of range..,1: CH[23] converted data is out of range determined.." bitfld.long 0x0 22. "AWOR_CH22,Analog watchdog out of range status for channel 22 provided corresponding WEN_CH22 bit is set." "0: CH[22] converted data is not out of range..,1: CH[22] converted data is out of range determined.." newline bitfld.long 0x0 21. "AWOR_CH21,Analog watchdog out of range status for channel 21 provided corresponding WEN_CH21 bit is set." "0: CH[21] converted data is not out of range..,1: CH[21] converted data is out of range determined.." bitfld.long 0x0 20. "AWOR_CH20,Analog watchdog out of range status for channel 20 provided corresponding WEN_CH20 bit is set." "0: CH[20] converted data is not out of range..,1: CH[20] converted data is out of range determined.." newline bitfld.long 0x0 19. "AWOR_CH19,Analog watchdog out of range status for channel 19 provided corresponding WEN_CH19 bit is set." "0: CH[19] converted data is not out of range..,1: CH[19] converted data is out of range determined.." bitfld.long 0x0 18. "AWOR_CH18,Analog watchdog out of range status for channel 18 provided corresponding WEN_CH18 bit is set." "0: CH[18] converted data is not out of range..,1: CH[18] converted data is out of range determined.." newline bitfld.long 0x0 17. "AWOR_CH17,Analog watchdog out of range status for channel 17 provided corresponding WEN_CH17 bit is set." "0: CH[17] converted data is not out of range..,1: CH[17] converted data is out of range determined.." bitfld.long 0x0 16. "AWOR_CH16,Analog watchdog out of range status for channel 16 provided corresponding WEN_CH16 bit is set." "0: CH[16] converted data is not out of range..,1: CH[16] converted data is out of range determined.." newline bitfld.long 0x0 15. "AWOR_CH15,Analog watchdog out of range status for channel 15 provided corresponding WEN_CH15 bit is set." "0: CH[15] converted data is not out of range..,1: CH[15] converted data is out of range determined.." bitfld.long 0x0 14. "AWOR_CH14,Analog watchdog out of range status for channel 14 provided corresponding WEN_CH14 bit is set." "0: CH[14] converted data is not out of range..,1: CH[14] converted data is out of range determined.." newline bitfld.long 0x0 13. "AWOR_CH13,Analog watchdog out of range status for channel 13 provided corresponding WEN_CH13 bit is set." "0: CH[13] converted data is not out of range..,1: CH[13] converted data is out of range determined.." bitfld.long 0x0 12. "AWOR_CH12,Analog watchdog out of range status for channel 12 provided corresponding WEN_CH12 bit is set." "0: CH[12] converted data is not out of range..,1: CH[12] converted data is out of range determined.." newline bitfld.long 0x0 11. "AWOR_CH11,Analog watchdog out of range status for channel 11 provided corresponding WEN_CH11 bit is set." "0: CH[11] converted data is not out of range..,1: CH[11] converted data is out of range determined.." bitfld.long 0x0 10. "AWOR_CH10,Analog watchdog out of range status for channel 10 provided corresponding WEN_CH10 bit is set." "0: CH[10] converted data is not out of range..,1: CH[10] converted data is out of range determined.." newline bitfld.long 0x0 9. "AWOR_CH9,Analog watchdog out of range status for channel 9 provided corresponding WEN_CH9 bit is set." "0: CH[9] converted data is not out of range..,1: CH[9] converted data is out of range determined.." bitfld.long 0x0 8. "AWOR_CH8,Analog watchdog out of range status for channel 8 provided corresponding WEN_CH8 bit is set." "0: CH[8] converted data is not out of range..,1: CH[8] converted data is out of range determined.." newline bitfld.long 0x0 7. "AWOR_CH7,Analog watchdog out of range status for channel 7 provided corresponding WEN_CH7 bit is set." "0: CH[7] converted data is not out of range..,1: CH[7] converted data is out of range determined.." bitfld.long 0x0 6. "AWOR_CH6,Analog watchdog out of range status for channel 6 provided corresponding WEN_CH6 bit is set." "0: CH[6] converted data is not out of range..,1: CH[6] converted data is out of range determined.." newline bitfld.long 0x0 5. "AWOR_CH5,Analog watchdog out of range status for channel 5 provided corresponding WEN_CH5 bit is set." "0: CH[5] converted data is not out of range..,1: CH[5] converted data is out of range determined.." bitfld.long 0x0 4. "AWOR_CH4,Analog watchdog out of range status for channel 4 provided corresponding WEN_CH4 bit is set." "0: CH[4] converted data is not out of range..,1: CH[4] converted data is out of range determined.." newline bitfld.long 0x0 3. "AWOR_CH3,Analog watchdog out of range status for channel 3 provided corresponding WEN_CH3 bit is set." "0: CH[3] converted data is not out of range..,1: CH[3] converted data is out of range determined.." bitfld.long 0x0 2. "AWOR_CH2,Analog watchdog out of range status for channel 2 provided corresponding WEN_CH2 bit is set." "0: CH[2] converted data is not out of range..,1: CH[2] converted data is out of range determined.." newline bitfld.long 0x0 1. "AWOR_CH1,Analog watchdog out of range status for channel 1 provided corresponding WEN_CH1 bit is set." "0: CH[1] converted data is not out of range..,1: CH[1] converted data is out of range determined.." bitfld.long 0x0 0. "AWOR_CH0,Analog watchdog out of range status for channel 0 provided corresponding WEN_CH0 bit is set." "0: CH[0] converted data is not out of range..,1: CH[0] converted data is out of range determined.." line.long 0x4 "ICAWORR1,Internal Channel Analog Watchdog Out of Range Register 1" bitfld.long 0x4 31. "AWOR_CH63,Analog watchdog out of range status for channel 63 provided corresponding WEN_CH63 bit is set." "0: CH[63] converted data is not out of range..,1: CH[63] converted data is out of range determined.." bitfld.long 0x4 30. "AWOR_CH62,Analog watchdog out of range status for channel 62 provided corresponding WEN_CH62 bit is set." "0: CH[62] converted data is not out of range..,1: CH[62] converted data is out of range determined.." newline bitfld.long 0x4 29. "AWOR_CH61,Analog watchdog out of range status for channel 61 provided corresponding WEN_CH61 bit is set." "0: CH[61] converted data is not out of range..,1: CH[61] converted data is out of range determined.." bitfld.long 0x4 28. "AWOR_CH60,Analog watchdog out of range status for channel 60 provided corresponding WEN_CH60 bit is set." "0: CH[60] converted data is not out of range..,1: CH[60] converted data is out of range determined.." newline bitfld.long 0x4 27. "AWOR_CH59,Analog watchdog out of range status for channel 59 provided corresponding WEN_CH59 bit is set." "0: CH[59] converted data is not out of range..,1: CH[59] converted data is out of range determined.." bitfld.long 0x4 26. "AWOR_CH58,Analog watchdog out of range status for channel 58 provided corresponding WEN_CH58 bit is set." "0: CH[58] converted data is not out of range..,1: CH[58] converted data is out of range determined.." newline bitfld.long 0x4 25. "AWOR_CH57,Analog watchdog out of range status for channel 57 provided corresponding WEN_CH57 bit is set." "0: CH[57] converted data is not out of range..,1: CH[57] converted data is out of range determined.." bitfld.long 0x4 24. "AWOR_CH56,Analog watchdog out of range status for channel 56 provided corresponding WEN_CH56 bit is set." "0: CH[56] converted data is not out of range..,1: CH[56] converted data is out of range determined.." newline bitfld.long 0x4 23. "AWOR_CH55,Analog watchdog out of range status for channel 55 provided corresponding WEN_CH55 bit is set." "0: CH[55] converted data is not out of range..,1: CH[55] converted data is out of range determined.." bitfld.long 0x4 22. "AWOR_CH54,Analog watchdog out of range status for channel 54 provided corresponding WEN_CH54 bit is set." "0: CH[54] converted data is not out of range..,1: CH[54] converted data is out of range determined.." newline bitfld.long 0x4 21. "AWOR_CH53,Analog watchdog out of range status for channel 53 provided corresponding WEN_CH53 bit is set." "0: CH[53] converted data is not out of range..,1: CH[53] converted data is out of range determined.." bitfld.long 0x4 20. "AWOR_CH52,Analog watchdog out of range status for channel 52 provided corresponding WEN_CH52 bit is set." "0: CH[52] converted data is not out of range..,1: CH[52] converted data is out of range determined.." newline bitfld.long 0x4 19. "AWOR_CH51,Analog watchdog out of range status for channel 51 provided corresponding WEN_CH51 bit is set." "0: CH[51] converted data is not out of range..,1: CH[51] converted data is out of range determined.." bitfld.long 0x4 18. "AWOR_CH50,Analog watchdog out of range status for channel 50 provided corresponding WEN_CH50 bit is set." "0: CH[50] converted data is not out of range..,1: CH[50] converted data is out of range determined.." newline bitfld.long 0x4 17. "AWOR_CH49,Analog watchdog out of range status for channel 49 provided corresponding WEN_CH49 bit is set." "0: CH[49] converted data is not out of range..,1: CH[49] converted data is out of range determined.." bitfld.long 0x4 16. "AWOR_CH48,Analog watchdog out of range status for channel 48 provided corresponding WEN_CH48 bit is set." "0: CH[48] converted data is not out of range..,1: CH[48] converted data is out of range determined.." newline bitfld.long 0x4 15. "AWOR_CH47,Analog watchdog out of range status for channel 47 provided corresponding WEN_CH47 bit is set." "0: CH[47] converted data is not out of range..,1: CH[47] converted data is out of range determined.." bitfld.long 0x4 14. "AWOR_CH46,Analog watchdog out of range status for channel 46 provided corresponding WEN_CH46 bit is set." "0: CH[46] converted data is not out of range..,1: CH[46] converted data is out of range determined.." newline bitfld.long 0x4 13. "AWOR_CH45,Analog watchdog out of range status for channel 45 provided corresponding WEN_CH45 bit is set." "0: CH[45] converted data is not out of range..,1: CH[45] converted data is out of range determined.." bitfld.long 0x4 12. "AWOR_CH44,Analog watchdog out of range status for channel 44 provided corresponding WEN_CH44 bit is set." "0: CH[44] converted data is not out of range..,1: CH[44] converted data is out of range determined.." newline bitfld.long 0x4 11. "AWOR_CH43,Analog watchdog out of range status for channel 43 provided corresponding WEN_CH43 bit is set." "0: CH[43] converted data is not out of range..,1: CH[43] converted data is out of range determined.." bitfld.long 0x4 10. "AWOR_CH42,Analog watchdog out of range status for channel 42 provided corresponding WEN_CH42 bit is set." "0: CH[42] converted data is not out of range..,1: CH[42] converted data is out of range determined.." newline bitfld.long 0x4 9. "AWOR_CH41,Analog watchdog out of range status for channel 41 provided corresponding WEN_CH41 bit is set." "0: CH[41] converted data is not out of range..,1: CH[41] converted data is out of range determined.." bitfld.long 0x4 8. "AWOR_CH40,Analog watchdog out of range status for channel 40 provided corresponding WEN_CH40 bit is set." "0: CH[40] converted data is not out of range..,1: CH[40] converted data is out of range determined.." newline bitfld.long 0x4 7. "AWOR_CH39,Analog watchdog out of range status for channel 39 provided corresponding WEN_CH39 bit is set." "0: CH[39] converted data is not out of range..,1: CH[39] converted data is out of range determined.." bitfld.long 0x4 6. "AWOR_CH38,Analog watchdog out of range status for channel 38 provided corresponding WEN_CH38 bit is set." "0: CH[38] converted data is not out of range..,1: CH[38] converted data is out of range determined.." newline bitfld.long 0x4 5. "AWOR_CH37,Analog watchdog out of range status for channel 37 provided corresponding WEN_CH37 bit is set." "0: CH[37] converted data is not out of range..,1: CH[37] converted data is out of range determined.." bitfld.long 0x4 4. "AWOR_CH36,Analog watchdog out of range status for channel 36 provided corresponding WEN_CH36 bit is set." "0: CH[36] converted data is not out of range..,1: CH[36] converted data is out of range determined.." newline bitfld.long 0x4 3. "AWOR_CH35,Analog watchdog out of range status for channel 35 provided corresponding WEN_CH35 bit is set." "0: CH[35] converted data is not out of range..,1: CH[35] converted data is out of range determined.." bitfld.long 0x4 2. "AWOR_CH34,Analog watchdog out of range status for channel 34 provided corresponding WEN_CH34 bit is set." "0: CH[34] converted data is not out of range..,1: CH[34] converted data is out of range determined.." newline bitfld.long 0x4 1. "AWOR_CH33,Analog watchdog out of range status for channel 33 provided corresponding WEN_CH33 bit is set." "0: CH[33] converted data is not out of range..,1: CH[33] converted data is out of range determined.." bitfld.long 0x4 0. "AWOR_CH32,Analog watchdog out of range status for channel 32 provided corresponding WEN_CH32 bit is set." "0: CH[32] converted data is not out of range..,1: CH[32] converted data is out of range determined.." line.long 0x8 "ICAWORR2,Internal Channel Analog Watchdog Out of Range Register 2" bitfld.long 0x8 31. "AWOR_CH95,Analog watchdog out of range status for channel 95 provided corresponding WEN_CH95 bit is set." "0: CH[95] converted data is not out of range..,1: CH[95] converted data is out of range determined.." bitfld.long 0x8 30. "AWOR_CH94,Analog watchdog out of range status for channel 94 provided corresponding WEN_CH94 bit is set." "0: CH[94] converted data is not out of range..,1: CH[94] converted data is out of range determined.." newline bitfld.long 0x8 29. "AWOR_CH93,Analog watchdog out of range status for channel 93 provided corresponding WEN_CH93 bit is set." "0: CH[93] converted data is not out of range..,1: CH[93] converted data is out of range determined.." bitfld.long 0x8 28. "AWOR_CH92,Analog watchdog out of range status for channel 92 provided corresponding WEN_CH92 bit is set." "0: CH[92] converted data is not out of range..,1: CH[92] converted data is out of range determined.." newline bitfld.long 0x8 27. "AWOR_CH91,Analog watchdog out of range status for channel 91 provided corresponding WEN_CH91 bit is set." "0: CH[91] converted data is not out of range..,1: CH[91] converted data is out of range determined.." bitfld.long 0x8 26. "AWOR_CH90,Analog watchdog out of range status for channel 90 provided corresponding WEN_CH90 bit is set." "0: CH[90] converted data is not out of range..,1: CH[90] converted data is out of range determined.." newline bitfld.long 0x8 25. "AWOR_CH89,Analog watchdog out of range status for channel 89 provided corresponding WEN_CH89 bit is set." "0: CH[89] converted data is not out of range..,1: CH[89] converted data is out of range determined.." bitfld.long 0x8 24. "AWOR_CH88,Analog watchdog out of range status for channel 88 provided corresponding WEN_CH88 bit is set." "0: CH[88] converted data is not out of range..,1: CH[88] converted data is out of range determined.." newline bitfld.long 0x8 23. "AWOR_CH87,Analog watchdog out of range status for channel 87 provided corresponding WEN_CH87 bit is set." "0: CH[87] converted data is not out of range..,1: CH[87] converted data is out of range determined.." bitfld.long 0x8 22. "AWOR_CH86,Analog watchdog out of range status for channel 86 provided corresponding WEN_CH86 bit is set." "0: CH[86] converted data is not out of range..,1: CH[86] converted data is out of range determined.." newline bitfld.long 0x8 21. "AWOR_CH85,Analog watchdog out of range status for channel 85 provided corresponding WEN_CH85 bit is set." "0: CH[85] converted data is not out of range..,1: CH[85] converted data is out of range determined.." bitfld.long 0x8 20. "AWOR_CH84,Analog watchdog out of range status for channel 84 provided corresponding WEN_CH84 bit is set." "0: CH[84] converted data is not out of range..,1: CH[84] converted data is out of range determined.." newline bitfld.long 0x8 19. "AWOR_CH83,Analog watchdog out of range status for channel 83 provided corresponding WEN_CH83 bit is set." "0: CH[83] converted data is not out of range..,1: CH[83] converted data is out of range determined.." bitfld.long 0x8 18. "AWOR_CH82,Analog watchdog out of range status for channel 82 provided corresponding WEN_CH82 bit is set." "0: CH[82] converted data is not out of range..,1: CH[82] converted data is out of range determined.." newline bitfld.long 0x8 17. "AWOR_CH81,Analog watchdog out of range status for channel 81 provided corresponding WEN_CH81 bit is set." "0: CH[81] converted data is not out of range..,1: CH[81] converted data is out of range determined.." bitfld.long 0x8 16. "AWOR_CH80,Analog watchdog out of range status for channel 80 provided corresponding WEN_CH80 bit is set." "0: CH[80] converted data is not out of range..,1: CH[80] converted data is out of range determined.." newline bitfld.long 0x8 15. "AWOR_CH79,Analog watchdog out of range status for channel 79 provided corresponding WEN_CH79 bit is set." "0: CH[79] converted data is not out of range..,1: CH[79] converted data is out of range determined.." bitfld.long 0x8 14. "AWOR_CH78,Analog watchdog out of range status for channel 78 provided corresponding WEN_CH78 bit is set." "0: CH[78] converted data is not out of range..,1: CH[78] converted data is out of range determined.." newline bitfld.long 0x8 13. "AWOR_CH77,Analog watchdog out of range status for channel 77 provided corresponding WEN_CH77 bit is set." "0: CH[77] converted data is not out of range..,1: CH[77] converted data is out of range determined.." bitfld.long 0x8 12. "AWOR_CH76,Analog watchdog out of range status for channel 76 provided corresponding WEN_CH76 bit is set." "0: CH[76] converted data is not out of range..,1: CH[76] converted data is out of range determined.." newline bitfld.long 0x8 11. "AWOR_CH75,Analog watchdog out of range status for channel 75 provided corresponding WEN_CH75 bit is set." "0: CH[75] converted data is not out of range..,1: CH[75] converted data is out of range determined.." bitfld.long 0x8 10. "AWOR_CH74,Analog watchdog out of range status for channel 74 provided corresponding WEN_CH74 bit is set." "0: CH[74] converted data is not out of range..,1: CH[74] converted data is out of range determined.." newline bitfld.long 0x8 9. "AWOR_CH73,Analog watchdog out of range status for channel 73 provided corresponding WEN_CH73 bit is set." "0: CH[73] converted data is not out of range..,1: CH[73] converted data is out of range determined.." bitfld.long 0x8 8. "AWOR_CH72,Analog watchdog out of range status for channel 72 provided corresponding WEN_CH72 bit is set." "0: CH[72] converted data is not out of range..,1: CH[72] converted data is out of range determined.." newline bitfld.long 0x8 7. "AWOR_CH71,Analog watchdog out of range status for channel 71 provided corresponding WEN_CH71 bit is set." "0: CH[71] converted data is not out of range..,1: CH[71] converted data is out of range determined.." bitfld.long 0x8 6. "AWOR_CH70,Analog watchdog out of range status for channel 70 provided corresponding WEN_CH70 bit is set." "0: CH[70] converted data is not out of range..,1: CH[70] converted data is out of range determined.." newline bitfld.long 0x8 5. "AWOR_CH69,Analog watchdog out of range status for channel 69 provided corresponding WEN_CH69 bit is set." "0: CH[69] converted data is not out of range..,1: CH[69] converted data is out of range determined.." bitfld.long 0x8 4. "AWOR_CH68,Analog watchdog out of range status for channel 68 provided corresponding WEN_CH68 bit is set." "0: CH[68] converted data is not out of range..,1: CH[68] converted data is out of range determined.." newline bitfld.long 0x8 3. "AWOR_CH67,Analog watchdog out of range status for channel 67 provided corresponding WEN_CH67 bit is set." "0: CH[67] converted data is not out of range..,1: CH[67] converted data is out of range determined.." bitfld.long 0x8 2. "AWOR_CH66,Analog watchdog out of range status for channel 66 provided corresponding WEN_CH66 bit is set." "0: CH[66] converted data is not out of range..,1: CH[66] converted data is out of range determined.." newline bitfld.long 0x8 1. "AWOR_CH65,Analog watchdog out of range status for channel 65 provided corresponding WEN_CH65 bit is set." "0: CH[65] converted data is not out of range..,1: CH[65] converted data is out of range determined.." bitfld.long 0x8 0. "AWOR_CH64,Analog watchdog out of range status for channel 64 provided corresponding WEN_CH64 bit is set." "0: CH[64] converted data is not out of range..,1: CH[64] converted data is out of range determined.." group.long 0x400++0x1B line.long 0x0 "TCIPR,Test Channel Interrupt Pending Register" bitfld.long 0x0 31. "EOC_CH127,End of conversion interrupt pending bit for channel 127" "0: End of conversion for CH[127] has not occurred.,1: End of conversion for CH[127] has occurred" bitfld.long 0x0 30. "EOC_CH126,End of conversion interrupt pending bit for channel 126" "0: End of conversion for CH[126] has not occurred.,1: End of conversion for CH[126] has occurred" newline bitfld.long 0x0 29. "EOC_CH125,End of conversion interrupt pending bit for channel 125" "0: End of conversion for CH[125] has not occurred.,1: End of conversion for CH[125] has occurred" bitfld.long 0x0 28. "EOC_CH124,End of conversion interrupt pending bit for channel 124" "0: End of conversion for CH[124] has not occurred.,1: End of conversion for CH[124] has occurred" newline bitfld.long 0x0 26. "EOC_CH122,End of conversion interrupt pending bit for channel 122" "0: End of conversion for CH[122] has not occurred.,1: End of conversion for CH[122] has occurred" bitfld.long 0x0 13. "EOC_CH109,End of conversion interrupt pending bit for channel 109" "0: End of conversion for CH[109] has not occurred.,1: End of conversion for CH[109] has occurred" newline bitfld.long 0x0 8. "EOC_CH104,End of conversion interrupt pending bit for channel 104" "0: End of conversion for CH[104] has not occurred.,1: End of conversion for CH[104] has occurred" bitfld.long 0x0 7. "EOC_CH103,End of conversion interrupt pending bit for channel 103" "0: End of conversion for CH[103] has not occurred.,1: End of conversion for CH[103] has occurred" newline bitfld.long 0x0 3. "EOC_CH99,End of conversion interrupt pending bit for channel 99" "0: End of conversion for CH[99] has not occurred.,1: End of conversion for CH[99] has occurred" bitfld.long 0x0 1. "EOC_CH97,End of conversion interrupt pending bit for channel 97" "0: End of conversion for CH[97] has not occurred.,1: End of conversion for CH[97] has occurred" newline bitfld.long 0x0 0. "EOC_CH96,End of conversion interrupt pending bit for channel 96" "0: End of conversion for CH[96] has not occurred.,1: End of conversion for CH[96] has occurred" line.long 0x4 "TCIMR,Test Channel Interrupt Mask Register" bitfld.long 0x4 31. "IM_CH127,IM_CH127" "0: Interrupt for CH[127] is disabled.,1: Interrupt for CH[127] is enabled." bitfld.long 0x4 30. "IM_CH126,IM_CH126" "0: Interrupt for CH[126] is disabled.,1: Interrupt for CH[126] is enabled." newline bitfld.long 0x4 29. "IM_CH125,IM_CH125" "0: Interrupt for CH[125] is disabled.,1: Interrupt for CH[125] is enabled." bitfld.long 0x4 28. "IM_CH124,IM_CH124" "0: Interrupt for CH[124] is disabled.,1: Interrupt for CH[124] is enabled." newline bitfld.long 0x4 26. "IM_CH122,IM_CH122" "0: Interrupt for CH[122] is disabled.,1: Interrupt for CH[122] is enabled." bitfld.long 0x4 13. "IM_CH109,IM_CH109" "0: Interrupt for CH[109] is disabled.,1: Interrupt for CH[109] is enabled." newline bitfld.long 0x4 8. "IM_CH104,IM_CH104" "0: Interrupt for CH[104] is disabled.,1: Interrupt for CH[104] is enabled." bitfld.long 0x4 7. "IM_CH103,IM_CH103" "0: Interrupt for CH[103] is disabled.,1: Interrupt for CH[103] is enabled." newline bitfld.long 0x4 3. "IM_CH99,IM_CH99" "0: Interrupt for CH[99] is disabled.,1: Interrupt for CH[99] is enabled." bitfld.long 0x4 1. "IM_CH97,IM_CH97" "0: Interrupt for CH[97] is disabled.,1: Interrupt for CH[97] is enabled." newline bitfld.long 0x4 0. "IM_CH96,IM_CH96" "0: Interrupt for CH[96] is disabled.,1: Interrupt for CH[96] is enabled." line.long 0x8 "TCDSR,Test Channel DMA Select Register" bitfld.long 0x8 31. "DS_CH127,DS_CH127" "0: CH[127] is disabled to transfer data in DMA mode.,1: CH[127] is enabled to transfer data in DMA mode." bitfld.long 0x8 30. "DS_CH126,DS_CH126" "0: CH[126] is disabled to transfer data in DMA mode.,1: CH[126] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 29. "DS_CH125,DS_CH125" "0: CH[125] is disabled to transfer data in DMA mode.,1: CH[125] is enabled to transfer data in DMA mode." bitfld.long 0x8 28. "DS_CH124,DS_CH124" "0: CH[124] is disabled to transfer data in DMA mode.,1: CH[124] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 26. "DS_CH122,DS_CH122" "0: CH[122] is disabled to transfer data in DMA mode.,1: CH[122] is enabled to transfer data in DMA mode." bitfld.long 0x8 13. "DS_CH109,DS_CH109" "0: CH[109] is disabled to transfer data in DMA mode.,1: CH[109] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 8. "DS_CH104,DS_CH104" "0: CH[104] is disabled to transfer data in DMA mode.,1: CH[104] is enabled to transfer data in DMA mode." bitfld.long 0x8 7. "DS_CH103,DS_CH103" "0: CH[103] is disabled to transfer data in DMA mode.,1: CH[103] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 3. "DS_CH99,DS_CH99" "0: CH[99] is disabled to transfer data in DMA mode.,1: CH[99] is enabled to transfer data in DMA mode." bitfld.long 0x8 1. "DS_CH97,DS_CH97" "0: CH[97] is disabled to transfer data in DMA mode.,1: CH[97] is enabled to transfer data in DMA mode." newline bitfld.long 0x8 0. "DS_CH96,DS_CH96" "0: CH[96] is disabled to transfer data in DMA mode.,1: CH[96] is enabled to transfer data in DMA mode." line.long 0xC "TCNCMR,Test Channel Normal Conversion Mask Register" bitfld.long 0xC 31. "NCE_CH127,NCE_CH127" "0: Normal conversion is disabled for CH[127].,1: Normal conversion is enabled for CH[127]." bitfld.long 0xC 30. "NCE_CH126,NCE_CH126" "0: Normal conversion is disabled for CH[126].,1: Normal conversion is enabled for CH[126]." newline bitfld.long 0xC 29. "NCE_CH125,NCE_CH125" "0: Normal conversion is disabled for CH[125].,1: Normal conversion is enabled for CH[125]." bitfld.long 0xC 28. "NCE_CH124,NCE_CH124" "0: Normal conversion is disabled for CH[124].,1: Normal conversion is enabled for CH[124]." newline bitfld.long 0xC 26. "NCE_CH122,NCE_CH122" "0: Normal conversion is disabled for CH[122].,1: Normal conversion is enabled for CH[122]." bitfld.long 0xC 13. "NCE_CH109,NCE_CH109" "0: Normal conversion is disabled for CH[109].,1: Normal conversion is enabled for CH[109]." newline bitfld.long 0xC 8. "NCE_CH104,NCE_CH104" "0: Normal conversion is disabled for CH[104].,1: Normal conversion is enabled for CH[104]." bitfld.long 0xC 7. "NCE_CH103,NCE_CH103" "0: Normal conversion is disabled for CH[103].,1: Normal conversion is enabled for CH[103]." newline bitfld.long 0xC 3. "NCE_CH99,NCE_CH99" "0: Normal conversion is disabled for CH[99].,1: Normal conversion is enabled for CH[99]." bitfld.long 0xC 1. "NCE_CH97,NCE_CH97" "0: Normal conversion is disabled for CH[97].,1: Normal conversion is enabled for CH[97]." newline bitfld.long 0xC 0. "NCE_CH96,NCE_CH96" "0: Normal conversion is disabled for CH[96].,1: Normal conversion is enabled for CH[96]." line.long 0x10 "TCJCMR,Test Channel Injected Conversion Mask Register" bitfld.long 0x10 31. "JCE_CH127,JCE_CH127" "0: Injected conversion is disabled for CH[127].,1: Injected conversion is enabled for CH[127]." bitfld.long 0x10 30. "JCE_CH126,JCE_CH126" "0: Injected conversion is disabled for CH[126].,1: Injected conversion is enabled for CH[126]." newline bitfld.long 0x10 29. "JCE_CH125,JCE_CH125" "0: Injected conversion is disabled for CH[125].,1: Injected conversion is enabled for CH[125]." bitfld.long 0x10 28. "JCE_CH124,JCE_CH124" "0: Injected conversion is disabled for CH[124].,1: Injected conversion is enabled for CH[124]." newline bitfld.long 0x10 26. "JCE_CH122,JCE_CH122" "0: Injected conversion is disabled for CH[122].,1: Injected conversion is enabled for CH[122]." bitfld.long 0x10 13. "JCE_CH109,JCE_CH109" "0: Injected conversion is disabled for CH[109].,1: Injected conversion is enabled for CH[109]." newline bitfld.long 0x10 8. "JCE_CH104,JCE_CH104" "0: Injected conversion is disabled for CH[104].,1: Injected conversion is enabled for CH[104]." bitfld.long 0x10 7. "JCE_CH103,JCE_CH103" "0: Injected conversion is disabled for CH[103].,1: Injected conversion is enabled for CH[103]." newline bitfld.long 0x10 3. "JCE_CH99,JCE_CH99" "0: Injected conversion is disabled for CH[99].,1: Injected conversion is enabled for CH[99]." bitfld.long 0x10 1. "JCE_CH97,JCE_CH97" "0: Injected conversion is disabled for CH[97].,1: Injected conversion is enabled for CH[97]." newline bitfld.long 0x10 0. "JCE_CH96,JCE_CH96" "0: Injected conversion is disabled for CH[96].,1: Injected conversion is enabled for CH[96]." line.long 0x14 "TCWSELR0,Test Channel Watchdog Select Register 0" bitfld.long 0x14 28.--30. "WSEL_CH103,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "WSEL_CH99,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 4.--6. "WSEL_CH97,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "WSEL_CH96,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" line.long 0x18 "TCWSELR1,Test Channel Watchdog Select Register 1" bitfld.long 0x18 20.--22. "WSEL_CH109,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "WSEL_CH104,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" group.long 0x420++0xB line.long 0x0 "TCWSELR3,Test Channel Watchdog Select Register 3" bitfld.long 0x0 28.--30. "WSEL_CH127,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "WSEL_CH126,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "WSEL_CH125,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "WSEL_CH124,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "WSEL_CH122,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" line.long 0x4 "TCWENR,Test Channel Watchdog Enable Register" bitfld.long 0x4 31. "WEN_CH127,WEN_CH127" "0: Watchdog feature is disabled for CH[127].,1: Watchdog feature is enabled for CH[127]." bitfld.long 0x4 30. "WEN_CH126,WEN_CH126" "0: Watchdog feature is disabled for CH[126].,1: Watchdog feature is enabled for CH[126]." newline bitfld.long 0x4 29. "WEN_CH125,WEN_CH125" "0: Watchdog feature is disabled for CH[125].,1: Watchdog feature is enabled for CH[125]." bitfld.long 0x4 28. "WEN_CH124,WEN_CH124" "0: Watchdog feature is disabled for CH[124].,1: Watchdog feature is enabled for CH[124]." newline bitfld.long 0x4 26. "WEN_CH122,WEN_CH122" "0: Watchdog feature is disabled for CH[122].,1: Watchdog feature is enabled for CH[122]." bitfld.long 0x4 13. "WEN_CH109,WEN_CH109" "0: Watchdog feature is disabled for CH[109].,1: Watchdog feature is enabled for CH[109]." newline bitfld.long 0x4 8. "WEN_CH104,WEN_CH104" "0: Watchdog feature is disabled for CH[104].,1: Watchdog feature is enabled for CH[104]." bitfld.long 0x4 7. "WEN_CH103,WEN_CH103" "0: Watchdog feature is disabled for CH[103].,1: Watchdog feature is enabled for CH[103]." newline bitfld.long 0x4 3. "WEN_CH99,WEN_CH99" "0: Watchdog feature is disabled for CH[99].,1: Watchdog feature is enabled for CH[99]." bitfld.long 0x4 1. "WEN_CH97,WEN_CH97" "0: Watchdog feature is disabled for CH[97].,1: Watchdog feature is enabled for CH[97]." newline bitfld.long 0x4 0. "WEN_CH96,WEN_CH96" "0: Watchdog feature is disabled for CH[96].,1: Watchdog feature is enabled for CH[96]." line.long 0x8 "TCAWORR,Test Channel Analog Watchdog Out of Range Register" bitfld.long 0x8 31. "AWOR_CH127,Analog watchdog out of range status for channel 127 provided corresponding WEN_CH127 bit is set." "0: CH[127] converted data is not out of range..,1: CH[127] converted data is out of range.." bitfld.long 0x8 30. "AWOR_CH126,Analog watchdog out of range status for channel 126 provided corresponding WEN_CH126 bit is set." "0: CH[126] converted data is not out of range..,1: CH[126] converted data is out of range.." newline bitfld.long 0x8 29. "AWOR_CH125,Analog watchdog out of range status for channel 125 provided corresponding WEN_CH125 bit is set." "0: CH[125] converted data is not out of range..,1: CH[125] converted data is out of range.." bitfld.long 0x8 28. "AWOR_CH124,Analog watchdog out of range status for channel 124 provided corresponding WEN_CH124 bit is set." "0: CH[124] converted data is not out of range..,1: CH[124] converted data is out of range.." newline bitfld.long 0x8 26. "AWOR_CH122,Analog watchdog out of range status for channel 122 provided corresponding WEN_CH122 bit is set." "0: CH[122] converted data is not out of range..,1: CH[122] converted data is out of range.." bitfld.long 0x8 13. "AWOR_CH109,Analog watchdog out of range status for channel 109 provided corresponding WEN_CH109 bit is set." "0: CH[109] converted data is not out of range..,1: CH[109] converted data is out of range.." newline bitfld.long 0x8 8. "AWOR_CH104,Analog watchdog out of range status for channel 104 provided corresponding WEN_CH104 bit is set." "0: CH[104] converted data is not out of range..,1: CH[104] converted data is out of range.." bitfld.long 0x8 7. "AWOR_CH103,Analog watchdog out of range status for channel 103 provided corresponding WEN_CH103 bit is set." "0: CH[103] converted data is not out of range..,1: CH[103] converted data is out of range.." newline bitfld.long 0x8 3. "AWOR_CH99,Analog watchdog out of range status for channel 99 provided corresponding WEN_CH99 bit is set." "0: CH[99] converted data is not out of range..,1: CH[99] converted data is out of range determined.." bitfld.long 0x8 1. "AWOR_CH97,Analog watchdog out of range status for channel 97 provided corresponding WEN_CH97 bit is set." "0: CH[97] converted data is not out of range..,1: CH[97] converted data is out of range determined.." newline bitfld.long 0x8 0. "AWOR_CH96,Analog watchdog out of range status for channel 96 provided corresponding WEN_CH96 bit is set." "0: CH[96] converted data is not out of range..,1: CH[96] converted data is out of range determined.." group.long 0x44C++0xB line.long 0x0 "TCCAPR7,Test Channel Connection with Analog Pin Register 7" bitfld.long 0x0 31. "ESIC_TCH31,Enable short with internal channel for test channel 31" "0: Test channel 31 cannot be shorted with internal..,1: Test channel 31 can be shorted with internal.." hexmask.long.byte 0x0 24.--30. 1. "ICSEL_TCH31,Internal channel selection for short with test channel 31" newline bitfld.long 0x0 23. "ESIC_TCH30,Enable short with internal channel for test channel 30" "0: Test channel 30 cannot be shorted with internal..,1: Test channel 30 can be shorted with internal.." hexmask.long.byte 0x0 16.--22. 1. "ICSEL_TCH30,Internal channel selection for short with test channel 30" newline bitfld.long 0x0 15. "ESIC_TCH29,Enable short with internal channel for test channel 29" "0: Test channel 29 cannot be shorted with internal..,1: Test channel 29 can be shorted with internal.." hexmask.long.byte 0x0 8.--14. 1. "ICSEL_TCH29,Internal channel selection for short with test channel 29" newline bitfld.long 0x0 7. "ESIC_TCH28,Enable short with internal channel for test channel 28" "0: Test channel 28 cannot be shorted with internal..,1: Test channel 28 can be shorted with internal.." hexmask.long.byte 0x0 0.--6. 1. "ICSEL_TCH28,Internal channel selection for short with test channel 28" line.long 0x4 "TCDR96,Test Channel Data Register 96" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x8 "TCDR97,Test Channel Data Register 97" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." group.long 0x45C++0x3 line.long 0x0 "TCDR99,Test Channel Data Register 99" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." group.long 0x46C++0x7 line.long 0x0 "TCDR103,Test Channel Data Register 103" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x4 "TCDR104,Test Channel Data Register 104" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." group.long 0x484++0x3 line.long 0x0 "TCDR109,Test Channel Data Register 109" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." group.long 0x4B8++0x3 line.long 0x0 "TCDR122,Test Channel Data Register 122" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." group.long 0x4C0++0xF line.long 0x0 "TCDR124,Test Channel Data Register 124" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x4 "TCDR125,Test Channel Data Register 125" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x8 "TCDR126,Test Channel Data Register 126" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xC "TCDR127,Test Channel Data Register 127" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." group.long 0x500++0x3 line.long 0x0 "ECDSDR,External Channel Decode Signals Delay Register" hexmask.long.word 0x0 0.--11. 1. "DSD,This bit field defines the delay between the external decode signals and the start of the sampling phase. It is used to take into account of the settling time required for the external mux. The decode signal delay is calculated as (DSD X 1/Frequency.." group.long 0x510++0x7 line.long 0x0 "ECIPR0,External Channel Interrupt Pending Register 0" bitfld.long 0x0 31. "EOC_CH159,EOC_CH159" "0: End of conversion for CH[159] has not occurred.,1: End of conversion for CH[159] has occurred." bitfld.long 0x0 30. "EOC_CH158,EOC_CH158" "0: End of conversion for CH[158] has not occurred.,1: End of conversion for CH[158] has occurred." newline bitfld.long 0x0 29. "EOC_CH157,EOC_CH157" "0: End of conversion for CH[157] has not occurred.,1: End of conversion for CH[157] has occurred." bitfld.long 0x0 28. "EOC_CH156,EOC_CH156" "0: End of conversion for CH[156] has not occurred.,1: End of conversion for CH[156] has occurred." newline bitfld.long 0x0 27. "EOC_CH155,EOC_CH155" "0: End of conversion for CH[155] has not occurred.,1: End of conversion for CH[155] has occurred." bitfld.long 0x0 26. "EOC_CH154,EOC_CH154" "0: End of conversion for CH[154] has not occurred.,1: End of conversion for CH[154] has occurred." newline bitfld.long 0x0 25. "EOC_CH153,EOC_CH153" "0: End of conversion for CH[153] has not occurred.,1: End of conversion for CH[153] has occurred." bitfld.long 0x0 24. "EOC_CH152,EOC_CH152" "0: End of conversion for CH[152] has not occurred.,1: End of conversion for CH[152] has occurred." newline bitfld.long 0x0 23. "EOC_CH151,EOC_CH151" "0: End of conversion for CH[151] has not occurred.,1: End of conversion for CH[151] has occurred." bitfld.long 0x0 22. "EOC_CH150,EOC_CH150" "0: End of conversion for CH[150] has not occurred.,1: End of conversion for CH[150] has occurred." newline bitfld.long 0x0 21. "EOC_CH149,EOC_CH149" "0: End of conversion for CH[149] has not occurred.,1: End of conversion for CH[149] has occurred." bitfld.long 0x0 20. "EOC_CH148,EOC_CH148" "0: End of conversion for CH[148] has not occurred.,1: End of conversion for CH[148] has occurred." newline bitfld.long 0x0 19. "EOC_CH147,EOC_CH147" "0: End of conversion for CH[147] has not occurred.,1: End of conversion for CH[147] has occurred." bitfld.long 0x0 18. "EOC_CH146,EOC_CH146" "0: End of conversion for CH[146] has not occurred.,1: End of conversion for CH[146] has occurred." newline bitfld.long 0x0 17. "EOC_CH145,EOC_CH145" "0: End of conversion for CH[145] has not occurred.,1: End of conversion for CH[145] has occurred." bitfld.long 0x0 16. "EOC_CH144,EOC_CH144" "0: End of conversion for CH[144] has not occurred.,1: End of conversion for CH[144] has occurred." newline bitfld.long 0x0 15. "EOC_CH143,EOC_CH143" "0: End of conversion for CH[143] has not occurred.,1: End of conversion for CH[143] has occurred." bitfld.long 0x0 14. "EOC_CH142,EOC_CH142" "0: End of conversion for CH[142] has not occurred.,1: End of conversion for CH[142] has occurred." newline bitfld.long 0x0 13. "EOC_CH141,EOC_CH141" "0: End of conversion for CH[141] has not occurred.,1: End of conversion for CH[141] has occurred." bitfld.long 0x0 12. "EOC_CH140,EOC_CH140" "0: End of conversion for CH[140] has not occurred.,1: End of conversion for CH[140] has occurred." newline bitfld.long 0x0 11. "EOC_CH139,EOC_CH139" "0: End of conversion for CH[139] has not occurred.,1: End of conversion for CH[139] has occurred." bitfld.long 0x0 10. "EOC_CH138,EOC_CH138" "0: End of conversion for CH[138] has not occurred.,1: End of conversion for CH[138] has occurred." newline bitfld.long 0x0 9. "EOC_CH137,EOC_CH137" "0: End of conversion for CH[137] has not occurred.,1: End of conversion for CH[137] has occurred." bitfld.long 0x0 8. "EOC_CH136,EOC_CH136" "0: End of conversion for CH[136] has not occurred.,1: End of conversion for CH[136] has occurred." newline bitfld.long 0x0 7. "EOC_CH135,EOC_CH135" "0: End of conversion for CH[135] has not occurred.,1: End of conversion for CH[135] has occurred." bitfld.long 0x0 6. "EOC_CH134,EOC_CH134" "0: End of conversion for CH[134] has not occurred.,1: End of conversion for CH[134] has occurred." newline bitfld.long 0x0 5. "EOC_CH133,EOC_CH133" "0: End of conversion for CH[133] has not occurred.,1: End of conversion for CH[133] has occurred." bitfld.long 0x0 4. "EOC_CH132,EOC_CH132" "0: End of conversion for CH[132] has not occurred.,1: End of conversion for CH[132] has occurred." newline bitfld.long 0x0 3. "EOC_CH131,EOC_CH131" "0: End of conversion for CH[131] has not occurred.,1: End of conversion for CH[131] has occurred." bitfld.long 0x0 2. "EOC_CH130,EOC_CH130" "0: End of conversion for CH[130] has not occurred.,1: End of conversion for CH[130] has occurred." newline bitfld.long 0x0 1. "EOC_CH129,EOC_CH129" "0: End of conversion for CH[129] has not occurred.,1: End of conversion for CH[129] has occurred." bitfld.long 0x0 0. "EOC_CH128,EOC_CH128" "0: End of conversion for CH[128] has not occurred.,1: End of conversion for CH[128] has occurred." line.long 0x4 "ECIPR1,External Channel Interrupt Pending Register 1" bitfld.long 0x4 31. "EOC_CH191,EOC_CH191" "0: End of conversion for CH[191] has not occurred.,1: End of conversion for CH[191] has occurred." bitfld.long 0x4 30. "EOC_CH190,EOC_CH190" "0: End of conversion for CH[190] has not occurred.,1: End of conversion for CH[190] has occurred." newline bitfld.long 0x4 29. "EOC_CH189,EOC_CH189" "0: End of conversion for CH[189] has not occurred.,1: End of conversion for CH[189] has occurred." bitfld.long 0x4 28. "EOC_CH188,EOC_CH188" "0: End of conversion for CH[188] has not occurred.,1: End of conversion for CH[188] has occurred." newline bitfld.long 0x4 27. "EOC_CH187,EOC_CH187" "0: End of conversion for CH[187] has not occurred.,1: End of conversion for CH[187] has occurred." bitfld.long 0x4 26. "EOC_CH186,EOC_CH186" "0: End of conversion for CH[186] has not occurred.,1: End of conversion for CH[186] has occurred." newline bitfld.long 0x4 25. "EOC_CH185,EOC_CH185" "0: End of conversion for CH[185] has not occurred.,1: End of conversion for CH[185] has occurred." bitfld.long 0x4 24. "EOC_CH184,EOC_CH184" "0: End of conversion for CH[184] has not occurred.,1: End of conversion for CH[184] has occurred." newline bitfld.long 0x4 23. "EOC_CH183,EOC_CH183" "0: End of conversion for CH[183] has not occurred.,1: End of conversion for CH[183] has occurred." bitfld.long 0x4 22. "EOC_CH182,EOC_CH182" "0: End of conversion for CH[182] has not occurred.,1: End of conversion for CH[182] has occurred." newline bitfld.long 0x4 21. "EOC_CH181,EOC_CH181" "0: End of conversion for CH[181] has not occurred.,1: End of conversion for CH[181] has occurred." bitfld.long 0x4 20. "EOC_CH180,EOC_CH180" "0: End of conversion for CH[180] has not occurred.,1: End of conversion for CH[180] has occurred." newline bitfld.long 0x4 19. "EOC_CH179,EOC_CH179" "0: End of conversion for CH[179] has not occurred.,1: End of conversion for CH[179] has occurred." bitfld.long 0x4 18. "EOC_CH178,EOC_CH178" "0: End of conversion for CH[178] has not occurred.,1: End of conversion for CH[178] has occurred." newline bitfld.long 0x4 17. "EOC_CH177,EOC_CH177" "0: End of conversion for CH[177] has not occurred.,1: End of conversion for CH[177] has occurred." bitfld.long 0x4 16. "EOC_CH176,EOC_CH176" "0: End of conversion for CH[176] has not occurred.,1: End of conversion for CH[176] has occurred." newline bitfld.long 0x4 15. "EOC_CH175,EOC_CH175" "0: End of conversion for CH[175] has not occurred.,1: End of conversion for CH[175] has occurred." bitfld.long 0x4 14. "EOC_CH174,EOC_CH174" "0: End of conversion for CH[174] has not occurred.,1: End of conversion for CH[174] has occurred." newline bitfld.long 0x4 13. "EOC_CH173,EOC_CH173" "0: End of conversion for CH[173] has not occurred.,1: End of conversion for CH[173] has occurred." bitfld.long 0x4 12. "EOC_CH172,EOC_CH172" "0: End of conversion for CH[172] has not occurred.,1: End of conversion for CH[172] has occurred." newline bitfld.long 0x4 11. "EOC_CH171,EOC_CH171" "0: End of conversion for CH[171] has not occurred.,1: End of conversion for CH[171] has occurred." bitfld.long 0x4 10. "EOC_CH170,EOC_CH170" "0: End of conversion for CH[170] has not occurred.,1: End of conversion for CH[170] has occurred." newline bitfld.long 0x4 9. "EOC_CH169,EOC_CH169" "0: End of conversion for CH[169] has not occurred.,1: End of conversion for CH[169] has occurred." bitfld.long 0x4 8. "EOC_CH168,EOC_CH168" "0: End of conversion for CH[168] has not occurred.,1: End of conversion for CH[168] has occurred." newline bitfld.long 0x4 7. "EOC_CH167,EOC_CH167" "0: End of conversion for CH[167] has not occurred.,1: End of conversion for CH[167] has occurred." bitfld.long 0x4 6. "EOC_CH166,EOC_CH166" "0: End of conversion for CH[166] has not occurred.,1: End of conversion for CH[166] has occurred." newline bitfld.long 0x4 5. "EOC_CH165,EOC_CH165" "0: End of conversion for CH[165] has not occurred.,1: End of conversion for CH[165] has occurred." bitfld.long 0x4 4. "EOC_CH164,EOC_CH164" "0: End of conversion for CH[164] has not occurred.,1: End of conversion for CH[164] has occurred." newline bitfld.long 0x4 3. "EOC_CH163,EOC_CH163" "0: End of conversion for CH[163] has not occurred.,1: End of conversion for CH[163] has occurred." bitfld.long 0x4 2. "EOC_CH162,EOC_CH162" "0: End of conversion for CH[162] has not occurred.,1: End of conversion for CH[162] has occurred." newline bitfld.long 0x4 1. "EOC_CH161,EOC_CH161" "0: End of conversion for CH[161] has not occurred.,1: End of conversion for CH[161] has occurred." bitfld.long 0x4 0. "EOC_CH160,EOC_CH160" "0: End of conversion for CH[160] has not occurred.,1: End of conversion for CH[160] has occurred." group.long 0x520++0x7 line.long 0x0 "ECIMR0,External Channel Interrupt Mask Register 0" bitfld.long 0x0 31. "IM_CH159,IM_CH159" "0: Interrupt for CH[159] is disabled.,1: Interrupt for CH[159] is enabled." bitfld.long 0x0 30. "IM_CH158,IM_CH158" "0: Interrupt for CH[158] is disabled.,1: Interrupt for CH[158] is enabled." newline bitfld.long 0x0 29. "IM_CH157,IM_CH157" "0: Interrupt for CH[157] is disabled.,1: Interrupt for CH[157] is enabled." bitfld.long 0x0 28. "IM_CH156,IM_CH156" "0: Interrupt for CH[156] is disabled.,1: Interrupt for CH[156] is enabled." newline bitfld.long 0x0 27. "IM_CH155,IM_CH155" "0: Interrupt for CH[155] is disabled.,1: Interrupt for CH[155] is enabled." bitfld.long 0x0 26. "IM_CH154,IM_CH154" "0: Interrupt for CH[154] is disabled.,1: Interrupt for CH[154] is enabled." newline bitfld.long 0x0 25. "IM_CH153,IM_CH153" "0: Interrupt for CH[153] is disabled.,1: Interrupt for CH[153] is enabled." bitfld.long 0x0 24. "IM_CH152,IM_CH152" "0: Interrupt for CH[152] is disabled.,1: Interrupt for CH[152] is enabled." newline bitfld.long 0x0 23. "IM_CH151,IM_CH151" "0: Interrupt for CH[151] is disabled.,1: Interrupt for CH[151] is enabled." bitfld.long 0x0 22. "IM_CH150,IM_CH150" "0: Interrupt for CH[150] is disabled.,1: Interrupt for CH[150] is enabled." newline bitfld.long 0x0 21. "IM_CH149,IM_CH149" "0: Interrupt for CH[149] is disabled.,1: Interrupt for CH[149] is enabled." bitfld.long 0x0 20. "IM_CH148,IM_CH148" "0: Interrupt for CH[148] is disabled.,1: Interrupt for CH[148] is enabled." newline bitfld.long 0x0 19. "IM_CH147,IM_CH147" "0: Interrupt for CH[147] is disabled.,1: Interrupt for CH[147] is enabled." bitfld.long 0x0 18. "IM_CH146,IM_CH146" "0: Interrupt for CH[146] is disabled.,1: Interrupt for CH[146] is enabled." newline bitfld.long 0x0 17. "IM_CH145,IM_CH145" "0: Interrupt for CH[145] is disabled.,1: Interrupt for CH[145] is enabled." bitfld.long 0x0 16. "IM_CH144,IM_CH144" "0: Interrupt for CH[144] is disabled.,1: Interrupt for CH[144] is enabled." newline bitfld.long 0x0 15. "IM_CH143,IM_CH143" "0: Interrupt for CH[143] is disabled.,1: Interrupt for CH[143] is enabled." bitfld.long 0x0 14. "IM_CH142,IM_CH142" "0: Interrupt for CH[142] is disabled.,1: Interrupt for CH[142] is enabled." newline bitfld.long 0x0 13. "IM_CH141,IM_CH141" "0: Interrupt for CH[141] is disabled.,1: Interrupt for CH[141] is enabled." bitfld.long 0x0 12. "IM_CH140,IM_CH140" "0: Interrupt for CH[140] is disabled.,1: Interrupt for CH[140] is enabled." newline bitfld.long 0x0 11. "IM_CH139,IM_CH139" "0: Interrupt for CH[139] is disabled.,1: Interrupt for CH[139] is enabled." bitfld.long 0x0 10. "IM_CH138,IM_CH138" "0: Interrupt for CH[138] is disabled.,1: Interrupt for CH[138] is enabled." newline bitfld.long 0x0 9. "IM_CH137,IM_CH137" "0: Interrupt for CH[137] is disabled.,1: Interrupt for CH[137] is enabled." bitfld.long 0x0 8. "IM_CH136,IM_CH136" "0: Interrupt for CH[136] is disabled.,1: Interrupt for CH[136] is enabled." newline bitfld.long 0x0 7. "IM_CH135,IM_CH135" "0: Interrupt for CH[135] is disabled.,1: Interrupt for CH[135] is enabled." bitfld.long 0x0 6. "IM_CH134,IM_CH134" "0: Interrupt for CH[134] is disabled.,1: Interrupt for CH[134] is enabled." newline bitfld.long 0x0 5. "IM_CH133,IM_CH133" "0: Interrupt for CH[133] is disabled.,1: Interrupt for CH[133] is enabled." bitfld.long 0x0 4. "IM_CH132,IM_CH132" "0: Interrupt for CH[132] is disabled.,1: Interrupt for CH[132] is enabled." newline bitfld.long 0x0 3. "IM_CH131,IM_CH131" "0: Interrupt for CH[131] is disabled.,1: Interrupt for CH[131] is enabled." bitfld.long 0x0 2. "IM_CH130,IM_CH130" "0: Interrupt for CH[130] is disabled.,1: Interrupt for CH[130] is enabled." newline bitfld.long 0x0 1. "IM_CH129,IM_CH129" "0: Interrupt for CH[129] is disabled.,1: Interrupt for CH[129] is enabled." bitfld.long 0x0 0. "IM_CH128,IM_CH128" "0: Interrupt for CH[128] is disabled.,1: Interrupt for CH[128] is enabled." line.long 0x4 "ECIMR1,External Channel Interrupt Mask Register 1" bitfld.long 0x4 31. "IM_CH191,IM_CH191" "0: Interrupt for CH[191] is disabled.,1: Interrupt for CH[191] is enabled." bitfld.long 0x4 30. "IM_CH190,IM_CH190" "0: Interrupt for CH[190] is disabled.,1: Interrupt for CH[190] is enabled." newline bitfld.long 0x4 29. "IM_CH189,IM_CH189" "0: Interrupt for CH[189] is disabled.,1: Interrupt for CH[189] is enabled." bitfld.long 0x4 28. "IM_CH188,IM_CH188" "0: Interrupt for CH[188] is disabled.,1: Interrupt for CH[188] is enabled." newline bitfld.long 0x4 27. "IM_CH187,IM_CH187" "0: Interrupt for CH[187] is disabled.,1: Interrupt for CH[187] is enabled." bitfld.long 0x4 26. "IM_CH186,IM_CH186" "0: Interrupt for CH[186] is disabled.,1: Interrupt for CH[186] is enabled." newline bitfld.long 0x4 25. "IM_CH185,IM_CH185" "0: Interrupt for CH[185] is disabled.,1: Interrupt for CH[185] is enabled." bitfld.long 0x4 24. "IM_CH184,IM_CH184" "0: Interrupt for CH[184] is disabled.,1: Interrupt for CH[184] is enabled." newline bitfld.long 0x4 23. "IM_CH183,IM_CH183" "0: Interrupt for CH[183] is disabled.,1: Interrupt for CH[183] is enabled." bitfld.long 0x4 22. "IM_CH182,IM_CH182" "0: Interrupt for CH[182] is disabled.,1: Interrupt for CH[182] is enabled." newline bitfld.long 0x4 21. "IM_CH181,IM_CH181" "0: Interrupt for CH[181] is disabled.,1: Interrupt for CH[181] is enabled." bitfld.long 0x4 20. "IM_CH180,IM_CH180" "0: Interrupt for CH[180] is disabled.,1: Interrupt for CH[180] is enabled." newline bitfld.long 0x4 19. "IM_CH179,IM_CH179" "0: Interrupt for CH[179] is disabled.,1: Interrupt for CH[179] is enabled." bitfld.long 0x4 18. "IM_CH178,IM_CH178" "0: Interrupt for CH[178] is disabled.,1: Interrupt for CH[178] is enabled." newline bitfld.long 0x4 17. "IM_CH177,IM_CH177" "0: Interrupt for CH[177] is disabled.,1: Interrupt for CH[177] is enabled." bitfld.long 0x4 16. "IM_CH176,IM_CH176" "0: Interrupt for CH[176] is disabled.,1: Interrupt for CH[176] is enabled." newline bitfld.long 0x4 15. "IM_CH175,IM_CH175" "0: Interrupt for CH[175] is disabled.,1: Interrupt for CH[175] is enabled." bitfld.long 0x4 14. "IM_CH174,IM_CH174" "0: Interrupt for CH[174] is disabled.,1: Interrupt for CH[174] is enabled." newline bitfld.long 0x4 13. "IM_CH173,IM_CH173" "0: Interrupt for CH[173] is disabled.,1: Interrupt for CH[173] is enabled." bitfld.long 0x4 12. "IM_CH172,IM_CH172" "0: Interrupt for CH[172] is disabled.,1: Interrupt for CH[172] is enabled." newline bitfld.long 0x4 11. "IM_CH171,IM_CH171" "0: Interrupt for CH[171] is disabled.,1: Interrupt for CH[171] is enabled." bitfld.long 0x4 10. "IM_CH170,IM_CH170" "0: Interrupt for CH[170] is disabled.,1: Interrupt for CH[170] is enabled." newline bitfld.long 0x4 9. "IM_CH169,IM_CH169" "0: Interrupt for CH[169] is disabled.,1: Interrupt for CH[169] is enabled." bitfld.long 0x4 8. "IM_CH168,IM_CH168" "0: Interrupt for CH[168] is disabled.,1: Interrupt for CH[168] is enabled." newline bitfld.long 0x4 7. "IM_CH167,IM_CH167" "0: Interrupt for CH[167] is disabled.,1: Interrupt for CH[167] is enabled." bitfld.long 0x4 6. "IM_CH166,IM_CH166" "0: Interrupt for CH[166] is disabled.,1: Interrupt for CH[166] is enabled." newline bitfld.long 0x4 5. "IM_CH165,IM_CH165" "0: Interrupt for CH[165] is disabled.,1: Interrupt for CH[165] is enabled." bitfld.long 0x4 4. "IM_CH164,IM_CH164" "0: Interrupt for CH[164] is disabled.,1: Interrupt for CH[164] is enabled." newline bitfld.long 0x4 3. "IM_CH163,IM_CH163" "0: Interrupt for CH[163] is disabled.,1: Interrupt for CH[163] is enabled." bitfld.long 0x4 2. "IM_CH162,IM_CH162" "0: Interrupt for CH[162] is disabled.,1: Interrupt for CH[162] is enabled." newline bitfld.long 0x4 1. "IM_CH161,IM_CH161" "0: Interrupt for CH[161] is disabled.,1: Interrupt for CH[161] is enabled." bitfld.long 0x4 0. "IM_CH160,IM_CH160" "0: Interrupt for CH[160] is disabled.,1: Interrupt for CH[160] is enabled." group.long 0x530++0x7 line.long 0x0 "ECDSR0,External Channel DMA Select Register 0" bitfld.long 0x0 31. "DS_CH159,DS_CH159" "0: CH[159] is disabled to transfer data in DMA mode.,1: CH[159] is enabled to transfer data in DMA mode." bitfld.long 0x0 30. "DS_CH158,DS_CH158" "0: CH[158] is disabled to transfer data in DMA mode.,1: CH[158] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 29. "DS_CH157,DS_CH157" "0: CH[157] is disabled to transfer data in DMA mode.,1: CH[157] is enabled to transfer data in DMA mode." bitfld.long 0x0 28. "DS_CH156,DS_CH156" "0: CH[156] is disabled to transfer data in DMA mode.,1: CH[156] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 27. "DS_CH155,DS_CH155" "0: CH[155] is disabled to transfer data in DMA mode.,1: CH[155] is enabled to transfer data in DMA mode." bitfld.long 0x0 26. "DS_CH154,DS_CH154" "0: CH[154] is disabled to transfer data in DMA mode.,1: CH[154] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 25. "DS_CH153,DS_CH153" "0: CH[153] is disabled to transfer data in DMA mode.,1: CH[153] is enabled to transfer data in DMA mode." bitfld.long 0x0 24. "DS_CH152,DS_CH152" "0: CH[152] is disabled to transfer data in DMA mode.,1: CH[152] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 23. "DS_CH151,DS_CH151" "0: CH[151] is disabled to transfer data in DMA mode.,1: CH[151] is enabled to transfer data in DMA mode." bitfld.long 0x0 22. "DS_CH150,DS_CH150" "0: CH[150] is disabled to transfer data in DMA mode.,1: CH[150] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 21. "DS_CH149,DS_CH149" "0: CH[149] is disabled to transfer data in DMA mode.,1: CH[149] is enabled to transfer data in DMA mode." bitfld.long 0x0 20. "DS_CH148,DS_CH148" "0: CH[148] is disabled to transfer data in DMA mode.,1: CH[148] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 19. "DS_CH147,DS_CH147" "0: CH[147] is disabled to transfer data in DMA mode.,1: CH[147] is enabled to transfer data in DMA mode." bitfld.long 0x0 18. "DS_CH146,DS_CH146" "0: CH[146] is disabled to transfer data in DMA mode.,1: CH[146] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 17. "DS_CH145,DS_CH145" "0: CH[145] is disabled to transfer data in DMA mode.,1: CH[145] is enabled to transfer data in DMA mode." bitfld.long 0x0 16. "DS_CH144,DS_CH144" "0: CH[144] is disabled to transfer data in DMA mode.,1: CH[144] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 15. "DS_CH143,DS_CH143" "0: CH[143] is disabled to transfer data in DMA mode.,1: CH[143] is enabled to transfer data in DMA mode." bitfld.long 0x0 14. "DS_CH142,DS_CH142" "0: CH[142] is disabled to transfer data in DMA mode.,1: CH[142] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 13. "DS_CH141,DS_CH141" "0: CH[141] is disabled to transfer data in DMA mode.,1: CH[141] is enabled to transfer data in DMA mode." bitfld.long 0x0 12. "DS_CH140,DS_CH140" "0: CH[140] is disabled to transfer data in DMA mode.,1: CH[140] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 11. "DS_CH139,DS_CH139" "0: CH[139] is disabled to transfer data in DMA mode.,1: CH[139] is enabled to transfer data in DMA mode." bitfld.long 0x0 10. "DS_CH138,DS_CH138" "0: CH[138] is disabled to transfer data in DMA mode.,1: CH[138] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 9. "DS_CH137,DS_CH137" "0: CH[137] is disabled to transfer data in DMA mode.,1: CH[137] is enabled to transfer data in DMA mode." bitfld.long 0x0 8. "DS_CH136,DS_CH136" "0: CH[136] is disabled to transfer data in DMA mode.,1: CH[136] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 7. "DS_CH135,DS_CH135" "0: CH[135] is disabled to transfer data in DMA mode.,1: CH[135] is enabled to transfer data in DMA mode." bitfld.long 0x0 6. "DS_CH134,DS_CH134" "0: CH[134] is disabled to transfer data in DMA mode.,1: CH[134] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 5. "DS_CH133,DS_CH133" "0: CH[133] is disabled to transfer data in DMA mode.,1: CH[133] is enabled to transfer data in DMA mode." bitfld.long 0x0 4. "DS_CH132,DS_CH132" "0: CH[132] is disabled to transfer data in DMA mode.,1: CH[132] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 3. "DS_CH131,DS_CH131" "0: CH[131] is disabled to transfer data in DMA mode.,1: CH[131] is enabled to transfer data in DMA mode." bitfld.long 0x0 2. "DS_CH130,DS_CH130" "0: CH[130] is disabled to transfer data in DMA mode.,1: CH[130] is enabled to transfer data in DMA mode." newline bitfld.long 0x0 1. "DS_CH129,DS_CH129" "0: CH[129] is disabled to transfer data in DMA mode.,1: CH[129] is enabled to transfer data in DMA mode." bitfld.long 0x0 0. "DS_CH128,DS_CH128" "0: CH[128] is disabled to transfer data in DMA mode.,1: CH[128] is enabled to transfer data in DMA mode." line.long 0x4 "ECDSR1,External Channel DMA Select Register 1" bitfld.long 0x4 31. "DS_CH191,DS_CH191" "0: CH[191] is disabled to transfer data in DMA mode.,1: CH[191] is enabled to transfer data in DMA mode." bitfld.long 0x4 30. "DS_CH190,DS_CH190" "0: CH[190] is disabled to transfer data in DMA mode.,1: CH[190] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 29. "DS_CH189,DS_CH189" "0: CH[189] is disabled to transfer data in DMA mode.,1: CH[189] is enabled to transfer data in DMA mode." bitfld.long 0x4 28. "DS_CH188,DS_CH188" "0: CH[188] is disabled to transfer data in DMA mode.,1: CH[188] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 27. "DS_CH187,DS_CH187" "0: CH[187] is disabled to transfer data in DMA mode.,1: CH[187] is enabled to transfer data in DMA mode." bitfld.long 0x4 26. "DS_CH186,DS_CH186" "0: CH[186] is disabled to transfer data in DMA mode.,1: CH[186] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 25. "DS_CH185,DS_CH185" "0: CH[185] is disabled to transfer data in DMA mode.,1: CH[185] is enabled to transfer data in DMA mode." bitfld.long 0x4 24. "DS_CH184,DS_CH184" "0: CH[184] is disabled to transfer data in DMA mode.,1: CH[184] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 23. "DS_CH183,DS_CH183" "0: CH[183] is disabled to transfer data in DMA mode.,1: CH[183] is enabled to transfer data in DMA mode." bitfld.long 0x4 22. "DS_CH182,DS_CH182" "0: CH[182] is disabled to transfer data in DMA mode.,1: CH[182] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 21. "DS_CH181,DS_CH181" "0: CH[181] is disabled to transfer data in DMA mode.,1: CH[181] is enabled to transfer data in DMA mode." bitfld.long 0x4 20. "DS_CH180,DS_CH180" "0: CH[180] is disabled to transfer data in DMA mode.,1: CH[180] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 19. "DS_CH179,DS_CH179" "0: CH[179] is disabled to transfer data in DMA mode.,1: CH[179] is enabled to transfer data in DMA mode." bitfld.long 0x4 18. "DS_CH178,DS_CH178" "0: CH[178] is disabled to transfer data in DMA mode.,1: CH[178] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 17. "DS_CH177,DS_CH177" "0: CH[177] is disabled to transfer data in DMA mode.,1: CH[177] is enabled to transfer data in DMA mode." bitfld.long 0x4 16. "DS_CH176,DS_CH176" "0: CH[176] is disabled to transfer data in DMA mode.,1: CH[176] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 15. "DS_CH175,DS_CH175" "0: CH[175] is disabled to transfer data in DMA mode.,1: CH[175] is enabled to transfer data in DMA mode." bitfld.long 0x4 14. "DS_CH174,DS_CH174" "0: CH[174] is disabled to transfer data in DMA mode.,1: CH[174] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 13. "DS_CH173,DS_CH173" "0: CH[173] is disabled to transfer data in DMA mode.,1: CH[173] is enabled to transfer data in DMA mode." bitfld.long 0x4 12. "DS_CH172,DS_CH172" "0: CH[172] is disabled to transfer data in DMA mode.,1: CH[172] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 11. "DS_CH171,DS_CH171" "0: CH[171] is disabled to transfer data in DMA mode.,1: CH[171] is enabled to transfer data in DMA mode." bitfld.long 0x4 10. "DS_CH170,DS_CH170" "0: CH[170] is disabled to transfer data in DMA mode.,1: CH[170] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 9. "DS_CH169,DS_CH169" "0: CH[169] is disabled to transfer data in DMA mode.,1: CH[169] is enabled to transfer data in DMA mode." bitfld.long 0x4 8. "DS_CH168,DS_CH168" "0: CH[168] is disabled to transfer data in DMA mode.,1: CH[168] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 7. "DS_CH167,DS_CH167" "0: CH[167] is disabled to transfer data in DMA mode.,1: CH[167] is enabled to transfer data in DMA mode." bitfld.long 0x4 6. "DS_CH166,DS_CH166" "0: CH[166] is disabled to transfer data in DMA mode.,1: CH[166] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 5. "DS_CH165,DS_CH165" "0: CH[165] is disabled to transfer data in DMA mode.,1: CH[165] is enabled to transfer data in DMA mode." bitfld.long 0x4 4. "DS_CH164,DS_CH164" "0: CH[164] is disabled to transfer data in DMA mode.,1: CH[164] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 3. "DS_CH163,DS_CH163" "0: CH[163] is disabled to transfer data in DMA mode.,1: CH[163] is enabled to transfer data in DMA mode." bitfld.long 0x4 2. "DS_CH162,DS_CH162" "0: CH[162] is disabled to transfer data in DMA mode.,1: CH[162] is enabled to transfer data in DMA mode." newline bitfld.long 0x4 1. "DS_CH161,DS_CH161" "0: CH[161] is disabled to transfer data in DMA mode.,1: CH[161] is enabled to transfer data in DMA mode." bitfld.long 0x4 0. "DS_CH160,DS_CH160" "0: CH[160] is disabled to transfer data in DMA mode.,1: CH[160] is enabled to transfer data in DMA mode." group.long 0x540++0x7 line.long 0x0 "ECNCMR0,External Channel Normal Conversion Mask Register 0" bitfld.long 0x0 31. "NCE_CH159,NCE_CH159" "0: Normal conversion is disabled for CH[159].,1: Normal conversion is enabled for CH[159]." bitfld.long 0x0 30. "NCE_CH158,NCE_CH158" "0: Normal conversion is disabled for CH[158].,1: Normal conversion is enabled for CH[158]." newline bitfld.long 0x0 29. "NCE_CH157,NCE_CH157" "0: Normal conversion is disabled for CH[157].,1: Normal conversion is enabled for CH[157]." bitfld.long 0x0 28. "NCE_CH156,NCE_CH156" "0: Normal conversion is disabled for CH[156].,1: Normal conversion is enabled for CH[156]." newline bitfld.long 0x0 27. "NCE_CH155,NCE_CH155" "0: Normal conversion is disabled for CH[155].,1: Normal conversion is enabled for CH[155]." bitfld.long 0x0 26. "NCE_CH154,NCE_CH154" "0: Normal conversion is disabled for CH[154].,1: Normal conversion is enabled for CH[154]." newline bitfld.long 0x0 25. "NCE_CH153,NCE_CH153" "0: Normal conversion is disabled for CH[153].,1: Normal conversion is enabled for CH[153]." bitfld.long 0x0 24. "NCE_CH152,NCE_CH152" "0: Normal conversion is disabled for CH[152].,1: Normal conversion is enabled for CH[152]." newline bitfld.long 0x0 23. "NCE_CH151,NCE_CH151" "0: Normal conversion is disabled for CH[151].,1: Normal conversion is enabled for CH[151]." bitfld.long 0x0 22. "NCE_CH150,NCE_CH150" "0: Normal conversion is disabled for CH[150].,1: Normal conversion is enabled for CH[150]." newline bitfld.long 0x0 21. "NCE_CH149,NCE_CH149" "0: Normal conversion is disabled for CH[149].,1: Normal conversion is enabled for CH[149]." bitfld.long 0x0 20. "NCE_CH148,NCE_CH148" "0: Normal conversion is disabled for CH[148].,1: Normal conversion is enabled for CH[148]." newline bitfld.long 0x0 19. "NCE_CH147,NCE_CH147" "0: Normal conversion is disabled for CH[147].,1: Normal conversion is enabled for CH[147]." bitfld.long 0x0 18. "NCE_CH146,NCE_CH146" "0: Normal conversion is disabled for CH[146].,1: Normal conversion is enabled for CH[146]." newline bitfld.long 0x0 17. "NCE_CH145,NCE_CH145" "0: Normal conversion is disabled for CH[145].,1: Normal conversion is enabled for CH[145]." bitfld.long 0x0 16. "NCE_CH144,NCE_CH144" "0: Normal conversion is disabled for CH[144].,1: Normal conversion is enabled for CH[144]." newline bitfld.long 0x0 15. "NCE_CH143,NCE_CH143" "0: Normal conversion is disabled for CH[143].,1: Normal conversion is enabled for CH[143]." bitfld.long 0x0 14. "NCE_CH142,NCE_CH142" "0: Normal conversion is disabled for CH[142].,1: Normal conversion is enabled for CH[142]." newline bitfld.long 0x0 13. "NCE_CH141,NCE_CH141" "0: Normal conversion is disabled for CH[141].,1: Normal conversion is enabled for CH[141]." bitfld.long 0x0 12. "NCE_CH140,NCE_CH140" "0: Normal conversion is disabled for CH[140].,1: Normal conversion is enabled for CH[140]." newline bitfld.long 0x0 11. "NCE_CH139,NCE_CH139" "0: Normal conversion is disabled for CH[139].,1: Normal conversion is enabled for CH[139]." bitfld.long 0x0 10. "NCE_CH138,NCE_CH138" "0: Normal conversion is disabled for CH[138].,1: Normal conversion is enabled for CH[138]." newline bitfld.long 0x0 9. "NCE_CH137,NCE_CH137" "0: Normal conversion is disabled for CH[137].,1: Normal conversion is enabled for CH[137]." bitfld.long 0x0 8. "NCE_CH136,NCE_CH136" "0: Normal conversion is disabled for CH[136].,1: Normal conversion is enabled for CH[136]." newline bitfld.long 0x0 7. "NCE_CH135,NCE_CH135" "0: Normal conversion is disabled for CH[135].,1: Normal conversion is enabled for CH[135]." bitfld.long 0x0 6. "NCE_CH134,NCE_CH134" "0: Normal conversion is disabled for CH[134].,1: Normal conversion is enabled for CH[134]." newline bitfld.long 0x0 5. "NCE_CH133,NCE_CH133" "0: Normal conversion is disabled for CH[133].,1: Normal conversion is enabled for CH[133]." bitfld.long 0x0 4. "NCE_CH132,NCE_CH132" "0: Normal conversion is disabled for CH[132].,1: Normal conversion is enabled for CH[132]." newline bitfld.long 0x0 3. "NCE_CH131,NCE_CH131" "0: Normal conversion is disabled for CH[131].,1: Normal conversion is enabled for CH[131]." bitfld.long 0x0 2. "NCE_CH130,NCE_CH130" "0: Normal conversion is disabled for CH[130].,1: Normal conversion is enabled for CH[130]." newline bitfld.long 0x0 1. "NCE_CH129,NCE_CH129" "0: Normal conversion is disabled for CH[129].,1: Normal conversion is enabled for CH[129]." bitfld.long 0x0 0. "NCE_CH128,NCE_CH128" "0: Normal conversion is disabled for CH[128].,1: Normal conversion is enabled for CH[128]." line.long 0x4 "ECNCMR1,External Channel Normal Conversion Mask Register 1" bitfld.long 0x4 31. "NCE_CH191,NCE_CH191" "0: Normal conversion is disabled for CH[191].,1: Normal conversion is enabled for CH[191]." bitfld.long 0x4 30. "NCE_CH190,NCE_CH190" "0: Normal conversion is disabled for CH[190].,1: Normal conversion is enabled for CH[190]." newline bitfld.long 0x4 29. "NCE_CH189,NCE_CH189" "0: Normal conversion is disabled for CH[189].,1: Normal conversion is enabled for CH[189]." bitfld.long 0x4 28. "NCE_CH188,NCE_CH188" "0: Normal conversion is disabled for CH[188].,1: Normal conversion is enabled for CH[188]." newline bitfld.long 0x4 27. "NCE_CH187,NCE_CH187" "0: Normal conversion is disabled for CH[187].,1: Normal conversion is enabled for CH[187]." bitfld.long 0x4 26. "NCE_CH186,NCE_CH186" "0: Normal conversion is disabled for CH[186].,1: Normal conversion is enabled for CH[186]." newline bitfld.long 0x4 25. "NCE_CH185,NCE_CH185" "0: Normal conversion is disabled for CH[185].,1: Normal conversion is enabled for CH[185]." bitfld.long 0x4 24. "NCE_CH184,NCE_CH184" "0: Normal conversion is disabled for CH[184].,1: Normal conversion is enabled for CH[184]." newline bitfld.long 0x4 23. "NCE_CH183,NCE_CH183" "0: Normal conversion is disabled for CH[183].,1: Normal conversion is enabled for CH[183]." bitfld.long 0x4 22. "NCE_CH182,NCE_CH182" "0: Normal conversion is disabled for CH[182].,1: Normal conversion is enabled for CH[182]." newline bitfld.long 0x4 21. "NCE_CH181,NCE_CH181" "0: Normal conversion is disabled for CH[181].,1: Normal conversion is enabled for CH[181]." bitfld.long 0x4 20. "NCE_CH180,NCE_CH180" "0: Normal conversion is disabled for CH[180].,1: Normal conversion is enabled for CH[180]." newline bitfld.long 0x4 19. "NCE_CH179,NCE_CH179" "0: Normal conversion is disabled for CH[179].,1: Normal conversion is enabled for CH[179]." bitfld.long 0x4 18. "NCE_CH178,NCE_CH178" "0: Normal conversion is disabled for CH[178].,1: Normal conversion is enabled for CH[178]." newline bitfld.long 0x4 17. "NCE_CH177,NCE_CH177" "0: Normal conversion is disabled for CH[177].,1: Normal conversion is enabled for CH[177]." bitfld.long 0x4 16. "NCE_CH176,NCE_CH176" "0: Normal conversion is disabled for CH[176].,1: Normal conversion is enabled for CH[176]." newline bitfld.long 0x4 15. "NCE_CH175,NCE_CH175" "0: Normal conversion is disabled for CH[175].,1: Normal conversion is enabled for CH[175]." bitfld.long 0x4 14. "NCE_CH174,NCE_CH174" "0: Normal conversion is disabled for CH[174].,1: Normal conversion is enabled for CH[174]." newline bitfld.long 0x4 13. "NCE_CH173,NCE_CH173" "0: Normal conversion is disabled for CH[173].,1: Normal conversion is enabled for CH[173]." bitfld.long 0x4 12. "NCE_CH172,NCE_CH172" "0: Normal conversion is disabled for CH[172].,1: Normal conversion is enabled for CH[172]." newline bitfld.long 0x4 11. "NCE_CH171,NCE_CH171" "0: Normal conversion is disabled for CH[171].,1: Normal conversion is enabled for CH[171]." bitfld.long 0x4 10. "NCE_CH170,NCE_CH170" "0: Normal conversion is disabled for CH[170].,1: Normal conversion is enabled for CH[170]." newline bitfld.long 0x4 9. "NCE_CH169,NCE_CH169" "0: Normal conversion is disabled for CH[169].,1: Normal conversion is enabled for CH[169]." bitfld.long 0x4 8. "NCE_CH168,NCE_CH168" "0: Normal conversion is disabled for CH[168].,1: Normal conversion is enabled for CH[168]." newline bitfld.long 0x4 7. "NCE_CH167,NCE_CH167" "0: Normal conversion is disabled for CH[167].,1: Normal conversion is enabled for CH[167]." bitfld.long 0x4 6. "NCE_CH166,NCE_CH166" "0: Normal conversion is disabled for CH[166].,1: Normal conversion is enabled for CH[166]." newline bitfld.long 0x4 5. "NCE_CH165,NCE_CH165" "0: Normal conversion is disabled for CH[165].,1: Normal conversion is enabled for CH[165]." bitfld.long 0x4 4. "NCE_CH164,NCE_CH164" "0: Normal conversion is disabled for CH[164].,1: Normal conversion is enabled for CH[164]." newline bitfld.long 0x4 3. "NCE_CH163,NCE_CH163" "0: Normal conversion is disabled for CH[163].,1: Normal conversion is enabled for CH[163]." bitfld.long 0x4 2. "NCE_CH162,NCE_CH162" "0: Normal conversion is disabled for CH[162].,1: Normal conversion is enabled for CH[162]." newline bitfld.long 0x4 1. "NCE_CH161,NCE_CH161" "0: Normal conversion is disabled for CH[161].,1: Normal conversion is enabled for CH[161]." bitfld.long 0x4 0. "NCE_CH160,NCE_CH160" "0: Normal conversion is disabled for CH[160].,1: Normal conversion is enabled for CH[160]." group.long 0x550++0x7 line.long 0x0 "ECJCMR0,External Channel Injected Conversion Mask Register 0" bitfld.long 0x0 31. "JCE_CH159,JCE_CH159" "0: Injected conversion is disabled for CH[159].,1: Injected conversion is enabled for CH[159]." bitfld.long 0x0 30. "JCE_CH158,JCE_CH158" "0: Injected conversion is disabled for CH[158].,1: Injected conversion is enabled for CH[158]." newline bitfld.long 0x0 29. "JCE_CH157,JCE_CH157" "0: Injected conversion is disabled for CH[157].,1: Injected conversion is enabled for CH[157]." bitfld.long 0x0 28. "JCE_CH156,JCE_CH156" "0: Injected conversion is disabled for CH[156].,1: Injected conversion is enabled for CH[156]." newline bitfld.long 0x0 27. "JCE_CH155,JCE_CH155" "0: Injected conversion is disabled for CH[155].,1: Injected conversion is enabled for CH[155]." bitfld.long 0x0 26. "JCE_CH154,JCE_CH154" "0: Injected conversion is disabled for CH[154].,1: Injected conversion is enabled for CH[154]." newline bitfld.long 0x0 25. "JCE_CH153,JCE_CH153" "0: Injected conversion is disabled for CH[153].,1: Injected conversion is enabled for CH[153]." bitfld.long 0x0 24. "JCE_CH152,JCE_CH152" "0: Injected conversion is disabled for CH[152].,1: Injected conversion is enabled for CH[152]." newline bitfld.long 0x0 23. "JCE_CH151,JCE_CH151" "0: Injected conversion is disabled for CH[151].,1: Injected conversion is enabled for CH[151]." bitfld.long 0x0 22. "JCE_CH150,JCE_CH150" "0: Injected conversion is disabled for CH[150].,1: Injected conversion is enabled for CH[150]." newline bitfld.long 0x0 21. "JCE_CH149,JCE_CH149" "0: Injected conversion is disabled for CH[149].,1: Injected conversion is enabled for CH[149]." bitfld.long 0x0 20. "JCE_CH148,JCE_CH148" "0: Injected conversion is disabled for CH[148].,1: Injected conversion is enabled for CH[148]." newline bitfld.long 0x0 19. "JCE_CH147,JCE_CH147" "0: Injected conversion is disabled for CH[147].,1: Injected conversion is enabled for CH[147]." bitfld.long 0x0 18. "JCE_CH146,JCE_CH146" "0: Injected conversion is disabled for CH[146].,1: Injected conversion is enabled for CH[146]." newline bitfld.long 0x0 17. "JCE_CH145,JCE_CH145" "0: Injected conversion is disabled for CH[145].,1: Injected conversion is enabled for CH[145]." bitfld.long 0x0 16. "JCE_CH144,JCE_CH144" "0: Injected conversion is disabled for CH[144].,1: Injected conversion is enabled for CH[144]." newline bitfld.long 0x0 15. "JCE_CH143,JCE_CH143" "0: Injected conversion is disabled for CH[143].,1: Injected conversion is enabled for CH[143]." bitfld.long 0x0 14. "JCE_CH142,JCE_CH142" "0: Injected conversion is disabled for CH[142].,1: Injected conversion is enabled for CH[142]." newline bitfld.long 0x0 13. "JCE_CH141,JCE_CH141" "0: Injected conversion is disabled for CH[141].,1: Injected conversion is enabled for CH[141]." bitfld.long 0x0 12. "JCE_CH140,JCE_CH140" "0: Injected conversion is disabled for CH[140].,1: Injected conversion is enabled for CH[140]." newline bitfld.long 0x0 11. "JCE_CH139,JCE_CH139" "0: Injected conversion is disabled for CH[139].,1: Injected conversion is enabled for CH[139]." bitfld.long 0x0 10. "JCE_CH138,JCE_CH138" "0: Injected conversion is disabled for CH[138].,1: Injected conversion is enabled for CH[138]." newline bitfld.long 0x0 9. "JCE_CH137,JCE_CH137" "0: Injected conversion is disabled for CH[137].,1: Injected conversion is enabled for CH[137]." bitfld.long 0x0 8. "JCE_CH136,JCE_CH136" "0: Injected conversion is disabled for CH[136].,1: Injected conversion is enabled for CH[136]." newline bitfld.long 0x0 7. "JCE_CH135,JCE_CH135" "0: Injected conversion is disabled for CH[135].,1: Injected conversion is enabled for CH[135]." bitfld.long 0x0 6. "JCE_CH134,JCE_CH134" "0: Injected conversion is disabled for CH[134].,1: Injected conversion is enabled for CH[134]." newline bitfld.long 0x0 5. "JCE_CH133,JCE_CH133" "0: Injected conversion is disabled for CH[133].,1: Injected conversion is enabled for CH[133]." bitfld.long 0x0 4. "JCE_CH132,JCE_CH132" "0: Injected conversion is disabled for CH[132].,1: Injected conversion is enabled for CH[132]." newline bitfld.long 0x0 3. "JCE_CH131,JCE_CH131" "0: Injected conversion is disabled for CH[131].,1: Injected conversion is enabled for CH[131]." bitfld.long 0x0 2. "JCE_CH130,JCE_CH130" "0: Injected conversion is disabled for CH[130].,1: Injected conversion is enabled for CH[130]." newline bitfld.long 0x0 1. "JCE_CH129,JCE_CH129" "0: Injected conversion is disabled for CH[129].,1: Injected conversion is enabled for CH[129]." bitfld.long 0x0 0. "JCE_CH128,JCE_CH128" "0: Injected conversion is disabled for CH[128].,1: Injected conversion is enabled for CH[128]." line.long 0x4 "ECJCMR1,External Channel Injected Conversion Mask Register 1" bitfld.long 0x4 31. "JCE_CH191,JCE_CH191" "0: Injected conversion is disabled for CH[191].,1: Injected conversion is enabled for CH[191]." bitfld.long 0x4 30. "JCE_CH190,JCE_CH190" "0: Injected conversion is disabled for CH[190].,1: Injected conversion is enabled for CH[190]." newline bitfld.long 0x4 29. "JCE_CH189,JCE_CH189" "0: Injected conversion is disabled for CH[189].,1: Injected conversion is enabled for CH[189]." bitfld.long 0x4 28. "JCE_CH188,JCE_CH188" "0: Injected conversion is disabled for CH[188].,1: Injected conversion is enabled for CH[188]." newline bitfld.long 0x4 27. "JCE_CH187,JCE_CH187" "0: Injected conversion is disabled for CH[187].,1: Injected conversion is enabled for CH[187]." bitfld.long 0x4 26. "JCE_CH186,JCE_CH186" "0: Injected conversion is disabled for CH[186].,1: Injected conversion is enabled for CH[186]." newline bitfld.long 0x4 25. "JCE_CH185,JCE_CH185" "0: Injected conversion is disabled for CH[185].,1: Injected conversion is enabled for CH[185]." bitfld.long 0x4 24. "JCE_CH184,JCE_CH184" "0: Injected conversion is disabled for CH[184].,1: Injected conversion is enabled for CH[184]." newline bitfld.long 0x4 23. "JCE_CH183,JCE_CH183" "0: Injected conversion is disabled for CH[183].,1: Injected conversion is enabled for CH[183]." bitfld.long 0x4 22. "JCE_CH182,JCE_CH182" "0: Injected conversion is disabled for CH[182].,1: Injected conversion is enabled for CH[182]." newline bitfld.long 0x4 21. "JCE_CH181,JCE_CH181" "0: Injected conversion is disabled for CH[181].,1: Injected conversion is enabled for CH[181]." bitfld.long 0x4 20. "JCE_CH180,JCE_CH180" "0: Injected conversion is disabled for CH[180].,1: Injected conversion is enabled for CH[180]." newline bitfld.long 0x4 19. "JCE_CH179,JCE_CH179" "0: Injected conversion is disabled for CH[179].,1: Injected conversion is enabled for CH[179]." bitfld.long 0x4 18. "JCE_CH178,JCE_CH178" "0: Injected conversion is disabled for CH[178].,1: Injected conversion is enabled for CH[178]." newline bitfld.long 0x4 17. "JCE_CH177,JCE_CH177" "0: Injected conversion is disabled for CH[177].,1: Injected conversion is enabled for CH[177]." bitfld.long 0x4 16. "JCE_CH176,JCE_CH176" "0: Injected conversion is disabled for CH[176].,1: Injected conversion is enabled for CH[176]." newline bitfld.long 0x4 15. "JCE_CH175,JCE_CH175" "0: Injected conversion is disabled for CH[175].,1: Injected conversion is enabled for CH[175]." bitfld.long 0x4 14. "JCE_CH174,JCE_CH174" "0: Injected conversion is disabled for CH[174].,1: Injected conversion is enabled for CH[174]." newline bitfld.long 0x4 13. "JCE_CH173,JCE_CH173" "0: Injected conversion is disabled for CH[173].,1: Injected conversion is enabled for CH[173]." bitfld.long 0x4 12. "JCE_CH172,JCE_CH172" "0: Injected conversion is disabled for CH[172].,1: Injected conversion is enabled for CH[172]." newline bitfld.long 0x4 11. "JCE_CH171,JCE_CH171" "0: Injected conversion is disabled for CH[171].,1: Injected conversion is enabled for CH[171]." bitfld.long 0x4 10. "JCE_CH170,JCE_CH170" "0: Injected conversion is disabled for CH[170].,1: Injected conversion is enabled for CH[170]." newline bitfld.long 0x4 9. "JCE_CH169,JCE_CH169" "0: Injected conversion is disabled for CH[169].,1: Injected conversion is enabled for CH[169]." bitfld.long 0x4 8. "JCE_CH168,JCE_CH168" "0: Injected conversion is disabled for CH[168].,1: Injected conversion is enabled for CH[168]." newline bitfld.long 0x4 7. "JCE_CH167,JCE_CH167" "0: Injected conversion is disabled for CH[167].,1: Injected conversion is enabled for CH[167]." bitfld.long 0x4 6. "JCE_CH166,JCE_CH166" "0: Injected conversion is disabled for CH[166].,1: Injected conversion is enabled for CH[166]." newline bitfld.long 0x4 5. "JCE_CH165,JCE_CH165" "0: Injected conversion is disabled for CH[165].,1: Injected conversion is enabled for CH[165]." bitfld.long 0x4 4. "JCE_CH164,JCE_CH164" "0: Injected conversion is disabled for CH[164].,1: Injected conversion is enabled for CH[164]." newline bitfld.long 0x4 3. "JCE_CH163,JCE_CH163" "0: Injected conversion is disabled for CH[163].,1: Injected conversion is enabled for CH[163]." bitfld.long 0x4 2. "JCE_CH162,JCE_CH162" "0: Injected conversion is disabled for CH[162].,1: Injected conversion is enabled for CH[162]." newline bitfld.long 0x4 1. "JCE_CH161,JCE_CH161" "0: Injected conversion is disabled for CH[161].,1: Injected conversion is enabled for CH[161]." bitfld.long 0x4 0. "JCE_CH160,JCE_CH160" "0: Injected conversion is disabled for CH[160].,1: Injected conversion is enabled for CH[160]." group.long 0x560++0x1F line.long 0x0 "ECWSELR0,External Channel Watchdog Selection Register 0" bitfld.long 0x0 28.--30. "WSEL_CH135,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "WSEL_CH134,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "WSEL_CH133,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "WSEL_CH132,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "WSEL_CH131,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "WSEL_CH130,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "WSEL_CH129,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "WSEL_CH128,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" line.long 0x4 "ECWSELR1,External Channel Watchdog Selection Register 1" bitfld.long 0x4 28.--30. "WSEL_CH143,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "WSEL_CH142,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20.--22. "WSEL_CH141,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "WSEL_CH140,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12.--14. "WSEL_CH139,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "WSEL_CH138,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "WSEL_CH137,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "WSEL_CH136,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" line.long 0x8 "ECWSELR2,External Channel Watchdog Selection Register 2" bitfld.long 0x8 28.--30. "WSEL_CH151,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "WSEL_CH150,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20.--22. "WSEL_CH149,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "WSEL_CH148,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 12.--14. "WSEL_CH147,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "WSEL_CH146,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4.--6. "WSEL_CH145,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "WSEL_CH144,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" line.long 0xC "ECWSELR3,External Channel Watchdog Selection Register 3" bitfld.long 0xC 28.--30. "WSEL_CH159,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "WSEL_CH158,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 20.--22. "WSEL_CH157,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "WSEL_CH156,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "WSEL_CH155,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--10. "WSEL_CH154,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4.--6. "WSEL_CH153,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "WSEL_CH152,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" line.long 0x10 "ECWSELR4,External Channel Watchdog Selection Register 4" bitfld.long 0x10 28.--30. "WSEL_CH167,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "WSEL_CH166,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 20.--22. "WSEL_CH165,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "WSEL_CH164,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 12.--14. "WSEL_CH163,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8.--10. "WSEL_CH162,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 4.--6. "WSEL_CH161,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "WSEL_CH160,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" line.long 0x14 "ECWSELR5,External Channel Watchdog Selection Register 5" bitfld.long 0x14 28.--30. "WSEL_CH175,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "WSEL_CH174,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 20.--22. "WSEL_CH173,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "WSEL_CH172,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "WSEL_CH171,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x14 8.--10. "WSEL_CH170,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 4.--6. "WSEL_CH169,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "WSEL_CH168,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" line.long 0x18 "ECWSELR6,External Channel Watchdog Selection Register 6" bitfld.long 0x18 28.--30. "WSEL_CH183,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "WSEL_CH182,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 20.--22. "WSEL_CH181,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "WSEL_CH180,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "WSEL_CH179,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x18 8.--10. "WSEL_CH178,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 4.--6. "WSEL_CH177,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "WSEL_CH176,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" line.long 0x1C "ECWSELR7,External Channel Watchdog Selection Register 7" bitfld.long 0x1C 28.--30. "WSEL_CH191,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--26. "WSEL_CH190,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 20.--22. "WSEL_CH189,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 16.--18. "WSEL_CH188,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 12.--14. "WSEL_CH187,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 8.--10. "WSEL_CH186,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 4.--6. "WSEL_CH185,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "WSEL_CH184,0000 THRHLR0 register is selected" "0,1,2,3,4,5,6,7" group.long 0x5A0++0x7 line.long 0x0 "ECWENR0,External Channel Watchdog Enable Register 0" bitfld.long 0x0 31. "WEN_CH159,WEN_CH159" "0: Watchdog feature is disabled for CH[159].,1: Watchdog feature is enabled for CH[159]." bitfld.long 0x0 30. "WEN_CH158,WEN_CH158" "0: Watchdog feature is disabled for CH[158].,1: Watchdog feature is enabled for CH[158]." newline bitfld.long 0x0 29. "WEN_CH157,WEN_CH157" "0: Watchdog feature is disabled for CH[157].,1: Watchdog feature is enabled for CH[157]." bitfld.long 0x0 28. "WEN_CH156,WEN_CH156" "0: Watchdog feature is disabled for CH[156].,1: Watchdog feature is enabled for CH[156]." newline bitfld.long 0x0 27. "WEN_CH155,WEN_CH155" "0: Watchdog feature is disabled for CH[155].,1: Watchdog feature is enabled for CH[155]." bitfld.long 0x0 26. "WEN_CH154,WEN_CH154" "0: Watchdog feature is disabled for CH[154].,1: Watchdog feature is enabled for CH[154]." newline bitfld.long 0x0 25. "WEN_CH153,WEN_CH153" "0: Watchdog feature is disabled for CH[153].,1: Watchdog feature is enabled for CH[153]." bitfld.long 0x0 24. "WEN_CH152,WEN_CH152" "0: Watchdog feature is disabled for CH[152].,1: Watchdog feature is enabled for CH[152]." newline bitfld.long 0x0 23. "WEN_CH151,WEN_CH151" "0: Watchdog feature is disabled for CH[151].,1: Watchdog feature is enabled for CH[151]." bitfld.long 0x0 22. "WEN_CH150,WEN_CH150" "0: Watchdog feature is disabled for CH[150].,1: Watchdog feature is enabled for CH[150]." newline bitfld.long 0x0 21. "WEN_CH149,WEN_CH149" "0: Watchdog feature is disabled for CH[149].,1: Watchdog feature is enabled for CH[149]." bitfld.long 0x0 20. "WEN_CH148,WEN_CH148" "0: Watchdog feature is disabled for CH[148].,1: Watchdog feature is enabled for CH[148]." newline bitfld.long 0x0 19. "WEN_CH147,WEN_CH147" "0: Watchdog feature is disabled for CH[147].,1: Watchdog feature is enabled for CH[147]." bitfld.long 0x0 18. "WEN_CH146,WEN_CH146" "0: Watchdog feature is disabled for CH[146].,1: Watchdog feature is enabled for CH[146]." newline bitfld.long 0x0 17. "WEN_CH145,WEN_CH145" "0: Watchdog feature is disabled for CH[145].,1: Watchdog feature is enabled for CH[145]." bitfld.long 0x0 16. "WEN_CH144,WEN_CH144" "0: Watchdog feature is disabled for CH[144].,1: Watchdog feature is enabled for CH[144]." newline bitfld.long 0x0 15. "WEN_CH143,WEN_CH143" "0: Watchdog feature is disabled for CH[143].,1: Watchdog feature is enabled for CH[143]." bitfld.long 0x0 14. "WEN_CH142,WEN_CH142" "0: Watchdog feature is disabled for CH[142].,1: Watchdog feature is enabled for CH[142]." newline bitfld.long 0x0 13. "WEN_CH141,WEN_CH141" "0: Watchdog feature is disabled for CH[141].,1: Watchdog feature is enabled for CH[141]." bitfld.long 0x0 12. "WEN_CH140,WEN_CH140" "0: Watchdog feature is disabled for CH[140].,1: Watchdog feature is enabled for CH[140]." newline bitfld.long 0x0 11. "WEN_CH139,WEN_CH139" "0: Watchdog feature is disabled for CH[139].,1: Watchdog feature is enabled for CH[139]." bitfld.long 0x0 10. "WEN_CH138,WEN_CH138" "0: Watchdog feature is disabled for CH[138].,1: Watchdog feature is enabled for CH[138]." newline bitfld.long 0x0 9. "WEN_CH137,WEN_CH137" "0: Watchdog feature is disabled for CH[137].,1: Watchdog feature is enabled for CH[137]." bitfld.long 0x0 8. "WEN_CH136,WEN_CH136" "0: Watchdog feature is disabled for CH[136].,1: Watchdog feature is enabled for CH[136]." newline bitfld.long 0x0 7. "WEN_CH135,WEN_CH135" "0: Watchdog feature is disabled for CH[135].,1: Watchdog feature is enabled for CH[135]." bitfld.long 0x0 6. "WEN_CH134,WEN_CH134" "0: Watchdog feature is disabled for CH[134].,1: Watchdog feature is enabled for CH[134]." newline bitfld.long 0x0 5. "WEN_CH133,WEN_CH133" "0: Watchdog feature is disabled for CH[133].,1: Watchdog feature is enabled for CH[133]." bitfld.long 0x0 4. "WEN_CH132,WEN_CH132" "0: Watchdog feature is disabled for CH[132].,1: Watchdog feature is enabled for CH[132]." newline bitfld.long 0x0 3. "WEN_CH131,WEN_CH131" "0: Watchdog feature is disabled for CH[131].,1: Watchdog feature is enabled for CH[131]." bitfld.long 0x0 2. "WEN_CH130,WEN_CH130" "0: Watchdog feature is disabled for CH[130].,1: Watchdog feature is enabled for CH[130]." newline bitfld.long 0x0 1. "WEN_CH129,WEN_CH129" "0: Watchdog feature is disabled for CH[129].,1: Watchdog feature is enabled for CH[129]." bitfld.long 0x0 0. "WEN_CH128,WEN_CH128" "0: Watchdog feature is disabled for CH[128].,1: Watchdog feature is enabled for CH[128]." line.long 0x4 "ECWENR1,External Channel Watchdog Enable Register 1" bitfld.long 0x4 31. "WEN_CH191,WEN_CH191" "0: Watchdog feature is disabled for CH[191].,1: Watchdog feature is enabled for CH[191]." bitfld.long 0x4 30. "WEN_CH190,WEN_CH190" "0: Watchdog feature is disabled for CH[190].,1: Watchdog feature is enabled for CH[190]." newline bitfld.long 0x4 29. "WEN_CH189,WEN_CH189" "0: Watchdog feature is disabled for CH[189].,1: Watchdog feature is enabled for CH[189]." bitfld.long 0x4 28. "WEN_CH188,WEN_CH188" "0: Watchdog feature is disabled for CH[188].,1: Watchdog feature is enabled for CH[188]." newline bitfld.long 0x4 27. "WEN_CH187,WEN_CH187" "0: Watchdog feature is disabled for CH[187].,1: Watchdog feature is enabled for CH[187]." bitfld.long 0x4 26. "WEN_CH186,WEN_CH186" "0: Watchdog feature is disabled for CH[186].,1: Watchdog feature is enabled for CH[186]." newline bitfld.long 0x4 25. "WEN_CH185,WEN_CH185" "0: Watchdog feature is disabled for CH[185].,1: Watchdog feature is enabled for CH[185]." bitfld.long 0x4 24. "WEN_CH184,WEN_CH184" "0: Watchdog feature is disabled for CH[184].,1: Watchdog feature is enabled for CH[184]." newline bitfld.long 0x4 23. "WEN_CH183,WEN_CH183" "0: Watchdog feature is disabled for CH[183].,1: Watchdog feature is enabled for CH[183]." bitfld.long 0x4 22. "WEN_CH182,WEN_CH182" "0: Watchdog feature is disabled for CH[182].,1: Watchdog feature is enabled for CH[182]." newline bitfld.long 0x4 21. "WEN_CH181,WEN_CH181" "0: Watchdog feature is disabled for CH[181].,1: Watchdog feature is enabled for CH[181]." bitfld.long 0x4 20. "WEN_CH180,WEN_CH180" "0: Watchdog feature is disabled for CH[180].,1: Watchdog feature is enabled for CH[180]." newline bitfld.long 0x4 19. "WEN_CH179,WEN_CH179" "0: Watchdog feature is disabled for CH[179].,1: Watchdog feature is enabled for CH[179]." bitfld.long 0x4 18. "WEN_CH178,WEN_CH178" "0: Watchdog feature is disabled for CH[178].,1: Watchdog feature is enabled for CH[178]." newline bitfld.long 0x4 17. "WEN_CH177,WEN_CH177" "0: Watchdog feature is disabled for CH[177].,1: Watchdog feature is enabled for CH[177]." bitfld.long 0x4 16. "WEN_CH176,WEN_CH176" "0: Watchdog feature is disabled for CH[176].,1: Watchdog feature is enabled for CH[176]." newline bitfld.long 0x4 15. "WEN_CH175,WEN_CH175" "0: Watchdog feature is disabled for CH[175].,1: Watchdog feature is enabled for CH[175]." bitfld.long 0x4 14. "WEN_CH174,WEN_CH174" "0: Watchdog feature is disabled for CH[174].,1: Watchdog feature is enabled for CH[174]." newline bitfld.long 0x4 13. "WEN_CH173,WEN_CH173" "0: Watchdog feature is disabled for CH[173].,1: Watchdog feature is enabled for CH[173]." bitfld.long 0x4 12. "WEN_CH172,WEN_CH172" "0: Watchdog feature is disabled for CH[172].,1: Watchdog feature is enabled for CH[172]." newline bitfld.long 0x4 11. "WEN_CH171,WEN_CH171" "0: Watchdog feature is disabled for CH[171].,1: Watchdog feature is enabled for CH[171]." bitfld.long 0x4 10. "WEN_CH170,WEN_CH170" "0: Watchdog feature is disabled for CH[170].,1: Watchdog feature is enabled for CH[170]." newline bitfld.long 0x4 9. "WEN_CH169,WEN_CH169" "0: Watchdog feature is disabled for CH[169].,1: Watchdog feature is enabled for CH[169]." bitfld.long 0x4 8. "WEN_CH168,WEN_CH168" "0: Watchdog feature is disabled for CH[168].,1: Watchdog feature is enabled for CH[168]." newline bitfld.long 0x4 7. "WEN_CH167,WEN_CH167" "0: Watchdog feature is disabled for CH[167].,1: Watchdog feature is enabled for CH[167]." bitfld.long 0x4 6. "WEN_CH166,WEN_CH166" "0: Watchdog feature is disabled for CH[166].,1: Watchdog feature is enabled for CH[166]." newline bitfld.long 0x4 5. "WEN_CH165,WEN_CH165" "0: Watchdog feature is disabled for CH[165].,1: Watchdog feature is enabled for CH[165]." bitfld.long 0x4 4. "WEN_CH164,WEN_CH164" "0: Watchdog feature is disabled for CH[164].,1: Watchdog feature is enabled for CH[164]." newline bitfld.long 0x4 3. "WEN_CH163,WEN_CH163" "0: Watchdog feature is disabled for CH[163].,1: Watchdog feature is enabled for CH[163]." bitfld.long 0x4 2. "WEN_CH162,WEN_CH162" "0: Watchdog feature is disabled for CH[162].,1: Watchdog feature is enabled for CH[162]." newline bitfld.long 0x4 1. "WEN_CH161,WEN_CH161" "0: Watchdog feature is disabled for CH[161].,1: Watchdog feature is enabled for CH[161]." bitfld.long 0x4 0. "WEN_CH160,WEN_CH160" "0: Watchdog feature is disabled for CH[160].,1: Watchdog feature is enabled for CH[160]." group.long 0x5B0++0x7 line.long 0x0 "ECAWORR0,External Channel Analog Watchdog Out of Range Register 0" bitfld.long 0x0 31. "AWOR_CH159,Analog watchdog out of range status for channel 159 provided corresponding WEN_CH159 bit is set." "0: CH[159] converted data is not out of range..,1: CH[159] converted data is out of range.." bitfld.long 0x0 30. "AWOR_CH158,Analog watchdog out of range status for channel 158 provided corresponding WEN_CH158 bit is set." "0: CH[158] converted data is not out of range..,1: CH[158] converted data is out of range.." newline bitfld.long 0x0 29. "AWOR_CH157,Analog watchdog out of range status for channel 157 provided corresponding WEN_CH157 bit is set." "0: CH[157] converted data is not out of range..,1: CH[157] converted data is out of range.." bitfld.long 0x0 28. "AWOR_CH156,Analog watchdog out of range status for channel 156 provided corresponding WEN_CH156 bit is set." "0: CH[156] converted data is not out of range..,1: CH[156] converted data is out of range.." newline bitfld.long 0x0 27. "AWOR_CH155,Analog watchdog out of range status for channel 155 provided corresponding WEN_CH155 bit is set." "0: CH[155] converted data is not out of range..,1: CH[155] converted data is out of range.." bitfld.long 0x0 26. "AWOR_CH154,Analog watchdog out of range status for channel 154 provided corresponding WEN_CH154 bit is set." "0: CH[154] converted data is not out of range..,1: CH[154] converted data is out of range.." newline bitfld.long 0x0 25. "AWOR_CH153,Analog watchdog out of range status for channel 153 provided corresponding WEN_CH153 bit is set." "0: CH[153] converted data is not out of range..,1: CH[153] converted data is out of range.." bitfld.long 0x0 24. "AWOR_CH152,Analog watchdog out of range status for channel 152 provided corresponding WEN_CH152 bit is set." "0: CH[152] converted data is not out of range..,1: CH[152] converted data is out of range.." newline bitfld.long 0x0 23. "AWOR_CH151,Analog watchdog out of range status for channel 151 provided corresponding WEN_CH151 bit is set." "0: CH[151] converted data is not out of range..,1: CH[151] converted data is out of range.." bitfld.long 0x0 22. "AWOR_CH150,Analog watchdog out of range status for channel 150 provided corresponding WEN_CH150 bit is set." "0: CH[150] converted data is not out of range..,1: CH[150] converted data is out of range.." newline bitfld.long 0x0 21. "AWOR_CH149,Analog watchdog out of range status for channel 149 provided corresponding WEN_CH149 bit is set." "0: CH[149] converted data is not out of range..,1: CH[149] converted data is out of range.." bitfld.long 0x0 20. "AWOR_CH148,Analog watchdog out of range status for channel 148 provided corresponding WEN_CH148 bit is set." "0: CH[148] converted data is not out of range..,1: CH[148] converted data is out of range.." newline bitfld.long 0x0 19. "AWOR_CH147,Analog watchdog out of range status for channel 147 provided corresponding WEN_CH147 bit is set." "0: CH[147] converted data is not out of range..,1: CH[147] converted data is out of range.." bitfld.long 0x0 18. "AWOR_CH146,Analog watchdog out of range status for channel 146 provided corresponding WEN_CH146 bit is set." "0: CH[146] converted data is not out of range..,1: CH[146] converted data is out of range.." newline bitfld.long 0x0 17. "AWOR_CH145,Analog watchdog out of range status for channel 145 provided corresponding WEN_CH145 bit is set." "0: CH[145] converted data is not out of range..,1: CH[145] converted data is out of range.." bitfld.long 0x0 16. "AWOR_CH144,Analog watchdog out of range status for channel 144 provided corresponding WEN_CH144 bit is set." "0: CH[144] converted data is not out of range..,1: CH[144] converted data is out of range.." newline bitfld.long 0x0 15. "AWOR_CH143,Analog watchdog out of range status for channel 143 provided corresponding WEN_CH143 bit is set." "0: CH[143] converted data is not out of range..,1: CH[143] converted data is out of range.." bitfld.long 0x0 14. "AWOR_CH142,Analog watchdog out of range status for channel 142 provided corresponding WEN_CH142 bit is set." "0: CH[142] converted data is not out of range..,1: CH[142] converted data is out of range.." newline bitfld.long 0x0 13. "AWOR_CH141,Analog watchdog out of range status for channel 141 provided corresponding WEN_CH141 bit is set." "0: CH[141] converted data is not out of range..,1: CH[141] converted data is out of range.." bitfld.long 0x0 12. "AWOR_CH140,Analog watchdog out of range status for channel 140 provided corresponding WEN_CH140 bit is set." "0: CH[140] converted data is not out of range..,1: CH[140] converted data is out of range.." newline bitfld.long 0x0 11. "AWOR_CH139,Analog watchdog out of range status for channel 139 provided corresponding WEN_CH139 bit is set." "0: CH[139] converted data is not out of range..,1: CH[139] converted data is out of range.." bitfld.long 0x0 10. "AWOR_CH138,Analog watchdog out of range status for channel 138 provided corresponding WEN_CH138 bit is set." "0: CH[138] converted data is not out of range..,1: CH[138] converted data is out of range.." newline bitfld.long 0x0 9. "AWOR_CH137,Analog watchdog out of range status for channel 137 provided corresponding WEN_CH137 bit is set." "0: CH[137] converted data is not out of range..,1: CH[137] converted data is out of range.." bitfld.long 0x0 8. "AWOR_CH136,Analog watchdog out of range status for channel 136 provided corresponding WEN_CH136 bit is set." "0: CH[136] converted data is not out of range..,1: CH[136] converted data is out of range.." newline bitfld.long 0x0 7. "AWOR_CH135,Analog watchdog out of range status for channel 135 provided corresponding WEN_CH135 bit is set." "0: CH[135] converted data is not out of range..,1: CH[135] converted data is out of range.." bitfld.long 0x0 6. "AWOR_CH134,Analog watchdog out of range status for channel 134 provided corresponding WEN_CH134 bit is set." "0: CH[134] converted data is not out of range..,1: CH[134] converted data is out of range.." newline bitfld.long 0x0 5. "AWOR_CH133,Analog watchdog out of range status for channel 133 provided corresponding WEN_CH133 bit is set." "0: CH[133] converted data is not out of range..,1: CH[133] converted data is out of range.." bitfld.long 0x0 4. "AWOR_CH132,Analog watchdog out of range status for channel 132 provided corresponding WEN_CH132 bit is set." "0: CH[132] converted data is not out of range..,1: CH[132] converted data is out of range.." newline bitfld.long 0x0 3. "AWOR_CH131,Analog watchdog out of range status for channel 131 provided corresponding WEN_CH131 bit is set." "0: CH[131] converted data is not out of range..,1: CH[131] converted data is out of range.." bitfld.long 0x0 2. "AWOR_CH130,Analog watchdog out of range status for channel 130 provided corresponding WEN_CH130 bit is set." "0: CH[130] converted data is not out of range..,1: CH[130] converted data is out of range.." newline bitfld.long 0x0 1. "AWOR_CH129,Analog watchdog out of range status for channel 129 provided corresponding WEN_CH129 bit is set." "0: CH[129] converted data is not out of range..,1: CH[129] converted data is out of range.." bitfld.long 0x0 0. "AWOR_CH128,Analog watchdog out of range status for channel 128 provided corresponding WEN_CH128 bit is set." "0: CH[128] converted data is not out of range..,1: CH[128] converted data is out of range.." line.long 0x4 "ECAWORR1,External Channel Analog Watchdog Out of Range Register 1" bitfld.long 0x4 31. "AWOR_CH191,Analog watchdog out of range status for channel 191 provided corresponding WEN_CH191 bit is set." "0: CH[191] converted data is not out of range..,1: CH[191] converted data is out of range.." bitfld.long 0x4 30. "AWOR_CH190,Analog watchdog out of range status for channel 190 provided corresponding WEN_CH190 bit is set." "0: CH[190] converted data is not out of range..,1: CH[190] converted data is out of range.." newline bitfld.long 0x4 29. "AWOR_CH189,Analog watchdog out of range status for channel 189 provided corresponding WEN_CH189 bit is set." "0: CH[189] converted data is not out of range..,1: CH[189] converted data is out of range.." bitfld.long 0x4 28. "AWOR_CH188,Analog watchdog out of range status for channel 188 provided corresponding WEN_CH188 bit is set." "0: CH[188] converted data is not out of range..,1: CH[188] converted data is out of range.." newline bitfld.long 0x4 27. "AWOR_CH187,Analog watchdog out of range status for channel 187 provided corresponding WEN_CH187 bit is set." "0: CH[187] converted data is not out of range..,1: CH[187] converted data is out of range.." bitfld.long 0x4 26. "AWOR_CH186,Analog watchdog out of range status for channel 186 provided corresponding WEN_CH186 bit is set." "0: CH[186] converted data is not out of range..,1: CH[186] converted data is out of range.." newline bitfld.long 0x4 25. "AWOR_CH185,Analog watchdog out of range status for channel 185 provided corresponding WEN_CH185 bit is set." "0: CH[185] converted data is not out of range..,1: CH[185] converted data is out of range.." bitfld.long 0x4 24. "AWOR_CH184,Analog watchdog out of range status for channel 184 provided corresponding WEN_CH184 bit is set." "0: CH[184] converted data is not out of range..,1: CH[184] converted data is out of range.." newline bitfld.long 0x4 23. "AWOR_CH183,Analog watchdog out of range status for channel 183 provided corresponding WEN_CH183 bit is set." "0: CH[183] converted data is not out of range..,1: CH[183] converted data is out of range.." bitfld.long 0x4 22. "AWOR_CH182,Analog watchdog out of range status for channel 182 provided corresponding WEN_CH182 bit is set." "0: CH[182] converted data is not out of range..,1: CH[182] converted data is out of range.." newline bitfld.long 0x4 21. "AWOR_CH181,Analog watchdog out of range status for channel 181 provided corresponding WEN_CH181 bit is set." "0: CH[181] converted data is not out of range..,1: CH[181] converted data is out of range.." bitfld.long 0x4 20. "AWOR_CH180,Analog watchdog out of range status for channel 180 provided corresponding WEN_CH180 bit is set." "0: CH[180] converted data is not out of range..,1: CH[180] converted data is out of range.." newline bitfld.long 0x4 19. "AWOR_CH179,Analog watchdog out of range status for channel 179 provided corresponding WEN_CH179 bit is set." "0: CH[179] converted data is not out of range..,1: CH[179] converted data is out of range.." bitfld.long 0x4 18. "AWOR_CH178,Analog watchdog out of range status for channel 178 provided corresponding WEN_CH178 bit is set." "0: CH[178] converted data is not out of range..,1: CH[178] converted data is out of range.." newline bitfld.long 0x4 17. "AWOR_CH177,Analog watchdog out of range status for channel 177 provided corresponding WEN_CH177 bit is set." "0: CH[177] converted data is not out of range..,1: CH[177] converted data is out of range.." bitfld.long 0x4 16. "AWOR_CH176,Analog watchdog out of range status for channel 176 provided corresponding WEN_CH176 bit is set." "0: CH[176] converted data is not out of range..,1: CH[176] converted data is out of range.." newline bitfld.long 0x4 15. "AWOR_CH175,Analog watchdog out of range status for channel 175 provided corresponding WEN_CH175 bit is set." "0: CH[175] converted data is not out of range..,1: CH[175] converted data is out of range.." bitfld.long 0x4 14. "AWOR_CH174,Analog watchdog out of range status for channel 174 provided corresponding WEN_CH174 bit is set." "0: CH[174] converted data is not out of range..,1: CH[174] converted data is out of range.." newline bitfld.long 0x4 13. "AWOR_CH173,Analog watchdog out of range status for channel 173 provided corresponding WEN_CH173 bit is set." "0: CH[173] converted data is not out of range..,1: CH[173] converted data is out of range.." bitfld.long 0x4 12. "AWOR_CH172,Analog watchdog out of range status for channel 172 provided corresponding WEN_CH172 bit is set." "0: CH[172] converted data is not out of range..,1: CH[172] converted data is out of range.." newline bitfld.long 0x4 11. "AWOR_CH171,Analog watchdog out of range status for channel 171 provided corresponding WEN_CH171 bit is set." "0: CH[171] converted data is not out of range..,1: CH[171] converted data is out of range.." bitfld.long 0x4 10. "AWOR_CH170,Analog watchdog out of range status for channel 170 provided corresponding WEN_CH170 bit is set." "0: CH[170] converted data is not out of range..,1: CH[170] converted data is out of range.." newline bitfld.long 0x4 9. "AWOR_CH169,Analog watchdog out of range status for channel 169 provided corresponding WEN_CH169 bit is set." "0: CH[169] converted data is not out of range..,1: CH[169] converted data is out of range.." bitfld.long 0x4 8. "AWOR_CH168,Analog watchdog out of range status for channel 168 provided corresponding WEN_CH168 bit is set." "0: CH[168] converted data is not out of range..,1: CH[168] converted data is out of range.." newline bitfld.long 0x4 7. "AWOR_CH167,Analog watchdog out of range status for channel 167 provided corresponding WEN_CH167 bit is set." "0: CH[167] converted data is not out of range..,1: CH[167] converted data is out of range.." bitfld.long 0x4 6. "AWOR_CH166,Analog watchdog out of range status for channel 166 provided corresponding WEN_CH166 bit is set." "0: CH[166] converted data is not out of range..,1: CH[166] converted data is out of range.." newline bitfld.long 0x4 5. "AWOR_CH165,Analog watchdog out of range status for channel 165 provided corresponding WEN_CH165 bit is set." "0: CH[165] converted data is not out of range..,1: CH[165] converted data is out of range.." bitfld.long 0x4 4. "AWOR_CH164,Analog watchdog out of range status for channel 164 provided corresponding WEN_CH164 bit is set." "0: CH[164] converted data is not out of range..,1: CH[164] converted data is out of range.." newline bitfld.long 0x4 3. "AWOR_CH163,Analog watchdog out of range status for channel 163 provided corresponding WEN_CH163 bit is set." "0: CH[163] converted data is not out of range..,1: CH[163] converted data is out of range.." bitfld.long 0x4 2. "AWOR_CH162,Analog watchdog out of range status for channel 162 provided corresponding WEN_CH162 bit is set." "0: CH[162] converted data is not out of range..,1: CH[162] converted data is out of range.." newline bitfld.long 0x4 1. "AWOR_CH161,Analog watchdog out of range status for channel 161 provided corresponding WEN_CH161 bit is set." "0: CH[161] converted data is not out of range..,1: CH[161] converted data is out of range.." bitfld.long 0x4 0. "AWOR_CH160,Analog watchdog out of range status for channel 160 provided corresponding WEN_CH160 bit is set." "0: CH[160] converted data is not out of range..,1: CH[160] converted data is out of range.." group.long 0x5C0++0x7 line.long 0x0 "ECMICR0,External Channel Mapping to Internal Channel Register 0" hexmask.long.byte 0x0 24.--30. 1. "ICSEL_ECH152_159,Internal channel selection for external channels (128 + 8x) to (135+8*x) where x = 0 1 2..15" hexmask.long.byte 0x0 16.--22. 1. "ICSEL_ECH144_151,Internal channel selection for external channels (128 + 8x) to (135+8*x) where x = 0 1 2..15" newline hexmask.long.byte 0x0 8.--14. 1. "ICSEL_ECH136_143,Internal channel selection for external channels (128 + 8x) to (135+8*x) where x = 0 1 2..15" hexmask.long.byte 0x0 0.--6. 1. "ICSEL_ECH128_135,Internal channel selection for external channels (128 + 8x) to (135+8*x) where x = 0 1 2..15" line.long 0x4 "ECMICR1,External Channel Mapping to Internal Channel Register 1" hexmask.long.byte 0x4 24.--30. 1. "ICSEL_ECH184_191,Internal channel selection for external channels (128 + 8x) to (135+8*x) where x = 0 1 2..15" hexmask.long.byte 0x4 16.--22. 1. "ICSEL_ECH176_183,Internal channel selection for external channels (128 + 8x) to (135+8*x) where x = 0 1 2..15" newline hexmask.long.byte 0x4 8.--14. 1. "ICSEL_ECH168_175,Internal channel selection for external channels (128 + 8x) to (135+8*x) where x = 0 1 2..15" hexmask.long.byte 0x4 0.--6. 1. "ICSEL_ECH160_167,Internal channel selection for external channels (128 + 8x) to (135+8*x) where x = 0 1 2..15" group.long 0x5D0++0xFF line.long 0x0 "ECDR128,External Channel Data Register 128" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x4 "ECDR129,External Channel Data Register 129" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x8 "ECDR130,External Channel Data Register 130" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xC "ECDR131,External Channel Data Register 131" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x10 "ECDR132,External Channel Data Register 132" bitfld.long 0x10 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x10 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x10 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x10 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x10 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x10 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x10 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x14 "ECDR133,External Channel Data Register 133" bitfld.long 0x14 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x14 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x14 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x14 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x14 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x14 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x14 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x18 "ECDR134,External Channel Data Register 134" bitfld.long 0x18 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x18 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x18 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x18 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x18 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x18 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x18 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x1C "ECDR135,External Channel Data Register 135" bitfld.long 0x1C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x1C 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x1C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x1C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x1C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x1C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x1C 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x20 "ECDR136,External Channel Data Register 136" bitfld.long 0x20 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x20 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x20 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x20 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x20 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x20 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x20 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x24 "ECDR137,External Channel Data Register 137" bitfld.long 0x24 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x24 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x24 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x24 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x24 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x24 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x24 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x28 "ECDR138,External Channel Data Register 138" bitfld.long 0x28 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x28 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x28 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x28 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x28 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x28 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x28 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x2C "ECDR139,External Channel Data Register 139" bitfld.long 0x2C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x2C 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x2C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x2C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x2C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x2C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x2C 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x30 "ECDR140,External Channel Data Register 140" bitfld.long 0x30 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x30 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x30 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x30 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x30 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x30 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x30 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x34 "ECDR141,External Channel Data Register 141" bitfld.long 0x34 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x34 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x34 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x34 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x34 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x34 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x34 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x38 "ECDR142,External Channel Data Register 142" bitfld.long 0x38 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x38 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x38 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x38 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x38 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x38 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x38 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x3C "ECDR143,External Channel Data Register 143" bitfld.long 0x3C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x3C 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x3C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x3C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x3C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x3C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x3C 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x40 "ECDR144,External Channel Data Register 144" bitfld.long 0x40 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x40 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x40 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x40 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x40 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x40 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x40 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x44 "ECDR145,External Channel Data Register 145" bitfld.long 0x44 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x44 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x44 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x44 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x44 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x44 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x44 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x48 "ECDR146,External Channel Data Register 146" bitfld.long 0x48 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x48 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x48 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x48 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x48 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x48 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x48 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x4C "ECDR147,External Channel Data Register 147" bitfld.long 0x4C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x4C 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x4C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x4C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x4C 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x50 "ECDR148,External Channel Data Register 148" bitfld.long 0x50 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x50 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x50 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x50 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x50 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x50 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x50 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x54 "ECDR149,External Channel Data Register 149" bitfld.long 0x54 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x54 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x54 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x54 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x54 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x54 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x54 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x58 "ECDR150,External Channel Data Register 150" bitfld.long 0x58 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x58 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x58 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x58 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x58 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x58 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x58 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x5C "ECDR151,External Channel Data Register 151" bitfld.long 0x5C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x5C 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x5C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x5C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x5C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x5C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x5C 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x60 "ECDR152,External Channel Data Register 152" bitfld.long 0x60 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x60 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x60 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x60 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x60 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x60 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x60 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x64 "ECDR153,External Channel Data Register 153" bitfld.long 0x64 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x64 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x64 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x64 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x64 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x64 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x64 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x68 "ECDR154,External Channel Data Register 154" bitfld.long 0x68 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x68 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x68 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x68 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x68 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x68 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x68 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x6C "ECDR155,External Channel Data Register 155" bitfld.long 0x6C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x6C 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x6C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x6C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x6C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x6C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x6C 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x70 "ECDR156,External Channel Data Register 156" bitfld.long 0x70 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x70 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x70 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x70 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x70 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x70 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x70 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x74 "ECDR157,External Channel Data Register 157" bitfld.long 0x74 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x74 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x74 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x74 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x74 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x74 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x74 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x78 "ECDR158,External Channel Data Register 158" bitfld.long 0x78 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x78 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x78 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x78 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x78 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x78 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x78 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x7C "ECDR159,External Channel Data Register 159" bitfld.long 0x7C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x7C 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x7C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x7C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x7C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x7C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x7C 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x80 "ECDR160,External Channel Data Register 160" bitfld.long 0x80 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x80 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x80 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x80 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x80 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x80 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x80 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x84 "ECDR161,External Channel Data Register 161" bitfld.long 0x84 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x84 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x84 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x84 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x84 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x84 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x84 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x88 "ECDR162,External Channel Data Register 162" bitfld.long 0x88 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x88 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x88 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x88 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x88 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x88 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x88 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x8C "ECDR163,External Channel Data Register 163" bitfld.long 0x8C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x8C 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x8C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x8C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x8C 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x90 "ECDR164,External Channel Data Register 164" bitfld.long 0x90 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x90 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x90 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x90 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x90 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x90 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x90 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x94 "ECDR165,External Channel Data Register 165" bitfld.long 0x94 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x94 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x94 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x94 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x94 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x94 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x94 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x98 "ECDR166,External Channel Data Register 166" bitfld.long 0x98 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x98 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x98 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x98 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x98 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x98 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x98 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x9C "ECDR167,External Channel Data Register 167" bitfld.long 0x9C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x9C 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x9C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x9C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x9C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x9C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x9C 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xA0 "ECDR168,External Channel Data Register 168" bitfld.long 0xA0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xA0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xA0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xA0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xA0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xA0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xA0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xA4 "ECDR169,External Channel Data Register 169" bitfld.long 0xA4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xA4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xA4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xA4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xA4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xA4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xA4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xA8 "ECDR170,External Channel Data Register 170" bitfld.long 0xA8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xA8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xA8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xA8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xA8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xA8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xA8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xAC "ECDR171,External Channel Data Register 171" bitfld.long 0xAC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xAC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xAC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xAC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xAC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xAC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xAC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xB0 "ECDR172,External Channel Data Register 172" bitfld.long 0xB0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xB0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xB0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xB0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xB0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xB0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xB0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xB4 "ECDR173,External Channel Data Register 173" bitfld.long 0xB4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xB4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xB4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xB4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xB4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xB4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xB4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xB8 "ECDR174,External Channel Data Register 174" bitfld.long 0xB8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xB8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xB8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xB8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xB8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xB8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xB8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xBC "ECDR175,External Channel Data Register 175" bitfld.long 0xBC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xBC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xBC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xBC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xBC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xBC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xBC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xC0 "ECDR176,External Channel Data Register 176" bitfld.long 0xC0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xC0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xC0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xC0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xC0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xC4 "ECDR177,External Channel Data Register 177" bitfld.long 0xC4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xC4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xC4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xC4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xC4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xC8 "ECDR178,External Channel Data Register 178" bitfld.long 0xC8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xC8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xC8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xC8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xC8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xCC "ECDR179,External Channel Data Register 179" bitfld.long 0xCC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xCC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xCC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xCC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xCC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xCC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xCC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xD0 "ECDR180,External Channel Data Register 180" bitfld.long 0xD0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xD0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xD0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xD0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xD0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xD0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xD0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xD4 "ECDR181,External Channel Data Register 181" bitfld.long 0xD4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xD4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xD4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xD4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xD4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xD4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xD4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xD8 "ECDR182,External Channel Data Register 182" bitfld.long 0xD8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xD8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xD8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xD8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xD8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xD8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xD8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xDC "ECDR183,External Channel Data Register 183" bitfld.long 0xDC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xDC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xDC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xDC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xDC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xDC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xDC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xE0 "ECDR184,External Channel Data Register 184" bitfld.long 0xE0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xE0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xE0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xE0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xE0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xE0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xE0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xE4 "ECDR185,External Channel Data Register 185" bitfld.long 0xE4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xE4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xE4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xE4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xE4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xE4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xE4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xE8 "ECDR186,External Channel Data Register 186" bitfld.long 0xE8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xE8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xE8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xE8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xE8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xE8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xE8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xEC "ECDR187,External Channel Data Register 187" bitfld.long 0xEC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xEC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xEC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xEC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xEC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xEC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xEC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xF0 "ECDR188,External Channel Data Register 188" bitfld.long 0xF0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xF0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xF0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xF0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xF0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xF0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xF0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xF4 "ECDR189,External Channel Data Register 189" bitfld.long 0xF4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xF4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xF4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xF4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xF4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xF4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xF4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xF8 "ECDR190,External Channel Data Register 190" bitfld.long 0xF8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xF8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xF8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xF8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xF8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xF8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xF8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xFC "ECDR191,External Channel Data Register 191" bitfld.long 0xFC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xFC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xFC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xFC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xFC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xFC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xFC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." tree.end tree "SAR_ADC_LP_RUN_0" base ad:0x72230000 group.long 0x0++0x3 line.long 0x0 "MCR,Main Configuration Register" bitfld.long 0x0 31. "OWREN,This bit enables or disables the functionality to overwrite unread converted data in ICDR TCDR ECDR registers." "0: Prevents overwrite of unread converted data new..,1: Enables converted data to be overwritten by a.." bitfld.long 0x0 30. "WLSIDE,Write left/right-aligned" "0: The conversion data in ICDR TCDR ECDR registers..,1: Conversion data is left-aligned (from 15 to (15.." newline bitfld.long 0x0 29. "MODE,One Shot/Scan" "0: One Shot Mode: Configures the normal conversion..,1: Scan Mode: Configures continuous chain.." bitfld.long 0x0 28. "XSTRTEN,This bit enables or disables the external start signal to initial a normal conversion. This can be used to synchronize multiple SARADCs concurrently." "0: External start signal is disabled,1: External start signal high level will start a.." newline bitfld.long 0x0 27. "NSTART,Setting this bit starts the chain or scan conversion. Resetting this bit during scan mode causes the current chain conversion to finish then stops the operation." "0: Cause the current chain conversion to finish and..,1: Starts the chain or scan conversion" bitfld.long 0x0 26. "NTRGEN,NTRGEN" "0: Normal trigger disabled to start a normal..,1: Normal trigger enabled to start a normal.." newline bitfld.long 0x0 24.--25. "NEDGESEL,NEDGESEL" "0: Falling edge of normal trigger is selected,1: Rising edge of normal trigger is selected,2: Both rising and falling edges of normal trigger..,3: Both rising and falling edges of normal trigger.." bitfld.long 0x0 23. "JSTART,Setting this bit will start the configured injected analog channels to be converted by software. Resetting this bit has no effect as the injected chain conversion cannot be interrupted." "0: Writting '0' has not effect,1: Starts the injected chain conversion" newline bitfld.long 0x0 22. "JTRGEN,JTRGEN" "0: Injection trigger disabled for channel injection..,1: Injection trigger enabled for channel injection" bitfld.long 0x0 20.--21. "JEDGESEL,JEDGESEL" "0: Falling edge of injection trigger is selected,1: Rising edge of injection trigger is selected,?,3: Both rising and falling edges of injection.." newline bitfld.long 0x0 19. "JTRGSEQ,JTRGSEQ" "0: Injection trigger sequence mode is disabled,1: Injection trigger sequence mode is enabled" bitfld.long 0x0 15. "WTRIGOUT,This control bit enables the Trigger on every threshold crossover event (crossing of Lower/Upper thresholds) of each WDG monitor to external trigger port (up to 16 ports for up to 16 WDGs)." "0: Trigger outputs disabled,1: Trigger ouputs enabled" newline bitfld.long 0x0 7. "ABORTCHAIN,When this bit is set the ongoing Chain Conversion is aborted. This bit is reset by hardware as soon as a new conversion is requested." "0: Conversion is not affected,1: Aborts the ongoing chain conversion" bitfld.long 0x0 6. "ABORT,When this bit is set the ongoing conversion is aborted and a new conversion is invoked. This bit is reset by hardware as soon as a new conversion is invoked." "0: Conversion is not affected,1: Aborts the ongoing conversion" newline bitfld.long 0x0 4. "FRZ,This bit enables to stop the SARADC conversions at the end of current channel conversion when SoC enters debug mode." "0: Conversions are not stopped,1: When SoC enters debug mode further conversions.." bitfld.long 0x0 2. "FCE,This bit enables the fast comparison mode for upcoming channel conversions." "0: Fast comparision mode disabled,1: Fast comparision mode enabled" newline bitfld.long 0x0 1. "EDCSELF,This bit selects the format for 3-bit output port ipp_decode_extch used as select line for external decode channel 8:1 muxes. The last three bits of external channel number are passed as is (if value 0) or converted to gray code (if value 1) and.." "0: Binary format,1: Gray code format" bitfld.long 0x0 0. "PWDN,When this bit is set the analog module is requested to enter Power Down mode." "0: SARADC is in normal mode,1: SARADC has been requested to power down" rgroup.long 0x4++0x3 line.long 0x0 "MSR,Main Status Register" bitfld.long 0x0 27. "NSTART,This status bit is used to signal that a normal conversion is ongoing." "0: Normal conversion is not taking place,1: Normal conversion is ongoing or the normal.." bitfld.long 0x0 23. "JSTART,This status bit is used to signal that an injected conversion is ongoing." "0: Injected conversion is not taking place,1: Injected conversion is ongoing" newline bitfld.long 0x0 18. "JABORTCHAIN,This status bit is used to signal that an Injected conversion chain has been aborted. This bit is reset when a new conversion starts." "0: Last injected conversion chain has not been..,1: Last injected conversion chain has been aborted" hexmask.long.byte 0x0 8.--15. 1. "CHADDR,Channel under measure address" newline bitfld.long 0x0 0.--2. "ADCSTATUS,The value of this parameter depends on ADC status. While requesting an external channel conversion SARADC digital interface needs to wait for a fixed time determined by DSD bitfield of DSDR before proceeding to actual sampling phase." "0: IDLE,1: Power-down,2: Wait state,?,4: Sample,?,6: Conversion,?" group.long 0x10++0x7 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 3. "JEOC,This bit indicates the end of conversion for an injected channel." "0: End of conversion of injected channel has not..,1: End of conversion of injected channel has.." bitfld.long 0x0 2. "JECH,This bit indicates the end of conversion for an injected chain." "0: End of conversion of injected chain has not..,1: End of conversion of injected chain has occurred.." newline bitfld.long 0x0 1. "NEOC,This bit indicates the end of conversion for a normal channel." "0: End of conversion of normal channel has not..,1: End of conversion of normal channel has occurred.." bitfld.long 0x0 0. "NECH,This bit indicates the end of conversion for an normal chain." "0: End of conversion of normal chain has not..,1: End of conversion of normal chain has occurred.." line.long 0x4 "ICIPR0,Internal Channel Interrupt Pending Register 0" bitfld.long 0x4 23. "EOC_CH23,End of conversion interrupt pending bit for channel 23" "0: End of conversion for CH[23] has not occured,1: End of conversion for CH[23] has occured" bitfld.long 0x4 22. "EOC_CH22,End of conversion interrupt pending bit for channel 22" "0: End of conversion for CH[22] has not occured,1: End of conversion for CH[22] has occured" newline bitfld.long 0x4 21. "EOC_CH21,End of conversion interrupt pending bit for channel 21" "0: End of conversion for CH[21] has not occured,1: End of conversion for CH[21] has occured" bitfld.long 0x4 20. "EOC_CH20,End of conversion interrupt pending bit for channel 20" "0: End of conversion for CH[20] has not occured,1: End of conversion for CH[20] has occured" newline bitfld.long 0x4 19. "EOC_CH19,End of conversion interrupt pending bit for channel 19" "0: End of conversion for CH[19] has not occured,1: End of conversion for CH[19] has occured" bitfld.long 0x4 18. "EOC_CH18,End of conversion interrupt pending bit for channel 18" "0: End of conversion for CH[18] has not occured,1: End of conversion for CH[18] has occured" newline bitfld.long 0x4 17. "EOC_CH17,End of conversion interrupt pending bit for channel 17" "0: End of conversion for CH[17] has not occured,1: End of conversion for CH[17] has occured" bitfld.long 0x4 16. "EOC_CH16,End of conversion interrupt pending bit for channel 16" "0: End of conversion for CH[16] has not occured,1: End of conversion for CH[16] has occured" newline bitfld.long 0x4 15. "EOC_CH15,End of conversion interrupt pending bit for channel 15" "0: End of conversion for CH[15] has not occured,1: End of conversion for CH[15] has occured" bitfld.long 0x4 14. "EOC_CH14,End of conversion interrupt pending bit for channel 14" "0: End of conversion for CH[14] has not occured,1: End of conversion for CH[14] has occured" newline bitfld.long 0x4 13. "EOC_CH13,End of conversion interrupt pending bit for channel 13" "0: End of conversion for CH[13] has not occured,1: End of conversion for CH[13] has occured" bitfld.long 0x4 12. "EOC_CH12,End of conversion interrupt pending bit for channel 12" "0: End of conversion for CH[12] has not occured,1: End of conversion for CH[12] has occured" newline bitfld.long 0x4 11. "EOC_CH11,End of conversion interrupt pending bit for channel 11" "0: End of conversion for CH[11] has not occured,1: End of conversion for CH[11] has occured" bitfld.long 0x4 10. "EOC_CH10,End of conversion interrupt pending bit for channel 10" "0: End of conversion for CH[10] has not occured,1: End of conversion for CH[10] has occured" newline bitfld.long 0x4 9. "EOC_CH9,End of conversion interrupt pending bit for channel 9" "0: End of conversion for CH[9] has not occured,1: End of conversion for CH[9] has occured" bitfld.long 0x4 8. "EOC_CH8,End of conversion interrupt pending bit for channel 8" "0: End of conversion for CH[8] has not occured,1: End of conversion for CH[8] has occured" newline bitfld.long 0x4 7. "EOC_CH7,End of conversion interrupt pending bit for channel 7" "0: End of conversion for CH[7] has not occured,1: End of conversion for CH[7] has occured" bitfld.long 0x4 6. "EOC_CH6,End of conversion interrupt pending bit for channel 6" "0: End of conversion for CH[6] has not occured,1: End of conversion for CH[6] has occured" newline bitfld.long 0x4 5. "EOC_CH5,End of conversion interrupt pending bit for channel 5" "0: End of conversion for CH[5] has not occured,1: End of conversion for CH[5] has occured" bitfld.long 0x4 4. "EOC_CH4,End of conversion interrupt pending bit for channel 4" "0: End of conversion for CH[4] has not occured,1: End of conversion for CH[4] has occured" newline bitfld.long 0x4 3. "EOC_CH3,End of conversion interrupt pending bit for channel 3" "0: End of conversion for CH[3] has not occured,1: End of conversion for CH[3] has occured" bitfld.long 0x4 2. "EOC_CH2,End of conversion interrupt pending bit for channel 2" "0: End of conversion for CH[2] has not occured,1: End of conversion for CH[2] has occured" newline bitfld.long 0x4 1. "EOC_CH1,End of conversion interrupt pending bit for channel 1" "0: End of conversion for CH[1] has not occured,1: End of conversion for CH[1] has occured" bitfld.long 0x4 0. "EOC_CH0,End of conversion interrupt pending bit for channel 0" "0: End of conversion for CH[0] has not occured,1: End of conversion for CH[0] has occured" group.long 0x20++0x7 line.long 0x0 "IMR,Interrupt Mask Register" bitfld.long 0x0 3. "MSKJEOC,Mask bit for JEOC" "0: JEOC interrupt is disabled,1: JEOC interrupt is enabled" bitfld.long 0x0 2. "MSKJECH,Mask bit for JECH" "0: JECH interrupt is disabled,1: JECH interrupt is enabled" newline bitfld.long 0x0 1. "MSKNEOC,Mask bit for NEOC" "0: NEOC interrupt is disabled,1: NEOC interrupt is enabled" bitfld.long 0x0 0. "MSKNECH,Mask bit for NECH" "0: NECH interrupt is disabled,1: NECH interrupt is enabled" line.long 0x4 "ICIMR0,Internal Channel Interrupt Mask Register 0" bitfld.long 0x4 23. "IM_CH23,Interrupt mask bit for channel 23" "0: Interupt for CH[23] is disabled,1: Interupt for CH[23] is enabled" bitfld.long 0x4 22. "IM_CH22,Interrupt mask bit for channel 22" "0: Interupt for CH[22] is disabled,1: Interupt for CH[22] is enabled" newline bitfld.long 0x4 21. "IM_CH21,Interrupt mask bit for channel 21" "0: Interupt for CH[21] is disabled,1: Interupt for CH[21] is enabled" bitfld.long 0x4 20. "IM_CH20,Interrupt mask bit for channel 20" "0: Interupt for CH[20] is disabled,1: Interupt for CH[20] is enabled" newline bitfld.long 0x4 19. "IM_CH19,Interrupt mask bit for channel 19" "0: Interupt for CH[19] is disabled,1: Interupt for CH[19] is enabled" bitfld.long 0x4 18. "IM_CH18,Interrupt mask bit for channel 18" "0: Interupt for CH[18] is disabled,1: Interupt for CH[18] is enabled" newline bitfld.long 0x4 17. "IM_CH17,Interrupt mask bit for channel 17" "0: Interupt for CH[17] is disabled,1: Interupt for CH[17] is enabled" bitfld.long 0x4 16. "IM_CH16,Interrupt mask bit for channel 16" "0: Interupt for CH[16] is disabled,1: Interupt for CH[16] is enabled" newline bitfld.long 0x4 15. "IM_CH15,Interrupt mask bit for channel 15" "0: Interupt for CH[15] is disabled,1: Interupt for CH[15] is enabled" bitfld.long 0x4 14. "IM_CH14,Interrupt mask bit for channel 14" "0: Interupt for CH[14] is disabled,1: Interupt for CH[14] is enabled" newline bitfld.long 0x4 13. "IM_CH13,Interrupt mask bit for channel 13" "0: Interupt for CH[13] is disabled,1: Interupt for CH[13] is enabled" bitfld.long 0x4 12. "IM_CH12,Interrupt mask bit for channel 12" "0: Interupt for CH[12] is disabled,1: Interupt for CH[12] is enabled" newline bitfld.long 0x4 11. "IM_CH11,Interrupt mask bit for channel 11" "0: Interupt for CH[11] is disabled,1: Interupt for CH[11] is enabled" bitfld.long 0x4 10. "IM_CH10,Interrupt mask bit for channel 10" "0: Interupt for CH[10] is disabled,1: Interupt for CH[10] is enabled" newline bitfld.long 0x4 9. "IM_CH9,Interrupt mask bit for channel 9" "0: Interupt for CH[9] is disabled,1: Interupt for CH[9] is enabled" bitfld.long 0x4 8. "IM_CH8,Interrupt mask bit for channel 8" "0: Interupt for CH[8] is disabled,1: Interupt for CH[8] is enabled" newline bitfld.long 0x4 7. "IM_CH7,Interrupt mask bit for channel 7" "0: Interupt for CH[7] is disabled,1: Interupt for CH[7] is enabled" bitfld.long 0x4 6. "IM_CH6,Interrupt mask bit for channel 6" "0: Interupt for CH[6] is disabled,1: Interupt for CH[6] is enabled" newline bitfld.long 0x4 5. "IM_CH5,Interrupt mask bit for channel 5" "0: Interupt for CH[5] is disabled,1: Interupt for CH[5] is enabled" bitfld.long 0x4 4. "IM_CH4,Interrupt mask bit for channel 4" "0: Interupt for CH[4] is disabled,1: Interupt for CH[4] is enabled" newline bitfld.long 0x4 3. "IM_CH3,Interrupt mask bit for channel 3" "0: Interupt for CH[3] is disabled,1: Interupt for CH[3] is enabled" bitfld.long 0x4 2. "IM_CH2,Interrupt mask bit for channel 2" "0: Interupt for CH[2] is disabled,1: Interupt for CH[2] is enabled" newline bitfld.long 0x4 1. "IM_CH1,Interrupt mask bit for channel 1" "0: Interupt for CH[1] is disabled,1: Interupt for CH[1] is enabled" bitfld.long 0x4 0. "IM_CH0,Interrupt mask bit for channel 0" "0: Interupt for CH[0] is disabled,1: Interupt for CH[0] is enabled" group.long 0x30++0xB line.long 0x0 "WTISR,Watchdog Threshold Interrupt Status Register" bitfld.long 0x0 3. "WDG1H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 1." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 2. "WDG1L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 1." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." newline bitfld.long 0x0 1. "WDG0H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold as reported by WDG monitor 0." "0: Converted data is not higher than the programmed..,1: Converted data is higher than the programmed.." bitfld.long 0x0 0. "WDG0L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold as reported by WDG monitor 0." "0: Converted data is not lower than the programmed..,1: Converted data is lower than the programmed.." line.long 0x4 "WTIMR,Watchdog Threshold Interrupt Mask Register" bitfld.long 0x4 3. "MSKWDG1H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG1H is disabled.,1: Inetrupt for WDG1H is enabled." bitfld.long 0x4 2. "MSKWDG1L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG1L is disabled.,1: Inetrupt for WDG1L is enabled." newline bitfld.long 0x4 1. "MSKWDG0H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold." "0: Interupt for WDG0H is disabled.,1: Inetrupt for WDG0H is enabled." bitfld.long 0x4 0. "MSKWDG0L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold." "0: Interupt for WDG0L is disabled.,1: Inetrupt for WDG0L is enabled." line.long 0x8 "WLTCR,Watchdog Level Trigger Configuration Register" bitfld.long 0x8 1. "LTMW1,LTMW1" "0: Level Trigger Mode,1: Hysteresis Mode" bitfld.long 0x8 0. "LTMW0,LTMW0" "0: Level Trigger Mode,1: Hysteresis Mode" group.long 0x60++0x7 line.long 0x0 "WTHRHLR0,Watchdog Threshold Register 0" hexmask.long.word 0x0 16.--25. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x0 0.--9. 1. "THRL,Low threshold value for channel x" line.long 0x4 "WTHRHLR1,Watchdog Threshold Register 1" hexmask.long.word 0x4 16.--25. 1. "THRH,High threshold value for channel x" hexmask.long.word 0x4 0.--9. 1. "THRL,Low threshold value for channel x" group.long 0x94++0x13 line.long 0x0 "CTR0,Conversion Timing Register 0" bitfld.long 0x0 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x0 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x4 "CTR1,Conversion Timing Register 1" bitfld.long 0x4 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x4 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x4 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x8 "CTR2,Conversion Timing Register 2" bitfld.long 0x8 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0x8 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0x8 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0xC "CTR3,Conversion Timing Register 3" bitfld.long 0xC 31. "CRES,This bit selects the conversion resolution for the conversion." "0: 12-bit resolution in case of 12-bit SARADC.,1: 10-bit resolution in case of 12-bit SARADC." hexmask.long.byte 0xC 8.--11. 1. "PRECHG,This bitfield defines the precharging phase duration to be applied when this phase is enabled by PCE bit of channel data register. This duration is calculated as (PRECHG X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum.." newline hexmask.long.byte 0xC 0.--7. 1. "INPSAMP,This bitfield defines the sampling phase duration to be applied. This duration is calculated as (INPSAMP X 1/Frequency of SARADC clock). Refer to device datasheet for the minimum duration required for sampling phase." line.long 0x10 "ICNCMR0,Internal Channel Normal Conversion Mask Register 0" bitfld.long 0x10 23. "NCE_CH23,NCE_CH23" "0: Normal conversion is disabled for CH[23].,1: Normal conversion is enabled for CH[23]." bitfld.long 0x10 22. "NCE_CH22,NCE_CH22" "0: Normal conversion is disabled for CH[22].,1: Normal conversion is enabled for CH[22]." newline bitfld.long 0x10 21. "NCE_CH21,NCE_CH21" "0: Normal conversion is disabled for CH[21].,1: Normal conversion is enabled for CH[21]." bitfld.long 0x10 20. "NCE_CH20,NCE_CH20" "0: Normal conversion is disabled for CH[20].,1: Normal conversion is enabled for CH[20]." newline bitfld.long 0x10 19. "NCE_CH19,NCE_CH19" "0: Normal conversion is disabled for CH[19].,1: Normal conversion is enabled for CH[19]." bitfld.long 0x10 18. "NCE_CH18,NCE_CH18" "0: Normal conversion is disabled for CH[18].,1: Normal conversion is enabled for CH[18]." newline bitfld.long 0x10 17. "NCE_CH17,NCE_CH17" "0: Normal conversion is disabled for CH[17].,1: Normal conversion is enabled for CH[17]." bitfld.long 0x10 16. "NCE_CH16,NCE_CH16" "0: Normal conversion is disabled for CH[16].,1: Normal conversion is enabled for CH[16]." newline bitfld.long 0x10 15. "NCE_CH15,NCE_CH15" "0: Normal conversion is disabled for CH[15].,1: Normal conversion is enabled for CH[15]." bitfld.long 0x10 14. "NCE_CH14,NCE_CH14" "0: Normal conversion is disabled for CH[14].,1: Normal conversion is enabled for CH[14]." newline bitfld.long 0x10 13. "NCE_CH13,NCE_CH13" "0: Normal conversion is disabled for CH[13].,1: Normal conversion is enabled for CH[13]." bitfld.long 0x10 12. "NCE_CH12,NCE_CH12" "0: Normal conversion is disabled for CH[12].,1: Normal conversion is enabled for CH[12]." newline bitfld.long 0x10 11. "NCE_CH11,NCE_CH11" "0: Normal conversion is disabled for CH[11].,1: Normal conversion is enabled for CH[11]." bitfld.long 0x10 10. "NCE_CH10,NCE_CH10" "0: Normal conversion is disabled for CH[10].,1: Normal conversion is enabled for CH[10]." newline bitfld.long 0x10 9. "NCE_CH9,NCE_CH9" "0: Normal conversion is disabled for CH[9].,1: Normal conversion is enabled for CH[9]." bitfld.long 0x10 8. "NCE_CH8,NCE_CH8" "0: Normal conversion is disabled for CH[8].,1: Normal conversion is enabled for CH[8]." newline bitfld.long 0x10 7. "NCE_CH7,NCE_CH7" "0: Normal conversion is disabled for CH[7].,1: Normal conversion is enabled for CH[7]." bitfld.long 0x10 6. "NCE_CH6,NCE_CH6" "0: Normal conversion is disabled for CH[6].,1: Normal conversion is enabled for CH[6]." newline bitfld.long 0x10 5. "NCE_CH5,NCE_CH5" "0: Normal conversion is disabled for CH[5].,1: Normal conversion is enabled for CH[5]." bitfld.long 0x10 4. "NCE_CH4,NCE_CH4" "0: Normal conversion is disabled for CH[4].,1: Normal conversion is enabled for CH[4]." newline bitfld.long 0x10 3. "NCE_CH3,NCE_CH3" "0: Normal conversion is disabled for CH[3].,1: Normal conversion is enabled for CH[3]." bitfld.long 0x10 2. "NCE_CH2,NCE_CH2" "0: Normal conversion is disabled for CH[2].,1: Normal conversion is enabled for CH[2]." newline bitfld.long 0x10 1. "NCE_CH1,NCE_CH1" "0: Normal conversion is disabled for CH[1].,1: Normal conversion is enabled for CH[1]." bitfld.long 0x10 0. "NCE_CH0,NCE_CH0" "0: Normal conversion is disabled for CH[0].,1: Normal conversion is enabled for CH[0]." group.long 0xB4++0x3 line.long 0x0 "ICJCMR0,Internal Channel Injected Conversion Mask Register 0" bitfld.long 0x0 23. "JCE_CH23,JCE_CH23" "0: Injected conversion is disabled for CH[23].,1: Injected conversion is enabled for CH[23]." bitfld.long 0x0 22. "JCE_CH22,JCE_CH22" "0: Injected conversion is disabled for CH[22].,1: Injected conversion is enabled for CH[22]." newline bitfld.long 0x0 21. "JCE_CH21,JCE_CH21" "0: Injected conversion is disabled for CH[21].,1: Injected conversion is enabled for CH[21]." bitfld.long 0x0 20. "JCE_CH20,JCE_CH20" "0: Injected conversion is disabled for CH[20].,1: Injected conversion is enabled for CH[20]." newline bitfld.long 0x0 19. "JCE_CH19,JCE_CH19" "0: Injected conversion is disabled for CH[19].,1: Injected conversion is enabled for CH[19]." bitfld.long 0x0 18. "JCE_CH18,JCE_CH18" "0: Injected conversion is disabled for CH[18].,1: Injected conversion is enabled for CH[18]." newline bitfld.long 0x0 17. "JCE_CH17,JCE_CH17" "0: Injected conversion is disabled for CH[17].,1: Injected conversion is enabled for CH[17]." bitfld.long 0x0 16. "JCE_CH16,JCE_CH16" "0: Injected conversion is disabled for CH[16].,1: Injected conversion is enabled for CH[16]." newline bitfld.long 0x0 15. "JCE_CH15,JCE_CH15" "0: Injected conversion is disabled for CH[15].,1: Injected conversion is enabled for CH[15]." bitfld.long 0x0 14. "JCE_CH14,JCE_CH14" "0: Injected conversion is disabled for CH[14].,1: Injected conversion is enabled for CH[14]." newline bitfld.long 0x0 13. "JCE_CH13,JCE_CH13" "0: Injected conversion is disabled for CH[13].,1: Injected conversion is enabled for CH[13]." bitfld.long 0x0 12. "JCE_CH12,JCE_CH12" "0: Injected conversion is disabled for CH[12].,1: Injected conversion is enabled for CH[12]." newline bitfld.long 0x0 11. "JCE_CH11,JCE_CH11" "0: Injected conversion is disabled for CH[11].,1: Injected conversion is enabled for CH[11]." bitfld.long 0x0 10. "JCE_CH10,JCE_CH10" "0: Injected conversion is disabled for CH[10].,1: Injected conversion is enabled for CH[10]." newline bitfld.long 0x0 9. "JCE_CH9,JCE_CH9" "0: Injected conversion is disabled for CH[9].,1: Injected conversion is enabled for CH[9]." bitfld.long 0x0 8. "JCE_CH8,JCE_CH8" "0: Injected conversion is disabled for CH[8].,1: Injected conversion is enabled for CH[8]." newline bitfld.long 0x0 7. "JCE_CH7,JCE_CH7" "0: Injected conversion is disabled for CH[7].,1: Injected conversion is enabled for CH[7]." bitfld.long 0x0 6. "JCE_CH6,JCE_CH6" "0: Injected conversion is disabled for CH[6].,1: Injected conversion is enabled for CH[6]." newline bitfld.long 0x0 5. "JCE_CH5,JCE_CH5" "0: Injected conversion is disabled for CH[5].,1: Injected conversion is enabled for CH[5]." bitfld.long 0x0 4. "JCE_CH4,JCE_CH4" "0: Injected conversion is disabled for CH[4].,1: Injected conversion is enabled for CH[4]." newline bitfld.long 0x0 3. "JCE_CH3,JCE_CH3" "0: Injected conversion is disabled for CH[3].,1: Injected conversion is enabled for CH[3]." bitfld.long 0x0 2. "JCE_CH2,JCE_CH2" "0: Injected conversion is disabled for CH[2].,1: Injected conversion is enabled for CH[2]." newline bitfld.long 0x0 1. "JCE_CH1,JCE_CH1" "0: Injected conversion is disabled for CH[1].,1: Injected conversion is enabled for CH[1]." bitfld.long 0x0 0. "JCE_CH0,JCE_CH0" "0: Injected conversion is disabled for CH[0].,1: Injected conversion is enabled for CH[0]." group.long 0xC8++0x3 line.long 0x0 "PDEDR,Power Down Exit Delay Register" hexmask.long.byte 0x0 0.--7. 1. "PDED,Defines the delay between the power-down bit reset and the starting of conversion." group.long 0x100++0x5F line.long 0x0 "ICDR0,Internal Channel Data Register 0" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x0 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4 "ICDR1,Internal Channel Data Register 1" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x8 "ICDR2,Internal Channel Data Register 2" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x8 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0xC "ICDR3,Internal Channel Data Register 3" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0xC 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x10 "ICDR4,Internal Channel Data Register 4" bitfld.long 0x10 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x10 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x10 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x10 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x10 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x10 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x10 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x14 "ICDR5,Internal Channel Data Register 5" bitfld.long 0x14 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x14 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x14 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x14 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x14 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x14 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x14 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x18 "ICDR6,Internal Channel Data Register 6" bitfld.long 0x18 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x18 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x18 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x18 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x18 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x18 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x18 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x1C "ICDR7,Internal Channel Data Register 7" bitfld.long 0x1C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x1C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x1C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x1C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x1C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x1C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x1C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x20 "ICDR8,Internal Channel Data Register 8" bitfld.long 0x20 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x20 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x20 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x20 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x20 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x20 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x20 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x24 "ICDR9,Internal Channel Data Register 9" bitfld.long 0x24 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x24 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x24 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x24 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x24 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x24 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x24 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x28 "ICDR10,Internal Channel Data Register 10" bitfld.long 0x28 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x28 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x28 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x28 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x28 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x28 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x28 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x2C "ICDR11,Internal Channel Data Register 11" bitfld.long 0x2C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x2C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x2C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x2C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x2C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x2C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x2C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x30 "ICDR12,Internal Channel Data Register 12" bitfld.long 0x30 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x30 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x30 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x30 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x30 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x30 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x30 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x34 "ICDR13,Internal Channel Data Register 13" bitfld.long 0x34 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x34 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x34 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x34 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x34 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x34 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x34 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x38 "ICDR14,Internal Channel Data Register 14" bitfld.long 0x38 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x38 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x38 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x38 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x38 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x38 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x38 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x3C "ICDR15,Internal Channel Data Register 15" bitfld.long 0x3C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x3C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x3C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x3C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x3C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x3C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x3C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x40 "ICDR16,Internal Channel Data Register 16" bitfld.long 0x40 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x40 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x40 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x40 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x40 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x40 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x40 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x44 "ICDR17,Internal Channel Data Register 17" bitfld.long 0x44 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x44 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x44 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x44 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x44 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x44 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x44 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x48 "ICDR18,Internal Channel Data Register 18" bitfld.long 0x48 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x48 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x48 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x48 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x48 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x48 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x48 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x4C "ICDR19,Internal Channel Data Register 19" bitfld.long 0x4C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x4C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x4C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x4C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x4C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x50 "ICDR20,Internal Channel Data Register 20" bitfld.long 0x50 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x50 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x50 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x50 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x50 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x50 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x50 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x54 "ICDR21,Internal Channel Data Register 21" bitfld.long 0x54 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x54 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x54 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x54 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x54 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x54 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x54 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x58 "ICDR22,Internal Channel Data Register 22" bitfld.long 0x58 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x58 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x58 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x58 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x58 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x58 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x58 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" line.long 0x5C "ICDR23,Internal Channel Data Register 23" bitfld.long 0x5C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled.,1: Precharge pahe is enabled." bitfld.long 0x5C 24.--25. "CTSEL,This bitfield selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected.,1: CTR1 is selected.,2: CTR2 is selected.,3: CTR3 is selected." newline bitfld.long 0x5C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x5C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x5C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:" "0: Converted data has not been overwritten.,1: Previous converted data has been overwritten.." bitfld.long 0x5C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode.,1: Data is a result of Injected conversion mode.,2: Data is a result of CTU conversion mode.,?" newline hexmask.long.word 0x5C 0.--15. 1. "CDATA,Note: The data organization inside the CDATA field is dependent on:" group.long 0x2B0++0xB line.long 0x0 "ICWSELR0,Internal Channel Watchdog Select Register 0" bitfld.long 0x0 28. "WSEL_CH7,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x0 24. "WSEL_CH6,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x0 20. "WSEL_CH5,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x0 16. "WSEL_CH4,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x0 12. "WSEL_CH3,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x0 8. "WSEL_CH2,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x0 4. "WSEL_CH1,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x0 0. "WSEL_CH0,0000 THRHLR0 register is selected" "0,1" line.long 0x4 "ICWSELR1,Internal Channel Watchdog Select Register 1" bitfld.long 0x4 28. "WSEL_CH15,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x4 24. "WSEL_CH14,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x4 20. "WSEL_CH13,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x4 16. "WSEL_CH12,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x4 12. "WSEL_CH11,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x4 8. "WSEL_CH10,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x4 4. "WSEL_CH9,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x4 0. "WSEL_CH8,0000 THRHLR0 register is selected" "0,1" line.long 0x8 "ICWSELR2,Internal Channel Watchdog Select Register 2" bitfld.long 0x8 28. "WSEL_CH23,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x8 24. "WSEL_CH22,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x8 20. "WSEL_CH21,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x8 16. "WSEL_CH20,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x8 12. "WSEL_CH19,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x8 8. "WSEL_CH18,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x8 4. "WSEL_CH17,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x8 0. "WSEL_CH16,0000 THRHLR0 register is selected" "0,1" group.long 0x2E0++0x3 line.long 0x0 "ICWENR0,Internal Channel Watchdog Enable Register 0" bitfld.long 0x0 23. "WEN_CH23,WEN_CH23" "0: Watchdog feature is disabled for CH[23],1: Watchdog feature is enabled fir CH[23]" bitfld.long 0x0 22. "WEN_CH22,WEN_CH22" "0: Watchdog feature is disabled for CH[22],1: Watchdog feature is enabled fir CH[22]" newline bitfld.long 0x0 21. "WEN_CH21,WEN_CH21" "0: Watchdog feature is disabled for CH[21],1: Watchdog feature is enabled fir CH[21]" bitfld.long 0x0 20. "WEN_CH20,WEN_CH20" "0: Watchdog feature is disabled for CH[20],1: Watchdog feature is enabled fir CH[20]" newline bitfld.long 0x0 19. "WEN_CH19,WEN_CH19" "0: Watchdog feature is disabled for CH[19],1: Watchdog feature is enabled fir CH[19]" bitfld.long 0x0 18. "WEN_CH18,WEN_CH18" "0: Watchdog feature is disabled for CH[18],1: Watchdog feature is enabled fir CH[18]" newline bitfld.long 0x0 17. "WEN_CH17,WEN_CH17" "0: Watchdog feature is disabled for CH[17],1: Watchdog feature is enabled fir CH[17]" bitfld.long 0x0 16. "WEN_CH16,WEN_CH16" "0: Watchdog feature is disabled for CH[16],1: Watchdog feature is enabled fir CH[16]" newline bitfld.long 0x0 15. "WEN_CH15,WEN_CH15" "0: Watchdog feature is disabled for CH[15],1: Watchdog feature is enabled fir CH[15]" bitfld.long 0x0 14. "WEN_CH14,WEN_CH14" "0: Watchdog feature is disabled for CH[14],1: Watchdog feature is enabled fir CH[14]" newline bitfld.long 0x0 13. "WEN_CH13,WEN_CH13" "0: Watchdog feature is disabled for CH[13],1: Watchdog feature is enabled fir CH[13]" bitfld.long 0x0 12. "WEN_CH12,WEN_CH12" "0: Watchdog feature is disabled for CH[12],1: Watchdog feature is enabled fir CH[12]" newline bitfld.long 0x0 11. "WEN_CH11,WEN_CH11" "0: Watchdog feature is disabled for CH[11],1: Watchdog feature is enabled fir CH[11]" bitfld.long 0x0 10. "WEN_CH10,WEN_CH10" "0: Watchdog feature is disabled for CH[10],1: Watchdog feature is enabled fir CH[10]" newline bitfld.long 0x0 9. "WEN_CH9,WEN_CH9" "0: Watchdog feature is disabled for CH[9],1: Watchdog feature is enabled fir CH[9]" bitfld.long 0x0 8. "WEN_CH8,WEN_CH8" "0: Watchdog feature is disabled for CH[8],1: Watchdog feature is enabled fir CH[8]" newline bitfld.long 0x0 7. "WEN_CH7,WEN_CH7" "0: Watchdog feature is disabled for CH[7],1: Watchdog feature is enabled fir CH[7]" bitfld.long 0x0 6. "WEN_CH6,WEN_CH6" "0: Watchdog feature is disabled for CH[6],1: Watchdog feature is enabled fir CH[6]" newline bitfld.long 0x0 5. "WEN_CH5,WEN_CH5" "0: Watchdog feature is disabled for CH[5],1: Watchdog feature is enabled fir CH[5]" bitfld.long 0x0 4. "WEN_CH4,WEN_CH4" "0: Watchdog feature is disabled for CH[4],1: Watchdog feature is enabled fir CH[4]" newline bitfld.long 0x0 3. "WEN_CH3,WEN_CH3" "0: Watchdog feature is disabled for CH[3],1: Watchdog feature is enabled fir CH[3]" bitfld.long 0x0 2. "WEN_CH2,WEN_CH2" "0: Watchdog feature is disabled for CH[2],1: Watchdog feature is enabled fir CH[2]" newline bitfld.long 0x0 1. "WEN_CH1,WEN_CH1" "0: Watchdog feature is disabled for CH[1],1: Watchdog feature is enabled fir CH[1]" bitfld.long 0x0 0. "WEN_CH0,WEN_CH0" "0: Watchdog feature is disabled for CH[0],1: Watchdog feature is enabled fir CH[0]" group.long 0x2F0++0x3 line.long 0x0 "ICAWORR0,Internal Channel Analog Watchdog Out of Range Register 0" bitfld.long 0x0 23. "AWOR_CH23,Analog watchdog out of range status for channel 23 provided corresponding WEN_CH23 bit is set." "0: CH[23] converted data is not out of range..,1: CH[23] converted data is out of range determined.." bitfld.long 0x0 22. "AWOR_CH22,Analog watchdog out of range status for channel 22 provided corresponding WEN_CH22 bit is set." "0: CH[22] converted data is not out of range..,1: CH[22] converted data is out of range determined.." newline bitfld.long 0x0 21. "AWOR_CH21,Analog watchdog out of range status for channel 21 provided corresponding WEN_CH21 bit is set." "0: CH[21] converted data is not out of range..,1: CH[21] converted data is out of range determined.." bitfld.long 0x0 20. "AWOR_CH20,Analog watchdog out of range status for channel 20 provided corresponding WEN_CH20 bit is set." "0: CH[20] converted data is not out of range..,1: CH[20] converted data is out of range determined.." newline bitfld.long 0x0 19. "AWOR_CH19,Analog watchdog out of range status for channel 19 provided corresponding WEN_CH19 bit is set." "0: CH[19] converted data is not out of range..,1: CH[19] converted data is out of range determined.." bitfld.long 0x0 18. "AWOR_CH18,Analog watchdog out of range status for channel 18 provided corresponding WEN_CH18 bit is set." "0: CH[18] converted data is not out of range..,1: CH[18] converted data is out of range determined.." newline bitfld.long 0x0 17. "AWOR_CH17,Analog watchdog out of range status for channel 17 provided corresponding WEN_CH17 bit is set." "0: CH[17] converted data is not out of range..,1: CH[17] converted data is out of range determined.." bitfld.long 0x0 16. "AWOR_CH16,Analog watchdog out of range status for channel 16 provided corresponding WEN_CH16 bit is set." "0: CH[16] converted data is not out of range..,1: CH[16] converted data is out of range determined.." newline bitfld.long 0x0 15. "AWOR_CH15,Analog watchdog out of range status for channel 15 provided corresponding WEN_CH15 bit is set." "0: CH[15] converted data is not out of range..,1: CH[15] converted data is out of range determined.." bitfld.long 0x0 14. "AWOR_CH14,Analog watchdog out of range status for channel 14 provided corresponding WEN_CH14 bit is set." "0: CH[14] converted data is not out of range..,1: CH[14] converted data is out of range determined.." newline bitfld.long 0x0 13. "AWOR_CH13,Analog watchdog out of range status for channel 13 provided corresponding WEN_CH13 bit is set." "0: CH[13] converted data is not out of range..,1: CH[13] converted data is out of range determined.." bitfld.long 0x0 12. "AWOR_CH12,Analog watchdog out of range status for channel 12 provided corresponding WEN_CH12 bit is set." "0: CH[12] converted data is not out of range..,1: CH[12] converted data is out of range determined.." newline bitfld.long 0x0 11. "AWOR_CH11,Analog watchdog out of range status for channel 11 provided corresponding WEN_CH11 bit is set." "0: CH[11] converted data is not out of range..,1: CH[11] converted data is out of range determined.." bitfld.long 0x0 10. "AWOR_CH10,Analog watchdog out of range status for channel 10 provided corresponding WEN_CH10 bit is set." "0: CH[10] converted data is not out of range..,1: CH[10] converted data is out of range determined.." newline bitfld.long 0x0 9. "AWOR_CH9,Analog watchdog out of range status for channel 9 provided corresponding WEN_CH9 bit is set." "0: CH[9] converted data is not out of range..,1: CH[9] converted data is out of range determined.." bitfld.long 0x0 8. "AWOR_CH8,Analog watchdog out of range status for channel 8 provided corresponding WEN_CH8 bit is set." "0: CH[8] converted data is not out of range..,1: CH[8] converted data is out of range determined.." newline bitfld.long 0x0 7. "AWOR_CH7,Analog watchdog out of range status for channel 7 provided corresponding WEN_CH7 bit is set." "0: CH[7] converted data is not out of range..,1: CH[7] converted data is out of range determined.." bitfld.long 0x0 6. "AWOR_CH6,Analog watchdog out of range status for channel 6 provided corresponding WEN_CH6 bit is set." "0: CH[6] converted data is not out of range..,1: CH[6] converted data is out of range determined.." newline bitfld.long 0x0 5. "AWOR_CH5,Analog watchdog out of range status for channel 5 provided corresponding WEN_CH5 bit is set." "0: CH[5] converted data is not out of range..,1: CH[5] converted data is out of range determined.." bitfld.long 0x0 4. "AWOR_CH4,Analog watchdog out of range status for channel 4 provided corresponding WEN_CH4 bit is set." "0: CH[4] converted data is not out of range..,1: CH[4] converted data is out of range determined.." newline bitfld.long 0x0 3. "AWOR_CH3,Analog watchdog out of range status for channel 3 provided corresponding WEN_CH3 bit is set." "0: CH[3] converted data is not out of range..,1: CH[3] converted data is out of range determined.." bitfld.long 0x0 2. "AWOR_CH2,Analog watchdog out of range status for channel 2 provided corresponding WEN_CH2 bit is set." "0: CH[2] converted data is not out of range..,1: CH[2] converted data is out of range determined.." newline bitfld.long 0x0 1. "AWOR_CH1,Analog watchdog out of range status for channel 1 provided corresponding WEN_CH1 bit is set." "0: CH[1] converted data is not out of range..,1: CH[1] converted data is out of range determined.." bitfld.long 0x0 0. "AWOR_CH0,Analog watchdog out of range status for channel 0 provided corresponding WEN_CH0 bit is set." "0: CH[0] converted data is not out of range..,1: CH[0] converted data is out of range determined.." group.long 0x500++0x3 line.long 0x0 "ECDSDR,External Channel Decode Signals Delay Register" hexmask.long.word 0x0 0.--11. 1. "DSD,This bit field defines the delay between the external decode signals and the start of the sampling phase. It is used to take into account of the settling time required for the external mux. The decode signal delay is calculated as (DSD X 1/Frequency.." group.long 0x510++0x7 line.long 0x0 "ECIPR0,External Channel Interrupt Pending Register 0" bitfld.long 0x0 31. "EOC_CH159,EOC_CH159" "0: End of conversion for CH[159] has not occurred.,1: End of conversion for CH[159] has occurred." bitfld.long 0x0 30. "EOC_CH158,EOC_CH158" "0: End of conversion for CH[158] has not occurred.,1: End of conversion for CH[158] has occurred." newline bitfld.long 0x0 29. "EOC_CH157,EOC_CH157" "0: End of conversion for CH[157] has not occurred.,1: End of conversion for CH[157] has occurred." bitfld.long 0x0 28. "EOC_CH156,EOC_CH156" "0: End of conversion for CH[156] has not occurred.,1: End of conversion for CH[156] has occurred." newline bitfld.long 0x0 27. "EOC_CH155,EOC_CH155" "0: End of conversion for CH[155] has not occurred.,1: End of conversion for CH[155] has occurred." bitfld.long 0x0 26. "EOC_CH154,EOC_CH154" "0: End of conversion for CH[154] has not occurred.,1: End of conversion for CH[154] has occurred." newline bitfld.long 0x0 25. "EOC_CH153,EOC_CH153" "0: End of conversion for CH[153] has not occurred.,1: End of conversion for CH[153] has occurred." bitfld.long 0x0 24. "EOC_CH152,EOC_CH152" "0: End of conversion for CH[152] has not occurred.,1: End of conversion for CH[152] has occurred." newline bitfld.long 0x0 23. "EOC_CH151,EOC_CH151" "0: End of conversion for CH[151] has not occurred.,1: End of conversion for CH[151] has occurred." bitfld.long 0x0 22. "EOC_CH150,EOC_CH150" "0: End of conversion for CH[150] has not occurred.,1: End of conversion for CH[150] has occurred." newline bitfld.long 0x0 21. "EOC_CH149,EOC_CH149" "0: End of conversion for CH[149] has not occurred.,1: End of conversion for CH[149] has occurred." bitfld.long 0x0 20. "EOC_CH148,EOC_CH148" "0: End of conversion for CH[148] has not occurred.,1: End of conversion for CH[148] has occurred." newline bitfld.long 0x0 19. "EOC_CH147,EOC_CH147" "0: End of conversion for CH[147] has not occurred.,1: End of conversion for CH[147] has occurred." bitfld.long 0x0 18. "EOC_CH146,EOC_CH146" "0: End of conversion for CH[146] has not occurred.,1: End of conversion for CH[146] has occurred." newline bitfld.long 0x0 17. "EOC_CH145,EOC_CH145" "0: End of conversion for CH[145] has not occurred.,1: End of conversion for CH[145] has occurred." bitfld.long 0x0 16. "EOC_CH144,EOC_CH144" "0: End of conversion for CH[144] has not occurred.,1: End of conversion for CH[144] has occurred." newline bitfld.long 0x0 15. "EOC_CH143,EOC_CH143" "0: End of conversion for CH[143] has not occurred.,1: End of conversion for CH[143] has occurred." bitfld.long 0x0 14. "EOC_CH142,EOC_CH142" "0: End of conversion for CH[142] has not occurred.,1: End of conversion for CH[142] has occurred." newline bitfld.long 0x0 13. "EOC_CH141,EOC_CH141" "0: End of conversion for CH[141] has not occurred.,1: End of conversion for CH[141] has occurred." bitfld.long 0x0 12. "EOC_CH140,EOC_CH140" "0: End of conversion for CH[140] has not occurred.,1: End of conversion for CH[140] has occurred." newline bitfld.long 0x0 11. "EOC_CH139,EOC_CH139" "0: End of conversion for CH[139] has not occurred.,1: End of conversion for CH[139] has occurred." bitfld.long 0x0 10. "EOC_CH138,EOC_CH138" "0: End of conversion for CH[138] has not occurred.,1: End of conversion for CH[138] has occurred." newline bitfld.long 0x0 9. "EOC_CH137,EOC_CH137" "0: End of conversion for CH[137] has not occurred.,1: End of conversion for CH[137] has occurred." bitfld.long 0x0 8. "EOC_CH136,EOC_CH136" "0: End of conversion for CH[136] has not occurred.,1: End of conversion for CH[136] has occurred." newline bitfld.long 0x0 7. "EOC_CH135,EOC_CH135" "0: End of conversion for CH[135] has not occurred.,1: End of conversion for CH[135] has occurred." bitfld.long 0x0 6. "EOC_CH134,EOC_CH134" "0: End of conversion for CH[134] has not occurred.,1: End of conversion for CH[134] has occurred." newline bitfld.long 0x0 5. "EOC_CH133,EOC_CH133" "0: End of conversion for CH[133] has not occurred.,1: End of conversion for CH[133] has occurred." bitfld.long 0x0 4. "EOC_CH132,EOC_CH132" "0: End of conversion for CH[132] has not occurred.,1: End of conversion for CH[132] has occurred." newline bitfld.long 0x0 3. "EOC_CH131,EOC_CH131" "0: End of conversion for CH[131] has not occurred.,1: End of conversion for CH[131] has occurred." bitfld.long 0x0 2. "EOC_CH130,EOC_CH130" "0: End of conversion for CH[130] has not occurred.,1: End of conversion for CH[130] has occurred." newline bitfld.long 0x0 1. "EOC_CH129,EOC_CH129" "0: End of conversion for CH[129] has not occurred.,1: End of conversion for CH[129] has occurred." bitfld.long 0x0 0. "EOC_CH128,EOC_CH128" "0: End of conversion for CH[128] has not occurred.,1: End of conversion for CH[128] has occurred." line.long 0x4 "ECIPR1,External Channel Interrupt Pending Register 1" bitfld.long 0x4 31. "EOC_CH191,EOC_CH191" "0: End of conversion for CH[191] has not occurred.,1: End of conversion for CH[191] has occurred." bitfld.long 0x4 30. "EOC_CH190,EOC_CH190" "0: End of conversion for CH[190] has not occurred.,1: End of conversion for CH[190] has occurred." newline bitfld.long 0x4 29. "EOC_CH189,EOC_CH189" "0: End of conversion for CH[189] has not occurred.,1: End of conversion for CH[189] has occurred." bitfld.long 0x4 28. "EOC_CH188,EOC_CH188" "0: End of conversion for CH[188] has not occurred.,1: End of conversion for CH[188] has occurred." newline bitfld.long 0x4 27. "EOC_CH187,EOC_CH187" "0: End of conversion for CH[187] has not occurred.,1: End of conversion for CH[187] has occurred." bitfld.long 0x4 26. "EOC_CH186,EOC_CH186" "0: End of conversion for CH[186] has not occurred.,1: End of conversion for CH[186] has occurred." newline bitfld.long 0x4 25. "EOC_CH185,EOC_CH185" "0: End of conversion for CH[185] has not occurred.,1: End of conversion for CH[185] has occurred." bitfld.long 0x4 24. "EOC_CH184,EOC_CH184" "0: End of conversion for CH[184] has not occurred.,1: End of conversion for CH[184] has occurred." newline bitfld.long 0x4 23. "EOC_CH183,EOC_CH183" "0: End of conversion for CH[183] has not occurred.,1: End of conversion for CH[183] has occurred." bitfld.long 0x4 22. "EOC_CH182,EOC_CH182" "0: End of conversion for CH[182] has not occurred.,1: End of conversion for CH[182] has occurred." newline bitfld.long 0x4 21. "EOC_CH181,EOC_CH181" "0: End of conversion for CH[181] has not occurred.,1: End of conversion for CH[181] has occurred." bitfld.long 0x4 20. "EOC_CH180,EOC_CH180" "0: End of conversion for CH[180] has not occurred.,1: End of conversion for CH[180] has occurred." newline bitfld.long 0x4 19. "EOC_CH179,EOC_CH179" "0: End of conversion for CH[179] has not occurred.,1: End of conversion for CH[179] has occurred." bitfld.long 0x4 18. "EOC_CH178,EOC_CH178" "0: End of conversion for CH[178] has not occurred.,1: End of conversion for CH[178] has occurred." newline bitfld.long 0x4 17. "EOC_CH177,EOC_CH177" "0: End of conversion for CH[177] has not occurred.,1: End of conversion for CH[177] has occurred." bitfld.long 0x4 16. "EOC_CH176,EOC_CH176" "0: End of conversion for CH[176] has not occurred.,1: End of conversion for CH[176] has occurred." newline bitfld.long 0x4 15. "EOC_CH175,EOC_CH175" "0: End of conversion for CH[175] has not occurred.,1: End of conversion for CH[175] has occurred." bitfld.long 0x4 14. "EOC_CH174,EOC_CH174" "0: End of conversion for CH[174] has not occurred.,1: End of conversion for CH[174] has occurred." newline bitfld.long 0x4 13. "EOC_CH173,EOC_CH173" "0: End of conversion for CH[173] has not occurred.,1: End of conversion for CH[173] has occurred." bitfld.long 0x4 12. "EOC_CH172,EOC_CH172" "0: End of conversion for CH[172] has not occurred.,1: End of conversion for CH[172] has occurred." newline bitfld.long 0x4 11. "EOC_CH171,EOC_CH171" "0: End of conversion for CH[171] has not occurred.,1: End of conversion for CH[171] has occurred." bitfld.long 0x4 10. "EOC_CH170,EOC_CH170" "0: End of conversion for CH[170] has not occurred.,1: End of conversion for CH[170] has occurred." newline bitfld.long 0x4 9. "EOC_CH169,EOC_CH169" "0: End of conversion for CH[169] has not occurred.,1: End of conversion for CH[169] has occurred." bitfld.long 0x4 8. "EOC_CH168,EOC_CH168" "0: End of conversion for CH[168] has not occurred.,1: End of conversion for CH[168] has occurred." newline bitfld.long 0x4 7. "EOC_CH167,EOC_CH167" "0: End of conversion for CH[167] has not occurred.,1: End of conversion for CH[167] has occurred." bitfld.long 0x4 6. "EOC_CH166,EOC_CH166" "0: End of conversion for CH[166] has not occurred.,1: End of conversion for CH[166] has occurred." newline bitfld.long 0x4 5. "EOC_CH165,EOC_CH165" "0: End of conversion for CH[165] has not occurred.,1: End of conversion for CH[165] has occurred." bitfld.long 0x4 4. "EOC_CH164,EOC_CH164" "0: End of conversion for CH[164] has not occurred.,1: End of conversion for CH[164] has occurred." newline bitfld.long 0x4 3. "EOC_CH163,EOC_CH163" "0: End of conversion for CH[163] has not occurred.,1: End of conversion for CH[163] has occurred." bitfld.long 0x4 2. "EOC_CH162,EOC_CH162" "0: End of conversion for CH[162] has not occurred.,1: End of conversion for CH[162] has occurred." newline bitfld.long 0x4 1. "EOC_CH161,EOC_CH161" "0: End of conversion for CH[161] has not occurred.,1: End of conversion for CH[161] has occurred." bitfld.long 0x4 0. "EOC_CH160,EOC_CH160" "0: End of conversion for CH[160] has not occurred.,1: End of conversion for CH[160] has occurred." group.long 0x520++0x7 line.long 0x0 "ECIMR0,External Channel Interrupt Mask Register 0" bitfld.long 0x0 31. "IM_CH159,IM_CH159" "0: Interrupt for CH[159] is disabled.,1: Interrupt for CH[159] is enabled." bitfld.long 0x0 30. "IM_CH158,IM_CH158" "0: Interrupt for CH[158] is disabled.,1: Interrupt for CH[158] is enabled." newline bitfld.long 0x0 29. "IM_CH157,IM_CH157" "0: Interrupt for CH[157] is disabled.,1: Interrupt for CH[157] is enabled." bitfld.long 0x0 28. "IM_CH156,IM_CH156" "0: Interrupt for CH[156] is disabled.,1: Interrupt for CH[156] is enabled." newline bitfld.long 0x0 27. "IM_CH155,IM_CH155" "0: Interrupt for CH[155] is disabled.,1: Interrupt for CH[155] is enabled." bitfld.long 0x0 26. "IM_CH154,IM_CH154" "0: Interrupt for CH[154] is disabled.,1: Interrupt for CH[154] is enabled." newline bitfld.long 0x0 25. "IM_CH153,IM_CH153" "0: Interrupt for CH[153] is disabled.,1: Interrupt for CH[153] is enabled." bitfld.long 0x0 24. "IM_CH152,IM_CH152" "0: Interrupt for CH[152] is disabled.,1: Interrupt for CH[152] is enabled." newline bitfld.long 0x0 23. "IM_CH151,IM_CH151" "0: Interrupt for CH[151] is disabled.,1: Interrupt for CH[151] is enabled." bitfld.long 0x0 22. "IM_CH150,IM_CH150" "0: Interrupt for CH[150] is disabled.,1: Interrupt for CH[150] is enabled." newline bitfld.long 0x0 21. "IM_CH149,IM_CH149" "0: Interrupt for CH[149] is disabled.,1: Interrupt for CH[149] is enabled." bitfld.long 0x0 20. "IM_CH148,IM_CH148" "0: Interrupt for CH[148] is disabled.,1: Interrupt for CH[148] is enabled." newline bitfld.long 0x0 19. "IM_CH147,IM_CH147" "0: Interrupt for CH[147] is disabled.,1: Interrupt for CH[147] is enabled." bitfld.long 0x0 18. "IM_CH146,IM_CH146" "0: Interrupt for CH[146] is disabled.,1: Interrupt for CH[146] is enabled." newline bitfld.long 0x0 17. "IM_CH145,IM_CH145" "0: Interrupt for CH[145] is disabled.,1: Interrupt for CH[145] is enabled." bitfld.long 0x0 16. "IM_CH144,IM_CH144" "0: Interrupt for CH[144] is disabled.,1: Interrupt for CH[144] is enabled." newline bitfld.long 0x0 15. "IM_CH143,IM_CH143" "0: Interrupt for CH[143] is disabled.,1: Interrupt for CH[143] is enabled." bitfld.long 0x0 14. "IM_CH142,IM_CH142" "0: Interrupt for CH[142] is disabled.,1: Interrupt for CH[142] is enabled." newline bitfld.long 0x0 13. "IM_CH141,IM_CH141" "0: Interrupt for CH[141] is disabled.,1: Interrupt for CH[141] is enabled." bitfld.long 0x0 12. "IM_CH140,IM_CH140" "0: Interrupt for CH[140] is disabled.,1: Interrupt for CH[140] is enabled." newline bitfld.long 0x0 11. "IM_CH139,IM_CH139" "0: Interrupt for CH[139] is disabled.,1: Interrupt for CH[139] is enabled." bitfld.long 0x0 10. "IM_CH138,IM_CH138" "0: Interrupt for CH[138] is disabled.,1: Interrupt for CH[138] is enabled." newline bitfld.long 0x0 9. "IM_CH137,IM_CH137" "0: Interrupt for CH[137] is disabled.,1: Interrupt for CH[137] is enabled." bitfld.long 0x0 8. "IM_CH136,IM_CH136" "0: Interrupt for CH[136] is disabled.,1: Interrupt for CH[136] is enabled." newline bitfld.long 0x0 7. "IM_CH135,IM_CH135" "0: Interrupt for CH[135] is disabled.,1: Interrupt for CH[135] is enabled." bitfld.long 0x0 6. "IM_CH134,IM_CH134" "0: Interrupt for CH[134] is disabled.,1: Interrupt for CH[134] is enabled." newline bitfld.long 0x0 5. "IM_CH133,IM_CH133" "0: Interrupt for CH[133] is disabled.,1: Interrupt for CH[133] is enabled." bitfld.long 0x0 4. "IM_CH132,IM_CH132" "0: Interrupt for CH[132] is disabled.,1: Interrupt for CH[132] is enabled." newline bitfld.long 0x0 3. "IM_CH131,IM_CH131" "0: Interrupt for CH[131] is disabled.,1: Interrupt for CH[131] is enabled." bitfld.long 0x0 2. "IM_CH130,IM_CH130" "0: Interrupt for CH[130] is disabled.,1: Interrupt for CH[130] is enabled." newline bitfld.long 0x0 1. "IM_CH129,IM_CH129" "0: Interrupt for CH[129] is disabled.,1: Interrupt for CH[129] is enabled." bitfld.long 0x0 0. "IM_CH128,IM_CH128" "0: Interrupt for CH[128] is disabled.,1: Interrupt for CH[128] is enabled." line.long 0x4 "ECIMR1,External Channel Interrupt Mask Register 1" bitfld.long 0x4 31. "IM_CH191,IM_CH191" "0: Interrupt for CH[191] is disabled.,1: Interrupt for CH[191] is enabled." bitfld.long 0x4 30. "IM_CH190,IM_CH190" "0: Interrupt for CH[190] is disabled.,1: Interrupt for CH[190] is enabled." newline bitfld.long 0x4 29. "IM_CH189,IM_CH189" "0: Interrupt for CH[189] is disabled.,1: Interrupt for CH[189] is enabled." bitfld.long 0x4 28. "IM_CH188,IM_CH188" "0: Interrupt for CH[188] is disabled.,1: Interrupt for CH[188] is enabled." newline bitfld.long 0x4 27. "IM_CH187,IM_CH187" "0: Interrupt for CH[187] is disabled.,1: Interrupt for CH[187] is enabled." bitfld.long 0x4 26. "IM_CH186,IM_CH186" "0: Interrupt for CH[186] is disabled.,1: Interrupt for CH[186] is enabled." newline bitfld.long 0x4 25. "IM_CH185,IM_CH185" "0: Interrupt for CH[185] is disabled.,1: Interrupt for CH[185] is enabled." bitfld.long 0x4 24. "IM_CH184,IM_CH184" "0: Interrupt for CH[184] is disabled.,1: Interrupt for CH[184] is enabled." newline bitfld.long 0x4 23. "IM_CH183,IM_CH183" "0: Interrupt for CH[183] is disabled.,1: Interrupt for CH[183] is enabled." bitfld.long 0x4 22. "IM_CH182,IM_CH182" "0: Interrupt for CH[182] is disabled.,1: Interrupt for CH[182] is enabled." newline bitfld.long 0x4 21. "IM_CH181,IM_CH181" "0: Interrupt for CH[181] is disabled.,1: Interrupt for CH[181] is enabled." bitfld.long 0x4 20. "IM_CH180,IM_CH180" "0: Interrupt for CH[180] is disabled.,1: Interrupt for CH[180] is enabled." newline bitfld.long 0x4 19. "IM_CH179,IM_CH179" "0: Interrupt for CH[179] is disabled.,1: Interrupt for CH[179] is enabled." bitfld.long 0x4 18. "IM_CH178,IM_CH178" "0: Interrupt for CH[178] is disabled.,1: Interrupt for CH[178] is enabled." newline bitfld.long 0x4 17. "IM_CH177,IM_CH177" "0: Interrupt for CH[177] is disabled.,1: Interrupt for CH[177] is enabled." bitfld.long 0x4 16. "IM_CH176,IM_CH176" "0: Interrupt for CH[176] is disabled.,1: Interrupt for CH[176] is enabled." newline bitfld.long 0x4 15. "IM_CH175,IM_CH175" "0: Interrupt for CH[175] is disabled.,1: Interrupt for CH[175] is enabled." bitfld.long 0x4 14. "IM_CH174,IM_CH174" "0: Interrupt for CH[174] is disabled.,1: Interrupt for CH[174] is enabled." newline bitfld.long 0x4 13. "IM_CH173,IM_CH173" "0: Interrupt for CH[173] is disabled.,1: Interrupt for CH[173] is enabled." bitfld.long 0x4 12. "IM_CH172,IM_CH172" "0: Interrupt for CH[172] is disabled.,1: Interrupt for CH[172] is enabled." newline bitfld.long 0x4 11. "IM_CH171,IM_CH171" "0: Interrupt for CH[171] is disabled.,1: Interrupt for CH[171] is enabled." bitfld.long 0x4 10. "IM_CH170,IM_CH170" "0: Interrupt for CH[170] is disabled.,1: Interrupt for CH[170] is enabled." newline bitfld.long 0x4 9. "IM_CH169,IM_CH169" "0: Interrupt for CH[169] is disabled.,1: Interrupt for CH[169] is enabled." bitfld.long 0x4 8. "IM_CH168,IM_CH168" "0: Interrupt for CH[168] is disabled.,1: Interrupt for CH[168] is enabled." newline bitfld.long 0x4 7. "IM_CH167,IM_CH167" "0: Interrupt for CH[167] is disabled.,1: Interrupt for CH[167] is enabled." bitfld.long 0x4 6. "IM_CH166,IM_CH166" "0: Interrupt for CH[166] is disabled.,1: Interrupt for CH[166] is enabled." newline bitfld.long 0x4 5. "IM_CH165,IM_CH165" "0: Interrupt for CH[165] is disabled.,1: Interrupt for CH[165] is enabled." bitfld.long 0x4 4. "IM_CH164,IM_CH164" "0: Interrupt for CH[164] is disabled.,1: Interrupt for CH[164] is enabled." newline bitfld.long 0x4 3. "IM_CH163,IM_CH163" "0: Interrupt for CH[163] is disabled.,1: Interrupt for CH[163] is enabled." bitfld.long 0x4 2. "IM_CH162,IM_CH162" "0: Interrupt for CH[162] is disabled.,1: Interrupt for CH[162] is enabled." newline bitfld.long 0x4 1. "IM_CH161,IM_CH161" "0: Interrupt for CH[161] is disabled.,1: Interrupt for CH[161] is enabled." bitfld.long 0x4 0. "IM_CH160,IM_CH160" "0: Interrupt for CH[160] is disabled.,1: Interrupt for CH[160] is enabled." group.long 0x540++0x7 line.long 0x0 "ECNCMR0,External Channel Normal Conversion Mask Register 0" bitfld.long 0x0 31. "NCE_CH159,NCE_CH159" "0: Normal conversion is disabled for CH[159].,1: Normal conversion is enabled for CH[159]." bitfld.long 0x0 30. "NCE_CH158,NCE_CH158" "0: Normal conversion is disabled for CH[158].,1: Normal conversion is enabled for CH[158]." newline bitfld.long 0x0 29. "NCE_CH157,NCE_CH157" "0: Normal conversion is disabled for CH[157].,1: Normal conversion is enabled for CH[157]." bitfld.long 0x0 28. "NCE_CH156,NCE_CH156" "0: Normal conversion is disabled for CH[156].,1: Normal conversion is enabled for CH[156]." newline bitfld.long 0x0 27. "NCE_CH155,NCE_CH155" "0: Normal conversion is disabled for CH[155].,1: Normal conversion is enabled for CH[155]." bitfld.long 0x0 26. "NCE_CH154,NCE_CH154" "0: Normal conversion is disabled for CH[154].,1: Normal conversion is enabled for CH[154]." newline bitfld.long 0x0 25. "NCE_CH153,NCE_CH153" "0: Normal conversion is disabled for CH[153].,1: Normal conversion is enabled for CH[153]." bitfld.long 0x0 24. "NCE_CH152,NCE_CH152" "0: Normal conversion is disabled for CH[152].,1: Normal conversion is enabled for CH[152]." newline bitfld.long 0x0 23. "NCE_CH151,NCE_CH151" "0: Normal conversion is disabled for CH[151].,1: Normal conversion is enabled for CH[151]." bitfld.long 0x0 22. "NCE_CH150,NCE_CH150" "0: Normal conversion is disabled for CH[150].,1: Normal conversion is enabled for CH[150]." newline bitfld.long 0x0 21. "NCE_CH149,NCE_CH149" "0: Normal conversion is disabled for CH[149].,1: Normal conversion is enabled for CH[149]." bitfld.long 0x0 20. "NCE_CH148,NCE_CH148" "0: Normal conversion is disabled for CH[148].,1: Normal conversion is enabled for CH[148]." newline bitfld.long 0x0 19. "NCE_CH147,NCE_CH147" "0: Normal conversion is disabled for CH[147].,1: Normal conversion is enabled for CH[147]." bitfld.long 0x0 18. "NCE_CH146,NCE_CH146" "0: Normal conversion is disabled for CH[146].,1: Normal conversion is enabled for CH[146]." newline bitfld.long 0x0 17. "NCE_CH145,NCE_CH145" "0: Normal conversion is disabled for CH[145].,1: Normal conversion is enabled for CH[145]." bitfld.long 0x0 16. "NCE_CH144,NCE_CH144" "0: Normal conversion is disabled for CH[144].,1: Normal conversion is enabled for CH[144]." newline bitfld.long 0x0 15. "NCE_CH143,NCE_CH143" "0: Normal conversion is disabled for CH[143].,1: Normal conversion is enabled for CH[143]." bitfld.long 0x0 14. "NCE_CH142,NCE_CH142" "0: Normal conversion is disabled for CH[142].,1: Normal conversion is enabled for CH[142]." newline bitfld.long 0x0 13. "NCE_CH141,NCE_CH141" "0: Normal conversion is disabled for CH[141].,1: Normal conversion is enabled for CH[141]." bitfld.long 0x0 12. "NCE_CH140,NCE_CH140" "0: Normal conversion is disabled for CH[140].,1: Normal conversion is enabled for CH[140]." newline bitfld.long 0x0 11. "NCE_CH139,NCE_CH139" "0: Normal conversion is disabled for CH[139].,1: Normal conversion is enabled for CH[139]." bitfld.long 0x0 10. "NCE_CH138,NCE_CH138" "0: Normal conversion is disabled for CH[138].,1: Normal conversion is enabled for CH[138]." newline bitfld.long 0x0 9. "NCE_CH137,NCE_CH137" "0: Normal conversion is disabled for CH[137].,1: Normal conversion is enabled for CH[137]." bitfld.long 0x0 8. "NCE_CH136,NCE_CH136" "0: Normal conversion is disabled for CH[136].,1: Normal conversion is enabled for CH[136]." newline bitfld.long 0x0 7. "NCE_CH135,NCE_CH135" "0: Normal conversion is disabled for CH[135].,1: Normal conversion is enabled for CH[135]." bitfld.long 0x0 6. "NCE_CH134,NCE_CH134" "0: Normal conversion is disabled for CH[134].,1: Normal conversion is enabled for CH[134]." newline bitfld.long 0x0 5. "NCE_CH133,NCE_CH133" "0: Normal conversion is disabled for CH[133].,1: Normal conversion is enabled for CH[133]." bitfld.long 0x0 4. "NCE_CH132,NCE_CH132" "0: Normal conversion is disabled for CH[132].,1: Normal conversion is enabled for CH[132]." newline bitfld.long 0x0 3. "NCE_CH131,NCE_CH131" "0: Normal conversion is disabled for CH[131].,1: Normal conversion is enabled for CH[131]." bitfld.long 0x0 2. "NCE_CH130,NCE_CH130" "0: Normal conversion is disabled for CH[130].,1: Normal conversion is enabled for CH[130]." newline bitfld.long 0x0 1. "NCE_CH129,NCE_CH129" "0: Normal conversion is disabled for CH[129].,1: Normal conversion is enabled for CH[129]." bitfld.long 0x0 0. "NCE_CH128,NCE_CH128" "0: Normal conversion is disabled for CH[128].,1: Normal conversion is enabled for CH[128]." line.long 0x4 "ECNCMR1,External Channel Normal Conversion Mask Register 1" bitfld.long 0x4 31. "NCE_CH191,NCE_CH191" "0: Normal conversion is disabled for CH[191].,1: Normal conversion is enabled for CH[191]." bitfld.long 0x4 30. "NCE_CH190,NCE_CH190" "0: Normal conversion is disabled for CH[190].,1: Normal conversion is enabled for CH[190]." newline bitfld.long 0x4 29. "NCE_CH189,NCE_CH189" "0: Normal conversion is disabled for CH[189].,1: Normal conversion is enabled for CH[189]." bitfld.long 0x4 28. "NCE_CH188,NCE_CH188" "0: Normal conversion is disabled for CH[188].,1: Normal conversion is enabled for CH[188]." newline bitfld.long 0x4 27. "NCE_CH187,NCE_CH187" "0: Normal conversion is disabled for CH[187].,1: Normal conversion is enabled for CH[187]." bitfld.long 0x4 26. "NCE_CH186,NCE_CH186" "0: Normal conversion is disabled for CH[186].,1: Normal conversion is enabled for CH[186]." newline bitfld.long 0x4 25. "NCE_CH185,NCE_CH185" "0: Normal conversion is disabled for CH[185].,1: Normal conversion is enabled for CH[185]." bitfld.long 0x4 24. "NCE_CH184,NCE_CH184" "0: Normal conversion is disabled for CH[184].,1: Normal conversion is enabled for CH[184]." newline bitfld.long 0x4 23. "NCE_CH183,NCE_CH183" "0: Normal conversion is disabled for CH[183].,1: Normal conversion is enabled for CH[183]." bitfld.long 0x4 22. "NCE_CH182,NCE_CH182" "0: Normal conversion is disabled for CH[182].,1: Normal conversion is enabled for CH[182]." newline bitfld.long 0x4 21. "NCE_CH181,NCE_CH181" "0: Normal conversion is disabled for CH[181].,1: Normal conversion is enabled for CH[181]." bitfld.long 0x4 20. "NCE_CH180,NCE_CH180" "0: Normal conversion is disabled for CH[180].,1: Normal conversion is enabled for CH[180]." newline bitfld.long 0x4 19. "NCE_CH179,NCE_CH179" "0: Normal conversion is disabled for CH[179].,1: Normal conversion is enabled for CH[179]." bitfld.long 0x4 18. "NCE_CH178,NCE_CH178" "0: Normal conversion is disabled for CH[178].,1: Normal conversion is enabled for CH[178]." newline bitfld.long 0x4 17. "NCE_CH177,NCE_CH177" "0: Normal conversion is disabled for CH[177].,1: Normal conversion is enabled for CH[177]." bitfld.long 0x4 16. "NCE_CH176,NCE_CH176" "0: Normal conversion is disabled for CH[176].,1: Normal conversion is enabled for CH[176]." newline bitfld.long 0x4 15. "NCE_CH175,NCE_CH175" "0: Normal conversion is disabled for CH[175].,1: Normal conversion is enabled for CH[175]." bitfld.long 0x4 14. "NCE_CH174,NCE_CH174" "0: Normal conversion is disabled for CH[174].,1: Normal conversion is enabled for CH[174]." newline bitfld.long 0x4 13. "NCE_CH173,NCE_CH173" "0: Normal conversion is disabled for CH[173].,1: Normal conversion is enabled for CH[173]." bitfld.long 0x4 12. "NCE_CH172,NCE_CH172" "0: Normal conversion is disabled for CH[172].,1: Normal conversion is enabled for CH[172]." newline bitfld.long 0x4 11. "NCE_CH171,NCE_CH171" "0: Normal conversion is disabled for CH[171].,1: Normal conversion is enabled for CH[171]." bitfld.long 0x4 10. "NCE_CH170,NCE_CH170" "0: Normal conversion is disabled for CH[170].,1: Normal conversion is enabled for CH[170]." newline bitfld.long 0x4 9. "NCE_CH169,NCE_CH169" "0: Normal conversion is disabled for CH[169].,1: Normal conversion is enabled for CH[169]." bitfld.long 0x4 8. "NCE_CH168,NCE_CH168" "0: Normal conversion is disabled for CH[168].,1: Normal conversion is enabled for CH[168]." newline bitfld.long 0x4 7. "NCE_CH167,NCE_CH167" "0: Normal conversion is disabled for CH[167].,1: Normal conversion is enabled for CH[167]." bitfld.long 0x4 6. "NCE_CH166,NCE_CH166" "0: Normal conversion is disabled for CH[166].,1: Normal conversion is enabled for CH[166]." newline bitfld.long 0x4 5. "NCE_CH165,NCE_CH165" "0: Normal conversion is disabled for CH[165].,1: Normal conversion is enabled for CH[165]." bitfld.long 0x4 4. "NCE_CH164,NCE_CH164" "0: Normal conversion is disabled for CH[164].,1: Normal conversion is enabled for CH[164]." newline bitfld.long 0x4 3. "NCE_CH163,NCE_CH163" "0: Normal conversion is disabled for CH[163].,1: Normal conversion is enabled for CH[163]." bitfld.long 0x4 2. "NCE_CH162,NCE_CH162" "0: Normal conversion is disabled for CH[162].,1: Normal conversion is enabled for CH[162]." newline bitfld.long 0x4 1. "NCE_CH161,NCE_CH161" "0: Normal conversion is disabled for CH[161].,1: Normal conversion is enabled for CH[161]." bitfld.long 0x4 0. "NCE_CH160,NCE_CH160" "0: Normal conversion is disabled for CH[160].,1: Normal conversion is enabled for CH[160]." group.long 0x550++0x7 line.long 0x0 "ECJCMR0,External Channel Injected Conversion Mask Register 0" bitfld.long 0x0 31. "JCE_CH159,JCE_CH159" "0: Injected conversion is disabled for CH[159].,1: Injected conversion is enabled for CH[159]." bitfld.long 0x0 30. "JCE_CH158,JCE_CH158" "0: Injected conversion is disabled for CH[158].,1: Injected conversion is enabled for CH[158]." newline bitfld.long 0x0 29. "JCE_CH157,JCE_CH157" "0: Injected conversion is disabled for CH[157].,1: Injected conversion is enabled for CH[157]." bitfld.long 0x0 28. "JCE_CH156,JCE_CH156" "0: Injected conversion is disabled for CH[156].,1: Injected conversion is enabled for CH[156]." newline bitfld.long 0x0 27. "JCE_CH155,JCE_CH155" "0: Injected conversion is disabled for CH[155].,1: Injected conversion is enabled for CH[155]." bitfld.long 0x0 26. "JCE_CH154,JCE_CH154" "0: Injected conversion is disabled for CH[154].,1: Injected conversion is enabled for CH[154]." newline bitfld.long 0x0 25. "JCE_CH153,JCE_CH153" "0: Injected conversion is disabled for CH[153].,1: Injected conversion is enabled for CH[153]." bitfld.long 0x0 24. "JCE_CH152,JCE_CH152" "0: Injected conversion is disabled for CH[152].,1: Injected conversion is enabled for CH[152]." newline bitfld.long 0x0 23. "JCE_CH151,JCE_CH151" "0: Injected conversion is disabled for CH[151].,1: Injected conversion is enabled for CH[151]." bitfld.long 0x0 22. "JCE_CH150,JCE_CH150" "0: Injected conversion is disabled for CH[150].,1: Injected conversion is enabled for CH[150]." newline bitfld.long 0x0 21. "JCE_CH149,JCE_CH149" "0: Injected conversion is disabled for CH[149].,1: Injected conversion is enabled for CH[149]." bitfld.long 0x0 20. "JCE_CH148,JCE_CH148" "0: Injected conversion is disabled for CH[148].,1: Injected conversion is enabled for CH[148]." newline bitfld.long 0x0 19. "JCE_CH147,JCE_CH147" "0: Injected conversion is disabled for CH[147].,1: Injected conversion is enabled for CH[147]." bitfld.long 0x0 18. "JCE_CH146,JCE_CH146" "0: Injected conversion is disabled for CH[146].,1: Injected conversion is enabled for CH[146]." newline bitfld.long 0x0 17. "JCE_CH145,JCE_CH145" "0: Injected conversion is disabled for CH[145].,1: Injected conversion is enabled for CH[145]." bitfld.long 0x0 16. "JCE_CH144,JCE_CH144" "0: Injected conversion is disabled for CH[144].,1: Injected conversion is enabled for CH[144]." newline bitfld.long 0x0 15. "JCE_CH143,JCE_CH143" "0: Injected conversion is disabled for CH[143].,1: Injected conversion is enabled for CH[143]." bitfld.long 0x0 14. "JCE_CH142,JCE_CH142" "0: Injected conversion is disabled for CH[142].,1: Injected conversion is enabled for CH[142]." newline bitfld.long 0x0 13. "JCE_CH141,JCE_CH141" "0: Injected conversion is disabled for CH[141].,1: Injected conversion is enabled for CH[141]." bitfld.long 0x0 12. "JCE_CH140,JCE_CH140" "0: Injected conversion is disabled for CH[140].,1: Injected conversion is enabled for CH[140]." newline bitfld.long 0x0 11. "JCE_CH139,JCE_CH139" "0: Injected conversion is disabled for CH[139].,1: Injected conversion is enabled for CH[139]." bitfld.long 0x0 10. "JCE_CH138,JCE_CH138" "0: Injected conversion is disabled for CH[138].,1: Injected conversion is enabled for CH[138]." newline bitfld.long 0x0 9. "JCE_CH137,JCE_CH137" "0: Injected conversion is disabled for CH[137].,1: Injected conversion is enabled for CH[137]." bitfld.long 0x0 8. "JCE_CH136,JCE_CH136" "0: Injected conversion is disabled for CH[136].,1: Injected conversion is enabled for CH[136]." newline bitfld.long 0x0 7. "JCE_CH135,JCE_CH135" "0: Injected conversion is disabled for CH[135].,1: Injected conversion is enabled for CH[135]." bitfld.long 0x0 6. "JCE_CH134,JCE_CH134" "0: Injected conversion is disabled for CH[134].,1: Injected conversion is enabled for CH[134]." newline bitfld.long 0x0 5. "JCE_CH133,JCE_CH133" "0: Injected conversion is disabled for CH[133].,1: Injected conversion is enabled for CH[133]." bitfld.long 0x0 4. "JCE_CH132,JCE_CH132" "0: Injected conversion is disabled for CH[132].,1: Injected conversion is enabled for CH[132]." newline bitfld.long 0x0 3. "JCE_CH131,JCE_CH131" "0: Injected conversion is disabled for CH[131].,1: Injected conversion is enabled for CH[131]." bitfld.long 0x0 2. "JCE_CH130,JCE_CH130" "0: Injected conversion is disabled for CH[130].,1: Injected conversion is enabled for CH[130]." newline bitfld.long 0x0 1. "JCE_CH129,JCE_CH129" "0: Injected conversion is disabled for CH[129].,1: Injected conversion is enabled for CH[129]." bitfld.long 0x0 0. "JCE_CH128,JCE_CH128" "0: Injected conversion is disabled for CH[128].,1: Injected conversion is enabled for CH[128]." line.long 0x4 "ECJCMR1,External Channel Injected Conversion Mask Register 1" bitfld.long 0x4 31. "JCE_CH191,JCE_CH191" "0: Injected conversion is disabled for CH[191].,1: Injected conversion is enabled for CH[191]." bitfld.long 0x4 30. "JCE_CH190,JCE_CH190" "0: Injected conversion is disabled for CH[190].,1: Injected conversion is enabled for CH[190]." newline bitfld.long 0x4 29. "JCE_CH189,JCE_CH189" "0: Injected conversion is disabled for CH[189].,1: Injected conversion is enabled for CH[189]." bitfld.long 0x4 28. "JCE_CH188,JCE_CH188" "0: Injected conversion is disabled for CH[188].,1: Injected conversion is enabled for CH[188]." newline bitfld.long 0x4 27. "JCE_CH187,JCE_CH187" "0: Injected conversion is disabled for CH[187].,1: Injected conversion is enabled for CH[187]." bitfld.long 0x4 26. "JCE_CH186,JCE_CH186" "0: Injected conversion is disabled for CH[186].,1: Injected conversion is enabled for CH[186]." newline bitfld.long 0x4 25. "JCE_CH185,JCE_CH185" "0: Injected conversion is disabled for CH[185].,1: Injected conversion is enabled for CH[185]." bitfld.long 0x4 24. "JCE_CH184,JCE_CH184" "0: Injected conversion is disabled for CH[184].,1: Injected conversion is enabled for CH[184]." newline bitfld.long 0x4 23. "JCE_CH183,JCE_CH183" "0: Injected conversion is disabled for CH[183].,1: Injected conversion is enabled for CH[183]." bitfld.long 0x4 22. "JCE_CH182,JCE_CH182" "0: Injected conversion is disabled for CH[182].,1: Injected conversion is enabled for CH[182]." newline bitfld.long 0x4 21. "JCE_CH181,JCE_CH181" "0: Injected conversion is disabled for CH[181].,1: Injected conversion is enabled for CH[181]." bitfld.long 0x4 20. "JCE_CH180,JCE_CH180" "0: Injected conversion is disabled for CH[180].,1: Injected conversion is enabled for CH[180]." newline bitfld.long 0x4 19. "JCE_CH179,JCE_CH179" "0: Injected conversion is disabled for CH[179].,1: Injected conversion is enabled for CH[179]." bitfld.long 0x4 18. "JCE_CH178,JCE_CH178" "0: Injected conversion is disabled for CH[178].,1: Injected conversion is enabled for CH[178]." newline bitfld.long 0x4 17. "JCE_CH177,JCE_CH177" "0: Injected conversion is disabled for CH[177].,1: Injected conversion is enabled for CH[177]." bitfld.long 0x4 16. "JCE_CH176,JCE_CH176" "0: Injected conversion is disabled for CH[176].,1: Injected conversion is enabled for CH[176]." newline bitfld.long 0x4 15. "JCE_CH175,JCE_CH175" "0: Injected conversion is disabled for CH[175].,1: Injected conversion is enabled for CH[175]." bitfld.long 0x4 14. "JCE_CH174,JCE_CH174" "0: Injected conversion is disabled for CH[174].,1: Injected conversion is enabled for CH[174]." newline bitfld.long 0x4 13. "JCE_CH173,JCE_CH173" "0: Injected conversion is disabled for CH[173].,1: Injected conversion is enabled for CH[173]." bitfld.long 0x4 12. "JCE_CH172,JCE_CH172" "0: Injected conversion is disabled for CH[172].,1: Injected conversion is enabled for CH[172]." newline bitfld.long 0x4 11. "JCE_CH171,JCE_CH171" "0: Injected conversion is disabled for CH[171].,1: Injected conversion is enabled for CH[171]." bitfld.long 0x4 10. "JCE_CH170,JCE_CH170" "0: Injected conversion is disabled for CH[170].,1: Injected conversion is enabled for CH[170]." newline bitfld.long 0x4 9. "JCE_CH169,JCE_CH169" "0: Injected conversion is disabled for CH[169].,1: Injected conversion is enabled for CH[169]." bitfld.long 0x4 8. "JCE_CH168,JCE_CH168" "0: Injected conversion is disabled for CH[168].,1: Injected conversion is enabled for CH[168]." newline bitfld.long 0x4 7. "JCE_CH167,JCE_CH167" "0: Injected conversion is disabled for CH[167].,1: Injected conversion is enabled for CH[167]." bitfld.long 0x4 6. "JCE_CH166,JCE_CH166" "0: Injected conversion is disabled for CH[166].,1: Injected conversion is enabled for CH[166]." newline bitfld.long 0x4 5. "JCE_CH165,JCE_CH165" "0: Injected conversion is disabled for CH[165].,1: Injected conversion is enabled for CH[165]." bitfld.long 0x4 4. "JCE_CH164,JCE_CH164" "0: Injected conversion is disabled for CH[164].,1: Injected conversion is enabled for CH[164]." newline bitfld.long 0x4 3. "JCE_CH163,JCE_CH163" "0: Injected conversion is disabled for CH[163].,1: Injected conversion is enabled for CH[163]." bitfld.long 0x4 2. "JCE_CH162,JCE_CH162" "0: Injected conversion is disabled for CH[162].,1: Injected conversion is enabled for CH[162]." newline bitfld.long 0x4 1. "JCE_CH161,JCE_CH161" "0: Injected conversion is disabled for CH[161].,1: Injected conversion is enabled for CH[161]." bitfld.long 0x4 0. "JCE_CH160,JCE_CH160" "0: Injected conversion is disabled for CH[160].,1: Injected conversion is enabled for CH[160]." group.long 0x560++0x1F line.long 0x0 "ECWSELR0,External Channel Watchdog Selection Register 0" bitfld.long 0x0 28. "WSEL_CH135,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x0 24. "WSEL_CH134,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x0 20. "WSEL_CH133,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x0 16. "WSEL_CH132,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x0 12. "WSEL_CH131,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x0 8. "WSEL_CH130,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x0 4. "WSEL_CH129,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x0 0. "WSEL_CH128,0000 THRHLR0 register is selected" "0,1" line.long 0x4 "ECWSELR1,External Channel Watchdog Selection Register 1" bitfld.long 0x4 28. "WSEL_CH143,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x4 24. "WSEL_CH142,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x4 20. "WSEL_CH141,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x4 16. "WSEL_CH140,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x4 12. "WSEL_CH139,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x4 8. "WSEL_CH138,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x4 4. "WSEL_CH137,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x4 0. "WSEL_CH136,0000 THRHLR0 register is selected" "0,1" line.long 0x8 "ECWSELR2,External Channel Watchdog Selection Register 2" bitfld.long 0x8 28. "WSEL_CH151,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x8 24. "WSEL_CH150,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x8 20. "WSEL_CH149,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x8 16. "WSEL_CH148,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x8 12. "WSEL_CH147,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x8 8. "WSEL_CH146,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x8 4. "WSEL_CH145,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x8 0. "WSEL_CH144,0000 THRHLR0 register is selected" "0,1" line.long 0xC "ECWSELR3,External Channel Watchdog Selection Register 3" bitfld.long 0xC 28. "WSEL_CH159,0000 THRHLR0 register is selected" "0,1" bitfld.long 0xC 24. "WSEL_CH158,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0xC 20. "WSEL_CH157,0000 THRHLR0 register is selected" "0,1" bitfld.long 0xC 16. "WSEL_CH156,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0xC 12. "WSEL_CH155,0000 THRHLR0 register is selected" "0,1" bitfld.long 0xC 8. "WSEL_CH154,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0xC 4. "WSEL_CH153,0000 THRHLR0 register is selected" "0,1" bitfld.long 0xC 0. "WSEL_CH152,0000 THRHLR0 register is selected" "0,1" line.long 0x10 "ECWSELR4,External Channel Watchdog Selection Register 4" bitfld.long 0x10 28. "WSEL_CH167,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x10 24. "WSEL_CH166,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x10 20. "WSEL_CH165,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x10 16. "WSEL_CH164,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x10 12. "WSEL_CH163,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x10 8. "WSEL_CH162,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x10 4. "WSEL_CH161,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x10 0. "WSEL_CH160,0000 THRHLR0 register is selected" "0,1" line.long 0x14 "ECWSELR5,External Channel Watchdog Selection Register 5" bitfld.long 0x14 28. "WSEL_CH175,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x14 24. "WSEL_CH174,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x14 20. "WSEL_CH173,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x14 16. "WSEL_CH172,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x14 12. "WSEL_CH171,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x14 8. "WSEL_CH170,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x14 4. "WSEL_CH169,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x14 0. "WSEL_CH168,0000 THRHLR0 register is selected" "0,1" line.long 0x18 "ECWSELR6,External Channel Watchdog Selection Register 6" bitfld.long 0x18 28. "WSEL_CH183,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x18 24. "WSEL_CH182,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x18 20. "WSEL_CH181,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x18 16. "WSEL_CH180,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x18 12. "WSEL_CH179,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x18 8. "WSEL_CH178,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x18 4. "WSEL_CH177,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x18 0. "WSEL_CH176,0000 THRHLR0 register is selected" "0,1" line.long 0x1C "ECWSELR7,External Channel Watchdog Selection Register 7" bitfld.long 0x1C 28. "WSEL_CH191,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x1C 24. "WSEL_CH190,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x1C 20. "WSEL_CH189,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x1C 16. "WSEL_CH188,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x1C 12. "WSEL_CH187,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x1C 8. "WSEL_CH186,0000 THRHLR0 register is selected" "0,1" newline bitfld.long 0x1C 4. "WSEL_CH185,0000 THRHLR0 register is selected" "0,1" bitfld.long 0x1C 0. "WSEL_CH184,0000 THRHLR0 register is selected" "0,1" group.long 0x5A0++0x7 line.long 0x0 "ECWENR0,External Channel Watchdog Enable Register 0" bitfld.long 0x0 31. "WEN_CH159,WEN_CH159" "0: Watchdog feature is disabled for CH[159].,1: Watchdog feature is enabled for CH[159]." bitfld.long 0x0 30. "WEN_CH158,WEN_CH158" "0: Watchdog feature is disabled for CH[158].,1: Watchdog feature is enabled for CH[158]." newline bitfld.long 0x0 29. "WEN_CH157,WEN_CH157" "0: Watchdog feature is disabled for CH[157].,1: Watchdog feature is enabled for CH[157]." bitfld.long 0x0 28. "WEN_CH156,WEN_CH156" "0: Watchdog feature is disabled for CH[156].,1: Watchdog feature is enabled for CH[156]." newline bitfld.long 0x0 27. "WEN_CH155,WEN_CH155" "0: Watchdog feature is disabled for CH[155].,1: Watchdog feature is enabled for CH[155]." bitfld.long 0x0 26. "WEN_CH154,WEN_CH154" "0: Watchdog feature is disabled for CH[154].,1: Watchdog feature is enabled for CH[154]." newline bitfld.long 0x0 25. "WEN_CH153,WEN_CH153" "0: Watchdog feature is disabled for CH[153].,1: Watchdog feature is enabled for CH[153]." bitfld.long 0x0 24. "WEN_CH152,WEN_CH152" "0: Watchdog feature is disabled for CH[152].,1: Watchdog feature is enabled for CH[152]." newline bitfld.long 0x0 23. "WEN_CH151,WEN_CH151" "0: Watchdog feature is disabled for CH[151].,1: Watchdog feature is enabled for CH[151]." bitfld.long 0x0 22. "WEN_CH150,WEN_CH150" "0: Watchdog feature is disabled for CH[150].,1: Watchdog feature is enabled for CH[150]." newline bitfld.long 0x0 21. "WEN_CH149,WEN_CH149" "0: Watchdog feature is disabled for CH[149].,1: Watchdog feature is enabled for CH[149]." bitfld.long 0x0 20. "WEN_CH148,WEN_CH148" "0: Watchdog feature is disabled for CH[148].,1: Watchdog feature is enabled for CH[148]." newline bitfld.long 0x0 19. "WEN_CH147,WEN_CH147" "0: Watchdog feature is disabled for CH[147].,1: Watchdog feature is enabled for CH[147]." bitfld.long 0x0 18. "WEN_CH146,WEN_CH146" "0: Watchdog feature is disabled for CH[146].,1: Watchdog feature is enabled for CH[146]." newline bitfld.long 0x0 17. "WEN_CH145,WEN_CH145" "0: Watchdog feature is disabled for CH[145].,1: Watchdog feature is enabled for CH[145]." bitfld.long 0x0 16. "WEN_CH144,WEN_CH144" "0: Watchdog feature is disabled for CH[144].,1: Watchdog feature is enabled for CH[144]." newline bitfld.long 0x0 15. "WEN_CH143,WEN_CH143" "0: Watchdog feature is disabled for CH[143].,1: Watchdog feature is enabled for CH[143]." bitfld.long 0x0 14. "WEN_CH142,WEN_CH142" "0: Watchdog feature is disabled for CH[142].,1: Watchdog feature is enabled for CH[142]." newline bitfld.long 0x0 13. "WEN_CH141,WEN_CH141" "0: Watchdog feature is disabled for CH[141].,1: Watchdog feature is enabled for CH[141]." bitfld.long 0x0 12. "WEN_CH140,WEN_CH140" "0: Watchdog feature is disabled for CH[140].,1: Watchdog feature is enabled for CH[140]." newline bitfld.long 0x0 11. "WEN_CH139,WEN_CH139" "0: Watchdog feature is disabled for CH[139].,1: Watchdog feature is enabled for CH[139]." bitfld.long 0x0 10. "WEN_CH138,WEN_CH138" "0: Watchdog feature is disabled for CH[138].,1: Watchdog feature is enabled for CH[138]." newline bitfld.long 0x0 9. "WEN_CH137,WEN_CH137" "0: Watchdog feature is disabled for CH[137].,1: Watchdog feature is enabled for CH[137]." bitfld.long 0x0 8. "WEN_CH136,WEN_CH136" "0: Watchdog feature is disabled for CH[136].,1: Watchdog feature is enabled for CH[136]." newline bitfld.long 0x0 7. "WEN_CH135,WEN_CH135" "0: Watchdog feature is disabled for CH[135].,1: Watchdog feature is enabled for CH[135]." bitfld.long 0x0 6. "WEN_CH134,WEN_CH134" "0: Watchdog feature is disabled for CH[134].,1: Watchdog feature is enabled for CH[134]." newline bitfld.long 0x0 5. "WEN_CH133,WEN_CH133" "0: Watchdog feature is disabled for CH[133].,1: Watchdog feature is enabled for CH[133]." bitfld.long 0x0 4. "WEN_CH132,WEN_CH132" "0: Watchdog feature is disabled for CH[132].,1: Watchdog feature is enabled for CH[132]." newline bitfld.long 0x0 3. "WEN_CH131,WEN_CH131" "0: Watchdog feature is disabled for CH[131].,1: Watchdog feature is enabled for CH[131]." bitfld.long 0x0 2. "WEN_CH130,WEN_CH130" "0: Watchdog feature is disabled for CH[130].,1: Watchdog feature is enabled for CH[130]." newline bitfld.long 0x0 1. "WEN_CH129,WEN_CH129" "0: Watchdog feature is disabled for CH[129].,1: Watchdog feature is enabled for CH[129]." bitfld.long 0x0 0. "WEN_CH128,WEN_CH128" "0: Watchdog feature is disabled for CH[128].,1: Watchdog feature is enabled for CH[128]." line.long 0x4 "ECWENR1,External Channel Watchdog Enable Register 1" bitfld.long 0x4 31. "WEN_CH191,WEN_CH191" "0: Watchdog feature is disabled for CH[191].,1: Watchdog feature is enabled for CH[191]." bitfld.long 0x4 30. "WEN_CH190,WEN_CH190" "0: Watchdog feature is disabled for CH[190].,1: Watchdog feature is enabled for CH[190]." newline bitfld.long 0x4 29. "WEN_CH189,WEN_CH189" "0: Watchdog feature is disabled for CH[189].,1: Watchdog feature is enabled for CH[189]." bitfld.long 0x4 28. "WEN_CH188,WEN_CH188" "0: Watchdog feature is disabled for CH[188].,1: Watchdog feature is enabled for CH[188]." newline bitfld.long 0x4 27. "WEN_CH187,WEN_CH187" "0: Watchdog feature is disabled for CH[187].,1: Watchdog feature is enabled for CH[187]." bitfld.long 0x4 26. "WEN_CH186,WEN_CH186" "0: Watchdog feature is disabled for CH[186].,1: Watchdog feature is enabled for CH[186]." newline bitfld.long 0x4 25. "WEN_CH185,WEN_CH185" "0: Watchdog feature is disabled for CH[185].,1: Watchdog feature is enabled for CH[185]." bitfld.long 0x4 24. "WEN_CH184,WEN_CH184" "0: Watchdog feature is disabled for CH[184].,1: Watchdog feature is enabled for CH[184]." newline bitfld.long 0x4 23. "WEN_CH183,WEN_CH183" "0: Watchdog feature is disabled for CH[183].,1: Watchdog feature is enabled for CH[183]." bitfld.long 0x4 22. "WEN_CH182,WEN_CH182" "0: Watchdog feature is disabled for CH[182].,1: Watchdog feature is enabled for CH[182]." newline bitfld.long 0x4 21. "WEN_CH181,WEN_CH181" "0: Watchdog feature is disabled for CH[181].,1: Watchdog feature is enabled for CH[181]." bitfld.long 0x4 20. "WEN_CH180,WEN_CH180" "0: Watchdog feature is disabled for CH[180].,1: Watchdog feature is enabled for CH[180]." newline bitfld.long 0x4 19. "WEN_CH179,WEN_CH179" "0: Watchdog feature is disabled for CH[179].,1: Watchdog feature is enabled for CH[179]." bitfld.long 0x4 18. "WEN_CH178,WEN_CH178" "0: Watchdog feature is disabled for CH[178].,1: Watchdog feature is enabled for CH[178]." newline bitfld.long 0x4 17. "WEN_CH177,WEN_CH177" "0: Watchdog feature is disabled for CH[177].,1: Watchdog feature is enabled for CH[177]." bitfld.long 0x4 16. "WEN_CH176,WEN_CH176" "0: Watchdog feature is disabled for CH[176].,1: Watchdog feature is enabled for CH[176]." newline bitfld.long 0x4 15. "WEN_CH175,WEN_CH175" "0: Watchdog feature is disabled for CH[175].,1: Watchdog feature is enabled for CH[175]." bitfld.long 0x4 14. "WEN_CH174,WEN_CH174" "0: Watchdog feature is disabled for CH[174].,1: Watchdog feature is enabled for CH[174]." newline bitfld.long 0x4 13. "WEN_CH173,WEN_CH173" "0: Watchdog feature is disabled for CH[173].,1: Watchdog feature is enabled for CH[173]." bitfld.long 0x4 12. "WEN_CH172,WEN_CH172" "0: Watchdog feature is disabled for CH[172].,1: Watchdog feature is enabled for CH[172]." newline bitfld.long 0x4 11. "WEN_CH171,WEN_CH171" "0: Watchdog feature is disabled for CH[171].,1: Watchdog feature is enabled for CH[171]." bitfld.long 0x4 10. "WEN_CH170,WEN_CH170" "0: Watchdog feature is disabled for CH[170].,1: Watchdog feature is enabled for CH[170]." newline bitfld.long 0x4 9. "WEN_CH169,WEN_CH169" "0: Watchdog feature is disabled for CH[169].,1: Watchdog feature is enabled for CH[169]." bitfld.long 0x4 8. "WEN_CH168,WEN_CH168" "0: Watchdog feature is disabled for CH[168].,1: Watchdog feature is enabled for CH[168]." newline bitfld.long 0x4 7. "WEN_CH167,WEN_CH167" "0: Watchdog feature is disabled for CH[167].,1: Watchdog feature is enabled for CH[167]." bitfld.long 0x4 6. "WEN_CH166,WEN_CH166" "0: Watchdog feature is disabled for CH[166].,1: Watchdog feature is enabled for CH[166]." newline bitfld.long 0x4 5. "WEN_CH165,WEN_CH165" "0: Watchdog feature is disabled for CH[165].,1: Watchdog feature is enabled for CH[165]." bitfld.long 0x4 4. "WEN_CH164,WEN_CH164" "0: Watchdog feature is disabled for CH[164].,1: Watchdog feature is enabled for CH[164]." newline bitfld.long 0x4 3. "WEN_CH163,WEN_CH163" "0: Watchdog feature is disabled for CH[163].,1: Watchdog feature is enabled for CH[163]." bitfld.long 0x4 2. "WEN_CH162,WEN_CH162" "0: Watchdog feature is disabled for CH[162].,1: Watchdog feature is enabled for CH[162]." newline bitfld.long 0x4 1. "WEN_CH161,WEN_CH161" "0: Watchdog feature is disabled for CH[161].,1: Watchdog feature is enabled for CH[161]." bitfld.long 0x4 0. "WEN_CH160,WEN_CH160" "0: Watchdog feature is disabled for CH[160].,1: Watchdog feature is enabled for CH[160]." group.long 0x5B0++0x7 line.long 0x0 "ECAWORR0,External Channel Analog Watchdog Out of Range Register 0" bitfld.long 0x0 31. "AWOR_CH159,Analog watchdog out of range status for channel 159 provided corresponding WEN_CH159 bit is set." "0: CH[159] converted data is not out of range..,1: CH[159] converted data is out of range.." bitfld.long 0x0 30. "AWOR_CH158,Analog watchdog out of range status for channel 158 provided corresponding WEN_CH158 bit is set." "0: CH[158] converted data is not out of range..,1: CH[158] converted data is out of range.." newline bitfld.long 0x0 29. "AWOR_CH157,Analog watchdog out of range status for channel 157 provided corresponding WEN_CH157 bit is set." "0: CH[157] converted data is not out of range..,1: CH[157] converted data is out of range.." bitfld.long 0x0 28. "AWOR_CH156,Analog watchdog out of range status for channel 156 provided corresponding WEN_CH156 bit is set." "0: CH[156] converted data is not out of range..,1: CH[156] converted data is out of range.." newline bitfld.long 0x0 27. "AWOR_CH155,Analog watchdog out of range status for channel 155 provided corresponding WEN_CH155 bit is set." "0: CH[155] converted data is not out of range..,1: CH[155] converted data is out of range.." bitfld.long 0x0 26. "AWOR_CH154,Analog watchdog out of range status for channel 154 provided corresponding WEN_CH154 bit is set." "0: CH[154] converted data is not out of range..,1: CH[154] converted data is out of range.." newline bitfld.long 0x0 25. "AWOR_CH153,Analog watchdog out of range status for channel 153 provided corresponding WEN_CH153 bit is set." "0: CH[153] converted data is not out of range..,1: CH[153] converted data is out of range.." bitfld.long 0x0 24. "AWOR_CH152,Analog watchdog out of range status for channel 152 provided corresponding WEN_CH152 bit is set." "0: CH[152] converted data is not out of range..,1: CH[152] converted data is out of range.." newline bitfld.long 0x0 23. "AWOR_CH151,Analog watchdog out of range status for channel 151 provided corresponding WEN_CH151 bit is set." "0: CH[151] converted data is not out of range..,1: CH[151] converted data is out of range.." bitfld.long 0x0 22. "AWOR_CH150,Analog watchdog out of range status for channel 150 provided corresponding WEN_CH150 bit is set." "0: CH[150] converted data is not out of range..,1: CH[150] converted data is out of range.." newline bitfld.long 0x0 21. "AWOR_CH149,Analog watchdog out of range status for channel 149 provided corresponding WEN_CH149 bit is set." "0: CH[149] converted data is not out of range..,1: CH[149] converted data is out of range.." bitfld.long 0x0 20. "AWOR_CH148,Analog watchdog out of range status for channel 148 provided corresponding WEN_CH148 bit is set." "0: CH[148] converted data is not out of range..,1: CH[148] converted data is out of range.." newline bitfld.long 0x0 19. "AWOR_CH147,Analog watchdog out of range status for channel 147 provided corresponding WEN_CH147 bit is set." "0: CH[147] converted data is not out of range..,1: CH[147] converted data is out of range.." bitfld.long 0x0 18. "AWOR_CH146,Analog watchdog out of range status for channel 146 provided corresponding WEN_CH146 bit is set." "0: CH[146] converted data is not out of range..,1: CH[146] converted data is out of range.." newline bitfld.long 0x0 17. "AWOR_CH145,Analog watchdog out of range status for channel 145 provided corresponding WEN_CH145 bit is set." "0: CH[145] converted data is not out of range..,1: CH[145] converted data is out of range.." bitfld.long 0x0 16. "AWOR_CH144,Analog watchdog out of range status for channel 144 provided corresponding WEN_CH144 bit is set." "0: CH[144] converted data is not out of range..,1: CH[144] converted data is out of range.." newline bitfld.long 0x0 15. "AWOR_CH143,Analog watchdog out of range status for channel 143 provided corresponding WEN_CH143 bit is set." "0: CH[143] converted data is not out of range..,1: CH[143] converted data is out of range.." bitfld.long 0x0 14. "AWOR_CH142,Analog watchdog out of range status for channel 142 provided corresponding WEN_CH142 bit is set." "0: CH[142] converted data is not out of range..,1: CH[142] converted data is out of range.." newline bitfld.long 0x0 13. "AWOR_CH141,Analog watchdog out of range status for channel 141 provided corresponding WEN_CH141 bit is set." "0: CH[141] converted data is not out of range..,1: CH[141] converted data is out of range.." bitfld.long 0x0 12. "AWOR_CH140,Analog watchdog out of range status for channel 140 provided corresponding WEN_CH140 bit is set." "0: CH[140] converted data is not out of range..,1: CH[140] converted data is out of range.." newline bitfld.long 0x0 11. "AWOR_CH139,Analog watchdog out of range status for channel 139 provided corresponding WEN_CH139 bit is set." "0: CH[139] converted data is not out of range..,1: CH[139] converted data is out of range.." bitfld.long 0x0 10. "AWOR_CH138,Analog watchdog out of range status for channel 138 provided corresponding WEN_CH138 bit is set." "0: CH[138] converted data is not out of range..,1: CH[138] converted data is out of range.." newline bitfld.long 0x0 9. "AWOR_CH137,Analog watchdog out of range status for channel 137 provided corresponding WEN_CH137 bit is set." "0: CH[137] converted data is not out of range..,1: CH[137] converted data is out of range.." bitfld.long 0x0 8. "AWOR_CH136,Analog watchdog out of range status for channel 136 provided corresponding WEN_CH136 bit is set." "0: CH[136] converted data is not out of range..,1: CH[136] converted data is out of range.." newline bitfld.long 0x0 7. "AWOR_CH135,Analog watchdog out of range status for channel 135 provided corresponding WEN_CH135 bit is set." "0: CH[135] converted data is not out of range..,1: CH[135] converted data is out of range.." bitfld.long 0x0 6. "AWOR_CH134,Analog watchdog out of range status for channel 134 provided corresponding WEN_CH134 bit is set." "0: CH[134] converted data is not out of range..,1: CH[134] converted data is out of range.." newline bitfld.long 0x0 5. "AWOR_CH133,Analog watchdog out of range status for channel 133 provided corresponding WEN_CH133 bit is set." "0: CH[133] converted data is not out of range..,1: CH[133] converted data is out of range.." bitfld.long 0x0 4. "AWOR_CH132,Analog watchdog out of range status for channel 132 provided corresponding WEN_CH132 bit is set." "0: CH[132] converted data is not out of range..,1: CH[132] converted data is out of range.." newline bitfld.long 0x0 3. "AWOR_CH131,Analog watchdog out of range status for channel 131 provided corresponding WEN_CH131 bit is set." "0: CH[131] converted data is not out of range..,1: CH[131] converted data is out of range.." bitfld.long 0x0 2. "AWOR_CH130,Analog watchdog out of range status for channel 130 provided corresponding WEN_CH130 bit is set." "0: CH[130] converted data is not out of range..,1: CH[130] converted data is out of range.." newline bitfld.long 0x0 1. "AWOR_CH129,Analog watchdog out of range status for channel 129 provided corresponding WEN_CH129 bit is set." "0: CH[129] converted data is not out of range..,1: CH[129] converted data is out of range.." bitfld.long 0x0 0. "AWOR_CH128,Analog watchdog out of range status for channel 128 provided corresponding WEN_CH128 bit is set." "0: CH[128] converted data is not out of range..,1: CH[128] converted data is out of range.." line.long 0x4 "ECAWORR1,External Channel Analog Watchdog Out of Range Register 1" bitfld.long 0x4 31. "AWOR_CH191,Analog watchdog out of range status for channel 191 provided corresponding WEN_CH191 bit is set." "0: CH[191] converted data is not out of range..,1: CH[191] converted data is out of range.." bitfld.long 0x4 30. "AWOR_CH190,Analog watchdog out of range status for channel 190 provided corresponding WEN_CH190 bit is set." "0: CH[190] converted data is not out of range..,1: CH[190] converted data is out of range.." newline bitfld.long 0x4 29. "AWOR_CH189,Analog watchdog out of range status for channel 189 provided corresponding WEN_CH189 bit is set." "0: CH[189] converted data is not out of range..,1: CH[189] converted data is out of range.." bitfld.long 0x4 28. "AWOR_CH188,Analog watchdog out of range status for channel 188 provided corresponding WEN_CH188 bit is set." "0: CH[188] converted data is not out of range..,1: CH[188] converted data is out of range.." newline bitfld.long 0x4 27. "AWOR_CH187,Analog watchdog out of range status for channel 187 provided corresponding WEN_CH187 bit is set." "0: CH[187] converted data is not out of range..,1: CH[187] converted data is out of range.." bitfld.long 0x4 26. "AWOR_CH186,Analog watchdog out of range status for channel 186 provided corresponding WEN_CH186 bit is set." "0: CH[186] converted data is not out of range..,1: CH[186] converted data is out of range.." newline bitfld.long 0x4 25. "AWOR_CH185,Analog watchdog out of range status for channel 185 provided corresponding WEN_CH185 bit is set." "0: CH[185] converted data is not out of range..,1: CH[185] converted data is out of range.." bitfld.long 0x4 24. "AWOR_CH184,Analog watchdog out of range status for channel 184 provided corresponding WEN_CH184 bit is set." "0: CH[184] converted data is not out of range..,1: CH[184] converted data is out of range.." newline bitfld.long 0x4 23. "AWOR_CH183,Analog watchdog out of range status for channel 183 provided corresponding WEN_CH183 bit is set." "0: CH[183] converted data is not out of range..,1: CH[183] converted data is out of range.." bitfld.long 0x4 22. "AWOR_CH182,Analog watchdog out of range status for channel 182 provided corresponding WEN_CH182 bit is set." "0: CH[182] converted data is not out of range..,1: CH[182] converted data is out of range.." newline bitfld.long 0x4 21. "AWOR_CH181,Analog watchdog out of range status for channel 181 provided corresponding WEN_CH181 bit is set." "0: CH[181] converted data is not out of range..,1: CH[181] converted data is out of range.." bitfld.long 0x4 20. "AWOR_CH180,Analog watchdog out of range status for channel 180 provided corresponding WEN_CH180 bit is set." "0: CH[180] converted data is not out of range..,1: CH[180] converted data is out of range.." newline bitfld.long 0x4 19. "AWOR_CH179,Analog watchdog out of range status for channel 179 provided corresponding WEN_CH179 bit is set." "0: CH[179] converted data is not out of range..,1: CH[179] converted data is out of range.." bitfld.long 0x4 18. "AWOR_CH178,Analog watchdog out of range status for channel 178 provided corresponding WEN_CH178 bit is set." "0: CH[178] converted data is not out of range..,1: CH[178] converted data is out of range.." newline bitfld.long 0x4 17. "AWOR_CH177,Analog watchdog out of range status for channel 177 provided corresponding WEN_CH177 bit is set." "0: CH[177] converted data is not out of range..,1: CH[177] converted data is out of range.." bitfld.long 0x4 16. "AWOR_CH176,Analog watchdog out of range status for channel 176 provided corresponding WEN_CH176 bit is set." "0: CH[176] converted data is not out of range..,1: CH[176] converted data is out of range.." newline bitfld.long 0x4 15. "AWOR_CH175,Analog watchdog out of range status for channel 175 provided corresponding WEN_CH175 bit is set." "0: CH[175] converted data is not out of range..,1: CH[175] converted data is out of range.." bitfld.long 0x4 14. "AWOR_CH174,Analog watchdog out of range status for channel 174 provided corresponding WEN_CH174 bit is set." "0: CH[174] converted data is not out of range..,1: CH[174] converted data is out of range.." newline bitfld.long 0x4 13. "AWOR_CH173,Analog watchdog out of range status for channel 173 provided corresponding WEN_CH173 bit is set." "0: CH[173] converted data is not out of range..,1: CH[173] converted data is out of range.." bitfld.long 0x4 12. "AWOR_CH172,Analog watchdog out of range status for channel 172 provided corresponding WEN_CH172 bit is set." "0: CH[172] converted data is not out of range..,1: CH[172] converted data is out of range.." newline bitfld.long 0x4 11. "AWOR_CH171,Analog watchdog out of range status for channel 171 provided corresponding WEN_CH171 bit is set." "0: CH[171] converted data is not out of range..,1: CH[171] converted data is out of range.." bitfld.long 0x4 10. "AWOR_CH170,Analog watchdog out of range status for channel 170 provided corresponding WEN_CH170 bit is set." "0: CH[170] converted data is not out of range..,1: CH[170] converted data is out of range.." newline bitfld.long 0x4 9. "AWOR_CH169,Analog watchdog out of range status for channel 169 provided corresponding WEN_CH169 bit is set." "0: CH[169] converted data is not out of range..,1: CH[169] converted data is out of range.." bitfld.long 0x4 8. "AWOR_CH168,Analog watchdog out of range status for channel 168 provided corresponding WEN_CH168 bit is set." "0: CH[168] converted data is not out of range..,1: CH[168] converted data is out of range.." newline bitfld.long 0x4 7. "AWOR_CH167,Analog watchdog out of range status for channel 167 provided corresponding WEN_CH167 bit is set." "0: CH[167] converted data is not out of range..,1: CH[167] converted data is out of range.." bitfld.long 0x4 6. "AWOR_CH166,Analog watchdog out of range status for channel 166 provided corresponding WEN_CH166 bit is set." "0: CH[166] converted data is not out of range..,1: CH[166] converted data is out of range.." newline bitfld.long 0x4 5. "AWOR_CH165,Analog watchdog out of range status for channel 165 provided corresponding WEN_CH165 bit is set." "0: CH[165] converted data is not out of range..,1: CH[165] converted data is out of range.." bitfld.long 0x4 4. "AWOR_CH164,Analog watchdog out of range status for channel 164 provided corresponding WEN_CH164 bit is set." "0: CH[164] converted data is not out of range..,1: CH[164] converted data is out of range.." newline bitfld.long 0x4 3. "AWOR_CH163,Analog watchdog out of range status for channel 163 provided corresponding WEN_CH163 bit is set." "0: CH[163] converted data is not out of range..,1: CH[163] converted data is out of range.." bitfld.long 0x4 2. "AWOR_CH162,Analog watchdog out of range status for channel 162 provided corresponding WEN_CH162 bit is set." "0: CH[162] converted data is not out of range..,1: CH[162] converted data is out of range.." newline bitfld.long 0x4 1. "AWOR_CH161,Analog watchdog out of range status for channel 161 provided corresponding WEN_CH161 bit is set." "0: CH[161] converted data is not out of range..,1: CH[161] converted data is out of range.." bitfld.long 0x4 0. "AWOR_CH160,Analog watchdog out of range status for channel 160 provided corresponding WEN_CH160 bit is set." "0: CH[160] converted data is not out of range..,1: CH[160] converted data is out of range.." group.long 0x5C0++0x7 line.long 0x0 "ECMICR0,External Channel Mapping to Internal Channel Register 0" hexmask.long.byte 0x0 24.--30. 1. "ICSEL_ECH152_159,Internal channel selection for external channels (128 + 8x) to (135+8*x) where x = 0 1 2..15" hexmask.long.byte 0x0 16.--22. 1. "ICSEL_ECH144_151,Internal channel selection for external channels (128 + 8x) to (135+8*x) where x = 0 1 2..15" newline hexmask.long.byte 0x0 8.--14. 1. "ICSEL_ECH136_143,Internal channel selection for external channels (128 + 8x) to (135+8*x) where x = 0 1 2..15" hexmask.long.byte 0x0 0.--6. 1. "ICSEL_ECH128_135,Internal channel selection for external channels (128 + 8x) to (135+8*x) where x = 0 1 2..15" line.long 0x4 "ECMICR1,External Channel Mapping to Internal Channel Register 1" hexmask.long.byte 0x4 24.--30. 1. "ICSEL_ECH184_191,Internal channel selection for external channels (128 + 8x) to (135+8*x) where x = 0 1 2..15" hexmask.long.byte 0x4 16.--22. 1. "ICSEL_ECH176_183,Internal channel selection for external channels (128 + 8x) to (135+8*x) where x = 0 1 2..15" newline hexmask.long.byte 0x4 8.--14. 1. "ICSEL_ECH168_175,Internal channel selection for external channels (128 + 8x) to (135+8*x) where x = 0 1 2..15" hexmask.long.byte 0x4 0.--6. 1. "ICSEL_ECH160_167,Internal channel selection for external channels (128 + 8x) to (135+8*x) where x = 0 1 2..15" group.long 0x5D0++0xFF line.long 0x0 "ECDR128,External Channel Data Register 128" bitfld.long 0x0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x4 "ECDR129,External Channel Data Register 129" bitfld.long 0x4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x8 "ECDR130,External Channel Data Register 130" bitfld.long 0x8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xC "ECDR131,External Channel Data Register 131" bitfld.long 0xC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x10 "ECDR132,External Channel Data Register 132" bitfld.long 0x10 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x10 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x10 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x10 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x10 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x10 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x10 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x14 "ECDR133,External Channel Data Register 133" bitfld.long 0x14 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x14 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x14 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x14 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x14 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x14 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x14 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x18 "ECDR134,External Channel Data Register 134" bitfld.long 0x18 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x18 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x18 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x18 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x18 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x18 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x18 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x1C "ECDR135,External Channel Data Register 135" bitfld.long 0x1C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x1C 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x1C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x1C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x1C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x1C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x1C 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x20 "ECDR136,External Channel Data Register 136" bitfld.long 0x20 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x20 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x20 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x20 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x20 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x20 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x20 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x24 "ECDR137,External Channel Data Register 137" bitfld.long 0x24 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x24 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x24 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x24 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x24 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x24 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x24 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x28 "ECDR138,External Channel Data Register 138" bitfld.long 0x28 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x28 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x28 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x28 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x28 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x28 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x28 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x2C "ECDR139,External Channel Data Register 139" bitfld.long 0x2C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x2C 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x2C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x2C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x2C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x2C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x2C 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x30 "ECDR140,External Channel Data Register 140" bitfld.long 0x30 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x30 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x30 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x30 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x30 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x30 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x30 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x34 "ECDR141,External Channel Data Register 141" bitfld.long 0x34 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x34 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x34 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x34 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x34 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x34 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x34 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x38 "ECDR142,External Channel Data Register 142" bitfld.long 0x38 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x38 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x38 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x38 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x38 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x38 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x38 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x3C "ECDR143,External Channel Data Register 143" bitfld.long 0x3C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x3C 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x3C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x3C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x3C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x3C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x3C 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x40 "ECDR144,External Channel Data Register 144" bitfld.long 0x40 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x40 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x40 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x40 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x40 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x40 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x40 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x44 "ECDR145,External Channel Data Register 145" bitfld.long 0x44 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x44 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x44 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x44 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x44 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x44 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x44 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x48 "ECDR146,External Channel Data Register 146" bitfld.long 0x48 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x48 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x48 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x48 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x48 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x48 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x48 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x4C "ECDR147,External Channel Data Register 147" bitfld.long 0x4C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x4C 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x4C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x4C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x4C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x4C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x4C 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x50 "ECDR148,External Channel Data Register 148" bitfld.long 0x50 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x50 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x50 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x50 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x50 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x50 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x50 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x54 "ECDR149,External Channel Data Register 149" bitfld.long 0x54 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x54 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x54 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x54 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x54 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x54 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x54 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x58 "ECDR150,External Channel Data Register 150" bitfld.long 0x58 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x58 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x58 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x58 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x58 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x58 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x58 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x5C "ECDR151,External Channel Data Register 151" bitfld.long 0x5C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x5C 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x5C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x5C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x5C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x5C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x5C 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x60 "ECDR152,External Channel Data Register 152" bitfld.long 0x60 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x60 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x60 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x60 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x60 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x60 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x60 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x64 "ECDR153,External Channel Data Register 153" bitfld.long 0x64 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x64 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x64 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x64 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x64 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x64 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x64 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x68 "ECDR154,External Channel Data Register 154" bitfld.long 0x68 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x68 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x68 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x68 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x68 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x68 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x68 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x6C "ECDR155,External Channel Data Register 155" bitfld.long 0x6C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x6C 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x6C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x6C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x6C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x6C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x6C 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x70 "ECDR156,External Channel Data Register 156" bitfld.long 0x70 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x70 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x70 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x70 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x70 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x70 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x70 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x74 "ECDR157,External Channel Data Register 157" bitfld.long 0x74 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x74 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x74 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x74 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x74 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x74 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x74 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x78 "ECDR158,External Channel Data Register 158" bitfld.long 0x78 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x78 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x78 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x78 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x78 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x78 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x78 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x7C "ECDR159,External Channel Data Register 159" bitfld.long 0x7C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x7C 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x7C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x7C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x7C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x7C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x7C 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x80 "ECDR160,External Channel Data Register 160" bitfld.long 0x80 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x80 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x80 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x80 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x80 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x80 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x80 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x84 "ECDR161,External Channel Data Register 161" bitfld.long 0x84 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x84 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x84 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x84 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x84 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x84 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x84 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x88 "ECDR162,External Channel Data Register 162" bitfld.long 0x88 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x88 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x88 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x88 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x88 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x88 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x88 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x8C "ECDR163,External Channel Data Register 163" bitfld.long 0x8C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x8C 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x8C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x8C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x8C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x8C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x8C 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x90 "ECDR164,External Channel Data Register 164" bitfld.long 0x90 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x90 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x90 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x90 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x90 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x90 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x90 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x94 "ECDR165,External Channel Data Register 165" bitfld.long 0x94 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x94 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x94 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x94 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x94 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x94 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x94 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x98 "ECDR166,External Channel Data Register 166" bitfld.long 0x98 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x98 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x98 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x98 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x98 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x98 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x98 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0x9C "ECDR167,External Channel Data Register 167" bitfld.long 0x9C 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0x9C 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0x9C 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0x9C 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0x9C 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0x9C 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0x9C 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xA0 "ECDR168,External Channel Data Register 168" bitfld.long 0xA0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xA0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xA0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xA0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xA0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xA0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xA0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xA4 "ECDR169,External Channel Data Register 169" bitfld.long 0xA4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xA4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xA4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xA4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xA4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xA4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xA4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xA8 "ECDR170,External Channel Data Register 170" bitfld.long 0xA8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xA8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xA8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xA8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xA8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xA8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xA8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xAC "ECDR171,External Channel Data Register 171" bitfld.long 0xAC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xAC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xAC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xAC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xAC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xAC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xAC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xB0 "ECDR172,External Channel Data Register 172" bitfld.long 0xB0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xB0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xB0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xB0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xB0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xB0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xB0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xB4 "ECDR173,External Channel Data Register 173" bitfld.long 0xB4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xB4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xB4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xB4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xB4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xB4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xB4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xB8 "ECDR174,External Channel Data Register 174" bitfld.long 0xB8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xB8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xB8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xB8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xB8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xB8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xB8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xBC "ECDR175,External Channel Data Register 175" bitfld.long 0xBC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xBC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xBC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xBC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xBC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xBC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xBC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xC0 "ECDR176,External Channel Data Register 176" bitfld.long 0xC0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xC0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xC0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xC0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xC0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xC4 "ECDR177,External Channel Data Register 177" bitfld.long 0xC4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xC4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xC4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xC4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xC4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xC8 "ECDR178,External Channel Data Register 178" bitfld.long 0xC8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xC8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xC8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xC8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xC8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xC8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xC8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xCC "ECDR179,External Channel Data Register 179" bitfld.long 0xCC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xCC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xCC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xCC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xCC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xCC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xCC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xD0 "ECDR180,External Channel Data Register 180" bitfld.long 0xD0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xD0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xD0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xD0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xD0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xD0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xD0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xD4 "ECDR181,External Channel Data Register 181" bitfld.long 0xD4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xD4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xD4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xD4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xD4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xD4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xD4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xD8 "ECDR182,External Channel Data Register 182" bitfld.long 0xD8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xD8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xD8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xD8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xD8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xD8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xD8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xDC "ECDR183,External Channel Data Register 183" bitfld.long 0xDC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xDC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xDC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xDC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xDC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xDC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xDC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xE0 "ECDR184,External Channel Data Register 184" bitfld.long 0xE0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xE0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xE0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xE0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xE0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xE0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xE0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xE4 "ECDR185,External Channel Data Register 185" bitfld.long 0xE4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xE4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xE4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xE4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xE4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xE4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xE4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xE8 "ECDR186,External Channel Data Register 186" bitfld.long 0xE8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xE8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xE8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xE8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xE8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xE8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xE8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xEC "ECDR187,External Channel Data Register 187" bitfld.long 0xEC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xEC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xEC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xEC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xEC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xEC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xEC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xF0 "ECDR188,External Channel Data Register 188" bitfld.long 0xF0 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xF0 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xF0 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xF0 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xF0 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xF0 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xF0 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xF4 "ECDR189,External Channel Data Register 189" bitfld.long 0xF4 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xF4 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xF4 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xF4 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xF4 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xF4 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xF4 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xF8 "ECDR190,External Channel Data Register 190" bitfld.long 0xF8 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xF8 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xF8 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xF8 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xF8 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xF8 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xF8 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." line.long 0xFC "ECDR191,External Channel Data Register 191" bitfld.long 0xFC 27. "PCE,This bit enables the precharging phase during channel conversion." "0: Precharge phase is disabled,1: Precharge phase is enabled" bitfld.long 0xFC 24.--25. "CTSEL,This bit field selects the conversion timing register for each channel to select different precharge and sampling phase durations." "0: CTR0 is selected,1: CTR1 is selected,2: CTR2 is selected,3: CTR3 is selected" newline bitfld.long 0xFC 20. "FCERR,This bit is used to notify error condition on current fast comparator operation inside ADC analog block. It is automatically cleared when data is read." "0: Cleared by reading the Converted by software.,1: Fast Comparator Error Condition has occured in.." bitfld.long 0xFC 19. "VALID,This bit is used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read." "0: Converted data has been read by software.,1: Converted data is valid and has not been read yet." newline bitfld.long 0xFC 18. "OVERW,This bit signals that the previous converted data has been overwritten by a new conversion." "0: Converted data has not been overwritten,1: Previous converted data has been overwritten.." bitfld.long 0xFC 16.--17. "RESULT,This bit reflects the mode of conversion for the corresponding channel." "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" newline hexmask.long.word 0xFC 0.--15. 1. "CDATA,Note: If MCR[WLSIDE] is set to ‘0’ than the converted data is read right aligned with lower 12/10 bits representing the actual converted data(width of actual converted data depends on selected resolution of current conversion selectable by.." tree.end tree.end tree "SAR_ADCQ (Queued SARADC Digital Subsystem)" base ad:0x0 tree "SAR_ADCQ_12BIT_0" base ad:0x70328000 group.long 0x0++0x7 line.long 0x0 "GLBL_Q_SETUP,Global Setup register" bitfld.long 0x0 1. "DEBUG_EN,Debug Enable" "0: ADCQ in normal mode. No saving of FIFO pointers..,1: ADCQ in debug mode. Operation is frozen after.." newline bitfld.long 0x0 0. "SUSP_MODE,Suspension Mode" "0: The current cmd in active sequence is aborted..,1: The current cmd in active sequence is allowed to.." line.long 0x4 "GLBL_Q_CTRL,Global Control Register" bitfld.long 0x4 29. "Q1_DATAQ_DMA_ENABLE,Queue1 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 28. "Q0_DATAQ_DMA_ENABLE,Queue0 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 25. "Q1_CMDQ_DMA_ENABLE,Queue1 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 24. "Q0_CMDQ_DMA_ENABLE,Queue0 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 17. "Q1_RESET_CNTRS,Reset Queue1 Counters" "0,1" newline bitfld.long 0x4 16. "Q0_RESET_CNTRS,Reset Queue0 Counters" "0,1" newline bitfld.long 0x4 13. "Q1_ABORT,Abort Queue1" "0,1" newline bitfld.long 0x4 12. "Q0_ABORT,Abort Queue0" "0,1" newline bitfld.long 0x4 9. "Q1_FLUSH,Flush Queue1" "0,1" newline bitfld.long 0x4 8. "Q0_FLUSH,Flush Queue0" "0,1" newline bitfld.long 0x4 5. "Q1_SW_TRIG,Queue1 Software Trigger" "0,1" newline bitfld.long 0x4 4. "Q0_SW_TRIG,Queue0 Software Trigger" "0,1" newline bitfld.long 0x4 1. "Q1_TRIG_EN,Queue1 Trigger Enable" "0,1" newline bitfld.long 0x4 0. "Q0_TRIG_EN,Queue0 Trigger Enable" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "GLBL_Q_STATUS,Global Status register" hexmask.long.byte 0x0 8.--11. 1. "Q1_STATUS,These fields show the current state of the Queue1." newline hexmask.long.byte 0x0 0.--3. 1. "Q0_STATUS,These fields show the current state of the Queue0." group.long 0xC++0x3 line.long 0x0 "GLBL_IRQ_CTRL,Global IRQ Control register" bitfld.long 0x0 15. "XB_ERR_IRQ_EN,ADCXBAR Error Interrupt Enable" "0,1" newline bitfld.long 0x0 3. "Q1_ERR_IRQ_EN,Queue1 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "Q1_STAT_IRQ_EN,Queue1 Status Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "Q0_ERR_IRQ_EN,Queue0 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "Q0_STAT_IRQ_EN,Queue0 Status Interrupt Enable" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "GLBL_IRQ_STATUS,Global IRQ Status register" bitfld.long 0x0 15. "XB_ERR_IRQ,ADCXBAR Error Interrupt state" "0: ADCXBAR interrupt is not asserted.,1: ADCXBAR interrupt is asserted." newline bitfld.long 0x0 3. "Q1_ERR_IRQ,Queue1 Error Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 2. "Q1_STAT_IRQ,Queue1 Status Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 1. "Q0_ERR_IRQ,Queue0 Error Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." newline bitfld.long 0x0 0. "Q0_STAT_IRQ,Queue0 Status Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." group.long 0x14++0x3 line.long 0x0 "GLBL_OUTPUT,Global Output register" bitfld.long 0x0 4. "GLOBAL_OUT_Q_RST_CNTRS,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 3. "GLOBAL_OUT_Q_FLUSH,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 2. "GLOBAL_OUT_Q_ABORT,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 1. "GLOBAL_OUT_Q_SW_TRIG,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 0. "GLOBAL_OUT_Q_TRIG_EN,Whatever is written to this bit is reflected on the corresponding output pin. This can be used to provide a reset queue counters command to all participating queues across the ADCQs. Each queue can participate in this global.." "0,1" rgroup.long 0x18++0x7 line.long 0x0 "GLBL_CONFIG,Global Configuration register" hexmask.long.byte 0x0 8.--13. 1. "NUM_OF_TRIG_IN,Number of Input HW Triggers" newline bitfld.long 0x0 0.--2. "NUM_OF_QUEUES,Number of Queues" "?,1: Q0 queue supported,2: Q0 and Q1 supported,3: Q0 Q1 and Q2 supported,4: Q0 Q1 Q2 Q3 supported,?,?,?" line.long 0x4 "GLBL_ADC_IF_STATUS,Global ADC Interface Status register" hexmask.long.byte 0x4 20.--23. 1. "SUSPENDED_Q_NUM,Suspended Queues" newline hexmask.long.byte 0x4 8.--15. 1. "ACTIVE_ADC_CH_NUM,Current ADC CH Number" newline hexmask.long.byte 0x4 4.--7. 1. "ACTIVE_Q_NUM,Current Queue number" newline bitfld.long 0x4 0. "ADC_IF_BUSY,ADC Interface Busy" "0,1" group.long 0x20++0xB line.long 0x0 "GLBL_Q_MEAS_TIMER,Global Queue Measurement Timer register" hexmask.long.word 0x0 16.--31. 1. "DELTA_TMR_CURR_VAL,Current Value of ?T Counter" newline hexmask.long.word 0x0 0.--15. 1. "DELTA_TMR_RELOAD_VAL,Reload Value of ?T Counter" line.long 0x4 "GLBL_ADC_CNV_TIMEOUT,Global ADC Conversion Timeout register" hexmask.long.word 0x4 16.--31. 1. "ADC_CNV_CURR_VAL,Current value of timeout counter" newline hexmask.long.word 0x4 0.--15. 1. "ADC_CNV_RELOAD_VAL,Reload value of timeout counter" line.long 0x8 "GLBL_DMA_ID,Global DMA ID register" bitfld.long 0x8 31. "MID3_EN,Enable Master ID 3" "0,1" newline hexmask.long.byte 0x8 24.--30. 1. "MID3,Master ID 3" newline bitfld.long 0x8 23. "MID2_EN,Enable Master ID 2" "0,1" newline hexmask.long.byte 0x8 16.--22. 1. "MID2,Master ID 2" newline bitfld.long 0x8 15. "MID1_EN,Enable Master ID 1" "0,1" newline hexmask.long.byte 0x8 8.--14. 1. "MID1,Master ID 1" newline bitfld.long 0x8 7. "MID0_EN,Enable Master ID 0" "0,1" newline hexmask.long.byte 0x8 0.--6. 1. "MID0,Master ID 0" rgroup.long 0x30++0x3 line.long 0x0 "GLBL_HW_VER,Global Hardware Version register" hexmask.long 0x0 0.--31. 1. "NUM,Hardware Version Number" group.long 0x80++0xB line.long 0x0 "XB_Q_PRIORITY,ADCXBAR Queue Priority Assignment register" bitfld.long 0x0 4.--5. "Q1_PRIO_NUM,Queue1 Priority Number" "0,1,2,3" newline bitfld.long 0x0 0.--1. "Q0_PRIO_NUM,Queue0 Priority Number" "0,1,2,3" line.long 0x4 "XB_IRQ_CTRL,ADCXBAR Interrupt Control register" bitfld.long 0x4 0. "ADC_CNV_TO_ERR_IRQ_EN,ADC Conversion Timeout Error Interrupt Enable" "0,1" line.long 0x8 "XB_IRQ_STATUS,ADCXBAR Interrupt Status register" bitfld.long 0x8 0. "ADC_CNV_TO_ERR,ADC Conversion Timeout Error" "0,1" group.long 0x800++0xB line.long 0x0 "Q0_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 30. "AUX_ITF_SEL,Select Auxiliary Interface" "0,1" newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q0_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q0_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x80C++0x3 line.long 0x0 "Q0_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x810++0x3 line.long 0x0 "Q0_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x814++0x3 line.long 0x0 "Q0_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x818++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q0_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x820++0xF line.long 0x0 "Q0_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q0_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q0_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q0_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x830++0x3 line.long 0x0 "Q0_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x840++0x3 line.long 0x0 "Q0_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x860++0x3 line.long 0x0 "Q0_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" group.long 0x1000++0xB line.long 0x0 "Q1_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q1_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q1_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x100C++0x3 line.long 0x0 "Q1_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x1010++0x3 line.long 0x0 "Q1_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x1014++0x3 line.long 0x0 "Q1_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x1018++0x7 line.long 0x0 "Q1_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q1_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x1020++0xF line.long 0x0 "Q1_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q1_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q1_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q1_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x1030++0x3 line.long 0x0 "Q1_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x1040++0x3 line.long 0x0 "Q1_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x1060++0x3 line.long 0x0 "Q1_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" tree.end tree "SAR_ADCQ_12BIT_1" base ad:0x70928000 group.long 0x0++0x7 line.long 0x0 "GLBL_Q_SETUP,Global Setup register" bitfld.long 0x0 1. "DEBUG_EN,Debug Enable" "0: ADCQ in normal mode. No saving of FIFO pointers..,1: ADCQ in debug mode. Operation is frozen after.." newline bitfld.long 0x0 0. "SUSP_MODE,Suspension Mode" "0: The current cmd in active sequence is aborted..,1: The current cmd in active sequence is allowed to.." line.long 0x4 "GLBL_Q_CTRL,Global Control Register" bitfld.long 0x4 29. "Q1_DATAQ_DMA_ENABLE,Queue1 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 28. "Q0_DATAQ_DMA_ENABLE,Queue0 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 25. "Q1_CMDQ_DMA_ENABLE,Queue1 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 24. "Q0_CMDQ_DMA_ENABLE,Queue0 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 17. "Q1_RESET_CNTRS,Reset Queue1 Counters" "0,1" newline bitfld.long 0x4 16. "Q0_RESET_CNTRS,Reset Queue0 Counters" "0,1" newline bitfld.long 0x4 13. "Q1_ABORT,Abort Queue1" "0,1" newline bitfld.long 0x4 12. "Q0_ABORT,Abort Queue0" "0,1" newline bitfld.long 0x4 9. "Q1_FLUSH,Flush Queue1" "0,1" newline bitfld.long 0x4 8. "Q0_FLUSH,Flush Queue0" "0,1" newline bitfld.long 0x4 5. "Q1_SW_TRIG,Queue1 Software Trigger" "0,1" newline bitfld.long 0x4 4. "Q0_SW_TRIG,Queue0 Software Trigger" "0,1" newline bitfld.long 0x4 1. "Q1_TRIG_EN,Queue1 Trigger Enable" "0,1" newline bitfld.long 0x4 0. "Q0_TRIG_EN,Queue0 Trigger Enable" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "GLBL_Q_STATUS,Global Status register" hexmask.long.byte 0x0 8.--11. 1. "Q1_STATUS,These fields show the current state of the Queue1." newline hexmask.long.byte 0x0 0.--3. 1. "Q0_STATUS,These fields show the current state of the Queue0." group.long 0xC++0x3 line.long 0x0 "GLBL_IRQ_CTRL,Global IRQ Control register" bitfld.long 0x0 15. "XB_ERR_IRQ_EN,ADCXBAR Error Interrupt Enable" "0,1" newline bitfld.long 0x0 3. "Q1_ERR_IRQ_EN,Queue1 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "Q1_STAT_IRQ_EN,Queue1 Status Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "Q0_ERR_IRQ_EN,Queue0 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "Q0_STAT_IRQ_EN,Queue0 Status Interrupt Enable" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "GLBL_IRQ_STATUS,Global IRQ Status register" bitfld.long 0x0 15. "XB_ERR_IRQ,ADCXBAR Error Interrupt state" "0: ADCXBAR interrupt is not asserted.,1: ADCXBAR interrupt is asserted." newline bitfld.long 0x0 3. "Q1_ERR_IRQ,Queue1 Error Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 2. "Q1_STAT_IRQ,Queue1 Status Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 1. "Q0_ERR_IRQ,Queue0 Error Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." newline bitfld.long 0x0 0. "Q0_STAT_IRQ,Queue0 Status Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." group.long 0x14++0x3 line.long 0x0 "GLBL_OUTPUT,Global Output register" bitfld.long 0x0 4. "GLOBAL_OUT_Q_RST_CNTRS,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 3. "GLOBAL_OUT_Q_FLUSH,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 2. "GLOBAL_OUT_Q_ABORT,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 1. "GLOBAL_OUT_Q_SW_TRIG,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 0. "GLOBAL_OUT_Q_TRIG_EN,Whatever is written to this bit is reflected on the corresponding output pin. This can be used to provide a reset queue counters command to all participating queues across the ADCQs. Each queue can participate in this global.." "0,1" rgroup.long 0x18++0x7 line.long 0x0 "GLBL_CONFIG,Global Configuration register" hexmask.long.byte 0x0 8.--13. 1. "NUM_OF_TRIG_IN,Number of Input HW Triggers" newline bitfld.long 0x0 0.--2. "NUM_OF_QUEUES,Number of Queues" "?,1: Q0 queue supported,2: Q0 and Q1 supported,3: Q0 Q1 and Q2 supported,4: Q0 Q1 Q2 Q3 supported,?,?,?" line.long 0x4 "GLBL_ADC_IF_STATUS,Global ADC Interface Status register" hexmask.long.byte 0x4 20.--23. 1. "SUSPENDED_Q_NUM,Suspended Queues" newline hexmask.long.byte 0x4 8.--15. 1. "ACTIVE_ADC_CH_NUM,Current ADC CH Number" newline hexmask.long.byte 0x4 4.--7. 1. "ACTIVE_Q_NUM,Current Queue number" newline bitfld.long 0x4 0. "ADC_IF_BUSY,ADC Interface Busy" "0,1" group.long 0x20++0xB line.long 0x0 "GLBL_Q_MEAS_TIMER,Global Queue Measurement Timer register" hexmask.long.word 0x0 16.--31. 1. "DELTA_TMR_CURR_VAL,Current Value of ?T Counter" newline hexmask.long.word 0x0 0.--15. 1. "DELTA_TMR_RELOAD_VAL,Reload Value of ?T Counter" line.long 0x4 "GLBL_ADC_CNV_TIMEOUT,Global ADC Conversion Timeout register" hexmask.long.word 0x4 16.--31. 1. "ADC_CNV_CURR_VAL,Current value of timeout counter" newline hexmask.long.word 0x4 0.--15. 1. "ADC_CNV_RELOAD_VAL,Reload value of timeout counter" line.long 0x8 "GLBL_DMA_ID,Global DMA ID register" bitfld.long 0x8 31. "MID3_EN,Enable Master ID 3" "0,1" newline hexmask.long.byte 0x8 24.--30. 1. "MID3,Master ID 3" newline bitfld.long 0x8 23. "MID2_EN,Enable Master ID 2" "0,1" newline hexmask.long.byte 0x8 16.--22. 1. "MID2,Master ID 2" newline bitfld.long 0x8 15. "MID1_EN,Enable Master ID 1" "0,1" newline hexmask.long.byte 0x8 8.--14. 1. "MID1,Master ID 1" newline bitfld.long 0x8 7. "MID0_EN,Enable Master ID 0" "0,1" newline hexmask.long.byte 0x8 0.--6. 1. "MID0,Master ID 0" rgroup.long 0x30++0x3 line.long 0x0 "GLBL_HW_VER,Global Hardware Version register" hexmask.long 0x0 0.--31. 1. "NUM,Hardware Version Number" group.long 0x80++0xB line.long 0x0 "XB_Q_PRIORITY,ADCXBAR Queue Priority Assignment register" bitfld.long 0x0 4.--5. "Q1_PRIO_NUM,Queue1 Priority Number" "0,1,2,3" newline bitfld.long 0x0 0.--1. "Q0_PRIO_NUM,Queue0 Priority Number" "0,1,2,3" line.long 0x4 "XB_IRQ_CTRL,ADCXBAR Interrupt Control register" bitfld.long 0x4 0. "ADC_CNV_TO_ERR_IRQ_EN,ADC Conversion Timeout Error Interrupt Enable" "0,1" line.long 0x8 "XB_IRQ_STATUS,ADCXBAR Interrupt Status register" bitfld.long 0x8 0. "ADC_CNV_TO_ERR,ADC Conversion Timeout Error" "0,1" group.long 0x800++0xB line.long 0x0 "Q0_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 30. "AUX_ITF_SEL,Select Auxiliary Interface" "0,1" newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q0_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q0_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x80C++0x3 line.long 0x0 "Q0_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x810++0x3 line.long 0x0 "Q0_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x814++0x3 line.long 0x0 "Q0_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x818++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q0_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x820++0xF line.long 0x0 "Q0_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q0_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q0_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q0_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x830++0x3 line.long 0x0 "Q0_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x840++0x3 line.long 0x0 "Q0_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x860++0x3 line.long 0x0 "Q0_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" group.long 0x1000++0xB line.long 0x0 "Q1_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q1_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q1_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x100C++0x3 line.long 0x0 "Q1_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x1010++0x3 line.long 0x0 "Q1_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x1014++0x3 line.long 0x0 "Q1_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x1018++0x7 line.long 0x0 "Q1_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q1_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x1020++0xF line.long 0x0 "Q1_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q1_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q1_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q1_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x1030++0x3 line.long 0x0 "Q1_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x1040++0x3 line.long 0x0 "Q1_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x1060++0x3 line.long 0x0 "Q1_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" tree.end tree "SAR_ADCQ_12BIT_2" base ad:0x7032C000 group.long 0x0++0x7 line.long 0x0 "GLBL_Q_SETUP,Global Setup register" bitfld.long 0x0 1. "DEBUG_EN,Debug Enable" "0: ADCQ in normal mode. No saving of FIFO pointers..,1: ADCQ in debug mode. Operation is frozen after.." newline bitfld.long 0x0 0. "SUSP_MODE,Suspension Mode" "0: The current cmd in active sequence is aborted..,1: The current cmd in active sequence is allowed to.." line.long 0x4 "GLBL_Q_CTRL,Global Control Register" bitfld.long 0x4 29. "Q1_DATAQ_DMA_ENABLE,Queue1 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 28. "Q0_DATAQ_DMA_ENABLE,Queue0 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 25. "Q1_CMDQ_DMA_ENABLE,Queue1 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 24. "Q0_CMDQ_DMA_ENABLE,Queue0 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 17. "Q1_RESET_CNTRS,Reset Queue1 Counters" "0,1" newline bitfld.long 0x4 16. "Q0_RESET_CNTRS,Reset Queue0 Counters" "0,1" newline bitfld.long 0x4 13. "Q1_ABORT,Abort Queue1" "0,1" newline bitfld.long 0x4 12. "Q0_ABORT,Abort Queue0" "0,1" newline bitfld.long 0x4 9. "Q1_FLUSH,Flush Queue1" "0,1" newline bitfld.long 0x4 8. "Q0_FLUSH,Flush Queue0" "0,1" newline bitfld.long 0x4 5. "Q1_SW_TRIG,Queue1 Software Trigger" "0,1" newline bitfld.long 0x4 4. "Q0_SW_TRIG,Queue0 Software Trigger" "0,1" newline bitfld.long 0x4 1. "Q1_TRIG_EN,Queue1 Trigger Enable" "0,1" newline bitfld.long 0x4 0. "Q0_TRIG_EN,Queue0 Trigger Enable" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "GLBL_Q_STATUS,Global Status register" hexmask.long.byte 0x0 8.--11. 1. "Q1_STATUS,These fields show the current state of the Queue1." newline hexmask.long.byte 0x0 0.--3. 1. "Q0_STATUS,These fields show the current state of the Queue0." group.long 0xC++0x3 line.long 0x0 "GLBL_IRQ_CTRL,Global IRQ Control register" bitfld.long 0x0 15. "XB_ERR_IRQ_EN,ADCXBAR Error Interrupt Enable" "0,1" newline bitfld.long 0x0 3. "Q1_ERR_IRQ_EN,Queue1 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "Q1_STAT_IRQ_EN,Queue1 Status Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "Q0_ERR_IRQ_EN,Queue0 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "Q0_STAT_IRQ_EN,Queue0 Status Interrupt Enable" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "GLBL_IRQ_STATUS,Global IRQ Status register" bitfld.long 0x0 15. "XB_ERR_IRQ,ADCXBAR Error Interrupt state" "0: ADCXBAR interrupt is not asserted.,1: ADCXBAR interrupt is asserted." newline bitfld.long 0x0 3. "Q1_ERR_IRQ,Queue1 Error Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 2. "Q1_STAT_IRQ,Queue1 Status Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 1. "Q0_ERR_IRQ,Queue0 Error Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." newline bitfld.long 0x0 0. "Q0_STAT_IRQ,Queue0 Status Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." group.long 0x14++0x3 line.long 0x0 "GLBL_OUTPUT,Global Output register" bitfld.long 0x0 4. "GLOBAL_OUT_Q_RST_CNTRS,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 3. "GLOBAL_OUT_Q_FLUSH,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 2. "GLOBAL_OUT_Q_ABORT,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 1. "GLOBAL_OUT_Q_SW_TRIG,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 0. "GLOBAL_OUT_Q_TRIG_EN,Whatever is written to this bit is reflected on the corresponding output pin. This can be used to provide a reset queue counters command to all participating queues across the ADCQs. Each queue can participate in this global.." "0,1" rgroup.long 0x18++0x7 line.long 0x0 "GLBL_CONFIG,Global Configuration register" hexmask.long.byte 0x0 8.--13. 1. "NUM_OF_TRIG_IN,Number of Input HW Triggers" newline bitfld.long 0x0 0.--2. "NUM_OF_QUEUES,Number of Queues" "?,1: Q0 queue supported,2: Q0 and Q1 supported,3: Q0 Q1 and Q2 supported,4: Q0 Q1 Q2 Q3 supported,?,?,?" line.long 0x4 "GLBL_ADC_IF_STATUS,Global ADC Interface Status register" hexmask.long.byte 0x4 20.--23. 1. "SUSPENDED_Q_NUM,Suspended Queues" newline hexmask.long.byte 0x4 8.--15. 1. "ACTIVE_ADC_CH_NUM,Current ADC CH Number" newline hexmask.long.byte 0x4 4.--7. 1. "ACTIVE_Q_NUM,Current Queue number" newline bitfld.long 0x4 0. "ADC_IF_BUSY,ADC Interface Busy" "0,1" group.long 0x20++0xB line.long 0x0 "GLBL_Q_MEAS_TIMER,Global Queue Measurement Timer register" hexmask.long.word 0x0 16.--31. 1. "DELTA_TMR_CURR_VAL,Current Value of ?T Counter" newline hexmask.long.word 0x0 0.--15. 1. "DELTA_TMR_RELOAD_VAL,Reload Value of ?T Counter" line.long 0x4 "GLBL_ADC_CNV_TIMEOUT,Global ADC Conversion Timeout register" hexmask.long.word 0x4 16.--31. 1. "ADC_CNV_CURR_VAL,Current value of timeout counter" newline hexmask.long.word 0x4 0.--15. 1. "ADC_CNV_RELOAD_VAL,Reload value of timeout counter" line.long 0x8 "GLBL_DMA_ID,Global DMA ID register" bitfld.long 0x8 31. "MID3_EN,Enable Master ID 3" "0,1" newline hexmask.long.byte 0x8 24.--30. 1. "MID3,Master ID 3" newline bitfld.long 0x8 23. "MID2_EN,Enable Master ID 2" "0,1" newline hexmask.long.byte 0x8 16.--22. 1. "MID2,Master ID 2" newline bitfld.long 0x8 15. "MID1_EN,Enable Master ID 1" "0,1" newline hexmask.long.byte 0x8 8.--14. 1. "MID1,Master ID 1" newline bitfld.long 0x8 7. "MID0_EN,Enable Master ID 0" "0,1" newline hexmask.long.byte 0x8 0.--6. 1. "MID0,Master ID 0" rgroup.long 0x30++0x3 line.long 0x0 "GLBL_HW_VER,Global Hardware Version register" hexmask.long 0x0 0.--31. 1. "NUM,Hardware Version Number" group.long 0x80++0xB line.long 0x0 "XB_Q_PRIORITY,ADCXBAR Queue Priority Assignment register" bitfld.long 0x0 4.--5. "Q1_PRIO_NUM,Queue1 Priority Number" "0,1,2,3" newline bitfld.long 0x0 0.--1. "Q0_PRIO_NUM,Queue0 Priority Number" "0,1,2,3" line.long 0x4 "XB_IRQ_CTRL,ADCXBAR Interrupt Control register" bitfld.long 0x4 0. "ADC_CNV_TO_ERR_IRQ_EN,ADC Conversion Timeout Error Interrupt Enable" "0,1" line.long 0x8 "XB_IRQ_STATUS,ADCXBAR Interrupt Status register" bitfld.long 0x8 0. "ADC_CNV_TO_ERR,ADC Conversion Timeout Error" "0,1" group.long 0x800++0xB line.long 0x0 "Q0_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 30. "AUX_ITF_SEL,Select Auxiliary Interface" "0,1" newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q0_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q0_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x80C++0x3 line.long 0x0 "Q0_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x810++0x3 line.long 0x0 "Q0_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x814++0x3 line.long 0x0 "Q0_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x818++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q0_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x820++0xF line.long 0x0 "Q0_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q0_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q0_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q0_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x830++0x3 line.long 0x0 "Q0_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x840++0x3 line.long 0x0 "Q0_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x860++0x3 line.long 0x0 "Q0_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" group.long 0x1000++0xB line.long 0x0 "Q1_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q1_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q1_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x100C++0x3 line.long 0x0 "Q1_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x1010++0x3 line.long 0x0 "Q1_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x1014++0x3 line.long 0x0 "Q1_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x1018++0x7 line.long 0x0 "Q1_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q1_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x1020++0xF line.long 0x0 "Q1_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q1_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q1_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q1_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x1030++0x3 line.long 0x0 "Q1_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x1040++0x3 line.long 0x0 "Q1_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x1060++0x3 line.long 0x0 "Q1_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" tree.end tree "SAR_ADCQ_12BIT_3" base ad:0x7092C000 group.long 0x0++0x7 line.long 0x0 "GLBL_Q_SETUP,Global Setup register" bitfld.long 0x0 1. "DEBUG_EN,Debug Enable" "0: ADCQ in normal mode. No saving of FIFO pointers..,1: ADCQ in debug mode. Operation is frozen after.." newline bitfld.long 0x0 0. "SUSP_MODE,Suspension Mode" "0: The current cmd in active sequence is aborted..,1: The current cmd in active sequence is allowed to.." line.long 0x4 "GLBL_Q_CTRL,Global Control Register" bitfld.long 0x4 29. "Q1_DATAQ_DMA_ENABLE,Queue1 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 28. "Q0_DATAQ_DMA_ENABLE,Queue0 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 25. "Q1_CMDQ_DMA_ENABLE,Queue1 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 24. "Q0_CMDQ_DMA_ENABLE,Queue0 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 17. "Q1_RESET_CNTRS,Reset Queue1 Counters" "0,1" newline bitfld.long 0x4 16. "Q0_RESET_CNTRS,Reset Queue0 Counters" "0,1" newline bitfld.long 0x4 13. "Q1_ABORT,Abort Queue1" "0,1" newline bitfld.long 0x4 12. "Q0_ABORT,Abort Queue0" "0,1" newline bitfld.long 0x4 9. "Q1_FLUSH,Flush Queue1" "0,1" newline bitfld.long 0x4 8. "Q0_FLUSH,Flush Queue0" "0,1" newline bitfld.long 0x4 5. "Q1_SW_TRIG,Queue1 Software Trigger" "0,1" newline bitfld.long 0x4 4. "Q0_SW_TRIG,Queue0 Software Trigger" "0,1" newline bitfld.long 0x4 1. "Q1_TRIG_EN,Queue1 Trigger Enable" "0,1" newline bitfld.long 0x4 0. "Q0_TRIG_EN,Queue0 Trigger Enable" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "GLBL_Q_STATUS,Global Status register" hexmask.long.byte 0x0 8.--11. 1. "Q1_STATUS,These fields show the current state of the Queue1." newline hexmask.long.byte 0x0 0.--3. 1. "Q0_STATUS,These fields show the current state of the Queue0." group.long 0xC++0x3 line.long 0x0 "GLBL_IRQ_CTRL,Global IRQ Control register" bitfld.long 0x0 15. "XB_ERR_IRQ_EN,ADCXBAR Error Interrupt Enable" "0,1" newline bitfld.long 0x0 3. "Q1_ERR_IRQ_EN,Queue1 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "Q1_STAT_IRQ_EN,Queue1 Status Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "Q0_ERR_IRQ_EN,Queue0 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "Q0_STAT_IRQ_EN,Queue0 Status Interrupt Enable" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "GLBL_IRQ_STATUS,Global IRQ Status register" bitfld.long 0x0 15. "XB_ERR_IRQ,ADCXBAR Error Interrupt state" "0: ADCXBAR interrupt is not asserted.,1: ADCXBAR interrupt is asserted." newline bitfld.long 0x0 3. "Q1_ERR_IRQ,Queue1 Error Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 2. "Q1_STAT_IRQ,Queue1 Status Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 1. "Q0_ERR_IRQ,Queue0 Error Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." newline bitfld.long 0x0 0. "Q0_STAT_IRQ,Queue0 Status Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." group.long 0x14++0x3 line.long 0x0 "GLBL_OUTPUT,Global Output register" bitfld.long 0x0 4. "GLOBAL_OUT_Q_RST_CNTRS,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 3. "GLOBAL_OUT_Q_FLUSH,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 2. "GLOBAL_OUT_Q_ABORT,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 1. "GLOBAL_OUT_Q_SW_TRIG,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 0. "GLOBAL_OUT_Q_TRIG_EN,Whatever is written to this bit is reflected on the corresponding output pin. This can be used to provide a reset queue counters command to all participating queues across the ADCQs. Each queue can participate in this global.." "0,1" rgroup.long 0x18++0x7 line.long 0x0 "GLBL_CONFIG,Global Configuration register" hexmask.long.byte 0x0 8.--13. 1. "NUM_OF_TRIG_IN,Number of Input HW Triggers" newline bitfld.long 0x0 0.--2. "NUM_OF_QUEUES,Number of Queues" "?,1: Q0 queue supported,2: Q0 and Q1 supported,3: Q0 Q1 and Q2 supported,4: Q0 Q1 Q2 Q3 supported,?,?,?" line.long 0x4 "GLBL_ADC_IF_STATUS,Global ADC Interface Status register" hexmask.long.byte 0x4 20.--23. 1. "SUSPENDED_Q_NUM,Suspended Queues" newline hexmask.long.byte 0x4 8.--15. 1. "ACTIVE_ADC_CH_NUM,Current ADC CH Number" newline hexmask.long.byte 0x4 4.--7. 1. "ACTIVE_Q_NUM,Current Queue number" newline bitfld.long 0x4 0. "ADC_IF_BUSY,ADC Interface Busy" "0,1" group.long 0x20++0xB line.long 0x0 "GLBL_Q_MEAS_TIMER,Global Queue Measurement Timer register" hexmask.long.word 0x0 16.--31. 1. "DELTA_TMR_CURR_VAL,Current Value of ?T Counter" newline hexmask.long.word 0x0 0.--15. 1. "DELTA_TMR_RELOAD_VAL,Reload Value of ?T Counter" line.long 0x4 "GLBL_ADC_CNV_TIMEOUT,Global ADC Conversion Timeout register" hexmask.long.word 0x4 16.--31. 1. "ADC_CNV_CURR_VAL,Current value of timeout counter" newline hexmask.long.word 0x4 0.--15. 1. "ADC_CNV_RELOAD_VAL,Reload value of timeout counter" line.long 0x8 "GLBL_DMA_ID,Global DMA ID register" bitfld.long 0x8 31. "MID3_EN,Enable Master ID 3" "0,1" newline hexmask.long.byte 0x8 24.--30. 1. "MID3,Master ID 3" newline bitfld.long 0x8 23. "MID2_EN,Enable Master ID 2" "0,1" newline hexmask.long.byte 0x8 16.--22. 1. "MID2,Master ID 2" newline bitfld.long 0x8 15. "MID1_EN,Enable Master ID 1" "0,1" newline hexmask.long.byte 0x8 8.--14. 1. "MID1,Master ID 1" newline bitfld.long 0x8 7. "MID0_EN,Enable Master ID 0" "0,1" newline hexmask.long.byte 0x8 0.--6. 1. "MID0,Master ID 0" rgroup.long 0x30++0x3 line.long 0x0 "GLBL_HW_VER,Global Hardware Version register" hexmask.long 0x0 0.--31. 1. "NUM,Hardware Version Number" group.long 0x80++0xB line.long 0x0 "XB_Q_PRIORITY,ADCXBAR Queue Priority Assignment register" bitfld.long 0x0 4.--5. "Q1_PRIO_NUM,Queue1 Priority Number" "0,1,2,3" newline bitfld.long 0x0 0.--1. "Q0_PRIO_NUM,Queue0 Priority Number" "0,1,2,3" line.long 0x4 "XB_IRQ_CTRL,ADCXBAR Interrupt Control register" bitfld.long 0x4 0. "ADC_CNV_TO_ERR_IRQ_EN,ADC Conversion Timeout Error Interrupt Enable" "0,1" line.long 0x8 "XB_IRQ_STATUS,ADCXBAR Interrupt Status register" bitfld.long 0x8 0. "ADC_CNV_TO_ERR,ADC Conversion Timeout Error" "0,1" group.long 0x800++0xB line.long 0x0 "Q0_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 30. "AUX_ITF_SEL,Select Auxiliary Interface" "0,1" newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q0_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q0_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x80C++0x3 line.long 0x0 "Q0_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x810++0x3 line.long 0x0 "Q0_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x814++0x3 line.long 0x0 "Q0_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x818++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q0_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x820++0xF line.long 0x0 "Q0_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q0_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q0_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q0_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x830++0x3 line.long 0x0 "Q0_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x840++0x3 line.long 0x0 "Q0_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x860++0x3 line.long 0x0 "Q0_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" group.long 0x1000++0xB line.long 0x0 "Q1_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q1_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q1_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x100C++0x3 line.long 0x0 "Q1_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x1010++0x3 line.long 0x0 "Q1_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x1014++0x3 line.long 0x0 "Q1_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x1018++0x7 line.long 0x0 "Q1_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q1_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x1020++0xF line.long 0x0 "Q1_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q1_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q1_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q1_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x1030++0x3 line.long 0x0 "Q1_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x1040++0x3 line.long 0x0 "Q1_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x1060++0x3 line.long 0x0 "Q1_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" tree.end tree "SAR_ADCQ_12BIT_4" base ad:0x70330000 group.long 0x0++0x7 line.long 0x0 "GLBL_Q_SETUP,Global Setup register" bitfld.long 0x0 1. "DEBUG_EN,Debug Enable" "0: ADCQ in normal mode. No saving of FIFO pointers..,1: ADCQ in debug mode. Operation is frozen after.." newline bitfld.long 0x0 0. "SUSP_MODE,Suspension Mode" "0: The current cmd in active sequence is aborted..,1: The current cmd in active sequence is allowed to.." line.long 0x4 "GLBL_Q_CTRL,Global Control Register" bitfld.long 0x4 29. "Q1_DATAQ_DMA_ENABLE,Queue1 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 28. "Q0_DATAQ_DMA_ENABLE,Queue0 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 25. "Q1_CMDQ_DMA_ENABLE,Queue1 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 24. "Q0_CMDQ_DMA_ENABLE,Queue0 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 17. "Q1_RESET_CNTRS,Reset Queue1 Counters" "0,1" newline bitfld.long 0x4 16. "Q0_RESET_CNTRS,Reset Queue0 Counters" "0,1" newline bitfld.long 0x4 13. "Q1_ABORT,Abort Queue1" "0,1" newline bitfld.long 0x4 12. "Q0_ABORT,Abort Queue0" "0,1" newline bitfld.long 0x4 9. "Q1_FLUSH,Flush Queue1" "0,1" newline bitfld.long 0x4 8. "Q0_FLUSH,Flush Queue0" "0,1" newline bitfld.long 0x4 5. "Q1_SW_TRIG,Queue1 Software Trigger" "0,1" newline bitfld.long 0x4 4. "Q0_SW_TRIG,Queue0 Software Trigger" "0,1" newline bitfld.long 0x4 1. "Q1_TRIG_EN,Queue1 Trigger Enable" "0,1" newline bitfld.long 0x4 0. "Q0_TRIG_EN,Queue0 Trigger Enable" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "GLBL_Q_STATUS,Global Status register" hexmask.long.byte 0x0 8.--11. 1. "Q1_STATUS,These fields show the current state of the Queue1." newline hexmask.long.byte 0x0 0.--3. 1. "Q0_STATUS,These fields show the current state of the Queue0." group.long 0xC++0x3 line.long 0x0 "GLBL_IRQ_CTRL,Global IRQ Control register" bitfld.long 0x0 15. "XB_ERR_IRQ_EN,ADCXBAR Error Interrupt Enable" "0,1" newline bitfld.long 0x0 3. "Q1_ERR_IRQ_EN,Queue1 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "Q1_STAT_IRQ_EN,Queue1 Status Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "Q0_ERR_IRQ_EN,Queue0 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "Q0_STAT_IRQ_EN,Queue0 Status Interrupt Enable" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "GLBL_IRQ_STATUS,Global IRQ Status register" bitfld.long 0x0 15. "XB_ERR_IRQ,ADCXBAR Error Interrupt state" "0: ADCXBAR interrupt is not asserted.,1: ADCXBAR interrupt is asserted." newline bitfld.long 0x0 3. "Q1_ERR_IRQ,Queue1 Error Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 2. "Q1_STAT_IRQ,Queue1 Status Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 1. "Q0_ERR_IRQ,Queue0 Error Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." newline bitfld.long 0x0 0. "Q0_STAT_IRQ,Queue0 Status Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." group.long 0x14++0x3 line.long 0x0 "GLBL_OUTPUT,Global Output register" bitfld.long 0x0 4. "GLOBAL_OUT_Q_RST_CNTRS,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 3. "GLOBAL_OUT_Q_FLUSH,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 2. "GLOBAL_OUT_Q_ABORT,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 1. "GLOBAL_OUT_Q_SW_TRIG,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 0. "GLOBAL_OUT_Q_TRIG_EN,Whatever is written to this bit is reflected on the corresponding output pin. This can be used to provide a reset queue counters command to all participating queues across the ADCQs. Each queue can participate in this global.." "0,1" rgroup.long 0x18++0x7 line.long 0x0 "GLBL_CONFIG,Global Configuration register" hexmask.long.byte 0x0 8.--13. 1. "NUM_OF_TRIG_IN,Number of Input HW Triggers" newline bitfld.long 0x0 0.--2. "NUM_OF_QUEUES,Number of Queues" "?,1: Q0 queue supported,2: Q0 and Q1 supported,3: Q0 Q1 and Q2 supported,4: Q0 Q1 Q2 Q3 supported,?,?,?" line.long 0x4 "GLBL_ADC_IF_STATUS,Global ADC Interface Status register" hexmask.long.byte 0x4 20.--23. 1. "SUSPENDED_Q_NUM,Suspended Queues" newline hexmask.long.byte 0x4 8.--15. 1. "ACTIVE_ADC_CH_NUM,Current ADC CH Number" newline hexmask.long.byte 0x4 4.--7. 1. "ACTIVE_Q_NUM,Current Queue number" newline bitfld.long 0x4 0. "ADC_IF_BUSY,ADC Interface Busy" "0,1" group.long 0x20++0xB line.long 0x0 "GLBL_Q_MEAS_TIMER,Global Queue Measurement Timer register" hexmask.long.word 0x0 16.--31. 1. "DELTA_TMR_CURR_VAL,Current Value of ?T Counter" newline hexmask.long.word 0x0 0.--15. 1. "DELTA_TMR_RELOAD_VAL,Reload Value of ?T Counter" line.long 0x4 "GLBL_ADC_CNV_TIMEOUT,Global ADC Conversion Timeout register" hexmask.long.word 0x4 16.--31. 1. "ADC_CNV_CURR_VAL,Current value of timeout counter" newline hexmask.long.word 0x4 0.--15. 1. "ADC_CNV_RELOAD_VAL,Reload value of timeout counter" line.long 0x8 "GLBL_DMA_ID,Global DMA ID register" bitfld.long 0x8 31. "MID3_EN,Enable Master ID 3" "0,1" newline hexmask.long.byte 0x8 24.--30. 1. "MID3,Master ID 3" newline bitfld.long 0x8 23. "MID2_EN,Enable Master ID 2" "0,1" newline hexmask.long.byte 0x8 16.--22. 1. "MID2,Master ID 2" newline bitfld.long 0x8 15. "MID1_EN,Enable Master ID 1" "0,1" newline hexmask.long.byte 0x8 8.--14. 1. "MID1,Master ID 1" newline bitfld.long 0x8 7. "MID0_EN,Enable Master ID 0" "0,1" newline hexmask.long.byte 0x8 0.--6. 1. "MID0,Master ID 0" rgroup.long 0x30++0x3 line.long 0x0 "GLBL_HW_VER,Global Hardware Version register" hexmask.long 0x0 0.--31. 1. "NUM,Hardware Version Number" group.long 0x80++0xB line.long 0x0 "XB_Q_PRIORITY,ADCXBAR Queue Priority Assignment register" bitfld.long 0x0 4.--5. "Q1_PRIO_NUM,Queue1 Priority Number" "0,1,2,3" newline bitfld.long 0x0 0.--1. "Q0_PRIO_NUM,Queue0 Priority Number" "0,1,2,3" line.long 0x4 "XB_IRQ_CTRL,ADCXBAR Interrupt Control register" bitfld.long 0x4 0. "ADC_CNV_TO_ERR_IRQ_EN,ADC Conversion Timeout Error Interrupt Enable" "0,1" line.long 0x8 "XB_IRQ_STATUS,ADCXBAR Interrupt Status register" bitfld.long 0x8 0. "ADC_CNV_TO_ERR,ADC Conversion Timeout Error" "0,1" group.long 0x800++0xB line.long 0x0 "Q0_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 30. "AUX_ITF_SEL,Select Auxiliary Interface" "0,1" newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q0_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q0_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x80C++0x3 line.long 0x0 "Q0_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x810++0x3 line.long 0x0 "Q0_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x814++0x3 line.long 0x0 "Q0_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x818++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q0_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x820++0xF line.long 0x0 "Q0_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q0_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q0_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q0_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x830++0x3 line.long 0x0 "Q0_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x840++0x3 line.long 0x0 "Q0_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x860++0x3 line.long 0x0 "Q0_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" group.long 0x1000++0xB line.long 0x0 "Q1_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q1_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q1_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x100C++0x3 line.long 0x0 "Q1_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x1010++0x3 line.long 0x0 "Q1_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x1014++0x3 line.long 0x0 "Q1_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x1018++0x7 line.long 0x0 "Q1_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q1_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x1020++0xF line.long 0x0 "Q1_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q1_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q1_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q1_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x1030++0x3 line.long 0x0 "Q1_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x1040++0x3 line.long 0x0 "Q1_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x1060++0x3 line.long 0x0 "Q1_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" tree.end tree "SAR_ADCQ_12BIT_5" base ad:0x70930000 group.long 0x0++0x7 line.long 0x0 "GLBL_Q_SETUP,Global Setup register" bitfld.long 0x0 1. "DEBUG_EN,Debug Enable" "0: ADCQ in normal mode. No saving of FIFO pointers..,1: ADCQ in debug mode. Operation is frozen after.." newline bitfld.long 0x0 0. "SUSP_MODE,Suspension Mode" "0: The current cmd in active sequence is aborted..,1: The current cmd in active sequence is allowed to.." line.long 0x4 "GLBL_Q_CTRL,Global Control Register" bitfld.long 0x4 29. "Q1_DATAQ_DMA_ENABLE,Queue1 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 28. "Q0_DATAQ_DMA_ENABLE,Queue0 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 25. "Q1_CMDQ_DMA_ENABLE,Queue1 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 24. "Q0_CMDQ_DMA_ENABLE,Queue0 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 17. "Q1_RESET_CNTRS,Reset Queue1 Counters" "0,1" newline bitfld.long 0x4 16. "Q0_RESET_CNTRS,Reset Queue0 Counters" "0,1" newline bitfld.long 0x4 13. "Q1_ABORT,Abort Queue1" "0,1" newline bitfld.long 0x4 12. "Q0_ABORT,Abort Queue0" "0,1" newline bitfld.long 0x4 9. "Q1_FLUSH,Flush Queue1" "0,1" newline bitfld.long 0x4 8. "Q0_FLUSH,Flush Queue0" "0,1" newline bitfld.long 0x4 5. "Q1_SW_TRIG,Queue1 Software Trigger" "0,1" newline bitfld.long 0x4 4. "Q0_SW_TRIG,Queue0 Software Trigger" "0,1" newline bitfld.long 0x4 1. "Q1_TRIG_EN,Queue1 Trigger Enable" "0,1" newline bitfld.long 0x4 0. "Q0_TRIG_EN,Queue0 Trigger Enable" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "GLBL_Q_STATUS,Global Status register" hexmask.long.byte 0x0 8.--11. 1. "Q1_STATUS,These fields show the current state of the Queue1." newline hexmask.long.byte 0x0 0.--3. 1. "Q0_STATUS,These fields show the current state of the Queue0." group.long 0xC++0x3 line.long 0x0 "GLBL_IRQ_CTRL,Global IRQ Control register" bitfld.long 0x0 15. "XB_ERR_IRQ_EN,ADCXBAR Error Interrupt Enable" "0,1" newline bitfld.long 0x0 3. "Q1_ERR_IRQ_EN,Queue1 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "Q1_STAT_IRQ_EN,Queue1 Status Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "Q0_ERR_IRQ_EN,Queue0 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "Q0_STAT_IRQ_EN,Queue0 Status Interrupt Enable" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "GLBL_IRQ_STATUS,Global IRQ Status register" bitfld.long 0x0 15. "XB_ERR_IRQ,ADCXBAR Error Interrupt state" "0: ADCXBAR interrupt is not asserted.,1: ADCXBAR interrupt is asserted." newline bitfld.long 0x0 3. "Q1_ERR_IRQ,Queue1 Error Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 2. "Q1_STAT_IRQ,Queue1 Status Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 1. "Q0_ERR_IRQ,Queue0 Error Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." newline bitfld.long 0x0 0. "Q0_STAT_IRQ,Queue0 Status Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." group.long 0x14++0x3 line.long 0x0 "GLBL_OUTPUT,Global Output register" bitfld.long 0x0 4. "GLOBAL_OUT_Q_RST_CNTRS,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 3. "GLOBAL_OUT_Q_FLUSH,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 2. "GLOBAL_OUT_Q_ABORT,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 1. "GLOBAL_OUT_Q_SW_TRIG,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 0. "GLOBAL_OUT_Q_TRIG_EN,Whatever is written to this bit is reflected on the corresponding output pin. This can be used to provide a reset queue counters command to all participating queues across the ADCQs. Each queue can participate in this global.." "0,1" rgroup.long 0x18++0x7 line.long 0x0 "GLBL_CONFIG,Global Configuration register" hexmask.long.byte 0x0 8.--13. 1. "NUM_OF_TRIG_IN,Number of Input HW Triggers" newline bitfld.long 0x0 0.--2. "NUM_OF_QUEUES,Number of Queues" "?,1: Q0 queue supported,2: Q0 and Q1 supported,3: Q0 Q1 and Q2 supported,4: Q0 Q1 Q2 Q3 supported,?,?,?" line.long 0x4 "GLBL_ADC_IF_STATUS,Global ADC Interface Status register" hexmask.long.byte 0x4 20.--23. 1. "SUSPENDED_Q_NUM,Suspended Queues" newline hexmask.long.byte 0x4 8.--15. 1. "ACTIVE_ADC_CH_NUM,Current ADC CH Number" newline hexmask.long.byte 0x4 4.--7. 1. "ACTIVE_Q_NUM,Current Queue number" newline bitfld.long 0x4 0. "ADC_IF_BUSY,ADC Interface Busy" "0,1" group.long 0x20++0xB line.long 0x0 "GLBL_Q_MEAS_TIMER,Global Queue Measurement Timer register" hexmask.long.word 0x0 16.--31. 1. "DELTA_TMR_CURR_VAL,Current Value of ?T Counter" newline hexmask.long.word 0x0 0.--15. 1. "DELTA_TMR_RELOAD_VAL,Reload Value of ?T Counter" line.long 0x4 "GLBL_ADC_CNV_TIMEOUT,Global ADC Conversion Timeout register" hexmask.long.word 0x4 16.--31. 1. "ADC_CNV_CURR_VAL,Current value of timeout counter" newline hexmask.long.word 0x4 0.--15. 1. "ADC_CNV_RELOAD_VAL,Reload value of timeout counter" line.long 0x8 "GLBL_DMA_ID,Global DMA ID register" bitfld.long 0x8 31. "MID3_EN,Enable Master ID 3" "0,1" newline hexmask.long.byte 0x8 24.--30. 1. "MID3,Master ID 3" newline bitfld.long 0x8 23. "MID2_EN,Enable Master ID 2" "0,1" newline hexmask.long.byte 0x8 16.--22. 1. "MID2,Master ID 2" newline bitfld.long 0x8 15. "MID1_EN,Enable Master ID 1" "0,1" newline hexmask.long.byte 0x8 8.--14. 1. "MID1,Master ID 1" newline bitfld.long 0x8 7. "MID0_EN,Enable Master ID 0" "0,1" newline hexmask.long.byte 0x8 0.--6. 1. "MID0,Master ID 0" rgroup.long 0x30++0x3 line.long 0x0 "GLBL_HW_VER,Global Hardware Version register" hexmask.long 0x0 0.--31. 1. "NUM,Hardware Version Number" group.long 0x80++0xB line.long 0x0 "XB_Q_PRIORITY,ADCXBAR Queue Priority Assignment register" bitfld.long 0x0 4.--5. "Q1_PRIO_NUM,Queue1 Priority Number" "0,1,2,3" newline bitfld.long 0x0 0.--1. "Q0_PRIO_NUM,Queue0 Priority Number" "0,1,2,3" line.long 0x4 "XB_IRQ_CTRL,ADCXBAR Interrupt Control register" bitfld.long 0x4 0. "ADC_CNV_TO_ERR_IRQ_EN,ADC Conversion Timeout Error Interrupt Enable" "0,1" line.long 0x8 "XB_IRQ_STATUS,ADCXBAR Interrupt Status register" bitfld.long 0x8 0. "ADC_CNV_TO_ERR,ADC Conversion Timeout Error" "0,1" group.long 0x800++0xB line.long 0x0 "Q0_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 30. "AUX_ITF_SEL,Select Auxiliary Interface" "0,1" newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q0_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q0_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x80C++0x3 line.long 0x0 "Q0_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x810++0x3 line.long 0x0 "Q0_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x814++0x3 line.long 0x0 "Q0_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x818++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q0_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x820++0xF line.long 0x0 "Q0_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q0_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q0_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q0_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x830++0x3 line.long 0x0 "Q0_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x840++0x3 line.long 0x0 "Q0_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x860++0x3 line.long 0x0 "Q0_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" group.long 0x1000++0xB line.long 0x0 "Q1_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q1_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q1_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x100C++0x3 line.long 0x0 "Q1_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x1010++0x3 line.long 0x0 "Q1_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x1014++0x3 line.long 0x0 "Q1_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x1018++0x7 line.long 0x0 "Q1_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q1_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x1020++0xF line.long 0x0 "Q1_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q1_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q1_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q1_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x1030++0x3 line.long 0x0 "Q1_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x1040++0x3 line.long 0x0 "Q1_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x1060++0x3 line.long 0x0 "Q1_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" tree.end tree "SAR_ADCQ_12BIT_6" base ad:0x70334000 group.long 0x0++0x7 line.long 0x0 "GLBL_Q_SETUP,Global Setup register" bitfld.long 0x0 1. "DEBUG_EN,Debug Enable" "0: ADCQ in normal mode. No saving of FIFO pointers..,1: ADCQ in debug mode. Operation is frozen after.." newline bitfld.long 0x0 0. "SUSP_MODE,Suspension Mode" "0: The current cmd in active sequence is aborted..,1: The current cmd in active sequence is allowed to.." line.long 0x4 "GLBL_Q_CTRL,Global Control Register" bitfld.long 0x4 29. "Q1_DATAQ_DMA_ENABLE,Queue1 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 28. "Q0_DATAQ_DMA_ENABLE,Queue0 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 25. "Q1_CMDQ_DMA_ENABLE,Queue1 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 24. "Q0_CMDQ_DMA_ENABLE,Queue0 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 17. "Q1_RESET_CNTRS,Reset Queue1 Counters" "0,1" newline bitfld.long 0x4 16. "Q0_RESET_CNTRS,Reset Queue0 Counters" "0,1" newline bitfld.long 0x4 13. "Q1_ABORT,Abort Queue1" "0,1" newline bitfld.long 0x4 12. "Q0_ABORT,Abort Queue0" "0,1" newline bitfld.long 0x4 9. "Q1_FLUSH,Flush Queue1" "0,1" newline bitfld.long 0x4 8. "Q0_FLUSH,Flush Queue0" "0,1" newline bitfld.long 0x4 5. "Q1_SW_TRIG,Queue1 Software Trigger" "0,1" newline bitfld.long 0x4 4. "Q0_SW_TRIG,Queue0 Software Trigger" "0,1" newline bitfld.long 0x4 1. "Q1_TRIG_EN,Queue1 Trigger Enable" "0,1" newline bitfld.long 0x4 0. "Q0_TRIG_EN,Queue0 Trigger Enable" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "GLBL_Q_STATUS,Global Status register" hexmask.long.byte 0x0 8.--11. 1. "Q1_STATUS,These fields show the current state of the Queue1." newline hexmask.long.byte 0x0 0.--3. 1. "Q0_STATUS,These fields show the current state of the Queue0." group.long 0xC++0x3 line.long 0x0 "GLBL_IRQ_CTRL,Global IRQ Control register" bitfld.long 0x0 15. "XB_ERR_IRQ_EN,ADCXBAR Error Interrupt Enable" "0,1" newline bitfld.long 0x0 3. "Q1_ERR_IRQ_EN,Queue1 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "Q1_STAT_IRQ_EN,Queue1 Status Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "Q0_ERR_IRQ_EN,Queue0 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "Q0_STAT_IRQ_EN,Queue0 Status Interrupt Enable" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "GLBL_IRQ_STATUS,Global IRQ Status register" bitfld.long 0x0 15. "XB_ERR_IRQ,ADCXBAR Error Interrupt state" "0: ADCXBAR interrupt is not asserted.,1: ADCXBAR interrupt is asserted." newline bitfld.long 0x0 3. "Q1_ERR_IRQ,Queue1 Error Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 2. "Q1_STAT_IRQ,Queue1 Status Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 1. "Q0_ERR_IRQ,Queue0 Error Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." newline bitfld.long 0x0 0. "Q0_STAT_IRQ,Queue0 Status Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." group.long 0x14++0x3 line.long 0x0 "GLBL_OUTPUT,Global Output register" bitfld.long 0x0 4. "GLOBAL_OUT_Q_RST_CNTRS,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 3. "GLOBAL_OUT_Q_FLUSH,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 2. "GLOBAL_OUT_Q_ABORT,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 1. "GLOBAL_OUT_Q_SW_TRIG,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 0. "GLOBAL_OUT_Q_TRIG_EN,Whatever is written to this bit is reflected on the corresponding output pin. This can be used to provide a reset queue counters command to all participating queues across the ADCQs. Each queue can participate in this global.." "0,1" rgroup.long 0x18++0x7 line.long 0x0 "GLBL_CONFIG,Global Configuration register" hexmask.long.byte 0x0 8.--13. 1. "NUM_OF_TRIG_IN,Number of Input HW Triggers" newline bitfld.long 0x0 0.--2. "NUM_OF_QUEUES,Number of Queues" "?,1: Q0 queue supported,2: Q0 and Q1 supported,3: Q0 Q1 and Q2 supported,4: Q0 Q1 Q2 Q3 supported,?,?,?" line.long 0x4 "GLBL_ADC_IF_STATUS,Global ADC Interface Status register" hexmask.long.byte 0x4 20.--23. 1. "SUSPENDED_Q_NUM,Suspended Queues" newline hexmask.long.byte 0x4 8.--15. 1. "ACTIVE_ADC_CH_NUM,Current ADC CH Number" newline hexmask.long.byte 0x4 4.--7. 1. "ACTIVE_Q_NUM,Current Queue number" newline bitfld.long 0x4 0. "ADC_IF_BUSY,ADC Interface Busy" "0,1" group.long 0x20++0xB line.long 0x0 "GLBL_Q_MEAS_TIMER,Global Queue Measurement Timer register" hexmask.long.word 0x0 16.--31. 1. "DELTA_TMR_CURR_VAL,Current Value of ?T Counter" newline hexmask.long.word 0x0 0.--15. 1. "DELTA_TMR_RELOAD_VAL,Reload Value of ?T Counter" line.long 0x4 "GLBL_ADC_CNV_TIMEOUT,Global ADC Conversion Timeout register" hexmask.long.word 0x4 16.--31. 1. "ADC_CNV_CURR_VAL,Current value of timeout counter" newline hexmask.long.word 0x4 0.--15. 1. "ADC_CNV_RELOAD_VAL,Reload value of timeout counter" line.long 0x8 "GLBL_DMA_ID,Global DMA ID register" bitfld.long 0x8 31. "MID3_EN,Enable Master ID 3" "0,1" newline hexmask.long.byte 0x8 24.--30. 1. "MID3,Master ID 3" newline bitfld.long 0x8 23. "MID2_EN,Enable Master ID 2" "0,1" newline hexmask.long.byte 0x8 16.--22. 1. "MID2,Master ID 2" newline bitfld.long 0x8 15. "MID1_EN,Enable Master ID 1" "0,1" newline hexmask.long.byte 0x8 8.--14. 1. "MID1,Master ID 1" newline bitfld.long 0x8 7. "MID0_EN,Enable Master ID 0" "0,1" newline hexmask.long.byte 0x8 0.--6. 1. "MID0,Master ID 0" rgroup.long 0x30++0x3 line.long 0x0 "GLBL_HW_VER,Global Hardware Version register" hexmask.long 0x0 0.--31. 1. "NUM,Hardware Version Number" group.long 0x80++0xB line.long 0x0 "XB_Q_PRIORITY,ADCXBAR Queue Priority Assignment register" bitfld.long 0x0 4.--5. "Q1_PRIO_NUM,Queue1 Priority Number" "0,1,2,3" newline bitfld.long 0x0 0.--1. "Q0_PRIO_NUM,Queue0 Priority Number" "0,1,2,3" line.long 0x4 "XB_IRQ_CTRL,ADCXBAR Interrupt Control register" bitfld.long 0x4 0. "ADC_CNV_TO_ERR_IRQ_EN,ADC Conversion Timeout Error Interrupt Enable" "0,1" line.long 0x8 "XB_IRQ_STATUS,ADCXBAR Interrupt Status register" bitfld.long 0x8 0. "ADC_CNV_TO_ERR,ADC Conversion Timeout Error" "0,1" group.long 0x800++0xB line.long 0x0 "Q0_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 30. "AUX_ITF_SEL,Select Auxiliary Interface" "0,1" newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q0_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q0_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x80C++0x3 line.long 0x0 "Q0_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x810++0x3 line.long 0x0 "Q0_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x814++0x3 line.long 0x0 "Q0_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x818++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q0_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x820++0xF line.long 0x0 "Q0_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q0_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q0_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q0_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x830++0x3 line.long 0x0 "Q0_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x840++0x3 line.long 0x0 "Q0_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x860++0x3 line.long 0x0 "Q0_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" group.long 0x1000++0xB line.long 0x0 "Q1_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q1_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q1_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x100C++0x3 line.long 0x0 "Q1_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x1010++0x3 line.long 0x0 "Q1_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x1014++0x3 line.long 0x0 "Q1_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x1018++0x7 line.long 0x0 "Q1_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q1_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x1020++0xF line.long 0x0 "Q1_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q1_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q1_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q1_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x1030++0x3 line.long 0x0 "Q1_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x1040++0x3 line.long 0x0 "Q1_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x1060++0x3 line.long 0x0 "Q1_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" tree.end tree "SAR_ADCQ_12BIT_7" base ad:0x70934000 group.long 0x0++0x7 line.long 0x0 "GLBL_Q_SETUP,Global Setup register" bitfld.long 0x0 1. "DEBUG_EN,Debug Enable" "0: ADCQ in normal mode. No saving of FIFO pointers..,1: ADCQ in debug mode. Operation is frozen after.." newline bitfld.long 0x0 0. "SUSP_MODE,Suspension Mode" "0: The current cmd in active sequence is aborted..,1: The current cmd in active sequence is allowed to.." line.long 0x4 "GLBL_Q_CTRL,Global Control Register" bitfld.long 0x4 29. "Q1_DATAQ_DMA_ENABLE,Queue1 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 28. "Q0_DATAQ_DMA_ENABLE,Queue0 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 25. "Q1_CMDQ_DMA_ENABLE,Queue1 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 24. "Q0_CMDQ_DMA_ENABLE,Queue0 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 17. "Q1_RESET_CNTRS,Reset Queue1 Counters" "0,1" newline bitfld.long 0x4 16. "Q0_RESET_CNTRS,Reset Queue0 Counters" "0,1" newline bitfld.long 0x4 13. "Q1_ABORT,Abort Queue1" "0,1" newline bitfld.long 0x4 12. "Q0_ABORT,Abort Queue0" "0,1" newline bitfld.long 0x4 9. "Q1_FLUSH,Flush Queue1" "0,1" newline bitfld.long 0x4 8. "Q0_FLUSH,Flush Queue0" "0,1" newline bitfld.long 0x4 5. "Q1_SW_TRIG,Queue1 Software Trigger" "0,1" newline bitfld.long 0x4 4. "Q0_SW_TRIG,Queue0 Software Trigger" "0,1" newline bitfld.long 0x4 1. "Q1_TRIG_EN,Queue1 Trigger Enable" "0,1" newline bitfld.long 0x4 0. "Q0_TRIG_EN,Queue0 Trigger Enable" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "GLBL_Q_STATUS,Global Status register" hexmask.long.byte 0x0 8.--11. 1. "Q1_STATUS,These fields show the current state of the Queue1." newline hexmask.long.byte 0x0 0.--3. 1. "Q0_STATUS,These fields show the current state of the Queue0." group.long 0xC++0x3 line.long 0x0 "GLBL_IRQ_CTRL,Global IRQ Control register" bitfld.long 0x0 15. "XB_ERR_IRQ_EN,ADCXBAR Error Interrupt Enable" "0,1" newline bitfld.long 0x0 3. "Q1_ERR_IRQ_EN,Queue1 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "Q1_STAT_IRQ_EN,Queue1 Status Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "Q0_ERR_IRQ_EN,Queue0 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "Q0_STAT_IRQ_EN,Queue0 Status Interrupt Enable" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "GLBL_IRQ_STATUS,Global IRQ Status register" bitfld.long 0x0 15. "XB_ERR_IRQ,ADCXBAR Error Interrupt state" "0: ADCXBAR interrupt is not asserted.,1: ADCXBAR interrupt is asserted." newline bitfld.long 0x0 3. "Q1_ERR_IRQ,Queue1 Error Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 2. "Q1_STAT_IRQ,Queue1 Status Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 1. "Q0_ERR_IRQ,Queue0 Error Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." newline bitfld.long 0x0 0. "Q0_STAT_IRQ,Queue0 Status Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." group.long 0x14++0x3 line.long 0x0 "GLBL_OUTPUT,Global Output register" bitfld.long 0x0 4. "GLOBAL_OUT_Q_RST_CNTRS,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 3. "GLOBAL_OUT_Q_FLUSH,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 2. "GLOBAL_OUT_Q_ABORT,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 1. "GLOBAL_OUT_Q_SW_TRIG,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 0. "GLOBAL_OUT_Q_TRIG_EN,Whatever is written to this bit is reflected on the corresponding output pin. This can be used to provide a reset queue counters command to all participating queues across the ADCQs. Each queue can participate in this global.." "0,1" rgroup.long 0x18++0x7 line.long 0x0 "GLBL_CONFIG,Global Configuration register" hexmask.long.byte 0x0 8.--13. 1. "NUM_OF_TRIG_IN,Number of Input HW Triggers" newline bitfld.long 0x0 0.--2. "NUM_OF_QUEUES,Number of Queues" "?,1: Q0 queue supported,2: Q0 and Q1 supported,3: Q0 Q1 and Q2 supported,4: Q0 Q1 Q2 Q3 supported,?,?,?" line.long 0x4 "GLBL_ADC_IF_STATUS,Global ADC Interface Status register" hexmask.long.byte 0x4 20.--23. 1. "SUSPENDED_Q_NUM,Suspended Queues" newline hexmask.long.byte 0x4 8.--15. 1. "ACTIVE_ADC_CH_NUM,Current ADC CH Number" newline hexmask.long.byte 0x4 4.--7. 1. "ACTIVE_Q_NUM,Current Queue number" newline bitfld.long 0x4 0. "ADC_IF_BUSY,ADC Interface Busy" "0,1" group.long 0x20++0xB line.long 0x0 "GLBL_Q_MEAS_TIMER,Global Queue Measurement Timer register" hexmask.long.word 0x0 16.--31. 1. "DELTA_TMR_CURR_VAL,Current Value of ?T Counter" newline hexmask.long.word 0x0 0.--15. 1. "DELTA_TMR_RELOAD_VAL,Reload Value of ?T Counter" line.long 0x4 "GLBL_ADC_CNV_TIMEOUT,Global ADC Conversion Timeout register" hexmask.long.word 0x4 16.--31. 1. "ADC_CNV_CURR_VAL,Current value of timeout counter" newline hexmask.long.word 0x4 0.--15. 1. "ADC_CNV_RELOAD_VAL,Reload value of timeout counter" line.long 0x8 "GLBL_DMA_ID,Global DMA ID register" bitfld.long 0x8 31. "MID3_EN,Enable Master ID 3" "0,1" newline hexmask.long.byte 0x8 24.--30. 1. "MID3,Master ID 3" newline bitfld.long 0x8 23. "MID2_EN,Enable Master ID 2" "0,1" newline hexmask.long.byte 0x8 16.--22. 1. "MID2,Master ID 2" newline bitfld.long 0x8 15. "MID1_EN,Enable Master ID 1" "0,1" newline hexmask.long.byte 0x8 8.--14. 1. "MID1,Master ID 1" newline bitfld.long 0x8 7. "MID0_EN,Enable Master ID 0" "0,1" newline hexmask.long.byte 0x8 0.--6. 1. "MID0,Master ID 0" rgroup.long 0x30++0x3 line.long 0x0 "GLBL_HW_VER,Global Hardware Version register" hexmask.long 0x0 0.--31. 1. "NUM,Hardware Version Number" group.long 0x80++0xB line.long 0x0 "XB_Q_PRIORITY,ADCXBAR Queue Priority Assignment register" bitfld.long 0x0 4.--5. "Q1_PRIO_NUM,Queue1 Priority Number" "0,1,2,3" newline bitfld.long 0x0 0.--1. "Q0_PRIO_NUM,Queue0 Priority Number" "0,1,2,3" line.long 0x4 "XB_IRQ_CTRL,ADCXBAR Interrupt Control register" bitfld.long 0x4 0. "ADC_CNV_TO_ERR_IRQ_EN,ADC Conversion Timeout Error Interrupt Enable" "0,1" line.long 0x8 "XB_IRQ_STATUS,ADCXBAR Interrupt Status register" bitfld.long 0x8 0. "ADC_CNV_TO_ERR,ADC Conversion Timeout Error" "0,1" group.long 0x800++0xB line.long 0x0 "Q0_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 30. "AUX_ITF_SEL,Select Auxiliary Interface" "0,1" newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q0_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q0_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x80C++0x3 line.long 0x0 "Q0_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x810++0x3 line.long 0x0 "Q0_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x814++0x3 line.long 0x0 "Q0_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x818++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q0_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x820++0xF line.long 0x0 "Q0_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q0_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q0_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q0_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x830++0x3 line.long 0x0 "Q0_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x840++0x3 line.long 0x0 "Q0_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x860++0x3 line.long 0x0 "Q0_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" group.long 0x1000++0xB line.long 0x0 "Q1_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q1_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q1_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x100C++0x3 line.long 0x0 "Q1_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x1010++0x3 line.long 0x0 "Q1_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x1014++0x3 line.long 0x0 "Q1_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x1018++0x7 line.long 0x0 "Q1_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q1_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x1020++0xF line.long 0x0 "Q1_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q1_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q1_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q1_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x1030++0x3 line.long 0x0 "Q1_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x1040++0x3 line.long 0x0 "Q1_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x1060++0x3 line.long 0x0 "Q1_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" tree.end tree "SAR_ADCQ_12BIT_8" base ad:0x70338000 group.long 0x0++0x7 line.long 0x0 "GLBL_Q_SETUP,Global Setup register" bitfld.long 0x0 1. "DEBUG_EN,Debug Enable" "0: ADCQ in normal mode. No saving of FIFO pointers..,1: ADCQ in debug mode. Operation is frozen after.." newline bitfld.long 0x0 0. "SUSP_MODE,Suspension Mode" "0: The current cmd in active sequence is aborted..,1: The current cmd in active sequence is allowed to.." line.long 0x4 "GLBL_Q_CTRL,Global Control Register" bitfld.long 0x4 29. "Q1_DATAQ_DMA_ENABLE,Queue1 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 28. "Q0_DATAQ_DMA_ENABLE,Queue0 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 25. "Q1_CMDQ_DMA_ENABLE,Queue1 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 24. "Q0_CMDQ_DMA_ENABLE,Queue0 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 17. "Q1_RESET_CNTRS,Reset Queue1 Counters" "0,1" newline bitfld.long 0x4 16. "Q0_RESET_CNTRS,Reset Queue0 Counters" "0,1" newline bitfld.long 0x4 13. "Q1_ABORT,Abort Queue1" "0,1" newline bitfld.long 0x4 12. "Q0_ABORT,Abort Queue0" "0,1" newline bitfld.long 0x4 9. "Q1_FLUSH,Flush Queue1" "0,1" newline bitfld.long 0x4 8. "Q0_FLUSH,Flush Queue0" "0,1" newline bitfld.long 0x4 5. "Q1_SW_TRIG,Queue1 Software Trigger" "0,1" newline bitfld.long 0x4 4. "Q0_SW_TRIG,Queue0 Software Trigger" "0,1" newline bitfld.long 0x4 1. "Q1_TRIG_EN,Queue1 Trigger Enable" "0,1" newline bitfld.long 0x4 0. "Q0_TRIG_EN,Queue0 Trigger Enable" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "GLBL_Q_STATUS,Global Status register" hexmask.long.byte 0x0 8.--11. 1. "Q1_STATUS,These fields show the current state of the Queue1." newline hexmask.long.byte 0x0 0.--3. 1. "Q0_STATUS,These fields show the current state of the Queue0." group.long 0xC++0x3 line.long 0x0 "GLBL_IRQ_CTRL,Global IRQ Control register" bitfld.long 0x0 15. "XB_ERR_IRQ_EN,ADCXBAR Error Interrupt Enable" "0,1" newline bitfld.long 0x0 3. "Q1_ERR_IRQ_EN,Queue1 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "Q1_STAT_IRQ_EN,Queue1 Status Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "Q0_ERR_IRQ_EN,Queue0 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "Q0_STAT_IRQ_EN,Queue0 Status Interrupt Enable" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "GLBL_IRQ_STATUS,Global IRQ Status register" bitfld.long 0x0 15. "XB_ERR_IRQ,ADCXBAR Error Interrupt state" "0: ADCXBAR interrupt is not asserted.,1: ADCXBAR interrupt is asserted." newline bitfld.long 0x0 3. "Q1_ERR_IRQ,Queue1 Error Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 2. "Q1_STAT_IRQ,Queue1 Status Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 1. "Q0_ERR_IRQ,Queue0 Error Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." newline bitfld.long 0x0 0. "Q0_STAT_IRQ,Queue0 Status Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." group.long 0x14++0x3 line.long 0x0 "GLBL_OUTPUT,Global Output register" bitfld.long 0x0 4. "GLOBAL_OUT_Q_RST_CNTRS,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 3. "GLOBAL_OUT_Q_FLUSH,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 2. "GLOBAL_OUT_Q_ABORT,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 1. "GLOBAL_OUT_Q_SW_TRIG,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 0. "GLOBAL_OUT_Q_TRIG_EN,Whatever is written to this bit is reflected on the corresponding output pin. This can be used to provide a reset queue counters command to all participating queues across the ADCQs. Each queue can participate in this global.." "0,1" rgroup.long 0x18++0x7 line.long 0x0 "GLBL_CONFIG,Global Configuration register" hexmask.long.byte 0x0 8.--13. 1. "NUM_OF_TRIG_IN,Number of Input HW Triggers" newline bitfld.long 0x0 0.--2. "NUM_OF_QUEUES,Number of Queues" "?,1: Q0 queue supported,2: Q0 and Q1 supported,3: Q0 Q1 and Q2 supported,4: Q0 Q1 Q2 Q3 supported,?,?,?" line.long 0x4 "GLBL_ADC_IF_STATUS,Global ADC Interface Status register" hexmask.long.byte 0x4 20.--23. 1. "SUSPENDED_Q_NUM,Suspended Queues" newline hexmask.long.byte 0x4 8.--15. 1. "ACTIVE_ADC_CH_NUM,Current ADC CH Number" newline hexmask.long.byte 0x4 4.--7. 1. "ACTIVE_Q_NUM,Current Queue number" newline bitfld.long 0x4 0. "ADC_IF_BUSY,ADC Interface Busy" "0,1" group.long 0x20++0xB line.long 0x0 "GLBL_Q_MEAS_TIMER,Global Queue Measurement Timer register" hexmask.long.word 0x0 16.--31. 1. "DELTA_TMR_CURR_VAL,Current Value of ?T Counter" newline hexmask.long.word 0x0 0.--15. 1. "DELTA_TMR_RELOAD_VAL,Reload Value of ?T Counter" line.long 0x4 "GLBL_ADC_CNV_TIMEOUT,Global ADC Conversion Timeout register" hexmask.long.word 0x4 16.--31. 1. "ADC_CNV_CURR_VAL,Current value of timeout counter" newline hexmask.long.word 0x4 0.--15. 1. "ADC_CNV_RELOAD_VAL,Reload value of timeout counter" line.long 0x8 "GLBL_DMA_ID,Global DMA ID register" bitfld.long 0x8 31. "MID3_EN,Enable Master ID 3" "0,1" newline hexmask.long.byte 0x8 24.--30. 1. "MID3,Master ID 3" newline bitfld.long 0x8 23. "MID2_EN,Enable Master ID 2" "0,1" newline hexmask.long.byte 0x8 16.--22. 1. "MID2,Master ID 2" newline bitfld.long 0x8 15. "MID1_EN,Enable Master ID 1" "0,1" newline hexmask.long.byte 0x8 8.--14. 1. "MID1,Master ID 1" newline bitfld.long 0x8 7. "MID0_EN,Enable Master ID 0" "0,1" newline hexmask.long.byte 0x8 0.--6. 1. "MID0,Master ID 0" rgroup.long 0x30++0x3 line.long 0x0 "GLBL_HW_VER,Global Hardware Version register" hexmask.long 0x0 0.--31. 1. "NUM,Hardware Version Number" group.long 0x80++0xB line.long 0x0 "XB_Q_PRIORITY,ADCXBAR Queue Priority Assignment register" bitfld.long 0x0 4.--5. "Q1_PRIO_NUM,Queue1 Priority Number" "0,1,2,3" newline bitfld.long 0x0 0.--1. "Q0_PRIO_NUM,Queue0 Priority Number" "0,1,2,3" line.long 0x4 "XB_IRQ_CTRL,ADCXBAR Interrupt Control register" bitfld.long 0x4 0. "ADC_CNV_TO_ERR_IRQ_EN,ADC Conversion Timeout Error Interrupt Enable" "0,1" line.long 0x8 "XB_IRQ_STATUS,ADCXBAR Interrupt Status register" bitfld.long 0x8 0. "ADC_CNV_TO_ERR,ADC Conversion Timeout Error" "0,1" group.long 0x800++0xB line.long 0x0 "Q0_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 30. "AUX_ITF_SEL,Select Auxiliary Interface" "0,1" newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q0_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q0_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x80C++0x3 line.long 0x0 "Q0_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x810++0x3 line.long 0x0 "Q0_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x814++0x3 line.long 0x0 "Q0_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x818++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q0_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x820++0xF line.long 0x0 "Q0_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q0_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q0_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q0_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x830++0x3 line.long 0x0 "Q0_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x840++0x3 line.long 0x0 "Q0_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x860++0x3 line.long 0x0 "Q0_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" group.long 0x1000++0xB line.long 0x0 "Q1_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q1_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q1_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x100C++0x3 line.long 0x0 "Q1_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x1010++0x3 line.long 0x0 "Q1_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x1014++0x3 line.long 0x0 "Q1_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x1018++0x7 line.long 0x0 "Q1_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q1_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x1020++0xF line.long 0x0 "Q1_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q1_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q1_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q1_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x1030++0x3 line.long 0x0 "Q1_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x1040++0x3 line.long 0x0 "Q1_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x1060++0x3 line.long 0x0 "Q1_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" tree.end tree "SAR_ADCQ_12BIT_9" base ad:0x70938000 group.long 0x0++0x7 line.long 0x0 "GLBL_Q_SETUP,Global Setup register" bitfld.long 0x0 1. "DEBUG_EN,Debug Enable" "0: ADCQ in normal mode. No saving of FIFO pointers..,1: ADCQ in debug mode. Operation is frozen after.." newline bitfld.long 0x0 0. "SUSP_MODE,Suspension Mode" "0: The current cmd in active sequence is aborted..,1: The current cmd in active sequence is allowed to.." line.long 0x4 "GLBL_Q_CTRL,Global Control Register" bitfld.long 0x4 29. "Q1_DATAQ_DMA_ENABLE,Queue1 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 28. "Q0_DATAQ_DMA_ENABLE,Queue0 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 25. "Q1_CMDQ_DMA_ENABLE,Queue1 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 24. "Q0_CMDQ_DMA_ENABLE,Queue0 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 17. "Q1_RESET_CNTRS,Reset Queue1 Counters" "0,1" newline bitfld.long 0x4 16. "Q0_RESET_CNTRS,Reset Queue0 Counters" "0,1" newline bitfld.long 0x4 13. "Q1_ABORT,Abort Queue1" "0,1" newline bitfld.long 0x4 12. "Q0_ABORT,Abort Queue0" "0,1" newline bitfld.long 0x4 9. "Q1_FLUSH,Flush Queue1" "0,1" newline bitfld.long 0x4 8. "Q0_FLUSH,Flush Queue0" "0,1" newline bitfld.long 0x4 5. "Q1_SW_TRIG,Queue1 Software Trigger" "0,1" newline bitfld.long 0x4 4. "Q0_SW_TRIG,Queue0 Software Trigger" "0,1" newline bitfld.long 0x4 1. "Q1_TRIG_EN,Queue1 Trigger Enable" "0,1" newline bitfld.long 0x4 0. "Q0_TRIG_EN,Queue0 Trigger Enable" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "GLBL_Q_STATUS,Global Status register" hexmask.long.byte 0x0 8.--11. 1. "Q1_STATUS,These fields show the current state of the Queue1." newline hexmask.long.byte 0x0 0.--3. 1. "Q0_STATUS,These fields show the current state of the Queue0." group.long 0xC++0x3 line.long 0x0 "GLBL_IRQ_CTRL,Global IRQ Control register" bitfld.long 0x0 15. "XB_ERR_IRQ_EN,ADCXBAR Error Interrupt Enable" "0,1" newline bitfld.long 0x0 3. "Q1_ERR_IRQ_EN,Queue1 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "Q1_STAT_IRQ_EN,Queue1 Status Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "Q0_ERR_IRQ_EN,Queue0 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "Q0_STAT_IRQ_EN,Queue0 Status Interrupt Enable" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "GLBL_IRQ_STATUS,Global IRQ Status register" bitfld.long 0x0 15. "XB_ERR_IRQ,ADCXBAR Error Interrupt state" "0: ADCXBAR interrupt is not asserted.,1: ADCXBAR interrupt is asserted." newline bitfld.long 0x0 3. "Q1_ERR_IRQ,Queue1 Error Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 2. "Q1_STAT_IRQ,Queue1 Status Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 1. "Q0_ERR_IRQ,Queue0 Error Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." newline bitfld.long 0x0 0. "Q0_STAT_IRQ,Queue0 Status Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." group.long 0x14++0x3 line.long 0x0 "GLBL_OUTPUT,Global Output register" bitfld.long 0x0 4. "GLOBAL_OUT_Q_RST_CNTRS,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 3. "GLOBAL_OUT_Q_FLUSH,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 2. "GLOBAL_OUT_Q_ABORT,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 1. "GLOBAL_OUT_Q_SW_TRIG,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 0. "GLOBAL_OUT_Q_TRIG_EN,Whatever is written to this bit is reflected on the corresponding output pin. This can be used to provide a reset queue counters command to all participating queues across the ADCQs. Each queue can participate in this global.." "0,1" rgroup.long 0x18++0x7 line.long 0x0 "GLBL_CONFIG,Global Configuration register" hexmask.long.byte 0x0 8.--13. 1. "NUM_OF_TRIG_IN,Number of Input HW Triggers" newline bitfld.long 0x0 0.--2. "NUM_OF_QUEUES,Number of Queues" "?,1: Q0 queue supported,2: Q0 and Q1 supported,3: Q0 Q1 and Q2 supported,4: Q0 Q1 Q2 Q3 supported,?,?,?" line.long 0x4 "GLBL_ADC_IF_STATUS,Global ADC Interface Status register" hexmask.long.byte 0x4 20.--23. 1. "SUSPENDED_Q_NUM,Suspended Queues" newline hexmask.long.byte 0x4 8.--15. 1. "ACTIVE_ADC_CH_NUM,Current ADC CH Number" newline hexmask.long.byte 0x4 4.--7. 1. "ACTIVE_Q_NUM,Current Queue number" newline bitfld.long 0x4 0. "ADC_IF_BUSY,ADC Interface Busy" "0,1" group.long 0x20++0xB line.long 0x0 "GLBL_Q_MEAS_TIMER,Global Queue Measurement Timer register" hexmask.long.word 0x0 16.--31. 1. "DELTA_TMR_CURR_VAL,Current Value of ?T Counter" newline hexmask.long.word 0x0 0.--15. 1. "DELTA_TMR_RELOAD_VAL,Reload Value of ?T Counter" line.long 0x4 "GLBL_ADC_CNV_TIMEOUT,Global ADC Conversion Timeout register" hexmask.long.word 0x4 16.--31. 1. "ADC_CNV_CURR_VAL,Current value of timeout counter" newline hexmask.long.word 0x4 0.--15. 1. "ADC_CNV_RELOAD_VAL,Reload value of timeout counter" line.long 0x8 "GLBL_DMA_ID,Global DMA ID register" bitfld.long 0x8 31. "MID3_EN,Enable Master ID 3" "0,1" newline hexmask.long.byte 0x8 24.--30. 1. "MID3,Master ID 3" newline bitfld.long 0x8 23. "MID2_EN,Enable Master ID 2" "0,1" newline hexmask.long.byte 0x8 16.--22. 1. "MID2,Master ID 2" newline bitfld.long 0x8 15. "MID1_EN,Enable Master ID 1" "0,1" newline hexmask.long.byte 0x8 8.--14. 1. "MID1,Master ID 1" newline bitfld.long 0x8 7. "MID0_EN,Enable Master ID 0" "0,1" newline hexmask.long.byte 0x8 0.--6. 1. "MID0,Master ID 0" rgroup.long 0x30++0x3 line.long 0x0 "GLBL_HW_VER,Global Hardware Version register" hexmask.long 0x0 0.--31. 1. "NUM,Hardware Version Number" group.long 0x80++0xB line.long 0x0 "XB_Q_PRIORITY,ADCXBAR Queue Priority Assignment register" bitfld.long 0x0 4.--5. "Q1_PRIO_NUM,Queue1 Priority Number" "0,1,2,3" newline bitfld.long 0x0 0.--1. "Q0_PRIO_NUM,Queue0 Priority Number" "0,1,2,3" line.long 0x4 "XB_IRQ_CTRL,ADCXBAR Interrupt Control register" bitfld.long 0x4 0. "ADC_CNV_TO_ERR_IRQ_EN,ADC Conversion Timeout Error Interrupt Enable" "0,1" line.long 0x8 "XB_IRQ_STATUS,ADCXBAR Interrupt Status register" bitfld.long 0x8 0. "ADC_CNV_TO_ERR,ADC Conversion Timeout Error" "0,1" group.long 0x800++0xB line.long 0x0 "Q0_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 30. "AUX_ITF_SEL,Select Auxiliary Interface" "0,1" newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q0_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q0_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x80C++0x3 line.long 0x0 "Q0_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x810++0x3 line.long 0x0 "Q0_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x814++0x3 line.long 0x0 "Q0_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x818++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q0_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x820++0xF line.long 0x0 "Q0_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q0_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q0_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q0_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x830++0x3 line.long 0x0 "Q0_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x840++0x3 line.long 0x0 "Q0_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x860++0x3 line.long 0x0 "Q0_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" group.long 0x1000++0xB line.long 0x0 "Q1_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q1_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q1_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x100C++0x3 line.long 0x0 "Q1_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x1010++0x3 line.long 0x0 "Q1_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x1014++0x3 line.long 0x0 "Q1_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x1018++0x7 line.long 0x0 "Q1_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q1_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x1020++0xF line.long 0x0 "Q1_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q1_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q1_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q1_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x1030++0x3 line.long 0x0 "Q1_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x1040++0x3 line.long 0x0 "Q1_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x1060++0x3 line.long 0x0 "Q1_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" tree.end tree "SAR_ADCQ_12BIT_10" base ad:0x7033C000 group.long 0x0++0x7 line.long 0x0 "GLBL_Q_SETUP,Global Setup register" bitfld.long 0x0 1. "DEBUG_EN,Debug Enable" "0: ADCQ in normal mode. No saving of FIFO pointers..,1: ADCQ in debug mode. Operation is frozen after.." newline bitfld.long 0x0 0. "SUSP_MODE,Suspension Mode" "0: The current cmd in active sequence is aborted..,1: The current cmd in active sequence is allowed to.." line.long 0x4 "GLBL_Q_CTRL,Global Control Register" bitfld.long 0x4 29. "Q1_DATAQ_DMA_ENABLE,Queue1 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 28. "Q0_DATAQ_DMA_ENABLE,Queue0 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 25. "Q1_CMDQ_DMA_ENABLE,Queue1 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 24. "Q0_CMDQ_DMA_ENABLE,Queue0 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 17. "Q1_RESET_CNTRS,Reset Queue1 Counters" "0,1" newline bitfld.long 0x4 16. "Q0_RESET_CNTRS,Reset Queue0 Counters" "0,1" newline bitfld.long 0x4 13. "Q1_ABORT,Abort Queue1" "0,1" newline bitfld.long 0x4 12. "Q0_ABORT,Abort Queue0" "0,1" newline bitfld.long 0x4 9. "Q1_FLUSH,Flush Queue1" "0,1" newline bitfld.long 0x4 8. "Q0_FLUSH,Flush Queue0" "0,1" newline bitfld.long 0x4 5. "Q1_SW_TRIG,Queue1 Software Trigger" "0,1" newline bitfld.long 0x4 4. "Q0_SW_TRIG,Queue0 Software Trigger" "0,1" newline bitfld.long 0x4 1. "Q1_TRIG_EN,Queue1 Trigger Enable" "0,1" newline bitfld.long 0x4 0. "Q0_TRIG_EN,Queue0 Trigger Enable" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "GLBL_Q_STATUS,Global Status register" hexmask.long.byte 0x0 8.--11. 1. "Q1_STATUS,These fields show the current state of the Queue1." newline hexmask.long.byte 0x0 0.--3. 1. "Q0_STATUS,These fields show the current state of the Queue0." group.long 0xC++0x3 line.long 0x0 "GLBL_IRQ_CTRL,Global IRQ Control register" bitfld.long 0x0 15. "XB_ERR_IRQ_EN,ADCXBAR Error Interrupt Enable" "0,1" newline bitfld.long 0x0 3. "Q1_ERR_IRQ_EN,Queue1 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "Q1_STAT_IRQ_EN,Queue1 Status Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "Q0_ERR_IRQ_EN,Queue0 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "Q0_STAT_IRQ_EN,Queue0 Status Interrupt Enable" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "GLBL_IRQ_STATUS,Global IRQ Status register" bitfld.long 0x0 15. "XB_ERR_IRQ,ADCXBAR Error Interrupt state" "0: ADCXBAR interrupt is not asserted.,1: ADCXBAR interrupt is asserted." newline bitfld.long 0x0 3. "Q1_ERR_IRQ,Queue1 Error Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 2. "Q1_STAT_IRQ,Queue1 Status Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 1. "Q0_ERR_IRQ,Queue0 Error Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." newline bitfld.long 0x0 0. "Q0_STAT_IRQ,Queue0 Status Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." group.long 0x14++0x3 line.long 0x0 "GLBL_OUTPUT,Global Output register" bitfld.long 0x0 4. "GLOBAL_OUT_Q_RST_CNTRS,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 3. "GLOBAL_OUT_Q_FLUSH,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 2. "GLOBAL_OUT_Q_ABORT,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 1. "GLOBAL_OUT_Q_SW_TRIG,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 0. "GLOBAL_OUT_Q_TRIG_EN,Whatever is written to this bit is reflected on the corresponding output pin. This can be used to provide a reset queue counters command to all participating queues across the ADCQs. Each queue can participate in this global.." "0,1" rgroup.long 0x18++0x7 line.long 0x0 "GLBL_CONFIG,Global Configuration register" hexmask.long.byte 0x0 8.--13. 1. "NUM_OF_TRIG_IN,Number of Input HW Triggers" newline bitfld.long 0x0 0.--2. "NUM_OF_QUEUES,Number of Queues" "?,1: Q0 queue supported,2: Q0 and Q1 supported,3: Q0 Q1 and Q2 supported,4: Q0 Q1 Q2 Q3 supported,?,?,?" line.long 0x4 "GLBL_ADC_IF_STATUS,Global ADC Interface Status register" hexmask.long.byte 0x4 20.--23. 1. "SUSPENDED_Q_NUM,Suspended Queues" newline hexmask.long.byte 0x4 8.--15. 1. "ACTIVE_ADC_CH_NUM,Current ADC CH Number" newline hexmask.long.byte 0x4 4.--7. 1. "ACTIVE_Q_NUM,Current Queue number" newline bitfld.long 0x4 0. "ADC_IF_BUSY,ADC Interface Busy" "0,1" group.long 0x20++0xB line.long 0x0 "GLBL_Q_MEAS_TIMER,Global Queue Measurement Timer register" hexmask.long.word 0x0 16.--31. 1. "DELTA_TMR_CURR_VAL,Current Value of ?T Counter" newline hexmask.long.word 0x0 0.--15. 1. "DELTA_TMR_RELOAD_VAL,Reload Value of ?T Counter" line.long 0x4 "GLBL_ADC_CNV_TIMEOUT,Global ADC Conversion Timeout register" hexmask.long.word 0x4 16.--31. 1. "ADC_CNV_CURR_VAL,Current value of timeout counter" newline hexmask.long.word 0x4 0.--15. 1. "ADC_CNV_RELOAD_VAL,Reload value of timeout counter" line.long 0x8 "GLBL_DMA_ID,Global DMA ID register" bitfld.long 0x8 31. "MID3_EN,Enable Master ID 3" "0,1" newline hexmask.long.byte 0x8 24.--30. 1. "MID3,Master ID 3" newline bitfld.long 0x8 23. "MID2_EN,Enable Master ID 2" "0,1" newline hexmask.long.byte 0x8 16.--22. 1. "MID2,Master ID 2" newline bitfld.long 0x8 15. "MID1_EN,Enable Master ID 1" "0,1" newline hexmask.long.byte 0x8 8.--14. 1. "MID1,Master ID 1" newline bitfld.long 0x8 7. "MID0_EN,Enable Master ID 0" "0,1" newline hexmask.long.byte 0x8 0.--6. 1. "MID0,Master ID 0" rgroup.long 0x30++0x3 line.long 0x0 "GLBL_HW_VER,Global Hardware Version register" hexmask.long 0x0 0.--31. 1. "NUM,Hardware Version Number" group.long 0x80++0xB line.long 0x0 "XB_Q_PRIORITY,ADCXBAR Queue Priority Assignment register" bitfld.long 0x0 4.--5. "Q1_PRIO_NUM,Queue1 Priority Number" "0,1,2,3" newline bitfld.long 0x0 0.--1. "Q0_PRIO_NUM,Queue0 Priority Number" "0,1,2,3" line.long 0x4 "XB_IRQ_CTRL,ADCXBAR Interrupt Control register" bitfld.long 0x4 0. "ADC_CNV_TO_ERR_IRQ_EN,ADC Conversion Timeout Error Interrupt Enable" "0,1" line.long 0x8 "XB_IRQ_STATUS,ADCXBAR Interrupt Status register" bitfld.long 0x8 0. "ADC_CNV_TO_ERR,ADC Conversion Timeout Error" "0,1" group.long 0x800++0xB line.long 0x0 "Q0_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 30. "AUX_ITF_SEL,Select Auxiliary Interface" "0,1" newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q0_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q0_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x80C++0x3 line.long 0x0 "Q0_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x810++0x3 line.long 0x0 "Q0_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x814++0x3 line.long 0x0 "Q0_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x818++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q0_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x820++0xF line.long 0x0 "Q0_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q0_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q0_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q0_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x830++0x3 line.long 0x0 "Q0_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x840++0x3 line.long 0x0 "Q0_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x860++0x3 line.long 0x0 "Q0_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" group.long 0x1000++0xB line.long 0x0 "Q1_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q1_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q1_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x100C++0x3 line.long 0x0 "Q1_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x1010++0x3 line.long 0x0 "Q1_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x1014++0x3 line.long 0x0 "Q1_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x1018++0x7 line.long 0x0 "Q1_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q1_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x1020++0xF line.long 0x0 "Q1_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q1_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q1_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q1_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x1030++0x3 line.long 0x0 "Q1_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x1040++0x3 line.long 0x0 "Q1_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x1060++0x3 line.long 0x0 "Q1_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" tree.end tree "SAR_ADCQ_12BIT_SV_0" base ad:0x70324000 group.long 0x0++0x7 line.long 0x0 "GLBL_Q_SETUP,Global Setup register" bitfld.long 0x0 1. "DEBUG_EN,Debug Enable" "0: ADCQ in normal mode. No saving of FIFO pointers..,1: ADCQ in debug mode. Operation is frozen after.." newline bitfld.long 0x0 0. "SUSP_MODE,Suspension Mode" "0: The current cmd in active sequence is aborted..,1: The current cmd in active sequence is allowed to.." line.long 0x4 "GLBL_Q_CTRL,Global Control Register" bitfld.long 0x4 29. "Q1_DATAQ_DMA_ENABLE,Queue1 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 28. "Q0_DATAQ_DMA_ENABLE,Queue0 DATAQ DMA Enable" "0: DATAQ DMA Interface is disabled.,1: DATAQ DMA Interface is enabled." newline bitfld.long 0x4 25. "Q1_CMDQ_DMA_ENABLE,Queue1 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 24. "Q0_CMDQ_DMA_ENABLE,Queue0 CMDQ DMA Enable" "0: CMDQ DMA Interface is disabled.,1: CMDQ DMA Interface is enabled." newline bitfld.long 0x4 17. "Q1_RESET_CNTRS,Reset Queue1 Counters" "0,1" newline bitfld.long 0x4 16. "Q0_RESET_CNTRS,Reset Queue0 Counters" "0,1" newline bitfld.long 0x4 13. "Q1_ABORT,Abort Queue1" "0,1" newline bitfld.long 0x4 12. "Q0_ABORT,Abort Queue0" "0,1" newline bitfld.long 0x4 9. "Q1_FLUSH,Flush Queue1" "0,1" newline bitfld.long 0x4 8. "Q0_FLUSH,Flush Queue0" "0,1" newline bitfld.long 0x4 5. "Q1_SW_TRIG,Queue1 Software Trigger" "0,1" newline bitfld.long 0x4 4. "Q0_SW_TRIG,Queue0 Software Trigger" "0,1" newline bitfld.long 0x4 1. "Q1_TRIG_EN,Queue1 Trigger Enable" "0,1" newline bitfld.long 0x4 0. "Q0_TRIG_EN,Queue0 Trigger Enable" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "GLBL_Q_STATUS,Global Status register" hexmask.long.byte 0x0 8.--11. 1. "Q1_STATUS,These fields show the current state of the Queue1." newline hexmask.long.byte 0x0 0.--3. 1. "Q0_STATUS,These fields show the current state of the Queue0." group.long 0xC++0x3 line.long 0x0 "GLBL_IRQ_CTRL,Global IRQ Control register" bitfld.long 0x0 15. "XB_ERR_IRQ_EN,ADCXBAR Error Interrupt Enable" "0,1" newline bitfld.long 0x0 3. "Q1_ERR_IRQ_EN,Queue1 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "Q1_STAT_IRQ_EN,Queue1 Status Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "Q0_ERR_IRQ_EN,Queue0 Error Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "Q0_STAT_IRQ_EN,Queue0 Status Interrupt Enable" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "GLBL_IRQ_STATUS,Global IRQ Status register" bitfld.long 0x0 15. "XB_ERR_IRQ,ADCXBAR Error Interrupt state" "0: ADCXBAR interrupt is not asserted.,1: ADCXBAR interrupt is asserted." newline bitfld.long 0x0 3. "Q1_ERR_IRQ,Queue1 Error Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 2. "Q1_STAT_IRQ,Queue1 Status Interrupt state" "0: Queue1 interrupt is not asserted.,1: Queue1 interrupt is asserted." newline bitfld.long 0x0 1. "Q0_ERR_IRQ,Queue0 Error Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." newline bitfld.long 0x0 0. "Q0_STAT_IRQ,Queue0 Status Interrupt state" "0: Queue0 interrupt is not asserted.,1: Queue0 interrupt is asserted." group.long 0x14++0x3 line.long 0x0 "GLBL_OUTPUT,Global Output register" bitfld.long 0x0 4. "GLOBAL_OUT_Q_RST_CNTRS,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 3. "GLOBAL_OUT_Q_FLUSH,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 2. "GLOBAL_OUT_Q_ABORT,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 1. "GLOBAL_OUT_Q_SW_TRIG,Whatever is written to this bit is reflected on the corresponding output pin." "0,1" newline bitfld.long 0x0 0. "GLOBAL_OUT_Q_TRIG_EN,Whatever is written to this bit is reflected on the corresponding output pin. This can be used to provide a reset queue counters command to all participating queues across the ADCQs. Each queue can participate in this global.." "0,1" rgroup.long 0x18++0x7 line.long 0x0 "GLBL_CONFIG,Global Configuration register" hexmask.long.byte 0x0 8.--13. 1. "NUM_OF_TRIG_IN,Number of Input HW Triggers" newline bitfld.long 0x0 0.--2. "NUM_OF_QUEUES,Number of Queues" "?,1: Q0 queue supported,2: Q0 and Q1 supported,3: Q0 Q1 and Q2 supported,4: Q0 Q1 Q2 Q3 supported,?,?,?" line.long 0x4 "GLBL_ADC_IF_STATUS,Global ADC Interface Status register" hexmask.long.byte 0x4 20.--23. 1. "SUSPENDED_Q_NUM,Suspended Queues" newline hexmask.long.byte 0x4 8.--15. 1. "ACTIVE_ADC_CH_NUM,Current ADC CH Number" newline hexmask.long.byte 0x4 4.--7. 1. "ACTIVE_Q_NUM,Current Queue number" newline bitfld.long 0x4 0. "ADC_IF_BUSY,ADC Interface Busy" "0,1" group.long 0x20++0xB line.long 0x0 "GLBL_Q_MEAS_TIMER,Global Queue Measurement Timer register" hexmask.long.word 0x0 16.--31. 1. "DELTA_TMR_CURR_VAL,Current Value of ?T Counter" newline hexmask.long.word 0x0 0.--15. 1. "DELTA_TMR_RELOAD_VAL,Reload Value of ?T Counter" line.long 0x4 "GLBL_ADC_CNV_TIMEOUT,Global ADC Conversion Timeout register" hexmask.long.word 0x4 16.--31. 1. "ADC_CNV_CURR_VAL,Current value of timeout counter" newline hexmask.long.word 0x4 0.--15. 1. "ADC_CNV_RELOAD_VAL,Reload value of timeout counter" line.long 0x8 "GLBL_DMA_ID,Global DMA ID register" bitfld.long 0x8 31. "MID3_EN,Enable Master ID 3" "0,1" newline hexmask.long.byte 0x8 24.--30. 1. "MID3,Master ID 3" newline bitfld.long 0x8 23. "MID2_EN,Enable Master ID 2" "0,1" newline hexmask.long.byte 0x8 16.--22. 1. "MID2,Master ID 2" newline bitfld.long 0x8 15. "MID1_EN,Enable Master ID 1" "0,1" newline hexmask.long.byte 0x8 8.--14. 1. "MID1,Master ID 1" newline bitfld.long 0x8 7. "MID0_EN,Enable Master ID 0" "0,1" newline hexmask.long.byte 0x8 0.--6. 1. "MID0,Master ID 0" rgroup.long 0x30++0x3 line.long 0x0 "GLBL_HW_VER,Global Hardware Version register" hexmask.long 0x0 0.--31. 1. "NUM,Hardware Version Number" group.long 0x80++0xB line.long 0x0 "XB_Q_PRIORITY,ADCXBAR Queue Priority Assignment register" bitfld.long 0x0 4.--5. "Q1_PRIO_NUM,Queue1 Priority Number" "0,1,2,3" newline bitfld.long 0x0 0.--1. "Q0_PRIO_NUM,Queue0 Priority Number" "0,1,2,3" line.long 0x4 "XB_IRQ_CTRL,ADCXBAR Interrupt Control register" bitfld.long 0x4 0. "ADC_CNV_TO_ERR_IRQ_EN,ADC Conversion Timeout Error Interrupt Enable" "0,1" line.long 0x8 "XB_IRQ_STATUS,ADCXBAR Interrupt Status register" bitfld.long 0x8 0. "ADC_CNV_TO_ERR,ADC Conversion Timeout Error" "0,1" group.long 0x800++0xB line.long 0x0 "Q0_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 30. "AUX_ITF_SEL,Select Auxiliary Interface" "0,1" newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q0_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q0_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x80C++0x3 line.long 0x0 "Q0_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x810++0x3 line.long 0x0 "Q0_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x814++0x3 line.long 0x0 "Q0_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x818++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q0_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x820++0xF line.long 0x0 "Q0_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q0_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q0_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q0_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x830++0x3 line.long 0x0 "Q0_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x840++0x3 line.long 0x0 "Q0_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x860++0x3 line.long 0x0 "Q0_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" group.long 0x1000++0xB line.long 0x0 "Q1_SETUP,Queue Setup register" bitfld.long 0x0 31. "ALIGN_DATA,Align Conversion Data in DATAQ" "0: ADC Conversion Result is stored in Left Aligned..,1: ADC Conversion Result is stored in Right Aligned.." newline bitfld.long 0x0 28. "UNMSK_GLBL_CNTR_RST,Unmask Global Reset Queue Counters" "0: The global queue counters reset input of the..,1: The queue participates in the global queue.." newline bitfld.long 0x0 27. "UNMSK_GLBL_FLUSH,Unmask Global Flush" "0: The global flush input of the queue is masked..,1: The queue participates in the global queue flush.." newline bitfld.long 0x0 26. "UNMSK_GLBL_ABORT,Unmask Global Abort" "0: The global abort input of the queue is masked..,1: The queue participates in the global queue abort.." newline bitfld.long 0x0 25. "UNMSK_GLBL_SW_TRIG,Unmask Global Software Trigger" "0: The global SW trigger is masked for the queue..,1: The queue participates in the global software.." newline bitfld.long 0x0 24. "UNMSK_GLBL_TRIG_EN,Unmask Global Software Trigger" "0: The global trigger enable input of the queue is..,1: The queue participates in the global trigger.." newline hexmask.long.byte 0x0 16.--23. 1. "CMDQ_WM,CMDQ watermark level" newline bitfld.long 0x0 10. "DQ_SEQ_STATUS_EN,DATAQ Sequence Status Enable" "0: Disable appending of the sequence status to the..,1: Enable appending of the sequence status to the.." newline bitfld.long 0x0 9. "DQ_TRIGGER_TS_EN,Unmask Global Software Trigger" "0: Disable the timestamp capture for the trigger..,1: Enable the timestamp capture for the trigger.." newline bitfld.long 0x0 8. "DQ_CAPTURE_TS_EN,DATAQ Capture TS Enable" "0: Disable the timestamp capture for the ADC data..,1: Enable the timestamp capture for the ADC data in.." newline hexmask.long.byte 0x0 0.--7. 1. "DATAQ_WM,DATAQ watermark level" line.long 0x4 "Q1_RISE,Queue Rise edge enable register" hexmask.long 0x4 0.--31. 1. "RISE_EDG_EN,Rising Edge Enable for HW Trig" line.long 0x8 "Q1_FALL,Queue Fall edge enable register" hexmask.long 0x8 0.--31. 1. "FALL_EDG_EN,Falling Edge Enable for HW Trig" rgroup.long 0x100C++0x3 line.long 0x0 "Q1_CONFIG,Queue Configuration register" bitfld.long 0x0 30. "AUX_ITF_PRESENT,AUX interface present" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DEPTH_DATAQ,Depth of DATAQ" newline hexmask.long.byte 0x0 0.--7. 1. "DEPTH_CMDQ,Depth of CMDQ" group.long 0x1010++0x3 line.long 0x0 "Q1_CTRL,Queue Control register" bitfld.long 0x0 7. "Q_SCAN_MODE_STOP,Queue Scan Mode Stop" "0,1" newline bitfld.long 0x0 6. "Q_DATAQ_DMA_ENABLE,Queue DATAQ DMA Enable" "0: DATAQ DMA disabled.,1: DATAQ DMA enabled." newline bitfld.long 0x0 5. "Q_CMDQ_DMA_ENABLE,Queue CMDQ DMA Enable" "0: CMDQ DMA disabled.,1: CMDQ DMA enabled." newline bitfld.long 0x0 4. "Q_RESET_CNTRS,Queue Reset Counters" "0,1" newline bitfld.long 0x0 3. "Q_FLUSH,Queue Flush" "0,1" newline bitfld.long 0x0 2. "Q_ABORT,Queue Abort" "0,1" newline bitfld.long 0x0 1. "Q_SW_TRIGGER,Queue Software Trigger" "0,1" newline bitfld.long 0x0 0. "Q_TRIG_EN,Queue Trigger Enable" "0: Disable the queue trigger.,1: Enable the queue to be triggered either by the.." rgroup.long 0x1014++0x3 line.long 0x0 "Q1_STATE,Queue Status register" hexmask.long.byte 0x0 0.--3. 1. "Q_STATE,Queue State" group.long 0x1018++0x7 line.long 0x0 "Q1_IRQ_CTRL,Queue IRQ control register" bitfld.long 0x0 31. "FIFO_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register" "0,1" newline bitfld.long 0x0 21. "CMD_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 20. "SEQ_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 19. "SEQ_ADC_CNTR_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 18. "TRIG_NO_SEQ_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 17. "TRIG_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 16. "TRIG_PENDING_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 12. "DATAQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 11. "DATAQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 10. "DATAQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 9. "DATAQ_ABOVE_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 8. "DATAQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 6. "END_OF_CH_CONV_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 5. "END_OF_SEQ_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 4. "CMDQ_UNDRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 3. "CMDQ_OVRN_ERR_IRQ_EN,Enables the assertion of the error interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 2. "CMDQ_FULL_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 1. "CMDQ_BELOW_WM_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" newline bitfld.long 0x0 0. "CMDQ_EMPTY_IRQ_EN,Enables the assertion of the status interrupt when the corresponding bit is set in the Q_IRQ_STATUS register." "0,1" line.long 0x4 "Q1_IRQ_STATUS,Queue IRQ Status register" bitfld.long 0x4 31. "FIFO_ERR,When set it indicates the malfunctioning of the CMDQ or DATAQ FIFO logic. Follow the ABORT or FLUSH procedure for recovery (refer to Section1.4: Functional description for details)." "0,1" newline bitfld.long 0x4 21. "CMDQ_CNTR_OVRN_ERR,This bit is set when the command counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 20. "SEQ_CNTR_OVRN_ERR,This bit is set when the sequence counter wraps around if the SW does not clear this counter periodically." "0,1" newline bitfld.long 0x4 19. "SEQ_ADC_CNTR_OVRN_ERR,This bit is set when the sequence ADC command counter wraps around.This can either be caused by a SW programming error in defining a very long measurement sequence or a design error." "0,1" newline bitfld.long 0x4 18. "TRIG_NO_SEQ_ERR,This bit is set in following two cases" "0,1" newline bitfld.long 0x4 17. "TRIG_OVRN_ERR,This bit is set when a trigger is already pending and a new one is detected while the CMDQ is executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 16. "TRIG_PENDING,This bit is set when a new trigger occurs while the CMDQ is already executing a measurement sequence of a previous trigger." "0,1" newline bitfld.long 0x4 12. "DATAQ_UNDRN_ERR,This bit is set when the system tries to read data from the DATAQ even when the DATAQ is empty." "0,1" newline bitfld.long 0x4 11. "DATAQ_OVRN_ERR,This bit is set when there is no space in the DATAQ and a new ADC DATA arrives. The new data does not overwrite any previous data and is lost." "0,1" newline bitfld.long 0x4 10. "DATAQ_FULL,This bit is set when the DATAQ is full and it can take no more data." "0,1" newline bitfld.long 0x4 9. "DATAQ_ABOVE_WM,This bit is set when the number of entries in the DATAQ is superior or equals the DATAQ water mark level." "0,1" newline bitfld.long 0x4 8. "DATAQ_EMPTY,This bit is set when the DATAQ is empty otherwise it is 0 when any unread data is present in the DATAQ." "0,1" newline bitfld.long 0x4 6. "END_OF_CH_CONV,This bit is set on completion of every ADC channel conversion." "0,1" newline bitfld.long 0x4 5. "END_OF_SEQ,This bit is set when a measurement sequence is completed which is when the last command of the sequence has completed its execution and the queue moves to WAITING_FOR_TRIGGER state." "0,1" newline bitfld.long 0x4 4. "CMDQ_UNDRN_ERR,This bit is set when the auxiliary read interface tries to read data from the CMDQ even when the CMDQ is empty." "0,1" newline bitfld.long 0x4 3. "CMDQ_OVRN_ERR,This bit is set when there is no space in the CMDQ and the system tries to push a new ADC command. The new command does not overwrite any previous entry and is lost." "0,1" newline bitfld.long 0x4 2. "CMDQ_FULL,This bit is set when the CMDQ is full and it can take no more commands." "0,1" newline bitfld.long 0x4 1. "CMDQ_BELOW_WM,This bit is set when number of free entries in the CMDQ is >= the CMDQ water mark level." "0,1" newline bitfld.long 0x4 0. "CMDQ_EMPTY,This bit is set when the CMDQ is empty otherwise it is 0 when any valid entry exists in the CMDQ." "0,1" rgroup.long 0x1020++0xF line.long 0x0 "Q1_CMD_CNTR,Queue Command Counter register" hexmask.long.word 0x0 16.--31. 1. "SEQ_CNTR,Sequence Counter Value" newline hexmask.long.word 0x0 0.--15. 1. "CMD_CNTR,Command Counter Value" line.long 0x4 "Q1_SEQ_STATUS,Queue Sequence Status register" hexmask.long.byte 0x4 0.--7. 1. "SEQ_ADC_CNTR,ADC command in sequence counter value" line.long 0x8 "Q1_CMDQ_POINTERS,Queue CMDQ Pointers register" hexmask.long.word 0x8 16.--24. 1. "CMDQ_ACTIVE_ENTRIES,CMDQ active entries" newline hexmask.long.byte 0x8 8.--15. 1. "CMDQ_WR_PTR,CMDQ write pointer" newline hexmask.long.byte 0x8 0.--7. 1. "CMDQ_RD_PTR,CMDQ read pointer" line.long 0xC "Q1_DATAQ_POINTERS,Queue DATAQ Pointers register" hexmask.long.word 0xC 16.--24. 1. "DATAQ_ACTIVE_ENTRIES,DATAQ active entries" newline hexmask.long.byte 0xC 8.--15. 1. "DATAQ_WR_PTR,DATAQ write pointer" newline hexmask.long.byte 0xC 0.--7. 1. "DATAQ_RD_PTR,DATAQ read pointer" group.long 0x1030++0x3 line.long 0x0 "Q1_DBG_RD_PTRS,Queue Debug Read Pointers register" bitfld.long 0x0 25. "DATAQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the DATAQ_DBG_RD_PTR follows the DATAQ_RD_PTR." "0: The content of the DATAQ FIFO location pointed..,1: The content of the DATAQ FIFO location pointed.." newline bitfld.long 0x0 24. "CMDQ_DBG_DATA_VALID,The definition of this bit is valid for normal mode too since in normal mode the CMDQ_DBG_RD_PTR follows the CMDQ_RD_PTR." "0: The content of the CMDQ FIFO location pointed by..,1: The content of the CMDQ FIFO location pointed by.." newline hexmask.long.byte 0x0 8.--15. 1. "DATAQ_DBG_RD_PTR,This field allows to read the contents of DATAQ FIFO in debug mode. The content of the DATAQ FIFO location pointed by DATAQ_DBG_RD_PTR is visible on the Q_DATAQ_POP register." newline hexmask.long.byte 0x0 0.--7. 1. "CMDQ_DBG_RD_PTR,This field allows to read the contents of CMDQ FIFO in debug mode. The content of the CMDQ FIFO location pointed by CMDQ_DBG_RD_PTR is visible on the Q_CMDQ_PUSH register." wgroup.long 0x1040++0x3 line.long 0x0 "Q1_CMDQ_PUSH,CMDQ PUSH register" bitfld.long 0x0 31. "LAST_CMD_OF_SEQ,Last command of sequence" "0,1" newline bitfld.long 0x0 30. "DATAQ_CAPTURE_TS_EN,Timestamp capture enable bit" "0,1" newline bitfld.long 0x0 29. "TRIG_OUT,Single trigger output (with per command control)" "0,1" newline bitfld.long 0x0 28. "CMD_DLY_CFG,Command delay configuration" "0: Delay is executed linearly,1: Delay is executed exponentialy" newline bitfld.long 0x0 27. "EN_END_OF_SEQ_IRQ,Enable signaling of interrupt on end of chain/sequence" "0,1" newline bitfld.long 0x0 24.--26. "SEQ_TYPE,Sequence Type" "0: Triggered One-shot,1: Non-triggered One-shot,?,?,4: Triggered Scan,5: Non-triggered Scan,6: Triggered-Once Scan,?" newline bitfld.long 0x0 20.--22. "CMD_REPEAT,Command repeat" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "CMD_DLY,Command delay" newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ADC_CH_NUM,It is the ADC Channel Number for which conversion result is expected." rgroup.long 0x1060++0x3 line.long 0x0 "Q1_DATAQ_POP,DATAQ POP register" hexmask.long.word 0x0 16.--31. 1. "ADC_DATA_TS_SEQ_CNTR,ADC conversion data when DATA_TYPE[2:0] = 000 001 or 010." newline hexmask.long.byte 0x0 8.--15. 1. "DAT_ADC_CH_NUM_TS_SEQ_ADC_CNTR,ADC Channel Number when DATA_TYPE[2:0] = 000 001 or 010" newline bitfld.long 0x0 3.--5. "DATA_TYPE,Data type" "0: ADC data for intermediate commands of sequence.,1: ADC data for first command of sequence.,2: ADC data for last command of sequence.,3: Sequence status.,?,5: Timestamp data,6: Timestamp Trigger,?" newline bitfld.long 0x0 0.--2. "ERROR_CODE,Error Code" "0: NO_ERROR: No error occurred.,1: SUSPENDED: Marker for denoting that this entry..,2: CMD_MISSING: This bit is set for ADC data in..,3: ADC_CNV_TIMEOUT: After launch of a conversion if..,?,?,?,?" tree.end tree.end tree "SDADC (Sigma-Delta Analog-to-Digital Converter Digital Interface)" base ad:0x0 tree "SDADC_0" base ad:0x70374000 group.long 0x0++0x1F line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 31. "EXTFILTER,External Filter selection" "0: Only Internal Filter (Finished and valid data),1: External Filter (Raw data after COMB filter to.." bitfld.long 0x0 30. "LTMW,Level Trigger Mode selection for Watchdog" "0: Level trigger mode,1: Hysteresis mode" newline hexmask.long.byte 0x0 24.--28. 1. "PDR,Programmable Decimation Rate" bitfld.long 0x0 20.--22. "PGAN,Programmable Gain" "0: Gain = 1,1: Gain = 2,2: Gain = 4,3: Gain = 8,?,?,?,7: Gain = 16" newline bitfld.long 0x0 19. "ODF,Output Data Format" "0: Output data is unsigned,1: Output data is signed and sign extended to 16 bits" bitfld.long 0x0 18. "ODA,Output Data Alignment" "0: Output data is right-aligned,1: Output data is left-aligned" newline bitfld.long 0x0 17. "EMSEL,External Modulator Selection" "0: External modulator data and clock inputs are..,1: External modulator data stream and clock inputs.." bitfld.long 0x0 16. "HPFEN,High Pass Filter Enable" "0: High-pass (DC removal) filter is disabled,1: High-pass (DC removal) filter is enabled" newline bitfld.long 0x0 15. "WDGEN,Watchdog Enable" "0: WDG disabled,1: WDG is enabled" bitfld.long 0x0 13.--14. "TRIGEDSEL,Trigger Edge Selection" "0: Falling edge of trigger input is selected,1: Rising edge of trigger input is selected,2: Both edges of trigger input are selected,3: Both edges of trigger input are selected" newline bitfld.long 0x0 12. "TRIGEN,Trigger Enable" "0: Trigger input is disabled,1: Trigger input is enabled" hexmask.long.byte 0x0 8.--11. 1. "TRIGSEL,Trigger Input Selection" newline bitfld.long 0x0 7. "FRZ,Freeze" "0: Conversions are not stopped,1: Conversions are stopped" bitfld.long 0x0 6. "BANDSEL,Output Data Rate Bandwidth Selection" "0: 1/3 (default),1: 1/6" newline bitfld.long 0x0 5. "FSEL,ADC Internal Filter Selection" "0: Comb + FIR (default),1: Comb alone" bitfld.long 0x0 4. "VCOMSEL,Common Voltage Bias Selection" "0: Negative input terminal is biased with VREFN,1: Negative input terminal is biased with VREFP/2.." newline bitfld.long 0x0 3. "WRMODE,Wrap-Around Mode" "0: Wraparound mechanism disabled (in this case the..,1: Wraparound mechanism enabled" bitfld.long 0x0 2. "GECEN,Accurate Gain Error Mode Enable" "0: Gain error calibration mode disabled,1: Gain error calibration mode enabled" newline bitfld.long 0x0 1. "MODE,Mode selection" "0: Differential input mode selected,1: Single-ended input mode selected" bitfld.long 0x0 0. "EN,Enable for SDADC block" "0: SDADC internal modulator placed in low..,1: SDADC internal modulator enabled" line.long 0x4 "CSR,Channel Selection Register" hexmask.long.byte 0x4 16.--23. 1. "BIASEN,Bias enable" bitfld.long 0x4 8.--10. "ANCHSEL_WRAP,Analog Channel Selection Wraparound Value (ANCHSEL_WRAP)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "ANCHSEL,Analog Channel Selection (ANCHSEL)" line.long 0x8 "RKR,Reset Key Register" hexmask.long.word 0x8 0.--15. 1. "RESET_KEY,Reset Key" line.long 0xC "SFR,Status Flag Register" bitfld.long 0xC 16.--18. "ANCHSEL_CNT,Analog Channel Selection Counter (ANCHSEL_CNT)" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8. "DFEF,Data FIFO Empty Flag" "0: Data FIFO is not empty.,1: Data FIFO is empty." newline bitfld.long 0xC 4. "WTHH,Watchdog Upper Threshold Cross Over Event" "0: Watchdog Upper Threshold Cross Over Event did..,1: Watchdog Upper Threshold Cross Over Event.." bitfld.long 0xC 3. "WTHL,Watchdog Lower Threshold Cross Over Event" "0: Watchdog Lower Threshold Cross Over Event did..,1: Watchdog Lower Threshold Cross Over Event.." newline bitfld.long 0xC 2. "CDVF,Converted Data Valid Flag" "0: Data output from SDADC is not valid.,1: Data output from SDADC is valid." bitfld.long 0xC 1. "DFORF,Data FIFO Overrun Flag" "0: No overrun has occurred since the last time the..,1: Overrun has occurred or the DFORF has not been.." newline bitfld.long 0xC 0. "DFFF,Data FIFO Full Flag" "0: The number of data words in FIFO is less than or..,1: The number of data words in FIFO is greater than.." line.long 0x10 "RSER,Request Select and Enable Register" bitfld.long 0x10 17. "WTHDIRS,WDG Threshold Cross Over Event DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." bitfld.long 0x10 16. "DFFDIRS,Data FIFO Full DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." newline bitfld.long 0x10 15. "GGE,Global Gating Enable" "0: Gating feature disabled.,1: Gating feature enabled." bitfld.long 0x10 14. "DIRFWGS,DMA/Interrupt or FIFO Write Gating Select" "0: DMA/Interrupt request is gated.,1: Write to FIFO is gated." newline bitfld.long 0x10 13. "SGARE,Synchronized Gate Assert Request Enable" "0: Global gate signal assertion is not synchronized.,1: Global gate signal assertion is synchronized.." bitfld.long 0x10 12. "CLERE,Capture Last Event Request Enable" "0: Don\qt copy the last data word/timestamp.,1: Copy the last data word and timestamp if.." newline bitfld.long 0x10 11. "CTRE,Capture TimeStamp Request Enable" "0: Don\qt capture the timestamp.,1: Capture the timestamp information inside FIFO." bitfld.long 0x10 3. "WTHDIRE,WDG Threshold Cross Over Event DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled on WDG..,1: Interrupt/DMA request is enabled on WDG.." newline bitfld.long 0x10 2. "CDVEE,Conversion Data Valid Event Enable" "0: Event output disabled.,1: Event output assertion/deassertion based on the.." bitfld.long 0x10 1. "DFORIE,Data FIFO Overrun Interrupt Enable" "0: Interrupt request is disabled when data FIFO..,1: Interrupt request is enabled when data FIFO.." newline bitfld.long 0x10 0. "DFFDIRE,Data FIFO Full DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled when data FIFO..,1: Interrupt/DMA request is enabled when data FIFO.." line.long 0x14 "OSDR,Output Settling Delay Register" hexmask.long.byte 0x14 0.--7. 1. "OSD,Output Settling Delay" line.long 0x18 "FCR,FIFO Control Register" bitfld.long 0x18 16. "FRST,FIFO Flush Reset" "0: No effect.,1: Generate a single cycle reset event to flush the.." hexmask.long.byte 0x18 8.--11. 1. "FTHLD,FIFO Threshold" newline bitfld.long 0x18 3. "FOWEN,FIFO Over Write Enable" "0: Data FIFO OW option disabled.,1: Data FIFO OW option enabled." bitfld.long 0x18 1.--2. "FSIZE,FIFO Size" "0: FIFO depth = 1 data word,1: FIFO depth = 4 data words,2: FIFO depth = 8 data words,3: FIFO depth = 16 data words" newline bitfld.long 0x18 0. "FE,FIFO Enable" "0: Data FIFO is not enabled for multiple data..,1: Data FIFO is enabled; FIFO depth is indicated by.." line.long 0x1C "STKR,Software Trigger Key Register" hexmask.long.word 0x1C 0.--15. 1. "ST_KEY,Software Trigger Key" rgroup.long 0x20++0x3 line.long 0x0 "CDR,Converted Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CDATA,Converted Data Register" group.long 0x24++0x3 line.long 0x0 "WTHHLR,WDG Threshold Register" hexmask.long.word 0x0 16.--31. 1. "THRH,WDG Upper Threshold Value" hexmask.long.word 0x0 0.--15. 1. "THRL,WDG Lower Threshold Value" rgroup.long 0x28++0x7 line.long 0x0 "LDREG,Latest Data Register" hexmask.long.word 0x0 0.--15. 1. "LDR,Latest Data Register" line.long 0x4 "LTREG,Latest Time-Stamp Register" hexmask.long.tbyte 0x4 0.--23. 1. "LTR,Latest Time-Stamp Register" group.long 0x30++0x3 line.long 0x0 "PSICR,PSI Control Register" hexmask.long.byte 0x0 10.--13. 1. "DEST,Destination Address of Decimation Filter or DSPL module" bitfld.long 0x0 8.--9. "RSVRD,This bit is Read/Write independent of DSPL module availability but it is functional only when DSPL module in not present." "0,1,2,3" newline bitfld.long 0x0 7. "FLUSH,Master block Flush request" "0: No flush request.,1: Flush request." bitfld.long 0x0 6. "RPSI,Return Parallel Side Interface" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "MESSAGE_TAG,The MESSAGE_TAG bit fields are used to route the data to different sub-blocks inside the decimation filter." bitfld.long 0x0 1. "INIT,Initialization Mode" "0: Normal mode.,1: Initialization mode." newline bitfld.long 0x0 0. "PSIEN,Parallel Side Interface (PSI) Enable" "0: Disable.,1: Enable." tree.end tree "SDADC_1" base ad:0x70974000 group.long 0x0++0x1F line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 31. "EXTFILTER,External Filter selection" "0: Only Internal Filter (Finished and valid data),1: External Filter (Raw data after COMB filter to.." bitfld.long 0x0 30. "LTMW,Level Trigger Mode selection for Watchdog" "0: Level trigger mode,1: Hysteresis mode" newline hexmask.long.byte 0x0 24.--28. 1. "PDR,Programmable Decimation Rate" bitfld.long 0x0 20.--22. "PGAN,Programmable Gain" "0: Gain = 1,1: Gain = 2,2: Gain = 4,3: Gain = 8,?,?,?,7: Gain = 16" newline bitfld.long 0x0 19. "ODF,Output Data Format" "0: Output data is unsigned,1: Output data is signed and sign extended to 16 bits" bitfld.long 0x0 18. "ODA,Output Data Alignment" "0: Output data is right-aligned,1: Output data is left-aligned" newline bitfld.long 0x0 17. "EMSEL,External Modulator Selection" "0: External modulator data and clock inputs are..,1: External modulator data stream and clock inputs.." bitfld.long 0x0 16. "HPFEN,High Pass Filter Enable" "0: High-pass (DC removal) filter is disabled,1: High-pass (DC removal) filter is enabled" newline bitfld.long 0x0 15. "WDGEN,Watchdog Enable" "0: WDG disabled,1: WDG is enabled" bitfld.long 0x0 13.--14. "TRIGEDSEL,Trigger Edge Selection" "0: Falling edge of trigger input is selected,1: Rising edge of trigger input is selected,2: Both edges of trigger input are selected,3: Both edges of trigger input are selected" newline bitfld.long 0x0 12. "TRIGEN,Trigger Enable" "0: Trigger input is disabled,1: Trigger input is enabled" hexmask.long.byte 0x0 8.--11. 1. "TRIGSEL,Trigger Input Selection" newline bitfld.long 0x0 7. "FRZ,Freeze" "0: Conversions are not stopped,1: Conversions are stopped" bitfld.long 0x0 6. "BANDSEL,Output Data Rate Bandwidth Selection" "0: 1/3 (default),1: 1/6" newline bitfld.long 0x0 5. "FSEL,ADC Internal Filter Selection" "0: Comb + FIR (default),1: Comb alone" bitfld.long 0x0 4. "VCOMSEL,Common Voltage Bias Selection" "0: Negative input terminal is biased with VREFN,1: Negative input terminal is biased with VREFP/2.." newline bitfld.long 0x0 3. "WRMODE,Wrap-Around Mode" "0: Wraparound mechanism disabled (in this case the..,1: Wraparound mechanism enabled" bitfld.long 0x0 2. "GECEN,Accurate Gain Error Mode Enable" "0: Gain error calibration mode disabled,1: Gain error calibration mode enabled" newline bitfld.long 0x0 1. "MODE,Mode selection" "0: Differential input mode selected,1: Single-ended input mode selected" bitfld.long 0x0 0. "EN,Enable for SDADC block" "0: SDADC internal modulator placed in low..,1: SDADC internal modulator enabled" line.long 0x4 "CSR,Channel Selection Register" hexmask.long.byte 0x4 16.--23. 1. "BIASEN,Bias enable" bitfld.long 0x4 8.--10. "ANCHSEL_WRAP,Analog Channel Selection Wraparound Value (ANCHSEL_WRAP)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "ANCHSEL,Analog Channel Selection (ANCHSEL)" line.long 0x8 "RKR,Reset Key Register" hexmask.long.word 0x8 0.--15. 1. "RESET_KEY,Reset Key" line.long 0xC "SFR,Status Flag Register" bitfld.long 0xC 16.--18. "ANCHSEL_CNT,Analog Channel Selection Counter (ANCHSEL_CNT)" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8. "DFEF,Data FIFO Empty Flag" "0: Data FIFO is not empty.,1: Data FIFO is empty." newline bitfld.long 0xC 4. "WTHH,Watchdog Upper Threshold Cross Over Event" "0: Watchdog Upper Threshold Cross Over Event did..,1: Watchdog Upper Threshold Cross Over Event.." bitfld.long 0xC 3. "WTHL,Watchdog Lower Threshold Cross Over Event" "0: Watchdog Lower Threshold Cross Over Event did..,1: Watchdog Lower Threshold Cross Over Event.." newline bitfld.long 0xC 2. "CDVF,Converted Data Valid Flag" "0: Data output from SDADC is not valid.,1: Data output from SDADC is valid." bitfld.long 0xC 1. "DFORF,Data FIFO Overrun Flag" "0: No overrun has occurred since the last time the..,1: Overrun has occurred or the DFORF has not been.." newline bitfld.long 0xC 0. "DFFF,Data FIFO Full Flag" "0: The number of data words in FIFO is less than or..,1: The number of data words in FIFO is greater than.." line.long 0x10 "RSER,Request Select and Enable Register" bitfld.long 0x10 17. "WTHDIRS,WDG Threshold Cross Over Event DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." bitfld.long 0x10 16. "DFFDIRS,Data FIFO Full DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." newline bitfld.long 0x10 15. "GGE,Global Gating Enable" "0: Gating feature disabled.,1: Gating feature enabled." bitfld.long 0x10 14. "DIRFWGS,DMA/Interrupt or FIFO Write Gating Select" "0: DMA/Interrupt request is gated.,1: Write to FIFO is gated." newline bitfld.long 0x10 13. "SGARE,Synchronized Gate Assert Request Enable" "0: Global gate signal assertion is not synchronized.,1: Global gate signal assertion is synchronized.." bitfld.long 0x10 12. "CLERE,Capture Last Event Request Enable" "0: Don\qt copy the last data word/timestamp.,1: Copy the last data word and timestamp if.." newline bitfld.long 0x10 11. "CTRE,Capture TimeStamp Request Enable" "0: Don\qt capture the timestamp.,1: Capture the timestamp information inside FIFO." bitfld.long 0x10 3. "WTHDIRE,WDG Threshold Cross Over Event DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled on WDG..,1: Interrupt/DMA request is enabled on WDG.." newline bitfld.long 0x10 2. "CDVEE,Conversion Data Valid Event Enable" "0: Event output disabled.,1: Event output assertion/deassertion based on the.." bitfld.long 0x10 1. "DFORIE,Data FIFO Overrun Interrupt Enable" "0: Interrupt request is disabled when data FIFO..,1: Interrupt request is enabled when data FIFO.." newline bitfld.long 0x10 0. "DFFDIRE,Data FIFO Full DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled when data FIFO..,1: Interrupt/DMA request is enabled when data FIFO.." line.long 0x14 "OSDR,Output Settling Delay Register" hexmask.long.byte 0x14 0.--7. 1. "OSD,Output Settling Delay" line.long 0x18 "FCR,FIFO Control Register" bitfld.long 0x18 16. "FRST,FIFO Flush Reset" "0: No effect.,1: Generate a single cycle reset event to flush the.." hexmask.long.byte 0x18 8.--11. 1. "FTHLD,FIFO Threshold" newline bitfld.long 0x18 3. "FOWEN,FIFO Over Write Enable" "0: Data FIFO OW option disabled.,1: Data FIFO OW option enabled." bitfld.long 0x18 1.--2. "FSIZE,FIFO Size" "0: FIFO depth = 1 data word,1: FIFO depth = 4 data words,2: FIFO depth = 8 data words,3: FIFO depth = 16 data words" newline bitfld.long 0x18 0. "FE,FIFO Enable" "0: Data FIFO is not enabled for multiple data..,1: Data FIFO is enabled; FIFO depth is indicated by.." line.long 0x1C "STKR,Software Trigger Key Register" hexmask.long.word 0x1C 0.--15. 1. "ST_KEY,Software Trigger Key" rgroup.long 0x20++0x3 line.long 0x0 "CDR,Converted Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CDATA,Converted Data Register" group.long 0x24++0x3 line.long 0x0 "WTHHLR,WDG Threshold Register" hexmask.long.word 0x0 16.--31. 1. "THRH,WDG Upper Threshold Value" hexmask.long.word 0x0 0.--15. 1. "THRL,WDG Lower Threshold Value" rgroup.long 0x28++0x7 line.long 0x0 "LDREG,Latest Data Register" hexmask.long.word 0x0 0.--15. 1. "LDR,Latest Data Register" line.long 0x4 "LTREG,Latest Time-Stamp Register" hexmask.long.tbyte 0x4 0.--23. 1. "LTR,Latest Time-Stamp Register" group.long 0x30++0x3 line.long 0x0 "PSICR,PSI Control Register" hexmask.long.byte 0x0 10.--13. 1. "DEST,Destination Address of Decimation Filter or DSPL module" bitfld.long 0x0 8.--9. "RSVRD,This bit is Read/Write independent of DSPL module availability but it is functional only when DSPL module in not present." "0,1,2,3" newline bitfld.long 0x0 7. "FLUSH,Master block Flush request" "0: No flush request.,1: Flush request." bitfld.long 0x0 6. "RPSI,Return Parallel Side Interface" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "MESSAGE_TAG,The MESSAGE_TAG bit fields are used to route the data to different sub-blocks inside the decimation filter." bitfld.long 0x0 1. "INIT,Initialization Mode" "0: Normal mode.,1: Initialization mode." newline bitfld.long 0x0 0. "PSIEN,Parallel Side Interface (PSI) Enable" "0: Disable.,1: Enable." tree.end tree "SDADC_2" base ad:0x70378000 group.long 0x0++0x1F line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 31. "EXTFILTER,External Filter selection" "0: Only Internal Filter (Finished and valid data),1: External Filter (Raw data after COMB filter to.." bitfld.long 0x0 30. "LTMW,Level Trigger Mode selection for Watchdog" "0: Level trigger mode,1: Hysteresis mode" newline hexmask.long.byte 0x0 24.--28. 1. "PDR,Programmable Decimation Rate" bitfld.long 0x0 20.--22. "PGAN,Programmable Gain" "0: Gain = 1,1: Gain = 2,2: Gain = 4,3: Gain = 8,?,?,?,7: Gain = 16" newline bitfld.long 0x0 19. "ODF,Output Data Format" "0: Output data is unsigned,1: Output data is signed and sign extended to 16 bits" bitfld.long 0x0 18. "ODA,Output Data Alignment" "0: Output data is right-aligned,1: Output data is left-aligned" newline bitfld.long 0x0 17. "EMSEL,External Modulator Selection" "0: External modulator data and clock inputs are..,1: External modulator data stream and clock inputs.." bitfld.long 0x0 16. "HPFEN,High Pass Filter Enable" "0: High-pass (DC removal) filter is disabled,1: High-pass (DC removal) filter is enabled" newline bitfld.long 0x0 15. "WDGEN,Watchdog Enable" "0: WDG disabled,1: WDG is enabled" bitfld.long 0x0 13.--14. "TRIGEDSEL,Trigger Edge Selection" "0: Falling edge of trigger input is selected,1: Rising edge of trigger input is selected,2: Both edges of trigger input are selected,3: Both edges of trigger input are selected" newline bitfld.long 0x0 12. "TRIGEN,Trigger Enable" "0: Trigger input is disabled,1: Trigger input is enabled" hexmask.long.byte 0x0 8.--11. 1. "TRIGSEL,Trigger Input Selection" newline bitfld.long 0x0 7. "FRZ,Freeze" "0: Conversions are not stopped,1: Conversions are stopped" bitfld.long 0x0 6. "BANDSEL,Output Data Rate Bandwidth Selection" "0: 1/3 (default),1: 1/6" newline bitfld.long 0x0 5. "FSEL,ADC Internal Filter Selection" "0: Comb + FIR (default),1: Comb alone" bitfld.long 0x0 4. "VCOMSEL,Common Voltage Bias Selection" "0: Negative input terminal is biased with VREFN,1: Negative input terminal is biased with VREFP/2.." newline bitfld.long 0x0 3. "WRMODE,Wrap-Around Mode" "0: Wraparound mechanism disabled (in this case the..,1: Wraparound mechanism enabled" bitfld.long 0x0 2. "GECEN,Accurate Gain Error Mode Enable" "0: Gain error calibration mode disabled,1: Gain error calibration mode enabled" newline bitfld.long 0x0 1. "MODE,Mode selection" "0: Differential input mode selected,1: Single-ended input mode selected" bitfld.long 0x0 0. "EN,Enable for SDADC block" "0: SDADC internal modulator placed in low..,1: SDADC internal modulator enabled" line.long 0x4 "CSR,Channel Selection Register" hexmask.long.byte 0x4 16.--23. 1. "BIASEN,Bias enable" bitfld.long 0x4 8.--10. "ANCHSEL_WRAP,Analog Channel Selection Wraparound Value (ANCHSEL_WRAP)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "ANCHSEL,Analog Channel Selection (ANCHSEL)" line.long 0x8 "RKR,Reset Key Register" hexmask.long.word 0x8 0.--15. 1. "RESET_KEY,Reset Key" line.long 0xC "SFR,Status Flag Register" bitfld.long 0xC 16.--18. "ANCHSEL_CNT,Analog Channel Selection Counter (ANCHSEL_CNT)" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8. "DFEF,Data FIFO Empty Flag" "0: Data FIFO is not empty.,1: Data FIFO is empty." newline bitfld.long 0xC 4. "WTHH,Watchdog Upper Threshold Cross Over Event" "0: Watchdog Upper Threshold Cross Over Event did..,1: Watchdog Upper Threshold Cross Over Event.." bitfld.long 0xC 3. "WTHL,Watchdog Lower Threshold Cross Over Event" "0: Watchdog Lower Threshold Cross Over Event did..,1: Watchdog Lower Threshold Cross Over Event.." newline bitfld.long 0xC 2. "CDVF,Converted Data Valid Flag" "0: Data output from SDADC is not valid.,1: Data output from SDADC is valid." bitfld.long 0xC 1. "DFORF,Data FIFO Overrun Flag" "0: No overrun has occurred since the last time the..,1: Overrun has occurred or the DFORF has not been.." newline bitfld.long 0xC 0. "DFFF,Data FIFO Full Flag" "0: The number of data words in FIFO is less than or..,1: The number of data words in FIFO is greater than.." line.long 0x10 "RSER,Request Select and Enable Register" bitfld.long 0x10 17. "WTHDIRS,WDG Threshold Cross Over Event DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." bitfld.long 0x10 16. "DFFDIRS,Data FIFO Full DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." newline bitfld.long 0x10 15. "GGE,Global Gating Enable" "0: Gating feature disabled.,1: Gating feature enabled." bitfld.long 0x10 14. "DIRFWGS,DMA/Interrupt or FIFO Write Gating Select" "0: DMA/Interrupt request is gated.,1: Write to FIFO is gated." newline bitfld.long 0x10 13. "SGARE,Synchronized Gate Assert Request Enable" "0: Global gate signal assertion is not synchronized.,1: Global gate signal assertion is synchronized.." bitfld.long 0x10 12. "CLERE,Capture Last Event Request Enable" "0: Don\qt copy the last data word/timestamp.,1: Copy the last data word and timestamp if.." newline bitfld.long 0x10 11. "CTRE,Capture TimeStamp Request Enable" "0: Don\qt capture the timestamp.,1: Capture the timestamp information inside FIFO." bitfld.long 0x10 3. "WTHDIRE,WDG Threshold Cross Over Event DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled on WDG..,1: Interrupt/DMA request is enabled on WDG.." newline bitfld.long 0x10 2. "CDVEE,Conversion Data Valid Event Enable" "0: Event output disabled.,1: Event output assertion/deassertion based on the.." bitfld.long 0x10 1. "DFORIE,Data FIFO Overrun Interrupt Enable" "0: Interrupt request is disabled when data FIFO..,1: Interrupt request is enabled when data FIFO.." newline bitfld.long 0x10 0. "DFFDIRE,Data FIFO Full DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled when data FIFO..,1: Interrupt/DMA request is enabled when data FIFO.." line.long 0x14 "OSDR,Output Settling Delay Register" hexmask.long.byte 0x14 0.--7. 1. "OSD,Output Settling Delay" line.long 0x18 "FCR,FIFO Control Register" bitfld.long 0x18 16. "FRST,FIFO Flush Reset" "0: No effect.,1: Generate a single cycle reset event to flush the.." hexmask.long.byte 0x18 8.--11. 1. "FTHLD,FIFO Threshold" newline bitfld.long 0x18 3. "FOWEN,FIFO Over Write Enable" "0: Data FIFO OW option disabled.,1: Data FIFO OW option enabled." bitfld.long 0x18 1.--2. "FSIZE,FIFO Size" "0: FIFO depth = 1 data word,1: FIFO depth = 4 data words,2: FIFO depth = 8 data words,3: FIFO depth = 16 data words" newline bitfld.long 0x18 0. "FE,FIFO Enable" "0: Data FIFO is not enabled for multiple data..,1: Data FIFO is enabled; FIFO depth is indicated by.." line.long 0x1C "STKR,Software Trigger Key Register" hexmask.long.word 0x1C 0.--15. 1. "ST_KEY,Software Trigger Key" rgroup.long 0x20++0x3 line.long 0x0 "CDR,Converted Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CDATA,Converted Data Register" group.long 0x24++0x3 line.long 0x0 "WTHHLR,WDG Threshold Register" hexmask.long.word 0x0 16.--31. 1. "THRH,WDG Upper Threshold Value" hexmask.long.word 0x0 0.--15. 1. "THRL,WDG Lower Threshold Value" rgroup.long 0x28++0x7 line.long 0x0 "LDREG,Latest Data Register" hexmask.long.word 0x0 0.--15. 1. "LDR,Latest Data Register" line.long 0x4 "LTREG,Latest Time-Stamp Register" hexmask.long.tbyte 0x4 0.--23. 1. "LTR,Latest Time-Stamp Register" group.long 0x30++0x3 line.long 0x0 "PSICR,PSI Control Register" hexmask.long.byte 0x0 10.--13. 1. "DEST,Destination Address of Decimation Filter or DSPL module" bitfld.long 0x0 8.--9. "RSVRD,This bit is Read/Write independent of DSPL module availability but it is functional only when DSPL module in not present." "0,1,2,3" newline bitfld.long 0x0 7. "FLUSH,Master block Flush request" "0: No flush request.,1: Flush request." bitfld.long 0x0 6. "RPSI,Return Parallel Side Interface" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "MESSAGE_TAG,The MESSAGE_TAG bit fields are used to route the data to different sub-blocks inside the decimation filter." bitfld.long 0x0 1. "INIT,Initialization Mode" "0: Normal mode.,1: Initialization mode." newline bitfld.long 0x0 0. "PSIEN,Parallel Side Interface (PSI) Enable" "0: Disable.,1: Enable." tree.end tree "SDADC_3" base ad:0x70978000 group.long 0x0++0x1F line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 31. "EXTFILTER,External Filter selection" "0: Only Internal Filter (Finished and valid data),1: External Filter (Raw data after COMB filter to.." bitfld.long 0x0 30. "LTMW,Level Trigger Mode selection for Watchdog" "0: Level trigger mode,1: Hysteresis mode" newline hexmask.long.byte 0x0 24.--28. 1. "PDR,Programmable Decimation Rate" bitfld.long 0x0 20.--22. "PGAN,Programmable Gain" "0: Gain = 1,1: Gain = 2,2: Gain = 4,3: Gain = 8,?,?,?,7: Gain = 16" newline bitfld.long 0x0 19. "ODF,Output Data Format" "0: Output data is unsigned,1: Output data is signed and sign extended to 16 bits" bitfld.long 0x0 18. "ODA,Output Data Alignment" "0: Output data is right-aligned,1: Output data is left-aligned" newline bitfld.long 0x0 17. "EMSEL,External Modulator Selection" "0: External modulator data and clock inputs are..,1: External modulator data stream and clock inputs.." bitfld.long 0x0 16. "HPFEN,High Pass Filter Enable" "0: High-pass (DC removal) filter is disabled,1: High-pass (DC removal) filter is enabled" newline bitfld.long 0x0 15. "WDGEN,Watchdog Enable" "0: WDG disabled,1: WDG is enabled" bitfld.long 0x0 13.--14. "TRIGEDSEL,Trigger Edge Selection" "0: Falling edge of trigger input is selected,1: Rising edge of trigger input is selected,2: Both edges of trigger input are selected,3: Both edges of trigger input are selected" newline bitfld.long 0x0 12. "TRIGEN,Trigger Enable" "0: Trigger input is disabled,1: Trigger input is enabled" hexmask.long.byte 0x0 8.--11. 1. "TRIGSEL,Trigger Input Selection" newline bitfld.long 0x0 7. "FRZ,Freeze" "0: Conversions are not stopped,1: Conversions are stopped" bitfld.long 0x0 6. "BANDSEL,Output Data Rate Bandwidth Selection" "0: 1/3 (default),1: 1/6" newline bitfld.long 0x0 5. "FSEL,ADC Internal Filter Selection" "0: Comb + FIR (default),1: Comb alone" bitfld.long 0x0 4. "VCOMSEL,Common Voltage Bias Selection" "0: Negative input terminal is biased with VREFN,1: Negative input terminal is biased with VREFP/2.." newline bitfld.long 0x0 3. "WRMODE,Wrap-Around Mode" "0: Wraparound mechanism disabled (in this case the..,1: Wraparound mechanism enabled" bitfld.long 0x0 2. "GECEN,Accurate Gain Error Mode Enable" "0: Gain error calibration mode disabled,1: Gain error calibration mode enabled" newline bitfld.long 0x0 1. "MODE,Mode selection" "0: Differential input mode selected,1: Single-ended input mode selected" bitfld.long 0x0 0. "EN,Enable for SDADC block" "0: SDADC internal modulator placed in low..,1: SDADC internal modulator enabled" line.long 0x4 "CSR,Channel Selection Register" hexmask.long.byte 0x4 16.--23. 1. "BIASEN,Bias enable" bitfld.long 0x4 8.--10. "ANCHSEL_WRAP,Analog Channel Selection Wraparound Value (ANCHSEL_WRAP)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "ANCHSEL,Analog Channel Selection (ANCHSEL)" line.long 0x8 "RKR,Reset Key Register" hexmask.long.word 0x8 0.--15. 1. "RESET_KEY,Reset Key" line.long 0xC "SFR,Status Flag Register" bitfld.long 0xC 16.--18. "ANCHSEL_CNT,Analog Channel Selection Counter (ANCHSEL_CNT)" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8. "DFEF,Data FIFO Empty Flag" "0: Data FIFO is not empty.,1: Data FIFO is empty." newline bitfld.long 0xC 4. "WTHH,Watchdog Upper Threshold Cross Over Event" "0: Watchdog Upper Threshold Cross Over Event did..,1: Watchdog Upper Threshold Cross Over Event.." bitfld.long 0xC 3. "WTHL,Watchdog Lower Threshold Cross Over Event" "0: Watchdog Lower Threshold Cross Over Event did..,1: Watchdog Lower Threshold Cross Over Event.." newline bitfld.long 0xC 2. "CDVF,Converted Data Valid Flag" "0: Data output from SDADC is not valid.,1: Data output from SDADC is valid." bitfld.long 0xC 1. "DFORF,Data FIFO Overrun Flag" "0: No overrun has occurred since the last time the..,1: Overrun has occurred or the DFORF has not been.." newline bitfld.long 0xC 0. "DFFF,Data FIFO Full Flag" "0: The number of data words in FIFO is less than or..,1: The number of data words in FIFO is greater than.." line.long 0x10 "RSER,Request Select and Enable Register" bitfld.long 0x10 17. "WTHDIRS,WDG Threshold Cross Over Event DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." bitfld.long 0x10 16. "DFFDIRS,Data FIFO Full DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." newline bitfld.long 0x10 15. "GGE,Global Gating Enable" "0: Gating feature disabled.,1: Gating feature enabled." bitfld.long 0x10 14. "DIRFWGS,DMA/Interrupt or FIFO Write Gating Select" "0: DMA/Interrupt request is gated.,1: Write to FIFO is gated." newline bitfld.long 0x10 13. "SGARE,Synchronized Gate Assert Request Enable" "0: Global gate signal assertion is not synchronized.,1: Global gate signal assertion is synchronized.." bitfld.long 0x10 12. "CLERE,Capture Last Event Request Enable" "0: Don\qt copy the last data word/timestamp.,1: Copy the last data word and timestamp if.." newline bitfld.long 0x10 11. "CTRE,Capture TimeStamp Request Enable" "0: Don\qt capture the timestamp.,1: Capture the timestamp information inside FIFO." bitfld.long 0x10 3. "WTHDIRE,WDG Threshold Cross Over Event DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled on WDG..,1: Interrupt/DMA request is enabled on WDG.." newline bitfld.long 0x10 2. "CDVEE,Conversion Data Valid Event Enable" "0: Event output disabled.,1: Event output assertion/deassertion based on the.." bitfld.long 0x10 1. "DFORIE,Data FIFO Overrun Interrupt Enable" "0: Interrupt request is disabled when data FIFO..,1: Interrupt request is enabled when data FIFO.." newline bitfld.long 0x10 0. "DFFDIRE,Data FIFO Full DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled when data FIFO..,1: Interrupt/DMA request is enabled when data FIFO.." line.long 0x14 "OSDR,Output Settling Delay Register" hexmask.long.byte 0x14 0.--7. 1. "OSD,Output Settling Delay" line.long 0x18 "FCR,FIFO Control Register" bitfld.long 0x18 16. "FRST,FIFO Flush Reset" "0: No effect.,1: Generate a single cycle reset event to flush the.." hexmask.long.byte 0x18 8.--11. 1. "FTHLD,FIFO Threshold" newline bitfld.long 0x18 3. "FOWEN,FIFO Over Write Enable" "0: Data FIFO OW option disabled.,1: Data FIFO OW option enabled." bitfld.long 0x18 1.--2. "FSIZE,FIFO Size" "0: FIFO depth = 1 data word,1: FIFO depth = 4 data words,2: FIFO depth = 8 data words,3: FIFO depth = 16 data words" newline bitfld.long 0x18 0. "FE,FIFO Enable" "0: Data FIFO is not enabled for multiple data..,1: Data FIFO is enabled; FIFO depth is indicated by.." line.long 0x1C "STKR,Software Trigger Key Register" hexmask.long.word 0x1C 0.--15. 1. "ST_KEY,Software Trigger Key" rgroup.long 0x20++0x3 line.long 0x0 "CDR,Converted Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CDATA,Converted Data Register" group.long 0x24++0x3 line.long 0x0 "WTHHLR,WDG Threshold Register" hexmask.long.word 0x0 16.--31. 1. "THRH,WDG Upper Threshold Value" hexmask.long.word 0x0 0.--15. 1. "THRL,WDG Lower Threshold Value" rgroup.long 0x28++0x7 line.long 0x0 "LDREG,Latest Data Register" hexmask.long.word 0x0 0.--15. 1. "LDR,Latest Data Register" line.long 0x4 "LTREG,Latest Time-Stamp Register" hexmask.long.tbyte 0x4 0.--23. 1. "LTR,Latest Time-Stamp Register" group.long 0x30++0x3 line.long 0x0 "PSICR,PSI Control Register" hexmask.long.byte 0x0 10.--13. 1. "DEST,Destination Address of Decimation Filter or DSPL module" bitfld.long 0x0 8.--9. "RSVRD,This bit is Read/Write independent of DSPL module availability but it is functional only when DSPL module in not present." "0,1,2,3" newline bitfld.long 0x0 7. "FLUSH,Master block Flush request" "0: No flush request.,1: Flush request." bitfld.long 0x0 6. "RPSI,Return Parallel Side Interface" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "MESSAGE_TAG,The MESSAGE_TAG bit fields are used to route the data to different sub-blocks inside the decimation filter." bitfld.long 0x0 1. "INIT,Initialization Mode" "0: Normal mode.,1: Initialization mode." newline bitfld.long 0x0 0. "PSIEN,Parallel Side Interface (PSI) Enable" "0: Disable.,1: Enable." tree.end tree "SDADC_4" base ad:0x7037C000 group.long 0x0++0x1F line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 31. "EXTFILTER,External Filter selection" "0: Only Internal Filter (Finished and valid data),1: External Filter (Raw data after COMB filter to.." bitfld.long 0x0 30. "LTMW,Level Trigger Mode selection for Watchdog" "0: Level trigger mode,1: Hysteresis mode" newline hexmask.long.byte 0x0 24.--28. 1. "PDR,Programmable Decimation Rate" bitfld.long 0x0 20.--22. "PGAN,Programmable Gain" "0: Gain = 1,1: Gain = 2,2: Gain = 4,3: Gain = 8,?,?,?,7: Gain = 16" newline bitfld.long 0x0 19. "ODF,Output Data Format" "0: Output data is unsigned,1: Output data is signed and sign extended to 16 bits" bitfld.long 0x0 18. "ODA,Output Data Alignment" "0: Output data is right-aligned,1: Output data is left-aligned" newline bitfld.long 0x0 17. "EMSEL,External Modulator Selection" "0: External modulator data and clock inputs are..,1: External modulator data stream and clock inputs.." bitfld.long 0x0 16. "HPFEN,High Pass Filter Enable" "0: High-pass (DC removal) filter is disabled,1: High-pass (DC removal) filter is enabled" newline bitfld.long 0x0 15. "WDGEN,Watchdog Enable" "0: WDG disabled,1: WDG is enabled" bitfld.long 0x0 13.--14. "TRIGEDSEL,Trigger Edge Selection" "0: Falling edge of trigger input is selected,1: Rising edge of trigger input is selected,2: Both edges of trigger input are selected,3: Both edges of trigger input are selected" newline bitfld.long 0x0 12. "TRIGEN,Trigger Enable" "0: Trigger input is disabled,1: Trigger input is enabled" hexmask.long.byte 0x0 8.--11. 1. "TRIGSEL,Trigger Input Selection" newline bitfld.long 0x0 7. "FRZ,Freeze" "0: Conversions are not stopped,1: Conversions are stopped" bitfld.long 0x0 6. "BANDSEL,Output Data Rate Bandwidth Selection" "0: 1/3 (default),1: 1/6" newline bitfld.long 0x0 5. "FSEL,ADC Internal Filter Selection" "0: Comb + FIR (default),1: Comb alone" bitfld.long 0x0 4. "VCOMSEL,Common Voltage Bias Selection" "0: Negative input terminal is biased with VREFN,1: Negative input terminal is biased with VREFP/2.." newline bitfld.long 0x0 3. "WRMODE,Wrap-Around Mode" "0: Wraparound mechanism disabled (in this case the..,1: Wraparound mechanism enabled" bitfld.long 0x0 2. "GECEN,Accurate Gain Error Mode Enable" "0: Gain error calibration mode disabled,1: Gain error calibration mode enabled" newline bitfld.long 0x0 1. "MODE,Mode selection" "0: Differential input mode selected,1: Single-ended input mode selected" bitfld.long 0x0 0. "EN,Enable for SDADC block" "0: SDADC internal modulator placed in low..,1: SDADC internal modulator enabled" line.long 0x4 "CSR,Channel Selection Register" hexmask.long.byte 0x4 16.--23. 1. "BIASEN,Bias enable" bitfld.long 0x4 8.--10. "ANCHSEL_WRAP,Analog Channel Selection Wraparound Value (ANCHSEL_WRAP)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "ANCHSEL,Analog Channel Selection (ANCHSEL)" line.long 0x8 "RKR,Reset Key Register" hexmask.long.word 0x8 0.--15. 1. "RESET_KEY,Reset Key" line.long 0xC "SFR,Status Flag Register" bitfld.long 0xC 16.--18. "ANCHSEL_CNT,Analog Channel Selection Counter (ANCHSEL_CNT)" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8. "DFEF,Data FIFO Empty Flag" "0: Data FIFO is not empty.,1: Data FIFO is empty." newline bitfld.long 0xC 4. "WTHH,Watchdog Upper Threshold Cross Over Event" "0: Watchdog Upper Threshold Cross Over Event did..,1: Watchdog Upper Threshold Cross Over Event.." bitfld.long 0xC 3. "WTHL,Watchdog Lower Threshold Cross Over Event" "0: Watchdog Lower Threshold Cross Over Event did..,1: Watchdog Lower Threshold Cross Over Event.." newline bitfld.long 0xC 2. "CDVF,Converted Data Valid Flag" "0: Data output from SDADC is not valid.,1: Data output from SDADC is valid." bitfld.long 0xC 1. "DFORF,Data FIFO Overrun Flag" "0: No overrun has occurred since the last time the..,1: Overrun has occurred or the DFORF has not been.." newline bitfld.long 0xC 0. "DFFF,Data FIFO Full Flag" "0: The number of data words in FIFO is less than or..,1: The number of data words in FIFO is greater than.." line.long 0x10 "RSER,Request Select and Enable Register" bitfld.long 0x10 17. "WTHDIRS,WDG Threshold Cross Over Event DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." bitfld.long 0x10 16. "DFFDIRS,Data FIFO Full DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." newline bitfld.long 0x10 15. "GGE,Global Gating Enable" "0: Gating feature disabled.,1: Gating feature enabled." bitfld.long 0x10 14. "DIRFWGS,DMA/Interrupt or FIFO Write Gating Select" "0: DMA/Interrupt request is gated.,1: Write to FIFO is gated." newline bitfld.long 0x10 13. "SGARE,Synchronized Gate Assert Request Enable" "0: Global gate signal assertion is not synchronized.,1: Global gate signal assertion is synchronized.." bitfld.long 0x10 12. "CLERE,Capture Last Event Request Enable" "0: Don\qt copy the last data word/timestamp.,1: Copy the last data word and timestamp if.." newline bitfld.long 0x10 11. "CTRE,Capture TimeStamp Request Enable" "0: Don\qt capture the timestamp.,1: Capture the timestamp information inside FIFO." bitfld.long 0x10 3. "WTHDIRE,WDG Threshold Cross Over Event DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled on WDG..,1: Interrupt/DMA request is enabled on WDG.." newline bitfld.long 0x10 2. "CDVEE,Conversion Data Valid Event Enable" "0: Event output disabled.,1: Event output assertion/deassertion based on the.." bitfld.long 0x10 1. "DFORIE,Data FIFO Overrun Interrupt Enable" "0: Interrupt request is disabled when data FIFO..,1: Interrupt request is enabled when data FIFO.." newline bitfld.long 0x10 0. "DFFDIRE,Data FIFO Full DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled when data FIFO..,1: Interrupt/DMA request is enabled when data FIFO.." line.long 0x14 "OSDR,Output Settling Delay Register" hexmask.long.byte 0x14 0.--7. 1. "OSD,Output Settling Delay" line.long 0x18 "FCR,FIFO Control Register" bitfld.long 0x18 16. "FRST,FIFO Flush Reset" "0: No effect.,1: Generate a single cycle reset event to flush the.." hexmask.long.byte 0x18 8.--11. 1. "FTHLD,FIFO Threshold" newline bitfld.long 0x18 3. "FOWEN,FIFO Over Write Enable" "0: Data FIFO OW option disabled.,1: Data FIFO OW option enabled." bitfld.long 0x18 1.--2. "FSIZE,FIFO Size" "0: FIFO depth = 1 data word,1: FIFO depth = 4 data words,2: FIFO depth = 8 data words,3: FIFO depth = 16 data words" newline bitfld.long 0x18 0. "FE,FIFO Enable" "0: Data FIFO is not enabled for multiple data..,1: Data FIFO is enabled; FIFO depth is indicated by.." line.long 0x1C "STKR,Software Trigger Key Register" hexmask.long.word 0x1C 0.--15. 1. "ST_KEY,Software Trigger Key" rgroup.long 0x20++0x3 line.long 0x0 "CDR,Converted Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CDATA,Converted Data Register" group.long 0x24++0x3 line.long 0x0 "WTHHLR,WDG Threshold Register" hexmask.long.word 0x0 16.--31. 1. "THRH,WDG Upper Threshold Value" hexmask.long.word 0x0 0.--15. 1. "THRL,WDG Lower Threshold Value" rgroup.long 0x28++0x7 line.long 0x0 "LDREG,Latest Data Register" hexmask.long.word 0x0 0.--15. 1. "LDR,Latest Data Register" line.long 0x4 "LTREG,Latest Time-Stamp Register" hexmask.long.tbyte 0x4 0.--23. 1. "LTR,Latest Time-Stamp Register" group.long 0x30++0x3 line.long 0x0 "PSICR,PSI Control Register" hexmask.long.byte 0x0 10.--13. 1. "DEST,Destination Address of Decimation Filter or DSPL module" bitfld.long 0x0 8.--9. "RSVRD,This bit is Read/Write independent of DSPL module availability but it is functional only when DSPL module in not present." "0,1,2,3" newline bitfld.long 0x0 7. "FLUSH,Master block Flush request" "0: No flush request.,1: Flush request." bitfld.long 0x0 6. "RPSI,Return Parallel Side Interface" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "MESSAGE_TAG,The MESSAGE_TAG bit fields are used to route the data to different sub-blocks inside the decimation filter." bitfld.long 0x0 1. "INIT,Initialization Mode" "0: Normal mode.,1: Initialization mode." newline bitfld.long 0x0 0. "PSIEN,Parallel Side Interface (PSI) Enable" "0: Disable.,1: Enable." tree.end tree "SDADC_5" base ad:0x7097C000 group.long 0x0++0x1F line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 31. "EXTFILTER,External Filter selection" "0: Only Internal Filter (Finished and valid data),1: External Filter (Raw data after COMB filter to.." bitfld.long 0x0 30. "LTMW,Level Trigger Mode selection for Watchdog" "0: Level trigger mode,1: Hysteresis mode" newline hexmask.long.byte 0x0 24.--28. 1. "PDR,Programmable Decimation Rate" bitfld.long 0x0 20.--22. "PGAN,Programmable Gain" "0: Gain = 1,1: Gain = 2,2: Gain = 4,3: Gain = 8,?,?,?,7: Gain = 16" newline bitfld.long 0x0 19. "ODF,Output Data Format" "0: Output data is unsigned,1: Output data is signed and sign extended to 16 bits" bitfld.long 0x0 18. "ODA,Output Data Alignment" "0: Output data is right-aligned,1: Output data is left-aligned" newline bitfld.long 0x0 17. "EMSEL,External Modulator Selection" "0: External modulator data and clock inputs are..,1: External modulator data stream and clock inputs.." bitfld.long 0x0 16. "HPFEN,High Pass Filter Enable" "0: High-pass (DC removal) filter is disabled,1: High-pass (DC removal) filter is enabled" newline bitfld.long 0x0 15. "WDGEN,Watchdog Enable" "0: WDG disabled,1: WDG is enabled" bitfld.long 0x0 13.--14. "TRIGEDSEL,Trigger Edge Selection" "0: Falling edge of trigger input is selected,1: Rising edge of trigger input is selected,2: Both edges of trigger input are selected,3: Both edges of trigger input are selected" newline bitfld.long 0x0 12. "TRIGEN,Trigger Enable" "0: Trigger input is disabled,1: Trigger input is enabled" hexmask.long.byte 0x0 8.--11. 1. "TRIGSEL,Trigger Input Selection" newline bitfld.long 0x0 7. "FRZ,Freeze" "0: Conversions are not stopped,1: Conversions are stopped" bitfld.long 0x0 6. "BANDSEL,Output Data Rate Bandwidth Selection" "0: 1/3 (default),1: 1/6" newline bitfld.long 0x0 5. "FSEL,ADC Internal Filter Selection" "0: Comb + FIR (default),1: Comb alone" bitfld.long 0x0 4. "VCOMSEL,Common Voltage Bias Selection" "0: Negative input terminal is biased with VREFN,1: Negative input terminal is biased with VREFP/2.." newline bitfld.long 0x0 3. "WRMODE,Wrap-Around Mode" "0: Wraparound mechanism disabled (in this case the..,1: Wraparound mechanism enabled" bitfld.long 0x0 2. "GECEN,Accurate Gain Error Mode Enable" "0: Gain error calibration mode disabled,1: Gain error calibration mode enabled" newline bitfld.long 0x0 1. "MODE,Mode selection" "0: Differential input mode selected,1: Single-ended input mode selected" bitfld.long 0x0 0. "EN,Enable for SDADC block" "0: SDADC internal modulator placed in low..,1: SDADC internal modulator enabled" line.long 0x4 "CSR,Channel Selection Register" hexmask.long.byte 0x4 16.--23. 1. "BIASEN,Bias enable" bitfld.long 0x4 8.--10. "ANCHSEL_WRAP,Analog Channel Selection Wraparound Value (ANCHSEL_WRAP)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "ANCHSEL,Analog Channel Selection (ANCHSEL)" line.long 0x8 "RKR,Reset Key Register" hexmask.long.word 0x8 0.--15. 1. "RESET_KEY,Reset Key" line.long 0xC "SFR,Status Flag Register" bitfld.long 0xC 16.--18. "ANCHSEL_CNT,Analog Channel Selection Counter (ANCHSEL_CNT)" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8. "DFEF,Data FIFO Empty Flag" "0: Data FIFO is not empty.,1: Data FIFO is empty." newline bitfld.long 0xC 4. "WTHH,Watchdog Upper Threshold Cross Over Event" "0: Watchdog Upper Threshold Cross Over Event did..,1: Watchdog Upper Threshold Cross Over Event.." bitfld.long 0xC 3. "WTHL,Watchdog Lower Threshold Cross Over Event" "0: Watchdog Lower Threshold Cross Over Event did..,1: Watchdog Lower Threshold Cross Over Event.." newline bitfld.long 0xC 2. "CDVF,Converted Data Valid Flag" "0: Data output from SDADC is not valid.,1: Data output from SDADC is valid." bitfld.long 0xC 1. "DFORF,Data FIFO Overrun Flag" "0: No overrun has occurred since the last time the..,1: Overrun has occurred or the DFORF has not been.." newline bitfld.long 0xC 0. "DFFF,Data FIFO Full Flag" "0: The number of data words in FIFO is less than or..,1: The number of data words in FIFO is greater than.." line.long 0x10 "RSER,Request Select and Enable Register" bitfld.long 0x10 17. "WTHDIRS,WDG Threshold Cross Over Event DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." bitfld.long 0x10 16. "DFFDIRS,Data FIFO Full DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." newline bitfld.long 0x10 15. "GGE,Global Gating Enable" "0: Gating feature disabled.,1: Gating feature enabled." bitfld.long 0x10 14. "DIRFWGS,DMA/Interrupt or FIFO Write Gating Select" "0: DMA/Interrupt request is gated.,1: Write to FIFO is gated." newline bitfld.long 0x10 13. "SGARE,Synchronized Gate Assert Request Enable" "0: Global gate signal assertion is not synchronized.,1: Global gate signal assertion is synchronized.." bitfld.long 0x10 12. "CLERE,Capture Last Event Request Enable" "0: Don\qt copy the last data word/timestamp.,1: Copy the last data word and timestamp if.." newline bitfld.long 0x10 11. "CTRE,Capture TimeStamp Request Enable" "0: Don\qt capture the timestamp.,1: Capture the timestamp information inside FIFO." bitfld.long 0x10 3. "WTHDIRE,WDG Threshold Cross Over Event DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled on WDG..,1: Interrupt/DMA request is enabled on WDG.." newline bitfld.long 0x10 2. "CDVEE,Conversion Data Valid Event Enable" "0: Event output disabled.,1: Event output assertion/deassertion based on the.." bitfld.long 0x10 1. "DFORIE,Data FIFO Overrun Interrupt Enable" "0: Interrupt request is disabled when data FIFO..,1: Interrupt request is enabled when data FIFO.." newline bitfld.long 0x10 0. "DFFDIRE,Data FIFO Full DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled when data FIFO..,1: Interrupt/DMA request is enabled when data FIFO.." line.long 0x14 "OSDR,Output Settling Delay Register" hexmask.long.byte 0x14 0.--7. 1. "OSD,Output Settling Delay" line.long 0x18 "FCR,FIFO Control Register" bitfld.long 0x18 16. "FRST,FIFO Flush Reset" "0: No effect.,1: Generate a single cycle reset event to flush the.." hexmask.long.byte 0x18 8.--11. 1. "FTHLD,FIFO Threshold" newline bitfld.long 0x18 3. "FOWEN,FIFO Over Write Enable" "0: Data FIFO OW option disabled.,1: Data FIFO OW option enabled." bitfld.long 0x18 1.--2. "FSIZE,FIFO Size" "0: FIFO depth = 1 data word,1: FIFO depth = 4 data words,2: FIFO depth = 8 data words,3: FIFO depth = 16 data words" newline bitfld.long 0x18 0. "FE,FIFO Enable" "0: Data FIFO is not enabled for multiple data..,1: Data FIFO is enabled; FIFO depth is indicated by.." line.long 0x1C "STKR,Software Trigger Key Register" hexmask.long.word 0x1C 0.--15. 1. "ST_KEY,Software Trigger Key" rgroup.long 0x20++0x3 line.long 0x0 "CDR,Converted Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CDATA,Converted Data Register" group.long 0x24++0x3 line.long 0x0 "WTHHLR,WDG Threshold Register" hexmask.long.word 0x0 16.--31. 1. "THRH,WDG Upper Threshold Value" hexmask.long.word 0x0 0.--15. 1. "THRL,WDG Lower Threshold Value" rgroup.long 0x28++0x7 line.long 0x0 "LDREG,Latest Data Register" hexmask.long.word 0x0 0.--15. 1. "LDR,Latest Data Register" line.long 0x4 "LTREG,Latest Time-Stamp Register" hexmask.long.tbyte 0x4 0.--23. 1. "LTR,Latest Time-Stamp Register" group.long 0x30++0x3 line.long 0x0 "PSICR,PSI Control Register" hexmask.long.byte 0x0 10.--13. 1. "DEST,Destination Address of Decimation Filter or DSPL module" bitfld.long 0x0 8.--9. "RSVRD,This bit is Read/Write independent of DSPL module availability but it is functional only when DSPL module in not present." "0,1,2,3" newline bitfld.long 0x0 7. "FLUSH,Master block Flush request" "0: No flush request.,1: Flush request." bitfld.long 0x0 6. "RPSI,Return Parallel Side Interface" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "MESSAGE_TAG,The MESSAGE_TAG bit fields are used to route the data to different sub-blocks inside the decimation filter." bitfld.long 0x0 1. "INIT,Initialization Mode" "0: Normal mode.,1: Initialization mode." newline bitfld.long 0x0 0. "PSIEN,Parallel Side Interface (PSI) Enable" "0: Disable.,1: Enable." tree.end tree "SDADC_6" base ad:0x70380000 group.long 0x0++0x1F line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 31. "EXTFILTER,External Filter selection" "0: Only Internal Filter (Finished and valid data),1: External Filter (Raw data after COMB filter to.." bitfld.long 0x0 30. "LTMW,Level Trigger Mode selection for Watchdog" "0: Level trigger mode,1: Hysteresis mode" newline hexmask.long.byte 0x0 24.--28. 1. "PDR,Programmable Decimation Rate" bitfld.long 0x0 20.--22. "PGAN,Programmable Gain" "0: Gain = 1,1: Gain = 2,2: Gain = 4,3: Gain = 8,?,?,?,7: Gain = 16" newline bitfld.long 0x0 19. "ODF,Output Data Format" "0: Output data is unsigned,1: Output data is signed and sign extended to 16 bits" bitfld.long 0x0 18. "ODA,Output Data Alignment" "0: Output data is right-aligned,1: Output data is left-aligned" newline bitfld.long 0x0 17. "EMSEL,External Modulator Selection" "0: External modulator data and clock inputs are..,1: External modulator data stream and clock inputs.." bitfld.long 0x0 16. "HPFEN,High Pass Filter Enable" "0: High-pass (DC removal) filter is disabled,1: High-pass (DC removal) filter is enabled" newline bitfld.long 0x0 15. "WDGEN,Watchdog Enable" "0: WDG disabled,1: WDG is enabled" bitfld.long 0x0 13.--14. "TRIGEDSEL,Trigger Edge Selection" "0: Falling edge of trigger input is selected,1: Rising edge of trigger input is selected,2: Both edges of trigger input are selected,3: Both edges of trigger input are selected" newline bitfld.long 0x0 12. "TRIGEN,Trigger Enable" "0: Trigger input is disabled,1: Trigger input is enabled" hexmask.long.byte 0x0 8.--11. 1. "TRIGSEL,Trigger Input Selection" newline bitfld.long 0x0 7. "FRZ,Freeze" "0: Conversions are not stopped,1: Conversions are stopped" bitfld.long 0x0 6. "BANDSEL,Output Data Rate Bandwidth Selection" "0: 1/3 (default),1: 1/6" newline bitfld.long 0x0 5. "FSEL,ADC Internal Filter Selection" "0: Comb + FIR (default),1: Comb alone" bitfld.long 0x0 4. "VCOMSEL,Common Voltage Bias Selection" "0: Negative input terminal is biased with VREFN,1: Negative input terminal is biased with VREFP/2.." newline bitfld.long 0x0 3. "WRMODE,Wrap-Around Mode" "0: Wraparound mechanism disabled (in this case the..,1: Wraparound mechanism enabled" bitfld.long 0x0 2. "GECEN,Accurate Gain Error Mode Enable" "0: Gain error calibration mode disabled,1: Gain error calibration mode enabled" newline bitfld.long 0x0 1. "MODE,Mode selection" "0: Differential input mode selected,1: Single-ended input mode selected" bitfld.long 0x0 0. "EN,Enable for SDADC block" "0: SDADC internal modulator placed in low..,1: SDADC internal modulator enabled" line.long 0x4 "CSR,Channel Selection Register" hexmask.long.byte 0x4 16.--23. 1. "BIASEN,Bias enable" bitfld.long 0x4 8.--10. "ANCHSEL_WRAP,Analog Channel Selection Wraparound Value (ANCHSEL_WRAP)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "ANCHSEL,Analog Channel Selection (ANCHSEL)" line.long 0x8 "RKR,Reset Key Register" hexmask.long.word 0x8 0.--15. 1. "RESET_KEY,Reset Key" line.long 0xC "SFR,Status Flag Register" bitfld.long 0xC 16.--18. "ANCHSEL_CNT,Analog Channel Selection Counter (ANCHSEL_CNT)" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8. "DFEF,Data FIFO Empty Flag" "0: Data FIFO is not empty.,1: Data FIFO is empty." newline bitfld.long 0xC 4. "WTHH,Watchdog Upper Threshold Cross Over Event" "0: Watchdog Upper Threshold Cross Over Event did..,1: Watchdog Upper Threshold Cross Over Event.." bitfld.long 0xC 3. "WTHL,Watchdog Lower Threshold Cross Over Event" "0: Watchdog Lower Threshold Cross Over Event did..,1: Watchdog Lower Threshold Cross Over Event.." newline bitfld.long 0xC 2. "CDVF,Converted Data Valid Flag" "0: Data output from SDADC is not valid.,1: Data output from SDADC is valid." bitfld.long 0xC 1. "DFORF,Data FIFO Overrun Flag" "0: No overrun has occurred since the last time the..,1: Overrun has occurred or the DFORF has not been.." newline bitfld.long 0xC 0. "DFFF,Data FIFO Full Flag" "0: The number of data words in FIFO is less than or..,1: The number of data words in FIFO is greater than.." line.long 0x10 "RSER,Request Select and Enable Register" bitfld.long 0x10 17. "WTHDIRS,WDG Threshold Cross Over Event DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." bitfld.long 0x10 16. "DFFDIRS,Data FIFO Full DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." newline bitfld.long 0x10 15. "GGE,Global Gating Enable" "0: Gating feature disabled.,1: Gating feature enabled." bitfld.long 0x10 14. "DIRFWGS,DMA/Interrupt or FIFO Write Gating Select" "0: DMA/Interrupt request is gated.,1: Write to FIFO is gated." newline bitfld.long 0x10 13. "SGARE,Synchronized Gate Assert Request Enable" "0: Global gate signal assertion is not synchronized.,1: Global gate signal assertion is synchronized.." bitfld.long 0x10 12. "CLERE,Capture Last Event Request Enable" "0: Don\qt copy the last data word/timestamp.,1: Copy the last data word and timestamp if.." newline bitfld.long 0x10 11. "CTRE,Capture TimeStamp Request Enable" "0: Don\qt capture the timestamp.,1: Capture the timestamp information inside FIFO." bitfld.long 0x10 3. "WTHDIRE,WDG Threshold Cross Over Event DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled on WDG..,1: Interrupt/DMA request is enabled on WDG.." newline bitfld.long 0x10 2. "CDVEE,Conversion Data Valid Event Enable" "0: Event output disabled.,1: Event output assertion/deassertion based on the.." bitfld.long 0x10 1. "DFORIE,Data FIFO Overrun Interrupt Enable" "0: Interrupt request is disabled when data FIFO..,1: Interrupt request is enabled when data FIFO.." newline bitfld.long 0x10 0. "DFFDIRE,Data FIFO Full DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled when data FIFO..,1: Interrupt/DMA request is enabled when data FIFO.." line.long 0x14 "OSDR,Output Settling Delay Register" hexmask.long.byte 0x14 0.--7. 1. "OSD,Output Settling Delay" line.long 0x18 "FCR,FIFO Control Register" bitfld.long 0x18 16. "FRST,FIFO Flush Reset" "0: No effect.,1: Generate a single cycle reset event to flush the.." hexmask.long.byte 0x18 8.--11. 1. "FTHLD,FIFO Threshold" newline bitfld.long 0x18 3. "FOWEN,FIFO Over Write Enable" "0: Data FIFO OW option disabled.,1: Data FIFO OW option enabled." bitfld.long 0x18 1.--2. "FSIZE,FIFO Size" "0: FIFO depth = 1 data word,1: FIFO depth = 4 data words,2: FIFO depth = 8 data words,3: FIFO depth = 16 data words" newline bitfld.long 0x18 0. "FE,FIFO Enable" "0: Data FIFO is not enabled for multiple data..,1: Data FIFO is enabled; FIFO depth is indicated by.." line.long 0x1C "STKR,Software Trigger Key Register" hexmask.long.word 0x1C 0.--15. 1. "ST_KEY,Software Trigger Key" rgroup.long 0x20++0x3 line.long 0x0 "CDR,Converted Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CDATA,Converted Data Register" group.long 0x24++0x3 line.long 0x0 "WTHHLR,WDG Threshold Register" hexmask.long.word 0x0 16.--31. 1. "THRH,WDG Upper Threshold Value" hexmask.long.word 0x0 0.--15. 1. "THRL,WDG Lower Threshold Value" rgroup.long 0x28++0x7 line.long 0x0 "LDREG,Latest Data Register" hexmask.long.word 0x0 0.--15. 1. "LDR,Latest Data Register" line.long 0x4 "LTREG,Latest Time-Stamp Register" hexmask.long.tbyte 0x4 0.--23. 1. "LTR,Latest Time-Stamp Register" group.long 0x30++0x3 line.long 0x0 "PSICR,PSI Control Register" hexmask.long.byte 0x0 10.--13. 1. "DEST,Destination Address of Decimation Filter or DSPL module" bitfld.long 0x0 8.--9. "RSVRD,This bit is Read/Write independent of DSPL module availability but it is functional only when DSPL module in not present." "0,1,2,3" newline bitfld.long 0x0 7. "FLUSH,Master block Flush request" "0: No flush request.,1: Flush request." bitfld.long 0x0 6. "RPSI,Return Parallel Side Interface" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "MESSAGE_TAG,The MESSAGE_TAG bit fields are used to route the data to different sub-blocks inside the decimation filter." bitfld.long 0x0 1. "INIT,Initialization Mode" "0: Normal mode.,1: Initialization mode." newline bitfld.long 0x0 0. "PSIEN,Parallel Side Interface (PSI) Enable" "0: Disable.,1: Enable." tree.end tree "SDADC_7" base ad:0x70980000 group.long 0x0++0x1F line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 31. "EXTFILTER,External Filter selection" "0: Only Internal Filter (Finished and valid data),1: External Filter (Raw data after COMB filter to.." bitfld.long 0x0 30. "LTMW,Level Trigger Mode selection for Watchdog" "0: Level trigger mode,1: Hysteresis mode" newline hexmask.long.byte 0x0 24.--28. 1. "PDR,Programmable Decimation Rate" bitfld.long 0x0 20.--22. "PGAN,Programmable Gain" "0: Gain = 1,1: Gain = 2,2: Gain = 4,3: Gain = 8,?,?,?,7: Gain = 16" newline bitfld.long 0x0 19. "ODF,Output Data Format" "0: Output data is unsigned,1: Output data is signed and sign extended to 16 bits" bitfld.long 0x0 18. "ODA,Output Data Alignment" "0: Output data is right-aligned,1: Output data is left-aligned" newline bitfld.long 0x0 17. "EMSEL,External Modulator Selection" "0: External modulator data and clock inputs are..,1: External modulator data stream and clock inputs.." bitfld.long 0x0 16. "HPFEN,High Pass Filter Enable" "0: High-pass (DC removal) filter is disabled,1: High-pass (DC removal) filter is enabled" newline bitfld.long 0x0 15. "WDGEN,Watchdog Enable" "0: WDG disabled,1: WDG is enabled" bitfld.long 0x0 13.--14. "TRIGEDSEL,Trigger Edge Selection" "0: Falling edge of trigger input is selected,1: Rising edge of trigger input is selected,2: Both edges of trigger input are selected,3: Both edges of trigger input are selected" newline bitfld.long 0x0 12. "TRIGEN,Trigger Enable" "0: Trigger input is disabled,1: Trigger input is enabled" hexmask.long.byte 0x0 8.--11. 1. "TRIGSEL,Trigger Input Selection" newline bitfld.long 0x0 7. "FRZ,Freeze" "0: Conversions are not stopped,1: Conversions are stopped" bitfld.long 0x0 6. "BANDSEL,Output Data Rate Bandwidth Selection" "0: 1/3 (default),1: 1/6" newline bitfld.long 0x0 5. "FSEL,ADC Internal Filter Selection" "0: Comb + FIR (default),1: Comb alone" bitfld.long 0x0 4. "VCOMSEL,Common Voltage Bias Selection" "0: Negative input terminal is biased with VREFN,1: Negative input terminal is biased with VREFP/2.." newline bitfld.long 0x0 3. "WRMODE,Wrap-Around Mode" "0: Wraparound mechanism disabled (in this case the..,1: Wraparound mechanism enabled" bitfld.long 0x0 2. "GECEN,Accurate Gain Error Mode Enable" "0: Gain error calibration mode disabled,1: Gain error calibration mode enabled" newline bitfld.long 0x0 1. "MODE,Mode selection" "0: Differential input mode selected,1: Single-ended input mode selected" bitfld.long 0x0 0. "EN,Enable for SDADC block" "0: SDADC internal modulator placed in low..,1: SDADC internal modulator enabled" line.long 0x4 "CSR,Channel Selection Register" hexmask.long.byte 0x4 16.--23. 1. "BIASEN,Bias enable" bitfld.long 0x4 8.--10. "ANCHSEL_WRAP,Analog Channel Selection Wraparound Value (ANCHSEL_WRAP)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "ANCHSEL,Analog Channel Selection (ANCHSEL)" line.long 0x8 "RKR,Reset Key Register" hexmask.long.word 0x8 0.--15. 1. "RESET_KEY,Reset Key" line.long 0xC "SFR,Status Flag Register" bitfld.long 0xC 16.--18. "ANCHSEL_CNT,Analog Channel Selection Counter (ANCHSEL_CNT)" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8. "DFEF,Data FIFO Empty Flag" "0: Data FIFO is not empty.,1: Data FIFO is empty." newline bitfld.long 0xC 4. "WTHH,Watchdog Upper Threshold Cross Over Event" "0: Watchdog Upper Threshold Cross Over Event did..,1: Watchdog Upper Threshold Cross Over Event.." bitfld.long 0xC 3. "WTHL,Watchdog Lower Threshold Cross Over Event" "0: Watchdog Lower Threshold Cross Over Event did..,1: Watchdog Lower Threshold Cross Over Event.." newline bitfld.long 0xC 2. "CDVF,Converted Data Valid Flag" "0: Data output from SDADC is not valid.,1: Data output from SDADC is valid." bitfld.long 0xC 1. "DFORF,Data FIFO Overrun Flag" "0: No overrun has occurred since the last time the..,1: Overrun has occurred or the DFORF has not been.." newline bitfld.long 0xC 0. "DFFF,Data FIFO Full Flag" "0: The number of data words in FIFO is less than or..,1: The number of data words in FIFO is greater than.." line.long 0x10 "RSER,Request Select and Enable Register" bitfld.long 0x10 17. "WTHDIRS,WDG Threshold Cross Over Event DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." bitfld.long 0x10 16. "DFFDIRS,Data FIFO Full DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." newline bitfld.long 0x10 15. "GGE,Global Gating Enable" "0: Gating feature disabled.,1: Gating feature enabled." bitfld.long 0x10 14. "DIRFWGS,DMA/Interrupt or FIFO Write Gating Select" "0: DMA/Interrupt request is gated.,1: Write to FIFO is gated." newline bitfld.long 0x10 13. "SGARE,Synchronized Gate Assert Request Enable" "0: Global gate signal assertion is not synchronized.,1: Global gate signal assertion is synchronized.." bitfld.long 0x10 12. "CLERE,Capture Last Event Request Enable" "0: Don\qt copy the last data word/timestamp.,1: Copy the last data word and timestamp if.." newline bitfld.long 0x10 11. "CTRE,Capture TimeStamp Request Enable" "0: Don\qt capture the timestamp.,1: Capture the timestamp information inside FIFO." bitfld.long 0x10 3. "WTHDIRE,WDG Threshold Cross Over Event DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled on WDG..,1: Interrupt/DMA request is enabled on WDG.." newline bitfld.long 0x10 2. "CDVEE,Conversion Data Valid Event Enable" "0: Event output disabled.,1: Event output assertion/deassertion based on the.." bitfld.long 0x10 1. "DFORIE,Data FIFO Overrun Interrupt Enable" "0: Interrupt request is disabled when data FIFO..,1: Interrupt request is enabled when data FIFO.." newline bitfld.long 0x10 0. "DFFDIRE,Data FIFO Full DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled when data FIFO..,1: Interrupt/DMA request is enabled when data FIFO.." line.long 0x14 "OSDR,Output Settling Delay Register" hexmask.long.byte 0x14 0.--7. 1. "OSD,Output Settling Delay" line.long 0x18 "FCR,FIFO Control Register" bitfld.long 0x18 16. "FRST,FIFO Flush Reset" "0: No effect.,1: Generate a single cycle reset event to flush the.." hexmask.long.byte 0x18 8.--11. 1. "FTHLD,FIFO Threshold" newline bitfld.long 0x18 3. "FOWEN,FIFO Over Write Enable" "0: Data FIFO OW option disabled.,1: Data FIFO OW option enabled." bitfld.long 0x18 1.--2. "FSIZE,FIFO Size" "0: FIFO depth = 1 data word,1: FIFO depth = 4 data words,2: FIFO depth = 8 data words,3: FIFO depth = 16 data words" newline bitfld.long 0x18 0. "FE,FIFO Enable" "0: Data FIFO is not enabled for multiple data..,1: Data FIFO is enabled; FIFO depth is indicated by.." line.long 0x1C "STKR,Software Trigger Key Register" hexmask.long.word 0x1C 0.--15. 1. "ST_KEY,Software Trigger Key" rgroup.long 0x20++0x3 line.long 0x0 "CDR,Converted Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CDATA,Converted Data Register" group.long 0x24++0x3 line.long 0x0 "WTHHLR,WDG Threshold Register" hexmask.long.word 0x0 16.--31. 1. "THRH,WDG Upper Threshold Value" hexmask.long.word 0x0 0.--15. 1. "THRL,WDG Lower Threshold Value" rgroup.long 0x28++0x7 line.long 0x0 "LDREG,Latest Data Register" hexmask.long.word 0x0 0.--15. 1. "LDR,Latest Data Register" line.long 0x4 "LTREG,Latest Time-Stamp Register" hexmask.long.tbyte 0x4 0.--23. 1. "LTR,Latest Time-Stamp Register" group.long 0x30++0x3 line.long 0x0 "PSICR,PSI Control Register" hexmask.long.byte 0x0 10.--13. 1. "DEST,Destination Address of Decimation Filter or DSPL module" bitfld.long 0x0 8.--9. "RSVRD,This bit is Read/Write independent of DSPL module availability but it is functional only when DSPL module in not present." "0,1,2,3" newline bitfld.long 0x0 7. "FLUSH,Master block Flush request" "0: No flush request.,1: Flush request." bitfld.long 0x0 6. "RPSI,Return Parallel Side Interface" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "MESSAGE_TAG,The MESSAGE_TAG bit fields are used to route the data to different sub-blocks inside the decimation filter." bitfld.long 0x0 1. "INIT,Initialization Mode" "0: Normal mode.,1: Initialization mode." newline bitfld.long 0x0 0. "PSIEN,Parallel Side Interface (PSI) Enable" "0: Disable.,1: Enable." tree.end tree "SDADC_8" base ad:0x70384000 group.long 0x0++0x1F line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 31. "EXTFILTER,External Filter selection" "0: Only Internal Filter (Finished and valid data),1: External Filter (Raw data after COMB filter to.." bitfld.long 0x0 30. "LTMW,Level Trigger Mode selection for Watchdog" "0: Level trigger mode,1: Hysteresis mode" newline hexmask.long.byte 0x0 24.--28. 1. "PDR,Programmable Decimation Rate" bitfld.long 0x0 20.--22. "PGAN,Programmable Gain" "0: Gain = 1,1: Gain = 2,2: Gain = 4,3: Gain = 8,?,?,?,7: Gain = 16" newline bitfld.long 0x0 19. "ODF,Output Data Format" "0: Output data is unsigned,1: Output data is signed and sign extended to 16 bits" bitfld.long 0x0 18. "ODA,Output Data Alignment" "0: Output data is right-aligned,1: Output data is left-aligned" newline bitfld.long 0x0 17. "EMSEL,External Modulator Selection" "0: External modulator data and clock inputs are..,1: External modulator data stream and clock inputs.." bitfld.long 0x0 16. "HPFEN,High Pass Filter Enable" "0: High-pass (DC removal) filter is disabled,1: High-pass (DC removal) filter is enabled" newline bitfld.long 0x0 15. "WDGEN,Watchdog Enable" "0: WDG disabled,1: WDG is enabled" bitfld.long 0x0 13.--14. "TRIGEDSEL,Trigger Edge Selection" "0: Falling edge of trigger input is selected,1: Rising edge of trigger input is selected,2: Both edges of trigger input are selected,3: Both edges of trigger input are selected" newline bitfld.long 0x0 12. "TRIGEN,Trigger Enable" "0: Trigger input is disabled,1: Trigger input is enabled" hexmask.long.byte 0x0 8.--11. 1. "TRIGSEL,Trigger Input Selection" newline bitfld.long 0x0 7. "FRZ,Freeze" "0: Conversions are not stopped,1: Conversions are stopped" bitfld.long 0x0 6. "BANDSEL,Output Data Rate Bandwidth Selection" "0: 1/3 (default),1: 1/6" newline bitfld.long 0x0 5. "FSEL,ADC Internal Filter Selection" "0: Comb + FIR (default),1: Comb alone" bitfld.long 0x0 4. "VCOMSEL,Common Voltage Bias Selection" "0: Negative input terminal is biased with VREFN,1: Negative input terminal is biased with VREFP/2.." newline bitfld.long 0x0 3. "WRMODE,Wrap-Around Mode" "0: Wraparound mechanism disabled (in this case the..,1: Wraparound mechanism enabled" bitfld.long 0x0 2. "GECEN,Accurate Gain Error Mode Enable" "0: Gain error calibration mode disabled,1: Gain error calibration mode enabled" newline bitfld.long 0x0 1. "MODE,Mode selection" "0: Differential input mode selected,1: Single-ended input mode selected" bitfld.long 0x0 0. "EN,Enable for SDADC block" "0: SDADC internal modulator placed in low..,1: SDADC internal modulator enabled" line.long 0x4 "CSR,Channel Selection Register" hexmask.long.byte 0x4 16.--23. 1. "BIASEN,Bias enable" bitfld.long 0x4 8.--10. "ANCHSEL_WRAP,Analog Channel Selection Wraparound Value (ANCHSEL_WRAP)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "ANCHSEL,Analog Channel Selection (ANCHSEL)" line.long 0x8 "RKR,Reset Key Register" hexmask.long.word 0x8 0.--15. 1. "RESET_KEY,Reset Key" line.long 0xC "SFR,Status Flag Register" bitfld.long 0xC 16.--18. "ANCHSEL_CNT,Analog Channel Selection Counter (ANCHSEL_CNT)" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8. "DFEF,Data FIFO Empty Flag" "0: Data FIFO is not empty.,1: Data FIFO is empty." newline bitfld.long 0xC 4. "WTHH,Watchdog Upper Threshold Cross Over Event" "0: Watchdog Upper Threshold Cross Over Event did..,1: Watchdog Upper Threshold Cross Over Event.." bitfld.long 0xC 3. "WTHL,Watchdog Lower Threshold Cross Over Event" "0: Watchdog Lower Threshold Cross Over Event did..,1: Watchdog Lower Threshold Cross Over Event.." newline bitfld.long 0xC 2. "CDVF,Converted Data Valid Flag" "0: Data output from SDADC is not valid.,1: Data output from SDADC is valid." bitfld.long 0xC 1. "DFORF,Data FIFO Overrun Flag" "0: No overrun has occurred since the last time the..,1: Overrun has occurred or the DFORF has not been.." newline bitfld.long 0xC 0. "DFFF,Data FIFO Full Flag" "0: The number of data words in FIFO is less than or..,1: The number of data words in FIFO is greater than.." line.long 0x10 "RSER,Request Select and Enable Register" bitfld.long 0x10 17. "WTHDIRS,WDG Threshold Cross Over Event DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." bitfld.long 0x10 16. "DFFDIRS,Data FIFO Full DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." newline bitfld.long 0x10 15. "GGE,Global Gating Enable" "0: Gating feature disabled.,1: Gating feature enabled." bitfld.long 0x10 14. "DIRFWGS,DMA/Interrupt or FIFO Write Gating Select" "0: DMA/Interrupt request is gated.,1: Write to FIFO is gated." newline bitfld.long 0x10 13. "SGARE,Synchronized Gate Assert Request Enable" "0: Global gate signal assertion is not synchronized.,1: Global gate signal assertion is synchronized.." bitfld.long 0x10 12. "CLERE,Capture Last Event Request Enable" "0: Don\qt copy the last data word/timestamp.,1: Copy the last data word and timestamp if.." newline bitfld.long 0x10 11. "CTRE,Capture TimeStamp Request Enable" "0: Don\qt capture the timestamp.,1: Capture the timestamp information inside FIFO." bitfld.long 0x10 3. "WTHDIRE,WDG Threshold Cross Over Event DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled on WDG..,1: Interrupt/DMA request is enabled on WDG.." newline bitfld.long 0x10 2. "CDVEE,Conversion Data Valid Event Enable" "0: Event output disabled.,1: Event output assertion/deassertion based on the.." bitfld.long 0x10 1. "DFORIE,Data FIFO Overrun Interrupt Enable" "0: Interrupt request is disabled when data FIFO..,1: Interrupt request is enabled when data FIFO.." newline bitfld.long 0x10 0. "DFFDIRE,Data FIFO Full DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled when data FIFO..,1: Interrupt/DMA request is enabled when data FIFO.." line.long 0x14 "OSDR,Output Settling Delay Register" hexmask.long.byte 0x14 0.--7. 1. "OSD,Output Settling Delay" line.long 0x18 "FCR,FIFO Control Register" bitfld.long 0x18 16. "FRST,FIFO Flush Reset" "0: No effect.,1: Generate a single cycle reset event to flush the.." hexmask.long.byte 0x18 8.--11. 1. "FTHLD,FIFO Threshold" newline bitfld.long 0x18 3. "FOWEN,FIFO Over Write Enable" "0: Data FIFO OW option disabled.,1: Data FIFO OW option enabled." bitfld.long 0x18 1.--2. "FSIZE,FIFO Size" "0: FIFO depth = 1 data word,1: FIFO depth = 4 data words,2: FIFO depth = 8 data words,3: FIFO depth = 16 data words" newline bitfld.long 0x18 0. "FE,FIFO Enable" "0: Data FIFO is not enabled for multiple data..,1: Data FIFO is enabled; FIFO depth is indicated by.." line.long 0x1C "STKR,Software Trigger Key Register" hexmask.long.word 0x1C 0.--15. 1. "ST_KEY,Software Trigger Key" rgroup.long 0x20++0x3 line.long 0x0 "CDR,Converted Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CDATA,Converted Data Register" group.long 0x24++0x3 line.long 0x0 "WTHHLR,WDG Threshold Register" hexmask.long.word 0x0 16.--31. 1. "THRH,WDG Upper Threshold Value" hexmask.long.word 0x0 0.--15. 1. "THRL,WDG Lower Threshold Value" rgroup.long 0x28++0x7 line.long 0x0 "LDREG,Latest Data Register" hexmask.long.word 0x0 0.--15. 1. "LDR,Latest Data Register" line.long 0x4 "LTREG,Latest Time-Stamp Register" hexmask.long.tbyte 0x4 0.--23. 1. "LTR,Latest Time-Stamp Register" group.long 0x30++0x3 line.long 0x0 "PSICR,PSI Control Register" hexmask.long.byte 0x0 10.--13. 1. "DEST,Destination Address of Decimation Filter or DSPL module" bitfld.long 0x0 8.--9. "RSVRD,This bit is Read/Write independent of DSPL module availability but it is functional only when DSPL module in not present." "0,1,2,3" newline bitfld.long 0x0 7. "FLUSH,Master block Flush request" "0: No flush request.,1: Flush request." bitfld.long 0x0 6. "RPSI,Return Parallel Side Interface" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "MESSAGE_TAG,The MESSAGE_TAG bit fields are used to route the data to different sub-blocks inside the decimation filter." bitfld.long 0x0 1. "INIT,Initialization Mode" "0: Normal mode.,1: Initialization mode." newline bitfld.long 0x0 0. "PSIEN,Parallel Side Interface (PSI) Enable" "0: Disable.,1: Enable." tree.end tree "SDADC_9" base ad:0x70984000 group.long 0x0++0x1F line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 31. "EXTFILTER,External Filter selection" "0: Only Internal Filter (Finished and valid data),1: External Filter (Raw data after COMB filter to.." bitfld.long 0x0 30. "LTMW,Level Trigger Mode selection for Watchdog" "0: Level trigger mode,1: Hysteresis mode" newline hexmask.long.byte 0x0 24.--28. 1. "PDR,Programmable Decimation Rate" bitfld.long 0x0 20.--22. "PGAN,Programmable Gain" "0: Gain = 1,1: Gain = 2,2: Gain = 4,3: Gain = 8,?,?,?,7: Gain = 16" newline bitfld.long 0x0 19. "ODF,Output Data Format" "0: Output data is unsigned,1: Output data is signed and sign extended to 16 bits" bitfld.long 0x0 18. "ODA,Output Data Alignment" "0: Output data is right-aligned,1: Output data is left-aligned" newline bitfld.long 0x0 17. "EMSEL,External Modulator Selection" "0: External modulator data and clock inputs are..,1: External modulator data stream and clock inputs.." bitfld.long 0x0 16. "HPFEN,High Pass Filter Enable" "0: High-pass (DC removal) filter is disabled,1: High-pass (DC removal) filter is enabled" newline bitfld.long 0x0 15. "WDGEN,Watchdog Enable" "0: WDG disabled,1: WDG is enabled" bitfld.long 0x0 13.--14. "TRIGEDSEL,Trigger Edge Selection" "0: Falling edge of trigger input is selected,1: Rising edge of trigger input is selected,2: Both edges of trigger input are selected,3: Both edges of trigger input are selected" newline bitfld.long 0x0 12. "TRIGEN,Trigger Enable" "0: Trigger input is disabled,1: Trigger input is enabled" hexmask.long.byte 0x0 8.--11. 1. "TRIGSEL,Trigger Input Selection" newline bitfld.long 0x0 7. "FRZ,Freeze" "0: Conversions are not stopped,1: Conversions are stopped" bitfld.long 0x0 6. "BANDSEL,Output Data Rate Bandwidth Selection" "0: 1/3 (default),1: 1/6" newline bitfld.long 0x0 5. "FSEL,ADC Internal Filter Selection" "0: Comb + FIR (default),1: Comb alone" bitfld.long 0x0 4. "VCOMSEL,Common Voltage Bias Selection" "0: Negative input terminal is biased with VREFN,1: Negative input terminal is biased with VREFP/2.." newline bitfld.long 0x0 3. "WRMODE,Wrap-Around Mode" "0: Wraparound mechanism disabled (in this case the..,1: Wraparound mechanism enabled" bitfld.long 0x0 2. "GECEN,Accurate Gain Error Mode Enable" "0: Gain error calibration mode disabled,1: Gain error calibration mode enabled" newline bitfld.long 0x0 1. "MODE,Mode selection" "0: Differential input mode selected,1: Single-ended input mode selected" bitfld.long 0x0 0. "EN,Enable for SDADC block" "0: SDADC internal modulator placed in low..,1: SDADC internal modulator enabled" line.long 0x4 "CSR,Channel Selection Register" hexmask.long.byte 0x4 16.--23. 1. "BIASEN,Bias enable" bitfld.long 0x4 8.--10. "ANCHSEL_WRAP,Analog Channel Selection Wraparound Value (ANCHSEL_WRAP)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "ANCHSEL,Analog Channel Selection (ANCHSEL)" line.long 0x8 "RKR,Reset Key Register" hexmask.long.word 0x8 0.--15. 1. "RESET_KEY,Reset Key" line.long 0xC "SFR,Status Flag Register" bitfld.long 0xC 16.--18. "ANCHSEL_CNT,Analog Channel Selection Counter (ANCHSEL_CNT)" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8. "DFEF,Data FIFO Empty Flag" "0: Data FIFO is not empty.,1: Data FIFO is empty." newline bitfld.long 0xC 4. "WTHH,Watchdog Upper Threshold Cross Over Event" "0: Watchdog Upper Threshold Cross Over Event did..,1: Watchdog Upper Threshold Cross Over Event.." bitfld.long 0xC 3. "WTHL,Watchdog Lower Threshold Cross Over Event" "0: Watchdog Lower Threshold Cross Over Event did..,1: Watchdog Lower Threshold Cross Over Event.." newline bitfld.long 0xC 2. "CDVF,Converted Data Valid Flag" "0: Data output from SDADC is not valid.,1: Data output from SDADC is valid." bitfld.long 0xC 1. "DFORF,Data FIFO Overrun Flag" "0: No overrun has occurred since the last time the..,1: Overrun has occurred or the DFORF has not been.." newline bitfld.long 0xC 0. "DFFF,Data FIFO Full Flag" "0: The number of data words in FIFO is less than or..,1: The number of data words in FIFO is greater than.." line.long 0x10 "RSER,Request Select and Enable Register" bitfld.long 0x10 17. "WTHDIRS,WDG Threshold Cross Over Event DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." bitfld.long 0x10 16. "DFFDIRS,Data FIFO Full DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." newline bitfld.long 0x10 15. "GGE,Global Gating Enable" "0: Gating feature disabled.,1: Gating feature enabled." bitfld.long 0x10 14. "DIRFWGS,DMA/Interrupt or FIFO Write Gating Select" "0: DMA/Interrupt request is gated.,1: Write to FIFO is gated." newline bitfld.long 0x10 13. "SGARE,Synchronized Gate Assert Request Enable" "0: Global gate signal assertion is not synchronized.,1: Global gate signal assertion is synchronized.." bitfld.long 0x10 12. "CLERE,Capture Last Event Request Enable" "0: Don\qt copy the last data word/timestamp.,1: Copy the last data word and timestamp if.." newline bitfld.long 0x10 11. "CTRE,Capture TimeStamp Request Enable" "0: Don\qt capture the timestamp.,1: Capture the timestamp information inside FIFO." bitfld.long 0x10 3. "WTHDIRE,WDG Threshold Cross Over Event DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled on WDG..,1: Interrupt/DMA request is enabled on WDG.." newline bitfld.long 0x10 2. "CDVEE,Conversion Data Valid Event Enable" "0: Event output disabled.,1: Event output assertion/deassertion based on the.." bitfld.long 0x10 1. "DFORIE,Data FIFO Overrun Interrupt Enable" "0: Interrupt request is disabled when data FIFO..,1: Interrupt request is enabled when data FIFO.." newline bitfld.long 0x10 0. "DFFDIRE,Data FIFO Full DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled when data FIFO..,1: Interrupt/DMA request is enabled when data FIFO.." line.long 0x14 "OSDR,Output Settling Delay Register" hexmask.long.byte 0x14 0.--7. 1. "OSD,Output Settling Delay" line.long 0x18 "FCR,FIFO Control Register" bitfld.long 0x18 16. "FRST,FIFO Flush Reset" "0: No effect.,1: Generate a single cycle reset event to flush the.." hexmask.long.byte 0x18 8.--11. 1. "FTHLD,FIFO Threshold" newline bitfld.long 0x18 3. "FOWEN,FIFO Over Write Enable" "0: Data FIFO OW option disabled.,1: Data FIFO OW option enabled." bitfld.long 0x18 1.--2. "FSIZE,FIFO Size" "0: FIFO depth = 1 data word,1: FIFO depth = 4 data words,2: FIFO depth = 8 data words,3: FIFO depth = 16 data words" newline bitfld.long 0x18 0. "FE,FIFO Enable" "0: Data FIFO is not enabled for multiple data..,1: Data FIFO is enabled; FIFO depth is indicated by.." line.long 0x1C "STKR,Software Trigger Key Register" hexmask.long.word 0x1C 0.--15. 1. "ST_KEY,Software Trigger Key" rgroup.long 0x20++0x3 line.long 0x0 "CDR,Converted Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CDATA,Converted Data Register" group.long 0x24++0x3 line.long 0x0 "WTHHLR,WDG Threshold Register" hexmask.long.word 0x0 16.--31. 1. "THRH,WDG Upper Threshold Value" hexmask.long.word 0x0 0.--15. 1. "THRL,WDG Lower Threshold Value" rgroup.long 0x28++0x7 line.long 0x0 "LDREG,Latest Data Register" hexmask.long.word 0x0 0.--15. 1. "LDR,Latest Data Register" line.long 0x4 "LTREG,Latest Time-Stamp Register" hexmask.long.tbyte 0x4 0.--23. 1. "LTR,Latest Time-Stamp Register" group.long 0x30++0x3 line.long 0x0 "PSICR,PSI Control Register" hexmask.long.byte 0x0 10.--13. 1. "DEST,Destination Address of Decimation Filter or DSPL module" bitfld.long 0x0 8.--9. "RSVRD,This bit is Read/Write independent of DSPL module availability but it is functional only when DSPL module in not present." "0,1,2,3" newline bitfld.long 0x0 7. "FLUSH,Master block Flush request" "0: No flush request.,1: Flush request." bitfld.long 0x0 6. "RPSI,Return Parallel Side Interface" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "MESSAGE_TAG,The MESSAGE_TAG bit fields are used to route the data to different sub-blocks inside the decimation filter." bitfld.long 0x0 1. "INIT,Initialization Mode" "0: Normal mode.,1: Initialization mode." newline bitfld.long 0x0 0. "PSIEN,Parallel Side Interface (PSI) Enable" "0: Disable.,1: Enable." tree.end tree "SDADC_10" base ad:0x70388000 group.long 0x0++0x1F line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 31. "EXTFILTER,External Filter selection" "0: Only Internal Filter (Finished and valid data),1: External Filter (Raw data after COMB filter to.." bitfld.long 0x0 30. "LTMW,Level Trigger Mode selection for Watchdog" "0: Level trigger mode,1: Hysteresis mode" newline hexmask.long.byte 0x0 24.--28. 1. "PDR,Programmable Decimation Rate" bitfld.long 0x0 20.--22. "PGAN,Programmable Gain" "0: Gain = 1,1: Gain = 2,2: Gain = 4,3: Gain = 8,?,?,?,7: Gain = 16" newline bitfld.long 0x0 19. "ODF,Output Data Format" "0: Output data is unsigned,1: Output data is signed and sign extended to 16 bits" bitfld.long 0x0 18. "ODA,Output Data Alignment" "0: Output data is right-aligned,1: Output data is left-aligned" newline bitfld.long 0x0 17. "EMSEL,External Modulator Selection" "0: External modulator data and clock inputs are..,1: External modulator data stream and clock inputs.." bitfld.long 0x0 16. "HPFEN,High Pass Filter Enable" "0: High-pass (DC removal) filter is disabled,1: High-pass (DC removal) filter is enabled" newline bitfld.long 0x0 15. "WDGEN,Watchdog Enable" "0: WDG disabled,1: WDG is enabled" bitfld.long 0x0 13.--14. "TRIGEDSEL,Trigger Edge Selection" "0: Falling edge of trigger input is selected,1: Rising edge of trigger input is selected,2: Both edges of trigger input are selected,3: Both edges of trigger input are selected" newline bitfld.long 0x0 12. "TRIGEN,Trigger Enable" "0: Trigger input is disabled,1: Trigger input is enabled" hexmask.long.byte 0x0 8.--11. 1. "TRIGSEL,Trigger Input Selection" newline bitfld.long 0x0 7. "FRZ,Freeze" "0: Conversions are not stopped,1: Conversions are stopped" bitfld.long 0x0 6. "BANDSEL,Output Data Rate Bandwidth Selection" "0: 1/3 (default),1: 1/6" newline bitfld.long 0x0 5. "FSEL,ADC Internal Filter Selection" "0: Comb + FIR (default),1: Comb alone" bitfld.long 0x0 4. "VCOMSEL,Common Voltage Bias Selection" "0: Negative input terminal is biased with VREFN,1: Negative input terminal is biased with VREFP/2.." newline bitfld.long 0x0 3. "WRMODE,Wrap-Around Mode" "0: Wraparound mechanism disabled (in this case the..,1: Wraparound mechanism enabled" bitfld.long 0x0 2. "GECEN,Accurate Gain Error Mode Enable" "0: Gain error calibration mode disabled,1: Gain error calibration mode enabled" newline bitfld.long 0x0 1. "MODE,Mode selection" "0: Differential input mode selected,1: Single-ended input mode selected" bitfld.long 0x0 0. "EN,Enable for SDADC block" "0: SDADC internal modulator placed in low..,1: SDADC internal modulator enabled" line.long 0x4 "CSR,Channel Selection Register" hexmask.long.byte 0x4 16.--23. 1. "BIASEN,Bias enable" bitfld.long 0x4 8.--10. "ANCHSEL_WRAP,Analog Channel Selection Wraparound Value (ANCHSEL_WRAP)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "ANCHSEL,Analog Channel Selection (ANCHSEL)" line.long 0x8 "RKR,Reset Key Register" hexmask.long.word 0x8 0.--15. 1. "RESET_KEY,Reset Key" line.long 0xC "SFR,Status Flag Register" bitfld.long 0xC 16.--18. "ANCHSEL_CNT,Analog Channel Selection Counter (ANCHSEL_CNT)" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8. "DFEF,Data FIFO Empty Flag" "0: Data FIFO is not empty.,1: Data FIFO is empty." newline bitfld.long 0xC 4. "WTHH,Watchdog Upper Threshold Cross Over Event" "0: Watchdog Upper Threshold Cross Over Event did..,1: Watchdog Upper Threshold Cross Over Event.." bitfld.long 0xC 3. "WTHL,Watchdog Lower Threshold Cross Over Event" "0: Watchdog Lower Threshold Cross Over Event did..,1: Watchdog Lower Threshold Cross Over Event.." newline bitfld.long 0xC 2. "CDVF,Converted Data Valid Flag" "0: Data output from SDADC is not valid.,1: Data output from SDADC is valid." bitfld.long 0xC 1. "DFORF,Data FIFO Overrun Flag" "0: No overrun has occurred since the last time the..,1: Overrun has occurred or the DFORF has not been.." newline bitfld.long 0xC 0. "DFFF,Data FIFO Full Flag" "0: The number of data words in FIFO is less than or..,1: The number of data words in FIFO is greater than.." line.long 0x10 "RSER,Request Select and Enable Register" bitfld.long 0x10 17. "WTHDIRS,WDG Threshold Cross Over Event DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." bitfld.long 0x10 16. "DFFDIRS,Data FIFO Full DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." newline bitfld.long 0x10 15. "GGE,Global Gating Enable" "0: Gating feature disabled.,1: Gating feature enabled." bitfld.long 0x10 14. "DIRFWGS,DMA/Interrupt or FIFO Write Gating Select" "0: DMA/Interrupt request is gated.,1: Write to FIFO is gated." newline bitfld.long 0x10 13. "SGARE,Synchronized Gate Assert Request Enable" "0: Global gate signal assertion is not synchronized.,1: Global gate signal assertion is synchronized.." bitfld.long 0x10 12. "CLERE,Capture Last Event Request Enable" "0: Don\qt copy the last data word/timestamp.,1: Copy the last data word and timestamp if.." newline bitfld.long 0x10 11. "CTRE,Capture TimeStamp Request Enable" "0: Don\qt capture the timestamp.,1: Capture the timestamp information inside FIFO." bitfld.long 0x10 3. "WTHDIRE,WDG Threshold Cross Over Event DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled on WDG..,1: Interrupt/DMA request is enabled on WDG.." newline bitfld.long 0x10 2. "CDVEE,Conversion Data Valid Event Enable" "0: Event output disabled.,1: Event output assertion/deassertion based on the.." bitfld.long 0x10 1. "DFORIE,Data FIFO Overrun Interrupt Enable" "0: Interrupt request is disabled when data FIFO..,1: Interrupt request is enabled when data FIFO.." newline bitfld.long 0x10 0. "DFFDIRE,Data FIFO Full DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled when data FIFO..,1: Interrupt/DMA request is enabled when data FIFO.." line.long 0x14 "OSDR,Output Settling Delay Register" hexmask.long.byte 0x14 0.--7. 1. "OSD,Output Settling Delay" line.long 0x18 "FCR,FIFO Control Register" bitfld.long 0x18 16. "FRST,FIFO Flush Reset" "0: No effect.,1: Generate a single cycle reset event to flush the.." hexmask.long.byte 0x18 8.--11. 1. "FTHLD,FIFO Threshold" newline bitfld.long 0x18 3. "FOWEN,FIFO Over Write Enable" "0: Data FIFO OW option disabled.,1: Data FIFO OW option enabled." bitfld.long 0x18 1.--2. "FSIZE,FIFO Size" "0: FIFO depth = 1 data word,1: FIFO depth = 4 data words,2: FIFO depth = 8 data words,3: FIFO depth = 16 data words" newline bitfld.long 0x18 0. "FE,FIFO Enable" "0: Data FIFO is not enabled for multiple data..,1: Data FIFO is enabled; FIFO depth is indicated by.." line.long 0x1C "STKR,Software Trigger Key Register" hexmask.long.word 0x1C 0.--15. 1. "ST_KEY,Software Trigger Key" rgroup.long 0x20++0x3 line.long 0x0 "CDR,Converted Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CDATA,Converted Data Register" group.long 0x24++0x3 line.long 0x0 "WTHHLR,WDG Threshold Register" hexmask.long.word 0x0 16.--31. 1. "THRH,WDG Upper Threshold Value" hexmask.long.word 0x0 0.--15. 1. "THRL,WDG Lower Threshold Value" rgroup.long 0x28++0x7 line.long 0x0 "LDREG,Latest Data Register" hexmask.long.word 0x0 0.--15. 1. "LDR,Latest Data Register" line.long 0x4 "LTREG,Latest Time-Stamp Register" hexmask.long.tbyte 0x4 0.--23. 1. "LTR,Latest Time-Stamp Register" group.long 0x30++0x3 line.long 0x0 "PSICR,PSI Control Register" hexmask.long.byte 0x0 10.--13. 1. "DEST,Destination Address of Decimation Filter or DSPL module" bitfld.long 0x0 8.--9. "RSVRD,This bit is Read/Write independent of DSPL module availability but it is functional only when DSPL module in not present." "0,1,2,3" newline bitfld.long 0x0 7. "FLUSH,Master block Flush request" "0: No flush request.,1: Flush request." bitfld.long 0x0 6. "RPSI,Return Parallel Side Interface" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "MESSAGE_TAG,The MESSAGE_TAG bit fields are used to route the data to different sub-blocks inside the decimation filter." bitfld.long 0x0 1. "INIT,Initialization Mode" "0: Normal mode.,1: Initialization mode." newline bitfld.long 0x0 0. "PSIEN,Parallel Side Interface (PSI) Enable" "0: Disable.,1: Enable." tree.end tree "SDADC_11" base ad:0x70988000 group.long 0x0++0x1F line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 31. "EXTFILTER,External Filter selection" "0: Only Internal Filter (Finished and valid data),1: External Filter (Raw data after COMB filter to.." bitfld.long 0x0 30. "LTMW,Level Trigger Mode selection for Watchdog" "0: Level trigger mode,1: Hysteresis mode" newline hexmask.long.byte 0x0 24.--28. 1. "PDR,Programmable Decimation Rate" bitfld.long 0x0 20.--22. "PGAN,Programmable Gain" "0: Gain = 1,1: Gain = 2,2: Gain = 4,3: Gain = 8,?,?,?,7: Gain = 16" newline bitfld.long 0x0 19. "ODF,Output Data Format" "0: Output data is unsigned,1: Output data is signed and sign extended to 16 bits" bitfld.long 0x0 18. "ODA,Output Data Alignment" "0: Output data is right-aligned,1: Output data is left-aligned" newline bitfld.long 0x0 17. "EMSEL,External Modulator Selection" "0: External modulator data and clock inputs are..,1: External modulator data stream and clock inputs.." bitfld.long 0x0 16. "HPFEN,High Pass Filter Enable" "0: High-pass (DC removal) filter is disabled,1: High-pass (DC removal) filter is enabled" newline bitfld.long 0x0 15. "WDGEN,Watchdog Enable" "0: WDG disabled,1: WDG is enabled" bitfld.long 0x0 13.--14. "TRIGEDSEL,Trigger Edge Selection" "0: Falling edge of trigger input is selected,1: Rising edge of trigger input is selected,2: Both edges of trigger input are selected,3: Both edges of trigger input are selected" newline bitfld.long 0x0 12. "TRIGEN,Trigger Enable" "0: Trigger input is disabled,1: Trigger input is enabled" hexmask.long.byte 0x0 8.--11. 1. "TRIGSEL,Trigger Input Selection" newline bitfld.long 0x0 7. "FRZ,Freeze" "0: Conversions are not stopped,1: Conversions are stopped" bitfld.long 0x0 6. "BANDSEL,Output Data Rate Bandwidth Selection" "0: 1/3 (default),1: 1/6" newline bitfld.long 0x0 5. "FSEL,ADC Internal Filter Selection" "0: Comb + FIR (default),1: Comb alone" bitfld.long 0x0 4. "VCOMSEL,Common Voltage Bias Selection" "0: Negative input terminal is biased with VREFN,1: Negative input terminal is biased with VREFP/2.." newline bitfld.long 0x0 3. "WRMODE,Wrap-Around Mode" "0: Wraparound mechanism disabled (in this case the..,1: Wraparound mechanism enabled" bitfld.long 0x0 2. "GECEN,Accurate Gain Error Mode Enable" "0: Gain error calibration mode disabled,1: Gain error calibration mode enabled" newline bitfld.long 0x0 1. "MODE,Mode selection" "0: Differential input mode selected,1: Single-ended input mode selected" bitfld.long 0x0 0. "EN,Enable for SDADC block" "0: SDADC internal modulator placed in low..,1: SDADC internal modulator enabled" line.long 0x4 "CSR,Channel Selection Register" hexmask.long.byte 0x4 16.--23. 1. "BIASEN,Bias enable" bitfld.long 0x4 8.--10. "ANCHSEL_WRAP,Analog Channel Selection Wraparound Value (ANCHSEL_WRAP)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "ANCHSEL,Analog Channel Selection (ANCHSEL)" line.long 0x8 "RKR,Reset Key Register" hexmask.long.word 0x8 0.--15. 1. "RESET_KEY,Reset Key" line.long 0xC "SFR,Status Flag Register" bitfld.long 0xC 16.--18. "ANCHSEL_CNT,Analog Channel Selection Counter (ANCHSEL_CNT)" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8. "DFEF,Data FIFO Empty Flag" "0: Data FIFO is not empty.,1: Data FIFO is empty." newline bitfld.long 0xC 4. "WTHH,Watchdog Upper Threshold Cross Over Event" "0: Watchdog Upper Threshold Cross Over Event did..,1: Watchdog Upper Threshold Cross Over Event.." bitfld.long 0xC 3. "WTHL,Watchdog Lower Threshold Cross Over Event" "0: Watchdog Lower Threshold Cross Over Event did..,1: Watchdog Lower Threshold Cross Over Event.." newline bitfld.long 0xC 2. "CDVF,Converted Data Valid Flag" "0: Data output from SDADC is not valid.,1: Data output from SDADC is valid." bitfld.long 0xC 1. "DFORF,Data FIFO Overrun Flag" "0: No overrun has occurred since the last time the..,1: Overrun has occurred or the DFORF has not been.." newline bitfld.long 0xC 0. "DFFF,Data FIFO Full Flag" "0: The number of data words in FIFO is less than or..,1: The number of data words in FIFO is greater than.." line.long 0x10 "RSER,Request Select and Enable Register" bitfld.long 0x10 17. "WTHDIRS,WDG Threshold Cross Over Event DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." bitfld.long 0x10 16. "DFFDIRS,Data FIFO Full DMA/Interrupt Request Select" "0: Interrupt request is selected.,1: DMA request is selected." newline bitfld.long 0x10 15. "GGE,Global Gating Enable" "0: Gating feature disabled.,1: Gating feature enabled." bitfld.long 0x10 14. "DIRFWGS,DMA/Interrupt or FIFO Write Gating Select" "0: DMA/Interrupt request is gated.,1: Write to FIFO is gated." newline bitfld.long 0x10 13. "SGARE,Synchronized Gate Assert Request Enable" "0: Global gate signal assertion is not synchronized.,1: Global gate signal assertion is synchronized.." bitfld.long 0x10 12. "CLERE,Capture Last Event Request Enable" "0: Don\qt copy the last data word/timestamp.,1: Copy the last data word and timestamp if.." newline bitfld.long 0x10 11. "CTRE,Capture TimeStamp Request Enable" "0: Don\qt capture the timestamp.,1: Capture the timestamp information inside FIFO." bitfld.long 0x10 3. "WTHDIRE,WDG Threshold Cross Over Event DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled on WDG..,1: Interrupt/DMA request is enabled on WDG.." newline bitfld.long 0x10 2. "CDVEE,Conversion Data Valid Event Enable" "0: Event output disabled.,1: Event output assertion/deassertion based on the.." bitfld.long 0x10 1. "DFORIE,Data FIFO Overrun Interrupt Enable" "0: Interrupt request is disabled when data FIFO..,1: Interrupt request is enabled when data FIFO.." newline bitfld.long 0x10 0. "DFFDIRE,Data FIFO Full DMA/Interrupt Request Enable" "0: Interrupt/DMA request is disabled when data FIFO..,1: Interrupt/DMA request is enabled when data FIFO.." line.long 0x14 "OSDR,Output Settling Delay Register" hexmask.long.byte 0x14 0.--7. 1. "OSD,Output Settling Delay" line.long 0x18 "FCR,FIFO Control Register" bitfld.long 0x18 16. "FRST,FIFO Flush Reset" "0: No effect.,1: Generate a single cycle reset event to flush the.." hexmask.long.byte 0x18 8.--11. 1. "FTHLD,FIFO Threshold" newline bitfld.long 0x18 3. "FOWEN,FIFO Over Write Enable" "0: Data FIFO OW option disabled.,1: Data FIFO OW option enabled." bitfld.long 0x18 1.--2. "FSIZE,FIFO Size" "0: FIFO depth = 1 data word,1: FIFO depth = 4 data words,2: FIFO depth = 8 data words,3: FIFO depth = 16 data words" newline bitfld.long 0x18 0. "FE,FIFO Enable" "0: Data FIFO is not enabled for multiple data..,1: Data FIFO is enabled; FIFO depth is indicated by.." line.long 0x1C "STKR,Software Trigger Key Register" hexmask.long.word 0x1C 0.--15. 1. "ST_KEY,Software Trigger Key" rgroup.long 0x20++0x3 line.long 0x0 "CDR,Converted Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CDATA,Converted Data Register" group.long 0x24++0x3 line.long 0x0 "WTHHLR,WDG Threshold Register" hexmask.long.word 0x0 16.--31. 1. "THRH,WDG Upper Threshold Value" hexmask.long.word 0x0 0.--15. 1. "THRL,WDG Lower Threshold Value" rgroup.long 0x28++0x7 line.long 0x0 "LDREG,Latest Data Register" hexmask.long.word 0x0 0.--15. 1. "LDR,Latest Data Register" line.long 0x4 "LTREG,Latest Time-Stamp Register" hexmask.long.tbyte 0x4 0.--23. 1. "LTR,Latest Time-Stamp Register" group.long 0x30++0x3 line.long 0x0 "PSICR,PSI Control Register" hexmask.long.byte 0x0 10.--13. 1. "DEST,Destination Address of Decimation Filter or DSPL module" bitfld.long 0x0 8.--9. "RSVRD,This bit is Read/Write independent of DSPL module availability but it is functional only when DSPL module in not present." "0,1,2,3" newline bitfld.long 0x0 7. "FLUSH,Master block Flush request" "0: No flush request.,1: Flush request." bitfld.long 0x0 6. "RPSI,Return Parallel Side Interface" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "MESSAGE_TAG,The MESSAGE_TAG bit fields are used to route the data to different sub-blocks inside the decimation filter." bitfld.long 0x0 1. "INIT,Initialization Mode" "0: Normal mode.,1: Initialization mode." newline bitfld.long 0x0 0. "PSIEN,Parallel Side Interface (PSI) Enable" "0: Disable.,1: Enable." tree.end tree.end tree "SDMMC (Secure Digital and MultiMediaCard Controller)" base ad:0x0 tree "SDMMC_0" base ad:0x75400000 group.long 0x0++0x3 line.long 0x0 "SDMASYSADDR,SDMA system address/argument2 register" hexmask.long 0x0 0.--31. 1. "SDMA_SYSADDRESS,SDMA system address (Low) / Argument 2 (Low)" group.word 0x4++0x3 line.word 0x0 "BLOCKSIZE,Block size register" bitfld.word 0x0 12.--14. "SDMA_BUFBOUNDARY,Host SDMA buffer size" "0: 4Kbytes (Detects A11 Carry out),1: 8Kbytes (Detects A12 Carry out),2: 16Kbytes (Detects A13 Carry out),3: 32Kbytes (Detects A14 Carry out),4: 64Kbytes (Detects A15 Carry out),5: 128Kbytes (Detects A16 Carry out),6: 256Kbytes (Detects A17 Carry out),7: 512Kbytes (Detects A18 Carry out)" newline hexmask.word 0x0 0.--11. 1. "XFER_BLOCKSIZE,Transfer Block Size" line.word 0x2 "BLOCKCOUNT,Block count register" hexmask.word 0x2 0.--15. 1. "XFER_BLOCKCOUNT,Block count for current transfer" group.long 0x8++0x3 line.long 0x0 "ARGUMENT1,Argument 1 register" hexmask.long 0x0 0.--31. 1. "COMMAND_ARGUMENT1,Command argument 1" group.word 0xC++0x3 line.word 0x0 "TRANSFERMODE,Transfer mode register" bitfld.word 0x0 5. "XFERMODE_MULTIBLKSEL,Multi/Single block select" "0: Single block,1: Multiple block" newline bitfld.word 0x0 4. "XFERMODE_DATAXFERDIR,Data transfer direction select" "0: Write (Host to card),1: Read (card to Host)" newline bitfld.word 0x0 2.--3. "XFERMODE_AUTOCMDENA,Auto CMD enable" "0: Auto command disabled,1: Auto CMD12 enable,2: Auto CMD23 enable,?" newline bitfld.word 0x0 1. "XFERMODE_BLKCNTENA,Block count enable" "0: Disable,1: Enable" newline bitfld.word 0x0 0. "XFERMODE_DMAENABLE,DMA enable" "0: Disable,1: Enable" line.word 0x2 "COMMAND,Command register" hexmask.word.byte 0x2 8.--13. 1. "COMMAND_CMDINDEX,Command index" newline bitfld.word 0x2 6.--7. "COMMAND_CMDTYPE,Command type" "0: Normal,1: Suspend,2: Resume,3: Abort" newline bitfld.word 0x2 5. "COMMAND_DATAPRESENT,Data present select" "0: No Data Present,1: Data Present" newline bitfld.word 0x2 4. "COMMAND_INDEXCHKENA,Command index check enable" "0: Disable,1: Enable" newline bitfld.word 0x2 3. "COMMAND_CRCCHKENA,Command CRC check enable" "0: Disable,1: Enable" newline bitfld.word 0x2 0.--1. "COMMAND_RESPONSETYPE,Response type select" "0: No Response,1: Response length 136,2: Response length 48,3: Response length 48 check. Busy after response." rgroup.word 0x10++0xF line.word 0x0 "RESPONSE0,Response 0 register" hexmask.word 0x0 0.--15. 1. "COMMAND_RESPONSE,Command response" line.word 0x2 "RESPONSE1,Response 1 register" hexmask.word 0x2 0.--15. 1. "COMMAND_RESPONSE,Command response" line.word 0x4 "RESPONSE2,Response 2 register" hexmask.word 0x4 0.--15. 1. "COMMAND_RESPONSE,Command response" line.word 0x6 "RESPONSE3,Response 3 register" hexmask.word 0x6 0.--15. 1. "COMMAND_RESPONSE,Command response" line.word 0x8 "RESPONSE4,Response 4 register" hexmask.word 0x8 0.--15. 1. "COMMAND_RESPONSE,Command response" line.word 0xA "RESPONSE5,Response 5 register" hexmask.word 0xA 0.--15. 1. "COMMAND_RESPONSE,Command response" line.word 0xC "RESPONSE6,Response 6 register" hexmask.word 0xC 0.--15. 1. "COMMAND_RESPONSE,Command response" line.word 0xE "RESPONSE7,Response 7 register" hexmask.word 0xE 0.--15. 1. "COMMAND_RESPONSE,Command response" group.long 0x20++0x3 line.long 0x0 "DATAPORT,Data port register" hexmask.long 0x0 0.--31. 1. "PIOBUFRDDATA,Buffer data" rgroup.long 0x24++0x3 line.long 0x0 "PRESENTSTATE,Present state register" bitfld.long 0x0 28. "SDMMC_DAT7,DAT[7:4] line signal level" "0,1" newline bitfld.long 0x0 27. "SDMMC_DAT6,DAT[7:4] line signal level" "0,1" newline bitfld.long 0x0 26. "SDMMC_DAT5,DAT[7:4] line signal level" "0,1" newline bitfld.long 0x0 25. "SDMMC_DAT4,DAT[7:4] line signal level" "0,1" newline bitfld.long 0x0 24. "SDMMC_CMD,CMD line signal level" "0,1" newline bitfld.long 0x0 23. "SDMMC_DAT3,DAT[3:0] line signal level" "0,1" newline bitfld.long 0x0 22. "SDMMC_DAT2,DAT[3:0] line signal level" "0,1" newline bitfld.long 0x0 21. "SDMMC_DAT1,DAT[3:0] line signal level" "0,1" newline bitfld.long 0x0 20. "SDMMC_DAT0,DAT[3:0] line signal level" "0,1" newline bitfld.long 0x0 19. "SDMMC_WP,Write protect switch pin level" "0: Write protected,1: Write enabled" newline bitfld.long 0x0 18. "SDMMC_CD_N,Cart detect pin level" "0: No card present,1: Card present" newline bitfld.long 0x0 17. "CARDDET_STATESTABLE,Card state stable" "0: Reset of debouncing,1: No card or Inserted" newline bitfld.long 0x0 16. "CARDDET_INSERTED,Card inserted" "0: Reset or debouncing or no card,1: Card inserted" newline bitfld.long 0x0 11. "DMACTRL_PIOBUFRDENA,Buffer read enable" "0: Read disable,1: Read enable" newline bitfld.long 0x0 10. "DMACTRL_PIOBUFWRENA,Buffer write enable" "0: Write Disable,1: Write Enable." newline bitfld.long 0x0 9. "DMACTRL_RDXFERACTIVE,Read transfer active" "0: No valid data,1: Transferring data" newline bitfld.long 0x0 8. "DMACTRL_WRXFERACTIVE,Write transfer active" "0: No valid data,1: Transferring data" newline bitfld.long 0x0 2. "DMACTRL_DATALINEACTIVE,DAT line active" "0: DAT line inactive,1: DAT line active" newline bitfld.long 0x0 1. "PRESENTSTATE_INHIBITDAT,Command inhibit (DAT)" "0: Can issue command which uses the DAT line,1: Cannot issue command which uses the DAT line" newline bitfld.long 0x0 0. "PRESENTSTATE_INHIBITCMD,Command inhibit (CMD)" "0,1" group.byte 0x28++0x3 line.byte 0x0 "HOSTCONTROL1,Host control 1 register" bitfld.byte 0x0 7. "HOSTCTRL1_CDSIGSELECT,Card detect signal detection" "0: Card detection pin is selected (for normal use),1: The card detect test level is selected" newline bitfld.byte 0x0 6. "HOSTCTRL1_CDTESTLEVEL,Card detect test level" "0: No Card,1: Card Inserted" newline bitfld.byte 0x0 5. "HOSTCTRL1_EXTDATAWIDTH,Extended data transfer width" "0: Bus Width is Selected by Data Transfer Width,1: 8-bit Bus Width" newline bitfld.byte 0x0 3.--4. "HOSTCTRL1_DMASELECT,DMA select" "0: SDMA is selected,1: 32-bit address ADMA1 is selected,2: 32-bit address ADMA2 is selected,?" newline bitfld.byte 0x0 2. "HOSTCTRL1_HIGHSPEEDENA,High speed enable" "0: Normal speed mode,1: High speed mode" newline bitfld.byte 0x0 1. "HOSTCTRL1_DATAWIDTH,Data transfer width" "0: 1 bit mode,1: 4 bit mode" line.byte 0x1 "POWERCONTROL,Power control register" bitfld.byte 0x1 1.--3. "PWRCTRL_SDBUSVOLTAGE,eMMC bus voltage select" "?,?,?,?,?,?,?,7: 3.3 Flattop" newline bitfld.byte 0x1 0. "SD_BUS_POWER,Before setting this bit the SD host driver shall set SD Bus Voltage Select. If the HC detects the No Card State this bit shall be cleared." "0: Power off,1: Power on" line.byte 0x2 "BLOCKGAPCONTROL,Block gap control register" bitfld.byte 0x2 7. "BLKGAPCTRL_BOOTACKENA,To check for the boot acknowledge in boot operation." "0: Will not wait for boot ack from eMMC card,1: Wait for boot ack from eMMC card" newline bitfld.byte 0x2 6. "BLKGAPCTRL_ALTBOOTMODE,To start boot code access in alternative mode." "0: To stop alternate boot mode access,1: To start alternate boot mode access" newline bitfld.byte 0x2 5. "BLKGAPCTRL_BOOTENABLE,To start boot code access." "0: To stop boot code access,1: To start boot code access" newline bitfld.byte 0x2 4. "BLKGAPCTRL_SPIMODE,SPI mode enable bit." "0: SDMMC mode,1: SPI mode" newline bitfld.byte 0x2 3. "BLKGAPCTRL_INTERRUPT,This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. If the SD card cannot signal an.." "0,1" newline bitfld.byte 0x2 2. "BLKGAPCTRL_RDWAITCTRL,The read wait function is optional for SDIO cards. If the card supports read wait set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD clock to hold read.." "0: Disable Read Wait Control,1: Enable Read Wait Control" newline bitfld.byte 0x2 1. "BLKGAPCTRL_CONTINUE,Continue request" "0: Ignored,1: Restart" newline bitfld.byte 0x2 0. "BLKGAPCTRL_STOPATBLKGAP,Stop at block gap request" "0: Transfer,1: Stop" line.byte 0x3 "WAKEUPCONTROL,Wake up control register" bitfld.byte 0x3 2. "WAKEUP_EN_CARD_REMOVAL,Wakeup Event Enable On SD Card Removal." "0: Disable,1: Enable" newline bitfld.byte 0x3 1. "WAKEUP_EN_CARD_INSERTION,Wakeup Event Enable On SD Card Insertion" "0: Disable,1: Enable" newline bitfld.byte 0x3 0. "WAKEUP_EN_CARD_INTERRUPT,Wakeup Event Enable On Card Interrupt" "0: Disable,1: Enable" group.word 0x2C++0x1 line.word 0x0 "CLOCKCONTROL,Clock control register" hexmask.word.byte 0x0 8.--15. 1. "CLKCTRL_SDMMCCLKFREQSEL,sdmmcctrl_clk frequency select (Lower bits)" newline bitfld.word 0x0 6.--7. "CLKCTRL_SDMMCCLKFREQSEL_UPPERBITS,Upper bits of sdmmcctrl_clk frequency select" "0,1,2,3" newline bitfld.word 0x0 2. "CLKCTRL_SDMMCCLKENA,SDMMC clock enable" "0: Disable,1: Enable" newline bitfld.word 0x0 1. "CLKGEN_INTCLKSTABLE,Internal clock stable" "0: Not Ready,1: Ready" newline bitfld.word 0x0 0. "CLKCTRL_INTCLKENA,Internal clock enable" "0: Stop,1: Oscillate" group.byte 0x2E++0x1 line.byte 0x0 "TIMEOUTCONTROL,Timeout control register" hexmask.byte 0x0 0.--3. 1. "TIMEOUT_CTRVALUE,Data timeout counter value" line.byte 0x1 "SOFTWARERESET,Software reset register" bitfld.byte 0x1 2. "SWRESET_FOR_DAT,Software reset for DAT line" "0: Work,1: Reset" newline bitfld.byte 0x1 1. "SWRESET_FOR_CMD,Software reset for CMD line" "0: Work,1: Reset" newline bitfld.byte 0x1 0. "SWRESET_FOR_ALL,Software reset for all" "0: Work,1: Reset" group.word 0x30++0xB line.word 0x0 "NORMALINTRSTS,Normal interrupt status register" bitfld.word 0x0 15. "REG_ERRORINTRSTS,Error interrupt" "0: No error,1: Error" newline bitfld.word 0x0 14. "NORMALINTRSTS_BOOTCOMPLETE,Boot terminate interrupt" "0: Boot operation is not terminated.,1: Boot operation is terminated." newline bitfld.word 0x0 13. "NORMALINTRSTS_RCVBOOTACK,Boot ack rcv" "0: Boot ack is not received.,1: Boot ack is received." newline bitfld.word 0x0 12. "NORMALINTRSTS_RETUNINGEVENT,Re-Tuning event" "0: Re-tuning is not required.,1: Re-tuning should be performed." newline bitfld.word 0x0 11. "NORMALINTRSTS_INTC,INT_C" "0,1" newline bitfld.word 0x0 10. "NORMALINTRSTS_INTB,INT_B" "0,1" newline bitfld.word 0x0 9. "NORMALINTRSTS_INTA,INT_A" "0,1" newline bitfld.word 0x0 8. "NORMALINTRSTS_CARDINTSTS,Card interrupt" "0: No card interrupt,1: Generate card interrupt" newline bitfld.word 0x0 7. "NORMALINTRSTS_CARDREMSTS,Card removal" "0: Card state stable or debouncing,1: Card removed" newline bitfld.word 0x0 6. "NORMALINTRSTS_CARDINSSTS,Card insertion" "0: Card state stable or debouncing,1: Card inserted" newline bitfld.word 0x0 5. "NORMALINTRSTS_BUFRDREADY,Buffer read ready" "0: Not ready to read buffer,1: Ready to read buffer" newline bitfld.word 0x0 4. "NORMALINTRSTS_BUFWRREADY,Buffer write ready" "0: Not ready to write buffer,1: Ready to write buffer" newline bitfld.word 0x0 3. "NORMALINTRSTS_DMAINTERRUPT,DMA interrupt" "0: No DMA interrupt,1: DMA interrupt is generated" newline bitfld.word 0x0 2. "NORMALINTRSTS_BLKGAPEVENT,Block gap event" "0: No Block gap event,1: Transaction stopped at block gap" newline bitfld.word 0x0 1. "NORMALINTRSTS_XFERCOMPLETE,Transfer complete" "0: No Data transfer complete,1: Data transfer complete" newline bitfld.word 0x0 0. "NORMALINTRSTS_CMDCOMPLETE,Command complete" "0: No Command Complete,1: Command Complete" line.word 0x2 "ERRORINTRSTS,Error interrupt status register" bitfld.word 0x2 12. "ERRORINTRSTS_HOSTERROR,Target response error" "0: No error,1: Error" newline bitfld.word 0x2 9. "ERRORINTRSTS_ADMAERROR,DMA error" "0: No error,1: Error" newline bitfld.word 0x2 8. "ERRORINTRSTS_AUTOCMDERROR,Auto CMD error" "0: No error,1: Error" newline bitfld.word 0x2 6. "ERRORINTRSTS_DATAENDBITERROR,Data end bit error" "0: No error,1: Error" newline bitfld.word 0x2 5. "ERRORINTRSTS_DATACRCERROR,Data CRC error" "0: No error,1: Error" newline bitfld.word 0x2 4. "ERRORINTRSTS_DATATIMEOUTERROR,Data timeout error" "0: No error,1: Timeout" newline bitfld.word 0x2 3. "ERRORINTRSTS_CMDINDEXERROR,Command index error" "0: No error,1: Error" newline bitfld.word 0x2 2. "ERRORINTRSTS_CMDENDBITERROR,Command end bit error" "0: No error,1: End Bit Error Generated" newline bitfld.word 0x2 1. "ERRORINTRSTS_CMDCRCERROR,Command CRC error" "0: level on the CMD line at the next sdmmcctrl_clk..,1: CRC error generated" newline bitfld.word 0x2 0. "ERRORINTRSTS_CMDTIMEOUTERROR,Command timeout error" "0: No error,1: Timeout" line.word 0x4 "NORMALINTRSTSENA,Normal interrupt status enable register" bitfld.word 0x4 15. "NORMALINTRSTS_ENABLEREGBIT15,Fixed to 0" "0,1" newline bitfld.word 0x4 14. "NORMALINTRSTS_ENABLEREGBIT14,Boot terminate interrupt enable" "0: Masked,1: Enabled" newline bitfld.word 0x4 13. "NORMALINTRSTS_ENABLEREGBIT13,Boot ack rcv enable" "0: Masked,1: Enabled" newline bitfld.word 0x4 12. "NORMALINTRSTS_ENABLEREGBIT12,Re-Tuning event status enable" "0: Masked,1: Enabled" newline bitfld.word 0x4 11. "NORMALINTRSTS_ENABLEREGBIT11,INT_C status enable" "0,1" newline bitfld.word 0x4 10. "NORMALINTRSTS_ENABLEREGBIT10,INT_B status enable" "0,1" newline bitfld.word 0x4 9. "NORMALINTRSTS_ENABLEREGBIT9,INT_A status enable" "0,1" newline bitfld.word 0x4 8. "SDHCREGSET_CARDINTSTSENA,Card interrupt status enable" "0: Masked,1: Enabled" newline bitfld.word 0x4 7. "SDHCREGSET_CARDREMSTSENA,Card removal status enable" "0: Masked,1: Enabled" newline bitfld.word 0x4 6. "SDHCREGSET_CARDINSSTSENA,Card insertion status enable" "0: Masked,1: Enabled" newline bitfld.word 0x4 5. "NORMALINTRSTS_ENABLEREGBIT5,Buffer read ready status enable" "0: Masked,1: Enabled" newline bitfld.word 0x4 4. "NORMALINTRSTS_ENABLEREGBIT4,Buffer write ready status enable" "0: Masked,1: Enabled" newline bitfld.word 0x4 3. "NORMALINTRSTS_ENABLEREGBIT3,DMA interrupt status enable" "0: Masked,1: Enabled" newline bitfld.word 0x4 2. "NORMALINTRSTS_ENABLEREGBIT2,Block gap event status enable" "0: Masked,1: Enabled" newline bitfld.word 0x4 1. "NORMALINTRSTS_ENABLEREGBIT1,Transfer complete status enable" "0: Masked,1: Enabled" newline bitfld.word 0x4 0. "NORMALINTRSTS_ENABLEREGBIT0,Command complete status enable" "0: Masked,1: Enabled" line.word 0x6 "ERRORINTRSTSENA,Error interrupt status enable register" bitfld.word 0x6 12. "ERRORINTRSTS_ENABLEREGBIT12,Target response error signal enable" "0: Masked,1: Enabled" newline bitfld.word 0x6 9. "ERRORINTRSTS_ENABLEREGBIT9,ADMA error status enable" "0: Masked,1: Enabled" newline bitfld.word 0x6 8. "ERRORINTRSTS_ENABLEREGBIT8,Auto CMD12 error status enable" "0: Masked,1: Enabled" newline bitfld.word 0x6 6. "ERRORINTRSTS_ENABLEREGBIT6,Data end bit error" "0: Masked,1: Enabled" newline bitfld.word 0x6 5. "ERRORINTRSTS_ENABLEREGBIT5,STA_EN: data CRC error status enable" "0: Masked,1: Enabled" newline bitfld.word 0x6 4. "ERRORINTRSTS_ENABLEREGBIT4,Data timeout error status enable" "0: Masked,1: Enabled" newline bitfld.word 0x6 3. "ERRORINTRSTS_ENABLEREGBIT3,Command index error status enable" "0: Masked,1: Enabled" newline bitfld.word 0x6 2. "ERRORINTRSTS_ENABLEREGBIT2,Command end bit error status enable" "0: Masked,1: Enabled" newline bitfld.word 0x6 1. "ERRORINTRSTS_ENABLEREGBIT1,Command CRC error status enable" "0: Masked,1: Enabled" newline bitfld.word 0x6 0. "ERRORINTRSTS_ENABLEREGBIT0,Command time-out error status enable" "0: Masked,1: Enabled" line.word 0x8 "NORMALINTRSIGENA,Normal interrupt signal enable register" bitfld.word 0x8 15. "NORMALINTRSTS_ENABLEREGBIT15,Fixed to 0" "0,1" newline bitfld.word 0x8 14. "NORMALINTRSTS_ENABLEREGBIT14,Boot terminate interrupt signal enable" "0: Masked,1: Enabled" newline bitfld.word 0x8 13. "NORMALINTRSTS_ENABLEREGBIT13,Boot ack rcv signal enable" "0: Masked,1: Enabled" newline bitfld.word 0x8 12. "NORMALINTRSTS_ENABLEREGBIT12,Re-Tuning event signal enable" "0: Masked,1: Enabled" newline bitfld.word 0x8 11. "NORMALINTRSTS_ENABLEREGBIT11,INT_C signal enable" "0: Masked,1: Enabled" newline bitfld.word 0x8 10. "NORMALINTRSTS_ENABLEREGBIT10,INT_B signal enable" "0: Masked,1: Enabled" newline bitfld.word 0x8 9. "NORMALINTRSTS_ENABLEREGBIT9,INT_A signal enable" "0: Masked,1: Enabled" newline bitfld.word 0x8 8. "SDHCREGSET_CARDINTSTSENA,Card interrupt signal enable" "0: Masked,1: Enabled" newline bitfld.word 0x8 7. "SDHCREGSET_CARDREMSTSENA,Card removal signal enable" "0: Masked,1: Enabled" newline bitfld.word 0x8 6. "SDHCREGSET_CARDINSSTSENA,Card insertion signal enable" "0: Masked,1: Enabled" newline bitfld.word 0x8 5. "NORMALINTRSTS_ENABLEREGBIT5,Buffer read ready signal enable" "0: Masked,1: Enabled" newline bitfld.word 0x8 4. "NORMALINTRSTS_ENABLEREGBIT4,Buffer write ready signal enable" "0: Masked,1: Enabled" newline bitfld.word 0x8 3. "NORMALINTRSTS_ENABLEREGBIT3,DMA interrupt signal enable" "0: Masked,1: Enabled" newline bitfld.word 0x8 2. "NORMALINTRSTS_ENABLEREGBIT2,Block gap event signal enable" "0: Masked,1: Enabled" newline bitfld.word 0x8 1. "NORMALINTRSTS_ENABLEREGBIT1,Transfer complete signal enable" "0: Masked,1: Enabled" newline bitfld.word 0x8 0. "NORMALINTRSTS_ENABLEREGBIT0,Command complete signal enable" "0: Masked,1: Enabled" line.word 0xA "ERRORINTRSIGENA,Error interrupt signal enable register" bitfld.word 0xA 12. "ERRORINTRSIG_ENABLEREGBIT12,Target response error signal enable" "0: Masked,1: Enabled" newline bitfld.word 0xA 10. "ERRORINTRSIG_ENABLEREGBIT10,Tuning error signal enable" "0: Masked,1: Enabled" newline bitfld.word 0xA 9. "ERRORINTRSIG_ENABLEREGBIT9,ADMA error signal enable" "0: Masked,1: Enabled" newline bitfld.word 0xA 8. "ERRORINTRSIG_ENABLEREGBIT8,Auto CMD12 error signal enable" "0: Masked,1: Enabled" newline bitfld.word 0xA 7. "ERRORINTRSIG_ENABLEREGBIT7,Current limit error signal enable" "0: Masked,1: Enabled" newline bitfld.word 0xA 6. "ERRORINTRSIG_ENABLEREGBIT6,Data end bit error signal enable" "0: Masked,1: Enabled" newline bitfld.word 0xA 5. "ERRORINTRSIG_ENABLEREGBIT5,Data CRC error signal enable" "0: Masked,1: Enabled" newline bitfld.word 0xA 4. "ERRORINTRSIG_ENABLEREGBIT4,Data timeout error signal enable" "0: Masked,1: Enabled" newline bitfld.word 0xA 3. "ERRORINTRSIG_ENABLEREGBIT3,Command index error signal enable" "0: Masked,1: Enabled" newline bitfld.word 0xA 2. "ERRORINTRSIG_ENABLEREGBIT2,Command end bit error signal enable" "0: Masked,1: Enabled" newline bitfld.word 0xA 1. "ERRORINTRSIG_ENABLEREGBIT1,Command CRC error signal enable" "0: Masked,1: Enabled" newline bitfld.word 0xA 0. "ERRORINTRSIG_ENABLEREGBIT0,Command time-out error signal enable" "0: Masked,1: Enabled" rgroup.word 0x3C++0x1 line.word 0x0 "AUTOCMDERRSTS,Auto CMD error status enable register" bitfld.word 0x0 7. "AUTOCMDERRSTS_NEXTERROR,Command not issued by Auto CMD12 error" "0: No error,1: Not issued" newline bitfld.word 0x0 4. "AUTOCMDERRSTS_INDEXERROR,Auto CMD index error" "0: No error,1: Error" newline bitfld.word 0x0 3. "AUTOCMDERRSTS_ENDBITERROR,Auto CMD end bit error" "0: No error,1: End bit error generated" newline bitfld.word 0x0 2. "AUTOCMDERRSTS_CRCERROR,Auto CMD CRC error" "0: No error,1: CRC error generated" newline bitfld.word 0x0 1. "AUTOCMDERRSTS_TIMEOUTERROR,Auto CMD timeout error" "0: No error,1: Timeout" newline bitfld.word 0x0 0. "AUTOCMDERRSTS_NOTEXECERROR,Auto CMD12 not executed" "0: Executed,1: Not executed" group.word 0x3E++0x1 line.word 0x0 "HOSTCONTROL2,Host control 2 register" bitfld.word 0x0 15. "HOSTCTRL2_PRESETVALUEENABLE,Preset value enable" "0: sdmmccard_clk and driver strength are controlled..,1: Automatic selection by preset value are enabled" newline bitfld.word 0x0 14. "HOSTCTRL2_ASYNCHINTRENABLE,Asynchronous interrupt enable" "0: Disabled,1: Enabled" newline bitfld.word 0x0 7. "HOSTCTRL2_SAMPLINGCLKSELECT,Sampling clock select" "0: Fixed clock is used to sample data,1: Tuned clock is used to sample data" newline bitfld.word 0x0 6. "HOSTCTRL2_EXECUTETUNING,Execute tuning" "0: Not tuned or tuning completed,1: Execute tuning" newline bitfld.word 0x0 4.--5. "HOSTCTRL2_DRIVERSTRENGTH,Driver strength select" "0,1,2,3" newline bitfld.word 0x0 3. "HOSTCTRL2_1P8VSIGNALLINGENA,1.8V signaling enable" "0,1" newline bitfld.word 0x0 0.--2. "HOSTCTRL2_UHSMODESELECT,This field is used to select DDR Mode of eMMC. Set is to 100b to enable High Speed DDR mode." "0,1,2,3,4,5,6,7" rgroup.long 0x40++0xF line.long 0x0 "CAPABILITIES31_0,Capabilities[31:0] register" bitfld.long 0x0 30.--31. "CORECFG_SLOTTYPE,Slot type support" "0: Removable card slot,1: Embedded slot for one device,2: Shared bus slot,?" newline bitfld.long 0x0 29. "CORECFG_ASYNCHINTRSUPPORT,CORECFG_ASYNCHINTRSUPPORT" "0: Core does not support monitoring of asynchronous..,1: Core supports monitoring of asynchronous interrupt" newline bitfld.long 0x0 24. "CORECFG_3P3VOLTSUPPORT,Voltage support 3.3V" "0: 3.3V Not supported,1: 3.3V Supported" newline bitfld.long 0x0 23. "CORECFG_SUSPENDRESUME,CORECFG_SUSPENDRESUME" "0: Not Supported,1: Supported" newline bitfld.long 0x0 22. "CORECFG_SDMASUPPORT,SDMA support" "0: SDMA Not Supported,1: SDMA Supported" newline bitfld.long 0x0 21. "CORECFG_HIGHSPEEDSUPPORT,High speed support" "0: High speed not supported,1: High speed supported" newline bitfld.long 0x0 19. "CORECFG_ADMA2SUPPORT,ADMA2 support" "0: ADMA2 not supported,1: ADMA2 supported" newline bitfld.long 0x0 18. "CORECFG_8BITSUPPORT,Extended media bus support" "0: Extended media bus not supported,1: Extended media bus supported" newline bitfld.long 0x0 16.--17. "CORECFG_MAXBLKLENGTH,Max block length" "0: 512byte,1: 1024byte,2: 2048byte,3: 4096byte" newline hexmask.long.byte 0x0 8.--15. 1. "CORECFG_BASECLKFREQ,Base clock frequency of SDMMC_CLK" newline bitfld.long 0x0 7. "CORECFG_TIMEOUTCLKUNIT,Timeout clock unit" "0: KHz,1: MHz" newline hexmask.long.byte 0x0 0.--5. 1. "CORECFG_TIMEOUTCLKFREQ,Timeout clock frequency" line.long 0x4 "CAPABILITIES63_32,Capabilities[63:32] register" bitfld.long 0x4 25. "CORECFG_SPIBLKMODE,SPI block mode" "0: Not supported,1: Supported" newline bitfld.long 0x4 24. "CORECFG_SPISUPPORT,SPI mode" "0: Not supported,1: Supported" newline bitfld.long 0x4 14.--15. "CORECFG_RETUNINGMODES,Re-tuning modes" "0,1,2,3" newline bitfld.long 0x4 2. "CORECFG_DDRMODESUPPORT,DDR mode support" "0: DDR mode is not supported.,1: DDR mode is supported." line.long 0x8 "MAXCURRENTCAP31_0,Maximum current capabilities[31:0] register" hexmask.long.byte 0x8 0.--7. 1. "CORECFG_MAXCURRENT3P3V,Maximum Current for 3.3V" line.long 0xC "MAXCURRENTCAP63_32,Maximum current capabilities[63:32] register" wgroup.word 0x50++0x3 line.word 0x0 "FORCEEVENTFORAUTOCMDERRSTS,Force event for auto CMD error status register" bitfld.word 0x0 7. "FORCECMDNOTISSUEDBYAUTOCMD12ERR,Force event for command not issued by Auto CMD12 Error" "0: No interrupt,1: Interrupt is generated" newline bitfld.word 0x0 4. "FORCEAUTOCMDINDEXERR,Force event for Auto CMD index error" "0: No interrupt,1: Interrupt is generated" newline bitfld.word 0x0 3. "FORCEAUTOCMDENDBITERR,Force event for Auto CMD index error" "0: No interrupt,1: Interrupt is generated" newline bitfld.word 0x0 2. "FORCEAUTOCMDCRCERR,Force event for Auto CMD CRC error" "0: No interrupt,1: Interrupt is generated" newline bitfld.word 0x0 1. "FORCEAUTOCMDTIMEOUTERR,Force event for Auto CMD timeout error" "0: No interrupt,1: Interrupt is generated" newline bitfld.word 0x0 0. "FORCEAUTOCMDNOTEXEC,Force event for Auto CMD12 NOT executed" "0: No interrupt,1: Interrupt is generated" line.word 0x2 "FORCEEVENTFORERRINTSTS,Force event for error interrupt status register" bitfld.word 0x2 9. "FORCEADMAERR,Force event for ADMA error" "0: No interrupt,1: Interrupt is generated" newline bitfld.word 0x2 8. "FORCEAUTOCMDERR,Force event for Auto CMD error" "0: No interrupt,1: Interrupt is generated" newline bitfld.word 0x2 7. "FORCECURRLIMERR,Force event for current limit error" "0: No interrupt,1: Interrupt is generated" newline bitfld.word 0x2 6. "FORCEDATENDBITERR,Force event for data end bit error" "0: No interrupt,1: Interrupt is generated" newline bitfld.word 0x2 5. "FORCEDATCRCERR,Force event for data CRC error 1" "0: No interrupt,1: Interrupt is generated" newline bitfld.word 0x2 4. "FORCEDATTIMEOUTERR,Force event for data timeout error 1" "0: No interrupt,1: Interrupt is generated" newline bitfld.word 0x2 3. "FORCECMDINDEXERR,Force event for command index error 1" "0: No interrupt,1: Interrupt is generated" newline bitfld.word 0x2 2. "FORCECMDENDBITERR,Force event for command end bit error" "0: No interrupt,1: Interrupt is generated" newline bitfld.word 0x2 1. "FORCECMDCRCERR,Force event for command CRC error" "0: No interrupt,1: Interrupt is generated" newline bitfld.word 0x2 0. "FORCECMDTIMEOUTERR,Force event for command timeout error" "0: No interrupt,1: Interrupt is generated" rgroup.byte 0x54++0x0 line.byte 0x0 "ADMAERRSTS,ADMA error status register" bitfld.byte 0x0 2. "ADMAERRSTS_ADMALENMISMATCHERR,ADMA length mismatch error" "0: No error,1: Error" newline bitfld.byte 0x0 0.--1. "ADMAERRSTS_ADMAERRORSTATE,ADMA error state" "0: ST_STOP (Stop DMA) points to next of the error..,1: ST_FDS (Fetch Descriptor) points to the error..,2: Never set this state (Not used),3: ST_TFR (Transfer Data) points to the next of the.." group.word 0x58++0x7 line.word 0x0 "ADMASYSADDR0,ADMA system address 0 register" hexmask.word 0x0 0.--15. 1. "ADMA_SYSADDRESS,ADMA_system address" line.word 0x2 "ADMASYSADDR1,ADMA system address 1 register" hexmask.word 0x2 0.--15. 1. "ADMA_SYSADDRESS,ADMA_system address" line.word 0x4 "ADMASYSADDR2,ADMA system address 2 register" hexmask.word 0x4 0.--15. 1. "ADMA_SYSADDRESS,ADMA_system address" line.word 0x6 "ADMASYSADDR3,ADMA system address 3 register" hexmask.word 0x6 0.--15. 1. "ADMA_SYSADDRESS,ADMA_system address" rgroup.word 0x60++0xF line.word 0x0 "PRESETVALUE0,Preset value 0 register" line.word 0x2 "PRESETVALUE1,Preset value 1 register" line.word 0x4 "PRESETVALUE2,Preset value 2 register" line.word 0x6 "PRESETVALUE3,Preset value 3 register" line.word 0x8 "PRESETVALUE4,Preset value 4 register" line.word 0xA "PRESETVALUE5,Preset value 5 register" line.word 0xC "PRESETVALUE6,Preset value 6 register" line.word 0xE "PRESETVALUE7,Preset value 7 register" group.long 0x70++0x3 line.long 0x0 "BOOTTIMEOUTCNT,Boot timeout control register" hexmask.long 0x0 0.--31. 1. "BOOT_TIMEOUTCNT,Boot data timeout counter value" rgroup.word 0xFC++0x3 line.word 0x0 "SLOTINTRSTS,Slot interrupt status register" bitfld.word 0x0 0. "SDHCHOSTIF_SLOTINTRSTS,Interrupt signal for slot#0" "0,1" line.word 0x2 "HOSTCONTROLLERVER,Host controller version register" hexmask.word.byte 0x2 8.--15. 1. "SDHC_VENVERNUM,Vendor version number" newline hexmask.word.byte 0x2 0.--7. 1. "SPECIFICATIONVERSIONNUMBER,Specification version number" group.long 0x208++0x3 line.long 0x0 "CORE_CONFIG,Core configuration register" hexmask.long.byte 0x0 24.--31. 1. "MAXCURRENT_3P3V,Maximum current for 3.3V." newline bitfld.long 0x0 18.--19. "CORECFG_SLOTTYPE,Select slot type" "0: Removable card slot,1: Embedded slot for one device,2: Shared bus slot,?" newline bitfld.long 0x0 17. "CORECFG_ASYNCHINTRSUPPORT,Enable asynchronous interrupt support" "0: Core does not support monitoring of asynchronous..,1: Core supports monitoring of asynchronous interrupt" newline bitfld.long 0x0 16. "CORECFG_ADMA2SUPPORT,Selection for ADMA2 support" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "BASECLKFREQ_SDMMC_CLK,Base clock frequency for SDMMC clock." group.long 0x210++0x3 line.long 0x0 "FB_CLK_SEL,Feedback clock selection register" bitfld.long 0x0 0.--1. "FEEDBACKCLK_SEL,Selects feedback clock from the sources of loopback." "0: Loopback from output of SDMMC HC IP (delayed..,1: OPEN,2: OPEN,3: Loopback from external SDMMC device pin.." rgroup.long 0x220++0x13 line.long 0x0 "DBG_STA1,Debug status 1 register" hexmask.long.word 0x0 0.--15. 1. "DMADEBUGBUS,DMA_CTRL debug bus" line.long 0x4 "DBG_STA2,Debug status 2 register" hexmask.long.word 0x4 0.--15. 1. "CMDDEBUGBUS,CMD_CTRL debug bus" line.long 0x8 "DBG_STA3,Debug status 3 register" hexmask.long.word 0x8 0.--15. 1. "TXDDEBUGBUS,TXD_CTRL debug bus" line.long 0xC "DBG_STA4,Debug status 4 register" hexmask.long.byte 0xC 0.--7. 1. "RXDDEBUGBUS0,RXD_CTRL debug bus" line.long 0x10 "DBG_STA5,Debug status 5 register" hexmask.long.byte 0x10 0.--7. 1. "RXDDEBUGBUS1,RXD_CTRL debug bus (RX CLK)" tree.end tree.end tree "SENT" base ad:0x0 tree "SENT_0" base ad:0x70EE8000 group.long 0x0++0x13 line.long 0x0 "GBL_CTRL,Global Control register" hexmask.long.byte 0x0 24.--31. 1. "TSPRSC,Time Stamp Prescaler Value" newline hexmask.long.byte 0x0 16.--20. 1. "FIFOWM,DMA Read FIFO Water Mark Level" newline bitfld.long 0x0 15. "NIB_LEN_VAR_LIMIT,Decides the allowable jitter/clock drift limit for nibble length measurement." "0: Allows a jitter/clock drift of approx up to..,1: Allows a jitter/clock drift as per SAE spec (50%)." newline bitfld.long 0x0 14. "INT_EXT_TS_SEL,Internal/External Time-stamp Select" "0: Internal counter is used to provide time-stamp..,1: External time-stamp bus is used" newline bitfld.long 0x0 13. "SENT_8NIB_EN,Decides maximum number of data nibbles that can be supported by a SENT channel in case of Fast message reception. Default value is 0." "0: Maximum 6 data nibbles supported per channel.,1: Maximum 8 data nibbles supported per channel." newline bitfld.long 0x0 10. "FMFOIE,Fast Message FIFO Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x0 9. "FMDUIE,Fast Message DMA Underflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x0 8. "SMDUIE,Slow Serial Message DMA Underflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x0 6. "FIFO_EN,FIFO enable bit" "0: FIFO is disabled.,1: FIFO is enabled." newline bitfld.long 0x0 4. "FAST_CLR,Fast Clearing Enable bit" "0: Fast Clearing is disabled. Bits will be cleared..,1: Fast Clearing is enabled." newline bitfld.long 0x0 2. "DBG_FRZ,Debug Freeze" "0: No effect in debug mode,1: Freeze in debug mode" newline bitfld.long 0x0 0. "SENT_EN,SENT Receiver Global Enable" "0: Entire module is disabled.,1: Module is enabled." line.long 0x4 "CHNL_EN,Channel Enable register" bitfld.long 0x4 14. "EN_CH14,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 13. "EN_CH13,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 12. "EN_CH12,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 11. "EN_CH11,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 10. "EN_CH10,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 9. "EN_CH9,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 8. "EN_CH8,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 7. "EN_CH7,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 6. "EN_CH6,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 5. "EN_CH5,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 4. "EN_CH4,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 3. "EN_CH3,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 2. "EN_CH2,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 1. "EN_CH1,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 0. "EN_CH0,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." line.long 0x8 "GBL_STATUS,Global Status register" bitfld.long 0x8 10. "FMFO,Fast Message FIFO Overflow" "0: No Overflow,1: Overflow occurred" newline bitfld.long 0x8 9. "FMDU,Fast Message DMA Underflow" "0: No underflow,1: Underflow occurred" newline bitfld.long 0x8 8. "SMDU,Slow Serial Message DMA Underflow" "0: No underflow,1: Underflow occurred" line.long 0xC "FMSG_RDY,Fast Message Ready status register" bitfld.long 0xC 14. "F_RDY14,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 13. "F_RDY13,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 12. "F_RDY12,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 11. "F_RDY11,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 10. "F_RDY10,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 9. "F_RDY9,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 8. "F_RDY8,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 7. "F_RDY7,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 6. "F_RDY6,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 5. "F_RDY5,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 4. "F_RDY4,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 3. "F_RDY3,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 2. "F_RDY2,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 1. "F_RDY1,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 0. "F_RDY0,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." line.long 0x10 "SMSG_RDY,Slow Serial Message Ready status register" bitfld.long 0x10 14. "S_RDY14,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 13. "S_RDY13,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 12. "S_RDY12,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 11. "S_RDY11,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 10. "S_RDY10,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 9. "S_RDY9,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 8. "S_RDY8,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 7. "S_RDY7,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 6. "S_RDY6,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 5. "S_RDY5,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 4. "S_RDY4,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 3. "S_RDY3,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 2. "S_RDY2,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 1. "S_RDY1,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 0. "S_RDY0,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." rgroup.long 0x14++0x3 line.long 0x0 "ERR_STATUS_ALL,Combined Error Status register" bitfld.long 0x0 18. "FMFO,Fast Message FIFO Overflow" "0: No Overflow,1: Overflow occurred" newline bitfld.long 0x0 17. "FMDU,Fast Message DMA Underflow" "0: No underflow,1: Underflow occurred" newline bitfld.long 0x0 16. "SMDU,Slow Serial Message DMA Underflow" "0: No underflow,1: Underflow occurred" newline bitfld.long 0x0 14. "CH_ERR_ALL14,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 13. "CH_ERR_ALL13,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 12. "CH_ERR_ALL12,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 11. "CH_ERR_ALL11,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 10. "CH_ERR_ALL10,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 9. "CH_ERR_ALL9,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 8. "CH_ERR_ALL8,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 7. "CH_ERR_ALL7,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 6. "CH_ERR_ALL6,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 5. "CH_ERR_ALL5,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 4. "CH_ERR_ALL4,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 3. "CH_ERR_ALL3,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 2. "CH_ERR_ALL2,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 1. "CH_ERR_ALL1,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 0. "CH_ERR_ALL0,Combined error flag of Channel Status Register" "0,1" group.long 0x18++0x17 line.long 0x0 "DATA_CTRL1,Data Control register 1" hexmask.long.byte 0x0 28.--31. 1. "NIBBCH0,Number of Data Nibbles supported in Channel 0" newline hexmask.long.byte 0x0 24.--27. 1. "NIBBCH1,Number of Data Nibbles supported in Channel 1" newline hexmask.long.byte 0x0 20.--23. 1. "NIBBCH2,Number of Data Nibbles supported in Channel 2" newline hexmask.long.byte 0x0 16.--19. 1. "NIBBCH3,Number of Data Nibbles supported in Channel 3" newline hexmask.long.byte 0x0 12.--15. 1. "NIBBCH4,Number of Data Nibbles supported in Channel 4" newline hexmask.long.byte 0x0 8.--11. 1. "NIBBCH5,Number of Data Nibbles supported in Channel 5" newline hexmask.long.byte 0x0 4.--7. 1. "NIBBCH6,Number of Data Nibbles supported in Channel 6" newline hexmask.long.byte 0x0 0.--3. 1. "NIBBCH7,Number of Data Nibbles supported in Channel 7" line.long 0x4 "DATA_CTRL2,Data Control register 2" hexmask.long.byte 0x4 28.--31. 1. "NIBBCH8,Number of Data Nibbles supported in Channel 8" newline hexmask.long.byte 0x4 24.--27. 1. "NIBBCH9,Number of Data Nibbles supported in Channel 9" newline hexmask.long.byte 0x4 20.--23. 1. "NIBBCH10,Number of Data Nibbles supported in Channel 10" newline hexmask.long.byte 0x4 16.--19. 1. "NIBBCH11,Number of Data Nibbles supported in Channel 11" newline hexmask.long.byte 0x4 12.--15. 1. "NIBBCH12,Number of Data Nibbles supported in Channel 12" newline hexmask.long.byte 0x4 8.--11. 1. "NIBBCH13,Number of Data Nibbles supported in Channel 13" newline hexmask.long.byte 0x4 4.--7. 1. "NIBBCH14,Number of Data Nibbles supported in Channel 14" line.long 0x8 "DATA_RESORT1,Data Re-sort register 1" bitfld.long 0x8 28.--30. "RESORTCH0,Re-sorting scheme for Channel 0" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0x8 24.--26. "RESORTCH1,Re-sorting scheme for Channel 1" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0x8 20.--22. "RESORTCH2,Re-sorting scheme for Channel 2" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0x8 16.--18. "RESORTCH3,Re-sorting scheme for Channel 3" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0x8 12.--14. "RESORTCH4,Re-sorting scheme for Channel 4" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0x8 8.--10. "RESORTCH5,Re-sorting scheme for Channel 5" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0x8 4.--6. "RESORTCH6,Re-sorting scheme for Channel 6" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0x8 0.--2. "RESORTCH7,Re-sorting scheme for Channel 7" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" line.long 0xC "DATA_RESORT2,Data Re-sort register 2" bitfld.long 0xC 28.--30. "RESORTCH8,Re-sorting scheme for Channel 8" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0xC 24.--26. "RESORTCH9,Re-sorting scheme for Channel 9" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0xC 20.--22. "RESORTCH10,Re-sorting scheme for Channel 10" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0xC 16.--18. "RESORTCH11,Re-sorting scheme for Channel 11" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0xC 12.--14. "RESORTCH12,Re-sorting scheme for Channel 12" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0xC 8.--10. "RESORTCH13,Re-sorting scheme for Channel 13" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0xC 4.--6. "RESORTCH14,Re-sorting scheme for Channel 14" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" line.long 0x10 "FDMA_CTRL,Fast Message DMA Control register" bitfld.long 0x10 14. "FDMA_EN14,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 13. "FDMA_EN13,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 12. "FDMA_EN12,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 11. "FDMA_EN11,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 10. "FDMA_EN10,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 9. "FDMA_EN9,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 8. "FDMA_EN8,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 7. "FDMA_EN7,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 6. "FDMA_EN6,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 5. "FDMA_EN5,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 4. "FDMA_EN4,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 3. "FDMA_EN3,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 2. "FDMA_EN2,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 1. "FDMA_EN1,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 0. "FDMA_EN0,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." line.long 0x14 "SDMA_CTRL,Slow Serial Message DMA Control register" bitfld.long 0x14 14. "SDMA_EN14,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 13. "SDMA_EN13,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 12. "SDMA_EN12,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 11. "SDMA_EN11,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 10. "SDMA_EN10,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 9. "SDMA_EN9,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 8. "SDMA_EN8,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 7. "SDMA_EN7,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 6. "SDMA_EN6,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 5. "SDMA_EN5,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 4. "SDMA_EN4,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 3. "SDMA_EN3,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 2. "SDMA_EN2,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 1. "SDMA_EN1,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 0. "SDMA_EN0,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." group.long 0x34++0x7 line.long 0x0 "FRDY_IE,Fast Message Ready Interrupt Control register" bitfld.long 0x0 14. "FRDY_IE14,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 13. "FRDY_IE13,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 12. "FRDY_IE12,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 11. "FRDY_IE11,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 10. "FRDY_IE10,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 9. "FRDY_IE9,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 8. "FRDY_IE8,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 7. "FRDY_IE7,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 6. "FRDY_IE6,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 5. "FRDY_IE5,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 4. "FRDY_IE4,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 3. "FRDY_IE3,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 2. "FRDY_IE2,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 1. "FRDY_IE1,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 0. "FRDY_IE0,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." line.long 0x4 "SRDY_IE,Slow Serial Message Ready Interrupt Enable register" bitfld.long 0x4 14. "SRDY_IE14,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 13. "SRDY_IE13,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 12. "SRDY_IE12,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 11. "SRDY_IE11,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 10. "SRDY_IE10,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 9. "SRDY_IE9,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 8. "SRDY_IE8,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 7. "SRDY_IE7,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 6. "SRDY_IE6,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 5. "SRDY_IE5,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 4. "SRDY_IE4,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 3. "SRDY_IE3,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 2. "SRDY_IE2,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 1. "SRDY_IE1,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 0. "SRDY_IE0,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." rgroup.long 0x40++0x13 line.long 0x0 "DMA_FMSG_DATA,DMA Fast Message Data read register" hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x0 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x0 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x0 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x0 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x0 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x0 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x0 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0x4 "DMA_FMSG_CRC,DMA Fast Message CRC read register" hexmask.long.byte 0x4 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x8 "DMA_FMSG_TS,DMA Fast Message Time Stamp read register" hexmask.long 0x8 0.--31. 1. "TS,TS" line.long 0xC "DMA_FMSG_DATA2,DMA Fast Message Data 2read register" hexmask.long.byte 0xC 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0xC 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x10 "DMA_SMSG_BIT3_C0,DMA Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x10 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x10 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x10 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x10 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x10 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x10 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x50++0x7 line.long 0x0 "DMA_SMSG_BIT3_C1,The DMA_SMSG_BIT3 is common for all types of slow serial messages. Bit C defines the type of enhanced packet and bit TYPE defines whether it is short serial or enhanced serial message. Since this register is used to read both Short and.." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "DMA_SMSG_BIT2_C0,DMA Slow Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x54++0x7 line.long 0x0 "DMA_SMSG_BIT2_C1,This register (DMA_SMSG_BIT2) is common for all types of slow serial messages. Hence. the register fields have been placed in such a way to match the bit positions in actual message defined by SAE Specification as shown in Figure42..." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "DMA_SMSG_TS,DMA Slow Serial Message Time Stamp read register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" group.long 0x60++0xB line.long 0x0 "CH0_CLK_CTRL,Channel 0 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH0_STATUS,Channel 0 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH0_CONFIG,Channel 0 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0x70++0xB line.long 0x0 "CH1_CLK_CTRL,Channel 1 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH1_STATUS,Channel 1 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH1_CONFIG,Channel 1 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0x80++0xB line.long 0x0 "CH2_CLK_CTRL,Channel 2 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH2_STATUS,Channel 2 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH2_CONFIG,Channel 2 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0x90++0xB line.long 0x0 "CH3_CLK_CTRL,Channel 3 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH3_STATUS,Channel 3 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH3_CONFIG,Channel 3 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0xA0++0xB line.long 0x0 "CH4_CLK_CTRL,Channel 4 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH4_STATUS,Channel 4 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH4_CONFIG,Channel 4 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0xB0++0xB line.long 0x0 "CH5_CLK_CTRL,Channel 5 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH5_STATUS,Channel 5 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH5_CONFIG,Channel 5 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0xC0++0xB line.long 0x0 "CH6_CLK_CTRL,Channel 6 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH6_STATUS,Channel 6 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH6_CONFIG,Channel 6 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0xD0++0xB line.long 0x0 "CH7_CLK_CTRL,Channel 7 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH7_STATUS,Channel 7 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH7_CONFIG,Channel 7 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0xE0++0xB line.long 0x0 "CH8_CLK_CTRL,Channel 8 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH8_STATUS,Channel 8 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH8_CONFIG,Channel 8 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0xF0++0xB line.long 0x0 "CH9_CLK_CTRL,Channel 9 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH9_STATUS,Channel 9 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH9_CONFIG,Channel 9 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0x100++0xB line.long 0x0 "CH10_CLK_CTRL,Channel 10 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH10_STATUS,Channel 10 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH10_CONFIG,Channel 10 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0x110++0xB line.long 0x0 "CH11_CLK_CTRL,Channel 11 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH11_STATUS,Channel 11 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH11_CONFIG,Channel 11 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0x120++0xB line.long 0x0 "CH12_CLK_CTRL,Channel 12 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH12_STATUS,Channel 12 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH12_CONFIG,Channel 12 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0x130++0xB line.long 0x0 "CH13_CLK_CTRL,Channel 13 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH13_STATUS,Channel 13 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH13_CONFIG,Channel 13 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0x140++0xB line.long 0x0 "CH14_CLK_CTRL,Channel 14 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH14_STATUS,Channel 14 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH14_CONFIG,Channel 14 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" rgroup.long 0x160++0xF line.long 0x0 "CH0_FMSG_DATA,Channel 0 Fast Message Data read register" hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x0 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x0 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x0 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x0 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x0 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x0 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x0 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0x4 "CH0_FMSG_CRC,Channel 0 Fast Message CRC read register" hexmask.long.byte 0x4 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x8 "CH0_FMSG_TS,Channel 0 Fast Message Time Stamp read register" hexmask.long 0x8 0.--31. 1. "TS,Time Stamp for received message" line.long 0xC "CH0_SMSG_BIT3_C0,Channel 0 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0xC 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0xC 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0xC 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0xC 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0xC 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0xC 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x16C++0x7 line.long 0x0 "CH0_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH0_SMSG_BIT2_C0,Channel 0 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x170++0x17 line.long 0x0 "CH0_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH0_SMSG_TS,Channel 0 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH1_FMSG_DATA,Channel 1 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH1_FMSG_CRC,Channel 1 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH1_FMSG_TS,Channel 1 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH1_SMSG_BIT3_C0,Channel 1 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x184++0x7 line.long 0x0 "CH1_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH1_SMSG_BIT2_C0,Channel 1 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x188++0x17 line.long 0x0 "CH1_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH1_SMSG_TS,Channel 1 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH2_FMSG_DATA,Channel 2 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH2_FMSG_CRC,Channel 2 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH2_FMSG_TS,Channel 2 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH2_SMSG_BIT3_C0,Channel 2 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x19C++0x7 line.long 0x0 "CH2_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH2_SMSG_BIT2_C0,Channel 2 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x1A0++0x17 line.long 0x0 "CH2_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH2_SMSG_TS,Channel 2 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH3_FMSG_DATA,Channel 3 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH3_FMSG_CRC,Channel 3 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH3_FMSG_TS,Channel 3 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH3_SMSG_BIT3_C0,Channel 3 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x1B4++0x7 line.long 0x0 "CH3_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH3_SMSG_BIT2_C0,Channel 3 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x1B8++0x17 line.long 0x0 "CH3_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH3_SMSG_TS,Channel 3 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH4_FMSG_DATA,Channel 4 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH4_FMSG_CRC,Channel 4 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH4_FMSG_TS,Channel 4 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH4_SMSG_BIT3_C0,Channel 4 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x1CC++0x7 line.long 0x0 "CH4_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH4_SMSG_BIT2_C0,Channel 4 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x1D0++0x17 line.long 0x0 "CH4_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH4_SMSG_TS,Channel 4 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH5_FMSG_DATA,Channel 5 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH5_FMSG_CRC,Channel 5 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH5_FMSG_TS,Channel 5 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH5_SMSG_BIT3_C0,Channel 5 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x1E4++0x7 line.long 0x0 "CH5_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH5_SMSG_BIT2_C0,Channel 5 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x1E8++0x17 line.long 0x0 "CH5_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH5_SMSG_TS,Channel 5 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH6_FMSG_DATA,Channel 6 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH6_FMSG_CRC,Channel 6 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH6_FMSG_TS,Channel 6 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH6_SMSG_BIT3_C0,Channel 6 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x1FC++0x7 line.long 0x0 "CH6_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH6_SMSG_BIT2_C0,Channel 6 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x200++0x17 line.long 0x0 "CH6_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH6_SMSG_TS,Channel 6 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH7_FMSG_DATA,Channel 7 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH7_FMSG_CRC,Channel 7 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH7_FMSG_TS,Channel 7 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH7_SMSG_BIT3_C0,Channel 7 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x214++0x7 line.long 0x0 "CH7_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH7_SMSG_BIT2_C0,Channel 7 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x218++0x17 line.long 0x0 "CH7_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH7_SMSG_TS,Channel 7 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH8_FMSG_DATA,Channel 8 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH8_FMSG_CRC,Channel 8 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH8_FMSG_TS,Channel 8 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH8_SMSG_BIT3_C0,Channel 8 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x22C++0x7 line.long 0x0 "CH8_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH8_SMSG_BIT2_C0,Channel 8 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x230++0x17 line.long 0x0 "CH8_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH8_SMSG_TS,Channel 8 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH9_FMSG_DATA,Channel 9 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH9_FMSG_CRC,Channel 9 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH9_FMSG_TS,Channel 9 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH9_SMSG_BIT3_C0,Channel 9 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x244++0x7 line.long 0x0 "CH9_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH9_SMSG_BIT2_C0,Channel 9 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x248++0x17 line.long 0x0 "CH9_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH9_SMSG_TS,Channel 9 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH10_FMSG_DATA,Channel 10 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH10_FMSG_CRC,Channel 10 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH10_FMSG_TS,Channel 10 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH10_SMSG_BIT3_C0,Channel 10 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x25C++0x7 line.long 0x0 "CH10_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH10_SMSG_BIT2_C0,Channel 10 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x260++0x17 line.long 0x0 "CH10_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH10_SMSG_TS,Channel 10 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH11_FMSG_DATA,Channel 11 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH11_FMSG_CRC,Channel 11 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH11_FMSG_TS,Channel 11 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH11_SMSG_BIT3_C0,Channel 11 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x274++0x7 line.long 0x0 "CH11_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH11_SMSG_BIT2_C0,Channel 11 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x278++0x17 line.long 0x0 "CH11_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH11_SMSG_TS,Channel 11 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH12_FMSG_DATA,Channel 12 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH12_FMSG_CRC,Channel 12 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH12_FMSG_TS,Channel 12 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH12_SMSG_BIT3_C0,Channel 12 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x28C++0x7 line.long 0x0 "CH12_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH12_SMSG_BIT2_C0,Channel 12 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x290++0x17 line.long 0x0 "CH12_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH12_SMSG_TS,Channel 12 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH13_FMSG_DATA,Channel 13 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH13_FMSG_CRC,Channel 13 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH13_FMSG_TS,Channel 13 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH13_SMSG_BIT3_C0,Channel 13 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x2A4++0x7 line.long 0x0 "CH13_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH13_SMSG_BIT2_C0,Channel 13 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x2A8++0x17 line.long 0x0 "CH13_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH13_SMSG_TS,Channel 13 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH14_FMSG_DATA,Channel 14 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH14_FMSG_CRC,Channel 14 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH14_FMSG_TS,Channel 14 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH14_SMSG_BIT3_C0,Channel 14 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x2BC++0x7 line.long 0x0 "CH14_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH14_SMSG_BIT2_C0,Channel 14 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x2C0++0x7 line.long 0x0 "CH14_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH14_SMSG_TS,Channel 14 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" rgroup.long 0x2E4++0x3B line.long 0x0 "CH0_FMSG_DATA2,Channel 0 Fast Message Data 2 read register" hexmask.long.byte 0x0 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x0 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x4 "CH1_FMSG_DATA2,Channel 1 Fast Message Data 2 read register" hexmask.long.byte 0x4 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x4 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x8 "CH2_FMSG_DATA2,Channel 2 Fast Message Data 2 read register" hexmask.long.byte 0x8 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0xC "CH3_FMSG_DATA2,Channel 3 Fast Message Data 2 read register" hexmask.long.byte 0xC 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0xC 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x10 "CH4_FMSG_DATA2,Channel 4 Fast Message Data 2 read register" hexmask.long.byte 0x10 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x10 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x14 "CH5_FMSG_DATA2,Channel 5 Fast Message Data 2 read register" hexmask.long.byte 0x14 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x14 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x18 "CH6_FMSG_DATA2,Channel 6 Fast Message Data 2 read register" hexmask.long.byte 0x18 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x18 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x1C "CH7_FMSG_DATA2,Channel 7 Fast Message Data 2 read register" hexmask.long.byte 0x1C 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x1C 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x20 "CH8_FMSG_DATA2,Channel 8 Fast Message Data 2 read register" hexmask.long.byte 0x20 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x20 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x24 "CH9_FMSG_DATA2,Channel 9 Fast Message Data 2 read register" hexmask.long.byte 0x24 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x24 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x28 "CH10_FMSG_DATA2,Channel 10 Fast Message Data 2 read register" hexmask.long.byte 0x28 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x28 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x2C "CH11_FMSG_DATA2,Channel 11 Fast Message Data 2 read register" hexmask.long.byte 0x2C 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x2C 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x30 "CH12_FMSG_DATA2,Channel 12 Fast Message Data 2 read register" hexmask.long.byte 0x30 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x30 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x34 "CH13_FMSG_DATA2,Channel 13 Fast Message Data 2 read register" hexmask.long.byte 0x34 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x34 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x38 "CH14_FMSG_DATA2,Channel 14 Fast Message Data 2 read register" hexmask.long.byte 0x38 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x38 0.--3. 1. "DNIB7,Data Nibble 7" group.long 0x324++0x3B line.long 0x0 "CH0_CNTR,Channel 0 Counter Register" hexmask.long.byte 0x0 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x0 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x4 "CH1_CNTR,Channel 1 Counter Register" hexmask.long.byte 0x4 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x4 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x8 "CH2_CNTR,Channel 2 Counter Register" hexmask.long.byte 0x8 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x8 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0xC "CH3_CNTR,Channel 3 Counter Register" hexmask.long.byte 0xC 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0xC 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x10 "CH4_CNTR,Channel 4 Counter Register" hexmask.long.byte 0x10 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x10 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x14 "CH5_CNTR,Channel 5 Counter Register" hexmask.long.byte 0x14 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x14 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x18 "CH6_CNTR,Channel 6 Counter Register" hexmask.long.byte 0x18 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x18 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x1C "CH7_CNTR,Channel 7 Counter Register" hexmask.long.byte 0x1C 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x1C 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x20 "CH8_CNTR,Channel 8 Counter Register" hexmask.long.byte 0x20 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x20 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x24 "CH9_CNTR,Channel 9 Counter Register" hexmask.long.byte 0x24 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x24 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x28 "CH10_CNTR,Channel 10 Counter Register" hexmask.long.byte 0x28 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x28 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x2C "CH11_CNTR,Channel 11 Counter Register" hexmask.long.byte 0x2C 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x2C 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x30 "CH12_CNTR,Channel 12 Counter Register" hexmask.long.byte 0x30 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x30 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x34 "CH13_CNTR,Channel 13 Counter Register" hexmask.long.byte 0x34 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x34 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x38 "CH14_CNTR,Channel 14 Counter Register" hexmask.long.byte 0x38 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x38 0.--7. 1. "FRAME_CNT,Valid frame counter" tree.end tree "SENT_1" base ad:0x714E8000 group.long 0x0++0x13 line.long 0x0 "GBL_CTRL,Global Control register" hexmask.long.byte 0x0 24.--31. 1. "TSPRSC,Time Stamp Prescaler Value" newline hexmask.long.byte 0x0 16.--20. 1. "FIFOWM,DMA Read FIFO Water Mark Level" newline bitfld.long 0x0 15. "NIB_LEN_VAR_LIMIT,Decides the allowable jitter/clock drift limit for nibble length measurement." "0: Allows a jitter/clock drift of approx up to..,1: Allows a jitter/clock drift as per SAE spec (50%)." newline bitfld.long 0x0 14. "INT_EXT_TS_SEL,Internal/External Time-stamp Select" "0: Internal counter is used to provide time-stamp..,1: External time-stamp bus is used" newline bitfld.long 0x0 13. "SENT_8NIB_EN,Decides maximum number of data nibbles that can be supported by a SENT channel in case of Fast message reception. Default value is 0." "0: Maximum 6 data nibbles supported per channel.,1: Maximum 8 data nibbles supported per channel." newline bitfld.long 0x0 10. "FMFOIE,Fast Message FIFO Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x0 9. "FMDUIE,Fast Message DMA Underflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x0 8. "SMDUIE,Slow Serial Message DMA Underflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x0 6. "FIFO_EN,FIFO enable bit" "0: FIFO is disabled.,1: FIFO is enabled." newline bitfld.long 0x0 4. "FAST_CLR,Fast Clearing Enable bit" "0: Fast Clearing is disabled. Bits will be cleared..,1: Fast Clearing is enabled." newline bitfld.long 0x0 2. "DBG_FRZ,Debug Freeze" "0: No effect in debug mode,1: Freeze in debug mode" newline bitfld.long 0x0 0. "SENT_EN,SENT Receiver Global Enable" "0: Entire module is disabled.,1: Module is enabled." line.long 0x4 "CHNL_EN,Channel Enable register" bitfld.long 0x4 14. "EN_CH14,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 13. "EN_CH13,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 12. "EN_CH12,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 11. "EN_CH11,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 10. "EN_CH10,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 9. "EN_CH9,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 8. "EN_CH8,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 7. "EN_CH7,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 6. "EN_CH6,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 5. "EN_CH5,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 4. "EN_CH4,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 3. "EN_CH3,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 2. "EN_CH2,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 1. "EN_CH1,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." newline bitfld.long 0x4 0. "EN_CH0,Enable bits for Channels 0 to (CH-1)" "0: Channel is disabled.,1: Channel is enabled. Channel parameter registers.." line.long 0x8 "GBL_STATUS,Global Status register" bitfld.long 0x8 10. "FMFO,Fast Message FIFO Overflow" "0: No Overflow,1: Overflow occurred" newline bitfld.long 0x8 9. "FMDU,Fast Message DMA Underflow" "0: No underflow,1: Underflow occurred" newline bitfld.long 0x8 8. "SMDU,Slow Serial Message DMA Underflow" "0: No underflow,1: Underflow occurred" line.long 0xC "FMSG_RDY,Fast Message Ready status register" bitfld.long 0xC 14. "F_RDY14,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 13. "F_RDY13,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 12. "F_RDY12,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 11. "F_RDY11,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 10. "F_RDY10,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 9. "F_RDY9,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 8. "F_RDY8,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 7. "F_RDY7,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 6. "F_RDY6,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 5. "F_RDY5,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 4. "F_RDY4,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 3. "F_RDY3,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 2. "F_RDY2,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 1. "F_RDY1,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." newline bitfld.long 0xC 0. "F_RDY0,Fast Message Data Ready Status Bit" "0: No Fast Message is available to be read out via..,1: Fast Message is available to be read out via.." line.long 0x10 "SMSG_RDY,Slow Serial Message Ready status register" bitfld.long 0x10 14. "S_RDY14,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 13. "S_RDY13,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 12. "S_RDY12,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 11. "S_RDY11,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 10. "S_RDY10,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 9. "S_RDY9,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 8. "S_RDY8,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 7. "S_RDY7,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 6. "S_RDY6,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 5. "S_RDY5,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 4. "S_RDY4,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 3. "S_RDY3,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 2. "S_RDY2,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 1. "S_RDY1,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." newline bitfld.long 0x10 0. "S_RDY0,Slow Serial Message Data Ready Status Bit" "0: No Slow Serial Message is available to be read..,1: Slow Serial Message is available to be read out.." rgroup.long 0x14++0x3 line.long 0x0 "ERR_STATUS_ALL,Combined Error Status register" bitfld.long 0x0 18. "FMFO,Fast Message FIFO Overflow" "0: No Overflow,1: Overflow occurred" newline bitfld.long 0x0 17. "FMDU,Fast Message DMA Underflow" "0: No underflow,1: Underflow occurred" newline bitfld.long 0x0 16. "SMDU,Slow Serial Message DMA Underflow" "0: No underflow,1: Underflow occurred" newline bitfld.long 0x0 14. "CH_ERR_ALL14,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 13. "CH_ERR_ALL13,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 12. "CH_ERR_ALL12,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 11. "CH_ERR_ALL11,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 10. "CH_ERR_ALL10,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 9. "CH_ERR_ALL9,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 8. "CH_ERR_ALL8,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 7. "CH_ERR_ALL7,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 6. "CH_ERR_ALL6,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 5. "CH_ERR_ALL5,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 4. "CH_ERR_ALL4,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 3. "CH_ERR_ALL3,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 2. "CH_ERR_ALL2,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 1. "CH_ERR_ALL1,Combined error flag of Channel Status Register" "0,1" newline bitfld.long 0x0 0. "CH_ERR_ALL0,Combined error flag of Channel Status Register" "0,1" group.long 0x18++0x17 line.long 0x0 "DATA_CTRL1,Data Control register 1" hexmask.long.byte 0x0 28.--31. 1. "NIBBCH0,Number of Data Nibbles supported in Channel 0" newline hexmask.long.byte 0x0 24.--27. 1. "NIBBCH1,Number of Data Nibbles supported in Channel 1" newline hexmask.long.byte 0x0 20.--23. 1. "NIBBCH2,Number of Data Nibbles supported in Channel 2" newline hexmask.long.byte 0x0 16.--19. 1. "NIBBCH3,Number of Data Nibbles supported in Channel 3" newline hexmask.long.byte 0x0 12.--15. 1. "NIBBCH4,Number of Data Nibbles supported in Channel 4" newline hexmask.long.byte 0x0 8.--11. 1. "NIBBCH5,Number of Data Nibbles supported in Channel 5" newline hexmask.long.byte 0x0 4.--7. 1. "NIBBCH6,Number of Data Nibbles supported in Channel 6" newline hexmask.long.byte 0x0 0.--3. 1. "NIBBCH7,Number of Data Nibbles supported in Channel 7" line.long 0x4 "DATA_CTRL2,Data Control register 2" hexmask.long.byte 0x4 28.--31. 1. "NIBBCH8,Number of Data Nibbles supported in Channel 8" newline hexmask.long.byte 0x4 24.--27. 1. "NIBBCH9,Number of Data Nibbles supported in Channel 9" newline hexmask.long.byte 0x4 20.--23. 1. "NIBBCH10,Number of Data Nibbles supported in Channel 10" newline hexmask.long.byte 0x4 16.--19. 1. "NIBBCH11,Number of Data Nibbles supported in Channel 11" newline hexmask.long.byte 0x4 12.--15. 1. "NIBBCH12,Number of Data Nibbles supported in Channel 12" newline hexmask.long.byte 0x4 8.--11. 1. "NIBBCH13,Number of Data Nibbles supported in Channel 13" newline hexmask.long.byte 0x4 4.--7. 1. "NIBBCH14,Number of Data Nibbles supported in Channel 14" line.long 0x8 "DATA_RESORT1,Data Re-sort register 1" bitfld.long 0x8 28.--30. "RESORTCH0,Re-sorting scheme for Channel 0" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0x8 24.--26. "RESORTCH1,Re-sorting scheme for Channel 1" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0x8 20.--22. "RESORTCH2,Re-sorting scheme for Channel 2" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0x8 16.--18. "RESORTCH3,Re-sorting scheme for Channel 3" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0x8 12.--14. "RESORTCH4,Re-sorting scheme for Channel 4" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0x8 8.--10. "RESORTCH5,Re-sorting scheme for Channel 5" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0x8 4.--6. "RESORTCH6,Re-sorting scheme for Channel 6" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0x8 0.--2. "RESORTCH7,Re-sorting scheme for Channel 7" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" line.long 0xC "DATA_RESORT2,Data Re-sort register 2" bitfld.long 0xC 28.--30. "RESORTCH8,Re-sorting scheme for Channel 8" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0xC 24.--26. "RESORTCH9,Re-sorting scheme for Channel 9" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0xC 20.--22. "RESORTCH10,Re-sorting scheme for Channel 10" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0xC 16.--18. "RESORTCH11,Re-sorting scheme for Channel 11" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0xC 12.--14. "RESORTCH12,Re-sorting scheme for Channel 12" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0xC 8.--10. "RESORTCH13,Re-sorting scheme for Channel 13" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" newline bitfld.long 0xC 4.--6. "RESORTCH14,Re-sorting scheme for Channel 14" "0: No re-sorting,1: Re-sorting frame format type H.1,2: No re-sorting,3: Re-sorting frame format type H.3,4: No re-sorting,5: No re-sorting,6: Re-sorting frame format type H.6,7: Re-sorting frame format type H.7" line.long 0x10 "FDMA_CTRL,Fast Message DMA Control register" bitfld.long 0x10 14. "FDMA_EN14,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 13. "FDMA_EN13,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 12. "FDMA_EN12,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 11. "FDMA_EN11,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 10. "FDMA_EN10,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 9. "FDMA_EN9,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 8. "FDMA_EN8,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 7. "FDMA_EN7,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 6. "FDMA_EN6,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 5. "FDMA_EN5,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 4. "FDMA_EN4,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 3. "FDMA_EN3,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 2. "FDMA_EN2,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 1. "FDMA_EN1,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." newline bitfld.long 0x10 0. "FDMA_EN0,Enable DMA for Fast Messages on Channels 0 to (CH-1)" "0: DMA for Fast Messages is disabled.,1: DMA for Fast Messages is enabled." line.long 0x14 "SDMA_CTRL,Slow Serial Message DMA Control register" bitfld.long 0x14 14. "SDMA_EN14,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 13. "SDMA_EN13,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 12. "SDMA_EN12,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 11. "SDMA_EN11,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 10. "SDMA_EN10,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 9. "SDMA_EN9,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 8. "SDMA_EN8,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 7. "SDMA_EN7,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 6. "SDMA_EN6,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 5. "SDMA_EN5,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 4. "SDMA_EN4,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 3. "SDMA_EN3,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 2. "SDMA_EN2,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 1. "SDMA_EN1,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." newline bitfld.long 0x14 0. "SDMA_EN0,Enable DMA for Slow Serial Messages on Channels 0 to (CH-1)" "0: DMA for Slow Serial Messages is disabled.,1: DMA for Slow Serial Messages is enabled." group.long 0x34++0x7 line.long 0x0 "FRDY_IE,Fast Message Ready Interrupt Control register" bitfld.long 0x0 14. "FRDY_IE14,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 13. "FRDY_IE13,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 12. "FRDY_IE12,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 11. "FRDY_IE11,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 10. "FRDY_IE10,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 9. "FRDY_IE9,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 8. "FRDY_IE8,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 7. "FRDY_IE7,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 6. "FRDY_IE6,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 5. "FRDY_IE5,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 4. "FRDY_IE4,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 3. "FRDY_IE3,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 2. "FRDY_IE2,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 1. "FRDY_IE1,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." newline bitfld.long 0x0 0. "FRDY_IE0,Enable for Fast Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Fast Messages is..,1: Interrupt on reception of Fast Messages is.." line.long 0x4 "SRDY_IE,Slow Serial Message Ready Interrupt Enable register" bitfld.long 0x4 14. "SRDY_IE14,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 13. "SRDY_IE13,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 12. "SRDY_IE12,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 11. "SRDY_IE11,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 10. "SRDY_IE10,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 9. "SRDY_IE9,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 8. "SRDY_IE8,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 7. "SRDY_IE7,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 6. "SRDY_IE6,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 5. "SRDY_IE5,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 4. "SRDY_IE4,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 3. "SRDY_IE3,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 2. "SRDY_IE2,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 1. "SRDY_IE1,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." newline bitfld.long 0x4 0. "SRDY_IE0,Enable for Slow Serial Message Ready Interrupt on Channels 0 to (CH-1)" "0: Interrupt on reception of Slow Serial Messages..,1: Interrupt on reception of Slow Serial Messages.." rgroup.long 0x40++0x13 line.long 0x0 "DMA_FMSG_DATA,DMA Fast Message Data read register" hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x0 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x0 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x0 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x0 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x0 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x0 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x0 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0x4 "DMA_FMSG_CRC,DMA Fast Message CRC read register" hexmask.long.byte 0x4 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x8 "DMA_FMSG_TS,DMA Fast Message Time Stamp read register" hexmask.long 0x8 0.--31. 1. "TS,TS" line.long 0xC "DMA_FMSG_DATA2,DMA Fast Message Data 2read register" hexmask.long.byte 0xC 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0xC 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x10 "DMA_SMSG_BIT3_C0,DMA Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x10 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x10 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x10 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x10 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x10 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x10 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x50++0x7 line.long 0x0 "DMA_SMSG_BIT3_C1,The DMA_SMSG_BIT3 is common for all types of slow serial messages. Bit C defines the type of enhanced packet and bit TYPE defines whether it is short serial or enhanced serial message. Since this register is used to read both Short and.." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "DMA_SMSG_BIT2_C0,DMA Slow Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x54++0x7 line.long 0x0 "DMA_SMSG_BIT2_C1,This register (DMA_SMSG_BIT2) is common for all types of slow serial messages. Hence. the register fields have been placed in such a way to match the bit positions in actual message defined by SAE Specification as shown in Figure42..." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "DMA_SMSG_TS,DMA Slow Serial Message Time Stamp read register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" group.long 0x60++0xB line.long 0x0 "CH0_CLK_CTRL,Channel 0 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH0_STATUS,Channel 0 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH0_CONFIG,Channel 0 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0x70++0xB line.long 0x0 "CH1_CLK_CTRL,Channel 1 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH1_STATUS,Channel 1 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH1_CONFIG,Channel 1 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0x80++0xB line.long 0x0 "CH2_CLK_CTRL,Channel 2 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH2_STATUS,Channel 2 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH2_CONFIG,Channel 2 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0x90++0xB line.long 0x0 "CH3_CLK_CTRL,Channel 3 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH3_STATUS,Channel 3 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH3_CONFIG,Channel 3 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0xA0++0xB line.long 0x0 "CH4_CLK_CTRL,Channel 4 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH4_STATUS,Channel 4 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH4_CONFIG,Channel 4 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0xB0++0xB line.long 0x0 "CH5_CLK_CTRL,Channel 5 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH5_STATUS,Channel 5 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH5_CONFIG,Channel 5 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0xC0++0xB line.long 0x0 "CH6_CLK_CTRL,Channel 6 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH6_STATUS,Channel 6 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH6_CONFIG,Channel 6 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0xD0++0xB line.long 0x0 "CH7_CLK_CTRL,Channel 7 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH7_STATUS,Channel 7 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH7_CONFIG,Channel 7 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0xE0++0xB line.long 0x0 "CH8_CLK_CTRL,Channel 8 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH8_STATUS,Channel 8 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH8_CONFIG,Channel 8 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0xF0++0xB line.long 0x0 "CH9_CLK_CTRL,Channel 9 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH9_STATUS,Channel 9 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH9_CONFIG,Channel 9 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0x100++0xB line.long 0x0 "CH10_CLK_CTRL,Channel 10 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH10_STATUS,Channel 10 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH10_CONFIG,Channel 10 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0x110++0xB line.long 0x0 "CH11_CLK_CTRL,Channel 11 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH11_STATUS,Channel 11 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH11_CONFIG,Channel 11 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0x120++0xB line.long 0x0 "CH12_CLK_CTRL,Channel 12 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH12_STATUS,Channel 12 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH12_CONFIG,Channel 12 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0x130++0xB line.long 0x0 "CH13_CLK_CTRL,Channel 13 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH13_STATUS,Channel 13 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH13_CONFIG,Channel 13 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" group.long 0x140++0xB line.long 0x0 "CH14_CLK_CTRL,Channel 14 Clock Control register" hexmask.long.word 0x0 16.--30. 1. "CM_PRSC,Compensated Prescaler Value" newline bitfld.long 0x0 15. "COMP_EN,Compensation Enable" "0: Compensation is disabled.,1: Compensation is enabled." newline hexmask.long.word 0x0 0.--13. 1. "PRSC,Rx Prescaler Value" line.long 0x4 "CH14_STATUS,Channel 14 Status Register" bitfld.long 0x4 31. "BUS_IDLE,Bus Idle Status" "0: Bus is not idle.,1: Channel has been idle for more than the allowed.." newline bitfld.long 0x4 30. "RDI,SENT Channel Receive Data Input signal" "0,1" newline bitfld.long 0x4 27. "CAL_RESYNC,Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized" "0: No interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 26. "CAL_20_25,Calibration Variation 2025% Interrupt Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 25. "SMSG_OFLW,Slow Serial Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred." newline bitfld.long 0x4 24. "FMSG_OFLW,Fast Message Overflow Status" "0: No Interrupt,1: Interrupt Status condition has occurred" newline bitfld.long 0x4 22. "PP_DIAG_ERR,This diagnostic checks status bit indicates that the ratio of calibration pulse length to overall message length (with pause pulse) is more than ±1.5625% between two messages. This check is valid only for messages with pause pulse. This bit.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 21. "CAL_LEN_ERR,This diagnostic checks status bit indicates that Calibration pulse is more than 56 ticks ±25%. This bit indicates whether this diagnostic has failed or passed on this channel and is cleared by writing a 1 to it." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 20. "CAL_DIAG_ERR,Successive Calibration pulses differ by ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the frequency of protocol clock (see Section1.5.3: High frequency receiver clock (protocol clock) requirements). This.." "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 19. "NIB_VAL_ERR,Any nibble data value <0 or >15. This diagnostic checks status bit indicates whether this diagnostic has" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 18. "SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 17. "FMSG_CRC_ERR,Checksum error in Fast Message" "0: Error Check has passed.,1: Error Check has failed." newline bitfld.long 0x4 16. "NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This diagnostic checks status bit indicates whether this diagnostic has failed or passed on this channel. This bit will not set in case of 'Option 2' for successive.." "0: Error Check has passed.,1: Error Check has failed." line.long 0x8 "CH14_CONFIG,Channel 14 Configuration register" hexmask.long.byte 0x8 28.--31. 1. "BUS_IDLE_CNT,Bus Idle Count" newline bitfld.long 0x8 27. "IE_CAL_RESYNC,Successive Calibration Check Resynchronized Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 26. "IE_CAL_20_25,Calibration Variation 20 - 25% Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 25. "IE_SMSG_OFLW,Slow Serial Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 24. "IE_FMSG_OFLW,Fast Message Overflow Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 23. "FCRC_CHK_OFF,Fast Message CRC Check Off" "0: Check is enabled.,1: Check is disabled/off." newline bitfld.long 0x8 22. "IE_PP_DIAG_ERR,Ratio of calibration pulse length to message length varies by more than ±1.5625% between two frames." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 21. "IE_CAL_LEN_ERR,Calibration pulse is wider than 56 ticks ±25%. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 20. "IE_CAL_DIAG_ERR,Successive Calibration pulses differ by more than ±1.56%. SAE spec defines it be 1.5625% but the accuracy of this check depends on the protocol clock. For instance for 62.5 MHz this check will fail for 1.56% and passes for 1.55%. This.." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 19. "IE_NIB_VAL_ERR,Any nibble data value <0 or >15" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 18. "IE_SMSG_CRC_ERR,Checksum error in Slow Serial Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 17. "IE_FMSG_CRC_ERR,Checksum error in Fast Message" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 16. "IE_NUM_EDGES_ERR,Not the expected number of negative edges between calibration pulse. This bit enables interrupt assertion when its respective diagnostic check fails on the corresponding channel." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 15. "DCHNG_INT,Enable for Interrupt on Reception of Fast Message with Changed Data" "0: All Fast Messages will be received even if data..,1: Only Fast Messages with differing values of data.." newline bitfld.long 0x8 14. "CAL_RNG,Valid Calibration Pulse Range Selection" "0: 20% variation is acceptable.,1: 25% variation is acceptable." newline bitfld.long 0x8 13. "PP_CHKSEL,Pause Pulse Diagnostic Check Selection" "0: Both Successive Calibration Pulse Check and..,1: Only Pause Pulse Diagnostic is run. Successive.." newline bitfld.long 0x8 12. "FCRC_TYPE,Fast Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 11. "FCRC_SC_EN,Fast Message CRC Status and Communication Nibble Enable" "0: Status and Communication Nibble not included in..,1: Status and Communication Nibble is included in.." newline bitfld.long 0x8 10. "SCRC_TYPE,Slow Serial Message CRC Type" "0: XOR based implementation (Recommended by SAE..,1: Legacy LUT based implementation." newline bitfld.long 0x8 9. "PAUSE_EN,Pause Pulse Enable" "0: Detection of Pause Pulse is disabled.,1: Detection of Pause Pulse enabled." newline bitfld.long 0x8 8. "SUCC_CAL_CHK,Successive Calibration Pulse Check Method" "0: Option 2 such as Low Latency Option as per SAE..,1: Option 1 such as Preferred but High Latency.." newline hexmask.long.byte 0x8 0.--7. 1. "FIL_CNT,Input Filter Sample Count" rgroup.long 0x160++0xF line.long 0x0 "CH0_FMSG_DATA,Channel 0 Fast Message Data read register" hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x0 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x0 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x0 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x0 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x0 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x0 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x0 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0x4 "CH0_FMSG_CRC,Channel 0 Fast Message CRC read register" hexmask.long.byte 0x4 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x8 "CH0_FMSG_TS,Channel 0 Fast Message Time Stamp read register" hexmask.long 0x8 0.--31. 1. "TS,Time Stamp for received message" line.long 0xC "CH0_SMSG_BIT3_C0,Channel 0 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0xC 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0xC 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0xC 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0xC 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0xC 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0xC 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x16C++0x7 line.long 0x0 "CH0_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH0_SMSG_BIT2_C0,Channel 0 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x170++0x17 line.long 0x0 "CH0_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH0_SMSG_TS,Channel 0 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH1_FMSG_DATA,Channel 1 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH1_FMSG_CRC,Channel 1 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH1_FMSG_TS,Channel 1 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH1_SMSG_BIT3_C0,Channel 1 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x184++0x7 line.long 0x0 "CH1_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH1_SMSG_BIT2_C0,Channel 1 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x188++0x17 line.long 0x0 "CH1_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH1_SMSG_TS,Channel 1 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH2_FMSG_DATA,Channel 2 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH2_FMSG_CRC,Channel 2 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH2_FMSG_TS,Channel 2 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH2_SMSG_BIT3_C0,Channel 2 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x19C++0x7 line.long 0x0 "CH2_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH2_SMSG_BIT2_C0,Channel 2 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x1A0++0x17 line.long 0x0 "CH2_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH2_SMSG_TS,Channel 2 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH3_FMSG_DATA,Channel 3 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH3_FMSG_CRC,Channel 3 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH3_FMSG_TS,Channel 3 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH3_SMSG_BIT3_C0,Channel 3 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x1B4++0x7 line.long 0x0 "CH3_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH3_SMSG_BIT2_C0,Channel 3 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x1B8++0x17 line.long 0x0 "CH3_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH3_SMSG_TS,Channel 3 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH4_FMSG_DATA,Channel 4 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH4_FMSG_CRC,Channel 4 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH4_FMSG_TS,Channel 4 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH4_SMSG_BIT3_C0,Channel 4 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x1CC++0x7 line.long 0x0 "CH4_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH4_SMSG_BIT2_C0,Channel 4 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x1D0++0x17 line.long 0x0 "CH4_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH4_SMSG_TS,Channel 4 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH5_FMSG_DATA,Channel 5 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH5_FMSG_CRC,Channel 5 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH5_FMSG_TS,Channel 5 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH5_SMSG_BIT3_C0,Channel 5 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x1E4++0x7 line.long 0x0 "CH5_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH5_SMSG_BIT2_C0,Channel 5 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x1E8++0x17 line.long 0x0 "CH5_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH5_SMSG_TS,Channel 5 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH6_FMSG_DATA,Channel 6 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH6_FMSG_CRC,Channel 6 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH6_FMSG_TS,Channel 6 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH6_SMSG_BIT3_C0,Channel 6 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x1FC++0x7 line.long 0x0 "CH6_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH6_SMSG_BIT2_C0,Channel 6 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x200++0x17 line.long 0x0 "CH6_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH6_SMSG_TS,Channel 6 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH7_FMSG_DATA,Channel 7 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH7_FMSG_CRC,Channel 7 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH7_FMSG_TS,Channel 7 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH7_SMSG_BIT3_C0,Channel 7 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x214++0x7 line.long 0x0 "CH7_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH7_SMSG_BIT2_C0,Channel 7 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x218++0x17 line.long 0x0 "CH7_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH7_SMSG_TS,Channel 7 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH8_FMSG_DATA,Channel 8 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH8_FMSG_CRC,Channel 8 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH8_FMSG_TS,Channel 8 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH8_SMSG_BIT3_C0,Channel 8 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x22C++0x7 line.long 0x0 "CH8_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH8_SMSG_BIT2_C0,Channel 8 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x230++0x17 line.long 0x0 "CH8_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH8_SMSG_TS,Channel 8 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH9_FMSG_DATA,Channel 9 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH9_FMSG_CRC,Channel 9 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH9_FMSG_TS,Channel 9 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH9_SMSG_BIT3_C0,Channel 9 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x244++0x7 line.long 0x0 "CH9_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH9_SMSG_BIT2_C0,Channel 9 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x248++0x17 line.long 0x0 "CH9_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH9_SMSG_TS,Channel 9 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH10_FMSG_DATA,Channel 10 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH10_FMSG_CRC,Channel 10 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH10_FMSG_TS,Channel 10 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH10_SMSG_BIT3_C0,Channel 10 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x25C++0x7 line.long 0x0 "CH10_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH10_SMSG_BIT2_C0,Channel 10 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x260++0x17 line.long 0x0 "CH10_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH10_SMSG_TS,Channel 10 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH11_FMSG_DATA,Channel 11 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH11_FMSG_CRC,Channel 11 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH11_FMSG_TS,Channel 11 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH11_SMSG_BIT3_C0,Channel 11 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x274++0x7 line.long 0x0 "CH11_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH11_SMSG_BIT2_C0,Channel 11 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x278++0x17 line.long 0x0 "CH11_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH11_SMSG_TS,Channel 11 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH12_FMSG_DATA,Channel 12 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH12_FMSG_CRC,Channel 12 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH12_FMSG_TS,Channel 12 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH12_SMSG_BIT3_C0,Channel 12 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x28C++0x7 line.long 0x0 "CH12_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH12_SMSG_BIT2_C0,Channel 12 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x290++0x17 line.long 0x0 "CH12_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH12_SMSG_TS,Channel 12 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH13_FMSG_DATA,Channel 13 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH13_FMSG_CRC,Channel 13 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH13_FMSG_TS,Channel 13 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH13_SMSG_BIT3_C0,Channel 13 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x2A4++0x7 line.long 0x0 "CH13_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH13_SMSG_BIT2_C0,Channel 13 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x2A8++0x17 line.long 0x0 "CH13_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH13_SMSG_TS,Channel 13 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" line.long 0x8 "CH14_FMSG_DATA,Channel 14 Fast Message Data read register" hexmask.long.byte 0x8 28.--31. 1. "CHNUM,Channel Number" newline hexmask.long.byte 0x8 24.--27. 1. "SCNIB,Status and Communication Nibble of message" newline hexmask.long.byte 0x8 20.--23. 1. "DNIB1,Data Nibble 1" newline hexmask.long.byte 0x8 16.--19. 1. "DNIB2,Data Nibble 2" newline hexmask.long.byte 0x8 12.--15. 1. "DNIB3,Data Nibble 3" newline hexmask.long.byte 0x8 8.--11. 1. "DNIB4,Data Nibble 4" newline hexmask.long.byte 0x8 4.--7. 1. "DNIB5,Data Nibble 5" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB6,Data Nibble 6" line.long 0xC "CH14_FMSG_CRC,Channel 14 Fast Message CRC read register" hexmask.long.byte 0xC 16.--19. 1. "CRC4B,4-bit CRC value of the message" line.long 0x10 "CH14_FMSG_TS,Channel 14 Fast Message Time Stamp read register" hexmask.long 0x10 0.--31. 1. "TS,Time Stamp for received message" line.long 0x14 "CH14_SMSG_BIT3_C0,Channel 14 Slow Serial Message Bit3 Read Register" hexmask.long.byte 0x14 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x14 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x14 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x14 8.--9. "ID7_6,ID Field" "0,1,2,3" newline bitfld.long 0x14 6.--7. "ID5_4,ID Field" "0,1,2,3" newline hexmask.long.byte 0x14 1.--4. 1. "ID3_0,ID or Data Field" rgroup.long 0x2BC++0x7 line.long 0x0 "CH14_SMSG_BIT3_C1,This is CHn_SMSG_BIT3 register." hexmask.long.byte 0x0 28.--31. 1. "CHNUM,Channel Number" newline bitfld.long 0x0 27. "TYPE,Serial Message Type" "0: Short Serial Message,1: Enhanced Serial Message" newline bitfld.long 0x0 10. "CFG,Configuration bit C" "0: Enhanced Serial Message with 8-bit ID field,1: Enhanced Serial Message with 4-bit ID field" newline bitfld.long 0x0 8.--9. "ID3_2,ID Field" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID1_0,ID Field" "0,1,2,3" newline hexmask.long.byte 0x0 1.--4. 1. "DATA15_12,ID or Data Field" line.long 0x4 "CH14_SMSG_BIT2_C0,Channel 14 Serial Message Bit2 Read Register" hexmask.long.byte 0x4 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x4 8.--11. 1. "ID3_0,ID or Data Field" newline hexmask.long.byte 0x4 0.--7. 1. "DATA7_0,Data Field" rgroup.long 0x2C0++0x7 line.long 0x0 "CH14_SMSG_BIT2_C1,This is CHn_SMSG_BIT2 register." hexmask.long.byte 0x0 16.--21. 1. "SMCRC,6-bit CRC value of the message" newline hexmask.long.byte 0x0 8.--11. 1. "DATA11_8,ID or Data Field" newline hexmask.long.byte 0x0 0.--7. 1. "DATA7_0,Data Field" line.long 0x4 "CH14_SMSG_TS,Channel 14 Serial Message Time Stamp Read Register" hexmask.long 0x4 0.--31. 1. "TS,Time Stamp for the received message" rgroup.long 0x2E4++0x3B line.long 0x0 "CH0_FMSG_DATA2,Channel 0 Fast Message Data 2 read register" hexmask.long.byte 0x0 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x0 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x4 "CH1_FMSG_DATA2,Channel 1 Fast Message Data 2 read register" hexmask.long.byte 0x4 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x4 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x8 "CH2_FMSG_DATA2,Channel 2 Fast Message Data 2 read register" hexmask.long.byte 0x8 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x8 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0xC "CH3_FMSG_DATA2,Channel 3 Fast Message Data 2 read register" hexmask.long.byte 0xC 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0xC 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x10 "CH4_FMSG_DATA2,Channel 4 Fast Message Data 2 read register" hexmask.long.byte 0x10 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x10 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x14 "CH5_FMSG_DATA2,Channel 5 Fast Message Data 2 read register" hexmask.long.byte 0x14 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x14 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x18 "CH6_FMSG_DATA2,Channel 6 Fast Message Data 2 read register" hexmask.long.byte 0x18 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x18 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x1C "CH7_FMSG_DATA2,Channel 7 Fast Message Data 2 read register" hexmask.long.byte 0x1C 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x1C 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x20 "CH8_FMSG_DATA2,Channel 8 Fast Message Data 2 read register" hexmask.long.byte 0x20 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x20 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x24 "CH9_FMSG_DATA2,Channel 9 Fast Message Data 2 read register" hexmask.long.byte 0x24 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x24 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x28 "CH10_FMSG_DATA2,Channel 10 Fast Message Data 2 read register" hexmask.long.byte 0x28 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x28 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x2C "CH11_FMSG_DATA2,Channel 11 Fast Message Data 2 read register" hexmask.long.byte 0x2C 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x2C 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x30 "CH12_FMSG_DATA2,Channel 12 Fast Message Data 2 read register" hexmask.long.byte 0x30 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x30 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x34 "CH13_FMSG_DATA2,Channel 13 Fast Message Data 2 read register" hexmask.long.byte 0x34 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x34 0.--3. 1. "DNIB7,Data Nibble 7" line.long 0x38 "CH14_FMSG_DATA2,Channel 14 Fast Message Data 2 read register" hexmask.long.byte 0x38 4.--7. 1. "DNIB8,Data Nibble 8" newline hexmask.long.byte 0x38 0.--3. 1. "DNIB7,Data Nibble 7" group.long 0x324++0x3B line.long 0x0 "CH0_CNTR,Channel 0 Counter Register" hexmask.long.byte 0x0 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x0 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x4 "CH1_CNTR,Channel 1 Counter Register" hexmask.long.byte 0x4 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x4 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x8 "CH2_CNTR,Channel 2 Counter Register" hexmask.long.byte 0x8 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x8 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0xC "CH3_CNTR,Channel 3 Counter Register" hexmask.long.byte 0xC 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0xC 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x10 "CH4_CNTR,Channel 4 Counter Register" hexmask.long.byte 0x10 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x10 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x14 "CH5_CNTR,Channel 5 Counter Register" hexmask.long.byte 0x14 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x14 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x18 "CH6_CNTR,Channel 6 Counter Register" hexmask.long.byte 0x18 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x18 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x1C "CH7_CNTR,Channel 7 Counter Register" hexmask.long.byte 0x1C 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x1C 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x20 "CH8_CNTR,Channel 8 Counter Register" hexmask.long.byte 0x20 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x20 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x24 "CH9_CNTR,Channel 9 Counter Register" hexmask.long.byte 0x24 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x24 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x28 "CH10_CNTR,Channel 10 Counter Register" hexmask.long.byte 0x28 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x28 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x2C "CH11_CNTR,Channel 11 Counter Register" hexmask.long.byte 0x2C 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x2C 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x30 "CH12_CNTR,Channel 12 Counter Register" hexmask.long.byte 0x30 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x30 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x34 "CH13_CNTR,Channel 13 Counter Register" hexmask.long.byte 0x34 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x34 0.--7. 1. "FRAME_CNT,Valid frame counter" line.long 0x38 "CH14_CNTR,Channel 14 Counter Register" hexmask.long.byte 0x38 16.--23. 1. "EDGE_CNT,Edge counter" newline hexmask.long.byte 0x38 0.--7. 1. "FRAME_CNT,Valid frame counter" tree.end tree.end tree "SIPI (Serial Interprocessor Interface)" base ad:0x0 tree "SIPI_0" base ad:0x704AC000 group.long 0x0++0x7 line.long 0x0 "CCR0,SIPI Channel Control Register" bitfld.long 0x0 16. "TC,Send Trigger Command" "0: Trigger command not sent,1: Trigger command sent" bitfld.long 0x0 6.--7. "WL,Word Length Transfer" "0: 8-bit,1: 16-bit,2: 32-bit,3: not used" newline bitfld.long 0x0 5. "CHEN,Channel Enable" "0: Channel is disabled,1: Channel is enabled" bitfld.long 0x0 4. "ST,Streaming Transfer" "0: Streaming transfer is disabled,1: Streaming transfer is enabled" newline bitfld.long 0x0 3. "IDT,ID Read Request Transfer" "0: ID read request not sent,1: ID read request sent" bitfld.long 0x0 2. "RRT,Read Request Transfer" "0: Read request will not be sent,1: Read request transfer by the initiator. This bit.." newline bitfld.long 0x0 1. "WRT,Write Request Transfer" "0: No write request will be sent,1: Write request transfer by the initiator. This.." bitfld.long 0x0 0. "DEN,DMA Enable. When enabling DMA mode this bit should be set by software. It will then be cleared by hardware after one major loop has completed." "0: Channel will be used for bus interface access,1: Channel will be used for DMA access" line.long 0x4 "CSR0,SIPI Channel Status Register" bitfld.long 0x4 7. "RAR,Read Answer Reception" "0: Read answer not received,1: Read answer received" bitfld.long 0x4 4.--6. "TID,Transaction ID of transmitted frame" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "ACKR,Acknowledge Received" "0: Acknowledge not received,1: Acknowledge received" bitfld.long 0x4 2. "CB,Channel Busy" "0: Channel free,1: Channel busy" group.long 0xC++0x7 line.long 0x0 "CIR0,SIPI Channel Interrupt Register" bitfld.long 0x0 5. "WAIE,Write Acknowledge Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 4. "RAIE,Read Answer Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x0 3. "TCIE,Trigger Command Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 2. "TOIE,Timeout Error Interrupt Enabled" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x0 1. "TIDIE,Transaction ID Error Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 0. "ACKIE,Acknowledge Error Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" line.long 0x4 "CTOR0,SIPI Channel Timeout Register" hexmask.long.byte 0x4 0.--7. 1. "TOR,Timeout value for transmitted requests. Timeout counter runs on the prescaled peripheral clock. Prescaler is defined by SIPI_MCR[PRSCLR]. These bits can only be written by software in initialization mode SIPI_MCR[INIT]=1." rgroup.long 0x14++0x3 line.long 0x0 "CCRC0,SIPI Channel CRC Register" hexmask.long.word 0x0 16.--31. 1. "CRCI,Reflects received CRC value at initiator" hexmask.long.word 0x0 0.--15. 1. "CRCT,Reflects received CRC value at target" group.long 0x18++0xF line.long 0x0 "CAR0,SIPI Channel Address Register" hexmask.long 0x0 0.--31. 1. "CAR,These bits contain the address of the target node." line.long 0x4 "CDR0,SIPI Channel Data Register" hexmask.long 0x4 0.--31. 1. "CDR,Data register bits" line.long 0x8 "CCR1,SIPI Channel Control Register" bitfld.long 0x8 16. "TC,Send Trigger Command" "0: Trigger command not sent,1: Trigger command sent" bitfld.long 0x8 6.--7. "WL,Word Length Transfer" "0: 8-bit,1: 16-bit,2: 32-bit,3: not used" newline bitfld.long 0x8 5. "CHEN,Channel Enable" "0: Channel is disabled,1: Channel is enabled" bitfld.long 0x8 4. "ST,Streaming Transfer" "0: Streaming transfer is disabled,1: Streaming transfer is enabled" newline bitfld.long 0x8 3. "IDT,ID Read Request Transfer" "0: ID read request not sent,1: ID read request sent" bitfld.long 0x8 2. "RRT,Read Request Transfer" "0: Read request will not be sent,1: Read request transfer by the initiator. This bit.." newline bitfld.long 0x8 1. "WRT,Write Request Transfer" "0: No write request will be sent,1: Write request transfer by the initiator. This.." bitfld.long 0x8 0. "DEN,DMA Enable. When enabling DMA mode this bit should be set by software. It will then be cleared by hardware after one major loop has completed." "0: Channel will be used for bus interface access,1: Channel will be used for DMA access" line.long 0xC "CSR1,SIPI Channel Status Register" bitfld.long 0xC 7. "RAR,Read Answer Reception" "0: Read answer not received,1: Read answer received" bitfld.long 0xC 4.--6. "TID,Transaction ID of transmitted frame" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 3. "ACKR,Acknowledge Received" "0: Acknowledge not received,1: Acknowledge received" bitfld.long 0xC 2. "CB,Channel Busy" "0: Channel free,1: Channel busy" group.long 0x2C++0x7 line.long 0x0 "CIR1,SIPI Channel Interrupt Register" bitfld.long 0x0 5. "WAIE,Write Acknowledge Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 4. "RAIE,Read Answer Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x0 3. "TCIE,Trigger Command Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 2. "TOIE,Timeout Error Interrupt Enabled" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x0 1. "TIDIE,Transaction ID Error Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 0. "ACKIE,Acknowledge Error Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" line.long 0x4 "CTOR1,SIPI Channel Timeout Register" hexmask.long.byte 0x4 0.--7. 1. "TOR,Timeout value for transmitted requests. Timeout counter runs on the prescaled peripheral clock. Prescaler is defined by SIPI_MCR[PRSCLR]. These bits can only be written by software in initialization mode SIPI_MCR[INIT]=1." rgroup.long 0x34++0x3 line.long 0x0 "CCRC1,SIPI Channel CRC Register" hexmask.long.word 0x0 16.--31. 1. "CRCI,Reflects received CRC value at initiator" hexmask.long.word 0x0 0.--15. 1. "CRCT,Reflects received CRC value at target" group.long 0x38++0xF line.long 0x0 "CAR1,SIPI Channel Address Register" hexmask.long 0x0 0.--31. 1. "CAR,These bits contain the address of the target node." line.long 0x4 "CDR1,SIPI Channel Data Register" hexmask.long 0x4 0.--31. 1. "CDR,Data register bits" line.long 0x8 "CCR2,SIPI Channel Control Register" bitfld.long 0x8 16. "TC,Send Trigger Command" "0: Trigger command not sent,1: Trigger command sent" bitfld.long 0x8 6.--7. "WL,Word Length Transfer" "0: 8-bit,1: 16-bit,2: 32-bit,3: not used" newline bitfld.long 0x8 5. "CHEN,Channel Enable" "0: Channel is disabled,1: Channel is enabled" bitfld.long 0x8 4. "ST,Streaming Transfer" "0: Streaming transfer is disabled,1: Streaming transfer is enabled" newline bitfld.long 0x8 3. "IDT,ID Read Request Transfer" "0: ID read request not sent,1: ID read request sent" bitfld.long 0x8 2. "RRT,Read Request Transfer" "0: Read request will not be sent,1: Read request transfer by the initiator. This bit.." newline bitfld.long 0x8 1. "WRT,Write Request Transfer" "0: No write request will be sent,1: Write request transfer by the initiator. This.." bitfld.long 0x8 0. "DEN,DMA Enable. When enabling DMA mode this bit should be set by software. It will then be cleared by hardware after one major loop has completed." "0: Channel will be used for bus interface access,1: Channel will be used for DMA access" line.long 0xC "CSR2,SIPI Channel Status Register" bitfld.long 0xC 7. "RAR,Read Answer Reception" "0: Read answer not received,1: Read answer received" bitfld.long 0xC 4.--6. "TID,Transaction ID of transmitted frame" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 3. "ACKR,Acknowledge Received" "0: Acknowledge not received,1: Acknowledge received" bitfld.long 0xC 2. "CB,Channel Busy" "0: Channel free,1: Channel busy" group.long 0x4C++0x7 line.long 0x0 "CIR2,SIPI Channel Interrupt Register" bitfld.long 0x0 5. "WAIE,Write Acknowledge Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 4. "RAIE,Read Answer Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x0 3. "TCIE,Trigger Command Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 2. "TOIE,Timeout Error Interrupt Enabled" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x0 1. "TIDIE,Transaction ID Error Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 0. "ACKIE,Acknowledge Error Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" line.long 0x4 "CTOR2,SIPI Channel Timeout Register" hexmask.long.byte 0x4 0.--7. 1. "TOR,Timeout value for transmitted requests. Timeout counter runs on the prescaled peripheral clock. Prescaler is defined by SIPI_MCR[PRSCLR]. These bits can only be written by software in initialization mode SIPI_MCR[INIT]=1." rgroup.long 0x54++0x3 line.long 0x0 "CCRC2,SIPI Channel CRC Register" hexmask.long.word 0x0 16.--31. 1. "CRCI,Reflects received CRC value at initiator" hexmask.long.word 0x0 0.--15. 1. "CRCT,Reflects received CRC value at target" group.long 0x58++0x2B line.long 0x0 "CAR2,SIPI Channel Address Register" hexmask.long 0x0 0.--31. 1. "CAR,These bits contain the address of the target node." line.long 0x4 "CDR20,SIPI Channel Data Register" hexmask.long 0x4 0.--31. 1. "CDR,Data register bits" line.long 0x8 "CDR21,SIPI Channel Data Register" hexmask.long 0x8 0.--31. 1. "CDR,Data register bits" line.long 0xC "CDR22,SIPI Channel Data Register" hexmask.long 0xC 0.--31. 1. "CDR,Data register bits" line.long 0x10 "CDR23,SIPI Channel Data Register" hexmask.long 0x10 0.--31. 1. "CDR,Data register bits" line.long 0x14 "CDR24,SIPI Channel Data Register" hexmask.long 0x14 0.--31. 1. "CDR,Data register bits" line.long 0x18 "CDR25,SIPI Channel Data Register" hexmask.long 0x18 0.--31. 1. "CDR,Data register bits" line.long 0x1C "CDR26,SIPI Channel Data Register" hexmask.long 0x1C 0.--31. 1. "CDR,Data register bits" line.long 0x20 "CDR27,SIPI Channel Data Register" hexmask.long 0x20 0.--31. 1. "CDR,Data register bits" line.long 0x24 "CCR3,SIPI Channel Control Register" bitfld.long 0x24 16. "TC,Send Trigger Command" "0: Trigger command not sent,1: Trigger command sent" bitfld.long 0x24 6.--7. "WL,Word Length Transfer" "0: 8-bit,1: 16-bit,2: 32-bit,3: not used" newline bitfld.long 0x24 5. "CHEN,Channel Enable" "0: Channel is disabled,1: Channel is enabled" bitfld.long 0x24 4. "ST,Streaming Transfer" "0: Streaming transfer is disabled,1: Streaming transfer is enabled" newline bitfld.long 0x24 3. "IDT,ID Read Request Transfer" "0: ID read request not sent,1: ID read request sent" bitfld.long 0x24 2. "RRT,Read Request Transfer" "0: Read request will not be sent,1: Read request transfer by the initiator. This bit.." newline bitfld.long 0x24 1. "WRT,Write Request Transfer" "0: No write request will be sent,1: Write request transfer by the initiator. This.." bitfld.long 0x24 0. "DEN,DMA Enable. When enabling DMA mode this bit should be set by software. It will then be cleared by hardware after one major loop has completed." "0: Channel will be used for bus interface access,1: Channel will be used for DMA access" line.long 0x28 "CSR3,SIPI Channel Status Register" bitfld.long 0x28 7. "RAR,Read Answer Reception" "0: Read answer not received,1: Read answer received" bitfld.long 0x28 4.--6. "TID,Transaction ID of transmitted frame" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 3. "ACKR,Acknowledge Received" "0: Acknowledge not received,1: Acknowledge received" bitfld.long 0x28 2. "CB,Channel Busy" "0: Channel free,1: Channel busy" group.long 0x88++0x7 line.long 0x0 "CIR3,SIPI Channel Interrupt Register" bitfld.long 0x0 5. "WAIE,Write Acknowledge Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 4. "RAIE,Read Answer Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x0 3. "TCIE,Trigger Command Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 2. "TOIE,Timeout Error Interrupt Enabled" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x0 1. "TIDIE,Transaction ID Error Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 0. "ACKIE,Acknowledge Error Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" line.long 0x4 "CTOR3,SIPI Channel Timeout Register" hexmask.long.byte 0x4 0.--7. 1. "TOR,Timeout value for transmitted requests. Timeout counter runs on the prescaled peripheral clock. Prescaler is defined by SIPI_MCR[PRSCLR]. These bits can only be written by software in initialization mode SIPI_MCR[INIT]=1." rgroup.long 0x90++0x3 line.long 0x0 "CCRC3,SIPI Channel CRC Register" hexmask.long.word 0x0 16.--31. 1. "CRCI,Reflects received CRC value at initiator" hexmask.long.word 0x0 0.--15. 1. "CRCT,Reflects received CRC value at target" group.long 0x94++0x1F line.long 0x0 "CAR3,SIPI Channel Address Register" hexmask.long 0x0 0.--31. 1. "CAR,These bits contain the address of the target node." line.long 0x4 "CDR3,SIPI Channel Data Register" hexmask.long 0x4 0.--31. 1. "CDR,Data register bits" line.long 0x8 "MCR,SIPI Module Configuration Register" bitfld.long 0x8 31. "FRZ,Freeze Enable" "0: Not enabled to enter Freeze mode,1: Enabled to enter Freeze mode" bitfld.long 0x8 29. "HALT,Halt Mode Enable" "0: No Freeze mode request,1: Enters Freeze mode if FRZ bit is asserted" newline hexmask.long.word 0x8 16.--26. 1. "PRSCLR,These bits should be programmed by software in initialization mode SIPI_MCR[INIT]=1 writes during other times are ignored. The timeout counter runs on the prescaled system clock. Default value is 64 (0x040). The allowed programmable values are:" bitfld.long 0x8 14.--15. "AID,Address Increment/Decrement" "0: No change. address stays same,1: Address increments by 4,2: Address decrements by 4.,?" newline bitfld.long 0x8 10. "CRCIE,CRC Error Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x8 9. "MCRIE,Max Count Reached Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x8 4. "CHNSB,Channel coding select bit" "0,1" bitfld.long 0x8 3. "TEN,Target Enable" "0,1" newline bitfld.long 0x8 2. "INIT,Setting this bit puts the module in initialization mode. This bit should be cleared by software. Most register bits are configured using this bit. The SIPI_MCR[MOEN] bit needs to be set first and then the INIT bit can be set and both bits cannot be.." "0: Normal Mode,1: Initialization Mode" bitfld.long 0x8 1. "MOEN,Module Enable" "0,1" newline bitfld.long 0x8 0. "SR,Soft Reset" "0,1" line.long 0xC "SR,SIPI Status Register" bitfld.long 0xC 31. "FRZACK,Freeze Mode Acknowledge" "0: SIPI not in Freeze mode,1: SIPI in Freeze mode" bitfld.long 0xC 30. "LPMACK,Low Power Mode Acknowledge" "0: SIPI not in any low power modes,1: SIPI is in Disable mode" newline bitfld.long 0xC 10. "GCRCE,Global CRC Error Bit" "0: No CRC error,1: CRC error occurred" bitfld.long 0xC 9. "MCR,Maximum Count Reached" "0,1" newline hexmask.long.byte 0xC 4.--7. 1. "TE,Trigger Event on Respective Channels" hexmask.long.byte 0xC 0.--3. 1. "STATE,These bits reflect the transmit state machine status. They can be polled for determination of state machine status." line.long 0x10 "MAXCR,SIPI Max Count Register" hexmask.long 0x10 2.--31. 1. "MXCNT,This field contains the maximum address count value at the target node. It should be programmed via direct write request through the initiator." line.long 0x14 "ARR,SIPI Address Reload Register" hexmask.long 0x14 2.--31. 1. "ADRLD,Contains the reload value for the address counter at the target node. It should be configured by direct write request from the initiator." line.long 0x18 "ACR,SIPI Address Count Register" hexmask.long 0x18 2.--31. 1. "ADCNT,Reflects the count value of address counter at target node. It should be configured by direct write request from the initiator. This register can be read/written by software anytime. At the end of the streaming operation SIPI_ACR will point to the.." line.long 0x1C "ERR,SIPI Channel Error Register" bitfld.long 0x1C 26. "TOE3,Timeout Error for Channel 3" "0: Timeout error has not occurred,1: Timeout error has occurred" bitfld.long 0x1C 25. "TIDE3,Transaction ID Error for Channel 3" "0: Received transaction ID matched with the stored ID,1: Received transaction ID did not match with the.." newline bitfld.long 0x1C 24. "ACKE3,Acknowledge Error for Channel 3" "0: Acknowledge received is correct.,1: Acknowledge received is not correct." bitfld.long 0x1C 18. "TOE2,Timeout Error for Channel 2" "0: Timeout error has not occurred,1: Timeout error has occurred" newline bitfld.long 0x1C 17. "TIDE2,Transaction ID Error for Channel 2" "0: Received transaction ID matched with the stored ID,1: Received transaction ID didn't match with the.." bitfld.long 0x1C 16. "ACKE2,Acknowledge Error for Channel 2" "0: Acknowledge received is correct.,1: Acknowledge received is not correct." newline bitfld.long 0x1C 10. "TOE1,Timeout Error for Channel 1" "0: Timeout error has not occurred,1: Timeout error has occurred" bitfld.long 0x1C 9. "TIDE1,Transaction ID Error for Channel 1" "0: Received transaction ID matched with the stored ID,1: Received transaction ID didn't match with the.." newline bitfld.long 0x1C 8. "ACKE1,Acknowledge Error for Channel 1" "0: Acknowledge received is correct.,1: Acknowledge received is not correct." bitfld.long 0x1C 2. "TOE0,Timeout Error for Channel 0" "0: Timeout error has not occurred,1: Timeout error has occurred" newline bitfld.long 0x1C 1. "TIDE0,Transaction ID Error for Channel 0" "0: Received transaction ID matched with the stored ID,1: Received transaction ID didn't match with the.." bitfld.long 0x1C 0. "ACKE0,Acknowledge Error for Channel 0" "0: Acknowledge received is correct.,1: Acknowledge received is not correct." tree.end tree "SIPI_1" base ad:0x70AAC000 group.long 0x0++0x7 line.long 0x0 "CCR0,SIPI Channel Control Register" bitfld.long 0x0 16. "TC,Send Trigger Command" "0: Trigger command not sent,1: Trigger command sent" bitfld.long 0x0 6.--7. "WL,Word Length Transfer" "0: 8-bit,1: 16-bit,2: 32-bit,3: not used" newline bitfld.long 0x0 5. "CHEN,Channel Enable" "0: Channel is disabled,1: Channel is enabled" bitfld.long 0x0 4. "ST,Streaming Transfer" "0: Streaming transfer is disabled,1: Streaming transfer is enabled" newline bitfld.long 0x0 3. "IDT,ID Read Request Transfer" "0: ID read request not sent,1: ID read request sent" bitfld.long 0x0 2. "RRT,Read Request Transfer" "0: Read request will not be sent,1: Read request transfer by the initiator. This bit.." newline bitfld.long 0x0 1. "WRT,Write Request Transfer" "0: No write request will be sent,1: Write request transfer by the initiator. This.." bitfld.long 0x0 0. "DEN,DMA Enable. When enabling DMA mode this bit should be set by software. It will then be cleared by hardware after one major loop has completed." "0: Channel will be used for bus interface access,1: Channel will be used for DMA access" line.long 0x4 "CSR0,SIPI Channel Status Register" bitfld.long 0x4 7. "RAR,Read Answer Reception" "0: Read answer not received,1: Read answer received" bitfld.long 0x4 4.--6. "TID,Transaction ID of transmitted frame" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "ACKR,Acknowledge Received" "0: Acknowledge not received,1: Acknowledge received" bitfld.long 0x4 2. "CB,Channel Busy" "0: Channel free,1: Channel busy" group.long 0xC++0x7 line.long 0x0 "CIR0,SIPI Channel Interrupt Register" bitfld.long 0x0 5. "WAIE,Write Acknowledge Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 4. "RAIE,Read Answer Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x0 3. "TCIE,Trigger Command Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 2. "TOIE,Timeout Error Interrupt Enabled" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x0 1. "TIDIE,Transaction ID Error Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 0. "ACKIE,Acknowledge Error Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" line.long 0x4 "CTOR0,SIPI Channel Timeout Register" hexmask.long.byte 0x4 0.--7. 1. "TOR,Timeout value for transmitted requests. Timeout counter runs on the prescaled peripheral clock. Prescaler is defined by SIPI_MCR[PRSCLR]. These bits can only be written by software in initialization mode SIPI_MCR[INIT]=1." rgroup.long 0x14++0x3 line.long 0x0 "CCRC0,SIPI Channel CRC Register" hexmask.long.word 0x0 16.--31. 1. "CRCI,Reflects received CRC value at initiator" hexmask.long.word 0x0 0.--15. 1. "CRCT,Reflects received CRC value at target" group.long 0x18++0xF line.long 0x0 "CAR0,SIPI Channel Address Register" hexmask.long 0x0 0.--31. 1. "CAR,These bits contain the address of the target node." line.long 0x4 "CDR0,SIPI Channel Data Register" hexmask.long 0x4 0.--31. 1. "CDR,Data register bits" line.long 0x8 "CCR1,SIPI Channel Control Register" bitfld.long 0x8 16. "TC,Send Trigger Command" "0: Trigger command not sent,1: Trigger command sent" bitfld.long 0x8 6.--7. "WL,Word Length Transfer" "0: 8-bit,1: 16-bit,2: 32-bit,3: not used" newline bitfld.long 0x8 5. "CHEN,Channel Enable" "0: Channel is disabled,1: Channel is enabled" bitfld.long 0x8 4. "ST,Streaming Transfer" "0: Streaming transfer is disabled,1: Streaming transfer is enabled" newline bitfld.long 0x8 3. "IDT,ID Read Request Transfer" "0: ID read request not sent,1: ID read request sent" bitfld.long 0x8 2. "RRT,Read Request Transfer" "0: Read request will not be sent,1: Read request transfer by the initiator. This bit.." newline bitfld.long 0x8 1. "WRT,Write Request Transfer" "0: No write request will be sent,1: Write request transfer by the initiator. This.." bitfld.long 0x8 0. "DEN,DMA Enable. When enabling DMA mode this bit should be set by software. It will then be cleared by hardware after one major loop has completed." "0: Channel will be used for bus interface access,1: Channel will be used for DMA access" line.long 0xC "CSR1,SIPI Channel Status Register" bitfld.long 0xC 7. "RAR,Read Answer Reception" "0: Read answer not received,1: Read answer received" bitfld.long 0xC 4.--6. "TID,Transaction ID of transmitted frame" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 3. "ACKR,Acknowledge Received" "0: Acknowledge not received,1: Acknowledge received" bitfld.long 0xC 2. "CB,Channel Busy" "0: Channel free,1: Channel busy" group.long 0x2C++0x7 line.long 0x0 "CIR1,SIPI Channel Interrupt Register" bitfld.long 0x0 5. "WAIE,Write Acknowledge Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 4. "RAIE,Read Answer Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x0 3. "TCIE,Trigger Command Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 2. "TOIE,Timeout Error Interrupt Enabled" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x0 1. "TIDIE,Transaction ID Error Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 0. "ACKIE,Acknowledge Error Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" line.long 0x4 "CTOR1,SIPI Channel Timeout Register" hexmask.long.byte 0x4 0.--7. 1. "TOR,Timeout value for transmitted requests. Timeout counter runs on the prescaled peripheral clock. Prescaler is defined by SIPI_MCR[PRSCLR]. These bits can only be written by software in initialization mode SIPI_MCR[INIT]=1." rgroup.long 0x34++0x3 line.long 0x0 "CCRC1,SIPI Channel CRC Register" hexmask.long.word 0x0 16.--31. 1. "CRCI,Reflects received CRC value at initiator" hexmask.long.word 0x0 0.--15. 1. "CRCT,Reflects received CRC value at target" group.long 0x38++0xF line.long 0x0 "CAR1,SIPI Channel Address Register" hexmask.long 0x0 0.--31. 1. "CAR,These bits contain the address of the target node." line.long 0x4 "CDR1,SIPI Channel Data Register" hexmask.long 0x4 0.--31. 1. "CDR,Data register bits" line.long 0x8 "CCR2,SIPI Channel Control Register" bitfld.long 0x8 16. "TC,Send Trigger Command" "0: Trigger command not sent,1: Trigger command sent" bitfld.long 0x8 6.--7. "WL,Word Length Transfer" "0: 8-bit,1: 16-bit,2: 32-bit,3: not used" newline bitfld.long 0x8 5. "CHEN,Channel Enable" "0: Channel is disabled,1: Channel is enabled" bitfld.long 0x8 4. "ST,Streaming Transfer" "0: Streaming transfer is disabled,1: Streaming transfer is enabled" newline bitfld.long 0x8 3. "IDT,ID Read Request Transfer" "0: ID read request not sent,1: ID read request sent" bitfld.long 0x8 2. "RRT,Read Request Transfer" "0: Read request will not be sent,1: Read request transfer by the initiator. This bit.." newline bitfld.long 0x8 1. "WRT,Write Request Transfer" "0: No write request will be sent,1: Write request transfer by the initiator. This.." bitfld.long 0x8 0. "DEN,DMA Enable. When enabling DMA mode this bit should be set by software. It will then be cleared by hardware after one major loop has completed." "0: Channel will be used for bus interface access,1: Channel will be used for DMA access" line.long 0xC "CSR2,SIPI Channel Status Register" bitfld.long 0xC 7. "RAR,Read Answer Reception" "0: Read answer not received,1: Read answer received" bitfld.long 0xC 4.--6. "TID,Transaction ID of transmitted frame" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 3. "ACKR,Acknowledge Received" "0: Acknowledge not received,1: Acknowledge received" bitfld.long 0xC 2. "CB,Channel Busy" "0: Channel free,1: Channel busy" group.long 0x4C++0x7 line.long 0x0 "CIR2,SIPI Channel Interrupt Register" bitfld.long 0x0 5. "WAIE,Write Acknowledge Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 4. "RAIE,Read Answer Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x0 3. "TCIE,Trigger Command Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 2. "TOIE,Timeout Error Interrupt Enabled" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x0 1. "TIDIE,Transaction ID Error Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 0. "ACKIE,Acknowledge Error Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" line.long 0x4 "CTOR2,SIPI Channel Timeout Register" hexmask.long.byte 0x4 0.--7. 1. "TOR,Timeout value for transmitted requests. Timeout counter runs on the prescaled peripheral clock. Prescaler is defined by SIPI_MCR[PRSCLR]. These bits can only be written by software in initialization mode SIPI_MCR[INIT]=1." rgroup.long 0x54++0x3 line.long 0x0 "CCRC2,SIPI Channel CRC Register" hexmask.long.word 0x0 16.--31. 1. "CRCI,Reflects received CRC value at initiator" hexmask.long.word 0x0 0.--15. 1. "CRCT,Reflects received CRC value at target" group.long 0x58++0x2B line.long 0x0 "CAR2,SIPI Channel Address Register" hexmask.long 0x0 0.--31. 1. "CAR,These bits contain the address of the target node." line.long 0x4 "CDR20,SIPI Channel Data Register" hexmask.long 0x4 0.--31. 1. "CDR,Data register bits" line.long 0x8 "CDR21,SIPI Channel Data Register" hexmask.long 0x8 0.--31. 1. "CDR,Data register bits" line.long 0xC "CDR22,SIPI Channel Data Register" hexmask.long 0xC 0.--31. 1. "CDR,Data register bits" line.long 0x10 "CDR23,SIPI Channel Data Register" hexmask.long 0x10 0.--31. 1. "CDR,Data register bits" line.long 0x14 "CDR24,SIPI Channel Data Register" hexmask.long 0x14 0.--31. 1. "CDR,Data register bits" line.long 0x18 "CDR25,SIPI Channel Data Register" hexmask.long 0x18 0.--31. 1. "CDR,Data register bits" line.long 0x1C "CDR26,SIPI Channel Data Register" hexmask.long 0x1C 0.--31. 1. "CDR,Data register bits" line.long 0x20 "CDR27,SIPI Channel Data Register" hexmask.long 0x20 0.--31. 1. "CDR,Data register bits" line.long 0x24 "CCR3,SIPI Channel Control Register" bitfld.long 0x24 16. "TC,Send Trigger Command" "0: Trigger command not sent,1: Trigger command sent" bitfld.long 0x24 6.--7. "WL,Word Length Transfer" "0: 8-bit,1: 16-bit,2: 32-bit,3: not used" newline bitfld.long 0x24 5. "CHEN,Channel Enable" "0: Channel is disabled,1: Channel is enabled" bitfld.long 0x24 4. "ST,Streaming Transfer" "0: Streaming transfer is disabled,1: Streaming transfer is enabled" newline bitfld.long 0x24 3. "IDT,ID Read Request Transfer" "0: ID read request not sent,1: ID read request sent" bitfld.long 0x24 2. "RRT,Read Request Transfer" "0: Read request will not be sent,1: Read request transfer by the initiator. This bit.." newline bitfld.long 0x24 1. "WRT,Write Request Transfer" "0: No write request will be sent,1: Write request transfer by the initiator. This.." bitfld.long 0x24 0. "DEN,DMA Enable. When enabling DMA mode this bit should be set by software. It will then be cleared by hardware after one major loop has completed." "0: Channel will be used for bus interface access,1: Channel will be used for DMA access" line.long 0x28 "CSR3,SIPI Channel Status Register" bitfld.long 0x28 7. "RAR,Read Answer Reception" "0: Read answer not received,1: Read answer received" bitfld.long 0x28 4.--6. "TID,Transaction ID of transmitted frame" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 3. "ACKR,Acknowledge Received" "0: Acknowledge not received,1: Acknowledge received" bitfld.long 0x28 2. "CB,Channel Busy" "0: Channel free,1: Channel busy" group.long 0x88++0x7 line.long 0x0 "CIR3,SIPI Channel Interrupt Register" bitfld.long 0x0 5. "WAIE,Write Acknowledge Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 4. "RAIE,Read Answer Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x0 3. "TCIE,Trigger Command Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 2. "TOIE,Timeout Error Interrupt Enabled" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x0 1. "TIDIE,Transaction ID Error Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x0 0. "ACKIE,Acknowledge Error Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" line.long 0x4 "CTOR3,SIPI Channel Timeout Register" hexmask.long.byte 0x4 0.--7. 1. "TOR,Timeout value for transmitted requests. Timeout counter runs on the prescaled peripheral clock. Prescaler is defined by SIPI_MCR[PRSCLR]. These bits can only be written by software in initialization mode SIPI_MCR[INIT]=1." rgroup.long 0x90++0x3 line.long 0x0 "CCRC3,SIPI Channel CRC Register" hexmask.long.word 0x0 16.--31. 1. "CRCI,Reflects received CRC value at initiator" hexmask.long.word 0x0 0.--15. 1. "CRCT,Reflects received CRC value at target" group.long 0x94++0x1F line.long 0x0 "CAR3,SIPI Channel Address Register" hexmask.long 0x0 0.--31. 1. "CAR,These bits contain the address of the target node." line.long 0x4 "CDR3,SIPI Channel Data Register" hexmask.long 0x4 0.--31. 1. "CDR,Data register bits" line.long 0x8 "MCR,SIPI Module Configuration Register" bitfld.long 0x8 31. "FRZ,Freeze Enable" "0: Not enabled to enter Freeze mode,1: Enabled to enter Freeze mode" bitfld.long 0x8 29. "HALT,Halt Mode Enable" "0: No Freeze mode request,1: Enters Freeze mode if FRZ bit is asserted" newline hexmask.long.word 0x8 16.--26. 1. "PRSCLR,These bits should be programmed by software in initialization mode SIPI_MCR[INIT]=1 writes during other times are ignored. The timeout counter runs on the prescaled system clock. Default value is 64 (0x040). The allowed programmable values are:" bitfld.long 0x8 14.--15. "AID,Address Increment/Decrement" "0: No change. address stays same,1: Address increments by 4,2: Address decrements by 4.,?" newline bitfld.long 0x8 10. "CRCIE,CRC Error Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x8 9. "MCRIE,Max Count Reached Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x8 4. "CHNSB,Channel coding select bit" "0,1" bitfld.long 0x8 3. "TEN,Target Enable" "0,1" newline bitfld.long 0x8 2. "INIT,Setting this bit puts the module in initialization mode. This bit should be cleared by software. Most register bits are configured using this bit. The SIPI_MCR[MOEN] bit needs to be set first and then the INIT bit can be set and both bits cannot be.." "0: Normal Mode,1: Initialization Mode" bitfld.long 0x8 1. "MOEN,Module Enable" "0,1" newline bitfld.long 0x8 0. "SR,Soft Reset" "0,1" line.long 0xC "SR,SIPI Status Register" bitfld.long 0xC 31. "FRZACK,Freeze Mode Acknowledge" "0: SIPI not in Freeze mode,1: SIPI in Freeze mode" bitfld.long 0xC 30. "LPMACK,Low Power Mode Acknowledge" "0: SIPI not in any low power modes,1: SIPI is in Disable mode" newline bitfld.long 0xC 10. "GCRCE,Global CRC Error Bit" "0: No CRC error,1: CRC error occurred" bitfld.long 0xC 9. "MCR,Maximum Count Reached" "0,1" newline hexmask.long.byte 0xC 4.--7. 1. "TE,Trigger Event on Respective Channels" hexmask.long.byte 0xC 0.--3. 1. "STATE,These bits reflect the transmit state machine status. They can be polled for determination of state machine status." line.long 0x10 "MAXCR,SIPI Max Count Register" hexmask.long 0x10 2.--31. 1. "MXCNT,This field contains the maximum address count value at the target node. It should be programmed via direct write request through the initiator." line.long 0x14 "ARR,SIPI Address Reload Register" hexmask.long 0x14 2.--31. 1. "ADRLD,Contains the reload value for the address counter at the target node. It should be configured by direct write request from the initiator." line.long 0x18 "ACR,SIPI Address Count Register" hexmask.long 0x18 2.--31. 1. "ADCNT,Reflects the count value of address counter at target node. It should be configured by direct write request from the initiator. This register can be read/written by software anytime. At the end of the streaming operation SIPI_ACR will point to the.." line.long 0x1C "ERR,SIPI Channel Error Register" bitfld.long 0x1C 26. "TOE3,Timeout Error for Channel 3" "0: Timeout error has not occurred,1: Timeout error has occurred" bitfld.long 0x1C 25. "TIDE3,Transaction ID Error for Channel 3" "0: Received transaction ID matched with the stored ID,1: Received transaction ID did not match with the.." newline bitfld.long 0x1C 24. "ACKE3,Acknowledge Error for Channel 3" "0: Acknowledge received is correct.,1: Acknowledge received is not correct." bitfld.long 0x1C 18. "TOE2,Timeout Error for Channel 2" "0: Timeout error has not occurred,1: Timeout error has occurred" newline bitfld.long 0x1C 17. "TIDE2,Transaction ID Error for Channel 2" "0: Received transaction ID matched with the stored ID,1: Received transaction ID didn't match with the.." bitfld.long 0x1C 16. "ACKE2,Acknowledge Error for Channel 2" "0: Acknowledge received is correct.,1: Acknowledge received is not correct." newline bitfld.long 0x1C 10. "TOE1,Timeout Error for Channel 1" "0: Timeout error has not occurred,1: Timeout error has occurred" bitfld.long 0x1C 9. "TIDE1,Transaction ID Error for Channel 1" "0: Received transaction ID matched with the stored ID,1: Received transaction ID didn't match with the.." newline bitfld.long 0x1C 8. "ACKE1,Acknowledge Error for Channel 1" "0: Acknowledge received is correct.,1: Acknowledge received is not correct." bitfld.long 0x1C 2. "TOE0,Timeout Error for Channel 0" "0: Timeout error has not occurred,1: Timeout error has occurred" newline bitfld.long 0x1C 1. "TIDE0,Transaction ID Error for Channel 0" "0: Received transaction ID matched with the stored ID,1: Received transaction ID didn't match with the.." bitfld.long 0x1C 0. "ACKE0,Acknowledge Error for Channel 0" "0: Acknowledge received is correct.,1: Acknowledge received is not correct." tree.end tree.end tree "SIUL2 (System Integration Unit Lite2)" base ad:0x0 tree "SIUL2_0" base ad:0x71168000 rgroup.long 0x4++0x7 line.long 0x0 "MIDR1,SIUL2 MCU ID register 1" hexmask.long.word 0x0 16.--31. 1. "PARTNUM,MCU Part Number" bitfld.long 0x0 15. "ED,Emulation Device" "0,1" newline hexmask.long.byte 0x0 10.--14. 1. "PKG,Package Settings" bitfld.long 0x0 8.--9. "PKG_VAR,Package Variant" "0,1,2,3" newline hexmask.long.byte 0x0 4.--7. 1. "MAJOR_MASK,Major Mask revision" hexmask.long.byte 0x0 0.--3. 1. "MINOR_MASK,Minor Mask revision" line.long 0x4 "MIDR2,SIUL2 MCU ID register 2" bitfld.long 0x4 31. "SF,Manufacturer" "0,1" hexmask.long.byte 0x4 23.--30. 1. "NVM_SIZE,NVM memory size" newline hexmask.long.byte 0x4 8.--15. 1. "FAMILYNUM,ASCII character in MCU part number" group.long 0x10++0x3 line.long 0x0 "DISR0,SIUL2 DMA/interrupt status flag register 0" bitfld.long 0x0 15. "EIF15,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." bitfld.long 0x0 14. "EIF14,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." newline bitfld.long 0x0 13. "EIF13,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." bitfld.long 0x0 12. "EIF12,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." newline bitfld.long 0x0 11. "EIF11,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." bitfld.long 0x0 10. "EIF10,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." newline bitfld.long 0x0 9. "EIF9,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." bitfld.long 0x0 8. "EIF8,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." newline bitfld.long 0x0 7. "EIF7,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." bitfld.long 0x0 6. "EIF6,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." newline bitfld.long 0x0 5. "EIF5,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." bitfld.long 0x0 4. "EIF4,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." newline bitfld.long 0x0 3. "EIF3,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." bitfld.long 0x0 2. "EIF2,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." newline bitfld.long 0x0 1. "EIF1,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." bitfld.long 0x0 0. "EIF0,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." group.long 0x18++0x3 line.long 0x0 "DIRER0,SIUL2 DMA/interrupt request enable register 0" bitfld.long 0x0 15. "EIRE15,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." bitfld.long 0x0 14. "EIRE14,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." newline bitfld.long 0x0 13. "EIRE13,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." bitfld.long 0x0 12. "EIRE12,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." newline bitfld.long 0x0 11. "EIRE11,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." bitfld.long 0x0 10. "EIRE10,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." newline bitfld.long 0x0 9. "EIRE9,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." bitfld.long 0x0 8. "EIRE8,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." newline bitfld.long 0x0 7. "EIRE7,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." bitfld.long 0x0 6. "EIRE6,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." newline bitfld.long 0x0 5. "EIRE5,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." bitfld.long 0x0 4. "EIRE4,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." newline bitfld.long 0x0 3. "EIRE3,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." bitfld.long 0x0 2. "EIRE2,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." newline bitfld.long 0x0 1. "EIRE1,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." bitfld.long 0x0 0. "EIRE0,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." group.long 0x20++0x3 line.long 0x0 "DIRSR0,SIUL2 DMA/interrupt request select register 0" bitfld.long 0x0 15. "DIRS15,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" bitfld.long 0x0 14. "DIRS14,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" newline bitfld.long 0x0 13. "DIRS13,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" bitfld.long 0x0 12. "DIRS12,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" newline bitfld.long 0x0 11. "DIRS11,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" bitfld.long 0x0 10. "DIRS10,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" newline bitfld.long 0x0 9. "DIRS9,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" bitfld.long 0x0 8. "DIRS8,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" newline bitfld.long 0x0 7. "DIRS7,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" bitfld.long 0x0 6. "DIRS6,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" newline bitfld.long 0x0 5. "DIRS5,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" bitfld.long 0x0 4. "DIRS4,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" newline bitfld.long 0x0 3. "DIRS3,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" bitfld.long 0x0 2. "DIRS2,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" newline bitfld.long 0x0 1. "DIRS1,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" bitfld.long 0x0 0. "DIRS0,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" group.long 0x28++0x3 line.long 0x0 "IREER0,SIUL2 interrupt rising-edge event enable register 0" bitfld.long 0x0 15. "IREE15,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 14. "IREE14,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 13. "IREE13,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 12. "IREE12,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 11. "IREE11,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 10. "IREE10,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 9. "IREE9,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 8. "IREE8,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 7. "IREE7,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 6. "IREE6,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 5. "IREE5,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 4. "IREE4,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 3. "IREE3,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 2. "IREE2,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 1. "IREE1,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 0. "IREE0,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." group.long 0x30++0x3 line.long 0x0 "IFEER0,SIUL2 interrupt falling-edge event enable register 0" bitfld.long 0x0 15. "IFEE15,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x0 14. "IFEE14,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x0 13. "IFEE13,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x0 12. "IFEE12,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x0 11. "IFEE11,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x0 10. "IFEE10,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x0 9. "IFEE9,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x0 8. "IFEE8,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x0 7. "IFEE7,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x0 6. "IFEE6,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x0 5. "IFEE5,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x0 4. "IFEE4,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x0 3. "IFEE3,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x0 2. "IFEE2,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x0 1. "IFEE1,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x0 0. "IFEE0,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." group.long 0x38++0x3 line.long 0x0 "IFER0,SIUL2 Interrupt filter enable register 0" bitfld.long 0x0 15. "IFE15,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x0 14. "IFE14,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x0 13. "IFE13,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x0 12. "IFE12,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x0 11. "IFE11,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x0 10. "IFE10,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x0 9. "IFE9,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x0 8. "IFE8,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x0 7. "IFE7,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x0 6. "IFE6,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x0 5. "IFE5,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x0 4. "IFE4,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x0 3. "IFE3,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x0 2. "IFE2,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x0 1. "IFE1,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x0 0. "IFE0,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." group.long 0x40++0x3F line.long 0x0 "IFMCR0,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x0 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x4 "IFMCR1,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x4 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x8 "IFMCR2,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x8 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0xC "IFMCR3,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0xC 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x10 "IFMCR4,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x10 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x14 "IFMCR5,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x14 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x18 "IFMCR6,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x18 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x1C "IFMCR7,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x1C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x20 "IFMCR8,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x20 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x24 "IFMCR9,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x24 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x28 "IFMCR10,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x28 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x2C "IFMCR11,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x2C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x30 "IFMCR12,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x30 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x34 "IFMCR13,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x34 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x38 "IFMCR14,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x38 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x3C "IFMCR15,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x3C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" group.long 0xC0++0x3 line.long 0x0 "IFCPR,SIUL2 interrupt filter clock prescaler register" hexmask.long.byte 0x0 0.--3. 1. "IFCP,Interrupt Filter Clock Prescaler setting" group.long 0x100++0x3 line.long 0x0 "SCR0,SIUL2 Soc configuration register 0" bitfld.long 0x0 29. "LVDS0_OPT2,LVDS" "0: Termination register is enabled for LVDS RX when..,1: Termination register is disabled for LVDS RX.." bitfld.long 0x0 28. "LVDS1_OPT2,LVDS" "0: Termination register is enabled for LVDS RX when..,1: Termination register is disabled for LVDS RX.." newline bitfld.long 0x0 26. "LVDS3_OPT2,LVDS" "0: Termination register is enabled for LVDS RX when..,1: Termination register is disabled for LVDS RX.." group.long 0x180++0xF line.long 0x0 "IPFCPR0,SIUL2 input pin filter clock prescaler register 0" bitfld.long 0x0 11. "JEN,Enable jitter injection to increase periodic noise immunity." "0: The pseudo-random clock division feature is..,1: The pseudo-random clock division feature is.." hexmask.long.word 0x0 0.--10. 1. "IPFCP,Input Pin Filter Clock Prescaler setting" line.long 0x4 "IPFCPR1,SIUL2 input pin filter clock prescaler register 1" bitfld.long 0x4 11. "JEN,Enable jitter injection to increase periodic noise immunity." "0: The pseudo-random clock division feature is..,1: The pseudo-random clock division feature is.." hexmask.long.word 0x4 0.--10. 1. "IPFCP,Input Pin Filter Clock Prescaler setting" line.long 0x8 "IPFCPR2,SIUL2 input pin filter clock prescaler register 2" bitfld.long 0x8 11. "JEN,Enable jitter injection to increase periodic noise immunity." "0: The pseudo-random clock division feature is..,1: The pseudo-random clock division feature is.." hexmask.long.word 0x8 0.--10. 1. "IPFCP,Input Pin Filter Clock Prescaler setting" line.long 0xC "IPFCPR3,SIUL2 input pin filter clock prescaler register 3" bitfld.long 0xC 11. "JEN,Enable jitter injection to increase periodic noise immunity." "0: The pseudo-random clock division feature is..,1: The pseudo-random clock division feature is.." hexmask.long.word 0xC 0.--10. 1. "IPFCP,Input Pin Filter Clock Prescaler setting" group.long 0x240++0xFFF line.long 0x0 "MSCR_IO0,SIUL2 I/O pin multiplexed signal configuration register 0" bitfld.long 0x0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x0 0.--7. 1. "SSS,Source Signal Select" line.long 0x4 "MSCR_IO1,SIUL2 I/O pin multiplexed signal configuration register 1" bitfld.long 0x4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4 0.--7. 1. "SSS,Source Signal Select" line.long 0x8 "MSCR_IO2,SIUL2 I/O pin multiplexed signal configuration register 2" bitfld.long 0x8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x8 0.--7. 1. "SSS,Source Signal Select" line.long 0xC "MSCR_IO3,SIUL2 I/O pin multiplexed signal configuration register 3" bitfld.long 0xC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xC 0.--7. 1. "SSS,Source Signal Select" line.long 0x10 "MSCR_IO4,SIUL2 I/O pin multiplexed signal configuration register 4" bitfld.long 0x10 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x10 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x10 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x10 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x10 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x10 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x10 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x10 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x10 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x10 0.--7. 1. "SSS,Source Signal Select" line.long 0x14 "MSCR_IO5,SIUL2 I/O pin multiplexed signal configuration register 5" bitfld.long 0x14 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x14 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x14 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x14 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x14 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x14 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x14 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x14 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x14 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x14 0.--7. 1. "SSS,Source Signal Select" line.long 0x18 "MSCR_IO6,SIUL2 I/O pin multiplexed signal configuration register 6" bitfld.long 0x18 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x18 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x18 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x18 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x18 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x18 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x18 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x18 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x18 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x18 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x18 0.--7. 1. "SSS,Source Signal Select" line.long 0x1C "MSCR_IO7,SIUL2 I/O pin multiplexed signal configuration register 7" bitfld.long 0x1C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1C 0.--7. 1. "SSS,Source Signal Select" line.long 0x20 "MSCR_IO8,SIUL2 I/O pin multiplexed signal configuration register 8" bitfld.long 0x20 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x20 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x20 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x20 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x20 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x20 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x20 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x20 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x20 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x20 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x20 0.--7. 1. "SSS,Source Signal Select" line.long 0x24 "MSCR_IO9,SIUL2 I/O pin multiplexed signal configuration register 9" bitfld.long 0x24 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x24 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x24 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x24 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x24 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x24 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x24 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x24 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x24 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x24 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x24 0.--7. 1. "SSS,Source Signal Select" line.long 0x28 "MSCR_IO10,SIUL2 I/O pin multiplexed signal configuration register 10" bitfld.long 0x28 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x28 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x28 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x28 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x28 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x28 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x28 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x28 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x28 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x28 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x28 0.--7. 1. "SSS,Source Signal Select" line.long 0x2C "MSCR_IO11,SIUL2 I/O pin multiplexed signal configuration register 11" bitfld.long 0x2C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2C 0.--7. 1. "SSS,Source Signal Select" line.long 0x30 "MSCR_IO12,SIUL2 I/O pin multiplexed signal configuration register 12" bitfld.long 0x30 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x30 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x30 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x30 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x30 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x30 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x30 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x30 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x30 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x30 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x30 0.--7. 1. "SSS,Source Signal Select" line.long 0x34 "MSCR_IO13,SIUL2 I/O pin multiplexed signal configuration register 13" bitfld.long 0x34 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x34 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x34 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x34 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x34 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x34 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x34 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x34 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x34 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x34 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x34 0.--7. 1. "SSS,Source Signal Select" line.long 0x38 "MSCR_IO14,SIUL2 I/O pin multiplexed signal configuration register 14" bitfld.long 0x38 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x38 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x38 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x38 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x38 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x38 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x38 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x38 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x38 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x38 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x38 0.--7. 1. "SSS,Source Signal Select" line.long 0x3C "MSCR_IO15,SIUL2 I/O pin multiplexed signal configuration register 15" bitfld.long 0x3C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3C 0.--7. 1. "SSS,Source Signal Select" line.long 0x40 "MSCR_IO16,SIUL2 I/O pin multiplexed signal configuration register 16" bitfld.long 0x40 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x40 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x40 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x40 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x40 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x40 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x40 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x40 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x40 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x40 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x40 0.--7. 1. "SSS,Source Signal Select" line.long 0x44 "MSCR_IO17,SIUL2 I/O pin multiplexed signal configuration register 17" bitfld.long 0x44 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x44 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x44 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x44 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x44 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x44 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x44 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x44 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x44 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x44 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x44 0.--7. 1. "SSS,Source Signal Select" line.long 0x48 "MSCR_IO18,SIUL2 I/O pin multiplexed signal configuration register 18" bitfld.long 0x48 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x48 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x48 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x48 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x48 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x48 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x48 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x48 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x48 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x48 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x48 0.--7. 1. "SSS,Source Signal Select" line.long 0x4C "MSCR_IO19,SIUL2 I/O pin multiplexed signal configuration register 19" bitfld.long 0x4C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4C 0.--7. 1. "SSS,Source Signal Select" line.long 0x50 "MSCR_IO20,SIUL2 I/O pin multiplexed signal configuration register 20" bitfld.long 0x50 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x50 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x50 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x50 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x50 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x50 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x50 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x50 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x50 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x50 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x50 0.--7. 1. "SSS,Source Signal Select" line.long 0x54 "MSCR_IO21,SIUL2 I/O pin multiplexed signal configuration register 21" bitfld.long 0x54 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x54 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x54 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x54 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x54 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x54 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x54 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x54 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x54 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x54 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x54 0.--7. 1. "SSS,Source Signal Select" line.long 0x58 "MSCR_IO22,SIUL2 I/O pin multiplexed signal configuration register 22" bitfld.long 0x58 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x58 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x58 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x58 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x58 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x58 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x58 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x58 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x58 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x58 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x58 0.--7. 1. "SSS,Source Signal Select" line.long 0x5C "MSCR_IO23,SIUL2 I/O pin multiplexed signal configuration register 23" bitfld.long 0x5C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5C 0.--7. 1. "SSS,Source Signal Select" line.long 0x60 "MSCR_IO24,SIUL2 I/O pin multiplexed signal configuration register 24" bitfld.long 0x60 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x60 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x60 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x60 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x60 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x60 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x60 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x60 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x60 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x60 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x60 0.--7. 1. "SSS,Source Signal Select" line.long 0x64 "MSCR_IO25,SIUL2 I/O pin multiplexed signal configuration register 25" bitfld.long 0x64 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x64 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x64 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x64 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x64 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x64 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x64 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x64 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x64 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x64 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x64 0.--7. 1. "SSS,Source Signal Select" line.long 0x68 "MSCR_IO26,SIUL2 I/O pin multiplexed signal configuration register 26" bitfld.long 0x68 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x68 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x68 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x68 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x68 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x68 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x68 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x68 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x68 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x68 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x68 0.--7. 1. "SSS,Source Signal Select" line.long 0x6C "MSCR_IO27,SIUL2 I/O pin multiplexed signal configuration register 27" bitfld.long 0x6C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6C 0.--7. 1. "SSS,Source Signal Select" line.long 0x70 "MSCR_IO28,SIUL2 I/O pin multiplexed signal configuration register 28" bitfld.long 0x70 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x70 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x70 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x70 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x70 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x70 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x70 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x70 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x70 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x70 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x70 0.--7. 1. "SSS,Source Signal Select" line.long 0x74 "MSCR_IO29,SIUL2 I/O pin multiplexed signal configuration register 29" bitfld.long 0x74 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x74 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x74 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x74 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x74 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x74 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x74 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x74 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x74 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x74 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x74 0.--7. 1. "SSS,Source Signal Select" line.long 0x78 "MSCR_IO30,SIUL2 I/O pin multiplexed signal configuration register 30" bitfld.long 0x78 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x78 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x78 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x78 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x78 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x78 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x78 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x78 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x78 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x78 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x78 0.--7. 1. "SSS,Source Signal Select" line.long 0x7C "MSCR_IO31,SIUL2 I/O pin multiplexed signal configuration register 31" bitfld.long 0x7C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7C 0.--7. 1. "SSS,Source Signal Select" line.long 0x80 "MSCR_IO32,SIUL2 I/O pin multiplexed signal configuration register 32" bitfld.long 0x80 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x80 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x80 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x80 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x80 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x80 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x80 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x80 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x80 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x80 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x80 0.--7. 1. "SSS,Source Signal Select" line.long 0x84 "MSCR_IO33,SIUL2 I/O pin multiplexed signal configuration register 33" bitfld.long 0x84 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x84 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x84 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x84 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x84 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x84 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x84 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x84 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x84 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x84 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x84 0.--7. 1. "SSS,Source Signal Select" line.long 0x88 "MSCR_IO34,SIUL2 I/O pin multiplexed signal configuration register 34" bitfld.long 0x88 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x88 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x88 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x88 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x88 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x88 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x88 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x88 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x88 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x88 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x88 0.--7. 1. "SSS,Source Signal Select" line.long 0x8C "MSCR_IO35,SIUL2 I/O pin multiplexed signal configuration register 35" bitfld.long 0x8C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x8C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x8C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x8C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x8C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x8C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x8C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x8C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x8C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x8C 0.--7. 1. "SSS,Source Signal Select" line.long 0x90 "MSCR_IO36,SIUL2 I/O pin multiplexed signal configuration register 36" bitfld.long 0x90 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x90 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x90 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x90 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x90 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x90 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x90 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x90 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x90 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x90 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x90 0.--7. 1. "SSS,Source Signal Select" line.long 0x94 "MSCR_IO37,SIUL2 I/O pin multiplexed signal configuration register 37" bitfld.long 0x94 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x94 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x94 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x94 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x94 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x94 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x94 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x94 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x94 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x94 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x94 0.--7. 1. "SSS,Source Signal Select" line.long 0x98 "MSCR_IO38,SIUL2 I/O pin multiplexed signal configuration register 38" bitfld.long 0x98 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x98 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x98 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x98 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x98 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x98 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x98 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x98 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x98 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x98 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x98 0.--7. 1. "SSS,Source Signal Select" line.long 0x9C "MSCR_IO39,SIUL2 I/O pin multiplexed signal configuration register 39" bitfld.long 0x9C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x9C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x9C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x9C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x9C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x9C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x9C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x9C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x9C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x9C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x9C 0.--7. 1. "SSS,Source Signal Select" line.long 0xA0 "MSCR_IO40,SIUL2 I/O pin multiplexed signal configuration register 40" bitfld.long 0xA0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xA0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xA0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xA0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xA0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xA0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xA0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xA0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xA0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xA0 0.--7. 1. "SSS,Source Signal Select" line.long 0xA4 "MSCR_IO41,SIUL2 I/O pin multiplexed signal configuration register 41" bitfld.long 0xA4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xA4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xA4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xA4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xA4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xA4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xA4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xA4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xA4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xA4 0.--7. 1. "SSS,Source Signal Select" line.long 0xA8 "MSCR_IO42,SIUL2 I/O pin multiplexed signal configuration register 42" bitfld.long 0xA8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xA8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xA8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xA8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xA8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xA8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xA8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xA8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xA8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xA8 0.--7. 1. "SSS,Source Signal Select" line.long 0xAC "MSCR_IO43,SIUL2 I/O pin multiplexed signal configuration register 43" bitfld.long 0xAC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xAC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xAC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xAC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xAC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xAC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xAC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xAC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xAC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xAC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xAC 0.--7. 1. "SSS,Source Signal Select" line.long 0xB0 "MSCR_IO44,SIUL2 I/O pin multiplexed signal configuration register 44" bitfld.long 0xB0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xB0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xB0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xB0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xB0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xB0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xB0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xB0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xB0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xB0 0.--7. 1. "SSS,Source Signal Select" line.long 0xB4 "MSCR_IO45,SIUL2 I/O pin multiplexed signal configuration register 45" bitfld.long 0xB4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xB4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xB4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xB4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xB4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xB4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xB4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xB4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xB4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xB4 0.--7. 1. "SSS,Source Signal Select" line.long 0xB8 "MSCR_IO46,SIUL2 I/O pin multiplexed signal configuration register 46" bitfld.long 0xB8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xB8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xB8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xB8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xB8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xB8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xB8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xB8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xB8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xB8 0.--7. 1. "SSS,Source Signal Select" line.long 0xBC "MSCR_IO47,SIUL2 I/O pin multiplexed signal configuration register 47" bitfld.long 0xBC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xBC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xBC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xBC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xBC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xBC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xBC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xBC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xBC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xBC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xBC 0.--7. 1. "SSS,Source Signal Select" line.long 0xC0 "MSCR_IO48,SIUL2 I/O pin multiplexed signal configuration register 48" bitfld.long 0xC0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xC0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xC0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xC0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xC0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xC0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xC0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xC0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xC0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xC0 0.--7. 1. "SSS,Source Signal Select" line.long 0xC4 "MSCR_IO49,SIUL2 I/O pin multiplexed signal configuration register 49" bitfld.long 0xC4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xC4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xC4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xC4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xC4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xC4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xC4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xC4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xC4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xC4 0.--7. 1. "SSS,Source Signal Select" line.long 0xC8 "MSCR_IO50,SIUL2 I/O pin multiplexed signal configuration register 50" bitfld.long 0xC8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xC8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xC8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xC8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xC8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xC8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xC8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xC8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xC8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xC8 0.--7. 1. "SSS,Source Signal Select" line.long 0xCC "MSCR_IO51,SIUL2 I/O pin multiplexed signal configuration register 51" bitfld.long 0xCC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xCC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xCC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xCC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xCC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xCC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xCC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xCC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xCC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xCC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xCC 0.--7. 1. "SSS,Source Signal Select" line.long 0xD0 "MSCR_IO52,SIUL2 I/O pin multiplexed signal configuration register 52" bitfld.long 0xD0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xD0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xD0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xD0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xD0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xD0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xD0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xD0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xD0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xD0 0.--7. 1. "SSS,Source Signal Select" line.long 0xD4 "MSCR_IO53,SIUL2 I/O pin multiplexed signal configuration register 53" bitfld.long 0xD4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xD4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xD4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xD4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xD4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xD4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xD4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xD4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xD4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xD4 0.--7. 1. "SSS,Source Signal Select" line.long 0xD8 "MSCR_IO54,SIUL2 I/O pin multiplexed signal configuration register 54" bitfld.long 0xD8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xD8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xD8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xD8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xD8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xD8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xD8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xD8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xD8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xD8 0.--7. 1. "SSS,Source Signal Select" line.long 0xDC "MSCR_IO55,SIUL2 I/O pin multiplexed signal configuration register 55" bitfld.long 0xDC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xDC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xDC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xDC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xDC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xDC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xDC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xDC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xDC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xDC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xDC 0.--7. 1. "SSS,Source Signal Select" line.long 0xE0 "MSCR_IO56,SIUL2 I/O pin multiplexed signal configuration register 56" bitfld.long 0xE0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xE0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xE0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xE0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xE0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xE0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xE0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xE0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xE0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xE0 0.--7. 1. "SSS,Source Signal Select" line.long 0xE4 "MSCR_IO57,SIUL2 I/O pin multiplexed signal configuration register 57" bitfld.long 0xE4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xE4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xE4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xE4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xE4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xE4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xE4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xE4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xE4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xE4 0.--7. 1. "SSS,Source Signal Select" line.long 0xE8 "MSCR_IO58,SIUL2 I/O pin multiplexed signal configuration register 58" bitfld.long 0xE8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xE8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xE8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xE8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xE8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xE8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xE8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xE8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xE8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xE8 0.--7. 1. "SSS,Source Signal Select" line.long 0xEC "MSCR_IO59,SIUL2 I/O pin multiplexed signal configuration register 59" bitfld.long 0xEC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xEC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xEC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xEC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xEC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xEC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xEC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xEC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xEC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xEC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xEC 0.--7. 1. "SSS,Source Signal Select" line.long 0xF0 "MSCR_IO60,SIUL2 I/O pin multiplexed signal configuration register 60" bitfld.long 0xF0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xF0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xF0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xF0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xF0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xF0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xF0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xF0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xF0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xF0 0.--7. 1. "SSS,Source Signal Select" line.long 0xF4 "MSCR_IO61,SIUL2 I/O pin multiplexed signal configuration register 61" bitfld.long 0xF4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xF4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xF4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xF4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xF4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xF4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xF4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xF4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xF4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xF4 0.--7. 1. "SSS,Source Signal Select" line.long 0xF8 "MSCR_IO62,SIUL2 I/O pin multiplexed signal configuration register 62" bitfld.long 0xF8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xF8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xF8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xF8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xF8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xF8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xF8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xF8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xF8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xF8 0.--7. 1. "SSS,Source Signal Select" line.long 0xFC "MSCR_IO63,SIUL2 I/O pin multiplexed signal configuration register 63" bitfld.long 0xFC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xFC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xFC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xFC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xFC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xFC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xFC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xFC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xFC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xFC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xFC 0.--7. 1. "SSS,Source Signal Select" line.long 0x100 "MSCR_IO64,SIUL2 I/O pin multiplexed signal configuration register 64" bitfld.long 0x100 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x100 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x100 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x100 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x100 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x100 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x100 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x100 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x100 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x100 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x100 0.--7. 1. "SSS,Source Signal Select" line.long 0x104 "MSCR_IO65,SIUL2 I/O pin multiplexed signal configuration register 65" bitfld.long 0x104 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x104 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x104 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x104 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x104 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x104 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x104 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x104 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x104 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x104 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x104 0.--7. 1. "SSS,Source Signal Select" line.long 0x108 "MSCR_IO66,SIUL2 I/O pin multiplexed signal configuration register 66" bitfld.long 0x108 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x108 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x108 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x108 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x108 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x108 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x108 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x108 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x108 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x108 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x108 0.--7. 1. "SSS,Source Signal Select" line.long 0x10C "MSCR_IO67,SIUL2 I/O pin multiplexed signal configuration register 67" bitfld.long 0x10C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x10C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x10C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x10C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x10C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x10C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x10C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x10C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x10C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x10C 0.--7. 1. "SSS,Source Signal Select" line.long 0x110 "MSCR_IO68,SIUL2 I/O pin multiplexed signal configuration register 68" bitfld.long 0x110 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x110 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x110 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x110 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x110 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x110 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x110 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x110 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x110 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x110 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x110 0.--7. 1. "SSS,Source Signal Select" line.long 0x114 "MSCR_IO69,SIUL2 I/O pin multiplexed signal configuration register 69" bitfld.long 0x114 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x114 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x114 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x114 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x114 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x114 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x114 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x114 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x114 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x114 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x114 0.--7. 1. "SSS,Source Signal Select" line.long 0x118 "MSCR_IO70,SIUL2 I/O pin multiplexed signal configuration register 70" bitfld.long 0x118 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x118 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x118 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x118 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x118 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x118 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x118 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x118 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x118 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x118 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x118 0.--7. 1. "SSS,Source Signal Select" line.long 0x11C "MSCR_IO71,SIUL2 I/O pin multiplexed signal configuration register 71" bitfld.long 0x11C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x11C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x11C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x11C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x11C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x11C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x11C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x11C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x11C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x11C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x11C 0.--7. 1. "SSS,Source Signal Select" line.long 0x120 "MSCR_IO72,SIUL2 I/O pin multiplexed signal configuration register 72" bitfld.long 0x120 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x120 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x120 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x120 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x120 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x120 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x120 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x120 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x120 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x120 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x120 0.--7. 1. "SSS,Source Signal Select" line.long 0x124 "MSCR_IO73,SIUL2 I/O pin multiplexed signal configuration register 73" bitfld.long 0x124 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x124 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x124 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x124 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x124 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x124 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x124 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x124 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x124 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x124 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x124 0.--7. 1. "SSS,Source Signal Select" line.long 0x128 "MSCR_IO74,SIUL2 I/O pin multiplexed signal configuration register 74" bitfld.long 0x128 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x128 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x128 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x128 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x128 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x128 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x128 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x128 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x128 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x128 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x128 0.--7. 1. "SSS,Source Signal Select" line.long 0x12C "MSCR_IO75,SIUL2 I/O pin multiplexed signal configuration register 75" bitfld.long 0x12C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x12C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x12C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x12C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x12C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x12C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x12C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x12C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x12C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x12C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x12C 0.--7. 1. "SSS,Source Signal Select" line.long 0x130 "MSCR_IO76,SIUL2 I/O pin multiplexed signal configuration register 76" bitfld.long 0x130 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x130 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x130 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x130 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x130 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x130 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x130 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x130 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x130 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x130 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x130 0.--7. 1. "SSS,Source Signal Select" line.long 0x134 "MSCR_IO77,SIUL2 I/O pin multiplexed signal configuration register 77" bitfld.long 0x134 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x134 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x134 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x134 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x134 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x134 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x134 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x134 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x134 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x134 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x134 0.--7. 1. "SSS,Source Signal Select" line.long 0x138 "MSCR_IO78,SIUL2 I/O pin multiplexed signal configuration register 78" bitfld.long 0x138 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x138 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x138 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x138 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x138 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x138 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x138 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x138 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x138 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x138 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x138 0.--7. 1. "SSS,Source Signal Select" line.long 0x13C "MSCR_IO79,SIUL2 I/O pin multiplexed signal configuration register 79" bitfld.long 0x13C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x13C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x13C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x13C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x13C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x13C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x13C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x13C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x13C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x13C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x13C 0.--7. 1. "SSS,Source Signal Select" line.long 0x140 "MSCR_IO80,SIUL2 I/O pin multiplexed signal configuration register 80" bitfld.long 0x140 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x140 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x140 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x140 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x140 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x140 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x140 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x140 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x140 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x140 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x140 0.--7. 1. "SSS,Source Signal Select" line.long 0x144 "MSCR_IO81,SIUL2 I/O pin multiplexed signal configuration register 81" bitfld.long 0x144 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x144 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x144 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x144 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x144 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x144 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x144 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x144 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x144 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x144 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x144 0.--7. 1. "SSS,Source Signal Select" line.long 0x148 "MSCR_IO82,SIUL2 I/O pin multiplexed signal configuration register 82" bitfld.long 0x148 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x148 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x148 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x148 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x148 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x148 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x148 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x148 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x148 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x148 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x148 0.--7. 1. "SSS,Source Signal Select" line.long 0x14C "MSCR_IO83,SIUL2 I/O pin multiplexed signal configuration register 83" bitfld.long 0x14C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x14C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x14C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x14C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x14C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x14C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x14C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x14C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x14C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x14C 0.--7. 1. "SSS,Source Signal Select" line.long 0x150 "MSCR_IO84,SIUL2 I/O pin multiplexed signal configuration register 84" bitfld.long 0x150 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x150 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x150 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x150 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x150 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x150 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x150 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x150 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x150 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x150 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x150 0.--7. 1. "SSS,Source Signal Select" line.long 0x154 "MSCR_IO85,SIUL2 I/O pin multiplexed signal configuration register 85" bitfld.long 0x154 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x154 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x154 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x154 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x154 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x154 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x154 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x154 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x154 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x154 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x154 0.--7. 1. "SSS,Source Signal Select" line.long 0x158 "MSCR_IO86,SIUL2 I/O pin multiplexed signal configuration register 86" bitfld.long 0x158 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x158 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x158 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x158 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x158 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x158 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x158 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x158 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x158 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x158 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x158 0.--7. 1. "SSS,Source Signal Select" line.long 0x15C "MSCR_IO87,SIUL2 I/O pin multiplexed signal configuration register 87" bitfld.long 0x15C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x15C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x15C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x15C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x15C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x15C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x15C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x15C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x15C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x15C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x15C 0.--7. 1. "SSS,Source Signal Select" line.long 0x160 "MSCR_IO88,SIUL2 I/O pin multiplexed signal configuration register 88" bitfld.long 0x160 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x160 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x160 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x160 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x160 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x160 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x160 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x160 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x160 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x160 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x160 0.--7. 1. "SSS,Source Signal Select" line.long 0x164 "MSCR_IO89,SIUL2 I/O pin multiplexed signal configuration register 89" bitfld.long 0x164 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x164 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x164 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x164 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x164 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x164 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x164 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x164 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x164 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x164 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x164 0.--7. 1. "SSS,Source Signal Select" line.long 0x168 "MSCR_IO90,SIUL2 I/O pin multiplexed signal configuration register 90" bitfld.long 0x168 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x168 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x168 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x168 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x168 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x168 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x168 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x168 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x168 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x168 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x168 0.--7. 1. "SSS,Source Signal Select" line.long 0x16C "MSCR_IO91,SIUL2 I/O pin multiplexed signal configuration register 91" bitfld.long 0x16C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x16C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x16C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x16C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x16C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x16C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x16C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x16C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x16C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x16C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x16C 0.--7. 1. "SSS,Source Signal Select" line.long 0x170 "MSCR_IO92,SIUL2 I/O pin multiplexed signal configuration register 92" bitfld.long 0x170 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x170 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x170 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x170 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x170 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x170 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x170 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x170 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x170 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x170 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x170 0.--7. 1. "SSS,Source Signal Select" line.long 0x174 "MSCR_IO93,SIUL2 I/O pin multiplexed signal configuration register 93" bitfld.long 0x174 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x174 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x174 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x174 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x174 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x174 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x174 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x174 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x174 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x174 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x174 0.--7. 1. "SSS,Source Signal Select" line.long 0x178 "MSCR_IO94,SIUL2 I/O pin multiplexed signal configuration register 94" bitfld.long 0x178 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x178 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x178 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x178 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x178 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x178 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x178 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x178 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x178 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x178 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x178 0.--7. 1. "SSS,Source Signal Select" line.long 0x17C "MSCR_IO95,SIUL2 I/O pin multiplexed signal configuration register 95" bitfld.long 0x17C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x17C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x17C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x17C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x17C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x17C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x17C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x17C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x17C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x17C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x17C 0.--7. 1. "SSS,Source Signal Select" line.long 0x180 "MSCR_IO96,SIUL2 I/O pin multiplexed signal configuration register 96" bitfld.long 0x180 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x180 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x180 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x180 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x180 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x180 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x180 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x180 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x180 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x180 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x180 0.--7. 1. "SSS,Source Signal Select" line.long 0x184 "MSCR_IO97,SIUL2 I/O pin multiplexed signal configuration register 97" bitfld.long 0x184 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x184 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x184 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x184 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x184 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x184 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x184 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x184 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x184 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x184 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x184 0.--7. 1. "SSS,Source Signal Select" line.long 0x188 "MSCR_IO98,SIUL2 I/O pin multiplexed signal configuration register 98" bitfld.long 0x188 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x188 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x188 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x188 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x188 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x188 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x188 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x188 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x188 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x188 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x188 0.--7. 1. "SSS,Source Signal Select" line.long 0x18C "MSCR_IO99,SIUL2 I/O pin multiplexed signal configuration register 99" bitfld.long 0x18C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x18C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x18C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x18C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x18C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x18C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x18C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x18C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x18C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x18C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x18C 0.--7. 1. "SSS,Source Signal Select" line.long 0x190 "MSCR_IO100,SIUL2 I/O pin multiplexed signal configuration register 100" bitfld.long 0x190 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x190 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x190 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x190 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x190 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x190 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x190 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x190 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x190 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x190 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x190 0.--7. 1. "SSS,Source Signal Select" line.long 0x194 "MSCR_IO101,SIUL2 I/O pin multiplexed signal configuration register 101" bitfld.long 0x194 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x194 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x194 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x194 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x194 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x194 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x194 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x194 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x194 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x194 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x194 0.--7. 1. "SSS,Source Signal Select" line.long 0x198 "MSCR_IO102,SIUL2 I/O pin multiplexed signal configuration register 102" bitfld.long 0x198 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x198 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x198 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x198 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x198 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x198 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x198 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x198 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x198 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x198 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x198 0.--7. 1. "SSS,Source Signal Select" line.long 0x19C "MSCR_IO103,SIUL2 I/O pin multiplexed signal configuration register 103" bitfld.long 0x19C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x19C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x19C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x19C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x19C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x19C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x19C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x19C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x19C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x19C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x19C 0.--7. 1. "SSS,Source Signal Select" line.long 0x1A0 "MSCR_IO104,SIUL2 I/O pin multiplexed signal configuration register 104" bitfld.long 0x1A0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1A0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1A0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1A0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1A0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1A0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1A0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1A0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1A0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1A0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1A0 0.--7. 1. "SSS,Source Signal Select" line.long 0x1A4 "MSCR_IO105,SIUL2 I/O pin multiplexed signal configuration register 105" bitfld.long 0x1A4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1A4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1A4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1A4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1A4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1A4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1A4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1A4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1A4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1A4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1A4 0.--7. 1. "SSS,Source Signal Select" line.long 0x1A8 "MSCR_IO106,SIUL2 I/O pin multiplexed signal configuration register 106" bitfld.long 0x1A8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1A8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1A8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1A8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1A8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1A8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1A8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1A8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1A8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1A8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1A8 0.--7. 1. "SSS,Source Signal Select" line.long 0x1AC "MSCR_IO107,SIUL2 I/O pin multiplexed signal configuration register 107" bitfld.long 0x1AC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1AC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1AC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1AC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1AC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1AC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1AC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1AC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1AC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1AC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1AC 0.--7. 1. "SSS,Source Signal Select" line.long 0x1B0 "MSCR_IO108,SIUL2 I/O pin multiplexed signal configuration register 108" bitfld.long 0x1B0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1B0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1B0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1B0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1B0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1B0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1B0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1B0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1B0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1B0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1B0 0.--7. 1. "SSS,Source Signal Select" line.long 0x1B4 "MSCR_IO109,SIUL2 I/O pin multiplexed signal configuration register 109" bitfld.long 0x1B4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1B4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1B4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1B4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1B4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1B4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1B4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1B4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1B4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1B4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1B4 0.--7. 1. "SSS,Source Signal Select" line.long 0x1B8 "MSCR_IO110,SIUL2 I/O pin multiplexed signal configuration register 110" bitfld.long 0x1B8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1B8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1B8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1B8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1B8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1B8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1B8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1B8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1B8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1B8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1B8 0.--7. 1. "SSS,Source Signal Select" line.long 0x1BC "MSCR_IO111,SIUL2 I/O pin multiplexed signal configuration register 111" bitfld.long 0x1BC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1BC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1BC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1BC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1BC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1BC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1BC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1BC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1BC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1BC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1BC 0.--7. 1. "SSS,Source Signal Select" line.long 0x1C0 "MSCR_IO112,SIUL2 I/O pin multiplexed signal configuration register 112" bitfld.long 0x1C0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1C0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1C0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1C0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1C0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1C0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1C0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1C0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1C0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1C0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1C0 0.--7. 1. "SSS,Source Signal Select" line.long 0x1C4 "MSCR_IO113,SIUL2 I/O pin multiplexed signal configuration register 113" bitfld.long 0x1C4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1C4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1C4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1C4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1C4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1C4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1C4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1C4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1C4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1C4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1C4 0.--7. 1. "SSS,Source Signal Select" line.long 0x1C8 "MSCR_IO114,SIUL2 I/O pin multiplexed signal configuration register 114" bitfld.long 0x1C8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1C8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1C8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1C8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1C8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1C8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1C8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1C8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1C8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1C8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1C8 0.--7. 1. "SSS,Source Signal Select" line.long 0x1CC "MSCR_IO115,SIUL2 I/O pin multiplexed signal configuration register 115" bitfld.long 0x1CC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1CC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1CC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1CC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1CC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1CC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1CC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1CC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1CC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1CC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1CC 0.--7. 1. "SSS,Source Signal Select" line.long 0x1D0 "MSCR_IO116,SIUL2 I/O pin multiplexed signal configuration register 116" bitfld.long 0x1D0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1D0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1D0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1D0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1D0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1D0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1D0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1D0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1D0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1D0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1D0 0.--7. 1. "SSS,Source Signal Select" line.long 0x1D4 "MSCR_IO117,SIUL2 I/O pin multiplexed signal configuration register 117" bitfld.long 0x1D4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1D4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1D4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1D4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1D4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1D4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1D4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1D4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1D4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1D4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1D4 0.--7. 1. "SSS,Source Signal Select" line.long 0x1D8 "MSCR_IO118,SIUL2 I/O pin multiplexed signal configuration register 118" bitfld.long 0x1D8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1D8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1D8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1D8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1D8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1D8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1D8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1D8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1D8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1D8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1D8 0.--7. 1. "SSS,Source Signal Select" line.long 0x1DC "MSCR_IO119,SIUL2 I/O pin multiplexed signal configuration register 119" bitfld.long 0x1DC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1DC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1DC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1DC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1DC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1DC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1DC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1DC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1DC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1DC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1DC 0.--7. 1. "SSS,Source Signal Select" line.long 0x1E0 "MSCR_IO120,SIUL2 I/O pin multiplexed signal configuration register 120" bitfld.long 0x1E0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1E0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1E0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1E0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1E0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1E0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1E0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1E0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1E0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1E0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1E0 0.--7. 1. "SSS,Source Signal Select" line.long 0x1E4 "MSCR_IO121,SIUL2 I/O pin multiplexed signal configuration register 121" bitfld.long 0x1E4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1E4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1E4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1E4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1E4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1E4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1E4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1E4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1E4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1E4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1E4 0.--7. 1. "SSS,Source Signal Select" line.long 0x1E8 "MSCR_IO122,SIUL2 I/O pin multiplexed signal configuration register 122" bitfld.long 0x1E8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1E8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1E8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1E8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1E8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1E8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1E8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1E8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1E8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1E8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1E8 0.--7. 1. "SSS,Source Signal Select" line.long 0x1EC "MSCR_IO123,SIUL2 I/O pin multiplexed signal configuration register 123" bitfld.long 0x1EC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1EC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1EC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1EC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1EC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1EC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1EC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1EC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1EC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1EC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1EC 0.--7. 1. "SSS,Source Signal Select" line.long 0x1F0 "MSCR_IO124,SIUL2 I/O pin multiplexed signal configuration register 124" bitfld.long 0x1F0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1F0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1F0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1F0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1F0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1F0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1F0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1F0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1F0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1F0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1F0 0.--7. 1. "SSS,Source Signal Select" line.long 0x1F4 "MSCR_IO125,SIUL2 I/O pin multiplexed signal configuration register 125" bitfld.long 0x1F4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1F4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1F4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1F4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1F4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1F4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1F4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1F4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1F4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1F4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1F4 0.--7. 1. "SSS,Source Signal Select" line.long 0x1F8 "MSCR_IO126,SIUL2 I/O pin multiplexed signal configuration register 126" bitfld.long 0x1F8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1F8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1F8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1F8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1F8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1F8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1F8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1F8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1F8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1F8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1F8 0.--7. 1. "SSS,Source Signal Select" line.long 0x1FC "MSCR_IO127,SIUL2 I/O pin multiplexed signal configuration register 127" bitfld.long 0x1FC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1FC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1FC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1FC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1FC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1FC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1FC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1FC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1FC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1FC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1FC 0.--7. 1. "SSS,Source Signal Select" line.long 0x200 "MSCR_IO128,SIUL2 I/O pin multiplexed signal configuration register 128" bitfld.long 0x200 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x200 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x200 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x200 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x200 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x200 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x200 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x200 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x200 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x200 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x200 0.--7. 1. "SSS,Source Signal Select" line.long 0x204 "MSCR_IO129,SIUL2 I/O pin multiplexed signal configuration register 129" bitfld.long 0x204 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x204 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x204 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x204 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x204 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x204 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x204 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x204 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x204 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x204 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x204 0.--7. 1. "SSS,Source Signal Select" line.long 0x208 "MSCR_IO130,SIUL2 I/O pin multiplexed signal configuration register 130" bitfld.long 0x208 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x208 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x208 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x208 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x208 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x208 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x208 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x208 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x208 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x208 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x208 0.--7. 1. "SSS,Source Signal Select" line.long 0x20C "MSCR_IO131,SIUL2 I/O pin multiplexed signal configuration register 131" bitfld.long 0x20C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x20C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x20C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x20C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x20C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x20C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x20C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x20C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x20C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x20C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x20C 0.--7. 1. "SSS,Source Signal Select" line.long 0x210 "MSCR_IO132,SIUL2 I/O pin multiplexed signal configuration register 132" bitfld.long 0x210 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x210 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x210 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x210 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x210 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x210 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x210 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x210 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x210 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x210 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x210 0.--7. 1. "SSS,Source Signal Select" line.long 0x214 "MSCR_IO133,SIUL2 I/O pin multiplexed signal configuration register 133" bitfld.long 0x214 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x214 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x214 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x214 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x214 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x214 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x214 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x214 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x214 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x214 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x214 0.--7. 1. "SSS,Source Signal Select" line.long 0x218 "MSCR_IO134,SIUL2 I/O pin multiplexed signal configuration register 134" bitfld.long 0x218 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x218 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x218 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x218 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x218 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x218 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x218 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x218 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x218 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x218 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x218 0.--7. 1. "SSS,Source Signal Select" line.long 0x21C "MSCR_IO135,SIUL2 I/O pin multiplexed signal configuration register 135" bitfld.long 0x21C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x21C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x21C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x21C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x21C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x21C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x21C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x21C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x21C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x21C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x21C 0.--7. 1. "SSS,Source Signal Select" line.long 0x220 "MSCR_IO136,SIUL2 I/O pin multiplexed signal configuration register 136" bitfld.long 0x220 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x220 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x220 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x220 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x220 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x220 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x220 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x220 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x220 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x220 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x220 0.--7. 1. "SSS,Source Signal Select" line.long 0x224 "MSCR_IO137,SIUL2 I/O pin multiplexed signal configuration register 137" bitfld.long 0x224 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x224 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x224 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x224 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x224 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x224 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x224 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x224 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x224 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x224 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x224 0.--7. 1. "SSS,Source Signal Select" line.long 0x228 "MSCR_IO138,SIUL2 I/O pin multiplexed signal configuration register 138" bitfld.long 0x228 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x228 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x228 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x228 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x228 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x228 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x228 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x228 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x228 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x228 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x228 0.--7. 1. "SSS,Source Signal Select" line.long 0x22C "MSCR_IO139,SIUL2 I/O pin multiplexed signal configuration register 139" bitfld.long 0x22C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x22C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x22C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x22C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x22C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x22C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x22C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x22C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x22C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x22C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x22C 0.--7. 1. "SSS,Source Signal Select" line.long 0x230 "MSCR_IO140,SIUL2 I/O pin multiplexed signal configuration register 140" bitfld.long 0x230 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x230 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x230 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x230 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x230 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x230 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x230 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x230 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x230 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x230 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x230 0.--7. 1. "SSS,Source Signal Select" line.long 0x234 "MSCR_IO141,SIUL2 I/O pin multiplexed signal configuration register 141" bitfld.long 0x234 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x234 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x234 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x234 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x234 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x234 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x234 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x234 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x234 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x234 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x234 0.--7. 1. "SSS,Source Signal Select" line.long 0x238 "MSCR_IO142,SIUL2 I/O pin multiplexed signal configuration register 142" bitfld.long 0x238 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x238 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x238 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x238 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x238 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x238 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x238 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x238 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x238 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x238 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x238 0.--7. 1. "SSS,Source Signal Select" line.long 0x23C "MSCR_IO143,SIUL2 I/O pin multiplexed signal configuration register 143" bitfld.long 0x23C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x23C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x23C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x23C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x23C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x23C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x23C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x23C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x23C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x23C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x23C 0.--7. 1. "SSS,Source Signal Select" line.long 0x240 "MSCR_IO144,SIUL2 I/O pin multiplexed signal configuration register 144" bitfld.long 0x240 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x240 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x240 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x240 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x240 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x240 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x240 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x240 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x240 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x240 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x240 0.--7. 1. "SSS,Source Signal Select" line.long 0x244 "MSCR_IO145,SIUL2 I/O pin multiplexed signal configuration register 145" bitfld.long 0x244 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x244 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x244 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x244 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x244 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x244 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x244 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x244 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x244 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x244 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x244 0.--7. 1. "SSS,Source Signal Select" line.long 0x248 "MSCR_IO146,SIUL2 I/O pin multiplexed signal configuration register 146" bitfld.long 0x248 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x248 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x248 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x248 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x248 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x248 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x248 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x248 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x248 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x248 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x248 0.--7. 1. "SSS,Source Signal Select" line.long 0x24C "MSCR_IO147,SIUL2 I/O pin multiplexed signal configuration register 147" bitfld.long 0x24C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x24C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x24C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x24C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x24C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x24C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x24C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x24C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x24C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x24C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x24C 0.--7. 1. "SSS,Source Signal Select" line.long 0x250 "MSCR_IO148,SIUL2 I/O pin multiplexed signal configuration register 148" bitfld.long 0x250 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x250 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x250 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x250 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x250 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x250 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x250 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x250 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x250 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x250 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x250 0.--7. 1. "SSS,Source Signal Select" line.long 0x254 "MSCR_IO149,SIUL2 I/O pin multiplexed signal configuration register 149" bitfld.long 0x254 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x254 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x254 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x254 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x254 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x254 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x254 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x254 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x254 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x254 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x254 0.--7. 1. "SSS,Source Signal Select" line.long 0x258 "MSCR_IO150,SIUL2 I/O pin multiplexed signal configuration register 150" bitfld.long 0x258 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x258 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x258 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x258 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x258 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x258 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x258 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x258 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x258 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x258 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x258 0.--7. 1. "SSS,Source Signal Select" line.long 0x25C "MSCR_IO151,SIUL2 I/O pin multiplexed signal configuration register 151" bitfld.long 0x25C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x25C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x25C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x25C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x25C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x25C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x25C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x25C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x25C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x25C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x25C 0.--7. 1. "SSS,Source Signal Select" line.long 0x260 "MSCR_IO152,SIUL2 I/O pin multiplexed signal configuration register 152" bitfld.long 0x260 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x260 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x260 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x260 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x260 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x260 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x260 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x260 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x260 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x260 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x260 0.--7. 1. "SSS,Source Signal Select" line.long 0x264 "MSCR_IO153,SIUL2 I/O pin multiplexed signal configuration register 153" bitfld.long 0x264 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x264 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x264 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x264 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x264 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x264 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x264 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x264 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x264 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x264 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x264 0.--7. 1. "SSS,Source Signal Select" line.long 0x268 "MSCR_IO154,SIUL2 I/O pin multiplexed signal configuration register 154" bitfld.long 0x268 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x268 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x268 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x268 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x268 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x268 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x268 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x268 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x268 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x268 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x268 0.--7. 1. "SSS,Source Signal Select" line.long 0x26C "MSCR_IO155,SIUL2 I/O pin multiplexed signal configuration register 155" bitfld.long 0x26C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x26C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x26C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x26C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x26C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x26C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x26C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x26C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x26C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x26C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x26C 0.--7. 1. "SSS,Source Signal Select" line.long 0x270 "MSCR_IO156,SIUL2 I/O pin multiplexed signal configuration register 156" bitfld.long 0x270 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x270 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x270 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x270 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x270 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x270 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x270 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x270 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x270 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x270 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x270 0.--7. 1. "SSS,Source Signal Select" line.long 0x274 "MSCR_IO157,SIUL2 I/O pin multiplexed signal configuration register 157" bitfld.long 0x274 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x274 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x274 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x274 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x274 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x274 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x274 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x274 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x274 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x274 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x274 0.--7. 1. "SSS,Source Signal Select" line.long 0x278 "MSCR_IO158,SIUL2 I/O pin multiplexed signal configuration register 158" bitfld.long 0x278 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x278 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x278 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x278 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x278 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x278 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x278 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x278 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x278 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x278 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x278 0.--7. 1. "SSS,Source Signal Select" line.long 0x27C "MSCR_IO159,SIUL2 I/O pin multiplexed signal configuration register 159" bitfld.long 0x27C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x27C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x27C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x27C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x27C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x27C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x27C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x27C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x27C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x27C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x27C 0.--7. 1. "SSS,Source Signal Select" line.long 0x280 "MSCR_IO160,SIUL2 I/O pin multiplexed signal configuration register 160" bitfld.long 0x280 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x280 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x280 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x280 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x280 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x280 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x280 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x280 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x280 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x280 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x280 0.--7. 1. "SSS,Source Signal Select" line.long 0x284 "MSCR_IO161,SIUL2 I/O pin multiplexed signal configuration register 161" bitfld.long 0x284 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x284 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x284 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x284 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x284 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x284 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x284 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x284 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x284 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x284 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x284 0.--7. 1. "SSS,Source Signal Select" line.long 0x288 "MSCR_IO162,SIUL2 I/O pin multiplexed signal configuration register 162" bitfld.long 0x288 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x288 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x288 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x288 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x288 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x288 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x288 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x288 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x288 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x288 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x288 0.--7. 1. "SSS,Source Signal Select" line.long 0x28C "MSCR_IO163,SIUL2 I/O pin multiplexed signal configuration register 163" bitfld.long 0x28C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x28C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x28C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x28C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x28C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x28C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x28C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x28C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x28C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x28C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x28C 0.--7. 1. "SSS,Source Signal Select" line.long 0x290 "MSCR_IO164,SIUL2 I/O pin multiplexed signal configuration register 164" bitfld.long 0x290 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x290 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x290 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x290 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x290 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x290 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x290 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x290 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x290 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x290 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x290 0.--7. 1. "SSS,Source Signal Select" line.long 0x294 "MSCR_IO165,SIUL2 I/O pin multiplexed signal configuration register 165" bitfld.long 0x294 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x294 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x294 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x294 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x294 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x294 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x294 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x294 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x294 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x294 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x294 0.--7. 1. "SSS,Source Signal Select" line.long 0x298 "MSCR_IO166,SIUL2 I/O pin multiplexed signal configuration register 166" bitfld.long 0x298 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x298 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x298 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x298 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x298 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x298 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x298 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x298 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x298 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x298 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x298 0.--7. 1. "SSS,Source Signal Select" line.long 0x29C "MSCR_IO167,SIUL2 I/O pin multiplexed signal configuration register 167" bitfld.long 0x29C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x29C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x29C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x29C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x29C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x29C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x29C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x29C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x29C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x29C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x29C 0.--7. 1. "SSS,Source Signal Select" line.long 0x2A0 "MSCR_IO168,SIUL2 I/O pin multiplexed signal configuration register 168" bitfld.long 0x2A0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2A0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2A0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2A0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2A0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2A0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2A0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2A0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2A0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2A0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2A0 0.--7. 1. "SSS,Source Signal Select" line.long 0x2A4 "MSCR_IO169,SIUL2 I/O pin multiplexed signal configuration register 169" bitfld.long 0x2A4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2A4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2A4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2A4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2A4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2A4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2A4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2A4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2A4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2A4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2A4 0.--7. 1. "SSS,Source Signal Select" line.long 0x2A8 "MSCR_IO170,SIUL2 I/O pin multiplexed signal configuration register 170" bitfld.long 0x2A8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2A8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2A8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2A8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2A8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2A8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2A8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2A8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2A8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2A8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2A8 0.--7. 1. "SSS,Source Signal Select" line.long 0x2AC "MSCR_IO171,SIUL2 I/O pin multiplexed signal configuration register 171" bitfld.long 0x2AC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2AC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2AC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2AC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2AC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2AC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2AC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2AC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2AC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2AC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2AC 0.--7. 1. "SSS,Source Signal Select" line.long 0x2B0 "MSCR_IO172,SIUL2 I/O pin multiplexed signal configuration register 172" bitfld.long 0x2B0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2B0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2B0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2B0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2B0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2B0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2B0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2B0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2B0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2B0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2B0 0.--7. 1. "SSS,Source Signal Select" line.long 0x2B4 "MSCR_IO173,SIUL2 I/O pin multiplexed signal configuration register 173" bitfld.long 0x2B4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2B4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2B4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2B4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2B4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2B4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2B4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2B4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2B4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2B4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2B4 0.--7. 1. "SSS,Source Signal Select" line.long 0x2B8 "MSCR_IO174,SIUL2 I/O pin multiplexed signal configuration register 174" bitfld.long 0x2B8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2B8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2B8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2B8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2B8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2B8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2B8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2B8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2B8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2B8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2B8 0.--7. 1. "SSS,Source Signal Select" line.long 0x2BC "MSCR_IO175,SIUL2 I/O pin multiplexed signal configuration register 175" bitfld.long 0x2BC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2BC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2BC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2BC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2BC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2BC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2BC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2BC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2BC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2BC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2BC 0.--7. 1. "SSS,Source Signal Select" line.long 0x2C0 "MSCR_IO176,SIUL2 I/O pin multiplexed signal configuration register 176" bitfld.long 0x2C0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2C0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2C0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2C0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2C0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2C0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2C0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2C0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2C0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2C0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2C0 0.--7. 1. "SSS,Source Signal Select" line.long 0x2C4 "MSCR_IO177,SIUL2 I/O pin multiplexed signal configuration register 177" bitfld.long 0x2C4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2C4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2C4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2C4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2C4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2C4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2C4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2C4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2C4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2C4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2C4 0.--7. 1. "SSS,Source Signal Select" line.long 0x2C8 "MSCR_IO178,SIUL2 I/O pin multiplexed signal configuration register 178" bitfld.long 0x2C8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2C8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2C8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2C8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2C8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2C8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2C8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2C8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2C8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2C8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2C8 0.--7. 1. "SSS,Source Signal Select" line.long 0x2CC "MSCR_IO179,SIUL2 I/O pin multiplexed signal configuration register 179" bitfld.long 0x2CC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2CC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2CC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2CC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2CC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2CC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2CC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2CC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2CC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2CC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2CC 0.--7. 1. "SSS,Source Signal Select" line.long 0x2D0 "MSCR_IO180,SIUL2 I/O pin multiplexed signal configuration register 180" bitfld.long 0x2D0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2D0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2D0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2D0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2D0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2D0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2D0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2D0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2D0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2D0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2D0 0.--7. 1. "SSS,Source Signal Select" line.long 0x2D4 "MSCR_IO181,SIUL2 I/O pin multiplexed signal configuration register 181" bitfld.long 0x2D4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2D4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2D4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2D4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2D4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2D4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2D4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2D4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2D4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2D4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2D4 0.--7. 1. "SSS,Source Signal Select" line.long 0x2D8 "MSCR_IO182,SIUL2 I/O pin multiplexed signal configuration register 182" bitfld.long 0x2D8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2D8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2D8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2D8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2D8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2D8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2D8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2D8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2D8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2D8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2D8 0.--7. 1. "SSS,Source Signal Select" line.long 0x2DC "MSCR_IO183,SIUL2 I/O pin multiplexed signal configuration register 183" bitfld.long 0x2DC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2DC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2DC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2DC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2DC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2DC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2DC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2DC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2DC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2DC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2DC 0.--7. 1. "SSS,Source Signal Select" line.long 0x2E0 "MSCR_IO184,SIUL2 I/O pin multiplexed signal configuration register 184" bitfld.long 0x2E0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2E0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2E0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2E0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2E0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2E0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2E0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2E0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2E0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2E0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2E0 0.--7. 1. "SSS,Source Signal Select" line.long 0x2E4 "MSCR_IO185,SIUL2 I/O pin multiplexed signal configuration register 185" bitfld.long 0x2E4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2E4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2E4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2E4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2E4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2E4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2E4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2E4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2E4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2E4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2E4 0.--7. 1. "SSS,Source Signal Select" line.long 0x2E8 "MSCR_IO186,SIUL2 I/O pin multiplexed signal configuration register 186" bitfld.long 0x2E8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2E8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2E8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2E8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2E8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2E8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2E8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2E8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2E8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2E8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2E8 0.--7. 1. "SSS,Source Signal Select" line.long 0x2EC "MSCR_IO187,SIUL2 I/O pin multiplexed signal configuration register 187" bitfld.long 0x2EC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2EC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2EC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2EC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2EC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2EC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2EC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2EC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2EC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2EC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2EC 0.--7. 1. "SSS,Source Signal Select" line.long 0x2F0 "MSCR_IO188,SIUL2 I/O pin multiplexed signal configuration register 188" bitfld.long 0x2F0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2F0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2F0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2F0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2F0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2F0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2F0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2F0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2F0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2F0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2F0 0.--7. 1. "SSS,Source Signal Select" line.long 0x2F4 "MSCR_IO189,SIUL2 I/O pin multiplexed signal configuration register 189" bitfld.long 0x2F4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2F4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2F4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2F4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2F4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2F4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2F4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2F4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2F4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2F4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2F4 0.--7. 1. "SSS,Source Signal Select" line.long 0x2F8 "MSCR_IO190,SIUL2 I/O pin multiplexed signal configuration register 190" bitfld.long 0x2F8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2F8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2F8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2F8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2F8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2F8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2F8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2F8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2F8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2F8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2F8 0.--7. 1. "SSS,Source Signal Select" line.long 0x2FC "MSCR_IO191,SIUL2 I/O pin multiplexed signal configuration register 191" bitfld.long 0x2FC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2FC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2FC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2FC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2FC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2FC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2FC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2FC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2FC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2FC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2FC 0.--7. 1. "SSS,Source Signal Select" line.long 0x300 "MSCR_IO192,SIUL2 I/O pin multiplexed signal configuration register 192" bitfld.long 0x300 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x300 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x300 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x300 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x300 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x300 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x300 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x300 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x300 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x300 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x300 0.--7. 1. "SSS,Source Signal Select" line.long 0x304 "MSCR_IO193,SIUL2 I/O pin multiplexed signal configuration register 193" bitfld.long 0x304 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x304 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x304 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x304 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x304 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x304 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x304 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x304 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x304 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x304 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x304 0.--7. 1. "SSS,Source Signal Select" line.long 0x308 "MSCR_IO194,SIUL2 I/O pin multiplexed signal configuration register 194" bitfld.long 0x308 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x308 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x308 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x308 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x308 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x308 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x308 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x308 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x308 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x308 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x308 0.--7. 1. "SSS,Source Signal Select" line.long 0x30C "MSCR_IO195,SIUL2 I/O pin multiplexed signal configuration register 195" bitfld.long 0x30C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x30C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x30C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x30C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x30C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x30C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x30C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x30C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x30C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x30C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x30C 0.--7. 1. "SSS,Source Signal Select" line.long 0x310 "MSCR_IO196,SIUL2 I/O pin multiplexed signal configuration register 196" bitfld.long 0x310 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x310 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x310 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x310 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x310 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x310 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x310 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x310 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x310 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x310 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x310 0.--7. 1. "SSS,Source Signal Select" line.long 0x314 "MSCR_IO197,SIUL2 I/O pin multiplexed signal configuration register 197" bitfld.long 0x314 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x314 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x314 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x314 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x314 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x314 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x314 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x314 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x314 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x314 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x314 0.--7. 1. "SSS,Source Signal Select" line.long 0x318 "MSCR_IO198,SIUL2 I/O pin multiplexed signal configuration register 198" bitfld.long 0x318 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x318 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x318 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x318 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x318 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x318 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x318 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x318 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x318 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x318 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x318 0.--7. 1. "SSS,Source Signal Select" line.long 0x31C "MSCR_IO199,SIUL2 I/O pin multiplexed signal configuration register 199" bitfld.long 0x31C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x31C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x31C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x31C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x31C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x31C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x31C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x31C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x31C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x31C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x31C 0.--7. 1. "SSS,Source Signal Select" line.long 0x320 "MSCR_IO200,SIUL2 I/O pin multiplexed signal configuration register 200" bitfld.long 0x320 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x320 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x320 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x320 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x320 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x320 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x320 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x320 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x320 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x320 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x320 0.--7. 1. "SSS,Source Signal Select" line.long 0x324 "MSCR_IO201,SIUL2 I/O pin multiplexed signal configuration register 201" bitfld.long 0x324 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x324 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x324 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x324 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x324 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x324 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x324 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x324 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x324 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x324 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x324 0.--7. 1. "SSS,Source Signal Select" line.long 0x328 "MSCR_IO202,SIUL2 I/O pin multiplexed signal configuration register 202" bitfld.long 0x328 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x328 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x328 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x328 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x328 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x328 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x328 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x328 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x328 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x328 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x328 0.--7. 1. "SSS,Source Signal Select" line.long 0x32C "MSCR_IO203,SIUL2 I/O pin multiplexed signal configuration register 203" bitfld.long 0x32C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x32C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x32C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x32C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x32C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x32C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x32C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x32C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x32C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x32C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x32C 0.--7. 1. "SSS,Source Signal Select" line.long 0x330 "MSCR_IO204,SIUL2 I/O pin multiplexed signal configuration register 204" bitfld.long 0x330 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x330 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x330 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x330 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x330 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x330 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x330 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x330 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x330 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x330 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x330 0.--7. 1. "SSS,Source Signal Select" line.long 0x334 "MSCR_IO205,SIUL2 I/O pin multiplexed signal configuration register 205" bitfld.long 0x334 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x334 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x334 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x334 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x334 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x334 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x334 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x334 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x334 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x334 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x334 0.--7. 1. "SSS,Source Signal Select" line.long 0x338 "MSCR_IO206,SIUL2 I/O pin multiplexed signal configuration register 206" bitfld.long 0x338 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x338 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x338 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x338 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x338 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x338 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x338 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x338 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x338 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x338 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x338 0.--7. 1. "SSS,Source Signal Select" line.long 0x33C "MSCR_IO207,SIUL2 I/O pin multiplexed signal configuration register 207" bitfld.long 0x33C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x33C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x33C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x33C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x33C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x33C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x33C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x33C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x33C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x33C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x33C 0.--7. 1. "SSS,Source Signal Select" line.long 0x340 "MSCR_IO208,SIUL2 I/O pin multiplexed signal configuration register 208" bitfld.long 0x340 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x340 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x340 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x340 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x340 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x340 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x340 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x340 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x340 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x340 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x340 0.--7. 1. "SSS,Source Signal Select" line.long 0x344 "MSCR_IO209,SIUL2 I/O pin multiplexed signal configuration register 209" bitfld.long 0x344 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x344 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x344 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x344 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x344 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x344 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x344 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x344 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x344 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x344 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x344 0.--7. 1. "SSS,Source Signal Select" line.long 0x348 "MSCR_IO210,SIUL2 I/O pin multiplexed signal configuration register 210" bitfld.long 0x348 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x348 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x348 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x348 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x348 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x348 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x348 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x348 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x348 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x348 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x348 0.--7. 1. "SSS,Source Signal Select" line.long 0x34C "MSCR_IO211,SIUL2 I/O pin multiplexed signal configuration register 211" bitfld.long 0x34C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x34C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x34C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x34C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x34C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x34C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x34C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x34C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x34C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x34C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x34C 0.--7. 1. "SSS,Source Signal Select" line.long 0x350 "MSCR_IO212,SIUL2 I/O pin multiplexed signal configuration register 212" bitfld.long 0x350 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x350 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x350 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x350 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x350 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x350 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x350 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x350 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x350 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x350 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x350 0.--7. 1. "SSS,Source Signal Select" line.long 0x354 "MSCR_IO213,SIUL2 I/O pin multiplexed signal configuration register 213" bitfld.long 0x354 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x354 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x354 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x354 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x354 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x354 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x354 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x354 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x354 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x354 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x354 0.--7. 1. "SSS,Source Signal Select" line.long 0x358 "MSCR_IO214,SIUL2 I/O pin multiplexed signal configuration register 214" bitfld.long 0x358 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x358 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x358 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x358 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x358 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x358 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x358 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x358 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x358 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x358 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x358 0.--7. 1. "SSS,Source Signal Select" line.long 0x35C "MSCR_IO215,SIUL2 I/O pin multiplexed signal configuration register 215" bitfld.long 0x35C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x35C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x35C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x35C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x35C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x35C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x35C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x35C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x35C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x35C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x35C 0.--7. 1. "SSS,Source Signal Select" line.long 0x360 "MSCR_IO216,SIUL2 I/O pin multiplexed signal configuration register 216" bitfld.long 0x360 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x360 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x360 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x360 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x360 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x360 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x360 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x360 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x360 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x360 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x360 0.--7. 1. "SSS,Source Signal Select" line.long 0x364 "MSCR_IO217,SIUL2 I/O pin multiplexed signal configuration register 217" bitfld.long 0x364 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x364 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x364 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x364 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x364 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x364 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x364 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x364 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x364 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x364 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x364 0.--7. 1. "SSS,Source Signal Select" line.long 0x368 "MSCR_IO218,SIUL2 I/O pin multiplexed signal configuration register 218" bitfld.long 0x368 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x368 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x368 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x368 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x368 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x368 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x368 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x368 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x368 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x368 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x368 0.--7. 1. "SSS,Source Signal Select" line.long 0x36C "MSCR_IO219,SIUL2 I/O pin multiplexed signal configuration register 219" bitfld.long 0x36C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x36C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x36C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x36C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x36C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x36C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x36C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x36C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x36C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x36C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x36C 0.--7. 1. "SSS,Source Signal Select" line.long 0x370 "MSCR_IO220,SIUL2 I/O pin multiplexed signal configuration register 220" bitfld.long 0x370 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x370 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x370 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x370 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x370 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x370 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x370 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x370 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x370 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x370 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x370 0.--7. 1. "SSS,Source Signal Select" line.long 0x374 "MSCR_IO221,SIUL2 I/O pin multiplexed signal configuration register 221" bitfld.long 0x374 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x374 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x374 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x374 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x374 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x374 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x374 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x374 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x374 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x374 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x374 0.--7. 1. "SSS,Source Signal Select" line.long 0x378 "MSCR_IO222,SIUL2 I/O pin multiplexed signal configuration register 222" bitfld.long 0x378 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x378 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x378 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x378 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x378 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x378 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x378 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x378 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x378 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x378 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x378 0.--7. 1. "SSS,Source Signal Select" line.long 0x37C "MSCR_IO223,SIUL2 I/O pin multiplexed signal configuration register 223" bitfld.long 0x37C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x37C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x37C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x37C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x37C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x37C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x37C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x37C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x37C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x37C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x37C 0.--7. 1. "SSS,Source Signal Select" line.long 0x380 "MSCR_IO224,SIUL2 I/O pin multiplexed signal configuration register 224" bitfld.long 0x380 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x380 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x380 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x380 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x380 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x380 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x380 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x380 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x380 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x380 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x380 0.--7. 1. "SSS,Source Signal Select" line.long 0x384 "MSCR_IO225,SIUL2 I/O pin multiplexed signal configuration register 225" bitfld.long 0x384 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x384 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x384 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x384 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x384 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x384 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x384 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x384 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x384 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x384 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x384 0.--7. 1. "SSS,Source Signal Select" line.long 0x388 "MSCR_IO226,SIUL2 I/O pin multiplexed signal configuration register 226" bitfld.long 0x388 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x388 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x388 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x388 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x388 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x388 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x388 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x388 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x388 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x388 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x388 0.--7. 1. "SSS,Source Signal Select" line.long 0x38C "MSCR_IO227,SIUL2 I/O pin multiplexed signal configuration register 227" bitfld.long 0x38C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x38C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x38C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x38C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x38C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x38C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x38C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x38C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x38C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x38C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x38C 0.--7. 1. "SSS,Source Signal Select" line.long 0x390 "MSCR_IO228,SIUL2 I/O pin multiplexed signal configuration register 228" bitfld.long 0x390 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x390 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x390 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x390 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x390 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x390 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x390 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x390 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x390 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x390 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x390 0.--7. 1. "SSS,Source Signal Select" line.long 0x394 "MSCR_IO229,SIUL2 I/O pin multiplexed signal configuration register 229" bitfld.long 0x394 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x394 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x394 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x394 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x394 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x394 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x394 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x394 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x394 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x394 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x394 0.--7. 1. "SSS,Source Signal Select" line.long 0x398 "MSCR_IO230,SIUL2 I/O pin multiplexed signal configuration register 230" bitfld.long 0x398 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x398 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x398 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x398 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x398 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x398 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x398 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x398 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x398 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x398 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x398 0.--7. 1. "SSS,Source Signal Select" line.long 0x39C "MSCR_IO231,SIUL2 I/O pin multiplexed signal configuration register 231" bitfld.long 0x39C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x39C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x39C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x39C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x39C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x39C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x39C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x39C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x39C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x39C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x39C 0.--7. 1. "SSS,Source Signal Select" line.long 0x3A0 "MSCR_IO232,SIUL2 I/O pin multiplexed signal configuration register 232" bitfld.long 0x3A0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3A0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3A0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3A0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3A0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3A0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3A0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3A0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3A0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3A0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3A0 0.--7. 1. "SSS,Source Signal Select" line.long 0x3A4 "MSCR_IO233,SIUL2 I/O pin multiplexed signal configuration register 233" bitfld.long 0x3A4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3A4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3A4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3A4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3A4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3A4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3A4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3A4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3A4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3A4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3A4 0.--7. 1. "SSS,Source Signal Select" line.long 0x3A8 "MSCR_IO234,SIUL2 I/O pin multiplexed signal configuration register 234" bitfld.long 0x3A8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3A8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3A8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3A8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3A8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3A8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3A8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3A8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3A8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3A8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3A8 0.--7. 1. "SSS,Source Signal Select" line.long 0x3AC "MSCR_IO235,SIUL2 I/O pin multiplexed signal configuration register 235" bitfld.long 0x3AC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3AC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3AC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3AC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3AC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3AC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3AC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3AC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3AC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3AC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3AC 0.--7. 1. "SSS,Source Signal Select" line.long 0x3B0 "MSCR_IO236,SIUL2 I/O pin multiplexed signal configuration register 236" bitfld.long 0x3B0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3B0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3B0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3B0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3B0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3B0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3B0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3B0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3B0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3B0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3B0 0.--7. 1. "SSS,Source Signal Select" line.long 0x3B4 "MSCR_IO237,SIUL2 I/O pin multiplexed signal configuration register 237" bitfld.long 0x3B4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3B4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3B4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3B4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3B4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3B4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3B4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3B4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3B4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3B4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3B4 0.--7. 1. "SSS,Source Signal Select" line.long 0x3B8 "MSCR_IO238,SIUL2 I/O pin multiplexed signal configuration register 238" bitfld.long 0x3B8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3B8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3B8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3B8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3B8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3B8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3B8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3B8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3B8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3B8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3B8 0.--7. 1. "SSS,Source Signal Select" line.long 0x3BC "MSCR_IO239,SIUL2 I/O pin multiplexed signal configuration register 239" bitfld.long 0x3BC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3BC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3BC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3BC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3BC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3BC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3BC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3BC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3BC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3BC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3BC 0.--7. 1. "SSS,Source Signal Select" line.long 0x3C0 "MSCR_IO240,SIUL2 I/O pin multiplexed signal configuration register 240" bitfld.long 0x3C0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3C0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3C0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3C0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3C0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3C0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3C0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3C0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3C0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3C0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3C0 0.--7. 1. "SSS,Source Signal Select" line.long 0x3C4 "MSCR_IO241,SIUL2 I/O pin multiplexed signal configuration register 241" bitfld.long 0x3C4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3C4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3C4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3C4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3C4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3C4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3C4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3C4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3C4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3C4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3C4 0.--7. 1. "SSS,Source Signal Select" line.long 0x3C8 "MSCR_IO242,SIUL2 I/O pin multiplexed signal configuration register 242" bitfld.long 0x3C8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3C8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3C8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3C8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3C8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3C8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3C8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3C8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3C8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3C8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3C8 0.--7. 1. "SSS,Source Signal Select" line.long 0x3CC "MSCR_IO243,SIUL2 I/O pin multiplexed signal configuration register 243" bitfld.long 0x3CC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3CC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3CC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3CC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3CC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3CC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3CC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3CC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3CC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3CC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3CC 0.--7. 1. "SSS,Source Signal Select" line.long 0x3D0 "MSCR_IO244,SIUL2 I/O pin multiplexed signal configuration register 244" bitfld.long 0x3D0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3D0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3D0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3D0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3D0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3D0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3D0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3D0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3D0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3D0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3D0 0.--7. 1. "SSS,Source Signal Select" line.long 0x3D4 "MSCR_IO245,SIUL2 I/O pin multiplexed signal configuration register 245" bitfld.long 0x3D4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3D4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3D4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3D4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3D4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3D4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3D4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3D4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3D4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3D4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3D4 0.--7. 1. "SSS,Source Signal Select" line.long 0x3D8 "MSCR_IO246,SIUL2 I/O pin multiplexed signal configuration register 246" bitfld.long 0x3D8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3D8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3D8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3D8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3D8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3D8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3D8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3D8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3D8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3D8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3D8 0.--7. 1. "SSS,Source Signal Select" line.long 0x3DC "MSCR_IO247,SIUL2 I/O pin multiplexed signal configuration register 247" bitfld.long 0x3DC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3DC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3DC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3DC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3DC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3DC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3DC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3DC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3DC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3DC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3DC 0.--7. 1. "SSS,Source Signal Select" line.long 0x3E0 "MSCR_IO248,SIUL2 I/O pin multiplexed signal configuration register 248" bitfld.long 0x3E0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3E0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3E0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3E0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3E0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3E0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3E0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3E0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3E0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3E0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3E0 0.--7. 1. "SSS,Source Signal Select" line.long 0x3E4 "MSCR_IO249,SIUL2 I/O pin multiplexed signal configuration register 249" bitfld.long 0x3E4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3E4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3E4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3E4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3E4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3E4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3E4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3E4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3E4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3E4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3E4 0.--7. 1. "SSS,Source Signal Select" line.long 0x3E8 "MSCR_IO250,SIUL2 I/O pin multiplexed signal configuration register 250" bitfld.long 0x3E8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3E8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3E8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3E8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3E8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3E8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3E8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3E8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3E8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3E8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3E8 0.--7. 1. "SSS,Source Signal Select" line.long 0x3EC "MSCR_IO251,SIUL2 I/O pin multiplexed signal configuration register 251" bitfld.long 0x3EC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3EC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3EC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3EC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3EC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3EC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3EC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3EC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3EC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3EC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3EC 0.--7. 1. "SSS,Source Signal Select" line.long 0x3F0 "MSCR_IO252,SIUL2 I/O pin multiplexed signal configuration register 252" bitfld.long 0x3F0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3F0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3F0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3F0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3F0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3F0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3F0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3F0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3F0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3F0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3F0 0.--7. 1. "SSS,Source Signal Select" line.long 0x3F4 "MSCR_IO253,SIUL2 I/O pin multiplexed signal configuration register 253" bitfld.long 0x3F4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3F4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3F4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3F4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3F4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3F4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3F4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3F4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3F4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3F4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3F4 0.--7. 1. "SSS,Source Signal Select" line.long 0x3F8 "MSCR_IO254,SIUL2 I/O pin multiplexed signal configuration register 254" bitfld.long 0x3F8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3F8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3F8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3F8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3F8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3F8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3F8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3F8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3F8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3F8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3F8 0.--7. 1. "SSS,Source Signal Select" line.long 0x3FC "MSCR_IO255,SIUL2 I/O pin multiplexed signal configuration register 255" bitfld.long 0x3FC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3FC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3FC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3FC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3FC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3FC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3FC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3FC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3FC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3FC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3FC 0.--7. 1. "SSS,Source Signal Select" line.long 0x400 "MSCR_IO256,SIUL2 I/O pin multiplexed signal configuration register 256" bitfld.long 0x400 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x400 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x400 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x400 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x400 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x400 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x400 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x400 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x400 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x400 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x400 0.--7. 1. "SSS,Source Signal Select" line.long 0x404 "MSCR_IO257,SIUL2 I/O pin multiplexed signal configuration register 257" bitfld.long 0x404 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x404 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x404 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x404 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x404 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x404 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x404 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x404 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x404 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x404 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x404 0.--7. 1. "SSS,Source Signal Select" line.long 0x408 "MSCR_IO258,SIUL2 I/O pin multiplexed signal configuration register 258" bitfld.long 0x408 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x408 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x408 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x408 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x408 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x408 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x408 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x408 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x408 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x408 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x408 0.--7. 1. "SSS,Source Signal Select" line.long 0x40C "MSCR_IO259,SIUL2 I/O pin multiplexed signal configuration register 259" bitfld.long 0x40C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x40C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x40C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x40C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x40C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x40C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x40C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x40C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x40C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x40C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x40C 0.--7. 1. "SSS,Source Signal Select" line.long 0x410 "MSCR_IO260,SIUL2 I/O pin multiplexed signal configuration register 260" bitfld.long 0x410 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x410 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x410 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x410 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x410 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x410 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x410 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x410 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x410 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x410 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x410 0.--7. 1. "SSS,Source Signal Select" line.long 0x414 "MSCR_IO261,SIUL2 I/O pin multiplexed signal configuration register 261" bitfld.long 0x414 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x414 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x414 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x414 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x414 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x414 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x414 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x414 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x414 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x414 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x414 0.--7. 1. "SSS,Source Signal Select" line.long 0x418 "MSCR_IO262,SIUL2 I/O pin multiplexed signal configuration register 262" bitfld.long 0x418 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x418 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x418 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x418 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x418 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x418 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x418 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x418 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x418 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x418 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x418 0.--7. 1. "SSS,Source Signal Select" line.long 0x41C "MSCR_IO263,SIUL2 I/O pin multiplexed signal configuration register 263" bitfld.long 0x41C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x41C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x41C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x41C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x41C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x41C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x41C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x41C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x41C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x41C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x41C 0.--7. 1. "SSS,Source Signal Select" line.long 0x420 "MSCR_IO264,SIUL2 I/O pin multiplexed signal configuration register 264" bitfld.long 0x420 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x420 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x420 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x420 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x420 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x420 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x420 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x420 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x420 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x420 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x420 0.--7. 1. "SSS,Source Signal Select" line.long 0x424 "MSCR_IO265,SIUL2 I/O pin multiplexed signal configuration register 265" bitfld.long 0x424 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x424 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x424 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x424 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x424 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x424 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x424 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x424 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x424 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x424 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x424 0.--7. 1. "SSS,Source Signal Select" line.long 0x428 "MSCR_IO266,SIUL2 I/O pin multiplexed signal configuration register 266" bitfld.long 0x428 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x428 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x428 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x428 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x428 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x428 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x428 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x428 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x428 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x428 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x428 0.--7. 1. "SSS,Source Signal Select" line.long 0x42C "MSCR_IO267,SIUL2 I/O pin multiplexed signal configuration register 267" bitfld.long 0x42C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x42C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x42C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x42C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x42C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x42C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x42C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x42C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x42C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x42C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x42C 0.--7. 1. "SSS,Source Signal Select" line.long 0x430 "MSCR_IO268,SIUL2 I/O pin multiplexed signal configuration register 268" bitfld.long 0x430 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x430 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x430 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x430 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x430 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x430 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x430 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x430 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x430 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x430 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x430 0.--7. 1. "SSS,Source Signal Select" line.long 0x434 "MSCR_IO269,SIUL2 I/O pin multiplexed signal configuration register 269" bitfld.long 0x434 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x434 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x434 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x434 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x434 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x434 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x434 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x434 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x434 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x434 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x434 0.--7. 1. "SSS,Source Signal Select" line.long 0x438 "MSCR_IO270,SIUL2 I/O pin multiplexed signal configuration register 270" bitfld.long 0x438 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x438 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x438 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x438 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x438 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x438 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x438 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x438 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x438 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x438 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x438 0.--7. 1. "SSS,Source Signal Select" line.long 0x43C "MSCR_IO271,SIUL2 I/O pin multiplexed signal configuration register 271" bitfld.long 0x43C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x43C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x43C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x43C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x43C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x43C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x43C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x43C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x43C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x43C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x43C 0.--7. 1. "SSS,Source Signal Select" line.long 0x440 "MSCR_IO272,SIUL2 I/O pin multiplexed signal configuration register 272" bitfld.long 0x440 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x440 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x440 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x440 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x440 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x440 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x440 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x440 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x440 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x440 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x440 0.--7. 1. "SSS,Source Signal Select" line.long 0x444 "MSCR_IO273,SIUL2 I/O pin multiplexed signal configuration register 273" bitfld.long 0x444 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x444 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x444 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x444 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x444 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x444 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x444 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x444 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x444 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x444 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x444 0.--7. 1. "SSS,Source Signal Select" line.long 0x448 "MSCR_IO274,SIUL2 I/O pin multiplexed signal configuration register 274" bitfld.long 0x448 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x448 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x448 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x448 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x448 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x448 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x448 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x448 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x448 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x448 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x448 0.--7. 1. "SSS,Source Signal Select" line.long 0x44C "MSCR_IO275,SIUL2 I/O pin multiplexed signal configuration register 275" bitfld.long 0x44C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x44C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x44C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x44C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x44C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x44C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x44C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x44C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x44C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x44C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x44C 0.--7. 1. "SSS,Source Signal Select" line.long 0x450 "MSCR_IO276,SIUL2 I/O pin multiplexed signal configuration register 276" bitfld.long 0x450 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x450 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x450 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x450 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x450 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x450 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x450 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x450 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x450 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x450 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x450 0.--7. 1. "SSS,Source Signal Select" line.long 0x454 "MSCR_IO277,SIUL2 I/O pin multiplexed signal configuration register 277" bitfld.long 0x454 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x454 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x454 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x454 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x454 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x454 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x454 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x454 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x454 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x454 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x454 0.--7. 1. "SSS,Source Signal Select" line.long 0x458 "MSCR_IO278,SIUL2 I/O pin multiplexed signal configuration register 278" bitfld.long 0x458 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x458 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x458 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x458 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x458 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x458 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x458 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x458 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x458 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x458 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x458 0.--7. 1. "SSS,Source Signal Select" line.long 0x45C "MSCR_IO279,SIUL2 I/O pin multiplexed signal configuration register 279" bitfld.long 0x45C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x45C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x45C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x45C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x45C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x45C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x45C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x45C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x45C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x45C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x45C 0.--7. 1. "SSS,Source Signal Select" line.long 0x460 "MSCR_IO280,SIUL2 I/O pin multiplexed signal configuration register 280" bitfld.long 0x460 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x460 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x460 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x460 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x460 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x460 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x460 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x460 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x460 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x460 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x460 0.--7. 1. "SSS,Source Signal Select" line.long 0x464 "MSCR_IO281,SIUL2 I/O pin multiplexed signal configuration register 281" bitfld.long 0x464 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x464 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x464 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x464 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x464 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x464 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x464 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x464 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x464 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x464 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x464 0.--7. 1. "SSS,Source Signal Select" line.long 0x468 "MSCR_IO282,SIUL2 I/O pin multiplexed signal configuration register 282" bitfld.long 0x468 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x468 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x468 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x468 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x468 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x468 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x468 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x468 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x468 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x468 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x468 0.--7. 1. "SSS,Source Signal Select" line.long 0x46C "MSCR_IO283,SIUL2 I/O pin multiplexed signal configuration register 283" bitfld.long 0x46C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x46C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x46C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x46C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x46C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x46C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x46C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x46C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x46C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x46C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x46C 0.--7. 1. "SSS,Source Signal Select" line.long 0x470 "MSCR_IO284,SIUL2 I/O pin multiplexed signal configuration register 284" bitfld.long 0x470 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x470 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x470 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x470 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x470 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x470 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x470 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x470 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x470 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x470 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x470 0.--7. 1. "SSS,Source Signal Select" line.long 0x474 "MSCR_IO285,SIUL2 I/O pin multiplexed signal configuration register 285" bitfld.long 0x474 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x474 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x474 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x474 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x474 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x474 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x474 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x474 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x474 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x474 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x474 0.--7. 1. "SSS,Source Signal Select" line.long 0x478 "MSCR_IO286,SIUL2 I/O pin multiplexed signal configuration register 286" bitfld.long 0x478 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x478 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x478 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x478 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x478 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x478 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x478 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x478 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x478 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x478 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x478 0.--7. 1. "SSS,Source Signal Select" line.long 0x47C "MSCR_IO287,SIUL2 I/O pin multiplexed signal configuration register 287" bitfld.long 0x47C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x47C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x47C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x47C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x47C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x47C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x47C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x47C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x47C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x47C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x47C 0.--7. 1. "SSS,Source Signal Select" line.long 0x480 "MSCR_IO288,SIUL2 I/O pin multiplexed signal configuration register 288" bitfld.long 0x480 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x480 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x480 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x480 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x480 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x480 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x480 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x480 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x480 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x480 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x480 0.--7. 1. "SSS,Source Signal Select" line.long 0x484 "MSCR_IO289,SIUL2 I/O pin multiplexed signal configuration register 289" bitfld.long 0x484 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x484 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x484 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x484 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x484 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x484 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x484 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x484 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x484 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x484 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x484 0.--7. 1. "SSS,Source Signal Select" line.long 0x488 "MSCR_IO290,SIUL2 I/O pin multiplexed signal configuration register 290" bitfld.long 0x488 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x488 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x488 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x488 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x488 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x488 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x488 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x488 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x488 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x488 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x488 0.--7. 1. "SSS,Source Signal Select" line.long 0x48C "MSCR_IO291,SIUL2 I/O pin multiplexed signal configuration register 291" bitfld.long 0x48C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x48C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x48C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x48C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x48C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x48C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x48C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x48C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x48C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x48C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x48C 0.--7. 1. "SSS,Source Signal Select" line.long 0x490 "MSCR_IO292,SIUL2 I/O pin multiplexed signal configuration register 292" bitfld.long 0x490 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x490 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x490 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x490 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x490 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x490 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x490 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x490 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x490 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x490 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x490 0.--7. 1. "SSS,Source Signal Select" line.long 0x494 "MSCR_IO293,SIUL2 I/O pin multiplexed signal configuration register 293" bitfld.long 0x494 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x494 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x494 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x494 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x494 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x494 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x494 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x494 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x494 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x494 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x494 0.--7. 1. "SSS,Source Signal Select" line.long 0x498 "MSCR_IO294,SIUL2 I/O pin multiplexed signal configuration register 294" bitfld.long 0x498 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x498 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x498 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x498 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x498 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x498 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x498 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x498 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x498 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x498 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x498 0.--7. 1. "SSS,Source Signal Select" line.long 0x49C "MSCR_IO295,SIUL2 I/O pin multiplexed signal configuration register 295" bitfld.long 0x49C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x49C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x49C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x49C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x49C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x49C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x49C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x49C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x49C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x49C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x49C 0.--7. 1. "SSS,Source Signal Select" line.long 0x4A0 "MSCR_IO296,SIUL2 I/O pin multiplexed signal configuration register 296" bitfld.long 0x4A0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4A0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4A0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4A0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4A0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4A0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4A0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4A0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4A0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4A0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4A0 0.--7. 1. "SSS,Source Signal Select" line.long 0x4A4 "MSCR_IO297,SIUL2 I/O pin multiplexed signal configuration register 297" bitfld.long 0x4A4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4A4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4A4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4A4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4A4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4A4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4A4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4A4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4A4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4A4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4A4 0.--7. 1. "SSS,Source Signal Select" line.long 0x4A8 "MSCR_IO298,SIUL2 I/O pin multiplexed signal configuration register 298" bitfld.long 0x4A8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4A8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4A8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4A8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4A8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4A8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4A8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4A8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4A8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4A8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4A8 0.--7. 1. "SSS,Source Signal Select" line.long 0x4AC "MSCR_IO299,SIUL2 I/O pin multiplexed signal configuration register 299" bitfld.long 0x4AC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4AC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4AC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4AC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4AC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4AC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4AC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4AC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4AC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4AC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4AC 0.--7. 1. "SSS,Source Signal Select" line.long 0x4B0 "MSCR_IO300,SIUL2 I/O pin multiplexed signal configuration register 300" bitfld.long 0x4B0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4B0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4B0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4B0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4B0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4B0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4B0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4B0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4B0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4B0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4B0 0.--7. 1. "SSS,Source Signal Select" line.long 0x4B4 "MSCR_IO301,SIUL2 I/O pin multiplexed signal configuration register 301" bitfld.long 0x4B4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4B4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4B4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4B4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4B4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4B4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4B4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4B4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4B4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4B4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4B4 0.--7. 1. "SSS,Source Signal Select" line.long 0x4B8 "MSCR_IO302,SIUL2 I/O pin multiplexed signal configuration register 302" bitfld.long 0x4B8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4B8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4B8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4B8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4B8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4B8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4B8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4B8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4B8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4B8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4B8 0.--7. 1. "SSS,Source Signal Select" line.long 0x4BC "MSCR_IO303,SIUL2 I/O pin multiplexed signal configuration register 303" bitfld.long 0x4BC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4BC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4BC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4BC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4BC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4BC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4BC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4BC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4BC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4BC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4BC 0.--7. 1. "SSS,Source Signal Select" line.long 0x4C0 "MSCR_IO304,SIUL2 I/O pin multiplexed signal configuration register 304" bitfld.long 0x4C0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4C0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4C0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4C0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4C0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4C0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4C0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4C0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4C0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4C0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4C0 0.--7. 1. "SSS,Source Signal Select" line.long 0x4C4 "MSCR_IO305,SIUL2 I/O pin multiplexed signal configuration register 305" bitfld.long 0x4C4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4C4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4C4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4C4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4C4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4C4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4C4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4C4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4C4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4C4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4C4 0.--7. 1. "SSS,Source Signal Select" line.long 0x4C8 "MSCR_IO306,SIUL2 I/O pin multiplexed signal configuration register 306" bitfld.long 0x4C8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4C8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4C8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4C8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4C8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4C8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4C8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4C8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4C8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4C8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4C8 0.--7. 1. "SSS,Source Signal Select" line.long 0x4CC "MSCR_IO307,SIUL2 I/O pin multiplexed signal configuration register 307" bitfld.long 0x4CC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4CC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4CC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4CC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4CC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4CC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4CC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4CC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4CC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4CC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4CC 0.--7. 1. "SSS,Source Signal Select" line.long 0x4D0 "MSCR_IO308,SIUL2 I/O pin multiplexed signal configuration register 308" bitfld.long 0x4D0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4D0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4D0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4D0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4D0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4D0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4D0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4D0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4D0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4D0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4D0 0.--7. 1. "SSS,Source Signal Select" line.long 0x4D4 "MSCR_IO309,SIUL2 I/O pin multiplexed signal configuration register 309" bitfld.long 0x4D4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4D4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4D4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4D4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4D4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4D4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4D4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4D4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4D4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4D4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4D4 0.--7. 1. "SSS,Source Signal Select" line.long 0x4D8 "MSCR_IO310,SIUL2 I/O pin multiplexed signal configuration register 310" bitfld.long 0x4D8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4D8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4D8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4D8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4D8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4D8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4D8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4D8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4D8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4D8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4D8 0.--7. 1. "SSS,Source Signal Select" line.long 0x4DC "MSCR_IO311,SIUL2 I/O pin multiplexed signal configuration register 311" bitfld.long 0x4DC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4DC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4DC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4DC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4DC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4DC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4DC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4DC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4DC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4DC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4DC 0.--7. 1. "SSS,Source Signal Select" line.long 0x4E0 "MSCR_IO312,SIUL2 I/O pin multiplexed signal configuration register 312" bitfld.long 0x4E0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4E0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4E0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4E0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4E0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4E0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4E0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4E0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4E0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4E0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4E0 0.--7. 1. "SSS,Source Signal Select" line.long 0x4E4 "MSCR_IO313,SIUL2 I/O pin multiplexed signal configuration register 313" bitfld.long 0x4E4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4E4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4E4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4E4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4E4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4E4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4E4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4E4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4E4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4E4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4E4 0.--7. 1. "SSS,Source Signal Select" line.long 0x4E8 "MSCR_IO314,SIUL2 I/O pin multiplexed signal configuration register 314" bitfld.long 0x4E8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4E8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4E8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4E8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4E8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4E8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4E8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4E8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4E8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4E8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4E8 0.--7. 1. "SSS,Source Signal Select" line.long 0x4EC "MSCR_IO315,SIUL2 I/O pin multiplexed signal configuration register 315" bitfld.long 0x4EC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4EC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4EC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4EC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4EC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4EC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4EC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4EC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4EC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4EC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4EC 0.--7. 1. "SSS,Source Signal Select" line.long 0x4F0 "MSCR_IO316,SIUL2 I/O pin multiplexed signal configuration register 316" bitfld.long 0x4F0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4F0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4F0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4F0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4F0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4F0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4F0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4F0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4F0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4F0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4F0 0.--7. 1. "SSS,Source Signal Select" line.long 0x4F4 "MSCR_IO317,SIUL2 I/O pin multiplexed signal configuration register 317" bitfld.long 0x4F4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4F4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4F4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4F4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4F4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4F4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4F4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4F4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4F4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4F4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4F4 0.--7. 1. "SSS,Source Signal Select" line.long 0x4F8 "MSCR_IO318,SIUL2 I/O pin multiplexed signal configuration register 318" bitfld.long 0x4F8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4F8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4F8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4F8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4F8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4F8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4F8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4F8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4F8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4F8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4F8 0.--7. 1. "SSS,Source Signal Select" line.long 0x4FC "MSCR_IO319,SIUL2 I/O pin multiplexed signal configuration register 319" bitfld.long 0x4FC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4FC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4FC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4FC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4FC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4FC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4FC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4FC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4FC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4FC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4FC 0.--7. 1. "SSS,Source Signal Select" line.long 0x500 "MSCR_IO320,SIUL2 I/O pin multiplexed signal configuration register 320" bitfld.long 0x500 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x500 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x500 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x500 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x500 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x500 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x500 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x500 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x500 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x500 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x500 0.--7. 1. "SSS,Source Signal Select" line.long 0x504 "MSCR_IO321,SIUL2 I/O pin multiplexed signal configuration register 321" bitfld.long 0x504 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x504 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x504 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x504 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x504 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x504 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x504 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x504 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x504 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x504 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x504 0.--7. 1. "SSS,Source Signal Select" line.long 0x508 "MSCR_IO322,SIUL2 I/O pin multiplexed signal configuration register 322" bitfld.long 0x508 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x508 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x508 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x508 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x508 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x508 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x508 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x508 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x508 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x508 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x508 0.--7. 1. "SSS,Source Signal Select" line.long 0x50C "MSCR_IO323,SIUL2 I/O pin multiplexed signal configuration register 323" bitfld.long 0x50C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x50C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x50C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x50C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x50C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x50C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x50C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x50C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x50C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x50C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x50C 0.--7. 1. "SSS,Source Signal Select" line.long 0x510 "MSCR_IO324,SIUL2 I/O pin multiplexed signal configuration register 324" bitfld.long 0x510 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x510 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x510 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x510 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x510 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x510 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x510 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x510 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x510 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x510 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x510 0.--7. 1. "SSS,Source Signal Select" line.long 0x514 "MSCR_IO325,SIUL2 I/O pin multiplexed signal configuration register 325" bitfld.long 0x514 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x514 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x514 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x514 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x514 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x514 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x514 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x514 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x514 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x514 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x514 0.--7. 1. "SSS,Source Signal Select" line.long 0x518 "MSCR_IO326,SIUL2 I/O pin multiplexed signal configuration register 326" bitfld.long 0x518 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x518 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x518 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x518 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x518 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x518 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x518 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x518 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x518 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x518 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x518 0.--7. 1. "SSS,Source Signal Select" line.long 0x51C "MSCR_IO327,SIUL2 I/O pin multiplexed signal configuration register 327" bitfld.long 0x51C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x51C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x51C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x51C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x51C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x51C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x51C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x51C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x51C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x51C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x51C 0.--7. 1. "SSS,Source Signal Select" line.long 0x520 "MSCR_IO328,SIUL2 I/O pin multiplexed signal configuration register 328" bitfld.long 0x520 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x520 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x520 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x520 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x520 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x520 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x520 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x520 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x520 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x520 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x520 0.--7. 1. "SSS,Source Signal Select" line.long 0x524 "MSCR_IO329,SIUL2 I/O pin multiplexed signal configuration register 329" bitfld.long 0x524 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x524 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x524 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x524 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x524 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x524 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x524 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x524 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x524 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x524 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x524 0.--7. 1. "SSS,Source Signal Select" line.long 0x528 "MSCR_IO330,SIUL2 I/O pin multiplexed signal configuration register 330" bitfld.long 0x528 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x528 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x528 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x528 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x528 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x528 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x528 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x528 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x528 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x528 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x528 0.--7. 1. "SSS,Source Signal Select" line.long 0x52C "MSCR_IO331,SIUL2 I/O pin multiplexed signal configuration register 331" bitfld.long 0x52C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x52C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x52C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x52C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x52C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x52C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x52C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x52C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x52C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x52C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x52C 0.--7. 1. "SSS,Source Signal Select" line.long 0x530 "MSCR_IO332,SIUL2 I/O pin multiplexed signal configuration register 332" bitfld.long 0x530 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x530 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x530 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x530 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x530 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x530 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x530 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x530 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x530 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x530 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x530 0.--7. 1. "SSS,Source Signal Select" line.long 0x534 "MSCR_IO333,SIUL2 I/O pin multiplexed signal configuration register 333" bitfld.long 0x534 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x534 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x534 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x534 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x534 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x534 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x534 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x534 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x534 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x534 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x534 0.--7. 1. "SSS,Source Signal Select" line.long 0x538 "MSCR_IO334,SIUL2 I/O pin multiplexed signal configuration register 334" bitfld.long 0x538 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x538 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x538 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x538 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x538 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x538 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x538 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x538 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x538 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x538 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x538 0.--7. 1. "SSS,Source Signal Select" line.long 0x53C "MSCR_IO335,SIUL2 I/O pin multiplexed signal configuration register 335" bitfld.long 0x53C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x53C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x53C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x53C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x53C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x53C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x53C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x53C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x53C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x53C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x53C 0.--7. 1. "SSS,Source Signal Select" line.long 0x540 "MSCR_IO336,SIUL2 I/O pin multiplexed signal configuration register 336" bitfld.long 0x540 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x540 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x540 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x540 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x540 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x540 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x540 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x540 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x540 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x540 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x540 0.--7. 1. "SSS,Source Signal Select" line.long 0x544 "MSCR_IO337,SIUL2 I/O pin multiplexed signal configuration register 337" bitfld.long 0x544 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x544 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x544 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x544 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x544 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x544 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x544 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x544 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x544 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x544 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x544 0.--7. 1. "SSS,Source Signal Select" line.long 0x548 "MSCR_IO338,SIUL2 I/O pin multiplexed signal configuration register 338" bitfld.long 0x548 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x548 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x548 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x548 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x548 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x548 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x548 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x548 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x548 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x548 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x548 0.--7. 1. "SSS,Source Signal Select" line.long 0x54C "MSCR_IO339,SIUL2 I/O pin multiplexed signal configuration register 339" bitfld.long 0x54C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x54C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x54C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x54C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x54C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x54C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x54C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x54C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x54C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x54C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x54C 0.--7. 1. "SSS,Source Signal Select" line.long 0x550 "MSCR_IO340,SIUL2 I/O pin multiplexed signal configuration register 340" bitfld.long 0x550 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x550 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x550 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x550 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x550 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x550 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x550 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x550 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x550 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x550 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x550 0.--7. 1. "SSS,Source Signal Select" line.long 0x554 "MSCR_IO341,SIUL2 I/O pin multiplexed signal configuration register 341" bitfld.long 0x554 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x554 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x554 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x554 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x554 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x554 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x554 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x554 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x554 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x554 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x554 0.--7. 1. "SSS,Source Signal Select" line.long 0x558 "MSCR_IO342,SIUL2 I/O pin multiplexed signal configuration register 342" bitfld.long 0x558 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x558 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x558 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x558 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x558 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x558 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x558 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x558 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x558 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x558 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x558 0.--7. 1. "SSS,Source Signal Select" line.long 0x55C "MSCR_IO343,SIUL2 I/O pin multiplexed signal configuration register 343" bitfld.long 0x55C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x55C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x55C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x55C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x55C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x55C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x55C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x55C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x55C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x55C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x55C 0.--7. 1. "SSS,Source Signal Select" line.long 0x560 "MSCR_IO344,SIUL2 I/O pin multiplexed signal configuration register 344" bitfld.long 0x560 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x560 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x560 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x560 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x560 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x560 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x560 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x560 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x560 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x560 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x560 0.--7. 1. "SSS,Source Signal Select" line.long 0x564 "MSCR_IO345,SIUL2 I/O pin multiplexed signal configuration register 345" bitfld.long 0x564 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x564 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x564 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x564 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x564 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x564 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x564 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x564 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x564 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x564 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x564 0.--7. 1. "SSS,Source Signal Select" line.long 0x568 "MSCR_IO346,SIUL2 I/O pin multiplexed signal configuration register 346" bitfld.long 0x568 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x568 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x568 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x568 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x568 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x568 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x568 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x568 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x568 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x568 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x568 0.--7. 1. "SSS,Source Signal Select" line.long 0x56C "MSCR_IO347,SIUL2 I/O pin multiplexed signal configuration register 347" bitfld.long 0x56C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x56C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x56C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x56C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x56C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x56C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x56C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x56C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x56C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x56C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x56C 0.--7. 1. "SSS,Source Signal Select" line.long 0x570 "MSCR_IO348,SIUL2 I/O pin multiplexed signal configuration register 348" bitfld.long 0x570 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x570 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x570 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x570 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x570 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x570 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x570 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x570 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x570 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x570 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x570 0.--7. 1. "SSS,Source Signal Select" line.long 0x574 "MSCR_IO349,SIUL2 I/O pin multiplexed signal configuration register 349" bitfld.long 0x574 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x574 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x574 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x574 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x574 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x574 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x574 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x574 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x574 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x574 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x574 0.--7. 1. "SSS,Source Signal Select" line.long 0x578 "MSCR_IO350,SIUL2 I/O pin multiplexed signal configuration register 350" bitfld.long 0x578 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x578 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x578 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x578 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x578 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x578 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x578 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x578 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x578 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x578 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x578 0.--7. 1. "SSS,Source Signal Select" line.long 0x57C "MSCR_IO351,SIUL2 I/O pin multiplexed signal configuration register 351" bitfld.long 0x57C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x57C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x57C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x57C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x57C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x57C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x57C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x57C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x57C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x57C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x57C 0.--7. 1. "SSS,Source Signal Select" line.long 0x580 "MSCR_IO352,SIUL2 I/O pin multiplexed signal configuration register 352" bitfld.long 0x580 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x580 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x580 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x580 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x580 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x580 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x580 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x580 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x580 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x580 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x580 0.--7. 1. "SSS,Source Signal Select" line.long 0x584 "MSCR_IO353,SIUL2 I/O pin multiplexed signal configuration register 353" bitfld.long 0x584 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x584 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x584 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x584 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x584 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x584 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x584 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x584 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x584 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x584 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x584 0.--7. 1. "SSS,Source Signal Select" line.long 0x588 "MSCR_IO354,SIUL2 I/O pin multiplexed signal configuration register 354" bitfld.long 0x588 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x588 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x588 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x588 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x588 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x588 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x588 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x588 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x588 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x588 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x588 0.--7. 1. "SSS,Source Signal Select" line.long 0x58C "MSCR_IO355,SIUL2 I/O pin multiplexed signal configuration register 355" bitfld.long 0x58C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x58C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x58C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x58C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x58C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x58C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x58C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x58C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x58C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x58C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x58C 0.--7. 1. "SSS,Source Signal Select" line.long 0x590 "MSCR_IO356,SIUL2 I/O pin multiplexed signal configuration register 356" bitfld.long 0x590 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x590 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x590 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x590 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x590 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x590 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x590 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x590 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x590 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x590 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x590 0.--7. 1. "SSS,Source Signal Select" line.long 0x594 "MSCR_IO357,SIUL2 I/O pin multiplexed signal configuration register 357" bitfld.long 0x594 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x594 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x594 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x594 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x594 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x594 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x594 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x594 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x594 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x594 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x594 0.--7. 1. "SSS,Source Signal Select" line.long 0x598 "MSCR_IO358,SIUL2 I/O pin multiplexed signal configuration register 358" bitfld.long 0x598 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x598 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x598 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x598 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x598 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x598 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x598 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x598 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x598 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x598 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x598 0.--7. 1. "SSS,Source Signal Select" line.long 0x59C "MSCR_IO359,SIUL2 I/O pin multiplexed signal configuration register 359" bitfld.long 0x59C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x59C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x59C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x59C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x59C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x59C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x59C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x59C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x59C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x59C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x59C 0.--7. 1. "SSS,Source Signal Select" line.long 0x5A0 "MSCR_IO360,SIUL2 I/O pin multiplexed signal configuration register 360" bitfld.long 0x5A0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5A0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5A0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5A0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5A0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5A0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5A0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5A0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5A0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5A0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5A0 0.--7. 1. "SSS,Source Signal Select" line.long 0x5A4 "MSCR_IO361,SIUL2 I/O pin multiplexed signal configuration register 361" bitfld.long 0x5A4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5A4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5A4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5A4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5A4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5A4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5A4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5A4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5A4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5A4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5A4 0.--7. 1. "SSS,Source Signal Select" line.long 0x5A8 "MSCR_IO362,SIUL2 I/O pin multiplexed signal configuration register 362" bitfld.long 0x5A8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5A8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5A8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5A8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5A8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5A8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5A8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5A8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5A8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5A8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5A8 0.--7. 1. "SSS,Source Signal Select" line.long 0x5AC "MSCR_IO363,SIUL2 I/O pin multiplexed signal configuration register 363" bitfld.long 0x5AC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5AC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5AC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5AC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5AC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5AC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5AC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5AC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5AC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5AC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5AC 0.--7. 1. "SSS,Source Signal Select" line.long 0x5B0 "MSCR_IO364,SIUL2 I/O pin multiplexed signal configuration register 364" bitfld.long 0x5B0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5B0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5B0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5B0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5B0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5B0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5B0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5B0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5B0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5B0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5B0 0.--7. 1. "SSS,Source Signal Select" line.long 0x5B4 "MSCR_IO365,SIUL2 I/O pin multiplexed signal configuration register 365" bitfld.long 0x5B4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5B4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5B4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5B4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5B4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5B4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5B4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5B4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5B4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5B4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5B4 0.--7. 1. "SSS,Source Signal Select" line.long 0x5B8 "MSCR_IO366,SIUL2 I/O pin multiplexed signal configuration register 366" bitfld.long 0x5B8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5B8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5B8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5B8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5B8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5B8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5B8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5B8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5B8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5B8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5B8 0.--7. 1. "SSS,Source Signal Select" line.long 0x5BC "MSCR_IO367,SIUL2 I/O pin multiplexed signal configuration register 367" bitfld.long 0x5BC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5BC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5BC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5BC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5BC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5BC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5BC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5BC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5BC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5BC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5BC 0.--7. 1. "SSS,Source Signal Select" line.long 0x5C0 "MSCR_IO368,SIUL2 I/O pin multiplexed signal configuration register 368" bitfld.long 0x5C0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5C0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5C0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5C0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5C0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5C0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5C0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5C0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5C0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5C0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5C0 0.--7. 1. "SSS,Source Signal Select" line.long 0x5C4 "MSCR_IO369,SIUL2 I/O pin multiplexed signal configuration register 369" bitfld.long 0x5C4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5C4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5C4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5C4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5C4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5C4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5C4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5C4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5C4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5C4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5C4 0.--7. 1. "SSS,Source Signal Select" line.long 0x5C8 "MSCR_IO370,SIUL2 I/O pin multiplexed signal configuration register 370" bitfld.long 0x5C8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5C8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5C8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5C8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5C8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5C8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5C8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5C8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5C8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5C8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5C8 0.--7. 1. "SSS,Source Signal Select" line.long 0x5CC "MSCR_IO371,SIUL2 I/O pin multiplexed signal configuration register 371" bitfld.long 0x5CC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5CC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5CC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5CC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5CC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5CC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5CC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5CC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5CC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5CC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5CC 0.--7. 1. "SSS,Source Signal Select" line.long 0x5D0 "MSCR_IO372,SIUL2 I/O pin multiplexed signal configuration register 372" bitfld.long 0x5D0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5D0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5D0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5D0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5D0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5D0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5D0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5D0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5D0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5D0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5D0 0.--7. 1. "SSS,Source Signal Select" line.long 0x5D4 "MSCR_IO373,SIUL2 I/O pin multiplexed signal configuration register 373" bitfld.long 0x5D4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5D4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5D4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5D4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5D4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5D4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5D4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5D4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5D4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5D4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5D4 0.--7. 1. "SSS,Source Signal Select" line.long 0x5D8 "MSCR_IO374,SIUL2 I/O pin multiplexed signal configuration register 374" bitfld.long 0x5D8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5D8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5D8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5D8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5D8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5D8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5D8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5D8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5D8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5D8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5D8 0.--7. 1. "SSS,Source Signal Select" line.long 0x5DC "MSCR_IO375,SIUL2 I/O pin multiplexed signal configuration register 375" bitfld.long 0x5DC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5DC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5DC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5DC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5DC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5DC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5DC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5DC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5DC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5DC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5DC 0.--7. 1. "SSS,Source Signal Select" line.long 0x5E0 "MSCR_IO376,SIUL2 I/O pin multiplexed signal configuration register 376" bitfld.long 0x5E0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5E0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5E0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5E0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5E0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5E0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5E0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5E0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5E0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5E0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5E0 0.--7. 1. "SSS,Source Signal Select" line.long 0x5E4 "MSCR_IO377,SIUL2 I/O pin multiplexed signal configuration register 377" bitfld.long 0x5E4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5E4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5E4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5E4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5E4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5E4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5E4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5E4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5E4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5E4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5E4 0.--7. 1. "SSS,Source Signal Select" line.long 0x5E8 "MSCR_IO378,SIUL2 I/O pin multiplexed signal configuration register 378" bitfld.long 0x5E8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5E8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5E8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5E8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5E8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5E8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5E8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5E8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5E8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5E8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5E8 0.--7. 1. "SSS,Source Signal Select" line.long 0x5EC "MSCR_IO379,SIUL2 I/O pin multiplexed signal configuration register 379" bitfld.long 0x5EC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5EC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5EC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5EC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5EC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5EC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5EC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5EC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5EC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5EC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5EC 0.--7. 1. "SSS,Source Signal Select" line.long 0x5F0 "MSCR_IO380,SIUL2 I/O pin multiplexed signal configuration register 380" bitfld.long 0x5F0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5F0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5F0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5F0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5F0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5F0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5F0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5F0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5F0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5F0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5F0 0.--7. 1. "SSS,Source Signal Select" line.long 0x5F4 "MSCR_IO381,SIUL2 I/O pin multiplexed signal configuration register 381" bitfld.long 0x5F4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5F4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5F4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5F4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5F4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5F4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5F4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5F4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5F4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5F4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5F4 0.--7. 1. "SSS,Source Signal Select" line.long 0x5F8 "MSCR_IO382,SIUL2 I/O pin multiplexed signal configuration register 382" bitfld.long 0x5F8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5F8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5F8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5F8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5F8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5F8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5F8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5F8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5F8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5F8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5F8 0.--7. 1. "SSS,Source Signal Select" line.long 0x5FC "MSCR_IO383,SIUL2 I/O pin multiplexed signal configuration register 383" bitfld.long 0x5FC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5FC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5FC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5FC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5FC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5FC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5FC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5FC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5FC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5FC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5FC 0.--7. 1. "SSS,Source Signal Select" line.long 0x600 "MSCR_IO384,SIUL2 I/O pin multiplexed signal configuration register 384" bitfld.long 0x600 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x600 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x600 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x600 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x600 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x600 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x600 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x600 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x600 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x600 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x600 0.--7. 1. "SSS,Source Signal Select" line.long 0x604 "MSCR_IO385,SIUL2 I/O pin multiplexed signal configuration register 385" bitfld.long 0x604 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x604 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x604 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x604 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x604 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x604 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x604 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x604 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x604 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x604 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x604 0.--7. 1. "SSS,Source Signal Select" line.long 0x608 "MSCR_IO386,SIUL2 I/O pin multiplexed signal configuration register 386" bitfld.long 0x608 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x608 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x608 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x608 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x608 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x608 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x608 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x608 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x608 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x608 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x608 0.--7. 1. "SSS,Source Signal Select" line.long 0x60C "MSCR_IO387,SIUL2 I/O pin multiplexed signal configuration register 387" bitfld.long 0x60C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x60C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x60C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x60C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x60C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x60C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x60C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x60C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x60C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x60C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x60C 0.--7. 1. "SSS,Source Signal Select" line.long 0x610 "MSCR_IO388,SIUL2 I/O pin multiplexed signal configuration register 388" bitfld.long 0x610 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x610 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x610 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x610 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x610 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x610 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x610 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x610 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x610 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x610 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x610 0.--7. 1. "SSS,Source Signal Select" line.long 0x614 "MSCR_IO389,SIUL2 I/O pin multiplexed signal configuration register 389" bitfld.long 0x614 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x614 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x614 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x614 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x614 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x614 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x614 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x614 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x614 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x614 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x614 0.--7. 1. "SSS,Source Signal Select" line.long 0x618 "MSCR_IO390,SIUL2 I/O pin multiplexed signal configuration register 390" bitfld.long 0x618 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x618 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x618 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x618 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x618 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x618 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x618 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x618 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x618 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x618 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x618 0.--7. 1. "SSS,Source Signal Select" line.long 0x61C "MSCR_IO391,SIUL2 I/O pin multiplexed signal configuration register 391" bitfld.long 0x61C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x61C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x61C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x61C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x61C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x61C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x61C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x61C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x61C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x61C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x61C 0.--7. 1. "SSS,Source Signal Select" line.long 0x620 "MSCR_IO392,SIUL2 I/O pin multiplexed signal configuration register 392" bitfld.long 0x620 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x620 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x620 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x620 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x620 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x620 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x620 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x620 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x620 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x620 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x620 0.--7. 1. "SSS,Source Signal Select" line.long 0x624 "MSCR_IO393,SIUL2 I/O pin multiplexed signal configuration register 393" bitfld.long 0x624 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x624 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x624 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x624 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x624 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x624 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x624 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x624 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x624 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x624 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x624 0.--7. 1. "SSS,Source Signal Select" line.long 0x628 "MSCR_IO394,SIUL2 I/O pin multiplexed signal configuration register 394" bitfld.long 0x628 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x628 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x628 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x628 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x628 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x628 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x628 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x628 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x628 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x628 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x628 0.--7. 1. "SSS,Source Signal Select" line.long 0x62C "MSCR_IO395,SIUL2 I/O pin multiplexed signal configuration register 395" bitfld.long 0x62C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x62C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x62C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x62C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x62C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x62C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x62C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x62C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x62C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x62C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x62C 0.--7. 1. "SSS,Source Signal Select" line.long 0x630 "MSCR_IO396,SIUL2 I/O pin multiplexed signal configuration register 396" bitfld.long 0x630 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x630 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x630 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x630 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x630 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x630 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x630 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x630 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x630 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x630 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x630 0.--7. 1. "SSS,Source Signal Select" line.long 0x634 "MSCR_IO397,SIUL2 I/O pin multiplexed signal configuration register 397" bitfld.long 0x634 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x634 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x634 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x634 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x634 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x634 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x634 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x634 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x634 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x634 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x634 0.--7. 1. "SSS,Source Signal Select" line.long 0x638 "MSCR_IO398,SIUL2 I/O pin multiplexed signal configuration register 398" bitfld.long 0x638 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x638 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x638 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x638 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x638 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x638 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x638 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x638 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x638 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x638 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x638 0.--7. 1. "SSS,Source Signal Select" line.long 0x63C "MSCR_IO399,SIUL2 I/O pin multiplexed signal configuration register 399" bitfld.long 0x63C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x63C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x63C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x63C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x63C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x63C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x63C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x63C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x63C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x63C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x63C 0.--7. 1. "SSS,Source Signal Select" line.long 0x640 "MSCR_IO400,SIUL2 I/O pin multiplexed signal configuration register 400" bitfld.long 0x640 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x640 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x640 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x640 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x640 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x640 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x640 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x640 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x640 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x640 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x640 0.--7. 1. "SSS,Source Signal Select" line.long 0x644 "MSCR_IO401,SIUL2 I/O pin multiplexed signal configuration register 401" bitfld.long 0x644 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x644 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x644 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x644 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x644 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x644 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x644 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x644 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x644 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x644 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x644 0.--7. 1. "SSS,Source Signal Select" line.long 0x648 "MSCR_IO402,SIUL2 I/O pin multiplexed signal configuration register 402" bitfld.long 0x648 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x648 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x648 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x648 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x648 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x648 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x648 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x648 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x648 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x648 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x648 0.--7. 1. "SSS,Source Signal Select" line.long 0x64C "MSCR_IO403,SIUL2 I/O pin multiplexed signal configuration register 403" bitfld.long 0x64C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x64C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x64C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x64C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x64C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x64C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x64C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x64C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x64C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x64C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x64C 0.--7. 1. "SSS,Source Signal Select" line.long 0x650 "MSCR_IO404,SIUL2 I/O pin multiplexed signal configuration register 404" bitfld.long 0x650 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x650 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x650 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x650 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x650 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x650 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x650 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x650 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x650 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x650 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x650 0.--7. 1. "SSS,Source Signal Select" line.long 0x654 "MSCR_IO405,SIUL2 I/O pin multiplexed signal configuration register 405" bitfld.long 0x654 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x654 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x654 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x654 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x654 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x654 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x654 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x654 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x654 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x654 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x654 0.--7. 1. "SSS,Source Signal Select" line.long 0x658 "MSCR_IO406,SIUL2 I/O pin multiplexed signal configuration register 406" bitfld.long 0x658 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x658 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x658 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x658 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x658 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x658 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x658 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x658 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x658 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x658 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x658 0.--7. 1. "SSS,Source Signal Select" line.long 0x65C "MSCR_IO407,SIUL2 I/O pin multiplexed signal configuration register 407" bitfld.long 0x65C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x65C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x65C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x65C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x65C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x65C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x65C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x65C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x65C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x65C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x65C 0.--7. 1. "SSS,Source Signal Select" line.long 0x660 "MSCR_IO408,SIUL2 I/O pin multiplexed signal configuration register 408" bitfld.long 0x660 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x660 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x660 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x660 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x660 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x660 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x660 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x660 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x660 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x660 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x660 0.--7. 1. "SSS,Source Signal Select" line.long 0x664 "MSCR_IO409,SIUL2 I/O pin multiplexed signal configuration register 409" bitfld.long 0x664 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x664 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x664 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x664 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x664 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x664 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x664 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x664 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x664 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x664 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x664 0.--7. 1. "SSS,Source Signal Select" line.long 0x668 "MSCR_IO410,SIUL2 I/O pin multiplexed signal configuration register 410" bitfld.long 0x668 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x668 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x668 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x668 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x668 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x668 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x668 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x668 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x668 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x668 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x668 0.--7. 1. "SSS,Source Signal Select" line.long 0x66C "MSCR_IO411,SIUL2 I/O pin multiplexed signal configuration register 411" bitfld.long 0x66C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x66C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x66C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x66C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x66C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x66C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x66C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x66C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x66C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x66C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x66C 0.--7. 1. "SSS,Source Signal Select" line.long 0x670 "MSCR_IO412,SIUL2 I/O pin multiplexed signal configuration register 412" bitfld.long 0x670 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x670 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x670 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x670 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x670 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x670 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x670 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x670 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x670 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x670 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x670 0.--7. 1. "SSS,Source Signal Select" line.long 0x674 "MSCR_IO413,SIUL2 I/O pin multiplexed signal configuration register 413" bitfld.long 0x674 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x674 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x674 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x674 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x674 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x674 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x674 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x674 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x674 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x674 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x674 0.--7. 1. "SSS,Source Signal Select" line.long 0x678 "MSCR_IO414,SIUL2 I/O pin multiplexed signal configuration register 414" bitfld.long 0x678 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x678 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x678 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x678 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x678 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x678 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x678 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x678 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x678 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x678 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x678 0.--7. 1. "SSS,Source Signal Select" line.long 0x67C "MSCR_IO415,SIUL2 I/O pin multiplexed signal configuration register 415" bitfld.long 0x67C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x67C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x67C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x67C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x67C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x67C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x67C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x67C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x67C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x67C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x67C 0.--7. 1. "SSS,Source Signal Select" line.long 0x680 "MSCR_IO416,SIUL2 I/O pin multiplexed signal configuration register 416" bitfld.long 0x680 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x680 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x680 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x680 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x680 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x680 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x680 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x680 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x680 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x680 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x680 0.--7. 1. "SSS,Source Signal Select" line.long 0x684 "MSCR_IO417,SIUL2 I/O pin multiplexed signal configuration register 417" bitfld.long 0x684 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x684 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x684 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x684 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x684 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x684 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x684 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x684 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x684 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x684 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x684 0.--7. 1. "SSS,Source Signal Select" line.long 0x688 "MSCR_IO418,SIUL2 I/O pin multiplexed signal configuration register 418" bitfld.long 0x688 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x688 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x688 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x688 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x688 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x688 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x688 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x688 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x688 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x688 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x688 0.--7. 1. "SSS,Source Signal Select" line.long 0x68C "MSCR_IO419,SIUL2 I/O pin multiplexed signal configuration register 419" bitfld.long 0x68C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x68C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x68C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x68C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x68C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x68C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x68C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x68C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x68C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x68C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x68C 0.--7. 1. "SSS,Source Signal Select" line.long 0x690 "MSCR_IO420,SIUL2 I/O pin multiplexed signal configuration register 420" bitfld.long 0x690 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x690 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x690 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x690 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x690 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x690 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x690 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x690 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x690 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x690 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x690 0.--7. 1. "SSS,Source Signal Select" line.long 0x694 "MSCR_IO421,SIUL2 I/O pin multiplexed signal configuration register 421" bitfld.long 0x694 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x694 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x694 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x694 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x694 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x694 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x694 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x694 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x694 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x694 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x694 0.--7. 1. "SSS,Source Signal Select" line.long 0x698 "MSCR_IO422,SIUL2 I/O pin multiplexed signal configuration register 422" bitfld.long 0x698 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x698 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x698 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x698 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x698 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x698 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x698 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x698 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x698 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x698 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x698 0.--7. 1. "SSS,Source Signal Select" line.long 0x69C "MSCR_IO423,SIUL2 I/O pin multiplexed signal configuration register 423" bitfld.long 0x69C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x69C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x69C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x69C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x69C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x69C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x69C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x69C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x69C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x69C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x69C 0.--7. 1. "SSS,Source Signal Select" line.long 0x6A0 "MSCR_IO424,SIUL2 I/O pin multiplexed signal configuration register 424" bitfld.long 0x6A0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6A0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6A0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6A0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6A0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6A0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6A0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6A0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6A0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6A0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6A0 0.--7. 1. "SSS,Source Signal Select" line.long 0x6A4 "MSCR_IO425,SIUL2 I/O pin multiplexed signal configuration register 425" bitfld.long 0x6A4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6A4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6A4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6A4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6A4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6A4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6A4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6A4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6A4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6A4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6A4 0.--7. 1. "SSS,Source Signal Select" line.long 0x6A8 "MSCR_IO426,SIUL2 I/O pin multiplexed signal configuration register 426" bitfld.long 0x6A8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6A8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6A8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6A8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6A8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6A8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6A8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6A8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6A8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6A8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6A8 0.--7. 1. "SSS,Source Signal Select" line.long 0x6AC "MSCR_IO427,SIUL2 I/O pin multiplexed signal configuration register 427" bitfld.long 0x6AC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6AC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6AC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6AC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6AC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6AC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6AC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6AC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6AC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6AC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6AC 0.--7. 1. "SSS,Source Signal Select" line.long 0x6B0 "MSCR_IO428,SIUL2 I/O pin multiplexed signal configuration register 428" bitfld.long 0x6B0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6B0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6B0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6B0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6B0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6B0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6B0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6B0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6B0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6B0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6B0 0.--7. 1. "SSS,Source Signal Select" line.long 0x6B4 "MSCR_IO429,SIUL2 I/O pin multiplexed signal configuration register 429" bitfld.long 0x6B4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6B4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6B4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6B4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6B4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6B4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6B4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6B4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6B4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6B4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6B4 0.--7. 1. "SSS,Source Signal Select" line.long 0x6B8 "MSCR_IO430,SIUL2 I/O pin multiplexed signal configuration register 430" bitfld.long 0x6B8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6B8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6B8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6B8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6B8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6B8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6B8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6B8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6B8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6B8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6B8 0.--7. 1. "SSS,Source Signal Select" line.long 0x6BC "MSCR_IO431,SIUL2 I/O pin multiplexed signal configuration register 431" bitfld.long 0x6BC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6BC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6BC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6BC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6BC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6BC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6BC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6BC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6BC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6BC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6BC 0.--7. 1. "SSS,Source Signal Select" line.long 0x6C0 "MSCR_IO432,SIUL2 I/O pin multiplexed signal configuration register 432" bitfld.long 0x6C0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6C0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6C0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6C0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6C0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6C0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6C0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6C0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6C0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6C0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6C0 0.--7. 1. "SSS,Source Signal Select" line.long 0x6C4 "MSCR_IO433,SIUL2 I/O pin multiplexed signal configuration register 433" bitfld.long 0x6C4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6C4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6C4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6C4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6C4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6C4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6C4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6C4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6C4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6C4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6C4 0.--7. 1. "SSS,Source Signal Select" line.long 0x6C8 "MSCR_IO434,SIUL2 I/O pin multiplexed signal configuration register 434" bitfld.long 0x6C8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6C8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6C8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6C8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6C8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6C8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6C8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6C8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6C8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6C8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6C8 0.--7. 1. "SSS,Source Signal Select" line.long 0x6CC "MSCR_IO435,SIUL2 I/O pin multiplexed signal configuration register 435" bitfld.long 0x6CC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6CC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6CC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6CC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6CC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6CC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6CC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6CC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6CC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6CC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6CC 0.--7. 1. "SSS,Source Signal Select" line.long 0x6D0 "MSCR_IO436,SIUL2 I/O pin multiplexed signal configuration register 436" bitfld.long 0x6D0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6D0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6D0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6D0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6D0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6D0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6D0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6D0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6D0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6D0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6D0 0.--7. 1. "SSS,Source Signal Select" line.long 0x6D4 "MSCR_IO437,SIUL2 I/O pin multiplexed signal configuration register 437" bitfld.long 0x6D4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6D4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6D4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6D4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6D4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6D4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6D4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6D4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6D4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6D4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6D4 0.--7. 1. "SSS,Source Signal Select" line.long 0x6D8 "MSCR_IO438,SIUL2 I/O pin multiplexed signal configuration register 438" bitfld.long 0x6D8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6D8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6D8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6D8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6D8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6D8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6D8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6D8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6D8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6D8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6D8 0.--7. 1. "SSS,Source Signal Select" line.long 0x6DC "MSCR_IO439,SIUL2 I/O pin multiplexed signal configuration register 439" bitfld.long 0x6DC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6DC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6DC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6DC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6DC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6DC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6DC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6DC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6DC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6DC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6DC 0.--7. 1. "SSS,Source Signal Select" line.long 0x6E0 "MSCR_IO440,SIUL2 I/O pin multiplexed signal configuration register 440" bitfld.long 0x6E0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6E0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6E0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6E0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6E0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6E0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6E0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6E0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6E0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6E0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6E0 0.--7. 1. "SSS,Source Signal Select" line.long 0x6E4 "MSCR_IO441,SIUL2 I/O pin multiplexed signal configuration register 441" bitfld.long 0x6E4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6E4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6E4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6E4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6E4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6E4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6E4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6E4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6E4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6E4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6E4 0.--7. 1. "SSS,Source Signal Select" line.long 0x6E8 "MSCR_IO442,SIUL2 I/O pin multiplexed signal configuration register 442" bitfld.long 0x6E8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6E8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6E8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6E8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6E8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6E8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6E8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6E8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6E8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6E8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6E8 0.--7. 1. "SSS,Source Signal Select" line.long 0x6EC "MSCR_IO443,SIUL2 I/O pin multiplexed signal configuration register 443" bitfld.long 0x6EC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6EC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6EC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6EC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6EC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6EC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6EC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6EC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6EC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6EC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6EC 0.--7. 1. "SSS,Source Signal Select" line.long 0x6F0 "MSCR_IO444,SIUL2 I/O pin multiplexed signal configuration register 444" bitfld.long 0x6F0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6F0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6F0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6F0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6F0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6F0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6F0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6F0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6F0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6F0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6F0 0.--7. 1. "SSS,Source Signal Select" line.long 0x6F4 "MSCR_IO445,SIUL2 I/O pin multiplexed signal configuration register 445" bitfld.long 0x6F4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6F4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6F4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6F4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6F4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6F4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6F4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6F4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6F4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6F4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6F4 0.--7. 1. "SSS,Source Signal Select" line.long 0x6F8 "MSCR_IO446,SIUL2 I/O pin multiplexed signal configuration register 446" bitfld.long 0x6F8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6F8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6F8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6F8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6F8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6F8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6F8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6F8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6F8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6F8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6F8 0.--7. 1. "SSS,Source Signal Select" line.long 0x6FC "MSCR_IO447,SIUL2 I/O pin multiplexed signal configuration register 447" bitfld.long 0x6FC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6FC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6FC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6FC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6FC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6FC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6FC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6FC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6FC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6FC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6FC 0.--7. 1. "SSS,Source Signal Select" line.long 0x700 "MSCR_IO448,SIUL2 I/O pin multiplexed signal configuration register 448" bitfld.long 0x700 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x700 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x700 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x700 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x700 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x700 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x700 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x700 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x700 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x700 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x700 0.--7. 1. "SSS,Source Signal Select" line.long 0x704 "MSCR_IO449,SIUL2 I/O pin multiplexed signal configuration register 449" bitfld.long 0x704 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x704 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x704 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x704 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x704 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x704 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x704 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x704 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x704 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x704 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x704 0.--7. 1. "SSS,Source Signal Select" line.long 0x708 "MSCR_IO450,SIUL2 I/O pin multiplexed signal configuration register 450" bitfld.long 0x708 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x708 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x708 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x708 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x708 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x708 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x708 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x708 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x708 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x708 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x708 0.--7. 1. "SSS,Source Signal Select" line.long 0x70C "MSCR_IO451,SIUL2 I/O pin multiplexed signal configuration register 451" bitfld.long 0x70C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x70C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x70C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x70C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x70C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x70C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x70C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x70C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x70C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x70C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x70C 0.--7. 1. "SSS,Source Signal Select" line.long 0x710 "MSCR_IO452,SIUL2 I/O pin multiplexed signal configuration register 452" bitfld.long 0x710 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x710 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x710 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x710 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x710 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x710 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x710 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x710 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x710 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x710 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x710 0.--7. 1. "SSS,Source Signal Select" line.long 0x714 "MSCR_IO453,SIUL2 I/O pin multiplexed signal configuration register 453" bitfld.long 0x714 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x714 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x714 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x714 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x714 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x714 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x714 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x714 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x714 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x714 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x714 0.--7. 1. "SSS,Source Signal Select" line.long 0x718 "MSCR_IO454,SIUL2 I/O pin multiplexed signal configuration register 454" bitfld.long 0x718 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x718 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x718 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x718 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x718 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x718 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x718 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x718 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x718 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x718 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x718 0.--7. 1. "SSS,Source Signal Select" line.long 0x71C "MSCR_IO455,SIUL2 I/O pin multiplexed signal configuration register 455" bitfld.long 0x71C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x71C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x71C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x71C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x71C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x71C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x71C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x71C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x71C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x71C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x71C 0.--7. 1. "SSS,Source Signal Select" line.long 0x720 "MSCR_IO456,SIUL2 I/O pin multiplexed signal configuration register 456" bitfld.long 0x720 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x720 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x720 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x720 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x720 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x720 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x720 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x720 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x720 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x720 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x720 0.--7. 1. "SSS,Source Signal Select" line.long 0x724 "MSCR_IO457,SIUL2 I/O pin multiplexed signal configuration register 457" bitfld.long 0x724 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x724 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x724 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x724 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x724 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x724 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x724 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x724 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x724 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x724 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x724 0.--7. 1. "SSS,Source Signal Select" line.long 0x728 "MSCR_IO458,SIUL2 I/O pin multiplexed signal configuration register 458" bitfld.long 0x728 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x728 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x728 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x728 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x728 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x728 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x728 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x728 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x728 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x728 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x728 0.--7. 1. "SSS,Source Signal Select" line.long 0x72C "MSCR_IO459,SIUL2 I/O pin multiplexed signal configuration register 459" bitfld.long 0x72C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x72C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x72C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x72C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x72C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x72C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x72C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x72C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x72C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x72C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x72C 0.--7. 1. "SSS,Source Signal Select" line.long 0x730 "MSCR_IO460,SIUL2 I/O pin multiplexed signal configuration register 460" bitfld.long 0x730 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x730 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x730 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x730 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x730 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x730 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x730 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x730 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x730 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x730 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x730 0.--7. 1. "SSS,Source Signal Select" line.long 0x734 "MSCR_IO461,SIUL2 I/O pin multiplexed signal configuration register 461" bitfld.long 0x734 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x734 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x734 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x734 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x734 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x734 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x734 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x734 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x734 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x734 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x734 0.--7. 1. "SSS,Source Signal Select" line.long 0x738 "MSCR_IO462,SIUL2 I/O pin multiplexed signal configuration register 462" bitfld.long 0x738 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x738 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x738 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x738 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x738 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x738 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x738 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x738 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x738 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x738 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x738 0.--7. 1. "SSS,Source Signal Select" line.long 0x73C "MSCR_IO463,SIUL2 I/O pin multiplexed signal configuration register 463" bitfld.long 0x73C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x73C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x73C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x73C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x73C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x73C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x73C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x73C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x73C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x73C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x73C 0.--7. 1. "SSS,Source Signal Select" line.long 0x740 "MSCR_IO464,SIUL2 I/O pin multiplexed signal configuration register 464" bitfld.long 0x740 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x740 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x740 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x740 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x740 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x740 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x740 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x740 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x740 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x740 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x740 0.--7. 1. "SSS,Source Signal Select" line.long 0x744 "MSCR_IO465,SIUL2 I/O pin multiplexed signal configuration register 465" bitfld.long 0x744 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x744 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x744 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x744 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x744 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x744 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x744 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x744 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x744 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x744 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x744 0.--7. 1. "SSS,Source Signal Select" line.long 0x748 "MSCR_IO466,SIUL2 I/O pin multiplexed signal configuration register 466" bitfld.long 0x748 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x748 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x748 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x748 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x748 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x748 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x748 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x748 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x748 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x748 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x748 0.--7. 1. "SSS,Source Signal Select" line.long 0x74C "MSCR_IO467,SIUL2 I/O pin multiplexed signal configuration register 467" bitfld.long 0x74C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x74C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x74C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x74C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x74C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x74C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x74C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x74C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x74C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x74C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x74C 0.--7. 1. "SSS,Source Signal Select" line.long 0x750 "MSCR_IO468,SIUL2 I/O pin multiplexed signal configuration register 468" bitfld.long 0x750 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x750 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x750 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x750 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x750 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x750 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x750 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x750 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x750 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x750 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x750 0.--7. 1. "SSS,Source Signal Select" line.long 0x754 "MSCR_IO469,SIUL2 I/O pin multiplexed signal configuration register 469" bitfld.long 0x754 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x754 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x754 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x754 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x754 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x754 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x754 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x754 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x754 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x754 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x754 0.--7. 1. "SSS,Source Signal Select" line.long 0x758 "MSCR_IO470,SIUL2 I/O pin multiplexed signal configuration register 470" bitfld.long 0x758 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x758 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x758 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x758 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x758 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x758 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x758 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x758 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x758 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x758 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x758 0.--7. 1. "SSS,Source Signal Select" line.long 0x75C "MSCR_IO471,SIUL2 I/O pin multiplexed signal configuration register 471" bitfld.long 0x75C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x75C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x75C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x75C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x75C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x75C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x75C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x75C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x75C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x75C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x75C 0.--7. 1. "SSS,Source Signal Select" line.long 0x760 "MSCR_IO472,SIUL2 I/O pin multiplexed signal configuration register 472" bitfld.long 0x760 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x760 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x760 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x760 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x760 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x760 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x760 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x760 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x760 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x760 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x760 0.--7. 1. "SSS,Source Signal Select" line.long 0x764 "MSCR_IO473,SIUL2 I/O pin multiplexed signal configuration register 473" bitfld.long 0x764 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x764 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x764 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x764 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x764 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x764 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x764 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x764 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x764 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x764 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x764 0.--7. 1. "SSS,Source Signal Select" line.long 0x768 "MSCR_IO474,SIUL2 I/O pin multiplexed signal configuration register 474" bitfld.long 0x768 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x768 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x768 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x768 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x768 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x768 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x768 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x768 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x768 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x768 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x768 0.--7. 1. "SSS,Source Signal Select" line.long 0x76C "MSCR_IO475,SIUL2 I/O pin multiplexed signal configuration register 475" bitfld.long 0x76C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x76C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x76C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x76C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x76C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x76C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x76C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x76C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x76C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x76C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x76C 0.--7. 1. "SSS,Source Signal Select" line.long 0x770 "MSCR_IO476,SIUL2 I/O pin multiplexed signal configuration register 476" bitfld.long 0x770 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x770 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x770 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x770 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x770 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x770 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x770 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x770 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x770 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x770 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x770 0.--7. 1. "SSS,Source Signal Select" line.long 0x774 "MSCR_IO477,SIUL2 I/O pin multiplexed signal configuration register 477" bitfld.long 0x774 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x774 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x774 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x774 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x774 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x774 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x774 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x774 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x774 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x774 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x774 0.--7. 1. "SSS,Source Signal Select" line.long 0x778 "MSCR_IO478,SIUL2 I/O pin multiplexed signal configuration register 478" bitfld.long 0x778 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x778 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x778 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x778 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x778 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x778 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x778 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x778 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x778 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x778 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x778 0.--7. 1. "SSS,Source Signal Select" line.long 0x77C "MSCR_IO479,SIUL2 I/O pin multiplexed signal configuration register 479" bitfld.long 0x77C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x77C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x77C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x77C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x77C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x77C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x77C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x77C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x77C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x77C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x77C 0.--7. 1. "SSS,Source Signal Select" line.long 0x780 "MSCR_IO480,SIUL2 I/O pin multiplexed signal configuration register 480" bitfld.long 0x780 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x780 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x780 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x780 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x780 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x780 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x780 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x780 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x780 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x780 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x780 0.--7. 1. "SSS,Source Signal Select" line.long 0x784 "MSCR_IO481,SIUL2 I/O pin multiplexed signal configuration register 481" bitfld.long 0x784 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x784 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x784 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x784 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x784 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x784 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x784 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x784 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x784 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x784 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x784 0.--7. 1. "SSS,Source Signal Select" line.long 0x788 "MSCR_IO482,SIUL2 I/O pin multiplexed signal configuration register 482" bitfld.long 0x788 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x788 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x788 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x788 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x788 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x788 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x788 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x788 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x788 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x788 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x788 0.--7. 1. "SSS,Source Signal Select" line.long 0x78C "MSCR_IO483,SIUL2 I/O pin multiplexed signal configuration register 483" bitfld.long 0x78C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x78C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x78C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x78C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x78C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x78C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x78C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x78C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x78C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x78C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x78C 0.--7. 1. "SSS,Source Signal Select" line.long 0x790 "MSCR_IO484,SIUL2 I/O pin multiplexed signal configuration register 484" bitfld.long 0x790 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x790 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x790 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x790 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x790 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x790 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x790 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x790 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x790 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x790 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x790 0.--7. 1. "SSS,Source Signal Select" line.long 0x794 "MSCR_IO485,SIUL2 I/O pin multiplexed signal configuration register 485" bitfld.long 0x794 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x794 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x794 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x794 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x794 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x794 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x794 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x794 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x794 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x794 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x794 0.--7. 1. "SSS,Source Signal Select" line.long 0x798 "MSCR_IO486,SIUL2 I/O pin multiplexed signal configuration register 486" bitfld.long 0x798 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x798 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x798 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x798 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x798 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x798 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x798 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x798 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x798 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x798 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x798 0.--7. 1. "SSS,Source Signal Select" line.long 0x79C "MSCR_IO487,SIUL2 I/O pin multiplexed signal configuration register 487" bitfld.long 0x79C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x79C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x79C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x79C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x79C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x79C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x79C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x79C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x79C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x79C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x79C 0.--7. 1. "SSS,Source Signal Select" line.long 0x7A0 "MSCR_IO488,SIUL2 I/O pin multiplexed signal configuration register 488" bitfld.long 0x7A0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7A0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7A0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7A0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7A0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7A0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7A0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7A0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7A0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7A0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7A0 0.--7. 1. "SSS,Source Signal Select" line.long 0x7A4 "MSCR_IO489,SIUL2 I/O pin multiplexed signal configuration register 489" bitfld.long 0x7A4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7A4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7A4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7A4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7A4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7A4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7A4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7A4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7A4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7A4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7A4 0.--7. 1. "SSS,Source Signal Select" line.long 0x7A8 "MSCR_IO490,SIUL2 I/O pin multiplexed signal configuration register 490" bitfld.long 0x7A8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7A8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7A8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7A8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7A8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7A8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7A8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7A8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7A8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7A8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7A8 0.--7. 1. "SSS,Source Signal Select" line.long 0x7AC "MSCR_IO491,SIUL2 I/O pin multiplexed signal configuration register 491" bitfld.long 0x7AC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7AC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7AC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7AC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7AC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7AC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7AC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7AC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7AC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7AC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7AC 0.--7. 1. "SSS,Source Signal Select" line.long 0x7B0 "MSCR_IO492,SIUL2 I/O pin multiplexed signal configuration register 492" bitfld.long 0x7B0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7B0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7B0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7B0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7B0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7B0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7B0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7B0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7B0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7B0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7B0 0.--7. 1. "SSS,Source Signal Select" line.long 0x7B4 "MSCR_IO493,SIUL2 I/O pin multiplexed signal configuration register 493" bitfld.long 0x7B4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7B4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7B4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7B4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7B4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7B4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7B4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7B4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7B4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7B4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7B4 0.--7. 1. "SSS,Source Signal Select" line.long 0x7B8 "MSCR_IO494,SIUL2 I/O pin multiplexed signal configuration register 494" bitfld.long 0x7B8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7B8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7B8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7B8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7B8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7B8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7B8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7B8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7B8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7B8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7B8 0.--7. 1. "SSS,Source Signal Select" line.long 0x7BC "MSCR_IO495,SIUL2 I/O pin multiplexed signal configuration register 495" bitfld.long 0x7BC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7BC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7BC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7BC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7BC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7BC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7BC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7BC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7BC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7BC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7BC 0.--7. 1. "SSS,Source Signal Select" line.long 0x7C0 "MSCR_IO496,SIUL2 I/O pin multiplexed signal configuration register 496" bitfld.long 0x7C0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7C0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7C0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7C0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7C0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7C0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7C0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7C0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7C0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7C0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7C0 0.--7. 1. "SSS,Source Signal Select" line.long 0x7C4 "MSCR_IO497,SIUL2 I/O pin multiplexed signal configuration register 497" bitfld.long 0x7C4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7C4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7C4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7C4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7C4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7C4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7C4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7C4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7C4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7C4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7C4 0.--7. 1. "SSS,Source Signal Select" line.long 0x7C8 "MSCR_IO498,SIUL2 I/O pin multiplexed signal configuration register 498" bitfld.long 0x7C8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7C8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7C8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7C8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7C8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7C8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7C8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7C8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7C8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7C8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7C8 0.--7. 1. "SSS,Source Signal Select" line.long 0x7CC "MSCR_IO499,SIUL2 I/O pin multiplexed signal configuration register 499" bitfld.long 0x7CC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7CC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7CC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7CC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7CC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7CC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7CC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7CC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7CC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7CC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7CC 0.--7. 1. "SSS,Source Signal Select" line.long 0x7D0 "MSCR_IO500,SIUL2 I/O pin multiplexed signal configuration register 500" bitfld.long 0x7D0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7D0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7D0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7D0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7D0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7D0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7D0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7D0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7D0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7D0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7D0 0.--7. 1. "SSS,Source Signal Select" line.long 0x7D4 "MSCR_IO501,SIUL2 I/O pin multiplexed signal configuration register 501" bitfld.long 0x7D4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7D4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7D4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7D4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7D4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7D4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7D4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7D4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7D4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7D4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7D4 0.--7. 1. "SSS,Source Signal Select" line.long 0x7D8 "MSCR_IO502,SIUL2 I/O pin multiplexed signal configuration register 502" bitfld.long 0x7D8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7D8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7D8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7D8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7D8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7D8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7D8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7D8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7D8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7D8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7D8 0.--7. 1. "SSS,Source Signal Select" line.long 0x7DC "MSCR_IO503,SIUL2 I/O pin multiplexed signal configuration register 503" bitfld.long 0x7DC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7DC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7DC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7DC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7DC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7DC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7DC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7DC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7DC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7DC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7DC 0.--7. 1. "SSS,Source Signal Select" line.long 0x7E0 "MSCR_IO504,SIUL2 I/O pin multiplexed signal configuration register 504" bitfld.long 0x7E0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7E0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7E0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7E0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7E0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7E0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7E0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7E0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7E0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7E0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7E0 0.--7. 1. "SSS,Source Signal Select" line.long 0x7E4 "MSCR_IO505,SIUL2 I/O pin multiplexed signal configuration register 505" bitfld.long 0x7E4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7E4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7E4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7E4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7E4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7E4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7E4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7E4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7E4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7E4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7E4 0.--7. 1. "SSS,Source Signal Select" line.long 0x7E8 "MSCR_IO506,SIUL2 I/O pin multiplexed signal configuration register 506" bitfld.long 0x7E8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7E8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7E8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7E8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7E8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7E8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7E8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7E8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7E8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7E8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7E8 0.--7. 1. "SSS,Source Signal Select" line.long 0x7EC "MSCR_IO507,SIUL2 I/O pin multiplexed signal configuration register 507" bitfld.long 0x7EC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7EC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7EC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7EC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7EC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7EC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7EC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7EC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7EC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7EC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7EC 0.--7. 1. "SSS,Source Signal Select" line.long 0x7F0 "MSCR_IO508,SIUL2 I/O pin multiplexed signal configuration register 508" bitfld.long 0x7F0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7F0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7F0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7F0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7F0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7F0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7F0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7F0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7F0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7F0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7F0 0.--7. 1. "SSS,Source Signal Select" line.long 0x7F4 "MSCR_IO509,SIUL2 I/O pin multiplexed signal configuration register 509" bitfld.long 0x7F4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7F4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7F4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7F4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7F4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7F4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7F4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7F4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7F4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7F4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7F4 0.--7. 1. "SSS,Source Signal Select" line.long 0x7F8 "MSCR_IO510,SIUL2 I/O pin multiplexed signal configuration register 510" bitfld.long 0x7F8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7F8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7F8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7F8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7F8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7F8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7F8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7F8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7F8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7F8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7F8 0.--7. 1. "SSS,Source Signal Select" line.long 0x7FC "MSCR_IO511,SIUL2 I/O pin multiplexed signal configuration register 511" bitfld.long 0x7FC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7FC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7FC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7FC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7FC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7FC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7FC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7FC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7FC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7FC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7FC 0.--7. 1. "SSS,Source Signal Select" line.long 0x800 "MSCR_MUX512,SIUL2 multiplexed signal configuration register 512 for multiplexed input selectio512" bitfld.long 0x800 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x800 0.--7. 1. "SSS,Source Signal Select" line.long 0x804 "MSCR_MUX513,SIUL2 multiplexed signal configuration register 513 for multiplexed input selectio513" bitfld.long 0x804 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x804 0.--7. 1. "SSS,Source Signal Select" line.long 0x808 "MSCR_MUX514,SIUL2 multiplexed signal configuration register 514 for multiplexed input selectio514" bitfld.long 0x808 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x808 0.--7. 1. "SSS,Source Signal Select" line.long 0x80C "MSCR_MUX515,SIUL2 multiplexed signal configuration register 515 for multiplexed input selectio515" bitfld.long 0x80C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x80C 0.--7. 1. "SSS,Source Signal Select" line.long 0x810 "MSCR_MUX516,SIUL2 multiplexed signal configuration register 516 for multiplexed input selectio516" bitfld.long 0x810 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x810 0.--7. 1. "SSS,Source Signal Select" line.long 0x814 "MSCR_MUX517,SIUL2 multiplexed signal configuration register 517 for multiplexed input selectio517" bitfld.long 0x814 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x814 0.--7. 1. "SSS,Source Signal Select" line.long 0x818 "MSCR_MUX518,SIUL2 multiplexed signal configuration register 518 for multiplexed input selectio518" bitfld.long 0x818 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x818 0.--7. 1. "SSS,Source Signal Select" line.long 0x81C "MSCR_MUX519,SIUL2 multiplexed signal configuration register 519 for multiplexed input selectio519" bitfld.long 0x81C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x81C 0.--7. 1. "SSS,Source Signal Select" line.long 0x820 "MSCR_MUX520,SIUL2 multiplexed signal configuration register 520 for multiplexed input selectio520" bitfld.long 0x820 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x820 0.--7. 1. "SSS,Source Signal Select" line.long 0x824 "MSCR_MUX521,SIUL2 multiplexed signal configuration register 521 for multiplexed input selectio521" bitfld.long 0x824 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x824 0.--7. 1. "SSS,Source Signal Select" line.long 0x828 "MSCR_MUX522,SIUL2 multiplexed signal configuration register 522 for multiplexed input selectio522" bitfld.long 0x828 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x828 0.--7. 1. "SSS,Source Signal Select" line.long 0x82C "MSCR_MUX523,SIUL2 multiplexed signal configuration register 523 for multiplexed input selectio523" bitfld.long 0x82C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x82C 0.--7. 1. "SSS,Source Signal Select" line.long 0x830 "MSCR_MUX524,SIUL2 multiplexed signal configuration register 524 for multiplexed input selectio524" bitfld.long 0x830 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x830 0.--7. 1. "SSS,Source Signal Select" line.long 0x834 "MSCR_MUX525,SIUL2 multiplexed signal configuration register 525 for multiplexed input selectio525" bitfld.long 0x834 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x834 0.--7. 1. "SSS,Source Signal Select" line.long 0x838 "MSCR_MUX526,SIUL2 multiplexed signal configuration register 526 for multiplexed input selectio526" bitfld.long 0x838 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x838 0.--7. 1. "SSS,Source Signal Select" line.long 0x83C "MSCR_MUX527,SIUL2 multiplexed signal configuration register 527 for multiplexed input selectio527" bitfld.long 0x83C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x83C 0.--7. 1. "SSS,Source Signal Select" line.long 0x840 "MSCR_MUX528,SIUL2 multiplexed signal configuration register 528 for multiplexed input selectio528" bitfld.long 0x840 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x840 0.--7. 1. "SSS,Source Signal Select" line.long 0x844 "MSCR_MUX529,SIUL2 multiplexed signal configuration register 529 for multiplexed input selectio529" bitfld.long 0x844 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x844 0.--7. 1. "SSS,Source Signal Select" line.long 0x848 "MSCR_MUX530,SIUL2 multiplexed signal configuration register 530 for multiplexed input selectio530" bitfld.long 0x848 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x848 0.--7. 1. "SSS,Source Signal Select" line.long 0x84C "MSCR_MUX531,SIUL2 multiplexed signal configuration register 531 for multiplexed input selectio531" bitfld.long 0x84C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x84C 0.--7. 1. "SSS,Source Signal Select" line.long 0x850 "MSCR_MUX532,SIUL2 multiplexed signal configuration register 532 for multiplexed input selectio532" bitfld.long 0x850 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x850 0.--7. 1. "SSS,Source Signal Select" line.long 0x854 "MSCR_MUX533,SIUL2 multiplexed signal configuration register 533 for multiplexed input selectio533" bitfld.long 0x854 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x854 0.--7. 1. "SSS,Source Signal Select" line.long 0x858 "MSCR_MUX534,SIUL2 multiplexed signal configuration register 534 for multiplexed input selectio534" bitfld.long 0x858 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x858 0.--7. 1. "SSS,Source Signal Select" line.long 0x85C "MSCR_MUX535,SIUL2 multiplexed signal configuration register 535 for multiplexed input selectio535" bitfld.long 0x85C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x85C 0.--7. 1. "SSS,Source Signal Select" line.long 0x860 "MSCR_MUX536,SIUL2 multiplexed signal configuration register 536 for multiplexed input selectio536" bitfld.long 0x860 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x860 0.--7. 1. "SSS,Source Signal Select" line.long 0x864 "MSCR_MUX537,SIUL2 multiplexed signal configuration register 537 for multiplexed input selectio537" bitfld.long 0x864 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x864 0.--7. 1. "SSS,Source Signal Select" line.long 0x868 "MSCR_MUX538,SIUL2 multiplexed signal configuration register 538 for multiplexed input selectio538" bitfld.long 0x868 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x868 0.--7. 1. "SSS,Source Signal Select" line.long 0x86C "MSCR_MUX539,SIUL2 multiplexed signal configuration register 539 for multiplexed input selectio539" bitfld.long 0x86C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x86C 0.--7. 1. "SSS,Source Signal Select" line.long 0x870 "MSCR_MUX540,SIUL2 multiplexed signal configuration register 540 for multiplexed input selectio540" bitfld.long 0x870 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x870 0.--7. 1. "SSS,Source Signal Select" line.long 0x874 "MSCR_MUX541,SIUL2 multiplexed signal configuration register 541 for multiplexed input selectio541" bitfld.long 0x874 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x874 0.--7. 1. "SSS,Source Signal Select" line.long 0x878 "MSCR_MUX542,SIUL2 multiplexed signal configuration register 542 for multiplexed input selectio542" bitfld.long 0x878 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x878 0.--7. 1. "SSS,Source Signal Select" line.long 0x87C "MSCR_MUX543,SIUL2 multiplexed signal configuration register 543 for multiplexed input selectio543" bitfld.long 0x87C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x87C 0.--7. 1. "SSS,Source Signal Select" line.long 0x880 "MSCR_MUX544,SIUL2 multiplexed signal configuration register 544 for multiplexed input selectio544" bitfld.long 0x880 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x880 0.--7. 1. "SSS,Source Signal Select" line.long 0x884 "MSCR_MUX545,SIUL2 multiplexed signal configuration register 545 for multiplexed input selectio545" bitfld.long 0x884 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x884 0.--7. 1. "SSS,Source Signal Select" line.long 0x888 "MSCR_MUX546,SIUL2 multiplexed signal configuration register 546 for multiplexed input selectio546" bitfld.long 0x888 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x888 0.--7. 1. "SSS,Source Signal Select" line.long 0x88C "MSCR_MUX547,SIUL2 multiplexed signal configuration register 547 for multiplexed input selectio547" bitfld.long 0x88C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x88C 0.--7. 1. "SSS,Source Signal Select" line.long 0x890 "MSCR_MUX548,SIUL2 multiplexed signal configuration register 548 for multiplexed input selectio548" bitfld.long 0x890 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x890 0.--7. 1. "SSS,Source Signal Select" line.long 0x894 "MSCR_MUX549,SIUL2 multiplexed signal configuration register 549 for multiplexed input selectio549" bitfld.long 0x894 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x894 0.--7. 1. "SSS,Source Signal Select" line.long 0x898 "MSCR_MUX550,SIUL2 multiplexed signal configuration register 550 for multiplexed input selectio550" bitfld.long 0x898 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x898 0.--7. 1. "SSS,Source Signal Select" line.long 0x89C "MSCR_MUX551,SIUL2 multiplexed signal configuration register 551 for multiplexed input selectio551" bitfld.long 0x89C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x89C 0.--7. 1. "SSS,Source Signal Select" line.long 0x8A0 "MSCR_MUX552,SIUL2 multiplexed signal configuration register 552 for multiplexed input selectio552" bitfld.long 0x8A0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8A0 0.--7. 1. "SSS,Source Signal Select" line.long 0x8A4 "MSCR_MUX553,SIUL2 multiplexed signal configuration register 553 for multiplexed input selectio553" bitfld.long 0x8A4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8A4 0.--7. 1. "SSS,Source Signal Select" line.long 0x8A8 "MSCR_MUX554,SIUL2 multiplexed signal configuration register 554 for multiplexed input selectio554" bitfld.long 0x8A8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8A8 0.--7. 1. "SSS,Source Signal Select" line.long 0x8AC "MSCR_MUX555,SIUL2 multiplexed signal configuration register 555 for multiplexed input selectio555" bitfld.long 0x8AC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8AC 0.--7. 1. "SSS,Source Signal Select" line.long 0x8B0 "MSCR_MUX556,SIUL2 multiplexed signal configuration register 556 for multiplexed input selectio556" bitfld.long 0x8B0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8B0 0.--7. 1. "SSS,Source Signal Select" line.long 0x8B4 "MSCR_MUX557,SIUL2 multiplexed signal configuration register 557 for multiplexed input selectio557" bitfld.long 0x8B4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8B4 0.--7. 1. "SSS,Source Signal Select" line.long 0x8B8 "MSCR_MUX558,SIUL2 multiplexed signal configuration register 558 for multiplexed input selectio558" bitfld.long 0x8B8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8B8 0.--7. 1. "SSS,Source Signal Select" line.long 0x8BC "MSCR_MUX559,SIUL2 multiplexed signal configuration register 559 for multiplexed input selectio559" bitfld.long 0x8BC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8BC 0.--7. 1. "SSS,Source Signal Select" line.long 0x8C0 "MSCR_MUX560,SIUL2 multiplexed signal configuration register 560 for multiplexed input selectio560" bitfld.long 0x8C0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8C0 0.--7. 1. "SSS,Source Signal Select" line.long 0x8C4 "MSCR_MUX561,SIUL2 multiplexed signal configuration register 561 for multiplexed input selectio561" bitfld.long 0x8C4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8C4 0.--7. 1. "SSS,Source Signal Select" line.long 0x8C8 "MSCR_MUX562,SIUL2 multiplexed signal configuration register 562 for multiplexed input selectio562" bitfld.long 0x8C8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8C8 0.--7. 1. "SSS,Source Signal Select" line.long 0x8CC "MSCR_MUX563,SIUL2 multiplexed signal configuration register 563 for multiplexed input selectio563" bitfld.long 0x8CC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8CC 0.--7. 1. "SSS,Source Signal Select" line.long 0x8D0 "MSCR_MUX564,SIUL2 multiplexed signal configuration register 564 for multiplexed input selectio564" bitfld.long 0x8D0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8D0 0.--7. 1. "SSS,Source Signal Select" line.long 0x8D4 "MSCR_MUX565,SIUL2 multiplexed signal configuration register 565 for multiplexed input selectio565" bitfld.long 0x8D4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8D4 0.--7. 1. "SSS,Source Signal Select" line.long 0x8D8 "MSCR_MUX566,SIUL2 multiplexed signal configuration register 566 for multiplexed input selectio566" bitfld.long 0x8D8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8D8 0.--7. 1. "SSS,Source Signal Select" line.long 0x8DC "MSCR_MUX567,SIUL2 multiplexed signal configuration register 567 for multiplexed input selectio567" bitfld.long 0x8DC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8DC 0.--7. 1. "SSS,Source Signal Select" line.long 0x8E0 "MSCR_MUX568,SIUL2 multiplexed signal configuration register 568 for multiplexed input selectio568" bitfld.long 0x8E0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8E0 0.--7. 1. "SSS,Source Signal Select" line.long 0x8E4 "MSCR_MUX569,SIUL2 multiplexed signal configuration register 569 for multiplexed input selectio569" bitfld.long 0x8E4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8E4 0.--7. 1. "SSS,Source Signal Select" line.long 0x8E8 "MSCR_MUX570,SIUL2 multiplexed signal configuration register 570 for multiplexed input selectio570" bitfld.long 0x8E8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8E8 0.--7. 1. "SSS,Source Signal Select" line.long 0x8EC "MSCR_MUX571,SIUL2 multiplexed signal configuration register 571 for multiplexed input selectio571" bitfld.long 0x8EC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8EC 0.--7. 1. "SSS,Source Signal Select" line.long 0x8F0 "MSCR_MUX572,SIUL2 multiplexed signal configuration register 572 for multiplexed input selectio572" bitfld.long 0x8F0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8F0 0.--7. 1. "SSS,Source Signal Select" line.long 0x8F4 "MSCR_MUX573,SIUL2 multiplexed signal configuration register 573 for multiplexed input selectio573" bitfld.long 0x8F4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8F4 0.--7. 1. "SSS,Source Signal Select" line.long 0x8F8 "MSCR_MUX574,SIUL2 multiplexed signal configuration register 574 for multiplexed input selectio574" bitfld.long 0x8F8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8F8 0.--7. 1. "SSS,Source Signal Select" line.long 0x8FC "MSCR_MUX575,SIUL2 multiplexed signal configuration register 575 for multiplexed input selectio575" bitfld.long 0x8FC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8FC 0.--7. 1. "SSS,Source Signal Select" line.long 0x900 "MSCR_MUX576,SIUL2 multiplexed signal configuration register 576 for multiplexed input selectio576" bitfld.long 0x900 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x900 0.--7. 1. "SSS,Source Signal Select" line.long 0x904 "MSCR_MUX577,SIUL2 multiplexed signal configuration register 577 for multiplexed input selectio577" bitfld.long 0x904 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x904 0.--7. 1. "SSS,Source Signal Select" line.long 0x908 "MSCR_MUX578,SIUL2 multiplexed signal configuration register 578 for multiplexed input selectio578" bitfld.long 0x908 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x908 0.--7. 1. "SSS,Source Signal Select" line.long 0x90C "MSCR_MUX579,SIUL2 multiplexed signal configuration register 579 for multiplexed input selectio579" bitfld.long 0x90C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x90C 0.--7. 1. "SSS,Source Signal Select" line.long 0x910 "MSCR_MUX580,SIUL2 multiplexed signal configuration register 580 for multiplexed input selectio580" bitfld.long 0x910 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x910 0.--7. 1. "SSS,Source Signal Select" line.long 0x914 "MSCR_MUX581,SIUL2 multiplexed signal configuration register 581 for multiplexed input selectio581" bitfld.long 0x914 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x914 0.--7. 1. "SSS,Source Signal Select" line.long 0x918 "MSCR_MUX582,SIUL2 multiplexed signal configuration register 582 for multiplexed input selectio582" bitfld.long 0x918 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x918 0.--7. 1. "SSS,Source Signal Select" line.long 0x91C "MSCR_MUX583,SIUL2 multiplexed signal configuration register 583 for multiplexed input selectio583" bitfld.long 0x91C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x91C 0.--7. 1. "SSS,Source Signal Select" line.long 0x920 "MSCR_MUX584,SIUL2 multiplexed signal configuration register 584 for multiplexed input selectio584" bitfld.long 0x920 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x920 0.--7. 1. "SSS,Source Signal Select" line.long 0x924 "MSCR_MUX585,SIUL2 multiplexed signal configuration register 585 for multiplexed input selectio585" bitfld.long 0x924 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x924 0.--7. 1. "SSS,Source Signal Select" line.long 0x928 "MSCR_MUX586,SIUL2 multiplexed signal configuration register 586 for multiplexed input selectio586" bitfld.long 0x928 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x928 0.--7. 1. "SSS,Source Signal Select" line.long 0x92C "MSCR_MUX587,SIUL2 multiplexed signal configuration register 587 for multiplexed input selectio587" bitfld.long 0x92C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x92C 0.--7. 1. "SSS,Source Signal Select" line.long 0x930 "MSCR_MUX588,SIUL2 multiplexed signal configuration register 588 for multiplexed input selectio588" bitfld.long 0x930 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x930 0.--7. 1. "SSS,Source Signal Select" line.long 0x934 "MSCR_MUX589,SIUL2 multiplexed signal configuration register 589 for multiplexed input selectio589" bitfld.long 0x934 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x934 0.--7. 1. "SSS,Source Signal Select" line.long 0x938 "MSCR_MUX590,SIUL2 multiplexed signal configuration register 590 for multiplexed input selectio590" bitfld.long 0x938 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x938 0.--7. 1. "SSS,Source Signal Select" line.long 0x93C "MSCR_MUX591,SIUL2 multiplexed signal configuration register 591 for multiplexed input selectio591" bitfld.long 0x93C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x93C 0.--7. 1. "SSS,Source Signal Select" line.long 0x940 "MSCR_MUX592,SIUL2 multiplexed signal configuration register 592 for multiplexed input selectio592" bitfld.long 0x940 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x940 0.--7. 1. "SSS,Source Signal Select" line.long 0x944 "MSCR_MUX593,SIUL2 multiplexed signal configuration register 593 for multiplexed input selectio593" bitfld.long 0x944 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x944 0.--7. 1. "SSS,Source Signal Select" line.long 0x948 "MSCR_MUX594,SIUL2 multiplexed signal configuration register 594 for multiplexed input selectio594" bitfld.long 0x948 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x948 0.--7. 1. "SSS,Source Signal Select" line.long 0x94C "MSCR_MUX595,SIUL2 multiplexed signal configuration register 595 for multiplexed input selectio595" bitfld.long 0x94C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x94C 0.--7. 1. "SSS,Source Signal Select" line.long 0x950 "MSCR_MUX596,SIUL2 multiplexed signal configuration register 596 for multiplexed input selectio596" bitfld.long 0x950 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x950 0.--7. 1. "SSS,Source Signal Select" line.long 0x954 "MSCR_MUX597,SIUL2 multiplexed signal configuration register 597 for multiplexed input selectio597" bitfld.long 0x954 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x954 0.--7. 1. "SSS,Source Signal Select" line.long 0x958 "MSCR_MUX598,SIUL2 multiplexed signal configuration register 598 for multiplexed input selectio598" bitfld.long 0x958 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x958 0.--7. 1. "SSS,Source Signal Select" line.long 0x95C "MSCR_MUX599,SIUL2 multiplexed signal configuration register 599 for multiplexed input selectio599" bitfld.long 0x95C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x95C 0.--7. 1. "SSS,Source Signal Select" line.long 0x960 "MSCR_MUX600,SIUL2 multiplexed signal configuration register 600 for multiplexed input selectio600" bitfld.long 0x960 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x960 0.--7. 1. "SSS,Source Signal Select" line.long 0x964 "MSCR_MUX601,SIUL2 multiplexed signal configuration register 601 for multiplexed input selectio601" bitfld.long 0x964 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x964 0.--7. 1. "SSS,Source Signal Select" line.long 0x968 "MSCR_MUX602,SIUL2 multiplexed signal configuration register 602 for multiplexed input selectio602" bitfld.long 0x968 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x968 0.--7. 1. "SSS,Source Signal Select" line.long 0x96C "MSCR_MUX603,SIUL2 multiplexed signal configuration register 603 for multiplexed input selectio603" bitfld.long 0x96C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x96C 0.--7. 1. "SSS,Source Signal Select" line.long 0x970 "MSCR_MUX604,SIUL2 multiplexed signal configuration register 604 for multiplexed input selectio604" bitfld.long 0x970 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x970 0.--7. 1. "SSS,Source Signal Select" line.long 0x974 "MSCR_MUX605,SIUL2 multiplexed signal configuration register 605 for multiplexed input selectio605" bitfld.long 0x974 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x974 0.--7. 1. "SSS,Source Signal Select" line.long 0x978 "MSCR_MUX606,SIUL2 multiplexed signal configuration register 606 for multiplexed input selectio606" bitfld.long 0x978 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x978 0.--7. 1. "SSS,Source Signal Select" line.long 0x97C "MSCR_MUX607,SIUL2 multiplexed signal configuration register 607 for multiplexed input selectio607" bitfld.long 0x97C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x97C 0.--7. 1. "SSS,Source Signal Select" line.long 0x980 "MSCR_MUX608,SIUL2 multiplexed signal configuration register 608 for multiplexed input selectio608" bitfld.long 0x980 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x980 0.--7. 1. "SSS,Source Signal Select" line.long 0x984 "MSCR_MUX609,SIUL2 multiplexed signal configuration register 609 for multiplexed input selectio609" bitfld.long 0x984 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x984 0.--7. 1. "SSS,Source Signal Select" line.long 0x988 "MSCR_MUX610,SIUL2 multiplexed signal configuration register 610 for multiplexed input selectio610" bitfld.long 0x988 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x988 0.--7. 1. "SSS,Source Signal Select" line.long 0x98C "MSCR_MUX611,SIUL2 multiplexed signal configuration register 611 for multiplexed input selectio611" bitfld.long 0x98C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x98C 0.--7. 1. "SSS,Source Signal Select" line.long 0x990 "MSCR_MUX612,SIUL2 multiplexed signal configuration register 612 for multiplexed input selectio612" bitfld.long 0x990 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x990 0.--7. 1. "SSS,Source Signal Select" line.long 0x994 "MSCR_MUX613,SIUL2 multiplexed signal configuration register 613 for multiplexed input selectio613" bitfld.long 0x994 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x994 0.--7. 1. "SSS,Source Signal Select" line.long 0x998 "MSCR_MUX614,SIUL2 multiplexed signal configuration register 614 for multiplexed input selectio614" bitfld.long 0x998 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x998 0.--7. 1. "SSS,Source Signal Select" line.long 0x99C "MSCR_MUX615,SIUL2 multiplexed signal configuration register 615 for multiplexed input selectio615" bitfld.long 0x99C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x99C 0.--7. 1. "SSS,Source Signal Select" line.long 0x9A0 "MSCR_MUX616,SIUL2 multiplexed signal configuration register 616 for multiplexed input selectio616" bitfld.long 0x9A0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9A0 0.--7. 1. "SSS,Source Signal Select" line.long 0x9A4 "MSCR_MUX617,SIUL2 multiplexed signal configuration register 617 for multiplexed input selectio617" bitfld.long 0x9A4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9A4 0.--7. 1. "SSS,Source Signal Select" line.long 0x9A8 "MSCR_MUX618,SIUL2 multiplexed signal configuration register 618 for multiplexed input selectio618" bitfld.long 0x9A8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9A8 0.--7. 1. "SSS,Source Signal Select" line.long 0x9AC "MSCR_MUX619,SIUL2 multiplexed signal configuration register 619 for multiplexed input selectio619" bitfld.long 0x9AC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9AC 0.--7. 1. "SSS,Source Signal Select" line.long 0x9B0 "MSCR_MUX620,SIUL2 multiplexed signal configuration register 620 for multiplexed input selectio620" bitfld.long 0x9B0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9B0 0.--7. 1. "SSS,Source Signal Select" line.long 0x9B4 "MSCR_MUX621,SIUL2 multiplexed signal configuration register 621 for multiplexed input selectio621" bitfld.long 0x9B4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9B4 0.--7. 1. "SSS,Source Signal Select" line.long 0x9B8 "MSCR_MUX622,SIUL2 multiplexed signal configuration register 622 for multiplexed input selectio622" bitfld.long 0x9B8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9B8 0.--7. 1. "SSS,Source Signal Select" line.long 0x9BC "MSCR_MUX623,SIUL2 multiplexed signal configuration register 623 for multiplexed input selectio623" bitfld.long 0x9BC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9BC 0.--7. 1. "SSS,Source Signal Select" line.long 0x9C0 "MSCR_MUX624,SIUL2 multiplexed signal configuration register 624 for multiplexed input selectio624" bitfld.long 0x9C0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9C0 0.--7. 1. "SSS,Source Signal Select" line.long 0x9C4 "MSCR_MUX625,SIUL2 multiplexed signal configuration register 625 for multiplexed input selectio625" bitfld.long 0x9C4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9C4 0.--7. 1. "SSS,Source Signal Select" line.long 0x9C8 "MSCR_MUX626,SIUL2 multiplexed signal configuration register 626 for multiplexed input selectio626" bitfld.long 0x9C8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9C8 0.--7. 1. "SSS,Source Signal Select" line.long 0x9CC "MSCR_MUX627,SIUL2 multiplexed signal configuration register 627 for multiplexed input selectio627" bitfld.long 0x9CC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9CC 0.--7. 1. "SSS,Source Signal Select" line.long 0x9D0 "MSCR_MUX628,SIUL2 multiplexed signal configuration register 628 for multiplexed input selectio628" bitfld.long 0x9D0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9D0 0.--7. 1. "SSS,Source Signal Select" line.long 0x9D4 "MSCR_MUX629,SIUL2 multiplexed signal configuration register 629 for multiplexed input selectio629" bitfld.long 0x9D4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9D4 0.--7. 1. "SSS,Source Signal Select" line.long 0x9D8 "MSCR_MUX630,SIUL2 multiplexed signal configuration register 630 for multiplexed input selectio630" bitfld.long 0x9D8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9D8 0.--7. 1. "SSS,Source Signal Select" line.long 0x9DC "MSCR_MUX631,SIUL2 multiplexed signal configuration register 631 for multiplexed input selectio631" bitfld.long 0x9DC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9DC 0.--7. 1. "SSS,Source Signal Select" line.long 0x9E0 "MSCR_MUX632,SIUL2 multiplexed signal configuration register 632 for multiplexed input selectio632" bitfld.long 0x9E0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9E0 0.--7. 1. "SSS,Source Signal Select" line.long 0x9E4 "MSCR_MUX633,SIUL2 multiplexed signal configuration register 633 for multiplexed input selectio633" bitfld.long 0x9E4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9E4 0.--7. 1. "SSS,Source Signal Select" line.long 0x9E8 "MSCR_MUX634,SIUL2 multiplexed signal configuration register 634 for multiplexed input selectio634" bitfld.long 0x9E8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9E8 0.--7. 1. "SSS,Source Signal Select" line.long 0x9EC "MSCR_MUX635,SIUL2 multiplexed signal configuration register 635 for multiplexed input selectio635" bitfld.long 0x9EC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9EC 0.--7. 1. "SSS,Source Signal Select" line.long 0x9F0 "MSCR_MUX636,SIUL2 multiplexed signal configuration register 636 for multiplexed input selectio636" bitfld.long 0x9F0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9F0 0.--7. 1. "SSS,Source Signal Select" line.long 0x9F4 "MSCR_MUX637,SIUL2 multiplexed signal configuration register 637 for multiplexed input selectio637" bitfld.long 0x9F4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9F4 0.--7. 1. "SSS,Source Signal Select" line.long 0x9F8 "MSCR_MUX638,SIUL2 multiplexed signal configuration register 638 for multiplexed input selectio638" bitfld.long 0x9F8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9F8 0.--7. 1. "SSS,Source Signal Select" line.long 0x9FC "MSCR_MUX639,SIUL2 multiplexed signal configuration register 639 for multiplexed input selectio639" bitfld.long 0x9FC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9FC 0.--7. 1. "SSS,Source Signal Select" line.long 0xA00 "MSCR_MUX640,SIUL2 multiplexed signal configuration register 640 for multiplexed input selectio640" bitfld.long 0xA00 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA00 0.--7. 1. "SSS,Source Signal Select" line.long 0xA04 "MSCR_MUX641,SIUL2 multiplexed signal configuration register 641 for multiplexed input selectio641" bitfld.long 0xA04 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA04 0.--7. 1. "SSS,Source Signal Select" line.long 0xA08 "MSCR_MUX642,SIUL2 multiplexed signal configuration register 642 for multiplexed input selectio642" bitfld.long 0xA08 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA08 0.--7. 1. "SSS,Source Signal Select" line.long 0xA0C "MSCR_MUX643,SIUL2 multiplexed signal configuration register 643 for multiplexed input selectio643" bitfld.long 0xA0C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA0C 0.--7. 1. "SSS,Source Signal Select" line.long 0xA10 "MSCR_MUX644,SIUL2 multiplexed signal configuration register 644 for multiplexed input selectio644" bitfld.long 0xA10 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA10 0.--7. 1. "SSS,Source Signal Select" line.long 0xA14 "MSCR_MUX645,SIUL2 multiplexed signal configuration register 645 for multiplexed input selectio645" bitfld.long 0xA14 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA14 0.--7. 1. "SSS,Source Signal Select" line.long 0xA18 "MSCR_MUX646,SIUL2 multiplexed signal configuration register 646 for multiplexed input selectio646" bitfld.long 0xA18 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA18 0.--7. 1. "SSS,Source Signal Select" line.long 0xA1C "MSCR_MUX647,SIUL2 multiplexed signal configuration register 647 for multiplexed input selectio647" bitfld.long 0xA1C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA1C 0.--7. 1. "SSS,Source Signal Select" line.long 0xA20 "MSCR_MUX648,SIUL2 multiplexed signal configuration register 648 for multiplexed input selectio648" bitfld.long 0xA20 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA20 0.--7. 1. "SSS,Source Signal Select" line.long 0xA24 "MSCR_MUX649,SIUL2 multiplexed signal configuration register 649 for multiplexed input selectio649" bitfld.long 0xA24 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA24 0.--7. 1. "SSS,Source Signal Select" line.long 0xA28 "MSCR_MUX650,SIUL2 multiplexed signal configuration register 650 for multiplexed input selectio650" bitfld.long 0xA28 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA28 0.--7. 1. "SSS,Source Signal Select" line.long 0xA2C "MSCR_MUX651,SIUL2 multiplexed signal configuration register 651 for multiplexed input selectio651" bitfld.long 0xA2C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA2C 0.--7. 1. "SSS,Source Signal Select" line.long 0xA30 "MSCR_MUX652,SIUL2 multiplexed signal configuration register 652 for multiplexed input selectio652" bitfld.long 0xA30 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA30 0.--7. 1. "SSS,Source Signal Select" line.long 0xA34 "MSCR_MUX653,SIUL2 multiplexed signal configuration register 653 for multiplexed input selectio653" bitfld.long 0xA34 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA34 0.--7. 1. "SSS,Source Signal Select" line.long 0xA38 "MSCR_MUX654,SIUL2 multiplexed signal configuration register 654 for multiplexed input selectio654" bitfld.long 0xA38 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA38 0.--7. 1. "SSS,Source Signal Select" line.long 0xA3C "MSCR_MUX655,SIUL2 multiplexed signal configuration register 655 for multiplexed input selectio655" bitfld.long 0xA3C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA3C 0.--7. 1. "SSS,Source Signal Select" line.long 0xA40 "MSCR_MUX656,SIUL2 multiplexed signal configuration register 656 for multiplexed input selectio656" bitfld.long 0xA40 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA40 0.--7. 1. "SSS,Source Signal Select" line.long 0xA44 "MSCR_MUX657,SIUL2 multiplexed signal configuration register 657 for multiplexed input selectio657" bitfld.long 0xA44 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA44 0.--7. 1. "SSS,Source Signal Select" line.long 0xA48 "MSCR_MUX658,SIUL2 multiplexed signal configuration register 658 for multiplexed input selectio658" bitfld.long 0xA48 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA48 0.--7. 1. "SSS,Source Signal Select" line.long 0xA4C "MSCR_MUX659,SIUL2 multiplexed signal configuration register 659 for multiplexed input selectio659" bitfld.long 0xA4C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA4C 0.--7. 1. "SSS,Source Signal Select" line.long 0xA50 "MSCR_MUX660,SIUL2 multiplexed signal configuration register 660 for multiplexed input selectio660" bitfld.long 0xA50 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA50 0.--7. 1. "SSS,Source Signal Select" line.long 0xA54 "MSCR_MUX661,SIUL2 multiplexed signal configuration register 661 for multiplexed input selectio661" bitfld.long 0xA54 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA54 0.--7. 1. "SSS,Source Signal Select" line.long 0xA58 "MSCR_MUX662,SIUL2 multiplexed signal configuration register 662 for multiplexed input selectio662" bitfld.long 0xA58 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA58 0.--7. 1. "SSS,Source Signal Select" line.long 0xA5C "MSCR_MUX663,SIUL2 multiplexed signal configuration register 663 for multiplexed input selectio663" bitfld.long 0xA5C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA5C 0.--7. 1. "SSS,Source Signal Select" line.long 0xA60 "MSCR_MUX664,SIUL2 multiplexed signal configuration register 664 for multiplexed input selectio664" bitfld.long 0xA60 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA60 0.--7. 1. "SSS,Source Signal Select" line.long 0xA64 "MSCR_MUX665,SIUL2 multiplexed signal configuration register 665 for multiplexed input selectio665" bitfld.long 0xA64 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA64 0.--7. 1. "SSS,Source Signal Select" line.long 0xA68 "MSCR_MUX666,SIUL2 multiplexed signal configuration register 666 for multiplexed input selectio666" bitfld.long 0xA68 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA68 0.--7. 1. "SSS,Source Signal Select" line.long 0xA6C "MSCR_MUX667,SIUL2 multiplexed signal configuration register 667 for multiplexed input selectio667" bitfld.long 0xA6C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA6C 0.--7. 1. "SSS,Source Signal Select" line.long 0xA70 "MSCR_MUX668,SIUL2 multiplexed signal configuration register 668 for multiplexed input selectio668" bitfld.long 0xA70 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA70 0.--7. 1. "SSS,Source Signal Select" line.long 0xA74 "MSCR_MUX669,SIUL2 multiplexed signal configuration register 669 for multiplexed input selectio669" bitfld.long 0xA74 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA74 0.--7. 1. "SSS,Source Signal Select" line.long 0xA78 "MSCR_MUX670,SIUL2 multiplexed signal configuration register 670 for multiplexed input selectio670" bitfld.long 0xA78 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA78 0.--7. 1. "SSS,Source Signal Select" line.long 0xA7C "MSCR_MUX671,SIUL2 multiplexed signal configuration register 671 for multiplexed input selectio671" bitfld.long 0xA7C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA7C 0.--7. 1. "SSS,Source Signal Select" line.long 0xA80 "MSCR_MUX672,SIUL2 multiplexed signal configuration register 672 for multiplexed input selectio672" bitfld.long 0xA80 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA80 0.--7. 1. "SSS,Source Signal Select" line.long 0xA84 "MSCR_MUX673,SIUL2 multiplexed signal configuration register 673 for multiplexed input selectio673" bitfld.long 0xA84 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA84 0.--7. 1. "SSS,Source Signal Select" line.long 0xA88 "MSCR_MUX674,SIUL2 multiplexed signal configuration register 674 for multiplexed input selectio674" bitfld.long 0xA88 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA88 0.--7. 1. "SSS,Source Signal Select" line.long 0xA8C "MSCR_MUX675,SIUL2 multiplexed signal configuration register 675 for multiplexed input selectio675" bitfld.long 0xA8C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA8C 0.--7. 1. "SSS,Source Signal Select" line.long 0xA90 "MSCR_MUX676,SIUL2 multiplexed signal configuration register 676 for multiplexed input selectio676" bitfld.long 0xA90 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA90 0.--7. 1. "SSS,Source Signal Select" line.long 0xA94 "MSCR_MUX677,SIUL2 multiplexed signal configuration register 677 for multiplexed input selectio677" bitfld.long 0xA94 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA94 0.--7. 1. "SSS,Source Signal Select" line.long 0xA98 "MSCR_MUX678,SIUL2 multiplexed signal configuration register 678 for multiplexed input selectio678" bitfld.long 0xA98 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA98 0.--7. 1. "SSS,Source Signal Select" line.long 0xA9C "MSCR_MUX679,SIUL2 multiplexed signal configuration register 679 for multiplexed input selectio679" bitfld.long 0xA9C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA9C 0.--7. 1. "SSS,Source Signal Select" line.long 0xAA0 "MSCR_MUX680,SIUL2 multiplexed signal configuration register 680 for multiplexed input selectio680" bitfld.long 0xAA0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAA0 0.--7. 1. "SSS,Source Signal Select" line.long 0xAA4 "MSCR_MUX681,SIUL2 multiplexed signal configuration register 681 for multiplexed input selectio681" bitfld.long 0xAA4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAA4 0.--7. 1. "SSS,Source Signal Select" line.long 0xAA8 "MSCR_MUX682,SIUL2 multiplexed signal configuration register 682 for multiplexed input selectio682" bitfld.long 0xAA8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAA8 0.--7. 1. "SSS,Source Signal Select" line.long 0xAAC "MSCR_MUX683,SIUL2 multiplexed signal configuration register 683 for multiplexed input selectio683" bitfld.long 0xAAC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAAC 0.--7. 1. "SSS,Source Signal Select" line.long 0xAB0 "MSCR_MUX684,SIUL2 multiplexed signal configuration register 684 for multiplexed input selectio684" bitfld.long 0xAB0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAB0 0.--7. 1. "SSS,Source Signal Select" line.long 0xAB4 "MSCR_MUX685,SIUL2 multiplexed signal configuration register 685 for multiplexed input selectio685" bitfld.long 0xAB4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAB4 0.--7. 1. "SSS,Source Signal Select" line.long 0xAB8 "MSCR_MUX686,SIUL2 multiplexed signal configuration register 686 for multiplexed input selectio686" bitfld.long 0xAB8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAB8 0.--7. 1. "SSS,Source Signal Select" line.long 0xABC "MSCR_MUX687,SIUL2 multiplexed signal configuration register 687 for multiplexed input selectio687" bitfld.long 0xABC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xABC 0.--7. 1. "SSS,Source Signal Select" line.long 0xAC0 "MSCR_MUX688,SIUL2 multiplexed signal configuration register 688 for multiplexed input selectio688" bitfld.long 0xAC0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAC0 0.--7. 1. "SSS,Source Signal Select" line.long 0xAC4 "MSCR_MUX689,SIUL2 multiplexed signal configuration register 689 for multiplexed input selectio689" bitfld.long 0xAC4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAC4 0.--7. 1. "SSS,Source Signal Select" line.long 0xAC8 "MSCR_MUX690,SIUL2 multiplexed signal configuration register 690 for multiplexed input selectio690" bitfld.long 0xAC8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAC8 0.--7. 1. "SSS,Source Signal Select" line.long 0xACC "MSCR_MUX691,SIUL2 multiplexed signal configuration register 691 for multiplexed input selectio691" bitfld.long 0xACC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xACC 0.--7. 1. "SSS,Source Signal Select" line.long 0xAD0 "MSCR_MUX692,SIUL2 multiplexed signal configuration register 692 for multiplexed input selectio692" bitfld.long 0xAD0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAD0 0.--7. 1. "SSS,Source Signal Select" line.long 0xAD4 "MSCR_MUX693,SIUL2 multiplexed signal configuration register 693 for multiplexed input selectio693" bitfld.long 0xAD4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAD4 0.--7. 1. "SSS,Source Signal Select" line.long 0xAD8 "MSCR_MUX694,SIUL2 multiplexed signal configuration register 694 for multiplexed input selectio694" bitfld.long 0xAD8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAD8 0.--7. 1. "SSS,Source Signal Select" line.long 0xADC "MSCR_MUX695,SIUL2 multiplexed signal configuration register 695 for multiplexed input selectio695" bitfld.long 0xADC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xADC 0.--7. 1. "SSS,Source Signal Select" line.long 0xAE0 "MSCR_MUX696,SIUL2 multiplexed signal configuration register 696 for multiplexed input selectio696" bitfld.long 0xAE0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAE0 0.--7. 1. "SSS,Source Signal Select" line.long 0xAE4 "MSCR_MUX697,SIUL2 multiplexed signal configuration register 697 for multiplexed input selectio697" bitfld.long 0xAE4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAE4 0.--7. 1. "SSS,Source Signal Select" line.long 0xAE8 "MSCR_MUX698,SIUL2 multiplexed signal configuration register 698 for multiplexed input selectio698" bitfld.long 0xAE8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAE8 0.--7. 1. "SSS,Source Signal Select" line.long 0xAEC "MSCR_MUX699,SIUL2 multiplexed signal configuration register 699 for multiplexed input selectio699" bitfld.long 0xAEC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAEC 0.--7. 1. "SSS,Source Signal Select" line.long 0xAF0 "MSCR_MUX700,SIUL2 multiplexed signal configuration register 700 for multiplexed input selectio700" bitfld.long 0xAF0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAF0 0.--7. 1. "SSS,Source Signal Select" line.long 0xAF4 "MSCR_MUX701,SIUL2 multiplexed signal configuration register 701 for multiplexed input selectio701" bitfld.long 0xAF4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAF4 0.--7. 1. "SSS,Source Signal Select" line.long 0xAF8 "MSCR_MUX702,SIUL2 multiplexed signal configuration register 702 for multiplexed input selectio702" bitfld.long 0xAF8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAF8 0.--7. 1. "SSS,Source Signal Select" line.long 0xAFC "MSCR_MUX703,SIUL2 multiplexed signal configuration register 703 for multiplexed input selectio703" bitfld.long 0xAFC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAFC 0.--7. 1. "SSS,Source Signal Select" line.long 0xB00 "MSCR_MUX704,SIUL2 multiplexed signal configuration register 704 for multiplexed input selectio704" bitfld.long 0xB00 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB00 0.--7. 1. "SSS,Source Signal Select" line.long 0xB04 "MSCR_MUX705,SIUL2 multiplexed signal configuration register 705 for multiplexed input selectio705" bitfld.long 0xB04 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB04 0.--7. 1. "SSS,Source Signal Select" line.long 0xB08 "MSCR_MUX706,SIUL2 multiplexed signal configuration register 706 for multiplexed input selectio706" bitfld.long 0xB08 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB08 0.--7. 1. "SSS,Source Signal Select" line.long 0xB0C "MSCR_MUX707,SIUL2 multiplexed signal configuration register 707 for multiplexed input selectio707" bitfld.long 0xB0C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB0C 0.--7. 1. "SSS,Source Signal Select" line.long 0xB10 "MSCR_MUX708,SIUL2 multiplexed signal configuration register 708 for multiplexed input selectio708" bitfld.long 0xB10 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB10 0.--7. 1. "SSS,Source Signal Select" line.long 0xB14 "MSCR_MUX709,SIUL2 multiplexed signal configuration register 709 for multiplexed input selectio709" bitfld.long 0xB14 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB14 0.--7. 1. "SSS,Source Signal Select" line.long 0xB18 "MSCR_MUX710,SIUL2 multiplexed signal configuration register 710 for multiplexed input selectio710" bitfld.long 0xB18 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB18 0.--7. 1. "SSS,Source Signal Select" line.long 0xB1C "MSCR_MUX711,SIUL2 multiplexed signal configuration register 711 for multiplexed input selectio711" bitfld.long 0xB1C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB1C 0.--7. 1. "SSS,Source Signal Select" line.long 0xB20 "MSCR_MUX712,SIUL2 multiplexed signal configuration register 712 for multiplexed input selectio712" bitfld.long 0xB20 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB20 0.--7. 1. "SSS,Source Signal Select" line.long 0xB24 "MSCR_MUX713,SIUL2 multiplexed signal configuration register 713 for multiplexed input selectio713" bitfld.long 0xB24 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB24 0.--7. 1. "SSS,Source Signal Select" line.long 0xB28 "MSCR_MUX714,SIUL2 multiplexed signal configuration register 714 for multiplexed input selectio714" bitfld.long 0xB28 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB28 0.--7. 1. "SSS,Source Signal Select" line.long 0xB2C "MSCR_MUX715,SIUL2 multiplexed signal configuration register 715 for multiplexed input selectio715" bitfld.long 0xB2C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB2C 0.--7. 1. "SSS,Source Signal Select" line.long 0xB30 "MSCR_MUX716,SIUL2 multiplexed signal configuration register 716 for multiplexed input selectio716" bitfld.long 0xB30 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB30 0.--7. 1. "SSS,Source Signal Select" line.long 0xB34 "MSCR_MUX717,SIUL2 multiplexed signal configuration register 717 for multiplexed input selectio717" bitfld.long 0xB34 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB34 0.--7. 1. "SSS,Source Signal Select" line.long 0xB38 "MSCR_MUX718,SIUL2 multiplexed signal configuration register 718 for multiplexed input selectio718" bitfld.long 0xB38 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB38 0.--7. 1. "SSS,Source Signal Select" line.long 0xB3C "MSCR_MUX719,SIUL2 multiplexed signal configuration register 719 for multiplexed input selectio719" bitfld.long 0xB3C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB3C 0.--7. 1. "SSS,Source Signal Select" line.long 0xB40 "MSCR_MUX720,SIUL2 multiplexed signal configuration register 720 for multiplexed input selectio720" bitfld.long 0xB40 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB40 0.--7. 1. "SSS,Source Signal Select" line.long 0xB44 "MSCR_MUX721,SIUL2 multiplexed signal configuration register 721 for multiplexed input selectio721" bitfld.long 0xB44 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB44 0.--7. 1. "SSS,Source Signal Select" line.long 0xB48 "MSCR_MUX722,SIUL2 multiplexed signal configuration register 722 for multiplexed input selectio722" bitfld.long 0xB48 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB48 0.--7. 1. "SSS,Source Signal Select" line.long 0xB4C "MSCR_MUX723,SIUL2 multiplexed signal configuration register 723 for multiplexed input selectio723" bitfld.long 0xB4C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB4C 0.--7. 1. "SSS,Source Signal Select" line.long 0xB50 "MSCR_MUX724,SIUL2 multiplexed signal configuration register 724 for multiplexed input selectio724" bitfld.long 0xB50 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB50 0.--7. 1. "SSS,Source Signal Select" line.long 0xB54 "MSCR_MUX725,SIUL2 multiplexed signal configuration register 725 for multiplexed input selectio725" bitfld.long 0xB54 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB54 0.--7. 1. "SSS,Source Signal Select" line.long 0xB58 "MSCR_MUX726,SIUL2 multiplexed signal configuration register 726 for multiplexed input selectio726" bitfld.long 0xB58 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB58 0.--7. 1. "SSS,Source Signal Select" line.long 0xB5C "MSCR_MUX727,SIUL2 multiplexed signal configuration register 727 for multiplexed input selectio727" bitfld.long 0xB5C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB5C 0.--7. 1. "SSS,Source Signal Select" line.long 0xB60 "MSCR_MUX728,SIUL2 multiplexed signal configuration register 728 for multiplexed input selectio728" bitfld.long 0xB60 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB60 0.--7. 1. "SSS,Source Signal Select" line.long 0xB64 "MSCR_MUX729,SIUL2 multiplexed signal configuration register 729 for multiplexed input selectio729" bitfld.long 0xB64 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB64 0.--7. 1. "SSS,Source Signal Select" line.long 0xB68 "MSCR_MUX730,SIUL2 multiplexed signal configuration register 730 for multiplexed input selectio730" bitfld.long 0xB68 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB68 0.--7. 1. "SSS,Source Signal Select" line.long 0xB6C "MSCR_MUX731,SIUL2 multiplexed signal configuration register 731 for multiplexed input selectio731" bitfld.long 0xB6C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB6C 0.--7. 1. "SSS,Source Signal Select" line.long 0xB70 "MSCR_MUX732,SIUL2 multiplexed signal configuration register 732 for multiplexed input selectio732" bitfld.long 0xB70 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB70 0.--7. 1. "SSS,Source Signal Select" line.long 0xB74 "MSCR_MUX733,SIUL2 multiplexed signal configuration register 733 for multiplexed input selectio733" bitfld.long 0xB74 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB74 0.--7. 1. "SSS,Source Signal Select" line.long 0xB78 "MSCR_MUX734,SIUL2 multiplexed signal configuration register 734 for multiplexed input selectio734" bitfld.long 0xB78 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB78 0.--7. 1. "SSS,Source Signal Select" line.long 0xB7C "MSCR_MUX735,SIUL2 multiplexed signal configuration register 735 for multiplexed input selectio735" bitfld.long 0xB7C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB7C 0.--7. 1. "SSS,Source Signal Select" line.long 0xB80 "MSCR_MUX736,SIUL2 multiplexed signal configuration register 736 for multiplexed input selectio736" bitfld.long 0xB80 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB80 0.--7. 1. "SSS,Source Signal Select" line.long 0xB84 "MSCR_MUX737,SIUL2 multiplexed signal configuration register 737 for multiplexed input selectio737" bitfld.long 0xB84 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB84 0.--7. 1. "SSS,Source Signal Select" line.long 0xB88 "MSCR_MUX738,SIUL2 multiplexed signal configuration register 738 for multiplexed input selectio738" bitfld.long 0xB88 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB88 0.--7. 1. "SSS,Source Signal Select" line.long 0xB8C "MSCR_MUX739,SIUL2 multiplexed signal configuration register 739 for multiplexed input selectio739" bitfld.long 0xB8C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB8C 0.--7. 1. "SSS,Source Signal Select" line.long 0xB90 "MSCR_MUX740,SIUL2 multiplexed signal configuration register 740 for multiplexed input selectio740" bitfld.long 0xB90 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB90 0.--7. 1. "SSS,Source Signal Select" line.long 0xB94 "MSCR_MUX741,SIUL2 multiplexed signal configuration register 741 for multiplexed input selectio741" bitfld.long 0xB94 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB94 0.--7. 1. "SSS,Source Signal Select" line.long 0xB98 "MSCR_MUX742,SIUL2 multiplexed signal configuration register 742 for multiplexed input selectio742" bitfld.long 0xB98 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB98 0.--7. 1. "SSS,Source Signal Select" line.long 0xB9C "MSCR_MUX743,SIUL2 multiplexed signal configuration register 743 for multiplexed input selectio743" bitfld.long 0xB9C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB9C 0.--7. 1. "SSS,Source Signal Select" line.long 0xBA0 "MSCR_MUX744,SIUL2 multiplexed signal configuration register 744 for multiplexed input selectio744" bitfld.long 0xBA0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBA0 0.--7. 1. "SSS,Source Signal Select" line.long 0xBA4 "MSCR_MUX745,SIUL2 multiplexed signal configuration register 745 for multiplexed input selectio745" bitfld.long 0xBA4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBA4 0.--7. 1. "SSS,Source Signal Select" line.long 0xBA8 "MSCR_MUX746,SIUL2 multiplexed signal configuration register 746 for multiplexed input selectio746" bitfld.long 0xBA8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBA8 0.--7. 1. "SSS,Source Signal Select" line.long 0xBAC "MSCR_MUX747,SIUL2 multiplexed signal configuration register 747 for multiplexed input selectio747" bitfld.long 0xBAC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBAC 0.--7. 1. "SSS,Source Signal Select" line.long 0xBB0 "MSCR_MUX748,SIUL2 multiplexed signal configuration register 748 for multiplexed input selectio748" bitfld.long 0xBB0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBB0 0.--7. 1. "SSS,Source Signal Select" line.long 0xBB4 "MSCR_MUX749,SIUL2 multiplexed signal configuration register 749 for multiplexed input selectio749" bitfld.long 0xBB4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBB4 0.--7. 1. "SSS,Source Signal Select" line.long 0xBB8 "MSCR_MUX750,SIUL2 multiplexed signal configuration register 750 for multiplexed input selectio750" bitfld.long 0xBB8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBB8 0.--7. 1. "SSS,Source Signal Select" line.long 0xBBC "MSCR_MUX751,SIUL2 multiplexed signal configuration register 751 for multiplexed input selectio751" bitfld.long 0xBBC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBBC 0.--7. 1. "SSS,Source Signal Select" line.long 0xBC0 "MSCR_MUX752,SIUL2 multiplexed signal configuration register 752 for multiplexed input selectio752" bitfld.long 0xBC0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBC0 0.--7. 1. "SSS,Source Signal Select" line.long 0xBC4 "MSCR_MUX753,SIUL2 multiplexed signal configuration register 753 for multiplexed input selectio753" bitfld.long 0xBC4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBC4 0.--7. 1. "SSS,Source Signal Select" line.long 0xBC8 "MSCR_MUX754,SIUL2 multiplexed signal configuration register 754 for multiplexed input selectio754" bitfld.long 0xBC8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBC8 0.--7. 1. "SSS,Source Signal Select" line.long 0xBCC "MSCR_MUX755,SIUL2 multiplexed signal configuration register 755 for multiplexed input selectio755" bitfld.long 0xBCC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBCC 0.--7. 1. "SSS,Source Signal Select" line.long 0xBD0 "MSCR_MUX756,SIUL2 multiplexed signal configuration register 756 for multiplexed input selectio756" bitfld.long 0xBD0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBD0 0.--7. 1. "SSS,Source Signal Select" line.long 0xBD4 "MSCR_MUX757,SIUL2 multiplexed signal configuration register 757 for multiplexed input selectio757" bitfld.long 0xBD4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBD4 0.--7. 1. "SSS,Source Signal Select" line.long 0xBD8 "MSCR_MUX758,SIUL2 multiplexed signal configuration register 758 for multiplexed input selectio758" bitfld.long 0xBD8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBD8 0.--7. 1. "SSS,Source Signal Select" line.long 0xBDC "MSCR_MUX759,SIUL2 multiplexed signal configuration register 759 for multiplexed input selectio759" bitfld.long 0xBDC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBDC 0.--7. 1. "SSS,Source Signal Select" line.long 0xBE0 "MSCR_MUX760,SIUL2 multiplexed signal configuration register 760 for multiplexed input selectio760" bitfld.long 0xBE0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBE0 0.--7. 1. "SSS,Source Signal Select" line.long 0xBE4 "MSCR_MUX761,SIUL2 multiplexed signal configuration register 761 for multiplexed input selectio761" bitfld.long 0xBE4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBE4 0.--7. 1. "SSS,Source Signal Select" line.long 0xBE8 "MSCR_MUX762,SIUL2 multiplexed signal configuration register 762 for multiplexed input selectio762" bitfld.long 0xBE8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBE8 0.--7. 1. "SSS,Source Signal Select" line.long 0xBEC "MSCR_MUX763,SIUL2 multiplexed signal configuration register 763 for multiplexed input selectio763" bitfld.long 0xBEC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBEC 0.--7. 1. "SSS,Source Signal Select" line.long 0xBF0 "MSCR_MUX764,SIUL2 multiplexed signal configuration register 764 for multiplexed input selectio764" bitfld.long 0xBF0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBF0 0.--7. 1. "SSS,Source Signal Select" line.long 0xBF4 "MSCR_MUX765,SIUL2 multiplexed signal configuration register 765 for multiplexed input selectio765" bitfld.long 0xBF4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBF4 0.--7. 1. "SSS,Source Signal Select" line.long 0xBF8 "MSCR_MUX766,SIUL2 multiplexed signal configuration register 766 for multiplexed input selectio766" bitfld.long 0xBF8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBF8 0.--7. 1. "SSS,Source Signal Select" line.long 0xBFC "MSCR_MUX767,SIUL2 multiplexed signal configuration register 767 for multiplexed input selectio767" bitfld.long 0xBFC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBFC 0.--7. 1. "SSS,Source Signal Select" line.long 0xC00 "MSCR_MUX768,SIUL2 multiplexed signal configuration register 768 for multiplexed input selectio768" bitfld.long 0xC00 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC00 0.--7. 1. "SSS,Source Signal Select" line.long 0xC04 "MSCR_MUX769,SIUL2 multiplexed signal configuration register 769 for multiplexed input selectio769" bitfld.long 0xC04 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC04 0.--7. 1. "SSS,Source Signal Select" line.long 0xC08 "MSCR_MUX770,SIUL2 multiplexed signal configuration register 770 for multiplexed input selectio770" bitfld.long 0xC08 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC08 0.--7. 1. "SSS,Source Signal Select" line.long 0xC0C "MSCR_MUX771,SIUL2 multiplexed signal configuration register 771 for multiplexed input selectio771" bitfld.long 0xC0C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC0C 0.--7. 1. "SSS,Source Signal Select" line.long 0xC10 "MSCR_MUX772,SIUL2 multiplexed signal configuration register 772 for multiplexed input selectio772" bitfld.long 0xC10 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC10 0.--7. 1. "SSS,Source Signal Select" line.long 0xC14 "MSCR_MUX773,SIUL2 multiplexed signal configuration register 773 for multiplexed input selectio773" bitfld.long 0xC14 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC14 0.--7. 1. "SSS,Source Signal Select" line.long 0xC18 "MSCR_MUX774,SIUL2 multiplexed signal configuration register 774 for multiplexed input selectio774" bitfld.long 0xC18 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC18 0.--7. 1. "SSS,Source Signal Select" line.long 0xC1C "MSCR_MUX775,SIUL2 multiplexed signal configuration register 775 for multiplexed input selectio775" bitfld.long 0xC1C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC1C 0.--7. 1. "SSS,Source Signal Select" line.long 0xC20 "MSCR_MUX776,SIUL2 multiplexed signal configuration register 776 for multiplexed input selectio776" bitfld.long 0xC20 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC20 0.--7. 1. "SSS,Source Signal Select" line.long 0xC24 "MSCR_MUX777,SIUL2 multiplexed signal configuration register 777 for multiplexed input selectio777" bitfld.long 0xC24 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC24 0.--7. 1. "SSS,Source Signal Select" line.long 0xC28 "MSCR_MUX778,SIUL2 multiplexed signal configuration register 778 for multiplexed input selectio778" bitfld.long 0xC28 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC28 0.--7. 1. "SSS,Source Signal Select" line.long 0xC2C "MSCR_MUX779,SIUL2 multiplexed signal configuration register 779 for multiplexed input selectio779" bitfld.long 0xC2C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC2C 0.--7. 1. "SSS,Source Signal Select" line.long 0xC30 "MSCR_MUX780,SIUL2 multiplexed signal configuration register 780 for multiplexed input selectio780" bitfld.long 0xC30 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC30 0.--7. 1. "SSS,Source Signal Select" line.long 0xC34 "MSCR_MUX781,SIUL2 multiplexed signal configuration register 781 for multiplexed input selectio781" bitfld.long 0xC34 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC34 0.--7. 1. "SSS,Source Signal Select" line.long 0xC38 "MSCR_MUX782,SIUL2 multiplexed signal configuration register 782 for multiplexed input selectio782" bitfld.long 0xC38 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC38 0.--7. 1. "SSS,Source Signal Select" line.long 0xC3C "MSCR_MUX783,SIUL2 multiplexed signal configuration register 783 for multiplexed input selectio783" bitfld.long 0xC3C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC3C 0.--7. 1. "SSS,Source Signal Select" line.long 0xC40 "MSCR_MUX784,SIUL2 multiplexed signal configuration register 784 for multiplexed input selectio784" bitfld.long 0xC40 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC40 0.--7. 1. "SSS,Source Signal Select" line.long 0xC44 "MSCR_MUX785,SIUL2 multiplexed signal configuration register 785 for multiplexed input selectio785" bitfld.long 0xC44 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC44 0.--7. 1. "SSS,Source Signal Select" line.long 0xC48 "MSCR_MUX786,SIUL2 multiplexed signal configuration register 786 for multiplexed input selectio786" bitfld.long 0xC48 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC48 0.--7. 1. "SSS,Source Signal Select" line.long 0xC4C "MSCR_MUX787,SIUL2 multiplexed signal configuration register 787 for multiplexed input selectio787" bitfld.long 0xC4C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC4C 0.--7. 1. "SSS,Source Signal Select" line.long 0xC50 "MSCR_MUX788,SIUL2 multiplexed signal configuration register 788 for multiplexed input selectio788" bitfld.long 0xC50 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC50 0.--7. 1. "SSS,Source Signal Select" line.long 0xC54 "MSCR_MUX789,SIUL2 multiplexed signal configuration register 789 for multiplexed input selectio789" bitfld.long 0xC54 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC54 0.--7. 1. "SSS,Source Signal Select" line.long 0xC58 "MSCR_MUX790,SIUL2 multiplexed signal configuration register 790 for multiplexed input selectio790" bitfld.long 0xC58 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC58 0.--7. 1. "SSS,Source Signal Select" line.long 0xC5C "MSCR_MUX791,SIUL2 multiplexed signal configuration register 791 for multiplexed input selectio791" bitfld.long 0xC5C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC5C 0.--7. 1. "SSS,Source Signal Select" line.long 0xC60 "MSCR_MUX792,SIUL2 multiplexed signal configuration register 792 for multiplexed input selectio792" bitfld.long 0xC60 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC60 0.--7. 1. "SSS,Source Signal Select" line.long 0xC64 "MSCR_MUX793,SIUL2 multiplexed signal configuration register 793 for multiplexed input selectio793" bitfld.long 0xC64 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC64 0.--7. 1. "SSS,Source Signal Select" line.long 0xC68 "MSCR_MUX794,SIUL2 multiplexed signal configuration register 794 for multiplexed input selectio794" bitfld.long 0xC68 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC68 0.--7. 1. "SSS,Source Signal Select" line.long 0xC6C "MSCR_MUX795,SIUL2 multiplexed signal configuration register 795 for multiplexed input selectio795" bitfld.long 0xC6C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC6C 0.--7. 1. "SSS,Source Signal Select" line.long 0xC70 "MSCR_MUX796,SIUL2 multiplexed signal configuration register 796 for multiplexed input selectio796" bitfld.long 0xC70 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC70 0.--7. 1. "SSS,Source Signal Select" line.long 0xC74 "MSCR_MUX797,SIUL2 multiplexed signal configuration register 797 for multiplexed input selectio797" bitfld.long 0xC74 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC74 0.--7. 1. "SSS,Source Signal Select" line.long 0xC78 "MSCR_MUX798,SIUL2 multiplexed signal configuration register 798 for multiplexed input selectio798" bitfld.long 0xC78 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC78 0.--7. 1. "SSS,Source Signal Select" line.long 0xC7C "MSCR_MUX799,SIUL2 multiplexed signal configuration register 799 for multiplexed input selectio799" bitfld.long 0xC7C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC7C 0.--7. 1. "SSS,Source Signal Select" line.long 0xC80 "MSCR_MUX800,SIUL2 multiplexed signal configuration register 800 for multiplexed input selectio800" bitfld.long 0xC80 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC80 0.--7. 1. "SSS,Source Signal Select" line.long 0xC84 "MSCR_MUX801,SIUL2 multiplexed signal configuration register 801 for multiplexed input selectio801" bitfld.long 0xC84 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC84 0.--7. 1. "SSS,Source Signal Select" line.long 0xC88 "MSCR_MUX802,SIUL2 multiplexed signal configuration register 802 for multiplexed input selectio802" bitfld.long 0xC88 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC88 0.--7. 1. "SSS,Source Signal Select" line.long 0xC8C "MSCR_MUX803,SIUL2 multiplexed signal configuration register 803 for multiplexed input selectio803" bitfld.long 0xC8C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC8C 0.--7. 1. "SSS,Source Signal Select" line.long 0xC90 "MSCR_MUX804,SIUL2 multiplexed signal configuration register 804 for multiplexed input selectio804" bitfld.long 0xC90 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC90 0.--7. 1. "SSS,Source Signal Select" line.long 0xC94 "MSCR_MUX805,SIUL2 multiplexed signal configuration register 805 for multiplexed input selectio805" bitfld.long 0xC94 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC94 0.--7. 1. "SSS,Source Signal Select" line.long 0xC98 "MSCR_MUX806,SIUL2 multiplexed signal configuration register 806 for multiplexed input selectio806" bitfld.long 0xC98 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC98 0.--7. 1. "SSS,Source Signal Select" line.long 0xC9C "MSCR_MUX807,SIUL2 multiplexed signal configuration register 807 for multiplexed input selectio807" bitfld.long 0xC9C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC9C 0.--7. 1. "SSS,Source Signal Select" line.long 0xCA0 "MSCR_MUX808,SIUL2 multiplexed signal configuration register 808 for multiplexed input selectio808" bitfld.long 0xCA0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCA0 0.--7. 1. "SSS,Source Signal Select" line.long 0xCA4 "MSCR_MUX809,SIUL2 multiplexed signal configuration register 809 for multiplexed input selectio809" bitfld.long 0xCA4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCA4 0.--7. 1. "SSS,Source Signal Select" line.long 0xCA8 "MSCR_MUX810,SIUL2 multiplexed signal configuration register 810 for multiplexed input selectio810" bitfld.long 0xCA8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCA8 0.--7. 1. "SSS,Source Signal Select" line.long 0xCAC "MSCR_MUX811,SIUL2 multiplexed signal configuration register 811 for multiplexed input selectio811" bitfld.long 0xCAC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCAC 0.--7. 1. "SSS,Source Signal Select" line.long 0xCB0 "MSCR_MUX812,SIUL2 multiplexed signal configuration register 812 for multiplexed input selectio812" bitfld.long 0xCB0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCB0 0.--7. 1. "SSS,Source Signal Select" line.long 0xCB4 "MSCR_MUX813,SIUL2 multiplexed signal configuration register 813 for multiplexed input selectio813" bitfld.long 0xCB4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCB4 0.--7. 1. "SSS,Source Signal Select" line.long 0xCB8 "MSCR_MUX814,SIUL2 multiplexed signal configuration register 814 for multiplexed input selectio814" bitfld.long 0xCB8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCB8 0.--7. 1. "SSS,Source Signal Select" line.long 0xCBC "MSCR_MUX815,SIUL2 multiplexed signal configuration register 815 for multiplexed input selectio815" bitfld.long 0xCBC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCBC 0.--7. 1. "SSS,Source Signal Select" line.long 0xCC0 "MSCR_MUX816,SIUL2 multiplexed signal configuration register 816 for multiplexed input selectio816" bitfld.long 0xCC0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCC0 0.--7. 1. "SSS,Source Signal Select" line.long 0xCC4 "MSCR_MUX817,SIUL2 multiplexed signal configuration register 817 for multiplexed input selectio817" bitfld.long 0xCC4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCC4 0.--7. 1. "SSS,Source Signal Select" line.long 0xCC8 "MSCR_MUX818,SIUL2 multiplexed signal configuration register 818 for multiplexed input selectio818" bitfld.long 0xCC8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCC8 0.--7. 1. "SSS,Source Signal Select" line.long 0xCCC "MSCR_MUX819,SIUL2 multiplexed signal configuration register 819 for multiplexed input selectio819" bitfld.long 0xCCC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCCC 0.--7. 1. "SSS,Source Signal Select" line.long 0xCD0 "MSCR_MUX820,SIUL2 multiplexed signal configuration register 820 for multiplexed input selectio820" bitfld.long 0xCD0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCD0 0.--7. 1. "SSS,Source Signal Select" line.long 0xCD4 "MSCR_MUX821,SIUL2 multiplexed signal configuration register 821 for multiplexed input selectio821" bitfld.long 0xCD4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCD4 0.--7. 1. "SSS,Source Signal Select" line.long 0xCD8 "MSCR_MUX822,SIUL2 multiplexed signal configuration register 822 for multiplexed input selectio822" bitfld.long 0xCD8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCD8 0.--7. 1. "SSS,Source Signal Select" line.long 0xCDC "MSCR_MUX823,SIUL2 multiplexed signal configuration register 823 for multiplexed input selectio823" bitfld.long 0xCDC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCDC 0.--7. 1. "SSS,Source Signal Select" line.long 0xCE0 "MSCR_MUX824,SIUL2 multiplexed signal configuration register 824 for multiplexed input selectio824" bitfld.long 0xCE0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCE0 0.--7. 1. "SSS,Source Signal Select" line.long 0xCE4 "MSCR_MUX825,SIUL2 multiplexed signal configuration register 825 for multiplexed input selectio825" bitfld.long 0xCE4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCE4 0.--7. 1. "SSS,Source Signal Select" line.long 0xCE8 "MSCR_MUX826,SIUL2 multiplexed signal configuration register 826 for multiplexed input selectio826" bitfld.long 0xCE8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCE8 0.--7. 1. "SSS,Source Signal Select" line.long 0xCEC "MSCR_MUX827,SIUL2 multiplexed signal configuration register 827 for multiplexed input selectio827" bitfld.long 0xCEC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCEC 0.--7. 1. "SSS,Source Signal Select" line.long 0xCF0 "MSCR_MUX828,SIUL2 multiplexed signal configuration register 828 for multiplexed input selectio828" bitfld.long 0xCF0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCF0 0.--7. 1. "SSS,Source Signal Select" line.long 0xCF4 "MSCR_MUX829,SIUL2 multiplexed signal configuration register 829 for multiplexed input selectio829" bitfld.long 0xCF4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCF4 0.--7. 1. "SSS,Source Signal Select" line.long 0xCF8 "MSCR_MUX830,SIUL2 multiplexed signal configuration register 830 for multiplexed input selectio830" bitfld.long 0xCF8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCF8 0.--7. 1. "SSS,Source Signal Select" line.long 0xCFC "MSCR_MUX831,SIUL2 multiplexed signal configuration register 831 for multiplexed input selectio831" bitfld.long 0xCFC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCFC 0.--7. 1. "SSS,Source Signal Select" line.long 0xD00 "MSCR_MUX832,SIUL2 multiplexed signal configuration register 832 for multiplexed input selectio832" bitfld.long 0xD00 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD00 0.--7. 1. "SSS,Source Signal Select" line.long 0xD04 "MSCR_MUX833,SIUL2 multiplexed signal configuration register 833 for multiplexed input selectio833" bitfld.long 0xD04 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD04 0.--7. 1. "SSS,Source Signal Select" line.long 0xD08 "MSCR_MUX834,SIUL2 multiplexed signal configuration register 834 for multiplexed input selectio834" bitfld.long 0xD08 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD08 0.--7. 1. "SSS,Source Signal Select" line.long 0xD0C "MSCR_MUX835,SIUL2 multiplexed signal configuration register 835 for multiplexed input selectio835" bitfld.long 0xD0C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD0C 0.--7. 1. "SSS,Source Signal Select" line.long 0xD10 "MSCR_MUX836,SIUL2 multiplexed signal configuration register 836 for multiplexed input selectio836" bitfld.long 0xD10 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD10 0.--7. 1. "SSS,Source Signal Select" line.long 0xD14 "MSCR_MUX837,SIUL2 multiplexed signal configuration register 837 for multiplexed input selectio837" bitfld.long 0xD14 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD14 0.--7. 1. "SSS,Source Signal Select" line.long 0xD18 "MSCR_MUX838,SIUL2 multiplexed signal configuration register 838 for multiplexed input selectio838" bitfld.long 0xD18 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD18 0.--7. 1. "SSS,Source Signal Select" line.long 0xD1C "MSCR_MUX839,SIUL2 multiplexed signal configuration register 839 for multiplexed input selectio839" bitfld.long 0xD1C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD1C 0.--7. 1. "SSS,Source Signal Select" line.long 0xD20 "MSCR_MUX840,SIUL2 multiplexed signal configuration register 840 for multiplexed input selectio840" bitfld.long 0xD20 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD20 0.--7. 1. "SSS,Source Signal Select" line.long 0xD24 "MSCR_MUX841,SIUL2 multiplexed signal configuration register 841 for multiplexed input selectio841" bitfld.long 0xD24 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD24 0.--7. 1. "SSS,Source Signal Select" line.long 0xD28 "MSCR_MUX842,SIUL2 multiplexed signal configuration register 842 for multiplexed input selectio842" bitfld.long 0xD28 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD28 0.--7. 1. "SSS,Source Signal Select" line.long 0xD2C "MSCR_MUX843,SIUL2 multiplexed signal configuration register 843 for multiplexed input selectio843" bitfld.long 0xD2C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD2C 0.--7. 1. "SSS,Source Signal Select" line.long 0xD30 "MSCR_MUX844,SIUL2 multiplexed signal configuration register 844 for multiplexed input selectio844" bitfld.long 0xD30 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD30 0.--7. 1. "SSS,Source Signal Select" line.long 0xD34 "MSCR_MUX845,SIUL2 multiplexed signal configuration register 845 for multiplexed input selectio845" bitfld.long 0xD34 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD34 0.--7. 1. "SSS,Source Signal Select" line.long 0xD38 "MSCR_MUX846,SIUL2 multiplexed signal configuration register 846 for multiplexed input selectio846" bitfld.long 0xD38 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD38 0.--7. 1. "SSS,Source Signal Select" line.long 0xD3C "MSCR_MUX847,SIUL2 multiplexed signal configuration register 847 for multiplexed input selectio847" bitfld.long 0xD3C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD3C 0.--7. 1. "SSS,Source Signal Select" line.long 0xD40 "MSCR_MUX848,SIUL2 multiplexed signal configuration register 848 for multiplexed input selectio848" bitfld.long 0xD40 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD40 0.--7. 1. "SSS,Source Signal Select" line.long 0xD44 "MSCR_MUX849,SIUL2 multiplexed signal configuration register 849 for multiplexed input selectio849" bitfld.long 0xD44 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD44 0.--7. 1. "SSS,Source Signal Select" line.long 0xD48 "MSCR_MUX850,SIUL2 multiplexed signal configuration register 850 for multiplexed input selectio850" bitfld.long 0xD48 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD48 0.--7. 1. "SSS,Source Signal Select" line.long 0xD4C "MSCR_MUX851,SIUL2 multiplexed signal configuration register 851 for multiplexed input selectio851" bitfld.long 0xD4C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD4C 0.--7. 1. "SSS,Source Signal Select" line.long 0xD50 "MSCR_MUX852,SIUL2 multiplexed signal configuration register 852 for multiplexed input selectio852" bitfld.long 0xD50 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD50 0.--7. 1. "SSS,Source Signal Select" line.long 0xD54 "MSCR_MUX853,SIUL2 multiplexed signal configuration register 853 for multiplexed input selectio853" bitfld.long 0xD54 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD54 0.--7. 1. "SSS,Source Signal Select" line.long 0xD58 "MSCR_MUX854,SIUL2 multiplexed signal configuration register 854 for multiplexed input selectio854" bitfld.long 0xD58 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD58 0.--7. 1. "SSS,Source Signal Select" line.long 0xD5C "MSCR_MUX855,SIUL2 multiplexed signal configuration register 855 for multiplexed input selectio855" bitfld.long 0xD5C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD5C 0.--7. 1. "SSS,Source Signal Select" line.long 0xD60 "MSCR_MUX856,SIUL2 multiplexed signal configuration register 856 for multiplexed input selectio856" bitfld.long 0xD60 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD60 0.--7. 1. "SSS,Source Signal Select" line.long 0xD64 "MSCR_MUX857,SIUL2 multiplexed signal configuration register 857 for multiplexed input selectio857" bitfld.long 0xD64 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD64 0.--7. 1. "SSS,Source Signal Select" line.long 0xD68 "MSCR_MUX858,SIUL2 multiplexed signal configuration register 858 for multiplexed input selectio858" bitfld.long 0xD68 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD68 0.--7. 1. "SSS,Source Signal Select" line.long 0xD6C "MSCR_MUX859,SIUL2 multiplexed signal configuration register 859 for multiplexed input selectio859" bitfld.long 0xD6C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD6C 0.--7. 1. "SSS,Source Signal Select" line.long 0xD70 "MSCR_MUX860,SIUL2 multiplexed signal configuration register 860 for multiplexed input selectio860" bitfld.long 0xD70 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD70 0.--7. 1. "SSS,Source Signal Select" line.long 0xD74 "MSCR_MUX861,SIUL2 multiplexed signal configuration register 861 for multiplexed input selectio861" bitfld.long 0xD74 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD74 0.--7. 1. "SSS,Source Signal Select" line.long 0xD78 "MSCR_MUX862,SIUL2 multiplexed signal configuration register 862 for multiplexed input selectio862" bitfld.long 0xD78 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD78 0.--7. 1. "SSS,Source Signal Select" line.long 0xD7C "MSCR_MUX863,SIUL2 multiplexed signal configuration register 863 for multiplexed input selectio863" bitfld.long 0xD7C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD7C 0.--7. 1. "SSS,Source Signal Select" line.long 0xD80 "MSCR_MUX864,SIUL2 multiplexed signal configuration register 864 for multiplexed input selectio864" bitfld.long 0xD80 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD80 0.--7. 1. "SSS,Source Signal Select" line.long 0xD84 "MSCR_MUX865,SIUL2 multiplexed signal configuration register 865 for multiplexed input selectio865" bitfld.long 0xD84 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD84 0.--7. 1. "SSS,Source Signal Select" line.long 0xD88 "MSCR_MUX866,SIUL2 multiplexed signal configuration register 866 for multiplexed input selectio866" bitfld.long 0xD88 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD88 0.--7. 1. "SSS,Source Signal Select" line.long 0xD8C "MSCR_MUX867,SIUL2 multiplexed signal configuration register 867 for multiplexed input selectio867" bitfld.long 0xD8C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD8C 0.--7. 1. "SSS,Source Signal Select" line.long 0xD90 "MSCR_MUX868,SIUL2 multiplexed signal configuration register 868 for multiplexed input selectio868" bitfld.long 0xD90 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD90 0.--7. 1. "SSS,Source Signal Select" line.long 0xD94 "MSCR_MUX869,SIUL2 multiplexed signal configuration register 869 for multiplexed input selectio869" bitfld.long 0xD94 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD94 0.--7. 1. "SSS,Source Signal Select" line.long 0xD98 "MSCR_MUX870,SIUL2 multiplexed signal configuration register 870 for multiplexed input selectio870" bitfld.long 0xD98 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD98 0.--7. 1. "SSS,Source Signal Select" line.long 0xD9C "MSCR_MUX871,SIUL2 multiplexed signal configuration register 871 for multiplexed input selectio871" bitfld.long 0xD9C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD9C 0.--7. 1. "SSS,Source Signal Select" line.long 0xDA0 "MSCR_MUX872,SIUL2 multiplexed signal configuration register 872 for multiplexed input selectio872" bitfld.long 0xDA0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDA0 0.--7. 1. "SSS,Source Signal Select" line.long 0xDA4 "MSCR_MUX873,SIUL2 multiplexed signal configuration register 873 for multiplexed input selectio873" bitfld.long 0xDA4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDA4 0.--7. 1. "SSS,Source Signal Select" line.long 0xDA8 "MSCR_MUX874,SIUL2 multiplexed signal configuration register 874 for multiplexed input selectio874" bitfld.long 0xDA8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDA8 0.--7. 1. "SSS,Source Signal Select" line.long 0xDAC "MSCR_MUX875,SIUL2 multiplexed signal configuration register 875 for multiplexed input selectio875" bitfld.long 0xDAC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDAC 0.--7. 1. "SSS,Source Signal Select" line.long 0xDB0 "MSCR_MUX876,SIUL2 multiplexed signal configuration register 876 for multiplexed input selectio876" bitfld.long 0xDB0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDB0 0.--7. 1. "SSS,Source Signal Select" line.long 0xDB4 "MSCR_MUX877,SIUL2 multiplexed signal configuration register 877 for multiplexed input selectio877" bitfld.long 0xDB4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDB4 0.--7. 1. "SSS,Source Signal Select" line.long 0xDB8 "MSCR_MUX878,SIUL2 multiplexed signal configuration register 878 for multiplexed input selectio878" bitfld.long 0xDB8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDB8 0.--7. 1. "SSS,Source Signal Select" line.long 0xDBC "MSCR_MUX879,SIUL2 multiplexed signal configuration register 879 for multiplexed input selectio879" bitfld.long 0xDBC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDBC 0.--7. 1. "SSS,Source Signal Select" line.long 0xDC0 "MSCR_MUX880,SIUL2 multiplexed signal configuration register 880 for multiplexed input selectio880" bitfld.long 0xDC0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDC0 0.--7. 1. "SSS,Source Signal Select" line.long 0xDC4 "MSCR_MUX881,SIUL2 multiplexed signal configuration register 881 for multiplexed input selectio881" bitfld.long 0xDC4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDC4 0.--7. 1. "SSS,Source Signal Select" line.long 0xDC8 "MSCR_MUX882,SIUL2 multiplexed signal configuration register 882 for multiplexed input selectio882" bitfld.long 0xDC8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDC8 0.--7. 1. "SSS,Source Signal Select" line.long 0xDCC "MSCR_MUX883,SIUL2 multiplexed signal configuration register 883 for multiplexed input selectio883" bitfld.long 0xDCC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDCC 0.--7. 1. "SSS,Source Signal Select" line.long 0xDD0 "MSCR_MUX884,SIUL2 multiplexed signal configuration register 884 for multiplexed input selectio884" bitfld.long 0xDD0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDD0 0.--7. 1. "SSS,Source Signal Select" line.long 0xDD4 "MSCR_MUX885,SIUL2 multiplexed signal configuration register 885 for multiplexed input selectio885" bitfld.long 0xDD4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDD4 0.--7. 1. "SSS,Source Signal Select" line.long 0xDD8 "MSCR_MUX886,SIUL2 multiplexed signal configuration register 886 for multiplexed input selectio886" bitfld.long 0xDD8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDD8 0.--7. 1. "SSS,Source Signal Select" line.long 0xDDC "MSCR_MUX887,SIUL2 multiplexed signal configuration register 887 for multiplexed input selectio887" bitfld.long 0xDDC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDDC 0.--7. 1. "SSS,Source Signal Select" line.long 0xDE0 "MSCR_MUX888,SIUL2 multiplexed signal configuration register 888 for multiplexed input selectio888" bitfld.long 0xDE0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDE0 0.--7. 1. "SSS,Source Signal Select" line.long 0xDE4 "MSCR_MUX889,SIUL2 multiplexed signal configuration register 889 for multiplexed input selectio889" bitfld.long 0xDE4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDE4 0.--7. 1. "SSS,Source Signal Select" line.long 0xDE8 "MSCR_MUX890,SIUL2 multiplexed signal configuration register 890 for multiplexed input selectio890" bitfld.long 0xDE8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDE8 0.--7. 1. "SSS,Source Signal Select" line.long 0xDEC "MSCR_MUX891,SIUL2 multiplexed signal configuration register 891 for multiplexed input selectio891" bitfld.long 0xDEC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDEC 0.--7. 1. "SSS,Source Signal Select" line.long 0xDF0 "MSCR_MUX892,SIUL2 multiplexed signal configuration register 892 for multiplexed input selectio892" bitfld.long 0xDF0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDF0 0.--7. 1. "SSS,Source Signal Select" line.long 0xDF4 "MSCR_MUX893,SIUL2 multiplexed signal configuration register 893 for multiplexed input selectio893" bitfld.long 0xDF4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDF4 0.--7. 1. "SSS,Source Signal Select" line.long 0xDF8 "MSCR_MUX894,SIUL2 multiplexed signal configuration register 894 for multiplexed input selectio894" bitfld.long 0xDF8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDF8 0.--7. 1. "SSS,Source Signal Select" line.long 0xDFC "MSCR_MUX895,SIUL2 multiplexed signal configuration register 895 for multiplexed input selectio895" bitfld.long 0xDFC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDFC 0.--7. 1. "SSS,Source Signal Select" line.long 0xE00 "MSCR_MUX896,SIUL2 multiplexed signal configuration register 896 for multiplexed input selectio896" bitfld.long 0xE00 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE00 0.--7. 1. "SSS,Source Signal Select" line.long 0xE04 "MSCR_MUX897,SIUL2 multiplexed signal configuration register 897 for multiplexed input selectio897" bitfld.long 0xE04 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE04 0.--7. 1. "SSS,Source Signal Select" line.long 0xE08 "MSCR_MUX898,SIUL2 multiplexed signal configuration register 898 for multiplexed input selectio898" bitfld.long 0xE08 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE08 0.--7. 1. "SSS,Source Signal Select" line.long 0xE0C "MSCR_MUX899,SIUL2 multiplexed signal configuration register 899 for multiplexed input selectio899" bitfld.long 0xE0C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE0C 0.--7. 1. "SSS,Source Signal Select" line.long 0xE10 "MSCR_MUX900,SIUL2 multiplexed signal configuration register 900 for multiplexed input selectio900" bitfld.long 0xE10 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE10 0.--7. 1. "SSS,Source Signal Select" line.long 0xE14 "MSCR_MUX901,SIUL2 multiplexed signal configuration register 901 for multiplexed input selectio901" bitfld.long 0xE14 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE14 0.--7. 1. "SSS,Source Signal Select" line.long 0xE18 "MSCR_MUX902,SIUL2 multiplexed signal configuration register 902 for multiplexed input selectio902" bitfld.long 0xE18 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE18 0.--7. 1. "SSS,Source Signal Select" line.long 0xE1C "MSCR_MUX903,SIUL2 multiplexed signal configuration register 903 for multiplexed input selectio903" bitfld.long 0xE1C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE1C 0.--7. 1. "SSS,Source Signal Select" line.long 0xE20 "MSCR_MUX904,SIUL2 multiplexed signal configuration register 904 for multiplexed input selectio904" bitfld.long 0xE20 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE20 0.--7. 1. "SSS,Source Signal Select" line.long 0xE24 "MSCR_MUX905,SIUL2 multiplexed signal configuration register 905 for multiplexed input selectio905" bitfld.long 0xE24 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE24 0.--7. 1. "SSS,Source Signal Select" line.long 0xE28 "MSCR_MUX906,SIUL2 multiplexed signal configuration register 906 for multiplexed input selectio906" bitfld.long 0xE28 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE28 0.--7. 1. "SSS,Source Signal Select" line.long 0xE2C "MSCR_MUX907,SIUL2 multiplexed signal configuration register 907 for multiplexed input selectio907" bitfld.long 0xE2C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE2C 0.--7. 1. "SSS,Source Signal Select" line.long 0xE30 "MSCR_MUX908,SIUL2 multiplexed signal configuration register 908 for multiplexed input selectio908" bitfld.long 0xE30 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE30 0.--7. 1. "SSS,Source Signal Select" line.long 0xE34 "MSCR_MUX909,SIUL2 multiplexed signal configuration register 909 for multiplexed input selectio909" bitfld.long 0xE34 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE34 0.--7. 1. "SSS,Source Signal Select" line.long 0xE38 "MSCR_MUX910,SIUL2 multiplexed signal configuration register 910 for multiplexed input selectio910" bitfld.long 0xE38 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE38 0.--7. 1. "SSS,Source Signal Select" line.long 0xE3C "MSCR_MUX911,SIUL2 multiplexed signal configuration register 911 for multiplexed input selectio911" bitfld.long 0xE3C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE3C 0.--7. 1. "SSS,Source Signal Select" line.long 0xE40 "MSCR_MUX912,SIUL2 multiplexed signal configuration register 912 for multiplexed input selectio912" bitfld.long 0xE40 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE40 0.--7. 1. "SSS,Source Signal Select" line.long 0xE44 "MSCR_MUX913,SIUL2 multiplexed signal configuration register 913 for multiplexed input selectio913" bitfld.long 0xE44 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE44 0.--7. 1. "SSS,Source Signal Select" line.long 0xE48 "MSCR_MUX914,SIUL2 multiplexed signal configuration register 914 for multiplexed input selectio914" bitfld.long 0xE48 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE48 0.--7. 1. "SSS,Source Signal Select" line.long 0xE4C "MSCR_MUX915,SIUL2 multiplexed signal configuration register 915 for multiplexed input selectio915" bitfld.long 0xE4C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE4C 0.--7. 1. "SSS,Source Signal Select" line.long 0xE50 "MSCR_MUX916,SIUL2 multiplexed signal configuration register 916 for multiplexed input selectio916" bitfld.long 0xE50 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE50 0.--7. 1. "SSS,Source Signal Select" line.long 0xE54 "MSCR_MUX917,SIUL2 multiplexed signal configuration register 917 for multiplexed input selectio917" bitfld.long 0xE54 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE54 0.--7. 1. "SSS,Source Signal Select" line.long 0xE58 "MSCR_MUX918,SIUL2 multiplexed signal configuration register 918 for multiplexed input selectio918" bitfld.long 0xE58 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE58 0.--7. 1. "SSS,Source Signal Select" line.long 0xE5C "MSCR_MUX919,SIUL2 multiplexed signal configuration register 919 for multiplexed input selectio919" bitfld.long 0xE5C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE5C 0.--7. 1. "SSS,Source Signal Select" line.long 0xE60 "MSCR_MUX920,SIUL2 multiplexed signal configuration register 920 for multiplexed input selectio920" bitfld.long 0xE60 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE60 0.--7. 1. "SSS,Source Signal Select" line.long 0xE64 "MSCR_MUX921,SIUL2 multiplexed signal configuration register 921 for multiplexed input selectio921" bitfld.long 0xE64 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE64 0.--7. 1. "SSS,Source Signal Select" line.long 0xE68 "MSCR_MUX922,SIUL2 multiplexed signal configuration register 922 for multiplexed input selectio922" bitfld.long 0xE68 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE68 0.--7. 1. "SSS,Source Signal Select" line.long 0xE6C "MSCR_MUX923,SIUL2 multiplexed signal configuration register 923 for multiplexed input selectio923" bitfld.long 0xE6C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE6C 0.--7. 1. "SSS,Source Signal Select" line.long 0xE70 "MSCR_MUX924,SIUL2 multiplexed signal configuration register 924 for multiplexed input selectio924" bitfld.long 0xE70 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE70 0.--7. 1. "SSS,Source Signal Select" line.long 0xE74 "MSCR_MUX925,SIUL2 multiplexed signal configuration register 925 for multiplexed input selectio925" bitfld.long 0xE74 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE74 0.--7. 1. "SSS,Source Signal Select" line.long 0xE78 "MSCR_MUX926,SIUL2 multiplexed signal configuration register 926 for multiplexed input selectio926" bitfld.long 0xE78 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE78 0.--7. 1. "SSS,Source Signal Select" line.long 0xE7C "MSCR_MUX927,SIUL2 multiplexed signal configuration register 927 for multiplexed input selectio927" bitfld.long 0xE7C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE7C 0.--7. 1. "SSS,Source Signal Select" line.long 0xE80 "MSCR_MUX928,SIUL2 multiplexed signal configuration register 928 for multiplexed input selectio928" bitfld.long 0xE80 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE80 0.--7. 1. "SSS,Source Signal Select" line.long 0xE84 "MSCR_MUX929,SIUL2 multiplexed signal configuration register 929 for multiplexed input selectio929" bitfld.long 0xE84 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE84 0.--7. 1. "SSS,Source Signal Select" line.long 0xE88 "MSCR_MUX930,SIUL2 multiplexed signal configuration register 930 for multiplexed input selectio930" bitfld.long 0xE88 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE88 0.--7. 1. "SSS,Source Signal Select" line.long 0xE8C "MSCR_MUX931,SIUL2 multiplexed signal configuration register 931 for multiplexed input selectio931" bitfld.long 0xE8C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE8C 0.--7. 1. "SSS,Source Signal Select" line.long 0xE90 "MSCR_MUX932,SIUL2 multiplexed signal configuration register 932 for multiplexed input selectio932" bitfld.long 0xE90 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE90 0.--7. 1. "SSS,Source Signal Select" line.long 0xE94 "MSCR_MUX933,SIUL2 multiplexed signal configuration register 933 for multiplexed input selectio933" bitfld.long 0xE94 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE94 0.--7. 1. "SSS,Source Signal Select" line.long 0xE98 "MSCR_MUX934,SIUL2 multiplexed signal configuration register 934 for multiplexed input selectio934" bitfld.long 0xE98 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE98 0.--7. 1. "SSS,Source Signal Select" line.long 0xE9C "MSCR_MUX935,SIUL2 multiplexed signal configuration register 935 for multiplexed input selectio935" bitfld.long 0xE9C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE9C 0.--7. 1. "SSS,Source Signal Select" line.long 0xEA0 "MSCR_MUX936,SIUL2 multiplexed signal configuration register 936 for multiplexed input selectio936" bitfld.long 0xEA0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEA0 0.--7. 1. "SSS,Source Signal Select" line.long 0xEA4 "MSCR_MUX937,SIUL2 multiplexed signal configuration register 937 for multiplexed input selectio937" bitfld.long 0xEA4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEA4 0.--7. 1. "SSS,Source Signal Select" line.long 0xEA8 "MSCR_MUX938,SIUL2 multiplexed signal configuration register 938 for multiplexed input selectio938" bitfld.long 0xEA8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEA8 0.--7. 1. "SSS,Source Signal Select" line.long 0xEAC "MSCR_MUX939,SIUL2 multiplexed signal configuration register 939 for multiplexed input selectio939" bitfld.long 0xEAC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEAC 0.--7. 1. "SSS,Source Signal Select" line.long 0xEB0 "MSCR_MUX940,SIUL2 multiplexed signal configuration register 940 for multiplexed input selectio940" bitfld.long 0xEB0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEB0 0.--7. 1. "SSS,Source Signal Select" line.long 0xEB4 "MSCR_MUX941,SIUL2 multiplexed signal configuration register 941 for multiplexed input selectio941" bitfld.long 0xEB4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEB4 0.--7. 1. "SSS,Source Signal Select" line.long 0xEB8 "MSCR_MUX942,SIUL2 multiplexed signal configuration register 942 for multiplexed input selectio942" bitfld.long 0xEB8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEB8 0.--7. 1. "SSS,Source Signal Select" line.long 0xEBC "MSCR_MUX943,SIUL2 multiplexed signal configuration register 943 for multiplexed input selectio943" bitfld.long 0xEBC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEBC 0.--7. 1. "SSS,Source Signal Select" line.long 0xEC0 "MSCR_MUX944,SIUL2 multiplexed signal configuration register 944 for multiplexed input selectio944" bitfld.long 0xEC0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEC0 0.--7. 1. "SSS,Source Signal Select" line.long 0xEC4 "MSCR_MUX945,SIUL2 multiplexed signal configuration register 945 for multiplexed input selectio945" bitfld.long 0xEC4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEC4 0.--7. 1. "SSS,Source Signal Select" line.long 0xEC8 "MSCR_MUX946,SIUL2 multiplexed signal configuration register 946 for multiplexed input selectio946" bitfld.long 0xEC8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEC8 0.--7. 1. "SSS,Source Signal Select" line.long 0xECC "MSCR_MUX947,SIUL2 multiplexed signal configuration register 947 for multiplexed input selectio947" bitfld.long 0xECC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xECC 0.--7. 1. "SSS,Source Signal Select" line.long 0xED0 "MSCR_MUX948,SIUL2 multiplexed signal configuration register 948 for multiplexed input selectio948" bitfld.long 0xED0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xED0 0.--7. 1. "SSS,Source Signal Select" line.long 0xED4 "MSCR_MUX949,SIUL2 multiplexed signal configuration register 949 for multiplexed input selectio949" bitfld.long 0xED4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xED4 0.--7. 1. "SSS,Source Signal Select" line.long 0xED8 "MSCR_MUX950,SIUL2 multiplexed signal configuration register 950 for multiplexed input selectio950" bitfld.long 0xED8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xED8 0.--7. 1. "SSS,Source Signal Select" line.long 0xEDC "MSCR_MUX951,SIUL2 multiplexed signal configuration register 951 for multiplexed input selectio951" bitfld.long 0xEDC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEDC 0.--7. 1. "SSS,Source Signal Select" line.long 0xEE0 "MSCR_MUX952,SIUL2 multiplexed signal configuration register 952 for multiplexed input selectio952" bitfld.long 0xEE0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEE0 0.--7. 1. "SSS,Source Signal Select" line.long 0xEE4 "MSCR_MUX953,SIUL2 multiplexed signal configuration register 953 for multiplexed input selectio953" bitfld.long 0xEE4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEE4 0.--7. 1. "SSS,Source Signal Select" line.long 0xEE8 "MSCR_MUX954,SIUL2 multiplexed signal configuration register 954 for multiplexed input selectio954" bitfld.long 0xEE8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEE8 0.--7. 1. "SSS,Source Signal Select" line.long 0xEEC "MSCR_MUX955,SIUL2 multiplexed signal configuration register 955 for multiplexed input selectio955" bitfld.long 0xEEC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEEC 0.--7. 1. "SSS,Source Signal Select" line.long 0xEF0 "MSCR_MUX956,SIUL2 multiplexed signal configuration register 956 for multiplexed input selectio956" bitfld.long 0xEF0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEF0 0.--7. 1. "SSS,Source Signal Select" line.long 0xEF4 "MSCR_MUX957,SIUL2 multiplexed signal configuration register 957 for multiplexed input selectio957" bitfld.long 0xEF4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEF4 0.--7. 1. "SSS,Source Signal Select" line.long 0xEF8 "MSCR_MUX958,SIUL2 multiplexed signal configuration register 958 for multiplexed input selectio958" bitfld.long 0xEF8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEF8 0.--7. 1. "SSS,Source Signal Select" line.long 0xEFC "MSCR_MUX959,SIUL2 multiplexed signal configuration register 959 for multiplexed input selectio959" bitfld.long 0xEFC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEFC 0.--7. 1. "SSS,Source Signal Select" line.long 0xF00 "MSCR_MUX960,SIUL2 multiplexed signal configuration register 960 for multiplexed input selectio960" bitfld.long 0xF00 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF00 0.--7. 1. "SSS,Source Signal Select" line.long 0xF04 "MSCR_MUX961,SIUL2 multiplexed signal configuration register 961 for multiplexed input selectio961" bitfld.long 0xF04 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF04 0.--7. 1. "SSS,Source Signal Select" line.long 0xF08 "MSCR_MUX962,SIUL2 multiplexed signal configuration register 962 for multiplexed input selectio962" bitfld.long 0xF08 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF08 0.--7. 1. "SSS,Source Signal Select" line.long 0xF0C "MSCR_MUX963,SIUL2 multiplexed signal configuration register 963 for multiplexed input selectio963" bitfld.long 0xF0C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF0C 0.--7. 1. "SSS,Source Signal Select" line.long 0xF10 "MSCR_MUX964,SIUL2 multiplexed signal configuration register 964 for multiplexed input selectio964" bitfld.long 0xF10 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF10 0.--7. 1. "SSS,Source Signal Select" line.long 0xF14 "MSCR_MUX965,SIUL2 multiplexed signal configuration register 965 for multiplexed input selectio965" bitfld.long 0xF14 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF14 0.--7. 1. "SSS,Source Signal Select" line.long 0xF18 "MSCR_MUX966,SIUL2 multiplexed signal configuration register 966 for multiplexed input selectio966" bitfld.long 0xF18 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF18 0.--7. 1. "SSS,Source Signal Select" line.long 0xF1C "MSCR_MUX967,SIUL2 multiplexed signal configuration register 967 for multiplexed input selectio967" bitfld.long 0xF1C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF1C 0.--7. 1. "SSS,Source Signal Select" line.long 0xF20 "MSCR_MUX968,SIUL2 multiplexed signal configuration register 968 for multiplexed input selectio968" bitfld.long 0xF20 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF20 0.--7. 1. "SSS,Source Signal Select" line.long 0xF24 "MSCR_MUX969,SIUL2 multiplexed signal configuration register 969 for multiplexed input selectio969" bitfld.long 0xF24 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF24 0.--7. 1. "SSS,Source Signal Select" line.long 0xF28 "MSCR_MUX970,SIUL2 multiplexed signal configuration register 970 for multiplexed input selectio970" bitfld.long 0xF28 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF28 0.--7. 1. "SSS,Source Signal Select" line.long 0xF2C "MSCR_MUX971,SIUL2 multiplexed signal configuration register 971 for multiplexed input selectio971" bitfld.long 0xF2C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF2C 0.--7. 1. "SSS,Source Signal Select" line.long 0xF30 "MSCR_MUX972,SIUL2 multiplexed signal configuration register 972 for multiplexed input selectio972" bitfld.long 0xF30 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF30 0.--7. 1. "SSS,Source Signal Select" line.long 0xF34 "MSCR_MUX973,SIUL2 multiplexed signal configuration register 973 for multiplexed input selectio973" bitfld.long 0xF34 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF34 0.--7. 1. "SSS,Source Signal Select" line.long 0xF38 "MSCR_MUX974,SIUL2 multiplexed signal configuration register 974 for multiplexed input selectio974" bitfld.long 0xF38 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF38 0.--7. 1. "SSS,Source Signal Select" line.long 0xF3C "MSCR_MUX975,SIUL2 multiplexed signal configuration register 975 for multiplexed input selectio975" bitfld.long 0xF3C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF3C 0.--7. 1. "SSS,Source Signal Select" line.long 0xF40 "MSCR_MUX976,SIUL2 multiplexed signal configuration register 976 for multiplexed input selectio976" bitfld.long 0xF40 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF40 0.--7. 1. "SSS,Source Signal Select" line.long 0xF44 "MSCR_MUX977,SIUL2 multiplexed signal configuration register 977 for multiplexed input selectio977" bitfld.long 0xF44 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF44 0.--7. 1. "SSS,Source Signal Select" line.long 0xF48 "MSCR_MUX978,SIUL2 multiplexed signal configuration register 978 for multiplexed input selectio978" bitfld.long 0xF48 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF48 0.--7. 1. "SSS,Source Signal Select" line.long 0xF4C "MSCR_MUX979,SIUL2 multiplexed signal configuration register 979 for multiplexed input selectio979" bitfld.long 0xF4C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF4C 0.--7. 1. "SSS,Source Signal Select" line.long 0xF50 "MSCR_MUX980,SIUL2 multiplexed signal configuration register 980 for multiplexed input selectio980" bitfld.long 0xF50 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF50 0.--7. 1. "SSS,Source Signal Select" line.long 0xF54 "MSCR_MUX981,SIUL2 multiplexed signal configuration register 981 for multiplexed input selectio981" bitfld.long 0xF54 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF54 0.--7. 1. "SSS,Source Signal Select" line.long 0xF58 "MSCR_MUX982,SIUL2 multiplexed signal configuration register 982 for multiplexed input selectio982" bitfld.long 0xF58 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF58 0.--7. 1. "SSS,Source Signal Select" line.long 0xF5C "MSCR_MUX983,SIUL2 multiplexed signal configuration register 983 for multiplexed input selectio983" bitfld.long 0xF5C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF5C 0.--7. 1. "SSS,Source Signal Select" line.long 0xF60 "MSCR_MUX984,SIUL2 multiplexed signal configuration register 984 for multiplexed input selectio984" bitfld.long 0xF60 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF60 0.--7. 1. "SSS,Source Signal Select" line.long 0xF64 "MSCR_MUX985,SIUL2 multiplexed signal configuration register 985 for multiplexed input selectio985" bitfld.long 0xF64 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF64 0.--7. 1. "SSS,Source Signal Select" line.long 0xF68 "MSCR_MUX986,SIUL2 multiplexed signal configuration register 986 for multiplexed input selectio986" bitfld.long 0xF68 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF68 0.--7. 1. "SSS,Source Signal Select" line.long 0xF6C "MSCR_MUX987,SIUL2 multiplexed signal configuration register 987 for multiplexed input selectio987" bitfld.long 0xF6C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF6C 0.--7. 1. "SSS,Source Signal Select" line.long 0xF70 "MSCR_MUX988,SIUL2 multiplexed signal configuration register 988 for multiplexed input selectio988" bitfld.long 0xF70 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF70 0.--7. 1. "SSS,Source Signal Select" line.long 0xF74 "MSCR_MUX989,SIUL2 multiplexed signal configuration register 989 for multiplexed input selectio989" bitfld.long 0xF74 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF74 0.--7. 1. "SSS,Source Signal Select" line.long 0xF78 "MSCR_MUX990,SIUL2 multiplexed signal configuration register 990 for multiplexed input selectio990" bitfld.long 0xF78 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF78 0.--7. 1. "SSS,Source Signal Select" line.long 0xF7C "MSCR_MUX991,SIUL2 multiplexed signal configuration register 991 for multiplexed input selectio991" bitfld.long 0xF7C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF7C 0.--7. 1. "SSS,Source Signal Select" line.long 0xF80 "MSCR_MUX992,SIUL2 multiplexed signal configuration register 992 for multiplexed input selectio992" bitfld.long 0xF80 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF80 0.--7. 1. "SSS,Source Signal Select" line.long 0xF84 "MSCR_MUX993,SIUL2 multiplexed signal configuration register 993 for multiplexed input selectio993" bitfld.long 0xF84 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF84 0.--7. 1. "SSS,Source Signal Select" line.long 0xF88 "MSCR_MUX994,SIUL2 multiplexed signal configuration register 994 for multiplexed input selectio994" bitfld.long 0xF88 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF88 0.--7. 1. "SSS,Source Signal Select" line.long 0xF8C "MSCR_MUX995,SIUL2 multiplexed signal configuration register 995 for multiplexed input selectio995" bitfld.long 0xF8C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF8C 0.--7. 1. "SSS,Source Signal Select" line.long 0xF90 "MSCR_MUX996,SIUL2 multiplexed signal configuration register 996 for multiplexed input selectio996" bitfld.long 0xF90 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF90 0.--7. 1. "SSS,Source Signal Select" line.long 0xF94 "MSCR_MUX997,SIUL2 multiplexed signal configuration register 997 for multiplexed input selectio997" bitfld.long 0xF94 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF94 0.--7. 1. "SSS,Source Signal Select" line.long 0xF98 "MSCR_MUX998,SIUL2 multiplexed signal configuration register 998 for multiplexed input selectio998" bitfld.long 0xF98 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF98 0.--7. 1. "SSS,Source Signal Select" line.long 0xF9C "MSCR_MUX999,SIUL2 multiplexed signal configuration register 999 for multiplexed input selectio999" bitfld.long 0xF9C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF9C 0.--7. 1. "SSS,Source Signal Select" line.long 0xFA0 "MSCR_MUX1000,SIUL2 multiplexed signal configuration register 1000 for multiplexed input selectio1000" bitfld.long 0xFA0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFA0 0.--7. 1. "SSS,Source Signal Select" line.long 0xFA4 "MSCR_MUX1001,SIUL2 multiplexed signal configuration register 1001 for multiplexed input selectio1001" bitfld.long 0xFA4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFA4 0.--7. 1. "SSS,Source Signal Select" line.long 0xFA8 "MSCR_MUX1002,SIUL2 multiplexed signal configuration register 1002 for multiplexed input selectio1002" bitfld.long 0xFA8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFA8 0.--7. 1. "SSS,Source Signal Select" line.long 0xFAC "MSCR_MUX1003,SIUL2 multiplexed signal configuration register 1003 for multiplexed input selectio1003" bitfld.long 0xFAC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFAC 0.--7. 1. "SSS,Source Signal Select" line.long 0xFB0 "MSCR_MUX1004,SIUL2 multiplexed signal configuration register 1004 for multiplexed input selectio1004" bitfld.long 0xFB0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFB0 0.--7. 1. "SSS,Source Signal Select" line.long 0xFB4 "MSCR_MUX1005,SIUL2 multiplexed signal configuration register 1005 for multiplexed input selectio1005" bitfld.long 0xFB4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFB4 0.--7. 1. "SSS,Source Signal Select" line.long 0xFB8 "MSCR_MUX1006,SIUL2 multiplexed signal configuration register 1006 for multiplexed input selectio1006" bitfld.long 0xFB8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFB8 0.--7. 1. "SSS,Source Signal Select" line.long 0xFBC "MSCR_MUX1007,SIUL2 multiplexed signal configuration register 1007 for multiplexed input selectio1007" bitfld.long 0xFBC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFBC 0.--7. 1. "SSS,Source Signal Select" line.long 0xFC0 "MSCR_MUX1008,SIUL2 multiplexed signal configuration register 1008 for multiplexed input selectio1008" bitfld.long 0xFC0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFC0 0.--7. 1. "SSS,Source Signal Select" line.long 0xFC4 "MSCR_MUX1009,SIUL2 multiplexed signal configuration register 1009 for multiplexed input selectio1009" bitfld.long 0xFC4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFC4 0.--7. 1. "SSS,Source Signal Select" line.long 0xFC8 "MSCR_MUX1010,SIUL2 multiplexed signal configuration register 1010 for multiplexed input selectio1010" bitfld.long 0xFC8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFC8 0.--7. 1. "SSS,Source Signal Select" line.long 0xFCC "MSCR_MUX1011,SIUL2 multiplexed signal configuration register 1011 for multiplexed input selectio1011" bitfld.long 0xFCC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFCC 0.--7. 1. "SSS,Source Signal Select" line.long 0xFD0 "MSCR_MUX1012,SIUL2 multiplexed signal configuration register 1012 for multiplexed input selectio1012" bitfld.long 0xFD0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFD0 0.--7. 1. "SSS,Source Signal Select" line.long 0xFD4 "MSCR_MUX1013,SIUL2 multiplexed signal configuration register 1013 for multiplexed input selectio1013" bitfld.long 0xFD4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFD4 0.--7. 1. "SSS,Source Signal Select" line.long 0xFD8 "MSCR_MUX1014,SIUL2 multiplexed signal configuration register 1014 for multiplexed input selectio1014" bitfld.long 0xFD8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFD8 0.--7. 1. "SSS,Source Signal Select" line.long 0xFDC "MSCR_MUX1015,SIUL2 multiplexed signal configuration register 1015 for multiplexed input selectio1015" bitfld.long 0xFDC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFDC 0.--7. 1. "SSS,Source Signal Select" line.long 0xFE0 "MSCR_MUX1016,SIUL2 multiplexed signal configuration register 1016 for multiplexed input selectio1016" bitfld.long 0xFE0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFE0 0.--7. 1. "SSS,Source Signal Select" line.long 0xFE4 "MSCR_MUX1017,SIUL2 multiplexed signal configuration register 1017 for multiplexed input selectio1017" bitfld.long 0xFE4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFE4 0.--7. 1. "SSS,Source Signal Select" line.long 0xFE8 "MSCR_MUX1018,SIUL2 multiplexed signal configuration register 1018 for multiplexed input selectio1018" bitfld.long 0xFE8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFE8 0.--7. 1. "SSS,Source Signal Select" line.long 0xFEC "MSCR_MUX1019,SIUL2 multiplexed signal configuration register 1019 for multiplexed input selectio1019" bitfld.long 0xFEC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFEC 0.--7. 1. "SSS,Source Signal Select" line.long 0xFF0 "MSCR_MUX1020,SIUL2 multiplexed signal configuration register 1020 for multiplexed input selectio1020" bitfld.long 0xFF0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFF0 0.--7. 1. "SSS,Source Signal Select" line.long 0xFF4 "MSCR_MUX1021,SIUL2 multiplexed signal configuration register 1021 for multiplexed input selectio1021" bitfld.long 0xFF4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFF4 0.--7. 1. "SSS,Source Signal Select" line.long 0xFF8 "MSCR_MUX1022,SIUL2 multiplexed signal configuration register 1022 for multiplexed input selectio1022" bitfld.long 0xFF8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFF8 0.--7. 1. "SSS,Source Signal Select" line.long 0xFFC "MSCR_MUX1023,SIUL2 multiplexed signal configuration register 1023 for multiplexed input selectio1023" bitfld.long 0xFFC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFFC 0.--7. 1. "SSS,Source Signal Select" group.byte 0x1300++0x3FF line.byte 0x0 "GPDO3,SIUL2 GPIO pad data out register n" bitfld.byte 0x0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1 "GPDO2,SIUL2 GPIO pad data out register n" bitfld.byte 0x1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x2 "GPDO1,SIUL2 GPIO pad data out register n" bitfld.byte 0x2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x3 "GPDO0,SIUL2 GPIO pad data out register n" bitfld.byte 0x3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x4 "GPDO7,SIUL2 GPIO pad data out register n" bitfld.byte 0x4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x5 "GPDO6,SIUL2 GPIO pad data out register n" bitfld.byte 0x5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x6 "GPDO5,SIUL2 GPIO pad data out register n" bitfld.byte 0x6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x7 "GPDO4,SIUL2 GPIO pad data out register n" bitfld.byte 0x7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x8 "GPDO11,SIUL2 GPIO pad data out register n" bitfld.byte 0x8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x9 "GPDO10,SIUL2 GPIO pad data out register n" bitfld.byte 0x9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA "GPDO9,SIUL2 GPIO pad data out register n" bitfld.byte 0xA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB "GPDO8,SIUL2 GPIO pad data out register n" bitfld.byte 0xB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC "GPDO15,SIUL2 GPIO pad data out register n" bitfld.byte 0xC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD "GPDO14,SIUL2 GPIO pad data out register n" bitfld.byte 0xD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE "GPDO13,SIUL2 GPIO pad data out register n" bitfld.byte 0xE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF "GPDO12,SIUL2 GPIO pad data out register n" bitfld.byte 0xF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x10 "GPDO19,SIUL2 GPIO pad data out register n" bitfld.byte 0x10 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x11 "GPDO18,SIUL2 GPIO pad data out register n" bitfld.byte 0x11 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x12 "GPDO17,SIUL2 GPIO pad data out register n" bitfld.byte 0x12 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x13 "GPDO16,SIUL2 GPIO pad data out register n" bitfld.byte 0x13 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x14 "GPDO23,SIUL2 GPIO pad data out register n" bitfld.byte 0x14 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x15 "GPDO22,SIUL2 GPIO pad data out register n" bitfld.byte 0x15 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x16 "GPDO21,SIUL2 GPIO pad data out register n" bitfld.byte 0x16 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x17 "GPDO20,SIUL2 GPIO pad data out register n" bitfld.byte 0x17 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x18 "GPDO27,SIUL2 GPIO pad data out register n" bitfld.byte 0x18 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x19 "GPDO26,SIUL2 GPIO pad data out register n" bitfld.byte 0x19 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A "GPDO25,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B "GPDO24,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C "GPDO31,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D "GPDO30,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E "GPDO29,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F "GPDO28,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x20 "GPDO35,SIUL2 GPIO pad data out register n" bitfld.byte 0x20 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x21 "GPDO34,SIUL2 GPIO pad data out register n" bitfld.byte 0x21 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x22 "GPDO33,SIUL2 GPIO pad data out register n" bitfld.byte 0x22 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x23 "GPDO32,SIUL2 GPIO pad data out register n" bitfld.byte 0x23 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x24 "GPDO39,SIUL2 GPIO pad data out register n" bitfld.byte 0x24 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x25 "GPDO38,SIUL2 GPIO pad data out register n" bitfld.byte 0x25 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x26 "GPDO37,SIUL2 GPIO pad data out register n" bitfld.byte 0x26 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x27 "GPDO36,SIUL2 GPIO pad data out register n" bitfld.byte 0x27 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x28 "GPDO43,SIUL2 GPIO pad data out register n" bitfld.byte 0x28 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x29 "GPDO42,SIUL2 GPIO pad data out register n" bitfld.byte 0x29 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x2A "GPDO41,SIUL2 GPIO pad data out register n" bitfld.byte 0x2A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x2B "GPDO40,SIUL2 GPIO pad data out register n" bitfld.byte 0x2B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x2C "GPDO47,SIUL2 GPIO pad data out register n" bitfld.byte 0x2C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x2D "GPDO46,SIUL2 GPIO pad data out register n" bitfld.byte 0x2D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x2E "GPDO45,SIUL2 GPIO pad data out register n" bitfld.byte 0x2E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x2F "GPDO44,SIUL2 GPIO pad data out register n" bitfld.byte 0x2F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x30 "GPDO51,SIUL2 GPIO pad data out register n" bitfld.byte 0x30 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x31 "GPDO50,SIUL2 GPIO pad data out register n" bitfld.byte 0x31 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x32 "GPDO49,SIUL2 GPIO pad data out register n" bitfld.byte 0x32 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x33 "GPDO48,SIUL2 GPIO pad data out register n" bitfld.byte 0x33 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x34 "GPDO55,SIUL2 GPIO pad data out register n" bitfld.byte 0x34 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x35 "GPDO54,SIUL2 GPIO pad data out register n" bitfld.byte 0x35 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x36 "GPDO53,SIUL2 GPIO pad data out register n" bitfld.byte 0x36 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x37 "GPDO52,SIUL2 GPIO pad data out register n" bitfld.byte 0x37 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x38 "GPDO59,SIUL2 GPIO pad data out register n" bitfld.byte 0x38 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x39 "GPDO58,SIUL2 GPIO pad data out register n" bitfld.byte 0x39 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x3A "GPDO57,SIUL2 GPIO pad data out register n" bitfld.byte 0x3A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x3B "GPDO56,SIUL2 GPIO pad data out register n" bitfld.byte 0x3B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x3C "GPDO63,SIUL2 GPIO pad data out register n" bitfld.byte 0x3C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x3D "GPDO62,SIUL2 GPIO pad data out register n" bitfld.byte 0x3D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x3E "GPDO61,SIUL2 GPIO pad data out register n" bitfld.byte 0x3E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x3F "GPDO60,SIUL2 GPIO pad data out register n" bitfld.byte 0x3F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x40 "GPDO67,SIUL2 GPIO pad data out register n" bitfld.byte 0x40 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x41 "GPDO66,SIUL2 GPIO pad data out register n" bitfld.byte 0x41 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x42 "GPDO65,SIUL2 GPIO pad data out register n" bitfld.byte 0x42 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x43 "GPDO64,SIUL2 GPIO pad data out register n" bitfld.byte 0x43 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x44 "GPDO71,SIUL2 GPIO pad data out register n" bitfld.byte 0x44 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x45 "GPDO70,SIUL2 GPIO pad data out register n" bitfld.byte 0x45 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x46 "GPDO69,SIUL2 GPIO pad data out register n" bitfld.byte 0x46 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x47 "GPDO68,SIUL2 GPIO pad data out register n" bitfld.byte 0x47 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x48 "GPDO75,SIUL2 GPIO pad data out register n" bitfld.byte 0x48 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x49 "GPDO74,SIUL2 GPIO pad data out register n" bitfld.byte 0x49 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x4A "GPDO73,SIUL2 GPIO pad data out register n" bitfld.byte 0x4A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x4B "GPDO72,SIUL2 GPIO pad data out register n" bitfld.byte 0x4B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x4C "GPDO79,SIUL2 GPIO pad data out register n" bitfld.byte 0x4C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x4D "GPDO78,SIUL2 GPIO pad data out register n" bitfld.byte 0x4D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x4E "GPDO77,SIUL2 GPIO pad data out register n" bitfld.byte 0x4E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x4F "GPDO76,SIUL2 GPIO pad data out register n" bitfld.byte 0x4F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x50 "GPDO83,SIUL2 GPIO pad data out register n" bitfld.byte 0x50 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x51 "GPDO82,SIUL2 GPIO pad data out register n" bitfld.byte 0x51 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x52 "GPDO81,SIUL2 GPIO pad data out register n" bitfld.byte 0x52 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x53 "GPDO80,SIUL2 GPIO pad data out register n" bitfld.byte 0x53 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x54 "GPDO87,SIUL2 GPIO pad data out register n" bitfld.byte 0x54 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x55 "GPDO86,SIUL2 GPIO pad data out register n" bitfld.byte 0x55 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x56 "GPDO85,SIUL2 GPIO pad data out register n" bitfld.byte 0x56 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x57 "GPDO84,SIUL2 GPIO pad data out register n" bitfld.byte 0x57 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x58 "GPDO91,SIUL2 GPIO pad data out register n" bitfld.byte 0x58 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x59 "GPDO90,SIUL2 GPIO pad data out register n" bitfld.byte 0x59 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x5A "GPDO89,SIUL2 GPIO pad data out register n" bitfld.byte 0x5A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x5B "GPDO88,SIUL2 GPIO pad data out register n" bitfld.byte 0x5B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x5C "GPDO95,SIUL2 GPIO pad data out register n" bitfld.byte 0x5C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x5D "GPDO94,SIUL2 GPIO pad data out register n" bitfld.byte 0x5D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x5E "GPDO93,SIUL2 GPIO pad data out register n" bitfld.byte 0x5E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x5F "GPDO92,SIUL2 GPIO pad data out register n" bitfld.byte 0x5F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x60 "GPDO99,SIUL2 GPIO pad data out register n" bitfld.byte 0x60 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x61 "GPDO98,SIUL2 GPIO pad data out register n" bitfld.byte 0x61 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x62 "GPDO97,SIUL2 GPIO pad data out register n" bitfld.byte 0x62 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x63 "GPDO96,SIUL2 GPIO pad data out register n" bitfld.byte 0x63 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x64 "GPDO103,SIUL2 GPIO pad data out register n" bitfld.byte 0x64 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x65 "GPDO102,SIUL2 GPIO pad data out register n" bitfld.byte 0x65 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x66 "GPDO101,SIUL2 GPIO pad data out register n" bitfld.byte 0x66 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x67 "GPDO100,SIUL2 GPIO pad data out register n" bitfld.byte 0x67 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x68 "GPDO107,SIUL2 GPIO pad data out register n" bitfld.byte 0x68 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x69 "GPDO106,SIUL2 GPIO pad data out register n" bitfld.byte 0x69 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x6A "GPDO105,SIUL2 GPIO pad data out register n" bitfld.byte 0x6A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x6B "GPDO104,SIUL2 GPIO pad data out register n" bitfld.byte 0x6B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x6C "GPDO111,SIUL2 GPIO pad data out register n" bitfld.byte 0x6C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x6D "GPDO110,SIUL2 GPIO pad data out register n" bitfld.byte 0x6D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x6E "GPDO109,SIUL2 GPIO pad data out register n" bitfld.byte 0x6E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x6F "GPDO108,SIUL2 GPIO pad data out register n" bitfld.byte 0x6F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x70 "GPDO115,SIUL2 GPIO pad data out register n" bitfld.byte 0x70 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x71 "GPDO114,SIUL2 GPIO pad data out register n" bitfld.byte 0x71 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x72 "GPDO113,SIUL2 GPIO pad data out register n" bitfld.byte 0x72 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x73 "GPDO112,SIUL2 GPIO pad data out register n" bitfld.byte 0x73 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x74 "GPDO119,SIUL2 GPIO pad data out register n" bitfld.byte 0x74 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x75 "GPDO118,SIUL2 GPIO pad data out register n" bitfld.byte 0x75 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x76 "GPDO117,SIUL2 GPIO pad data out register n" bitfld.byte 0x76 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x77 "GPDO116,SIUL2 GPIO pad data out register n" bitfld.byte 0x77 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x78 "GPDO123,SIUL2 GPIO pad data out register n" bitfld.byte 0x78 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x79 "GPDO122,SIUL2 GPIO pad data out register n" bitfld.byte 0x79 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x7A "GPDO121,SIUL2 GPIO pad data out register n" bitfld.byte 0x7A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x7B "GPDO120,SIUL2 GPIO pad data out register n" bitfld.byte 0x7B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x7C "GPDO127,SIUL2 GPIO pad data out register n" bitfld.byte 0x7C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x7D "GPDO126,SIUL2 GPIO pad data out register n" bitfld.byte 0x7D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x7E "GPDO125,SIUL2 GPIO pad data out register n" bitfld.byte 0x7E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x7F "GPDO124,SIUL2 GPIO pad data out register n" bitfld.byte 0x7F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x80 "GPDO131,SIUL2 GPIO pad data out register n" bitfld.byte 0x80 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x81 "GPDO130,SIUL2 GPIO pad data out register n" bitfld.byte 0x81 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x82 "GPDO129,SIUL2 GPIO pad data out register n" bitfld.byte 0x82 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x83 "GPDO128,SIUL2 GPIO pad data out register n" bitfld.byte 0x83 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x84 "GPDO135,SIUL2 GPIO pad data out register n" bitfld.byte 0x84 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x85 "GPDO134,SIUL2 GPIO pad data out register n" bitfld.byte 0x85 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x86 "GPDO133,SIUL2 GPIO pad data out register n" bitfld.byte 0x86 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x87 "GPDO132,SIUL2 GPIO pad data out register n" bitfld.byte 0x87 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x88 "GPDO139,SIUL2 GPIO pad data out register n" bitfld.byte 0x88 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x89 "GPDO138,SIUL2 GPIO pad data out register n" bitfld.byte 0x89 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x8A "GPDO137,SIUL2 GPIO pad data out register n" bitfld.byte 0x8A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x8B "GPDO136,SIUL2 GPIO pad data out register n" bitfld.byte 0x8B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x8C "GPDO143,SIUL2 GPIO pad data out register n" bitfld.byte 0x8C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x8D "GPDO142,SIUL2 GPIO pad data out register n" bitfld.byte 0x8D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x8E "GPDO141,SIUL2 GPIO pad data out register n" bitfld.byte 0x8E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x8F "GPDO140,SIUL2 GPIO pad data out register n" bitfld.byte 0x8F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x90 "GPDO147,SIUL2 GPIO pad data out register n" bitfld.byte 0x90 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x91 "GPDO146,SIUL2 GPIO pad data out register n" bitfld.byte 0x91 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x92 "GPDO145,SIUL2 GPIO pad data out register n" bitfld.byte 0x92 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x93 "GPDO144,SIUL2 GPIO pad data out register n" bitfld.byte 0x93 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x94 "GPDO151,SIUL2 GPIO pad data out register n" bitfld.byte 0x94 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x95 "GPDO150,SIUL2 GPIO pad data out register n" bitfld.byte 0x95 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x96 "GPDO149,SIUL2 GPIO pad data out register n" bitfld.byte 0x96 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x97 "GPDO148,SIUL2 GPIO pad data out register n" bitfld.byte 0x97 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x98 "GPDO155,SIUL2 GPIO pad data out register n" bitfld.byte 0x98 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x99 "GPDO154,SIUL2 GPIO pad data out register n" bitfld.byte 0x99 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x9A "GPDO153,SIUL2 GPIO pad data out register n" bitfld.byte 0x9A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x9B "GPDO152,SIUL2 GPIO pad data out register n" bitfld.byte 0x9B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x9C "GPDO159,SIUL2 GPIO pad data out register n" bitfld.byte 0x9C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x9D "GPDO158,SIUL2 GPIO pad data out register n" bitfld.byte 0x9D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x9E "GPDO157,SIUL2 GPIO pad data out register n" bitfld.byte 0x9E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x9F "GPDO156,SIUL2 GPIO pad data out register n" bitfld.byte 0x9F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA0 "GPDO163,SIUL2 GPIO pad data out register n" bitfld.byte 0xA0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA1 "GPDO162,SIUL2 GPIO pad data out register n" bitfld.byte 0xA1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA2 "GPDO161,SIUL2 GPIO pad data out register n" bitfld.byte 0xA2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA3 "GPDO160,SIUL2 GPIO pad data out register n" bitfld.byte 0xA3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA4 "GPDO167,SIUL2 GPIO pad data out register n" bitfld.byte 0xA4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA5 "GPDO166,SIUL2 GPIO pad data out register n" bitfld.byte 0xA5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA6 "GPDO165,SIUL2 GPIO pad data out register n" bitfld.byte 0xA6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA7 "GPDO164,SIUL2 GPIO pad data out register n" bitfld.byte 0xA7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA8 "GPDO171,SIUL2 GPIO pad data out register n" bitfld.byte 0xA8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA9 "GPDO170,SIUL2 GPIO pad data out register n" bitfld.byte 0xA9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xAA "GPDO169,SIUL2 GPIO pad data out register n" bitfld.byte 0xAA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xAB "GPDO168,SIUL2 GPIO pad data out register n" bitfld.byte 0xAB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xAC "GPDO175,SIUL2 GPIO pad data out register n" bitfld.byte 0xAC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xAD "GPDO174,SIUL2 GPIO pad data out register n" bitfld.byte 0xAD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xAE "GPDO173,SIUL2 GPIO pad data out register n" bitfld.byte 0xAE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xAF "GPDO172,SIUL2 GPIO pad data out register n" bitfld.byte 0xAF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB0 "GPDO179,SIUL2 GPIO pad data out register n" bitfld.byte 0xB0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB1 "GPDO178,SIUL2 GPIO pad data out register n" bitfld.byte 0xB1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB2 "GPDO177,SIUL2 GPIO pad data out register n" bitfld.byte 0xB2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB3 "GPDO176,SIUL2 GPIO pad data out register n" bitfld.byte 0xB3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB4 "GPDO183,SIUL2 GPIO pad data out register n" bitfld.byte 0xB4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB5 "GPDO182,SIUL2 GPIO pad data out register n" bitfld.byte 0xB5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB6 "GPDO181,SIUL2 GPIO pad data out register n" bitfld.byte 0xB6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB7 "GPDO180,SIUL2 GPIO pad data out register n" bitfld.byte 0xB7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB8 "GPDO187,SIUL2 GPIO pad data out register n" bitfld.byte 0xB8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB9 "GPDO186,SIUL2 GPIO pad data out register n" bitfld.byte 0xB9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xBA "GPDO185,SIUL2 GPIO pad data out register n" bitfld.byte 0xBA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xBB "GPDO184,SIUL2 GPIO pad data out register n" bitfld.byte 0xBB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xBC "GPDO191,SIUL2 GPIO pad data out register n" bitfld.byte 0xBC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xBD "GPDO190,SIUL2 GPIO pad data out register n" bitfld.byte 0xBD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xBE "GPDO189,SIUL2 GPIO pad data out register n" bitfld.byte 0xBE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xBF "GPDO188,SIUL2 GPIO pad data out register n" bitfld.byte 0xBF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC0 "GPDO195,SIUL2 GPIO pad data out register n" bitfld.byte 0xC0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC1 "GPDO194,SIUL2 GPIO pad data out register n" bitfld.byte 0xC1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC2 "GPDO193,SIUL2 GPIO pad data out register n" bitfld.byte 0xC2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC3 "GPDO192,SIUL2 GPIO pad data out register n" bitfld.byte 0xC3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC4 "GPDO199,SIUL2 GPIO pad data out register n" bitfld.byte 0xC4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC5 "GPDO198,SIUL2 GPIO pad data out register n" bitfld.byte 0xC5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC6 "GPDO197,SIUL2 GPIO pad data out register n" bitfld.byte 0xC6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC7 "GPDO196,SIUL2 GPIO pad data out register n" bitfld.byte 0xC7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC8 "GPDO203,SIUL2 GPIO pad data out register n" bitfld.byte 0xC8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC9 "GPDO202,SIUL2 GPIO pad data out register n" bitfld.byte 0xC9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xCA "GPDO201,SIUL2 GPIO pad data out register n" bitfld.byte 0xCA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xCB "GPDO200,SIUL2 GPIO pad data out register n" bitfld.byte 0xCB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xCC "GPDO207,SIUL2 GPIO pad data out register n" bitfld.byte 0xCC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xCD "GPDO206,SIUL2 GPIO pad data out register n" bitfld.byte 0xCD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xCE "GPDO205,SIUL2 GPIO pad data out register n" bitfld.byte 0xCE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xCF "GPDO204,SIUL2 GPIO pad data out register n" bitfld.byte 0xCF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD0 "GPDO211,SIUL2 GPIO pad data out register n" bitfld.byte 0xD0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD1 "GPDO210,SIUL2 GPIO pad data out register n" bitfld.byte 0xD1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD2 "GPDO209,SIUL2 GPIO pad data out register n" bitfld.byte 0xD2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD3 "GPDO208,SIUL2 GPIO pad data out register n" bitfld.byte 0xD3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD4 "GPDO215,SIUL2 GPIO pad data out register n" bitfld.byte 0xD4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD5 "GPDO214,SIUL2 GPIO pad data out register n" bitfld.byte 0xD5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD6 "GPDO213,SIUL2 GPIO pad data out register n" bitfld.byte 0xD6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD7 "GPDO212,SIUL2 GPIO pad data out register n" bitfld.byte 0xD7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD8 "GPDO219,SIUL2 GPIO pad data out register n" bitfld.byte 0xD8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD9 "GPDO218,SIUL2 GPIO pad data out register n" bitfld.byte 0xD9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xDA "GPDO217,SIUL2 GPIO pad data out register n" bitfld.byte 0xDA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xDB "GPDO216,SIUL2 GPIO pad data out register n" bitfld.byte 0xDB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xDC "GPDO223,SIUL2 GPIO pad data out register n" bitfld.byte 0xDC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xDD "GPDO222,SIUL2 GPIO pad data out register n" bitfld.byte 0xDD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xDE "GPDO221,SIUL2 GPIO pad data out register n" bitfld.byte 0xDE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xDF "GPDO220,SIUL2 GPIO pad data out register n" bitfld.byte 0xDF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE0 "GPDO227,SIUL2 GPIO pad data out register n" bitfld.byte 0xE0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE1 "GPDO226,SIUL2 GPIO pad data out register n" bitfld.byte 0xE1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE2 "GPDO225,SIUL2 GPIO pad data out register n" bitfld.byte 0xE2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE3 "GPDO224,SIUL2 GPIO pad data out register n" bitfld.byte 0xE3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE4 "GPDO231,SIUL2 GPIO pad data out register n" bitfld.byte 0xE4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE5 "GPDO230,SIUL2 GPIO pad data out register n" bitfld.byte 0xE5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE6 "GPDO229,SIUL2 GPIO pad data out register n" bitfld.byte 0xE6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE7 "GPDO228,SIUL2 GPIO pad data out register n" bitfld.byte 0xE7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE8 "GPDO235,SIUL2 GPIO pad data out register n" bitfld.byte 0xE8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE9 "GPDO234,SIUL2 GPIO pad data out register n" bitfld.byte 0xE9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xEA "GPDO233,SIUL2 GPIO pad data out register n" bitfld.byte 0xEA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xEB "GPDO232,SIUL2 GPIO pad data out register n" bitfld.byte 0xEB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xEC "GPDO239,SIUL2 GPIO pad data out register n" bitfld.byte 0xEC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xED "GPDO238,SIUL2 GPIO pad data out register n" bitfld.byte 0xED 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xEE "GPDO237,SIUL2 GPIO pad data out register n" bitfld.byte 0xEE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xEF "GPDO236,SIUL2 GPIO pad data out register n" bitfld.byte 0xEF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF0 "GPDO243,SIUL2 GPIO pad data out register n" bitfld.byte 0xF0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF1 "GPDO242,SIUL2 GPIO pad data out register n" bitfld.byte 0xF1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF2 "GPDO241,SIUL2 GPIO pad data out register n" bitfld.byte 0xF2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF3 "GPDO240,SIUL2 GPIO pad data out register n" bitfld.byte 0xF3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF4 "GPDO247,SIUL2 GPIO pad data out register n" bitfld.byte 0xF4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF5 "GPDO246,SIUL2 GPIO pad data out register n" bitfld.byte 0xF5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF6 "GPDO245,SIUL2 GPIO pad data out register n" bitfld.byte 0xF6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF7 "GPDO244,SIUL2 GPIO pad data out register n" bitfld.byte 0xF7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF8 "GPDO251,SIUL2 GPIO pad data out register n" bitfld.byte 0xF8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF9 "GPDO250,SIUL2 GPIO pad data out register n" bitfld.byte 0xF9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xFA "GPDO249,SIUL2 GPIO pad data out register n" bitfld.byte 0xFA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xFB "GPDO248,SIUL2 GPIO pad data out register n" bitfld.byte 0xFB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xFC "GPDO255,SIUL2 GPIO pad data out register n" bitfld.byte 0xFC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xFD "GPDO254,SIUL2 GPIO pad data out register n" bitfld.byte 0xFD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xFE "GPDO253,SIUL2 GPIO pad data out register n" bitfld.byte 0xFE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xFF "GPDO252,SIUL2 GPIO pad data out register n" bitfld.byte 0xFF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x100 "GPDO259,SIUL2 GPIO pad data out register n" bitfld.byte 0x100 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x101 "GPDO258,SIUL2 GPIO pad data out register n" bitfld.byte 0x101 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x102 "GPDO257,SIUL2 GPIO pad data out register n" bitfld.byte 0x102 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x103 "GPDO256,SIUL2 GPIO pad data out register n" bitfld.byte 0x103 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x104 "GPDO263,SIUL2 GPIO pad data out register n" bitfld.byte 0x104 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x105 "GPDO262,SIUL2 GPIO pad data out register n" bitfld.byte 0x105 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x106 "GPDO261,SIUL2 GPIO pad data out register n" bitfld.byte 0x106 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x107 "GPDO260,SIUL2 GPIO pad data out register n" bitfld.byte 0x107 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x108 "GPDO267,SIUL2 GPIO pad data out register n" bitfld.byte 0x108 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x109 "GPDO266,SIUL2 GPIO pad data out register n" bitfld.byte 0x109 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x10A "GPDO265,SIUL2 GPIO pad data out register n" bitfld.byte 0x10A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x10B "GPDO264,SIUL2 GPIO pad data out register n" bitfld.byte 0x10B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x10C "GPDO271,SIUL2 GPIO pad data out register n" bitfld.byte 0x10C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x10D "GPDO270,SIUL2 GPIO pad data out register n" bitfld.byte 0x10D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x10E "GPDO269,SIUL2 GPIO pad data out register n" bitfld.byte 0x10E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x10F "GPDO268,SIUL2 GPIO pad data out register n" bitfld.byte 0x10F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x110 "GPDO275,SIUL2 GPIO pad data out register n" bitfld.byte 0x110 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x111 "GPDO274,SIUL2 GPIO pad data out register n" bitfld.byte 0x111 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x112 "GPDO273,SIUL2 GPIO pad data out register n" bitfld.byte 0x112 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x113 "GPDO272,SIUL2 GPIO pad data out register n" bitfld.byte 0x113 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x114 "GPDO279,SIUL2 GPIO pad data out register n" bitfld.byte 0x114 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x115 "GPDO278,SIUL2 GPIO pad data out register n" bitfld.byte 0x115 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x116 "GPDO277,SIUL2 GPIO pad data out register n" bitfld.byte 0x116 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x117 "GPDO276,SIUL2 GPIO pad data out register n" bitfld.byte 0x117 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x118 "GPDO283,SIUL2 GPIO pad data out register n" bitfld.byte 0x118 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x119 "GPDO282,SIUL2 GPIO pad data out register n" bitfld.byte 0x119 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x11A "GPDO281,SIUL2 GPIO pad data out register n" bitfld.byte 0x11A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x11B "GPDO280,SIUL2 GPIO pad data out register n" bitfld.byte 0x11B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x11C "GPDO287,SIUL2 GPIO pad data out register n" bitfld.byte 0x11C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x11D "GPDO286,SIUL2 GPIO pad data out register n" bitfld.byte 0x11D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x11E "GPDO285,SIUL2 GPIO pad data out register n" bitfld.byte 0x11E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x11F "GPDO284,SIUL2 GPIO pad data out register n" bitfld.byte 0x11F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x120 "GPDO291,SIUL2 GPIO pad data out register n" bitfld.byte 0x120 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x121 "GPDO290,SIUL2 GPIO pad data out register n" bitfld.byte 0x121 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x122 "GPDO289,SIUL2 GPIO pad data out register n" bitfld.byte 0x122 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x123 "GPDO288,SIUL2 GPIO pad data out register n" bitfld.byte 0x123 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x124 "GPDO295,SIUL2 GPIO pad data out register n" bitfld.byte 0x124 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x125 "GPDO294,SIUL2 GPIO pad data out register n" bitfld.byte 0x125 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x126 "GPDO293,SIUL2 GPIO pad data out register n" bitfld.byte 0x126 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x127 "GPDO292,SIUL2 GPIO pad data out register n" bitfld.byte 0x127 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x128 "GPDO299,SIUL2 GPIO pad data out register n" bitfld.byte 0x128 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x129 "GPDO298,SIUL2 GPIO pad data out register n" bitfld.byte 0x129 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x12A "GPDO297,SIUL2 GPIO pad data out register n" bitfld.byte 0x12A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x12B "GPDO296,SIUL2 GPIO pad data out register n" bitfld.byte 0x12B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x12C "GPDO303,SIUL2 GPIO pad data out register n" bitfld.byte 0x12C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x12D "GPDO302,SIUL2 GPIO pad data out register n" bitfld.byte 0x12D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x12E "GPDO301,SIUL2 GPIO pad data out register n" bitfld.byte 0x12E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x12F "GPDO300,SIUL2 GPIO pad data out register n" bitfld.byte 0x12F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x130 "GPDO307,SIUL2 GPIO pad data out register n" bitfld.byte 0x130 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x131 "GPDO306,SIUL2 GPIO pad data out register n" bitfld.byte 0x131 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x132 "GPDO305,SIUL2 GPIO pad data out register n" bitfld.byte 0x132 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x133 "GPDO304,SIUL2 GPIO pad data out register n" bitfld.byte 0x133 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x134 "GPDO311,SIUL2 GPIO pad data out register n" bitfld.byte 0x134 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x135 "GPDO310,SIUL2 GPIO pad data out register n" bitfld.byte 0x135 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x136 "GPDO309,SIUL2 GPIO pad data out register n" bitfld.byte 0x136 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x137 "GPDO308,SIUL2 GPIO pad data out register n" bitfld.byte 0x137 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x138 "GPDO315,SIUL2 GPIO pad data out register n" bitfld.byte 0x138 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x139 "GPDO314,SIUL2 GPIO pad data out register n" bitfld.byte 0x139 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x13A "GPDO313,SIUL2 GPIO pad data out register n" bitfld.byte 0x13A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x13B "GPDO312,SIUL2 GPIO pad data out register n" bitfld.byte 0x13B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x13C "GPDO319,SIUL2 GPIO pad data out register n" bitfld.byte 0x13C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x13D "GPDO318,SIUL2 GPIO pad data out register n" bitfld.byte 0x13D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x13E "GPDO317,SIUL2 GPIO pad data out register n" bitfld.byte 0x13E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x13F "GPDO316,SIUL2 GPIO pad data out register n" bitfld.byte 0x13F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x140 "GPDO323,SIUL2 GPIO pad data out register n" bitfld.byte 0x140 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x141 "GPDO322,SIUL2 GPIO pad data out register n" bitfld.byte 0x141 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x142 "GPDO321,SIUL2 GPIO pad data out register n" bitfld.byte 0x142 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x143 "GPDO320,SIUL2 GPIO pad data out register n" bitfld.byte 0x143 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x144 "GPDO327,SIUL2 GPIO pad data out register n" bitfld.byte 0x144 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x145 "GPDO326,SIUL2 GPIO pad data out register n" bitfld.byte 0x145 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x146 "GPDO325,SIUL2 GPIO pad data out register n" bitfld.byte 0x146 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x147 "GPDO324,SIUL2 GPIO pad data out register n" bitfld.byte 0x147 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x148 "GPDO331,SIUL2 GPIO pad data out register n" bitfld.byte 0x148 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x149 "GPDO330,SIUL2 GPIO pad data out register n" bitfld.byte 0x149 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x14A "GPDO329,SIUL2 GPIO pad data out register n" bitfld.byte 0x14A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x14B "GPDO328,SIUL2 GPIO pad data out register n" bitfld.byte 0x14B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x14C "GPDO335,SIUL2 GPIO pad data out register n" bitfld.byte 0x14C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x14D "GPDO334,SIUL2 GPIO pad data out register n" bitfld.byte 0x14D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x14E "GPDO333,SIUL2 GPIO pad data out register n" bitfld.byte 0x14E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x14F "GPDO332,SIUL2 GPIO pad data out register n" bitfld.byte 0x14F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x150 "GPDO339,SIUL2 GPIO pad data out register n" bitfld.byte 0x150 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x151 "GPDO338,SIUL2 GPIO pad data out register n" bitfld.byte 0x151 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x152 "GPDO337,SIUL2 GPIO pad data out register n" bitfld.byte 0x152 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x153 "GPDO336,SIUL2 GPIO pad data out register n" bitfld.byte 0x153 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x154 "GPDO343,SIUL2 GPIO pad data out register n" bitfld.byte 0x154 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x155 "GPDO342,SIUL2 GPIO pad data out register n" bitfld.byte 0x155 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x156 "GPDO341,SIUL2 GPIO pad data out register n" bitfld.byte 0x156 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x157 "GPDO340,SIUL2 GPIO pad data out register n" bitfld.byte 0x157 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x158 "GPDO347,SIUL2 GPIO pad data out register n" bitfld.byte 0x158 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x159 "GPDO346,SIUL2 GPIO pad data out register n" bitfld.byte 0x159 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x15A "GPDO345,SIUL2 GPIO pad data out register n" bitfld.byte 0x15A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x15B "GPDO344,SIUL2 GPIO pad data out register n" bitfld.byte 0x15B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x15C "GPDO351,SIUL2 GPIO pad data out register n" bitfld.byte 0x15C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x15D "GPDO350,SIUL2 GPIO pad data out register n" bitfld.byte 0x15D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x15E "GPDO349,SIUL2 GPIO pad data out register n" bitfld.byte 0x15E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x15F "GPDO348,SIUL2 GPIO pad data out register n" bitfld.byte 0x15F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x160 "GPDO355,SIUL2 GPIO pad data out register n" bitfld.byte 0x160 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x161 "GPDO354,SIUL2 GPIO pad data out register n" bitfld.byte 0x161 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x162 "GPDO353,SIUL2 GPIO pad data out register n" bitfld.byte 0x162 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x163 "GPDO352,SIUL2 GPIO pad data out register n" bitfld.byte 0x163 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x164 "GPDO359,SIUL2 GPIO pad data out register n" bitfld.byte 0x164 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x165 "GPDO358,SIUL2 GPIO pad data out register n" bitfld.byte 0x165 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x166 "GPDO357,SIUL2 GPIO pad data out register n" bitfld.byte 0x166 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x167 "GPDO356,SIUL2 GPIO pad data out register n" bitfld.byte 0x167 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x168 "GPDO363,SIUL2 GPIO pad data out register n" bitfld.byte 0x168 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x169 "GPDO362,SIUL2 GPIO pad data out register n" bitfld.byte 0x169 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x16A "GPDO361,SIUL2 GPIO pad data out register n" bitfld.byte 0x16A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x16B "GPDO360,SIUL2 GPIO pad data out register n" bitfld.byte 0x16B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x16C "GPDO367,SIUL2 GPIO pad data out register n" bitfld.byte 0x16C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x16D "GPDO366,SIUL2 GPIO pad data out register n" bitfld.byte 0x16D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x16E "GPDO365,SIUL2 GPIO pad data out register n" bitfld.byte 0x16E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x16F "GPDO364,SIUL2 GPIO pad data out register n" bitfld.byte 0x16F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x170 "GPDO371,SIUL2 GPIO pad data out register n" bitfld.byte 0x170 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x171 "GPDO370,SIUL2 GPIO pad data out register n" bitfld.byte 0x171 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x172 "GPDO369,SIUL2 GPIO pad data out register n" bitfld.byte 0x172 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x173 "GPDO368,SIUL2 GPIO pad data out register n" bitfld.byte 0x173 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x174 "GPDO375,SIUL2 GPIO pad data out register n" bitfld.byte 0x174 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x175 "GPDO374,SIUL2 GPIO pad data out register n" bitfld.byte 0x175 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x176 "GPDO373,SIUL2 GPIO pad data out register n" bitfld.byte 0x176 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x177 "GPDO372,SIUL2 GPIO pad data out register n" bitfld.byte 0x177 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x178 "GPDO379,SIUL2 GPIO pad data out register n" bitfld.byte 0x178 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x179 "GPDO378,SIUL2 GPIO pad data out register n" bitfld.byte 0x179 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x17A "GPDO377,SIUL2 GPIO pad data out register n" bitfld.byte 0x17A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x17B "GPDO376,SIUL2 GPIO pad data out register n" bitfld.byte 0x17B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x17C "GPDO383,SIUL2 GPIO pad data out register n" bitfld.byte 0x17C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x17D "GPDO382,SIUL2 GPIO pad data out register n" bitfld.byte 0x17D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x17E "GPDO381,SIUL2 GPIO pad data out register n" bitfld.byte 0x17E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x17F "GPDO380,SIUL2 GPIO pad data out register n" bitfld.byte 0x17F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x180 "GPDO387,SIUL2 GPIO pad data out register n" bitfld.byte 0x180 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x181 "GPDO386,SIUL2 GPIO pad data out register n" bitfld.byte 0x181 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x182 "GPDO385,SIUL2 GPIO pad data out register n" bitfld.byte 0x182 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x183 "GPDO384,SIUL2 GPIO pad data out register n" bitfld.byte 0x183 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x184 "GPDO391,SIUL2 GPIO pad data out register n" bitfld.byte 0x184 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x185 "GPDO390,SIUL2 GPIO pad data out register n" bitfld.byte 0x185 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x186 "GPDO389,SIUL2 GPIO pad data out register n" bitfld.byte 0x186 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x187 "GPDO388,SIUL2 GPIO pad data out register n" bitfld.byte 0x187 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x188 "GPDO395,SIUL2 GPIO pad data out register n" bitfld.byte 0x188 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x189 "GPDO394,SIUL2 GPIO pad data out register n" bitfld.byte 0x189 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x18A "GPDO393,SIUL2 GPIO pad data out register n" bitfld.byte 0x18A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x18B "GPDO392,SIUL2 GPIO pad data out register n" bitfld.byte 0x18B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x18C "GPDO399,SIUL2 GPIO pad data out register n" bitfld.byte 0x18C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x18D "GPDO398,SIUL2 GPIO pad data out register n" bitfld.byte 0x18D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x18E "GPDO397,SIUL2 GPIO pad data out register n" bitfld.byte 0x18E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x18F "GPDO396,SIUL2 GPIO pad data out register n" bitfld.byte 0x18F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x190 "GPDO403,SIUL2 GPIO pad data out register n" bitfld.byte 0x190 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x191 "GPDO402,SIUL2 GPIO pad data out register n" bitfld.byte 0x191 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x192 "GPDO401,SIUL2 GPIO pad data out register n" bitfld.byte 0x192 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x193 "GPDO400,SIUL2 GPIO pad data out register n" bitfld.byte 0x193 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x194 "GPDO407,SIUL2 GPIO pad data out register n" bitfld.byte 0x194 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x195 "GPDO406,SIUL2 GPIO pad data out register n" bitfld.byte 0x195 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x196 "GPDO405,SIUL2 GPIO pad data out register n" bitfld.byte 0x196 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x197 "GPDO404,SIUL2 GPIO pad data out register n" bitfld.byte 0x197 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x198 "GPDO411,SIUL2 GPIO pad data out register n" bitfld.byte 0x198 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x199 "GPDO410,SIUL2 GPIO pad data out register n" bitfld.byte 0x199 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x19A "GPDO409,SIUL2 GPIO pad data out register n" bitfld.byte 0x19A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x19B "GPDO408,SIUL2 GPIO pad data out register n" bitfld.byte 0x19B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x19C "GPDO415,SIUL2 GPIO pad data out register n" bitfld.byte 0x19C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x19D "GPDO414,SIUL2 GPIO pad data out register n" bitfld.byte 0x19D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x19E "GPDO413,SIUL2 GPIO pad data out register n" bitfld.byte 0x19E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x19F "GPDO412,SIUL2 GPIO pad data out register n" bitfld.byte 0x19F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A0 "GPDO419,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A1 "GPDO418,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A2 "GPDO417,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A3 "GPDO416,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A4 "GPDO423,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A5 "GPDO422,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A6 "GPDO421,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A7 "GPDO420,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A8 "GPDO427,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A9 "GPDO426,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1AA "GPDO425,SIUL2 GPIO pad data out register n" bitfld.byte 0x1AA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1AB "GPDO424,SIUL2 GPIO pad data out register n" bitfld.byte 0x1AB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1AC "GPDO431,SIUL2 GPIO pad data out register n" bitfld.byte 0x1AC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1AD "GPDO430,SIUL2 GPIO pad data out register n" bitfld.byte 0x1AD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1AE "GPDO429,SIUL2 GPIO pad data out register n" bitfld.byte 0x1AE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1AF "GPDO428,SIUL2 GPIO pad data out register n" bitfld.byte 0x1AF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B0 "GPDO435,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B1 "GPDO434,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B2 "GPDO433,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B3 "GPDO432,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B4 "GPDO439,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B5 "GPDO438,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B6 "GPDO437,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B7 "GPDO436,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B8 "GPDO443,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B9 "GPDO442,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1BA "GPDO441,SIUL2 GPIO pad data out register n" bitfld.byte 0x1BA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1BB "GPDO440,SIUL2 GPIO pad data out register n" bitfld.byte 0x1BB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1BC "GPDO447,SIUL2 GPIO pad data out register n" bitfld.byte 0x1BC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1BD "GPDO446,SIUL2 GPIO pad data out register n" bitfld.byte 0x1BD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1BE "GPDO445,SIUL2 GPIO pad data out register n" bitfld.byte 0x1BE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1BF "GPDO444,SIUL2 GPIO pad data out register n" bitfld.byte 0x1BF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C0 "GPDO451,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C1 "GPDO450,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C2 "GPDO449,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C3 "GPDO448,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C4 "GPDO455,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C5 "GPDO454,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C6 "GPDO453,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C7 "GPDO452,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C8 "GPDO459,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C9 "GPDO458,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1CA "GPDO457,SIUL2 GPIO pad data out register n" bitfld.byte 0x1CA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1CB "GPDO456,SIUL2 GPIO pad data out register n" bitfld.byte 0x1CB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1CC "GPDO463,SIUL2 GPIO pad data out register n" bitfld.byte 0x1CC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1CD "GPDO462,SIUL2 GPIO pad data out register n" bitfld.byte 0x1CD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1CE "GPDO461,SIUL2 GPIO pad data out register n" bitfld.byte 0x1CE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1CF "GPDO460,SIUL2 GPIO pad data out register n" bitfld.byte 0x1CF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D0 "GPDO467,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D1 "GPDO466,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D2 "GPDO465,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D3 "GPDO464,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D4 "GPDO471,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D5 "GPDO470,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D6 "GPDO469,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D7 "GPDO468,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D8 "GPDO475,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D9 "GPDO474,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1DA "GPDO473,SIUL2 GPIO pad data out register n" bitfld.byte 0x1DA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1DB "GPDO472,SIUL2 GPIO pad data out register n" bitfld.byte 0x1DB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1DC "GPDO479,SIUL2 GPIO pad data out register n" bitfld.byte 0x1DC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1DD "GPDO478,SIUL2 GPIO pad data out register n" bitfld.byte 0x1DD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1DE "GPDO477,SIUL2 GPIO pad data out register n" bitfld.byte 0x1DE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1DF "GPDO476,SIUL2 GPIO pad data out register n" bitfld.byte 0x1DF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E0 "GPDO483,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E1 "GPDO482,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E2 "GPDO481,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E3 "GPDO480,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E4 "GPDO487,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E5 "GPDO486,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E6 "GPDO485,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E7 "GPDO484,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E8 "GPDO491,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E9 "GPDO490,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1EA "GPDO489,SIUL2 GPIO pad data out register n" bitfld.byte 0x1EA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1EB "GPDO488,SIUL2 GPIO pad data out register n" bitfld.byte 0x1EB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1EC "GPDO495,SIUL2 GPIO pad data out register n" bitfld.byte 0x1EC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1ED "GPDO494,SIUL2 GPIO pad data out register n" bitfld.byte 0x1ED 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1EE "GPDO493,SIUL2 GPIO pad data out register n" bitfld.byte 0x1EE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1EF "GPDO492,SIUL2 GPIO pad data out register n" bitfld.byte 0x1EF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F0 "GPDO499,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F1 "GPDO498,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F2 "GPDO497,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F3 "GPDO496,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F4 "GPDO503,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F5 "GPDO502,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F6 "GPDO501,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F7 "GPDO500,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F8 "GPDO507,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F9 "GPDO506,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1FA "GPDO505,SIUL2 GPIO pad data out register n" bitfld.byte 0x1FA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1FB "GPDO504,SIUL2 GPIO pad data out register n" bitfld.byte 0x1FB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1FC "GPDO511,SIUL2 GPIO pad data out register n" bitfld.byte 0x1FC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1FD "GPDO510,SIUL2 GPIO pad data out register n" bitfld.byte 0x1FD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1FE "GPDO509,SIUL2 GPIO pad data out register n" bitfld.byte 0x1FE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1FF "GPDO508,SIUL2 GPIO pad data out register n" bitfld.byte 0x1FF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x200 "GPDI3,SIUL2 GPIO pad data in register n" bitfld.byte 0x200 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x201 "GPDI2,SIUL2 GPIO pad data in register n" bitfld.byte 0x201 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x202 "GPDI1,SIUL2 GPIO pad data in register n" bitfld.byte 0x202 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x203 "GPDI0,SIUL2 GPIO pad data in register n" bitfld.byte 0x203 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x204 "GPDI7,SIUL2 GPIO pad data in register n" bitfld.byte 0x204 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x205 "GPDI6,SIUL2 GPIO pad data in register n" bitfld.byte 0x205 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x206 "GPDI5,SIUL2 GPIO pad data in register n" bitfld.byte 0x206 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x207 "GPDI4,SIUL2 GPIO pad data in register n" bitfld.byte 0x207 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x208 "GPDI11,SIUL2 GPIO pad data in register n" bitfld.byte 0x208 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x209 "GPDI10,SIUL2 GPIO pad data in register n" bitfld.byte 0x209 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x20A "GPDI9,SIUL2 GPIO pad data in register n" bitfld.byte 0x20A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x20B "GPDI8,SIUL2 GPIO pad data in register n" bitfld.byte 0x20B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x20C "GPDI15,SIUL2 GPIO pad data in register n" bitfld.byte 0x20C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x20D "GPDI14,SIUL2 GPIO pad data in register n" bitfld.byte 0x20D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x20E "GPDI13,SIUL2 GPIO pad data in register n" bitfld.byte 0x20E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x20F "GPDI12,SIUL2 GPIO pad data in register n" bitfld.byte 0x20F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x210 "GPDI19,SIUL2 GPIO pad data in register n" bitfld.byte 0x210 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x211 "GPDI18,SIUL2 GPIO pad data in register n" bitfld.byte 0x211 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x212 "GPDI17,SIUL2 GPIO pad data in register n" bitfld.byte 0x212 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x213 "GPDI16,SIUL2 GPIO pad data in register n" bitfld.byte 0x213 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x214 "GPDI23,SIUL2 GPIO pad data in register n" bitfld.byte 0x214 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x215 "GPDI22,SIUL2 GPIO pad data in register n" bitfld.byte 0x215 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x216 "GPDI21,SIUL2 GPIO pad data in register n" bitfld.byte 0x216 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x217 "GPDI20,SIUL2 GPIO pad data in register n" bitfld.byte 0x217 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x218 "GPDI27,SIUL2 GPIO pad data in register n" bitfld.byte 0x218 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x219 "GPDI26,SIUL2 GPIO pad data in register n" bitfld.byte 0x219 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x21A "GPDI25,SIUL2 GPIO pad data in register n" bitfld.byte 0x21A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x21B "GPDI24,SIUL2 GPIO pad data in register n" bitfld.byte 0x21B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x21C "GPDI31,SIUL2 GPIO pad data in register n" bitfld.byte 0x21C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x21D "GPDI30,SIUL2 GPIO pad data in register n" bitfld.byte 0x21D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x21E "GPDI29,SIUL2 GPIO pad data in register n" bitfld.byte 0x21E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x21F "GPDI28,SIUL2 GPIO pad data in register n" bitfld.byte 0x21F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x220 "GPDI35,SIUL2 GPIO pad data in register n" bitfld.byte 0x220 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x221 "GPDI34,SIUL2 GPIO pad data in register n" bitfld.byte 0x221 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x222 "GPDI33,SIUL2 GPIO pad data in register n" bitfld.byte 0x222 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x223 "GPDI32,SIUL2 GPIO pad data in register n" bitfld.byte 0x223 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x224 "GPDI39,SIUL2 GPIO pad data in register n" bitfld.byte 0x224 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x225 "GPDI38,SIUL2 GPIO pad data in register n" bitfld.byte 0x225 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x226 "GPDI37,SIUL2 GPIO pad data in register n" bitfld.byte 0x226 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x227 "GPDI36,SIUL2 GPIO pad data in register n" bitfld.byte 0x227 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x228 "GPDI43,SIUL2 GPIO pad data in register n" bitfld.byte 0x228 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x229 "GPDI42,SIUL2 GPIO pad data in register n" bitfld.byte 0x229 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x22A "GPDI41,SIUL2 GPIO pad data in register n" bitfld.byte 0x22A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x22B "GPDI40,SIUL2 GPIO pad data in register n" bitfld.byte 0x22B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x22C "GPDI47,SIUL2 GPIO pad data in register n" bitfld.byte 0x22C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x22D "GPDI46,SIUL2 GPIO pad data in register n" bitfld.byte 0x22D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x22E "GPDI45,SIUL2 GPIO pad data in register n" bitfld.byte 0x22E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x22F "GPDI44,SIUL2 GPIO pad data in register n" bitfld.byte 0x22F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x230 "GPDI51,SIUL2 GPIO pad data in register n" bitfld.byte 0x230 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x231 "GPDI50,SIUL2 GPIO pad data in register n" bitfld.byte 0x231 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x232 "GPDI49,SIUL2 GPIO pad data in register n" bitfld.byte 0x232 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x233 "GPDI48,SIUL2 GPIO pad data in register n" bitfld.byte 0x233 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x234 "GPDI55,SIUL2 GPIO pad data in register n" bitfld.byte 0x234 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x235 "GPDI54,SIUL2 GPIO pad data in register n" bitfld.byte 0x235 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x236 "GPDI53,SIUL2 GPIO pad data in register n" bitfld.byte 0x236 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x237 "GPDI52,SIUL2 GPIO pad data in register n" bitfld.byte 0x237 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x238 "GPDI59,SIUL2 GPIO pad data in register n" bitfld.byte 0x238 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x239 "GPDI58,SIUL2 GPIO pad data in register n" bitfld.byte 0x239 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x23A "GPDI57,SIUL2 GPIO pad data in register n" bitfld.byte 0x23A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x23B "GPDI56,SIUL2 GPIO pad data in register n" bitfld.byte 0x23B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x23C "GPDI63,SIUL2 GPIO pad data in register n" bitfld.byte 0x23C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x23D "GPDI62,SIUL2 GPIO pad data in register n" bitfld.byte 0x23D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x23E "GPDI61,SIUL2 GPIO pad data in register n" bitfld.byte 0x23E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x23F "GPDI60,SIUL2 GPIO pad data in register n" bitfld.byte 0x23F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x240 "GPDI67,SIUL2 GPIO pad data in register n" bitfld.byte 0x240 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x241 "GPDI66,SIUL2 GPIO pad data in register n" bitfld.byte 0x241 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x242 "GPDI65,SIUL2 GPIO pad data in register n" bitfld.byte 0x242 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x243 "GPDI64,SIUL2 GPIO pad data in register n" bitfld.byte 0x243 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x244 "GPDI71,SIUL2 GPIO pad data in register n" bitfld.byte 0x244 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x245 "GPDI70,SIUL2 GPIO pad data in register n" bitfld.byte 0x245 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x246 "GPDI69,SIUL2 GPIO pad data in register n" bitfld.byte 0x246 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x247 "GPDI68,SIUL2 GPIO pad data in register n" bitfld.byte 0x247 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x248 "GPDI75,SIUL2 GPIO pad data in register n" bitfld.byte 0x248 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x249 "GPDI74,SIUL2 GPIO pad data in register n" bitfld.byte 0x249 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x24A "GPDI73,SIUL2 GPIO pad data in register n" bitfld.byte 0x24A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x24B "GPDI72,SIUL2 GPIO pad data in register n" bitfld.byte 0x24B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x24C "GPDI79,SIUL2 GPIO pad data in register n" bitfld.byte 0x24C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x24D "GPDI78,SIUL2 GPIO pad data in register n" bitfld.byte 0x24D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x24E "GPDI77,SIUL2 GPIO pad data in register n" bitfld.byte 0x24E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x24F "GPDI76,SIUL2 GPIO pad data in register n" bitfld.byte 0x24F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x250 "GPDI83,SIUL2 GPIO pad data in register n" bitfld.byte 0x250 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x251 "GPDI82,SIUL2 GPIO pad data in register n" bitfld.byte 0x251 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x252 "GPDI81,SIUL2 GPIO pad data in register n" bitfld.byte 0x252 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x253 "GPDI80,SIUL2 GPIO pad data in register n" bitfld.byte 0x253 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x254 "GPDI87,SIUL2 GPIO pad data in register n" bitfld.byte 0x254 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x255 "GPDI86,SIUL2 GPIO pad data in register n" bitfld.byte 0x255 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x256 "GPDI85,SIUL2 GPIO pad data in register n" bitfld.byte 0x256 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x257 "GPDI84,SIUL2 GPIO pad data in register n" bitfld.byte 0x257 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x258 "GPDI91,SIUL2 GPIO pad data in register n" bitfld.byte 0x258 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x259 "GPDI90,SIUL2 GPIO pad data in register n" bitfld.byte 0x259 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x25A "GPDI89,SIUL2 GPIO pad data in register n" bitfld.byte 0x25A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x25B "GPDI88,SIUL2 GPIO pad data in register n" bitfld.byte 0x25B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x25C "GPDI95,SIUL2 GPIO pad data in register n" bitfld.byte 0x25C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x25D "GPDI94,SIUL2 GPIO pad data in register n" bitfld.byte 0x25D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x25E "GPDI93,SIUL2 GPIO pad data in register n" bitfld.byte 0x25E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x25F "GPDI92,SIUL2 GPIO pad data in register n" bitfld.byte 0x25F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x260 "GPDI99,SIUL2 GPIO pad data in register n" bitfld.byte 0x260 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x261 "GPDI98,SIUL2 GPIO pad data in register n" bitfld.byte 0x261 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x262 "GPDI97,SIUL2 GPIO pad data in register n" bitfld.byte 0x262 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x263 "GPDI96,SIUL2 GPIO pad data in register n" bitfld.byte 0x263 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x264 "GPDI103,SIUL2 GPIO pad data in register n" bitfld.byte 0x264 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x265 "GPDI102,SIUL2 GPIO pad data in register n" bitfld.byte 0x265 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x266 "GPDI101,SIUL2 GPIO pad data in register n" bitfld.byte 0x266 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x267 "GPDI100,SIUL2 GPIO pad data in register n" bitfld.byte 0x267 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x268 "GPDI107,SIUL2 GPIO pad data in register n" bitfld.byte 0x268 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x269 "GPDI106,SIUL2 GPIO pad data in register n" bitfld.byte 0x269 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x26A "GPDI105,SIUL2 GPIO pad data in register n" bitfld.byte 0x26A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x26B "GPDI104,SIUL2 GPIO pad data in register n" bitfld.byte 0x26B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x26C "GPDI111,SIUL2 GPIO pad data in register n" bitfld.byte 0x26C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x26D "GPDI110,SIUL2 GPIO pad data in register n" bitfld.byte 0x26D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x26E "GPDI109,SIUL2 GPIO pad data in register n" bitfld.byte 0x26E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x26F "GPDI108,SIUL2 GPIO pad data in register n" bitfld.byte 0x26F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x270 "GPDI115,SIUL2 GPIO pad data in register n" bitfld.byte 0x270 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x271 "GPDI114,SIUL2 GPIO pad data in register n" bitfld.byte 0x271 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x272 "GPDI113,SIUL2 GPIO pad data in register n" bitfld.byte 0x272 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x273 "GPDI112,SIUL2 GPIO pad data in register n" bitfld.byte 0x273 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x274 "GPDI119,SIUL2 GPIO pad data in register n" bitfld.byte 0x274 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x275 "GPDI118,SIUL2 GPIO pad data in register n" bitfld.byte 0x275 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x276 "GPDI117,SIUL2 GPIO pad data in register n" bitfld.byte 0x276 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x277 "GPDI116,SIUL2 GPIO pad data in register n" bitfld.byte 0x277 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x278 "GPDI123,SIUL2 GPIO pad data in register n" bitfld.byte 0x278 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x279 "GPDI122,SIUL2 GPIO pad data in register n" bitfld.byte 0x279 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x27A "GPDI121,SIUL2 GPIO pad data in register n" bitfld.byte 0x27A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x27B "GPDI120,SIUL2 GPIO pad data in register n" bitfld.byte 0x27B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x27C "GPDI127,SIUL2 GPIO pad data in register n" bitfld.byte 0x27C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x27D "GPDI126,SIUL2 GPIO pad data in register n" bitfld.byte 0x27D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x27E "GPDI125,SIUL2 GPIO pad data in register n" bitfld.byte 0x27E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x27F "GPDI124,SIUL2 GPIO pad data in register n" bitfld.byte 0x27F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x280 "GPDI131,SIUL2 GPIO pad data in register n" bitfld.byte 0x280 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x281 "GPDI130,SIUL2 GPIO pad data in register n" bitfld.byte 0x281 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x282 "GPDI129,SIUL2 GPIO pad data in register n" bitfld.byte 0x282 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x283 "GPDI128,SIUL2 GPIO pad data in register n" bitfld.byte 0x283 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x284 "GPDI135,SIUL2 GPIO pad data in register n" bitfld.byte 0x284 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x285 "GPDI134,SIUL2 GPIO pad data in register n" bitfld.byte 0x285 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x286 "GPDI133,SIUL2 GPIO pad data in register n" bitfld.byte 0x286 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x287 "GPDI132,SIUL2 GPIO pad data in register n" bitfld.byte 0x287 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x288 "GPDI139,SIUL2 GPIO pad data in register n" bitfld.byte 0x288 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x289 "GPDI138,SIUL2 GPIO pad data in register n" bitfld.byte 0x289 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x28A "GPDI137,SIUL2 GPIO pad data in register n" bitfld.byte 0x28A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x28B "GPDI136,SIUL2 GPIO pad data in register n" bitfld.byte 0x28B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x28C "GPDI143,SIUL2 GPIO pad data in register n" bitfld.byte 0x28C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x28D "GPDI142,SIUL2 GPIO pad data in register n" bitfld.byte 0x28D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x28E "GPDI141,SIUL2 GPIO pad data in register n" bitfld.byte 0x28E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x28F "GPDI140,SIUL2 GPIO pad data in register n" bitfld.byte 0x28F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x290 "GPDI147,SIUL2 GPIO pad data in register n" bitfld.byte 0x290 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x291 "GPDI146,SIUL2 GPIO pad data in register n" bitfld.byte 0x291 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x292 "GPDI145,SIUL2 GPIO pad data in register n" bitfld.byte 0x292 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x293 "GPDI144,SIUL2 GPIO pad data in register n" bitfld.byte 0x293 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x294 "GPDI151,SIUL2 GPIO pad data in register n" bitfld.byte 0x294 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x295 "GPDI150,SIUL2 GPIO pad data in register n" bitfld.byte 0x295 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x296 "GPDI149,SIUL2 GPIO pad data in register n" bitfld.byte 0x296 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x297 "GPDI148,SIUL2 GPIO pad data in register n" bitfld.byte 0x297 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x298 "GPDI155,SIUL2 GPIO pad data in register n" bitfld.byte 0x298 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x299 "GPDI154,SIUL2 GPIO pad data in register n" bitfld.byte 0x299 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x29A "GPDI153,SIUL2 GPIO pad data in register n" bitfld.byte 0x29A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x29B "GPDI152,SIUL2 GPIO pad data in register n" bitfld.byte 0x29B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x29C "GPDI159,SIUL2 GPIO pad data in register n" bitfld.byte 0x29C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x29D "GPDI158,SIUL2 GPIO pad data in register n" bitfld.byte 0x29D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x29E "GPDI157,SIUL2 GPIO pad data in register n" bitfld.byte 0x29E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x29F "GPDI156,SIUL2 GPIO pad data in register n" bitfld.byte 0x29F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2A0 "GPDI163,SIUL2 GPIO pad data in register n" bitfld.byte 0x2A0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2A1 "GPDI162,SIUL2 GPIO pad data in register n" bitfld.byte 0x2A1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2A2 "GPDI161,SIUL2 GPIO pad data in register n" bitfld.byte 0x2A2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2A3 "GPDI160,SIUL2 GPIO pad data in register n" bitfld.byte 0x2A3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2A4 "GPDI167,SIUL2 GPIO pad data in register n" bitfld.byte 0x2A4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2A5 "GPDI166,SIUL2 GPIO pad data in register n" bitfld.byte 0x2A5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2A6 "GPDI165,SIUL2 GPIO pad data in register n" bitfld.byte 0x2A6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2A7 "GPDI164,SIUL2 GPIO pad data in register n" bitfld.byte 0x2A7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2A8 "GPDI171,SIUL2 GPIO pad data in register n" bitfld.byte 0x2A8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2A9 "GPDI170,SIUL2 GPIO pad data in register n" bitfld.byte 0x2A9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2AA "GPDI169,SIUL2 GPIO pad data in register n" bitfld.byte 0x2AA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2AB "GPDI168,SIUL2 GPIO pad data in register n" bitfld.byte 0x2AB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2AC "GPDI175,SIUL2 GPIO pad data in register n" bitfld.byte 0x2AC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2AD "GPDI174,SIUL2 GPIO pad data in register n" bitfld.byte 0x2AD 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2AE "GPDI173,SIUL2 GPIO pad data in register n" bitfld.byte 0x2AE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2AF "GPDI172,SIUL2 GPIO pad data in register n" bitfld.byte 0x2AF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2B0 "GPDI179,SIUL2 GPIO pad data in register n" bitfld.byte 0x2B0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2B1 "GPDI178,SIUL2 GPIO pad data in register n" bitfld.byte 0x2B1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2B2 "GPDI177,SIUL2 GPIO pad data in register n" bitfld.byte 0x2B2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2B3 "GPDI176,SIUL2 GPIO pad data in register n" bitfld.byte 0x2B3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2B4 "GPDI183,SIUL2 GPIO pad data in register n" bitfld.byte 0x2B4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2B5 "GPDI182,SIUL2 GPIO pad data in register n" bitfld.byte 0x2B5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2B6 "GPDI181,SIUL2 GPIO pad data in register n" bitfld.byte 0x2B6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2B7 "GPDI180,SIUL2 GPIO pad data in register n" bitfld.byte 0x2B7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2B8 "GPDI187,SIUL2 GPIO pad data in register n" bitfld.byte 0x2B8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2B9 "GPDI186,SIUL2 GPIO pad data in register n" bitfld.byte 0x2B9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2BA "GPDI185,SIUL2 GPIO pad data in register n" bitfld.byte 0x2BA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2BB "GPDI184,SIUL2 GPIO pad data in register n" bitfld.byte 0x2BB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2BC "GPDI191,SIUL2 GPIO pad data in register n" bitfld.byte 0x2BC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2BD "GPDI190,SIUL2 GPIO pad data in register n" bitfld.byte 0x2BD 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2BE "GPDI189,SIUL2 GPIO pad data in register n" bitfld.byte 0x2BE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2BF "GPDI188,SIUL2 GPIO pad data in register n" bitfld.byte 0x2BF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2C0 "GPDI195,SIUL2 GPIO pad data in register n" bitfld.byte 0x2C0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2C1 "GPDI194,SIUL2 GPIO pad data in register n" bitfld.byte 0x2C1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2C2 "GPDI193,SIUL2 GPIO pad data in register n" bitfld.byte 0x2C2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2C3 "GPDI192,SIUL2 GPIO pad data in register n" bitfld.byte 0x2C3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2C4 "GPDI199,SIUL2 GPIO pad data in register n" bitfld.byte 0x2C4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2C5 "GPDI198,SIUL2 GPIO pad data in register n" bitfld.byte 0x2C5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2C6 "GPDI197,SIUL2 GPIO pad data in register n" bitfld.byte 0x2C6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2C7 "GPDI196,SIUL2 GPIO pad data in register n" bitfld.byte 0x2C7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2C8 "GPDI203,SIUL2 GPIO pad data in register n" bitfld.byte 0x2C8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2C9 "GPDI202,SIUL2 GPIO pad data in register n" bitfld.byte 0x2C9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2CA "GPDI201,SIUL2 GPIO pad data in register n" bitfld.byte 0x2CA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2CB "GPDI200,SIUL2 GPIO pad data in register n" bitfld.byte 0x2CB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2CC "GPDI207,SIUL2 GPIO pad data in register n" bitfld.byte 0x2CC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2CD "GPDI206,SIUL2 GPIO pad data in register n" bitfld.byte 0x2CD 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2CE "GPDI205,SIUL2 GPIO pad data in register n" bitfld.byte 0x2CE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2CF "GPDI204,SIUL2 GPIO pad data in register n" bitfld.byte 0x2CF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2D0 "GPDI211,SIUL2 GPIO pad data in register n" bitfld.byte 0x2D0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2D1 "GPDI210,SIUL2 GPIO pad data in register n" bitfld.byte 0x2D1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2D2 "GPDI209,SIUL2 GPIO pad data in register n" bitfld.byte 0x2D2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2D3 "GPDI208,SIUL2 GPIO pad data in register n" bitfld.byte 0x2D3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2D4 "GPDI215,SIUL2 GPIO pad data in register n" bitfld.byte 0x2D4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2D5 "GPDI214,SIUL2 GPIO pad data in register n" bitfld.byte 0x2D5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2D6 "GPDI213,SIUL2 GPIO pad data in register n" bitfld.byte 0x2D6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2D7 "GPDI212,SIUL2 GPIO pad data in register n" bitfld.byte 0x2D7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2D8 "GPDI219,SIUL2 GPIO pad data in register n" bitfld.byte 0x2D8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2D9 "GPDI218,SIUL2 GPIO pad data in register n" bitfld.byte 0x2D9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2DA "GPDI217,SIUL2 GPIO pad data in register n" bitfld.byte 0x2DA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2DB "GPDI216,SIUL2 GPIO pad data in register n" bitfld.byte 0x2DB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2DC "GPDI223,SIUL2 GPIO pad data in register n" bitfld.byte 0x2DC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2DD "GPDI222,SIUL2 GPIO pad data in register n" bitfld.byte 0x2DD 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2DE "GPDI221,SIUL2 GPIO pad data in register n" bitfld.byte 0x2DE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2DF "GPDI220,SIUL2 GPIO pad data in register n" bitfld.byte 0x2DF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2E0 "GPDI227,SIUL2 GPIO pad data in register n" bitfld.byte 0x2E0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2E1 "GPDI226,SIUL2 GPIO pad data in register n" bitfld.byte 0x2E1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2E2 "GPDI225,SIUL2 GPIO pad data in register n" bitfld.byte 0x2E2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2E3 "GPDI224,SIUL2 GPIO pad data in register n" bitfld.byte 0x2E3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2E4 "GPDI231,SIUL2 GPIO pad data in register n" bitfld.byte 0x2E4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2E5 "GPDI230,SIUL2 GPIO pad data in register n" bitfld.byte 0x2E5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2E6 "GPDI229,SIUL2 GPIO pad data in register n" bitfld.byte 0x2E6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2E7 "GPDI228,SIUL2 GPIO pad data in register n" bitfld.byte 0x2E7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2E8 "GPDI235,SIUL2 GPIO pad data in register n" bitfld.byte 0x2E8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2E9 "GPDI234,SIUL2 GPIO pad data in register n" bitfld.byte 0x2E9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2EA "GPDI233,SIUL2 GPIO pad data in register n" bitfld.byte 0x2EA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2EB "GPDI232,SIUL2 GPIO pad data in register n" bitfld.byte 0x2EB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2EC "GPDI239,SIUL2 GPIO pad data in register n" bitfld.byte 0x2EC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2ED "GPDI238,SIUL2 GPIO pad data in register n" bitfld.byte 0x2ED 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2EE "GPDI237,SIUL2 GPIO pad data in register n" bitfld.byte 0x2EE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2EF "GPDI236,SIUL2 GPIO pad data in register n" bitfld.byte 0x2EF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2F0 "GPDI243,SIUL2 GPIO pad data in register n" bitfld.byte 0x2F0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2F1 "GPDI242,SIUL2 GPIO pad data in register n" bitfld.byte 0x2F1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2F2 "GPDI241,SIUL2 GPIO pad data in register n" bitfld.byte 0x2F2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2F3 "GPDI240,SIUL2 GPIO pad data in register n" bitfld.byte 0x2F3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2F4 "GPDI247,SIUL2 GPIO pad data in register n" bitfld.byte 0x2F4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2F5 "GPDI246,SIUL2 GPIO pad data in register n" bitfld.byte 0x2F5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2F6 "GPDI245,SIUL2 GPIO pad data in register n" bitfld.byte 0x2F6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2F7 "GPDI244,SIUL2 GPIO pad data in register n" bitfld.byte 0x2F7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2F8 "GPDI251,SIUL2 GPIO pad data in register n" bitfld.byte 0x2F8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2F9 "GPDI250,SIUL2 GPIO pad data in register n" bitfld.byte 0x2F9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2FA "GPDI249,SIUL2 GPIO pad data in register n" bitfld.byte 0x2FA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2FB "GPDI248,SIUL2 GPIO pad data in register n" bitfld.byte 0x2FB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2FC "GPDI255,SIUL2 GPIO pad data in register n" bitfld.byte 0x2FC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2FD "GPDI254,SIUL2 GPIO pad data in register n" bitfld.byte 0x2FD 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2FE "GPDI253,SIUL2 GPIO pad data in register n" bitfld.byte 0x2FE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2FF "GPDI252,SIUL2 GPIO pad data in register n" bitfld.byte 0x2FF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x300 "GPDI259,SIUL2 GPIO pad data in register n" bitfld.byte 0x300 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x301 "GPDI258,SIUL2 GPIO pad data in register n" bitfld.byte 0x301 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x302 "GPDI257,SIUL2 GPIO pad data in register n" bitfld.byte 0x302 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x303 "GPDI256,SIUL2 GPIO pad data in register n" bitfld.byte 0x303 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x304 "GPDI263,SIUL2 GPIO pad data in register n" bitfld.byte 0x304 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x305 "GPDI262,SIUL2 GPIO pad data in register n" bitfld.byte 0x305 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x306 "GPDI261,SIUL2 GPIO pad data in register n" bitfld.byte 0x306 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x307 "GPDI260,SIUL2 GPIO pad data in register n" bitfld.byte 0x307 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x308 "GPDI267,SIUL2 GPIO pad data in register n" bitfld.byte 0x308 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x309 "GPDI266,SIUL2 GPIO pad data in register n" bitfld.byte 0x309 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x30A "GPDI265,SIUL2 GPIO pad data in register n" bitfld.byte 0x30A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x30B "GPDI264,SIUL2 GPIO pad data in register n" bitfld.byte 0x30B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x30C "GPDI271,SIUL2 GPIO pad data in register n" bitfld.byte 0x30C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x30D "GPDI270,SIUL2 GPIO pad data in register n" bitfld.byte 0x30D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x30E "GPDI269,SIUL2 GPIO pad data in register n" bitfld.byte 0x30E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x30F "GPDI268,SIUL2 GPIO pad data in register n" bitfld.byte 0x30F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x310 "GPDI275,SIUL2 GPIO pad data in register n" bitfld.byte 0x310 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x311 "GPDI274,SIUL2 GPIO pad data in register n" bitfld.byte 0x311 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x312 "GPDI273,SIUL2 GPIO pad data in register n" bitfld.byte 0x312 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x313 "GPDI272,SIUL2 GPIO pad data in register n" bitfld.byte 0x313 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x314 "GPDI279,SIUL2 GPIO pad data in register n" bitfld.byte 0x314 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x315 "GPDI278,SIUL2 GPIO pad data in register n" bitfld.byte 0x315 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x316 "GPDI277,SIUL2 GPIO pad data in register n" bitfld.byte 0x316 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x317 "GPDI276,SIUL2 GPIO pad data in register n" bitfld.byte 0x317 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x318 "GPDI283,SIUL2 GPIO pad data in register n" bitfld.byte 0x318 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x319 "GPDI282,SIUL2 GPIO pad data in register n" bitfld.byte 0x319 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x31A "GPDI281,SIUL2 GPIO pad data in register n" bitfld.byte 0x31A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x31B "GPDI280,SIUL2 GPIO pad data in register n" bitfld.byte 0x31B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x31C "GPDI287,SIUL2 GPIO pad data in register n" bitfld.byte 0x31C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x31D "GPDI286,SIUL2 GPIO pad data in register n" bitfld.byte 0x31D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x31E "GPDI285,SIUL2 GPIO pad data in register n" bitfld.byte 0x31E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x31F "GPDI284,SIUL2 GPIO pad data in register n" bitfld.byte 0x31F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x320 "GPDI291,SIUL2 GPIO pad data in register n" bitfld.byte 0x320 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x321 "GPDI290,SIUL2 GPIO pad data in register n" bitfld.byte 0x321 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x322 "GPDI289,SIUL2 GPIO pad data in register n" bitfld.byte 0x322 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x323 "GPDI288,SIUL2 GPIO pad data in register n" bitfld.byte 0x323 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x324 "GPDI295,SIUL2 GPIO pad data in register n" bitfld.byte 0x324 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x325 "GPDI294,SIUL2 GPIO pad data in register n" bitfld.byte 0x325 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x326 "GPDI293,SIUL2 GPIO pad data in register n" bitfld.byte 0x326 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x327 "GPDI292,SIUL2 GPIO pad data in register n" bitfld.byte 0x327 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x328 "GPDI299,SIUL2 GPIO pad data in register n" bitfld.byte 0x328 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x329 "GPDI298,SIUL2 GPIO pad data in register n" bitfld.byte 0x329 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x32A "GPDI297,SIUL2 GPIO pad data in register n" bitfld.byte 0x32A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x32B "GPDI296,SIUL2 GPIO pad data in register n" bitfld.byte 0x32B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x32C "GPDI303,SIUL2 GPIO pad data in register n" bitfld.byte 0x32C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x32D "GPDI302,SIUL2 GPIO pad data in register n" bitfld.byte 0x32D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x32E "GPDI301,SIUL2 GPIO pad data in register n" bitfld.byte 0x32E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x32F "GPDI300,SIUL2 GPIO pad data in register n" bitfld.byte 0x32F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x330 "GPDI307,SIUL2 GPIO pad data in register n" bitfld.byte 0x330 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x331 "GPDI306,SIUL2 GPIO pad data in register n" bitfld.byte 0x331 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x332 "GPDI305,SIUL2 GPIO pad data in register n" bitfld.byte 0x332 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x333 "GPDI304,SIUL2 GPIO pad data in register n" bitfld.byte 0x333 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x334 "GPDI311,SIUL2 GPIO pad data in register n" bitfld.byte 0x334 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x335 "GPDI310,SIUL2 GPIO pad data in register n" bitfld.byte 0x335 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x336 "GPDI309,SIUL2 GPIO pad data in register n" bitfld.byte 0x336 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x337 "GPDI308,SIUL2 GPIO pad data in register n" bitfld.byte 0x337 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x338 "GPDI315,SIUL2 GPIO pad data in register n" bitfld.byte 0x338 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x339 "GPDI314,SIUL2 GPIO pad data in register n" bitfld.byte 0x339 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x33A "GPDI313,SIUL2 GPIO pad data in register n" bitfld.byte 0x33A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x33B "GPDI312,SIUL2 GPIO pad data in register n" bitfld.byte 0x33B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x33C "GPDI319,SIUL2 GPIO pad data in register n" bitfld.byte 0x33C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x33D "GPDI318,SIUL2 GPIO pad data in register n" bitfld.byte 0x33D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x33E "GPDI317,SIUL2 GPIO pad data in register n" bitfld.byte 0x33E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x33F "GPDI316,SIUL2 GPIO pad data in register n" bitfld.byte 0x33F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x340 "GPDI323,SIUL2 GPIO pad data in register n" bitfld.byte 0x340 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x341 "GPDI322,SIUL2 GPIO pad data in register n" bitfld.byte 0x341 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x342 "GPDI321,SIUL2 GPIO pad data in register n" bitfld.byte 0x342 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x343 "GPDI320,SIUL2 GPIO pad data in register n" bitfld.byte 0x343 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x344 "GPDI327,SIUL2 GPIO pad data in register n" bitfld.byte 0x344 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x345 "GPDI326,SIUL2 GPIO pad data in register n" bitfld.byte 0x345 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x346 "GPDI325,SIUL2 GPIO pad data in register n" bitfld.byte 0x346 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x347 "GPDI324,SIUL2 GPIO pad data in register n" bitfld.byte 0x347 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x348 "GPDI331,SIUL2 GPIO pad data in register n" bitfld.byte 0x348 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x349 "GPDI330,SIUL2 GPIO pad data in register n" bitfld.byte 0x349 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x34A "GPDI329,SIUL2 GPIO pad data in register n" bitfld.byte 0x34A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x34B "GPDI328,SIUL2 GPIO pad data in register n" bitfld.byte 0x34B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x34C "GPDI335,SIUL2 GPIO pad data in register n" bitfld.byte 0x34C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x34D "GPDI334,SIUL2 GPIO pad data in register n" bitfld.byte 0x34D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x34E "GPDI333,SIUL2 GPIO pad data in register n" bitfld.byte 0x34E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x34F "GPDI332,SIUL2 GPIO pad data in register n" bitfld.byte 0x34F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x350 "GPDI339,SIUL2 GPIO pad data in register n" bitfld.byte 0x350 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x351 "GPDI338,SIUL2 GPIO pad data in register n" bitfld.byte 0x351 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x352 "GPDI337,SIUL2 GPIO pad data in register n" bitfld.byte 0x352 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x353 "GPDI336,SIUL2 GPIO pad data in register n" bitfld.byte 0x353 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x354 "GPDI343,SIUL2 GPIO pad data in register n" bitfld.byte 0x354 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x355 "GPDI342,SIUL2 GPIO pad data in register n" bitfld.byte 0x355 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x356 "GPDI341,SIUL2 GPIO pad data in register n" bitfld.byte 0x356 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x357 "GPDI340,SIUL2 GPIO pad data in register n" bitfld.byte 0x357 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x358 "GPDI347,SIUL2 GPIO pad data in register n" bitfld.byte 0x358 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x359 "GPDI346,SIUL2 GPIO pad data in register n" bitfld.byte 0x359 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x35A "GPDI345,SIUL2 GPIO pad data in register n" bitfld.byte 0x35A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x35B "GPDI344,SIUL2 GPIO pad data in register n" bitfld.byte 0x35B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x35C "GPDI351,SIUL2 GPIO pad data in register n" bitfld.byte 0x35C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x35D "GPDI350,SIUL2 GPIO pad data in register n" bitfld.byte 0x35D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x35E "GPDI349,SIUL2 GPIO pad data in register n" bitfld.byte 0x35E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x35F "GPDI348,SIUL2 GPIO pad data in register n" bitfld.byte 0x35F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x360 "GPDI355,SIUL2 GPIO pad data in register n" bitfld.byte 0x360 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x361 "GPDI354,SIUL2 GPIO pad data in register n" bitfld.byte 0x361 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x362 "GPDI353,SIUL2 GPIO pad data in register n" bitfld.byte 0x362 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x363 "GPDI352,SIUL2 GPIO pad data in register n" bitfld.byte 0x363 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x364 "GPDI359,SIUL2 GPIO pad data in register n" bitfld.byte 0x364 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x365 "GPDI358,SIUL2 GPIO pad data in register n" bitfld.byte 0x365 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x366 "GPDI357,SIUL2 GPIO pad data in register n" bitfld.byte 0x366 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x367 "GPDI356,SIUL2 GPIO pad data in register n" bitfld.byte 0x367 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x368 "GPDI363,SIUL2 GPIO pad data in register n" bitfld.byte 0x368 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x369 "GPDI362,SIUL2 GPIO pad data in register n" bitfld.byte 0x369 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x36A "GPDI361,SIUL2 GPIO pad data in register n" bitfld.byte 0x36A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x36B "GPDI360,SIUL2 GPIO pad data in register n" bitfld.byte 0x36B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x36C "GPDI367,SIUL2 GPIO pad data in register n" bitfld.byte 0x36C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x36D "GPDI366,SIUL2 GPIO pad data in register n" bitfld.byte 0x36D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x36E "GPDI365,SIUL2 GPIO pad data in register n" bitfld.byte 0x36E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x36F "GPDI364,SIUL2 GPIO pad data in register n" bitfld.byte 0x36F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x370 "GPDI371,SIUL2 GPIO pad data in register n" bitfld.byte 0x370 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x371 "GPDI370,SIUL2 GPIO pad data in register n" bitfld.byte 0x371 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x372 "GPDI369,SIUL2 GPIO pad data in register n" bitfld.byte 0x372 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x373 "GPDI368,SIUL2 GPIO pad data in register n" bitfld.byte 0x373 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x374 "GPDI375,SIUL2 GPIO pad data in register n" bitfld.byte 0x374 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x375 "GPDI374,SIUL2 GPIO pad data in register n" bitfld.byte 0x375 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x376 "GPDI373,SIUL2 GPIO pad data in register n" bitfld.byte 0x376 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x377 "GPDI372,SIUL2 GPIO pad data in register n" bitfld.byte 0x377 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x378 "GPDI379,SIUL2 GPIO pad data in register n" bitfld.byte 0x378 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x379 "GPDI378,SIUL2 GPIO pad data in register n" bitfld.byte 0x379 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x37A "GPDI377,SIUL2 GPIO pad data in register n" bitfld.byte 0x37A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x37B "GPDI376,SIUL2 GPIO pad data in register n" bitfld.byte 0x37B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x37C "GPDI383,SIUL2 GPIO pad data in register n" bitfld.byte 0x37C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x37D "GPDI382,SIUL2 GPIO pad data in register n" bitfld.byte 0x37D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x37E "GPDI381,SIUL2 GPIO pad data in register n" bitfld.byte 0x37E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x37F "GPDI380,SIUL2 GPIO pad data in register n" bitfld.byte 0x37F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x380 "GPDI387,SIUL2 GPIO pad data in register n" bitfld.byte 0x380 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x381 "GPDI386,SIUL2 GPIO pad data in register n" bitfld.byte 0x381 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x382 "GPDI385,SIUL2 GPIO pad data in register n" bitfld.byte 0x382 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x383 "GPDI384,SIUL2 GPIO pad data in register n" bitfld.byte 0x383 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x384 "GPDI391,SIUL2 GPIO pad data in register n" bitfld.byte 0x384 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x385 "GPDI390,SIUL2 GPIO pad data in register n" bitfld.byte 0x385 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x386 "GPDI389,SIUL2 GPIO pad data in register n" bitfld.byte 0x386 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x387 "GPDI388,SIUL2 GPIO pad data in register n" bitfld.byte 0x387 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x388 "GPDI395,SIUL2 GPIO pad data in register n" bitfld.byte 0x388 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x389 "GPDI394,SIUL2 GPIO pad data in register n" bitfld.byte 0x389 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x38A "GPDI393,SIUL2 GPIO pad data in register n" bitfld.byte 0x38A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x38B "GPDI392,SIUL2 GPIO pad data in register n" bitfld.byte 0x38B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x38C "GPDI399,SIUL2 GPIO pad data in register n" bitfld.byte 0x38C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x38D "GPDI398,SIUL2 GPIO pad data in register n" bitfld.byte 0x38D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x38E "GPDI397,SIUL2 GPIO pad data in register n" bitfld.byte 0x38E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x38F "GPDI396,SIUL2 GPIO pad data in register n" bitfld.byte 0x38F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x390 "GPDI403,SIUL2 GPIO pad data in register n" bitfld.byte 0x390 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x391 "GPDI402,SIUL2 GPIO pad data in register n" bitfld.byte 0x391 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x392 "GPDI401,SIUL2 GPIO pad data in register n" bitfld.byte 0x392 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x393 "GPDI400,SIUL2 GPIO pad data in register n" bitfld.byte 0x393 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x394 "GPDI407,SIUL2 GPIO pad data in register n" bitfld.byte 0x394 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x395 "GPDI406,SIUL2 GPIO pad data in register n" bitfld.byte 0x395 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x396 "GPDI405,SIUL2 GPIO pad data in register n" bitfld.byte 0x396 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x397 "GPDI404,SIUL2 GPIO pad data in register n" bitfld.byte 0x397 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x398 "GPDI411,SIUL2 GPIO pad data in register n" bitfld.byte 0x398 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x399 "GPDI410,SIUL2 GPIO pad data in register n" bitfld.byte 0x399 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x39A "GPDI409,SIUL2 GPIO pad data in register n" bitfld.byte 0x39A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x39B "GPDI408,SIUL2 GPIO pad data in register n" bitfld.byte 0x39B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x39C "GPDI415,SIUL2 GPIO pad data in register n" bitfld.byte 0x39C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x39D "GPDI414,SIUL2 GPIO pad data in register n" bitfld.byte 0x39D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x39E "GPDI413,SIUL2 GPIO pad data in register n" bitfld.byte 0x39E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x39F "GPDI412,SIUL2 GPIO pad data in register n" bitfld.byte 0x39F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3A0 "GPDI419,SIUL2 GPIO pad data in register n" bitfld.byte 0x3A0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3A1 "GPDI418,SIUL2 GPIO pad data in register n" bitfld.byte 0x3A1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3A2 "GPDI417,SIUL2 GPIO pad data in register n" bitfld.byte 0x3A2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3A3 "GPDI416,SIUL2 GPIO pad data in register n" bitfld.byte 0x3A3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3A4 "GPDI423,SIUL2 GPIO pad data in register n" bitfld.byte 0x3A4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3A5 "GPDI422,SIUL2 GPIO pad data in register n" bitfld.byte 0x3A5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3A6 "GPDI421,SIUL2 GPIO pad data in register n" bitfld.byte 0x3A6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3A7 "GPDI420,SIUL2 GPIO pad data in register n" bitfld.byte 0x3A7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3A8 "GPDI427,SIUL2 GPIO pad data in register n" bitfld.byte 0x3A8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3A9 "GPDI426,SIUL2 GPIO pad data in register n" bitfld.byte 0x3A9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3AA "GPDI425,SIUL2 GPIO pad data in register n" bitfld.byte 0x3AA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3AB "GPDI424,SIUL2 GPIO pad data in register n" bitfld.byte 0x3AB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3AC "GPDI431,SIUL2 GPIO pad data in register n" bitfld.byte 0x3AC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3AD "GPDI430,SIUL2 GPIO pad data in register n" bitfld.byte 0x3AD 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3AE "GPDI429,SIUL2 GPIO pad data in register n" bitfld.byte 0x3AE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3AF "GPDI428,SIUL2 GPIO pad data in register n" bitfld.byte 0x3AF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3B0 "GPDI435,SIUL2 GPIO pad data in register n" bitfld.byte 0x3B0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3B1 "GPDI434,SIUL2 GPIO pad data in register n" bitfld.byte 0x3B1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3B2 "GPDI433,SIUL2 GPIO pad data in register n" bitfld.byte 0x3B2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3B3 "GPDI432,SIUL2 GPIO pad data in register n" bitfld.byte 0x3B3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3B4 "GPDI439,SIUL2 GPIO pad data in register n" bitfld.byte 0x3B4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3B5 "GPDI438,SIUL2 GPIO pad data in register n" bitfld.byte 0x3B5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3B6 "GPDI437,SIUL2 GPIO pad data in register n" bitfld.byte 0x3B6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3B7 "GPDI436,SIUL2 GPIO pad data in register n" bitfld.byte 0x3B7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3B8 "GPDI443,SIUL2 GPIO pad data in register n" bitfld.byte 0x3B8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3B9 "GPDI442,SIUL2 GPIO pad data in register n" bitfld.byte 0x3B9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3BA "GPDI441,SIUL2 GPIO pad data in register n" bitfld.byte 0x3BA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3BB "GPDI440,SIUL2 GPIO pad data in register n" bitfld.byte 0x3BB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3BC "GPDI447,SIUL2 GPIO pad data in register n" bitfld.byte 0x3BC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3BD "GPDI446,SIUL2 GPIO pad data in register n" bitfld.byte 0x3BD 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3BE "GPDI445,SIUL2 GPIO pad data in register n" bitfld.byte 0x3BE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3BF "GPDI444,SIUL2 GPIO pad data in register n" bitfld.byte 0x3BF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3C0 "GPDI451,SIUL2 GPIO pad data in register n" bitfld.byte 0x3C0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3C1 "GPDI450,SIUL2 GPIO pad data in register n" bitfld.byte 0x3C1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3C2 "GPDI449,SIUL2 GPIO pad data in register n" bitfld.byte 0x3C2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3C3 "GPDI448,SIUL2 GPIO pad data in register n" bitfld.byte 0x3C3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3C4 "GPDI455,SIUL2 GPIO pad data in register n" bitfld.byte 0x3C4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3C5 "GPDI454,SIUL2 GPIO pad data in register n" bitfld.byte 0x3C5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3C6 "GPDI453,SIUL2 GPIO pad data in register n" bitfld.byte 0x3C6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3C7 "GPDI452,SIUL2 GPIO pad data in register n" bitfld.byte 0x3C7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3C8 "GPDI459,SIUL2 GPIO pad data in register n" bitfld.byte 0x3C8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3C9 "GPDI458,SIUL2 GPIO pad data in register n" bitfld.byte 0x3C9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3CA "GPDI457,SIUL2 GPIO pad data in register n" bitfld.byte 0x3CA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3CB "GPDI456,SIUL2 GPIO pad data in register n" bitfld.byte 0x3CB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3CC "GPDI463,SIUL2 GPIO pad data in register n" bitfld.byte 0x3CC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3CD "GPDI462,SIUL2 GPIO pad data in register n" bitfld.byte 0x3CD 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3CE "GPDI461,SIUL2 GPIO pad data in register n" bitfld.byte 0x3CE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3CF "GPDI460,SIUL2 GPIO pad data in register n" bitfld.byte 0x3CF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3D0 "GPDI467,SIUL2 GPIO pad data in register n" bitfld.byte 0x3D0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3D1 "GPDI466,SIUL2 GPIO pad data in register n" bitfld.byte 0x3D1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3D2 "GPDI465,SIUL2 GPIO pad data in register n" bitfld.byte 0x3D2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3D3 "GPDI464,SIUL2 GPIO pad data in register n" bitfld.byte 0x3D3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3D4 "GPDI471,SIUL2 GPIO pad data in register n" bitfld.byte 0x3D4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3D5 "GPDI470,SIUL2 GPIO pad data in register n" bitfld.byte 0x3D5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3D6 "GPDI469,SIUL2 GPIO pad data in register n" bitfld.byte 0x3D6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3D7 "GPDI468,SIUL2 GPIO pad data in register n" bitfld.byte 0x3D7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3D8 "GPDI475,SIUL2 GPIO pad data in register n" bitfld.byte 0x3D8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3D9 "GPDI474,SIUL2 GPIO pad data in register n" bitfld.byte 0x3D9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3DA "GPDI473,SIUL2 GPIO pad data in register n" bitfld.byte 0x3DA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3DB "GPDI472,SIUL2 GPIO pad data in register n" bitfld.byte 0x3DB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3DC "GPDI479,SIUL2 GPIO pad data in register n" bitfld.byte 0x3DC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3DD "GPDI478,SIUL2 GPIO pad data in register n" bitfld.byte 0x3DD 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3DE "GPDI477,SIUL2 GPIO pad data in register n" bitfld.byte 0x3DE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3DF "GPDI476,SIUL2 GPIO pad data in register n" bitfld.byte 0x3DF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3E0 "GPDI483,SIUL2 GPIO pad data in register n" bitfld.byte 0x3E0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3E1 "GPDI482,SIUL2 GPIO pad data in register n" bitfld.byte 0x3E1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3E2 "GPDI481,SIUL2 GPIO pad data in register n" bitfld.byte 0x3E2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3E3 "GPDI480,SIUL2 GPIO pad data in register n" bitfld.byte 0x3E3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3E4 "GPDI487,SIUL2 GPIO pad data in register n" bitfld.byte 0x3E4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3E5 "GPDI486,SIUL2 GPIO pad data in register n" bitfld.byte 0x3E5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3E6 "GPDI485,SIUL2 GPIO pad data in register n" bitfld.byte 0x3E6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3E7 "GPDI484,SIUL2 GPIO pad data in register n" bitfld.byte 0x3E7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3E8 "GPDI491,SIUL2 GPIO pad data in register n" bitfld.byte 0x3E8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3E9 "GPDI490,SIUL2 GPIO pad data in register n" bitfld.byte 0x3E9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3EA "GPDI489,SIUL2 GPIO pad data in register n" bitfld.byte 0x3EA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3EB "GPDI488,SIUL2 GPIO pad data in register n" bitfld.byte 0x3EB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3EC "GPDI495,SIUL2 GPIO pad data in register n" bitfld.byte 0x3EC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3ED "GPDI494,SIUL2 GPIO pad data in register n" bitfld.byte 0x3ED 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3EE "GPDI493,SIUL2 GPIO pad data in register n" bitfld.byte 0x3EE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3EF "GPDI492,SIUL2 GPIO pad data in register n" bitfld.byte 0x3EF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3F0 "GPDI499,SIUL2 GPIO pad data in register n" bitfld.byte 0x3F0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3F1 "GPDI498,SIUL2 GPIO pad data in register n" bitfld.byte 0x3F1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3F2 "GPDI497,SIUL2 GPIO pad data in register n" bitfld.byte 0x3F2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3F3 "GPDI496,SIUL2 GPIO pad data in register n" bitfld.byte 0x3F3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3F4 "GPDI503,SIUL2 GPIO pad data in register n" bitfld.byte 0x3F4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3F5 "GPDI502,SIUL2 GPIO pad data in register n" bitfld.byte 0x3F5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3F6 "GPDI501,SIUL2 GPIO pad data in register n" bitfld.byte 0x3F6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3F7 "GPDI500,SIUL2 GPIO pad data in register n" bitfld.byte 0x3F7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3F8 "GPDI507,SIUL2 GPIO pad data in register n" bitfld.byte 0x3F8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3F9 "GPDI506,SIUL2 GPIO pad data in register n" bitfld.byte 0x3F9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3FA "GPDI505,SIUL2 GPIO pad data in register n" bitfld.byte 0x3FA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3FB "GPDI504,SIUL2 GPIO pad data in register n" bitfld.byte 0x3FB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3FC "GPDI511,SIUL2 GPIO pad data in register n" bitfld.byte 0x3FC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3FD "GPDI510,SIUL2 GPIO pad data in register n" bitfld.byte 0x3FD 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3FE "GPDI509,SIUL2 GPIO pad data in register n" bitfld.byte 0x3FE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3FF "GPDI508,SIUL2 GPIO pad data in register n" bitfld.byte 0x3FF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." group.word 0x1700++0x3F line.word 0x0 "PGPDO1,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x0 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x2 "PGPDO0,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x2 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x4 "PGPDO3,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x4 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x6 "PGPDO2,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x6 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x8 "PGPDO5,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x8 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0xA "PGPDO4,SIUL2 parallel GPIO pad data out register n" hexmask.word 0xA 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0xC "PGPDO7,SIUL2 parallel GPIO pad data out register n" hexmask.word 0xC 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0xE "PGPDO6,SIUL2 parallel GPIO pad data out register n" hexmask.word 0xE 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x10 "PGPDO9,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x10 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x12 "PGPDO8,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x12 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x14 "PGPDO11,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x14 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x16 "PGPDO10,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x16 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x18 "PGPDO13,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x18 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x1A "PGPDO12,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x1A 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x1C "PGPDO15,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x1C 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x1E "PGPDO14,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x1E 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x20 "PGPDO17,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x20 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x22 "PGPDO16,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x22 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x24 "PGPDO19,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x24 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x26 "PGPDO18,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x26 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x28 "PGPDO21,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x28 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x2A "PGPDO20,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x2A 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x2C "PGPDO23,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x2C 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x2E "PGPDO22,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x2E 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x30 "PGPDO25,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x30 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x32 "PGPDO24,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x32 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x34 "PGPDO27,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x34 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x36 "PGPDO26,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x36 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x38 "PGPDO29,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x38 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x3A "PGPDO28,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x3A 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x3C "PGPDO31,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x3C 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x3E "PGPDO30,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x3E 0.--15. 1. "PPDO,Parallel Pad Data Out" rgroup.word 0x1740++0x3F line.word 0x0 "PGPDI1,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x0 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x2 "PGPDI0,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x2 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x4 "PGPDI3,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x4 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x6 "PGPDI2,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x6 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x8 "PGPDI5,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x8 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0xA "PGPDI4,SIUL2 parallel GPIO pad data in register n" hexmask.word 0xA 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0xC "PGPDI7,SIUL2 parallel GPIO pad data in register n" hexmask.word 0xC 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0xE "PGPDI6,SIUL2 parallel GPIO pad data in register n" hexmask.word 0xE 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x10 "PGPDI9,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x10 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x12 "PGPDI8,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x12 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x14 "PGPDI11,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x14 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x16 "PGPDI10,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x16 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x18 "PGPDI13,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x18 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x1A "PGPDI12,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x1A 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x1C "PGPDI15,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x1C 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x1E "PGPDI14,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x1E 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x20 "PGPDI17,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x20 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x22 "PGPDI16,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x22 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x24 "PGPDI19,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x24 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x26 "PGPDI18,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x26 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x28 "PGPDI21,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x28 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x2A "PGPDI20,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x2A 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x2C "PGPDI23,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x2C 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x2E "PGPDI22,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x2E 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x30 "PGPDI25,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x30 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x32 "PGPDI24,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x32 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x34 "PGPDI27,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x34 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x36 "PGPDI26,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x36 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x38 "PGPDI29,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x38 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x3A "PGPDI28,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x3A 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x3C "PGPDI31,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x3C 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x3E "PGPDI30,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x3E 0.--15. 1. "PPDI,Parallel Pad Data In" group.long 0x1780++0x7F line.long 0x0 "MPGPDO0,SIUL2 masked parallel GPIO pad data output register 0" hexmask.long.word 0x0 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x0 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x4 "MPGPDO1,SIUL2 masked parallel GPIO pad data output register 1" hexmask.long.word 0x4 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x4 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x8 "MPGPDO2,SIUL2 masked parallel GPIO pad data output register 2" hexmask.long.word 0x8 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x8 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0xC "MPGPDO3,SIUL2 masked parallel GPIO pad data output register 3" hexmask.long.word 0xC 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0xC 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x10 "MPGPDO4,SIUL2 masked parallel GPIO pad data output register 4" hexmask.long.word 0x10 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x10 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x14 "MPGPDO5,SIUL2 masked parallel GPIO pad data output register 5" hexmask.long.word 0x14 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x14 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x18 "MPGPDO6,SIUL2 masked parallel GPIO pad data output register 6" hexmask.long.word 0x18 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x18 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x1C "MPGPDO7,SIUL2 masked parallel GPIO pad data output register 7" hexmask.long.word 0x1C 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x1C 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x20 "MPGPDO8,SIUL2 masked parallel GPIO pad data output register 8" hexmask.long.word 0x20 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x20 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x24 "MPGPDO9,SIUL2 masked parallel GPIO pad data output register 9" hexmask.long.word 0x24 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x24 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x28 "MPGPDO10,SIUL2 masked parallel GPIO pad data output register 10" hexmask.long.word 0x28 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x28 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x2C "MPGPDO11,SIUL2 masked parallel GPIO pad data output register 11" hexmask.long.word 0x2C 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x2C 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x30 "MPGPDO12,SIUL2 masked parallel GPIO pad data output register 12" hexmask.long.word 0x30 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x30 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x34 "MPGPDO13,SIUL2 masked parallel GPIO pad data output register 13" hexmask.long.word 0x34 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x34 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x38 "MPGPDO14,SIUL2 masked parallel GPIO pad data output register 14" hexmask.long.word 0x38 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x38 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x3C "MPGPDO15,SIUL2 masked parallel GPIO pad data output register 15" hexmask.long.word 0x3C 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x3C 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x40 "MPGPDO16,SIUL2 masked parallel GPIO pad data output register 16" hexmask.long.word 0x40 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x40 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x44 "MPGPDO17,SIUL2 masked parallel GPIO pad data output register 17" hexmask.long.word 0x44 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x44 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x48 "MPGPDO18,SIUL2 masked parallel GPIO pad data output register 18" hexmask.long.word 0x48 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x48 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x4C "MPGPDO19,SIUL2 masked parallel GPIO pad data output register 19" hexmask.long.word 0x4C 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x4C 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x50 "MPGPDO20,SIUL2 masked parallel GPIO pad data output register 20" hexmask.long.word 0x50 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x50 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x54 "MPGPDO21,SIUL2 masked parallel GPIO pad data output register 21" hexmask.long.word 0x54 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x54 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x58 "MPGPDO22,SIUL2 masked parallel GPIO pad data output register 22" hexmask.long.word 0x58 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x58 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x5C "MPGPDO23,SIUL2 masked parallel GPIO pad data output register 23" hexmask.long.word 0x5C 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x5C 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x60 "MPGPDO24,SIUL2 masked parallel GPIO pad data output register 24" hexmask.long.word 0x60 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x60 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x64 "MPGPDO25,SIUL2 masked parallel GPIO pad data output register 25" hexmask.long.word 0x64 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x64 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x68 "MPGPDO26,SIUL2 masked parallel GPIO pad data output register 26" hexmask.long.word 0x68 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x68 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x6C "MPGPDO27,SIUL2 masked parallel GPIO pad data output register 27" hexmask.long.word 0x6C 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x6C 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x70 "MPGPDO28,SIUL2 masked parallel GPIO pad data output register 28" hexmask.long.word 0x70 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x70 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x74 "MPGPDO29,SIUL2 masked parallel GPIO pad data output register 29" hexmask.long.word 0x74 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x74 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x78 "MPGPDO30,SIUL2 masked parallel GPIO pad data output register 30" hexmask.long.word 0x78 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x78 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x7C "MPGPDO31,SIUL2 masked parallel GPIO pad data output register 31" hexmask.long.word 0x7C 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x7C 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" tree.end tree "SIUL2_2" base ad:0x7116C000 group.long 0x10++0x3 line.long 0x0 "DISR0,SIUL2 DMA/interrupt status flag register 0" bitfld.long 0x0 15. "EIF15,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." bitfld.long 0x0 14. "EIF14,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." newline bitfld.long 0x0 13. "EIF13,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." bitfld.long 0x0 12. "EIF12,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." newline bitfld.long 0x0 11. "EIF11,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." bitfld.long 0x0 10. "EIF10,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." newline bitfld.long 0x0 9. "EIF9,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." bitfld.long 0x0 8. "EIF8,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." newline bitfld.long 0x0 7. "EIF7,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." bitfld.long 0x0 6. "EIF6,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." newline bitfld.long 0x0 5. "EIF5,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." bitfld.long 0x0 4. "EIF4,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." newline bitfld.long 0x0 3. "EIF3,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." bitfld.long 0x0 2. "EIF2,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." newline bitfld.long 0x0 1. "EIF1,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." bitfld.long 0x0 0. "EIF0,External Interrupt Status Flag x" "0: No interrupt or DMA event has occurred on the pad,1: An interrupt or DMA event as defined by.." group.long 0x18++0x3 line.long 0x0 "DIRER0,SIUL2 DMA/interrupt request enable register 0" bitfld.long 0x0 15. "EIRE15,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." bitfld.long 0x0 14. "EIRE14,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." newline bitfld.long 0x0 13. "EIRE13,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." bitfld.long 0x0 12. "EIRE12,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." newline bitfld.long 0x0 11. "EIRE11,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." bitfld.long 0x0 10. "EIRE10,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." newline bitfld.long 0x0 9. "EIRE9,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." bitfld.long 0x0 8. "EIRE8,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." newline bitfld.long 0x0 7. "EIRE7,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." bitfld.long 0x0 6. "EIRE6,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." newline bitfld.long 0x0 5. "EIRE5,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." bitfld.long 0x0 4. "EIRE4,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." newline bitfld.long 0x0 3. "EIRE3,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." bitfld.long 0x0 2. "EIRE2,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." newline bitfld.long 0x0 1. "EIRE1,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." bitfld.long 0x0 0. "EIRE0,External Interrupt or DMA Request Enable x" "0: Interrupt or DMA requests from the corresponding..,1: Set EIF[x] bit causes either a DMA or an.." group.long 0x20++0x3 line.long 0x0 "DIRSR0,SIUL2 DMA/interrupt request select register 0" bitfld.long 0x0 15. "DIRS15,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" bitfld.long 0x0 14. "DIRS14,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" newline bitfld.long 0x0 13. "DIRS13,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" bitfld.long 0x0 12. "DIRS12,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" newline bitfld.long 0x0 11. "DIRS11,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" bitfld.long 0x0 10. "DIRS10,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" newline bitfld.long 0x0 9. "DIRS9,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" bitfld.long 0x0 8. "DIRS8,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" newline bitfld.long 0x0 7. "DIRS7,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" bitfld.long 0x0 6. "DIRS6,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" newline bitfld.long 0x0 5. "DIRS5,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" bitfld.long 0x0 4. "DIRS4,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" newline bitfld.long 0x0 3. "DIRS3,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" bitfld.long 0x0 2. "DIRS2,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" newline bitfld.long 0x0 1. "DIRS1,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" bitfld.long 0x0 0. "DIRS0,DMA/Interrupt Request Select Register" "0: Interrupt request is selected,1: DMA request is selected" group.long 0x28++0x3 line.long 0x0 "IREER0,SIUL2 interrupt rising-edge event enable register 0" bitfld.long 0x0 15. "IREE15,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 14. "IREE14,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 13. "IREE13,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 12. "IREE12,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 11. "IREE11,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 10. "IREE10,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 9. "IREE9,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 8. "IREE8,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 7. "IREE7,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 6. "IREE6,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 5. "IREE5,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 4. "IREE4,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 3. "IREE3,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 2. "IREE2,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 1. "IREE1,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 0. "IREE0,Enable rising-edge events to cause the EIF[x] bit to be set." "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." group.long 0x30++0x3 line.long 0x0 "IFEER0,SIUL2 interrupt falling-edge event enable register 0" bitfld.long 0x0 15. "IFEE15,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x0 14. "IFEE14,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x0 13. "IFEE13,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x0 12. "IFEE12,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x0 11. "IFEE11,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x0 10. "IFEE10,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x0 9. "IFEE9,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x0 8. "IFEE8,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x0 7. "IFEE7,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x0 6. "IFEE6,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x0 5. "IFEE5,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x0 4. "IFEE4,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x0 3. "IFEE3,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x0 2. "IFEE2,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x0 1. "IFEE1,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x0 0. "IFEE0,Enable falling-edge events to cause the EIF[x] bit to be set." "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." group.long 0x38++0x3 line.long 0x0 "IFER0,SIUL2 Interrupt filter enable register 0" bitfld.long 0x0 15. "IFE15,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x0 14. "IFE14,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x0 13. "IFE13,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x0 12. "IFE12,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x0 11. "IFE11,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x0 10. "IFE10,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x0 9. "IFE9,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x0 8. "IFE8,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x0 7. "IFE7,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x0 6. "IFE6,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x0 5. "IFE5,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x0 4. "IFE4,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x0 3. "IFE3,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x0 2. "IFE2,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x0 1. "IFE1,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x0 0. "IFE0,Enable digital glitch filter on the interrupt pad input." "0: Filter is disabled.,1: Filter is enabled." group.long 0x40++0x3F line.long 0x0 "IFMCR0,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x0 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x4 "IFMCR1,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x4 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x8 "IFMCR2,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x8 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0xC "IFMCR3,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0xC 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x10 "IFMCR4,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x10 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x14 "IFMCR5,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x14 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x18 "IFMCR6,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x18 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x1C "IFMCR7,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x1C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x20 "IFMCR8,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x20 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x24 "IFMCR9,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x24 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x28 "IFMCR10,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x28 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x2C "IFMCR11,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x2C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x30 "IFMCR12,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x30 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x34 "IFMCR13,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x34 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x38 "IFMCR14,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x38 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" line.long 0x3C "IFMCR15,SIUL2 interrupt filter maximum counter register" hexmask.long.byte 0x3C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting (MAXCNTx)" group.long 0xC0++0x3 line.long 0x0 "IFCPR,SIUL2 interrupt filter clock prescaler register" hexmask.long.byte 0x0 0.--3. 1. "IFCP,Interrupt Filter Clock Prescaler setting" group.long 0x100++0x3 line.long 0x0 "SCR0,SIUL2 Soc configuration register 0" bitfld.long 0x0 31. "MCS_ADC_SEL_EN,This bit enables the GTM-ADCQ interface logic present in GTMINT module. By default this bit is 0 and should be set to 1 only after the ADCQ." "0: Disable GTM-ADCQ Interface.,1: Enable GTM-ADCQ Interface." hexmask.long.byte 0x0 16.--19. 1. "MCS4_ADC_SEL,External ADCQ mapped with MCS4" newline hexmask.long.byte 0x0 12.--15. 1. "MCS3_ADC_SEL,External ADCQ mapped with MCS3" hexmask.long.byte 0x0 8.--11. 1. "MCS2_ADC_SEL,External ADCQ mapped with MCS2" newline hexmask.long.byte 0x0 4.--7. 1. "MCS1_ADC_SEL,External ADCQ mapped with MCS1" hexmask.long.byte 0x0 0.--3. 1. "MCS0_ADC_SEL,External ADCQ mapped with MCS0" group.long 0x180++0xF line.long 0x0 "IPFCPR0,SIUL2 input pin filter clock prescaler register 0" bitfld.long 0x0 11. "JEN,Enable jitter injection to increase periodic noise immunity." "0: The pseudo-random clock division feature is..,1: The pseudo-random clock division feature is.." hexmask.long.word 0x0 0.--10. 1. "IPFCP,Input Pin Filter Clock Prescaler setting" line.long 0x4 "IPFCPR1,SIUL2 input pin filter clock prescaler register 1" bitfld.long 0x4 11. "JEN,Enable jitter injection to increase periodic noise immunity." "0: The pseudo-random clock division feature is..,1: The pseudo-random clock division feature is.." hexmask.long.word 0x4 0.--10. 1. "IPFCP,Input Pin Filter Clock Prescaler setting" line.long 0x8 "IPFCPR2,SIUL2 input pin filter clock prescaler register 2" bitfld.long 0x8 11. "JEN,Enable jitter injection to increase periodic noise immunity." "0: The pseudo-random clock division feature is..,1: The pseudo-random clock division feature is.." hexmask.long.word 0x8 0.--10. 1. "IPFCP,Input Pin Filter Clock Prescaler setting" line.long 0xC "IPFCPR3,SIUL2 input pin filter clock prescaler register 3" bitfld.long 0xC 11. "JEN,Enable jitter injection to increase periodic noise immunity." "0: The pseudo-random clock division feature is..,1: The pseudo-random clock division feature is.." hexmask.long.word 0xC 0.--10. 1. "IPFCP,Input Pin Filter Clock Prescaler setting" group.long 0x240++0xFFF line.long 0x0 "MSCR_IO0,SIUL2 I/O pin multiplexed signal configuration register 0" bitfld.long 0x0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x0 0.--7. 1. "SSS,Source Signal Select" line.long 0x4 "MSCR_IO1,SIUL2 I/O pin multiplexed signal configuration register 1" bitfld.long 0x4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4 0.--7. 1. "SSS,Source Signal Select" line.long 0x8 "MSCR_IO2,SIUL2 I/O pin multiplexed signal configuration register 2" bitfld.long 0x8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x8 0.--7. 1. "SSS,Source Signal Select" line.long 0xC "MSCR_IO3,SIUL2 I/O pin multiplexed signal configuration register 3" bitfld.long 0xC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xC 0.--7. 1. "SSS,Source Signal Select" line.long 0x10 "MSCR_IO4,SIUL2 I/O pin multiplexed signal configuration register 4" bitfld.long 0x10 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x10 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x10 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x10 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x10 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x10 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x10 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x10 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x10 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x10 0.--7. 1. "SSS,Source Signal Select" line.long 0x14 "MSCR_IO5,SIUL2 I/O pin multiplexed signal configuration register 5" bitfld.long 0x14 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x14 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x14 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x14 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x14 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x14 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x14 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x14 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x14 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x14 0.--7. 1. "SSS,Source Signal Select" line.long 0x18 "MSCR_IO6,SIUL2 I/O pin multiplexed signal configuration register 6" bitfld.long 0x18 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x18 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x18 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x18 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x18 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x18 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x18 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x18 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x18 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x18 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x18 0.--7. 1. "SSS,Source Signal Select" line.long 0x1C "MSCR_IO7,SIUL2 I/O pin multiplexed signal configuration register 7" bitfld.long 0x1C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1C 0.--7. 1. "SSS,Source Signal Select" line.long 0x20 "MSCR_IO8,SIUL2 I/O pin multiplexed signal configuration register 8" bitfld.long 0x20 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x20 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x20 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x20 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x20 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x20 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x20 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x20 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x20 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x20 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x20 0.--7. 1. "SSS,Source Signal Select" line.long 0x24 "MSCR_IO9,SIUL2 I/O pin multiplexed signal configuration register 9" bitfld.long 0x24 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x24 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x24 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x24 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x24 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x24 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x24 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x24 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x24 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x24 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x24 0.--7. 1. "SSS,Source Signal Select" line.long 0x28 "MSCR_IO10,SIUL2 I/O pin multiplexed signal configuration register 10" bitfld.long 0x28 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x28 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x28 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x28 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x28 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x28 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x28 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x28 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x28 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x28 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x28 0.--7. 1. "SSS,Source Signal Select" line.long 0x2C "MSCR_IO11,SIUL2 I/O pin multiplexed signal configuration register 11" bitfld.long 0x2C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2C 0.--7. 1. "SSS,Source Signal Select" line.long 0x30 "MSCR_IO12,SIUL2 I/O pin multiplexed signal configuration register 12" bitfld.long 0x30 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x30 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x30 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x30 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x30 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x30 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x30 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x30 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x30 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x30 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x30 0.--7. 1. "SSS,Source Signal Select" line.long 0x34 "MSCR_IO13,SIUL2 I/O pin multiplexed signal configuration register 13" bitfld.long 0x34 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x34 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x34 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x34 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x34 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x34 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x34 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x34 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x34 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x34 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x34 0.--7. 1. "SSS,Source Signal Select" line.long 0x38 "MSCR_IO14,SIUL2 I/O pin multiplexed signal configuration register 14" bitfld.long 0x38 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x38 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x38 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x38 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x38 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x38 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x38 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x38 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x38 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x38 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x38 0.--7. 1. "SSS,Source Signal Select" line.long 0x3C "MSCR_IO15,SIUL2 I/O pin multiplexed signal configuration register 15" bitfld.long 0x3C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3C 0.--7. 1. "SSS,Source Signal Select" line.long 0x40 "MSCR_IO16,SIUL2 I/O pin multiplexed signal configuration register 16" bitfld.long 0x40 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x40 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x40 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x40 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x40 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x40 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x40 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x40 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x40 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x40 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x40 0.--7. 1. "SSS,Source Signal Select" line.long 0x44 "MSCR_IO17,SIUL2 I/O pin multiplexed signal configuration register 17" bitfld.long 0x44 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x44 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x44 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x44 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x44 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x44 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x44 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x44 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x44 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x44 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x44 0.--7. 1. "SSS,Source Signal Select" line.long 0x48 "MSCR_IO18,SIUL2 I/O pin multiplexed signal configuration register 18" bitfld.long 0x48 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x48 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x48 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x48 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x48 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x48 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x48 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x48 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x48 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x48 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x48 0.--7. 1. "SSS,Source Signal Select" line.long 0x4C "MSCR_IO19,SIUL2 I/O pin multiplexed signal configuration register 19" bitfld.long 0x4C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4C 0.--7. 1. "SSS,Source Signal Select" line.long 0x50 "MSCR_IO20,SIUL2 I/O pin multiplexed signal configuration register 20" bitfld.long 0x50 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x50 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x50 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x50 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x50 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x50 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x50 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x50 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x50 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x50 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x50 0.--7. 1. "SSS,Source Signal Select" line.long 0x54 "MSCR_IO21,SIUL2 I/O pin multiplexed signal configuration register 21" bitfld.long 0x54 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x54 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x54 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x54 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x54 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x54 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x54 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x54 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x54 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x54 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x54 0.--7. 1. "SSS,Source Signal Select" line.long 0x58 "MSCR_IO22,SIUL2 I/O pin multiplexed signal configuration register 22" bitfld.long 0x58 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x58 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x58 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x58 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x58 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x58 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x58 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x58 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x58 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x58 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x58 0.--7. 1. "SSS,Source Signal Select" line.long 0x5C "MSCR_IO23,SIUL2 I/O pin multiplexed signal configuration register 23" bitfld.long 0x5C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5C 0.--7. 1. "SSS,Source Signal Select" line.long 0x60 "MSCR_IO24,SIUL2 I/O pin multiplexed signal configuration register 24" bitfld.long 0x60 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x60 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x60 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x60 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x60 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x60 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x60 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x60 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x60 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x60 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x60 0.--7. 1. "SSS,Source Signal Select" line.long 0x64 "MSCR_IO25,SIUL2 I/O pin multiplexed signal configuration register 25" bitfld.long 0x64 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x64 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x64 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x64 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x64 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x64 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x64 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x64 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x64 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x64 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x64 0.--7. 1. "SSS,Source Signal Select" line.long 0x68 "MSCR_IO26,SIUL2 I/O pin multiplexed signal configuration register 26" bitfld.long 0x68 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x68 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x68 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x68 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x68 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x68 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x68 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x68 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x68 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x68 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x68 0.--7. 1. "SSS,Source Signal Select" line.long 0x6C "MSCR_IO27,SIUL2 I/O pin multiplexed signal configuration register 27" bitfld.long 0x6C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6C 0.--7. 1. "SSS,Source Signal Select" line.long 0x70 "MSCR_IO28,SIUL2 I/O pin multiplexed signal configuration register 28" bitfld.long 0x70 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x70 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x70 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x70 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x70 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x70 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x70 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x70 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x70 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x70 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x70 0.--7. 1. "SSS,Source Signal Select" line.long 0x74 "MSCR_IO29,SIUL2 I/O pin multiplexed signal configuration register 29" bitfld.long 0x74 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x74 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x74 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x74 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x74 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x74 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x74 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x74 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x74 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x74 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x74 0.--7. 1. "SSS,Source Signal Select" line.long 0x78 "MSCR_IO30,SIUL2 I/O pin multiplexed signal configuration register 30" bitfld.long 0x78 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x78 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x78 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x78 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x78 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x78 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x78 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x78 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x78 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x78 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x78 0.--7. 1. "SSS,Source Signal Select" line.long 0x7C "MSCR_IO31,SIUL2 I/O pin multiplexed signal configuration register 31" bitfld.long 0x7C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7C 0.--7. 1. "SSS,Source Signal Select" line.long 0x80 "MSCR_IO32,SIUL2 I/O pin multiplexed signal configuration register 32" bitfld.long 0x80 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x80 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x80 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x80 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x80 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x80 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x80 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x80 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x80 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x80 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x80 0.--7. 1. "SSS,Source Signal Select" line.long 0x84 "MSCR_IO33,SIUL2 I/O pin multiplexed signal configuration register 33" bitfld.long 0x84 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x84 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x84 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x84 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x84 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x84 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x84 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x84 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x84 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x84 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x84 0.--7. 1. "SSS,Source Signal Select" line.long 0x88 "MSCR_IO34,SIUL2 I/O pin multiplexed signal configuration register 34" bitfld.long 0x88 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x88 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x88 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x88 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x88 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x88 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x88 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x88 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x88 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x88 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x88 0.--7. 1. "SSS,Source Signal Select" line.long 0x8C "MSCR_IO35,SIUL2 I/O pin multiplexed signal configuration register 35" bitfld.long 0x8C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x8C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x8C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x8C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x8C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x8C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x8C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x8C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x8C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x8C 0.--7. 1. "SSS,Source Signal Select" line.long 0x90 "MSCR_IO36,SIUL2 I/O pin multiplexed signal configuration register 36" bitfld.long 0x90 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x90 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x90 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x90 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x90 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x90 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x90 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x90 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x90 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x90 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x90 0.--7. 1. "SSS,Source Signal Select" line.long 0x94 "MSCR_IO37,SIUL2 I/O pin multiplexed signal configuration register 37" bitfld.long 0x94 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x94 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x94 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x94 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x94 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x94 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x94 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x94 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x94 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x94 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x94 0.--7. 1. "SSS,Source Signal Select" line.long 0x98 "MSCR_IO38,SIUL2 I/O pin multiplexed signal configuration register 38" bitfld.long 0x98 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x98 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x98 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x98 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x98 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x98 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x98 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x98 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x98 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x98 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x98 0.--7. 1. "SSS,Source Signal Select" line.long 0x9C "MSCR_IO39,SIUL2 I/O pin multiplexed signal configuration register 39" bitfld.long 0x9C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x9C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x9C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x9C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x9C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x9C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x9C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x9C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x9C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x9C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x9C 0.--7. 1. "SSS,Source Signal Select" line.long 0xA0 "MSCR_IO40,SIUL2 I/O pin multiplexed signal configuration register 40" bitfld.long 0xA0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xA0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xA0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xA0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xA0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xA0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xA0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xA0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xA0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xA0 0.--7. 1. "SSS,Source Signal Select" line.long 0xA4 "MSCR_IO41,SIUL2 I/O pin multiplexed signal configuration register 41" bitfld.long 0xA4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xA4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xA4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xA4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xA4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xA4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xA4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xA4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xA4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xA4 0.--7. 1. "SSS,Source Signal Select" line.long 0xA8 "MSCR_IO42,SIUL2 I/O pin multiplexed signal configuration register 42" bitfld.long 0xA8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xA8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xA8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xA8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xA8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xA8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xA8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xA8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xA8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xA8 0.--7. 1. "SSS,Source Signal Select" line.long 0xAC "MSCR_IO43,SIUL2 I/O pin multiplexed signal configuration register 43" bitfld.long 0xAC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xAC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xAC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xAC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xAC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xAC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xAC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xAC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xAC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xAC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xAC 0.--7. 1. "SSS,Source Signal Select" line.long 0xB0 "MSCR_IO44,SIUL2 I/O pin multiplexed signal configuration register 44" bitfld.long 0xB0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xB0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xB0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xB0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xB0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xB0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xB0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xB0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xB0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xB0 0.--7. 1. "SSS,Source Signal Select" line.long 0xB4 "MSCR_IO45,SIUL2 I/O pin multiplexed signal configuration register 45" bitfld.long 0xB4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xB4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xB4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xB4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xB4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xB4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xB4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xB4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xB4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xB4 0.--7. 1. "SSS,Source Signal Select" line.long 0xB8 "MSCR_IO46,SIUL2 I/O pin multiplexed signal configuration register 46" bitfld.long 0xB8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xB8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xB8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xB8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xB8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xB8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xB8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xB8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xB8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xB8 0.--7. 1. "SSS,Source Signal Select" line.long 0xBC "MSCR_IO47,SIUL2 I/O pin multiplexed signal configuration register 47" bitfld.long 0xBC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xBC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xBC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xBC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xBC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xBC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xBC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xBC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xBC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xBC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xBC 0.--7. 1. "SSS,Source Signal Select" line.long 0xC0 "MSCR_IO48,SIUL2 I/O pin multiplexed signal configuration register 48" bitfld.long 0xC0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xC0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xC0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xC0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xC0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xC0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xC0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xC0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xC0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xC0 0.--7. 1. "SSS,Source Signal Select" line.long 0xC4 "MSCR_IO49,SIUL2 I/O pin multiplexed signal configuration register 49" bitfld.long 0xC4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xC4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xC4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xC4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xC4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xC4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xC4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xC4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xC4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xC4 0.--7. 1. "SSS,Source Signal Select" line.long 0xC8 "MSCR_IO50,SIUL2 I/O pin multiplexed signal configuration register 50" bitfld.long 0xC8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xC8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xC8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xC8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xC8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xC8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xC8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xC8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xC8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xC8 0.--7. 1. "SSS,Source Signal Select" line.long 0xCC "MSCR_IO51,SIUL2 I/O pin multiplexed signal configuration register 51" bitfld.long 0xCC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xCC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xCC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xCC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xCC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xCC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xCC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xCC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xCC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xCC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xCC 0.--7. 1. "SSS,Source Signal Select" line.long 0xD0 "MSCR_IO52,SIUL2 I/O pin multiplexed signal configuration register 52" bitfld.long 0xD0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xD0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xD0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xD0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xD0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xD0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xD0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xD0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xD0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xD0 0.--7. 1. "SSS,Source Signal Select" line.long 0xD4 "MSCR_IO53,SIUL2 I/O pin multiplexed signal configuration register 53" bitfld.long 0xD4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xD4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xD4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xD4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xD4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xD4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xD4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xD4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xD4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xD4 0.--7. 1. "SSS,Source Signal Select" line.long 0xD8 "MSCR_IO54,SIUL2 I/O pin multiplexed signal configuration register 54" bitfld.long 0xD8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xD8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xD8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xD8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xD8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xD8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xD8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xD8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xD8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xD8 0.--7. 1. "SSS,Source Signal Select" line.long 0xDC "MSCR_IO55,SIUL2 I/O pin multiplexed signal configuration register 55" bitfld.long 0xDC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xDC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xDC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xDC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xDC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xDC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xDC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xDC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xDC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xDC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xDC 0.--7. 1. "SSS,Source Signal Select" line.long 0xE0 "MSCR_IO56,SIUL2 I/O pin multiplexed signal configuration register 56" bitfld.long 0xE0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xE0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xE0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xE0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xE0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xE0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xE0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xE0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xE0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xE0 0.--7. 1. "SSS,Source Signal Select" line.long 0xE4 "MSCR_IO57,SIUL2 I/O pin multiplexed signal configuration register 57" bitfld.long 0xE4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xE4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xE4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xE4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xE4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xE4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xE4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xE4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xE4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xE4 0.--7. 1. "SSS,Source Signal Select" line.long 0xE8 "MSCR_IO58,SIUL2 I/O pin multiplexed signal configuration register 58" bitfld.long 0xE8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xE8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xE8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xE8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xE8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xE8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xE8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xE8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xE8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xE8 0.--7. 1. "SSS,Source Signal Select" line.long 0xEC "MSCR_IO59,SIUL2 I/O pin multiplexed signal configuration register 59" bitfld.long 0xEC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xEC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xEC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xEC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xEC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xEC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xEC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xEC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xEC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xEC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xEC 0.--7. 1. "SSS,Source Signal Select" line.long 0xF0 "MSCR_IO60,SIUL2 I/O pin multiplexed signal configuration register 60" bitfld.long 0xF0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xF0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xF0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xF0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xF0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xF0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xF0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xF0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xF0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xF0 0.--7. 1. "SSS,Source Signal Select" line.long 0xF4 "MSCR_IO61,SIUL2 I/O pin multiplexed signal configuration register 61" bitfld.long 0xF4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xF4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xF4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xF4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xF4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xF4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xF4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xF4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xF4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xF4 0.--7. 1. "SSS,Source Signal Select" line.long 0xF8 "MSCR_IO62,SIUL2 I/O pin multiplexed signal configuration register 62" bitfld.long 0xF8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xF8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xF8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xF8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xF8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xF8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xF8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xF8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xF8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xF8 0.--7. 1. "SSS,Source Signal Select" line.long 0xFC "MSCR_IO63,SIUL2 I/O pin multiplexed signal configuration register 63" bitfld.long 0xFC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0xFC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0xFC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0xFC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0xFC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xFC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xFC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0xFC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0xFC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0xFC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0xFC 0.--7. 1. "SSS,Source Signal Select" line.long 0x100 "MSCR_IO64,SIUL2 I/O pin multiplexed signal configuration register 64" bitfld.long 0x100 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x100 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x100 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x100 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x100 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x100 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x100 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x100 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x100 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x100 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x100 0.--7. 1. "SSS,Source Signal Select" line.long 0x104 "MSCR_IO65,SIUL2 I/O pin multiplexed signal configuration register 65" bitfld.long 0x104 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x104 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x104 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x104 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x104 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x104 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x104 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x104 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x104 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x104 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x104 0.--7. 1. "SSS,Source Signal Select" line.long 0x108 "MSCR_IO66,SIUL2 I/O pin multiplexed signal configuration register 66" bitfld.long 0x108 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x108 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x108 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x108 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x108 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x108 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x108 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x108 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x108 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x108 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x108 0.--7. 1. "SSS,Source Signal Select" line.long 0x10C "MSCR_IO67,SIUL2 I/O pin multiplexed signal configuration register 67" bitfld.long 0x10C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x10C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x10C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x10C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x10C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x10C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x10C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x10C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x10C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x10C 0.--7. 1. "SSS,Source Signal Select" line.long 0x110 "MSCR_IO68,SIUL2 I/O pin multiplexed signal configuration register 68" bitfld.long 0x110 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x110 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x110 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x110 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x110 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x110 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x110 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x110 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x110 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x110 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x110 0.--7. 1. "SSS,Source Signal Select" line.long 0x114 "MSCR_IO69,SIUL2 I/O pin multiplexed signal configuration register 69" bitfld.long 0x114 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x114 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x114 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x114 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x114 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x114 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x114 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x114 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x114 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x114 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x114 0.--7. 1. "SSS,Source Signal Select" line.long 0x118 "MSCR_IO70,SIUL2 I/O pin multiplexed signal configuration register 70" bitfld.long 0x118 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x118 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x118 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x118 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x118 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x118 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x118 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x118 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x118 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x118 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x118 0.--7. 1. "SSS,Source Signal Select" line.long 0x11C "MSCR_IO71,SIUL2 I/O pin multiplexed signal configuration register 71" bitfld.long 0x11C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x11C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x11C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x11C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x11C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x11C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x11C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x11C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x11C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x11C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x11C 0.--7. 1. "SSS,Source Signal Select" line.long 0x120 "MSCR_IO72,SIUL2 I/O pin multiplexed signal configuration register 72" bitfld.long 0x120 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x120 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x120 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x120 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x120 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x120 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x120 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x120 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x120 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x120 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x120 0.--7. 1. "SSS,Source Signal Select" line.long 0x124 "MSCR_IO73,SIUL2 I/O pin multiplexed signal configuration register 73" bitfld.long 0x124 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x124 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x124 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x124 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x124 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x124 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x124 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x124 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x124 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x124 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x124 0.--7. 1. "SSS,Source Signal Select" line.long 0x128 "MSCR_IO74,SIUL2 I/O pin multiplexed signal configuration register 74" bitfld.long 0x128 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x128 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x128 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x128 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x128 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x128 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x128 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x128 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x128 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x128 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x128 0.--7. 1. "SSS,Source Signal Select" line.long 0x12C "MSCR_IO75,SIUL2 I/O pin multiplexed signal configuration register 75" bitfld.long 0x12C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x12C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x12C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x12C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x12C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x12C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x12C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x12C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x12C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x12C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x12C 0.--7. 1. "SSS,Source Signal Select" line.long 0x130 "MSCR_IO76,SIUL2 I/O pin multiplexed signal configuration register 76" bitfld.long 0x130 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x130 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x130 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x130 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x130 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x130 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x130 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x130 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x130 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x130 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x130 0.--7. 1. "SSS,Source Signal Select" line.long 0x134 "MSCR_IO77,SIUL2 I/O pin multiplexed signal configuration register 77" bitfld.long 0x134 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x134 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x134 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x134 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x134 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x134 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x134 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x134 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x134 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x134 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x134 0.--7. 1. "SSS,Source Signal Select" line.long 0x138 "MSCR_IO78,SIUL2 I/O pin multiplexed signal configuration register 78" bitfld.long 0x138 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x138 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x138 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x138 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x138 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x138 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x138 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x138 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x138 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x138 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x138 0.--7. 1. "SSS,Source Signal Select" line.long 0x13C "MSCR_IO79,SIUL2 I/O pin multiplexed signal configuration register 79" bitfld.long 0x13C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x13C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x13C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x13C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x13C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x13C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x13C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x13C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x13C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x13C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x13C 0.--7. 1. "SSS,Source Signal Select" line.long 0x140 "MSCR_IO80,SIUL2 I/O pin multiplexed signal configuration register 80" bitfld.long 0x140 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x140 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x140 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x140 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x140 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x140 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x140 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x140 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x140 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x140 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x140 0.--7. 1. "SSS,Source Signal Select" line.long 0x144 "MSCR_IO81,SIUL2 I/O pin multiplexed signal configuration register 81" bitfld.long 0x144 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x144 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x144 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x144 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x144 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x144 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x144 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x144 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x144 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x144 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x144 0.--7. 1. "SSS,Source Signal Select" line.long 0x148 "MSCR_IO82,SIUL2 I/O pin multiplexed signal configuration register 82" bitfld.long 0x148 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x148 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x148 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x148 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x148 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x148 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x148 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x148 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x148 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x148 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x148 0.--7. 1. "SSS,Source Signal Select" line.long 0x14C "MSCR_IO83,SIUL2 I/O pin multiplexed signal configuration register 83" bitfld.long 0x14C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x14C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x14C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x14C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x14C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x14C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x14C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x14C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x14C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x14C 0.--7. 1. "SSS,Source Signal Select" line.long 0x150 "MSCR_IO84,SIUL2 I/O pin multiplexed signal configuration register 84" bitfld.long 0x150 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x150 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x150 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x150 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x150 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x150 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x150 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x150 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x150 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x150 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x150 0.--7. 1. "SSS,Source Signal Select" line.long 0x154 "MSCR_IO85,SIUL2 I/O pin multiplexed signal configuration register 85" bitfld.long 0x154 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x154 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x154 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x154 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x154 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x154 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x154 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x154 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x154 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x154 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x154 0.--7. 1. "SSS,Source Signal Select" line.long 0x158 "MSCR_IO86,SIUL2 I/O pin multiplexed signal configuration register 86" bitfld.long 0x158 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x158 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x158 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x158 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x158 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x158 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x158 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x158 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x158 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x158 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x158 0.--7. 1. "SSS,Source Signal Select" line.long 0x15C "MSCR_IO87,SIUL2 I/O pin multiplexed signal configuration register 87" bitfld.long 0x15C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x15C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x15C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x15C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x15C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x15C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x15C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x15C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x15C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x15C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x15C 0.--7. 1. "SSS,Source Signal Select" line.long 0x160 "MSCR_IO88,SIUL2 I/O pin multiplexed signal configuration register 88" bitfld.long 0x160 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x160 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x160 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x160 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x160 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x160 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x160 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x160 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x160 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x160 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x160 0.--7. 1. "SSS,Source Signal Select" line.long 0x164 "MSCR_IO89,SIUL2 I/O pin multiplexed signal configuration register 89" bitfld.long 0x164 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x164 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x164 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x164 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x164 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x164 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x164 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x164 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x164 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x164 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x164 0.--7. 1. "SSS,Source Signal Select" line.long 0x168 "MSCR_IO90,SIUL2 I/O pin multiplexed signal configuration register 90" bitfld.long 0x168 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x168 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x168 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x168 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x168 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x168 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x168 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x168 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x168 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x168 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x168 0.--7. 1. "SSS,Source Signal Select" line.long 0x16C "MSCR_IO91,SIUL2 I/O pin multiplexed signal configuration register 91" bitfld.long 0x16C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x16C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x16C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x16C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x16C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x16C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x16C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x16C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x16C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x16C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x16C 0.--7. 1. "SSS,Source Signal Select" line.long 0x170 "MSCR_IO92,SIUL2 I/O pin multiplexed signal configuration register 92" bitfld.long 0x170 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x170 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x170 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x170 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x170 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x170 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x170 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x170 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x170 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x170 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x170 0.--7. 1. "SSS,Source Signal Select" line.long 0x174 "MSCR_IO93,SIUL2 I/O pin multiplexed signal configuration register 93" bitfld.long 0x174 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x174 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x174 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x174 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x174 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x174 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x174 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x174 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x174 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x174 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x174 0.--7. 1. "SSS,Source Signal Select" line.long 0x178 "MSCR_IO94,SIUL2 I/O pin multiplexed signal configuration register 94" bitfld.long 0x178 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x178 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x178 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x178 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x178 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x178 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x178 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x178 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x178 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x178 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x178 0.--7. 1. "SSS,Source Signal Select" line.long 0x17C "MSCR_IO95,SIUL2 I/O pin multiplexed signal configuration register 95" bitfld.long 0x17C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x17C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x17C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x17C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x17C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x17C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x17C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x17C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x17C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x17C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x17C 0.--7. 1. "SSS,Source Signal Select" line.long 0x180 "MSCR_IO96,SIUL2 I/O pin multiplexed signal configuration register 96" bitfld.long 0x180 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x180 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x180 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x180 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x180 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x180 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x180 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x180 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x180 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x180 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x180 0.--7. 1. "SSS,Source Signal Select" line.long 0x184 "MSCR_IO97,SIUL2 I/O pin multiplexed signal configuration register 97" bitfld.long 0x184 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x184 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x184 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x184 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x184 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x184 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x184 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x184 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x184 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x184 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x184 0.--7. 1. "SSS,Source Signal Select" line.long 0x188 "MSCR_IO98,SIUL2 I/O pin multiplexed signal configuration register 98" bitfld.long 0x188 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x188 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x188 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x188 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x188 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x188 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x188 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x188 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x188 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x188 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x188 0.--7. 1. "SSS,Source Signal Select" line.long 0x18C "MSCR_IO99,SIUL2 I/O pin multiplexed signal configuration register 99" bitfld.long 0x18C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x18C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x18C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x18C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x18C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x18C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x18C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x18C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x18C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x18C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x18C 0.--7. 1. "SSS,Source Signal Select" line.long 0x190 "MSCR_IO100,SIUL2 I/O pin multiplexed signal configuration register 100" bitfld.long 0x190 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x190 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x190 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x190 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x190 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x190 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x190 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x190 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x190 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x190 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x190 0.--7. 1. "SSS,Source Signal Select" line.long 0x194 "MSCR_IO101,SIUL2 I/O pin multiplexed signal configuration register 101" bitfld.long 0x194 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x194 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x194 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x194 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x194 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x194 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x194 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x194 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x194 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x194 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x194 0.--7. 1. "SSS,Source Signal Select" line.long 0x198 "MSCR_IO102,SIUL2 I/O pin multiplexed signal configuration register 102" bitfld.long 0x198 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x198 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x198 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x198 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x198 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x198 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x198 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x198 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x198 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x198 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x198 0.--7. 1. "SSS,Source Signal Select" line.long 0x19C "MSCR_IO103,SIUL2 I/O pin multiplexed signal configuration register 103" bitfld.long 0x19C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x19C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x19C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x19C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x19C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x19C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x19C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x19C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x19C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x19C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x19C 0.--7. 1. "SSS,Source Signal Select" line.long 0x1A0 "MSCR_IO104,SIUL2 I/O pin multiplexed signal configuration register 104" bitfld.long 0x1A0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1A0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1A0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1A0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1A0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1A0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1A0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1A0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1A0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1A0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1A0 0.--7. 1. "SSS,Source Signal Select" line.long 0x1A4 "MSCR_IO105,SIUL2 I/O pin multiplexed signal configuration register 105" bitfld.long 0x1A4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1A4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1A4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1A4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1A4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1A4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1A4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1A4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1A4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1A4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1A4 0.--7. 1. "SSS,Source Signal Select" line.long 0x1A8 "MSCR_IO106,SIUL2 I/O pin multiplexed signal configuration register 106" bitfld.long 0x1A8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1A8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1A8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1A8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1A8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1A8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1A8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1A8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1A8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1A8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1A8 0.--7. 1. "SSS,Source Signal Select" line.long 0x1AC "MSCR_IO107,SIUL2 I/O pin multiplexed signal configuration register 107" bitfld.long 0x1AC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1AC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1AC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1AC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1AC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1AC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1AC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1AC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1AC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1AC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1AC 0.--7. 1. "SSS,Source Signal Select" line.long 0x1B0 "MSCR_IO108,SIUL2 I/O pin multiplexed signal configuration register 108" bitfld.long 0x1B0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1B0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1B0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1B0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1B0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1B0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1B0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1B0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1B0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1B0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1B0 0.--7. 1. "SSS,Source Signal Select" line.long 0x1B4 "MSCR_IO109,SIUL2 I/O pin multiplexed signal configuration register 109" bitfld.long 0x1B4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1B4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1B4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1B4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1B4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1B4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1B4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1B4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1B4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1B4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1B4 0.--7. 1. "SSS,Source Signal Select" line.long 0x1B8 "MSCR_IO110,SIUL2 I/O pin multiplexed signal configuration register 110" bitfld.long 0x1B8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1B8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1B8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1B8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1B8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1B8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1B8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1B8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1B8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1B8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1B8 0.--7. 1. "SSS,Source Signal Select" line.long 0x1BC "MSCR_IO111,SIUL2 I/O pin multiplexed signal configuration register 111" bitfld.long 0x1BC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1BC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1BC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1BC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1BC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1BC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1BC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1BC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1BC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1BC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1BC 0.--7. 1. "SSS,Source Signal Select" line.long 0x1C0 "MSCR_IO112,SIUL2 I/O pin multiplexed signal configuration register 112" bitfld.long 0x1C0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1C0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1C0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1C0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1C0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1C0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1C0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1C0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1C0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1C0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1C0 0.--7. 1. "SSS,Source Signal Select" line.long 0x1C4 "MSCR_IO113,SIUL2 I/O pin multiplexed signal configuration register 113" bitfld.long 0x1C4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1C4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1C4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1C4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1C4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1C4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1C4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1C4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1C4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1C4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1C4 0.--7. 1. "SSS,Source Signal Select" line.long 0x1C8 "MSCR_IO114,SIUL2 I/O pin multiplexed signal configuration register 114" bitfld.long 0x1C8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1C8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1C8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1C8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1C8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1C8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1C8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1C8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1C8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1C8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1C8 0.--7. 1. "SSS,Source Signal Select" line.long 0x1CC "MSCR_IO115,SIUL2 I/O pin multiplexed signal configuration register 115" bitfld.long 0x1CC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1CC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1CC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1CC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1CC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1CC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1CC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1CC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1CC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1CC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1CC 0.--7. 1. "SSS,Source Signal Select" line.long 0x1D0 "MSCR_IO116,SIUL2 I/O pin multiplexed signal configuration register 116" bitfld.long 0x1D0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1D0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1D0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1D0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1D0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1D0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1D0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1D0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1D0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1D0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1D0 0.--7. 1. "SSS,Source Signal Select" line.long 0x1D4 "MSCR_IO117,SIUL2 I/O pin multiplexed signal configuration register 117" bitfld.long 0x1D4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1D4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1D4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1D4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1D4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1D4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1D4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1D4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1D4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1D4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1D4 0.--7. 1. "SSS,Source Signal Select" line.long 0x1D8 "MSCR_IO118,SIUL2 I/O pin multiplexed signal configuration register 118" bitfld.long 0x1D8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1D8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1D8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1D8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1D8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1D8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1D8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1D8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1D8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1D8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1D8 0.--7. 1. "SSS,Source Signal Select" line.long 0x1DC "MSCR_IO119,SIUL2 I/O pin multiplexed signal configuration register 119" bitfld.long 0x1DC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1DC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1DC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1DC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1DC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1DC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1DC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1DC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1DC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1DC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1DC 0.--7. 1. "SSS,Source Signal Select" line.long 0x1E0 "MSCR_IO120,SIUL2 I/O pin multiplexed signal configuration register 120" bitfld.long 0x1E0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1E0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1E0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1E0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1E0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1E0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1E0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1E0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1E0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1E0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1E0 0.--7. 1. "SSS,Source Signal Select" line.long 0x1E4 "MSCR_IO121,SIUL2 I/O pin multiplexed signal configuration register 121" bitfld.long 0x1E4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1E4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1E4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1E4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1E4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1E4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1E4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1E4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1E4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1E4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1E4 0.--7. 1. "SSS,Source Signal Select" line.long 0x1E8 "MSCR_IO122,SIUL2 I/O pin multiplexed signal configuration register 122" bitfld.long 0x1E8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1E8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1E8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1E8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1E8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1E8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1E8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1E8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1E8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1E8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1E8 0.--7. 1. "SSS,Source Signal Select" line.long 0x1EC "MSCR_IO123,SIUL2 I/O pin multiplexed signal configuration register 123" bitfld.long 0x1EC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1EC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1EC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1EC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1EC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1EC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1EC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1EC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1EC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1EC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1EC 0.--7. 1. "SSS,Source Signal Select" line.long 0x1F0 "MSCR_IO124,SIUL2 I/O pin multiplexed signal configuration register 124" bitfld.long 0x1F0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1F0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1F0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1F0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1F0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1F0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1F0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1F0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1F0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1F0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1F0 0.--7. 1. "SSS,Source Signal Select" line.long 0x1F4 "MSCR_IO125,SIUL2 I/O pin multiplexed signal configuration register 125" bitfld.long 0x1F4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1F4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1F4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1F4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1F4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1F4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1F4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1F4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1F4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1F4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1F4 0.--7. 1. "SSS,Source Signal Select" line.long 0x1F8 "MSCR_IO126,SIUL2 I/O pin multiplexed signal configuration register 126" bitfld.long 0x1F8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1F8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1F8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1F8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1F8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1F8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1F8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1F8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1F8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1F8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1F8 0.--7. 1. "SSS,Source Signal Select" line.long 0x1FC "MSCR_IO127,SIUL2 I/O pin multiplexed signal configuration register 127" bitfld.long 0x1FC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x1FC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x1FC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x1FC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x1FC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1FC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1FC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x1FC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x1FC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x1FC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x1FC 0.--7. 1. "SSS,Source Signal Select" line.long 0x200 "MSCR_IO128,SIUL2 I/O pin multiplexed signal configuration register 128" bitfld.long 0x200 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x200 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x200 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x200 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x200 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x200 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x200 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x200 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x200 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x200 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x200 0.--7. 1. "SSS,Source Signal Select" line.long 0x204 "MSCR_IO129,SIUL2 I/O pin multiplexed signal configuration register 129" bitfld.long 0x204 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x204 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x204 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x204 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x204 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x204 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x204 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x204 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x204 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x204 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x204 0.--7. 1. "SSS,Source Signal Select" line.long 0x208 "MSCR_IO130,SIUL2 I/O pin multiplexed signal configuration register 130" bitfld.long 0x208 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x208 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x208 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x208 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x208 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x208 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x208 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x208 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x208 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x208 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x208 0.--7. 1. "SSS,Source Signal Select" line.long 0x20C "MSCR_IO131,SIUL2 I/O pin multiplexed signal configuration register 131" bitfld.long 0x20C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x20C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x20C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x20C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x20C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x20C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x20C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x20C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x20C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x20C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x20C 0.--7. 1. "SSS,Source Signal Select" line.long 0x210 "MSCR_IO132,SIUL2 I/O pin multiplexed signal configuration register 132" bitfld.long 0x210 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x210 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x210 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x210 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x210 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x210 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x210 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x210 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x210 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x210 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x210 0.--7. 1. "SSS,Source Signal Select" line.long 0x214 "MSCR_IO133,SIUL2 I/O pin multiplexed signal configuration register 133" bitfld.long 0x214 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x214 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x214 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x214 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x214 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x214 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x214 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x214 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x214 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x214 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x214 0.--7. 1. "SSS,Source Signal Select" line.long 0x218 "MSCR_IO134,SIUL2 I/O pin multiplexed signal configuration register 134" bitfld.long 0x218 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x218 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x218 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x218 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x218 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x218 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x218 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x218 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x218 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x218 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x218 0.--7. 1. "SSS,Source Signal Select" line.long 0x21C "MSCR_IO135,SIUL2 I/O pin multiplexed signal configuration register 135" bitfld.long 0x21C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x21C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x21C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x21C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x21C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x21C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x21C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x21C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x21C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x21C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x21C 0.--7. 1. "SSS,Source Signal Select" line.long 0x220 "MSCR_IO136,SIUL2 I/O pin multiplexed signal configuration register 136" bitfld.long 0x220 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x220 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x220 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x220 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x220 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x220 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x220 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x220 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x220 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x220 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x220 0.--7. 1. "SSS,Source Signal Select" line.long 0x224 "MSCR_IO137,SIUL2 I/O pin multiplexed signal configuration register 137" bitfld.long 0x224 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x224 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x224 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x224 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x224 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x224 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x224 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x224 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x224 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x224 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x224 0.--7. 1. "SSS,Source Signal Select" line.long 0x228 "MSCR_IO138,SIUL2 I/O pin multiplexed signal configuration register 138" bitfld.long 0x228 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x228 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x228 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x228 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x228 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x228 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x228 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x228 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x228 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x228 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x228 0.--7. 1. "SSS,Source Signal Select" line.long 0x22C "MSCR_IO139,SIUL2 I/O pin multiplexed signal configuration register 139" bitfld.long 0x22C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x22C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x22C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x22C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x22C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x22C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x22C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x22C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x22C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x22C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x22C 0.--7. 1. "SSS,Source Signal Select" line.long 0x230 "MSCR_IO140,SIUL2 I/O pin multiplexed signal configuration register 140" bitfld.long 0x230 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x230 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x230 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x230 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x230 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x230 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x230 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x230 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x230 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x230 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x230 0.--7. 1. "SSS,Source Signal Select" line.long 0x234 "MSCR_IO141,SIUL2 I/O pin multiplexed signal configuration register 141" bitfld.long 0x234 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x234 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x234 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x234 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x234 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x234 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x234 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x234 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x234 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x234 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x234 0.--7. 1. "SSS,Source Signal Select" line.long 0x238 "MSCR_IO142,SIUL2 I/O pin multiplexed signal configuration register 142" bitfld.long 0x238 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x238 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x238 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x238 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x238 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x238 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x238 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x238 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x238 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x238 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x238 0.--7. 1. "SSS,Source Signal Select" line.long 0x23C "MSCR_IO143,SIUL2 I/O pin multiplexed signal configuration register 143" bitfld.long 0x23C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x23C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x23C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x23C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x23C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x23C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x23C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x23C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x23C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x23C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x23C 0.--7. 1. "SSS,Source Signal Select" line.long 0x240 "MSCR_IO144,SIUL2 I/O pin multiplexed signal configuration register 144" bitfld.long 0x240 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x240 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x240 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x240 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x240 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x240 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x240 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x240 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x240 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x240 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x240 0.--7. 1. "SSS,Source Signal Select" line.long 0x244 "MSCR_IO145,SIUL2 I/O pin multiplexed signal configuration register 145" bitfld.long 0x244 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x244 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x244 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x244 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x244 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x244 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x244 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x244 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x244 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x244 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x244 0.--7. 1. "SSS,Source Signal Select" line.long 0x248 "MSCR_IO146,SIUL2 I/O pin multiplexed signal configuration register 146" bitfld.long 0x248 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x248 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x248 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x248 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x248 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x248 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x248 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x248 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x248 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x248 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x248 0.--7. 1. "SSS,Source Signal Select" line.long 0x24C "MSCR_IO147,SIUL2 I/O pin multiplexed signal configuration register 147" bitfld.long 0x24C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x24C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x24C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x24C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x24C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x24C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x24C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x24C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x24C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x24C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x24C 0.--7. 1. "SSS,Source Signal Select" line.long 0x250 "MSCR_IO148,SIUL2 I/O pin multiplexed signal configuration register 148" bitfld.long 0x250 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x250 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x250 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x250 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x250 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x250 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x250 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x250 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x250 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x250 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x250 0.--7. 1. "SSS,Source Signal Select" line.long 0x254 "MSCR_IO149,SIUL2 I/O pin multiplexed signal configuration register 149" bitfld.long 0x254 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x254 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x254 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x254 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x254 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x254 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x254 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x254 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x254 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x254 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x254 0.--7. 1. "SSS,Source Signal Select" line.long 0x258 "MSCR_IO150,SIUL2 I/O pin multiplexed signal configuration register 150" bitfld.long 0x258 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x258 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x258 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x258 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x258 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x258 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x258 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x258 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x258 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x258 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x258 0.--7. 1. "SSS,Source Signal Select" line.long 0x25C "MSCR_IO151,SIUL2 I/O pin multiplexed signal configuration register 151" bitfld.long 0x25C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x25C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x25C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x25C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x25C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x25C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x25C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x25C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x25C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x25C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x25C 0.--7. 1. "SSS,Source Signal Select" line.long 0x260 "MSCR_IO152,SIUL2 I/O pin multiplexed signal configuration register 152" bitfld.long 0x260 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x260 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x260 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x260 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x260 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x260 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x260 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x260 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x260 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x260 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x260 0.--7. 1. "SSS,Source Signal Select" line.long 0x264 "MSCR_IO153,SIUL2 I/O pin multiplexed signal configuration register 153" bitfld.long 0x264 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x264 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x264 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x264 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x264 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x264 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x264 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x264 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x264 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x264 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x264 0.--7. 1. "SSS,Source Signal Select" line.long 0x268 "MSCR_IO154,SIUL2 I/O pin multiplexed signal configuration register 154" bitfld.long 0x268 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x268 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x268 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x268 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x268 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x268 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x268 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x268 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x268 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x268 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x268 0.--7. 1. "SSS,Source Signal Select" line.long 0x26C "MSCR_IO155,SIUL2 I/O pin multiplexed signal configuration register 155" bitfld.long 0x26C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x26C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x26C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x26C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x26C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x26C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x26C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x26C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x26C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x26C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x26C 0.--7. 1. "SSS,Source Signal Select" line.long 0x270 "MSCR_IO156,SIUL2 I/O pin multiplexed signal configuration register 156" bitfld.long 0x270 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x270 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x270 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x270 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x270 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x270 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x270 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x270 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x270 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x270 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x270 0.--7. 1. "SSS,Source Signal Select" line.long 0x274 "MSCR_IO157,SIUL2 I/O pin multiplexed signal configuration register 157" bitfld.long 0x274 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x274 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x274 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x274 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x274 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x274 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x274 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x274 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x274 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x274 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x274 0.--7. 1. "SSS,Source Signal Select" line.long 0x278 "MSCR_IO158,SIUL2 I/O pin multiplexed signal configuration register 158" bitfld.long 0x278 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x278 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x278 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x278 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x278 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x278 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x278 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x278 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x278 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x278 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x278 0.--7. 1. "SSS,Source Signal Select" line.long 0x27C "MSCR_IO159,SIUL2 I/O pin multiplexed signal configuration register 159" bitfld.long 0x27C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x27C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x27C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x27C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x27C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x27C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x27C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x27C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x27C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x27C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x27C 0.--7. 1. "SSS,Source Signal Select" line.long 0x280 "MSCR_IO160,SIUL2 I/O pin multiplexed signal configuration register 160" bitfld.long 0x280 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x280 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x280 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x280 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x280 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x280 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x280 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x280 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x280 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x280 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x280 0.--7. 1. "SSS,Source Signal Select" line.long 0x284 "MSCR_IO161,SIUL2 I/O pin multiplexed signal configuration register 161" bitfld.long 0x284 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x284 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x284 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x284 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x284 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x284 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x284 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x284 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x284 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x284 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x284 0.--7. 1. "SSS,Source Signal Select" line.long 0x288 "MSCR_IO162,SIUL2 I/O pin multiplexed signal configuration register 162" bitfld.long 0x288 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x288 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x288 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x288 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x288 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x288 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x288 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x288 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x288 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x288 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x288 0.--7. 1. "SSS,Source Signal Select" line.long 0x28C "MSCR_IO163,SIUL2 I/O pin multiplexed signal configuration register 163" bitfld.long 0x28C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x28C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x28C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x28C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x28C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x28C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x28C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x28C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x28C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x28C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x28C 0.--7. 1. "SSS,Source Signal Select" line.long 0x290 "MSCR_IO164,SIUL2 I/O pin multiplexed signal configuration register 164" bitfld.long 0x290 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x290 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x290 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x290 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x290 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x290 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x290 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x290 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x290 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x290 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x290 0.--7. 1. "SSS,Source Signal Select" line.long 0x294 "MSCR_IO165,SIUL2 I/O pin multiplexed signal configuration register 165" bitfld.long 0x294 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x294 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x294 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x294 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x294 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x294 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x294 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x294 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x294 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x294 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x294 0.--7. 1. "SSS,Source Signal Select" line.long 0x298 "MSCR_IO166,SIUL2 I/O pin multiplexed signal configuration register 166" bitfld.long 0x298 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x298 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x298 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x298 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x298 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x298 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x298 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x298 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x298 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x298 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x298 0.--7. 1. "SSS,Source Signal Select" line.long 0x29C "MSCR_IO167,SIUL2 I/O pin multiplexed signal configuration register 167" bitfld.long 0x29C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x29C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x29C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x29C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x29C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x29C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x29C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x29C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x29C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x29C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x29C 0.--7. 1. "SSS,Source Signal Select" line.long 0x2A0 "MSCR_IO168,SIUL2 I/O pin multiplexed signal configuration register 168" bitfld.long 0x2A0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2A0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2A0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2A0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2A0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2A0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2A0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2A0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2A0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2A0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2A0 0.--7. 1. "SSS,Source Signal Select" line.long 0x2A4 "MSCR_IO169,SIUL2 I/O pin multiplexed signal configuration register 169" bitfld.long 0x2A4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2A4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2A4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2A4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2A4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2A4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2A4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2A4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2A4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2A4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2A4 0.--7. 1. "SSS,Source Signal Select" line.long 0x2A8 "MSCR_IO170,SIUL2 I/O pin multiplexed signal configuration register 170" bitfld.long 0x2A8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2A8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2A8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2A8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2A8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2A8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2A8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2A8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2A8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2A8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2A8 0.--7. 1. "SSS,Source Signal Select" line.long 0x2AC "MSCR_IO171,SIUL2 I/O pin multiplexed signal configuration register 171" bitfld.long 0x2AC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2AC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2AC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2AC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2AC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2AC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2AC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2AC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2AC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2AC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2AC 0.--7. 1. "SSS,Source Signal Select" line.long 0x2B0 "MSCR_IO172,SIUL2 I/O pin multiplexed signal configuration register 172" bitfld.long 0x2B0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2B0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2B0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2B0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2B0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2B0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2B0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2B0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2B0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2B0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2B0 0.--7. 1. "SSS,Source Signal Select" line.long 0x2B4 "MSCR_IO173,SIUL2 I/O pin multiplexed signal configuration register 173" bitfld.long 0x2B4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2B4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2B4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2B4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2B4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2B4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2B4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2B4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2B4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2B4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2B4 0.--7. 1. "SSS,Source Signal Select" line.long 0x2B8 "MSCR_IO174,SIUL2 I/O pin multiplexed signal configuration register 174" bitfld.long 0x2B8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2B8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2B8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2B8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2B8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2B8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2B8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2B8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2B8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2B8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2B8 0.--7. 1. "SSS,Source Signal Select" line.long 0x2BC "MSCR_IO175,SIUL2 I/O pin multiplexed signal configuration register 175" bitfld.long 0x2BC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2BC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2BC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2BC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2BC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2BC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2BC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2BC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2BC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2BC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2BC 0.--7. 1. "SSS,Source Signal Select" line.long 0x2C0 "MSCR_IO176,SIUL2 I/O pin multiplexed signal configuration register 176" bitfld.long 0x2C0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2C0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2C0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2C0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2C0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2C0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2C0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2C0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2C0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2C0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2C0 0.--7. 1. "SSS,Source Signal Select" line.long 0x2C4 "MSCR_IO177,SIUL2 I/O pin multiplexed signal configuration register 177" bitfld.long 0x2C4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2C4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2C4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2C4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2C4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2C4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2C4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2C4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2C4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2C4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2C4 0.--7. 1. "SSS,Source Signal Select" line.long 0x2C8 "MSCR_IO178,SIUL2 I/O pin multiplexed signal configuration register 178" bitfld.long 0x2C8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2C8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2C8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2C8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2C8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2C8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2C8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2C8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2C8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2C8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2C8 0.--7. 1. "SSS,Source Signal Select" line.long 0x2CC "MSCR_IO179,SIUL2 I/O pin multiplexed signal configuration register 179" bitfld.long 0x2CC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2CC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2CC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2CC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2CC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2CC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2CC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2CC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2CC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2CC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2CC 0.--7. 1. "SSS,Source Signal Select" line.long 0x2D0 "MSCR_IO180,SIUL2 I/O pin multiplexed signal configuration register 180" bitfld.long 0x2D0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2D0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2D0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2D0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2D0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2D0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2D0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2D0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2D0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2D0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2D0 0.--7. 1. "SSS,Source Signal Select" line.long 0x2D4 "MSCR_IO181,SIUL2 I/O pin multiplexed signal configuration register 181" bitfld.long 0x2D4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2D4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2D4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2D4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2D4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2D4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2D4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2D4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2D4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2D4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2D4 0.--7. 1. "SSS,Source Signal Select" line.long 0x2D8 "MSCR_IO182,SIUL2 I/O pin multiplexed signal configuration register 182" bitfld.long 0x2D8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2D8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2D8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2D8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2D8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2D8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2D8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2D8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2D8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2D8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2D8 0.--7. 1. "SSS,Source Signal Select" line.long 0x2DC "MSCR_IO183,SIUL2 I/O pin multiplexed signal configuration register 183" bitfld.long 0x2DC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2DC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2DC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2DC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2DC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2DC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2DC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2DC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2DC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2DC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2DC 0.--7. 1. "SSS,Source Signal Select" line.long 0x2E0 "MSCR_IO184,SIUL2 I/O pin multiplexed signal configuration register 184" bitfld.long 0x2E0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2E0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2E0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2E0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2E0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2E0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2E0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2E0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2E0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2E0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2E0 0.--7. 1. "SSS,Source Signal Select" line.long 0x2E4 "MSCR_IO185,SIUL2 I/O pin multiplexed signal configuration register 185" bitfld.long 0x2E4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2E4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2E4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2E4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2E4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2E4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2E4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2E4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2E4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2E4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2E4 0.--7. 1. "SSS,Source Signal Select" line.long 0x2E8 "MSCR_IO186,SIUL2 I/O pin multiplexed signal configuration register 186" bitfld.long 0x2E8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2E8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2E8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2E8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2E8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2E8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2E8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2E8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2E8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2E8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2E8 0.--7. 1. "SSS,Source Signal Select" line.long 0x2EC "MSCR_IO187,SIUL2 I/O pin multiplexed signal configuration register 187" bitfld.long 0x2EC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2EC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2EC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2EC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2EC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2EC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2EC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2EC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2EC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2EC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2EC 0.--7. 1. "SSS,Source Signal Select" line.long 0x2F0 "MSCR_IO188,SIUL2 I/O pin multiplexed signal configuration register 188" bitfld.long 0x2F0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2F0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2F0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2F0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2F0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2F0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2F0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2F0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2F0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2F0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2F0 0.--7. 1. "SSS,Source Signal Select" line.long 0x2F4 "MSCR_IO189,SIUL2 I/O pin multiplexed signal configuration register 189" bitfld.long 0x2F4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2F4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2F4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2F4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2F4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2F4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2F4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2F4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2F4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2F4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2F4 0.--7. 1. "SSS,Source Signal Select" line.long 0x2F8 "MSCR_IO190,SIUL2 I/O pin multiplexed signal configuration register 190" bitfld.long 0x2F8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2F8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2F8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2F8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2F8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2F8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2F8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2F8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2F8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2F8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2F8 0.--7. 1. "SSS,Source Signal Select" line.long 0x2FC "MSCR_IO191,SIUL2 I/O pin multiplexed signal configuration register 191" bitfld.long 0x2FC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x2FC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x2FC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x2FC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x2FC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2FC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2FC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x2FC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x2FC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x2FC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x2FC 0.--7. 1. "SSS,Source Signal Select" line.long 0x300 "MSCR_IO192,SIUL2 I/O pin multiplexed signal configuration register 192" bitfld.long 0x300 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x300 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x300 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x300 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x300 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x300 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x300 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x300 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x300 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x300 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x300 0.--7. 1. "SSS,Source Signal Select" line.long 0x304 "MSCR_IO193,SIUL2 I/O pin multiplexed signal configuration register 193" bitfld.long 0x304 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x304 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x304 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x304 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x304 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x304 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x304 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x304 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x304 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x304 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x304 0.--7. 1. "SSS,Source Signal Select" line.long 0x308 "MSCR_IO194,SIUL2 I/O pin multiplexed signal configuration register 194" bitfld.long 0x308 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x308 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x308 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x308 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x308 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x308 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x308 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x308 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x308 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x308 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x308 0.--7. 1. "SSS,Source Signal Select" line.long 0x30C "MSCR_IO195,SIUL2 I/O pin multiplexed signal configuration register 195" bitfld.long 0x30C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x30C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x30C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x30C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x30C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x30C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x30C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x30C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x30C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x30C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x30C 0.--7. 1. "SSS,Source Signal Select" line.long 0x310 "MSCR_IO196,SIUL2 I/O pin multiplexed signal configuration register 196" bitfld.long 0x310 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x310 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x310 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x310 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x310 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x310 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x310 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x310 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x310 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x310 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x310 0.--7. 1. "SSS,Source Signal Select" line.long 0x314 "MSCR_IO197,SIUL2 I/O pin multiplexed signal configuration register 197" bitfld.long 0x314 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x314 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x314 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x314 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x314 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x314 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x314 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x314 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x314 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x314 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x314 0.--7. 1. "SSS,Source Signal Select" line.long 0x318 "MSCR_IO198,SIUL2 I/O pin multiplexed signal configuration register 198" bitfld.long 0x318 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x318 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x318 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x318 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x318 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x318 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x318 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x318 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x318 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x318 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x318 0.--7. 1. "SSS,Source Signal Select" line.long 0x31C "MSCR_IO199,SIUL2 I/O pin multiplexed signal configuration register 199" bitfld.long 0x31C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x31C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x31C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x31C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x31C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x31C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x31C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x31C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x31C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x31C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x31C 0.--7. 1. "SSS,Source Signal Select" line.long 0x320 "MSCR_IO200,SIUL2 I/O pin multiplexed signal configuration register 200" bitfld.long 0x320 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x320 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x320 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x320 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x320 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x320 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x320 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x320 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x320 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x320 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x320 0.--7. 1. "SSS,Source Signal Select" line.long 0x324 "MSCR_IO201,SIUL2 I/O pin multiplexed signal configuration register 201" bitfld.long 0x324 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x324 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x324 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x324 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x324 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x324 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x324 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x324 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x324 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x324 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x324 0.--7. 1. "SSS,Source Signal Select" line.long 0x328 "MSCR_IO202,SIUL2 I/O pin multiplexed signal configuration register 202" bitfld.long 0x328 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x328 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x328 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x328 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x328 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x328 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x328 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x328 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x328 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x328 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x328 0.--7. 1. "SSS,Source Signal Select" line.long 0x32C "MSCR_IO203,SIUL2 I/O pin multiplexed signal configuration register 203" bitfld.long 0x32C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x32C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x32C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x32C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x32C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x32C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x32C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x32C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x32C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x32C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x32C 0.--7. 1. "SSS,Source Signal Select" line.long 0x330 "MSCR_IO204,SIUL2 I/O pin multiplexed signal configuration register 204" bitfld.long 0x330 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x330 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x330 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x330 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x330 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x330 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x330 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x330 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x330 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x330 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x330 0.--7. 1. "SSS,Source Signal Select" line.long 0x334 "MSCR_IO205,SIUL2 I/O pin multiplexed signal configuration register 205" bitfld.long 0x334 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x334 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x334 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x334 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x334 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x334 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x334 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x334 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x334 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x334 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x334 0.--7. 1. "SSS,Source Signal Select" line.long 0x338 "MSCR_IO206,SIUL2 I/O pin multiplexed signal configuration register 206" bitfld.long 0x338 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x338 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x338 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x338 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x338 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x338 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x338 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x338 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x338 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x338 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x338 0.--7. 1. "SSS,Source Signal Select" line.long 0x33C "MSCR_IO207,SIUL2 I/O pin multiplexed signal configuration register 207" bitfld.long 0x33C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x33C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x33C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x33C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x33C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x33C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x33C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x33C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x33C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x33C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x33C 0.--7. 1. "SSS,Source Signal Select" line.long 0x340 "MSCR_IO208,SIUL2 I/O pin multiplexed signal configuration register 208" bitfld.long 0x340 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x340 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x340 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x340 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x340 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x340 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x340 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x340 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x340 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x340 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x340 0.--7. 1. "SSS,Source Signal Select" line.long 0x344 "MSCR_IO209,SIUL2 I/O pin multiplexed signal configuration register 209" bitfld.long 0x344 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x344 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x344 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x344 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x344 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x344 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x344 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x344 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x344 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x344 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x344 0.--7. 1. "SSS,Source Signal Select" line.long 0x348 "MSCR_IO210,SIUL2 I/O pin multiplexed signal configuration register 210" bitfld.long 0x348 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x348 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x348 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x348 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x348 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x348 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x348 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x348 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x348 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x348 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x348 0.--7. 1. "SSS,Source Signal Select" line.long 0x34C "MSCR_IO211,SIUL2 I/O pin multiplexed signal configuration register 211" bitfld.long 0x34C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x34C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x34C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x34C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x34C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x34C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x34C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x34C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x34C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x34C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x34C 0.--7. 1. "SSS,Source Signal Select" line.long 0x350 "MSCR_IO212,SIUL2 I/O pin multiplexed signal configuration register 212" bitfld.long 0x350 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x350 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x350 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x350 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x350 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x350 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x350 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x350 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x350 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x350 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x350 0.--7. 1. "SSS,Source Signal Select" line.long 0x354 "MSCR_IO213,SIUL2 I/O pin multiplexed signal configuration register 213" bitfld.long 0x354 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x354 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x354 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x354 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x354 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x354 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x354 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x354 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x354 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x354 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x354 0.--7. 1. "SSS,Source Signal Select" line.long 0x358 "MSCR_IO214,SIUL2 I/O pin multiplexed signal configuration register 214" bitfld.long 0x358 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x358 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x358 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x358 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x358 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x358 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x358 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x358 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x358 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x358 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x358 0.--7. 1. "SSS,Source Signal Select" line.long 0x35C "MSCR_IO215,SIUL2 I/O pin multiplexed signal configuration register 215" bitfld.long 0x35C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x35C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x35C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x35C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x35C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x35C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x35C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x35C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x35C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x35C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x35C 0.--7. 1. "SSS,Source Signal Select" line.long 0x360 "MSCR_IO216,SIUL2 I/O pin multiplexed signal configuration register 216" bitfld.long 0x360 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x360 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x360 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x360 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x360 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x360 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x360 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x360 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x360 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x360 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x360 0.--7. 1. "SSS,Source Signal Select" line.long 0x364 "MSCR_IO217,SIUL2 I/O pin multiplexed signal configuration register 217" bitfld.long 0x364 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x364 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x364 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x364 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x364 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x364 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x364 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x364 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x364 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x364 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x364 0.--7. 1. "SSS,Source Signal Select" line.long 0x368 "MSCR_IO218,SIUL2 I/O pin multiplexed signal configuration register 218" bitfld.long 0x368 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x368 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x368 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x368 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x368 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x368 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x368 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x368 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x368 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x368 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x368 0.--7. 1. "SSS,Source Signal Select" line.long 0x36C "MSCR_IO219,SIUL2 I/O pin multiplexed signal configuration register 219" bitfld.long 0x36C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x36C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x36C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x36C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x36C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x36C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x36C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x36C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x36C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x36C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x36C 0.--7. 1. "SSS,Source Signal Select" line.long 0x370 "MSCR_IO220,SIUL2 I/O pin multiplexed signal configuration register 220" bitfld.long 0x370 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x370 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x370 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x370 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x370 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x370 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x370 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x370 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x370 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x370 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x370 0.--7. 1. "SSS,Source Signal Select" line.long 0x374 "MSCR_IO221,SIUL2 I/O pin multiplexed signal configuration register 221" bitfld.long 0x374 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x374 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x374 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x374 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x374 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x374 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x374 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x374 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x374 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x374 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x374 0.--7. 1. "SSS,Source Signal Select" line.long 0x378 "MSCR_IO222,SIUL2 I/O pin multiplexed signal configuration register 222" bitfld.long 0x378 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x378 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x378 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x378 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x378 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x378 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x378 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x378 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x378 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x378 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x378 0.--7. 1. "SSS,Source Signal Select" line.long 0x37C "MSCR_IO223,SIUL2 I/O pin multiplexed signal configuration register 223" bitfld.long 0x37C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x37C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x37C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x37C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x37C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x37C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x37C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x37C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x37C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x37C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x37C 0.--7. 1. "SSS,Source Signal Select" line.long 0x380 "MSCR_IO224,SIUL2 I/O pin multiplexed signal configuration register 224" bitfld.long 0x380 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x380 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x380 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x380 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x380 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x380 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x380 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x380 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x380 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x380 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x380 0.--7. 1. "SSS,Source Signal Select" line.long 0x384 "MSCR_IO225,SIUL2 I/O pin multiplexed signal configuration register 225" bitfld.long 0x384 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x384 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x384 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x384 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x384 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x384 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x384 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x384 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x384 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x384 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x384 0.--7. 1. "SSS,Source Signal Select" line.long 0x388 "MSCR_IO226,SIUL2 I/O pin multiplexed signal configuration register 226" bitfld.long 0x388 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x388 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x388 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x388 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x388 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x388 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x388 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x388 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x388 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x388 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x388 0.--7. 1. "SSS,Source Signal Select" line.long 0x38C "MSCR_IO227,SIUL2 I/O pin multiplexed signal configuration register 227" bitfld.long 0x38C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x38C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x38C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x38C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x38C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x38C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x38C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x38C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x38C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x38C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x38C 0.--7. 1. "SSS,Source Signal Select" line.long 0x390 "MSCR_IO228,SIUL2 I/O pin multiplexed signal configuration register 228" bitfld.long 0x390 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x390 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x390 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x390 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x390 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x390 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x390 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x390 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x390 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x390 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x390 0.--7. 1. "SSS,Source Signal Select" line.long 0x394 "MSCR_IO229,SIUL2 I/O pin multiplexed signal configuration register 229" bitfld.long 0x394 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x394 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x394 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x394 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x394 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x394 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x394 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x394 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x394 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x394 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x394 0.--7. 1. "SSS,Source Signal Select" line.long 0x398 "MSCR_IO230,SIUL2 I/O pin multiplexed signal configuration register 230" bitfld.long 0x398 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x398 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x398 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x398 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x398 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x398 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x398 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x398 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x398 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x398 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x398 0.--7. 1. "SSS,Source Signal Select" line.long 0x39C "MSCR_IO231,SIUL2 I/O pin multiplexed signal configuration register 231" bitfld.long 0x39C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x39C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x39C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x39C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x39C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x39C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x39C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x39C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x39C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x39C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x39C 0.--7. 1. "SSS,Source Signal Select" line.long 0x3A0 "MSCR_IO232,SIUL2 I/O pin multiplexed signal configuration register 232" bitfld.long 0x3A0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3A0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3A0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3A0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3A0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3A0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3A0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3A0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3A0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3A0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3A0 0.--7. 1. "SSS,Source Signal Select" line.long 0x3A4 "MSCR_IO233,SIUL2 I/O pin multiplexed signal configuration register 233" bitfld.long 0x3A4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3A4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3A4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3A4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3A4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3A4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3A4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3A4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3A4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3A4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3A4 0.--7. 1. "SSS,Source Signal Select" line.long 0x3A8 "MSCR_IO234,SIUL2 I/O pin multiplexed signal configuration register 234" bitfld.long 0x3A8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3A8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3A8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3A8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3A8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3A8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3A8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3A8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3A8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3A8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3A8 0.--7. 1. "SSS,Source Signal Select" line.long 0x3AC "MSCR_IO235,SIUL2 I/O pin multiplexed signal configuration register 235" bitfld.long 0x3AC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3AC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3AC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3AC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3AC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3AC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3AC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3AC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3AC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3AC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3AC 0.--7. 1. "SSS,Source Signal Select" line.long 0x3B0 "MSCR_IO236,SIUL2 I/O pin multiplexed signal configuration register 236" bitfld.long 0x3B0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3B0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3B0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3B0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3B0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3B0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3B0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3B0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3B0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3B0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3B0 0.--7. 1. "SSS,Source Signal Select" line.long 0x3B4 "MSCR_IO237,SIUL2 I/O pin multiplexed signal configuration register 237" bitfld.long 0x3B4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3B4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3B4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3B4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3B4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3B4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3B4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3B4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3B4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3B4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3B4 0.--7. 1. "SSS,Source Signal Select" line.long 0x3B8 "MSCR_IO238,SIUL2 I/O pin multiplexed signal configuration register 238" bitfld.long 0x3B8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3B8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3B8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3B8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3B8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3B8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3B8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3B8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3B8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3B8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3B8 0.--7. 1. "SSS,Source Signal Select" line.long 0x3BC "MSCR_IO239,SIUL2 I/O pin multiplexed signal configuration register 239" bitfld.long 0x3BC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3BC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3BC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3BC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3BC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3BC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3BC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3BC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3BC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3BC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3BC 0.--7. 1. "SSS,Source Signal Select" line.long 0x3C0 "MSCR_IO240,SIUL2 I/O pin multiplexed signal configuration register 240" bitfld.long 0x3C0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3C0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3C0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3C0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3C0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3C0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3C0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3C0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3C0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3C0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3C0 0.--7. 1. "SSS,Source Signal Select" line.long 0x3C4 "MSCR_IO241,SIUL2 I/O pin multiplexed signal configuration register 241" bitfld.long 0x3C4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3C4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3C4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3C4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3C4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3C4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3C4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3C4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3C4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3C4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3C4 0.--7. 1. "SSS,Source Signal Select" line.long 0x3C8 "MSCR_IO242,SIUL2 I/O pin multiplexed signal configuration register 242" bitfld.long 0x3C8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3C8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3C8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3C8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3C8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3C8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3C8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3C8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3C8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3C8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3C8 0.--7. 1. "SSS,Source Signal Select" line.long 0x3CC "MSCR_IO243,SIUL2 I/O pin multiplexed signal configuration register 243" bitfld.long 0x3CC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3CC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3CC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3CC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3CC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3CC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3CC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3CC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3CC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3CC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3CC 0.--7. 1. "SSS,Source Signal Select" line.long 0x3D0 "MSCR_IO244,SIUL2 I/O pin multiplexed signal configuration register 244" bitfld.long 0x3D0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3D0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3D0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3D0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3D0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3D0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3D0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3D0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3D0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3D0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3D0 0.--7. 1. "SSS,Source Signal Select" line.long 0x3D4 "MSCR_IO245,SIUL2 I/O pin multiplexed signal configuration register 245" bitfld.long 0x3D4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3D4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3D4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3D4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3D4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3D4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3D4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3D4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3D4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3D4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3D4 0.--7. 1. "SSS,Source Signal Select" line.long 0x3D8 "MSCR_IO246,SIUL2 I/O pin multiplexed signal configuration register 246" bitfld.long 0x3D8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3D8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3D8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3D8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3D8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3D8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3D8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3D8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3D8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3D8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3D8 0.--7. 1. "SSS,Source Signal Select" line.long 0x3DC "MSCR_IO247,SIUL2 I/O pin multiplexed signal configuration register 247" bitfld.long 0x3DC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3DC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3DC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3DC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3DC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3DC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3DC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3DC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3DC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3DC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3DC 0.--7. 1. "SSS,Source Signal Select" line.long 0x3E0 "MSCR_IO248,SIUL2 I/O pin multiplexed signal configuration register 248" bitfld.long 0x3E0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3E0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3E0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3E0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3E0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3E0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3E0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3E0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3E0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3E0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3E0 0.--7. 1. "SSS,Source Signal Select" line.long 0x3E4 "MSCR_IO249,SIUL2 I/O pin multiplexed signal configuration register 249" bitfld.long 0x3E4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3E4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3E4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3E4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3E4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3E4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3E4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3E4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3E4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3E4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3E4 0.--7. 1. "SSS,Source Signal Select" line.long 0x3E8 "MSCR_IO250,SIUL2 I/O pin multiplexed signal configuration register 250" bitfld.long 0x3E8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3E8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3E8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3E8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3E8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3E8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3E8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3E8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3E8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3E8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3E8 0.--7. 1. "SSS,Source Signal Select" line.long 0x3EC "MSCR_IO251,SIUL2 I/O pin multiplexed signal configuration register 251" bitfld.long 0x3EC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3EC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3EC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3EC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3EC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3EC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3EC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3EC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3EC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3EC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3EC 0.--7. 1. "SSS,Source Signal Select" line.long 0x3F0 "MSCR_IO252,SIUL2 I/O pin multiplexed signal configuration register 252" bitfld.long 0x3F0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3F0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3F0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3F0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3F0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3F0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3F0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3F0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3F0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3F0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3F0 0.--7. 1. "SSS,Source Signal Select" line.long 0x3F4 "MSCR_IO253,SIUL2 I/O pin multiplexed signal configuration register 253" bitfld.long 0x3F4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3F4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3F4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3F4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3F4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3F4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3F4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3F4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3F4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3F4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3F4 0.--7. 1. "SSS,Source Signal Select" line.long 0x3F8 "MSCR_IO254,SIUL2 I/O pin multiplexed signal configuration register 254" bitfld.long 0x3F8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3F8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3F8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3F8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3F8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3F8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3F8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3F8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3F8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3F8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3F8 0.--7. 1. "SSS,Source Signal Select" line.long 0x3FC "MSCR_IO255,SIUL2 I/O pin multiplexed signal configuration register 255" bitfld.long 0x3FC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x3FC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x3FC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x3FC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x3FC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3FC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3FC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x3FC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x3FC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x3FC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x3FC 0.--7. 1. "SSS,Source Signal Select" line.long 0x400 "MSCR_IO256,SIUL2 I/O pin multiplexed signal configuration register 256" bitfld.long 0x400 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x400 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x400 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x400 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x400 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x400 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x400 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x400 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x400 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x400 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x400 0.--7. 1. "SSS,Source Signal Select" line.long 0x404 "MSCR_IO257,SIUL2 I/O pin multiplexed signal configuration register 257" bitfld.long 0x404 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x404 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x404 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x404 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x404 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x404 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x404 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x404 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x404 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x404 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x404 0.--7. 1. "SSS,Source Signal Select" line.long 0x408 "MSCR_IO258,SIUL2 I/O pin multiplexed signal configuration register 258" bitfld.long 0x408 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x408 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x408 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x408 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x408 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x408 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x408 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x408 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x408 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x408 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x408 0.--7. 1. "SSS,Source Signal Select" line.long 0x40C "MSCR_IO259,SIUL2 I/O pin multiplexed signal configuration register 259" bitfld.long 0x40C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x40C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x40C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x40C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x40C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x40C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x40C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x40C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x40C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x40C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x40C 0.--7. 1. "SSS,Source Signal Select" line.long 0x410 "MSCR_IO260,SIUL2 I/O pin multiplexed signal configuration register 260" bitfld.long 0x410 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x410 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x410 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x410 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x410 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x410 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x410 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x410 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x410 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x410 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x410 0.--7. 1. "SSS,Source Signal Select" line.long 0x414 "MSCR_IO261,SIUL2 I/O pin multiplexed signal configuration register 261" bitfld.long 0x414 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x414 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x414 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x414 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x414 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x414 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x414 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x414 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x414 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x414 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x414 0.--7. 1. "SSS,Source Signal Select" line.long 0x418 "MSCR_IO262,SIUL2 I/O pin multiplexed signal configuration register 262" bitfld.long 0x418 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x418 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x418 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x418 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x418 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x418 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x418 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x418 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x418 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x418 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x418 0.--7. 1. "SSS,Source Signal Select" line.long 0x41C "MSCR_IO263,SIUL2 I/O pin multiplexed signal configuration register 263" bitfld.long 0x41C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x41C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x41C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x41C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x41C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x41C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x41C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x41C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x41C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x41C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x41C 0.--7. 1. "SSS,Source Signal Select" line.long 0x420 "MSCR_IO264,SIUL2 I/O pin multiplexed signal configuration register 264" bitfld.long 0x420 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x420 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x420 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x420 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x420 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x420 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x420 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x420 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x420 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x420 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x420 0.--7. 1. "SSS,Source Signal Select" line.long 0x424 "MSCR_IO265,SIUL2 I/O pin multiplexed signal configuration register 265" bitfld.long 0x424 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x424 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x424 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x424 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x424 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x424 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x424 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x424 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x424 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x424 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x424 0.--7. 1. "SSS,Source Signal Select" line.long 0x428 "MSCR_IO266,SIUL2 I/O pin multiplexed signal configuration register 266" bitfld.long 0x428 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x428 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x428 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x428 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x428 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x428 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x428 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x428 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x428 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x428 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x428 0.--7. 1. "SSS,Source Signal Select" line.long 0x42C "MSCR_IO267,SIUL2 I/O pin multiplexed signal configuration register 267" bitfld.long 0x42C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x42C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x42C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x42C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x42C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x42C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x42C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x42C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x42C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x42C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x42C 0.--7. 1. "SSS,Source Signal Select" line.long 0x430 "MSCR_IO268,SIUL2 I/O pin multiplexed signal configuration register 268" bitfld.long 0x430 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x430 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x430 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x430 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x430 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x430 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x430 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x430 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x430 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x430 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x430 0.--7. 1. "SSS,Source Signal Select" line.long 0x434 "MSCR_IO269,SIUL2 I/O pin multiplexed signal configuration register 269" bitfld.long 0x434 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x434 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x434 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x434 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x434 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x434 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x434 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x434 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x434 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x434 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x434 0.--7. 1. "SSS,Source Signal Select" line.long 0x438 "MSCR_IO270,SIUL2 I/O pin multiplexed signal configuration register 270" bitfld.long 0x438 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x438 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x438 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x438 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x438 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x438 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x438 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x438 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x438 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x438 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x438 0.--7. 1. "SSS,Source Signal Select" line.long 0x43C "MSCR_IO271,SIUL2 I/O pin multiplexed signal configuration register 271" bitfld.long 0x43C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x43C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x43C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x43C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x43C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x43C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x43C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x43C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x43C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x43C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x43C 0.--7. 1. "SSS,Source Signal Select" line.long 0x440 "MSCR_IO272,SIUL2 I/O pin multiplexed signal configuration register 272" bitfld.long 0x440 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x440 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x440 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x440 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x440 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x440 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x440 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x440 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x440 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x440 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x440 0.--7. 1. "SSS,Source Signal Select" line.long 0x444 "MSCR_IO273,SIUL2 I/O pin multiplexed signal configuration register 273" bitfld.long 0x444 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x444 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x444 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x444 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x444 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x444 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x444 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x444 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x444 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x444 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x444 0.--7. 1. "SSS,Source Signal Select" line.long 0x448 "MSCR_IO274,SIUL2 I/O pin multiplexed signal configuration register 274" bitfld.long 0x448 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x448 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x448 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x448 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x448 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x448 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x448 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x448 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x448 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x448 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x448 0.--7. 1. "SSS,Source Signal Select" line.long 0x44C "MSCR_IO275,SIUL2 I/O pin multiplexed signal configuration register 275" bitfld.long 0x44C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x44C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x44C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x44C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x44C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x44C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x44C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x44C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x44C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x44C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x44C 0.--7. 1. "SSS,Source Signal Select" line.long 0x450 "MSCR_IO276,SIUL2 I/O pin multiplexed signal configuration register 276" bitfld.long 0x450 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x450 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x450 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x450 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x450 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x450 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x450 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x450 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x450 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x450 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x450 0.--7. 1. "SSS,Source Signal Select" line.long 0x454 "MSCR_IO277,SIUL2 I/O pin multiplexed signal configuration register 277" bitfld.long 0x454 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x454 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x454 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x454 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x454 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x454 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x454 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x454 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x454 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x454 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x454 0.--7. 1. "SSS,Source Signal Select" line.long 0x458 "MSCR_IO278,SIUL2 I/O pin multiplexed signal configuration register 278" bitfld.long 0x458 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x458 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x458 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x458 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x458 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x458 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x458 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x458 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x458 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x458 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x458 0.--7. 1. "SSS,Source Signal Select" line.long 0x45C "MSCR_IO279,SIUL2 I/O pin multiplexed signal configuration register 279" bitfld.long 0x45C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x45C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x45C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x45C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x45C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x45C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x45C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x45C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x45C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x45C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x45C 0.--7. 1. "SSS,Source Signal Select" line.long 0x460 "MSCR_IO280,SIUL2 I/O pin multiplexed signal configuration register 280" bitfld.long 0x460 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x460 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x460 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x460 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x460 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x460 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x460 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x460 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x460 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x460 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x460 0.--7. 1. "SSS,Source Signal Select" line.long 0x464 "MSCR_IO281,SIUL2 I/O pin multiplexed signal configuration register 281" bitfld.long 0x464 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x464 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x464 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x464 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x464 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x464 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x464 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x464 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x464 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x464 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x464 0.--7. 1. "SSS,Source Signal Select" line.long 0x468 "MSCR_IO282,SIUL2 I/O pin multiplexed signal configuration register 282" bitfld.long 0x468 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x468 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x468 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x468 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x468 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x468 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x468 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x468 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x468 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x468 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x468 0.--7. 1. "SSS,Source Signal Select" line.long 0x46C "MSCR_IO283,SIUL2 I/O pin multiplexed signal configuration register 283" bitfld.long 0x46C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x46C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x46C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x46C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x46C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x46C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x46C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x46C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x46C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x46C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x46C 0.--7. 1. "SSS,Source Signal Select" line.long 0x470 "MSCR_IO284,SIUL2 I/O pin multiplexed signal configuration register 284" bitfld.long 0x470 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x470 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x470 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x470 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x470 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x470 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x470 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x470 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x470 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x470 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x470 0.--7. 1. "SSS,Source Signal Select" line.long 0x474 "MSCR_IO285,SIUL2 I/O pin multiplexed signal configuration register 285" bitfld.long 0x474 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x474 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x474 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x474 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x474 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x474 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x474 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x474 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x474 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x474 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x474 0.--7. 1. "SSS,Source Signal Select" line.long 0x478 "MSCR_IO286,SIUL2 I/O pin multiplexed signal configuration register 286" bitfld.long 0x478 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x478 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x478 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x478 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x478 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x478 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x478 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x478 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x478 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x478 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x478 0.--7. 1. "SSS,Source Signal Select" line.long 0x47C "MSCR_IO287,SIUL2 I/O pin multiplexed signal configuration register 287" bitfld.long 0x47C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x47C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x47C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x47C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x47C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x47C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x47C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x47C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x47C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x47C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x47C 0.--7. 1. "SSS,Source Signal Select" line.long 0x480 "MSCR_IO288,SIUL2 I/O pin multiplexed signal configuration register 288" bitfld.long 0x480 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x480 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x480 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x480 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x480 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x480 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x480 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x480 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x480 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x480 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x480 0.--7. 1. "SSS,Source Signal Select" line.long 0x484 "MSCR_IO289,SIUL2 I/O pin multiplexed signal configuration register 289" bitfld.long 0x484 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x484 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x484 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x484 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x484 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x484 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x484 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x484 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x484 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x484 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x484 0.--7. 1. "SSS,Source Signal Select" line.long 0x488 "MSCR_IO290,SIUL2 I/O pin multiplexed signal configuration register 290" bitfld.long 0x488 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x488 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x488 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x488 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x488 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x488 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x488 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x488 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x488 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x488 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x488 0.--7. 1. "SSS,Source Signal Select" line.long 0x48C "MSCR_IO291,SIUL2 I/O pin multiplexed signal configuration register 291" bitfld.long 0x48C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x48C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x48C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x48C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x48C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x48C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x48C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x48C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x48C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x48C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x48C 0.--7. 1. "SSS,Source Signal Select" line.long 0x490 "MSCR_IO292,SIUL2 I/O pin multiplexed signal configuration register 292" bitfld.long 0x490 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x490 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x490 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x490 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x490 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x490 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x490 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x490 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x490 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x490 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x490 0.--7. 1. "SSS,Source Signal Select" line.long 0x494 "MSCR_IO293,SIUL2 I/O pin multiplexed signal configuration register 293" bitfld.long 0x494 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x494 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x494 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x494 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x494 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x494 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x494 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x494 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x494 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x494 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x494 0.--7. 1. "SSS,Source Signal Select" line.long 0x498 "MSCR_IO294,SIUL2 I/O pin multiplexed signal configuration register 294" bitfld.long 0x498 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x498 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x498 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x498 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x498 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x498 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x498 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x498 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x498 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x498 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x498 0.--7. 1. "SSS,Source Signal Select" line.long 0x49C "MSCR_IO295,SIUL2 I/O pin multiplexed signal configuration register 295" bitfld.long 0x49C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x49C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x49C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x49C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x49C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x49C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x49C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x49C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x49C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x49C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x49C 0.--7. 1. "SSS,Source Signal Select" line.long 0x4A0 "MSCR_IO296,SIUL2 I/O pin multiplexed signal configuration register 296" bitfld.long 0x4A0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4A0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4A0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4A0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4A0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4A0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4A0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4A0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4A0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4A0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4A0 0.--7. 1. "SSS,Source Signal Select" line.long 0x4A4 "MSCR_IO297,SIUL2 I/O pin multiplexed signal configuration register 297" bitfld.long 0x4A4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4A4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4A4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4A4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4A4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4A4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4A4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4A4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4A4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4A4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4A4 0.--7. 1. "SSS,Source Signal Select" line.long 0x4A8 "MSCR_IO298,SIUL2 I/O pin multiplexed signal configuration register 298" bitfld.long 0x4A8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4A8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4A8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4A8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4A8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4A8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4A8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4A8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4A8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4A8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4A8 0.--7. 1. "SSS,Source Signal Select" line.long 0x4AC "MSCR_IO299,SIUL2 I/O pin multiplexed signal configuration register 299" bitfld.long 0x4AC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4AC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4AC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4AC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4AC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4AC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4AC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4AC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4AC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4AC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4AC 0.--7. 1. "SSS,Source Signal Select" line.long 0x4B0 "MSCR_IO300,SIUL2 I/O pin multiplexed signal configuration register 300" bitfld.long 0x4B0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4B0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4B0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4B0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4B0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4B0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4B0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4B0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4B0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4B0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4B0 0.--7. 1. "SSS,Source Signal Select" line.long 0x4B4 "MSCR_IO301,SIUL2 I/O pin multiplexed signal configuration register 301" bitfld.long 0x4B4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4B4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4B4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4B4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4B4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4B4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4B4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4B4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4B4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4B4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4B4 0.--7. 1. "SSS,Source Signal Select" line.long 0x4B8 "MSCR_IO302,SIUL2 I/O pin multiplexed signal configuration register 302" bitfld.long 0x4B8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4B8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4B8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4B8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4B8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4B8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4B8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4B8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4B8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4B8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4B8 0.--7. 1. "SSS,Source Signal Select" line.long 0x4BC "MSCR_IO303,SIUL2 I/O pin multiplexed signal configuration register 303" bitfld.long 0x4BC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4BC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4BC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4BC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4BC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4BC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4BC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4BC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4BC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4BC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4BC 0.--7. 1. "SSS,Source Signal Select" line.long 0x4C0 "MSCR_IO304,SIUL2 I/O pin multiplexed signal configuration register 304" bitfld.long 0x4C0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4C0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4C0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4C0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4C0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4C0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4C0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4C0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4C0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4C0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4C0 0.--7. 1. "SSS,Source Signal Select" line.long 0x4C4 "MSCR_IO305,SIUL2 I/O pin multiplexed signal configuration register 305" bitfld.long 0x4C4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4C4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4C4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4C4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4C4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4C4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4C4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4C4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4C4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4C4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4C4 0.--7. 1. "SSS,Source Signal Select" line.long 0x4C8 "MSCR_IO306,SIUL2 I/O pin multiplexed signal configuration register 306" bitfld.long 0x4C8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4C8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4C8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4C8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4C8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4C8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4C8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4C8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4C8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4C8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4C8 0.--7. 1. "SSS,Source Signal Select" line.long 0x4CC "MSCR_IO307,SIUL2 I/O pin multiplexed signal configuration register 307" bitfld.long 0x4CC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4CC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4CC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4CC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4CC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4CC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4CC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4CC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4CC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4CC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4CC 0.--7. 1. "SSS,Source Signal Select" line.long 0x4D0 "MSCR_IO308,SIUL2 I/O pin multiplexed signal configuration register 308" bitfld.long 0x4D0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4D0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4D0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4D0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4D0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4D0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4D0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4D0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4D0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4D0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4D0 0.--7. 1. "SSS,Source Signal Select" line.long 0x4D4 "MSCR_IO309,SIUL2 I/O pin multiplexed signal configuration register 309" bitfld.long 0x4D4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4D4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4D4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4D4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4D4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4D4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4D4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4D4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4D4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4D4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4D4 0.--7. 1. "SSS,Source Signal Select" line.long 0x4D8 "MSCR_IO310,SIUL2 I/O pin multiplexed signal configuration register 310" bitfld.long 0x4D8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4D8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4D8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4D8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4D8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4D8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4D8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4D8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4D8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4D8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4D8 0.--7. 1. "SSS,Source Signal Select" line.long 0x4DC "MSCR_IO311,SIUL2 I/O pin multiplexed signal configuration register 311" bitfld.long 0x4DC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4DC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4DC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4DC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4DC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4DC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4DC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4DC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4DC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4DC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4DC 0.--7. 1. "SSS,Source Signal Select" line.long 0x4E0 "MSCR_IO312,SIUL2 I/O pin multiplexed signal configuration register 312" bitfld.long 0x4E0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4E0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4E0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4E0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4E0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4E0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4E0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4E0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4E0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4E0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4E0 0.--7. 1. "SSS,Source Signal Select" line.long 0x4E4 "MSCR_IO313,SIUL2 I/O pin multiplexed signal configuration register 313" bitfld.long 0x4E4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4E4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4E4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4E4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4E4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4E4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4E4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4E4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4E4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4E4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4E4 0.--7. 1. "SSS,Source Signal Select" line.long 0x4E8 "MSCR_IO314,SIUL2 I/O pin multiplexed signal configuration register 314" bitfld.long 0x4E8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4E8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4E8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4E8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4E8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4E8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4E8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4E8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4E8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4E8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4E8 0.--7. 1. "SSS,Source Signal Select" line.long 0x4EC "MSCR_IO315,SIUL2 I/O pin multiplexed signal configuration register 315" bitfld.long 0x4EC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4EC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4EC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4EC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4EC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4EC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4EC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4EC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4EC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4EC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4EC 0.--7. 1. "SSS,Source Signal Select" line.long 0x4F0 "MSCR_IO316,SIUL2 I/O pin multiplexed signal configuration register 316" bitfld.long 0x4F0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4F0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4F0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4F0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4F0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4F0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4F0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4F0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4F0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4F0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4F0 0.--7. 1. "SSS,Source Signal Select" line.long 0x4F4 "MSCR_IO317,SIUL2 I/O pin multiplexed signal configuration register 317" bitfld.long 0x4F4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4F4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4F4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4F4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4F4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4F4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4F4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4F4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4F4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4F4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4F4 0.--7. 1. "SSS,Source Signal Select" line.long 0x4F8 "MSCR_IO318,SIUL2 I/O pin multiplexed signal configuration register 318" bitfld.long 0x4F8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4F8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4F8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4F8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4F8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4F8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4F8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4F8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4F8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4F8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4F8 0.--7. 1. "SSS,Source Signal Select" line.long 0x4FC "MSCR_IO319,SIUL2 I/O pin multiplexed signal configuration register 319" bitfld.long 0x4FC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x4FC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x4FC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x4FC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x4FC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4FC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4FC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x4FC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x4FC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x4FC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x4FC 0.--7. 1. "SSS,Source Signal Select" line.long 0x500 "MSCR_IO320,SIUL2 I/O pin multiplexed signal configuration register 320" bitfld.long 0x500 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x500 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x500 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x500 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x500 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x500 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x500 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x500 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x500 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x500 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x500 0.--7. 1. "SSS,Source Signal Select" line.long 0x504 "MSCR_IO321,SIUL2 I/O pin multiplexed signal configuration register 321" bitfld.long 0x504 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x504 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x504 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x504 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x504 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x504 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x504 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x504 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x504 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x504 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x504 0.--7. 1. "SSS,Source Signal Select" line.long 0x508 "MSCR_IO322,SIUL2 I/O pin multiplexed signal configuration register 322" bitfld.long 0x508 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x508 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x508 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x508 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x508 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x508 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x508 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x508 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x508 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x508 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x508 0.--7. 1. "SSS,Source Signal Select" line.long 0x50C "MSCR_IO323,SIUL2 I/O pin multiplexed signal configuration register 323" bitfld.long 0x50C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x50C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x50C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x50C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x50C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x50C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x50C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x50C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x50C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x50C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x50C 0.--7. 1. "SSS,Source Signal Select" line.long 0x510 "MSCR_IO324,SIUL2 I/O pin multiplexed signal configuration register 324" bitfld.long 0x510 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x510 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x510 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x510 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x510 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x510 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x510 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x510 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x510 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x510 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x510 0.--7. 1. "SSS,Source Signal Select" line.long 0x514 "MSCR_IO325,SIUL2 I/O pin multiplexed signal configuration register 325" bitfld.long 0x514 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x514 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x514 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x514 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x514 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x514 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x514 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x514 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x514 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x514 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x514 0.--7. 1. "SSS,Source Signal Select" line.long 0x518 "MSCR_IO326,SIUL2 I/O pin multiplexed signal configuration register 326" bitfld.long 0x518 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x518 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x518 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x518 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x518 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x518 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x518 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x518 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x518 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x518 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x518 0.--7. 1. "SSS,Source Signal Select" line.long 0x51C "MSCR_IO327,SIUL2 I/O pin multiplexed signal configuration register 327" bitfld.long 0x51C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x51C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x51C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x51C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x51C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x51C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x51C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x51C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x51C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x51C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x51C 0.--7. 1. "SSS,Source Signal Select" line.long 0x520 "MSCR_IO328,SIUL2 I/O pin multiplexed signal configuration register 328" bitfld.long 0x520 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x520 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x520 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x520 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x520 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x520 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x520 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x520 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x520 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x520 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x520 0.--7. 1. "SSS,Source Signal Select" line.long 0x524 "MSCR_IO329,SIUL2 I/O pin multiplexed signal configuration register 329" bitfld.long 0x524 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x524 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x524 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x524 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x524 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x524 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x524 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x524 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x524 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x524 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x524 0.--7. 1. "SSS,Source Signal Select" line.long 0x528 "MSCR_IO330,SIUL2 I/O pin multiplexed signal configuration register 330" bitfld.long 0x528 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x528 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x528 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x528 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x528 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x528 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x528 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x528 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x528 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x528 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x528 0.--7. 1. "SSS,Source Signal Select" line.long 0x52C "MSCR_IO331,SIUL2 I/O pin multiplexed signal configuration register 331" bitfld.long 0x52C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x52C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x52C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x52C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x52C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x52C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x52C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x52C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x52C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x52C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x52C 0.--7. 1. "SSS,Source Signal Select" line.long 0x530 "MSCR_IO332,SIUL2 I/O pin multiplexed signal configuration register 332" bitfld.long 0x530 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x530 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x530 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x530 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x530 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x530 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x530 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x530 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x530 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x530 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x530 0.--7. 1. "SSS,Source Signal Select" line.long 0x534 "MSCR_IO333,SIUL2 I/O pin multiplexed signal configuration register 333" bitfld.long 0x534 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x534 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x534 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x534 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x534 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x534 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x534 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x534 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x534 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x534 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x534 0.--7. 1. "SSS,Source Signal Select" line.long 0x538 "MSCR_IO334,SIUL2 I/O pin multiplexed signal configuration register 334" bitfld.long 0x538 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x538 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x538 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x538 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x538 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x538 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x538 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x538 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x538 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x538 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x538 0.--7. 1. "SSS,Source Signal Select" line.long 0x53C "MSCR_IO335,SIUL2 I/O pin multiplexed signal configuration register 335" bitfld.long 0x53C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x53C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x53C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x53C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x53C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x53C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x53C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x53C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x53C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x53C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x53C 0.--7. 1. "SSS,Source Signal Select" line.long 0x540 "MSCR_IO336,SIUL2 I/O pin multiplexed signal configuration register 336" bitfld.long 0x540 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x540 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x540 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x540 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x540 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x540 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x540 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x540 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x540 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x540 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x540 0.--7. 1. "SSS,Source Signal Select" line.long 0x544 "MSCR_IO337,SIUL2 I/O pin multiplexed signal configuration register 337" bitfld.long 0x544 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x544 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x544 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x544 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x544 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x544 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x544 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x544 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x544 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x544 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x544 0.--7. 1. "SSS,Source Signal Select" line.long 0x548 "MSCR_IO338,SIUL2 I/O pin multiplexed signal configuration register 338" bitfld.long 0x548 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x548 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x548 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x548 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x548 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x548 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x548 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x548 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x548 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x548 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x548 0.--7. 1. "SSS,Source Signal Select" line.long 0x54C "MSCR_IO339,SIUL2 I/O pin multiplexed signal configuration register 339" bitfld.long 0x54C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x54C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x54C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x54C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x54C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x54C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x54C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x54C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x54C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x54C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x54C 0.--7. 1. "SSS,Source Signal Select" line.long 0x550 "MSCR_IO340,SIUL2 I/O pin multiplexed signal configuration register 340" bitfld.long 0x550 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x550 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x550 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x550 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x550 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x550 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x550 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x550 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x550 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x550 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x550 0.--7. 1. "SSS,Source Signal Select" line.long 0x554 "MSCR_IO341,SIUL2 I/O pin multiplexed signal configuration register 341" bitfld.long 0x554 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x554 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x554 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x554 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x554 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x554 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x554 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x554 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x554 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x554 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x554 0.--7. 1. "SSS,Source Signal Select" line.long 0x558 "MSCR_IO342,SIUL2 I/O pin multiplexed signal configuration register 342" bitfld.long 0x558 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x558 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x558 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x558 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x558 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x558 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x558 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x558 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x558 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x558 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x558 0.--7. 1. "SSS,Source Signal Select" line.long 0x55C "MSCR_IO343,SIUL2 I/O pin multiplexed signal configuration register 343" bitfld.long 0x55C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x55C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x55C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x55C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x55C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x55C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x55C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x55C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x55C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x55C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x55C 0.--7. 1. "SSS,Source Signal Select" line.long 0x560 "MSCR_IO344,SIUL2 I/O pin multiplexed signal configuration register 344" bitfld.long 0x560 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x560 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x560 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x560 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x560 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x560 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x560 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x560 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x560 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x560 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x560 0.--7. 1. "SSS,Source Signal Select" line.long 0x564 "MSCR_IO345,SIUL2 I/O pin multiplexed signal configuration register 345" bitfld.long 0x564 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x564 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x564 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x564 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x564 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x564 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x564 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x564 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x564 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x564 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x564 0.--7. 1. "SSS,Source Signal Select" line.long 0x568 "MSCR_IO346,SIUL2 I/O pin multiplexed signal configuration register 346" bitfld.long 0x568 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x568 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x568 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x568 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x568 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x568 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x568 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x568 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x568 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x568 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x568 0.--7. 1. "SSS,Source Signal Select" line.long 0x56C "MSCR_IO347,SIUL2 I/O pin multiplexed signal configuration register 347" bitfld.long 0x56C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x56C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x56C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x56C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x56C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x56C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x56C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x56C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x56C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x56C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x56C 0.--7. 1. "SSS,Source Signal Select" line.long 0x570 "MSCR_IO348,SIUL2 I/O pin multiplexed signal configuration register 348" bitfld.long 0x570 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x570 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x570 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x570 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x570 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x570 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x570 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x570 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x570 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x570 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x570 0.--7. 1. "SSS,Source Signal Select" line.long 0x574 "MSCR_IO349,SIUL2 I/O pin multiplexed signal configuration register 349" bitfld.long 0x574 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x574 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x574 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x574 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x574 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x574 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x574 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x574 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x574 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x574 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x574 0.--7. 1. "SSS,Source Signal Select" line.long 0x578 "MSCR_IO350,SIUL2 I/O pin multiplexed signal configuration register 350" bitfld.long 0x578 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x578 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x578 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x578 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x578 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x578 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x578 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x578 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x578 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x578 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x578 0.--7. 1. "SSS,Source Signal Select" line.long 0x57C "MSCR_IO351,SIUL2 I/O pin multiplexed signal configuration register 351" bitfld.long 0x57C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x57C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x57C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x57C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x57C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x57C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x57C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x57C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x57C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x57C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x57C 0.--7. 1. "SSS,Source Signal Select" line.long 0x580 "MSCR_IO352,SIUL2 I/O pin multiplexed signal configuration register 352" bitfld.long 0x580 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x580 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x580 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x580 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x580 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x580 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x580 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x580 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x580 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x580 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x580 0.--7. 1. "SSS,Source Signal Select" line.long 0x584 "MSCR_IO353,SIUL2 I/O pin multiplexed signal configuration register 353" bitfld.long 0x584 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x584 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x584 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x584 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x584 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x584 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x584 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x584 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x584 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x584 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x584 0.--7. 1. "SSS,Source Signal Select" line.long 0x588 "MSCR_IO354,SIUL2 I/O pin multiplexed signal configuration register 354" bitfld.long 0x588 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x588 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x588 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x588 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x588 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x588 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x588 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x588 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x588 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x588 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x588 0.--7. 1. "SSS,Source Signal Select" line.long 0x58C "MSCR_IO355,SIUL2 I/O pin multiplexed signal configuration register 355" bitfld.long 0x58C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x58C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x58C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x58C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x58C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x58C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x58C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x58C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x58C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x58C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x58C 0.--7. 1. "SSS,Source Signal Select" line.long 0x590 "MSCR_IO356,SIUL2 I/O pin multiplexed signal configuration register 356" bitfld.long 0x590 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x590 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x590 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x590 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x590 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x590 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x590 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x590 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x590 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x590 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x590 0.--7. 1. "SSS,Source Signal Select" line.long 0x594 "MSCR_IO357,SIUL2 I/O pin multiplexed signal configuration register 357" bitfld.long 0x594 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x594 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x594 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x594 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x594 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x594 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x594 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x594 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x594 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x594 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x594 0.--7. 1. "SSS,Source Signal Select" line.long 0x598 "MSCR_IO358,SIUL2 I/O pin multiplexed signal configuration register 358" bitfld.long 0x598 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x598 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x598 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x598 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x598 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x598 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x598 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x598 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x598 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x598 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x598 0.--7. 1. "SSS,Source Signal Select" line.long 0x59C "MSCR_IO359,SIUL2 I/O pin multiplexed signal configuration register 359" bitfld.long 0x59C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x59C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x59C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x59C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x59C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x59C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x59C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x59C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x59C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x59C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x59C 0.--7. 1. "SSS,Source Signal Select" line.long 0x5A0 "MSCR_IO360,SIUL2 I/O pin multiplexed signal configuration register 360" bitfld.long 0x5A0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5A0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5A0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5A0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5A0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5A0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5A0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5A0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5A0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5A0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5A0 0.--7. 1. "SSS,Source Signal Select" line.long 0x5A4 "MSCR_IO361,SIUL2 I/O pin multiplexed signal configuration register 361" bitfld.long 0x5A4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5A4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5A4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5A4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5A4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5A4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5A4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5A4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5A4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5A4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5A4 0.--7. 1. "SSS,Source Signal Select" line.long 0x5A8 "MSCR_IO362,SIUL2 I/O pin multiplexed signal configuration register 362" bitfld.long 0x5A8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5A8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5A8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5A8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5A8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5A8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5A8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5A8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5A8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5A8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5A8 0.--7. 1. "SSS,Source Signal Select" line.long 0x5AC "MSCR_IO363,SIUL2 I/O pin multiplexed signal configuration register 363" bitfld.long 0x5AC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5AC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5AC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5AC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5AC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5AC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5AC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5AC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5AC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5AC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5AC 0.--7. 1. "SSS,Source Signal Select" line.long 0x5B0 "MSCR_IO364,SIUL2 I/O pin multiplexed signal configuration register 364" bitfld.long 0x5B0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5B0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5B0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5B0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5B0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5B0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5B0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5B0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5B0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5B0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5B0 0.--7. 1. "SSS,Source Signal Select" line.long 0x5B4 "MSCR_IO365,SIUL2 I/O pin multiplexed signal configuration register 365" bitfld.long 0x5B4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5B4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5B4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5B4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5B4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5B4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5B4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5B4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5B4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5B4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5B4 0.--7. 1. "SSS,Source Signal Select" line.long 0x5B8 "MSCR_IO366,SIUL2 I/O pin multiplexed signal configuration register 366" bitfld.long 0x5B8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5B8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5B8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5B8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5B8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5B8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5B8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5B8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5B8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5B8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5B8 0.--7. 1. "SSS,Source Signal Select" line.long 0x5BC "MSCR_IO367,SIUL2 I/O pin multiplexed signal configuration register 367" bitfld.long 0x5BC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5BC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5BC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5BC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5BC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5BC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5BC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5BC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5BC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5BC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5BC 0.--7. 1. "SSS,Source Signal Select" line.long 0x5C0 "MSCR_IO368,SIUL2 I/O pin multiplexed signal configuration register 368" bitfld.long 0x5C0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5C0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5C0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5C0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5C0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5C0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5C0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5C0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5C0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5C0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5C0 0.--7. 1. "SSS,Source Signal Select" line.long 0x5C4 "MSCR_IO369,SIUL2 I/O pin multiplexed signal configuration register 369" bitfld.long 0x5C4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5C4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5C4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5C4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5C4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5C4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5C4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5C4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5C4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5C4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5C4 0.--7. 1. "SSS,Source Signal Select" line.long 0x5C8 "MSCR_IO370,SIUL2 I/O pin multiplexed signal configuration register 370" bitfld.long 0x5C8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5C8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5C8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5C8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5C8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5C8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5C8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5C8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5C8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5C8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5C8 0.--7. 1. "SSS,Source Signal Select" line.long 0x5CC "MSCR_IO371,SIUL2 I/O pin multiplexed signal configuration register 371" bitfld.long 0x5CC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5CC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5CC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5CC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5CC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5CC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5CC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5CC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5CC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5CC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5CC 0.--7. 1. "SSS,Source Signal Select" line.long 0x5D0 "MSCR_IO372,SIUL2 I/O pin multiplexed signal configuration register 372" bitfld.long 0x5D0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5D0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5D0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5D0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5D0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5D0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5D0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5D0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5D0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5D0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5D0 0.--7. 1. "SSS,Source Signal Select" line.long 0x5D4 "MSCR_IO373,SIUL2 I/O pin multiplexed signal configuration register 373" bitfld.long 0x5D4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5D4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5D4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5D4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5D4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5D4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5D4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5D4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5D4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5D4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5D4 0.--7. 1. "SSS,Source Signal Select" line.long 0x5D8 "MSCR_IO374,SIUL2 I/O pin multiplexed signal configuration register 374" bitfld.long 0x5D8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5D8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5D8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5D8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5D8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5D8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5D8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5D8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5D8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5D8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5D8 0.--7. 1. "SSS,Source Signal Select" line.long 0x5DC "MSCR_IO375,SIUL2 I/O pin multiplexed signal configuration register 375" bitfld.long 0x5DC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5DC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5DC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5DC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5DC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5DC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5DC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5DC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5DC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5DC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5DC 0.--7. 1. "SSS,Source Signal Select" line.long 0x5E0 "MSCR_IO376,SIUL2 I/O pin multiplexed signal configuration register 376" bitfld.long 0x5E0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5E0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5E0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5E0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5E0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5E0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5E0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5E0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5E0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5E0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5E0 0.--7. 1. "SSS,Source Signal Select" line.long 0x5E4 "MSCR_IO377,SIUL2 I/O pin multiplexed signal configuration register 377" bitfld.long 0x5E4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5E4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5E4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5E4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5E4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5E4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5E4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5E4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5E4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5E4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5E4 0.--7. 1. "SSS,Source Signal Select" line.long 0x5E8 "MSCR_IO378,SIUL2 I/O pin multiplexed signal configuration register 378" bitfld.long 0x5E8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5E8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5E8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5E8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5E8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5E8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5E8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5E8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5E8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5E8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5E8 0.--7. 1. "SSS,Source Signal Select" line.long 0x5EC "MSCR_IO379,SIUL2 I/O pin multiplexed signal configuration register 379" bitfld.long 0x5EC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5EC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5EC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5EC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5EC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5EC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5EC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5EC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5EC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5EC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5EC 0.--7. 1. "SSS,Source Signal Select" line.long 0x5F0 "MSCR_IO380,SIUL2 I/O pin multiplexed signal configuration register 380" bitfld.long 0x5F0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5F0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5F0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5F0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5F0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5F0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5F0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5F0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5F0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5F0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5F0 0.--7. 1. "SSS,Source Signal Select" line.long 0x5F4 "MSCR_IO381,SIUL2 I/O pin multiplexed signal configuration register 381" bitfld.long 0x5F4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5F4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5F4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5F4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5F4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5F4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5F4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5F4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5F4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5F4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5F4 0.--7. 1. "SSS,Source Signal Select" line.long 0x5F8 "MSCR_IO382,SIUL2 I/O pin multiplexed signal configuration register 382" bitfld.long 0x5F8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5F8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5F8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5F8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5F8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5F8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5F8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5F8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5F8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5F8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5F8 0.--7. 1. "SSS,Source Signal Select" line.long 0x5FC "MSCR_IO383,SIUL2 I/O pin multiplexed signal configuration register 383" bitfld.long 0x5FC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x5FC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x5FC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x5FC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x5FC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5FC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5FC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x5FC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x5FC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x5FC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x5FC 0.--7. 1. "SSS,Source Signal Select" line.long 0x600 "MSCR_IO384,SIUL2 I/O pin multiplexed signal configuration register 384" bitfld.long 0x600 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x600 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x600 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x600 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x600 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x600 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x600 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x600 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x600 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x600 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x600 0.--7. 1. "SSS,Source Signal Select" line.long 0x604 "MSCR_IO385,SIUL2 I/O pin multiplexed signal configuration register 385" bitfld.long 0x604 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x604 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x604 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x604 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x604 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x604 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x604 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x604 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x604 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x604 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x604 0.--7. 1. "SSS,Source Signal Select" line.long 0x608 "MSCR_IO386,SIUL2 I/O pin multiplexed signal configuration register 386" bitfld.long 0x608 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x608 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x608 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x608 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x608 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x608 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x608 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x608 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x608 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x608 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x608 0.--7. 1. "SSS,Source Signal Select" line.long 0x60C "MSCR_IO387,SIUL2 I/O pin multiplexed signal configuration register 387" bitfld.long 0x60C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x60C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x60C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x60C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x60C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x60C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x60C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x60C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x60C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x60C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x60C 0.--7. 1. "SSS,Source Signal Select" line.long 0x610 "MSCR_IO388,SIUL2 I/O pin multiplexed signal configuration register 388" bitfld.long 0x610 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x610 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x610 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x610 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x610 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x610 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x610 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x610 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x610 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x610 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x610 0.--7. 1. "SSS,Source Signal Select" line.long 0x614 "MSCR_IO389,SIUL2 I/O pin multiplexed signal configuration register 389" bitfld.long 0x614 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x614 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x614 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x614 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x614 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x614 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x614 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x614 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x614 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x614 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x614 0.--7. 1. "SSS,Source Signal Select" line.long 0x618 "MSCR_IO390,SIUL2 I/O pin multiplexed signal configuration register 390" bitfld.long 0x618 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x618 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x618 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x618 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x618 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x618 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x618 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x618 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x618 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x618 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x618 0.--7. 1. "SSS,Source Signal Select" line.long 0x61C "MSCR_IO391,SIUL2 I/O pin multiplexed signal configuration register 391" bitfld.long 0x61C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x61C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x61C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x61C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x61C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x61C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x61C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x61C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x61C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x61C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x61C 0.--7. 1. "SSS,Source Signal Select" line.long 0x620 "MSCR_IO392,SIUL2 I/O pin multiplexed signal configuration register 392" bitfld.long 0x620 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x620 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x620 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x620 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x620 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x620 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x620 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x620 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x620 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x620 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x620 0.--7. 1. "SSS,Source Signal Select" line.long 0x624 "MSCR_IO393,SIUL2 I/O pin multiplexed signal configuration register 393" bitfld.long 0x624 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x624 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x624 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x624 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x624 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x624 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x624 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x624 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x624 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x624 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x624 0.--7. 1. "SSS,Source Signal Select" line.long 0x628 "MSCR_IO394,SIUL2 I/O pin multiplexed signal configuration register 394" bitfld.long 0x628 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x628 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x628 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x628 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x628 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x628 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x628 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x628 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x628 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x628 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x628 0.--7. 1. "SSS,Source Signal Select" line.long 0x62C "MSCR_IO395,SIUL2 I/O pin multiplexed signal configuration register 395" bitfld.long 0x62C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x62C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x62C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x62C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x62C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x62C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x62C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x62C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x62C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x62C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x62C 0.--7. 1. "SSS,Source Signal Select" line.long 0x630 "MSCR_IO396,SIUL2 I/O pin multiplexed signal configuration register 396" bitfld.long 0x630 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x630 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x630 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x630 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x630 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x630 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x630 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x630 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x630 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x630 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x630 0.--7. 1. "SSS,Source Signal Select" line.long 0x634 "MSCR_IO397,SIUL2 I/O pin multiplexed signal configuration register 397" bitfld.long 0x634 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x634 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x634 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x634 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x634 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x634 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x634 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x634 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x634 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x634 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x634 0.--7. 1. "SSS,Source Signal Select" line.long 0x638 "MSCR_IO398,SIUL2 I/O pin multiplexed signal configuration register 398" bitfld.long 0x638 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x638 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x638 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x638 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x638 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x638 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x638 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x638 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x638 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x638 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x638 0.--7. 1. "SSS,Source Signal Select" line.long 0x63C "MSCR_IO399,SIUL2 I/O pin multiplexed signal configuration register 399" bitfld.long 0x63C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x63C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x63C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x63C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x63C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x63C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x63C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x63C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x63C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x63C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x63C 0.--7. 1. "SSS,Source Signal Select" line.long 0x640 "MSCR_IO400,SIUL2 I/O pin multiplexed signal configuration register 400" bitfld.long 0x640 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x640 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x640 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x640 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x640 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x640 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x640 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x640 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x640 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x640 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x640 0.--7. 1. "SSS,Source Signal Select" line.long 0x644 "MSCR_IO401,SIUL2 I/O pin multiplexed signal configuration register 401" bitfld.long 0x644 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x644 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x644 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x644 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x644 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x644 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x644 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x644 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x644 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x644 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x644 0.--7. 1. "SSS,Source Signal Select" line.long 0x648 "MSCR_IO402,SIUL2 I/O pin multiplexed signal configuration register 402" bitfld.long 0x648 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x648 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x648 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x648 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x648 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x648 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x648 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x648 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x648 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x648 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x648 0.--7. 1. "SSS,Source Signal Select" line.long 0x64C "MSCR_IO403,SIUL2 I/O pin multiplexed signal configuration register 403" bitfld.long 0x64C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x64C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x64C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x64C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x64C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x64C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x64C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x64C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x64C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x64C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x64C 0.--7. 1. "SSS,Source Signal Select" line.long 0x650 "MSCR_IO404,SIUL2 I/O pin multiplexed signal configuration register 404" bitfld.long 0x650 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x650 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x650 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x650 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x650 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x650 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x650 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x650 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x650 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x650 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x650 0.--7. 1. "SSS,Source Signal Select" line.long 0x654 "MSCR_IO405,SIUL2 I/O pin multiplexed signal configuration register 405" bitfld.long 0x654 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x654 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x654 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x654 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x654 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x654 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x654 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x654 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x654 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x654 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x654 0.--7. 1. "SSS,Source Signal Select" line.long 0x658 "MSCR_IO406,SIUL2 I/O pin multiplexed signal configuration register 406" bitfld.long 0x658 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x658 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x658 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x658 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x658 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x658 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x658 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x658 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x658 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x658 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x658 0.--7. 1. "SSS,Source Signal Select" line.long 0x65C "MSCR_IO407,SIUL2 I/O pin multiplexed signal configuration register 407" bitfld.long 0x65C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x65C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x65C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x65C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x65C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x65C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x65C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x65C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x65C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x65C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x65C 0.--7. 1. "SSS,Source Signal Select" line.long 0x660 "MSCR_IO408,SIUL2 I/O pin multiplexed signal configuration register 408" bitfld.long 0x660 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x660 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x660 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x660 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x660 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x660 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x660 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x660 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x660 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x660 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x660 0.--7. 1. "SSS,Source Signal Select" line.long 0x664 "MSCR_IO409,SIUL2 I/O pin multiplexed signal configuration register 409" bitfld.long 0x664 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x664 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x664 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x664 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x664 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x664 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x664 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x664 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x664 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x664 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x664 0.--7. 1. "SSS,Source Signal Select" line.long 0x668 "MSCR_IO410,SIUL2 I/O pin multiplexed signal configuration register 410" bitfld.long 0x668 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x668 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x668 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x668 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x668 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x668 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x668 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x668 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x668 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x668 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x668 0.--7. 1. "SSS,Source Signal Select" line.long 0x66C "MSCR_IO411,SIUL2 I/O pin multiplexed signal configuration register 411" bitfld.long 0x66C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x66C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x66C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x66C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x66C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x66C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x66C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x66C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x66C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x66C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x66C 0.--7. 1. "SSS,Source Signal Select" line.long 0x670 "MSCR_IO412,SIUL2 I/O pin multiplexed signal configuration register 412" bitfld.long 0x670 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x670 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x670 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x670 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x670 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x670 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x670 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x670 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x670 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x670 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x670 0.--7. 1. "SSS,Source Signal Select" line.long 0x674 "MSCR_IO413,SIUL2 I/O pin multiplexed signal configuration register 413" bitfld.long 0x674 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x674 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x674 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x674 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x674 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x674 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x674 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x674 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x674 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x674 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x674 0.--7. 1. "SSS,Source Signal Select" line.long 0x678 "MSCR_IO414,SIUL2 I/O pin multiplexed signal configuration register 414" bitfld.long 0x678 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x678 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x678 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x678 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x678 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x678 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x678 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x678 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x678 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x678 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x678 0.--7. 1. "SSS,Source Signal Select" line.long 0x67C "MSCR_IO415,SIUL2 I/O pin multiplexed signal configuration register 415" bitfld.long 0x67C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x67C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x67C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x67C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x67C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x67C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x67C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x67C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x67C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x67C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x67C 0.--7. 1. "SSS,Source Signal Select" line.long 0x680 "MSCR_IO416,SIUL2 I/O pin multiplexed signal configuration register 416" bitfld.long 0x680 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x680 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x680 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x680 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x680 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x680 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x680 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x680 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x680 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x680 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x680 0.--7. 1. "SSS,Source Signal Select" line.long 0x684 "MSCR_IO417,SIUL2 I/O pin multiplexed signal configuration register 417" bitfld.long 0x684 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x684 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x684 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x684 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x684 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x684 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x684 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x684 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x684 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x684 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x684 0.--7. 1. "SSS,Source Signal Select" line.long 0x688 "MSCR_IO418,SIUL2 I/O pin multiplexed signal configuration register 418" bitfld.long 0x688 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x688 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x688 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x688 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x688 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x688 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x688 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x688 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x688 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x688 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x688 0.--7. 1. "SSS,Source Signal Select" line.long 0x68C "MSCR_IO419,SIUL2 I/O pin multiplexed signal configuration register 419" bitfld.long 0x68C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x68C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x68C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x68C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x68C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x68C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x68C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x68C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x68C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x68C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x68C 0.--7. 1. "SSS,Source Signal Select" line.long 0x690 "MSCR_IO420,SIUL2 I/O pin multiplexed signal configuration register 420" bitfld.long 0x690 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x690 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x690 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x690 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x690 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x690 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x690 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x690 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x690 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x690 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x690 0.--7. 1. "SSS,Source Signal Select" line.long 0x694 "MSCR_IO421,SIUL2 I/O pin multiplexed signal configuration register 421" bitfld.long 0x694 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x694 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x694 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x694 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x694 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x694 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x694 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x694 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x694 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x694 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x694 0.--7. 1. "SSS,Source Signal Select" line.long 0x698 "MSCR_IO422,SIUL2 I/O pin multiplexed signal configuration register 422" bitfld.long 0x698 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x698 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x698 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x698 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x698 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x698 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x698 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x698 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x698 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x698 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x698 0.--7. 1. "SSS,Source Signal Select" line.long 0x69C "MSCR_IO423,SIUL2 I/O pin multiplexed signal configuration register 423" bitfld.long 0x69C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x69C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x69C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x69C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x69C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x69C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x69C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x69C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x69C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x69C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x69C 0.--7. 1. "SSS,Source Signal Select" line.long 0x6A0 "MSCR_IO424,SIUL2 I/O pin multiplexed signal configuration register 424" bitfld.long 0x6A0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6A0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6A0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6A0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6A0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6A0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6A0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6A0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6A0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6A0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6A0 0.--7. 1. "SSS,Source Signal Select" line.long 0x6A4 "MSCR_IO425,SIUL2 I/O pin multiplexed signal configuration register 425" bitfld.long 0x6A4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6A4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6A4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6A4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6A4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6A4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6A4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6A4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6A4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6A4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6A4 0.--7. 1. "SSS,Source Signal Select" line.long 0x6A8 "MSCR_IO426,SIUL2 I/O pin multiplexed signal configuration register 426" bitfld.long 0x6A8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6A8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6A8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6A8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6A8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6A8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6A8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6A8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6A8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6A8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6A8 0.--7. 1. "SSS,Source Signal Select" line.long 0x6AC "MSCR_IO427,SIUL2 I/O pin multiplexed signal configuration register 427" bitfld.long 0x6AC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6AC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6AC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6AC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6AC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6AC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6AC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6AC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6AC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6AC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6AC 0.--7. 1. "SSS,Source Signal Select" line.long 0x6B0 "MSCR_IO428,SIUL2 I/O pin multiplexed signal configuration register 428" bitfld.long 0x6B0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6B0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6B0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6B0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6B0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6B0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6B0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6B0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6B0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6B0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6B0 0.--7. 1. "SSS,Source Signal Select" line.long 0x6B4 "MSCR_IO429,SIUL2 I/O pin multiplexed signal configuration register 429" bitfld.long 0x6B4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6B4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6B4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6B4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6B4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6B4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6B4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6B4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6B4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6B4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6B4 0.--7. 1. "SSS,Source Signal Select" line.long 0x6B8 "MSCR_IO430,SIUL2 I/O pin multiplexed signal configuration register 430" bitfld.long 0x6B8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6B8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6B8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6B8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6B8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6B8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6B8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6B8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6B8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6B8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6B8 0.--7. 1. "SSS,Source Signal Select" line.long 0x6BC "MSCR_IO431,SIUL2 I/O pin multiplexed signal configuration register 431" bitfld.long 0x6BC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6BC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6BC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6BC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6BC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6BC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6BC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6BC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6BC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6BC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6BC 0.--7. 1. "SSS,Source Signal Select" line.long 0x6C0 "MSCR_IO432,SIUL2 I/O pin multiplexed signal configuration register 432" bitfld.long 0x6C0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6C0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6C0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6C0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6C0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6C0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6C0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6C0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6C0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6C0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6C0 0.--7. 1. "SSS,Source Signal Select" line.long 0x6C4 "MSCR_IO433,SIUL2 I/O pin multiplexed signal configuration register 433" bitfld.long 0x6C4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6C4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6C4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6C4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6C4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6C4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6C4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6C4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6C4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6C4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6C4 0.--7. 1. "SSS,Source Signal Select" line.long 0x6C8 "MSCR_IO434,SIUL2 I/O pin multiplexed signal configuration register 434" bitfld.long 0x6C8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6C8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6C8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6C8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6C8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6C8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6C8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6C8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6C8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6C8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6C8 0.--7. 1. "SSS,Source Signal Select" line.long 0x6CC "MSCR_IO435,SIUL2 I/O pin multiplexed signal configuration register 435" bitfld.long 0x6CC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6CC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6CC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6CC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6CC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6CC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6CC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6CC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6CC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6CC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6CC 0.--7. 1. "SSS,Source Signal Select" line.long 0x6D0 "MSCR_IO436,SIUL2 I/O pin multiplexed signal configuration register 436" bitfld.long 0x6D0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6D0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6D0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6D0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6D0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6D0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6D0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6D0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6D0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6D0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6D0 0.--7. 1. "SSS,Source Signal Select" line.long 0x6D4 "MSCR_IO437,SIUL2 I/O pin multiplexed signal configuration register 437" bitfld.long 0x6D4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6D4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6D4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6D4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6D4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6D4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6D4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6D4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6D4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6D4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6D4 0.--7. 1. "SSS,Source Signal Select" line.long 0x6D8 "MSCR_IO438,SIUL2 I/O pin multiplexed signal configuration register 438" bitfld.long 0x6D8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6D8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6D8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6D8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6D8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6D8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6D8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6D8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6D8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6D8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6D8 0.--7. 1. "SSS,Source Signal Select" line.long 0x6DC "MSCR_IO439,SIUL2 I/O pin multiplexed signal configuration register 439" bitfld.long 0x6DC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6DC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6DC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6DC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6DC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6DC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6DC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6DC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6DC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6DC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6DC 0.--7. 1. "SSS,Source Signal Select" line.long 0x6E0 "MSCR_IO440,SIUL2 I/O pin multiplexed signal configuration register 440" bitfld.long 0x6E0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6E0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6E0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6E0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6E0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6E0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6E0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6E0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6E0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6E0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6E0 0.--7. 1. "SSS,Source Signal Select" line.long 0x6E4 "MSCR_IO441,SIUL2 I/O pin multiplexed signal configuration register 441" bitfld.long 0x6E4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6E4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6E4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6E4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6E4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6E4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6E4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6E4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6E4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6E4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6E4 0.--7. 1. "SSS,Source Signal Select" line.long 0x6E8 "MSCR_IO442,SIUL2 I/O pin multiplexed signal configuration register 442" bitfld.long 0x6E8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6E8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6E8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6E8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6E8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6E8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6E8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6E8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6E8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6E8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6E8 0.--7. 1. "SSS,Source Signal Select" line.long 0x6EC "MSCR_IO443,SIUL2 I/O pin multiplexed signal configuration register 443" bitfld.long 0x6EC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6EC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6EC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6EC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6EC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6EC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6EC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6EC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6EC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6EC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6EC 0.--7. 1. "SSS,Source Signal Select" line.long 0x6F0 "MSCR_IO444,SIUL2 I/O pin multiplexed signal configuration register 444" bitfld.long 0x6F0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6F0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6F0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6F0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6F0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6F0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6F0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6F0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6F0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6F0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6F0 0.--7. 1. "SSS,Source Signal Select" line.long 0x6F4 "MSCR_IO445,SIUL2 I/O pin multiplexed signal configuration register 445" bitfld.long 0x6F4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6F4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6F4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6F4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6F4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6F4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6F4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6F4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6F4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6F4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6F4 0.--7. 1. "SSS,Source Signal Select" line.long 0x6F8 "MSCR_IO446,SIUL2 I/O pin multiplexed signal configuration register 446" bitfld.long 0x6F8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6F8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6F8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6F8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6F8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6F8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6F8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6F8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6F8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6F8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6F8 0.--7. 1. "SSS,Source Signal Select" line.long 0x6FC "MSCR_IO447,SIUL2 I/O pin multiplexed signal configuration register 447" bitfld.long 0x6FC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x6FC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x6FC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x6FC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x6FC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6FC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6FC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x6FC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x6FC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x6FC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x6FC 0.--7. 1. "SSS,Source Signal Select" line.long 0x700 "MSCR_IO448,SIUL2 I/O pin multiplexed signal configuration register 448" bitfld.long 0x700 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x700 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x700 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x700 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x700 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x700 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x700 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x700 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x700 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x700 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x700 0.--7. 1. "SSS,Source Signal Select" line.long 0x704 "MSCR_IO449,SIUL2 I/O pin multiplexed signal configuration register 449" bitfld.long 0x704 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x704 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x704 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x704 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x704 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x704 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x704 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x704 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x704 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x704 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x704 0.--7. 1. "SSS,Source Signal Select" line.long 0x708 "MSCR_IO450,SIUL2 I/O pin multiplexed signal configuration register 450" bitfld.long 0x708 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x708 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x708 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x708 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x708 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x708 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x708 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x708 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x708 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x708 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x708 0.--7. 1. "SSS,Source Signal Select" line.long 0x70C "MSCR_IO451,SIUL2 I/O pin multiplexed signal configuration register 451" bitfld.long 0x70C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x70C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x70C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x70C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x70C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x70C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x70C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x70C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x70C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x70C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x70C 0.--7. 1. "SSS,Source Signal Select" line.long 0x710 "MSCR_IO452,SIUL2 I/O pin multiplexed signal configuration register 452" bitfld.long 0x710 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x710 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x710 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x710 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x710 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x710 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x710 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x710 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x710 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x710 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x710 0.--7. 1. "SSS,Source Signal Select" line.long 0x714 "MSCR_IO453,SIUL2 I/O pin multiplexed signal configuration register 453" bitfld.long 0x714 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x714 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x714 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x714 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x714 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x714 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x714 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x714 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x714 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x714 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x714 0.--7. 1. "SSS,Source Signal Select" line.long 0x718 "MSCR_IO454,SIUL2 I/O pin multiplexed signal configuration register 454" bitfld.long 0x718 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x718 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x718 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x718 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x718 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x718 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x718 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x718 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x718 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x718 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x718 0.--7. 1. "SSS,Source Signal Select" line.long 0x71C "MSCR_IO455,SIUL2 I/O pin multiplexed signal configuration register 455" bitfld.long 0x71C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x71C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x71C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x71C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x71C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x71C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x71C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x71C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x71C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x71C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x71C 0.--7. 1. "SSS,Source Signal Select" line.long 0x720 "MSCR_IO456,SIUL2 I/O pin multiplexed signal configuration register 456" bitfld.long 0x720 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x720 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x720 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x720 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x720 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x720 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x720 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x720 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x720 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x720 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x720 0.--7. 1. "SSS,Source Signal Select" line.long 0x724 "MSCR_IO457,SIUL2 I/O pin multiplexed signal configuration register 457" bitfld.long 0x724 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x724 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x724 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x724 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x724 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x724 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x724 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x724 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x724 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x724 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x724 0.--7. 1. "SSS,Source Signal Select" line.long 0x728 "MSCR_IO458,SIUL2 I/O pin multiplexed signal configuration register 458" bitfld.long 0x728 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x728 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x728 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x728 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x728 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x728 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x728 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x728 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x728 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x728 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x728 0.--7. 1. "SSS,Source Signal Select" line.long 0x72C "MSCR_IO459,SIUL2 I/O pin multiplexed signal configuration register 459" bitfld.long 0x72C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x72C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x72C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x72C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x72C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x72C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x72C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x72C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x72C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x72C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x72C 0.--7. 1. "SSS,Source Signal Select" line.long 0x730 "MSCR_IO460,SIUL2 I/O pin multiplexed signal configuration register 460" bitfld.long 0x730 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x730 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x730 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x730 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x730 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x730 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x730 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x730 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x730 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x730 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x730 0.--7. 1. "SSS,Source Signal Select" line.long 0x734 "MSCR_IO461,SIUL2 I/O pin multiplexed signal configuration register 461" bitfld.long 0x734 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x734 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x734 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x734 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x734 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x734 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x734 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x734 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x734 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x734 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x734 0.--7. 1. "SSS,Source Signal Select" line.long 0x738 "MSCR_IO462,SIUL2 I/O pin multiplexed signal configuration register 462" bitfld.long 0x738 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x738 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x738 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x738 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x738 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x738 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x738 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x738 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x738 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x738 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x738 0.--7. 1. "SSS,Source Signal Select" line.long 0x73C "MSCR_IO463,SIUL2 I/O pin multiplexed signal configuration register 463" bitfld.long 0x73C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x73C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x73C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x73C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x73C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x73C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x73C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x73C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x73C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x73C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x73C 0.--7. 1. "SSS,Source Signal Select" line.long 0x740 "MSCR_IO464,SIUL2 I/O pin multiplexed signal configuration register 464" bitfld.long 0x740 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x740 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x740 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x740 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x740 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x740 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x740 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x740 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x740 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x740 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x740 0.--7. 1. "SSS,Source Signal Select" line.long 0x744 "MSCR_IO465,SIUL2 I/O pin multiplexed signal configuration register 465" bitfld.long 0x744 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x744 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x744 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x744 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x744 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x744 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x744 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x744 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x744 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x744 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x744 0.--7. 1. "SSS,Source Signal Select" line.long 0x748 "MSCR_IO466,SIUL2 I/O pin multiplexed signal configuration register 466" bitfld.long 0x748 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x748 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x748 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x748 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x748 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x748 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x748 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x748 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x748 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x748 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x748 0.--7. 1. "SSS,Source Signal Select" line.long 0x74C "MSCR_IO467,SIUL2 I/O pin multiplexed signal configuration register 467" bitfld.long 0x74C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x74C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x74C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x74C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x74C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x74C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x74C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x74C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x74C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x74C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x74C 0.--7. 1. "SSS,Source Signal Select" line.long 0x750 "MSCR_IO468,SIUL2 I/O pin multiplexed signal configuration register 468" bitfld.long 0x750 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x750 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x750 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x750 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x750 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x750 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x750 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x750 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x750 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x750 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x750 0.--7. 1. "SSS,Source Signal Select" line.long 0x754 "MSCR_IO469,SIUL2 I/O pin multiplexed signal configuration register 469" bitfld.long 0x754 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x754 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x754 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x754 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x754 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x754 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x754 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x754 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x754 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x754 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x754 0.--7. 1. "SSS,Source Signal Select" line.long 0x758 "MSCR_IO470,SIUL2 I/O pin multiplexed signal configuration register 470" bitfld.long 0x758 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x758 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x758 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x758 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x758 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x758 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x758 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x758 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x758 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x758 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x758 0.--7. 1. "SSS,Source Signal Select" line.long 0x75C "MSCR_IO471,SIUL2 I/O pin multiplexed signal configuration register 471" bitfld.long 0x75C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x75C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x75C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x75C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x75C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x75C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x75C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x75C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x75C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x75C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x75C 0.--7. 1. "SSS,Source Signal Select" line.long 0x760 "MSCR_IO472,SIUL2 I/O pin multiplexed signal configuration register 472" bitfld.long 0x760 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x760 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x760 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x760 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x760 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x760 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x760 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x760 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x760 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x760 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x760 0.--7. 1. "SSS,Source Signal Select" line.long 0x764 "MSCR_IO473,SIUL2 I/O pin multiplexed signal configuration register 473" bitfld.long 0x764 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x764 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x764 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x764 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x764 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x764 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x764 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x764 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x764 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x764 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x764 0.--7. 1. "SSS,Source Signal Select" line.long 0x768 "MSCR_IO474,SIUL2 I/O pin multiplexed signal configuration register 474" bitfld.long 0x768 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x768 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x768 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x768 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x768 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x768 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x768 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x768 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x768 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x768 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x768 0.--7. 1. "SSS,Source Signal Select" line.long 0x76C "MSCR_IO475,SIUL2 I/O pin multiplexed signal configuration register 475" bitfld.long 0x76C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x76C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x76C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x76C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x76C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x76C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x76C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x76C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x76C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x76C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x76C 0.--7. 1. "SSS,Source Signal Select" line.long 0x770 "MSCR_IO476,SIUL2 I/O pin multiplexed signal configuration register 476" bitfld.long 0x770 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x770 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x770 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x770 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x770 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x770 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x770 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x770 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x770 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x770 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x770 0.--7. 1. "SSS,Source Signal Select" line.long 0x774 "MSCR_IO477,SIUL2 I/O pin multiplexed signal configuration register 477" bitfld.long 0x774 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x774 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x774 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x774 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x774 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x774 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x774 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x774 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x774 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x774 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x774 0.--7. 1. "SSS,Source Signal Select" line.long 0x778 "MSCR_IO478,SIUL2 I/O pin multiplexed signal configuration register 478" bitfld.long 0x778 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x778 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x778 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x778 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x778 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x778 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x778 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x778 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x778 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x778 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x778 0.--7. 1. "SSS,Source Signal Select" line.long 0x77C "MSCR_IO479,SIUL2 I/O pin multiplexed signal configuration register 479" bitfld.long 0x77C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x77C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x77C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x77C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x77C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x77C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x77C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x77C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x77C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x77C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x77C 0.--7. 1. "SSS,Source Signal Select" line.long 0x780 "MSCR_IO480,SIUL2 I/O pin multiplexed signal configuration register 480" bitfld.long 0x780 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x780 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x780 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x780 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x780 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x780 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x780 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x780 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x780 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x780 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x780 0.--7. 1. "SSS,Source Signal Select" line.long 0x784 "MSCR_IO481,SIUL2 I/O pin multiplexed signal configuration register 481" bitfld.long 0x784 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x784 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x784 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x784 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x784 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x784 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x784 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x784 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x784 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x784 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x784 0.--7. 1. "SSS,Source Signal Select" line.long 0x788 "MSCR_IO482,SIUL2 I/O pin multiplexed signal configuration register 482" bitfld.long 0x788 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x788 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x788 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x788 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x788 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x788 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x788 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x788 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x788 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x788 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x788 0.--7. 1. "SSS,Source Signal Select" line.long 0x78C "MSCR_IO483,SIUL2 I/O pin multiplexed signal configuration register 483" bitfld.long 0x78C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x78C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x78C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x78C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x78C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x78C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x78C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x78C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x78C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x78C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x78C 0.--7. 1. "SSS,Source Signal Select" line.long 0x790 "MSCR_IO484,SIUL2 I/O pin multiplexed signal configuration register 484" bitfld.long 0x790 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x790 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x790 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x790 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x790 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x790 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x790 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x790 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x790 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x790 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x790 0.--7. 1. "SSS,Source Signal Select" line.long 0x794 "MSCR_IO485,SIUL2 I/O pin multiplexed signal configuration register 485" bitfld.long 0x794 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x794 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x794 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x794 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x794 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x794 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x794 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x794 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x794 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x794 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x794 0.--7. 1. "SSS,Source Signal Select" line.long 0x798 "MSCR_IO486,SIUL2 I/O pin multiplexed signal configuration register 486" bitfld.long 0x798 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x798 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x798 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x798 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x798 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x798 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x798 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x798 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x798 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x798 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x798 0.--7. 1. "SSS,Source Signal Select" line.long 0x79C "MSCR_IO487,SIUL2 I/O pin multiplexed signal configuration register 487" bitfld.long 0x79C 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x79C 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x79C 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x79C 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x79C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x79C 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x79C 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x79C 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x79C 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x79C 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x79C 0.--7. 1. "SSS,Source Signal Select" line.long 0x7A0 "MSCR_IO488,SIUL2 I/O pin multiplexed signal configuration register 488" bitfld.long 0x7A0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7A0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7A0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7A0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7A0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7A0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7A0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7A0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7A0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7A0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7A0 0.--7. 1. "SSS,Source Signal Select" line.long 0x7A4 "MSCR_IO489,SIUL2 I/O pin multiplexed signal configuration register 489" bitfld.long 0x7A4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7A4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7A4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7A4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7A4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7A4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7A4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7A4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7A4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7A4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7A4 0.--7. 1. "SSS,Source Signal Select" line.long 0x7A8 "MSCR_IO490,SIUL2 I/O pin multiplexed signal configuration register 490" bitfld.long 0x7A8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7A8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7A8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7A8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7A8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7A8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7A8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7A8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7A8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7A8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7A8 0.--7. 1. "SSS,Source Signal Select" line.long 0x7AC "MSCR_IO491,SIUL2 I/O pin multiplexed signal configuration register 491" bitfld.long 0x7AC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7AC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7AC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7AC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7AC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7AC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7AC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7AC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7AC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7AC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7AC 0.--7. 1. "SSS,Source Signal Select" line.long 0x7B0 "MSCR_IO492,SIUL2 I/O pin multiplexed signal configuration register 492" bitfld.long 0x7B0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7B0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7B0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7B0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7B0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7B0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7B0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7B0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7B0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7B0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7B0 0.--7. 1. "SSS,Source Signal Select" line.long 0x7B4 "MSCR_IO493,SIUL2 I/O pin multiplexed signal configuration register 493" bitfld.long 0x7B4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7B4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7B4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7B4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7B4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7B4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7B4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7B4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7B4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7B4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7B4 0.--7. 1. "SSS,Source Signal Select" line.long 0x7B8 "MSCR_IO494,SIUL2 I/O pin multiplexed signal configuration register 494" bitfld.long 0x7B8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7B8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7B8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7B8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7B8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7B8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7B8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7B8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7B8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7B8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7B8 0.--7. 1. "SSS,Source Signal Select" line.long 0x7BC "MSCR_IO495,SIUL2 I/O pin multiplexed signal configuration register 495" bitfld.long 0x7BC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7BC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7BC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7BC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7BC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7BC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7BC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7BC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7BC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7BC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7BC 0.--7. 1. "SSS,Source Signal Select" line.long 0x7C0 "MSCR_IO496,SIUL2 I/O pin multiplexed signal configuration register 496" bitfld.long 0x7C0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7C0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7C0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7C0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7C0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7C0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7C0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7C0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7C0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7C0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7C0 0.--7. 1. "SSS,Source Signal Select" line.long 0x7C4 "MSCR_IO497,SIUL2 I/O pin multiplexed signal configuration register 497" bitfld.long 0x7C4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7C4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7C4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7C4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7C4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7C4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7C4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7C4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7C4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7C4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7C4 0.--7. 1. "SSS,Source Signal Select" line.long 0x7C8 "MSCR_IO498,SIUL2 I/O pin multiplexed signal configuration register 498" bitfld.long 0x7C8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7C8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7C8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7C8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7C8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7C8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7C8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7C8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7C8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7C8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7C8 0.--7. 1. "SSS,Source Signal Select" line.long 0x7CC "MSCR_IO499,SIUL2 I/O pin multiplexed signal configuration register 499" bitfld.long 0x7CC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7CC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7CC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7CC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7CC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7CC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7CC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7CC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7CC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7CC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7CC 0.--7. 1. "SSS,Source Signal Select" line.long 0x7D0 "MSCR_IO500,SIUL2 I/O pin multiplexed signal configuration register 500" bitfld.long 0x7D0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7D0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7D0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7D0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7D0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7D0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7D0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7D0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7D0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7D0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7D0 0.--7. 1. "SSS,Source Signal Select" line.long 0x7D4 "MSCR_IO501,SIUL2 I/O pin multiplexed signal configuration register 501" bitfld.long 0x7D4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7D4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7D4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7D4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7D4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7D4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7D4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7D4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7D4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7D4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7D4 0.--7. 1. "SSS,Source Signal Select" line.long 0x7D8 "MSCR_IO502,SIUL2 I/O pin multiplexed signal configuration register 502" bitfld.long 0x7D8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7D8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7D8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7D8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7D8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7D8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7D8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7D8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7D8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7D8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7D8 0.--7. 1. "SSS,Source Signal Select" line.long 0x7DC "MSCR_IO503,SIUL2 I/O pin multiplexed signal configuration register 503" bitfld.long 0x7DC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7DC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7DC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7DC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7DC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7DC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7DC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7DC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7DC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7DC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7DC 0.--7. 1. "SSS,Source Signal Select" line.long 0x7E0 "MSCR_IO504,SIUL2 I/O pin multiplexed signal configuration register 504" bitfld.long 0x7E0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7E0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7E0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7E0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7E0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7E0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7E0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7E0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7E0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7E0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7E0 0.--7. 1. "SSS,Source Signal Select" line.long 0x7E4 "MSCR_IO505,SIUL2 I/O pin multiplexed signal configuration register 505" bitfld.long 0x7E4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7E4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7E4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7E4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7E4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7E4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7E4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7E4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7E4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7E4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7E4 0.--7. 1. "SSS,Source Signal Select" line.long 0x7E8 "MSCR_IO506,SIUL2 I/O pin multiplexed signal configuration register 506" bitfld.long 0x7E8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7E8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7E8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7E8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7E8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7E8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7E8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7E8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7E8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7E8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7E8 0.--7. 1. "SSS,Source Signal Select" line.long 0x7EC "MSCR_IO507,SIUL2 I/O pin multiplexed signal configuration register 507" bitfld.long 0x7EC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7EC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7EC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7EC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7EC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7EC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7EC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7EC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7EC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7EC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7EC 0.--7. 1. "SSS,Source Signal Select" line.long 0x7F0 "MSCR_IO508,SIUL2 I/O pin multiplexed signal configuration register 508" bitfld.long 0x7F0 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7F0 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7F0 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7F0 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7F0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7F0 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7F0 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7F0 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7F0 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7F0 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7F0 0.--7. 1. "SSS,Source Signal Select" line.long 0x7F4 "MSCR_IO509,SIUL2 I/O pin multiplexed signal configuration register 509" bitfld.long 0x7F4 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7F4 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7F4 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7F4 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7F4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7F4 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7F4 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7F4 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7F4 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7F4 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7F4 0.--7. 1. "SSS,Source Signal Select" line.long 0x7F8 "MSCR_IO510,SIUL2 I/O pin multiplexed signal configuration register 510" bitfld.long 0x7F8 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7F8 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7F8 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7F8 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7F8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7F8 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7F8 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7F8 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7F8 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7F8 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7F8 0.--7. 1. "SSS,Source Signal Select" line.long 0x7FC "MSCR_IO511,SIUL2 I/O pin multiplexed signal configuration register 511" bitfld.long 0x7FC 28.--29. "OERC,Output Edge Rate Control" "0: Weak drive,1: Medium drive,2: Strong drive,3: Very Strong / Ultra Strong drive" bitfld.long 0x7FC 24.--26. "ODC,Output Drive Control" "0: (output buffer disabled,1: Open-drain,2: Push-pull,3: Open-source,4: Microsecond channel LVDS,5: LFAST LVDS,?,?" newline bitfld.long 0x7FC 23. "SMC,Safe Mode Control" "0: Disable (the output buffer returns to its..,1: Does not disable" bitfld.long 0x7FC 20.--21. "ILS,Input Level Selection" "0: Automotive,1: TTL,2: LVDS,3: CMOS" newline bitfld.long 0x7FC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7FC 17. "WPDE,Weak Pulldown Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7FC 16. "WPUE,Weak Pullup Enable" "0: Disabled,1: Enabled" bitfld.long 0x7FC 15. "INV,Invert" "0: The output selected by the SSS field is not..,1: The output selected by the SSS field is inverted.." newline hexmask.long.byte 0x7FC 11.--14. 1. "FILPRESC,Filter Prescaler" bitfld.long 0x7FC 10. "FILBYPASS,Filter Bypass" "0: Filter bypass is disabled.,1: Filter bypass is enabled." newline hexmask.long.byte 0x7FC 0.--7. 1. "SSS,Source Signal Select" line.long 0x800 "MSCR_MUX512,SIUL2 multiplexed signal configuration register 512 for multiplexed input selectio512" bitfld.long 0x800 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x800 0.--7. 1. "SSS,Source Signal Select" line.long 0x804 "MSCR_MUX513,SIUL2 multiplexed signal configuration register 513 for multiplexed input selectio513" bitfld.long 0x804 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x804 0.--7. 1. "SSS,Source Signal Select" line.long 0x808 "MSCR_MUX514,SIUL2 multiplexed signal configuration register 514 for multiplexed input selectio514" bitfld.long 0x808 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x808 0.--7. 1. "SSS,Source Signal Select" line.long 0x80C "MSCR_MUX515,SIUL2 multiplexed signal configuration register 515 for multiplexed input selectio515" bitfld.long 0x80C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x80C 0.--7. 1. "SSS,Source Signal Select" line.long 0x810 "MSCR_MUX516,SIUL2 multiplexed signal configuration register 516 for multiplexed input selectio516" bitfld.long 0x810 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x810 0.--7. 1. "SSS,Source Signal Select" line.long 0x814 "MSCR_MUX517,SIUL2 multiplexed signal configuration register 517 for multiplexed input selectio517" bitfld.long 0x814 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x814 0.--7. 1. "SSS,Source Signal Select" line.long 0x818 "MSCR_MUX518,SIUL2 multiplexed signal configuration register 518 for multiplexed input selectio518" bitfld.long 0x818 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x818 0.--7. 1. "SSS,Source Signal Select" line.long 0x81C "MSCR_MUX519,SIUL2 multiplexed signal configuration register 519 for multiplexed input selectio519" bitfld.long 0x81C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x81C 0.--7. 1. "SSS,Source Signal Select" line.long 0x820 "MSCR_MUX520,SIUL2 multiplexed signal configuration register 520 for multiplexed input selectio520" bitfld.long 0x820 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x820 0.--7. 1. "SSS,Source Signal Select" line.long 0x824 "MSCR_MUX521,SIUL2 multiplexed signal configuration register 521 for multiplexed input selectio521" bitfld.long 0x824 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x824 0.--7. 1. "SSS,Source Signal Select" line.long 0x828 "MSCR_MUX522,SIUL2 multiplexed signal configuration register 522 for multiplexed input selectio522" bitfld.long 0x828 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x828 0.--7. 1. "SSS,Source Signal Select" line.long 0x82C "MSCR_MUX523,SIUL2 multiplexed signal configuration register 523 for multiplexed input selectio523" bitfld.long 0x82C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x82C 0.--7. 1. "SSS,Source Signal Select" line.long 0x830 "MSCR_MUX524,SIUL2 multiplexed signal configuration register 524 for multiplexed input selectio524" bitfld.long 0x830 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x830 0.--7. 1. "SSS,Source Signal Select" line.long 0x834 "MSCR_MUX525,SIUL2 multiplexed signal configuration register 525 for multiplexed input selectio525" bitfld.long 0x834 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x834 0.--7. 1. "SSS,Source Signal Select" line.long 0x838 "MSCR_MUX526,SIUL2 multiplexed signal configuration register 526 for multiplexed input selectio526" bitfld.long 0x838 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x838 0.--7. 1. "SSS,Source Signal Select" line.long 0x83C "MSCR_MUX527,SIUL2 multiplexed signal configuration register 527 for multiplexed input selectio527" bitfld.long 0x83C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x83C 0.--7. 1. "SSS,Source Signal Select" line.long 0x840 "MSCR_MUX528,SIUL2 multiplexed signal configuration register 528 for multiplexed input selectio528" bitfld.long 0x840 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x840 0.--7. 1. "SSS,Source Signal Select" line.long 0x844 "MSCR_MUX529,SIUL2 multiplexed signal configuration register 529 for multiplexed input selectio529" bitfld.long 0x844 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x844 0.--7. 1. "SSS,Source Signal Select" line.long 0x848 "MSCR_MUX530,SIUL2 multiplexed signal configuration register 530 for multiplexed input selectio530" bitfld.long 0x848 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x848 0.--7. 1. "SSS,Source Signal Select" line.long 0x84C "MSCR_MUX531,SIUL2 multiplexed signal configuration register 531 for multiplexed input selectio531" bitfld.long 0x84C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x84C 0.--7. 1. "SSS,Source Signal Select" line.long 0x850 "MSCR_MUX532,SIUL2 multiplexed signal configuration register 532 for multiplexed input selectio532" bitfld.long 0x850 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x850 0.--7. 1. "SSS,Source Signal Select" line.long 0x854 "MSCR_MUX533,SIUL2 multiplexed signal configuration register 533 for multiplexed input selectio533" bitfld.long 0x854 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x854 0.--7. 1. "SSS,Source Signal Select" line.long 0x858 "MSCR_MUX534,SIUL2 multiplexed signal configuration register 534 for multiplexed input selectio534" bitfld.long 0x858 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x858 0.--7. 1. "SSS,Source Signal Select" line.long 0x85C "MSCR_MUX535,SIUL2 multiplexed signal configuration register 535 for multiplexed input selectio535" bitfld.long 0x85C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x85C 0.--7. 1. "SSS,Source Signal Select" line.long 0x860 "MSCR_MUX536,SIUL2 multiplexed signal configuration register 536 for multiplexed input selectio536" bitfld.long 0x860 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x860 0.--7. 1. "SSS,Source Signal Select" line.long 0x864 "MSCR_MUX537,SIUL2 multiplexed signal configuration register 537 for multiplexed input selectio537" bitfld.long 0x864 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x864 0.--7. 1. "SSS,Source Signal Select" line.long 0x868 "MSCR_MUX538,SIUL2 multiplexed signal configuration register 538 for multiplexed input selectio538" bitfld.long 0x868 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x868 0.--7. 1. "SSS,Source Signal Select" line.long 0x86C "MSCR_MUX539,SIUL2 multiplexed signal configuration register 539 for multiplexed input selectio539" bitfld.long 0x86C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x86C 0.--7. 1. "SSS,Source Signal Select" line.long 0x870 "MSCR_MUX540,SIUL2 multiplexed signal configuration register 540 for multiplexed input selectio540" bitfld.long 0x870 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x870 0.--7. 1. "SSS,Source Signal Select" line.long 0x874 "MSCR_MUX541,SIUL2 multiplexed signal configuration register 541 for multiplexed input selectio541" bitfld.long 0x874 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x874 0.--7. 1. "SSS,Source Signal Select" line.long 0x878 "MSCR_MUX542,SIUL2 multiplexed signal configuration register 542 for multiplexed input selectio542" bitfld.long 0x878 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x878 0.--7. 1. "SSS,Source Signal Select" line.long 0x87C "MSCR_MUX543,SIUL2 multiplexed signal configuration register 543 for multiplexed input selectio543" bitfld.long 0x87C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x87C 0.--7. 1. "SSS,Source Signal Select" line.long 0x880 "MSCR_MUX544,SIUL2 multiplexed signal configuration register 544 for multiplexed input selectio544" bitfld.long 0x880 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x880 0.--7. 1. "SSS,Source Signal Select" line.long 0x884 "MSCR_MUX545,SIUL2 multiplexed signal configuration register 545 for multiplexed input selectio545" bitfld.long 0x884 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x884 0.--7. 1. "SSS,Source Signal Select" line.long 0x888 "MSCR_MUX546,SIUL2 multiplexed signal configuration register 546 for multiplexed input selectio546" bitfld.long 0x888 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x888 0.--7. 1. "SSS,Source Signal Select" line.long 0x88C "MSCR_MUX547,SIUL2 multiplexed signal configuration register 547 for multiplexed input selectio547" bitfld.long 0x88C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x88C 0.--7. 1. "SSS,Source Signal Select" line.long 0x890 "MSCR_MUX548,SIUL2 multiplexed signal configuration register 548 for multiplexed input selectio548" bitfld.long 0x890 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x890 0.--7. 1. "SSS,Source Signal Select" line.long 0x894 "MSCR_MUX549,SIUL2 multiplexed signal configuration register 549 for multiplexed input selectio549" bitfld.long 0x894 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x894 0.--7. 1. "SSS,Source Signal Select" line.long 0x898 "MSCR_MUX550,SIUL2 multiplexed signal configuration register 550 for multiplexed input selectio550" bitfld.long 0x898 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x898 0.--7. 1. "SSS,Source Signal Select" line.long 0x89C "MSCR_MUX551,SIUL2 multiplexed signal configuration register 551 for multiplexed input selectio551" bitfld.long 0x89C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x89C 0.--7. 1. "SSS,Source Signal Select" line.long 0x8A0 "MSCR_MUX552,SIUL2 multiplexed signal configuration register 552 for multiplexed input selectio552" bitfld.long 0x8A0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8A0 0.--7. 1. "SSS,Source Signal Select" line.long 0x8A4 "MSCR_MUX553,SIUL2 multiplexed signal configuration register 553 for multiplexed input selectio553" bitfld.long 0x8A4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8A4 0.--7. 1. "SSS,Source Signal Select" line.long 0x8A8 "MSCR_MUX554,SIUL2 multiplexed signal configuration register 554 for multiplexed input selectio554" bitfld.long 0x8A8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8A8 0.--7. 1. "SSS,Source Signal Select" line.long 0x8AC "MSCR_MUX555,SIUL2 multiplexed signal configuration register 555 for multiplexed input selectio555" bitfld.long 0x8AC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8AC 0.--7. 1. "SSS,Source Signal Select" line.long 0x8B0 "MSCR_MUX556,SIUL2 multiplexed signal configuration register 556 for multiplexed input selectio556" bitfld.long 0x8B0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8B0 0.--7. 1. "SSS,Source Signal Select" line.long 0x8B4 "MSCR_MUX557,SIUL2 multiplexed signal configuration register 557 for multiplexed input selectio557" bitfld.long 0x8B4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8B4 0.--7. 1. "SSS,Source Signal Select" line.long 0x8B8 "MSCR_MUX558,SIUL2 multiplexed signal configuration register 558 for multiplexed input selectio558" bitfld.long 0x8B8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8B8 0.--7. 1. "SSS,Source Signal Select" line.long 0x8BC "MSCR_MUX559,SIUL2 multiplexed signal configuration register 559 for multiplexed input selectio559" bitfld.long 0x8BC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8BC 0.--7. 1. "SSS,Source Signal Select" line.long 0x8C0 "MSCR_MUX560,SIUL2 multiplexed signal configuration register 560 for multiplexed input selectio560" bitfld.long 0x8C0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8C0 0.--7. 1. "SSS,Source Signal Select" line.long 0x8C4 "MSCR_MUX561,SIUL2 multiplexed signal configuration register 561 for multiplexed input selectio561" bitfld.long 0x8C4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8C4 0.--7. 1. "SSS,Source Signal Select" line.long 0x8C8 "MSCR_MUX562,SIUL2 multiplexed signal configuration register 562 for multiplexed input selectio562" bitfld.long 0x8C8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8C8 0.--7. 1. "SSS,Source Signal Select" line.long 0x8CC "MSCR_MUX563,SIUL2 multiplexed signal configuration register 563 for multiplexed input selectio563" bitfld.long 0x8CC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8CC 0.--7. 1. "SSS,Source Signal Select" line.long 0x8D0 "MSCR_MUX564,SIUL2 multiplexed signal configuration register 564 for multiplexed input selectio564" bitfld.long 0x8D0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8D0 0.--7. 1. "SSS,Source Signal Select" line.long 0x8D4 "MSCR_MUX565,SIUL2 multiplexed signal configuration register 565 for multiplexed input selectio565" bitfld.long 0x8D4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8D4 0.--7. 1. "SSS,Source Signal Select" line.long 0x8D8 "MSCR_MUX566,SIUL2 multiplexed signal configuration register 566 for multiplexed input selectio566" bitfld.long 0x8D8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8D8 0.--7. 1. "SSS,Source Signal Select" line.long 0x8DC "MSCR_MUX567,SIUL2 multiplexed signal configuration register 567 for multiplexed input selectio567" bitfld.long 0x8DC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8DC 0.--7. 1. "SSS,Source Signal Select" line.long 0x8E0 "MSCR_MUX568,SIUL2 multiplexed signal configuration register 568 for multiplexed input selectio568" bitfld.long 0x8E0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8E0 0.--7. 1. "SSS,Source Signal Select" line.long 0x8E4 "MSCR_MUX569,SIUL2 multiplexed signal configuration register 569 for multiplexed input selectio569" bitfld.long 0x8E4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8E4 0.--7. 1. "SSS,Source Signal Select" line.long 0x8E8 "MSCR_MUX570,SIUL2 multiplexed signal configuration register 570 for multiplexed input selectio570" bitfld.long 0x8E8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8E8 0.--7. 1. "SSS,Source Signal Select" line.long 0x8EC "MSCR_MUX571,SIUL2 multiplexed signal configuration register 571 for multiplexed input selectio571" bitfld.long 0x8EC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8EC 0.--7. 1. "SSS,Source Signal Select" line.long 0x8F0 "MSCR_MUX572,SIUL2 multiplexed signal configuration register 572 for multiplexed input selectio572" bitfld.long 0x8F0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8F0 0.--7. 1. "SSS,Source Signal Select" line.long 0x8F4 "MSCR_MUX573,SIUL2 multiplexed signal configuration register 573 for multiplexed input selectio573" bitfld.long 0x8F4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8F4 0.--7. 1. "SSS,Source Signal Select" line.long 0x8F8 "MSCR_MUX574,SIUL2 multiplexed signal configuration register 574 for multiplexed input selectio574" bitfld.long 0x8F8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8F8 0.--7. 1. "SSS,Source Signal Select" line.long 0x8FC "MSCR_MUX575,SIUL2 multiplexed signal configuration register 575 for multiplexed input selectio575" bitfld.long 0x8FC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x8FC 0.--7. 1. "SSS,Source Signal Select" line.long 0x900 "MSCR_MUX576,SIUL2 multiplexed signal configuration register 576 for multiplexed input selectio576" bitfld.long 0x900 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x900 0.--7. 1. "SSS,Source Signal Select" line.long 0x904 "MSCR_MUX577,SIUL2 multiplexed signal configuration register 577 for multiplexed input selectio577" bitfld.long 0x904 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x904 0.--7. 1. "SSS,Source Signal Select" line.long 0x908 "MSCR_MUX578,SIUL2 multiplexed signal configuration register 578 for multiplexed input selectio578" bitfld.long 0x908 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x908 0.--7. 1. "SSS,Source Signal Select" line.long 0x90C "MSCR_MUX579,SIUL2 multiplexed signal configuration register 579 for multiplexed input selectio579" bitfld.long 0x90C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x90C 0.--7. 1. "SSS,Source Signal Select" line.long 0x910 "MSCR_MUX580,SIUL2 multiplexed signal configuration register 580 for multiplexed input selectio580" bitfld.long 0x910 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x910 0.--7. 1. "SSS,Source Signal Select" line.long 0x914 "MSCR_MUX581,SIUL2 multiplexed signal configuration register 581 for multiplexed input selectio581" bitfld.long 0x914 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x914 0.--7. 1. "SSS,Source Signal Select" line.long 0x918 "MSCR_MUX582,SIUL2 multiplexed signal configuration register 582 for multiplexed input selectio582" bitfld.long 0x918 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x918 0.--7. 1. "SSS,Source Signal Select" line.long 0x91C "MSCR_MUX583,SIUL2 multiplexed signal configuration register 583 for multiplexed input selectio583" bitfld.long 0x91C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x91C 0.--7. 1. "SSS,Source Signal Select" line.long 0x920 "MSCR_MUX584,SIUL2 multiplexed signal configuration register 584 for multiplexed input selectio584" bitfld.long 0x920 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x920 0.--7. 1. "SSS,Source Signal Select" line.long 0x924 "MSCR_MUX585,SIUL2 multiplexed signal configuration register 585 for multiplexed input selectio585" bitfld.long 0x924 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x924 0.--7. 1. "SSS,Source Signal Select" line.long 0x928 "MSCR_MUX586,SIUL2 multiplexed signal configuration register 586 for multiplexed input selectio586" bitfld.long 0x928 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x928 0.--7. 1. "SSS,Source Signal Select" line.long 0x92C "MSCR_MUX587,SIUL2 multiplexed signal configuration register 587 for multiplexed input selectio587" bitfld.long 0x92C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x92C 0.--7. 1. "SSS,Source Signal Select" line.long 0x930 "MSCR_MUX588,SIUL2 multiplexed signal configuration register 588 for multiplexed input selectio588" bitfld.long 0x930 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x930 0.--7. 1. "SSS,Source Signal Select" line.long 0x934 "MSCR_MUX589,SIUL2 multiplexed signal configuration register 589 for multiplexed input selectio589" bitfld.long 0x934 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x934 0.--7. 1. "SSS,Source Signal Select" line.long 0x938 "MSCR_MUX590,SIUL2 multiplexed signal configuration register 590 for multiplexed input selectio590" bitfld.long 0x938 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x938 0.--7. 1. "SSS,Source Signal Select" line.long 0x93C "MSCR_MUX591,SIUL2 multiplexed signal configuration register 591 for multiplexed input selectio591" bitfld.long 0x93C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x93C 0.--7. 1. "SSS,Source Signal Select" line.long 0x940 "MSCR_MUX592,SIUL2 multiplexed signal configuration register 592 for multiplexed input selectio592" bitfld.long 0x940 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x940 0.--7. 1. "SSS,Source Signal Select" line.long 0x944 "MSCR_MUX593,SIUL2 multiplexed signal configuration register 593 for multiplexed input selectio593" bitfld.long 0x944 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x944 0.--7. 1. "SSS,Source Signal Select" line.long 0x948 "MSCR_MUX594,SIUL2 multiplexed signal configuration register 594 for multiplexed input selectio594" bitfld.long 0x948 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x948 0.--7. 1. "SSS,Source Signal Select" line.long 0x94C "MSCR_MUX595,SIUL2 multiplexed signal configuration register 595 for multiplexed input selectio595" bitfld.long 0x94C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x94C 0.--7. 1. "SSS,Source Signal Select" line.long 0x950 "MSCR_MUX596,SIUL2 multiplexed signal configuration register 596 for multiplexed input selectio596" bitfld.long 0x950 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x950 0.--7. 1. "SSS,Source Signal Select" line.long 0x954 "MSCR_MUX597,SIUL2 multiplexed signal configuration register 597 for multiplexed input selectio597" bitfld.long 0x954 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x954 0.--7. 1. "SSS,Source Signal Select" line.long 0x958 "MSCR_MUX598,SIUL2 multiplexed signal configuration register 598 for multiplexed input selectio598" bitfld.long 0x958 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x958 0.--7. 1. "SSS,Source Signal Select" line.long 0x95C "MSCR_MUX599,SIUL2 multiplexed signal configuration register 599 for multiplexed input selectio599" bitfld.long 0x95C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x95C 0.--7. 1. "SSS,Source Signal Select" line.long 0x960 "MSCR_MUX600,SIUL2 multiplexed signal configuration register 600 for multiplexed input selectio600" bitfld.long 0x960 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x960 0.--7. 1. "SSS,Source Signal Select" line.long 0x964 "MSCR_MUX601,SIUL2 multiplexed signal configuration register 601 for multiplexed input selectio601" bitfld.long 0x964 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x964 0.--7. 1. "SSS,Source Signal Select" line.long 0x968 "MSCR_MUX602,SIUL2 multiplexed signal configuration register 602 for multiplexed input selectio602" bitfld.long 0x968 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x968 0.--7. 1. "SSS,Source Signal Select" line.long 0x96C "MSCR_MUX603,SIUL2 multiplexed signal configuration register 603 for multiplexed input selectio603" bitfld.long 0x96C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x96C 0.--7. 1. "SSS,Source Signal Select" line.long 0x970 "MSCR_MUX604,SIUL2 multiplexed signal configuration register 604 for multiplexed input selectio604" bitfld.long 0x970 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x970 0.--7. 1. "SSS,Source Signal Select" line.long 0x974 "MSCR_MUX605,SIUL2 multiplexed signal configuration register 605 for multiplexed input selectio605" bitfld.long 0x974 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x974 0.--7. 1. "SSS,Source Signal Select" line.long 0x978 "MSCR_MUX606,SIUL2 multiplexed signal configuration register 606 for multiplexed input selectio606" bitfld.long 0x978 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x978 0.--7. 1. "SSS,Source Signal Select" line.long 0x97C "MSCR_MUX607,SIUL2 multiplexed signal configuration register 607 for multiplexed input selectio607" bitfld.long 0x97C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x97C 0.--7. 1. "SSS,Source Signal Select" line.long 0x980 "MSCR_MUX608,SIUL2 multiplexed signal configuration register 608 for multiplexed input selectio608" bitfld.long 0x980 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x980 0.--7. 1. "SSS,Source Signal Select" line.long 0x984 "MSCR_MUX609,SIUL2 multiplexed signal configuration register 609 for multiplexed input selectio609" bitfld.long 0x984 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x984 0.--7. 1. "SSS,Source Signal Select" line.long 0x988 "MSCR_MUX610,SIUL2 multiplexed signal configuration register 610 for multiplexed input selectio610" bitfld.long 0x988 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x988 0.--7. 1. "SSS,Source Signal Select" line.long 0x98C "MSCR_MUX611,SIUL2 multiplexed signal configuration register 611 for multiplexed input selectio611" bitfld.long 0x98C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x98C 0.--7. 1. "SSS,Source Signal Select" line.long 0x990 "MSCR_MUX612,SIUL2 multiplexed signal configuration register 612 for multiplexed input selectio612" bitfld.long 0x990 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x990 0.--7. 1. "SSS,Source Signal Select" line.long 0x994 "MSCR_MUX613,SIUL2 multiplexed signal configuration register 613 for multiplexed input selectio613" bitfld.long 0x994 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x994 0.--7. 1. "SSS,Source Signal Select" line.long 0x998 "MSCR_MUX614,SIUL2 multiplexed signal configuration register 614 for multiplexed input selectio614" bitfld.long 0x998 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x998 0.--7. 1. "SSS,Source Signal Select" line.long 0x99C "MSCR_MUX615,SIUL2 multiplexed signal configuration register 615 for multiplexed input selectio615" bitfld.long 0x99C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x99C 0.--7. 1. "SSS,Source Signal Select" line.long 0x9A0 "MSCR_MUX616,SIUL2 multiplexed signal configuration register 616 for multiplexed input selectio616" bitfld.long 0x9A0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9A0 0.--7. 1. "SSS,Source Signal Select" line.long 0x9A4 "MSCR_MUX617,SIUL2 multiplexed signal configuration register 617 for multiplexed input selectio617" bitfld.long 0x9A4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9A4 0.--7. 1. "SSS,Source Signal Select" line.long 0x9A8 "MSCR_MUX618,SIUL2 multiplexed signal configuration register 618 for multiplexed input selectio618" bitfld.long 0x9A8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9A8 0.--7. 1. "SSS,Source Signal Select" line.long 0x9AC "MSCR_MUX619,SIUL2 multiplexed signal configuration register 619 for multiplexed input selectio619" bitfld.long 0x9AC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9AC 0.--7. 1. "SSS,Source Signal Select" line.long 0x9B0 "MSCR_MUX620,SIUL2 multiplexed signal configuration register 620 for multiplexed input selectio620" bitfld.long 0x9B0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9B0 0.--7. 1. "SSS,Source Signal Select" line.long 0x9B4 "MSCR_MUX621,SIUL2 multiplexed signal configuration register 621 for multiplexed input selectio621" bitfld.long 0x9B4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9B4 0.--7. 1. "SSS,Source Signal Select" line.long 0x9B8 "MSCR_MUX622,SIUL2 multiplexed signal configuration register 622 for multiplexed input selectio622" bitfld.long 0x9B8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9B8 0.--7. 1. "SSS,Source Signal Select" line.long 0x9BC "MSCR_MUX623,SIUL2 multiplexed signal configuration register 623 for multiplexed input selectio623" bitfld.long 0x9BC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9BC 0.--7. 1. "SSS,Source Signal Select" line.long 0x9C0 "MSCR_MUX624,SIUL2 multiplexed signal configuration register 624 for multiplexed input selectio624" bitfld.long 0x9C0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9C0 0.--7. 1. "SSS,Source Signal Select" line.long 0x9C4 "MSCR_MUX625,SIUL2 multiplexed signal configuration register 625 for multiplexed input selectio625" bitfld.long 0x9C4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9C4 0.--7. 1. "SSS,Source Signal Select" line.long 0x9C8 "MSCR_MUX626,SIUL2 multiplexed signal configuration register 626 for multiplexed input selectio626" bitfld.long 0x9C8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9C8 0.--7. 1. "SSS,Source Signal Select" line.long 0x9CC "MSCR_MUX627,SIUL2 multiplexed signal configuration register 627 for multiplexed input selectio627" bitfld.long 0x9CC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9CC 0.--7. 1. "SSS,Source Signal Select" line.long 0x9D0 "MSCR_MUX628,SIUL2 multiplexed signal configuration register 628 for multiplexed input selectio628" bitfld.long 0x9D0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9D0 0.--7. 1. "SSS,Source Signal Select" line.long 0x9D4 "MSCR_MUX629,SIUL2 multiplexed signal configuration register 629 for multiplexed input selectio629" bitfld.long 0x9D4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9D4 0.--7. 1. "SSS,Source Signal Select" line.long 0x9D8 "MSCR_MUX630,SIUL2 multiplexed signal configuration register 630 for multiplexed input selectio630" bitfld.long 0x9D8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9D8 0.--7. 1. "SSS,Source Signal Select" line.long 0x9DC "MSCR_MUX631,SIUL2 multiplexed signal configuration register 631 for multiplexed input selectio631" bitfld.long 0x9DC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9DC 0.--7. 1. "SSS,Source Signal Select" line.long 0x9E0 "MSCR_MUX632,SIUL2 multiplexed signal configuration register 632 for multiplexed input selectio632" bitfld.long 0x9E0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9E0 0.--7. 1. "SSS,Source Signal Select" line.long 0x9E4 "MSCR_MUX633,SIUL2 multiplexed signal configuration register 633 for multiplexed input selectio633" bitfld.long 0x9E4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9E4 0.--7. 1. "SSS,Source Signal Select" line.long 0x9E8 "MSCR_MUX634,SIUL2 multiplexed signal configuration register 634 for multiplexed input selectio634" bitfld.long 0x9E8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9E8 0.--7. 1. "SSS,Source Signal Select" line.long 0x9EC "MSCR_MUX635,SIUL2 multiplexed signal configuration register 635 for multiplexed input selectio635" bitfld.long 0x9EC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9EC 0.--7. 1. "SSS,Source Signal Select" line.long 0x9F0 "MSCR_MUX636,SIUL2 multiplexed signal configuration register 636 for multiplexed input selectio636" bitfld.long 0x9F0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9F0 0.--7. 1. "SSS,Source Signal Select" line.long 0x9F4 "MSCR_MUX637,SIUL2 multiplexed signal configuration register 637 for multiplexed input selectio637" bitfld.long 0x9F4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9F4 0.--7. 1. "SSS,Source Signal Select" line.long 0x9F8 "MSCR_MUX638,SIUL2 multiplexed signal configuration register 638 for multiplexed input selectio638" bitfld.long 0x9F8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9F8 0.--7. 1. "SSS,Source Signal Select" line.long 0x9FC "MSCR_MUX639,SIUL2 multiplexed signal configuration register 639 for multiplexed input selectio639" bitfld.long 0x9FC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0x9FC 0.--7. 1. "SSS,Source Signal Select" line.long 0xA00 "MSCR_MUX640,SIUL2 multiplexed signal configuration register 640 for multiplexed input selectio640" bitfld.long 0xA00 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA00 0.--7. 1. "SSS,Source Signal Select" line.long 0xA04 "MSCR_MUX641,SIUL2 multiplexed signal configuration register 641 for multiplexed input selectio641" bitfld.long 0xA04 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA04 0.--7. 1. "SSS,Source Signal Select" line.long 0xA08 "MSCR_MUX642,SIUL2 multiplexed signal configuration register 642 for multiplexed input selectio642" bitfld.long 0xA08 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA08 0.--7. 1. "SSS,Source Signal Select" line.long 0xA0C "MSCR_MUX643,SIUL2 multiplexed signal configuration register 643 for multiplexed input selectio643" bitfld.long 0xA0C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA0C 0.--7. 1. "SSS,Source Signal Select" line.long 0xA10 "MSCR_MUX644,SIUL2 multiplexed signal configuration register 644 for multiplexed input selectio644" bitfld.long 0xA10 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA10 0.--7. 1. "SSS,Source Signal Select" line.long 0xA14 "MSCR_MUX645,SIUL2 multiplexed signal configuration register 645 for multiplexed input selectio645" bitfld.long 0xA14 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA14 0.--7. 1. "SSS,Source Signal Select" line.long 0xA18 "MSCR_MUX646,SIUL2 multiplexed signal configuration register 646 for multiplexed input selectio646" bitfld.long 0xA18 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA18 0.--7. 1. "SSS,Source Signal Select" line.long 0xA1C "MSCR_MUX647,SIUL2 multiplexed signal configuration register 647 for multiplexed input selectio647" bitfld.long 0xA1C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA1C 0.--7. 1. "SSS,Source Signal Select" line.long 0xA20 "MSCR_MUX648,SIUL2 multiplexed signal configuration register 648 for multiplexed input selectio648" bitfld.long 0xA20 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA20 0.--7. 1. "SSS,Source Signal Select" line.long 0xA24 "MSCR_MUX649,SIUL2 multiplexed signal configuration register 649 for multiplexed input selectio649" bitfld.long 0xA24 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA24 0.--7. 1. "SSS,Source Signal Select" line.long 0xA28 "MSCR_MUX650,SIUL2 multiplexed signal configuration register 650 for multiplexed input selectio650" bitfld.long 0xA28 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA28 0.--7. 1. "SSS,Source Signal Select" line.long 0xA2C "MSCR_MUX651,SIUL2 multiplexed signal configuration register 651 for multiplexed input selectio651" bitfld.long 0xA2C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA2C 0.--7. 1. "SSS,Source Signal Select" line.long 0xA30 "MSCR_MUX652,SIUL2 multiplexed signal configuration register 652 for multiplexed input selectio652" bitfld.long 0xA30 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA30 0.--7. 1. "SSS,Source Signal Select" line.long 0xA34 "MSCR_MUX653,SIUL2 multiplexed signal configuration register 653 for multiplexed input selectio653" bitfld.long 0xA34 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA34 0.--7. 1. "SSS,Source Signal Select" line.long 0xA38 "MSCR_MUX654,SIUL2 multiplexed signal configuration register 654 for multiplexed input selectio654" bitfld.long 0xA38 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA38 0.--7. 1. "SSS,Source Signal Select" line.long 0xA3C "MSCR_MUX655,SIUL2 multiplexed signal configuration register 655 for multiplexed input selectio655" bitfld.long 0xA3C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA3C 0.--7. 1. "SSS,Source Signal Select" line.long 0xA40 "MSCR_MUX656,SIUL2 multiplexed signal configuration register 656 for multiplexed input selectio656" bitfld.long 0xA40 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA40 0.--7. 1. "SSS,Source Signal Select" line.long 0xA44 "MSCR_MUX657,SIUL2 multiplexed signal configuration register 657 for multiplexed input selectio657" bitfld.long 0xA44 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA44 0.--7. 1. "SSS,Source Signal Select" line.long 0xA48 "MSCR_MUX658,SIUL2 multiplexed signal configuration register 658 for multiplexed input selectio658" bitfld.long 0xA48 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA48 0.--7. 1. "SSS,Source Signal Select" line.long 0xA4C "MSCR_MUX659,SIUL2 multiplexed signal configuration register 659 for multiplexed input selectio659" bitfld.long 0xA4C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA4C 0.--7. 1. "SSS,Source Signal Select" line.long 0xA50 "MSCR_MUX660,SIUL2 multiplexed signal configuration register 660 for multiplexed input selectio660" bitfld.long 0xA50 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA50 0.--7. 1. "SSS,Source Signal Select" line.long 0xA54 "MSCR_MUX661,SIUL2 multiplexed signal configuration register 661 for multiplexed input selectio661" bitfld.long 0xA54 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA54 0.--7. 1. "SSS,Source Signal Select" line.long 0xA58 "MSCR_MUX662,SIUL2 multiplexed signal configuration register 662 for multiplexed input selectio662" bitfld.long 0xA58 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA58 0.--7. 1. "SSS,Source Signal Select" line.long 0xA5C "MSCR_MUX663,SIUL2 multiplexed signal configuration register 663 for multiplexed input selectio663" bitfld.long 0xA5C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA5C 0.--7. 1. "SSS,Source Signal Select" line.long 0xA60 "MSCR_MUX664,SIUL2 multiplexed signal configuration register 664 for multiplexed input selectio664" bitfld.long 0xA60 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA60 0.--7. 1. "SSS,Source Signal Select" line.long 0xA64 "MSCR_MUX665,SIUL2 multiplexed signal configuration register 665 for multiplexed input selectio665" bitfld.long 0xA64 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA64 0.--7. 1. "SSS,Source Signal Select" line.long 0xA68 "MSCR_MUX666,SIUL2 multiplexed signal configuration register 666 for multiplexed input selectio666" bitfld.long 0xA68 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA68 0.--7. 1. "SSS,Source Signal Select" line.long 0xA6C "MSCR_MUX667,SIUL2 multiplexed signal configuration register 667 for multiplexed input selectio667" bitfld.long 0xA6C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA6C 0.--7. 1. "SSS,Source Signal Select" line.long 0xA70 "MSCR_MUX668,SIUL2 multiplexed signal configuration register 668 for multiplexed input selectio668" bitfld.long 0xA70 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA70 0.--7. 1. "SSS,Source Signal Select" line.long 0xA74 "MSCR_MUX669,SIUL2 multiplexed signal configuration register 669 for multiplexed input selectio669" bitfld.long 0xA74 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA74 0.--7. 1. "SSS,Source Signal Select" line.long 0xA78 "MSCR_MUX670,SIUL2 multiplexed signal configuration register 670 for multiplexed input selectio670" bitfld.long 0xA78 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA78 0.--7. 1. "SSS,Source Signal Select" line.long 0xA7C "MSCR_MUX671,SIUL2 multiplexed signal configuration register 671 for multiplexed input selectio671" bitfld.long 0xA7C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA7C 0.--7. 1. "SSS,Source Signal Select" line.long 0xA80 "MSCR_MUX672,SIUL2 multiplexed signal configuration register 672 for multiplexed input selectio672" bitfld.long 0xA80 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA80 0.--7. 1. "SSS,Source Signal Select" line.long 0xA84 "MSCR_MUX673,SIUL2 multiplexed signal configuration register 673 for multiplexed input selectio673" bitfld.long 0xA84 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA84 0.--7. 1. "SSS,Source Signal Select" line.long 0xA88 "MSCR_MUX674,SIUL2 multiplexed signal configuration register 674 for multiplexed input selectio674" bitfld.long 0xA88 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA88 0.--7. 1. "SSS,Source Signal Select" line.long 0xA8C "MSCR_MUX675,SIUL2 multiplexed signal configuration register 675 for multiplexed input selectio675" bitfld.long 0xA8C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA8C 0.--7. 1. "SSS,Source Signal Select" line.long 0xA90 "MSCR_MUX676,SIUL2 multiplexed signal configuration register 676 for multiplexed input selectio676" bitfld.long 0xA90 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA90 0.--7. 1. "SSS,Source Signal Select" line.long 0xA94 "MSCR_MUX677,SIUL2 multiplexed signal configuration register 677 for multiplexed input selectio677" bitfld.long 0xA94 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA94 0.--7. 1. "SSS,Source Signal Select" line.long 0xA98 "MSCR_MUX678,SIUL2 multiplexed signal configuration register 678 for multiplexed input selectio678" bitfld.long 0xA98 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA98 0.--7. 1. "SSS,Source Signal Select" line.long 0xA9C "MSCR_MUX679,SIUL2 multiplexed signal configuration register 679 for multiplexed input selectio679" bitfld.long 0xA9C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xA9C 0.--7. 1. "SSS,Source Signal Select" line.long 0xAA0 "MSCR_MUX680,SIUL2 multiplexed signal configuration register 680 for multiplexed input selectio680" bitfld.long 0xAA0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAA0 0.--7. 1. "SSS,Source Signal Select" line.long 0xAA4 "MSCR_MUX681,SIUL2 multiplexed signal configuration register 681 for multiplexed input selectio681" bitfld.long 0xAA4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAA4 0.--7. 1. "SSS,Source Signal Select" line.long 0xAA8 "MSCR_MUX682,SIUL2 multiplexed signal configuration register 682 for multiplexed input selectio682" bitfld.long 0xAA8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAA8 0.--7. 1. "SSS,Source Signal Select" line.long 0xAAC "MSCR_MUX683,SIUL2 multiplexed signal configuration register 683 for multiplexed input selectio683" bitfld.long 0xAAC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAAC 0.--7. 1. "SSS,Source Signal Select" line.long 0xAB0 "MSCR_MUX684,SIUL2 multiplexed signal configuration register 684 for multiplexed input selectio684" bitfld.long 0xAB0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAB0 0.--7. 1. "SSS,Source Signal Select" line.long 0xAB4 "MSCR_MUX685,SIUL2 multiplexed signal configuration register 685 for multiplexed input selectio685" bitfld.long 0xAB4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAB4 0.--7. 1. "SSS,Source Signal Select" line.long 0xAB8 "MSCR_MUX686,SIUL2 multiplexed signal configuration register 686 for multiplexed input selectio686" bitfld.long 0xAB8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAB8 0.--7. 1. "SSS,Source Signal Select" line.long 0xABC "MSCR_MUX687,SIUL2 multiplexed signal configuration register 687 for multiplexed input selectio687" bitfld.long 0xABC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xABC 0.--7. 1. "SSS,Source Signal Select" line.long 0xAC0 "MSCR_MUX688,SIUL2 multiplexed signal configuration register 688 for multiplexed input selectio688" bitfld.long 0xAC0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAC0 0.--7. 1. "SSS,Source Signal Select" line.long 0xAC4 "MSCR_MUX689,SIUL2 multiplexed signal configuration register 689 for multiplexed input selectio689" bitfld.long 0xAC4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAC4 0.--7. 1. "SSS,Source Signal Select" line.long 0xAC8 "MSCR_MUX690,SIUL2 multiplexed signal configuration register 690 for multiplexed input selectio690" bitfld.long 0xAC8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAC8 0.--7. 1. "SSS,Source Signal Select" line.long 0xACC "MSCR_MUX691,SIUL2 multiplexed signal configuration register 691 for multiplexed input selectio691" bitfld.long 0xACC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xACC 0.--7. 1. "SSS,Source Signal Select" line.long 0xAD0 "MSCR_MUX692,SIUL2 multiplexed signal configuration register 692 for multiplexed input selectio692" bitfld.long 0xAD0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAD0 0.--7. 1. "SSS,Source Signal Select" line.long 0xAD4 "MSCR_MUX693,SIUL2 multiplexed signal configuration register 693 for multiplexed input selectio693" bitfld.long 0xAD4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAD4 0.--7. 1. "SSS,Source Signal Select" line.long 0xAD8 "MSCR_MUX694,SIUL2 multiplexed signal configuration register 694 for multiplexed input selectio694" bitfld.long 0xAD8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAD8 0.--7. 1. "SSS,Source Signal Select" line.long 0xADC "MSCR_MUX695,SIUL2 multiplexed signal configuration register 695 for multiplexed input selectio695" bitfld.long 0xADC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xADC 0.--7. 1. "SSS,Source Signal Select" line.long 0xAE0 "MSCR_MUX696,SIUL2 multiplexed signal configuration register 696 for multiplexed input selectio696" bitfld.long 0xAE0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAE0 0.--7. 1. "SSS,Source Signal Select" line.long 0xAE4 "MSCR_MUX697,SIUL2 multiplexed signal configuration register 697 for multiplexed input selectio697" bitfld.long 0xAE4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAE4 0.--7. 1. "SSS,Source Signal Select" line.long 0xAE8 "MSCR_MUX698,SIUL2 multiplexed signal configuration register 698 for multiplexed input selectio698" bitfld.long 0xAE8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAE8 0.--7. 1. "SSS,Source Signal Select" line.long 0xAEC "MSCR_MUX699,SIUL2 multiplexed signal configuration register 699 for multiplexed input selectio699" bitfld.long 0xAEC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAEC 0.--7. 1. "SSS,Source Signal Select" line.long 0xAF0 "MSCR_MUX700,SIUL2 multiplexed signal configuration register 700 for multiplexed input selectio700" bitfld.long 0xAF0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAF0 0.--7. 1. "SSS,Source Signal Select" line.long 0xAF4 "MSCR_MUX701,SIUL2 multiplexed signal configuration register 701 for multiplexed input selectio701" bitfld.long 0xAF4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAF4 0.--7. 1. "SSS,Source Signal Select" line.long 0xAF8 "MSCR_MUX702,SIUL2 multiplexed signal configuration register 702 for multiplexed input selectio702" bitfld.long 0xAF8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAF8 0.--7. 1. "SSS,Source Signal Select" line.long 0xAFC "MSCR_MUX703,SIUL2 multiplexed signal configuration register 703 for multiplexed input selectio703" bitfld.long 0xAFC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xAFC 0.--7. 1. "SSS,Source Signal Select" line.long 0xB00 "MSCR_MUX704,SIUL2 multiplexed signal configuration register 704 for multiplexed input selectio704" bitfld.long 0xB00 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB00 0.--7. 1. "SSS,Source Signal Select" line.long 0xB04 "MSCR_MUX705,SIUL2 multiplexed signal configuration register 705 for multiplexed input selectio705" bitfld.long 0xB04 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB04 0.--7. 1. "SSS,Source Signal Select" line.long 0xB08 "MSCR_MUX706,SIUL2 multiplexed signal configuration register 706 for multiplexed input selectio706" bitfld.long 0xB08 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB08 0.--7. 1. "SSS,Source Signal Select" line.long 0xB0C "MSCR_MUX707,SIUL2 multiplexed signal configuration register 707 for multiplexed input selectio707" bitfld.long 0xB0C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB0C 0.--7. 1. "SSS,Source Signal Select" line.long 0xB10 "MSCR_MUX708,SIUL2 multiplexed signal configuration register 708 for multiplexed input selectio708" bitfld.long 0xB10 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB10 0.--7. 1. "SSS,Source Signal Select" line.long 0xB14 "MSCR_MUX709,SIUL2 multiplexed signal configuration register 709 for multiplexed input selectio709" bitfld.long 0xB14 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB14 0.--7. 1. "SSS,Source Signal Select" line.long 0xB18 "MSCR_MUX710,SIUL2 multiplexed signal configuration register 710 for multiplexed input selectio710" bitfld.long 0xB18 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB18 0.--7. 1. "SSS,Source Signal Select" line.long 0xB1C "MSCR_MUX711,SIUL2 multiplexed signal configuration register 711 for multiplexed input selectio711" bitfld.long 0xB1C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB1C 0.--7. 1. "SSS,Source Signal Select" line.long 0xB20 "MSCR_MUX712,SIUL2 multiplexed signal configuration register 712 for multiplexed input selectio712" bitfld.long 0xB20 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB20 0.--7. 1. "SSS,Source Signal Select" line.long 0xB24 "MSCR_MUX713,SIUL2 multiplexed signal configuration register 713 for multiplexed input selectio713" bitfld.long 0xB24 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB24 0.--7. 1. "SSS,Source Signal Select" line.long 0xB28 "MSCR_MUX714,SIUL2 multiplexed signal configuration register 714 for multiplexed input selectio714" bitfld.long 0xB28 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB28 0.--7. 1. "SSS,Source Signal Select" line.long 0xB2C "MSCR_MUX715,SIUL2 multiplexed signal configuration register 715 for multiplexed input selectio715" bitfld.long 0xB2C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB2C 0.--7. 1. "SSS,Source Signal Select" line.long 0xB30 "MSCR_MUX716,SIUL2 multiplexed signal configuration register 716 for multiplexed input selectio716" bitfld.long 0xB30 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB30 0.--7. 1. "SSS,Source Signal Select" line.long 0xB34 "MSCR_MUX717,SIUL2 multiplexed signal configuration register 717 for multiplexed input selectio717" bitfld.long 0xB34 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB34 0.--7. 1. "SSS,Source Signal Select" line.long 0xB38 "MSCR_MUX718,SIUL2 multiplexed signal configuration register 718 for multiplexed input selectio718" bitfld.long 0xB38 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB38 0.--7. 1. "SSS,Source Signal Select" line.long 0xB3C "MSCR_MUX719,SIUL2 multiplexed signal configuration register 719 for multiplexed input selectio719" bitfld.long 0xB3C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB3C 0.--7. 1. "SSS,Source Signal Select" line.long 0xB40 "MSCR_MUX720,SIUL2 multiplexed signal configuration register 720 for multiplexed input selectio720" bitfld.long 0xB40 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB40 0.--7. 1. "SSS,Source Signal Select" line.long 0xB44 "MSCR_MUX721,SIUL2 multiplexed signal configuration register 721 for multiplexed input selectio721" bitfld.long 0xB44 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB44 0.--7. 1. "SSS,Source Signal Select" line.long 0xB48 "MSCR_MUX722,SIUL2 multiplexed signal configuration register 722 for multiplexed input selectio722" bitfld.long 0xB48 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB48 0.--7. 1. "SSS,Source Signal Select" line.long 0xB4C "MSCR_MUX723,SIUL2 multiplexed signal configuration register 723 for multiplexed input selectio723" bitfld.long 0xB4C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB4C 0.--7. 1. "SSS,Source Signal Select" line.long 0xB50 "MSCR_MUX724,SIUL2 multiplexed signal configuration register 724 for multiplexed input selectio724" bitfld.long 0xB50 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB50 0.--7. 1. "SSS,Source Signal Select" line.long 0xB54 "MSCR_MUX725,SIUL2 multiplexed signal configuration register 725 for multiplexed input selectio725" bitfld.long 0xB54 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB54 0.--7. 1. "SSS,Source Signal Select" line.long 0xB58 "MSCR_MUX726,SIUL2 multiplexed signal configuration register 726 for multiplexed input selectio726" bitfld.long 0xB58 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB58 0.--7. 1. "SSS,Source Signal Select" line.long 0xB5C "MSCR_MUX727,SIUL2 multiplexed signal configuration register 727 for multiplexed input selectio727" bitfld.long 0xB5C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB5C 0.--7. 1. "SSS,Source Signal Select" line.long 0xB60 "MSCR_MUX728,SIUL2 multiplexed signal configuration register 728 for multiplexed input selectio728" bitfld.long 0xB60 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB60 0.--7. 1. "SSS,Source Signal Select" line.long 0xB64 "MSCR_MUX729,SIUL2 multiplexed signal configuration register 729 for multiplexed input selectio729" bitfld.long 0xB64 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB64 0.--7. 1. "SSS,Source Signal Select" line.long 0xB68 "MSCR_MUX730,SIUL2 multiplexed signal configuration register 730 for multiplexed input selectio730" bitfld.long 0xB68 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB68 0.--7. 1. "SSS,Source Signal Select" line.long 0xB6C "MSCR_MUX731,SIUL2 multiplexed signal configuration register 731 for multiplexed input selectio731" bitfld.long 0xB6C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB6C 0.--7. 1. "SSS,Source Signal Select" line.long 0xB70 "MSCR_MUX732,SIUL2 multiplexed signal configuration register 732 for multiplexed input selectio732" bitfld.long 0xB70 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB70 0.--7. 1. "SSS,Source Signal Select" line.long 0xB74 "MSCR_MUX733,SIUL2 multiplexed signal configuration register 733 for multiplexed input selectio733" bitfld.long 0xB74 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB74 0.--7. 1. "SSS,Source Signal Select" line.long 0xB78 "MSCR_MUX734,SIUL2 multiplexed signal configuration register 734 for multiplexed input selectio734" bitfld.long 0xB78 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB78 0.--7. 1. "SSS,Source Signal Select" line.long 0xB7C "MSCR_MUX735,SIUL2 multiplexed signal configuration register 735 for multiplexed input selectio735" bitfld.long 0xB7C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB7C 0.--7. 1. "SSS,Source Signal Select" line.long 0xB80 "MSCR_MUX736,SIUL2 multiplexed signal configuration register 736 for multiplexed input selectio736" bitfld.long 0xB80 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB80 0.--7. 1. "SSS,Source Signal Select" line.long 0xB84 "MSCR_MUX737,SIUL2 multiplexed signal configuration register 737 for multiplexed input selectio737" bitfld.long 0xB84 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB84 0.--7. 1. "SSS,Source Signal Select" line.long 0xB88 "MSCR_MUX738,SIUL2 multiplexed signal configuration register 738 for multiplexed input selectio738" bitfld.long 0xB88 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB88 0.--7. 1. "SSS,Source Signal Select" line.long 0xB8C "MSCR_MUX739,SIUL2 multiplexed signal configuration register 739 for multiplexed input selectio739" bitfld.long 0xB8C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB8C 0.--7. 1. "SSS,Source Signal Select" line.long 0xB90 "MSCR_MUX740,SIUL2 multiplexed signal configuration register 740 for multiplexed input selectio740" bitfld.long 0xB90 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB90 0.--7. 1. "SSS,Source Signal Select" line.long 0xB94 "MSCR_MUX741,SIUL2 multiplexed signal configuration register 741 for multiplexed input selectio741" bitfld.long 0xB94 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB94 0.--7. 1. "SSS,Source Signal Select" line.long 0xB98 "MSCR_MUX742,SIUL2 multiplexed signal configuration register 742 for multiplexed input selectio742" bitfld.long 0xB98 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB98 0.--7. 1. "SSS,Source Signal Select" line.long 0xB9C "MSCR_MUX743,SIUL2 multiplexed signal configuration register 743 for multiplexed input selectio743" bitfld.long 0xB9C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xB9C 0.--7. 1. "SSS,Source Signal Select" line.long 0xBA0 "MSCR_MUX744,SIUL2 multiplexed signal configuration register 744 for multiplexed input selectio744" bitfld.long 0xBA0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBA0 0.--7. 1. "SSS,Source Signal Select" line.long 0xBA4 "MSCR_MUX745,SIUL2 multiplexed signal configuration register 745 for multiplexed input selectio745" bitfld.long 0xBA4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBA4 0.--7. 1. "SSS,Source Signal Select" line.long 0xBA8 "MSCR_MUX746,SIUL2 multiplexed signal configuration register 746 for multiplexed input selectio746" bitfld.long 0xBA8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBA8 0.--7. 1. "SSS,Source Signal Select" line.long 0xBAC "MSCR_MUX747,SIUL2 multiplexed signal configuration register 747 for multiplexed input selectio747" bitfld.long 0xBAC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBAC 0.--7. 1. "SSS,Source Signal Select" line.long 0xBB0 "MSCR_MUX748,SIUL2 multiplexed signal configuration register 748 for multiplexed input selectio748" bitfld.long 0xBB0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBB0 0.--7. 1. "SSS,Source Signal Select" line.long 0xBB4 "MSCR_MUX749,SIUL2 multiplexed signal configuration register 749 for multiplexed input selectio749" bitfld.long 0xBB4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBB4 0.--7. 1. "SSS,Source Signal Select" line.long 0xBB8 "MSCR_MUX750,SIUL2 multiplexed signal configuration register 750 for multiplexed input selectio750" bitfld.long 0xBB8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBB8 0.--7. 1. "SSS,Source Signal Select" line.long 0xBBC "MSCR_MUX751,SIUL2 multiplexed signal configuration register 751 for multiplexed input selectio751" bitfld.long 0xBBC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBBC 0.--7. 1. "SSS,Source Signal Select" line.long 0xBC0 "MSCR_MUX752,SIUL2 multiplexed signal configuration register 752 for multiplexed input selectio752" bitfld.long 0xBC0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBC0 0.--7. 1. "SSS,Source Signal Select" line.long 0xBC4 "MSCR_MUX753,SIUL2 multiplexed signal configuration register 753 for multiplexed input selectio753" bitfld.long 0xBC4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBC4 0.--7. 1. "SSS,Source Signal Select" line.long 0xBC8 "MSCR_MUX754,SIUL2 multiplexed signal configuration register 754 for multiplexed input selectio754" bitfld.long 0xBC8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBC8 0.--7. 1. "SSS,Source Signal Select" line.long 0xBCC "MSCR_MUX755,SIUL2 multiplexed signal configuration register 755 for multiplexed input selectio755" bitfld.long 0xBCC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBCC 0.--7. 1. "SSS,Source Signal Select" line.long 0xBD0 "MSCR_MUX756,SIUL2 multiplexed signal configuration register 756 for multiplexed input selectio756" bitfld.long 0xBD0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBD0 0.--7. 1. "SSS,Source Signal Select" line.long 0xBD4 "MSCR_MUX757,SIUL2 multiplexed signal configuration register 757 for multiplexed input selectio757" bitfld.long 0xBD4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBD4 0.--7. 1. "SSS,Source Signal Select" line.long 0xBD8 "MSCR_MUX758,SIUL2 multiplexed signal configuration register 758 for multiplexed input selectio758" bitfld.long 0xBD8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBD8 0.--7. 1. "SSS,Source Signal Select" line.long 0xBDC "MSCR_MUX759,SIUL2 multiplexed signal configuration register 759 for multiplexed input selectio759" bitfld.long 0xBDC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBDC 0.--7. 1. "SSS,Source Signal Select" line.long 0xBE0 "MSCR_MUX760,SIUL2 multiplexed signal configuration register 760 for multiplexed input selectio760" bitfld.long 0xBE0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBE0 0.--7. 1. "SSS,Source Signal Select" line.long 0xBE4 "MSCR_MUX761,SIUL2 multiplexed signal configuration register 761 for multiplexed input selectio761" bitfld.long 0xBE4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBE4 0.--7. 1. "SSS,Source Signal Select" line.long 0xBE8 "MSCR_MUX762,SIUL2 multiplexed signal configuration register 762 for multiplexed input selectio762" bitfld.long 0xBE8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBE8 0.--7. 1. "SSS,Source Signal Select" line.long 0xBEC "MSCR_MUX763,SIUL2 multiplexed signal configuration register 763 for multiplexed input selectio763" bitfld.long 0xBEC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBEC 0.--7. 1. "SSS,Source Signal Select" line.long 0xBF0 "MSCR_MUX764,SIUL2 multiplexed signal configuration register 764 for multiplexed input selectio764" bitfld.long 0xBF0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBF0 0.--7. 1. "SSS,Source Signal Select" line.long 0xBF4 "MSCR_MUX765,SIUL2 multiplexed signal configuration register 765 for multiplexed input selectio765" bitfld.long 0xBF4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBF4 0.--7. 1. "SSS,Source Signal Select" line.long 0xBF8 "MSCR_MUX766,SIUL2 multiplexed signal configuration register 766 for multiplexed input selectio766" bitfld.long 0xBF8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBF8 0.--7. 1. "SSS,Source Signal Select" line.long 0xBFC "MSCR_MUX767,SIUL2 multiplexed signal configuration register 767 for multiplexed input selectio767" bitfld.long 0xBFC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xBFC 0.--7. 1. "SSS,Source Signal Select" line.long 0xC00 "MSCR_MUX768,SIUL2 multiplexed signal configuration register 768 for multiplexed input selectio768" bitfld.long 0xC00 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC00 0.--7. 1. "SSS,Source Signal Select" line.long 0xC04 "MSCR_MUX769,SIUL2 multiplexed signal configuration register 769 for multiplexed input selectio769" bitfld.long 0xC04 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC04 0.--7. 1. "SSS,Source Signal Select" line.long 0xC08 "MSCR_MUX770,SIUL2 multiplexed signal configuration register 770 for multiplexed input selectio770" bitfld.long 0xC08 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC08 0.--7. 1. "SSS,Source Signal Select" line.long 0xC0C "MSCR_MUX771,SIUL2 multiplexed signal configuration register 771 for multiplexed input selectio771" bitfld.long 0xC0C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC0C 0.--7. 1. "SSS,Source Signal Select" line.long 0xC10 "MSCR_MUX772,SIUL2 multiplexed signal configuration register 772 for multiplexed input selectio772" bitfld.long 0xC10 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC10 0.--7. 1. "SSS,Source Signal Select" line.long 0xC14 "MSCR_MUX773,SIUL2 multiplexed signal configuration register 773 for multiplexed input selectio773" bitfld.long 0xC14 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC14 0.--7. 1. "SSS,Source Signal Select" line.long 0xC18 "MSCR_MUX774,SIUL2 multiplexed signal configuration register 774 for multiplexed input selectio774" bitfld.long 0xC18 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC18 0.--7. 1. "SSS,Source Signal Select" line.long 0xC1C "MSCR_MUX775,SIUL2 multiplexed signal configuration register 775 for multiplexed input selectio775" bitfld.long 0xC1C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC1C 0.--7. 1. "SSS,Source Signal Select" line.long 0xC20 "MSCR_MUX776,SIUL2 multiplexed signal configuration register 776 for multiplexed input selectio776" bitfld.long 0xC20 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC20 0.--7. 1. "SSS,Source Signal Select" line.long 0xC24 "MSCR_MUX777,SIUL2 multiplexed signal configuration register 777 for multiplexed input selectio777" bitfld.long 0xC24 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC24 0.--7. 1. "SSS,Source Signal Select" line.long 0xC28 "MSCR_MUX778,SIUL2 multiplexed signal configuration register 778 for multiplexed input selectio778" bitfld.long 0xC28 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC28 0.--7. 1. "SSS,Source Signal Select" line.long 0xC2C "MSCR_MUX779,SIUL2 multiplexed signal configuration register 779 for multiplexed input selectio779" bitfld.long 0xC2C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC2C 0.--7. 1. "SSS,Source Signal Select" line.long 0xC30 "MSCR_MUX780,SIUL2 multiplexed signal configuration register 780 for multiplexed input selectio780" bitfld.long 0xC30 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC30 0.--7. 1. "SSS,Source Signal Select" line.long 0xC34 "MSCR_MUX781,SIUL2 multiplexed signal configuration register 781 for multiplexed input selectio781" bitfld.long 0xC34 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC34 0.--7. 1. "SSS,Source Signal Select" line.long 0xC38 "MSCR_MUX782,SIUL2 multiplexed signal configuration register 782 for multiplexed input selectio782" bitfld.long 0xC38 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC38 0.--7. 1. "SSS,Source Signal Select" line.long 0xC3C "MSCR_MUX783,SIUL2 multiplexed signal configuration register 783 for multiplexed input selectio783" bitfld.long 0xC3C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC3C 0.--7. 1. "SSS,Source Signal Select" line.long 0xC40 "MSCR_MUX784,SIUL2 multiplexed signal configuration register 784 for multiplexed input selectio784" bitfld.long 0xC40 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC40 0.--7. 1. "SSS,Source Signal Select" line.long 0xC44 "MSCR_MUX785,SIUL2 multiplexed signal configuration register 785 for multiplexed input selectio785" bitfld.long 0xC44 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC44 0.--7. 1. "SSS,Source Signal Select" line.long 0xC48 "MSCR_MUX786,SIUL2 multiplexed signal configuration register 786 for multiplexed input selectio786" bitfld.long 0xC48 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC48 0.--7. 1. "SSS,Source Signal Select" line.long 0xC4C "MSCR_MUX787,SIUL2 multiplexed signal configuration register 787 for multiplexed input selectio787" bitfld.long 0xC4C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC4C 0.--7. 1. "SSS,Source Signal Select" line.long 0xC50 "MSCR_MUX788,SIUL2 multiplexed signal configuration register 788 for multiplexed input selectio788" bitfld.long 0xC50 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC50 0.--7. 1. "SSS,Source Signal Select" line.long 0xC54 "MSCR_MUX789,SIUL2 multiplexed signal configuration register 789 for multiplexed input selectio789" bitfld.long 0xC54 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC54 0.--7. 1. "SSS,Source Signal Select" line.long 0xC58 "MSCR_MUX790,SIUL2 multiplexed signal configuration register 790 for multiplexed input selectio790" bitfld.long 0xC58 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC58 0.--7. 1. "SSS,Source Signal Select" line.long 0xC5C "MSCR_MUX791,SIUL2 multiplexed signal configuration register 791 for multiplexed input selectio791" bitfld.long 0xC5C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC5C 0.--7. 1. "SSS,Source Signal Select" line.long 0xC60 "MSCR_MUX792,SIUL2 multiplexed signal configuration register 792 for multiplexed input selectio792" bitfld.long 0xC60 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC60 0.--7. 1. "SSS,Source Signal Select" line.long 0xC64 "MSCR_MUX793,SIUL2 multiplexed signal configuration register 793 for multiplexed input selectio793" bitfld.long 0xC64 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC64 0.--7. 1. "SSS,Source Signal Select" line.long 0xC68 "MSCR_MUX794,SIUL2 multiplexed signal configuration register 794 for multiplexed input selectio794" bitfld.long 0xC68 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC68 0.--7. 1. "SSS,Source Signal Select" line.long 0xC6C "MSCR_MUX795,SIUL2 multiplexed signal configuration register 795 for multiplexed input selectio795" bitfld.long 0xC6C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC6C 0.--7. 1. "SSS,Source Signal Select" line.long 0xC70 "MSCR_MUX796,SIUL2 multiplexed signal configuration register 796 for multiplexed input selectio796" bitfld.long 0xC70 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC70 0.--7. 1. "SSS,Source Signal Select" line.long 0xC74 "MSCR_MUX797,SIUL2 multiplexed signal configuration register 797 for multiplexed input selectio797" bitfld.long 0xC74 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC74 0.--7. 1. "SSS,Source Signal Select" line.long 0xC78 "MSCR_MUX798,SIUL2 multiplexed signal configuration register 798 for multiplexed input selectio798" bitfld.long 0xC78 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC78 0.--7. 1. "SSS,Source Signal Select" line.long 0xC7C "MSCR_MUX799,SIUL2 multiplexed signal configuration register 799 for multiplexed input selectio799" bitfld.long 0xC7C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC7C 0.--7. 1. "SSS,Source Signal Select" line.long 0xC80 "MSCR_MUX800,SIUL2 multiplexed signal configuration register 800 for multiplexed input selectio800" bitfld.long 0xC80 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC80 0.--7. 1. "SSS,Source Signal Select" line.long 0xC84 "MSCR_MUX801,SIUL2 multiplexed signal configuration register 801 for multiplexed input selectio801" bitfld.long 0xC84 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC84 0.--7. 1. "SSS,Source Signal Select" line.long 0xC88 "MSCR_MUX802,SIUL2 multiplexed signal configuration register 802 for multiplexed input selectio802" bitfld.long 0xC88 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC88 0.--7. 1. "SSS,Source Signal Select" line.long 0xC8C "MSCR_MUX803,SIUL2 multiplexed signal configuration register 803 for multiplexed input selectio803" bitfld.long 0xC8C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC8C 0.--7. 1. "SSS,Source Signal Select" line.long 0xC90 "MSCR_MUX804,SIUL2 multiplexed signal configuration register 804 for multiplexed input selectio804" bitfld.long 0xC90 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC90 0.--7. 1. "SSS,Source Signal Select" line.long 0xC94 "MSCR_MUX805,SIUL2 multiplexed signal configuration register 805 for multiplexed input selectio805" bitfld.long 0xC94 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC94 0.--7. 1. "SSS,Source Signal Select" line.long 0xC98 "MSCR_MUX806,SIUL2 multiplexed signal configuration register 806 for multiplexed input selectio806" bitfld.long 0xC98 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC98 0.--7. 1. "SSS,Source Signal Select" line.long 0xC9C "MSCR_MUX807,SIUL2 multiplexed signal configuration register 807 for multiplexed input selectio807" bitfld.long 0xC9C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xC9C 0.--7. 1. "SSS,Source Signal Select" line.long 0xCA0 "MSCR_MUX808,SIUL2 multiplexed signal configuration register 808 for multiplexed input selectio808" bitfld.long 0xCA0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCA0 0.--7. 1. "SSS,Source Signal Select" line.long 0xCA4 "MSCR_MUX809,SIUL2 multiplexed signal configuration register 809 for multiplexed input selectio809" bitfld.long 0xCA4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCA4 0.--7. 1. "SSS,Source Signal Select" line.long 0xCA8 "MSCR_MUX810,SIUL2 multiplexed signal configuration register 810 for multiplexed input selectio810" bitfld.long 0xCA8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCA8 0.--7. 1. "SSS,Source Signal Select" line.long 0xCAC "MSCR_MUX811,SIUL2 multiplexed signal configuration register 811 for multiplexed input selectio811" bitfld.long 0xCAC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCAC 0.--7. 1. "SSS,Source Signal Select" line.long 0xCB0 "MSCR_MUX812,SIUL2 multiplexed signal configuration register 812 for multiplexed input selectio812" bitfld.long 0xCB0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCB0 0.--7. 1. "SSS,Source Signal Select" line.long 0xCB4 "MSCR_MUX813,SIUL2 multiplexed signal configuration register 813 for multiplexed input selectio813" bitfld.long 0xCB4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCB4 0.--7. 1. "SSS,Source Signal Select" line.long 0xCB8 "MSCR_MUX814,SIUL2 multiplexed signal configuration register 814 for multiplexed input selectio814" bitfld.long 0xCB8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCB8 0.--7. 1. "SSS,Source Signal Select" line.long 0xCBC "MSCR_MUX815,SIUL2 multiplexed signal configuration register 815 for multiplexed input selectio815" bitfld.long 0xCBC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCBC 0.--7. 1. "SSS,Source Signal Select" line.long 0xCC0 "MSCR_MUX816,SIUL2 multiplexed signal configuration register 816 for multiplexed input selectio816" bitfld.long 0xCC0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCC0 0.--7. 1. "SSS,Source Signal Select" line.long 0xCC4 "MSCR_MUX817,SIUL2 multiplexed signal configuration register 817 for multiplexed input selectio817" bitfld.long 0xCC4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCC4 0.--7. 1. "SSS,Source Signal Select" line.long 0xCC8 "MSCR_MUX818,SIUL2 multiplexed signal configuration register 818 for multiplexed input selectio818" bitfld.long 0xCC8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCC8 0.--7. 1. "SSS,Source Signal Select" line.long 0xCCC "MSCR_MUX819,SIUL2 multiplexed signal configuration register 819 for multiplexed input selectio819" bitfld.long 0xCCC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCCC 0.--7. 1. "SSS,Source Signal Select" line.long 0xCD0 "MSCR_MUX820,SIUL2 multiplexed signal configuration register 820 for multiplexed input selectio820" bitfld.long 0xCD0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCD0 0.--7. 1. "SSS,Source Signal Select" line.long 0xCD4 "MSCR_MUX821,SIUL2 multiplexed signal configuration register 821 for multiplexed input selectio821" bitfld.long 0xCD4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCD4 0.--7. 1. "SSS,Source Signal Select" line.long 0xCD8 "MSCR_MUX822,SIUL2 multiplexed signal configuration register 822 for multiplexed input selectio822" bitfld.long 0xCD8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCD8 0.--7. 1. "SSS,Source Signal Select" line.long 0xCDC "MSCR_MUX823,SIUL2 multiplexed signal configuration register 823 for multiplexed input selectio823" bitfld.long 0xCDC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCDC 0.--7. 1. "SSS,Source Signal Select" line.long 0xCE0 "MSCR_MUX824,SIUL2 multiplexed signal configuration register 824 for multiplexed input selectio824" bitfld.long 0xCE0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCE0 0.--7. 1. "SSS,Source Signal Select" line.long 0xCE4 "MSCR_MUX825,SIUL2 multiplexed signal configuration register 825 for multiplexed input selectio825" bitfld.long 0xCE4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCE4 0.--7. 1. "SSS,Source Signal Select" line.long 0xCE8 "MSCR_MUX826,SIUL2 multiplexed signal configuration register 826 for multiplexed input selectio826" bitfld.long 0xCE8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCE8 0.--7. 1. "SSS,Source Signal Select" line.long 0xCEC "MSCR_MUX827,SIUL2 multiplexed signal configuration register 827 for multiplexed input selectio827" bitfld.long 0xCEC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCEC 0.--7. 1. "SSS,Source Signal Select" line.long 0xCF0 "MSCR_MUX828,SIUL2 multiplexed signal configuration register 828 for multiplexed input selectio828" bitfld.long 0xCF0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCF0 0.--7. 1. "SSS,Source Signal Select" line.long 0xCF4 "MSCR_MUX829,SIUL2 multiplexed signal configuration register 829 for multiplexed input selectio829" bitfld.long 0xCF4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCF4 0.--7. 1. "SSS,Source Signal Select" line.long 0xCF8 "MSCR_MUX830,SIUL2 multiplexed signal configuration register 830 for multiplexed input selectio830" bitfld.long 0xCF8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCF8 0.--7. 1. "SSS,Source Signal Select" line.long 0xCFC "MSCR_MUX831,SIUL2 multiplexed signal configuration register 831 for multiplexed input selectio831" bitfld.long 0xCFC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xCFC 0.--7. 1. "SSS,Source Signal Select" line.long 0xD00 "MSCR_MUX832,SIUL2 multiplexed signal configuration register 832 for multiplexed input selectio832" bitfld.long 0xD00 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD00 0.--7. 1. "SSS,Source Signal Select" line.long 0xD04 "MSCR_MUX833,SIUL2 multiplexed signal configuration register 833 for multiplexed input selectio833" bitfld.long 0xD04 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD04 0.--7. 1. "SSS,Source Signal Select" line.long 0xD08 "MSCR_MUX834,SIUL2 multiplexed signal configuration register 834 for multiplexed input selectio834" bitfld.long 0xD08 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD08 0.--7. 1. "SSS,Source Signal Select" line.long 0xD0C "MSCR_MUX835,SIUL2 multiplexed signal configuration register 835 for multiplexed input selectio835" bitfld.long 0xD0C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD0C 0.--7. 1. "SSS,Source Signal Select" line.long 0xD10 "MSCR_MUX836,SIUL2 multiplexed signal configuration register 836 for multiplexed input selectio836" bitfld.long 0xD10 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD10 0.--7. 1. "SSS,Source Signal Select" line.long 0xD14 "MSCR_MUX837,SIUL2 multiplexed signal configuration register 837 for multiplexed input selectio837" bitfld.long 0xD14 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD14 0.--7. 1. "SSS,Source Signal Select" line.long 0xD18 "MSCR_MUX838,SIUL2 multiplexed signal configuration register 838 for multiplexed input selectio838" bitfld.long 0xD18 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD18 0.--7. 1. "SSS,Source Signal Select" line.long 0xD1C "MSCR_MUX839,SIUL2 multiplexed signal configuration register 839 for multiplexed input selectio839" bitfld.long 0xD1C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD1C 0.--7. 1. "SSS,Source Signal Select" line.long 0xD20 "MSCR_MUX840,SIUL2 multiplexed signal configuration register 840 for multiplexed input selectio840" bitfld.long 0xD20 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD20 0.--7. 1. "SSS,Source Signal Select" line.long 0xD24 "MSCR_MUX841,SIUL2 multiplexed signal configuration register 841 for multiplexed input selectio841" bitfld.long 0xD24 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD24 0.--7. 1. "SSS,Source Signal Select" line.long 0xD28 "MSCR_MUX842,SIUL2 multiplexed signal configuration register 842 for multiplexed input selectio842" bitfld.long 0xD28 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD28 0.--7. 1. "SSS,Source Signal Select" line.long 0xD2C "MSCR_MUX843,SIUL2 multiplexed signal configuration register 843 for multiplexed input selectio843" bitfld.long 0xD2C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD2C 0.--7. 1. "SSS,Source Signal Select" line.long 0xD30 "MSCR_MUX844,SIUL2 multiplexed signal configuration register 844 for multiplexed input selectio844" bitfld.long 0xD30 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD30 0.--7. 1. "SSS,Source Signal Select" line.long 0xD34 "MSCR_MUX845,SIUL2 multiplexed signal configuration register 845 for multiplexed input selectio845" bitfld.long 0xD34 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD34 0.--7. 1. "SSS,Source Signal Select" line.long 0xD38 "MSCR_MUX846,SIUL2 multiplexed signal configuration register 846 for multiplexed input selectio846" bitfld.long 0xD38 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD38 0.--7. 1. "SSS,Source Signal Select" line.long 0xD3C "MSCR_MUX847,SIUL2 multiplexed signal configuration register 847 for multiplexed input selectio847" bitfld.long 0xD3C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD3C 0.--7. 1. "SSS,Source Signal Select" line.long 0xD40 "MSCR_MUX848,SIUL2 multiplexed signal configuration register 848 for multiplexed input selectio848" bitfld.long 0xD40 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD40 0.--7. 1. "SSS,Source Signal Select" line.long 0xD44 "MSCR_MUX849,SIUL2 multiplexed signal configuration register 849 for multiplexed input selectio849" bitfld.long 0xD44 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD44 0.--7. 1. "SSS,Source Signal Select" line.long 0xD48 "MSCR_MUX850,SIUL2 multiplexed signal configuration register 850 for multiplexed input selectio850" bitfld.long 0xD48 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD48 0.--7. 1. "SSS,Source Signal Select" line.long 0xD4C "MSCR_MUX851,SIUL2 multiplexed signal configuration register 851 for multiplexed input selectio851" bitfld.long 0xD4C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD4C 0.--7. 1. "SSS,Source Signal Select" line.long 0xD50 "MSCR_MUX852,SIUL2 multiplexed signal configuration register 852 for multiplexed input selectio852" bitfld.long 0xD50 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD50 0.--7. 1. "SSS,Source Signal Select" line.long 0xD54 "MSCR_MUX853,SIUL2 multiplexed signal configuration register 853 for multiplexed input selectio853" bitfld.long 0xD54 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD54 0.--7. 1. "SSS,Source Signal Select" line.long 0xD58 "MSCR_MUX854,SIUL2 multiplexed signal configuration register 854 for multiplexed input selectio854" bitfld.long 0xD58 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD58 0.--7. 1. "SSS,Source Signal Select" line.long 0xD5C "MSCR_MUX855,SIUL2 multiplexed signal configuration register 855 for multiplexed input selectio855" bitfld.long 0xD5C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD5C 0.--7. 1. "SSS,Source Signal Select" line.long 0xD60 "MSCR_MUX856,SIUL2 multiplexed signal configuration register 856 for multiplexed input selectio856" bitfld.long 0xD60 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD60 0.--7. 1. "SSS,Source Signal Select" line.long 0xD64 "MSCR_MUX857,SIUL2 multiplexed signal configuration register 857 for multiplexed input selectio857" bitfld.long 0xD64 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD64 0.--7. 1. "SSS,Source Signal Select" line.long 0xD68 "MSCR_MUX858,SIUL2 multiplexed signal configuration register 858 for multiplexed input selectio858" bitfld.long 0xD68 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD68 0.--7. 1. "SSS,Source Signal Select" line.long 0xD6C "MSCR_MUX859,SIUL2 multiplexed signal configuration register 859 for multiplexed input selectio859" bitfld.long 0xD6C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD6C 0.--7. 1. "SSS,Source Signal Select" line.long 0xD70 "MSCR_MUX860,SIUL2 multiplexed signal configuration register 860 for multiplexed input selectio860" bitfld.long 0xD70 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD70 0.--7. 1. "SSS,Source Signal Select" line.long 0xD74 "MSCR_MUX861,SIUL2 multiplexed signal configuration register 861 for multiplexed input selectio861" bitfld.long 0xD74 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD74 0.--7. 1. "SSS,Source Signal Select" line.long 0xD78 "MSCR_MUX862,SIUL2 multiplexed signal configuration register 862 for multiplexed input selectio862" bitfld.long 0xD78 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD78 0.--7. 1. "SSS,Source Signal Select" line.long 0xD7C "MSCR_MUX863,SIUL2 multiplexed signal configuration register 863 for multiplexed input selectio863" bitfld.long 0xD7C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD7C 0.--7. 1. "SSS,Source Signal Select" line.long 0xD80 "MSCR_MUX864,SIUL2 multiplexed signal configuration register 864 for multiplexed input selectio864" bitfld.long 0xD80 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD80 0.--7. 1. "SSS,Source Signal Select" line.long 0xD84 "MSCR_MUX865,SIUL2 multiplexed signal configuration register 865 for multiplexed input selectio865" bitfld.long 0xD84 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD84 0.--7. 1. "SSS,Source Signal Select" line.long 0xD88 "MSCR_MUX866,SIUL2 multiplexed signal configuration register 866 for multiplexed input selectio866" bitfld.long 0xD88 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD88 0.--7. 1. "SSS,Source Signal Select" line.long 0xD8C "MSCR_MUX867,SIUL2 multiplexed signal configuration register 867 for multiplexed input selectio867" bitfld.long 0xD8C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD8C 0.--7. 1. "SSS,Source Signal Select" line.long 0xD90 "MSCR_MUX868,SIUL2 multiplexed signal configuration register 868 for multiplexed input selectio868" bitfld.long 0xD90 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD90 0.--7. 1. "SSS,Source Signal Select" line.long 0xD94 "MSCR_MUX869,SIUL2 multiplexed signal configuration register 869 for multiplexed input selectio869" bitfld.long 0xD94 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD94 0.--7. 1. "SSS,Source Signal Select" line.long 0xD98 "MSCR_MUX870,SIUL2 multiplexed signal configuration register 870 for multiplexed input selectio870" bitfld.long 0xD98 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD98 0.--7. 1. "SSS,Source Signal Select" line.long 0xD9C "MSCR_MUX871,SIUL2 multiplexed signal configuration register 871 for multiplexed input selectio871" bitfld.long 0xD9C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xD9C 0.--7. 1. "SSS,Source Signal Select" line.long 0xDA0 "MSCR_MUX872,SIUL2 multiplexed signal configuration register 872 for multiplexed input selectio872" bitfld.long 0xDA0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDA0 0.--7. 1. "SSS,Source Signal Select" line.long 0xDA4 "MSCR_MUX873,SIUL2 multiplexed signal configuration register 873 for multiplexed input selectio873" bitfld.long 0xDA4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDA4 0.--7. 1. "SSS,Source Signal Select" line.long 0xDA8 "MSCR_MUX874,SIUL2 multiplexed signal configuration register 874 for multiplexed input selectio874" bitfld.long 0xDA8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDA8 0.--7. 1. "SSS,Source Signal Select" line.long 0xDAC "MSCR_MUX875,SIUL2 multiplexed signal configuration register 875 for multiplexed input selectio875" bitfld.long 0xDAC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDAC 0.--7. 1. "SSS,Source Signal Select" line.long 0xDB0 "MSCR_MUX876,SIUL2 multiplexed signal configuration register 876 for multiplexed input selectio876" bitfld.long 0xDB0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDB0 0.--7. 1. "SSS,Source Signal Select" line.long 0xDB4 "MSCR_MUX877,SIUL2 multiplexed signal configuration register 877 for multiplexed input selectio877" bitfld.long 0xDB4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDB4 0.--7. 1. "SSS,Source Signal Select" line.long 0xDB8 "MSCR_MUX878,SIUL2 multiplexed signal configuration register 878 for multiplexed input selectio878" bitfld.long 0xDB8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDB8 0.--7. 1. "SSS,Source Signal Select" line.long 0xDBC "MSCR_MUX879,SIUL2 multiplexed signal configuration register 879 for multiplexed input selectio879" bitfld.long 0xDBC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDBC 0.--7. 1. "SSS,Source Signal Select" line.long 0xDC0 "MSCR_MUX880,SIUL2 multiplexed signal configuration register 880 for multiplexed input selectio880" bitfld.long 0xDC0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDC0 0.--7. 1. "SSS,Source Signal Select" line.long 0xDC4 "MSCR_MUX881,SIUL2 multiplexed signal configuration register 881 for multiplexed input selectio881" bitfld.long 0xDC4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDC4 0.--7. 1. "SSS,Source Signal Select" line.long 0xDC8 "MSCR_MUX882,SIUL2 multiplexed signal configuration register 882 for multiplexed input selectio882" bitfld.long 0xDC8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDC8 0.--7. 1. "SSS,Source Signal Select" line.long 0xDCC "MSCR_MUX883,SIUL2 multiplexed signal configuration register 883 for multiplexed input selectio883" bitfld.long 0xDCC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDCC 0.--7. 1. "SSS,Source Signal Select" line.long 0xDD0 "MSCR_MUX884,SIUL2 multiplexed signal configuration register 884 for multiplexed input selectio884" bitfld.long 0xDD0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDD0 0.--7. 1. "SSS,Source Signal Select" line.long 0xDD4 "MSCR_MUX885,SIUL2 multiplexed signal configuration register 885 for multiplexed input selectio885" bitfld.long 0xDD4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDD4 0.--7. 1. "SSS,Source Signal Select" line.long 0xDD8 "MSCR_MUX886,SIUL2 multiplexed signal configuration register 886 for multiplexed input selectio886" bitfld.long 0xDD8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDD8 0.--7. 1. "SSS,Source Signal Select" line.long 0xDDC "MSCR_MUX887,SIUL2 multiplexed signal configuration register 887 for multiplexed input selectio887" bitfld.long 0xDDC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDDC 0.--7. 1. "SSS,Source Signal Select" line.long 0xDE0 "MSCR_MUX888,SIUL2 multiplexed signal configuration register 888 for multiplexed input selectio888" bitfld.long 0xDE0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDE0 0.--7. 1. "SSS,Source Signal Select" line.long 0xDE4 "MSCR_MUX889,SIUL2 multiplexed signal configuration register 889 for multiplexed input selectio889" bitfld.long 0xDE4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDE4 0.--7. 1. "SSS,Source Signal Select" line.long 0xDE8 "MSCR_MUX890,SIUL2 multiplexed signal configuration register 890 for multiplexed input selectio890" bitfld.long 0xDE8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDE8 0.--7. 1. "SSS,Source Signal Select" line.long 0xDEC "MSCR_MUX891,SIUL2 multiplexed signal configuration register 891 for multiplexed input selectio891" bitfld.long 0xDEC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDEC 0.--7. 1. "SSS,Source Signal Select" line.long 0xDF0 "MSCR_MUX892,SIUL2 multiplexed signal configuration register 892 for multiplexed input selectio892" bitfld.long 0xDF0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDF0 0.--7. 1. "SSS,Source Signal Select" line.long 0xDF4 "MSCR_MUX893,SIUL2 multiplexed signal configuration register 893 for multiplexed input selectio893" bitfld.long 0xDF4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDF4 0.--7. 1. "SSS,Source Signal Select" line.long 0xDF8 "MSCR_MUX894,SIUL2 multiplexed signal configuration register 894 for multiplexed input selectio894" bitfld.long 0xDF8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDF8 0.--7. 1. "SSS,Source Signal Select" line.long 0xDFC "MSCR_MUX895,SIUL2 multiplexed signal configuration register 895 for multiplexed input selectio895" bitfld.long 0xDFC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xDFC 0.--7. 1. "SSS,Source Signal Select" line.long 0xE00 "MSCR_MUX896,SIUL2 multiplexed signal configuration register 896 for multiplexed input selectio896" bitfld.long 0xE00 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE00 0.--7. 1. "SSS,Source Signal Select" line.long 0xE04 "MSCR_MUX897,SIUL2 multiplexed signal configuration register 897 for multiplexed input selectio897" bitfld.long 0xE04 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE04 0.--7. 1. "SSS,Source Signal Select" line.long 0xE08 "MSCR_MUX898,SIUL2 multiplexed signal configuration register 898 for multiplexed input selectio898" bitfld.long 0xE08 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE08 0.--7. 1. "SSS,Source Signal Select" line.long 0xE0C "MSCR_MUX899,SIUL2 multiplexed signal configuration register 899 for multiplexed input selectio899" bitfld.long 0xE0C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE0C 0.--7. 1. "SSS,Source Signal Select" line.long 0xE10 "MSCR_MUX900,SIUL2 multiplexed signal configuration register 900 for multiplexed input selectio900" bitfld.long 0xE10 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE10 0.--7. 1. "SSS,Source Signal Select" line.long 0xE14 "MSCR_MUX901,SIUL2 multiplexed signal configuration register 901 for multiplexed input selectio901" bitfld.long 0xE14 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE14 0.--7. 1. "SSS,Source Signal Select" line.long 0xE18 "MSCR_MUX902,SIUL2 multiplexed signal configuration register 902 for multiplexed input selectio902" bitfld.long 0xE18 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE18 0.--7. 1. "SSS,Source Signal Select" line.long 0xE1C "MSCR_MUX903,SIUL2 multiplexed signal configuration register 903 for multiplexed input selectio903" bitfld.long 0xE1C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE1C 0.--7. 1. "SSS,Source Signal Select" line.long 0xE20 "MSCR_MUX904,SIUL2 multiplexed signal configuration register 904 for multiplexed input selectio904" bitfld.long 0xE20 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE20 0.--7. 1. "SSS,Source Signal Select" line.long 0xE24 "MSCR_MUX905,SIUL2 multiplexed signal configuration register 905 for multiplexed input selectio905" bitfld.long 0xE24 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE24 0.--7. 1. "SSS,Source Signal Select" line.long 0xE28 "MSCR_MUX906,SIUL2 multiplexed signal configuration register 906 for multiplexed input selectio906" bitfld.long 0xE28 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE28 0.--7. 1. "SSS,Source Signal Select" line.long 0xE2C "MSCR_MUX907,SIUL2 multiplexed signal configuration register 907 for multiplexed input selectio907" bitfld.long 0xE2C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE2C 0.--7. 1. "SSS,Source Signal Select" line.long 0xE30 "MSCR_MUX908,SIUL2 multiplexed signal configuration register 908 for multiplexed input selectio908" bitfld.long 0xE30 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE30 0.--7. 1. "SSS,Source Signal Select" line.long 0xE34 "MSCR_MUX909,SIUL2 multiplexed signal configuration register 909 for multiplexed input selectio909" bitfld.long 0xE34 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE34 0.--7. 1. "SSS,Source Signal Select" line.long 0xE38 "MSCR_MUX910,SIUL2 multiplexed signal configuration register 910 for multiplexed input selectio910" bitfld.long 0xE38 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE38 0.--7. 1. "SSS,Source Signal Select" line.long 0xE3C "MSCR_MUX911,SIUL2 multiplexed signal configuration register 911 for multiplexed input selectio911" bitfld.long 0xE3C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE3C 0.--7. 1. "SSS,Source Signal Select" line.long 0xE40 "MSCR_MUX912,SIUL2 multiplexed signal configuration register 912 for multiplexed input selectio912" bitfld.long 0xE40 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE40 0.--7. 1. "SSS,Source Signal Select" line.long 0xE44 "MSCR_MUX913,SIUL2 multiplexed signal configuration register 913 for multiplexed input selectio913" bitfld.long 0xE44 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE44 0.--7. 1. "SSS,Source Signal Select" line.long 0xE48 "MSCR_MUX914,SIUL2 multiplexed signal configuration register 914 for multiplexed input selectio914" bitfld.long 0xE48 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE48 0.--7. 1. "SSS,Source Signal Select" line.long 0xE4C "MSCR_MUX915,SIUL2 multiplexed signal configuration register 915 for multiplexed input selectio915" bitfld.long 0xE4C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE4C 0.--7. 1. "SSS,Source Signal Select" line.long 0xE50 "MSCR_MUX916,SIUL2 multiplexed signal configuration register 916 for multiplexed input selectio916" bitfld.long 0xE50 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE50 0.--7. 1. "SSS,Source Signal Select" line.long 0xE54 "MSCR_MUX917,SIUL2 multiplexed signal configuration register 917 for multiplexed input selectio917" bitfld.long 0xE54 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE54 0.--7. 1. "SSS,Source Signal Select" line.long 0xE58 "MSCR_MUX918,SIUL2 multiplexed signal configuration register 918 for multiplexed input selectio918" bitfld.long 0xE58 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE58 0.--7. 1. "SSS,Source Signal Select" line.long 0xE5C "MSCR_MUX919,SIUL2 multiplexed signal configuration register 919 for multiplexed input selectio919" bitfld.long 0xE5C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE5C 0.--7. 1. "SSS,Source Signal Select" line.long 0xE60 "MSCR_MUX920,SIUL2 multiplexed signal configuration register 920 for multiplexed input selectio920" bitfld.long 0xE60 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE60 0.--7. 1. "SSS,Source Signal Select" line.long 0xE64 "MSCR_MUX921,SIUL2 multiplexed signal configuration register 921 for multiplexed input selectio921" bitfld.long 0xE64 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE64 0.--7. 1. "SSS,Source Signal Select" line.long 0xE68 "MSCR_MUX922,SIUL2 multiplexed signal configuration register 922 for multiplexed input selectio922" bitfld.long 0xE68 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE68 0.--7. 1. "SSS,Source Signal Select" line.long 0xE6C "MSCR_MUX923,SIUL2 multiplexed signal configuration register 923 for multiplexed input selectio923" bitfld.long 0xE6C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE6C 0.--7. 1. "SSS,Source Signal Select" line.long 0xE70 "MSCR_MUX924,SIUL2 multiplexed signal configuration register 924 for multiplexed input selectio924" bitfld.long 0xE70 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE70 0.--7. 1. "SSS,Source Signal Select" line.long 0xE74 "MSCR_MUX925,SIUL2 multiplexed signal configuration register 925 for multiplexed input selectio925" bitfld.long 0xE74 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE74 0.--7. 1. "SSS,Source Signal Select" line.long 0xE78 "MSCR_MUX926,SIUL2 multiplexed signal configuration register 926 for multiplexed input selectio926" bitfld.long 0xE78 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE78 0.--7. 1. "SSS,Source Signal Select" line.long 0xE7C "MSCR_MUX927,SIUL2 multiplexed signal configuration register 927 for multiplexed input selectio927" bitfld.long 0xE7C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE7C 0.--7. 1. "SSS,Source Signal Select" line.long 0xE80 "MSCR_MUX928,SIUL2 multiplexed signal configuration register 928 for multiplexed input selectio928" bitfld.long 0xE80 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE80 0.--7. 1. "SSS,Source Signal Select" line.long 0xE84 "MSCR_MUX929,SIUL2 multiplexed signal configuration register 929 for multiplexed input selectio929" bitfld.long 0xE84 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE84 0.--7. 1. "SSS,Source Signal Select" line.long 0xE88 "MSCR_MUX930,SIUL2 multiplexed signal configuration register 930 for multiplexed input selectio930" bitfld.long 0xE88 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE88 0.--7. 1. "SSS,Source Signal Select" line.long 0xE8C "MSCR_MUX931,SIUL2 multiplexed signal configuration register 931 for multiplexed input selectio931" bitfld.long 0xE8C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE8C 0.--7. 1. "SSS,Source Signal Select" line.long 0xE90 "MSCR_MUX932,SIUL2 multiplexed signal configuration register 932 for multiplexed input selectio932" bitfld.long 0xE90 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE90 0.--7. 1. "SSS,Source Signal Select" line.long 0xE94 "MSCR_MUX933,SIUL2 multiplexed signal configuration register 933 for multiplexed input selectio933" bitfld.long 0xE94 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE94 0.--7. 1. "SSS,Source Signal Select" line.long 0xE98 "MSCR_MUX934,SIUL2 multiplexed signal configuration register 934 for multiplexed input selectio934" bitfld.long 0xE98 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE98 0.--7. 1. "SSS,Source Signal Select" line.long 0xE9C "MSCR_MUX935,SIUL2 multiplexed signal configuration register 935 for multiplexed input selectio935" bitfld.long 0xE9C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xE9C 0.--7. 1. "SSS,Source Signal Select" line.long 0xEA0 "MSCR_MUX936,SIUL2 multiplexed signal configuration register 936 for multiplexed input selectio936" bitfld.long 0xEA0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEA0 0.--7. 1. "SSS,Source Signal Select" line.long 0xEA4 "MSCR_MUX937,SIUL2 multiplexed signal configuration register 937 for multiplexed input selectio937" bitfld.long 0xEA4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEA4 0.--7. 1. "SSS,Source Signal Select" line.long 0xEA8 "MSCR_MUX938,SIUL2 multiplexed signal configuration register 938 for multiplexed input selectio938" bitfld.long 0xEA8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEA8 0.--7. 1. "SSS,Source Signal Select" line.long 0xEAC "MSCR_MUX939,SIUL2 multiplexed signal configuration register 939 for multiplexed input selectio939" bitfld.long 0xEAC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEAC 0.--7. 1. "SSS,Source Signal Select" line.long 0xEB0 "MSCR_MUX940,SIUL2 multiplexed signal configuration register 940 for multiplexed input selectio940" bitfld.long 0xEB0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEB0 0.--7. 1. "SSS,Source Signal Select" line.long 0xEB4 "MSCR_MUX941,SIUL2 multiplexed signal configuration register 941 for multiplexed input selectio941" bitfld.long 0xEB4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEB4 0.--7. 1. "SSS,Source Signal Select" line.long 0xEB8 "MSCR_MUX942,SIUL2 multiplexed signal configuration register 942 for multiplexed input selectio942" bitfld.long 0xEB8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEB8 0.--7. 1. "SSS,Source Signal Select" line.long 0xEBC "MSCR_MUX943,SIUL2 multiplexed signal configuration register 943 for multiplexed input selectio943" bitfld.long 0xEBC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEBC 0.--7. 1. "SSS,Source Signal Select" line.long 0xEC0 "MSCR_MUX944,SIUL2 multiplexed signal configuration register 944 for multiplexed input selectio944" bitfld.long 0xEC0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEC0 0.--7. 1. "SSS,Source Signal Select" line.long 0xEC4 "MSCR_MUX945,SIUL2 multiplexed signal configuration register 945 for multiplexed input selectio945" bitfld.long 0xEC4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEC4 0.--7. 1. "SSS,Source Signal Select" line.long 0xEC8 "MSCR_MUX946,SIUL2 multiplexed signal configuration register 946 for multiplexed input selectio946" bitfld.long 0xEC8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEC8 0.--7. 1. "SSS,Source Signal Select" line.long 0xECC "MSCR_MUX947,SIUL2 multiplexed signal configuration register 947 for multiplexed input selectio947" bitfld.long 0xECC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xECC 0.--7. 1. "SSS,Source Signal Select" line.long 0xED0 "MSCR_MUX948,SIUL2 multiplexed signal configuration register 948 for multiplexed input selectio948" bitfld.long 0xED0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xED0 0.--7. 1. "SSS,Source Signal Select" line.long 0xED4 "MSCR_MUX949,SIUL2 multiplexed signal configuration register 949 for multiplexed input selectio949" bitfld.long 0xED4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xED4 0.--7. 1. "SSS,Source Signal Select" line.long 0xED8 "MSCR_MUX950,SIUL2 multiplexed signal configuration register 950 for multiplexed input selectio950" bitfld.long 0xED8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xED8 0.--7. 1. "SSS,Source Signal Select" line.long 0xEDC "MSCR_MUX951,SIUL2 multiplexed signal configuration register 951 for multiplexed input selectio951" bitfld.long 0xEDC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEDC 0.--7. 1. "SSS,Source Signal Select" line.long 0xEE0 "MSCR_MUX952,SIUL2 multiplexed signal configuration register 952 for multiplexed input selectio952" bitfld.long 0xEE0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEE0 0.--7. 1. "SSS,Source Signal Select" line.long 0xEE4 "MSCR_MUX953,SIUL2 multiplexed signal configuration register 953 for multiplexed input selectio953" bitfld.long 0xEE4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEE4 0.--7. 1. "SSS,Source Signal Select" line.long 0xEE8 "MSCR_MUX954,SIUL2 multiplexed signal configuration register 954 for multiplexed input selectio954" bitfld.long 0xEE8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEE8 0.--7. 1. "SSS,Source Signal Select" line.long 0xEEC "MSCR_MUX955,SIUL2 multiplexed signal configuration register 955 for multiplexed input selectio955" bitfld.long 0xEEC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEEC 0.--7. 1. "SSS,Source Signal Select" line.long 0xEF0 "MSCR_MUX956,SIUL2 multiplexed signal configuration register 956 for multiplexed input selectio956" bitfld.long 0xEF0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEF0 0.--7. 1. "SSS,Source Signal Select" line.long 0xEF4 "MSCR_MUX957,SIUL2 multiplexed signal configuration register 957 for multiplexed input selectio957" bitfld.long 0xEF4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEF4 0.--7. 1. "SSS,Source Signal Select" line.long 0xEF8 "MSCR_MUX958,SIUL2 multiplexed signal configuration register 958 for multiplexed input selectio958" bitfld.long 0xEF8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEF8 0.--7. 1. "SSS,Source Signal Select" line.long 0xEFC "MSCR_MUX959,SIUL2 multiplexed signal configuration register 959 for multiplexed input selectio959" bitfld.long 0xEFC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xEFC 0.--7. 1. "SSS,Source Signal Select" line.long 0xF00 "MSCR_MUX960,SIUL2 multiplexed signal configuration register 960 for multiplexed input selectio960" bitfld.long 0xF00 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF00 0.--7. 1. "SSS,Source Signal Select" line.long 0xF04 "MSCR_MUX961,SIUL2 multiplexed signal configuration register 961 for multiplexed input selectio961" bitfld.long 0xF04 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF04 0.--7. 1. "SSS,Source Signal Select" line.long 0xF08 "MSCR_MUX962,SIUL2 multiplexed signal configuration register 962 for multiplexed input selectio962" bitfld.long 0xF08 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF08 0.--7. 1. "SSS,Source Signal Select" line.long 0xF0C "MSCR_MUX963,SIUL2 multiplexed signal configuration register 963 for multiplexed input selectio963" bitfld.long 0xF0C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF0C 0.--7. 1. "SSS,Source Signal Select" line.long 0xF10 "MSCR_MUX964,SIUL2 multiplexed signal configuration register 964 for multiplexed input selectio964" bitfld.long 0xF10 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF10 0.--7. 1. "SSS,Source Signal Select" line.long 0xF14 "MSCR_MUX965,SIUL2 multiplexed signal configuration register 965 for multiplexed input selectio965" bitfld.long 0xF14 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF14 0.--7. 1. "SSS,Source Signal Select" line.long 0xF18 "MSCR_MUX966,SIUL2 multiplexed signal configuration register 966 for multiplexed input selectio966" bitfld.long 0xF18 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF18 0.--7. 1. "SSS,Source Signal Select" line.long 0xF1C "MSCR_MUX967,SIUL2 multiplexed signal configuration register 967 for multiplexed input selectio967" bitfld.long 0xF1C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF1C 0.--7. 1. "SSS,Source Signal Select" line.long 0xF20 "MSCR_MUX968,SIUL2 multiplexed signal configuration register 968 for multiplexed input selectio968" bitfld.long 0xF20 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF20 0.--7. 1. "SSS,Source Signal Select" line.long 0xF24 "MSCR_MUX969,SIUL2 multiplexed signal configuration register 969 for multiplexed input selectio969" bitfld.long 0xF24 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF24 0.--7. 1. "SSS,Source Signal Select" line.long 0xF28 "MSCR_MUX970,SIUL2 multiplexed signal configuration register 970 for multiplexed input selectio970" bitfld.long 0xF28 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF28 0.--7. 1. "SSS,Source Signal Select" line.long 0xF2C "MSCR_MUX971,SIUL2 multiplexed signal configuration register 971 for multiplexed input selectio971" bitfld.long 0xF2C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF2C 0.--7. 1. "SSS,Source Signal Select" line.long 0xF30 "MSCR_MUX972,SIUL2 multiplexed signal configuration register 972 for multiplexed input selectio972" bitfld.long 0xF30 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF30 0.--7. 1. "SSS,Source Signal Select" line.long 0xF34 "MSCR_MUX973,SIUL2 multiplexed signal configuration register 973 for multiplexed input selectio973" bitfld.long 0xF34 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF34 0.--7. 1. "SSS,Source Signal Select" line.long 0xF38 "MSCR_MUX974,SIUL2 multiplexed signal configuration register 974 for multiplexed input selectio974" bitfld.long 0xF38 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF38 0.--7. 1. "SSS,Source Signal Select" line.long 0xF3C "MSCR_MUX975,SIUL2 multiplexed signal configuration register 975 for multiplexed input selectio975" bitfld.long 0xF3C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF3C 0.--7. 1. "SSS,Source Signal Select" line.long 0xF40 "MSCR_MUX976,SIUL2 multiplexed signal configuration register 976 for multiplexed input selectio976" bitfld.long 0xF40 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF40 0.--7. 1. "SSS,Source Signal Select" line.long 0xF44 "MSCR_MUX977,SIUL2 multiplexed signal configuration register 977 for multiplexed input selectio977" bitfld.long 0xF44 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF44 0.--7. 1. "SSS,Source Signal Select" line.long 0xF48 "MSCR_MUX978,SIUL2 multiplexed signal configuration register 978 for multiplexed input selectio978" bitfld.long 0xF48 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF48 0.--7. 1. "SSS,Source Signal Select" line.long 0xF4C "MSCR_MUX979,SIUL2 multiplexed signal configuration register 979 for multiplexed input selectio979" bitfld.long 0xF4C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF4C 0.--7. 1. "SSS,Source Signal Select" line.long 0xF50 "MSCR_MUX980,SIUL2 multiplexed signal configuration register 980 for multiplexed input selectio980" bitfld.long 0xF50 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF50 0.--7. 1. "SSS,Source Signal Select" line.long 0xF54 "MSCR_MUX981,SIUL2 multiplexed signal configuration register 981 for multiplexed input selectio981" bitfld.long 0xF54 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF54 0.--7. 1. "SSS,Source Signal Select" line.long 0xF58 "MSCR_MUX982,SIUL2 multiplexed signal configuration register 982 for multiplexed input selectio982" bitfld.long 0xF58 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF58 0.--7. 1. "SSS,Source Signal Select" line.long 0xF5C "MSCR_MUX983,SIUL2 multiplexed signal configuration register 983 for multiplexed input selectio983" bitfld.long 0xF5C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF5C 0.--7. 1. "SSS,Source Signal Select" line.long 0xF60 "MSCR_MUX984,SIUL2 multiplexed signal configuration register 984 for multiplexed input selectio984" bitfld.long 0xF60 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF60 0.--7. 1. "SSS,Source Signal Select" line.long 0xF64 "MSCR_MUX985,SIUL2 multiplexed signal configuration register 985 for multiplexed input selectio985" bitfld.long 0xF64 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF64 0.--7. 1. "SSS,Source Signal Select" line.long 0xF68 "MSCR_MUX986,SIUL2 multiplexed signal configuration register 986 for multiplexed input selectio986" bitfld.long 0xF68 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF68 0.--7. 1. "SSS,Source Signal Select" line.long 0xF6C "MSCR_MUX987,SIUL2 multiplexed signal configuration register 987 for multiplexed input selectio987" bitfld.long 0xF6C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF6C 0.--7. 1. "SSS,Source Signal Select" line.long 0xF70 "MSCR_MUX988,SIUL2 multiplexed signal configuration register 988 for multiplexed input selectio988" bitfld.long 0xF70 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF70 0.--7. 1. "SSS,Source Signal Select" line.long 0xF74 "MSCR_MUX989,SIUL2 multiplexed signal configuration register 989 for multiplexed input selectio989" bitfld.long 0xF74 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF74 0.--7. 1. "SSS,Source Signal Select" line.long 0xF78 "MSCR_MUX990,SIUL2 multiplexed signal configuration register 990 for multiplexed input selectio990" bitfld.long 0xF78 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF78 0.--7. 1. "SSS,Source Signal Select" line.long 0xF7C "MSCR_MUX991,SIUL2 multiplexed signal configuration register 991 for multiplexed input selectio991" bitfld.long 0xF7C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF7C 0.--7. 1. "SSS,Source Signal Select" line.long 0xF80 "MSCR_MUX992,SIUL2 multiplexed signal configuration register 992 for multiplexed input selectio992" bitfld.long 0xF80 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF80 0.--7. 1. "SSS,Source Signal Select" line.long 0xF84 "MSCR_MUX993,SIUL2 multiplexed signal configuration register 993 for multiplexed input selectio993" bitfld.long 0xF84 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF84 0.--7. 1. "SSS,Source Signal Select" line.long 0xF88 "MSCR_MUX994,SIUL2 multiplexed signal configuration register 994 for multiplexed input selectio994" bitfld.long 0xF88 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF88 0.--7. 1. "SSS,Source Signal Select" line.long 0xF8C "MSCR_MUX995,SIUL2 multiplexed signal configuration register 995 for multiplexed input selectio995" bitfld.long 0xF8C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF8C 0.--7. 1. "SSS,Source Signal Select" line.long 0xF90 "MSCR_MUX996,SIUL2 multiplexed signal configuration register 996 for multiplexed input selectio996" bitfld.long 0xF90 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF90 0.--7. 1. "SSS,Source Signal Select" line.long 0xF94 "MSCR_MUX997,SIUL2 multiplexed signal configuration register 997 for multiplexed input selectio997" bitfld.long 0xF94 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF94 0.--7. 1. "SSS,Source Signal Select" line.long 0xF98 "MSCR_MUX998,SIUL2 multiplexed signal configuration register 998 for multiplexed input selectio998" bitfld.long 0xF98 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF98 0.--7. 1. "SSS,Source Signal Select" line.long 0xF9C "MSCR_MUX999,SIUL2 multiplexed signal configuration register 999 for multiplexed input selectio999" bitfld.long 0xF9C 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xF9C 0.--7. 1. "SSS,Source Signal Select" line.long 0xFA0 "MSCR_MUX1000,SIUL2 multiplexed signal configuration register 1000 for multiplexed input selectio1000" bitfld.long 0xFA0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFA0 0.--7. 1. "SSS,Source Signal Select" line.long 0xFA4 "MSCR_MUX1001,SIUL2 multiplexed signal configuration register 1001 for multiplexed input selectio1001" bitfld.long 0xFA4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFA4 0.--7. 1. "SSS,Source Signal Select" line.long 0xFA8 "MSCR_MUX1002,SIUL2 multiplexed signal configuration register 1002 for multiplexed input selectio1002" bitfld.long 0xFA8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFA8 0.--7. 1. "SSS,Source Signal Select" line.long 0xFAC "MSCR_MUX1003,SIUL2 multiplexed signal configuration register 1003 for multiplexed input selectio1003" bitfld.long 0xFAC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFAC 0.--7. 1. "SSS,Source Signal Select" line.long 0xFB0 "MSCR_MUX1004,SIUL2 multiplexed signal configuration register 1004 for multiplexed input selectio1004" bitfld.long 0xFB0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFB0 0.--7. 1. "SSS,Source Signal Select" line.long 0xFB4 "MSCR_MUX1005,SIUL2 multiplexed signal configuration register 1005 for multiplexed input selectio1005" bitfld.long 0xFB4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFB4 0.--7. 1. "SSS,Source Signal Select" line.long 0xFB8 "MSCR_MUX1006,SIUL2 multiplexed signal configuration register 1006 for multiplexed input selectio1006" bitfld.long 0xFB8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFB8 0.--7. 1. "SSS,Source Signal Select" line.long 0xFBC "MSCR_MUX1007,SIUL2 multiplexed signal configuration register 1007 for multiplexed input selectio1007" bitfld.long 0xFBC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFBC 0.--7. 1. "SSS,Source Signal Select" line.long 0xFC0 "MSCR_MUX1008,SIUL2 multiplexed signal configuration register 1008 for multiplexed input selectio1008" bitfld.long 0xFC0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFC0 0.--7. 1. "SSS,Source Signal Select" line.long 0xFC4 "MSCR_MUX1009,SIUL2 multiplexed signal configuration register 1009 for multiplexed input selectio1009" bitfld.long 0xFC4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFC4 0.--7. 1. "SSS,Source Signal Select" line.long 0xFC8 "MSCR_MUX1010,SIUL2 multiplexed signal configuration register 1010 for multiplexed input selectio1010" bitfld.long 0xFC8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFC8 0.--7. 1. "SSS,Source Signal Select" line.long 0xFCC "MSCR_MUX1011,SIUL2 multiplexed signal configuration register 1011 for multiplexed input selectio1011" bitfld.long 0xFCC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFCC 0.--7. 1. "SSS,Source Signal Select" line.long 0xFD0 "MSCR_MUX1012,SIUL2 multiplexed signal configuration register 1012 for multiplexed input selectio1012" bitfld.long 0xFD0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFD0 0.--7. 1. "SSS,Source Signal Select" line.long 0xFD4 "MSCR_MUX1013,SIUL2 multiplexed signal configuration register 1013 for multiplexed input selectio1013" bitfld.long 0xFD4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFD4 0.--7. 1. "SSS,Source Signal Select" line.long 0xFD8 "MSCR_MUX1014,SIUL2 multiplexed signal configuration register 1014 for multiplexed input selectio1014" bitfld.long 0xFD8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFD8 0.--7. 1. "SSS,Source Signal Select" line.long 0xFDC "MSCR_MUX1015,SIUL2 multiplexed signal configuration register 1015 for multiplexed input selectio1015" bitfld.long 0xFDC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFDC 0.--7. 1. "SSS,Source Signal Select" line.long 0xFE0 "MSCR_MUX1016,SIUL2 multiplexed signal configuration register 1016 for multiplexed input selectio1016" bitfld.long 0xFE0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFE0 0.--7. 1. "SSS,Source Signal Select" line.long 0xFE4 "MSCR_MUX1017,SIUL2 multiplexed signal configuration register 1017 for multiplexed input selectio1017" bitfld.long 0xFE4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFE4 0.--7. 1. "SSS,Source Signal Select" line.long 0xFE8 "MSCR_MUX1018,SIUL2 multiplexed signal configuration register 1018 for multiplexed input selectio1018" bitfld.long 0xFE8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFE8 0.--7. 1. "SSS,Source Signal Select" line.long 0xFEC "MSCR_MUX1019,SIUL2 multiplexed signal configuration register 1019 for multiplexed input selectio1019" bitfld.long 0xFEC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFEC 0.--7. 1. "SSS,Source Signal Select" line.long 0xFF0 "MSCR_MUX1020,SIUL2 multiplexed signal configuration register 1020 for multiplexed input selectio1020" bitfld.long 0xFF0 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFF0 0.--7. 1. "SSS,Source Signal Select" line.long 0xFF4 "MSCR_MUX1021,SIUL2 multiplexed signal configuration register 1021 for multiplexed input selectio1021" bitfld.long 0xFF4 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFF4 0.--7. 1. "SSS,Source Signal Select" line.long 0xFF8 "MSCR_MUX1022,SIUL2 multiplexed signal configuration register 1022 for multiplexed input selectio1022" bitfld.long 0xFF8 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFF8 0.--7. 1. "SSS,Source Signal Select" line.long 0xFFC "MSCR_MUX1023,SIUL2 multiplexed signal configuration register 1023 for multiplexed input selectio1023" bitfld.long 0xFFC 15. "INV,Invert" "0: SSS selected input signal is connected directly..,1: SSS selected input signal is inverted before it.." hexmask.long.byte 0xFFC 0.--7. 1. "SSS,Source Signal Select" group.byte 0x1300++0x3FF line.byte 0x0 "GPDO3,SIUL2 GPIO pad data out register n" bitfld.byte 0x0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1 "GPDO2,SIUL2 GPIO pad data out register n" bitfld.byte 0x1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x2 "GPDO1,SIUL2 GPIO pad data out register n" bitfld.byte 0x2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x3 "GPDO0,SIUL2 GPIO pad data out register n" bitfld.byte 0x3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x4 "GPDO7,SIUL2 GPIO pad data out register n" bitfld.byte 0x4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x5 "GPDO6,SIUL2 GPIO pad data out register n" bitfld.byte 0x5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x6 "GPDO5,SIUL2 GPIO pad data out register n" bitfld.byte 0x6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x7 "GPDO4,SIUL2 GPIO pad data out register n" bitfld.byte 0x7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x8 "GPDO11,SIUL2 GPIO pad data out register n" bitfld.byte 0x8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x9 "GPDO10,SIUL2 GPIO pad data out register n" bitfld.byte 0x9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA "GPDO9,SIUL2 GPIO pad data out register n" bitfld.byte 0xA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB "GPDO8,SIUL2 GPIO pad data out register n" bitfld.byte 0xB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC "GPDO15,SIUL2 GPIO pad data out register n" bitfld.byte 0xC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD "GPDO14,SIUL2 GPIO pad data out register n" bitfld.byte 0xD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE "GPDO13,SIUL2 GPIO pad data out register n" bitfld.byte 0xE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF "GPDO12,SIUL2 GPIO pad data out register n" bitfld.byte 0xF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x10 "GPDO19,SIUL2 GPIO pad data out register n" bitfld.byte 0x10 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x11 "GPDO18,SIUL2 GPIO pad data out register n" bitfld.byte 0x11 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x12 "GPDO17,SIUL2 GPIO pad data out register n" bitfld.byte 0x12 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x13 "GPDO16,SIUL2 GPIO pad data out register n" bitfld.byte 0x13 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x14 "GPDO23,SIUL2 GPIO pad data out register n" bitfld.byte 0x14 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x15 "GPDO22,SIUL2 GPIO pad data out register n" bitfld.byte 0x15 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x16 "GPDO21,SIUL2 GPIO pad data out register n" bitfld.byte 0x16 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x17 "GPDO20,SIUL2 GPIO pad data out register n" bitfld.byte 0x17 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x18 "GPDO27,SIUL2 GPIO pad data out register n" bitfld.byte 0x18 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x19 "GPDO26,SIUL2 GPIO pad data out register n" bitfld.byte 0x19 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A "GPDO25,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B "GPDO24,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C "GPDO31,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D "GPDO30,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E "GPDO29,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F "GPDO28,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x20 "GPDO35,SIUL2 GPIO pad data out register n" bitfld.byte 0x20 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x21 "GPDO34,SIUL2 GPIO pad data out register n" bitfld.byte 0x21 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x22 "GPDO33,SIUL2 GPIO pad data out register n" bitfld.byte 0x22 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x23 "GPDO32,SIUL2 GPIO pad data out register n" bitfld.byte 0x23 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x24 "GPDO39,SIUL2 GPIO pad data out register n" bitfld.byte 0x24 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x25 "GPDO38,SIUL2 GPIO pad data out register n" bitfld.byte 0x25 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x26 "GPDO37,SIUL2 GPIO pad data out register n" bitfld.byte 0x26 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x27 "GPDO36,SIUL2 GPIO pad data out register n" bitfld.byte 0x27 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x28 "GPDO43,SIUL2 GPIO pad data out register n" bitfld.byte 0x28 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x29 "GPDO42,SIUL2 GPIO pad data out register n" bitfld.byte 0x29 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x2A "GPDO41,SIUL2 GPIO pad data out register n" bitfld.byte 0x2A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x2B "GPDO40,SIUL2 GPIO pad data out register n" bitfld.byte 0x2B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x2C "GPDO47,SIUL2 GPIO pad data out register n" bitfld.byte 0x2C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x2D "GPDO46,SIUL2 GPIO pad data out register n" bitfld.byte 0x2D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x2E "GPDO45,SIUL2 GPIO pad data out register n" bitfld.byte 0x2E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x2F "GPDO44,SIUL2 GPIO pad data out register n" bitfld.byte 0x2F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x30 "GPDO51,SIUL2 GPIO pad data out register n" bitfld.byte 0x30 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x31 "GPDO50,SIUL2 GPIO pad data out register n" bitfld.byte 0x31 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x32 "GPDO49,SIUL2 GPIO pad data out register n" bitfld.byte 0x32 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x33 "GPDO48,SIUL2 GPIO pad data out register n" bitfld.byte 0x33 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x34 "GPDO55,SIUL2 GPIO pad data out register n" bitfld.byte 0x34 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x35 "GPDO54,SIUL2 GPIO pad data out register n" bitfld.byte 0x35 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x36 "GPDO53,SIUL2 GPIO pad data out register n" bitfld.byte 0x36 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x37 "GPDO52,SIUL2 GPIO pad data out register n" bitfld.byte 0x37 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x38 "GPDO59,SIUL2 GPIO pad data out register n" bitfld.byte 0x38 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x39 "GPDO58,SIUL2 GPIO pad data out register n" bitfld.byte 0x39 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x3A "GPDO57,SIUL2 GPIO pad data out register n" bitfld.byte 0x3A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x3B "GPDO56,SIUL2 GPIO pad data out register n" bitfld.byte 0x3B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x3C "GPDO63,SIUL2 GPIO pad data out register n" bitfld.byte 0x3C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x3D "GPDO62,SIUL2 GPIO pad data out register n" bitfld.byte 0x3D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x3E "GPDO61,SIUL2 GPIO pad data out register n" bitfld.byte 0x3E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x3F "GPDO60,SIUL2 GPIO pad data out register n" bitfld.byte 0x3F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x40 "GPDO67,SIUL2 GPIO pad data out register n" bitfld.byte 0x40 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x41 "GPDO66,SIUL2 GPIO pad data out register n" bitfld.byte 0x41 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x42 "GPDO65,SIUL2 GPIO pad data out register n" bitfld.byte 0x42 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x43 "GPDO64,SIUL2 GPIO pad data out register n" bitfld.byte 0x43 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x44 "GPDO71,SIUL2 GPIO pad data out register n" bitfld.byte 0x44 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x45 "GPDO70,SIUL2 GPIO pad data out register n" bitfld.byte 0x45 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x46 "GPDO69,SIUL2 GPIO pad data out register n" bitfld.byte 0x46 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x47 "GPDO68,SIUL2 GPIO pad data out register n" bitfld.byte 0x47 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x48 "GPDO75,SIUL2 GPIO pad data out register n" bitfld.byte 0x48 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x49 "GPDO74,SIUL2 GPIO pad data out register n" bitfld.byte 0x49 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x4A "GPDO73,SIUL2 GPIO pad data out register n" bitfld.byte 0x4A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x4B "GPDO72,SIUL2 GPIO pad data out register n" bitfld.byte 0x4B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x4C "GPDO79,SIUL2 GPIO pad data out register n" bitfld.byte 0x4C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x4D "GPDO78,SIUL2 GPIO pad data out register n" bitfld.byte 0x4D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x4E "GPDO77,SIUL2 GPIO pad data out register n" bitfld.byte 0x4E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x4F "GPDO76,SIUL2 GPIO pad data out register n" bitfld.byte 0x4F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x50 "GPDO83,SIUL2 GPIO pad data out register n" bitfld.byte 0x50 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x51 "GPDO82,SIUL2 GPIO pad data out register n" bitfld.byte 0x51 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x52 "GPDO81,SIUL2 GPIO pad data out register n" bitfld.byte 0x52 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x53 "GPDO80,SIUL2 GPIO pad data out register n" bitfld.byte 0x53 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x54 "GPDO87,SIUL2 GPIO pad data out register n" bitfld.byte 0x54 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x55 "GPDO86,SIUL2 GPIO pad data out register n" bitfld.byte 0x55 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x56 "GPDO85,SIUL2 GPIO pad data out register n" bitfld.byte 0x56 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x57 "GPDO84,SIUL2 GPIO pad data out register n" bitfld.byte 0x57 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x58 "GPDO91,SIUL2 GPIO pad data out register n" bitfld.byte 0x58 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x59 "GPDO90,SIUL2 GPIO pad data out register n" bitfld.byte 0x59 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x5A "GPDO89,SIUL2 GPIO pad data out register n" bitfld.byte 0x5A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x5B "GPDO88,SIUL2 GPIO pad data out register n" bitfld.byte 0x5B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x5C "GPDO95,SIUL2 GPIO pad data out register n" bitfld.byte 0x5C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x5D "GPDO94,SIUL2 GPIO pad data out register n" bitfld.byte 0x5D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x5E "GPDO93,SIUL2 GPIO pad data out register n" bitfld.byte 0x5E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x5F "GPDO92,SIUL2 GPIO pad data out register n" bitfld.byte 0x5F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x60 "GPDO99,SIUL2 GPIO pad data out register n" bitfld.byte 0x60 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x61 "GPDO98,SIUL2 GPIO pad data out register n" bitfld.byte 0x61 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x62 "GPDO97,SIUL2 GPIO pad data out register n" bitfld.byte 0x62 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x63 "GPDO96,SIUL2 GPIO pad data out register n" bitfld.byte 0x63 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x64 "GPDO103,SIUL2 GPIO pad data out register n" bitfld.byte 0x64 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x65 "GPDO102,SIUL2 GPIO pad data out register n" bitfld.byte 0x65 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x66 "GPDO101,SIUL2 GPIO pad data out register n" bitfld.byte 0x66 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x67 "GPDO100,SIUL2 GPIO pad data out register n" bitfld.byte 0x67 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x68 "GPDO107,SIUL2 GPIO pad data out register n" bitfld.byte 0x68 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x69 "GPDO106,SIUL2 GPIO pad data out register n" bitfld.byte 0x69 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x6A "GPDO105,SIUL2 GPIO pad data out register n" bitfld.byte 0x6A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x6B "GPDO104,SIUL2 GPIO pad data out register n" bitfld.byte 0x6B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x6C "GPDO111,SIUL2 GPIO pad data out register n" bitfld.byte 0x6C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x6D "GPDO110,SIUL2 GPIO pad data out register n" bitfld.byte 0x6D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x6E "GPDO109,SIUL2 GPIO pad data out register n" bitfld.byte 0x6E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x6F "GPDO108,SIUL2 GPIO pad data out register n" bitfld.byte 0x6F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x70 "GPDO115,SIUL2 GPIO pad data out register n" bitfld.byte 0x70 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x71 "GPDO114,SIUL2 GPIO pad data out register n" bitfld.byte 0x71 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x72 "GPDO113,SIUL2 GPIO pad data out register n" bitfld.byte 0x72 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x73 "GPDO112,SIUL2 GPIO pad data out register n" bitfld.byte 0x73 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x74 "GPDO119,SIUL2 GPIO pad data out register n" bitfld.byte 0x74 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x75 "GPDO118,SIUL2 GPIO pad data out register n" bitfld.byte 0x75 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x76 "GPDO117,SIUL2 GPIO pad data out register n" bitfld.byte 0x76 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x77 "GPDO116,SIUL2 GPIO pad data out register n" bitfld.byte 0x77 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x78 "GPDO123,SIUL2 GPIO pad data out register n" bitfld.byte 0x78 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x79 "GPDO122,SIUL2 GPIO pad data out register n" bitfld.byte 0x79 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x7A "GPDO121,SIUL2 GPIO pad data out register n" bitfld.byte 0x7A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x7B "GPDO120,SIUL2 GPIO pad data out register n" bitfld.byte 0x7B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x7C "GPDO127,SIUL2 GPIO pad data out register n" bitfld.byte 0x7C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x7D "GPDO126,SIUL2 GPIO pad data out register n" bitfld.byte 0x7D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x7E "GPDO125,SIUL2 GPIO pad data out register n" bitfld.byte 0x7E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x7F "GPDO124,SIUL2 GPIO pad data out register n" bitfld.byte 0x7F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x80 "GPDO131,SIUL2 GPIO pad data out register n" bitfld.byte 0x80 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x81 "GPDO130,SIUL2 GPIO pad data out register n" bitfld.byte 0x81 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x82 "GPDO129,SIUL2 GPIO pad data out register n" bitfld.byte 0x82 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x83 "GPDO128,SIUL2 GPIO pad data out register n" bitfld.byte 0x83 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x84 "GPDO135,SIUL2 GPIO pad data out register n" bitfld.byte 0x84 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x85 "GPDO134,SIUL2 GPIO pad data out register n" bitfld.byte 0x85 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x86 "GPDO133,SIUL2 GPIO pad data out register n" bitfld.byte 0x86 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x87 "GPDO132,SIUL2 GPIO pad data out register n" bitfld.byte 0x87 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x88 "GPDO139,SIUL2 GPIO pad data out register n" bitfld.byte 0x88 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x89 "GPDO138,SIUL2 GPIO pad data out register n" bitfld.byte 0x89 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x8A "GPDO137,SIUL2 GPIO pad data out register n" bitfld.byte 0x8A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x8B "GPDO136,SIUL2 GPIO pad data out register n" bitfld.byte 0x8B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x8C "GPDO143,SIUL2 GPIO pad data out register n" bitfld.byte 0x8C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x8D "GPDO142,SIUL2 GPIO pad data out register n" bitfld.byte 0x8D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x8E "GPDO141,SIUL2 GPIO pad data out register n" bitfld.byte 0x8E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x8F "GPDO140,SIUL2 GPIO pad data out register n" bitfld.byte 0x8F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x90 "GPDO147,SIUL2 GPIO pad data out register n" bitfld.byte 0x90 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x91 "GPDO146,SIUL2 GPIO pad data out register n" bitfld.byte 0x91 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x92 "GPDO145,SIUL2 GPIO pad data out register n" bitfld.byte 0x92 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x93 "GPDO144,SIUL2 GPIO pad data out register n" bitfld.byte 0x93 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x94 "GPDO151,SIUL2 GPIO pad data out register n" bitfld.byte 0x94 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x95 "GPDO150,SIUL2 GPIO pad data out register n" bitfld.byte 0x95 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x96 "GPDO149,SIUL2 GPIO pad data out register n" bitfld.byte 0x96 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x97 "GPDO148,SIUL2 GPIO pad data out register n" bitfld.byte 0x97 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x98 "GPDO155,SIUL2 GPIO pad data out register n" bitfld.byte 0x98 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x99 "GPDO154,SIUL2 GPIO pad data out register n" bitfld.byte 0x99 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x9A "GPDO153,SIUL2 GPIO pad data out register n" bitfld.byte 0x9A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x9B "GPDO152,SIUL2 GPIO pad data out register n" bitfld.byte 0x9B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x9C "GPDO159,SIUL2 GPIO pad data out register n" bitfld.byte 0x9C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x9D "GPDO158,SIUL2 GPIO pad data out register n" bitfld.byte 0x9D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x9E "GPDO157,SIUL2 GPIO pad data out register n" bitfld.byte 0x9E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x9F "GPDO156,SIUL2 GPIO pad data out register n" bitfld.byte 0x9F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA0 "GPDO163,SIUL2 GPIO pad data out register n" bitfld.byte 0xA0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA1 "GPDO162,SIUL2 GPIO pad data out register n" bitfld.byte 0xA1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA2 "GPDO161,SIUL2 GPIO pad data out register n" bitfld.byte 0xA2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA3 "GPDO160,SIUL2 GPIO pad data out register n" bitfld.byte 0xA3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA4 "GPDO167,SIUL2 GPIO pad data out register n" bitfld.byte 0xA4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA5 "GPDO166,SIUL2 GPIO pad data out register n" bitfld.byte 0xA5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA6 "GPDO165,SIUL2 GPIO pad data out register n" bitfld.byte 0xA6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA7 "GPDO164,SIUL2 GPIO pad data out register n" bitfld.byte 0xA7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA8 "GPDO171,SIUL2 GPIO pad data out register n" bitfld.byte 0xA8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xA9 "GPDO170,SIUL2 GPIO pad data out register n" bitfld.byte 0xA9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xAA "GPDO169,SIUL2 GPIO pad data out register n" bitfld.byte 0xAA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xAB "GPDO168,SIUL2 GPIO pad data out register n" bitfld.byte 0xAB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xAC "GPDO175,SIUL2 GPIO pad data out register n" bitfld.byte 0xAC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xAD "GPDO174,SIUL2 GPIO pad data out register n" bitfld.byte 0xAD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xAE "GPDO173,SIUL2 GPIO pad data out register n" bitfld.byte 0xAE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xAF "GPDO172,SIUL2 GPIO pad data out register n" bitfld.byte 0xAF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB0 "GPDO179,SIUL2 GPIO pad data out register n" bitfld.byte 0xB0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB1 "GPDO178,SIUL2 GPIO pad data out register n" bitfld.byte 0xB1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB2 "GPDO177,SIUL2 GPIO pad data out register n" bitfld.byte 0xB2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB3 "GPDO176,SIUL2 GPIO pad data out register n" bitfld.byte 0xB3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB4 "GPDO183,SIUL2 GPIO pad data out register n" bitfld.byte 0xB4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB5 "GPDO182,SIUL2 GPIO pad data out register n" bitfld.byte 0xB5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB6 "GPDO181,SIUL2 GPIO pad data out register n" bitfld.byte 0xB6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB7 "GPDO180,SIUL2 GPIO pad data out register n" bitfld.byte 0xB7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB8 "GPDO187,SIUL2 GPIO pad data out register n" bitfld.byte 0xB8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xB9 "GPDO186,SIUL2 GPIO pad data out register n" bitfld.byte 0xB9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xBA "GPDO185,SIUL2 GPIO pad data out register n" bitfld.byte 0xBA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xBB "GPDO184,SIUL2 GPIO pad data out register n" bitfld.byte 0xBB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xBC "GPDO191,SIUL2 GPIO pad data out register n" bitfld.byte 0xBC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xBD "GPDO190,SIUL2 GPIO pad data out register n" bitfld.byte 0xBD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xBE "GPDO189,SIUL2 GPIO pad data out register n" bitfld.byte 0xBE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xBF "GPDO188,SIUL2 GPIO pad data out register n" bitfld.byte 0xBF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC0 "GPDO195,SIUL2 GPIO pad data out register n" bitfld.byte 0xC0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC1 "GPDO194,SIUL2 GPIO pad data out register n" bitfld.byte 0xC1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC2 "GPDO193,SIUL2 GPIO pad data out register n" bitfld.byte 0xC2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC3 "GPDO192,SIUL2 GPIO pad data out register n" bitfld.byte 0xC3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC4 "GPDO199,SIUL2 GPIO pad data out register n" bitfld.byte 0xC4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC5 "GPDO198,SIUL2 GPIO pad data out register n" bitfld.byte 0xC5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC6 "GPDO197,SIUL2 GPIO pad data out register n" bitfld.byte 0xC6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC7 "GPDO196,SIUL2 GPIO pad data out register n" bitfld.byte 0xC7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC8 "GPDO203,SIUL2 GPIO pad data out register n" bitfld.byte 0xC8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xC9 "GPDO202,SIUL2 GPIO pad data out register n" bitfld.byte 0xC9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xCA "GPDO201,SIUL2 GPIO pad data out register n" bitfld.byte 0xCA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xCB "GPDO200,SIUL2 GPIO pad data out register n" bitfld.byte 0xCB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xCC "GPDO207,SIUL2 GPIO pad data out register n" bitfld.byte 0xCC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xCD "GPDO206,SIUL2 GPIO pad data out register n" bitfld.byte 0xCD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xCE "GPDO205,SIUL2 GPIO pad data out register n" bitfld.byte 0xCE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xCF "GPDO204,SIUL2 GPIO pad data out register n" bitfld.byte 0xCF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD0 "GPDO211,SIUL2 GPIO pad data out register n" bitfld.byte 0xD0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD1 "GPDO210,SIUL2 GPIO pad data out register n" bitfld.byte 0xD1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD2 "GPDO209,SIUL2 GPIO pad data out register n" bitfld.byte 0xD2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD3 "GPDO208,SIUL2 GPIO pad data out register n" bitfld.byte 0xD3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD4 "GPDO215,SIUL2 GPIO pad data out register n" bitfld.byte 0xD4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD5 "GPDO214,SIUL2 GPIO pad data out register n" bitfld.byte 0xD5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD6 "GPDO213,SIUL2 GPIO pad data out register n" bitfld.byte 0xD6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD7 "GPDO212,SIUL2 GPIO pad data out register n" bitfld.byte 0xD7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD8 "GPDO219,SIUL2 GPIO pad data out register n" bitfld.byte 0xD8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xD9 "GPDO218,SIUL2 GPIO pad data out register n" bitfld.byte 0xD9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xDA "GPDO217,SIUL2 GPIO pad data out register n" bitfld.byte 0xDA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xDB "GPDO216,SIUL2 GPIO pad data out register n" bitfld.byte 0xDB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xDC "GPDO223,SIUL2 GPIO pad data out register n" bitfld.byte 0xDC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xDD "GPDO222,SIUL2 GPIO pad data out register n" bitfld.byte 0xDD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xDE "GPDO221,SIUL2 GPIO pad data out register n" bitfld.byte 0xDE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xDF "GPDO220,SIUL2 GPIO pad data out register n" bitfld.byte 0xDF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE0 "GPDO227,SIUL2 GPIO pad data out register n" bitfld.byte 0xE0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE1 "GPDO226,SIUL2 GPIO pad data out register n" bitfld.byte 0xE1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE2 "GPDO225,SIUL2 GPIO pad data out register n" bitfld.byte 0xE2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE3 "GPDO224,SIUL2 GPIO pad data out register n" bitfld.byte 0xE3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE4 "GPDO231,SIUL2 GPIO pad data out register n" bitfld.byte 0xE4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE5 "GPDO230,SIUL2 GPIO pad data out register n" bitfld.byte 0xE5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE6 "GPDO229,SIUL2 GPIO pad data out register n" bitfld.byte 0xE6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE7 "GPDO228,SIUL2 GPIO pad data out register n" bitfld.byte 0xE7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE8 "GPDO235,SIUL2 GPIO pad data out register n" bitfld.byte 0xE8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xE9 "GPDO234,SIUL2 GPIO pad data out register n" bitfld.byte 0xE9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xEA "GPDO233,SIUL2 GPIO pad data out register n" bitfld.byte 0xEA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xEB "GPDO232,SIUL2 GPIO pad data out register n" bitfld.byte 0xEB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xEC "GPDO239,SIUL2 GPIO pad data out register n" bitfld.byte 0xEC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xED "GPDO238,SIUL2 GPIO pad data out register n" bitfld.byte 0xED 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xEE "GPDO237,SIUL2 GPIO pad data out register n" bitfld.byte 0xEE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xEF "GPDO236,SIUL2 GPIO pad data out register n" bitfld.byte 0xEF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF0 "GPDO243,SIUL2 GPIO pad data out register n" bitfld.byte 0xF0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF1 "GPDO242,SIUL2 GPIO pad data out register n" bitfld.byte 0xF1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF2 "GPDO241,SIUL2 GPIO pad data out register n" bitfld.byte 0xF2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF3 "GPDO240,SIUL2 GPIO pad data out register n" bitfld.byte 0xF3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF4 "GPDO247,SIUL2 GPIO pad data out register n" bitfld.byte 0xF4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF5 "GPDO246,SIUL2 GPIO pad data out register n" bitfld.byte 0xF5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF6 "GPDO245,SIUL2 GPIO pad data out register n" bitfld.byte 0xF6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF7 "GPDO244,SIUL2 GPIO pad data out register n" bitfld.byte 0xF7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF8 "GPDO251,SIUL2 GPIO pad data out register n" bitfld.byte 0xF8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xF9 "GPDO250,SIUL2 GPIO pad data out register n" bitfld.byte 0xF9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xFA "GPDO249,SIUL2 GPIO pad data out register n" bitfld.byte 0xFA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xFB "GPDO248,SIUL2 GPIO pad data out register n" bitfld.byte 0xFB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xFC "GPDO255,SIUL2 GPIO pad data out register n" bitfld.byte 0xFC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xFD "GPDO254,SIUL2 GPIO pad data out register n" bitfld.byte 0xFD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xFE "GPDO253,SIUL2 GPIO pad data out register n" bitfld.byte 0xFE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0xFF "GPDO252,SIUL2 GPIO pad data out register n" bitfld.byte 0xFF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x100 "GPDO259,SIUL2 GPIO pad data out register n" bitfld.byte 0x100 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x101 "GPDO258,SIUL2 GPIO pad data out register n" bitfld.byte 0x101 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x102 "GPDO257,SIUL2 GPIO pad data out register n" bitfld.byte 0x102 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x103 "GPDO256,SIUL2 GPIO pad data out register n" bitfld.byte 0x103 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x104 "GPDO263,SIUL2 GPIO pad data out register n" bitfld.byte 0x104 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x105 "GPDO262,SIUL2 GPIO pad data out register n" bitfld.byte 0x105 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x106 "GPDO261,SIUL2 GPIO pad data out register n" bitfld.byte 0x106 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x107 "GPDO260,SIUL2 GPIO pad data out register n" bitfld.byte 0x107 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x108 "GPDO267,SIUL2 GPIO pad data out register n" bitfld.byte 0x108 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x109 "GPDO266,SIUL2 GPIO pad data out register n" bitfld.byte 0x109 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x10A "GPDO265,SIUL2 GPIO pad data out register n" bitfld.byte 0x10A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x10B "GPDO264,SIUL2 GPIO pad data out register n" bitfld.byte 0x10B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x10C "GPDO271,SIUL2 GPIO pad data out register n" bitfld.byte 0x10C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x10D "GPDO270,SIUL2 GPIO pad data out register n" bitfld.byte 0x10D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x10E "GPDO269,SIUL2 GPIO pad data out register n" bitfld.byte 0x10E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x10F "GPDO268,SIUL2 GPIO pad data out register n" bitfld.byte 0x10F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x110 "GPDO275,SIUL2 GPIO pad data out register n" bitfld.byte 0x110 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x111 "GPDO274,SIUL2 GPIO pad data out register n" bitfld.byte 0x111 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x112 "GPDO273,SIUL2 GPIO pad data out register n" bitfld.byte 0x112 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x113 "GPDO272,SIUL2 GPIO pad data out register n" bitfld.byte 0x113 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x114 "GPDO279,SIUL2 GPIO pad data out register n" bitfld.byte 0x114 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x115 "GPDO278,SIUL2 GPIO pad data out register n" bitfld.byte 0x115 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x116 "GPDO277,SIUL2 GPIO pad data out register n" bitfld.byte 0x116 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x117 "GPDO276,SIUL2 GPIO pad data out register n" bitfld.byte 0x117 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x118 "GPDO283,SIUL2 GPIO pad data out register n" bitfld.byte 0x118 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x119 "GPDO282,SIUL2 GPIO pad data out register n" bitfld.byte 0x119 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x11A "GPDO281,SIUL2 GPIO pad data out register n" bitfld.byte 0x11A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x11B "GPDO280,SIUL2 GPIO pad data out register n" bitfld.byte 0x11B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x11C "GPDO287,SIUL2 GPIO pad data out register n" bitfld.byte 0x11C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x11D "GPDO286,SIUL2 GPIO pad data out register n" bitfld.byte 0x11D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x11E "GPDO285,SIUL2 GPIO pad data out register n" bitfld.byte 0x11E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x11F "GPDO284,SIUL2 GPIO pad data out register n" bitfld.byte 0x11F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x120 "GPDO291,SIUL2 GPIO pad data out register n" bitfld.byte 0x120 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x121 "GPDO290,SIUL2 GPIO pad data out register n" bitfld.byte 0x121 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x122 "GPDO289,SIUL2 GPIO pad data out register n" bitfld.byte 0x122 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x123 "GPDO288,SIUL2 GPIO pad data out register n" bitfld.byte 0x123 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x124 "GPDO295,SIUL2 GPIO pad data out register n" bitfld.byte 0x124 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x125 "GPDO294,SIUL2 GPIO pad data out register n" bitfld.byte 0x125 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x126 "GPDO293,SIUL2 GPIO pad data out register n" bitfld.byte 0x126 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x127 "GPDO292,SIUL2 GPIO pad data out register n" bitfld.byte 0x127 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x128 "GPDO299,SIUL2 GPIO pad data out register n" bitfld.byte 0x128 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x129 "GPDO298,SIUL2 GPIO pad data out register n" bitfld.byte 0x129 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x12A "GPDO297,SIUL2 GPIO pad data out register n" bitfld.byte 0x12A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x12B "GPDO296,SIUL2 GPIO pad data out register n" bitfld.byte 0x12B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x12C "GPDO303,SIUL2 GPIO pad data out register n" bitfld.byte 0x12C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x12D "GPDO302,SIUL2 GPIO pad data out register n" bitfld.byte 0x12D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x12E "GPDO301,SIUL2 GPIO pad data out register n" bitfld.byte 0x12E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x12F "GPDO300,SIUL2 GPIO pad data out register n" bitfld.byte 0x12F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x130 "GPDO307,SIUL2 GPIO pad data out register n" bitfld.byte 0x130 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x131 "GPDO306,SIUL2 GPIO pad data out register n" bitfld.byte 0x131 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x132 "GPDO305,SIUL2 GPIO pad data out register n" bitfld.byte 0x132 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x133 "GPDO304,SIUL2 GPIO pad data out register n" bitfld.byte 0x133 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x134 "GPDO311,SIUL2 GPIO pad data out register n" bitfld.byte 0x134 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x135 "GPDO310,SIUL2 GPIO pad data out register n" bitfld.byte 0x135 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x136 "GPDO309,SIUL2 GPIO pad data out register n" bitfld.byte 0x136 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x137 "GPDO308,SIUL2 GPIO pad data out register n" bitfld.byte 0x137 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x138 "GPDO315,SIUL2 GPIO pad data out register n" bitfld.byte 0x138 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x139 "GPDO314,SIUL2 GPIO pad data out register n" bitfld.byte 0x139 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x13A "GPDO313,SIUL2 GPIO pad data out register n" bitfld.byte 0x13A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x13B "GPDO312,SIUL2 GPIO pad data out register n" bitfld.byte 0x13B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x13C "GPDO319,SIUL2 GPIO pad data out register n" bitfld.byte 0x13C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x13D "GPDO318,SIUL2 GPIO pad data out register n" bitfld.byte 0x13D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x13E "GPDO317,SIUL2 GPIO pad data out register n" bitfld.byte 0x13E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x13F "GPDO316,SIUL2 GPIO pad data out register n" bitfld.byte 0x13F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x140 "GPDO323,SIUL2 GPIO pad data out register n" bitfld.byte 0x140 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x141 "GPDO322,SIUL2 GPIO pad data out register n" bitfld.byte 0x141 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x142 "GPDO321,SIUL2 GPIO pad data out register n" bitfld.byte 0x142 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x143 "GPDO320,SIUL2 GPIO pad data out register n" bitfld.byte 0x143 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x144 "GPDO327,SIUL2 GPIO pad data out register n" bitfld.byte 0x144 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x145 "GPDO326,SIUL2 GPIO pad data out register n" bitfld.byte 0x145 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x146 "GPDO325,SIUL2 GPIO pad data out register n" bitfld.byte 0x146 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x147 "GPDO324,SIUL2 GPIO pad data out register n" bitfld.byte 0x147 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x148 "GPDO331,SIUL2 GPIO pad data out register n" bitfld.byte 0x148 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x149 "GPDO330,SIUL2 GPIO pad data out register n" bitfld.byte 0x149 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x14A "GPDO329,SIUL2 GPIO pad data out register n" bitfld.byte 0x14A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x14B "GPDO328,SIUL2 GPIO pad data out register n" bitfld.byte 0x14B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x14C "GPDO335,SIUL2 GPIO pad data out register n" bitfld.byte 0x14C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x14D "GPDO334,SIUL2 GPIO pad data out register n" bitfld.byte 0x14D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x14E "GPDO333,SIUL2 GPIO pad data out register n" bitfld.byte 0x14E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x14F "GPDO332,SIUL2 GPIO pad data out register n" bitfld.byte 0x14F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x150 "GPDO339,SIUL2 GPIO pad data out register n" bitfld.byte 0x150 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x151 "GPDO338,SIUL2 GPIO pad data out register n" bitfld.byte 0x151 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x152 "GPDO337,SIUL2 GPIO pad data out register n" bitfld.byte 0x152 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x153 "GPDO336,SIUL2 GPIO pad data out register n" bitfld.byte 0x153 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x154 "GPDO343,SIUL2 GPIO pad data out register n" bitfld.byte 0x154 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x155 "GPDO342,SIUL2 GPIO pad data out register n" bitfld.byte 0x155 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x156 "GPDO341,SIUL2 GPIO pad data out register n" bitfld.byte 0x156 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x157 "GPDO340,SIUL2 GPIO pad data out register n" bitfld.byte 0x157 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x158 "GPDO347,SIUL2 GPIO pad data out register n" bitfld.byte 0x158 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x159 "GPDO346,SIUL2 GPIO pad data out register n" bitfld.byte 0x159 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x15A "GPDO345,SIUL2 GPIO pad data out register n" bitfld.byte 0x15A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x15B "GPDO344,SIUL2 GPIO pad data out register n" bitfld.byte 0x15B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x15C "GPDO351,SIUL2 GPIO pad data out register n" bitfld.byte 0x15C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x15D "GPDO350,SIUL2 GPIO pad data out register n" bitfld.byte 0x15D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x15E "GPDO349,SIUL2 GPIO pad data out register n" bitfld.byte 0x15E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x15F "GPDO348,SIUL2 GPIO pad data out register n" bitfld.byte 0x15F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x160 "GPDO355,SIUL2 GPIO pad data out register n" bitfld.byte 0x160 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x161 "GPDO354,SIUL2 GPIO pad data out register n" bitfld.byte 0x161 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x162 "GPDO353,SIUL2 GPIO pad data out register n" bitfld.byte 0x162 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x163 "GPDO352,SIUL2 GPIO pad data out register n" bitfld.byte 0x163 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x164 "GPDO359,SIUL2 GPIO pad data out register n" bitfld.byte 0x164 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x165 "GPDO358,SIUL2 GPIO pad data out register n" bitfld.byte 0x165 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x166 "GPDO357,SIUL2 GPIO pad data out register n" bitfld.byte 0x166 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x167 "GPDO356,SIUL2 GPIO pad data out register n" bitfld.byte 0x167 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x168 "GPDO363,SIUL2 GPIO pad data out register n" bitfld.byte 0x168 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x169 "GPDO362,SIUL2 GPIO pad data out register n" bitfld.byte 0x169 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x16A "GPDO361,SIUL2 GPIO pad data out register n" bitfld.byte 0x16A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x16B "GPDO360,SIUL2 GPIO pad data out register n" bitfld.byte 0x16B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x16C "GPDO367,SIUL2 GPIO pad data out register n" bitfld.byte 0x16C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x16D "GPDO366,SIUL2 GPIO pad data out register n" bitfld.byte 0x16D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x16E "GPDO365,SIUL2 GPIO pad data out register n" bitfld.byte 0x16E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x16F "GPDO364,SIUL2 GPIO pad data out register n" bitfld.byte 0x16F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x170 "GPDO371,SIUL2 GPIO pad data out register n" bitfld.byte 0x170 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x171 "GPDO370,SIUL2 GPIO pad data out register n" bitfld.byte 0x171 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x172 "GPDO369,SIUL2 GPIO pad data out register n" bitfld.byte 0x172 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x173 "GPDO368,SIUL2 GPIO pad data out register n" bitfld.byte 0x173 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x174 "GPDO375,SIUL2 GPIO pad data out register n" bitfld.byte 0x174 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x175 "GPDO374,SIUL2 GPIO pad data out register n" bitfld.byte 0x175 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x176 "GPDO373,SIUL2 GPIO pad data out register n" bitfld.byte 0x176 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x177 "GPDO372,SIUL2 GPIO pad data out register n" bitfld.byte 0x177 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x178 "GPDO379,SIUL2 GPIO pad data out register n" bitfld.byte 0x178 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x179 "GPDO378,SIUL2 GPIO pad data out register n" bitfld.byte 0x179 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x17A "GPDO377,SIUL2 GPIO pad data out register n" bitfld.byte 0x17A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x17B "GPDO376,SIUL2 GPIO pad data out register n" bitfld.byte 0x17B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x17C "GPDO383,SIUL2 GPIO pad data out register n" bitfld.byte 0x17C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x17D "GPDO382,SIUL2 GPIO pad data out register n" bitfld.byte 0x17D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x17E "GPDO381,SIUL2 GPIO pad data out register n" bitfld.byte 0x17E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x17F "GPDO380,SIUL2 GPIO pad data out register n" bitfld.byte 0x17F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x180 "GPDO387,SIUL2 GPIO pad data out register n" bitfld.byte 0x180 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x181 "GPDO386,SIUL2 GPIO pad data out register n" bitfld.byte 0x181 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x182 "GPDO385,SIUL2 GPIO pad data out register n" bitfld.byte 0x182 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x183 "GPDO384,SIUL2 GPIO pad data out register n" bitfld.byte 0x183 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x184 "GPDO391,SIUL2 GPIO pad data out register n" bitfld.byte 0x184 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x185 "GPDO390,SIUL2 GPIO pad data out register n" bitfld.byte 0x185 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x186 "GPDO389,SIUL2 GPIO pad data out register n" bitfld.byte 0x186 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x187 "GPDO388,SIUL2 GPIO pad data out register n" bitfld.byte 0x187 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x188 "GPDO395,SIUL2 GPIO pad data out register n" bitfld.byte 0x188 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x189 "GPDO394,SIUL2 GPIO pad data out register n" bitfld.byte 0x189 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x18A "GPDO393,SIUL2 GPIO pad data out register n" bitfld.byte 0x18A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x18B "GPDO392,SIUL2 GPIO pad data out register n" bitfld.byte 0x18B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x18C "GPDO399,SIUL2 GPIO pad data out register n" bitfld.byte 0x18C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x18D "GPDO398,SIUL2 GPIO pad data out register n" bitfld.byte 0x18D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x18E "GPDO397,SIUL2 GPIO pad data out register n" bitfld.byte 0x18E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x18F "GPDO396,SIUL2 GPIO pad data out register n" bitfld.byte 0x18F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x190 "GPDO403,SIUL2 GPIO pad data out register n" bitfld.byte 0x190 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x191 "GPDO402,SIUL2 GPIO pad data out register n" bitfld.byte 0x191 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x192 "GPDO401,SIUL2 GPIO pad data out register n" bitfld.byte 0x192 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x193 "GPDO400,SIUL2 GPIO pad data out register n" bitfld.byte 0x193 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x194 "GPDO407,SIUL2 GPIO pad data out register n" bitfld.byte 0x194 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x195 "GPDO406,SIUL2 GPIO pad data out register n" bitfld.byte 0x195 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x196 "GPDO405,SIUL2 GPIO pad data out register n" bitfld.byte 0x196 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x197 "GPDO404,SIUL2 GPIO pad data out register n" bitfld.byte 0x197 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x198 "GPDO411,SIUL2 GPIO pad data out register n" bitfld.byte 0x198 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x199 "GPDO410,SIUL2 GPIO pad data out register n" bitfld.byte 0x199 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x19A "GPDO409,SIUL2 GPIO pad data out register n" bitfld.byte 0x19A 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x19B "GPDO408,SIUL2 GPIO pad data out register n" bitfld.byte 0x19B 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x19C "GPDO415,SIUL2 GPIO pad data out register n" bitfld.byte 0x19C 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x19D "GPDO414,SIUL2 GPIO pad data out register n" bitfld.byte 0x19D 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x19E "GPDO413,SIUL2 GPIO pad data out register n" bitfld.byte 0x19E 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x19F "GPDO412,SIUL2 GPIO pad data out register n" bitfld.byte 0x19F 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A0 "GPDO419,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A1 "GPDO418,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A2 "GPDO417,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A3 "GPDO416,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A4 "GPDO423,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A5 "GPDO422,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A6 "GPDO421,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A7 "GPDO420,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A8 "GPDO427,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1A9 "GPDO426,SIUL2 GPIO pad data out register n" bitfld.byte 0x1A9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1AA "GPDO425,SIUL2 GPIO pad data out register n" bitfld.byte 0x1AA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1AB "GPDO424,SIUL2 GPIO pad data out register n" bitfld.byte 0x1AB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1AC "GPDO431,SIUL2 GPIO pad data out register n" bitfld.byte 0x1AC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1AD "GPDO430,SIUL2 GPIO pad data out register n" bitfld.byte 0x1AD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1AE "GPDO429,SIUL2 GPIO pad data out register n" bitfld.byte 0x1AE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1AF "GPDO428,SIUL2 GPIO pad data out register n" bitfld.byte 0x1AF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B0 "GPDO435,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B1 "GPDO434,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B2 "GPDO433,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B3 "GPDO432,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B4 "GPDO439,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B5 "GPDO438,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B6 "GPDO437,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B7 "GPDO436,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B8 "GPDO443,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1B9 "GPDO442,SIUL2 GPIO pad data out register n" bitfld.byte 0x1B9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1BA "GPDO441,SIUL2 GPIO pad data out register n" bitfld.byte 0x1BA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1BB "GPDO440,SIUL2 GPIO pad data out register n" bitfld.byte 0x1BB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1BC "GPDO447,SIUL2 GPIO pad data out register n" bitfld.byte 0x1BC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1BD "GPDO446,SIUL2 GPIO pad data out register n" bitfld.byte 0x1BD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1BE "GPDO445,SIUL2 GPIO pad data out register n" bitfld.byte 0x1BE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1BF "GPDO444,SIUL2 GPIO pad data out register n" bitfld.byte 0x1BF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C0 "GPDO451,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C1 "GPDO450,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C2 "GPDO449,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C3 "GPDO448,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C4 "GPDO455,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C5 "GPDO454,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C6 "GPDO453,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C7 "GPDO452,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C8 "GPDO459,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1C9 "GPDO458,SIUL2 GPIO pad data out register n" bitfld.byte 0x1C9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1CA "GPDO457,SIUL2 GPIO pad data out register n" bitfld.byte 0x1CA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1CB "GPDO456,SIUL2 GPIO pad data out register n" bitfld.byte 0x1CB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1CC "GPDO463,SIUL2 GPIO pad data out register n" bitfld.byte 0x1CC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1CD "GPDO462,SIUL2 GPIO pad data out register n" bitfld.byte 0x1CD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1CE "GPDO461,SIUL2 GPIO pad data out register n" bitfld.byte 0x1CE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1CF "GPDO460,SIUL2 GPIO pad data out register n" bitfld.byte 0x1CF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D0 "GPDO467,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D1 "GPDO466,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D2 "GPDO465,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D3 "GPDO464,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D4 "GPDO471,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D5 "GPDO470,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D6 "GPDO469,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D7 "GPDO468,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D8 "GPDO475,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1D9 "GPDO474,SIUL2 GPIO pad data out register n" bitfld.byte 0x1D9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1DA "GPDO473,SIUL2 GPIO pad data out register n" bitfld.byte 0x1DA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1DB "GPDO472,SIUL2 GPIO pad data out register n" bitfld.byte 0x1DB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1DC "GPDO479,SIUL2 GPIO pad data out register n" bitfld.byte 0x1DC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1DD "GPDO478,SIUL2 GPIO pad data out register n" bitfld.byte 0x1DD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1DE "GPDO477,SIUL2 GPIO pad data out register n" bitfld.byte 0x1DE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1DF "GPDO476,SIUL2 GPIO pad data out register n" bitfld.byte 0x1DF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E0 "GPDO483,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E1 "GPDO482,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E2 "GPDO481,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E3 "GPDO480,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E4 "GPDO487,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E5 "GPDO486,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E6 "GPDO485,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E7 "GPDO484,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E8 "GPDO491,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1E9 "GPDO490,SIUL2 GPIO pad data out register n" bitfld.byte 0x1E9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1EA "GPDO489,SIUL2 GPIO pad data out register n" bitfld.byte 0x1EA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1EB "GPDO488,SIUL2 GPIO pad data out register n" bitfld.byte 0x1EB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1EC "GPDO495,SIUL2 GPIO pad data out register n" bitfld.byte 0x1EC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1ED "GPDO494,SIUL2 GPIO pad data out register n" bitfld.byte 0x1ED 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1EE "GPDO493,SIUL2 GPIO pad data out register n" bitfld.byte 0x1EE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1EF "GPDO492,SIUL2 GPIO pad data out register n" bitfld.byte 0x1EF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F0 "GPDO499,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F0 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F1 "GPDO498,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F1 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F2 "GPDO497,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F2 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F3 "GPDO496,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F3 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F4 "GPDO503,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F4 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F5 "GPDO502,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F5 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F6 "GPDO501,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F6 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F7 "GPDO500,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F7 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F8 "GPDO507,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F8 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1F9 "GPDO506,SIUL2 GPIO pad data out register n" bitfld.byte 0x1F9 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1FA "GPDO505,SIUL2 GPIO pad data out register n" bitfld.byte 0x1FA 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1FB "GPDO504,SIUL2 GPIO pad data out register n" bitfld.byte 0x1FB 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1FC "GPDO511,SIUL2 GPIO pad data out register n" bitfld.byte 0x1FC 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1FD "GPDO510,SIUL2 GPIO pad data out register n" bitfld.byte 0x1FD 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1FE "GPDO509,SIUL2 GPIO pad data out register n" bitfld.byte 0x1FE 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x1FF "GPDO508,SIUL2 GPIO pad data out register n" bitfld.byte 0x1FF 0. "PDO,Pad Data Out" "0: Logic low value is driven on the corresponding..,1: Logic high value is driven on the corresponding.." line.byte 0x200 "GPDI3,SIUL2 GPIO pad data in register n" bitfld.byte 0x200 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x201 "GPDI2,SIUL2 GPIO pad data in register n" bitfld.byte 0x201 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x202 "GPDI1,SIUL2 GPIO pad data in register n" bitfld.byte 0x202 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x203 "GPDI0,SIUL2 GPIO pad data in register n" bitfld.byte 0x203 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x204 "GPDI7,SIUL2 GPIO pad data in register n" bitfld.byte 0x204 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x205 "GPDI6,SIUL2 GPIO pad data in register n" bitfld.byte 0x205 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x206 "GPDI5,SIUL2 GPIO pad data in register n" bitfld.byte 0x206 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x207 "GPDI4,SIUL2 GPIO pad data in register n" bitfld.byte 0x207 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x208 "GPDI11,SIUL2 GPIO pad data in register n" bitfld.byte 0x208 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x209 "GPDI10,SIUL2 GPIO pad data in register n" bitfld.byte 0x209 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x20A "GPDI9,SIUL2 GPIO pad data in register n" bitfld.byte 0x20A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x20B "GPDI8,SIUL2 GPIO pad data in register n" bitfld.byte 0x20B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x20C "GPDI15,SIUL2 GPIO pad data in register n" bitfld.byte 0x20C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x20D "GPDI14,SIUL2 GPIO pad data in register n" bitfld.byte 0x20D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x20E "GPDI13,SIUL2 GPIO pad data in register n" bitfld.byte 0x20E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x20F "GPDI12,SIUL2 GPIO pad data in register n" bitfld.byte 0x20F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x210 "GPDI19,SIUL2 GPIO pad data in register n" bitfld.byte 0x210 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x211 "GPDI18,SIUL2 GPIO pad data in register n" bitfld.byte 0x211 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x212 "GPDI17,SIUL2 GPIO pad data in register n" bitfld.byte 0x212 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x213 "GPDI16,SIUL2 GPIO pad data in register n" bitfld.byte 0x213 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x214 "GPDI23,SIUL2 GPIO pad data in register n" bitfld.byte 0x214 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x215 "GPDI22,SIUL2 GPIO pad data in register n" bitfld.byte 0x215 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x216 "GPDI21,SIUL2 GPIO pad data in register n" bitfld.byte 0x216 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x217 "GPDI20,SIUL2 GPIO pad data in register n" bitfld.byte 0x217 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x218 "GPDI27,SIUL2 GPIO pad data in register n" bitfld.byte 0x218 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x219 "GPDI26,SIUL2 GPIO pad data in register n" bitfld.byte 0x219 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x21A "GPDI25,SIUL2 GPIO pad data in register n" bitfld.byte 0x21A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x21B "GPDI24,SIUL2 GPIO pad data in register n" bitfld.byte 0x21B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x21C "GPDI31,SIUL2 GPIO pad data in register n" bitfld.byte 0x21C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x21D "GPDI30,SIUL2 GPIO pad data in register n" bitfld.byte 0x21D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x21E "GPDI29,SIUL2 GPIO pad data in register n" bitfld.byte 0x21E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x21F "GPDI28,SIUL2 GPIO pad data in register n" bitfld.byte 0x21F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x220 "GPDI35,SIUL2 GPIO pad data in register n" bitfld.byte 0x220 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x221 "GPDI34,SIUL2 GPIO pad data in register n" bitfld.byte 0x221 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x222 "GPDI33,SIUL2 GPIO pad data in register n" bitfld.byte 0x222 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x223 "GPDI32,SIUL2 GPIO pad data in register n" bitfld.byte 0x223 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x224 "GPDI39,SIUL2 GPIO pad data in register n" bitfld.byte 0x224 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x225 "GPDI38,SIUL2 GPIO pad data in register n" bitfld.byte 0x225 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x226 "GPDI37,SIUL2 GPIO pad data in register n" bitfld.byte 0x226 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x227 "GPDI36,SIUL2 GPIO pad data in register n" bitfld.byte 0x227 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x228 "GPDI43,SIUL2 GPIO pad data in register n" bitfld.byte 0x228 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x229 "GPDI42,SIUL2 GPIO pad data in register n" bitfld.byte 0x229 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x22A "GPDI41,SIUL2 GPIO pad data in register n" bitfld.byte 0x22A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x22B "GPDI40,SIUL2 GPIO pad data in register n" bitfld.byte 0x22B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x22C "GPDI47,SIUL2 GPIO pad data in register n" bitfld.byte 0x22C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x22D "GPDI46,SIUL2 GPIO pad data in register n" bitfld.byte 0x22D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x22E "GPDI45,SIUL2 GPIO pad data in register n" bitfld.byte 0x22E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x22F "GPDI44,SIUL2 GPIO pad data in register n" bitfld.byte 0x22F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x230 "GPDI51,SIUL2 GPIO pad data in register n" bitfld.byte 0x230 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x231 "GPDI50,SIUL2 GPIO pad data in register n" bitfld.byte 0x231 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x232 "GPDI49,SIUL2 GPIO pad data in register n" bitfld.byte 0x232 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x233 "GPDI48,SIUL2 GPIO pad data in register n" bitfld.byte 0x233 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x234 "GPDI55,SIUL2 GPIO pad data in register n" bitfld.byte 0x234 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x235 "GPDI54,SIUL2 GPIO pad data in register n" bitfld.byte 0x235 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x236 "GPDI53,SIUL2 GPIO pad data in register n" bitfld.byte 0x236 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x237 "GPDI52,SIUL2 GPIO pad data in register n" bitfld.byte 0x237 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x238 "GPDI59,SIUL2 GPIO pad data in register n" bitfld.byte 0x238 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x239 "GPDI58,SIUL2 GPIO pad data in register n" bitfld.byte 0x239 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x23A "GPDI57,SIUL2 GPIO pad data in register n" bitfld.byte 0x23A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x23B "GPDI56,SIUL2 GPIO pad data in register n" bitfld.byte 0x23B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x23C "GPDI63,SIUL2 GPIO pad data in register n" bitfld.byte 0x23C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x23D "GPDI62,SIUL2 GPIO pad data in register n" bitfld.byte 0x23D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x23E "GPDI61,SIUL2 GPIO pad data in register n" bitfld.byte 0x23E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x23F "GPDI60,SIUL2 GPIO pad data in register n" bitfld.byte 0x23F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x240 "GPDI67,SIUL2 GPIO pad data in register n" bitfld.byte 0x240 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x241 "GPDI66,SIUL2 GPIO pad data in register n" bitfld.byte 0x241 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x242 "GPDI65,SIUL2 GPIO pad data in register n" bitfld.byte 0x242 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x243 "GPDI64,SIUL2 GPIO pad data in register n" bitfld.byte 0x243 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x244 "GPDI71,SIUL2 GPIO pad data in register n" bitfld.byte 0x244 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x245 "GPDI70,SIUL2 GPIO pad data in register n" bitfld.byte 0x245 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x246 "GPDI69,SIUL2 GPIO pad data in register n" bitfld.byte 0x246 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x247 "GPDI68,SIUL2 GPIO pad data in register n" bitfld.byte 0x247 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x248 "GPDI75,SIUL2 GPIO pad data in register n" bitfld.byte 0x248 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x249 "GPDI74,SIUL2 GPIO pad data in register n" bitfld.byte 0x249 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x24A "GPDI73,SIUL2 GPIO pad data in register n" bitfld.byte 0x24A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x24B "GPDI72,SIUL2 GPIO pad data in register n" bitfld.byte 0x24B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x24C "GPDI79,SIUL2 GPIO pad data in register n" bitfld.byte 0x24C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x24D "GPDI78,SIUL2 GPIO pad data in register n" bitfld.byte 0x24D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x24E "GPDI77,SIUL2 GPIO pad data in register n" bitfld.byte 0x24E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x24F "GPDI76,SIUL2 GPIO pad data in register n" bitfld.byte 0x24F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x250 "GPDI83,SIUL2 GPIO pad data in register n" bitfld.byte 0x250 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x251 "GPDI82,SIUL2 GPIO pad data in register n" bitfld.byte 0x251 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x252 "GPDI81,SIUL2 GPIO pad data in register n" bitfld.byte 0x252 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x253 "GPDI80,SIUL2 GPIO pad data in register n" bitfld.byte 0x253 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x254 "GPDI87,SIUL2 GPIO pad data in register n" bitfld.byte 0x254 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x255 "GPDI86,SIUL2 GPIO pad data in register n" bitfld.byte 0x255 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x256 "GPDI85,SIUL2 GPIO pad data in register n" bitfld.byte 0x256 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x257 "GPDI84,SIUL2 GPIO pad data in register n" bitfld.byte 0x257 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x258 "GPDI91,SIUL2 GPIO pad data in register n" bitfld.byte 0x258 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x259 "GPDI90,SIUL2 GPIO pad data in register n" bitfld.byte 0x259 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x25A "GPDI89,SIUL2 GPIO pad data in register n" bitfld.byte 0x25A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x25B "GPDI88,SIUL2 GPIO pad data in register n" bitfld.byte 0x25B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x25C "GPDI95,SIUL2 GPIO pad data in register n" bitfld.byte 0x25C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x25D "GPDI94,SIUL2 GPIO pad data in register n" bitfld.byte 0x25D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x25E "GPDI93,SIUL2 GPIO pad data in register n" bitfld.byte 0x25E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x25F "GPDI92,SIUL2 GPIO pad data in register n" bitfld.byte 0x25F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x260 "GPDI99,SIUL2 GPIO pad data in register n" bitfld.byte 0x260 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x261 "GPDI98,SIUL2 GPIO pad data in register n" bitfld.byte 0x261 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x262 "GPDI97,SIUL2 GPIO pad data in register n" bitfld.byte 0x262 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x263 "GPDI96,SIUL2 GPIO pad data in register n" bitfld.byte 0x263 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x264 "GPDI103,SIUL2 GPIO pad data in register n" bitfld.byte 0x264 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x265 "GPDI102,SIUL2 GPIO pad data in register n" bitfld.byte 0x265 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x266 "GPDI101,SIUL2 GPIO pad data in register n" bitfld.byte 0x266 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x267 "GPDI100,SIUL2 GPIO pad data in register n" bitfld.byte 0x267 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x268 "GPDI107,SIUL2 GPIO pad data in register n" bitfld.byte 0x268 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x269 "GPDI106,SIUL2 GPIO pad data in register n" bitfld.byte 0x269 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x26A "GPDI105,SIUL2 GPIO pad data in register n" bitfld.byte 0x26A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x26B "GPDI104,SIUL2 GPIO pad data in register n" bitfld.byte 0x26B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x26C "GPDI111,SIUL2 GPIO pad data in register n" bitfld.byte 0x26C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x26D "GPDI110,SIUL2 GPIO pad data in register n" bitfld.byte 0x26D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x26E "GPDI109,SIUL2 GPIO pad data in register n" bitfld.byte 0x26E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x26F "GPDI108,SIUL2 GPIO pad data in register n" bitfld.byte 0x26F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x270 "GPDI115,SIUL2 GPIO pad data in register n" bitfld.byte 0x270 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x271 "GPDI114,SIUL2 GPIO pad data in register n" bitfld.byte 0x271 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x272 "GPDI113,SIUL2 GPIO pad data in register n" bitfld.byte 0x272 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x273 "GPDI112,SIUL2 GPIO pad data in register n" bitfld.byte 0x273 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x274 "GPDI119,SIUL2 GPIO pad data in register n" bitfld.byte 0x274 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x275 "GPDI118,SIUL2 GPIO pad data in register n" bitfld.byte 0x275 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x276 "GPDI117,SIUL2 GPIO pad data in register n" bitfld.byte 0x276 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x277 "GPDI116,SIUL2 GPIO pad data in register n" bitfld.byte 0x277 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x278 "GPDI123,SIUL2 GPIO pad data in register n" bitfld.byte 0x278 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x279 "GPDI122,SIUL2 GPIO pad data in register n" bitfld.byte 0x279 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x27A "GPDI121,SIUL2 GPIO pad data in register n" bitfld.byte 0x27A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x27B "GPDI120,SIUL2 GPIO pad data in register n" bitfld.byte 0x27B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x27C "GPDI127,SIUL2 GPIO pad data in register n" bitfld.byte 0x27C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x27D "GPDI126,SIUL2 GPIO pad data in register n" bitfld.byte 0x27D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x27E "GPDI125,SIUL2 GPIO pad data in register n" bitfld.byte 0x27E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x27F "GPDI124,SIUL2 GPIO pad data in register n" bitfld.byte 0x27F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x280 "GPDI131,SIUL2 GPIO pad data in register n" bitfld.byte 0x280 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x281 "GPDI130,SIUL2 GPIO pad data in register n" bitfld.byte 0x281 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x282 "GPDI129,SIUL2 GPIO pad data in register n" bitfld.byte 0x282 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x283 "GPDI128,SIUL2 GPIO pad data in register n" bitfld.byte 0x283 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x284 "GPDI135,SIUL2 GPIO pad data in register n" bitfld.byte 0x284 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x285 "GPDI134,SIUL2 GPIO pad data in register n" bitfld.byte 0x285 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x286 "GPDI133,SIUL2 GPIO pad data in register n" bitfld.byte 0x286 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x287 "GPDI132,SIUL2 GPIO pad data in register n" bitfld.byte 0x287 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x288 "GPDI139,SIUL2 GPIO pad data in register n" bitfld.byte 0x288 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x289 "GPDI138,SIUL2 GPIO pad data in register n" bitfld.byte 0x289 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x28A "GPDI137,SIUL2 GPIO pad data in register n" bitfld.byte 0x28A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x28B "GPDI136,SIUL2 GPIO pad data in register n" bitfld.byte 0x28B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x28C "GPDI143,SIUL2 GPIO pad data in register n" bitfld.byte 0x28C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x28D "GPDI142,SIUL2 GPIO pad data in register n" bitfld.byte 0x28D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x28E "GPDI141,SIUL2 GPIO pad data in register n" bitfld.byte 0x28E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x28F "GPDI140,SIUL2 GPIO pad data in register n" bitfld.byte 0x28F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x290 "GPDI147,SIUL2 GPIO pad data in register n" bitfld.byte 0x290 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x291 "GPDI146,SIUL2 GPIO pad data in register n" bitfld.byte 0x291 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x292 "GPDI145,SIUL2 GPIO pad data in register n" bitfld.byte 0x292 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x293 "GPDI144,SIUL2 GPIO pad data in register n" bitfld.byte 0x293 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x294 "GPDI151,SIUL2 GPIO pad data in register n" bitfld.byte 0x294 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x295 "GPDI150,SIUL2 GPIO pad data in register n" bitfld.byte 0x295 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x296 "GPDI149,SIUL2 GPIO pad data in register n" bitfld.byte 0x296 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x297 "GPDI148,SIUL2 GPIO pad data in register n" bitfld.byte 0x297 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x298 "GPDI155,SIUL2 GPIO pad data in register n" bitfld.byte 0x298 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x299 "GPDI154,SIUL2 GPIO pad data in register n" bitfld.byte 0x299 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x29A "GPDI153,SIUL2 GPIO pad data in register n" bitfld.byte 0x29A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x29B "GPDI152,SIUL2 GPIO pad data in register n" bitfld.byte 0x29B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x29C "GPDI159,SIUL2 GPIO pad data in register n" bitfld.byte 0x29C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x29D "GPDI158,SIUL2 GPIO pad data in register n" bitfld.byte 0x29D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x29E "GPDI157,SIUL2 GPIO pad data in register n" bitfld.byte 0x29E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x29F "GPDI156,SIUL2 GPIO pad data in register n" bitfld.byte 0x29F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2A0 "GPDI163,SIUL2 GPIO pad data in register n" bitfld.byte 0x2A0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2A1 "GPDI162,SIUL2 GPIO pad data in register n" bitfld.byte 0x2A1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2A2 "GPDI161,SIUL2 GPIO pad data in register n" bitfld.byte 0x2A2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2A3 "GPDI160,SIUL2 GPIO pad data in register n" bitfld.byte 0x2A3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2A4 "GPDI167,SIUL2 GPIO pad data in register n" bitfld.byte 0x2A4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2A5 "GPDI166,SIUL2 GPIO pad data in register n" bitfld.byte 0x2A5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2A6 "GPDI165,SIUL2 GPIO pad data in register n" bitfld.byte 0x2A6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2A7 "GPDI164,SIUL2 GPIO pad data in register n" bitfld.byte 0x2A7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2A8 "GPDI171,SIUL2 GPIO pad data in register n" bitfld.byte 0x2A8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2A9 "GPDI170,SIUL2 GPIO pad data in register n" bitfld.byte 0x2A9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2AA "GPDI169,SIUL2 GPIO pad data in register n" bitfld.byte 0x2AA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2AB "GPDI168,SIUL2 GPIO pad data in register n" bitfld.byte 0x2AB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2AC "GPDI175,SIUL2 GPIO pad data in register n" bitfld.byte 0x2AC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2AD "GPDI174,SIUL2 GPIO pad data in register n" bitfld.byte 0x2AD 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2AE "GPDI173,SIUL2 GPIO pad data in register n" bitfld.byte 0x2AE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2AF "GPDI172,SIUL2 GPIO pad data in register n" bitfld.byte 0x2AF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2B0 "GPDI179,SIUL2 GPIO pad data in register n" bitfld.byte 0x2B0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2B1 "GPDI178,SIUL2 GPIO pad data in register n" bitfld.byte 0x2B1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2B2 "GPDI177,SIUL2 GPIO pad data in register n" bitfld.byte 0x2B2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2B3 "GPDI176,SIUL2 GPIO pad data in register n" bitfld.byte 0x2B3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2B4 "GPDI183,SIUL2 GPIO pad data in register n" bitfld.byte 0x2B4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2B5 "GPDI182,SIUL2 GPIO pad data in register n" bitfld.byte 0x2B5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2B6 "GPDI181,SIUL2 GPIO pad data in register n" bitfld.byte 0x2B6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2B7 "GPDI180,SIUL2 GPIO pad data in register n" bitfld.byte 0x2B7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2B8 "GPDI187,SIUL2 GPIO pad data in register n" bitfld.byte 0x2B8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2B9 "GPDI186,SIUL2 GPIO pad data in register n" bitfld.byte 0x2B9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2BA "GPDI185,SIUL2 GPIO pad data in register n" bitfld.byte 0x2BA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2BB "GPDI184,SIUL2 GPIO pad data in register n" bitfld.byte 0x2BB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2BC "GPDI191,SIUL2 GPIO pad data in register n" bitfld.byte 0x2BC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2BD "GPDI190,SIUL2 GPIO pad data in register n" bitfld.byte 0x2BD 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2BE "GPDI189,SIUL2 GPIO pad data in register n" bitfld.byte 0x2BE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2BF "GPDI188,SIUL2 GPIO pad data in register n" bitfld.byte 0x2BF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2C0 "GPDI195,SIUL2 GPIO pad data in register n" bitfld.byte 0x2C0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2C1 "GPDI194,SIUL2 GPIO pad data in register n" bitfld.byte 0x2C1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2C2 "GPDI193,SIUL2 GPIO pad data in register n" bitfld.byte 0x2C2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2C3 "GPDI192,SIUL2 GPIO pad data in register n" bitfld.byte 0x2C3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2C4 "GPDI199,SIUL2 GPIO pad data in register n" bitfld.byte 0x2C4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2C5 "GPDI198,SIUL2 GPIO pad data in register n" bitfld.byte 0x2C5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2C6 "GPDI197,SIUL2 GPIO pad data in register n" bitfld.byte 0x2C6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2C7 "GPDI196,SIUL2 GPIO pad data in register n" bitfld.byte 0x2C7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2C8 "GPDI203,SIUL2 GPIO pad data in register n" bitfld.byte 0x2C8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2C9 "GPDI202,SIUL2 GPIO pad data in register n" bitfld.byte 0x2C9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2CA "GPDI201,SIUL2 GPIO pad data in register n" bitfld.byte 0x2CA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2CB "GPDI200,SIUL2 GPIO pad data in register n" bitfld.byte 0x2CB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2CC "GPDI207,SIUL2 GPIO pad data in register n" bitfld.byte 0x2CC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2CD "GPDI206,SIUL2 GPIO pad data in register n" bitfld.byte 0x2CD 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2CE "GPDI205,SIUL2 GPIO pad data in register n" bitfld.byte 0x2CE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2CF "GPDI204,SIUL2 GPIO pad data in register n" bitfld.byte 0x2CF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2D0 "GPDI211,SIUL2 GPIO pad data in register n" bitfld.byte 0x2D0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2D1 "GPDI210,SIUL2 GPIO pad data in register n" bitfld.byte 0x2D1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2D2 "GPDI209,SIUL2 GPIO pad data in register n" bitfld.byte 0x2D2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2D3 "GPDI208,SIUL2 GPIO pad data in register n" bitfld.byte 0x2D3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2D4 "GPDI215,SIUL2 GPIO pad data in register n" bitfld.byte 0x2D4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2D5 "GPDI214,SIUL2 GPIO pad data in register n" bitfld.byte 0x2D5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2D6 "GPDI213,SIUL2 GPIO pad data in register n" bitfld.byte 0x2D6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2D7 "GPDI212,SIUL2 GPIO pad data in register n" bitfld.byte 0x2D7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2D8 "GPDI219,SIUL2 GPIO pad data in register n" bitfld.byte 0x2D8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2D9 "GPDI218,SIUL2 GPIO pad data in register n" bitfld.byte 0x2D9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2DA "GPDI217,SIUL2 GPIO pad data in register n" bitfld.byte 0x2DA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2DB "GPDI216,SIUL2 GPIO pad data in register n" bitfld.byte 0x2DB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2DC "GPDI223,SIUL2 GPIO pad data in register n" bitfld.byte 0x2DC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2DD "GPDI222,SIUL2 GPIO pad data in register n" bitfld.byte 0x2DD 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2DE "GPDI221,SIUL2 GPIO pad data in register n" bitfld.byte 0x2DE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2DF "GPDI220,SIUL2 GPIO pad data in register n" bitfld.byte 0x2DF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2E0 "GPDI227,SIUL2 GPIO pad data in register n" bitfld.byte 0x2E0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2E1 "GPDI226,SIUL2 GPIO pad data in register n" bitfld.byte 0x2E1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2E2 "GPDI225,SIUL2 GPIO pad data in register n" bitfld.byte 0x2E2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2E3 "GPDI224,SIUL2 GPIO pad data in register n" bitfld.byte 0x2E3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2E4 "GPDI231,SIUL2 GPIO pad data in register n" bitfld.byte 0x2E4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2E5 "GPDI230,SIUL2 GPIO pad data in register n" bitfld.byte 0x2E5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2E6 "GPDI229,SIUL2 GPIO pad data in register n" bitfld.byte 0x2E6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2E7 "GPDI228,SIUL2 GPIO pad data in register n" bitfld.byte 0x2E7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2E8 "GPDI235,SIUL2 GPIO pad data in register n" bitfld.byte 0x2E8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2E9 "GPDI234,SIUL2 GPIO pad data in register n" bitfld.byte 0x2E9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2EA "GPDI233,SIUL2 GPIO pad data in register n" bitfld.byte 0x2EA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2EB "GPDI232,SIUL2 GPIO pad data in register n" bitfld.byte 0x2EB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2EC "GPDI239,SIUL2 GPIO pad data in register n" bitfld.byte 0x2EC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2ED "GPDI238,SIUL2 GPIO pad data in register n" bitfld.byte 0x2ED 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2EE "GPDI237,SIUL2 GPIO pad data in register n" bitfld.byte 0x2EE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2EF "GPDI236,SIUL2 GPIO pad data in register n" bitfld.byte 0x2EF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2F0 "GPDI243,SIUL2 GPIO pad data in register n" bitfld.byte 0x2F0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2F1 "GPDI242,SIUL2 GPIO pad data in register n" bitfld.byte 0x2F1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2F2 "GPDI241,SIUL2 GPIO pad data in register n" bitfld.byte 0x2F2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2F3 "GPDI240,SIUL2 GPIO pad data in register n" bitfld.byte 0x2F3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2F4 "GPDI247,SIUL2 GPIO pad data in register n" bitfld.byte 0x2F4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2F5 "GPDI246,SIUL2 GPIO pad data in register n" bitfld.byte 0x2F5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2F6 "GPDI245,SIUL2 GPIO pad data in register n" bitfld.byte 0x2F6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2F7 "GPDI244,SIUL2 GPIO pad data in register n" bitfld.byte 0x2F7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2F8 "GPDI251,SIUL2 GPIO pad data in register n" bitfld.byte 0x2F8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2F9 "GPDI250,SIUL2 GPIO pad data in register n" bitfld.byte 0x2F9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2FA "GPDI249,SIUL2 GPIO pad data in register n" bitfld.byte 0x2FA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2FB "GPDI248,SIUL2 GPIO pad data in register n" bitfld.byte 0x2FB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2FC "GPDI255,SIUL2 GPIO pad data in register n" bitfld.byte 0x2FC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2FD "GPDI254,SIUL2 GPIO pad data in register n" bitfld.byte 0x2FD 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2FE "GPDI253,SIUL2 GPIO pad data in register n" bitfld.byte 0x2FE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x2FF "GPDI252,SIUL2 GPIO pad data in register n" bitfld.byte 0x2FF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x300 "GPDI259,SIUL2 GPIO pad data in register n" bitfld.byte 0x300 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x301 "GPDI258,SIUL2 GPIO pad data in register n" bitfld.byte 0x301 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x302 "GPDI257,SIUL2 GPIO pad data in register n" bitfld.byte 0x302 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x303 "GPDI256,SIUL2 GPIO pad data in register n" bitfld.byte 0x303 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x304 "GPDI263,SIUL2 GPIO pad data in register n" bitfld.byte 0x304 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x305 "GPDI262,SIUL2 GPIO pad data in register n" bitfld.byte 0x305 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x306 "GPDI261,SIUL2 GPIO pad data in register n" bitfld.byte 0x306 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x307 "GPDI260,SIUL2 GPIO pad data in register n" bitfld.byte 0x307 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x308 "GPDI267,SIUL2 GPIO pad data in register n" bitfld.byte 0x308 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x309 "GPDI266,SIUL2 GPIO pad data in register n" bitfld.byte 0x309 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x30A "GPDI265,SIUL2 GPIO pad data in register n" bitfld.byte 0x30A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x30B "GPDI264,SIUL2 GPIO pad data in register n" bitfld.byte 0x30B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x30C "GPDI271,SIUL2 GPIO pad data in register n" bitfld.byte 0x30C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x30D "GPDI270,SIUL2 GPIO pad data in register n" bitfld.byte 0x30D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x30E "GPDI269,SIUL2 GPIO pad data in register n" bitfld.byte 0x30E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x30F "GPDI268,SIUL2 GPIO pad data in register n" bitfld.byte 0x30F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x310 "GPDI275,SIUL2 GPIO pad data in register n" bitfld.byte 0x310 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x311 "GPDI274,SIUL2 GPIO pad data in register n" bitfld.byte 0x311 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x312 "GPDI273,SIUL2 GPIO pad data in register n" bitfld.byte 0x312 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x313 "GPDI272,SIUL2 GPIO pad data in register n" bitfld.byte 0x313 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x314 "GPDI279,SIUL2 GPIO pad data in register n" bitfld.byte 0x314 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x315 "GPDI278,SIUL2 GPIO pad data in register n" bitfld.byte 0x315 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x316 "GPDI277,SIUL2 GPIO pad data in register n" bitfld.byte 0x316 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x317 "GPDI276,SIUL2 GPIO pad data in register n" bitfld.byte 0x317 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x318 "GPDI283,SIUL2 GPIO pad data in register n" bitfld.byte 0x318 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x319 "GPDI282,SIUL2 GPIO pad data in register n" bitfld.byte 0x319 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x31A "GPDI281,SIUL2 GPIO pad data in register n" bitfld.byte 0x31A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x31B "GPDI280,SIUL2 GPIO pad data in register n" bitfld.byte 0x31B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x31C "GPDI287,SIUL2 GPIO pad data in register n" bitfld.byte 0x31C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x31D "GPDI286,SIUL2 GPIO pad data in register n" bitfld.byte 0x31D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x31E "GPDI285,SIUL2 GPIO pad data in register n" bitfld.byte 0x31E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x31F "GPDI284,SIUL2 GPIO pad data in register n" bitfld.byte 0x31F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x320 "GPDI291,SIUL2 GPIO pad data in register n" bitfld.byte 0x320 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x321 "GPDI290,SIUL2 GPIO pad data in register n" bitfld.byte 0x321 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x322 "GPDI289,SIUL2 GPIO pad data in register n" bitfld.byte 0x322 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x323 "GPDI288,SIUL2 GPIO pad data in register n" bitfld.byte 0x323 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x324 "GPDI295,SIUL2 GPIO pad data in register n" bitfld.byte 0x324 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x325 "GPDI294,SIUL2 GPIO pad data in register n" bitfld.byte 0x325 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x326 "GPDI293,SIUL2 GPIO pad data in register n" bitfld.byte 0x326 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x327 "GPDI292,SIUL2 GPIO pad data in register n" bitfld.byte 0x327 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x328 "GPDI299,SIUL2 GPIO pad data in register n" bitfld.byte 0x328 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x329 "GPDI298,SIUL2 GPIO pad data in register n" bitfld.byte 0x329 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x32A "GPDI297,SIUL2 GPIO pad data in register n" bitfld.byte 0x32A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x32B "GPDI296,SIUL2 GPIO pad data in register n" bitfld.byte 0x32B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x32C "GPDI303,SIUL2 GPIO pad data in register n" bitfld.byte 0x32C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x32D "GPDI302,SIUL2 GPIO pad data in register n" bitfld.byte 0x32D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x32E "GPDI301,SIUL2 GPIO pad data in register n" bitfld.byte 0x32E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x32F "GPDI300,SIUL2 GPIO pad data in register n" bitfld.byte 0x32F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x330 "GPDI307,SIUL2 GPIO pad data in register n" bitfld.byte 0x330 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x331 "GPDI306,SIUL2 GPIO pad data in register n" bitfld.byte 0x331 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x332 "GPDI305,SIUL2 GPIO pad data in register n" bitfld.byte 0x332 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x333 "GPDI304,SIUL2 GPIO pad data in register n" bitfld.byte 0x333 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x334 "GPDI311,SIUL2 GPIO pad data in register n" bitfld.byte 0x334 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x335 "GPDI310,SIUL2 GPIO pad data in register n" bitfld.byte 0x335 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x336 "GPDI309,SIUL2 GPIO pad data in register n" bitfld.byte 0x336 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x337 "GPDI308,SIUL2 GPIO pad data in register n" bitfld.byte 0x337 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x338 "GPDI315,SIUL2 GPIO pad data in register n" bitfld.byte 0x338 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x339 "GPDI314,SIUL2 GPIO pad data in register n" bitfld.byte 0x339 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x33A "GPDI313,SIUL2 GPIO pad data in register n" bitfld.byte 0x33A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x33B "GPDI312,SIUL2 GPIO pad data in register n" bitfld.byte 0x33B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x33C "GPDI319,SIUL2 GPIO pad data in register n" bitfld.byte 0x33C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x33D "GPDI318,SIUL2 GPIO pad data in register n" bitfld.byte 0x33D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x33E "GPDI317,SIUL2 GPIO pad data in register n" bitfld.byte 0x33E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x33F "GPDI316,SIUL2 GPIO pad data in register n" bitfld.byte 0x33F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x340 "GPDI323,SIUL2 GPIO pad data in register n" bitfld.byte 0x340 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x341 "GPDI322,SIUL2 GPIO pad data in register n" bitfld.byte 0x341 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x342 "GPDI321,SIUL2 GPIO pad data in register n" bitfld.byte 0x342 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x343 "GPDI320,SIUL2 GPIO pad data in register n" bitfld.byte 0x343 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x344 "GPDI327,SIUL2 GPIO pad data in register n" bitfld.byte 0x344 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x345 "GPDI326,SIUL2 GPIO pad data in register n" bitfld.byte 0x345 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x346 "GPDI325,SIUL2 GPIO pad data in register n" bitfld.byte 0x346 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x347 "GPDI324,SIUL2 GPIO pad data in register n" bitfld.byte 0x347 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x348 "GPDI331,SIUL2 GPIO pad data in register n" bitfld.byte 0x348 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x349 "GPDI330,SIUL2 GPIO pad data in register n" bitfld.byte 0x349 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x34A "GPDI329,SIUL2 GPIO pad data in register n" bitfld.byte 0x34A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x34B "GPDI328,SIUL2 GPIO pad data in register n" bitfld.byte 0x34B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x34C "GPDI335,SIUL2 GPIO pad data in register n" bitfld.byte 0x34C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x34D "GPDI334,SIUL2 GPIO pad data in register n" bitfld.byte 0x34D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x34E "GPDI333,SIUL2 GPIO pad data in register n" bitfld.byte 0x34E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x34F "GPDI332,SIUL2 GPIO pad data in register n" bitfld.byte 0x34F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x350 "GPDI339,SIUL2 GPIO pad data in register n" bitfld.byte 0x350 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x351 "GPDI338,SIUL2 GPIO pad data in register n" bitfld.byte 0x351 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x352 "GPDI337,SIUL2 GPIO pad data in register n" bitfld.byte 0x352 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x353 "GPDI336,SIUL2 GPIO pad data in register n" bitfld.byte 0x353 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x354 "GPDI343,SIUL2 GPIO pad data in register n" bitfld.byte 0x354 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x355 "GPDI342,SIUL2 GPIO pad data in register n" bitfld.byte 0x355 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x356 "GPDI341,SIUL2 GPIO pad data in register n" bitfld.byte 0x356 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x357 "GPDI340,SIUL2 GPIO pad data in register n" bitfld.byte 0x357 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x358 "GPDI347,SIUL2 GPIO pad data in register n" bitfld.byte 0x358 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x359 "GPDI346,SIUL2 GPIO pad data in register n" bitfld.byte 0x359 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x35A "GPDI345,SIUL2 GPIO pad data in register n" bitfld.byte 0x35A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x35B "GPDI344,SIUL2 GPIO pad data in register n" bitfld.byte 0x35B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x35C "GPDI351,SIUL2 GPIO pad data in register n" bitfld.byte 0x35C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x35D "GPDI350,SIUL2 GPIO pad data in register n" bitfld.byte 0x35D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x35E "GPDI349,SIUL2 GPIO pad data in register n" bitfld.byte 0x35E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x35F "GPDI348,SIUL2 GPIO pad data in register n" bitfld.byte 0x35F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x360 "GPDI355,SIUL2 GPIO pad data in register n" bitfld.byte 0x360 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x361 "GPDI354,SIUL2 GPIO pad data in register n" bitfld.byte 0x361 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x362 "GPDI353,SIUL2 GPIO pad data in register n" bitfld.byte 0x362 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x363 "GPDI352,SIUL2 GPIO pad data in register n" bitfld.byte 0x363 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x364 "GPDI359,SIUL2 GPIO pad data in register n" bitfld.byte 0x364 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x365 "GPDI358,SIUL2 GPIO pad data in register n" bitfld.byte 0x365 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x366 "GPDI357,SIUL2 GPIO pad data in register n" bitfld.byte 0x366 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x367 "GPDI356,SIUL2 GPIO pad data in register n" bitfld.byte 0x367 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x368 "GPDI363,SIUL2 GPIO pad data in register n" bitfld.byte 0x368 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x369 "GPDI362,SIUL2 GPIO pad data in register n" bitfld.byte 0x369 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x36A "GPDI361,SIUL2 GPIO pad data in register n" bitfld.byte 0x36A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x36B "GPDI360,SIUL2 GPIO pad data in register n" bitfld.byte 0x36B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x36C "GPDI367,SIUL2 GPIO pad data in register n" bitfld.byte 0x36C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x36D "GPDI366,SIUL2 GPIO pad data in register n" bitfld.byte 0x36D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x36E "GPDI365,SIUL2 GPIO pad data in register n" bitfld.byte 0x36E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x36F "GPDI364,SIUL2 GPIO pad data in register n" bitfld.byte 0x36F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x370 "GPDI371,SIUL2 GPIO pad data in register n" bitfld.byte 0x370 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x371 "GPDI370,SIUL2 GPIO pad data in register n" bitfld.byte 0x371 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x372 "GPDI369,SIUL2 GPIO pad data in register n" bitfld.byte 0x372 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x373 "GPDI368,SIUL2 GPIO pad data in register n" bitfld.byte 0x373 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x374 "GPDI375,SIUL2 GPIO pad data in register n" bitfld.byte 0x374 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x375 "GPDI374,SIUL2 GPIO pad data in register n" bitfld.byte 0x375 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x376 "GPDI373,SIUL2 GPIO pad data in register n" bitfld.byte 0x376 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x377 "GPDI372,SIUL2 GPIO pad data in register n" bitfld.byte 0x377 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x378 "GPDI379,SIUL2 GPIO pad data in register n" bitfld.byte 0x378 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x379 "GPDI378,SIUL2 GPIO pad data in register n" bitfld.byte 0x379 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x37A "GPDI377,SIUL2 GPIO pad data in register n" bitfld.byte 0x37A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x37B "GPDI376,SIUL2 GPIO pad data in register n" bitfld.byte 0x37B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x37C "GPDI383,SIUL2 GPIO pad data in register n" bitfld.byte 0x37C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x37D "GPDI382,SIUL2 GPIO pad data in register n" bitfld.byte 0x37D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x37E "GPDI381,SIUL2 GPIO pad data in register n" bitfld.byte 0x37E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x37F "GPDI380,SIUL2 GPIO pad data in register n" bitfld.byte 0x37F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x380 "GPDI387,SIUL2 GPIO pad data in register n" bitfld.byte 0x380 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x381 "GPDI386,SIUL2 GPIO pad data in register n" bitfld.byte 0x381 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x382 "GPDI385,SIUL2 GPIO pad data in register n" bitfld.byte 0x382 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x383 "GPDI384,SIUL2 GPIO pad data in register n" bitfld.byte 0x383 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x384 "GPDI391,SIUL2 GPIO pad data in register n" bitfld.byte 0x384 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x385 "GPDI390,SIUL2 GPIO pad data in register n" bitfld.byte 0x385 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x386 "GPDI389,SIUL2 GPIO pad data in register n" bitfld.byte 0x386 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x387 "GPDI388,SIUL2 GPIO pad data in register n" bitfld.byte 0x387 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x388 "GPDI395,SIUL2 GPIO pad data in register n" bitfld.byte 0x388 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x389 "GPDI394,SIUL2 GPIO pad data in register n" bitfld.byte 0x389 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x38A "GPDI393,SIUL2 GPIO pad data in register n" bitfld.byte 0x38A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x38B "GPDI392,SIUL2 GPIO pad data in register n" bitfld.byte 0x38B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x38C "GPDI399,SIUL2 GPIO pad data in register n" bitfld.byte 0x38C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x38D "GPDI398,SIUL2 GPIO pad data in register n" bitfld.byte 0x38D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x38E "GPDI397,SIUL2 GPIO pad data in register n" bitfld.byte 0x38E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x38F "GPDI396,SIUL2 GPIO pad data in register n" bitfld.byte 0x38F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x390 "GPDI403,SIUL2 GPIO pad data in register n" bitfld.byte 0x390 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x391 "GPDI402,SIUL2 GPIO pad data in register n" bitfld.byte 0x391 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x392 "GPDI401,SIUL2 GPIO pad data in register n" bitfld.byte 0x392 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x393 "GPDI400,SIUL2 GPIO pad data in register n" bitfld.byte 0x393 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x394 "GPDI407,SIUL2 GPIO pad data in register n" bitfld.byte 0x394 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x395 "GPDI406,SIUL2 GPIO pad data in register n" bitfld.byte 0x395 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x396 "GPDI405,SIUL2 GPIO pad data in register n" bitfld.byte 0x396 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x397 "GPDI404,SIUL2 GPIO pad data in register n" bitfld.byte 0x397 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x398 "GPDI411,SIUL2 GPIO pad data in register n" bitfld.byte 0x398 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x399 "GPDI410,SIUL2 GPIO pad data in register n" bitfld.byte 0x399 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x39A "GPDI409,SIUL2 GPIO pad data in register n" bitfld.byte 0x39A 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x39B "GPDI408,SIUL2 GPIO pad data in register n" bitfld.byte 0x39B 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x39C "GPDI415,SIUL2 GPIO pad data in register n" bitfld.byte 0x39C 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x39D "GPDI414,SIUL2 GPIO pad data in register n" bitfld.byte 0x39D 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x39E "GPDI413,SIUL2 GPIO pad data in register n" bitfld.byte 0x39E 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x39F "GPDI412,SIUL2 GPIO pad data in register n" bitfld.byte 0x39F 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3A0 "GPDI419,SIUL2 GPIO pad data in register n" bitfld.byte 0x3A0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3A1 "GPDI418,SIUL2 GPIO pad data in register n" bitfld.byte 0x3A1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3A2 "GPDI417,SIUL2 GPIO pad data in register n" bitfld.byte 0x3A2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3A3 "GPDI416,SIUL2 GPIO pad data in register n" bitfld.byte 0x3A3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3A4 "GPDI423,SIUL2 GPIO pad data in register n" bitfld.byte 0x3A4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3A5 "GPDI422,SIUL2 GPIO pad data in register n" bitfld.byte 0x3A5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3A6 "GPDI421,SIUL2 GPIO pad data in register n" bitfld.byte 0x3A6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3A7 "GPDI420,SIUL2 GPIO pad data in register n" bitfld.byte 0x3A7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3A8 "GPDI427,SIUL2 GPIO pad data in register n" bitfld.byte 0x3A8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3A9 "GPDI426,SIUL2 GPIO pad data in register n" bitfld.byte 0x3A9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3AA "GPDI425,SIUL2 GPIO pad data in register n" bitfld.byte 0x3AA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3AB "GPDI424,SIUL2 GPIO pad data in register n" bitfld.byte 0x3AB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3AC "GPDI431,SIUL2 GPIO pad data in register n" bitfld.byte 0x3AC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3AD "GPDI430,SIUL2 GPIO pad data in register n" bitfld.byte 0x3AD 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3AE "GPDI429,SIUL2 GPIO pad data in register n" bitfld.byte 0x3AE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3AF "GPDI428,SIUL2 GPIO pad data in register n" bitfld.byte 0x3AF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3B0 "GPDI435,SIUL2 GPIO pad data in register n" bitfld.byte 0x3B0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3B1 "GPDI434,SIUL2 GPIO pad data in register n" bitfld.byte 0x3B1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3B2 "GPDI433,SIUL2 GPIO pad data in register n" bitfld.byte 0x3B2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3B3 "GPDI432,SIUL2 GPIO pad data in register n" bitfld.byte 0x3B3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3B4 "GPDI439,SIUL2 GPIO pad data in register n" bitfld.byte 0x3B4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3B5 "GPDI438,SIUL2 GPIO pad data in register n" bitfld.byte 0x3B5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3B6 "GPDI437,SIUL2 GPIO pad data in register n" bitfld.byte 0x3B6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3B7 "GPDI436,SIUL2 GPIO pad data in register n" bitfld.byte 0x3B7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3B8 "GPDI443,SIUL2 GPIO pad data in register n" bitfld.byte 0x3B8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3B9 "GPDI442,SIUL2 GPIO pad data in register n" bitfld.byte 0x3B9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3BA "GPDI441,SIUL2 GPIO pad data in register n" bitfld.byte 0x3BA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3BB "GPDI440,SIUL2 GPIO pad data in register n" bitfld.byte 0x3BB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3BC "GPDI447,SIUL2 GPIO pad data in register n" bitfld.byte 0x3BC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3BD "GPDI446,SIUL2 GPIO pad data in register n" bitfld.byte 0x3BD 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3BE "GPDI445,SIUL2 GPIO pad data in register n" bitfld.byte 0x3BE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3BF "GPDI444,SIUL2 GPIO pad data in register n" bitfld.byte 0x3BF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3C0 "GPDI451,SIUL2 GPIO pad data in register n" bitfld.byte 0x3C0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3C1 "GPDI450,SIUL2 GPIO pad data in register n" bitfld.byte 0x3C1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3C2 "GPDI449,SIUL2 GPIO pad data in register n" bitfld.byte 0x3C2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3C3 "GPDI448,SIUL2 GPIO pad data in register n" bitfld.byte 0x3C3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3C4 "GPDI455,SIUL2 GPIO pad data in register n" bitfld.byte 0x3C4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3C5 "GPDI454,SIUL2 GPIO pad data in register n" bitfld.byte 0x3C5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3C6 "GPDI453,SIUL2 GPIO pad data in register n" bitfld.byte 0x3C6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3C7 "GPDI452,SIUL2 GPIO pad data in register n" bitfld.byte 0x3C7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3C8 "GPDI459,SIUL2 GPIO pad data in register n" bitfld.byte 0x3C8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3C9 "GPDI458,SIUL2 GPIO pad data in register n" bitfld.byte 0x3C9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3CA "GPDI457,SIUL2 GPIO pad data in register n" bitfld.byte 0x3CA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3CB "GPDI456,SIUL2 GPIO pad data in register n" bitfld.byte 0x3CB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3CC "GPDI463,SIUL2 GPIO pad data in register n" bitfld.byte 0x3CC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3CD "GPDI462,SIUL2 GPIO pad data in register n" bitfld.byte 0x3CD 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3CE "GPDI461,SIUL2 GPIO pad data in register n" bitfld.byte 0x3CE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3CF "GPDI460,SIUL2 GPIO pad data in register n" bitfld.byte 0x3CF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3D0 "GPDI467,SIUL2 GPIO pad data in register n" bitfld.byte 0x3D0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3D1 "GPDI466,SIUL2 GPIO pad data in register n" bitfld.byte 0x3D1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3D2 "GPDI465,SIUL2 GPIO pad data in register n" bitfld.byte 0x3D2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3D3 "GPDI464,SIUL2 GPIO pad data in register n" bitfld.byte 0x3D3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3D4 "GPDI471,SIUL2 GPIO pad data in register n" bitfld.byte 0x3D4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3D5 "GPDI470,SIUL2 GPIO pad data in register n" bitfld.byte 0x3D5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3D6 "GPDI469,SIUL2 GPIO pad data in register n" bitfld.byte 0x3D6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3D7 "GPDI468,SIUL2 GPIO pad data in register n" bitfld.byte 0x3D7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3D8 "GPDI475,SIUL2 GPIO pad data in register n" bitfld.byte 0x3D8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3D9 "GPDI474,SIUL2 GPIO pad data in register n" bitfld.byte 0x3D9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3DA "GPDI473,SIUL2 GPIO pad data in register n" bitfld.byte 0x3DA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3DB "GPDI472,SIUL2 GPIO pad data in register n" bitfld.byte 0x3DB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3DC "GPDI479,SIUL2 GPIO pad data in register n" bitfld.byte 0x3DC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3DD "GPDI478,SIUL2 GPIO pad data in register n" bitfld.byte 0x3DD 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3DE "GPDI477,SIUL2 GPIO pad data in register n" bitfld.byte 0x3DE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3DF "GPDI476,SIUL2 GPIO pad data in register n" bitfld.byte 0x3DF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3E0 "GPDI483,SIUL2 GPIO pad data in register n" bitfld.byte 0x3E0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3E1 "GPDI482,SIUL2 GPIO pad data in register n" bitfld.byte 0x3E1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3E2 "GPDI481,SIUL2 GPIO pad data in register n" bitfld.byte 0x3E2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3E3 "GPDI480,SIUL2 GPIO pad data in register n" bitfld.byte 0x3E3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3E4 "GPDI487,SIUL2 GPIO pad data in register n" bitfld.byte 0x3E4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3E5 "GPDI486,SIUL2 GPIO pad data in register n" bitfld.byte 0x3E5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3E6 "GPDI485,SIUL2 GPIO pad data in register n" bitfld.byte 0x3E6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3E7 "GPDI484,SIUL2 GPIO pad data in register n" bitfld.byte 0x3E7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3E8 "GPDI491,SIUL2 GPIO pad data in register n" bitfld.byte 0x3E8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3E9 "GPDI490,SIUL2 GPIO pad data in register n" bitfld.byte 0x3E9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3EA "GPDI489,SIUL2 GPIO pad data in register n" bitfld.byte 0x3EA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3EB "GPDI488,SIUL2 GPIO pad data in register n" bitfld.byte 0x3EB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3EC "GPDI495,SIUL2 GPIO pad data in register n" bitfld.byte 0x3EC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3ED "GPDI494,SIUL2 GPIO pad data in register n" bitfld.byte 0x3ED 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3EE "GPDI493,SIUL2 GPIO pad data in register n" bitfld.byte 0x3EE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3EF "GPDI492,SIUL2 GPIO pad data in register n" bitfld.byte 0x3EF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3F0 "GPDI499,SIUL2 GPIO pad data in register n" bitfld.byte 0x3F0 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3F1 "GPDI498,SIUL2 GPIO pad data in register n" bitfld.byte 0x3F1 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3F2 "GPDI497,SIUL2 GPIO pad data in register n" bitfld.byte 0x3F2 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3F3 "GPDI496,SIUL2 GPIO pad data in register n" bitfld.byte 0x3F3 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3F4 "GPDI503,SIUL2 GPIO pad data in register n" bitfld.byte 0x3F4 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3F5 "GPDI502,SIUL2 GPIO pad data in register n" bitfld.byte 0x3F5 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3F6 "GPDI501,SIUL2 GPIO pad data in register n" bitfld.byte 0x3F6 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3F7 "GPDI500,SIUL2 GPIO pad data in register n" bitfld.byte 0x3F7 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3F8 "GPDI507,SIUL2 GPIO pad data in register n" bitfld.byte 0x3F8 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3F9 "GPDI506,SIUL2 GPIO pad data in register n" bitfld.byte 0x3F9 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3FA "GPDI505,SIUL2 GPIO pad data in register n" bitfld.byte 0x3FA 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3FB "GPDI504,SIUL2 GPIO pad data in register n" bitfld.byte 0x3FB 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3FC "GPDI511,SIUL2 GPIO pad data in register n" bitfld.byte 0x3FC 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3FD "GPDI510,SIUL2 GPIO pad data in register n" bitfld.byte 0x3FD 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3FE "GPDI509,SIUL2 GPIO pad data in register n" bitfld.byte 0x3FE 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." line.byte 0x3FF "GPDI508,SIUL2 GPIO pad data in register n" bitfld.byte 0x3FF 0. "PDI,Pad Data In" "0: The value of the data in signal for the..,1: The value of the data in signal for the.." group.word 0x1700++0x3F line.word 0x0 "PGPDO1,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x0 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x2 "PGPDO0,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x2 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x4 "PGPDO3,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x4 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x6 "PGPDO2,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x6 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x8 "PGPDO5,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x8 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0xA "PGPDO4,SIUL2 parallel GPIO pad data out register n" hexmask.word 0xA 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0xC "PGPDO7,SIUL2 parallel GPIO pad data out register n" hexmask.word 0xC 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0xE "PGPDO6,SIUL2 parallel GPIO pad data out register n" hexmask.word 0xE 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x10 "PGPDO9,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x10 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x12 "PGPDO8,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x12 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x14 "PGPDO11,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x14 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x16 "PGPDO10,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x16 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x18 "PGPDO13,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x18 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x1A "PGPDO12,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x1A 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x1C "PGPDO15,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x1C 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x1E "PGPDO14,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x1E 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x20 "PGPDO17,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x20 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x22 "PGPDO16,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x22 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x24 "PGPDO19,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x24 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x26 "PGPDO18,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x26 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x28 "PGPDO21,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x28 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x2A "PGPDO20,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x2A 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x2C "PGPDO23,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x2C 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x2E "PGPDO22,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x2E 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x30 "PGPDO25,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x30 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x32 "PGPDO24,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x32 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x34 "PGPDO27,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x34 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x36 "PGPDO26,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x36 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x38 "PGPDO29,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x38 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x3A "PGPDO28,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x3A 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x3C "PGPDO31,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x3C 0.--15. 1. "PPDO,Parallel Pad Data Out" line.word 0x3E "PGPDO30,SIUL2 parallel GPIO pad data out register n" hexmask.word 0x3E 0.--15. 1. "PPDO,Parallel Pad Data Out" rgroup.word 0x1740++0x3F line.word 0x0 "PGPDI1,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x0 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x2 "PGPDI0,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x2 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x4 "PGPDI3,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x4 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x6 "PGPDI2,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x6 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x8 "PGPDI5,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x8 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0xA "PGPDI4,SIUL2 parallel GPIO pad data in register n" hexmask.word 0xA 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0xC "PGPDI7,SIUL2 parallel GPIO pad data in register n" hexmask.word 0xC 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0xE "PGPDI6,SIUL2 parallel GPIO pad data in register n" hexmask.word 0xE 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x10 "PGPDI9,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x10 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x12 "PGPDI8,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x12 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x14 "PGPDI11,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x14 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x16 "PGPDI10,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x16 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x18 "PGPDI13,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x18 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x1A "PGPDI12,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x1A 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x1C "PGPDI15,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x1C 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x1E "PGPDI14,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x1E 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x20 "PGPDI17,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x20 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x22 "PGPDI16,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x22 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x24 "PGPDI19,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x24 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x26 "PGPDI18,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x26 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x28 "PGPDI21,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x28 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x2A "PGPDI20,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x2A 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x2C "PGPDI23,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x2C 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x2E "PGPDI22,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x2E 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x30 "PGPDI25,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x30 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x32 "PGPDI24,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x32 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x34 "PGPDI27,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x34 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x36 "PGPDI26,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x36 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x38 "PGPDI29,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x38 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x3A "PGPDI28,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x3A 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x3C "PGPDI31,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x3C 0.--15. 1. "PPDI,Parallel Pad Data In" line.word 0x3E "PGPDI30,SIUL2 parallel GPIO pad data in register n" hexmask.word 0x3E 0.--15. 1. "PPDI,Parallel Pad Data In" group.long 0x1780++0x7F line.long 0x0 "MPGPDO0,SIUL2 masked parallel GPIO pad data output register 0" hexmask.long.word 0x0 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x0 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x4 "MPGPDO1,SIUL2 masked parallel GPIO pad data output register 1" hexmask.long.word 0x4 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x4 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x8 "MPGPDO2,SIUL2 masked parallel GPIO pad data output register 2" hexmask.long.word 0x8 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x8 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0xC "MPGPDO3,SIUL2 masked parallel GPIO pad data output register 3" hexmask.long.word 0xC 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0xC 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x10 "MPGPDO4,SIUL2 masked parallel GPIO pad data output register 4" hexmask.long.word 0x10 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x10 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x14 "MPGPDO5,SIUL2 masked parallel GPIO pad data output register 5" hexmask.long.word 0x14 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x14 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x18 "MPGPDO6,SIUL2 masked parallel GPIO pad data output register 6" hexmask.long.word 0x18 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x18 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x1C "MPGPDO7,SIUL2 masked parallel GPIO pad data output register 7" hexmask.long.word 0x1C 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x1C 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x20 "MPGPDO8,SIUL2 masked parallel GPIO pad data output register 8" hexmask.long.word 0x20 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x20 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x24 "MPGPDO9,SIUL2 masked parallel GPIO pad data output register 9" hexmask.long.word 0x24 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x24 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x28 "MPGPDO10,SIUL2 masked parallel GPIO pad data output register 10" hexmask.long.word 0x28 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x28 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x2C "MPGPDO11,SIUL2 masked parallel GPIO pad data output register 11" hexmask.long.word 0x2C 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x2C 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x30 "MPGPDO12,SIUL2 masked parallel GPIO pad data output register 12" hexmask.long.word 0x30 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x30 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x34 "MPGPDO13,SIUL2 masked parallel GPIO pad data output register 13" hexmask.long.word 0x34 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x34 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x38 "MPGPDO14,SIUL2 masked parallel GPIO pad data output register 14" hexmask.long.word 0x38 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x38 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x3C "MPGPDO15,SIUL2 masked parallel GPIO pad data output register 15" hexmask.long.word 0x3C 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x3C 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x40 "MPGPDO16,SIUL2 masked parallel GPIO pad data output register 16" hexmask.long.word 0x40 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x40 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x44 "MPGPDO17,SIUL2 masked parallel GPIO pad data output register 17" hexmask.long.word 0x44 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x44 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x48 "MPGPDO18,SIUL2 masked parallel GPIO pad data output register 18" hexmask.long.word 0x48 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x48 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x4C "MPGPDO19,SIUL2 masked parallel GPIO pad data output register 19" hexmask.long.word 0x4C 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x4C 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x50 "MPGPDO20,SIUL2 masked parallel GPIO pad data output register 20" hexmask.long.word 0x50 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x50 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x54 "MPGPDO21,SIUL2 masked parallel GPIO pad data output register 21" hexmask.long.word 0x54 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x54 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x58 "MPGPDO22,SIUL2 masked parallel GPIO pad data output register 22" hexmask.long.word 0x58 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x58 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x5C "MPGPDO23,SIUL2 masked parallel GPIO pad data output register 23" hexmask.long.word 0x5C 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x5C 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x60 "MPGPDO24,SIUL2 masked parallel GPIO pad data output register 24" hexmask.long.word 0x60 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x60 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x64 "MPGPDO25,SIUL2 masked parallel GPIO pad data output register 25" hexmask.long.word 0x64 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x64 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x68 "MPGPDO26,SIUL2 masked parallel GPIO pad data output register 26" hexmask.long.word 0x68 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x68 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x6C "MPGPDO27,SIUL2 masked parallel GPIO pad data output register 27" hexmask.long.word 0x6C 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x6C 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x70 "MPGPDO28,SIUL2 masked parallel GPIO pad data output register 28" hexmask.long.word 0x70 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x70 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x74 "MPGPDO29,SIUL2 masked parallel GPIO pad data output register 29" hexmask.long.word 0x74 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x74 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x78 "MPGPDO30,SIUL2 masked parallel GPIO pad data output register 30" hexmask.long.word 0x78 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x78 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" line.long 0x7C "MPGPDO31,SIUL2 masked parallel GPIO pad data output register 31" hexmask.long.word 0x7C 16.--31. 1. "MASK,Mask Field (MASK[x])" hexmask.long.word 0x7C 0.--15. 1. "MPPDO,Masked Parallel Pad Data Out (MPPDO[x])" tree.end tree.end tree "SPIQ (Queued Serial Peripheral Interface)" base ad:0x0 tree "SPIQ_0" tree "SPIQ_0_GLBL" base ad:0x70E70000 group.long 0x0++0x3 line.long 0x0 "MCR,Module configuration register" bitfld.long 0x0 31. "MSTR,Selects SPI functional mode" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK clock enable" "0: SCK is non continuous. It is generated only..,1: SCK is continuous. It is generated throughout.." newline hexmask.long.word 0x0 16.--27. 1. "PCS_DEFAULT_LEVEL,Selects PCS inactive level" newline bitfld.long 0x0 15. "SAFE_SPI_MODE,Selects if SafeSPI mode is enabled or not" "0: Module works in Normal SPI Mode,1: Module works in Safe SPI Mode" newline bitfld.long 0x0 9.--10. "SAMPLE_POINT,SAMPLE_POINT field controls when the SPI master samples SIN and drives SOUT in Modified Transfer Format." "0: 00,1: 00,2: Modified SPI Transfer,?" newline bitfld.long 0x0 8. "MTFE,Modified Timing Format Enable. The MTFE bit enables a modified transfer format to be used." "0: Modified SPI transfer format disabled,1: Modified SPI transfer format enabled" newline bitfld.long 0x0 6. "DEBUG_FREEZE,Freeze during debug mode" "0: Do not stop serial transfer,1: Stop serial transfer" newline bitfld.long 0x0 4. "LOOPBACK_EN,Loopback enable" "0: Loopback disabled,1: Internal loopback enabled" newline bitfld.long 0x0 2. "CRC_ERR_STOP,CRC Error Stop Enable" "0: Continue transfer after CRC error in received..,1: Stop transfer after CRC error in received SPI.." newline bitfld.long 0x0 1. "PAR_ERR_STOP,Parity Error Stop." "0: SPI frames transmission continue.,1: SPI frames transmission stop." newline bitfld.long 0x0 0. "MODULE_EN,Enable Module" "0: Module is disabled,1: Module is enabled)" rgroup.long 0x4++0x3 line.long 0x0 "HW_CONFIG_STATUS,HW configuration status" bitfld.long 0x0 16. "AUXFIFO_PRESENT_IN_Q0,Specifies if AuxFifo is instantiated for Queue0" "0: AuxFifo is not present in Queue[0],1: AuxFifo is present in Queue[0]" newline hexmask.long.byte 0x0 8.--11. 1. "NUM_TAC,This specifies the number of Transfer Attribute Control (TAC) registers instantiated in design" newline hexmask.long.byte 0x0 0.--3. 1. "NUM_QUEUES,This specifies the number of HW Queues instantiated in design" rgroup.long 0x10++0x3 line.long 0x0 "GLOBAL_STATUS,GLOBAL Status" hexmask.long.byte 0x0 16.--23. 1. "QUEUE_NUM,Specify the queue number in case of SPIQ_STATUS as: EOS ERROR FLUSH_IN_PROGRESS" newline bitfld.long 0x0 0.--2. "SPIQ_STATUS,SPIQ status" "0: IDLE => all queues are idle.,1: RUNNING => SPI transfer ongoing,2: WAIT_TRIGGER => no SPI transfer ongoing all..,3: SUSPENDED => all queues in suspended state..,?,?,?,7: ERROR => at least one queue is reporting ERROR.." group.long 0x20++0x3 line.long 0x0 "GLOBAL_IRQ_CTRL,GLOBAL interrupt control" hexmask.long.byte 0x0 16.--23. 1. "ERR_IRQ_EN,Interrupt enable for Error interrupts for individual Queues" newline hexmask.long.byte 0x0 0.--7. 1. "STATUS_IRQ_EN,Interrupt enable for Status interrupts for individual Queues" rgroup.long 0x24++0x3 line.long 0x0 "GLOBAL_IRQ_STATUS,GLOBAL interrupt status" hexmask.long.byte 0x0 16.--23. 1. "ERR_IRQ_STATUS,Error interrupts status from individual Queues" newline hexmask.long.byte 0x0 0.--7. 1. "STATUS_IRQ,Status interrupts from individual Queues" group.long 0x40++0x3F line.long 0x0 "TAC0_L,Transfer Attribute Control n Low" bitfld.long 0x0 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x0 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x0 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x0 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x0 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x0 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x0 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x0 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x4 "TAC0_H,Transfer Attribute Control n High" bitfld.long 0x4 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x4 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x4 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x4 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x4 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x8 "TAC1_L,Transfer Attribute Control n Low" bitfld.long 0x8 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x8 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x8 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x8 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x8 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x8 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x8 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x8 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0xC "TAC1_H,Transfer Attribute Control n High" bitfld.long 0xC 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0xC 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0xC 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0xC 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0xC 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x10 "TAC2_L,Transfer Attribute Control n Low" bitfld.long 0x10 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x10 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x10 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x10 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x10 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x10 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x10 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x10 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x14 "TAC2_H,Transfer Attribute Control n High" bitfld.long 0x14 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x14 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x14 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x14 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x14 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x18 "TAC3_L,Transfer Attribute Control n Low" bitfld.long 0x18 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x18 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x18 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x18 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x18 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x18 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x18 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x18 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x1C "TAC3_H,Transfer Attribute Control n High" bitfld.long 0x1C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x1C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x1C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x1C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x1C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x1C 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x20 "TAC4_L,Transfer Attribute Control n Low" bitfld.long 0x20 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x20 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x20 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x20 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x20 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x20 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x20 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x20 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x24 "TAC4_H,Transfer Attribute Control n High" bitfld.long 0x24 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x24 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x24 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x24 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x24 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x24 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x28 "TAC5_L,Transfer Attribute Control n Low" bitfld.long 0x28 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x28 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x28 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x28 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x28 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x28 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x28 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x28 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x2C "TAC5_H,Transfer Attribute Control n High" bitfld.long 0x2C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x2C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x2C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x2C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x2C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x2C 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x30 "TAC6_L,Transfer Attribute Control n Low" bitfld.long 0x30 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x30 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x30 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x30 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x30 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x30 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x30 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x30 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x34 "TAC6_H,Transfer Attribute Control n High" bitfld.long 0x34 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x34 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x34 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x34 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x34 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x34 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x38 "TAC7_L,Transfer Attribute Control n Low" bitfld.long 0x38 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x38 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x38 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x38 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x38 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x38 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x38 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x38 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x3C "TAC7_H,Transfer Attribute Control n High" bitfld.long 0x3C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x3C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x3C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x3C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x3C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x3C 0.--15. 1. "DTC,Data transfer Count per command entry" group.long 0xC0++0x3 line.long 0x0 "MONITOR_SLAVE_SELECT,Monitor slave select" bitfld.long 0x0 31. "MONITOR_SPI_CONNECTED,Monitor SPI module connected to one of the slave select" "0: Monitor SPI is not connected,1: Monitor SPI connected" newline hexmask.long.word 0x0 0.--11. 1. "MONITOR_SPI_SLAVE_SELECT,Slave select number on which Monitor SPI module is connected" tree.end tree "SPIQ_0_Q0" base ad:0x70E70100 group.long 0x0++0x3 line.long 0x0 "Q0_SETUP,Queue n setup" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "?,?,?,?,?,?,?,7: lowest to highest priority" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline hexmask.long.byte 0x0 8.--12. 1. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline hexmask.long.byte 0x0 0.--4. 1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" rgroup.long 0x4++0x3 line.long 0x0 "Q0_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q0_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q0_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q0_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q0_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q0_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q0_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline hexmask.long.byte 0x0 8.--12. 1. "TXFIFO_WR_PTR,TxFIFO write pointer" newline hexmask.long.byte 0x0 0.--4. 1. "TXFIFO_RD_PTR,TxFIFO read pointer" line.long 0x4 "Q0_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline hexmask.long.byte 0x4 8.--12. 1. "RXFIFO_WR_PTR,RxFIFO write pointer" newline hexmask.long.byte 0x4 0.--4. 1. "RXFIFO_RD_PTR,RxFIFO read pointer" group.long 0x8C++0x3 line.long 0x0 "Q0_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q0_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q0_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q0_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q0_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q0_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q0_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q0_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q0_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q0_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q0_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_0_Q1" base ad:0x70E70200 group.long 0x0++0x3 line.long 0x0 "Q1_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q1_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q1_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q1_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q1_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q1_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q1_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q1_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q1_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q1_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q1_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q1_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q1_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q1_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q1_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q1_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q1_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q1_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q1_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q1_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q1_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_0_Q2" base ad:0x70E70300 group.long 0x0++0x3 line.long 0x0 "Q2_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q2_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q2_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q2_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q2_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q2_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q2_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q2_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q2_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q2_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q2_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q2_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q2_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q2_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q2_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q2_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q2_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q2_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q2_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q2_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q2_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_0_Q3" base ad:0x70E70400 group.long 0x0++0x3 line.long 0x0 "Q3_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q3_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q3_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q3_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q3_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q3_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q3_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q3_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q3_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q3_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q3_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q3_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q3_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q3_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q3_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q3_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q3_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q3_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q3_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q3_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q3_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_0_Q4" base ad:0x70E70500 group.long 0x0++0x3 line.long 0x0 "Q4_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q4_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q4_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q4_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q4_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q4_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q4_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q4_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q4_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q4_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q4_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q4_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q4_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q4_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q4_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q4_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q4_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q4_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q4_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q4_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q4_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_0_Q5" base ad:0x70E70600 group.long 0x0++0x3 line.long 0x0 "Q5_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q5_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q5_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q5_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q5_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q5_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q5_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q5_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q5_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q5_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q5_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q5_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q5_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q5_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q5_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q5_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q5_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q5_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q5_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q5_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q5_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_0_Q6" base ad:0x70E70700 group.long 0x0++0x3 line.long 0x0 "Q6_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q6_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q6_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q6_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q6_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q6_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q6_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q6_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q6_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q6_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q6_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q6_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q6_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q6_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q6_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q6_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q6_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q6_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q6_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q6_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q6_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_0_Q7" base ad:0x70E70800 group.long 0x0++0x3 line.long 0x0 "Q7_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q7_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q7_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q7_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q7_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q7_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q7_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q7_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q7_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline hexmask.long.byte 0x0 8.--15. 1. "TXFIFO_WR_PTR,TxFIFO write pointer" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_RD_PTR,TxFIFO read pointer" line.long 0x4 "Q7_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline hexmask.long.byte 0x4 8.--15. 1. "RXFIFO_WR_PTR,RxFIFO write pointer" newline hexmask.long.byte 0x4 0.--7. 1. "RXFIFO_RD_PTR,RxFIFO read pointer" group.long 0x8C++0x3 line.long 0x0 "Q7_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q7_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q7_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q7_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q7_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q7_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q7_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q7_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q7_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q7_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q7_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree.end tree "SPIQ_1" tree "SPIQ_1_GLBL" base ad:0x71A2C000 group.long 0x0++0x3 line.long 0x0 "MCR,Module configuration register" bitfld.long 0x0 31. "MSTR,Selects SPI functional mode" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK clock enable" "0: SCK is non continuous. It is generated only..,1: SCK is continuous. It is generated throughout.." newline hexmask.long.word 0x0 16.--27. 1. "PCS_DEFAULT_LEVEL,Selects PCS inactive level" newline bitfld.long 0x0 15. "SAFE_SPI_MODE,Selects if SafeSPI mode is enabled or not" "0: Module works in Normal SPI Mode,1: Module works in Safe SPI Mode" newline bitfld.long 0x0 9.--10. "SAMPLE_POINT,SAMPLE_POINT field controls when the SPI master samples SIN and drives SOUT in Modified Transfer Format." "0: 00,1: 00,2: Modified SPI Transfer,?" newline bitfld.long 0x0 8. "MTFE,Modified Timing Format Enable. The MTFE bit enables a modified transfer format to be used." "0: Modified SPI transfer format disabled,1: Modified SPI transfer format enabled" newline bitfld.long 0x0 6. "DEBUG_FREEZE,Freeze during debug mode" "0: Do not stop serial transfer,1: Stop serial transfer" newline bitfld.long 0x0 4. "LOOPBACK_EN,Loopback enable" "0: Loopback disabled,1: Internal loopback enabled" newline bitfld.long 0x0 2. "CRC_ERR_STOP,CRC Error Stop Enable" "0: Continue transfer after CRC error in received..,1: Stop transfer after CRC error in received SPI.." newline bitfld.long 0x0 1. "PAR_ERR_STOP,Parity Error Stop." "0: SPI frames transmission continue.,1: SPI frames transmission stop." newline bitfld.long 0x0 0. "MODULE_EN,Enable Module" "0: Module is disabled,1: Module is enabled)" rgroup.long 0x4++0x3 line.long 0x0 "HW_CONFIG_STATUS,HW configuration status" bitfld.long 0x0 16. "AUXFIFO_PRESENT_IN_Q0,Specifies if AuxFifo is instantiated for Queue0" "0: AuxFifo is not present in Queue[0],1: AuxFifo is present in Queue[0]" newline hexmask.long.byte 0x0 8.--11. 1. "NUM_TAC,This specifies the number of Transfer Attribute Control (TAC) registers instantiated in design" newline hexmask.long.byte 0x0 0.--3. 1. "NUM_QUEUES,This specifies the number of HW Queues instantiated in design" rgroup.long 0x10++0x3 line.long 0x0 "GLOBAL_STATUS,GLOBAL Status" hexmask.long.byte 0x0 16.--23. 1. "QUEUE_NUM,Specify the queue number in case of SPIQ_STATUS as: EOS ERROR FLUSH_IN_PROGRESS" newline bitfld.long 0x0 0.--2. "SPIQ_STATUS,SPIQ status" "0: IDLE => all queues are idle.,1: RUNNING => SPI transfer ongoing,2: WAIT_TRIGGER => no SPI transfer ongoing all..,3: SUSPENDED => all queues in suspended state..,?,?,?,7: ERROR => at least one queue is reporting ERROR.." group.long 0x20++0x3 line.long 0x0 "GLOBAL_IRQ_CTRL,GLOBAL interrupt control" hexmask.long.byte 0x0 16.--23. 1. "ERR_IRQ_EN,Interrupt enable for Error interrupts for individual Queues" newline hexmask.long.byte 0x0 0.--7. 1. "STATUS_IRQ_EN,Interrupt enable for Status interrupts for individual Queues" rgroup.long 0x24++0x3 line.long 0x0 "GLOBAL_IRQ_STATUS,GLOBAL interrupt status" hexmask.long.byte 0x0 16.--23. 1. "ERR_IRQ_STATUS,Error interrupts status from individual Queues" newline hexmask.long.byte 0x0 0.--7. 1. "STATUS_IRQ,Status interrupts from individual Queues" group.long 0x40++0x3F line.long 0x0 "TAC0_L,Transfer Attribute Control n Low" bitfld.long 0x0 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x0 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x0 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x0 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x0 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x0 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x0 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x0 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x4 "TAC0_H,Transfer Attribute Control n High" bitfld.long 0x4 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x4 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x4 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x4 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x4 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x8 "TAC1_L,Transfer Attribute Control n Low" bitfld.long 0x8 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x8 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x8 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x8 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x8 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x8 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x8 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x8 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0xC "TAC1_H,Transfer Attribute Control n High" bitfld.long 0xC 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0xC 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0xC 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0xC 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0xC 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x10 "TAC2_L,Transfer Attribute Control n Low" bitfld.long 0x10 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x10 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x10 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x10 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x10 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x10 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x10 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x10 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x14 "TAC2_H,Transfer Attribute Control n High" bitfld.long 0x14 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x14 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x14 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x14 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x14 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x18 "TAC3_L,Transfer Attribute Control n Low" bitfld.long 0x18 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x18 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x18 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x18 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x18 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x18 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x18 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x18 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x1C "TAC3_H,Transfer Attribute Control n High" bitfld.long 0x1C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x1C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x1C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x1C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x1C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x1C 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x20 "TAC4_L,Transfer Attribute Control n Low" bitfld.long 0x20 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x20 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x20 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x20 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x20 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x20 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x20 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x20 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x24 "TAC4_H,Transfer Attribute Control n High" bitfld.long 0x24 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x24 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x24 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x24 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x24 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x24 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x28 "TAC5_L,Transfer Attribute Control n Low" bitfld.long 0x28 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x28 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x28 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x28 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x28 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x28 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x28 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x28 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x2C "TAC5_H,Transfer Attribute Control n High" bitfld.long 0x2C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x2C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x2C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x2C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x2C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x2C 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x30 "TAC6_L,Transfer Attribute Control n Low" bitfld.long 0x30 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x30 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x30 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x30 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x30 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x30 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x30 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x30 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x34 "TAC6_H,Transfer Attribute Control n High" bitfld.long 0x34 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x34 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x34 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x34 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x34 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x34 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x38 "TAC7_L,Transfer Attribute Control n Low" bitfld.long 0x38 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x38 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x38 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x38 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x38 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x38 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x38 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x38 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x3C "TAC7_H,Transfer Attribute Control n High" bitfld.long 0x3C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x3C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x3C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x3C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x3C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x3C 0.--15. 1. "DTC,Data transfer Count per command entry" group.long 0xC0++0x3 line.long 0x0 "MONITOR_SLAVE_SELECT,Monitor slave select" bitfld.long 0x0 31. "MONITOR_SPI_CONNECTED,Monitor SPI module connected to one of the slave select" "0: Monitor SPI is not connected,1: Monitor SPI connected" newline hexmask.long.word 0x0 0.--11. 1. "MONITOR_SPI_SLAVE_SELECT,Slave select number on which Monitor SPI module is connected" tree.end tree "SPIQ_1_Q0" base ad:0x71A2C100 group.long 0x0++0x3 line.long 0x0 "Q0_SETUP,Queue n setup" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "?,?,?,?,?,?,?,7: lowest to highest priority" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline hexmask.long.byte 0x0 8.--12. 1. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline hexmask.long.byte 0x0 0.--4. 1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" rgroup.long 0x4++0x3 line.long 0x0 "Q0_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q0_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q0_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q0_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q0_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q0_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q0_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline hexmask.long.byte 0x0 8.--12. 1. "TXFIFO_WR_PTR,TxFIFO write pointer" newline hexmask.long.byte 0x0 0.--4. 1. "TXFIFO_RD_PTR,TxFIFO read pointer" line.long 0x4 "Q0_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline hexmask.long.byte 0x4 8.--12. 1. "RXFIFO_WR_PTR,RxFIFO write pointer" newline hexmask.long.byte 0x4 0.--4. 1. "RXFIFO_RD_PTR,RxFIFO read pointer" group.long 0x8C++0x3 line.long 0x0 "Q0_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q0_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q0_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q0_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q0_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q0_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q0_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q0_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q0_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q0_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q0_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_1_Q1" base ad:0x71A2C200 group.long 0x0++0x3 line.long 0x0 "Q1_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q1_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q1_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q1_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q1_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q1_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q1_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q1_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q1_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q1_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q1_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q1_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q1_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q1_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q1_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q1_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q1_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q1_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q1_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q1_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q1_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_1_Q2" base ad:0x71A2C300 group.long 0x0++0x3 line.long 0x0 "Q2_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q2_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q2_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q2_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q2_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q2_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q2_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q2_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q2_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q2_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q2_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q2_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q2_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q2_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q2_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q2_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q2_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q2_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q2_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q2_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q2_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_1_Q3" base ad:0x71A2C400 group.long 0x0++0x3 line.long 0x0 "Q3_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q3_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q3_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q3_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q3_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q3_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q3_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q3_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q3_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q3_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q3_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q3_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q3_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q3_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q3_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q3_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q3_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q3_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q3_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q3_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q3_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_1_Q4" base ad:0x71A2C500 group.long 0x0++0x3 line.long 0x0 "Q4_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q4_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q4_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q4_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q4_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q4_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q4_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q4_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q4_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q4_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q4_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q4_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q4_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q4_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q4_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q4_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q4_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q4_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q4_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q4_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q4_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_1_Q5" base ad:0x71A2C600 group.long 0x0++0x3 line.long 0x0 "Q5_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q5_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q5_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q5_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q5_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q5_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q5_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q5_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q5_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q5_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q5_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q5_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q5_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q5_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q5_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q5_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q5_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q5_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q5_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q5_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q5_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_1_Q6" base ad:0x71A2C700 group.long 0x0++0x3 line.long 0x0 "Q6_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q6_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q6_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q6_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q6_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q6_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q6_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q6_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q6_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q6_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q6_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q6_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q6_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q6_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q6_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q6_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q6_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q6_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q6_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q6_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q6_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_1_Q7" base ad:0x71A2C800 group.long 0x0++0x3 line.long 0x0 "Q7_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q7_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q7_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q7_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q7_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q7_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q7_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q7_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q7_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline hexmask.long.byte 0x0 8.--15. 1. "TXFIFO_WR_PTR,TxFIFO write pointer" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_RD_PTR,TxFIFO read pointer" line.long 0x4 "Q7_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline hexmask.long.byte 0x4 8.--15. 1. "RXFIFO_WR_PTR,RxFIFO write pointer" newline hexmask.long.byte 0x4 0.--7. 1. "RXFIFO_RD_PTR,RxFIFO read pointer" group.long 0x8C++0x3 line.long 0x0 "Q7_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q7_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q7_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q7_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q7_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q7_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q7_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q7_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q7_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q7_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q7_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree.end tree "SPIQ_2" tree "SPIQ_2_GLBL" base ad:0x72030000 group.long 0x0++0x3 line.long 0x0 "MCR,Module configuration register" bitfld.long 0x0 31. "MSTR,Selects SPI functional mode" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK clock enable" "0: SCK is non continuous. It is generated only..,1: SCK is continuous. It is generated throughout.." newline hexmask.long.word 0x0 16.--27. 1. "PCS_DEFAULT_LEVEL,Selects PCS inactive level" newline bitfld.long 0x0 15. "SAFE_SPI_MODE,Selects if SafeSPI mode is enabled or not" "0: Module works in Normal SPI Mode,1: Module works in Safe SPI Mode" newline bitfld.long 0x0 9.--10. "SAMPLE_POINT,SAMPLE_POINT field controls when the SPI master samples SIN and drives SOUT in Modified Transfer Format." "0: 00,1: 00,2: Modified SPI Transfer,?" newline bitfld.long 0x0 8. "MTFE,Modified Timing Format Enable. The MTFE bit enables a modified transfer format to be used." "0: Modified SPI transfer format disabled,1: Modified SPI transfer format enabled" newline bitfld.long 0x0 6. "DEBUG_FREEZE,Freeze during debug mode" "0: Do not stop serial transfer,1: Stop serial transfer" newline bitfld.long 0x0 4. "LOOPBACK_EN,Loopback enable" "0: Loopback disabled,1: Internal loopback enabled" newline bitfld.long 0x0 2. "CRC_ERR_STOP,CRC Error Stop Enable" "0: Continue transfer after CRC error in received..,1: Stop transfer after CRC error in received SPI.." newline bitfld.long 0x0 1. "PAR_ERR_STOP,Parity Error Stop." "0: SPI frames transmission continue.,1: SPI frames transmission stop." newline bitfld.long 0x0 0. "MODULE_EN,Enable Module" "0: Module is disabled,1: Module is enabled)" rgroup.long 0x4++0x3 line.long 0x0 "HW_CONFIG_STATUS,HW configuration status" bitfld.long 0x0 16. "AUXFIFO_PRESENT_IN_Q0,Specifies if AuxFifo is instantiated for Queue0" "0: AuxFifo is not present in Queue[0],1: AuxFifo is present in Queue[0]" newline hexmask.long.byte 0x0 8.--11. 1. "NUM_TAC,This specifies the number of Transfer Attribute Control (TAC) registers instantiated in design" newline hexmask.long.byte 0x0 0.--3. 1. "NUM_QUEUES,This specifies the number of HW Queues instantiated in design" rgroup.long 0x10++0x3 line.long 0x0 "GLOBAL_STATUS,GLOBAL Status" hexmask.long.byte 0x0 16.--23. 1. "QUEUE_NUM,Specify the queue number in case of SPIQ_STATUS as: EOS ERROR FLUSH_IN_PROGRESS" newline bitfld.long 0x0 0.--2. "SPIQ_STATUS,SPIQ status" "0: IDLE => all queues are idle.,1: RUNNING => SPI transfer ongoing,2: WAIT_TRIGGER => no SPI transfer ongoing all..,3: SUSPENDED => all queues in suspended state..,?,?,?,7: ERROR => at least one queue is reporting ERROR.." group.long 0x20++0x3 line.long 0x0 "GLOBAL_IRQ_CTRL,GLOBAL interrupt control" hexmask.long.byte 0x0 16.--23. 1. "ERR_IRQ_EN,Interrupt enable for Error interrupts for individual Queues" newline hexmask.long.byte 0x0 0.--7. 1. "STATUS_IRQ_EN,Interrupt enable for Status interrupts for individual Queues" rgroup.long 0x24++0x3 line.long 0x0 "GLOBAL_IRQ_STATUS,GLOBAL interrupt status" hexmask.long.byte 0x0 16.--23. 1. "ERR_IRQ_STATUS,Error interrupts status from individual Queues" newline hexmask.long.byte 0x0 0.--7. 1. "STATUS_IRQ,Status interrupts from individual Queues" group.long 0x40++0x3F line.long 0x0 "TAC0_L,Transfer Attribute Control n Low" bitfld.long 0x0 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x0 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x0 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x0 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x0 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x0 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x0 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x0 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x4 "TAC0_H,Transfer Attribute Control n High" bitfld.long 0x4 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x4 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x4 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x4 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x4 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x8 "TAC1_L,Transfer Attribute Control n Low" bitfld.long 0x8 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x8 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x8 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x8 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x8 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x8 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x8 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x8 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0xC "TAC1_H,Transfer Attribute Control n High" bitfld.long 0xC 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0xC 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0xC 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0xC 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0xC 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x10 "TAC2_L,Transfer Attribute Control n Low" bitfld.long 0x10 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x10 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x10 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x10 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x10 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x10 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x10 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x10 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x14 "TAC2_H,Transfer Attribute Control n High" bitfld.long 0x14 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x14 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x14 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x14 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x14 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x18 "TAC3_L,Transfer Attribute Control n Low" bitfld.long 0x18 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x18 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x18 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x18 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x18 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x18 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x18 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x18 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x1C "TAC3_H,Transfer Attribute Control n High" bitfld.long 0x1C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x1C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x1C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x1C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x1C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x1C 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x20 "TAC4_L,Transfer Attribute Control n Low" bitfld.long 0x20 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x20 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x20 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x20 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x20 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x20 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x20 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x20 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x24 "TAC4_H,Transfer Attribute Control n High" bitfld.long 0x24 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x24 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x24 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x24 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x24 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x24 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x28 "TAC5_L,Transfer Attribute Control n Low" bitfld.long 0x28 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x28 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x28 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x28 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x28 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x28 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x28 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x28 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x2C "TAC5_H,Transfer Attribute Control n High" bitfld.long 0x2C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x2C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x2C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x2C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x2C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x2C 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x30 "TAC6_L,Transfer Attribute Control n Low" bitfld.long 0x30 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x30 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x30 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x30 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x30 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x30 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x30 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x30 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x34 "TAC6_H,Transfer Attribute Control n High" bitfld.long 0x34 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x34 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x34 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x34 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x34 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x34 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x38 "TAC7_L,Transfer Attribute Control n Low" bitfld.long 0x38 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x38 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x38 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x38 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x38 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x38 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x38 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x38 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x3C "TAC7_H,Transfer Attribute Control n High" bitfld.long 0x3C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x3C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x3C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x3C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x3C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x3C 0.--15. 1. "DTC,Data transfer Count per command entry" group.long 0xC0++0x3 line.long 0x0 "MONITOR_SLAVE_SELECT,Monitor slave select" bitfld.long 0x0 31. "MONITOR_SPI_CONNECTED,Monitor SPI module connected to one of the slave select" "0: Monitor SPI is not connected,1: Monitor SPI connected" newline hexmask.long.word 0x0 0.--11. 1. "MONITOR_SPI_SLAVE_SELECT,Slave select number on which Monitor SPI module is connected" tree.end tree "SPIQ_2_Q0" base ad:0x72030100 group.long 0x0++0x3 line.long 0x0 "Q0_SETUP,Queue n setup" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "?,?,?,?,?,?,?,7: lowest to highest priority" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline hexmask.long.byte 0x0 8.--12. 1. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline hexmask.long.byte 0x0 0.--4. 1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" rgroup.long 0x4++0x3 line.long 0x0 "Q0_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q0_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q0_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q0_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q0_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q0_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q0_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline hexmask.long.byte 0x0 8.--12. 1. "TXFIFO_WR_PTR,TxFIFO write pointer" newline hexmask.long.byte 0x0 0.--4. 1. "TXFIFO_RD_PTR,TxFIFO read pointer" line.long 0x4 "Q0_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline hexmask.long.byte 0x4 8.--12. 1. "RXFIFO_WR_PTR,RxFIFO write pointer" newline hexmask.long.byte 0x4 0.--4. 1. "RXFIFO_RD_PTR,RxFIFO read pointer" group.long 0x8C++0x3 line.long 0x0 "Q0_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q0_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q0_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q0_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q0_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q0_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q0_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q0_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q0_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q0_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q0_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_2_Q1" base ad:0x72030200 group.long 0x0++0x3 line.long 0x0 "Q1_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q1_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q1_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q1_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q1_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q1_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q1_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q1_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q1_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q1_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q1_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q1_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q1_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q1_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q1_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q1_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q1_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q1_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q1_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q1_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q1_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_2_Q2" base ad:0x72030300 group.long 0x0++0x3 line.long 0x0 "Q2_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q2_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q2_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q2_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q2_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q2_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q2_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q2_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q2_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q2_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q2_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q2_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q2_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q2_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q2_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q2_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q2_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q2_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q2_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q2_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q2_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_2_Q3" base ad:0x72030400 group.long 0x0++0x3 line.long 0x0 "Q3_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q3_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q3_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q3_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q3_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q3_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q3_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q3_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q3_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q3_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q3_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q3_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q3_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q3_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q3_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q3_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q3_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q3_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q3_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q3_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q3_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_2_Q4" base ad:0x72030500 group.long 0x0++0x3 line.long 0x0 "Q4_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q4_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q4_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q4_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q4_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q4_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q4_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q4_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q4_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q4_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q4_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q4_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q4_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q4_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q4_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q4_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q4_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q4_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q4_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q4_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q4_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_2_Q5" base ad:0x72030600 group.long 0x0++0x3 line.long 0x0 "Q5_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q5_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q5_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q5_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q5_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q5_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q5_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q5_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q5_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q5_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q5_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q5_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q5_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q5_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q5_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q5_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q5_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q5_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q5_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q5_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q5_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_2_Q6" base ad:0x72030700 group.long 0x0++0x3 line.long 0x0 "Q6_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q6_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q6_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q6_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q6_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q6_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q6_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q6_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q6_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q6_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q6_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q6_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q6_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q6_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q6_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q6_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q6_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q6_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q6_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q6_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q6_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_2_Q7" base ad:0x72030800 group.long 0x0++0x3 line.long 0x0 "Q7_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q7_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q7_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q7_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q7_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q7_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q7_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q7_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q7_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline hexmask.long.byte 0x0 8.--15. 1. "TXFIFO_WR_PTR,TxFIFO write pointer" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_RD_PTR,TxFIFO read pointer" line.long 0x4 "Q7_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline hexmask.long.byte 0x4 8.--15. 1. "RXFIFO_WR_PTR,RxFIFO write pointer" newline hexmask.long.byte 0x4 0.--7. 1. "RXFIFO_RD_PTR,RxFIFO read pointer" group.long 0x8C++0x3 line.long 0x0 "Q7_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q7_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q7_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q7_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q7_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q7_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q7_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q7_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q7_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q7_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q7_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree.end tree "SPIQ_3" tree "SPIQ_3_GLBL" base ad:0x71A34000 group.long 0x0++0x3 line.long 0x0 "MCR,Module configuration register" bitfld.long 0x0 31. "MSTR,Selects SPI functional mode" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK clock enable" "0: SCK is non continuous. It is generated only..,1: SCK is continuous. It is generated throughout.." newline hexmask.long.word 0x0 16.--27. 1. "PCS_DEFAULT_LEVEL,Selects PCS inactive level" newline bitfld.long 0x0 15. "SAFE_SPI_MODE,Selects if SafeSPI mode is enabled or not" "0: Module works in Normal SPI Mode,1: Module works in Safe SPI Mode" newline bitfld.long 0x0 9.--10. "SAMPLE_POINT,SAMPLE_POINT field controls when the SPI master samples SIN and drives SOUT in Modified Transfer Format." "0: 00,1: 00,2: Modified SPI Transfer,?" newline bitfld.long 0x0 8. "MTFE,Modified Timing Format Enable. The MTFE bit enables a modified transfer format to be used." "0: Modified SPI transfer format disabled,1: Modified SPI transfer format enabled" newline bitfld.long 0x0 6. "DEBUG_FREEZE,Freeze during debug mode" "0: Do not stop serial transfer,1: Stop serial transfer" newline bitfld.long 0x0 4. "LOOPBACK_EN,Loopback enable" "0: Loopback disabled,1: Internal loopback enabled" newline bitfld.long 0x0 2. "CRC_ERR_STOP,CRC Error Stop Enable" "0: Continue transfer after CRC error in received..,1: Stop transfer after CRC error in received SPI.." newline bitfld.long 0x0 1. "PAR_ERR_STOP,Parity Error Stop." "0: SPI frames transmission continue.,1: SPI frames transmission stop." newline bitfld.long 0x0 0. "MODULE_EN,Enable Module" "0: Module is disabled,1: Module is enabled)" rgroup.long 0x4++0x3 line.long 0x0 "HW_CONFIG_STATUS,HW configuration status" bitfld.long 0x0 16. "AUXFIFO_PRESENT_IN_Q0,Specifies if AuxFifo is instantiated for Queue0" "0: AuxFifo is not present in Queue[0],1: AuxFifo is present in Queue[0]" newline hexmask.long.byte 0x0 8.--11. 1. "NUM_TAC,This specifies the number of Transfer Attribute Control (TAC) registers instantiated in design" newline hexmask.long.byte 0x0 0.--3. 1. "NUM_QUEUES,This specifies the number of HW Queues instantiated in design" rgroup.long 0x10++0x3 line.long 0x0 "GLOBAL_STATUS,GLOBAL Status" hexmask.long.byte 0x0 16.--23. 1. "QUEUE_NUM,Specify the queue number in case of SPIQ_STATUS as: EOS ERROR FLUSH_IN_PROGRESS" newline bitfld.long 0x0 0.--2. "SPIQ_STATUS,SPIQ status" "0: IDLE => all queues are idle.,1: RUNNING => SPI transfer ongoing,2: WAIT_TRIGGER => no SPI transfer ongoing all..,3: SUSPENDED => all queues in suspended state..,?,?,?,7: ERROR => at least one queue is reporting ERROR.." group.long 0x20++0x3 line.long 0x0 "GLOBAL_IRQ_CTRL,GLOBAL interrupt control" hexmask.long.byte 0x0 16.--23. 1. "ERR_IRQ_EN,Interrupt enable for Error interrupts for individual Queues" newline hexmask.long.byte 0x0 0.--7. 1. "STATUS_IRQ_EN,Interrupt enable for Status interrupts for individual Queues" rgroup.long 0x24++0x3 line.long 0x0 "GLOBAL_IRQ_STATUS,GLOBAL interrupt status" hexmask.long.byte 0x0 16.--23. 1. "ERR_IRQ_STATUS,Error interrupts status from individual Queues" newline hexmask.long.byte 0x0 0.--7. 1. "STATUS_IRQ,Status interrupts from individual Queues" group.long 0x40++0x3F line.long 0x0 "TAC0_L,Transfer Attribute Control n Low" bitfld.long 0x0 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x0 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x0 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x0 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x0 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x0 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x0 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x0 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x4 "TAC0_H,Transfer Attribute Control n High" bitfld.long 0x4 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x4 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x4 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x4 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x4 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x8 "TAC1_L,Transfer Attribute Control n Low" bitfld.long 0x8 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x8 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x8 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x8 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x8 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x8 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x8 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x8 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0xC "TAC1_H,Transfer Attribute Control n High" bitfld.long 0xC 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0xC 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0xC 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0xC 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0xC 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x10 "TAC2_L,Transfer Attribute Control n Low" bitfld.long 0x10 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x10 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x10 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x10 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x10 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x10 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x10 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x10 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x14 "TAC2_H,Transfer Attribute Control n High" bitfld.long 0x14 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x14 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x14 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x14 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x14 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x18 "TAC3_L,Transfer Attribute Control n Low" bitfld.long 0x18 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x18 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x18 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x18 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x18 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x18 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x18 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x18 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x1C "TAC3_H,Transfer Attribute Control n High" bitfld.long 0x1C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x1C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x1C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x1C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x1C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x1C 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x20 "TAC4_L,Transfer Attribute Control n Low" bitfld.long 0x20 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x20 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x20 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x20 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x20 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x20 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x20 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x20 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x24 "TAC4_H,Transfer Attribute Control n High" bitfld.long 0x24 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x24 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x24 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x24 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x24 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x24 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x28 "TAC5_L,Transfer Attribute Control n Low" bitfld.long 0x28 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x28 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x28 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x28 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x28 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x28 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x28 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x28 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x2C "TAC5_H,Transfer Attribute Control n High" bitfld.long 0x2C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x2C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x2C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x2C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x2C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x2C 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x30 "TAC6_L,Transfer Attribute Control n Low" bitfld.long 0x30 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x30 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x30 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x30 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x30 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x30 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x30 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x30 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x34 "TAC6_H,Transfer Attribute Control n High" bitfld.long 0x34 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x34 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x34 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x34 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x34 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x34 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x38 "TAC7_L,Transfer Attribute Control n Low" bitfld.long 0x38 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x38 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x38 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x38 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x38 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x38 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x38 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x38 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x3C "TAC7_H,Transfer Attribute Control n High" bitfld.long 0x3C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x3C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x3C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x3C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x3C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x3C 0.--15. 1. "DTC,Data transfer Count per command entry" group.long 0xC0++0x3 line.long 0x0 "MONITOR_SLAVE_SELECT,Monitor slave select" bitfld.long 0x0 31. "MONITOR_SPI_CONNECTED,Monitor SPI module connected to one of the slave select" "0: Monitor SPI is not connected,1: Monitor SPI connected" newline hexmask.long.word 0x0 0.--11. 1. "MONITOR_SPI_SLAVE_SELECT,Slave select number on which Monitor SPI module is connected" tree.end tree "SPIQ_3_Q0" base ad:0x71A34100 group.long 0x0++0x3 line.long 0x0 "Q0_SETUP,Queue n setup" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "?,?,?,?,?,?,?,7: lowest to highest priority" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline hexmask.long.byte 0x0 8.--12. 1. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline hexmask.long.byte 0x0 0.--4. 1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" rgroup.long 0x4++0x3 line.long 0x0 "Q0_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q0_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q0_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q0_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q0_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q0_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q0_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline hexmask.long.byte 0x0 8.--12. 1. "TXFIFO_WR_PTR,TxFIFO write pointer" newline hexmask.long.byte 0x0 0.--4. 1. "TXFIFO_RD_PTR,TxFIFO read pointer" line.long 0x4 "Q0_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline hexmask.long.byte 0x4 8.--12. 1. "RXFIFO_WR_PTR,RxFIFO write pointer" newline hexmask.long.byte 0x4 0.--4. 1. "RXFIFO_RD_PTR,RxFIFO read pointer" group.long 0x8C++0x3 line.long 0x0 "Q0_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q0_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q0_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q0_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q0_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q0_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q0_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q0_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q0_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q0_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q0_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_3_Q1" base ad:0x71A34200 group.long 0x0++0x3 line.long 0x0 "Q1_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q1_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q1_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q1_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q1_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q1_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q1_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q1_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q1_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q1_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q1_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q1_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q1_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q1_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q1_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q1_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q1_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q1_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q1_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q1_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q1_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_3_Q2" base ad:0x71A34300 group.long 0x0++0x3 line.long 0x0 "Q2_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q2_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q2_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q2_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q2_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q2_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q2_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q2_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q2_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q2_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q2_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q2_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q2_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q2_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q2_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q2_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q2_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q2_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q2_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q2_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q2_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_3_Q3" base ad:0x71A34400 group.long 0x0++0x3 line.long 0x0 "Q3_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q3_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q3_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q3_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q3_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q3_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q3_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q3_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q3_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q3_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q3_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q3_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q3_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q3_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q3_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q3_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q3_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q3_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q3_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q3_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q3_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_3_Q4" base ad:0x71A34500 group.long 0x0++0x3 line.long 0x0 "Q4_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q4_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q4_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q4_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q4_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q4_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q4_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q4_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q4_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q4_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q4_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q4_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q4_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q4_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q4_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q4_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q4_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q4_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q4_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q4_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q4_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_3_Q5" base ad:0x71A34600 group.long 0x0++0x3 line.long 0x0 "Q5_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q5_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q5_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q5_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q5_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q5_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q5_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q5_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q5_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q5_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q5_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q5_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q5_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q5_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q5_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q5_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q5_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q5_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q5_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q5_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q5_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_3_Q6" base ad:0x71A34700 group.long 0x0++0x3 line.long 0x0 "Q6_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q6_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q6_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q6_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q6_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q6_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q6_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q6_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q6_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q6_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q6_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q6_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q6_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q6_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q6_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q6_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q6_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q6_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q6_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q6_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q6_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_3_Q7" base ad:0x71A34800 group.long 0x0++0x3 line.long 0x0 "Q7_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q7_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q7_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q7_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q7_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q7_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q7_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q7_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q7_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline hexmask.long.byte 0x0 8.--15. 1. "TXFIFO_WR_PTR,TxFIFO write pointer" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_RD_PTR,TxFIFO read pointer" line.long 0x4 "Q7_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline hexmask.long.byte 0x4 8.--15. 1. "RXFIFO_WR_PTR,RxFIFO write pointer" newline hexmask.long.byte 0x4 0.--7. 1. "RXFIFO_RD_PTR,RxFIFO read pointer" group.long 0x8C++0x3 line.long 0x0 "Q7_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q7_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q7_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q7_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q7_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q7_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q7_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q7_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q7_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q7_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q7_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree.end tree "SPIQ_4" tree "SPIQ_4_GLBL" base ad:0x70E78000 group.long 0x0++0x3 line.long 0x0 "MCR,Module configuration register" bitfld.long 0x0 31. "MSTR,Selects SPI functional mode" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK clock enable" "0: SCK is non continuous. It is generated only..,1: SCK is continuous. It is generated throughout.." newline hexmask.long.byte 0x0 16.--23. 1. "PCS_DEFAULT_LEVEL,Selects PCS inactive level" newline bitfld.long 0x0 15. "SAFE_SPI_MODE,Selects if SafeSPI mode is enabled or not" "0: Module works in Normal SPI Mode,1: Module works in Safe SPI Mode" newline bitfld.long 0x0 9.--10. "SAMPLE_POINT,SAMPLE_POINT field controls when the SPI master samples SIN and drives SOUT in Modified Transfer Format." "0: 00,1: 00,2: Modified SPI Transfer,?" newline bitfld.long 0x0 8. "MTFE,Modified Timing Format Enable. The MTFE bit enables a modified transfer format to be used." "0: Modified SPI transfer format disabled,1: Modified SPI transfer format enabled" newline bitfld.long 0x0 6. "DEBUG_FREEZE,Freeze during debug mode" "0: Do not stop serial transfer,1: Stop serial transfer" newline bitfld.long 0x0 4. "LOOPBACK_EN,Loopback enable" "0: Loopback disabled,1: Internal loopback enabled" newline bitfld.long 0x0 2. "CRC_ERR_STOP,CRC Error Stop Enable" "0: Continue transfer after CRC error in received..,1: Stop transfer after CRC error in received SPI.." newline bitfld.long 0x0 1. "PAR_ERR_STOP,Parity Error Stop." "0: SPI frames transmission continue.,1: SPI frames transmission stop." newline bitfld.long 0x0 0. "MODULE_EN,Enable Module" "0: Module is disabled,1: Module is enabled)" rgroup.long 0x4++0x3 line.long 0x0 "HW_CONFIG_STATUS,HW configuration status" bitfld.long 0x0 16. "AUXFIFO_PRESENT_IN_Q0,Specifies if AuxFifo is instantiated for Queue0" "0: AuxFifo is not present in Queue[0],1: AuxFifo is present in Queue[0]" newline hexmask.long.byte 0x0 8.--11. 1. "NUM_TAC,This specifies the number of Transfer Attribute Control (TAC) registers instantiated in design" newline hexmask.long.byte 0x0 0.--3. 1. "NUM_QUEUES,This specifies the number of HW Queues instantiated in design" rgroup.long 0x10++0x3 line.long 0x0 "GLOBAL_STATUS,GLOBAL Status" hexmask.long.byte 0x0 16.--23. 1. "QUEUE_NUM,Specify the queue number in case of SPIQ_STATUS as: EOS ERROR FLUSH_IN_PROGRESS" newline bitfld.long 0x0 0.--2. "SPIQ_STATUS,SPIQ status" "0: IDLE => all queues are idle.,1: RUNNING => SPI transfer ongoing,2: WAIT_TRIGGER => no SPI transfer ongoing all..,3: SUSPENDED => all queues in suspended state..,?,?,?,7: ERROR => at least one queue is reporting ERROR.." group.long 0x20++0x3 line.long 0x0 "GLOBAL_IRQ_CTRL,GLOBAL interrupt control" hexmask.long.byte 0x0 16.--23. 1. "ERR_IRQ_EN,Interrupt enable for Error interrupts for individual Queues" newline hexmask.long.byte 0x0 0.--7. 1. "STATUS_IRQ_EN,Interrupt enable for Status interrupts for individual Queues" rgroup.long 0x24++0x3 line.long 0x0 "GLOBAL_IRQ_STATUS,GLOBAL interrupt status" hexmask.long.byte 0x0 16.--23. 1. "ERR_IRQ_STATUS,Error interrupts status from individual Queues" newline hexmask.long.byte 0x0 0.--7. 1. "STATUS_IRQ,Status interrupts from individual Queues" group.long 0x40++0x3F line.long 0x0 "TAC0_L,Transfer Attribute Control n Low" bitfld.long 0x0 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x0 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x0 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x0 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x0 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x0 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x0 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x0 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x4 "TAC0_H,Transfer Attribute Control n High" bitfld.long 0x4 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x4 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x4 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x4 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x4 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x8 "TAC1_L,Transfer Attribute Control n Low" bitfld.long 0x8 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x8 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x8 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x8 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x8 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x8 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x8 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x8 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0xC "TAC1_H,Transfer Attribute Control n High" bitfld.long 0xC 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0xC 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0xC 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0xC 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0xC 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x10 "TAC2_L,Transfer Attribute Control n Low" bitfld.long 0x10 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x10 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x10 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x10 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x10 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x10 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x10 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x10 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x14 "TAC2_H,Transfer Attribute Control n High" bitfld.long 0x14 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x14 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x14 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x14 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x14 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x18 "TAC3_L,Transfer Attribute Control n Low" bitfld.long 0x18 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x18 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x18 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x18 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x18 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x18 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x18 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x18 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x1C "TAC3_H,Transfer Attribute Control n High" bitfld.long 0x1C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x1C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x1C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x1C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x1C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x1C 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x20 "TAC4_L,Transfer Attribute Control n Low" bitfld.long 0x20 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x20 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x20 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x20 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x20 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x20 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x20 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x20 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x24 "TAC4_H,Transfer Attribute Control n High" bitfld.long 0x24 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x24 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x24 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x24 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x24 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x24 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x28 "TAC5_L,Transfer Attribute Control n Low" bitfld.long 0x28 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x28 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x28 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x28 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x28 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x28 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x28 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x28 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x2C "TAC5_H,Transfer Attribute Control n High" bitfld.long 0x2C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x2C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x2C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x2C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x2C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x2C 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x30 "TAC6_L,Transfer Attribute Control n Low" bitfld.long 0x30 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x30 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x30 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x30 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x30 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x30 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x30 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x30 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x34 "TAC6_H,Transfer Attribute Control n High" bitfld.long 0x34 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x34 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x34 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x34 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x34 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x34 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x38 "TAC7_L,Transfer Attribute Control n Low" bitfld.long 0x38 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x38 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x38 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x38 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x38 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x38 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x38 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x38 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x3C "TAC7_H,Transfer Attribute Control n High" bitfld.long 0x3C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x3C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x3C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x3C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x3C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x3C 0.--15. 1. "DTC,Data transfer Count per command entry" group.long 0xC0++0x3 line.long 0x0 "MONITOR_SLAVE_SELECT,Monitor slave select" bitfld.long 0x0 31. "MONITOR_SPI_CONNECTED,Monitor SPI module connected to one of the slave select" "0: Monitor SPI is not connected,1: Monitor SPI connected" newline hexmask.long.byte 0x0 0.--7. 1. "MONITOR_SPI_SLAVE_SELECT,Slave select number on which Monitor SPI module is connected" tree.end tree "SPIQ_4_Q0" base ad:0x70E78100 group.long 0x0++0x3 line.long 0x0 "Q0_SETUP,Queue n setup" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "?,?,?,?,?,?,?,7: lowest to highest priority" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline hexmask.long.byte 0x0 8.--12. 1. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline hexmask.long.byte 0x0 0.--4. 1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" rgroup.long 0x4++0x3 line.long 0x0 "Q0_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q0_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q0_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q0_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q0_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q0_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q0_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline hexmask.long.byte 0x0 8.--12. 1. "TXFIFO_WR_PTR,TxFIFO write pointer" newline hexmask.long.byte 0x0 0.--4. 1. "TXFIFO_RD_PTR,TxFIFO read pointer" line.long 0x4 "Q0_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline hexmask.long.byte 0x4 8.--12. 1. "RXFIFO_WR_PTR,RxFIFO write pointer" newline hexmask.long.byte 0x4 0.--4. 1. "RXFIFO_RD_PTR,RxFIFO read pointer" group.long 0x8C++0x3 line.long 0x0 "Q0_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q0_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q0_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q0_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q0_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q0_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q0_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q0_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q0_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q0_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q0_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_4_Q1" base ad:0x70E78200 group.long 0x0++0x3 line.long 0x0 "Q1_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q1_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q1_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q1_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q1_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q1_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q1_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q1_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q1_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q1_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q1_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q1_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q1_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q1_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q1_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q1_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q1_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q1_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q1_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q1_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q1_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_4_Q2" base ad:0x70E78300 group.long 0x0++0x3 line.long 0x0 "Q2_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q2_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q2_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q2_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q2_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q2_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q2_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q2_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q2_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q2_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q2_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q2_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q2_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q2_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q2_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q2_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q2_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q2_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q2_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q2_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q2_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_4_Q3" base ad:0x70E78400 group.long 0x0++0x3 line.long 0x0 "Q3_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q3_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q3_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q3_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q3_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q3_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q3_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q3_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q3_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q3_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q3_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q3_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q3_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q3_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q3_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q3_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q3_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q3_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q3_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q3_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q3_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_4_Q4" base ad:0x70E78500 group.long 0x0++0x3 line.long 0x0 "Q4_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q4_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q4_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q4_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q4_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q4_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q4_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q4_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q4_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q4_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q4_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q4_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q4_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q4_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q4_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q4_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q4_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q4_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q4_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q4_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q4_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_4_Q5" base ad:0x70E78600 group.long 0x0++0x3 line.long 0x0 "Q5_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q5_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q5_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q5_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q5_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q5_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q5_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q5_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q5_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q5_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q5_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q5_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q5_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q5_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q5_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q5_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q5_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q5_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q5_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q5_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q5_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_4_Q6" base ad:0x70E78700 group.long 0x0++0x3 line.long 0x0 "Q6_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q6_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q6_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q6_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q6_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q6_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q6_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q6_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q6_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q6_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q6_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q6_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q6_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q6_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q6_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q6_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q6_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q6_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q6_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q6_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q6_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_4_Q7" base ad:0x70E78800 group.long 0x0++0x3 line.long 0x0 "Q7_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q7_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q7_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q7_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q7_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q7_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q7_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q7_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q7_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline hexmask.long.byte 0x0 8.--15. 1. "TXFIFO_WR_PTR,TxFIFO write pointer" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_RD_PTR,TxFIFO read pointer" line.long 0x4 "Q7_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline hexmask.long.byte 0x4 8.--15. 1. "RXFIFO_WR_PTR,RxFIFO write pointer" newline hexmask.long.byte 0x4 0.--7. 1. "RXFIFO_RD_PTR,RxFIFO read pointer" group.long 0x8C++0x3 line.long 0x0 "Q7_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q7_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q7_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q7_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q7_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q7_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q7_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q7_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q7_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q7_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q7_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree.end tree "SPIQ_5" tree "SPIQ_5_GLBL" base ad:0x7203C000 group.long 0x0++0x3 line.long 0x0 "MCR,Module configuration register" bitfld.long 0x0 31. "MSTR,Selects SPI functional mode" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK clock enable" "0: SCK is non continuous. It is generated only..,1: SCK is continuous. It is generated throughout.." newline hexmask.long.byte 0x0 16.--23. 1. "PCS_DEFAULT_LEVEL,Selects PCS inactive level" newline bitfld.long 0x0 15. "SAFE_SPI_MODE,Selects if SafeSPI mode is enabled or not" "0: Module works in Normal SPI Mode,1: Module works in Safe SPI Mode" newline bitfld.long 0x0 9.--10. "SAMPLE_POINT,SAMPLE_POINT field controls when the SPI master samples SIN and drives SOUT in Modified Transfer Format." "0: 00,1: 00,2: Modified SPI Transfer,?" newline bitfld.long 0x0 8. "MTFE,Modified Timing Format Enable. The MTFE bit enables a modified transfer format to be used." "0: Modified SPI transfer format disabled,1: Modified SPI transfer format enabled" newline bitfld.long 0x0 6. "DEBUG_FREEZE,Freeze during debug mode" "0: Do not stop serial transfer,1: Stop serial transfer" newline bitfld.long 0x0 4. "LOOPBACK_EN,Loopback enable" "0: Loopback disabled,1: Internal loopback enabled" newline bitfld.long 0x0 2. "CRC_ERR_STOP,CRC Error Stop Enable" "0: Continue transfer after CRC error in received..,1: Stop transfer after CRC error in received SPI.." newline bitfld.long 0x0 1. "PAR_ERR_STOP,Parity Error Stop." "0: SPI frames transmission continue.,1: SPI frames transmission stop." newline bitfld.long 0x0 0. "MODULE_EN,Enable Module" "0: Module is disabled,1: Module is enabled)" rgroup.long 0x4++0x3 line.long 0x0 "HW_CONFIG_STATUS,HW configuration status" bitfld.long 0x0 16. "AUXFIFO_PRESENT_IN_Q0,Specifies if AuxFifo is instantiated for Queue0" "0: AuxFifo is not present in Queue[0],1: AuxFifo is present in Queue[0]" newline hexmask.long.byte 0x0 8.--11. 1. "NUM_TAC,This specifies the number of Transfer Attribute Control (TAC) registers instantiated in design" newline hexmask.long.byte 0x0 0.--3. 1. "NUM_QUEUES,This specifies the number of HW Queues instantiated in design" rgroup.long 0x10++0x3 line.long 0x0 "GLOBAL_STATUS,GLOBAL Status" hexmask.long.byte 0x0 16.--23. 1. "QUEUE_NUM,Specify the queue number in case of SPIQ_STATUS as: EOS ERROR FLUSH_IN_PROGRESS" newline bitfld.long 0x0 0.--2. "SPIQ_STATUS,SPIQ status" "0: IDLE => all queues are idle.,1: RUNNING => SPI transfer ongoing,2: WAIT_TRIGGER => no SPI transfer ongoing all..,3: SUSPENDED => all queues in suspended state..,?,?,?,7: ERROR => at least one queue is reporting ERROR.." group.long 0x20++0x3 line.long 0x0 "GLOBAL_IRQ_CTRL,GLOBAL interrupt control" hexmask.long.byte 0x0 16.--23. 1. "ERR_IRQ_EN,Interrupt enable for Error interrupts for individual Queues" newline hexmask.long.byte 0x0 0.--7. 1. "STATUS_IRQ_EN,Interrupt enable for Status interrupts for individual Queues" rgroup.long 0x24++0x3 line.long 0x0 "GLOBAL_IRQ_STATUS,GLOBAL interrupt status" hexmask.long.byte 0x0 16.--23. 1. "ERR_IRQ_STATUS,Error interrupts status from individual Queues" newline hexmask.long.byte 0x0 0.--7. 1. "STATUS_IRQ,Status interrupts from individual Queues" group.long 0x40++0x3F line.long 0x0 "TAC0_L,Transfer Attribute Control n Low" bitfld.long 0x0 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x0 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x0 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x0 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x0 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x0 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x0 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x0 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x4 "TAC0_H,Transfer Attribute Control n High" bitfld.long 0x4 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x4 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x4 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x4 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x4 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x8 "TAC1_L,Transfer Attribute Control n Low" bitfld.long 0x8 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x8 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x8 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x8 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x8 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x8 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x8 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x8 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0xC "TAC1_H,Transfer Attribute Control n High" bitfld.long 0xC 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0xC 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0xC 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0xC 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0xC 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x10 "TAC2_L,Transfer Attribute Control n Low" bitfld.long 0x10 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x10 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x10 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x10 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x10 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x10 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x10 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x10 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x14 "TAC2_H,Transfer Attribute Control n High" bitfld.long 0x14 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x14 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x14 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x14 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x14 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x18 "TAC3_L,Transfer Attribute Control n Low" bitfld.long 0x18 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x18 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x18 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x18 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x18 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x18 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x18 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x18 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x1C "TAC3_H,Transfer Attribute Control n High" bitfld.long 0x1C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x1C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x1C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x1C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x1C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x1C 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x20 "TAC4_L,Transfer Attribute Control n Low" bitfld.long 0x20 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x20 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x20 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x20 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x20 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x20 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x20 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x20 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x24 "TAC4_H,Transfer Attribute Control n High" bitfld.long 0x24 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x24 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x24 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x24 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x24 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x24 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x28 "TAC5_L,Transfer Attribute Control n Low" bitfld.long 0x28 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x28 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x28 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x28 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x28 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x28 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x28 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x28 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x2C "TAC5_H,Transfer Attribute Control n High" bitfld.long 0x2C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x2C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x2C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x2C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x2C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x2C 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x30 "TAC6_L,Transfer Attribute Control n Low" bitfld.long 0x30 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x30 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x30 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x30 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x30 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x30 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x30 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x30 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x34 "TAC6_H,Transfer Attribute Control n High" bitfld.long 0x34 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x34 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x34 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x34 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x34 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x34 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x38 "TAC7_L,Transfer Attribute Control n Low" bitfld.long 0x38 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x38 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x38 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x38 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x38 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x38 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x38 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x38 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x3C "TAC7_H,Transfer Attribute Control n High" bitfld.long 0x3C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x3C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x3C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x3C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x3C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x3C 0.--15. 1. "DTC,Data transfer Count per command entry" group.long 0xC0++0x3 line.long 0x0 "MONITOR_SLAVE_SELECT,Monitor slave select" bitfld.long 0x0 31. "MONITOR_SPI_CONNECTED,Monitor SPI module connected to one of the slave select" "0: Monitor SPI is not connected,1: Monitor SPI connected" newline hexmask.long.byte 0x0 0.--7. 1. "MONITOR_SPI_SLAVE_SELECT,Slave select number on which Monitor SPI module is connected" tree.end tree "SPIQ_5_Q0" base ad:0x7203C100 group.long 0x0++0x3 line.long 0x0 "Q0_SETUP,Queue n setup" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "?,?,?,?,?,?,?,7: lowest to highest priority" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline hexmask.long.byte 0x0 8.--12. 1. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline hexmask.long.byte 0x0 0.--4. 1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" rgroup.long 0x4++0x3 line.long 0x0 "Q0_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q0_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q0_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q0_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q0_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q0_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q0_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline hexmask.long.byte 0x0 8.--12. 1. "TXFIFO_WR_PTR,TxFIFO write pointer" newline hexmask.long.byte 0x0 0.--4. 1. "TXFIFO_RD_PTR,TxFIFO read pointer" line.long 0x4 "Q0_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline hexmask.long.byte 0x4 8.--12. 1. "RXFIFO_WR_PTR,RxFIFO write pointer" newline hexmask.long.byte 0x4 0.--4. 1. "RXFIFO_RD_PTR,RxFIFO read pointer" group.long 0x8C++0x3 line.long 0x0 "Q0_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q0_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q0_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q0_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q0_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q0_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q0_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q0_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q0_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q0_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q0_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_5_Q1" base ad:0x7203C200 group.long 0x0++0x3 line.long 0x0 "Q1_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q1_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q1_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q1_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q1_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q1_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q1_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q1_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q1_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q1_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q1_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q1_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q1_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q1_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q1_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q1_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q1_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q1_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q1_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q1_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q1_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_5_Q2" base ad:0x7203C300 group.long 0x0++0x3 line.long 0x0 "Q2_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q2_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q2_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q2_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q2_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q2_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q2_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q2_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q2_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q2_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q2_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q2_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q2_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q2_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q2_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q2_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q2_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q2_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q2_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q2_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q2_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_5_Q3" base ad:0x7203C400 group.long 0x0++0x3 line.long 0x0 "Q3_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q3_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q3_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q3_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q3_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q3_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q3_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q3_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q3_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q3_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q3_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q3_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q3_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q3_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q3_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q3_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q3_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q3_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q3_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q3_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q3_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_5_Q4" base ad:0x7203C500 group.long 0x0++0x3 line.long 0x0 "Q4_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q4_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q4_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q4_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q4_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q4_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q4_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q4_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q4_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q4_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q4_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q4_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q4_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q4_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q4_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q4_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q4_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q4_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q4_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q4_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q4_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_5_Q5" base ad:0x7203C600 group.long 0x0++0x3 line.long 0x0 "Q5_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q5_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q5_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q5_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q5_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q5_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q5_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q5_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q5_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q5_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q5_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q5_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q5_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q5_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q5_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q5_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q5_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q5_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q5_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q5_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q5_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_5_Q6" base ad:0x7203C700 group.long 0x0++0x3 line.long 0x0 "Q6_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q6_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q6_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q6_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q6_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q6_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q6_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q6_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q6_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline bitfld.long 0x0 8.--9. "TXFIFO_WR_PTR,TxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x0 0.--1. "TXFIFO_RD_PTR,TxFIFO read pointer" "0,1,2,3" line.long 0x4 "Q6_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline bitfld.long 0x4 8.--9. "RXFIFO_WR_PTR,RxFIFO write pointer" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RXFIFO_RD_PTR,RxFIFO read pointer" "0,1,2,3" group.long 0x8C++0x3 line.long 0x0 "Q6_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q6_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q6_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q6_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q6_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q6_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q6_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q6_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q6_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q6_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q6_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree "SPIQ_5_Q7" base ad:0x7203C800 group.long 0x0++0x3 line.long 0x0 "Q7_SETUP,Queue n setup register" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "0: to 7 => lowest to highest priority,?,?,?,?,?,?,?" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline bitfld.long 0x0 8.--9. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" "0,1,2,3" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline bitfld.long 0x0 0.--1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" "0,1,2,3" rgroup.long 0x4++0x3 line.long 0x0 "Q7_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q7_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q7_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q7_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q7_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q7_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q7_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q7_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline hexmask.long.byte 0x0 8.--15. 1. "TXFIFO_WR_PTR,TxFIFO write pointer" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_RD_PTR,TxFIFO read pointer" line.long 0x4 "Q7_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline hexmask.long.byte 0x4 8.--15. 1. "RXFIFO_WR_PTR,RxFIFO write pointer" newline hexmask.long.byte 0x4 0.--7. 1. "RXFIFO_RD_PTR,RxFIFO read pointer" group.long 0x8C++0x3 line.long 0x0 "Q7_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q7_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q7_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q7_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q7_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q7_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q7_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q7_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q7_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q7_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q7_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree.end tree "SPIQ_6" tree "SPIQ_6_GLBL" base ad:0x70E7C000 group.long 0x0++0x3 line.long 0x0 "MCR,Module configuration register" bitfld.long 0x0 31. "MSTR,Selects SPI functional mode" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK clock enable" "0: SCK is non continuous. It is generated only..,1: SCK is continuous. It is generated throughout.." newline hexmask.long.byte 0x0 16.--23. 1. "PCS_DEFAULT_LEVEL,Selects PCS inactive level" newline bitfld.long 0x0 15. "SAFE_SPI_MODE,Selects if SafeSPI mode is enabled or not" "0: Module works in Normal SPI Mode,1: Module works in Safe SPI Mode" newline bitfld.long 0x0 9.--10. "SAMPLE_POINT,SAMPLE_POINT field controls when the SPI master samples SIN and drives SOUT in Modified Transfer Format." "0: 00,1: 00,2: Modified SPI Transfer,?" newline bitfld.long 0x0 8. "MTFE,Modified Timing Format Enable. The MTFE bit enables a modified transfer format to be used." "0: Modified SPI transfer format disabled,1: Modified SPI transfer format enabled" newline bitfld.long 0x0 6. "DEBUG_FREEZE,Freeze during debug mode" "0: Do not stop serial transfer,1: Stop serial transfer" newline bitfld.long 0x0 4. "LOOPBACK_EN,Loopback enable" "0: Loopback disabled,1: Internal loopback enabled" newline bitfld.long 0x0 2. "CRC_ERR_STOP,CRC Error Stop Enable" "0: Continue transfer after CRC error in received..,1: Stop transfer after CRC error in received SPI.." newline bitfld.long 0x0 1. "PAR_ERR_STOP,Parity Error Stop." "0: SPI frames transmission continue.,1: SPI frames transmission stop." newline bitfld.long 0x0 0. "MODULE_EN,Enable Module" "0: Module is disabled,1: Module is enabled)" rgroup.long 0x4++0x3 line.long 0x0 "HW_CONFIG_STATUS,HW configuration status" bitfld.long 0x0 16. "AUXFIFO_PRESENT_IN_Q0,Specifies if AuxFifo is instantiated for Queue0" "0: AuxFifo is not present in Queue[0],1: AuxFifo is present in Queue[0]" newline hexmask.long.byte 0x0 8.--11. 1. "NUM_TAC,This specifies the number of Transfer Attribute Control (TAC) registers instantiated in design" newline hexmask.long.byte 0x0 0.--3. 1. "NUM_QUEUES,This specifies the number of HW Queues instantiated in design" rgroup.long 0x10++0x3 line.long 0x0 "GLOBAL_STATUS,GLOBAL Status" hexmask.long.byte 0x0 16.--23. 1. "QUEUE_NUM,Specify the queue number in case of SPIQ_STATUS as: EOS ERROR FLUSH_IN_PROGRESS" newline bitfld.long 0x0 0.--2. "SPIQ_STATUS,SPIQ status" "0: IDLE => all queues are idle.,1: RUNNING => SPI transfer ongoing,2: WAIT_TRIGGER => no SPI transfer ongoing all..,3: SUSPENDED => all queues in suspended state..,?,?,?,7: ERROR => at least one queue is reporting ERROR.." group.long 0x20++0x3 line.long 0x0 "GLOBAL_IRQ_CTRL,GLOBAL interrupt control" bitfld.long 0x0 16. "ERR_IRQ_EN,Interrupt enable for Error interrupts for individual Queues" "0,1" newline bitfld.long 0x0 0. "STATUS_IRQ_EN,Interrupt enable for Status interrupts for individual Queues" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "GLOBAL_IRQ_STATUS,GLOBAL interrupt status" bitfld.long 0x0 16. "ERR_IRQ_STATUS,Error interrupts status from individual Queues" "0,1" newline bitfld.long 0x0 0. "STATUS_IRQ,Status interrupts from individual Queues" "0,1" group.long 0x40++0x3F line.long 0x0 "TAC0_L,Transfer Attribute Control n Low" bitfld.long 0x0 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x0 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x0 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x0 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x0 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x0 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x0 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x0 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x4 "TAC0_H,Transfer Attribute Control n High" bitfld.long 0x4 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x4 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x4 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x4 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x4 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x8 "TAC1_L,Transfer Attribute Control n Low" bitfld.long 0x8 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x8 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x8 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x8 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x8 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x8 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x8 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x8 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0xC "TAC1_H,Transfer Attribute Control n High" bitfld.long 0xC 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0xC 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0xC 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0xC 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0xC 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x10 "TAC2_L,Transfer Attribute Control n Low" bitfld.long 0x10 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x10 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x10 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x10 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x10 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x10 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x10 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x10 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x14 "TAC2_H,Transfer Attribute Control n High" bitfld.long 0x14 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x14 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x14 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x14 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x14 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x18 "TAC3_L,Transfer Attribute Control n Low" bitfld.long 0x18 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x18 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x18 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x18 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x18 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x18 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x18 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x18 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x1C "TAC3_H,Transfer Attribute Control n High" bitfld.long 0x1C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x1C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x1C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x1C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x1C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x1C 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x20 "TAC4_L,Transfer Attribute Control n Low" bitfld.long 0x20 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x20 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x20 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x20 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x20 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x20 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x20 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x20 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x24 "TAC4_H,Transfer Attribute Control n High" bitfld.long 0x24 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x24 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x24 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x24 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x24 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x24 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x28 "TAC5_L,Transfer Attribute Control n Low" bitfld.long 0x28 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x28 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x28 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x28 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x28 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x28 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x28 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x28 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x2C "TAC5_H,Transfer Attribute Control n High" bitfld.long 0x2C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x2C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x2C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x2C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x2C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x2C 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x30 "TAC6_L,Transfer Attribute Control n Low" bitfld.long 0x30 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x30 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x30 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x30 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x30 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x30 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x30 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x30 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x34 "TAC6_H,Transfer Attribute Control n High" bitfld.long 0x34 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x34 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x34 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x34 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x34 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x34 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x38 "TAC7_L,Transfer Attribute Control n Low" bitfld.long 0x38 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x38 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x38 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x38 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x38 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x38 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x38 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x38 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x3C "TAC7_H,Transfer Attribute Control n High" bitfld.long 0x3C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x3C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x3C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x3C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x3C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x3C 0.--15. 1. "DTC,Data transfer Count per command entry" group.long 0xC0++0x3 line.long 0x0 "MONITOR_SLAVE_SELECT,Monitor slave select" bitfld.long 0x0 31. "MONITOR_SPI_CONNECTED,Monitor SPI module connected to one of the slave select" "0: Monitor SPI is not connected,1: Monitor SPI connected" newline hexmask.long.byte 0x0 0.--7. 1. "MONITOR_SPI_SLAVE_SELECT,Slave select number on which Monitor SPI module is connected" tree.end tree "SPIQ_6_Q0" base ad:0x70E7C100 group.long 0x0++0x3 line.long 0x0 "Q0_SETUP,Queue n setup" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "?,?,?,?,?,?,?,7: lowest to highest priority" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline hexmask.long.byte 0x0 8.--11. 1. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline hexmask.long.byte 0x0 0.--3. 1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" rgroup.long 0x4++0x3 line.long 0x0 "Q0_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q0_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q0_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q0_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q0_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q0_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q0_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline hexmask.long.byte 0x0 8.--11. 1. "TXFIFO_WR_PTR,TxFIFO write pointer" newline hexmask.long.byte 0x0 0.--3. 1. "TXFIFO_RD_PTR,TxFIFO read pointer" line.long 0x4 "Q0_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline hexmask.long.byte 0x4 8.--11. 1. "RXFIFO_WR_PTR,RxFIFO write pointer" newline hexmask.long.byte 0x4 0.--3. 1. "RXFIFO_RD_PTR,RxFIFO read pointer" group.long 0x8C++0x3 line.long 0x0 "Q0_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q0_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q0_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q0_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q0_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q0_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q0_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q0_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q0_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q0_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q0_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree.end tree "SPIQ_7" tree "SPIQ_7_GLBL" base ad:0x71A44000 group.long 0x0++0x3 line.long 0x0 "MCR,Module configuration register" bitfld.long 0x0 31. "MSTR,Selects SPI functional mode" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK clock enable" "0: SCK is non continuous. It is generated only..,1: SCK is continuous. It is generated throughout.." newline hexmask.long.byte 0x0 16.--23. 1. "PCS_DEFAULT_LEVEL,Selects PCS inactive level" newline bitfld.long 0x0 15. "SAFE_SPI_MODE,Selects if SafeSPI mode is enabled or not" "0: Module works in Normal SPI Mode,1: Module works in Safe SPI Mode" newline bitfld.long 0x0 9.--10. "SAMPLE_POINT,SAMPLE_POINT field controls when the SPI master samples SIN and drives SOUT in Modified Transfer Format." "0: 00,1: 00,2: Modified SPI Transfer,?" newline bitfld.long 0x0 8. "MTFE,Modified Timing Format Enable. The MTFE bit enables a modified transfer format to be used." "0: Modified SPI transfer format disabled,1: Modified SPI transfer format enabled" newline bitfld.long 0x0 6. "DEBUG_FREEZE,Freeze during debug mode" "0: Do not stop serial transfer,1: Stop serial transfer" newline bitfld.long 0x0 4. "LOOPBACK_EN,Loopback enable" "0: Loopback disabled,1: Internal loopback enabled" newline bitfld.long 0x0 2. "CRC_ERR_STOP,CRC Error Stop Enable" "0: Continue transfer after CRC error in received..,1: Stop transfer after CRC error in received SPI.." newline bitfld.long 0x0 1. "PAR_ERR_STOP,Parity Error Stop." "0: SPI frames transmission continue.,1: SPI frames transmission stop." newline bitfld.long 0x0 0. "MODULE_EN,Enable Module" "0: Module is disabled,1: Module is enabled)" rgroup.long 0x4++0x3 line.long 0x0 "HW_CONFIG_STATUS,HW configuration status" bitfld.long 0x0 16. "AUXFIFO_PRESENT_IN_Q0,Specifies if AuxFifo is instantiated for Queue0" "0: AuxFifo is not present in Queue[0],1: AuxFifo is present in Queue[0]" newline hexmask.long.byte 0x0 8.--11. 1. "NUM_TAC,This specifies the number of Transfer Attribute Control (TAC) registers instantiated in design" newline hexmask.long.byte 0x0 0.--3. 1. "NUM_QUEUES,This specifies the number of HW Queues instantiated in design" rgroup.long 0x10++0x3 line.long 0x0 "GLOBAL_STATUS,GLOBAL Status" hexmask.long.byte 0x0 16.--23. 1. "QUEUE_NUM,Specify the queue number in case of SPIQ_STATUS as: EOS ERROR FLUSH_IN_PROGRESS" newline bitfld.long 0x0 0.--2. "SPIQ_STATUS,SPIQ status" "0: IDLE => all queues are idle.,1: RUNNING => SPI transfer ongoing,2: WAIT_TRIGGER => no SPI transfer ongoing all..,3: SUSPENDED => all queues in suspended state..,?,?,?,7: ERROR => at least one queue is reporting ERROR.." group.long 0x20++0x3 line.long 0x0 "GLOBAL_IRQ_CTRL,GLOBAL interrupt control" bitfld.long 0x0 16. "ERR_IRQ_EN,Interrupt enable for Error interrupts for individual Queues" "0,1" newline bitfld.long 0x0 0. "STATUS_IRQ_EN,Interrupt enable for Status interrupts for individual Queues" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "GLOBAL_IRQ_STATUS,GLOBAL interrupt status" bitfld.long 0x0 16. "ERR_IRQ_STATUS,Error interrupts status from individual Queues" "0,1" newline bitfld.long 0x0 0. "STATUS_IRQ,Status interrupts from individual Queues" "0,1" group.long 0x40++0x3F line.long 0x0 "TAC0_L,Transfer Attribute Control n Low" bitfld.long 0x0 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x0 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x0 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x0 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x0 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x0 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x0 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x0 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x4 "TAC0_H,Transfer Attribute Control n High" bitfld.long 0x4 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x4 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x4 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x4 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x4 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x8 "TAC1_L,Transfer Attribute Control n Low" bitfld.long 0x8 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x8 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x8 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x8 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x8 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x8 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x8 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x8 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0xC "TAC1_H,Transfer Attribute Control n High" bitfld.long 0xC 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0xC 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0xC 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0xC 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0xC 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x10 "TAC2_L,Transfer Attribute Control n Low" bitfld.long 0x10 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x10 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x10 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x10 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x10 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x10 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x10 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x10 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x14 "TAC2_H,Transfer Attribute Control n High" bitfld.long 0x14 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x14 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x14 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x14 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x14 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x18 "TAC3_L,Transfer Attribute Control n Low" bitfld.long 0x18 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x18 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x18 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x18 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x18 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x18 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x18 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x18 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x1C "TAC3_H,Transfer Attribute Control n High" bitfld.long 0x1C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x1C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x1C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x1C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x1C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x1C 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x20 "TAC4_L,Transfer Attribute Control n Low" bitfld.long 0x20 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x20 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x20 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x20 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x20 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x20 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x20 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x20 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x24 "TAC4_H,Transfer Attribute Control n High" bitfld.long 0x24 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x24 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x24 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x24 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x24 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x24 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x28 "TAC5_L,Transfer Attribute Control n Low" bitfld.long 0x28 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x28 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x28 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x28 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x28 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x28 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x28 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x28 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x2C "TAC5_H,Transfer Attribute Control n High" bitfld.long 0x2C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x2C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x2C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x2C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x2C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x2C 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x30 "TAC6_L,Transfer Attribute Control n Low" bitfld.long 0x30 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x30 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x30 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x30 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x30 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x30 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x30 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x30 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x34 "TAC6_H,Transfer Attribute Control n High" bitfld.long 0x34 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x34 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x34 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x34 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x34 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x34 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x38 "TAC7_L,Transfer Attribute Control n Low" bitfld.long 0x38 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x38 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x38 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x38 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x38 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x38 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x38 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x38 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x3C "TAC7_H,Transfer Attribute Control n High" bitfld.long 0x3C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x3C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x3C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x3C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x3C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x3C 0.--15. 1. "DTC,Data transfer Count per command entry" group.long 0xC0++0x3 line.long 0x0 "MONITOR_SLAVE_SELECT,Monitor slave select" bitfld.long 0x0 31. "MONITOR_SPI_CONNECTED,Monitor SPI module connected to one of the slave select" "0: Monitor SPI is not connected,1: Monitor SPI connected" newline hexmask.long.byte 0x0 0.--7. 1. "MONITOR_SPI_SLAVE_SELECT,Slave select number on which Monitor SPI module is connected" tree.end tree "SPIQ_7_Q0" base ad:0x71A44100 group.long 0x0++0x3 line.long 0x0 "Q0_SETUP,Queue n setup" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "?,?,?,?,?,?,?,7: lowest to highest priority" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline hexmask.long.byte 0x0 8.--11. 1. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline hexmask.long.byte 0x0 0.--3. 1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" rgroup.long 0x4++0x3 line.long 0x0 "Q0_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q0_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q0_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q0_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q0_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q0_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q0_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline hexmask.long.byte 0x0 8.--11. 1. "TXFIFO_WR_PTR,TxFIFO write pointer" newline hexmask.long.byte 0x0 0.--3. 1. "TXFIFO_RD_PTR,TxFIFO read pointer" line.long 0x4 "Q0_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline hexmask.long.byte 0x4 8.--11. 1. "RXFIFO_WR_PTR,RxFIFO write pointer" newline hexmask.long.byte 0x4 0.--3. 1. "RXFIFO_RD_PTR,RxFIFO read pointer" group.long 0x8C++0x3 line.long 0x0 "Q0_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q0_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q0_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q0_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q0_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q0_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q0_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q0_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q0_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q0_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q0_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree.end tree "SPIQ_8" tree "SPIQ_8_GLBL" base ad:0x70E80000 group.long 0x0++0x3 line.long 0x0 "MCR,Module configuration register" bitfld.long 0x0 31. "MSTR,Selects SPI functional mode" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK clock enable" "0: SCK is non continuous. It is generated only..,1: SCK is continuous. It is generated throughout.." newline hexmask.long.byte 0x0 16.--23. 1. "PCS_DEFAULT_LEVEL,Selects PCS inactive level" newline bitfld.long 0x0 15. "SAFE_SPI_MODE,Selects if SafeSPI mode is enabled or not" "0: Module works in Normal SPI Mode,1: Module works in Safe SPI Mode" newline bitfld.long 0x0 9.--10. "SAMPLE_POINT,SAMPLE_POINT field controls when the SPI master samples SIN and drives SOUT in Modified Transfer Format." "0: 00,1: 00,2: Modified SPI Transfer,?" newline bitfld.long 0x0 8. "MTFE,Modified Timing Format Enable. The MTFE bit enables a modified transfer format to be used." "0: Modified SPI transfer format disabled,1: Modified SPI transfer format enabled" newline bitfld.long 0x0 6. "DEBUG_FREEZE,Freeze during debug mode" "0: Do not stop serial transfer,1: Stop serial transfer" newline bitfld.long 0x0 4. "LOOPBACK_EN,Loopback enable" "0: Loopback disabled,1: Internal loopback enabled" newline bitfld.long 0x0 2. "CRC_ERR_STOP,CRC Error Stop Enable" "0: Continue transfer after CRC error in received..,1: Stop transfer after CRC error in received SPI.." newline bitfld.long 0x0 1. "PAR_ERR_STOP,Parity Error Stop." "0: SPI frames transmission continue.,1: SPI frames transmission stop." newline bitfld.long 0x0 0. "MODULE_EN,Enable Module" "0: Module is disabled,1: Module is enabled)" rgroup.long 0x4++0x3 line.long 0x0 "HW_CONFIG_STATUS,HW configuration status" bitfld.long 0x0 16. "AUXFIFO_PRESENT_IN_Q0,Specifies if AuxFifo is instantiated for Queue0" "0: AuxFifo is not present in Queue[0],1: AuxFifo is present in Queue[0]" newline hexmask.long.byte 0x0 8.--11. 1. "NUM_TAC,This specifies the number of Transfer Attribute Control (TAC) registers instantiated in design" newline hexmask.long.byte 0x0 0.--3. 1. "NUM_QUEUES,This specifies the number of HW Queues instantiated in design" rgroup.long 0x10++0x3 line.long 0x0 "GLOBAL_STATUS,GLOBAL Status" hexmask.long.byte 0x0 16.--23. 1. "QUEUE_NUM,Specify the queue number in case of SPIQ_STATUS as: EOS ERROR FLUSH_IN_PROGRESS" newline bitfld.long 0x0 0.--2. "SPIQ_STATUS,SPIQ status" "0: IDLE => all queues are idle.,1: RUNNING => SPI transfer ongoing,2: WAIT_TRIGGER => no SPI transfer ongoing all..,3: SUSPENDED => all queues in suspended state..,?,?,?,7: ERROR => at least one queue is reporting ERROR.." group.long 0x20++0x3 line.long 0x0 "GLOBAL_IRQ_CTRL,GLOBAL interrupt control" bitfld.long 0x0 16. "ERR_IRQ_EN,Interrupt enable for Error interrupts for individual Queues" "0,1" newline bitfld.long 0x0 0. "STATUS_IRQ_EN,Interrupt enable for Status interrupts for individual Queues" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "GLOBAL_IRQ_STATUS,GLOBAL interrupt status" bitfld.long 0x0 16. "ERR_IRQ_STATUS,Error interrupts status from individual Queues" "0,1" newline bitfld.long 0x0 0. "STATUS_IRQ,Status interrupts from individual Queues" "0,1" group.long 0x40++0x3F line.long 0x0 "TAC0_L,Transfer Attribute Control n Low" bitfld.long 0x0 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x0 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x0 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x0 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x0 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x0 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x0 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x0 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x4 "TAC0_H,Transfer Attribute Control n High" bitfld.long 0x4 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x4 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x4 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x4 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x4 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x8 "TAC1_L,Transfer Attribute Control n Low" bitfld.long 0x8 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x8 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x8 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x8 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x8 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x8 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x8 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x8 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0xC "TAC1_H,Transfer Attribute Control n High" bitfld.long 0xC 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0xC 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0xC 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0xC 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0xC 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x10 "TAC2_L,Transfer Attribute Control n Low" bitfld.long 0x10 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x10 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x10 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x10 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x10 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x10 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x10 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x10 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x14 "TAC2_H,Transfer Attribute Control n High" bitfld.long 0x14 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x14 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x14 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x14 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x14 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x18 "TAC3_L,Transfer Attribute Control n Low" bitfld.long 0x18 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x18 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x18 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x18 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x18 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x18 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x18 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x18 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x1C "TAC3_H,Transfer Attribute Control n High" bitfld.long 0x1C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x1C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x1C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x1C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x1C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x1C 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x20 "TAC4_L,Transfer Attribute Control n Low" bitfld.long 0x20 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x20 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x20 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x20 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x20 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x20 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x20 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x20 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x24 "TAC4_H,Transfer Attribute Control n High" bitfld.long 0x24 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x24 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x24 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x24 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x24 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x24 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x28 "TAC5_L,Transfer Attribute Control n Low" bitfld.long 0x28 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x28 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x28 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x28 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x28 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x28 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x28 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x28 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x2C "TAC5_H,Transfer Attribute Control n High" bitfld.long 0x2C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x2C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x2C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x2C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x2C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x2C 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x30 "TAC6_L,Transfer Attribute Control n Low" bitfld.long 0x30 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x30 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x30 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x30 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x30 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x30 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x30 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x30 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x34 "TAC6_H,Transfer Attribute Control n High" bitfld.long 0x34 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x34 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x34 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x34 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x34 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x34 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x38 "TAC7_L,Transfer Attribute Control n Low" bitfld.long 0x38 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x38 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x38 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x38 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x38 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x38 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x38 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x38 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x3C "TAC7_H,Transfer Attribute Control n High" bitfld.long 0x3C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x3C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x3C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x3C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x3C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x3C 0.--15. 1. "DTC,Data transfer Count per command entry" group.long 0xC0++0x3 line.long 0x0 "MONITOR_SLAVE_SELECT,Monitor slave select" bitfld.long 0x0 31. "MONITOR_SPI_CONNECTED,Monitor SPI module connected to one of the slave select" "0: Monitor SPI is not connected,1: Monitor SPI connected" newline hexmask.long.byte 0x0 0.--7. 1. "MONITOR_SPI_SLAVE_SELECT,Slave select number on which Monitor SPI module is connected" tree.end tree "SPIQ_8_Q0" base ad:0x70E80100 group.long 0x0++0x3 line.long 0x0 "Q0_SETUP,Queue n setup" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "?,?,?,?,?,?,?,7: lowest to highest priority" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline hexmask.long.byte 0x0 8.--11. 1. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline hexmask.long.byte 0x0 0.--3. 1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" rgroup.long 0x4++0x3 line.long 0x0 "Q0_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q0_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q0_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q0_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q0_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q0_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q0_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline hexmask.long.byte 0x0 8.--11. 1. "TXFIFO_WR_PTR,TxFIFO write pointer" newline hexmask.long.byte 0x0 0.--3. 1. "TXFIFO_RD_PTR,TxFIFO read pointer" line.long 0x4 "Q0_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline hexmask.long.byte 0x4 8.--11. 1. "RXFIFO_WR_PTR,RxFIFO write pointer" newline hexmask.long.byte 0x4 0.--3. 1. "RXFIFO_RD_PTR,RxFIFO read pointer" group.long 0x8C++0x3 line.long 0x0 "Q0_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q0_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q0_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q0_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q0_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q0_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q0_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q0_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q0_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q0_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q0_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree.end tree "SPIQ_9" tree "SPIQ_9_GLBL" base ad:0x71A4C000 group.long 0x0++0x3 line.long 0x0 "MCR,Module configuration register" bitfld.long 0x0 31. "MSTR,Selects SPI functional mode" "0: Slave Mode,1: Master Mode" newline bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK clock enable" "0: SCK is non continuous. It is generated only..,1: SCK is continuous. It is generated throughout.." newline hexmask.long.byte 0x0 16.--23. 1. "PCS_DEFAULT_LEVEL,Selects PCS inactive level" newline bitfld.long 0x0 15. "SAFE_SPI_MODE,Selects if SafeSPI mode is enabled or not" "0: Module works in Normal SPI Mode,1: Module works in Safe SPI Mode" newline bitfld.long 0x0 9.--10. "SAMPLE_POINT,SAMPLE_POINT field controls when the SPI master samples SIN and drives SOUT in Modified Transfer Format." "0: 00,1: 00,2: Modified SPI Transfer,?" newline bitfld.long 0x0 8. "MTFE,Modified Timing Format Enable. The MTFE bit enables a modified transfer format to be used." "0: Modified SPI transfer format disabled,1: Modified SPI transfer format enabled" newline bitfld.long 0x0 6. "DEBUG_FREEZE,Freeze during debug mode" "0: Do not stop serial transfer,1: Stop serial transfer" newline bitfld.long 0x0 4. "LOOPBACK_EN,Loopback enable" "0: Loopback disabled,1: Internal loopback enabled" newline bitfld.long 0x0 2. "CRC_ERR_STOP,CRC Error Stop Enable" "0: Continue transfer after CRC error in received..,1: Stop transfer after CRC error in received SPI.." newline bitfld.long 0x0 1. "PAR_ERR_STOP,Parity Error Stop." "0: SPI frames transmission continue.,1: SPI frames transmission stop." newline bitfld.long 0x0 0. "MODULE_EN,Enable Module" "0: Module is disabled,1: Module is enabled)" rgroup.long 0x4++0x3 line.long 0x0 "HW_CONFIG_STATUS,HW configuration status" bitfld.long 0x0 16. "AUXFIFO_PRESENT_IN_Q0,Specifies if AuxFifo is instantiated for Queue0" "0: AuxFifo is not present in Queue[0],1: AuxFifo is present in Queue[0]" newline hexmask.long.byte 0x0 8.--11. 1. "NUM_TAC,This specifies the number of Transfer Attribute Control (TAC) registers instantiated in design" newline hexmask.long.byte 0x0 0.--3. 1. "NUM_QUEUES,This specifies the number of HW Queues instantiated in design" rgroup.long 0x10++0x3 line.long 0x0 "GLOBAL_STATUS,GLOBAL Status" hexmask.long.byte 0x0 16.--23. 1. "QUEUE_NUM,Specify the queue number in case of SPIQ_STATUS as: EOS ERROR FLUSH_IN_PROGRESS" newline bitfld.long 0x0 0.--2. "SPIQ_STATUS,SPIQ status" "0: IDLE => all queues are idle.,1: RUNNING => SPI transfer ongoing,2: WAIT_TRIGGER => no SPI transfer ongoing all..,3: SUSPENDED => all queues in suspended state..,?,?,?,7: ERROR => at least one queue is reporting ERROR.." group.long 0x20++0x3 line.long 0x0 "GLOBAL_IRQ_CTRL,GLOBAL interrupt control" bitfld.long 0x0 16. "ERR_IRQ_EN,Interrupt enable for Error interrupts for individual Queues" "0,1" newline bitfld.long 0x0 0. "STATUS_IRQ_EN,Interrupt enable for Status interrupts for individual Queues" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "GLOBAL_IRQ_STATUS,GLOBAL interrupt status" bitfld.long 0x0 16. "ERR_IRQ_STATUS,Error interrupts status from individual Queues" "0,1" newline bitfld.long 0x0 0. "STATUS_IRQ,Status interrupts from individual Queues" "0,1" group.long 0x40++0x3F line.long 0x0 "TAC0_L,Transfer Attribute Control n Low" bitfld.long 0x0 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x0 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x0 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x0 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x0 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x0 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x0 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x0 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x0 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x4 "TAC0_H,Transfer Attribute Control n High" bitfld.long 0x4 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x4 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x4 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x4 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x4 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x8 "TAC1_L,Transfer Attribute Control n Low" bitfld.long 0x8 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x8 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x8 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x8 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x8 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x8 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x8 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x8 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x8 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0xC "TAC1_H,Transfer Attribute Control n High" bitfld.long 0xC 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0xC 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0xC 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0xC 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0xC 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x10 "TAC2_L,Transfer Attribute Control n Low" bitfld.long 0x10 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x10 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x10 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x10 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x10 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x10 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x10 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x10 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x10 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x14 "TAC2_H,Transfer Attribute Control n High" bitfld.long 0x14 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x14 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x14 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x14 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x14 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x18 "TAC3_L,Transfer Attribute Control n Low" bitfld.long 0x18 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x18 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x18 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x18 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x18 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x18 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x18 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x18 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x18 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x1C "TAC3_H,Transfer Attribute Control n High" bitfld.long 0x1C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x1C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x1C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x1C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x1C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x1C 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x20 "TAC4_L,Transfer Attribute Control n Low" bitfld.long 0x20 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x20 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x20 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x20 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x20 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x20 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x20 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x20 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x20 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x24 "TAC4_H,Transfer Attribute Control n High" bitfld.long 0x24 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x24 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x24 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x24 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x24 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x24 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x28 "TAC5_L,Transfer Attribute Control n Low" bitfld.long 0x28 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x28 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x28 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x28 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x28 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x28 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x28 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x28 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x28 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x2C "TAC5_H,Transfer Attribute Control n High" bitfld.long 0x2C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x2C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x2C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x2C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x2C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x2C 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x30 "TAC6_L,Transfer Attribute Control n Low" bitfld.long 0x30 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x30 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x30 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x30 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x30 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x30 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x30 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x30 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x30 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x34 "TAC6_H,Transfer Attribute Control n High" bitfld.long 0x34 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x34 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x34 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x34 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x34 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x34 0.--15. 1. "DTC,Data transfer Count per command entry" line.long 0x38 "TAC7_L,Transfer Attribute Control n Low" bitfld.long 0x38 31. "DBR,Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK)." "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." newline bitfld.long 0x38 28.--29. "PBR,Baud Rate Prescaler. Selects the prescaler value for the baud rate. The baud rate is the frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection takes place." "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7" newline hexmask.long.byte 0x38 24.--27. 1. "BR,Baud Rate Scaler. Selects the scaler value for the baud rate. The prescaled protocol clock is divided by the Baud Rate Scaler to generate the frequency of the SCK. The baud rate is calculated by:" newline bitfld.long 0x38 22.--23. "PLD,Leading Delay Prescaler. Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 20.--21. "PTD,Trailing Delay Prescaler. Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS" "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 18.--19. "PNFD,Next Frame Delay Prescaler. Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline bitfld.long 0x38 16.--17. "PIWD,Inter Word Delay Prescaler. Selects the prescaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." "0: Prescaler value is 1,1: Prescaler value is 3,2: Prescaler value is 5,3: Prescaler value is 7" newline hexmask.long.byte 0x38 12.--15. 1. "LD,Leading Delay Scaler. Selects the scaler value for the delay between assertion of PCS and the first edge of the SCK. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x38 8.--11. 1. "TD,Trailing Delay Scaler. Selects the scaler value for the delay between the last SCK period and the negation of PCS. The delay is a multiple of the protocol clock period calculated by:" newline hexmask.long.byte 0x38 4.--7. 1. "NFD,Next Frame Delay Scaler. Selects the scaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame." newline hexmask.long.byte 0x38 0.--3. 1. "IWD,Inter Word Delay Scaler. Selects the scaler value for the delay between the last bit transfer of a word and first bit transfer of next word in continuous PCS select mode." line.long 0x3C "TAC7_H,Transfer Attribute Control n High" bitfld.long 0x3C 31. "CPOL,Clock Polarity." "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x3C 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x3C 29. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." newline hexmask.long.byte 0x3C 24.--28. 1. "SCK_DISABLE_CYCLES,Minimum number of protocol clocks delay between SCK polarity setup and PCS assertion" newline hexmask.long.byte 0x3C 16.--20. 1. "FMSZ,Frame Size" newline hexmask.long.word 0x3C 0.--15. 1. "DTC,Data transfer Count per command entry" group.long 0xC0++0x3 line.long 0x0 "MONITOR_SLAVE_SELECT,Monitor slave select" bitfld.long 0x0 31. "MONITOR_SPI_CONNECTED,Monitor SPI module connected to one of the slave select" "0: Monitor SPI is not connected,1: Monitor SPI connected" newline hexmask.long.byte 0x0 0.--7. 1. "MONITOR_SPI_SLAVE_SELECT,Slave select number on which Monitor SPI module is connected" tree.end tree "SPIQ_9_Q0" base ad:0x71A4C100 group.long 0x0++0x3 line.long 0x0 "Q0_SETUP,Queue n setup" bitfld.long 0x0 29.--31. "PRIORITY,Specifies Queue Priority" "?,?,?,?,?,?,?,7: lowest to highest priority" newline bitfld.long 0x0 25. "TIMESTAMP_NOT_TRANSFER_CNT,RxStatus field stores Timestamp value or Transfer count value" "0: RxStatus entry in RxFIFO stores transfer count,1: RxStatus entry in RxFIFO stores timestamp value" newline bitfld.long 0x0 24. "RX_STATUS_EN,Enable Status entry in RxFIFO" "0: no status entry in RxFIFO,1: RxFIFO has a status entry for each received word" newline bitfld.long 0x0 21.--23. "HW_TRIG_OUT_WIDTH,Width of trigger out generated by queue" "0: 2 cycle wide pulse,1: 3 cycle wide pulse,2: 4 cycle wide pulse,?,?,?,6: 8 cycle wide pulse,7: Trigger out signal is toggled on each trigger.." newline bitfld.long 0x0 15. "RXDMA_EN,DMA request Enable for RxFIFO" "0: Do not generate a DMA request for RxFIFO,1: Generate a DMA request when number of valid.." newline bitfld.long 0x0 14. "RXFULL_STALL_EN,Stall transmission in case of RxFIFO Full" "0: Continue transmission even if RxFIFO is full,1: Stop transmission in case of RxFIFO Full condition" newline hexmask.long.byte 0x0 8.--11. 1. "RXFIFO_THRESHOLD,Threshold value for RxFIFO" newline bitfld.long 0x0 7. "TXDMA_EN,DMA request Enable for TxFIFO" "0: Do not generate a DMA request for TxFIFO,1: Generate a DMA request when number of free.." newline bitfld.long 0x0 6. "HW_TRIG_EDGE,Selects rising or falling edge of HW trigger input to trigger the command" "0: Rising edge of HW trigger input,1: Falling edge of HW trigger input" newline bitfld.long 0x0 5. "HW_TRIG_EN,Trigger mechanism for Queue" "0: SW Trigger,1: HW Trigger" newline hexmask.long.byte 0x0 0.--3. 1. "TXFIFO_THRESHOLD,Threshold value for TxFIFO" rgroup.long 0x4++0x3 line.long 0x0 "Q0_HW_CFG,Queue n HW configuration register" hexmask.long.byte 0x0 8.--13. 1. "RXFIFO_DEPTH,Depth of RxFIFO" newline hexmask.long.byte 0x0 0.--5. 1. "TXFIFO_DEPTH,Depth of TxFIFO" rgroup.long 0x10++0x3 line.long 0x0 "Q0_STATUS,Queue n status register" hexmask.long.word 0x0 16.--31. 1. "TRANSFER_COUNT,SPI Transfer Counter" newline bitfld.long 0x0 0.--2. "Q_STATUS,Status of the queue" "0: IDLE => queue FIFOs are empty no SPI transfers..,1: RUNNING => queue FIFOs not empty queue selected..,2: WAIT_TRIGGER => queue FIFOs not empty command..,3: SUSPENDED => queue sequence suspended due to..,4: UNDERFLOW => queue selected for transfer but no..,5: STALLED => queue sequence stalled due to RxFIFO..,?,?" group.long 0x14++0x3 line.long 0x0 "Q0_CTRL,Queue n control register" bitfld.long 0x0 1. "Q_FLUSH,Flush all FIFOs" "0: No effect,1: Reset FIFO pointers and queue status bits" newline bitfld.long 0x0 0. "Q_SW_TRIG,SW Trigger for the queue" "0: No effect,1: Initiate a SW trigger for the next command entry" group.long 0x20++0x7 line.long 0x0 "Q0_IRQ_CTRL,Queue n interrupt control register" bitfld.long 0x0 31. "PARITY_ERR_IRQ_EN,Parity Error Interrupt Enable Bit" "0: Disable parity error interrupt,1: Enable parity error interrupt" newline bitfld.long 0x0 30. "CRC_ERR_IRQ_EN,CRC Error Interrupt Enable Bit" "0: Disable CRC error interrupt,1: Enable CRC error interrupt" newline bitfld.long 0x0 29. "TRIG_OVERRUN_ERR_IRQ_EN,Trigger Overrun Error Interrupt Enable Bit" "0: Disable Trigger overrun error interrupt,1: Enable Trigger overrun error interrupt" newline bitfld.long 0x0 28. "COMMAND_ERR_IRQ_EN,Command Error Interrupt Enable Bit" "0: Disable Command error interrupt,1: Enable Command error interrupt" newline bitfld.long 0x0 25. "EOS_IRQ_EN,End of Sequence Interrupt Enable Bit" "0: Disable End of Sequence interrupt,1: Enable End of Sequence interrupt" newline bitfld.long 0x0 24. "FRAME_END_IRQ_EN,Frame End Interrupt Enable Bit" "0: Disable Frame End interrupt,1: Enable Frame End interrupt" newline bitfld.long 0x0 12. "RXFIFO_OVERRUN_IRQ_EN,RX FIFO Overrun Interrupt Enable Bit" "0: Disable RxFIFO Overrun interrupt,1: Enable RxFIFO Overrun interrupt" newline bitfld.long 0x0 11. "RXFIFO_UNDERRUN_IRQ_EN,RX FIFO Underrun Interrupt Enable Bit" "0: Disable RxFIFO Underrun interrupt,1: Enable RxFIFO Underrun interrupt" newline bitfld.long 0x0 10. "RXFIFO_FULL_IRQ_EN,RX FIFO Full Interrupt Enable Bit" "0: Disable RxFIFO Full interrupt,1: Enable RxFIFO Full interrupt" newline bitfld.long 0x0 9. "RXFIFO_EMPTY_IRQ_EN,RX FIFO Empty Interrupt Enable Bit" "0: Disable RxFIFO Empty interrupt,1: Enable RxFIFO Empty interrupt" newline bitfld.long 0x0 8. "RXFIFO_THRESH_IRQ_EN,RX FIFO Threshold Interrupt Enable Bit" "0: Disable RxFIFO Threshold interrupt,1: Enable RxFIFO Threshold interrupt" newline bitfld.long 0x0 4. "TXFIFO_OVERRUN_IRQ_EN,TX FIFO Overrun Interrupt Enable Bit" "0: Disable TxFIFO Overrun interrupt,1: Enable TxFIFO Overrun interrupt" newline bitfld.long 0x0 3. "TXFIFO_UNDERRUN_IRQ_EN,TX FIFO Underrun Interrupt Enable Bit" "0: Disable TxFIFO Underrun interrupt,1: Enable TxFIFO Underrun interrupt" newline bitfld.long 0x0 2. "TXFIFO_FULL_IRQ_EN,TX FIFO Full Interrupt Enable Bit" "0: Disable TxFIFO Full interrupt,1: Enable TxFIFO Full interrupt" newline bitfld.long 0x0 1. "TXFIFO_EMPTY_IRQ_EN,TX FIFO Empty Interrupt Enable Bit" "0: Disable TxFIFO Empty interrupt,1: Enable TxFIFO Empty interrupt" newline bitfld.long 0x0 0. "TXFIFO_THRESH_IRQ_EN,TX FIFO Threshold Interrupt Enable Bit" "0: Disable TxFIFO Threshold interrupt,1: Enable TxFIFO Threshold interrupt" line.long 0x4 "Q0_IRQ_STATUS,Queue n interrupt status register" bitfld.long 0x4 31. "PARITY_ERR,This flag is set when a SPI frame with parity error has been" "0: No SPI Parity Error,1: SPI Parity Error" newline bitfld.long 0x4 30. "CRC_ERR,This flag is set when SPI frame with CRC mismatch has been received." "0: No SPI CRC Error,1: SPI CRC Error" newline bitfld.long 0x4 29. "TRIG_OVERRUN_ERR,This flag is set when a HW trigger occurs while the previous HW trigger was already pending." "0: No HW Trigger Overrun Error,1: HW Trigger Overrun Error" newline bitfld.long 0x4 28. "COMMAND_ERR,This flag is set to one when command entry field has TAC_NUM" "0: No command error,1: Command error" newline bitfld.long 0x4 25. "EOS,End of Sequence Flag" "0: Not end of sequence,1: Last bit for a frame with Cmd.EOS = 1 has been.." newline bitfld.long 0x4 24. "FRAME_END,Frame end interrupt is generated when PCS is de-asserted (that is after trailing delay of SPI transfer at the edge where PCS deassertion occurs)." "0: It is cleared when '1' is written on it.,1: Frame end interrupt is generated when PCS is.." newline bitfld.long 0x4 12. "RXFIFO_OVERRUN_ERR,This flag is set when the RxFIFO is full and another word is written onto RxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: RxFIFO is full and another word is written onto.." newline bitfld.long 0x4 11. "RXFIFO_UNDERRUN_ERR,This flag is set when the read interface tries to read data from the RxFIFO even when it is empty. It is cleared when '1' is written on it." "0: No underrun,1: Read interface tries to read data from the.." newline bitfld.long 0x4 10. "RXFIFO_FULL,This flag is set when the RxFIFO is full. It is auto cleared when content of RxFIFO is read by SPI Core and it is no longer full." "0: RxFIFO is not full,1: RxFIFO is full" newline bitfld.long 0x4 9. "RXFIFO_EMPTY,This flag is set when RxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: RxFIFO is not empty,1: RxFIFO is empty" newline bitfld.long 0x4 8. "RXFIFO_THRESH,This flag is set when number of valid entries in RxFIFO is greater than or equal to RxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of valid entries in RxFIFO is lesser than..,1: Number of valid entries in RxFIFO is greater.." newline bitfld.long 0x4 4. "TXFIFO_OVERRUN_ERR,This flag is set when the TxFIFO is full and another word is written onto TxFIFO_PUSH register. It is cleared when '1' is written on it." "0: No overrun,1: TxFIFO is full and another word is written onto.." newline bitfld.long 0x4 2. "TXFIFO_FULL,This flag is set when the TxFIFO is full. It is auto cleared when content of TxFIFO is read by SPI Core and it is no longer full." "0: TxFIFO is not full,1: TxFIFO is full" newline bitfld.long 0x4 1. "TXFIFO_EMPTY,This flag is set when TxFIFO is empty. It is auto cleared when the FIFO is non empty." "0: TxFIFO is not empty,1: TxFIFO is empty" newline bitfld.long 0x4 0. "TXFIFO_THRESH,This bit is set when number of free entries in TxFIFO is greater than or equal to TxFIFO threshold. It is auto cleared when the condition becomes false." "0: Number of free entries in TxFIFO is lesser than..,1: Number of free entries in TxFIFO is greater than.." wgroup.long 0x40++0x3 line.long 0x0 "Q0_TXFIFO_PUSH,Queue n TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,32 bit wide Txdata and command entries used for frame transfer." rgroup.long 0x44++0x3 line.long 0x0 "Q0_RXFIFO_POP,Queue n RxFIFO register" hexmask.long 0x0 0.--31. 1. "RXDATA_STATUS,32 bit wide Rxdata or RxStatus entries" rgroup.long 0x80++0x7 line.long 0x0 "Q0_TXFIFO_PTR,Queue n TxFIFO pointer register" hexmask.long.byte 0x0 16.--23. 1. "TXFIFO_ACTIVE_ENTRIES,Active number of entries in TxFIFO" newline hexmask.long.byte 0x0 8.--11. 1. "TXFIFO_WR_PTR,TxFIFO write pointer" newline hexmask.long.byte 0x0 0.--3. 1. "TXFIFO_RD_PTR,TxFIFO read pointer" line.long 0x4 "Q0_RXFIFO_PTR,Queue n RxFIFO pointer register" hexmask.long.byte 0x4 16.--23. 1. "RXFIFO_ACTIVE_ENTRIES,Active number of entries in RxFIFO" newline hexmask.long.byte 0x4 8.--11. 1. "RXFIFO_WR_PTR,RxFIFO write pointer" newline hexmask.long.byte 0x4 0.--3. 1. "RXFIFO_RD_PTR,RxFIFO read pointer" group.long 0x8C++0x3 line.long 0x0 "Q0_DEBUG_PTR,Queue debug pointer register" hexmask.long.byte 0x0 8.--15. 1. "RXFIFO_DBG_PTR,RxFIFO debug read pointer value" newline hexmask.long.byte 0x0 0.--7. 1. "TXFIFO_DBG_PTR,TxFIFO debug read pointer value" rgroup.long 0x90++0x7 line.long 0x0 "Q0_DEBUG_TXFIFO_DATA,Queue n debug TxFIFO register" hexmask.long 0x0 0.--31. 1. "TXDATA_COMMAND,Contents of TxFIFO at location pointed by TxFIFO_DBG_PTR in Q_DEBUG_PTR register" line.long 0x4 "Q0_DEBUG_RXFIFO_DATA,Queue n debug RxFIFO register" hexmask.long 0x4 0.--31. 1. "RXDATA_STATUS,Contents of RxFIFO at location pointed by RxFIFO_DBG_PTR in Q_DEBUG_PTR register" rgroup.long 0x9C++0x3 line.long 0x0 "Q0_DEBUG_TXFIFO_CMD,Queue n debug TxFIFO command register" hexmask.long 0x0 0.--31. 1. "TXCOMMAND,Command Entry value of last or ongoing SPI transfer done from the queue." group.long 0xC0++0xB line.long 0x0 "Q0_CRC_CFG,Queue n CRC configuration register" bitfld.long 0x0 4. "INV_OUT,Control of final CRC inversion" "0: Do not inverted calculated final CRC,1: Invert final CRC" newline bitfld.long 0x0 0.--2. "CRC_SIZE,Size of CRC computation" "0: 4 bit CRC,1: 8 bit CRC,2: 16 bit CRC,3: 32 bit CRC,?,?,?,7: 3 bit CRC" line.long 0x4 "Q0_CRC_INIT,Queue n CRC initialization register" hexmask.long 0x4 0.--31. 1. "CRC_INIT,CRC Initial Value" line.long 0x8 "Q0_CRC_POLY,Queue n CRC polynomial register" hexmask.long 0x8 0.--31. 1. "CRC_POLY,Programmable CRC polynomial" rgroup.long 0xCC++0x7 line.long 0x0 "Q0_CRC_TX,Queue n CRC Tx register" hexmask.long 0x0 0.--31. 1. "CRC_TX,Value of CRC calculated for data transmitted" line.long 0x4 "Q0_CRC_RX,Queue n CRC Rx register" hexmask.long 0x4 0.--31. 1. "CRC_RX,Value of CRC calculated for data received" group.long 0xD4++0x7 line.long 0x0 "Q0_CRC_TXMASK,Queue n CRC TXMASK register" hexmask.long 0x0 0.--31. 1. "CRC_TX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." line.long 0x4 "Q0_CRC_RXMASK,Queue n CRC RXMASK register" hexmask.long 0x4 0.--31. 1. "CRC_RX_MASK,Bit i = ‘1’ : exclude ‘i’th bit of SPI transmit frame for CRC calculation." tree.end tree.end tree.end tree "SSCM2 (System Status and Configuration Module)" base ad:0x711EC000 group.long 0x0++0x3 line.long 0x0 "STATUS,System status register" bitfld.long 0x0 31. "OTA_EN,OTA enable status" "0: OTA is disabled ( this bit mirrors the DCF bit..,1: OTA is enabled( this bit mirrors the DCF bit of.." newline bitfld.long 0x0 5. "EDC_ERR,EDC error" "0: No error detected,1: Error detected (single bit flips are considered.." newline bitfld.long 0x0 4. "OTA_ERR,This bit captures error during OTA signature reading" "0: No error in reading signature,1: Error in reading signature" newline bitfld.long 0x0 3. "EFUSE,EFUSE burn status" "0: EFUSE is not burnt.,1: EFUSE is burnt." newline bitfld.long 0x0 2. "DER,Write error in DCF data" "0,1" newline bitfld.long 0x0 1. "MER,Write Error in Memory Repair DCF Client" "0: DCF Client writing is successful.,1: Error during the DCF Client writing." newline bitfld.long 0x0 0. "CER,Write Error in DCF Client" "0: DCF Client writing is successful.,1: Error during the DCF Client writing." rgroup.long 0x4++0x3 line.long 0x0 "CONFIG,Configuration register" hexmask.long.byte 0x0 16.--19. 1. "MREV,Minor Mask Revision" newline hexmask.long.word 0x0 0.--9. 1. "JTAGID,JTAG Part ID Number" rgroup.long 0x10++0xB line.long 0x0 "LIFECYCLE,Life Cycle status register" bitfld.long 0x0 8.--9. "TLC,Test Life Cycle" "0: Failure Analysis,1: ST_PROD,?,3: IN_FIELD" newline bitfld.long 0x0 0.--2. "LC,Life Cycle" "0: FAIL_ANALYSIS,?,2: PROD_OEM,3: CUST_DELIV,?,?,?,7: IN_FIELD" line.long 0x4 "BCS_CTRL,BCS control register" bitfld.long 0x4 31. "HSM_STATE,HSM state" "0: HSM is disabled.,1: HSM is enabled." newline bitfld.long 0x4 2. "FAEL,FA Endless Loop" "0: Boot CPU will execute an endless loop.,1: Boot CPU will not execute an endless loop." newline bitfld.long 0x4 1. "WFH,Wait For HSM" "0: Boot CPU will not wait for the HSM,1: Boot CPU will wait for the HSM" newline bitfld.long 0x4 0. "EN,Enable" "0: BCS is executed.,1: BCS is bypassed." line.long 0x8 "CEN,CPU enable register" bitfld.long 0x8 31. "VAL,Valid Boot Record" "0: No valid boot record is found.,1: Valid boot record is found." newline bitfld.long 0x8 5. "CEN5,CPU5 Enable" "0: CPU5 is disabled and will not run some SW.,1: CPU5 is enabled and will run some SW." newline bitfld.long 0x8 4. "CEN4,CPU4 Enable" "0: CPU4 is disabled and will not run some SW.,1: CPU4 is enabled and will run some SW." newline bitfld.long 0x8 3. "CEN3,CPU3 Enable" "0: CPU3 is disabled and will not run some SW.,1: CPU3 is enabled andand will run some SW." newline bitfld.long 0x8 2. "CEN2,CPU2 Enable" "0: CPU2 is disabled and will not run some SW.,1: CPU2 is enabled and will run some SW." newline bitfld.long 0x8 1. "CEN1,CPU1 Enable" "0: CPU1 is disabled and will not run some SW.,1: CPU1 is enabled and will run some SW." newline bitfld.long 0x8 0. "CEN0,CPU0 Enable" "0: CPU0 is disabled and will not run some SW.,1: CPU0 is enabled and will run some SW." rgroup.long 0x20++0x17 line.long 0x0 "CPU0_SADDR,CPU 0 start address register" hexmask.long 0x0 0.--31. 1. "SADDR,Start Address" line.long 0x4 "CPU1_SADDR,CPU 1 start address register" hexmask.long 0x4 0.--31. 1. "SADDR,Start Address" line.long 0x8 "CPU2_SADDR,CPU 2 start address register" hexmask.long 0x8 0.--31. 1. "SADDR,Start Address" line.long 0xC "CPU3_SADDR,CPU 3 start address register" hexmask.long 0xC 0.--31. 1. "SADDR,Start Address" line.long 0x10 "CPU4_SADDR,CPU 4 start address register" hexmask.long 0x10 0.--31. 1. "SADDR,Start Address" line.long 0x14 "CPU5_SADDR,CPU 5 start address register" hexmask.long 0x14 0.--31. 1. "SADDR,Start Address" rgroup.long 0x60++0x17 line.long 0x0 "CPU0_SBL,CPU 0 secure boot length register" hexmask.long 0x0 0.--31. 1. "CL,Code length for CPU" line.long 0x4 "CPU1_SBL,CPU 1 secure boot length register" hexmask.long 0x4 0.--31. 1. "CL,Code length for CPU" line.long 0x8 "CPU2_SBL,CPU 2 secure boot length register" hexmask.long 0x8 0.--31. 1. "CL,Code length for CPU" line.long 0xC "CPU3_SBL,CPU 3 secure boot length register" hexmask.long 0xC 0.--31. 1. "CL,Code length for CPU" line.long 0x10 "CPU4_SBL,CPU 4 secure boot length register" hexmask.long 0x10 0.--31. 1. "CL,Code length for CPU" line.long 0x14 "CPU5_SBL,CPU 5 secure boot length register" hexmask.long 0x14 0.--31. 1. "CL,Code length for CPU" rgroup.long 0x80++0x3 line.long 0x0 "NACLA,Non active context logical address register" hexmask.long 0x0 0.--31. 1. "NON_ACTIVE_LOGICAL_ADDR,Non active logical address" tree.end tree "STCU3 (Self-Test Control Unit)" base ad:0x0 tree "CBIST" base ad:0x710A6F80 rgroup.long 0x0++0xF line.long 0x0 "STCU_CB_STATUS,Offline STCU CBIST status register" bitfld.long 0x0 7. "CB_STATUS7,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" bitfld.long 0x0 6. "CB_STATUS6,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" newline bitfld.long 0x0 5. "CB_STATUS5,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" bitfld.long 0x0 4. "CB_STATUS4,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" newline bitfld.long 0x0 3. "CB_STATUS3,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" bitfld.long 0x0 2. "CB_STATUS2,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" newline bitfld.long 0x0 1. "CB_STATUS1,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" bitfld.long 0x0 0. "CB_STATUS0,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" line.long 0x4 "STCU_CB_ENDFLAG,Offline STCU CBIST end flag registers" bitfld.long 0x4 7. "CB_ENDFLAG7,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" bitfld.long 0x4 6. "CB_ENDFLAG6,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" newline bitfld.long 0x4 5. "CB_ENDFLAG5,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" bitfld.long 0x4 4. "CB_ENDFLAG4,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" newline bitfld.long 0x4 3. "CB_ENDFLAG3,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" bitfld.long 0x4 2. "CB_ENDFLAG2,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" newline bitfld.long 0x4 1. "CB_ENDFLAG1,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" bitfld.long 0x4 0. "CB_ENDFLAG0,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" line.long 0x8 "STCU_CBSW_STATUS,Online STCU CBIST status register" bitfld.long 0x8 7. "CBSW_STATUS7,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" bitfld.long 0x8 6. "CBSW_STATUS6,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" newline bitfld.long 0x8 5. "CBSW_STATUS5,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" bitfld.long 0x8 4. "CBSW_STATUS4,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" newline bitfld.long 0x8 3. "CBSW_STATUS3,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" bitfld.long 0x8 2. "CBSW_STATUS2,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" newline bitfld.long 0x8 1. "CBSW_STATUS1,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" bitfld.long 0x8 0. "CBSW_STATUS0,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" line.long 0xC "STCU_CBSW_ENDFLAG,Online STCU CBIST endflag register" bitfld.long 0xC 7. "CBSW_ENDFLAG7,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" bitfld.long 0xC 6. "CBSW_ENDFLAG6,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" newline bitfld.long 0xC 5. "CBSW_ENDFLAG5,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" bitfld.long 0xC 4. "CBSW_ENDFLAG4,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" newline bitfld.long 0xC 3. "CBSW_ENDFLAG3,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" bitfld.long 0xC 2. "CBSW_ENDFLAG2,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" newline bitfld.long 0xC 1. "CBSW_ENDFLAG1,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" bitfld.long 0xC 0. "CBSW_ENDFLAG0,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" group.long 0x10++0x3 line.long 0x0 "STCU_CB_UFM,STCU CBIST Unrecoverable Fault Mapping Register" bitfld.long 0x0 7. "CB_UFM7,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 6. "CB_UFM6,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x0 5. "CB_UFM5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 4. "CB_UFM4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x0 3. "CB_UFM3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 2. "CB_UFM2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x0 1. "CB_UFM1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 0. "CB_UFM0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable Fault mapping" tree.end tree "CBIST_ADDRBLK" base ad:0x710A6F80 rgroup.long 0x0++0xF line.long 0x0 "STCU_CB_STATUS,Offline STCU CBIST status register" bitfld.long 0x0 7. "CB_STATUS7,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" bitfld.long 0x0 6. "CB_STATUS6,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" newline bitfld.long 0x0 5. "CB_STATUS5,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" bitfld.long 0x0 4. "CB_STATUS4,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" newline bitfld.long 0x0 3. "CB_STATUS3,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" bitfld.long 0x0 2. "CB_STATUS2,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" newline bitfld.long 0x0 1. "CB_STATUS1,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" bitfld.long 0x0 0. "CB_STATUS0,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" line.long 0x4 "STCU_CB_ENDFLAG,Offline STCU CBIST end flag registers" bitfld.long 0x4 7. "CB_ENDFLAG7,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" bitfld.long 0x4 6. "CB_ENDFLAG6,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" newline bitfld.long 0x4 5. "CB_ENDFLAG5,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" bitfld.long 0x4 4. "CB_ENDFLAG4,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" newline bitfld.long 0x4 3. "CB_ENDFLAG3,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" bitfld.long 0x4 2. "CB_ENDFLAG2,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" newline bitfld.long 0x4 1. "CB_ENDFLAG1,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" bitfld.long 0x4 0. "CB_ENDFLAG0,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" line.long 0x8 "STCU_CBSW_STATUS,Online STCU CBIST status register" bitfld.long 0x8 7. "CBSW_STATUS7,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" bitfld.long 0x8 6. "CBSW_STATUS6,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" newline bitfld.long 0x8 5. "CBSW_STATUS5,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" bitfld.long 0x8 4. "CBSW_STATUS4,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" newline bitfld.long 0x8 3. "CBSW_STATUS3,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" bitfld.long 0x8 2. "CBSW_STATUS2,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" newline bitfld.long 0x8 1. "CBSW_STATUS1,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" bitfld.long 0x8 0. "CBSW_STATUS0,0 : Failed CBIST execution." "0: Failed CBIST execution,1: Successful CBIST execution" line.long 0xC "STCU_CBSW_ENDFLAG,Online STCU CBIST endflag register" bitfld.long 0xC 7. "CBSW_ENDFLAG7,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" bitfld.long 0xC 6. "CBSW_ENDFLAG6,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" newline bitfld.long 0xC 5. "CBSW_ENDFLAG5,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" bitfld.long 0xC 4. "CBSW_ENDFLAG4,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" newline bitfld.long 0xC 3. "CBSW_ENDFLAG3,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" bitfld.long 0xC 2. "CBSW_ENDFLAG2,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" newline bitfld.long 0xC 1. "CBSW_ENDFLAG1,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" bitfld.long 0xC 0. "CBSW_ENDFLAG0,0 : CBIST execution not yet completed." "0: CBIST execution not yet completed,1: CBIST execution finished" group.long 0x10++0x3 line.long 0x0 "STCU_CB_UFM,STCU CBIST Unrecoverable Fault Mapping Register" bitfld.long 0x0 7. "CB_UFM7,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 6. "CB_UFM6,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x0 5. "CB_UFM5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 4. "CB_UFM4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x0 3. "CB_UFM3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 2. "CB_UFM2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x0 1. "CB_UFM1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 0. "CB_UFM0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable Fault mapping" tree.end tree "CBIST_PTR" base ad:0x710A8080 repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "STCU_CBISTN_PTR[$1],STCU CBISTn pointer register" hexmask.long.byte 0x0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next CBIST partition for BIST execution. The size of this field depends on the number of CBISTs partitions present on the device." bitfld.long 0x0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" repeat.end tree.end tree "CBIST_PTR_ADDRBLK" base ad:0x710A8080 group.long 0x0++0x1F line.long 0x0 "STCU_CBIST0_PTR,STCU CBISTn pointer register" hexmask.long.byte 0x0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next CBIST partition for BIST execution. The size of this field depends on the number of CBISTs partitions present on the device." bitfld.long 0x0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4 "STCU_CBIST1_PTR,STCU CBISTn pointer register" hexmask.long.byte 0x4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next CBIST partition for BIST execution. The size of this field depends on the number of CBISTs partitions present on the device." bitfld.long 0x4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x8 "STCU_CBIST2_PTR,STCU CBISTn pointer register" hexmask.long.byte 0x8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next CBIST partition for BIST execution. The size of this field depends on the number of CBISTs partitions present on the device." bitfld.long 0x8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xC "STCU_CBIST3_PTR,STCU CBISTn pointer register" hexmask.long.byte 0xC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next CBIST partition for BIST execution. The size of this field depends on the number of CBISTs partitions present on the device." bitfld.long 0xC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x10 "STCU_CBIST4_PTR,STCU CBISTn pointer register" hexmask.long.byte 0x10 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x10 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next CBIST partition for BIST execution. The size of this field depends on the number of CBISTs partitions present on the device." bitfld.long 0x10 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x14 "STCU_CBIST5_PTR,STCU CBISTn pointer register" hexmask.long.byte 0x14 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x14 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next CBIST partition for BIST execution. The size of this field depends on the number of CBISTs partitions present on the device." bitfld.long 0x14 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x18 "STCU_CBIST6_PTR,STCU CBISTn pointer register" hexmask.long.byte 0x18 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x18 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next CBIST partition for BIST execution. The size of this field depends on the number of CBISTs partitions present on the device." bitfld.long 0x18 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1C "STCU_CBIST7_PTR,STCU CBISTn pointer register" hexmask.long.byte 0x1C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next CBIST partition for BIST execution. The size of this field depends on the number of CBISTs partitions present on the device." bitfld.long 0x1C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" tree.end tree "CFG" base ad:0x710A4000 group.long 0x0++0x7 line.long 0x0 "STCU_RUN,STCU Offline RUN register" bitfld.long 0x0 11. "RUN_BYP,0 : Offline self-test is active. If the STCU_RUN[RUN] bit is not set before the hardcoded WDG timeout the WDTO error is generated in the STCU_ERR_STAT register" "0: Offline self-test is active,1: Offline self-test is bypassed and access to.." newline bitfld.long 0x0 10. "MBPLLEN,0 : Offline MBIST is executed without using the on-chip PLL" "0: Offline MBIST is executed without using the..,1: Offline MBIST is executed enabling the on-chip.." newline bitfld.long 0x0 9. "LBPLLEN,0 : Offline LBIST is executed without using the on-chip PLL" "0: Offline LBIST is executed without using the..,1: Offline LBIST is executed enabling the on-chip.." newline bitfld.long 0x0 8. "CBPLLEN,0 : Offline CBIST is executed without using the on-chip PLL" "0: Offline CBIST is executed without using the..,1: Offline CBIST is executed enabling the on-chip.." newline bitfld.long 0x0 0. "RUN,RUN bit is automatically cleared by STCU when offline self-test procedure has been completed" "0: Idle,1: Offline self-test procedure is running" line.long 0x4 "STCU_RUNSW,STCU Online RUN register" bitfld.long 0x4 10. "MBSWPLLEN,0 : Online MBIST is executed without using the on-chip PLL" "0: Online MBIST is executed without using the..,1: Online MBIST is executed using the PLL.." newline bitfld.long 0x4 9. "LBSWPLLEN,0 : Online LBIST is executed without using the on-chip PLL" "0: Online LBIST is executed without using the..,1: Online LBIST is executed using the PLL.." newline bitfld.long 0x4 8. "CBSWPLLEN,0 : Online CBIST is executed without using the on-chip PLL" "0: Online CBIST is executed without using the..,1: Online CBIST is executed using the PLL.." newline bitfld.long 0x4 1. "RUNSW_ABORT,This bit is automatically cleared by the STCU3 when the software self-test abort sequence has been completed" "0: Online self-test abort is not requested,1: Online self-test abort is requested" newline bitfld.long 0x4 0. "RUNSW,The RUNSW bit is automatically cleared by the STCU3 when the online self-test procedure has been completed" "0: Idle,1: Online self-test procedure is running" wgroup.long 0x8++0x3 line.long 0x0 "STCU_SKC,STCU security key register" hexmask.long 0x0 0.--31. 1. "SKC,STCU3 security key code for offline test" group.long 0x10++0x7 line.long 0x0 "STCU_CFG,STCU configuration register" hexmask.long.byte 0x0 24.--27. 1. "INIT_PTR,INIT_PTR defines the logical pointer to the first LBIST or MBIST to be scheduled when the self-test procedure is enabled. it indicates the first pointer of selected BIST type that is if INIT_PTR = 0000 first LBIST is selected." newline hexmask.long.byte 0x0 16.--19. 1. "LB_INIT_DELAY,Delay introduced between enabling configuration of LBIST and triggering the start of LBIST testing" newline bitfld.long 0x0 8. "WRP,0 : Specific STCU registers can be written through IPS bus interface after offline self-test sequence has completed" "0: Specific STCU registers can be written through..,1: Specific STCU registers cannot be written though.." newline bitfld.long 0x0 5. "CRCEN,0 : The CRC comparison is not performed and the STCU_ERR_STAT[CRCS][SW] and STCU_ERR_STAT[UF/RF] global flags are not updated in case of mismatches" "0: The CRC comparison is not performed and the..,1: The CRC comparison is performed and the status.." newline bitfld.long 0x0 0.--2. "CFG_CLK,CLK_CFG defines the ratio between the sys_clk (STCU input clock) and the TCK used to program MBIST and stcu_core_clk.The punch-out mechanism is used to generate the derived clocks. (Punch-out mechanism: for example if a clock has to be divided by.." "0,1,2,3,4,5,6,7" line.long 0x4 "STCU_RUN_DELAY,STCU delay value register" hexmask.long.word 0x4 16.--31. 1. "MB_DELAY,MB_DELAY defines the delay between the MBIST starts when more than a single MBIST is selected to be executed concurrently with the purpose of smoothing the power consumption transient. The next MBIST execution is delayed by the MB_DELAY value.." newline hexmask.long.word 0x4 0.--15. 1. "LB_DELAY,LB_DELAY defines the delay between the LBIST starts when more than a single LBIST is selected to be executed concurrently with the purpose of smoothing the power consumption transient" repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x18)++0x3 line.long 0x0 "STCU_PLLN_CFG[$1],STCU PLLn configuration register" bitfld.long 0x0 31. "PLL_EN,PLL enable" "0,1" newline hexmask.long.byte 0x0 24.--29. 1. "ODF2,The value of this field drives the 2nd output division factor of the PLL embedded in the device" newline bitfld.long 0x0 22.--23. "PLL_REF_SEL,Reserved (RC clock is always selected)" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "ODF1,The value of this field drives the 1st output division factor of the PLL embedded in the device" newline hexmask.long.byte 0x0 11.--14. 1. "CGM_IP_SEL,Input clock selection for CGM" newline bitfld.long 0x0 8.--10. "IDF,The value of this field drives the input division factor of the PLL embedded in the device" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--6. 1. "LDF,The value of this field drives the loop division factor of the PLL embedded in the device" repeat.end group.long 0x38++0x1F line.long 0x0 "STCU_PLL_MISC,STCU PLL external port configuration register" hexmask.long 0x0 0.--31. 1. "PLL_MISC_CONFIG,Output port for PLL usage outside IP from STCU (refer to the device configuration chapter)" line.long 0x4 "STCU_WDG,STCU end of count register" hexmask.long 0x4 0.--31. 1. "WDG_EOC,End of count value to define timing budget for online/ offline self-test execution and check that everything is working correctly in given timeslot." line.long 0x8 "STCU_INT_CTRL,STCU interrupt enable register" bitfld.long 0x8 2. "MB_INT_EN,0 : Interrupt is not generated at the end of the software MBIST execution phase of the selected memories" "0: Interrupt is not generated at the end of the..,1: At the end of the software MBIST execution phase.." newline bitfld.long 0x8 1. "LB_INT_EN,0 : Interrupt is not generated at the end of the software LBIST execution phase of the selected LBISTs" "0: Interrupt is not generated at the end of the..,1: At the end of the software LBIST execution phase.." newline bitfld.long 0x8 0. "CB_INT_EN,0 : Interrupt is not generated at the end of the software CBIST execution phase of the selected CBISTs" "0: Interrupt is not generated at the end of the..,1: At the end of the software CBIST execution phase.." line.long 0xC "STCU_INT_STATUS,STCU interrupt status bits register" bitfld.long 0xC 2. "INT_MB_STATUS,0 : No interrupt is pending" "0: No interrupt is pending,1: An interrupt highlighting that 'the online.." newline bitfld.long 0xC 1. "INT_LB_STATUS,0 : No interrupt is pending" "0: No interrupt is pending,1: An interrupt highlighting that 'the online.." newline bitfld.long 0xC 0. "INT_CB_STATUS,0 : No interrupt is pending" "0: No interrupt is pending,1: An interrupt highlighting that 'the online.." line.long 0x10 "STCU_CRCE,CRC expected signature register" hexmask.long 0x10 0.--31. 1. "CRCE,CRC exepected signature value" line.long 0x14 "STCU_CRCR,CRC read signature register" hexmask.long 0x14 0.--31. 1. "CRCR,Read CRC signature value" line.long 0x18 "STCU_ERR_STATUS,STCU error status register" bitfld.long 0x18 31. "ABORTHW,0 : No hardware abort was requested during the online self-test sequence." "0: No hardware abort was requested during the..,1: A hardware abort was detected during the online.." newline bitfld.long 0x18 30. "ABORTSW,0 : No software abort was requested during the online self-test sequence." "0: No software abort was requested during the..,1: A software abort was detected during the online.." newline bitfld.long 0x18 29. "UFSF,0 : No errors that trigger the unrecoverable faults condition." "0: No errors that trigger the unrecoverable faults..,1: There are errors that trigger the unrecoverable.." newline bitfld.long 0x18 28. "RFSF,0 : No errors that trigger the recoverable faults condition." "0: No errors that trigger the recoverable faults..,1: There are errors that trigger the recoverable.." newline hexmask.long.byte 0x18 20.--24. 1. "LOCKESW,0 : If PLL is enabled it is correctly locked during the self-test sequence" newline bitfld.long 0x18 19. "WDTOSW,0 : LBIST/MBIST/CBIST time slot have been completed within the assigned watchdog time." "0: LBIST/MBIST/CBIST time slot have been completed..,1: LBIST/MBIST/CBIST time slot haven’t been.." newline bitfld.long 0x18 18. "CRCSSW,This flag is activated only when online self-test is performed STCU_CFG[CRCEN] is set to 1 otherwise it is always forced to 0. This prevents the generation of the respective STCU_ERR_STAT[UFSF/RFSF] bits. In both the cases the content of the.." "0: Successful CRC comparison or comparison has been..,1: Failed CRC comparison" newline bitfld.long 0x18 17. "ENGESW,0 : Valid engine execution." "0: Valid engine execution,1: Invalid engine execution" newline bitfld.long 0x18 16. "INVPSW,0 : Valid pointer value." "0: Valid pointer value,1: Invalid pointer value" newline hexmask.long.byte 0x18 4.--8. 1. "LOCKE,0 : The PLL is correctly locked during the self-test sequence" newline bitfld.long 0x18 3. "WDTO,0 : LBIST/MBIST/CBIST time slot have been completed within the assigned watchdog time." "0: LBIST/MBIST/CBIST time slot have been completed..,1: LBIST/MBIST/CBIST time slot haven’t been.." newline bitfld.long 0x18 2. "CRCS,This flag is activated only when offline self-test is performed STCU_CFG[CRCEN] is set to 1 otherwise it is always forced to 0. This prevents the generation of the respective STCU_ERR_STAT[UFSF/RFSF] bits. In both the cases the content of the.." "0: Successful CRC comparison or comparison has been..,1: Failed CRC comparison" newline bitfld.long 0x18 1. "ENGE,0 : Valid engine execution." "0: Valid engine execution,1: Invalid engine execution" newline bitfld.long 0x18 0. "INVP,0 : Valid pointer value." "0: Valid pointer value,1: Invalid pointer value" line.long 0x1C "STCU_ERR_FM,STCU error fault mapping register" bitfld.long 0x1C 4. "LOCKEUFM,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable mapping" newline bitfld.long 0x1C 3. "WDTOUFM,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable mapping" newline bitfld.long 0x1C 2. "CRCSUFM,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable mapping" newline bitfld.long 0x1C 1. "ENGEUFM,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable mapping" newline bitfld.long 0x1C 0. "INVPUFM,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable mapping" tree.end tree "CFG_ADDRBLK" base ad:0x710A4000 group.long 0x0++0x7 line.long 0x0 "STCU_RUN,STCU Offline RUN register" bitfld.long 0x0 11. "RUN_BYP,0 : Offline self-test is active. If the STCU_RUN[RUN] bit is not set before the hardcoded WDG timeout the WDTO error is generated in the STCU_ERR_STAT register" "0: Offline self-test is active,1: Offline self-test is bypassed and access to.." newline bitfld.long 0x0 10. "MBPLLEN,0 : Offline MBIST is executed without using the on-chip PLL" "0: Offline MBIST is executed without using the..,1: Offline MBIST is executed enabling the on-chip.." newline bitfld.long 0x0 9. "LBPLLEN,0 : Offline LBIST is executed without using the on-chip PLL" "0: Offline LBIST is executed without using the..,1: Offline LBIST is executed enabling the on-chip.." newline bitfld.long 0x0 8. "CBPLLEN,0 : Offline CBIST is executed without using the on-chip PLL" "0: Offline CBIST is executed without using the..,1: Offline CBIST is executed enabling the on-chip.." newline bitfld.long 0x0 0. "RUN,RUN bit is automatically cleared by STCU when offline self-test procedure has been completed" "0: Idle,1: Offline self-test procedure is running" line.long 0x4 "STCU_RUNSW,STCU Online RUN register" bitfld.long 0x4 10. "MBSWPLLEN,0 : Online MBIST is executed without using the on-chip PLL" "0: Online MBIST is executed without using the..,1: Online MBIST is executed using the PLL.." newline bitfld.long 0x4 9. "LBSWPLLEN,0 : Online LBIST is executed without using the on-chip PLL" "0: Online LBIST is executed without using the..,1: Online LBIST is executed using the PLL.." newline bitfld.long 0x4 8. "CBSWPLLEN,0 : Online CBIST is executed without using the on-chip PLL" "0: Online CBIST is executed without using the..,1: Online CBIST is executed using the PLL.." newline bitfld.long 0x4 1. "RUNSW_ABORT,This bit is automatically cleared by the STCU3 when the software self-test abort sequence has been completed" "0: Online self-test abort is not requested,1: Online self-test abort is requested" newline bitfld.long 0x4 0. "RUNSW,The RUNSW bit is automatically cleared by the STCU3 when the online self-test procedure has been completed" "0: Idle,1: Online self-test procedure is running" wgroup.long 0x8++0x3 line.long 0x0 "STCU_SKC,STCU security key register" hexmask.long 0x0 0.--31. 1. "SKC,STCU3 security key code for offline test" group.long 0x10++0x1B line.long 0x0 "STCU_CFG,STCU configuration register" hexmask.long.byte 0x0 24.--27. 1. "INIT_PTR,INIT_PTR defines the logical pointer to the first LBIST or MBIST to be scheduled when the self-test procedure is enabled. it indicates the first pointer of selected BIST type that is if INIT_PTR = 0000 first LBIST is selected." newline hexmask.long.byte 0x0 16.--19. 1. "LB_INIT_DELAY,Delay introduced between enabling configuration of LBIST and triggering the start of LBIST testing" newline bitfld.long 0x0 8. "WRP,0 : Specific STCU registers can be written through IPS bus interface after offline self-test sequence has completed" "0: Specific STCU registers can be written through..,1: Specific STCU registers cannot be written though.." newline bitfld.long 0x0 5. "CRCEN,0 : The CRC comparison is not performed and the STCU_ERR_STAT[CRCS][SW] and STCU_ERR_STAT[UF/RF] global flags are not updated in case of mismatches" "0: The CRC comparison is not performed and the..,1: The CRC comparison is performed and the status.." newline bitfld.long 0x0 0.--2. "CFG_CLK,CLK_CFG defines the ratio between the sys_clk (STCU input clock) and the TCK used to program MBIST and stcu_core_clk.The punch-out mechanism is used to generate the derived clocks. (Punch-out mechanism: for example if a clock has to be divided by.." "0,1,2,3,4,5,6,7" line.long 0x4 "STCU_RUN_DELAY,STCU delay value register" hexmask.long.word 0x4 16.--31. 1. "MB_DELAY,MB_DELAY defines the delay between the MBIST starts when more than a single MBIST is selected to be executed concurrently with the purpose of smoothing the power consumption transient. The next MBIST execution is delayed by the MB_DELAY value.." newline hexmask.long.word 0x4 0.--15. 1. "LB_DELAY,LB_DELAY defines the delay between the LBIST starts when more than a single LBIST is selected to be executed concurrently with the purpose of smoothing the power consumption transient" line.long 0x8 "STCU_PLL0_CFG,STCU PLLn configuration register" bitfld.long 0x8 31. "PLL_EN,PLL enable" "0,1" newline hexmask.long.byte 0x8 24.--29. 1. "ODF2,The value of this field drives the 2nd output division factor of the PLL embedded in the device" newline bitfld.long 0x8 22.--23. "PLL_REF_SEL,Reserved (RC clock is always selected)" "0,1,2,3" newline hexmask.long.byte 0x8 16.--21. 1. "ODF1,The value of this field drives the 1st output division factor of the PLL embedded in the device" newline hexmask.long.byte 0x8 11.--14. 1. "CGM_IP_SEL,Input clock selection for CGM" newline bitfld.long 0x8 8.--10. "IDF,The value of this field drives the input division factor of the PLL embedded in the device" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--6. 1. "LDF,The value of this field drives the loop division factor of the PLL embedded in the device" line.long 0xC "STCU_PLL1_CFG,STCU PLLn configuration register" bitfld.long 0xC 31. "PLL_EN,PLL enable" "0,1" newline hexmask.long.byte 0xC 24.--29. 1. "ODF2,The value of this field drives the 2nd output division factor of the PLL embedded in the device" newline bitfld.long 0xC 22.--23. "PLL_REF_SEL,Reserved (RC clock is always selected)" "0,1,2,3" newline hexmask.long.byte 0xC 16.--21. 1. "ODF1,The value of this field drives the 1st output division factor of the PLL embedded in the device" newline hexmask.long.byte 0xC 11.--14. 1. "CGM_IP_SEL,Input clock selection for CGM" newline bitfld.long 0xC 8.--10. "IDF,The value of this field drives the input division factor of the PLL embedded in the device" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 0.--6. 1. "LDF,The value of this field drives the loop division factor of the PLL embedded in the device" line.long 0x10 "STCU_PLL2_CFG,STCU PLLn configuration register" bitfld.long 0x10 31. "PLL_EN,PLL enable" "0,1" newline hexmask.long.byte 0x10 24.--29. 1. "ODF2,The value of this field drives the 2nd output division factor of the PLL embedded in the device" newline bitfld.long 0x10 22.--23. "PLL_REF_SEL,Reserved (RC clock is always selected)" "0,1,2,3" newline hexmask.long.byte 0x10 16.--21. 1. "ODF1,The value of this field drives the 1st output division factor of the PLL embedded in the device" newline hexmask.long.byte 0x10 11.--14. 1. "CGM_IP_SEL,Input clock selection for CGM" newline bitfld.long 0x10 8.--10. "IDF,The value of this field drives the input division factor of the PLL embedded in the device" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--6. 1. "LDF,The value of this field drives the loop division factor of the PLL embedded in the device" line.long 0x14 "STCU_PLL3_CFG,STCU PLLn configuration register" bitfld.long 0x14 31. "PLL_EN,PLL enable" "0,1" newline hexmask.long.byte 0x14 24.--29. 1. "ODF2,The value of this field drives the 2nd output division factor of the PLL embedded in the device" newline bitfld.long 0x14 22.--23. "PLL_REF_SEL,Reserved (RC clock is always selected)" "0,1,2,3" newline hexmask.long.byte 0x14 16.--21. 1. "ODF1,The value of this field drives the 1st output division factor of the PLL embedded in the device" newline hexmask.long.byte 0x14 11.--14. 1. "CGM_IP_SEL,Input clock selection for CGM" newline bitfld.long 0x14 8.--10. "IDF,The value of this field drives the input division factor of the PLL embedded in the device" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--6. 1. "LDF,The value of this field drives the loop division factor of the PLL embedded in the device" line.long 0x18 "STCU_PLL4_CFG,STCU PLLn configuration register" bitfld.long 0x18 31. "PLL_EN,PLL enable" "0,1" newline hexmask.long.byte 0x18 24.--29. 1. "ODF2,The value of this field drives the 2nd output division factor of the PLL embedded in the device" newline bitfld.long 0x18 22.--23. "PLL_REF_SEL,Reserved (RC clock is always selected)" "0,1,2,3" newline hexmask.long.byte 0x18 16.--21. 1. "ODF1,The value of this field drives the 1st output division factor of the PLL embedded in the device" newline hexmask.long.byte 0x18 11.--14. 1. "CGM_IP_SEL,Input clock selection for CGM" newline bitfld.long 0x18 8.--10. "IDF,The value of this field drives the input division factor of the PLL embedded in the device" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--6. 1. "LDF,The value of this field drives the loop division factor of the PLL embedded in the device" group.long 0x38++0x1F line.long 0x0 "STCU_PLL_MISC,STCU PLL external port configuration register" hexmask.long 0x0 0.--31. 1. "PLL_MISC_CONFIG,Output port for PLL usage outside IP from STCU (refer to the device configuration chapter)" line.long 0x4 "STCU_WDG,STCU end of count register" hexmask.long 0x4 0.--31. 1. "WDG_EOC,End of count value to define timing budget for online/ offline self-test execution and check that everything is working correctly in given timeslot." line.long 0x8 "STCU_INT_CTRL,STCU interrupt enable register" bitfld.long 0x8 2. "MB_INT_EN,0 : Interrupt is not generated at the end of the software MBIST execution phase of the selected memories" "0: Interrupt is not generated at the end of the..,1: At the end of the software MBIST execution phase.." newline bitfld.long 0x8 1. "LB_INT_EN,0 : Interrupt is not generated at the end of the software LBIST execution phase of the selected LBISTs" "0: Interrupt is not generated at the end of the..,1: At the end of the software LBIST execution phase.." newline bitfld.long 0x8 0. "CB_INT_EN,0 : Interrupt is not generated at the end of the software CBIST execution phase of the selected CBISTs" "0: Interrupt is not generated at the end of the..,1: At the end of the software CBIST execution phase.." line.long 0xC "STCU_INT_STATUS,STCU interrupt status bits register" bitfld.long 0xC 2. "INT_MB_STATUS,0 : No interrupt is pending" "0: No interrupt is pending,1: An interrupt highlighting that 'the online.." newline bitfld.long 0xC 1. "INT_LB_STATUS,0 : No interrupt is pending" "0: No interrupt is pending,1: An interrupt highlighting that 'the online.." newline bitfld.long 0xC 0. "INT_CB_STATUS,0 : No interrupt is pending" "0: No interrupt is pending,1: An interrupt highlighting that 'the online.." line.long 0x10 "STCU_CRCE,CRC expected signature register" hexmask.long 0x10 0.--31. 1. "CRCE,CRC exepected signature value" line.long 0x14 "STCU_CRCR,CRC read signature register" hexmask.long 0x14 0.--31. 1. "CRCR,Read CRC signature value" line.long 0x18 "STCU_ERR_STATUS,STCU error status register" bitfld.long 0x18 31. "ABORTHW,0 : No hardware abort was requested during the online self-test sequence." "0: No hardware abort was requested during the..,1: A hardware abort was detected during the online.." newline bitfld.long 0x18 30. "ABORTSW,0 : No software abort was requested during the online self-test sequence." "0: No software abort was requested during the..,1: A software abort was detected during the online.." newline bitfld.long 0x18 29. "UFSF,0 : No errors that trigger the unrecoverable faults condition." "0: No errors that trigger the unrecoverable faults..,1: There are errors that trigger the unrecoverable.." newline bitfld.long 0x18 28. "RFSF,0 : No errors that trigger the recoverable faults condition." "0: No errors that trigger the recoverable faults..,1: There are errors that trigger the recoverable.." newline hexmask.long.byte 0x18 20.--24. 1. "LOCKESW,0 : If PLL is enabled it is correctly locked during the self-test sequence" newline bitfld.long 0x18 19. "WDTOSW,0 : LBIST/MBIST/CBIST time slot have been completed within the assigned watchdog time." "0: LBIST/MBIST/CBIST time slot have been completed..,1: LBIST/MBIST/CBIST time slot haven’t been.." newline bitfld.long 0x18 18. "CRCSSW,This flag is activated only when online self-test is performed STCU_CFG[CRCEN] is set to 1 otherwise it is always forced to 0. This prevents the generation of the respective STCU_ERR_STAT[UFSF/RFSF] bits. In both the cases the content of the.." "0: Successful CRC comparison or comparison has been..,1: Failed CRC comparison" newline bitfld.long 0x18 17. "ENGESW,0 : Valid engine execution." "0: Valid engine execution,1: Invalid engine execution" newline bitfld.long 0x18 16. "INVPSW,0 : Valid pointer value." "0: Valid pointer value,1: Invalid pointer value" newline hexmask.long.byte 0x18 4.--8. 1. "LOCKE,0 : The PLL is correctly locked during the self-test sequence" newline bitfld.long 0x18 3. "WDTO,0 : LBIST/MBIST/CBIST time slot have been completed within the assigned watchdog time." "0: LBIST/MBIST/CBIST time slot have been completed..,1: LBIST/MBIST/CBIST time slot haven’t been.." newline bitfld.long 0x18 2. "CRCS,This flag is activated only when offline self-test is performed STCU_CFG[CRCEN] is set to 1 otherwise it is always forced to 0. This prevents the generation of the respective STCU_ERR_STAT[UFSF/RFSF] bits. In both the cases the content of the.." "0: Successful CRC comparison or comparison has been..,1: Failed CRC comparison" newline bitfld.long 0x18 1. "ENGE,0 : Valid engine execution." "0: Valid engine execution,1: Invalid engine execution" newline bitfld.long 0x18 0. "INVP,0 : Valid pointer value." "0: Valid pointer value,1: Invalid pointer value" line.long 0x1C "STCU_ERR_FM,STCU error fault mapping register" bitfld.long 0x1C 4. "LOCKEUFM,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable mapping" newline bitfld.long 0x1C 3. "WDTOUFM,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable mapping" newline bitfld.long 0x1C 2. "CRCSUFM,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable mapping" newline bitfld.long 0x1C 1. "ENGEUFM,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable mapping" newline bitfld.long 0x1C 0. "INVPUFM,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable mapping" tree.end tree "LBIST" base ad:0x710A4070 rgroup.long 0x0++0xF line.long 0x0 "STCU_LB_STATUS,Offline STCU LBIST status registers" bitfld.long 0x0 0. "LB_STATUS0,0 : Failed LBIST execution." "0: Failed LBIST execution,1: Successful LBIST execution" line.long 0x4 "STCU_LB_ENDFLAG,Offline STCU LBIST endflag register" bitfld.long 0x4 0. "LB_ENDFLAG0,0 : LBIST execution not yet completed." "0: LBIST execution not yet completed,1: LBIST execution finished" line.long 0x8 "STCU_LBSW_STATUS,Online STCU LBIST status register" bitfld.long 0x8 0. "LBSW_STATUS0,0 : Failed LBIST execution." "0: Failed LBIST execution,1: Successful LBIST execution" line.long 0xC "STCU_LBSW_ENDFLAG,Online STCU LBIST endflag register" bitfld.long 0xC 0. "LBSW_ENDFLAG0,0 : LBIST execution not yet completed." "0: LBIST execution not yet completed,1: LBIST execution finished" group.long 0x10++0x3 line.long 0x0 "STCU_LB_UFM,STCU LBIST Unrecoverable Fault Mapping Register" bitfld.long 0x0 0. "LB_UFM0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable Fault mapping" tree.end tree "LBIST_ADDRBLK" base ad:0x710A4070 rgroup.long 0x0++0xF line.long 0x0 "STCU_LB_STATUS,Offline STCU LBIST status registers" bitfld.long 0x0 0. "LB_STATUS0,0 : Failed LBIST execution." "0: Failed LBIST execution,1: Successful LBIST execution" line.long 0x4 "STCU_LB_ENDFLAG,Offline STCU LBIST endflag register" bitfld.long 0x4 0. "LB_ENDFLAG0,0 : LBIST execution not yet completed." "0: LBIST execution not yet completed,1: LBIST execution finished" line.long 0x8 "STCU_LBSW_STATUS,Online STCU LBIST status register" bitfld.long 0x8 0. "LBSW_STATUS0,0 : Failed LBIST execution." "0: Failed LBIST execution,1: Successful LBIST execution" line.long 0xC "STCU_LBSW_ENDFLAG,Online STCU LBIST endflag register" bitfld.long 0xC 0. "LBSW_ENDFLAG0,0 : LBIST execution not yet completed." "0: LBIST execution not yet completed,1: LBIST execution finished" group.long 0x10++0x3 line.long 0x0 "STCU_LB_UFM,STCU LBIST Unrecoverable Fault Mapping Register" bitfld.long 0x0 0. "LB_UFM0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable Fault mapping" tree.end tree "LBIST_CONFIG" base ad:0x710A4084 group.long 0x0++0x13 line.long 0x0 "STCU_LBN_CFG,STCU LBISTn configuration register" bitfld.long 0x0 18. "LOW_POWER,Required in functional mode to reduce power consumption." "0,1" bitfld.long 0x0 16.--17. "TEST_MODE,Defines the type of test to be performed by LBIST controller." "0: Reserved,1: Reserved,?,?" hexmask.long.byte 0x0 0.--7. 1. "SHIFT_LEN,Defines the scan chain length for LBIST controller configuration." line.long 0x4 "STCU_LBN_PC,STCU LBISTn pattern count register" hexmask.long.word 0x4 0.--15. 1. "PC,Defines the pattern count value for LBIST controller configuration." line.long 0x8 "STCU_LBN_SEED0,STCU LBIST seed_0 register" hexmask.long 0x8 0.--31. 1. "LBN_SEED0,LBIST SEED_0 value" line.long 0xC "STCU_LBN_SEED1,STCU LBIST seed_1 register" hexmask.long 0xC 0.--31. 1. "LBN_SEED1,LBIST SEED_1 value" line.long 0x10 "STCU_LBN_SEED2,STCU LBIST seed_2 register" hexmask.long.word 0x10 0.--15. 1. "LBN_SEED2,LBIST SEED_2 value" group.long 0x18++0xB line.long 0x0 "STCU_LBN_MISRE0,STCU LBISTn Offline misre_0 register" hexmask.long 0x0 0.--31. 1. "LBN_MISRE0,Offline LBIST MISRE_0 value" line.long 0x4 "STCU_LBN_MISRE1,STCU LBISTn Offline misre_1 register" hexmask.long 0x4 0.--31. 1. "LBN_MISRE1,Offline LBIST MISRE_1 value" line.long 0x8 "STCU_LBN_MISRE2,STCU LBISTn Offline misre_2 register" hexmask.long.word 0x8 0.--15. 1. "LBN_MISRE2,Offline LBIST MISRE_2 value" rgroup.long 0x28++0xB line.long 0x0 "STCU_LBN_MISRR0,STCU LBISTn Offline misrr_0 register" hexmask.long 0x0 0.--31. 1. "LBN_MISRR0,Offline LBIST MISRR_0 value" line.long 0x4 "STCU_LBN_MISRR1,STCU LBISTn Offline misrr_1 register" hexmask.long 0x4 0.--31. 1. "LBN_MISRR1,Offline LBIST MISRR_1 value" line.long 0x8 "STCU_LBN_MISRR2,STCU LBISTn Offline misrr_2 register" hexmask.long.word 0x8 0.--15. 1. "LBN_MISRR2,Offline LBIST MISRR_2 value" group.long 0x38++0xB line.long 0x0 "STCU_LBSWN_MISRE0,STCU LBISTn Online misre_0 register" hexmask.long 0x0 0.--31. 1. "LBSWN_MISRE0,Online LBIST MISRE_0 value" line.long 0x4 "STCU_LBSWN_MISRE1,STCU LBISTn Online misre_1 register" hexmask.long 0x4 0.--31. 1. "LBSWN_MISRE1,Online LBIST MISRE_1 value" line.long 0x8 "STCU_LBSWN_MISRE2,STCU LBISTn Online misre_2 register" hexmask.long.word 0x8 0.--15. 1. "LBSWN_MISRE2,Online LBIST MISRE_2 value" rgroup.long 0x48++0xB line.long 0x0 "STCU_LBSWN_MISRR0,STCU LBISTn Online misrr_0 register" hexmask.long 0x0 0.--31. 1. "LBSWN_MISRR0,Online LBIST MISRR_0 value" line.long 0x4 "STCU_LBSWN_MISRR1,STCU LBISTn Online misrr_1 register" hexmask.long 0x4 0.--31. 1. "LBSWN_MISRR1,Online LBIST MISRR_1 value" line.long 0x8 "STCU_LBSWN_MISRR2,STCU LBISTn Online misrr_2 register" hexmask.long.word 0x8 0.--15. 1. "LBSWN_MISRR2,Online LBIST MISRR_2 value" tree.end tree "LBIST_CONFIG_ADDRBLK0" base ad:0x710A4084 group.long 0x0++0x13 line.long 0x0 "STCU_LBN_CFG,STCU LBISTn configuration register" bitfld.long 0x0 18. "LOW_POWER,Required in functional mode to reduce power consumption." "0,1" bitfld.long 0x0 16.--17. "TEST_MODE,Defines the type of test to be performed by LBIST controller." "0: Reserved,1: Reserved,?,?" hexmask.long.byte 0x0 0.--7. 1. "SHIFT_LEN,Defines the scan chain length for LBIST controller configuration." line.long 0x4 "STCU_LBN_PC,STCU LBISTn pattern count register" hexmask.long.word 0x4 0.--15. 1. "PC,Defines the pattern count value for LBIST controller configuration." line.long 0x8 "STCU_LBN_SEED0,STCU LBIST seed_0 register" hexmask.long 0x8 0.--31. 1. "LBN_SEED0,LBIST SEED_0 value" line.long 0xC "STCU_LBN_SEED1,STCU LBIST seed_1 register" hexmask.long 0xC 0.--31. 1. "LBN_SEED1,LBIST SEED_1 value" line.long 0x10 "STCU_LBN_SEED2,STCU LBIST seed_2 register" hexmask.long.word 0x10 0.--15. 1. "LBN_SEED2,LBIST SEED_2 value" group.long 0x18++0xB line.long 0x0 "STCU_LBN_MISRE0,STCU LBISTn Offline misre_0 register" hexmask.long 0x0 0.--31. 1. "LBN_MISRE0,Offline LBIST MISRE_0 value" line.long 0x4 "STCU_LBN_MISRE1,STCU LBISTn Offline misre_1 register" hexmask.long 0x4 0.--31. 1. "LBN_MISRE1,Offline LBIST MISRE_1 value" line.long 0x8 "STCU_LBN_MISRE2,STCU LBISTn Offline misre_2 register" hexmask.long.word 0x8 0.--15. 1. "LBN_MISRE2,Offline LBIST MISRE_2 value" rgroup.long 0x28++0xB line.long 0x0 "STCU_LBN_MISRR0,STCU LBISTn Offline misrr_0 register" hexmask.long 0x0 0.--31. 1. "LBN_MISRR0,Offline LBIST MISRR_0 value" line.long 0x4 "STCU_LBN_MISRR1,STCU LBISTn Offline misrr_1 register" hexmask.long 0x4 0.--31. 1. "LBN_MISRR1,Offline LBIST MISRR_1 value" line.long 0x8 "STCU_LBN_MISRR2,STCU LBISTn Offline misrr_2 register" hexmask.long.word 0x8 0.--15. 1. "LBN_MISRR2,Offline LBIST MISRR_2 value" group.long 0x38++0xB line.long 0x0 "STCU_LBSWN_MISRE0,STCU LBISTn Online misre_0 register" hexmask.long 0x0 0.--31. 1. "LBSWN_MISRE0,Online LBIST MISRE_0 value" line.long 0x4 "STCU_LBSWN_MISRE1,STCU LBISTn Online misre_1 register" hexmask.long 0x4 0.--31. 1. "LBSWN_MISRE1,Online LBIST MISRE_1 value" line.long 0x8 "STCU_LBSWN_MISRE2,STCU LBISTn Online misre_2 register" hexmask.long.word 0x8 0.--15. 1. "LBSWN_MISRE2,Online LBIST MISRE_2 value" rgroup.long 0x48++0xB line.long 0x0 "STCU_LBSWN_MISRR0,STCU LBISTn Online misrr_0 register" hexmask.long 0x0 0.--31. 1. "LBSWN_MISRR0,Online LBIST MISRR_0 value" line.long 0x4 "STCU_LBSWN_MISRR1,STCU LBISTn Online misrr_1 register" hexmask.long 0x4 0.--31. 1. "LBSWN_MISRR1,Online LBIST MISRR_1 value" line.long 0x8 "STCU_LBSWN_MISRR2,STCU LBISTn Online misrr_2 register" hexmask.long.word 0x8 0.--15. 1. "LBSWN_MISRR2,Online LBIST MISRR_2 value" tree.end tree "LBIST_PTR" base ad:0x710A7000 group.long 0x0++0x3 line.long 0x0 "STCU_LBIST0_PTR,STCU LBISTn pointer register" hexmask.long.byte 0x0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next LBIST partition for BIST execution. The size of this field depends on the number of LBISTs partitions present on the device." bitfld.long 0x0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" tree.end tree "LBIST_PTR_ADDRBLK" base ad:0x710A7000 group.long 0x0++0x3 line.long 0x0 "STCU_LBIST0_PTR,STCU LBISTn pointer register" hexmask.long.byte 0x0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next LBIST partition for BIST execution. The size of this field depends on the number of LBISTs partitions present on the device." bitfld.long 0x0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" tree.end tree "MBIST_CONFIG" base ad:0x710A4604 repeat 13. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "STCU_MBN_TM[$1],STCU MBISTn test mode selction register" bitfld.long 0x0 1. "MBU,0 : MBIST full algorithm or reduced one without PMOS test (PMOSEN set to 0) is applied." "0: MBIST full algorithm or reduced one without PMOS..,1: MBIST simplified multi-bit upset algorithm is.." bitfld.long 0x0 0. "PMOSEN,0 : MBIST PMOS test is not enabled." "0: MBIST PMOS test is not enabled,1: MBIST PMOS test is enabled" repeat.end tree.end tree "MBIST_CONFIG_ADDRBLK" base ad:0x710A4604 group.long 0x0++0x33 line.long 0x0 "STCU_MB0_TM,STCU MBISTn test mode selction register" bitfld.long 0x0 1. "MBU,0 : MBIST full algorithm or reduced one without PMOS test (PMOSEN set to 0) is applied." "0: MBIST full algorithm or reduced one without PMOS..,1: MBIST simplified multi-bit upset algorithm is.." bitfld.long 0x0 0. "PMOSEN,0 : MBIST PMOS test is not enabled." "0: MBIST PMOS test is not enabled,1: MBIST PMOS test is enabled" line.long 0x4 "STCU_MB1_TM,STCU MBISTn test mode selction register" bitfld.long 0x4 1. "MBU,0 : MBIST full algorithm or reduced one without PMOS test (PMOSEN set to 0) is applied." "0: MBIST full algorithm or reduced one without PMOS..,1: MBIST simplified multi-bit upset algorithm is.." bitfld.long 0x4 0. "PMOSEN,0 : MBIST PMOS test is not enabled." "0: MBIST PMOS test is not enabled,1: MBIST PMOS test is enabled" line.long 0x8 "STCU_MB2_TM,STCU MBISTn test mode selction register" bitfld.long 0x8 1. "MBU,0 : MBIST full algorithm or reduced one without PMOS test (PMOSEN set to 0) is applied." "0: MBIST full algorithm or reduced one without PMOS..,1: MBIST simplified multi-bit upset algorithm is.." bitfld.long 0x8 0. "PMOSEN,0 : MBIST PMOS test is not enabled." "0: MBIST PMOS test is not enabled,1: MBIST PMOS test is enabled" line.long 0xC "STCU_MB3_TM,STCU MBISTn test mode selction register" bitfld.long 0xC 1. "MBU,0 : MBIST full algorithm or reduced one without PMOS test (PMOSEN set to 0) is applied." "0: MBIST full algorithm or reduced one without PMOS..,1: MBIST simplified multi-bit upset algorithm is.." bitfld.long 0xC 0. "PMOSEN,0 : MBIST PMOS test is not enabled." "0: MBIST PMOS test is not enabled,1: MBIST PMOS test is enabled" line.long 0x10 "STCU_MB4_TM,STCU MBISTn test mode selction register" bitfld.long 0x10 1. "MBU,0 : MBIST full algorithm or reduced one without PMOS test (PMOSEN set to 0) is applied." "0: MBIST full algorithm or reduced one without PMOS..,1: MBIST simplified multi-bit upset algorithm is.." bitfld.long 0x10 0. "PMOSEN,0 : MBIST PMOS test is not enabled." "0: MBIST PMOS test is not enabled,1: MBIST PMOS test is enabled" line.long 0x14 "STCU_MB5_TM,STCU MBISTn test mode selction register" bitfld.long 0x14 1. "MBU,0 : MBIST full algorithm or reduced one without PMOS test (PMOSEN set to 0) is applied." "0: MBIST full algorithm or reduced one without PMOS..,1: MBIST simplified multi-bit upset algorithm is.." bitfld.long 0x14 0. "PMOSEN,0 : MBIST PMOS test is not enabled." "0: MBIST PMOS test is not enabled,1: MBIST PMOS test is enabled" line.long 0x18 "STCU_MB6_TM,STCU MBISTn test mode selction register" bitfld.long 0x18 1. "MBU,0 : MBIST full algorithm or reduced one without PMOS test (PMOSEN set to 0) is applied." "0: MBIST full algorithm or reduced one without PMOS..,1: MBIST simplified multi-bit upset algorithm is.." bitfld.long 0x18 0. "PMOSEN,0 : MBIST PMOS test is not enabled." "0: MBIST PMOS test is not enabled,1: MBIST PMOS test is enabled" line.long 0x1C "STCU_MB7_TM,STCU MBISTn test mode selction register" bitfld.long 0x1C 1. "MBU,0 : MBIST full algorithm or reduced one without PMOS test (PMOSEN set to 0) is applied." "0: MBIST full algorithm or reduced one without PMOS..,1: MBIST simplified multi-bit upset algorithm is.." bitfld.long 0x1C 0. "PMOSEN,0 : MBIST PMOS test is not enabled." "0: MBIST PMOS test is not enabled,1: MBIST PMOS test is enabled" line.long 0x20 "STCU_MB8_TM,STCU MBISTn test mode selction register" bitfld.long 0x20 1. "MBU,0 : MBIST full algorithm or reduced one without PMOS test (PMOSEN set to 0) is applied." "0: MBIST full algorithm or reduced one without PMOS..,1: MBIST simplified multi-bit upset algorithm is.." bitfld.long 0x20 0. "PMOSEN,0 : MBIST PMOS test is not enabled." "0: MBIST PMOS test is not enabled,1: MBIST PMOS test is enabled" line.long 0x24 "STCU_MB9_TM,STCU MBISTn test mode selction register" bitfld.long 0x24 1. "MBU,0 : MBIST full algorithm or reduced one without PMOS test (PMOSEN set to 0) is applied." "0: MBIST full algorithm or reduced one without PMOS..,1: MBIST simplified multi-bit upset algorithm is.." bitfld.long 0x24 0. "PMOSEN,0 : MBIST PMOS test is not enabled." "0: MBIST PMOS test is not enabled,1: MBIST PMOS test is enabled" line.long 0x28 "STCU_MB10_TM,STCU MBISTn test mode selction register" bitfld.long 0x28 1. "MBU,0 : MBIST full algorithm or reduced one without PMOS test (PMOSEN set to 0) is applied." "0: MBIST full algorithm or reduced one without PMOS..,1: MBIST simplified multi-bit upset algorithm is.." bitfld.long 0x28 0. "PMOSEN,0 : MBIST PMOS test is not enabled." "0: MBIST PMOS test is not enabled,1: MBIST PMOS test is enabled" line.long 0x2C "STCU_MB11_TM,STCU MBISTn test mode selction register" bitfld.long 0x2C 1. "MBU,0 : MBIST full algorithm or reduced one without PMOS test (PMOSEN set to 0) is applied." "0: MBIST full algorithm or reduced one without PMOS..,1: MBIST simplified multi-bit upset algorithm is.." bitfld.long 0x2C 0. "PMOSEN,0 : MBIST PMOS test is not enabled." "0: MBIST PMOS test is not enabled,1: MBIST PMOS test is enabled" line.long 0x30 "STCU_MB12_TM,STCU MBISTn test mode selction register" bitfld.long 0x30 1. "MBU,0 : MBIST full algorithm or reduced one without PMOS test (PMOSEN set to 0) is applied." "0: MBIST full algorithm or reduced one without PMOS..,1: MBIST simplified multi-bit upset algorithm is.." bitfld.long 0x30 0. "PMOSEN,0 : MBIST PMOS test is not enabled." "0: MBIST PMOS test is not enabled,1: MBIST PMOS test is enabled" tree.end tree "MBIST_PTR" base ad:0x710A7040 repeat 469. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "STCU_MBISTN_PTR[$1],STCU MBISTn pointer register" bitfld.long 0x0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" repeat.end tree.end tree "MBIST_PTR_ADDRBLK" base ad:0x710A7040 group.long 0x0++0x753 line.long 0x0 "STCU_MBIST0_PTR,STCU MBISTn pointer register" bitfld.long 0x0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4 "STCU_MBIST1_PTR,STCU MBISTn pointer register" bitfld.long 0x4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x8 "STCU_MBIST2_PTR,STCU MBISTn pointer register" bitfld.long 0x8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xC "STCU_MBIST3_PTR,STCU MBISTn pointer register" bitfld.long 0xC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x10 "STCU_MBIST4_PTR,STCU MBISTn pointer register" bitfld.long 0x10 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x10 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x10 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x10 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x10 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x14 "STCU_MBIST5_PTR,STCU MBISTn pointer register" bitfld.long 0x14 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x14 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x14 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x14 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x14 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x18 "STCU_MBIST6_PTR,STCU MBISTn pointer register" bitfld.long 0x18 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x18 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x18 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x18 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x18 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1C "STCU_MBIST7_PTR,STCU MBISTn pointer register" bitfld.long 0x1C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x20 "STCU_MBIST8_PTR,STCU MBISTn pointer register" bitfld.long 0x20 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x20 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x20 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x20 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x20 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x24 "STCU_MBIST9_PTR,STCU MBISTn pointer register" bitfld.long 0x24 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x24 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x24 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x24 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x24 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x28 "STCU_MBIST10_PTR,STCU MBISTn pointer register" bitfld.long 0x28 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x28 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x28 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x28 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x28 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2C "STCU_MBIST11_PTR,STCU MBISTn pointer register" bitfld.long 0x2C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x30 "STCU_MBIST12_PTR,STCU MBISTn pointer register" bitfld.long 0x30 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x30 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x30 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x30 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x30 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x34 "STCU_MBIST13_PTR,STCU MBISTn pointer register" bitfld.long 0x34 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x34 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x34 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x34 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x34 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x38 "STCU_MBIST14_PTR,STCU MBISTn pointer register" bitfld.long 0x38 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x38 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x38 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x38 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x38 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3C "STCU_MBIST15_PTR,STCU MBISTn pointer register" bitfld.long 0x3C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x40 "STCU_MBIST16_PTR,STCU MBISTn pointer register" bitfld.long 0x40 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x40 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x40 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x40 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x40 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x44 "STCU_MBIST17_PTR,STCU MBISTn pointer register" bitfld.long 0x44 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x44 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x44 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x44 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x44 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x48 "STCU_MBIST18_PTR,STCU MBISTn pointer register" bitfld.long 0x48 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x48 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x48 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x48 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x48 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4C "STCU_MBIST19_PTR,STCU MBISTn pointer register" bitfld.long 0x4C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x50 "STCU_MBIST20_PTR,STCU MBISTn pointer register" bitfld.long 0x50 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x50 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x50 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x50 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x50 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x54 "STCU_MBIST21_PTR,STCU MBISTn pointer register" bitfld.long 0x54 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x54 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x54 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x54 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x54 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x58 "STCU_MBIST22_PTR,STCU MBISTn pointer register" bitfld.long 0x58 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x58 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x58 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x58 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x58 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5C "STCU_MBIST23_PTR,STCU MBISTn pointer register" bitfld.long 0x5C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x60 "STCU_MBIST24_PTR,STCU MBISTn pointer register" bitfld.long 0x60 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x60 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x60 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x60 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x60 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x64 "STCU_MBIST25_PTR,STCU MBISTn pointer register" bitfld.long 0x64 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x64 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x64 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x64 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x64 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x68 "STCU_MBIST26_PTR,STCU MBISTn pointer register" bitfld.long 0x68 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x68 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x68 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x68 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x68 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6C "STCU_MBIST27_PTR,STCU MBISTn pointer register" bitfld.long 0x6C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x70 "STCU_MBIST28_PTR,STCU MBISTn pointer register" bitfld.long 0x70 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x70 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x70 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x70 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x70 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x74 "STCU_MBIST29_PTR,STCU MBISTn pointer register" bitfld.long 0x74 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x74 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x74 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x74 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x74 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x78 "STCU_MBIST30_PTR,STCU MBISTn pointer register" bitfld.long 0x78 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x78 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x78 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x78 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x78 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x7C "STCU_MBIST31_PTR,STCU MBISTn pointer register" bitfld.long 0x7C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x7C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x7C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x7C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x7C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x80 "STCU_MBIST32_PTR,STCU MBISTn pointer register" bitfld.long 0x80 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x80 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x80 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x80 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x80 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x84 "STCU_MBIST33_PTR,STCU MBISTn pointer register" bitfld.long 0x84 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x84 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x84 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x84 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x84 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x88 "STCU_MBIST34_PTR,STCU MBISTn pointer register" bitfld.long 0x88 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x88 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x88 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x88 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x88 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x8C "STCU_MBIST35_PTR,STCU MBISTn pointer register" bitfld.long 0x8C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x8C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x8C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x8C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x8C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x90 "STCU_MBIST36_PTR,STCU MBISTn pointer register" bitfld.long 0x90 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x90 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x90 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x90 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x90 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x94 "STCU_MBIST37_PTR,STCU MBISTn pointer register" bitfld.long 0x94 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x94 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x94 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x94 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x94 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x98 "STCU_MBIST38_PTR,STCU MBISTn pointer register" bitfld.long 0x98 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x98 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x98 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x98 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x98 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x9C "STCU_MBIST39_PTR,STCU MBISTn pointer register" bitfld.long 0x9C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x9C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x9C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x9C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x9C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xA0 "STCU_MBIST40_PTR,STCU MBISTn pointer register" bitfld.long 0xA0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xA0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xA0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xA0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xA0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xA4 "STCU_MBIST41_PTR,STCU MBISTn pointer register" bitfld.long 0xA4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xA4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xA4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xA4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xA4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xA8 "STCU_MBIST42_PTR,STCU MBISTn pointer register" bitfld.long 0xA8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xA8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xA8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xA8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xA8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xAC "STCU_MBIST43_PTR,STCU MBISTn pointer register" bitfld.long 0xAC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xAC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xAC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xAC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xAC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xB0 "STCU_MBIST44_PTR,STCU MBISTn pointer register" bitfld.long 0xB0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xB0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xB0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xB0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xB0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xB4 "STCU_MBIST45_PTR,STCU MBISTn pointer register" bitfld.long 0xB4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xB4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xB4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xB4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xB4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xB8 "STCU_MBIST46_PTR,STCU MBISTn pointer register" bitfld.long 0xB8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xB8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xB8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xB8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xB8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xBC "STCU_MBIST47_PTR,STCU MBISTn pointer register" bitfld.long 0xBC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xBC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xBC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xBC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xBC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xC0 "STCU_MBIST48_PTR,STCU MBISTn pointer register" bitfld.long 0xC0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xC0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xC0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xC0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xC0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xC4 "STCU_MBIST49_PTR,STCU MBISTn pointer register" bitfld.long 0xC4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xC4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xC4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xC4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xC4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xC8 "STCU_MBIST50_PTR,STCU MBISTn pointer register" bitfld.long 0xC8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xC8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xC8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xC8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xC8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xCC "STCU_MBIST51_PTR,STCU MBISTn pointer register" bitfld.long 0xCC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xCC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xCC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xCC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xCC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xD0 "STCU_MBIST52_PTR,STCU MBISTn pointer register" bitfld.long 0xD0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xD0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xD0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xD0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xD0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xD4 "STCU_MBIST53_PTR,STCU MBISTn pointer register" bitfld.long 0xD4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xD4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xD4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xD4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xD4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xD8 "STCU_MBIST54_PTR,STCU MBISTn pointer register" bitfld.long 0xD8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xD8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xD8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xD8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xD8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xDC "STCU_MBIST55_PTR,STCU MBISTn pointer register" bitfld.long 0xDC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xDC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xDC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xDC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xDC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xE0 "STCU_MBIST56_PTR,STCU MBISTn pointer register" bitfld.long 0xE0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xE0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xE0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xE0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xE0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xE4 "STCU_MBIST57_PTR,STCU MBISTn pointer register" bitfld.long 0xE4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xE4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xE4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xE4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xE4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xE8 "STCU_MBIST58_PTR,STCU MBISTn pointer register" bitfld.long 0xE8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xE8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xE8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xE8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xE8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xEC "STCU_MBIST59_PTR,STCU MBISTn pointer register" bitfld.long 0xEC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xEC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xEC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xEC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xEC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xF0 "STCU_MBIST60_PTR,STCU MBISTn pointer register" bitfld.long 0xF0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xF0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xF0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xF0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xF0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xF4 "STCU_MBIST61_PTR,STCU MBISTn pointer register" bitfld.long 0xF4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xF4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xF4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xF4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xF4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xF8 "STCU_MBIST62_PTR,STCU MBISTn pointer register" bitfld.long 0xF8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xF8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xF8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xF8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xF8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0xFC "STCU_MBIST63_PTR,STCU MBISTn pointer register" bitfld.long 0xFC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0xFC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0xFC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0xFC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0xFC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x100 "STCU_MBIST64_PTR,STCU MBISTn pointer register" bitfld.long 0x100 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x100 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x100 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x100 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x100 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x104 "STCU_MBIST65_PTR,STCU MBISTn pointer register" bitfld.long 0x104 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x104 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x104 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x104 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x104 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x108 "STCU_MBIST66_PTR,STCU MBISTn pointer register" bitfld.long 0x108 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x108 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x108 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x108 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x108 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x10C "STCU_MBIST67_PTR,STCU MBISTn pointer register" bitfld.long 0x10C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x10C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x10C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x10C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x10C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x110 "STCU_MBIST68_PTR,STCU MBISTn pointer register" bitfld.long 0x110 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x110 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x110 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x110 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x110 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x114 "STCU_MBIST69_PTR,STCU MBISTn pointer register" bitfld.long 0x114 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x114 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x114 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x114 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x114 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x118 "STCU_MBIST70_PTR,STCU MBISTn pointer register" bitfld.long 0x118 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x118 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x118 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x118 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x118 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x11C "STCU_MBIST71_PTR,STCU MBISTn pointer register" bitfld.long 0x11C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x11C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x11C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x11C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x11C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x120 "STCU_MBIST72_PTR,STCU MBISTn pointer register" bitfld.long 0x120 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x120 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x120 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x120 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x120 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x124 "STCU_MBIST73_PTR,STCU MBISTn pointer register" bitfld.long 0x124 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x124 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x124 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x124 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x124 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x128 "STCU_MBIST74_PTR,STCU MBISTn pointer register" bitfld.long 0x128 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x128 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x128 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x128 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x128 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x12C "STCU_MBIST75_PTR,STCU MBISTn pointer register" bitfld.long 0x12C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x12C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x12C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x12C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x12C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x130 "STCU_MBIST76_PTR,STCU MBISTn pointer register" bitfld.long 0x130 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x130 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x130 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x130 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x130 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x134 "STCU_MBIST77_PTR,STCU MBISTn pointer register" bitfld.long 0x134 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x134 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x134 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x134 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x134 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x138 "STCU_MBIST78_PTR,STCU MBISTn pointer register" bitfld.long 0x138 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x138 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x138 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x138 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x138 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x13C "STCU_MBIST79_PTR,STCU MBISTn pointer register" bitfld.long 0x13C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x13C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x13C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x13C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x13C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x140 "STCU_MBIST80_PTR,STCU MBISTn pointer register" bitfld.long 0x140 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x140 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x140 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x140 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x140 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x144 "STCU_MBIST81_PTR,STCU MBISTn pointer register" bitfld.long 0x144 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x144 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x144 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x144 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x144 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x148 "STCU_MBIST82_PTR,STCU MBISTn pointer register" bitfld.long 0x148 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x148 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x148 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x148 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x148 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x14C "STCU_MBIST83_PTR,STCU MBISTn pointer register" bitfld.long 0x14C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x14C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x14C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x14C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x14C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x150 "STCU_MBIST84_PTR,STCU MBISTn pointer register" bitfld.long 0x150 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x150 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x150 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x150 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x150 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x154 "STCU_MBIST85_PTR,STCU MBISTn pointer register" bitfld.long 0x154 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x154 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x154 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x154 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x154 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x158 "STCU_MBIST86_PTR,STCU MBISTn pointer register" bitfld.long 0x158 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x158 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x158 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x158 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x158 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x15C "STCU_MBIST87_PTR,STCU MBISTn pointer register" bitfld.long 0x15C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x15C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x15C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x15C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x15C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x160 "STCU_MBIST88_PTR,STCU MBISTn pointer register" bitfld.long 0x160 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x160 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x160 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x160 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x160 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x164 "STCU_MBIST89_PTR,STCU MBISTn pointer register" bitfld.long 0x164 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x164 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x164 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x164 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x164 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x168 "STCU_MBIST90_PTR,STCU MBISTn pointer register" bitfld.long 0x168 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x168 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x168 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x168 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x168 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x16C "STCU_MBIST91_PTR,STCU MBISTn pointer register" bitfld.long 0x16C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x16C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x16C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x16C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x16C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x170 "STCU_MBIST92_PTR,STCU MBISTn pointer register" bitfld.long 0x170 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x170 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x170 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x170 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x170 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x174 "STCU_MBIST93_PTR,STCU MBISTn pointer register" bitfld.long 0x174 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x174 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x174 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x174 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x174 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x178 "STCU_MBIST94_PTR,STCU MBISTn pointer register" bitfld.long 0x178 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x178 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x178 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x178 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x178 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x17C "STCU_MBIST95_PTR,STCU MBISTn pointer register" bitfld.long 0x17C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x17C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x17C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x17C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x17C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x180 "STCU_MBIST96_PTR,STCU MBISTn pointer register" bitfld.long 0x180 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x180 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x180 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x180 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x180 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x184 "STCU_MBIST97_PTR,STCU MBISTn pointer register" bitfld.long 0x184 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x184 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x184 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x184 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x184 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x188 "STCU_MBIST98_PTR,STCU MBISTn pointer register" bitfld.long 0x188 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x188 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x188 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x188 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x188 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x18C "STCU_MBIST99_PTR,STCU MBISTn pointer register" bitfld.long 0x18C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x18C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x18C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x18C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x18C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x190 "STCU_MBIST100_PTR,STCU MBISTn pointer register" bitfld.long 0x190 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x190 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x190 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x190 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x190 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x194 "STCU_MBIST101_PTR,STCU MBISTn pointer register" bitfld.long 0x194 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x194 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x194 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x194 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x194 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x198 "STCU_MBIST102_PTR,STCU MBISTn pointer register" bitfld.long 0x198 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x198 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x198 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x198 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x198 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x19C "STCU_MBIST103_PTR,STCU MBISTn pointer register" bitfld.long 0x19C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x19C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x19C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x19C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x19C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1A0 "STCU_MBIST104_PTR,STCU MBISTn pointer register" bitfld.long 0x1A0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1A0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1A0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1A0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1A0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1A4 "STCU_MBIST105_PTR,STCU MBISTn pointer register" bitfld.long 0x1A4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1A4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1A4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1A4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1A4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1A8 "STCU_MBIST106_PTR,STCU MBISTn pointer register" bitfld.long 0x1A8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1A8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1A8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1A8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1A8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1AC "STCU_MBIST107_PTR,STCU MBISTn pointer register" bitfld.long 0x1AC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1AC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1AC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1AC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1AC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1B0 "STCU_MBIST108_PTR,STCU MBISTn pointer register" bitfld.long 0x1B0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1B0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1B0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1B0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1B0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1B4 "STCU_MBIST109_PTR,STCU MBISTn pointer register" bitfld.long 0x1B4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1B4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1B4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1B4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1B4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1B8 "STCU_MBIST110_PTR,STCU MBISTn pointer register" bitfld.long 0x1B8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1B8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1B8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1B8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1B8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1BC "STCU_MBIST111_PTR,STCU MBISTn pointer register" bitfld.long 0x1BC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1BC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1BC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1BC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1BC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1C0 "STCU_MBIST112_PTR,STCU MBISTn pointer register" bitfld.long 0x1C0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1C0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1C0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1C0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1C0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1C4 "STCU_MBIST113_PTR,STCU MBISTn pointer register" bitfld.long 0x1C4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1C4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1C4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1C4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1C4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1C8 "STCU_MBIST114_PTR,STCU MBISTn pointer register" bitfld.long 0x1C8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1C8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1C8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1C8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1C8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1CC "STCU_MBIST115_PTR,STCU MBISTn pointer register" bitfld.long 0x1CC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1CC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1CC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1CC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1CC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1D0 "STCU_MBIST116_PTR,STCU MBISTn pointer register" bitfld.long 0x1D0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1D0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1D0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1D0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1D0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1D4 "STCU_MBIST117_PTR,STCU MBISTn pointer register" bitfld.long 0x1D4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1D4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1D4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1D4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1D4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1D8 "STCU_MBIST118_PTR,STCU MBISTn pointer register" bitfld.long 0x1D8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1D8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1D8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1D8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1D8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1DC "STCU_MBIST119_PTR,STCU MBISTn pointer register" bitfld.long 0x1DC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1DC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1DC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1DC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1DC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1E0 "STCU_MBIST120_PTR,STCU MBISTn pointer register" bitfld.long 0x1E0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1E0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1E0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1E0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1E0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1E4 "STCU_MBIST121_PTR,STCU MBISTn pointer register" bitfld.long 0x1E4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1E4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1E4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1E4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1E4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1E8 "STCU_MBIST122_PTR,STCU MBISTn pointer register" bitfld.long 0x1E8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1E8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1E8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1E8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1E8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1EC "STCU_MBIST123_PTR,STCU MBISTn pointer register" bitfld.long 0x1EC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1EC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1EC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1EC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1EC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1F0 "STCU_MBIST124_PTR,STCU MBISTn pointer register" bitfld.long 0x1F0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1F0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1F0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1F0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1F0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1F4 "STCU_MBIST125_PTR,STCU MBISTn pointer register" bitfld.long 0x1F4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1F4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1F4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1F4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1F4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1F8 "STCU_MBIST126_PTR,STCU MBISTn pointer register" bitfld.long 0x1F8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1F8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1F8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1F8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1F8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x1FC "STCU_MBIST127_PTR,STCU MBISTn pointer register" bitfld.long 0x1FC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x1FC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x1FC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x1FC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x1FC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x200 "STCU_MBIST128_PTR,STCU MBISTn pointer register" bitfld.long 0x200 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x200 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x200 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x200 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x200 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x204 "STCU_MBIST129_PTR,STCU MBISTn pointer register" bitfld.long 0x204 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x204 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x204 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x204 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x204 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x208 "STCU_MBIST130_PTR,STCU MBISTn pointer register" bitfld.long 0x208 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x208 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x208 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x208 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x208 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x20C "STCU_MBIST131_PTR,STCU MBISTn pointer register" bitfld.long 0x20C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x20C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x20C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x20C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x20C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x210 "STCU_MBIST132_PTR,STCU MBISTn pointer register" bitfld.long 0x210 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x210 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x210 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x210 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x210 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x214 "STCU_MBIST133_PTR,STCU MBISTn pointer register" bitfld.long 0x214 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x214 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x214 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x214 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x214 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x218 "STCU_MBIST134_PTR,STCU MBISTn pointer register" bitfld.long 0x218 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x218 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x218 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x218 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x218 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x21C "STCU_MBIST135_PTR,STCU MBISTn pointer register" bitfld.long 0x21C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x21C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x21C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x21C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x21C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x220 "STCU_MBIST136_PTR,STCU MBISTn pointer register" bitfld.long 0x220 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x220 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x220 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x220 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x220 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x224 "STCU_MBIST137_PTR,STCU MBISTn pointer register" bitfld.long 0x224 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x224 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x224 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x224 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x224 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x228 "STCU_MBIST138_PTR,STCU MBISTn pointer register" bitfld.long 0x228 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x228 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x228 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x228 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x228 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x22C "STCU_MBIST139_PTR,STCU MBISTn pointer register" bitfld.long 0x22C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x22C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x22C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x22C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x22C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x230 "STCU_MBIST140_PTR,STCU MBISTn pointer register" bitfld.long 0x230 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x230 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x230 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x230 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x230 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x234 "STCU_MBIST141_PTR,STCU MBISTn pointer register" bitfld.long 0x234 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x234 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x234 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x234 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x234 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x238 "STCU_MBIST142_PTR,STCU MBISTn pointer register" bitfld.long 0x238 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x238 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x238 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x238 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x238 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x23C "STCU_MBIST143_PTR,STCU MBISTn pointer register" bitfld.long 0x23C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x23C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x23C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x23C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x23C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x240 "STCU_MBIST144_PTR,STCU MBISTn pointer register" bitfld.long 0x240 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x240 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x240 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x240 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x240 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x244 "STCU_MBIST145_PTR,STCU MBISTn pointer register" bitfld.long 0x244 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x244 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x244 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x244 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x244 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x248 "STCU_MBIST146_PTR,STCU MBISTn pointer register" bitfld.long 0x248 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x248 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x248 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x248 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x248 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x24C "STCU_MBIST147_PTR,STCU MBISTn pointer register" bitfld.long 0x24C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x24C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x24C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x24C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x24C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x250 "STCU_MBIST148_PTR,STCU MBISTn pointer register" bitfld.long 0x250 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x250 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x250 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x250 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x250 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x254 "STCU_MBIST149_PTR,STCU MBISTn pointer register" bitfld.long 0x254 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x254 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x254 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x254 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x254 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x258 "STCU_MBIST150_PTR,STCU MBISTn pointer register" bitfld.long 0x258 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x258 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x258 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x258 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x258 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x25C "STCU_MBIST151_PTR,STCU MBISTn pointer register" bitfld.long 0x25C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x25C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x25C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x25C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x25C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x260 "STCU_MBIST152_PTR,STCU MBISTn pointer register" bitfld.long 0x260 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x260 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x260 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x260 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x260 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x264 "STCU_MBIST153_PTR,STCU MBISTn pointer register" bitfld.long 0x264 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x264 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x264 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x264 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x264 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x268 "STCU_MBIST154_PTR,STCU MBISTn pointer register" bitfld.long 0x268 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x268 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x268 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x268 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x268 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x26C "STCU_MBIST155_PTR,STCU MBISTn pointer register" bitfld.long 0x26C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x26C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x26C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x26C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x26C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x270 "STCU_MBIST156_PTR,STCU MBISTn pointer register" bitfld.long 0x270 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x270 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x270 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x270 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x270 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x274 "STCU_MBIST157_PTR,STCU MBISTn pointer register" bitfld.long 0x274 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x274 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x274 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x274 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x274 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x278 "STCU_MBIST158_PTR,STCU MBISTn pointer register" bitfld.long 0x278 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x278 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x278 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x278 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x278 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x27C "STCU_MBIST159_PTR,STCU MBISTn pointer register" bitfld.long 0x27C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x27C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x27C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x27C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x27C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x280 "STCU_MBIST160_PTR,STCU MBISTn pointer register" bitfld.long 0x280 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x280 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x280 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x280 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x280 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x284 "STCU_MBIST161_PTR,STCU MBISTn pointer register" bitfld.long 0x284 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x284 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x284 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x284 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x284 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x288 "STCU_MBIST162_PTR,STCU MBISTn pointer register" bitfld.long 0x288 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x288 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x288 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x288 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x288 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x28C "STCU_MBIST163_PTR,STCU MBISTn pointer register" bitfld.long 0x28C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x28C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x28C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x28C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x28C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x290 "STCU_MBIST164_PTR,STCU MBISTn pointer register" bitfld.long 0x290 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x290 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x290 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x290 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x290 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x294 "STCU_MBIST165_PTR,STCU MBISTn pointer register" bitfld.long 0x294 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x294 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x294 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x294 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x294 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x298 "STCU_MBIST166_PTR,STCU MBISTn pointer register" bitfld.long 0x298 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x298 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x298 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x298 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x298 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x29C "STCU_MBIST167_PTR,STCU MBISTn pointer register" bitfld.long 0x29C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x29C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x29C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x29C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x29C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2A0 "STCU_MBIST168_PTR,STCU MBISTn pointer register" bitfld.long 0x2A0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2A0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2A0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2A0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2A0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2A4 "STCU_MBIST169_PTR,STCU MBISTn pointer register" bitfld.long 0x2A4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2A4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2A4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2A4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2A4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2A8 "STCU_MBIST170_PTR,STCU MBISTn pointer register" bitfld.long 0x2A8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2A8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2A8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2A8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2A8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2AC "STCU_MBIST171_PTR,STCU MBISTn pointer register" bitfld.long 0x2AC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2AC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2AC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2AC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2AC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2B0 "STCU_MBIST172_PTR,STCU MBISTn pointer register" bitfld.long 0x2B0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2B0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2B0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2B0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2B0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2B4 "STCU_MBIST173_PTR,STCU MBISTn pointer register" bitfld.long 0x2B4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2B4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2B4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2B4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2B4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2B8 "STCU_MBIST174_PTR,STCU MBISTn pointer register" bitfld.long 0x2B8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2B8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2B8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2B8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2B8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2BC "STCU_MBIST175_PTR,STCU MBISTn pointer register" bitfld.long 0x2BC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2BC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2BC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2BC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2BC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2C0 "STCU_MBIST176_PTR,STCU MBISTn pointer register" bitfld.long 0x2C0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2C0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2C0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2C0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2C0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2C4 "STCU_MBIST177_PTR,STCU MBISTn pointer register" bitfld.long 0x2C4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2C4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2C4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2C4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2C4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2C8 "STCU_MBIST178_PTR,STCU MBISTn pointer register" bitfld.long 0x2C8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2C8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2C8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2C8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2C8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2CC "STCU_MBIST179_PTR,STCU MBISTn pointer register" bitfld.long 0x2CC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2CC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2CC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2CC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2CC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2D0 "STCU_MBIST180_PTR,STCU MBISTn pointer register" bitfld.long 0x2D0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2D0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2D0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2D0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2D0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2D4 "STCU_MBIST181_PTR,STCU MBISTn pointer register" bitfld.long 0x2D4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2D4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2D4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2D4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2D4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2D8 "STCU_MBIST182_PTR,STCU MBISTn pointer register" bitfld.long 0x2D8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2D8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2D8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2D8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2D8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2DC "STCU_MBIST183_PTR,STCU MBISTn pointer register" bitfld.long 0x2DC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2DC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2DC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2DC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2DC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2E0 "STCU_MBIST184_PTR,STCU MBISTn pointer register" bitfld.long 0x2E0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2E0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2E0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2E0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2E0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2E4 "STCU_MBIST185_PTR,STCU MBISTn pointer register" bitfld.long 0x2E4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2E4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2E4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2E4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2E4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2E8 "STCU_MBIST186_PTR,STCU MBISTn pointer register" bitfld.long 0x2E8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2E8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2E8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2E8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2E8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2EC "STCU_MBIST187_PTR,STCU MBISTn pointer register" bitfld.long 0x2EC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2EC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2EC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2EC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2EC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2F0 "STCU_MBIST188_PTR,STCU MBISTn pointer register" bitfld.long 0x2F0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2F0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2F0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2F0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2F0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2F4 "STCU_MBIST189_PTR,STCU MBISTn pointer register" bitfld.long 0x2F4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2F4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2F4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2F4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2F4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2F8 "STCU_MBIST190_PTR,STCU MBISTn pointer register" bitfld.long 0x2F8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2F8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2F8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2F8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2F8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x2FC "STCU_MBIST191_PTR,STCU MBISTn pointer register" bitfld.long 0x2FC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x2FC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x2FC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x2FC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x2FC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x300 "STCU_MBIST192_PTR,STCU MBISTn pointer register" bitfld.long 0x300 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x300 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x300 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x300 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x300 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x304 "STCU_MBIST193_PTR,STCU MBISTn pointer register" bitfld.long 0x304 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x304 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x304 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x304 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x304 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x308 "STCU_MBIST194_PTR,STCU MBISTn pointer register" bitfld.long 0x308 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x308 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x308 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x308 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x308 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x30C "STCU_MBIST195_PTR,STCU MBISTn pointer register" bitfld.long 0x30C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x30C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x30C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x30C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x30C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x310 "STCU_MBIST196_PTR,STCU MBISTn pointer register" bitfld.long 0x310 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x310 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x310 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x310 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x310 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x314 "STCU_MBIST197_PTR,STCU MBISTn pointer register" bitfld.long 0x314 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x314 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x314 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x314 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x314 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x318 "STCU_MBIST198_PTR,STCU MBISTn pointer register" bitfld.long 0x318 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x318 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x318 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x318 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x318 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x31C "STCU_MBIST199_PTR,STCU MBISTn pointer register" bitfld.long 0x31C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x31C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x31C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x31C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x31C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x320 "STCU_MBIST200_PTR,STCU MBISTn pointer register" bitfld.long 0x320 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x320 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x320 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x320 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x320 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x324 "STCU_MBIST201_PTR,STCU MBISTn pointer register" bitfld.long 0x324 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x324 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x324 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x324 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x324 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x328 "STCU_MBIST202_PTR,STCU MBISTn pointer register" bitfld.long 0x328 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x328 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x328 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x328 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x328 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x32C "STCU_MBIST203_PTR,STCU MBISTn pointer register" bitfld.long 0x32C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x32C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x32C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x32C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x32C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x330 "STCU_MBIST204_PTR,STCU MBISTn pointer register" bitfld.long 0x330 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x330 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x330 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x330 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x330 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x334 "STCU_MBIST205_PTR,STCU MBISTn pointer register" bitfld.long 0x334 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x334 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x334 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x334 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x334 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x338 "STCU_MBIST206_PTR,STCU MBISTn pointer register" bitfld.long 0x338 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x338 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x338 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x338 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x338 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x33C "STCU_MBIST207_PTR,STCU MBISTn pointer register" bitfld.long 0x33C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x33C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x33C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x33C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x33C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x340 "STCU_MBIST208_PTR,STCU MBISTn pointer register" bitfld.long 0x340 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x340 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x340 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x340 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x340 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x344 "STCU_MBIST209_PTR,STCU MBISTn pointer register" bitfld.long 0x344 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x344 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x344 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x344 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x344 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x348 "STCU_MBIST210_PTR,STCU MBISTn pointer register" bitfld.long 0x348 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x348 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x348 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x348 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x348 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x34C "STCU_MBIST211_PTR,STCU MBISTn pointer register" bitfld.long 0x34C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x34C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x34C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x34C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x34C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x350 "STCU_MBIST212_PTR,STCU MBISTn pointer register" bitfld.long 0x350 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x350 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x350 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x350 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x350 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x354 "STCU_MBIST213_PTR,STCU MBISTn pointer register" bitfld.long 0x354 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x354 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x354 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x354 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x354 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x358 "STCU_MBIST214_PTR,STCU MBISTn pointer register" bitfld.long 0x358 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x358 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x358 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x358 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x358 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x35C "STCU_MBIST215_PTR,STCU MBISTn pointer register" bitfld.long 0x35C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x35C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x35C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x35C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x35C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x360 "STCU_MBIST216_PTR,STCU MBISTn pointer register" bitfld.long 0x360 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x360 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x360 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x360 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x360 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x364 "STCU_MBIST217_PTR,STCU MBISTn pointer register" bitfld.long 0x364 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x364 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x364 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x364 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x364 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x368 "STCU_MBIST218_PTR,STCU MBISTn pointer register" bitfld.long 0x368 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x368 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x368 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x368 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x368 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x36C "STCU_MBIST219_PTR,STCU MBISTn pointer register" bitfld.long 0x36C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x36C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x36C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x36C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x36C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x370 "STCU_MBIST220_PTR,STCU MBISTn pointer register" bitfld.long 0x370 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x370 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x370 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x370 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x370 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x374 "STCU_MBIST221_PTR,STCU MBISTn pointer register" bitfld.long 0x374 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x374 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x374 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x374 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x374 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x378 "STCU_MBIST222_PTR,STCU MBISTn pointer register" bitfld.long 0x378 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x378 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x378 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x378 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x378 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x37C "STCU_MBIST223_PTR,STCU MBISTn pointer register" bitfld.long 0x37C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x37C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x37C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x37C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x37C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x380 "STCU_MBIST224_PTR,STCU MBISTn pointer register" bitfld.long 0x380 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x380 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x380 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x380 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x380 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x384 "STCU_MBIST225_PTR,STCU MBISTn pointer register" bitfld.long 0x384 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x384 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x384 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x384 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x384 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x388 "STCU_MBIST226_PTR,STCU MBISTn pointer register" bitfld.long 0x388 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x388 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x388 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x388 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x388 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x38C "STCU_MBIST227_PTR,STCU MBISTn pointer register" bitfld.long 0x38C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x38C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x38C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x38C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x38C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x390 "STCU_MBIST228_PTR,STCU MBISTn pointer register" bitfld.long 0x390 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x390 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x390 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x390 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x390 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x394 "STCU_MBIST229_PTR,STCU MBISTn pointer register" bitfld.long 0x394 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x394 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x394 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x394 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x394 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x398 "STCU_MBIST230_PTR,STCU MBISTn pointer register" bitfld.long 0x398 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x398 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x398 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x398 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x398 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x39C "STCU_MBIST231_PTR,STCU MBISTn pointer register" bitfld.long 0x39C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x39C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x39C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x39C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x39C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3A0 "STCU_MBIST232_PTR,STCU MBISTn pointer register" bitfld.long 0x3A0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3A0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3A0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3A0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3A0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3A4 "STCU_MBIST233_PTR,STCU MBISTn pointer register" bitfld.long 0x3A4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3A4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3A4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3A4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3A4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3A8 "STCU_MBIST234_PTR,STCU MBISTn pointer register" bitfld.long 0x3A8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3A8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3A8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3A8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3A8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3AC "STCU_MBIST235_PTR,STCU MBISTn pointer register" bitfld.long 0x3AC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3AC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3AC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3AC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3AC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3B0 "STCU_MBIST236_PTR,STCU MBISTn pointer register" bitfld.long 0x3B0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3B0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3B0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3B0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3B0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3B4 "STCU_MBIST237_PTR,STCU MBISTn pointer register" bitfld.long 0x3B4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3B4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3B4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3B4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3B4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3B8 "STCU_MBIST238_PTR,STCU MBISTn pointer register" bitfld.long 0x3B8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3B8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3B8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3B8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3B8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3BC "STCU_MBIST239_PTR,STCU MBISTn pointer register" bitfld.long 0x3BC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3BC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3BC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3BC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3BC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3C0 "STCU_MBIST240_PTR,STCU MBISTn pointer register" bitfld.long 0x3C0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3C0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3C0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3C0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3C0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3C4 "STCU_MBIST241_PTR,STCU MBISTn pointer register" bitfld.long 0x3C4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3C4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3C4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3C4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3C4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3C8 "STCU_MBIST242_PTR,STCU MBISTn pointer register" bitfld.long 0x3C8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3C8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3C8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3C8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3C8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3CC "STCU_MBIST243_PTR,STCU MBISTn pointer register" bitfld.long 0x3CC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3CC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3CC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3CC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3CC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3D0 "STCU_MBIST244_PTR,STCU MBISTn pointer register" bitfld.long 0x3D0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3D0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3D0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3D0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3D0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3D4 "STCU_MBIST245_PTR,STCU MBISTn pointer register" bitfld.long 0x3D4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3D4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3D4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3D4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3D4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3D8 "STCU_MBIST246_PTR,STCU MBISTn pointer register" bitfld.long 0x3D8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3D8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3D8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3D8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3D8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3DC "STCU_MBIST247_PTR,STCU MBISTn pointer register" bitfld.long 0x3DC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3DC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3DC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3DC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3DC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3E0 "STCU_MBIST248_PTR,STCU MBISTn pointer register" bitfld.long 0x3E0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3E0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3E0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3E0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3E0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3E4 "STCU_MBIST249_PTR,STCU MBISTn pointer register" bitfld.long 0x3E4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3E4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3E4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3E4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3E4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3E8 "STCU_MBIST250_PTR,STCU MBISTn pointer register" bitfld.long 0x3E8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3E8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3E8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3E8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3E8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3EC "STCU_MBIST251_PTR,STCU MBISTn pointer register" bitfld.long 0x3EC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3EC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3EC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3EC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3EC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3F0 "STCU_MBIST252_PTR,STCU MBISTn pointer register" bitfld.long 0x3F0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3F0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3F0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3F0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3F0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3F4 "STCU_MBIST253_PTR,STCU MBISTn pointer register" bitfld.long 0x3F4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3F4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3F4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3F4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3F4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3F8 "STCU_MBIST254_PTR,STCU MBISTn pointer register" bitfld.long 0x3F8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3F8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3F8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3F8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3F8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x3FC "STCU_MBIST255_PTR,STCU MBISTn pointer register" bitfld.long 0x3FC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x3FC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x3FC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x3FC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x3FC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x400 "STCU_MBIST256_PTR,STCU MBISTn pointer register" bitfld.long 0x400 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x400 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x400 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x400 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x400 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x404 "STCU_MBIST257_PTR,STCU MBISTn pointer register" bitfld.long 0x404 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x404 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x404 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x404 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x404 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x408 "STCU_MBIST258_PTR,STCU MBISTn pointer register" bitfld.long 0x408 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x408 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x408 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x408 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x408 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x40C "STCU_MBIST259_PTR,STCU MBISTn pointer register" bitfld.long 0x40C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x40C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x40C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x40C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x40C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x410 "STCU_MBIST260_PTR,STCU MBISTn pointer register" bitfld.long 0x410 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x410 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x410 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x410 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x410 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x414 "STCU_MBIST261_PTR,STCU MBISTn pointer register" bitfld.long 0x414 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x414 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x414 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x414 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x414 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x418 "STCU_MBIST262_PTR,STCU MBISTn pointer register" bitfld.long 0x418 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x418 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x418 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x418 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x418 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x41C "STCU_MBIST263_PTR,STCU MBISTn pointer register" bitfld.long 0x41C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x41C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x41C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x41C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x41C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x420 "STCU_MBIST264_PTR,STCU MBISTn pointer register" bitfld.long 0x420 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x420 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x420 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x420 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x420 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x424 "STCU_MBIST265_PTR,STCU MBISTn pointer register" bitfld.long 0x424 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x424 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x424 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x424 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x424 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x428 "STCU_MBIST266_PTR,STCU MBISTn pointer register" bitfld.long 0x428 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x428 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x428 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x428 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x428 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x42C "STCU_MBIST267_PTR,STCU MBISTn pointer register" bitfld.long 0x42C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x42C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x42C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x42C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x42C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x430 "STCU_MBIST268_PTR,STCU MBISTn pointer register" bitfld.long 0x430 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x430 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x430 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x430 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x430 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x434 "STCU_MBIST269_PTR,STCU MBISTn pointer register" bitfld.long 0x434 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x434 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x434 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x434 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x434 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x438 "STCU_MBIST270_PTR,STCU MBISTn pointer register" bitfld.long 0x438 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x438 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x438 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x438 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x438 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x43C "STCU_MBIST271_PTR,STCU MBISTn pointer register" bitfld.long 0x43C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x43C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x43C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x43C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x43C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x440 "STCU_MBIST272_PTR,STCU MBISTn pointer register" bitfld.long 0x440 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x440 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x440 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x440 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x440 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x444 "STCU_MBIST273_PTR,STCU MBISTn pointer register" bitfld.long 0x444 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x444 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x444 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x444 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x444 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x448 "STCU_MBIST274_PTR,STCU MBISTn pointer register" bitfld.long 0x448 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x448 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x448 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x448 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x448 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x44C "STCU_MBIST275_PTR,STCU MBISTn pointer register" bitfld.long 0x44C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x44C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x44C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x44C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x44C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x450 "STCU_MBIST276_PTR,STCU MBISTn pointer register" bitfld.long 0x450 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x450 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x450 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x450 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x450 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x454 "STCU_MBIST277_PTR,STCU MBISTn pointer register" bitfld.long 0x454 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x454 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x454 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x454 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x454 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x458 "STCU_MBIST278_PTR,STCU MBISTn pointer register" bitfld.long 0x458 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x458 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x458 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x458 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x458 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x45C "STCU_MBIST279_PTR,STCU MBISTn pointer register" bitfld.long 0x45C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x45C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x45C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x45C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x45C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x460 "STCU_MBIST280_PTR,STCU MBISTn pointer register" bitfld.long 0x460 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x460 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x460 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x460 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x460 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x464 "STCU_MBIST281_PTR,STCU MBISTn pointer register" bitfld.long 0x464 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x464 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x464 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x464 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x464 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x468 "STCU_MBIST282_PTR,STCU MBISTn pointer register" bitfld.long 0x468 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x468 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x468 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x468 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x468 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x46C "STCU_MBIST283_PTR,STCU MBISTn pointer register" bitfld.long 0x46C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x46C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x46C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x46C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x46C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x470 "STCU_MBIST284_PTR,STCU MBISTn pointer register" bitfld.long 0x470 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x470 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x470 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x470 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x470 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x474 "STCU_MBIST285_PTR,STCU MBISTn pointer register" bitfld.long 0x474 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x474 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x474 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x474 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x474 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x478 "STCU_MBIST286_PTR,STCU MBISTn pointer register" bitfld.long 0x478 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x478 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x478 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x478 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x478 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x47C "STCU_MBIST287_PTR,STCU MBISTn pointer register" bitfld.long 0x47C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x47C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x47C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x47C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x47C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x480 "STCU_MBIST288_PTR,STCU MBISTn pointer register" bitfld.long 0x480 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x480 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x480 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x480 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x480 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x484 "STCU_MBIST289_PTR,STCU MBISTn pointer register" bitfld.long 0x484 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x484 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x484 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x484 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x484 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x488 "STCU_MBIST290_PTR,STCU MBISTn pointer register" bitfld.long 0x488 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x488 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x488 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x488 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x488 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x48C "STCU_MBIST291_PTR,STCU MBISTn pointer register" bitfld.long 0x48C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x48C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x48C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x48C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x48C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x490 "STCU_MBIST292_PTR,STCU MBISTn pointer register" bitfld.long 0x490 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x490 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x490 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x490 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x490 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x494 "STCU_MBIST293_PTR,STCU MBISTn pointer register" bitfld.long 0x494 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x494 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x494 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x494 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x494 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x498 "STCU_MBIST294_PTR,STCU MBISTn pointer register" bitfld.long 0x498 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x498 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x498 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x498 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x498 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x49C "STCU_MBIST295_PTR,STCU MBISTn pointer register" bitfld.long 0x49C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x49C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x49C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x49C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x49C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4A0 "STCU_MBIST296_PTR,STCU MBISTn pointer register" bitfld.long 0x4A0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4A0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4A0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4A0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4A0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4A4 "STCU_MBIST297_PTR,STCU MBISTn pointer register" bitfld.long 0x4A4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4A4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4A4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4A4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4A4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4A8 "STCU_MBIST298_PTR,STCU MBISTn pointer register" bitfld.long 0x4A8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4A8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4A8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4A8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4A8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4AC "STCU_MBIST299_PTR,STCU MBISTn pointer register" bitfld.long 0x4AC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4AC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4AC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4AC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4AC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4B0 "STCU_MBIST300_PTR,STCU MBISTn pointer register" bitfld.long 0x4B0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4B0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4B0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4B0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4B0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4B4 "STCU_MBIST301_PTR,STCU MBISTn pointer register" bitfld.long 0x4B4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4B4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4B4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4B4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4B4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4B8 "STCU_MBIST302_PTR,STCU MBISTn pointer register" bitfld.long 0x4B8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4B8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4B8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4B8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4B8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4BC "STCU_MBIST303_PTR,STCU MBISTn pointer register" bitfld.long 0x4BC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4BC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4BC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4BC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4BC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4C0 "STCU_MBIST304_PTR,STCU MBISTn pointer register" bitfld.long 0x4C0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4C0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4C0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4C0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4C0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4C4 "STCU_MBIST305_PTR,STCU MBISTn pointer register" bitfld.long 0x4C4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4C4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4C4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4C4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4C4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4C8 "STCU_MBIST306_PTR,STCU MBISTn pointer register" bitfld.long 0x4C8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4C8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4C8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4C8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4C8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4CC "STCU_MBIST307_PTR,STCU MBISTn pointer register" bitfld.long 0x4CC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4CC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4CC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4CC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4CC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4D0 "STCU_MBIST308_PTR,STCU MBISTn pointer register" bitfld.long 0x4D0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4D0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4D0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4D0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4D0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4D4 "STCU_MBIST309_PTR,STCU MBISTn pointer register" bitfld.long 0x4D4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4D4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4D4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4D4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4D4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4D8 "STCU_MBIST310_PTR,STCU MBISTn pointer register" bitfld.long 0x4D8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4D8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4D8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4D8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4D8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4DC "STCU_MBIST311_PTR,STCU MBISTn pointer register" bitfld.long 0x4DC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4DC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4DC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4DC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4DC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4E0 "STCU_MBIST312_PTR,STCU MBISTn pointer register" bitfld.long 0x4E0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4E0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4E0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4E0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4E0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4E4 "STCU_MBIST313_PTR,STCU MBISTn pointer register" bitfld.long 0x4E4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4E4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4E4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4E4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4E4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4E8 "STCU_MBIST314_PTR,STCU MBISTn pointer register" bitfld.long 0x4E8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4E8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4E8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4E8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4E8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4EC "STCU_MBIST315_PTR,STCU MBISTn pointer register" bitfld.long 0x4EC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4EC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4EC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4EC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4EC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4F0 "STCU_MBIST316_PTR,STCU MBISTn pointer register" bitfld.long 0x4F0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4F0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4F0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4F0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4F0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4F4 "STCU_MBIST317_PTR,STCU MBISTn pointer register" bitfld.long 0x4F4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4F4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4F4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4F4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4F4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4F8 "STCU_MBIST318_PTR,STCU MBISTn pointer register" bitfld.long 0x4F8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4F8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4F8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4F8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4F8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x4FC "STCU_MBIST319_PTR,STCU MBISTn pointer register" bitfld.long 0x4FC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x4FC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x4FC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x4FC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x4FC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x500 "STCU_MBIST320_PTR,STCU MBISTn pointer register" bitfld.long 0x500 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x500 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x500 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x500 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x500 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x504 "STCU_MBIST321_PTR,STCU MBISTn pointer register" bitfld.long 0x504 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x504 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x504 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x504 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x504 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x508 "STCU_MBIST322_PTR,STCU MBISTn pointer register" bitfld.long 0x508 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x508 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x508 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x508 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x508 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x50C "STCU_MBIST323_PTR,STCU MBISTn pointer register" bitfld.long 0x50C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x50C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x50C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x50C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x50C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x510 "STCU_MBIST324_PTR,STCU MBISTn pointer register" bitfld.long 0x510 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x510 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x510 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x510 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x510 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x514 "STCU_MBIST325_PTR,STCU MBISTn pointer register" bitfld.long 0x514 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x514 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x514 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x514 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x514 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x518 "STCU_MBIST326_PTR,STCU MBISTn pointer register" bitfld.long 0x518 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x518 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x518 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x518 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x518 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x51C "STCU_MBIST327_PTR,STCU MBISTn pointer register" bitfld.long 0x51C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x51C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x51C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x51C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x51C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x520 "STCU_MBIST328_PTR,STCU MBISTn pointer register" bitfld.long 0x520 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x520 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x520 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x520 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x520 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x524 "STCU_MBIST329_PTR,STCU MBISTn pointer register" bitfld.long 0x524 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x524 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x524 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x524 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x524 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x528 "STCU_MBIST330_PTR,STCU MBISTn pointer register" bitfld.long 0x528 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x528 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x528 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x528 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x528 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x52C "STCU_MBIST331_PTR,STCU MBISTn pointer register" bitfld.long 0x52C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x52C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x52C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x52C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x52C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x530 "STCU_MBIST332_PTR,STCU MBISTn pointer register" bitfld.long 0x530 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x530 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x530 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x530 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x530 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x534 "STCU_MBIST333_PTR,STCU MBISTn pointer register" bitfld.long 0x534 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x534 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x534 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x534 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x534 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x538 "STCU_MBIST334_PTR,STCU MBISTn pointer register" bitfld.long 0x538 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x538 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x538 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x538 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x538 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x53C "STCU_MBIST335_PTR,STCU MBISTn pointer register" bitfld.long 0x53C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x53C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x53C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x53C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x53C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x540 "STCU_MBIST336_PTR,STCU MBISTn pointer register" bitfld.long 0x540 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x540 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x540 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x540 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x540 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x544 "STCU_MBIST337_PTR,STCU MBISTn pointer register" bitfld.long 0x544 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x544 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x544 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x544 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x544 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x548 "STCU_MBIST338_PTR,STCU MBISTn pointer register" bitfld.long 0x548 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x548 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x548 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x548 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x548 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x54C "STCU_MBIST339_PTR,STCU MBISTn pointer register" bitfld.long 0x54C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x54C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x54C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x54C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x54C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x550 "STCU_MBIST340_PTR,STCU MBISTn pointer register" bitfld.long 0x550 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x550 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x550 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x550 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x550 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x554 "STCU_MBIST341_PTR,STCU MBISTn pointer register" bitfld.long 0x554 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x554 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x554 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x554 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x554 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x558 "STCU_MBIST342_PTR,STCU MBISTn pointer register" bitfld.long 0x558 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x558 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x558 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x558 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x558 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x55C "STCU_MBIST343_PTR,STCU MBISTn pointer register" bitfld.long 0x55C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x55C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x55C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x55C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x55C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x560 "STCU_MBIST344_PTR,STCU MBISTn pointer register" bitfld.long 0x560 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x560 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x560 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x560 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x560 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x564 "STCU_MBIST345_PTR,STCU MBISTn pointer register" bitfld.long 0x564 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x564 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x564 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x564 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x564 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x568 "STCU_MBIST346_PTR,STCU MBISTn pointer register" bitfld.long 0x568 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x568 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x568 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x568 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x568 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x56C "STCU_MBIST347_PTR,STCU MBISTn pointer register" bitfld.long 0x56C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x56C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x56C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x56C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x56C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x570 "STCU_MBIST348_PTR,STCU MBISTn pointer register" bitfld.long 0x570 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x570 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x570 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x570 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x570 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x574 "STCU_MBIST349_PTR,STCU MBISTn pointer register" bitfld.long 0x574 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x574 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x574 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x574 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x574 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x578 "STCU_MBIST350_PTR,STCU MBISTn pointer register" bitfld.long 0x578 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x578 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x578 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x578 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x578 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x57C "STCU_MBIST351_PTR,STCU MBISTn pointer register" bitfld.long 0x57C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x57C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x57C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x57C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x57C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x580 "STCU_MBIST352_PTR,STCU MBISTn pointer register" bitfld.long 0x580 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x580 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x580 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x580 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x580 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x584 "STCU_MBIST353_PTR,STCU MBISTn pointer register" bitfld.long 0x584 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x584 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x584 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x584 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x584 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x588 "STCU_MBIST354_PTR,STCU MBISTn pointer register" bitfld.long 0x588 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x588 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x588 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x588 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x588 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x58C "STCU_MBIST355_PTR,STCU MBISTn pointer register" bitfld.long 0x58C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x58C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x58C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x58C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x58C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x590 "STCU_MBIST356_PTR,STCU MBISTn pointer register" bitfld.long 0x590 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x590 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x590 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x590 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x590 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x594 "STCU_MBIST357_PTR,STCU MBISTn pointer register" bitfld.long 0x594 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x594 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x594 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x594 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x594 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x598 "STCU_MBIST358_PTR,STCU MBISTn pointer register" bitfld.long 0x598 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x598 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x598 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x598 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x598 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x59C "STCU_MBIST359_PTR,STCU MBISTn pointer register" bitfld.long 0x59C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x59C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x59C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x59C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x59C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5A0 "STCU_MBIST360_PTR,STCU MBISTn pointer register" bitfld.long 0x5A0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5A0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5A0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5A0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5A0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5A4 "STCU_MBIST361_PTR,STCU MBISTn pointer register" bitfld.long 0x5A4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5A4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5A4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5A4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5A4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5A8 "STCU_MBIST362_PTR,STCU MBISTn pointer register" bitfld.long 0x5A8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5A8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5A8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5A8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5A8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5AC "STCU_MBIST363_PTR,STCU MBISTn pointer register" bitfld.long 0x5AC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5AC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5AC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5AC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5AC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5B0 "STCU_MBIST364_PTR,STCU MBISTn pointer register" bitfld.long 0x5B0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5B0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5B0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5B0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5B0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5B4 "STCU_MBIST365_PTR,STCU MBISTn pointer register" bitfld.long 0x5B4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5B4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5B4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5B4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5B4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5B8 "STCU_MBIST366_PTR,STCU MBISTn pointer register" bitfld.long 0x5B8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5B8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5B8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5B8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5B8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5BC "STCU_MBIST367_PTR,STCU MBISTn pointer register" bitfld.long 0x5BC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5BC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5BC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5BC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5BC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5C0 "STCU_MBIST368_PTR,STCU MBISTn pointer register" bitfld.long 0x5C0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5C0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5C0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5C0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5C0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5C4 "STCU_MBIST369_PTR,STCU MBISTn pointer register" bitfld.long 0x5C4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5C4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5C4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5C4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5C4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5C8 "STCU_MBIST370_PTR,STCU MBISTn pointer register" bitfld.long 0x5C8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5C8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5C8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5C8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5C8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5CC "STCU_MBIST371_PTR,STCU MBISTn pointer register" bitfld.long 0x5CC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5CC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5CC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5CC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5CC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5D0 "STCU_MBIST372_PTR,STCU MBISTn pointer register" bitfld.long 0x5D0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5D0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5D0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5D0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5D0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5D4 "STCU_MBIST373_PTR,STCU MBISTn pointer register" bitfld.long 0x5D4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5D4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5D4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5D4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5D4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5D8 "STCU_MBIST374_PTR,STCU MBISTn pointer register" bitfld.long 0x5D8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5D8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5D8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5D8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5D8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5DC "STCU_MBIST375_PTR,STCU MBISTn pointer register" bitfld.long 0x5DC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5DC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5DC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5DC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5DC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5E0 "STCU_MBIST376_PTR,STCU MBISTn pointer register" bitfld.long 0x5E0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5E0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5E0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5E0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5E0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5E4 "STCU_MBIST377_PTR,STCU MBISTn pointer register" bitfld.long 0x5E4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5E4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5E4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5E4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5E4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5E8 "STCU_MBIST378_PTR,STCU MBISTn pointer register" bitfld.long 0x5E8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5E8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5E8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5E8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5E8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5EC "STCU_MBIST379_PTR,STCU MBISTn pointer register" bitfld.long 0x5EC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5EC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5EC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5EC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5EC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5F0 "STCU_MBIST380_PTR,STCU MBISTn pointer register" bitfld.long 0x5F0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5F0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5F0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5F0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5F0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5F4 "STCU_MBIST381_PTR,STCU MBISTn pointer register" bitfld.long 0x5F4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5F4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5F4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5F4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5F4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5F8 "STCU_MBIST382_PTR,STCU MBISTn pointer register" bitfld.long 0x5F8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5F8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5F8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5F8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5F8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x5FC "STCU_MBIST383_PTR,STCU MBISTn pointer register" bitfld.long 0x5FC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x5FC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x5FC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x5FC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x5FC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x600 "STCU_MBIST384_PTR,STCU MBISTn pointer register" bitfld.long 0x600 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x600 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x600 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x600 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x600 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x604 "STCU_MBIST385_PTR,STCU MBISTn pointer register" bitfld.long 0x604 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x604 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x604 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x604 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x604 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x608 "STCU_MBIST386_PTR,STCU MBISTn pointer register" bitfld.long 0x608 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x608 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x608 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x608 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x608 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x60C "STCU_MBIST387_PTR,STCU MBISTn pointer register" bitfld.long 0x60C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x60C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x60C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x60C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x60C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x610 "STCU_MBIST388_PTR,STCU MBISTn pointer register" bitfld.long 0x610 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x610 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x610 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x610 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x610 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x614 "STCU_MBIST389_PTR,STCU MBISTn pointer register" bitfld.long 0x614 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x614 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x614 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x614 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x614 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x618 "STCU_MBIST390_PTR,STCU MBISTn pointer register" bitfld.long 0x618 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x618 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x618 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x618 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x618 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x61C "STCU_MBIST391_PTR,STCU MBISTn pointer register" bitfld.long 0x61C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x61C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x61C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x61C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x61C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x620 "STCU_MBIST392_PTR,STCU MBISTn pointer register" bitfld.long 0x620 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x620 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x620 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x620 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x620 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x624 "STCU_MBIST393_PTR,STCU MBISTn pointer register" bitfld.long 0x624 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x624 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x624 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x624 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x624 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x628 "STCU_MBIST394_PTR,STCU MBISTn pointer register" bitfld.long 0x628 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x628 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x628 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x628 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x628 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x62C "STCU_MBIST395_PTR,STCU MBISTn pointer register" bitfld.long 0x62C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x62C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x62C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x62C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x62C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x630 "STCU_MBIST396_PTR,STCU MBISTn pointer register" bitfld.long 0x630 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x630 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x630 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x630 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x630 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x634 "STCU_MBIST397_PTR,STCU MBISTn pointer register" bitfld.long 0x634 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x634 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x634 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x634 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x634 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x638 "STCU_MBIST398_PTR,STCU MBISTn pointer register" bitfld.long 0x638 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x638 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x638 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x638 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x638 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x63C "STCU_MBIST399_PTR,STCU MBISTn pointer register" bitfld.long 0x63C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x63C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x63C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x63C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x63C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x640 "STCU_MBIST400_PTR,STCU MBISTn pointer register" bitfld.long 0x640 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x640 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x640 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x640 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x640 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x644 "STCU_MBIST401_PTR,STCU MBISTn pointer register" bitfld.long 0x644 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x644 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x644 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x644 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x644 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x648 "STCU_MBIST402_PTR,STCU MBISTn pointer register" bitfld.long 0x648 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x648 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x648 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x648 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x648 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x64C "STCU_MBIST403_PTR,STCU MBISTn pointer register" bitfld.long 0x64C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x64C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x64C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x64C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x64C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x650 "STCU_MBIST404_PTR,STCU MBISTn pointer register" bitfld.long 0x650 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x650 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x650 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x650 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x650 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x654 "STCU_MBIST405_PTR,STCU MBISTn pointer register" bitfld.long 0x654 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x654 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x654 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x654 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x654 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x658 "STCU_MBIST406_PTR,STCU MBISTn pointer register" bitfld.long 0x658 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x658 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x658 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x658 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x658 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x65C "STCU_MBIST407_PTR,STCU MBISTn pointer register" bitfld.long 0x65C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x65C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x65C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x65C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x65C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x660 "STCU_MBIST408_PTR,STCU MBISTn pointer register" bitfld.long 0x660 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x660 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x660 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x660 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x660 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x664 "STCU_MBIST409_PTR,STCU MBISTn pointer register" bitfld.long 0x664 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x664 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x664 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x664 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x664 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x668 "STCU_MBIST410_PTR,STCU MBISTn pointer register" bitfld.long 0x668 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x668 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x668 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x668 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x668 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x66C "STCU_MBIST411_PTR,STCU MBISTn pointer register" bitfld.long 0x66C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x66C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x66C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x66C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x66C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x670 "STCU_MBIST412_PTR,STCU MBISTn pointer register" bitfld.long 0x670 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x670 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x670 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x670 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x670 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x674 "STCU_MBIST413_PTR,STCU MBISTn pointer register" bitfld.long 0x674 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x674 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x674 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x674 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x674 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x678 "STCU_MBIST414_PTR,STCU MBISTn pointer register" bitfld.long 0x678 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x678 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x678 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x678 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x678 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x67C "STCU_MBIST415_PTR,STCU MBISTn pointer register" bitfld.long 0x67C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x67C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x67C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x67C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x67C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x680 "STCU_MBIST416_PTR,STCU MBISTn pointer register" bitfld.long 0x680 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x680 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x680 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x680 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x680 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x684 "STCU_MBIST417_PTR,STCU MBISTn pointer register" bitfld.long 0x684 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x684 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x684 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x684 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x684 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x688 "STCU_MBIST418_PTR,STCU MBISTn pointer register" bitfld.long 0x688 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x688 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x688 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x688 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x688 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x68C "STCU_MBIST419_PTR,STCU MBISTn pointer register" bitfld.long 0x68C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x68C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x68C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x68C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x68C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x690 "STCU_MBIST420_PTR,STCU MBISTn pointer register" bitfld.long 0x690 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x690 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x690 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x690 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x690 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x694 "STCU_MBIST421_PTR,STCU MBISTn pointer register" bitfld.long 0x694 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x694 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x694 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x694 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x694 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x698 "STCU_MBIST422_PTR,STCU MBISTn pointer register" bitfld.long 0x698 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x698 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x698 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x698 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x698 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x69C "STCU_MBIST423_PTR,STCU MBISTn pointer register" bitfld.long 0x69C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x69C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x69C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x69C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x69C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6A0 "STCU_MBIST424_PTR,STCU MBISTn pointer register" bitfld.long 0x6A0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6A0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6A0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6A0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6A0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6A4 "STCU_MBIST425_PTR,STCU MBISTn pointer register" bitfld.long 0x6A4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6A4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6A4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6A4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6A4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6A8 "STCU_MBIST426_PTR,STCU MBISTn pointer register" bitfld.long 0x6A8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6A8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6A8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6A8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6A8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6AC "STCU_MBIST427_PTR,STCU MBISTn pointer register" bitfld.long 0x6AC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6AC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6AC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6AC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6AC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6B0 "STCU_MBIST428_PTR,STCU MBISTn pointer register" bitfld.long 0x6B0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6B0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6B0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6B0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6B0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6B4 "STCU_MBIST429_PTR,STCU MBISTn pointer register" bitfld.long 0x6B4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6B4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6B4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6B4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6B4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6B8 "STCU_MBIST430_PTR,STCU MBISTn pointer register" bitfld.long 0x6B8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6B8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6B8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6B8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6B8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6BC "STCU_MBIST431_PTR,STCU MBISTn pointer register" bitfld.long 0x6BC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6BC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6BC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6BC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6BC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6C0 "STCU_MBIST432_PTR,STCU MBISTn pointer register" bitfld.long 0x6C0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6C0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6C0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6C0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6C0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6C4 "STCU_MBIST433_PTR,STCU MBISTn pointer register" bitfld.long 0x6C4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6C4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6C4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6C4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6C4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6C8 "STCU_MBIST434_PTR,STCU MBISTn pointer register" bitfld.long 0x6C8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6C8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6C8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6C8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6C8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6CC "STCU_MBIST435_PTR,STCU MBISTn pointer register" bitfld.long 0x6CC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6CC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6CC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6CC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6CC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6D0 "STCU_MBIST436_PTR,STCU MBISTn pointer register" bitfld.long 0x6D0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6D0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6D0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6D0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6D0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6D4 "STCU_MBIST437_PTR,STCU MBISTn pointer register" bitfld.long 0x6D4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6D4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6D4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6D4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6D4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6D8 "STCU_MBIST438_PTR,STCU MBISTn pointer register" bitfld.long 0x6D8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6D8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6D8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6D8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6D8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6DC "STCU_MBIST439_PTR,STCU MBISTn pointer register" bitfld.long 0x6DC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6DC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6DC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6DC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6DC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6E0 "STCU_MBIST440_PTR,STCU MBISTn pointer register" bitfld.long 0x6E0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6E0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6E0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6E0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6E0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6E4 "STCU_MBIST441_PTR,STCU MBISTn pointer register" bitfld.long 0x6E4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6E4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6E4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6E4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6E4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6E8 "STCU_MBIST442_PTR,STCU MBISTn pointer register" bitfld.long 0x6E8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6E8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6E8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6E8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6E8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6EC "STCU_MBIST443_PTR,STCU MBISTn pointer register" bitfld.long 0x6EC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6EC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6EC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6EC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6EC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6F0 "STCU_MBIST444_PTR,STCU MBISTn pointer register" bitfld.long 0x6F0 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6F0 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6F0 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6F0 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6F0 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6F4 "STCU_MBIST445_PTR,STCU MBISTn pointer register" bitfld.long 0x6F4 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6F4 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6F4 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6F4 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6F4 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6F8 "STCU_MBIST446_PTR,STCU MBISTn pointer register" bitfld.long 0x6F8 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6F8 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6F8 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6F8 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6F8 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x6FC "STCU_MBIST447_PTR,STCU MBISTn pointer register" bitfld.long 0x6FC 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x6FC 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x6FC 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x6FC 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x6FC 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x700 "STCU_MBIST448_PTR,STCU MBISTn pointer register" bitfld.long 0x700 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x700 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x700 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x700 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x700 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x704 "STCU_MBIST449_PTR,STCU MBISTn pointer register" bitfld.long 0x704 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x704 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x704 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x704 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x704 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x708 "STCU_MBIST450_PTR,STCU MBISTn pointer register" bitfld.long 0x708 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x708 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x708 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x708 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x708 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x70C "STCU_MBIST451_PTR,STCU MBISTn pointer register" bitfld.long 0x70C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x70C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x70C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x70C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x70C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x710 "STCU_MBIST452_PTR,STCU MBISTn pointer register" bitfld.long 0x710 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x710 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x710 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x710 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x710 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x714 "STCU_MBIST453_PTR,STCU MBISTn pointer register" bitfld.long 0x714 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x714 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x714 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x714 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x714 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x718 "STCU_MBIST454_PTR,STCU MBISTn pointer register" bitfld.long 0x718 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x718 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x718 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x718 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x718 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x71C "STCU_MBIST455_PTR,STCU MBISTn pointer register" bitfld.long 0x71C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x71C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x71C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x71C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x71C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x720 "STCU_MBIST456_PTR,STCU MBISTn pointer register" bitfld.long 0x720 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x720 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x720 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x720 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x720 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x724 "STCU_MBIST457_PTR,STCU MBISTn pointer register" bitfld.long 0x724 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x724 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x724 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x724 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x724 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x728 "STCU_MBIST458_PTR,STCU MBISTn pointer register" bitfld.long 0x728 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x728 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x728 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x728 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x728 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x72C "STCU_MBIST459_PTR,STCU MBISTn pointer register" bitfld.long 0x72C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x72C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x72C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x72C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x72C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x730 "STCU_MBIST460_PTR,STCU MBISTn pointer register" bitfld.long 0x730 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x730 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x730 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x730 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x730 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x734 "STCU_MBIST461_PTR,STCU MBISTn pointer register" bitfld.long 0x734 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x734 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x734 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x734 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x734 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x738 "STCU_MBIST462_PTR,STCU MBISTn pointer register" bitfld.long 0x738 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x738 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x738 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x738 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x738 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x73C "STCU_MBIST463_PTR,STCU MBISTn pointer register" bitfld.long 0x73C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x73C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x73C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x73C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x73C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x740 "STCU_MBIST464_PTR,STCU MBISTn pointer register" bitfld.long 0x740 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x740 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x740 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x740 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x740 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x744 "STCU_MBIST465_PTR,STCU MBISTn pointer register" bitfld.long 0x744 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x744 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x744 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x744 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x744 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x748 "STCU_MBIST466_PTR,STCU MBISTn pointer register" bitfld.long 0x748 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x748 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x748 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x748 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x748 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x74C "STCU_MBIST467_PTR,STCU MBISTn pointer register" bitfld.long 0x74C 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x74C 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x74C 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x74C 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x74C 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" line.long 0x750 "STCU_MBIST468_PTR,STCU MBISTn pointer register" bitfld.long 0x750 31. "BIST_DELAY_ENABLE,Concurrent execution delay enable." "0,1" hexmask.long.byte 0x750 24.--27. 1. "BIST_TYPE,Indicates type of BIST for next BIST test execution. It provides a way to jump to other BIST pointer register files." hexmask.long.byte 0x750 16.--19. 1. "BIST_CTRL_NUM,Defines the logical pointer to the next MBIST for BIST execution. The size of this field depends on the number of MBISTs controllers present on the device." hexmask.long.word 0x750 1.--10. 1. "BIST_PTR_VAL,Pointer to the memory per MBIST controller for BIST execution. The size of this field depends on the total number of memory cuts." bitfld.long 0x750 0. "BIST_CFG,0 : Sequential mode." "0: Sequential mode,1: concurrent mode" tree.end tree "MBIST_STATUS" base ad:0x710A4644 rgroup.long 0x0++0x3 line.long 0x0 "STCU_MB0_STATUS0,STCU Offline MBIST0 Status Register" bitfld.long 0x0 2. "MB0_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB0_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB0_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x80++0x3 line.long 0x0 "STCU_MB0_ENDFLAG0,STCU Offline MBIST0 end flag Register" bitfld.long 0x0 2. "MB0_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB0_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB0_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x100++0x3 line.long 0x0 "STCU_MBSW0_STATUS0,STCU Online MBIST0 Status Register" bitfld.long 0x0 2. "MBSW0_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW0_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW0_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x180++0x3 line.long 0x0 "STCU_MBSW0_ENDFLAG0,STCU Online MBIST0 end flag Register" bitfld.long 0x0 2. "MBSW0_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW0_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW0_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x200++0x3 line.long 0x0 "STCU_MB0_UFM0,STCU MBIST0 Unrecoverable FM Register" bitfld.long 0x0 2. "MB0_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB0_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB0_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x280++0x3 line.long 0x0 "STCU_MB1_STATUS0,STCU Offline MBIST1 Status Register" bitfld.long 0x0 1. "MB1_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB1_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x300++0x3 line.long 0x0 "STCU_MB1_ENDFLAG0,STCU Offline MBIST1 end flag Register" bitfld.long 0x0 1. "MB1_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB1_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x380++0x3 line.long 0x0 "STCU_MBSW1_STATUS0,STCU Online MBIST1 Status Register" bitfld.long 0x0 1. "MBSW1_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW1_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x400++0x3 line.long 0x0 "STCU_MBSW1_ENDFLAG0,STCU Online MBIST1 end flag Register" bitfld.long 0x0 1. "MBSW1_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW1_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x480++0x3 line.long 0x0 "STCU_MB1_UFM0,STCU MBIST1 Unrecoverable FM Register" bitfld.long 0x0 1. "MB1_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB1_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x500++0x3 line.long 0x0 "STCU_MB2_STATUS0,STCU Offline MBIST2 Status Register" bitfld.long 0x0 23. "MB2_STATUS_23,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 22. "MB2_STATUS_22,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 21. "MB2_STATUS_21,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 20. "MB2_STATUS_20,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 19. "MB2_STATUS_19,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 18. "MB2_STATUS_18,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 17. "MB2_STATUS_17,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 16. "MB2_STATUS_16,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 15. "MB2_STATUS_15,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 14. "MB2_STATUS_14,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 13. "MB2_STATUS_13,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 12. "MB2_STATUS_12,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 11. "MB2_STATUS_11,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 10. "MB2_STATUS_10,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 9. "MB2_STATUS_9,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 8. "MB2_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MB2_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MB2_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MB2_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MB2_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MB2_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB2_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB2_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB2_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x580++0x3 line.long 0x0 "STCU_MB2_ENDFLAG0,STCU Offline MBIST2 end flag Register" bitfld.long 0x0 23. "MB2_ENDFLAG_23,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 22. "MB2_ENDFLAG_22,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 21. "MB2_ENDFLAG_21,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 20. "MB2_ENDFLAG_20,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 19. "MB2_ENDFLAG_19,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 18. "MB2_ENDFLAG_18,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 17. "MB2_ENDFLAG_17,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 16. "MB2_ENDFLAG_16,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MB2_ENDFLAG_15,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 14. "MB2_ENDFLAG_14,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MB2_ENDFLAG_13,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 12. "MB2_ENDFLAG_12,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MB2_ENDFLAG_11,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 10. "MB2_ENDFLAG_10,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MB2_ENDFLAG_9,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 8. "MB2_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MB2_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MB2_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MB2_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MB2_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MB2_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB2_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB2_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB2_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x600++0x3 line.long 0x0 "STCU_MBSW2_STATUS0,STCU Online MBIST2 Status Register" bitfld.long 0x0 23. "MBSW2_STATUS_23,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 22. "MBSW2_STATUS_22,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 21. "MBSW2_STATUS_21,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 20. "MBSW2_STATUS_20,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 19. "MBSW2_STATUS_19,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 18. "MBSW2_STATUS_18,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 17. "MBSW2_STATUS_17,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 16. "MBSW2_STATUS_16,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 15. "MBSW2_STATUS_15,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 14. "MBSW2_STATUS_14,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 13. "MBSW2_STATUS_13,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 12. "MBSW2_STATUS_12,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 11. "MBSW2_STATUS_11,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 10. "MBSW2_STATUS_10,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 9. "MBSW2_STATUS_9,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 8. "MBSW2_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MBSW2_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MBSW2_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MBSW2_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MBSW2_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MBSW2_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW2_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW2_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW2_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x680++0x3 line.long 0x0 "STCU_MBSW2_ENDFLAG0,STCU Online MBIST2 end flag Register" bitfld.long 0x0 23. "MBSW2_ENDFLAG_23,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 22. "MBSW2_ENDFLAG_22,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 21. "MBSW2_ENDFLAG_21,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 20. "MBSW2_ENDFLAG_20,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 19. "MBSW2_ENDFLAG_19,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 18. "MBSW2_ENDFLAG_18,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 17. "MBSW2_ENDFLAG_17,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 16. "MBSW2_ENDFLAG_16,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MBSW2_ENDFLAG_15,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 14. "MBSW2_ENDFLAG_14,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MBSW2_ENDFLAG_13,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 12. "MBSW2_ENDFLAG_12,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MBSW2_ENDFLAG_11,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 10. "MBSW2_ENDFLAG_10,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MBSW2_ENDFLAG_9,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 8. "MBSW2_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MBSW2_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MBSW2_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MBSW2_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MBSW2_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBSW2_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW2_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW2_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW2_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x700++0x3 line.long 0x0 "STCU_MB2_UFM0,STCU MBIST2 Unrecoverable FM Register" bitfld.long 0x0 23. "MB2_UFM_23,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 22. "MB2_UFM_22,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 21. "MB2_UFM_21,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 20. "MB2_UFM_20,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 19. "MB2_UFM_19,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 18. "MB2_UFM_18,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 17. "MB2_UFM_17,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 16. "MB2_UFM_16,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 15. "MB2_UFM_15,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 14. "MB2_UFM_14,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 13. "MB2_UFM_13,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 12. "MB2_UFM_12,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 11. "MB2_UFM_11,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 10. "MB2_UFM_10,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 9. "MB2_UFM_9,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 8. "MB2_UFM_8,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 7. "MB2_UFM_7,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 6. "MB2_UFM_6,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 5. "MB2_UFM_5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 4. "MB2_UFM_4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MB2_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB2_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB2_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB2_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x780++0x3 line.long 0x0 "STCU_MB3_STATUS0,STCU Offline MBIST3 Status Register" bitfld.long 0x0 25. "MB3_STATUS_25,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 24. "MB3_STATUS_24,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 23. "MB3_STATUS_23,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 22. "MB3_STATUS_22,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 21. "MB3_STATUS_21,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 20. "MB3_STATUS_20,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 19. "MB3_STATUS_19,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 18. "MB3_STATUS_18,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 17. "MB3_STATUS_17,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 16. "MB3_STATUS_16,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 15. "MB3_STATUS_15,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 14. "MB3_STATUS_14,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 13. "MB3_STATUS_13,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 12. "MB3_STATUS_12,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 11. "MB3_STATUS_11,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 10. "MB3_STATUS_10,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 9. "MB3_STATUS_9,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 8. "MB3_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MB3_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MB3_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MB3_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MB3_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MB3_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB3_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB3_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB3_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x800++0x3 line.long 0x0 "STCU_MB3_ENDFLAG0,STCU Offline MBIST3 end flag Register" bitfld.long 0x0 25. "MB3_ENDFLAG_25,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 24. "MB3_ENDFLAG_24,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 23. "MB3_ENDFLAG_23,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 22. "MB3_ENDFLAG_22,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 21. "MB3_ENDFLAG_21,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 20. "MB3_ENDFLAG_20,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 19. "MB3_ENDFLAG_19,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 18. "MB3_ENDFLAG_18,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 17. "MB3_ENDFLAG_17,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 16. "MB3_ENDFLAG_16,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MB3_ENDFLAG_15,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 14. "MB3_ENDFLAG_14,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MB3_ENDFLAG_13,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 12. "MB3_ENDFLAG_12,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MB3_ENDFLAG_11,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 10. "MB3_ENDFLAG_10,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MB3_ENDFLAG_9,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 8. "MB3_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MB3_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MB3_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MB3_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MB3_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MB3_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB3_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB3_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB3_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x880++0x3 line.long 0x0 "STCU_MBSW3_STATUS0,STCU Online MBIST3 Status Register" bitfld.long 0x0 25. "MBSW3_STATUS_25,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 24. "MBSW3_STATUS_24,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 23. "MBSW3_STATUS_23,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 22. "MBSW3_STATUS_22,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 21. "MBSW3_STATUS_21,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 20. "MBSW3_STATUS_20,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 19. "MBSW3_STATUS_19,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 18. "MBSW3_STATUS_18,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 17. "MBSW3_STATUS_17,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 16. "MBSW3_STATUS_16,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 15. "MBSW3_STATUS_15,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 14. "MBSW3_STATUS_14,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 13. "MBSW3_STATUS_13,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 12. "MBSW3_STATUS_12,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 11. "MBSW3_STATUS_11,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 10. "MBSW3_STATUS_10,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 9. "MBSW3_STATUS_9,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 8. "MBSW3_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MBSW3_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MBSW3_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MBSW3_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MBSW3_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MBSW3_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW3_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW3_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW3_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x900++0x3 line.long 0x0 "STCU_MBSW3_ENDFLAG0,STCU Online MBIST3 end flag Register" bitfld.long 0x0 25. "MBSW3_ENDFLAG_25,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 24. "MBSW3_ENDFLAG_24,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 23. "MBSW3_ENDFLAG_23,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 22. "MBSW3_ENDFLAG_22,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 21. "MBSW3_ENDFLAG_21,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 20. "MBSW3_ENDFLAG_20,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 19. "MBSW3_ENDFLAG_19,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 18. "MBSW3_ENDFLAG_18,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 17. "MBSW3_ENDFLAG_17,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 16. "MBSW3_ENDFLAG_16,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MBSW3_ENDFLAG_15,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 14. "MBSW3_ENDFLAG_14,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MBSW3_ENDFLAG_13,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 12. "MBSW3_ENDFLAG_12,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MBSW3_ENDFLAG_11,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 10. "MBSW3_ENDFLAG_10,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MBSW3_ENDFLAG_9,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 8. "MBSW3_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MBSW3_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MBSW3_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MBSW3_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MBSW3_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBSW3_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW3_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW3_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW3_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x980++0x3 line.long 0x0 "STCU_MB3_UFM0,STCU MBIST3 Unrecoverable FM Register" bitfld.long 0x0 25. "MB3_UFM_25,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 24. "MB3_UFM_24,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 23. "MB3_UFM_23,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 22. "MB3_UFM_22,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 21. "MB3_UFM_21,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 20. "MB3_UFM_20,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 19. "MB3_UFM_19,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 18. "MB3_UFM_18,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 17. "MB3_UFM_17,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 16. "MB3_UFM_16,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 15. "MB3_UFM_15,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 14. "MB3_UFM_14,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 13. "MB3_UFM_13,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 12. "MB3_UFM_12,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 11. "MB3_UFM_11,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 10. "MB3_UFM_10,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 9. "MB3_UFM_9,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 8. "MB3_UFM_8,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 7. "MB3_UFM_7,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 6. "MB3_UFM_6,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 5. "MB3_UFM_5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 4. "MB3_UFM_4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MB3_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB3_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB3_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB3_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0xA00++0x3 line.long 0x0 "STCU_MB4_STATUS0,STCU Offline MBIST4 Status Register" bitfld.long 0x0 8. "MB4_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MB4_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MB4_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MB4_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MB4_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MB4_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB4_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB4_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB4_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0xA80++0x3 line.long 0x0 "STCU_MB4_ENDFLAG0,STCU Offline MBIST4 end flag Register" bitfld.long 0x0 8. "MB4_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MB4_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MB4_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MB4_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MB4_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MB4_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB4_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB4_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB4_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0xB00++0x3 line.long 0x0 "STCU_MBSW4_STATUS0,STCU Online MBIST4 Status Register" bitfld.long 0x0 8. "MBSW4_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MBSW4_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MBSW4_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MBSW4_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MBSW4_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MBSW4_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW4_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW4_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW4_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0xB80++0x3 line.long 0x0 "STCU_MBSW4_ENDFLAG0,STCU Online MBIST4 end flag Register" bitfld.long 0x0 8. "MBSW4_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MBSW4_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MBSW4_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MBSW4_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MBSW4_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBSW4_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW4_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW4_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW4_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0xC00++0x3 line.long 0x0 "STCU_MB4_UFM0,STCU MBIST4 Unrecoverable FM Register" bitfld.long 0x0 8. "MB4_UFM_8,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 7. "MB4_UFM_7,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 6. "MB4_UFM_6,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 5. "MB4_UFM_5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 4. "MB4_UFM_4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MB4_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB4_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB4_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB4_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0xC80++0x3 line.long 0x0 "STCU_MB5_STATUS0,STCU Offline MBIST5 Status Register" bitfld.long 0x0 6. "MB5_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MB5_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MB5_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MB5_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB5_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB5_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB5_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0xD00++0x3 line.long 0x0 "STCU_MB5_ENDFLAG0,STCU Offline MBIST5 end flag Register" bitfld.long 0x0 6. "MB5_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MB5_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MB5_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MB5_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB5_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB5_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB5_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0xD80++0x3 line.long 0x0 "STCU_MBSW5_STATUS0,STCU Online MBIST5 Status Register" bitfld.long 0x0 6. "MBSW5_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MBSW5_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MBSW5_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MBSW5_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW5_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW5_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW5_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0xE00++0x3 line.long 0x0 "STCU_MBSW5_ENDFLAG0,STCU Online MBIST5 end flag Register" bitfld.long 0x0 6. "MBSW5_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MBSW5_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MBSW5_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBSW5_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW5_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW5_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW5_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0xE80++0x3 line.long 0x0 "STCU_MB5_UFM0,STCU MBIST5 Unrecoverable FM Register" bitfld.long 0x0 6. "MB5_UFM_6,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 5. "MB5_UFM_5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 4. "MB5_UFM_4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MB5_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB5_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB5_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB5_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0xF00++0x7 line.long 0x0 "STCU_MB6_STATUS0,STCU Offline MBIST6 Status Register" bitfld.long 0x0 31. "MB6_STATUS_31,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 30. "MB6_STATUS_30,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 29. "MB6_STATUS_29,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 28. "MB6_STATUS_28,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 27. "MB6_STATUS_27,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 26. "MB6_STATUS_26,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 25. "MB6_STATUS_25,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 24. "MB6_STATUS_24,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 23. "MB6_STATUS_23,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 22. "MB6_STATUS_22,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 21. "MB6_STATUS_21,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 20. "MB6_STATUS_20,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 19. "MB6_STATUS_19,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 18. "MB6_STATUS_18,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 17. "MB6_STATUS_17,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 16. "MB6_STATUS_16,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 15. "MB6_STATUS_15,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 14. "MB6_STATUS_14,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 13. "MB6_STATUS_13,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 12. "MB6_STATUS_12,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 11. "MB6_STATUS_11,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 10. "MB6_STATUS_10,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 9. "MB6_STATUS_9,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 8. "MB6_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MB6_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MB6_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MB6_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MB6_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MB6_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB6_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB6_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB6_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" line.long 0x4 "STCU_MB6_STATUS1,STCU Offline MBIST6 Status Register" bitfld.long 0x4 11. "MB6_STATUS_43,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 10. "MB6_STATUS_42,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 9. "MB6_STATUS_41,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 8. "MB6_STATUS_40,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 7. "MB6_STATUS_39,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 6. "MB6_STATUS_38,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 5. "MB6_STATUS_37,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 4. "MB6_STATUS_36,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 3. "MB6_STATUS_35,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 2. "MB6_STATUS_34,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 1. "MB6_STATUS_33,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 0. "MB6_STATUS_32,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0xF80++0x7 line.long 0x0 "STCU_MB6_ENDFLAG0,STCU Offline MBIST6 end flag Register" bitfld.long 0x0 31. "MB6_ENDFLAG_31,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 30. "MB6_ENDFLAG_30,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 29. "MB6_ENDFLAG_29,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 28. "MB6_ENDFLAG_28,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 27. "MB6_ENDFLAG_27,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 26. "MB6_ENDFLAG_26,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 25. "MB6_ENDFLAG_25,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 24. "MB6_ENDFLAG_24,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 23. "MB6_ENDFLAG_23,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 22. "MB6_ENDFLAG_22,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 21. "MB6_ENDFLAG_21,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 20. "MB6_ENDFLAG_20,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 19. "MB6_ENDFLAG_19,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 18. "MB6_ENDFLAG_18,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 17. "MB6_ENDFLAG_17,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 16. "MB6_ENDFLAG_16,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MB6_ENDFLAG_15,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 14. "MB6_ENDFLAG_14,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MB6_ENDFLAG_13,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 12. "MB6_ENDFLAG_12,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MB6_ENDFLAG_11,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 10. "MB6_ENDFLAG_10,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MB6_ENDFLAG_9,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 8. "MB6_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MB6_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MB6_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MB6_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MB6_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MB6_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB6_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB6_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB6_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" line.long 0x4 "STCU_MB6_ENDFLAG1,STCU Offline MBIST7 end flag Register" bitfld.long 0x4 11. "MB6_ENDFLAG_43,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 10. "MB6_ENDFLAG_42,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 9. "MB6_ENDFLAG_41,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 8. "MB6_ENDFLAG_40,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 7. "MB6_ENDFLAG_39,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 6. "MB6_ENDFLAG_38,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 5. "MB6_ENDFLAG_37,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 4. "MB6_ENDFLAG_36,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 3. "MB6_ENDFLAG_35,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 2. "MB6_ENDFLAG_34,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 1. "MB6_ENDFLAG_33,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 0. "MB6_ENDFLAG_32,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x1000++0x7 line.long 0x0 "STCU_MBSW6_STATUS0,STCU Online MBIST6 Status Register" bitfld.long 0x0 31. "MBSW6_STATUS_31,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 30. "MBSW6_STATUS_30,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 29. "MBSW6_STATUS_29,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 28. "MBSW6_STATUS_28,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 27. "MBSW6_STATUS_27,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 26. "MBSW6_STATUS_26,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 25. "MBSW6_STATUS_25,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 24. "MBSW6_STATUS_24,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 23. "MBSW6_STATUS_23,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 22. "MBSW6_STATUS_22,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 21. "MBSW6_STATUS_21,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 20. "MBSW6_STATUS_20,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 19. "MBSW6_STATUS_19,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 18. "MBSW6_STATUS_18,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 17. "MBSW6_STATUS_17,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 16. "MBSW6_STATUS_16,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 15. "MBSW6_STATUS_15,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 14. "MBSW6_STATUS_14,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 13. "MBSW6_STATUS_13,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 12. "MBSW6_STATUS_12,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 11. "MBSW6_STATUS_11,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 10. "MBSW6_STATUS_10,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 9. "MBSW6_STATUS_9,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 8. "MBSW6_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MBSW6_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MBSW6_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MBSW6_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MBSW6_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MBSW6_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW6_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW6_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW6_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" line.long 0x4 "STCU_MBSW6_STATUS1,STCU Online MBIST6 Status Register" bitfld.long 0x4 11. "MBSW6_STATUS_43,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 10. "MBSW6_STATUS_42,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 9. "MBSW6_STATUS_41,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 8. "MBSW6_STATUS_40,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 7. "MBSW6_STATUS_39,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 6. "MBSW6_STATUS_38,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 5. "MBSW6_STATUS_37,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 4. "MBSW6_STATUS_36,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 3. "MBSW6_STATUS_35,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 2. "MBSW6_STATUS_34,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 1. "MBSW6_STATUS_33,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 0. "MBSW6_STATUS_32,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1080++0x7 line.long 0x0 "STCU_MBSW6_ENDFLAG0,STCU Online MBIST6 end flag Register" bitfld.long 0x0 31. "MBSW6_ENDFLAG_31,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 30. "MBSW6_ENDFLAG_30,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 29. "MBSW6_ENDFLAG_29,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 28. "MBSW6_ENDFLAG_28,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 27. "MBSW6_ENDFLAG_27,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 26. "MBSW6_ENDFLAG_26,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 25. "MBSW6_ENDFLAG_25,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 24. "MBSW6_ENDFLAG_24,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 23. "MBSW6_ENDFLAG_23,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 22. "MBSW6_ENDFLAG_22,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 21. "MBSW6_ENDFLAG_21,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 20. "MBSW6_ENDFLAG_20,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 19. "MBSW6_ENDFLAG_19,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 18. "MBSW6_ENDFLAG_18,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 17. "MBSW6_ENDFLAG_17,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 16. "MBSW6_ENDFLAG_16,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MBSW6_ENDFLAG_15,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 14. "MBSW6_ENDFLAG_14,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MBSW6_ENDFLAG_13,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 12. "MBSW6_ENDFLAG_12,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MBSW6_ENDFLAG_11,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 10. "MBSW6_ENDFLAG_10,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MBSW6_ENDFLAG_9,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 8. "MBSW6_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MBSW6_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MBSW6_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MBSW6_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MBSW6_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBSW6_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW6_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW6_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW6_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" line.long 0x4 "STCU_MBSW6_ENDFLAG1,STCU Online MBIST6 end flag Register" bitfld.long 0x4 11. "MBSW6_ENDFLAG_43,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 10. "MBSW6_ENDFLAG_42,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 9. "MBSW6_ENDFLAG_41,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 8. "MBSW6_ENDFLAG_40,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 7. "MBSW6_ENDFLAG_39,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 6. "MBSW6_ENDFLAG_38,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 5. "MBSW6_ENDFLAG_37,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 4. "MBSW6_ENDFLAG_36,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 3. "MBSW6_ENDFLAG_35,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 2. "MBSW6_ENDFLAG_34,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 1. "MBSW6_ENDFLAG_33,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 0. "MBSW6_ENDFLAG_32,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x1100++0x7 line.long 0x0 "STCU_MB6_UFM0,STCU MBIST6 Unrecoverable FM Register" bitfld.long 0x0 31. "MB6_UFM_31,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 30. "MB6_UFM_30,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 29. "MB6_UFM_29,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 28. "MB6_UFM_28,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 27. "MB6_UFM_27,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 26. "MB6_UFM_26,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 25. "MB6_UFM_25,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 24. "MB6_UFM_24,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 23. "MB6_UFM_23,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 22. "MB6_UFM_22,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 21. "MB6_UFM_21,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 20. "MB6_UFM_20,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 19. "MB6_UFM_19,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 18. "MB6_UFM_18,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 17. "MB6_UFM_17,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 16. "MB6_UFM_16,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 15. "MB6_UFM_15,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 14. "MB6_UFM_14,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 13. "MB6_UFM_13,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 12. "MB6_UFM_12,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 11. "MB6_UFM_11,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 10. "MB6_UFM_10,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 9. "MB6_UFM_9,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 8. "MB6_UFM_8,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 7. "MB6_UFM_7,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 6. "MB6_UFM_6,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 5. "MB6_UFM_5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 4. "MB6_UFM_4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MB6_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB6_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB6_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB6_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" line.long 0x4 "STCU_MB6_UFM1,STCU MBIST6 Unrecoverable FM Register" bitfld.long 0x4 11. "MB6_UFM_43,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 10. "MB6_UFM_42,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 9. "MB6_UFM_41,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 8. "MB6_UFM_40,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 7. "MB6_UFM_39,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 6. "MB6_UFM_38,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 5. "MB6_UFM_37,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 4. "MB6_UFM_36,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 3. "MB6_UFM_35,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 2. "MB6_UFM_34,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 1. "MB6_UFM_33,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 0. "MB6_UFM_32,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x1180++0x7 line.long 0x0 "STCU_MB7_STATUS0,STCU Offline MBIST7 Status Register" bitfld.long 0x0 31. "MB7_STATUS_31,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 30. "MB7_STATUS_30,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 29. "MB7_STATUS_29,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 28. "MB7_STATUS_28,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 27. "MB7_STATUS_27,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 26. "MB7_STATUS_26,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 25. "MB7_STATUS_25,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 24. "MB7_STATUS_24,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 23. "MB7_STATUS_23,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 22. "MB7_STATUS_22,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 21. "MB7_STATUS_21,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 20. "MB7_STATUS_20,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 19. "MB7_STATUS_19,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 18. "MB7_STATUS_18,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 17. "MB7_STATUS_17,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 16. "MB7_STATUS_16,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 15. "MB7_STATUS_15,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 14. "MB7_STATUS_14,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 13. "MB7_STATUS_13,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 12. "MB7_STATUS_12,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 11. "MB7_STATUS_11,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 10. "MB7_STATUS_10,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 9. "MB7_STATUS_9,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 8. "MB7_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MB7_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MB7_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MB7_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MB7_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MB7_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB7_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB7_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB7_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" line.long 0x4 "STCU_MB7_STATUS1,STCU Offline MBIST7 Status Register" bitfld.long 0x4 11. "MB7_STATUS_43,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 10. "MB7_STATUS_42,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 9. "MB7_STATUS_41,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 8. "MB7_STATUS_40,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 7. "MB7_STATUS_39,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 6. "MB7_STATUS_38,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 5. "MB7_STATUS_37,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 4. "MB7_STATUS_36,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 3. "MB7_STATUS_35,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 2. "MB7_STATUS_34,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 1. "MB7_STATUS_33,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 0. "MB7_STATUS_32,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1200++0x7 line.long 0x0 "STCU_MB7_ENDFLAG0,STCU Offline MBIST7 end flag Register" bitfld.long 0x0 31. "MB7_ENDFLAG_31,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 30. "MB7_ENDFLAG_30,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 29. "MB7_ENDFLAG_29,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 28. "MB7_ENDFLAG_28,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 27. "MB7_ENDFLAG_27,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 26. "MB7_ENDFLAG_26,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 25. "MB7_ENDFLAG_25,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 24. "MB7_ENDFLAG_24,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 23. "MB7_ENDFLAG_23,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 22. "MB7_ENDFLAG_22,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 21. "MB7_ENDFLAG_21,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 20. "MB7_ENDFLAG_20,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 19. "MB7_ENDFLAG_19,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 18. "MB7_ENDFLAG_18,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 17. "MB7_ENDFLAG_17,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 16. "MB7_ENDFLAG_16,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MB7_ENDFLAG_15,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 14. "MB7_ENDFLAG_14,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MB7_ENDFLAG_13,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 12. "MB7_ENDFLAG_12,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MB7_ENDFLAG_11,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 10. "MB7_ENDFLAG_10,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MB7_ENDFLAG_9,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 8. "MB7_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MB7_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MB7_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MB7_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MB7_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MB7_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB7_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB7_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB7_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" line.long 0x4 "STCU_MB7_ENDFLAG1,STCU Offline MBIST7 end flag Register" bitfld.long 0x4 11. "MB7_ENDFLAG_43,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 10. "MB7_ENDFLAG_42,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 9. "MB7_ENDFLAG_41,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 8. "MB7_ENDFLAG_40,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 7. "MB7_ENDFLAG_39,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 6. "MB7_ENDFLAG_38,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 5. "MB7_ENDFLAG_37,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 4. "MB7_ENDFLAG_36,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 3. "MB7_ENDFLAG_35,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 2. "MB7_ENDFLAG_34,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 1. "MB7_ENDFLAG_33,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 0. "MB7_ENDFLAG_32,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x1280++0x7 line.long 0x0 "STCU_MBSW7_STATUS0,STCU Online MBIST7 Status Register" bitfld.long 0x0 31. "MBSW7_STATUS_31,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 30. "MBSW7_STATUS_30,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 29. "MBSW7_STATUS_29,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 28. "MBSW7_STATUS_28,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 27. "MBSW7_STATUS_27,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 26. "MBSW7_STATUS_26,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 25. "MBSW7_STATUS_25,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 24. "MBSW7_STATUS_24,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 23. "MBSW7_STATUS_23,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 22. "MBSW7_STATUS_22,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 21. "MBSW7_STATUS_21,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 20. "MBSW7_STATUS_20,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 19. "MBSW7_STATUS_19,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 18. "MBSW7_STATUS_18,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 17. "MBSW7_STATUS_17,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 16. "MBSW7_STATUS_16,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 15. "MBSW7_STATUS_15,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 14. "MBSW7_STATUS_14,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 13. "MBSW7_STATUS_13,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 12. "MBSW7_STATUS_12,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 11. "MBSW7_STATUS_11,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 10. "MBSW7_STATUS_10,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 9. "MBSW7_STATUS_9,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 8. "MBSW7_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MBSW7_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MBSW7_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MBSW7_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MBSW7_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MBSW7_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW7_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW7_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW7_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" line.long 0x4 "STCU_MBSW7_STATUS1,STCU Online MBIST7 Status Register" bitfld.long 0x4 11. "MBSW7_STATUS_43,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 10. "MBSW7_STATUS_42,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 9. "MBSW7_STATUS_41,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 8. "MBSW7_STATUS_40,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 7. "MBSW7_STATUS_39,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 6. "MBSW7_STATUS_38,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 5. "MBSW7_STATUS_37,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 4. "MBSW7_STATUS_36,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 3. "MBSW7_STATUS_35,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 2. "MBSW7_STATUS_34,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 1. "MBSW7_STATUS_33,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 0. "MBSW7_STATUS_32,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1300++0x7 line.long 0x0 "STCU_MBSW7_ENDFLAG0,STCU Online MBIST7 end flag Register" bitfld.long 0x0 31. "MBSW7_ENDFLAG_31,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 30. "MBSW7_ENDFLAG_30,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 29. "MBSW7_ENDFLAG_29,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 28. "MBSW7_ENDFLAG_28,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 27. "MBSW7_ENDFLAG_27,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 26. "MBSW7_ENDFLAG_26,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 25. "MBSW7_ENDFLAG_25,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 24. "MBSW7_ENDFLAG_24,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 23. "MBSW7_ENDFLAG_23,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 22. "MBSW7_ENDFLAG_22,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 21. "MBSW7_ENDFLAG_21,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 20. "MBSW7_ENDFLAG_20,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 19. "MBSW7_ENDFLAG_19,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 18. "MBSW7_ENDFLAG_18,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 17. "MBSW7_ENDFLAG_17,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 16. "MBSW7_ENDFLAG_16,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MBSW7_ENDFLAG_15,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 14. "MBSW7_ENDFLAG_14,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MBSW7_ENDFLAG_13,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 12. "MBSW7_ENDFLAG_12,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MBSW7_ENDFLAG_11,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 10. "MBSW7_ENDFLAG_10,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MBSW7_ENDFLAG_9,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 8. "MBSW7_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MBSW7_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MBSW7_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MBSW7_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MBSW7_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBSW7_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW7_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW7_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW7_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" line.long 0x4 "STCU_MBSW7_ENDFLAG1,STCU Online MBIST7 end flag Register" bitfld.long 0x4 11. "MBSW7_ENDFLAG_43,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 10. "MBSW7_ENDFLAG_42,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 9. "MBSW7_ENDFLAG_41,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 8. "MBSW7_ENDFLAG_40,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 7. "MBSW7_ENDFLAG_39,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 6. "MBSW7_ENDFLAG_38,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 5. "MBSW7_ENDFLAG_37,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 4. "MBSW7_ENDFLAG_36,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 3. "MBSW7_ENDFLAG_35,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 2. "MBSW7_ENDFLAG_34,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 1. "MBSW7_ENDFLAG_33,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 0. "MBSW7_ENDFLAG_32,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x1380++0x7 line.long 0x0 "STCU_MB7_UFM0,STCU MBIST7 Unrecoverable FM Register" bitfld.long 0x0 31. "MB7_UFM_31,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 30. "MB7_UFM_30,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 29. "MB7_UFM_29,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 28. "MB7_UFM_28,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 27. "MB7_UFM_27,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 26. "MB7_UFM_26,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 25. "MB7_UFM_25,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 24. "MB7_UFM_24,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 23. "MB7_UFM_23,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 22. "MB7_UFM_22,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 21. "MB7_UFM_21,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 20. "MB7_UFM_20,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 19. "MB7_UFM_19,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 18. "MB7_UFM_18,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 17. "MB7_UFM_17,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 16. "MB7_UFM_16,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 15. "MB7_UFM_15,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 14. "MB7_UFM_14,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 13. "MB7_UFM_13,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 12. "MB7_UFM_12,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 11. "MB7_UFM_11,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 10. "MB7_UFM_10,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 9. "MB7_UFM_9,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 8. "MB7_UFM_8,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 7. "MB7_UFM_7,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 6. "MB7_UFM_6,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 5. "MB7_UFM_5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 4. "MB7_UFM_4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MB7_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB7_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB7_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB7_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" line.long 0x4 "STCU_MB7_UFM1,STCU MBIST7 Unrecoverable FM Register" bitfld.long 0x4 11. "MB7_UFM_43,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 10. "MB7_UFM_42,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 9. "MB7_UFM_41,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 8. "MB7_UFM_40,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 7. "MB7_UFM_39,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 6. "MB7_UFM_38,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 5. "MB7_UFM_37,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 4. "MB7_UFM_36,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 3. "MB7_UFM_35,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 2. "MB7_UFM_34,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 1. "MB7_UFM_33,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 0. "MB7_UFM_32,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x1400++0x7 line.long 0x0 "STCU_MB8_STATUS0,STCU Offline MBIST8 Status Register" bitfld.long 0x0 31. "MB8_STATUS_31,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 30. "MB8_STATUS_30,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 29. "MB8_STATUS_29,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 28. "MB8_STATUS_28,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 27. "MB8_STATUS_27,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 26. "MB8_STATUS_26,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 25. "MB8_STATUS_25,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 24. "MB8_STATUS_24,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 23. "MB8_STATUS_23,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 22. "MB8_STATUS_22,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 21. "MB8_STATUS_21,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 20. "MB8_STATUS_20,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 19. "MB8_STATUS_19,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 18. "MB8_STATUS_18,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 17. "MB8_STATUS_17,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 16. "MB8_STATUS_16,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 15. "MB8_STATUS_15,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 14. "MB8_STATUS_14,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 13. "MB8_STATUS_13,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 12. "MB8_STATUS_12,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 11. "MB8_STATUS_11,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 10. "MB8_STATUS_10,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 9. "MB8_STATUS_9,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 8. "MB8_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MB8_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MB8_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MB8_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MB8_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MB8_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB8_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB8_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB8_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" line.long 0x4 "STCU_MB8_STATUS1,STCU Offline MBIST8 Status Register" bitfld.long 0x4 11. "MB8_STATUS_43,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 10. "MB8_STATUS_42,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 9. "MB8_STATUS_41,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 8. "MB8_STATUS_40,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 7. "MB8_STATUS_39,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 6. "MB8_STATUS_38,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 5. "MB8_STATUS_37,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 4. "MB8_STATUS_36,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 3. "MB8_STATUS_35,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 2. "MB8_STATUS_34,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 1. "MB8_STATUS_33,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 0. "MB8_STATUS_32,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1480++0x7 line.long 0x0 "STCU_MB8_ENDFLAG0,STCU Offline MBIST8 end flag Register" bitfld.long 0x0 31. "MB8_ENDFLAG_31,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 30. "MB8_ENDFLAG_30,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 29. "MB8_ENDFLAG_29,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 28. "MB8_ENDFLAG_28,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 27. "MB8_ENDFLAG_27,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 26. "MB8_ENDFLAG_26,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 25. "MB8_ENDFLAG_25,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 24. "MB8_ENDFLAG_24,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 23. "MB8_ENDFLAG_23,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 22. "MB8_ENDFLAG_22,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 21. "MB8_ENDFLAG_21,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 20. "MB8_ENDFLAG_20,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 19. "MB8_ENDFLAG_19,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 18. "MB8_ENDFLAG_18,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 17. "MB8_ENDFLAG_17,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 16. "MB8_ENDFLAG_16,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MB8_ENDFLAG_15,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 14. "MB8_ENDFLAG_14,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MB8_ENDFLAG_13,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 12. "MB8_ENDFLAG_12,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MB8_ENDFLAG_11,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 10. "MB8_ENDFLAG_10,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MB8_ENDFLAG_9,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 8. "MB8_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MB8_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MB8_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MB8_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MB8_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MB8_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB8_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB8_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB8_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" line.long 0x4 "STCU_MB8_ENDFLAG1,STCU Offline MBIST8 end flag Register" bitfld.long 0x4 11. "MB8_ENDFLAG_43,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 10. "MB8_ENDFLAG_42,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 9. "MB8_ENDFLAG_41,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 8. "MB8_ENDFLAG_40,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 7. "MB8_ENDFLAG_39,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 6. "MB8_ENDFLAG_38,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 5. "MB8_ENDFLAG_37,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 4. "MB8_ENDFLAG_36,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 3. "MB8_ENDFLAG_35,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 2. "MB8_ENDFLAG_34,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 1. "MB8_ENDFLAG_33,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 0. "MB8_ENDFLAG_32,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x1500++0x7 line.long 0x0 "STCU_MBSW8_STATUS0,STCU Online MBIST8 Status Register" bitfld.long 0x0 31. "MBSW8_STATUS_31,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 30. "MBSW8_STATUS_30,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 29. "MBSW8_STATUS_29,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 28. "MBSW8_STATUS_28,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 27. "MBSW8_STATUS_27,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 26. "MBSW8_STATUS_26,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 25. "MBSW8_STATUS_25,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 24. "MBSW8_STATUS_24,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 23. "MBSW8_STATUS_23,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 22. "MBSW8_STATUS_22,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 21. "MBSW8_STATUS_21,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 20. "MBSW8_STATUS_20,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 19. "MBSW8_STATUS_19,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 18. "MBSW8_STATUS_18,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 17. "MBSW8_STATUS_17,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 16. "MBSW8_STATUS_16,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 15. "MBSW8_STATUS_15,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 14. "MBSW8_STATUS_14,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 13. "MBSW8_STATUS_13,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 12. "MBSW8_STATUS_12,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 11. "MBSW8_STATUS_11,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 10. "MBSW8_STATUS_10,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 9. "MBSW8_STATUS_9,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 8. "MBSW8_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MBSW8_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MBSW8_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MBSW8_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MBSW8_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MBSW8_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW8_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW8_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW8_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" line.long 0x4 "STCU_MBSW8_STATUS1,STCU Online MBIST8 Status Register" bitfld.long 0x4 11. "MBSW8_STATUS_43,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 10. "MBSW8_STATUS_42,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 9. "MBSW8_STATUS_41,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 8. "MBSW8_STATUS_40,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 7. "MBSW8_STATUS_39,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 6. "MBSW8_STATUS_38,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 5. "MBSW8_STATUS_37,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 4. "MBSW8_STATUS_36,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 3. "MBSW8_STATUS_35,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 2. "MBSW8_STATUS_34,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 1. "MBSW8_STATUS_33,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 0. "MBSW8_STATUS_32,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1580++0x7 line.long 0x0 "STCU_MBSW8_ENDFLAG0,STCU Online MBIST8 end flag Register" bitfld.long 0x0 31. "MBSW8_ENDFLAG_31,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 30. "MBSW8_ENDFLAG_30,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 29. "MBSW8_ENDFLAG_29,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 28. "MBSW8_ENDFLAG_28,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 27. "MBSW8_ENDFLAG_27,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 26. "MBSW8_ENDFLAG_26,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 25. "MBSW8_ENDFLAG_25,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 24. "MBSW8_ENDFLAG_24,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 23. "MBSW8_ENDFLAG_23,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 22. "MBSW8_ENDFLAG_22,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 21. "MBSW8_ENDFLAG_21,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 20. "MBSW8_ENDFLAG_20,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 19. "MBSW8_ENDFLAG_19,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 18. "MBSW8_ENDFLAG_18,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 17. "MBSW8_ENDFLAG_17,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 16. "MBSW8_ENDFLAG_16,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MBSW8_ENDFLAG_15,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 14. "MBSW8_ENDFLAG_14,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MBSW8_ENDFLAG_13,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 12. "MBSW8_ENDFLAG_12,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MBSW8_ENDFLAG_11,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 10. "MBSW8_ENDFLAG_10,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MBSW8_ENDFLAG_9,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 8. "MBSW8_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MBSW8_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MBSW8_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MBSW8_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MBSW8_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBSW8_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW8_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW8_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW8_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" line.long 0x4 "STCU_MBSW8_ENDFLAG1,STCU Online MBIST8 end flag Register" bitfld.long 0x4 11. "MBSW8_ENDFLAG_43,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 10. "MBSW8_ENDFLAG_42,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 9. "MBSW8_ENDFLAG_41,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 8. "MBSW8_ENDFLAG_40,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 7. "MBSW8_ENDFLAG_39,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 6. "MBSW8_ENDFLAG_38,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 5. "MBSW8_ENDFLAG_37,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 4. "MBSW8_ENDFLAG_36,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 3. "MBSW8_ENDFLAG_35,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 2. "MBSW8_ENDFLAG_34,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 1. "MBSW8_ENDFLAG_33,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 0. "MBSW8_ENDFLAG_32,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x1600++0x7 line.long 0x0 "STCU_MB8_UFM0,STCU MBIST8 Unrecoverable FM Register" bitfld.long 0x0 31. "MB8_UFM_31,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 30. "MB8_UFM_30,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 29. "MB8_UFM_29,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 28. "MB8_UFM_28,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 27. "MB8_UFM_27,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 26. "MB8_UFM_26,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 25. "MB8_UFM_25,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 24. "MB8_UFM_24,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 23. "MB8_UFM_23,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 22. "MB8_UFM_22,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 21. "MB8_UFM_21,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 20. "MB8_UFM_20,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 19. "MB8_UFM_19,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 18. "MB8_UFM_18,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 17. "MB8_UFM_17,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 16. "MB8_UFM_16,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 15. "MB8_UFM_15,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 14. "MB8_UFM_14,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 13. "MB8_UFM_13,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 12. "MB8_UFM_12,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 11. "MB8_UFM_11,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 10. "MB8_UFM_10,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 9. "MB8_UFM_9,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 8. "MB8_UFM_8,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 7. "MB8_UFM_7,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 6. "MB8_UFM_6,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 5. "MB8_UFM_5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 4. "MB8_UFM_4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MB8_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB8_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB8_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB8_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" line.long 0x4 "STCU_MB8_UFM1,STCU MBIST8 Unrecoverable FM Register" bitfld.long 0x4 11. "MB8_UFM_43,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 10. "MB8_UFM_42,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 9. "MB8_UFM_41,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 8. "MB8_UFM_40,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 7. "MB8_UFM_39,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 6. "MB8_UFM_38,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 5. "MB8_UFM_37,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 4. "MB8_UFM_36,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 3. "MB8_UFM_35,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 2. "MB8_UFM_34,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 1. "MB8_UFM_33,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 0. "MB8_UFM_32,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x1680++0x3 line.long 0x0 "STCU_MB9_STATUS0,STCU Offline MBIST9 Status Register" bitfld.long 0x0 3. "MB9_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB9_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB9_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB9_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1700++0x3 line.long 0x0 "STCU_MB9_ENDFLAG0,STCU Offline MBIST9 end flag Register" bitfld.long 0x0 3. "MB9_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB9_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB9_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB9_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x1780++0x3 line.long 0x0 "STCU_MBSW9_STATUS0,STCU Online MBIST9 Status Register" bitfld.long 0x0 3. "MBSW9_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW9_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW9_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW9_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1800++0x3 line.long 0x0 "STCU_MBSW9_ENDFLAG0,STCU Online MBIST9 end flag Register" bitfld.long 0x0 3. "MBSW9_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW9_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW9_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW9_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x1880++0x3 line.long 0x0 "STCU_MB9_UFM0,STCU MBIST9 Unrecoverable FM Register" bitfld.long 0x0 3. "MB9_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB9_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB9_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB9_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x1900++0x3 line.long 0x0 "STCU_MB10_STATUS0,STCU Offline MBIST10 Status Register" bitfld.long 0x0 3. "MB10_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB10_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB10_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB10_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1980++0x3 line.long 0x0 "STCU_MB10_ENDFLAG0,STCU Offline MBIST10 end flag Register" bitfld.long 0x0 3. "MB10_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB10_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB10_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB10_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x1A00++0x3 line.long 0x0 "STCU_MBSW10_STATUS0,STCU Online MBIST10 Status Register" bitfld.long 0x0 3. "MBSW10_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW10_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW10_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW10_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1A80++0x3 line.long 0x0 "STCU_MBSW10_ENDFLAG0,STCU Online MBIST10 end flag Register" bitfld.long 0x0 3. "MBSW10_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW10_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW10_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW10_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x1B00++0x3 line.long 0x0 "STCU_MB10_UFM0,STCU MBIST10 Unrecoverable FM Register" bitfld.long 0x0 3. "MB10_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB10_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB10_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB10_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x1B80++0x3 line.long 0x0 "STCU_MB11_STATUS0,STCU Offline MBIST11 Status Register" bitfld.long 0x0 3. "MB11_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB11_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB11_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB11_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1C00++0x3 line.long 0x0 "STCU_MB11_ENDFLAG0,STCU Offline MBIST11 end flag Register" bitfld.long 0x0 3. "MB11_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB11_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB11_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB11_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x1C80++0x3 line.long 0x0 "STCU_MBSW11_STATUS0,STCU Online MBIST11 Status Register" bitfld.long 0x0 3. "MBSW11_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW11_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW11_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW11_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1D00++0x3 line.long 0x0 "STCU_MBSW11_ENDFLAG0,STCU Online MBIST11 end flag Register" bitfld.long 0x0 3. "MBSW11_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW11_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW11_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW11_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x1D80++0x3 line.long 0x0 "STCU_MB11_UFM0,STCU MBIST11 Unrecoverable FM Register" bitfld.long 0x0 3. "MB11_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB11_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB11_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB11_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x1E00++0x3 line.long 0x0 "STCU_MB12_STATUS0,STCU Offline MBIST12 Status Register" bitfld.long 0x0 7. "MB12_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MB12_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MB12_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MB12_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MB12_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB12_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB12_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB12_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1E80++0x3 line.long 0x0 "STCU_MB12_ENDFLAG0,STCU Offline MBIST12 end flag Register" bitfld.long 0x0 7. "MB12_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MB12_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MB12_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MB12_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MB12_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB12_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB12_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB12_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x1F00++0x3 line.long 0x0 "STCU_MBSW12_STATUS0,STCU Online MBIST12 Status Register" bitfld.long 0x0 7. "MBSW12_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MBSW12_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MBSW12_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MBSW12_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MBSW12_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW12_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW12_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW12_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1F80++0x3 line.long 0x0 "STCU_MBSW12_ENDFLAG0,STCU Online MBIST12 end flag Register" bitfld.long 0x0 7. "MBSW12_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MBSW12_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MBSW12_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MBSW12_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBSW12_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW12_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW12_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW12_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x2000++0x3 line.long 0x0 "STCU_MB12_UFM0,STCU MBIST12 Unrecoverable FM Register" bitfld.long 0x0 7. "MB12_UFM_7,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 6. "MB12_UFM_6,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 5. "MB12_UFM_5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 4. "MB12_UFM_4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MB12_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB12_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB12_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB12_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x2080++0x3 line.long 0x0 "STCU_MB13_STATUS0,STCU Offline MBIST13 Status Register" bitfld.long 0x0 5. "MB13_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MB13_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MB13_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB13_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB13_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB13_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x2100++0x3 line.long 0x0 "STCU_MB13_ENDFLAG0,STCU Offline MBIST13 end flag Register" bitfld.long 0x0 5. "MB13_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MB13_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MB13_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB13_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB13_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB13_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x2180++0x3 line.long 0x0 "STCU_MBSW13_STATUS0,STCU Online MBIST13 Status Register" bitfld.long 0x0 5. "MBSW13_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MBSW13_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MBSW13_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW13_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW13_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW13_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x2200++0x3 line.long 0x0 "STCU_MBSW13_ENDFLAG0,STCU Online MBIST13 end flag Register" bitfld.long 0x0 5. "MBSW13_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MBSW13_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBSW13_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW13_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW13_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW13_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x2280++0x3 line.long 0x0 "STCU_MB13_UFM0,STCU MBIST13 Unrecoverable FM Register" bitfld.long 0x0 5. "MB13_UFM_5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 4. "MB13_UFM_4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MB13_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB13_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB13_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB13_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x2300++0x3 line.long 0x0 "STCU_MB14_STATUS0,STCU Offline MBIST14 Status Register" bitfld.long 0x0 8. "MB14_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MB14_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MB14_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MB14_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MB14_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MB14_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB14_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB14_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB14_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x2380++0x3 line.long 0x0 "STCU_MB14_ENDFLAG0,STCU Offline MBIST14 end flag Register" bitfld.long 0x0 8. "MB14_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MB14_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MB14_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MB14_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MB14_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MB14_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB14_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB14_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB14_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x2400++0x3 line.long 0x0 "STCU_MBSW14_STATUS0,STCU Online MBIST14 Status Register" bitfld.long 0x0 8. "MBSW14_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MBSW14_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MBSW14_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MBSW14_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MBSW14_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MBSW14_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW14_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW14_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW14_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x2480++0x3 line.long 0x0 "STCU_MBSW14_ENDFLAG0,STCU Online MBIST14 end flag Register" bitfld.long 0x0 8. "MBSW14_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MBSW14_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MBSW14_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MBSW14_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MBSW14_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBSW14_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW14_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW14_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW14_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x2500++0x3 line.long 0x0 "STCU_MB14_UFM0,STCU MBIST14 Unrecoverable FM Register" bitfld.long 0x0 8. "MB14_UFM_8,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 7. "MB14_UFM_7,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 6. "MB14_UFM_6,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 5. "MB14_UFM_5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 4. "MB14_UFM_4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MB14_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB14_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB14_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB14_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" tree.end tree "MBIST_STATUS_ADDRBLK" base ad:0x710A4644 rgroup.long 0x0++0x3 line.long 0x0 "STCU_MB0_STATUS0,STCU Offline MBIST0 Status Register" bitfld.long 0x0 2. "MB0_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB0_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB0_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x80++0x3 line.long 0x0 "STCU_MB0_ENDFLAG0,STCU Offline MBIST0 end flag Register" bitfld.long 0x0 2. "MB0_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB0_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB0_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x100++0x3 line.long 0x0 "STCU_MBSW0_STATUS0,STCU Online MBIST0 Status Register" bitfld.long 0x0 2. "MBSW0_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW0_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW0_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x180++0x3 line.long 0x0 "STCU_MBSW0_ENDFLAG0,STCU Online MBIST0 end flag Register" bitfld.long 0x0 2. "MBSW0_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW0_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW0_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x200++0x3 line.long 0x0 "STCU_MB0_UFM0,STCU MBIST0 Unrecoverable FM Register" bitfld.long 0x0 2. "MB0_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB0_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB0_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x280++0x3 line.long 0x0 "STCU_MB1_STATUS0,STCU Offline MBIST1 Status Register" bitfld.long 0x0 1. "MB1_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB1_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x300++0x3 line.long 0x0 "STCU_MB1_ENDFLAG0,STCU Offline MBIST1 end flag Register" bitfld.long 0x0 1. "MB1_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB1_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x380++0x3 line.long 0x0 "STCU_MBSW1_STATUS0,STCU Online MBIST1 Status Register" bitfld.long 0x0 1. "MBSW1_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW1_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x400++0x3 line.long 0x0 "STCU_MBSW1_ENDFLAG0,STCU Online MBIST1 end flag Register" bitfld.long 0x0 1. "MBSW1_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW1_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x480++0x3 line.long 0x0 "STCU_MB1_UFM0,STCU MBIST1 Unrecoverable FM Register" bitfld.long 0x0 1. "MB1_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB1_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x500++0x3 line.long 0x0 "STCU_MB2_STATUS0,STCU Offline MBIST2 Status Register" bitfld.long 0x0 23. "MB2_STATUS_23,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 22. "MB2_STATUS_22,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 21. "MB2_STATUS_21,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 20. "MB2_STATUS_20,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 19. "MB2_STATUS_19,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 18. "MB2_STATUS_18,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 17. "MB2_STATUS_17,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 16. "MB2_STATUS_16,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 15. "MB2_STATUS_15,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 14. "MB2_STATUS_14,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 13. "MB2_STATUS_13,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 12. "MB2_STATUS_12,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 11. "MB2_STATUS_11,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 10. "MB2_STATUS_10,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 9. "MB2_STATUS_9,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 8. "MB2_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MB2_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MB2_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MB2_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MB2_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MB2_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB2_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB2_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB2_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x580++0x3 line.long 0x0 "STCU_MB2_ENDFLAG0,STCU Offline MBIST2 end flag Register" bitfld.long 0x0 23. "MB2_ENDFLAG_23,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 22. "MB2_ENDFLAG_22,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 21. "MB2_ENDFLAG_21,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 20. "MB2_ENDFLAG_20,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 19. "MB2_ENDFLAG_19,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 18. "MB2_ENDFLAG_18,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 17. "MB2_ENDFLAG_17,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 16. "MB2_ENDFLAG_16,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MB2_ENDFLAG_15,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 14. "MB2_ENDFLAG_14,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MB2_ENDFLAG_13,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 12. "MB2_ENDFLAG_12,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MB2_ENDFLAG_11,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 10. "MB2_ENDFLAG_10,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MB2_ENDFLAG_9,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 8. "MB2_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MB2_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MB2_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MB2_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MB2_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MB2_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB2_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB2_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB2_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x600++0x3 line.long 0x0 "STCU_MBSW2_STATUS0,STCU Online MBIST2 Status Register" bitfld.long 0x0 23. "MBSW2_STATUS_23,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 22. "MBSW2_STATUS_22,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 21. "MBSW2_STATUS_21,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 20. "MBSW2_STATUS_20,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 19. "MBSW2_STATUS_19,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 18. "MBSW2_STATUS_18,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 17. "MBSW2_STATUS_17,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 16. "MBSW2_STATUS_16,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 15. "MBSW2_STATUS_15,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 14. "MBSW2_STATUS_14,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 13. "MBSW2_STATUS_13,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 12. "MBSW2_STATUS_12,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 11. "MBSW2_STATUS_11,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 10. "MBSW2_STATUS_10,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 9. "MBSW2_STATUS_9,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 8. "MBSW2_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MBSW2_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MBSW2_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MBSW2_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MBSW2_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MBSW2_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW2_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW2_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW2_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x680++0x3 line.long 0x0 "STCU_MBSW2_ENDFLAG0,STCU Online MBIST2 end flag Register" bitfld.long 0x0 23. "MBSW2_ENDFLAG_23,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 22. "MBSW2_ENDFLAG_22,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 21. "MBSW2_ENDFLAG_21,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 20. "MBSW2_ENDFLAG_20,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 19. "MBSW2_ENDFLAG_19,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 18. "MBSW2_ENDFLAG_18,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 17. "MBSW2_ENDFLAG_17,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 16. "MBSW2_ENDFLAG_16,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MBSW2_ENDFLAG_15,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 14. "MBSW2_ENDFLAG_14,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MBSW2_ENDFLAG_13,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 12. "MBSW2_ENDFLAG_12,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MBSW2_ENDFLAG_11,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 10. "MBSW2_ENDFLAG_10,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MBSW2_ENDFLAG_9,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 8. "MBSW2_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MBSW2_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MBSW2_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MBSW2_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MBSW2_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBSW2_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW2_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW2_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW2_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x700++0x3 line.long 0x0 "STCU_MB2_UFM0,STCU MBIST2 Unrecoverable FM Register" bitfld.long 0x0 23. "MB2_UFM_23,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 22. "MB2_UFM_22,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 21. "MB2_UFM_21,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 20. "MB2_UFM_20,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 19. "MB2_UFM_19,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 18. "MB2_UFM_18,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 17. "MB2_UFM_17,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 16. "MB2_UFM_16,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 15. "MB2_UFM_15,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 14. "MB2_UFM_14,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 13. "MB2_UFM_13,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 12. "MB2_UFM_12,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 11. "MB2_UFM_11,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 10. "MB2_UFM_10,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 9. "MB2_UFM_9,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 8. "MB2_UFM_8,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 7. "MB2_UFM_7,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 6. "MB2_UFM_6,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 5. "MB2_UFM_5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 4. "MB2_UFM_4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MB2_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB2_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB2_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB2_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x780++0x3 line.long 0x0 "STCU_MB3_STATUS0,STCU Offline MBIST3 Status Register" bitfld.long 0x0 25. "MB3_STATUS_25,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 24. "MB3_STATUS_24,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 23. "MB3_STATUS_23,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 22. "MB3_STATUS_22,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 21. "MB3_STATUS_21,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 20. "MB3_STATUS_20,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 19. "MB3_STATUS_19,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 18. "MB3_STATUS_18,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 17. "MB3_STATUS_17,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 16. "MB3_STATUS_16,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 15. "MB3_STATUS_15,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 14. "MB3_STATUS_14,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 13. "MB3_STATUS_13,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 12. "MB3_STATUS_12,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 11. "MB3_STATUS_11,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 10. "MB3_STATUS_10,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 9. "MB3_STATUS_9,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 8. "MB3_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MB3_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MB3_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MB3_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MB3_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MB3_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB3_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB3_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB3_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x800++0x3 line.long 0x0 "STCU_MB3_ENDFLAG0,STCU Offline MBIST3 end flag Register" bitfld.long 0x0 25. "MB3_ENDFLAG_25,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 24. "MB3_ENDFLAG_24,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 23. "MB3_ENDFLAG_23,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 22. "MB3_ENDFLAG_22,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 21. "MB3_ENDFLAG_21,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 20. "MB3_ENDFLAG_20,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 19. "MB3_ENDFLAG_19,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 18. "MB3_ENDFLAG_18,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 17. "MB3_ENDFLAG_17,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 16. "MB3_ENDFLAG_16,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MB3_ENDFLAG_15,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 14. "MB3_ENDFLAG_14,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MB3_ENDFLAG_13,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 12. "MB3_ENDFLAG_12,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MB3_ENDFLAG_11,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 10. "MB3_ENDFLAG_10,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MB3_ENDFLAG_9,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 8. "MB3_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MB3_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MB3_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MB3_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MB3_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MB3_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB3_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB3_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB3_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x880++0x3 line.long 0x0 "STCU_MBSW3_STATUS0,STCU Online MBIST3 Status Register" bitfld.long 0x0 25. "MBSW3_STATUS_25,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 24. "MBSW3_STATUS_24,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 23. "MBSW3_STATUS_23,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 22. "MBSW3_STATUS_22,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 21. "MBSW3_STATUS_21,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 20. "MBSW3_STATUS_20,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 19. "MBSW3_STATUS_19,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 18. "MBSW3_STATUS_18,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 17. "MBSW3_STATUS_17,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 16. "MBSW3_STATUS_16,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 15. "MBSW3_STATUS_15,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 14. "MBSW3_STATUS_14,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 13. "MBSW3_STATUS_13,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 12. "MBSW3_STATUS_12,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 11. "MBSW3_STATUS_11,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 10. "MBSW3_STATUS_10,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 9. "MBSW3_STATUS_9,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 8. "MBSW3_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MBSW3_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MBSW3_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MBSW3_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MBSW3_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MBSW3_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW3_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW3_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW3_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x900++0x3 line.long 0x0 "STCU_MBSW3_ENDFLAG0,STCU Online MBIST3 end flag Register" bitfld.long 0x0 25. "MBSW3_ENDFLAG_25,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 24. "MBSW3_ENDFLAG_24,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 23. "MBSW3_ENDFLAG_23,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 22. "MBSW3_ENDFLAG_22,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 21. "MBSW3_ENDFLAG_21,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 20. "MBSW3_ENDFLAG_20,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 19. "MBSW3_ENDFLAG_19,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 18. "MBSW3_ENDFLAG_18,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 17. "MBSW3_ENDFLAG_17,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 16. "MBSW3_ENDFLAG_16,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MBSW3_ENDFLAG_15,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 14. "MBSW3_ENDFLAG_14,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MBSW3_ENDFLAG_13,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 12. "MBSW3_ENDFLAG_12,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MBSW3_ENDFLAG_11,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 10. "MBSW3_ENDFLAG_10,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MBSW3_ENDFLAG_9,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 8. "MBSW3_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MBSW3_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MBSW3_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MBSW3_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MBSW3_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBSW3_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW3_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW3_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW3_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x980++0x3 line.long 0x0 "STCU_MB3_UFM0,STCU MBIST3 Unrecoverable FM Register" bitfld.long 0x0 25. "MB3_UFM_25,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 24. "MB3_UFM_24,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 23. "MB3_UFM_23,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 22. "MB3_UFM_22,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 21. "MB3_UFM_21,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 20. "MB3_UFM_20,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 19. "MB3_UFM_19,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 18. "MB3_UFM_18,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 17. "MB3_UFM_17,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 16. "MB3_UFM_16,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 15. "MB3_UFM_15,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 14. "MB3_UFM_14,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 13. "MB3_UFM_13,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 12. "MB3_UFM_12,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 11. "MB3_UFM_11,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 10. "MB3_UFM_10,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 9. "MB3_UFM_9,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 8. "MB3_UFM_8,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 7. "MB3_UFM_7,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 6. "MB3_UFM_6,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 5. "MB3_UFM_5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 4. "MB3_UFM_4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MB3_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB3_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB3_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB3_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0xA00++0x3 line.long 0x0 "STCU_MB4_STATUS0,STCU Offline MBIST4 Status Register" bitfld.long 0x0 8. "MB4_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MB4_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MB4_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MB4_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MB4_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MB4_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB4_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB4_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB4_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0xA80++0x3 line.long 0x0 "STCU_MB4_ENDFLAG0,STCU Offline MBIST4 end flag Register" bitfld.long 0x0 8. "MB4_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MB4_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MB4_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MB4_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MB4_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MB4_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB4_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB4_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB4_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0xB00++0x3 line.long 0x0 "STCU_MBSW4_STATUS0,STCU Online MBIST4 Status Register" bitfld.long 0x0 8. "MBSW4_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MBSW4_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MBSW4_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MBSW4_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MBSW4_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MBSW4_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW4_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW4_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW4_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0xB80++0x3 line.long 0x0 "STCU_MBSW4_ENDFLAG0,STCU Online MBIST4 end flag Register" bitfld.long 0x0 8. "MBSW4_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MBSW4_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MBSW4_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MBSW4_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MBSW4_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBSW4_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW4_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW4_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW4_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0xC00++0x3 line.long 0x0 "STCU_MB4_UFM0,STCU MBIST4 Unrecoverable FM Register" bitfld.long 0x0 8. "MB4_UFM_8,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 7. "MB4_UFM_7,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 6. "MB4_UFM_6,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 5. "MB4_UFM_5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 4. "MB4_UFM_4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MB4_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB4_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB4_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB4_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0xC80++0x3 line.long 0x0 "STCU_MB5_STATUS0,STCU Offline MBIST5 Status Register" bitfld.long 0x0 6. "MB5_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MB5_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MB5_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MB5_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB5_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB5_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB5_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0xD00++0x3 line.long 0x0 "STCU_MB5_ENDFLAG0,STCU Offline MBIST5 end flag Register" bitfld.long 0x0 6. "MB5_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MB5_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MB5_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MB5_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB5_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB5_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB5_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0xD80++0x3 line.long 0x0 "STCU_MBSW5_STATUS0,STCU Online MBIST5 Status Register" bitfld.long 0x0 6. "MBSW5_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MBSW5_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MBSW5_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MBSW5_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW5_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW5_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW5_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0xE00++0x3 line.long 0x0 "STCU_MBSW5_ENDFLAG0,STCU Online MBIST5 end flag Register" bitfld.long 0x0 6. "MBSW5_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MBSW5_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MBSW5_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBSW5_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW5_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW5_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW5_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0xE80++0x3 line.long 0x0 "STCU_MB5_UFM0,STCU MBIST5 Unrecoverable FM Register" bitfld.long 0x0 6. "MB5_UFM_6,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 5. "MB5_UFM_5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 4. "MB5_UFM_4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MB5_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB5_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB5_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB5_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0xF00++0x7 line.long 0x0 "STCU_MB6_STATUS0,STCU Offline MBIST6 Status Register" bitfld.long 0x0 31. "MB6_STATUS_31,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 30. "MB6_STATUS_30,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 29. "MB6_STATUS_29,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 28. "MB6_STATUS_28,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 27. "MB6_STATUS_27,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 26. "MB6_STATUS_26,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 25. "MB6_STATUS_25,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 24. "MB6_STATUS_24,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 23. "MB6_STATUS_23,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 22. "MB6_STATUS_22,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 21. "MB6_STATUS_21,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 20. "MB6_STATUS_20,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 19. "MB6_STATUS_19,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 18. "MB6_STATUS_18,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 17. "MB6_STATUS_17,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 16. "MB6_STATUS_16,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 15. "MB6_STATUS_15,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 14. "MB6_STATUS_14,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 13. "MB6_STATUS_13,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 12. "MB6_STATUS_12,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 11. "MB6_STATUS_11,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 10. "MB6_STATUS_10,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 9. "MB6_STATUS_9,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 8. "MB6_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MB6_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MB6_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MB6_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MB6_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MB6_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB6_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB6_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB6_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" line.long 0x4 "STCU_MB6_STATUS1,STCU Offline MBIST6 Status Register" bitfld.long 0x4 11. "MB6_STATUS_43,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 10. "MB6_STATUS_42,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 9. "MB6_STATUS_41,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 8. "MB6_STATUS_40,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 7. "MB6_STATUS_39,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 6. "MB6_STATUS_38,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 5. "MB6_STATUS_37,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 4. "MB6_STATUS_36,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 3. "MB6_STATUS_35,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 2. "MB6_STATUS_34,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 1. "MB6_STATUS_33,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 0. "MB6_STATUS_32,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0xF80++0x7 line.long 0x0 "STCU_MB6_ENDFLAG0,STCU Offline MBIST6 end flag Register" bitfld.long 0x0 31. "MB6_ENDFLAG_31,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 30. "MB6_ENDFLAG_30,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 29. "MB6_ENDFLAG_29,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 28. "MB6_ENDFLAG_28,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 27. "MB6_ENDFLAG_27,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 26. "MB6_ENDFLAG_26,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 25. "MB6_ENDFLAG_25,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 24. "MB6_ENDFLAG_24,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 23. "MB6_ENDFLAG_23,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 22. "MB6_ENDFLAG_22,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 21. "MB6_ENDFLAG_21,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 20. "MB6_ENDFLAG_20,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 19. "MB6_ENDFLAG_19,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 18. "MB6_ENDFLAG_18,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 17. "MB6_ENDFLAG_17,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 16. "MB6_ENDFLAG_16,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MB6_ENDFLAG_15,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 14. "MB6_ENDFLAG_14,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MB6_ENDFLAG_13,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 12. "MB6_ENDFLAG_12,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MB6_ENDFLAG_11,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 10. "MB6_ENDFLAG_10,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MB6_ENDFLAG_9,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 8. "MB6_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MB6_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MB6_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MB6_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MB6_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MB6_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB6_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB6_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB6_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" line.long 0x4 "STCU_MB6_ENDFLAG1,STCU Offline MBIST7 end flag Register" bitfld.long 0x4 11. "MB6_ENDFLAG_43,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 10. "MB6_ENDFLAG_42,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 9. "MB6_ENDFLAG_41,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 8. "MB6_ENDFLAG_40,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 7. "MB6_ENDFLAG_39,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 6. "MB6_ENDFLAG_38,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 5. "MB6_ENDFLAG_37,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 4. "MB6_ENDFLAG_36,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 3. "MB6_ENDFLAG_35,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 2. "MB6_ENDFLAG_34,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 1. "MB6_ENDFLAG_33,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 0. "MB6_ENDFLAG_32,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x1000++0x7 line.long 0x0 "STCU_MBSW6_STATUS0,STCU Online MBIST6 Status Register" bitfld.long 0x0 31. "MBSW6_STATUS_31,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 30. "MBSW6_STATUS_30,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 29. "MBSW6_STATUS_29,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 28. "MBSW6_STATUS_28,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 27. "MBSW6_STATUS_27,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 26. "MBSW6_STATUS_26,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 25. "MBSW6_STATUS_25,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 24. "MBSW6_STATUS_24,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 23. "MBSW6_STATUS_23,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 22. "MBSW6_STATUS_22,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 21. "MBSW6_STATUS_21,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 20. "MBSW6_STATUS_20,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 19. "MBSW6_STATUS_19,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 18. "MBSW6_STATUS_18,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 17. "MBSW6_STATUS_17,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 16. "MBSW6_STATUS_16,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 15. "MBSW6_STATUS_15,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 14. "MBSW6_STATUS_14,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 13. "MBSW6_STATUS_13,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 12. "MBSW6_STATUS_12,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 11. "MBSW6_STATUS_11,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 10. "MBSW6_STATUS_10,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 9. "MBSW6_STATUS_9,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 8. "MBSW6_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MBSW6_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MBSW6_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MBSW6_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MBSW6_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MBSW6_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW6_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW6_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW6_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" line.long 0x4 "STCU_MBSW6_STATUS1,STCU Online MBIST6 Status Register" bitfld.long 0x4 11. "MBSW6_STATUS_43,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 10. "MBSW6_STATUS_42,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 9. "MBSW6_STATUS_41,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 8. "MBSW6_STATUS_40,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 7. "MBSW6_STATUS_39,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 6. "MBSW6_STATUS_38,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 5. "MBSW6_STATUS_37,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 4. "MBSW6_STATUS_36,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 3. "MBSW6_STATUS_35,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 2. "MBSW6_STATUS_34,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 1. "MBSW6_STATUS_33,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 0. "MBSW6_STATUS_32,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1080++0x7 line.long 0x0 "STCU_MBSW6_ENDFLAG0,STCU Online MBIST6 end flag Register" bitfld.long 0x0 31. "MBSW6_ENDFLAG_31,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 30. "MBSW6_ENDFLAG_30,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 29. "MBSW6_ENDFLAG_29,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 28. "MBSW6_ENDFLAG_28,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 27. "MBSW6_ENDFLAG_27,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 26. "MBSW6_ENDFLAG_26,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 25. "MBSW6_ENDFLAG_25,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 24. "MBSW6_ENDFLAG_24,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 23. "MBSW6_ENDFLAG_23,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 22. "MBSW6_ENDFLAG_22,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 21. "MBSW6_ENDFLAG_21,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 20. "MBSW6_ENDFLAG_20,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 19. "MBSW6_ENDFLAG_19,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 18. "MBSW6_ENDFLAG_18,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 17. "MBSW6_ENDFLAG_17,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 16. "MBSW6_ENDFLAG_16,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MBSW6_ENDFLAG_15,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 14. "MBSW6_ENDFLAG_14,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MBSW6_ENDFLAG_13,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 12. "MBSW6_ENDFLAG_12,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MBSW6_ENDFLAG_11,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 10. "MBSW6_ENDFLAG_10,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MBSW6_ENDFLAG_9,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 8. "MBSW6_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MBSW6_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MBSW6_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MBSW6_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MBSW6_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBSW6_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW6_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW6_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW6_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" line.long 0x4 "STCU_MBSW6_ENDFLAG1,STCU Online MBIST6 end flag Register" bitfld.long 0x4 11. "MBSW6_ENDFLAG_43,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 10. "MBSW6_ENDFLAG_42,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 9. "MBSW6_ENDFLAG_41,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 8. "MBSW6_ENDFLAG_40,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 7. "MBSW6_ENDFLAG_39,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 6. "MBSW6_ENDFLAG_38,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 5. "MBSW6_ENDFLAG_37,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 4. "MBSW6_ENDFLAG_36,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 3. "MBSW6_ENDFLAG_35,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 2. "MBSW6_ENDFLAG_34,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 1. "MBSW6_ENDFLAG_33,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 0. "MBSW6_ENDFLAG_32,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x1100++0x7 line.long 0x0 "STCU_MB6_UFM0,STCU MBIST6 Unrecoverable FM Register" bitfld.long 0x0 31. "MB6_UFM_31,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 30. "MB6_UFM_30,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 29. "MB6_UFM_29,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 28. "MB6_UFM_28,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 27. "MB6_UFM_27,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 26. "MB6_UFM_26,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 25. "MB6_UFM_25,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 24. "MB6_UFM_24,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 23. "MB6_UFM_23,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 22. "MB6_UFM_22,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 21. "MB6_UFM_21,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 20. "MB6_UFM_20,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 19. "MB6_UFM_19,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 18. "MB6_UFM_18,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 17. "MB6_UFM_17,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 16. "MB6_UFM_16,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 15. "MB6_UFM_15,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 14. "MB6_UFM_14,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 13. "MB6_UFM_13,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 12. "MB6_UFM_12,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 11. "MB6_UFM_11,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 10. "MB6_UFM_10,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 9. "MB6_UFM_9,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 8. "MB6_UFM_8,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 7. "MB6_UFM_7,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 6. "MB6_UFM_6,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 5. "MB6_UFM_5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 4. "MB6_UFM_4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MB6_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB6_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB6_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB6_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" line.long 0x4 "STCU_MB6_UFM1,STCU MBIST6 Unrecoverable FM Register" bitfld.long 0x4 11. "MB6_UFM_43,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 10. "MB6_UFM_42,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 9. "MB6_UFM_41,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 8. "MB6_UFM_40,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 7. "MB6_UFM_39,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 6. "MB6_UFM_38,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 5. "MB6_UFM_37,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 4. "MB6_UFM_36,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 3. "MB6_UFM_35,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 2. "MB6_UFM_34,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 1. "MB6_UFM_33,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 0. "MB6_UFM_32,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x1180++0x7 line.long 0x0 "STCU_MB7_STATUS0,STCU Offline MBIST7 Status Register" bitfld.long 0x0 31. "MB7_STATUS_31,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 30. "MB7_STATUS_30,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 29. "MB7_STATUS_29,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 28. "MB7_STATUS_28,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 27. "MB7_STATUS_27,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 26. "MB7_STATUS_26,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 25. "MB7_STATUS_25,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 24. "MB7_STATUS_24,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 23. "MB7_STATUS_23,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 22. "MB7_STATUS_22,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 21. "MB7_STATUS_21,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 20. "MB7_STATUS_20,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 19. "MB7_STATUS_19,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 18. "MB7_STATUS_18,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 17. "MB7_STATUS_17,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 16. "MB7_STATUS_16,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 15. "MB7_STATUS_15,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 14. "MB7_STATUS_14,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 13. "MB7_STATUS_13,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 12. "MB7_STATUS_12,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 11. "MB7_STATUS_11,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 10. "MB7_STATUS_10,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 9. "MB7_STATUS_9,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 8. "MB7_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MB7_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MB7_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MB7_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MB7_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MB7_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB7_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB7_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB7_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" line.long 0x4 "STCU_MB7_STATUS1,STCU Offline MBIST7 Status Register" bitfld.long 0x4 11. "MB7_STATUS_43,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 10. "MB7_STATUS_42,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 9. "MB7_STATUS_41,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 8. "MB7_STATUS_40,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 7. "MB7_STATUS_39,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 6. "MB7_STATUS_38,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 5. "MB7_STATUS_37,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 4. "MB7_STATUS_36,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 3. "MB7_STATUS_35,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 2. "MB7_STATUS_34,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 1. "MB7_STATUS_33,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 0. "MB7_STATUS_32,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1200++0x7 line.long 0x0 "STCU_MB7_ENDFLAG0,STCU Offline MBIST7 end flag Register" bitfld.long 0x0 31. "MB7_ENDFLAG_31,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 30. "MB7_ENDFLAG_30,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 29. "MB7_ENDFLAG_29,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 28. "MB7_ENDFLAG_28,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 27. "MB7_ENDFLAG_27,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 26. "MB7_ENDFLAG_26,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 25. "MB7_ENDFLAG_25,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 24. "MB7_ENDFLAG_24,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 23. "MB7_ENDFLAG_23,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 22. "MB7_ENDFLAG_22,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 21. "MB7_ENDFLAG_21,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 20. "MB7_ENDFLAG_20,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 19. "MB7_ENDFLAG_19,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 18. "MB7_ENDFLAG_18,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 17. "MB7_ENDFLAG_17,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 16. "MB7_ENDFLAG_16,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MB7_ENDFLAG_15,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 14. "MB7_ENDFLAG_14,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MB7_ENDFLAG_13,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 12. "MB7_ENDFLAG_12,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MB7_ENDFLAG_11,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 10. "MB7_ENDFLAG_10,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MB7_ENDFLAG_9,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 8. "MB7_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MB7_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MB7_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MB7_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MB7_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MB7_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB7_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB7_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB7_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" line.long 0x4 "STCU_MB7_ENDFLAG1,STCU Offline MBIST7 end flag Register" bitfld.long 0x4 11. "MB7_ENDFLAG_43,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 10. "MB7_ENDFLAG_42,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 9. "MB7_ENDFLAG_41,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 8. "MB7_ENDFLAG_40,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 7. "MB7_ENDFLAG_39,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 6. "MB7_ENDFLAG_38,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 5. "MB7_ENDFLAG_37,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 4. "MB7_ENDFLAG_36,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 3. "MB7_ENDFLAG_35,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 2. "MB7_ENDFLAG_34,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 1. "MB7_ENDFLAG_33,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 0. "MB7_ENDFLAG_32,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x1280++0x7 line.long 0x0 "STCU_MBSW7_STATUS0,STCU Online MBIST7 Status Register" bitfld.long 0x0 31. "MBSW7_STATUS_31,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 30. "MBSW7_STATUS_30,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 29. "MBSW7_STATUS_29,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 28. "MBSW7_STATUS_28,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 27. "MBSW7_STATUS_27,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 26. "MBSW7_STATUS_26,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 25. "MBSW7_STATUS_25,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 24. "MBSW7_STATUS_24,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 23. "MBSW7_STATUS_23,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 22. "MBSW7_STATUS_22,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 21. "MBSW7_STATUS_21,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 20. "MBSW7_STATUS_20,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 19. "MBSW7_STATUS_19,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 18. "MBSW7_STATUS_18,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 17. "MBSW7_STATUS_17,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 16. "MBSW7_STATUS_16,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 15. "MBSW7_STATUS_15,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 14. "MBSW7_STATUS_14,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 13. "MBSW7_STATUS_13,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 12. "MBSW7_STATUS_12,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 11. "MBSW7_STATUS_11,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 10. "MBSW7_STATUS_10,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 9. "MBSW7_STATUS_9,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 8. "MBSW7_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MBSW7_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MBSW7_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MBSW7_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MBSW7_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MBSW7_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW7_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW7_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW7_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" line.long 0x4 "STCU_MBSW7_STATUS1,STCU Online MBIST7 Status Register" bitfld.long 0x4 11. "MBSW7_STATUS_43,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 10. "MBSW7_STATUS_42,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 9. "MBSW7_STATUS_41,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 8. "MBSW7_STATUS_40,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 7. "MBSW7_STATUS_39,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 6. "MBSW7_STATUS_38,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 5. "MBSW7_STATUS_37,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 4. "MBSW7_STATUS_36,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 3. "MBSW7_STATUS_35,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 2. "MBSW7_STATUS_34,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 1. "MBSW7_STATUS_33,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 0. "MBSW7_STATUS_32,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1300++0x7 line.long 0x0 "STCU_MBSW7_ENDFLAG0,STCU Online MBIST7 end flag Register" bitfld.long 0x0 31. "MBSW7_ENDFLAG_31,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 30. "MBSW7_ENDFLAG_30,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 29. "MBSW7_ENDFLAG_29,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 28. "MBSW7_ENDFLAG_28,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 27. "MBSW7_ENDFLAG_27,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 26. "MBSW7_ENDFLAG_26,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 25. "MBSW7_ENDFLAG_25,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 24. "MBSW7_ENDFLAG_24,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 23. "MBSW7_ENDFLAG_23,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 22. "MBSW7_ENDFLAG_22,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 21. "MBSW7_ENDFLAG_21,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 20. "MBSW7_ENDFLAG_20,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 19. "MBSW7_ENDFLAG_19,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 18. "MBSW7_ENDFLAG_18,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 17. "MBSW7_ENDFLAG_17,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 16. "MBSW7_ENDFLAG_16,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MBSW7_ENDFLAG_15,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 14. "MBSW7_ENDFLAG_14,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MBSW7_ENDFLAG_13,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 12. "MBSW7_ENDFLAG_12,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MBSW7_ENDFLAG_11,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 10. "MBSW7_ENDFLAG_10,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MBSW7_ENDFLAG_9,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 8. "MBSW7_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MBSW7_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MBSW7_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MBSW7_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MBSW7_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBSW7_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW7_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW7_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW7_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" line.long 0x4 "STCU_MBSW7_ENDFLAG1,STCU Online MBIST7 end flag Register" bitfld.long 0x4 11. "MBSW7_ENDFLAG_43,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 10. "MBSW7_ENDFLAG_42,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 9. "MBSW7_ENDFLAG_41,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 8. "MBSW7_ENDFLAG_40,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 7. "MBSW7_ENDFLAG_39,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 6. "MBSW7_ENDFLAG_38,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 5. "MBSW7_ENDFLAG_37,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 4. "MBSW7_ENDFLAG_36,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 3. "MBSW7_ENDFLAG_35,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 2. "MBSW7_ENDFLAG_34,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 1. "MBSW7_ENDFLAG_33,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 0. "MBSW7_ENDFLAG_32,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x1380++0x7 line.long 0x0 "STCU_MB7_UFM0,STCU MBIST7 Unrecoverable FM Register" bitfld.long 0x0 31. "MB7_UFM_31,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 30. "MB7_UFM_30,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 29. "MB7_UFM_29,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 28. "MB7_UFM_28,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 27. "MB7_UFM_27,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 26. "MB7_UFM_26,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 25. "MB7_UFM_25,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 24. "MB7_UFM_24,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 23. "MB7_UFM_23,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 22. "MB7_UFM_22,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 21. "MB7_UFM_21,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 20. "MB7_UFM_20,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 19. "MB7_UFM_19,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 18. "MB7_UFM_18,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 17. "MB7_UFM_17,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 16. "MB7_UFM_16,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 15. "MB7_UFM_15,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 14. "MB7_UFM_14,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 13. "MB7_UFM_13,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 12. "MB7_UFM_12,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 11. "MB7_UFM_11,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 10. "MB7_UFM_10,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 9. "MB7_UFM_9,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 8. "MB7_UFM_8,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 7. "MB7_UFM_7,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 6. "MB7_UFM_6,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 5. "MB7_UFM_5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 4. "MB7_UFM_4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MB7_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB7_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB7_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB7_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" line.long 0x4 "STCU_MB7_UFM1,STCU MBIST7 Unrecoverable FM Register" bitfld.long 0x4 11. "MB7_UFM_43,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 10. "MB7_UFM_42,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 9. "MB7_UFM_41,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 8. "MB7_UFM_40,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 7. "MB7_UFM_39,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 6. "MB7_UFM_38,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 5. "MB7_UFM_37,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 4. "MB7_UFM_36,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 3. "MB7_UFM_35,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 2. "MB7_UFM_34,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 1. "MB7_UFM_33,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 0. "MB7_UFM_32,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x1400++0x7 line.long 0x0 "STCU_MB8_STATUS0,STCU Offline MBIST8 Status Register" bitfld.long 0x0 31. "MB8_STATUS_31,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 30. "MB8_STATUS_30,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 29. "MB8_STATUS_29,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 28. "MB8_STATUS_28,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 27. "MB8_STATUS_27,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 26. "MB8_STATUS_26,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 25. "MB8_STATUS_25,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 24. "MB8_STATUS_24,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 23. "MB8_STATUS_23,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 22. "MB8_STATUS_22,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 21. "MB8_STATUS_21,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 20. "MB8_STATUS_20,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 19. "MB8_STATUS_19,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 18. "MB8_STATUS_18,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 17. "MB8_STATUS_17,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 16. "MB8_STATUS_16,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 15. "MB8_STATUS_15,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 14. "MB8_STATUS_14,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 13. "MB8_STATUS_13,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 12. "MB8_STATUS_12,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 11. "MB8_STATUS_11,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 10. "MB8_STATUS_10,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 9. "MB8_STATUS_9,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 8. "MB8_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MB8_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MB8_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MB8_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MB8_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MB8_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB8_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB8_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB8_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" line.long 0x4 "STCU_MB8_STATUS1,STCU Offline MBIST8 Status Register" bitfld.long 0x4 11. "MB8_STATUS_43,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 10. "MB8_STATUS_42,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 9. "MB8_STATUS_41,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 8. "MB8_STATUS_40,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 7. "MB8_STATUS_39,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 6. "MB8_STATUS_38,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 5. "MB8_STATUS_37,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 4. "MB8_STATUS_36,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 3. "MB8_STATUS_35,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 2. "MB8_STATUS_34,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 1. "MB8_STATUS_33,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 0. "MB8_STATUS_32,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1480++0x7 line.long 0x0 "STCU_MB8_ENDFLAG0,STCU Offline MBIST8 end flag Register" bitfld.long 0x0 31. "MB8_ENDFLAG_31,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 30. "MB8_ENDFLAG_30,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 29. "MB8_ENDFLAG_29,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 28. "MB8_ENDFLAG_28,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 27. "MB8_ENDFLAG_27,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 26. "MB8_ENDFLAG_26,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 25. "MB8_ENDFLAG_25,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 24. "MB8_ENDFLAG_24,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 23. "MB8_ENDFLAG_23,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 22. "MB8_ENDFLAG_22,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 21. "MB8_ENDFLAG_21,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 20. "MB8_ENDFLAG_20,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 19. "MB8_ENDFLAG_19,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 18. "MB8_ENDFLAG_18,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 17. "MB8_ENDFLAG_17,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 16. "MB8_ENDFLAG_16,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MB8_ENDFLAG_15,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 14. "MB8_ENDFLAG_14,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MB8_ENDFLAG_13,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 12. "MB8_ENDFLAG_12,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MB8_ENDFLAG_11,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 10. "MB8_ENDFLAG_10,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MB8_ENDFLAG_9,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 8. "MB8_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MB8_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MB8_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MB8_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MB8_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MB8_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB8_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB8_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB8_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" line.long 0x4 "STCU_MB8_ENDFLAG1,STCU Offline MBIST8 end flag Register" bitfld.long 0x4 11. "MB8_ENDFLAG_43,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 10. "MB8_ENDFLAG_42,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 9. "MB8_ENDFLAG_41,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 8. "MB8_ENDFLAG_40,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 7. "MB8_ENDFLAG_39,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 6. "MB8_ENDFLAG_38,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 5. "MB8_ENDFLAG_37,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 4. "MB8_ENDFLAG_36,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 3. "MB8_ENDFLAG_35,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 2. "MB8_ENDFLAG_34,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 1. "MB8_ENDFLAG_33,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 0. "MB8_ENDFLAG_32,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x1500++0x7 line.long 0x0 "STCU_MBSW8_STATUS0,STCU Online MBIST8 Status Register" bitfld.long 0x0 31. "MBSW8_STATUS_31,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 30. "MBSW8_STATUS_30,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 29. "MBSW8_STATUS_29,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 28. "MBSW8_STATUS_28,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 27. "MBSW8_STATUS_27,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 26. "MBSW8_STATUS_26,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 25. "MBSW8_STATUS_25,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 24. "MBSW8_STATUS_24,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 23. "MBSW8_STATUS_23,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 22. "MBSW8_STATUS_22,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 21. "MBSW8_STATUS_21,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 20. "MBSW8_STATUS_20,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 19. "MBSW8_STATUS_19,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 18. "MBSW8_STATUS_18,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 17. "MBSW8_STATUS_17,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 16. "MBSW8_STATUS_16,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 15. "MBSW8_STATUS_15,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 14. "MBSW8_STATUS_14,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 13. "MBSW8_STATUS_13,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 12. "MBSW8_STATUS_12,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 11. "MBSW8_STATUS_11,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 10. "MBSW8_STATUS_10,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 9. "MBSW8_STATUS_9,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 8. "MBSW8_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MBSW8_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MBSW8_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MBSW8_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MBSW8_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MBSW8_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW8_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW8_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW8_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" line.long 0x4 "STCU_MBSW8_STATUS1,STCU Online MBIST8 Status Register" bitfld.long 0x4 11. "MBSW8_STATUS_43,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 10. "MBSW8_STATUS_42,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 9. "MBSW8_STATUS_41,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 8. "MBSW8_STATUS_40,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 7. "MBSW8_STATUS_39,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 6. "MBSW8_STATUS_38,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 5. "MBSW8_STATUS_37,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 4. "MBSW8_STATUS_36,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 3. "MBSW8_STATUS_35,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 2. "MBSW8_STATUS_34,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 1. "MBSW8_STATUS_33,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x4 0. "MBSW8_STATUS_32,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1580++0x7 line.long 0x0 "STCU_MBSW8_ENDFLAG0,STCU Online MBIST8 end flag Register" bitfld.long 0x0 31. "MBSW8_ENDFLAG_31,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 30. "MBSW8_ENDFLAG_30,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 29. "MBSW8_ENDFLAG_29,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 28. "MBSW8_ENDFLAG_28,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 27. "MBSW8_ENDFLAG_27,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 26. "MBSW8_ENDFLAG_26,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 25. "MBSW8_ENDFLAG_25,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 24. "MBSW8_ENDFLAG_24,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 23. "MBSW8_ENDFLAG_23,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 22. "MBSW8_ENDFLAG_22,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 21. "MBSW8_ENDFLAG_21,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 20. "MBSW8_ENDFLAG_20,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 19. "MBSW8_ENDFLAG_19,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 18. "MBSW8_ENDFLAG_18,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 17. "MBSW8_ENDFLAG_17,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 16. "MBSW8_ENDFLAG_16,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MBSW8_ENDFLAG_15,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 14. "MBSW8_ENDFLAG_14,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MBSW8_ENDFLAG_13,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 12. "MBSW8_ENDFLAG_12,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MBSW8_ENDFLAG_11,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 10. "MBSW8_ENDFLAG_10,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MBSW8_ENDFLAG_9,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 8. "MBSW8_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MBSW8_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MBSW8_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MBSW8_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MBSW8_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBSW8_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW8_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW8_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW8_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" line.long 0x4 "STCU_MBSW8_ENDFLAG1,STCU Online MBIST8 end flag Register" bitfld.long 0x4 11. "MBSW8_ENDFLAG_43,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 10. "MBSW8_ENDFLAG_42,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 9. "MBSW8_ENDFLAG_41,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 8. "MBSW8_ENDFLAG_40,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 7. "MBSW8_ENDFLAG_39,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 6. "MBSW8_ENDFLAG_38,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 5. "MBSW8_ENDFLAG_37,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 4. "MBSW8_ENDFLAG_36,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 3. "MBSW8_ENDFLAG_35,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 2. "MBSW8_ENDFLAG_34,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 1. "MBSW8_ENDFLAG_33,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 0. "MBSW8_ENDFLAG_32,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x1600++0x7 line.long 0x0 "STCU_MB8_UFM0,STCU MBIST8 Unrecoverable FM Register" bitfld.long 0x0 31. "MB8_UFM_31,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 30. "MB8_UFM_30,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 29. "MB8_UFM_29,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 28. "MB8_UFM_28,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 27. "MB8_UFM_27,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 26. "MB8_UFM_26,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 25. "MB8_UFM_25,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 24. "MB8_UFM_24,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 23. "MB8_UFM_23,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 22. "MB8_UFM_22,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 21. "MB8_UFM_21,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 20. "MB8_UFM_20,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 19. "MB8_UFM_19,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 18. "MB8_UFM_18,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 17. "MB8_UFM_17,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 16. "MB8_UFM_16,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 15. "MB8_UFM_15,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 14. "MB8_UFM_14,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 13. "MB8_UFM_13,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 12. "MB8_UFM_12,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 11. "MB8_UFM_11,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 10. "MB8_UFM_10,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 9. "MB8_UFM_9,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 8. "MB8_UFM_8,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 7. "MB8_UFM_7,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 6. "MB8_UFM_6,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 5. "MB8_UFM_5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 4. "MB8_UFM_4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MB8_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB8_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB8_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB8_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" line.long 0x4 "STCU_MB8_UFM1,STCU MBIST8 Unrecoverable FM Register" bitfld.long 0x4 11. "MB8_UFM_43,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 10. "MB8_UFM_42,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 9. "MB8_UFM_41,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 8. "MB8_UFM_40,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 7. "MB8_UFM_39,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 6. "MB8_UFM_38,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 5. "MB8_UFM_37,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 4. "MB8_UFM_36,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 3. "MB8_UFM_35,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 2. "MB8_UFM_34,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 1. "MB8_UFM_33,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 0. "MB8_UFM_32,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x1680++0x3 line.long 0x0 "STCU_MB9_STATUS0,STCU Offline MBIST9 Status Register" bitfld.long 0x0 3. "MB9_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB9_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB9_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB9_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1700++0x3 line.long 0x0 "STCU_MB9_ENDFLAG0,STCU Offline MBIST9 end flag Register" bitfld.long 0x0 3. "MB9_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB9_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB9_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB9_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x1780++0x3 line.long 0x0 "STCU_MBSW9_STATUS0,STCU Online MBIST9 Status Register" bitfld.long 0x0 3. "MBSW9_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW9_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW9_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW9_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1800++0x3 line.long 0x0 "STCU_MBSW9_ENDFLAG0,STCU Online MBIST9 end flag Register" bitfld.long 0x0 3. "MBSW9_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW9_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW9_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW9_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x1880++0x3 line.long 0x0 "STCU_MB9_UFM0,STCU MBIST9 Unrecoverable FM Register" bitfld.long 0x0 3. "MB9_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB9_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB9_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB9_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x1900++0x3 line.long 0x0 "STCU_MB10_STATUS0,STCU Offline MBIST10 Status Register" bitfld.long 0x0 3. "MB10_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB10_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB10_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB10_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1980++0x3 line.long 0x0 "STCU_MB10_ENDFLAG0,STCU Offline MBIST10 end flag Register" bitfld.long 0x0 3. "MB10_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB10_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB10_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB10_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x1A00++0x3 line.long 0x0 "STCU_MBSW10_STATUS0,STCU Online MBIST10 Status Register" bitfld.long 0x0 3. "MBSW10_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW10_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW10_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW10_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1A80++0x3 line.long 0x0 "STCU_MBSW10_ENDFLAG0,STCU Online MBIST10 end flag Register" bitfld.long 0x0 3. "MBSW10_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW10_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW10_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW10_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x1B00++0x3 line.long 0x0 "STCU_MB10_UFM0,STCU MBIST10 Unrecoverable FM Register" bitfld.long 0x0 3. "MB10_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB10_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB10_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB10_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x1B80++0x3 line.long 0x0 "STCU_MB11_STATUS0,STCU Offline MBIST11 Status Register" bitfld.long 0x0 3. "MB11_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB11_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB11_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB11_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1C00++0x3 line.long 0x0 "STCU_MB11_ENDFLAG0,STCU Offline MBIST11 end flag Register" bitfld.long 0x0 3. "MB11_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB11_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB11_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB11_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x1C80++0x3 line.long 0x0 "STCU_MBSW11_STATUS0,STCU Online MBIST11 Status Register" bitfld.long 0x0 3. "MBSW11_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW11_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW11_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW11_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1D00++0x3 line.long 0x0 "STCU_MBSW11_ENDFLAG0,STCU Online MBIST11 end flag Register" bitfld.long 0x0 3. "MBSW11_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW11_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW11_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW11_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x1D80++0x3 line.long 0x0 "STCU_MB11_UFM0,STCU MBIST11 Unrecoverable FM Register" bitfld.long 0x0 3. "MB11_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB11_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB11_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB11_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x1E00++0x3 line.long 0x0 "STCU_MB12_STATUS0,STCU Offline MBIST12 Status Register" bitfld.long 0x0 7. "MB12_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MB12_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MB12_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MB12_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MB12_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB12_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB12_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB12_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1E80++0x3 line.long 0x0 "STCU_MB12_ENDFLAG0,STCU Offline MBIST12 end flag Register" bitfld.long 0x0 7. "MB12_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MB12_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MB12_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MB12_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MB12_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB12_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB12_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB12_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x1F00++0x3 line.long 0x0 "STCU_MBSW12_STATUS0,STCU Online MBIST12 Status Register" bitfld.long 0x0 7. "MBSW12_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MBSW12_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MBSW12_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MBSW12_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MBSW12_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW12_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW12_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW12_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x1F80++0x3 line.long 0x0 "STCU_MBSW12_ENDFLAG0,STCU Online MBIST12 end flag Register" bitfld.long 0x0 7. "MBSW12_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MBSW12_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MBSW12_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MBSW12_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBSW12_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW12_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW12_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW12_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x2000++0x3 line.long 0x0 "STCU_MB12_UFM0,STCU MBIST12 Unrecoverable FM Register" bitfld.long 0x0 7. "MB12_UFM_7,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 6. "MB12_UFM_6,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 5. "MB12_UFM_5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 4. "MB12_UFM_4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MB12_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB12_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB12_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB12_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x2080++0x3 line.long 0x0 "STCU_MB13_STATUS0,STCU Offline MBIST13 Status Register" bitfld.long 0x0 5. "MB13_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MB13_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MB13_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB13_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB13_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB13_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x2100++0x3 line.long 0x0 "STCU_MB13_ENDFLAG0,STCU Offline MBIST13 end flag Register" bitfld.long 0x0 5. "MB13_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MB13_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MB13_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB13_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB13_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB13_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x2180++0x3 line.long 0x0 "STCU_MBSW13_STATUS0,STCU Online MBIST13 Status Register" bitfld.long 0x0 5. "MBSW13_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MBSW13_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MBSW13_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW13_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW13_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW13_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x2200++0x3 line.long 0x0 "STCU_MBSW13_ENDFLAG0,STCU Online MBIST13 end flag Register" bitfld.long 0x0 5. "MBSW13_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MBSW13_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBSW13_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW13_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW13_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW13_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x2280++0x3 line.long 0x0 "STCU_MB13_UFM0,STCU MBIST13 Unrecoverable FM Register" bitfld.long 0x0 5. "MB13_UFM_5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 4. "MB13_UFM_4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MB13_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB13_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB13_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB13_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" rgroup.long 0x2300++0x3 line.long 0x0 "STCU_MB14_STATUS0,STCU Offline MBIST14 Status Register" bitfld.long 0x0 8. "MB14_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MB14_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MB14_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MB14_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MB14_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MB14_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MB14_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MB14_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MB14_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x2380++0x3 line.long 0x0 "STCU_MB14_ENDFLAG0,STCU Offline MBIST14 end flag Register" bitfld.long 0x0 8. "MB14_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MB14_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MB14_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MB14_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MB14_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MB14_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MB14_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MB14_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MB14_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" rgroup.long 0x2400++0x3 line.long 0x0 "STCU_MBSW14_STATUS0,STCU Online MBIST14 Status Register" bitfld.long 0x0 8. "MBSW14_STATUS_8,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 7. "MBSW14_STATUS_7,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 6. "MBSW14_STATUS_6,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 5. "MBSW14_STATUS_5,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 4. "MBSW14_STATUS_4,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 3. "MBSW14_STATUS_3,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 2. "MBSW14_STATUS_2,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 1. "MBSW14_STATUS_1,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" newline bitfld.long 0x0 0. "MBSW14_STATUS_0,0 : Failed NMCUT BIST execution." "0: Failed NMCUT BIST execution,1: No Fault detected during the NMCUT BIST execution" rgroup.long 0x2480++0x3 line.long 0x0 "STCU_MBSW14_ENDFLAG0,STCU Online MBIST14 end flag Register" bitfld.long 0x0 8. "MBSW14_ENDFLAG_8,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MBSW14_ENDFLAG_7,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 6. "MBSW14_ENDFLAG_6,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MBSW14_ENDFLAG_5,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 4. "MBSW14_ENDFLAG_4,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBSW14_ENDFLAG_3,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 2. "MBSW14_ENDFLAG_2,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBSW14_ENDFLAG_1,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 0. "MBSW14_ENDFLAG_0,0 : MBIST execution still ongoing." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x2500++0x3 line.long 0x0 "STCU_MB14_UFM0,STCU MBIST14 Unrecoverable FM Register" bitfld.long 0x0 8. "MB14_UFM_8,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 7. "MB14_UFM_7,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 6. "MB14_UFM_6,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 5. "MB14_UFM_5,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 4. "MB14_UFM_4,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MB14_UFM_3,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 2. "MB14_UFM_2,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MB14_UFM_1,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 0. "MB14_UFM_0,0 : Recoverable fault mapping." "0: Recoverable fault mapping,1: Unrecoverable fault mapping" tree.end tree.end tree "STLA (Sequence Trigger Logic Analyzer)" base ad:0x7C118000 group.long 0x0++0x2F line.long 0x0 "L1SEL0,Level1 MUX Selection 0 register" bitfld.long 0x0 28.--30. "MUX_7,Input trigger selection bits for MUX 7." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "MUX_6,Input trigger selection bits for MUX 6." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "MUX_5,Input trigger selection bits for MUX 5." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "MUX_4,Input trigger selection bits for MUX 4." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "MUX_3,Input trigger selection bits for MUX 3." "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "MUX_2,Input trigger selection bits for MUX 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "MUX_1,Input trigger selection bits for MUX 1." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "MUX_0,Input trigger selection bits for MUX 0." "0,1,2,3,4,5,6,7" line.long 0x4 "L1SEL1,Level1 MUX Selection 1 register" bitfld.long 0x4 28.--30. "MUX_15,Input trigger selection bits for MUX 15." "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "MUX_14,Input trigger selection bits for MUX 14." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20.--22. "MUX_13,Input trigger selection bits for MUX 13." "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "MUX_12,Input trigger selection bits for MUX 12." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12.--14. "MUX_11,Input trigger selection bits for MUX 11." "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "MUX_10,Input trigger selection bits for MUX 10." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "MUX_9,Input trigger selection bits for MUX 9." "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "MUX_8,Input trigger selection bits for MUX 8." "0,1,2,3,4,5,6,7" line.long 0x8 "L1SEL2,Level1 MUX Selection 2 register" bitfld.long 0x8 28.--30. "MUX_23,Input trigger selection bits for MUX 23." "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "MUX_22,Input trigger selection bits for MUX 22." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20.--22. "MUX_21,Input trigger selection bits for MUX 21." "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "MUX_20,Input trigger selection bits for MUX 20." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 12.--14. "MUX_19,Input trigger selection bits for MUX 19." "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "MUX_18,Input trigger selection bits for MUX 18." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4.--6. "MUX_17,Input trigger selection bits for MUX 17." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "MUX_16,Input trigger selection bits for MUX 16." "0,1,2,3,4,5,6,7" line.long 0xC "L1SEL3,Level1 MUX Selection 3 register" bitfld.long 0xC 28.--30. "MUX_31,Input trigger selection bits for MUX 31." "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "MUX_30,Input trigger selection bits for MUX 30." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 20.--22. "MUX_29,Input trigger selection bits for MUX 29." "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "MUX_28,Input trigger selection bits for MUX 28." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "MUX_27,Input trigger selection bits for MUX 27." "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--10. "MUX_26,Input trigger selection bits for MUX 26." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4.--6. "MUX_25,Input trigger selection bits for MUX 25." "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "MUX_24,Input trigger selection bits for MUX 24." "0,1,2,3,4,5,6,7" line.long 0x10 "L1SEL4,Level1 MUX Selection 4 register" bitfld.long 0x10 28.--30. "MUX_39,Input trigger selection bits for MUX 39." "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "MUX_38,Input trigger selection bits for MUX 38." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 20.--22. "MUX_37,Input trigger selection bits for MUX 37." "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "MUX_36,Input trigger selection bits for MUX 36." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 12.--14. "MUX_35,Input trigger selection bits for MUX 35." "0,1,2,3,4,5,6,7" bitfld.long 0x10 8.--10. "MUX_34,Input trigger selection bits for MUX 34." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 4.--6. "MUX_33,Input trigger selection bits for MUX 33." "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "MUX_32,Input trigger selection bits for MUX 32." "0,1,2,3,4,5,6,7" line.long 0x14 "L1SEL5,Level1 MUX Selection 5 register" bitfld.long 0x14 28.--30. "MUX_47,Input trigger selection bits for MUX 47." "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "MUX_46,Input trigger selection bits for MUX 46." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 20.--22. "MUX_45,Input trigger selection bits for MUX 45." "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "MUX_44,Input trigger selection bits for MUX 44." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "MUX_43,Input trigger selection bits for MUX 43." "0,1,2,3,4,5,6,7" bitfld.long 0x14 8.--10. "MUX_42,Input trigger selection bits for MUX 42." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 4.--6. "MUX_41,Input trigger selection bits for MUX 41." "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "MUX_40,Input trigger selection bits for MUX 40." "0,1,2,3,4,5,6,7" line.long 0x18 "L1SEL6,Level1 MUX Selection 6 register" bitfld.long 0x18 28.--30. "MUX_55,Input trigger selection bits for MUX 55." "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "MUX_54,Input trigger selection bits for MUX 54." "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 20.--22. "MUX_53,Input trigger selection bits for MUX 53." "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "MUX_52,Input trigger selection bits for MUX 52." "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "MUX_51,Input trigger selection bits for MUX 51." "0,1,2,3,4,5,6,7" bitfld.long 0x18 8.--10. "MUX_50,Input trigger selection bits for MUX 50." "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 4.--6. "MUX_49,Input trigger selection bits for MUX 49." "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "MUX_48,Input trigger selection bits for MUX 48." "0,1,2,3,4,5,6,7" line.long 0x1C "L1SEL7,Level1 MUX Selection 7 register" bitfld.long 0x1C 28.--30. "MUX_63,Input trigger selection bits for MUX 63." "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--26. "MUX_62,Input trigger selection bits for MUX 62." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 20.--22. "MUX_61,Input trigger selection bits for MUX 61." "0,1,2,3,4,5,6,7" bitfld.long 0x1C 16.--18. "MUX_60,Input trigger selection bits for MUX 60." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 12.--14. "MUX_59,Input trigger selection bits for MUX 59." "0,1,2,3,4,5,6,7" bitfld.long 0x1C 8.--10. "MUX_58,Input trigger selection bits for MUX 58." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 4.--6. "MUX_57,Input trigger selection bits for MUX 57." "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "MUX_56,Input trigger selection bits for MUX 56." "0,1,2,3,4,5,6,7" line.long 0x20 "ITLD0,Input Triggers Level Detection control 0 register" bitfld.long 0x20 30.--31. "MUX15,MUX15 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x20 28.--29. "MUX14,MUX14 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x20 26.--27. "MUX13,MUX13 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x20 24.--25. "MUX12,MUX12 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x20 22.--23. "MUX11,MUX11 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x20 20.--21. "MUX10,MUX10 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x20 18.--19. "MUX9,MUX9 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x20 16.--17. "MUX8,MUX8" "0,1,2,3" newline bitfld.long 0x20 14.--15. "MUX7,MUX7 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x20 12.--13. "MUX6,MUX6 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x20 10.--11. "MUX5,MUX5 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x20 8.--9. "MUX4,MUX4 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x20 6.--7. "MUX3,MUX3 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x20 4.--5. "MUX2,MUX2 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x20 2.--3. "MUX1,MUX1 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x20 0.--1. "MUX0,MUX0 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" line.long 0x24 "ITLD1,Input Triggers Level Detection control 1 register" bitfld.long 0x24 30.--31. "MUX31,MUX31 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x24 28.--29. "MUX30,MUX30 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x24 26.--27. "MUX29,MUX29 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x24 24.--25. "MUX28,MUX28 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x24 22.--23. "MUX27,MUX27 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x24 20.--21. "MUX26,MUX26 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x24 18.--19. "MUX25,MUX25 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x24 16.--17. "MUX24,MUX24 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x24 14.--15. "MUX23,MUX23 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x24 12.--13. "MUX22,MUX22 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x24 10.--11. "MUX21,MUX21 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x24 8.--9. "MUX20,MUX20 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x24 6.--7. "MUX19,MUX19 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x24 4.--5. "MUX18,MUX18 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x24 2.--3. "MUX17,MUX17 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x24 0.--1. "MUX16,MUX16 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" line.long 0x28 "ITLD2,Input Triggers Level Detection control 2 register" bitfld.long 0x28 30.--31. "MUX47,MUX47 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x28 28.--29. "MUX46,MUX46 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x28 26.--27. "MUX45,MUX45 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x28 24.--25. "MUX44,MUX44 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x28 22.--23. "MUX43,MUX43 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x28 20.--21. "MUX42,MUX42 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x28 18.--19. "MUX41,MUX41 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x28 16.--17. "MUX40,MUX40 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x28 14.--15. "MUX39,MUX39 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x28 12.--13. "MUX38,MUX38 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x28 10.--11. "MUX37,MUX37 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x28 8.--9. "MUX36,MUX36 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x28 6.--7. "MUX35,MUX35 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x28 4.--5. "MUX34,MUX34 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x28 2.--3. "MUX33,MUX33 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x28 0.--1. "MUX32,MUX32 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" line.long 0x2C "ITLD3,Input Triggers Level Detection control 3 register" bitfld.long 0x2C 30.--31. "MUX63,MUX63 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x2C 28.--29. "MUX62,MUX62 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x2C 26.--27. "MUX61,MUX61 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x2C 24.--25. "MUX60,MUX60 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x2C 22.--23. "MUX59,MUX59 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x2C 20.--21. "MUX58,MUX58 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x2C 18.--19. "MUX57,MUX57 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x2C 16.--17. "MUX56,MUX56 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x2C 14.--15. "MUX55,MUX55 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x2C 12.--13. "MUX54,MUX54 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x2C 10.--11. "MUX53,MUX53 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x2C 8.--9. "MUX52,MUX52 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x2C 6.--7. "MUX51,MUX51 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x2C 4.--5. "MUX50,MUX50 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" newline bitfld.long 0x2C 2.--3. "MUX49,MUX49 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" bitfld.long 0x2C 0.--1. "MUX48,MUX48 Output Signal Detection" "0: Level detection (default),1: Posedge detection,2: Toggle detection,3: Level detection" group.long 0x60++0x17 line.long 0x0 "CL0CORE0RPR,Cluster0 Core0 Running interrupt Priority selection register" hexmask.long.byte 0x0 0.--7. 1. "RPR_COMP,Current or running interrupt priority comparison value. On match with the input running priority vector a trigger is generated to Level1 MUXs. The typical use case would be for posedge detection on match (to detect when the priority level is set.." line.long 0x4 "CL0CORE1RPR,Cluster0 Core1 Running interrupt Priority selection register" hexmask.long.byte 0x4 0.--7. 1. "RPR_COMP,Current or running interrupt priority comparison value. On match with the input running priority vector a trigger is generated to Level1 MUXs. The typical use case would be for posedge detection on match (to detect when the priority level is set.." line.long 0x8 "CL1CORE0RPR,Cluster1 Core0 Running interrupt Priority selection register" hexmask.long.byte 0x8 0.--7. 1. "RPR_COMP,Current or running interrupt priority comparison value. On match with the input running priority vector a trigger is generated to Level1 MUXs. The typical use case would be for posedge detection on match (to detect when the priority level is set.." line.long 0xC "CL1CORE1RPR,Cluster1 Core1 Running interrupt Priority selection register" hexmask.long.byte 0xC 0.--7. 1. "RPR_COMP,Current or running interrupt priority comparison value. On match with the input running priority vector a trigger is generated to Level1 MUXs. The typical use case would be for posedge detection on match (to detect when the priority level is set.." line.long 0x10 "CL2CORE0RPR,Cluster2 Core0 Running interrupt Priority selection register" hexmask.long.byte 0x10 0.--7. 1. "RPR_COMP,Current or running interrupt priority comparison value. On match with the input running priority vector a trigger is generated to Level1 MUXs. The typical use case would be for posedge detection on match (to detect when the priority level is set.." line.long 0x14 "CL2CORE1RPR,Cluster2 Core1 Running interrupt Priority selection register" hexmask.long.byte 0x14 0.--7. 1. "RPR_COMP,Current or running interrupt priority comparison value. On match with the input running priority vector a trigger is generated to Level1 MUXs. The typical use case would be for posedge detection on match (to detect when the priority level is set.." group.long 0x90++0xC7 line.long 0x0 "L2S0SEL0,Level2 MUX state 0 selection 0 register" hexmask.long.byte 0x0 24.--29. 1. "FIRSTANDI0PUT4,First AND Gate Input 4 Selection" hexmask.long.byte 0x0 16.--21. 1. "FIRSTANDI0PUT3,First AND Gate Input 3 Selection" newline hexmask.long.byte 0x0 8.--13. 1. "FIRSTANDI0PUT2,First AND Gate Input 2 Selection" hexmask.long.byte 0x0 0.--5. 1. "FIRSTANDI0PUT1,First AND Gate Input 1 Selection" line.long 0x4 "L2S0SEL1,Level2 MUX state 0 selection 1 register" hexmask.long.byte 0x4 24.--29. 1. "SECO0DANDINPUT4,Second AND Gate Input 4 Selection" hexmask.long.byte 0x4 16.--21. 1. "SECO0DANDINPUT3,Second AND Gate Input 3 Selection" newline hexmask.long.byte 0x4 8.--13. 1. "SECO0DANDINPUT2,Second AND Gate Input 2 Selection" hexmask.long.byte 0x4 0.--5. 1. "SECO0DANDINPUT1,Second AND Gate Input 1 Selection" line.long 0x8 "L2S0SEL2,Level2 MUX state 0 selection 2 register" hexmask.long.byte 0x8 24.--29. 1. "THIRDANDI0PUT4,Third AND Gate Input 4 Selection" hexmask.long.byte 0x8 16.--21. 1. "THIRDANDI0PUT3,Third AND Gate Input 3 Selection" newline hexmask.long.byte 0x8 8.--13. 1. "THIRDANDI0PUT2,Third AND Gate Input 2 Selection" hexmask.long.byte 0x8 0.--5. 1. "THIRDANDI0PUT1,Third AND Gate Input 1 Selection" line.long 0xC "L2S0SEL3,Level2 MUX state 0 selection 3 register" hexmask.long.byte 0xC 24.--29. 1. "FOURTHANDI0PUT4,Fourth AND Gate Input 4 Selection" hexmask.long.byte 0xC 16.--21. 1. "FOURTHANDI0PUT3,Fourth AND Gate Input 3 Selection" newline hexmask.long.byte 0xC 8.--13. 1. "FOURTHANDI0PUT2,Fourth AND Gate Input 2 Selection" hexmask.long.byte 0xC 0.--5. 1. "FOURTHANDI0PUT1,Fourth AND Gate Input 1 Selection" line.long 0x10 "L2S1SEL0,Level2 MUX state 1 selection 0 register" hexmask.long.byte 0x10 24.--29. 1. "FIRSTANDI1PUT4,First AND Gate Input 4 Selection" hexmask.long.byte 0x10 16.--21. 1. "FIRSTANDI1PUT3,First AND Gate Input 3 Selection" newline hexmask.long.byte 0x10 8.--13. 1. "FIRSTANDI1PUT2,First AND Gate Input 2 Selection" hexmask.long.byte 0x10 0.--5. 1. "FIRSTANDI1PUT1,First AND Gate Input 1 Selection" line.long 0x14 "L2S1SEL1,Level2 MUX state 1 selection 1 register" hexmask.long.byte 0x14 24.--29. 1. "SECO1DANDINPUT4,Second AND Gate Input 4 Selection" hexmask.long.byte 0x14 16.--21. 1. "SECO1DANDINPUT3,Second AND Gate Input 3 Selection" newline hexmask.long.byte 0x14 8.--13. 1. "SECO1DANDINPUT2,Second AND Gate Input 2 Selection" hexmask.long.byte 0x14 0.--5. 1. "SECO1DANDINPUT1,Second AND Gate Input 1 Selection" line.long 0x18 "L2S1SEL2,Level2 MUX state 1 selection 2 register" hexmask.long.byte 0x18 24.--29. 1. "THIRDANDI1PUT4,Third AND Gate Input 4 Selection" hexmask.long.byte 0x18 16.--21. 1. "THIRDANDI1PUT3,Third AND Gate Input 3 Selection" newline hexmask.long.byte 0x18 8.--13. 1. "THIRDANDI1PUT2,Third AND Gate Input 2 Selection" hexmask.long.byte 0x18 0.--5. 1. "THIRDANDI1PUT1,Third AND Gate Input 1 Selection" line.long 0x1C "L2S1SEL3,Level2 MUX state 1 selection 3 register" hexmask.long.byte 0x1C 24.--29. 1. "FOURTHANDI1PUT4,Fourth AND Gate Input 4 Selection" hexmask.long.byte 0x1C 16.--21. 1. "FOURTHANDI1PUT3,Fourth AND Gate Input 3 Selection" newline hexmask.long.byte 0x1C 8.--13. 1. "FOURTHANDI1PUT2,Fourth AND Gate Input 2 Selection" hexmask.long.byte 0x1C 0.--5. 1. "FOURTHANDI1PUT1,Fourth AND Gate Input 1 Selection" line.long 0x20 "L2S2SEL0,Level2 MUX state 2 selection 0 register" hexmask.long.byte 0x20 24.--29. 1. "FIRSTANDI2PUT4,First AND Gate Input 4 Selection" hexmask.long.byte 0x20 16.--21. 1. "FIRSTANDI2PUT3,First AND Gate Input 3 Selection" newline hexmask.long.byte 0x20 8.--13. 1. "FIRSTANDI2PUT2,First AND Gate Input 2 Selection" hexmask.long.byte 0x20 0.--5. 1. "FIRSTANDI2PUT1,First AND Gate Input 1 Selection" line.long 0x24 "L2S2SEL1,Level2 MUX state 2 selection 1 register" hexmask.long.byte 0x24 24.--29. 1. "SECO2DANDINPUT4,Second AND Gate Input 4 Selection" hexmask.long.byte 0x24 16.--21. 1. "SECO2DANDINPUT3,Second AND Gate Input 3 Selection" newline hexmask.long.byte 0x24 8.--13. 1. "SECO2DANDINPUT2,Second AND Gate Input 2 Selection" hexmask.long.byte 0x24 0.--5. 1. "SECO2DANDINPUT1,Second AND Gate Input 1 Selection" line.long 0x28 "L2S2SEL2,Level2 MUX state 2 selection 2 register" hexmask.long.byte 0x28 24.--29. 1. "THIRDANDI2PUT4,Third AND Gate Input 4 Selection" hexmask.long.byte 0x28 16.--21. 1. "THIRDANDI2PUT3,Third AND Gate Input 3 Selection" newline hexmask.long.byte 0x28 8.--13. 1. "THIRDANDI2PUT2,Third AND Gate Input 2 Selection" hexmask.long.byte 0x28 0.--5. 1. "THIRDANDI2PUT1,Third AND Gate Input 1 Selection" line.long 0x2C "L2S2SEL3,Level2 MUX state 2 selection 3 register" hexmask.long.byte 0x2C 24.--29. 1. "FOURTHANDI2PUT4,Fourth AND Gate Input 4 Selection" hexmask.long.byte 0x2C 16.--21. 1. "FOURTHANDI2PUT3,Fourth AND Gate Input 3 Selection" newline hexmask.long.byte 0x2C 8.--13. 1. "FOURTHANDI2PUT2,Fourth AND Gate Input 2 Selection" hexmask.long.byte 0x2C 0.--5. 1. "FOURTHANDI2PUT1,Fourth AND Gate Input 1 Selection" line.long 0x30 "L2S3SEL0,Level2 MUX state 3 selection 0 register" hexmask.long.byte 0x30 24.--29. 1. "FIRSTANDI3PUT4,First AND Gate Input 4 Selection" hexmask.long.byte 0x30 16.--21. 1. "FIRSTANDI3PUT3,First AND Gate Input 3 Selection" newline hexmask.long.byte 0x30 8.--13. 1. "FIRSTANDI3PUT2,First AND Gate Input 2 Selection" hexmask.long.byte 0x30 0.--5. 1. "FIRSTANDI3PUT1,First AND Gate Input 1 Selection" line.long 0x34 "L2S3SEL1,Level2 MUX state 3 selection 1 register" hexmask.long.byte 0x34 24.--29. 1. "SECO3DANDINPUT4,Second AND Gate Input 4 Selection" hexmask.long.byte 0x34 16.--21. 1. "SECO3DANDINPUT3,Second AND Gate Input 3 Selection" newline hexmask.long.byte 0x34 8.--13. 1. "SECO3DANDINPUT2,Second AND Gate Input 2 Selection" hexmask.long.byte 0x34 0.--5. 1. "SECO3DANDINPUT1,Second AND Gate Input 1 Selection" line.long 0x38 "L2S3SEL2,Level2 MUX state 3 selection 2 register" hexmask.long.byte 0x38 24.--29. 1. "THIRDANDI3PUT4,Third AND Gate Input 4 Selection" hexmask.long.byte 0x38 16.--21. 1. "THIRDANDI3PUT3,Third AND Gate Input 3 Selection" newline hexmask.long.byte 0x38 8.--13. 1. "THIRDANDI3PUT2,Third AND Gate Input 2 Selection" hexmask.long.byte 0x38 0.--5. 1. "THIRDANDI3PUT1,Third AND Gate Input 1 Selection" line.long 0x3C "L2S3SEL3,Level2 MUX state 3 selection 3 register" hexmask.long.byte 0x3C 24.--29. 1. "FOURTHANDI3PUT4,Fourth AND Gate Input 4 Selection" hexmask.long.byte 0x3C 16.--21. 1. "FOURTHANDI3PUT3,Fourth AND Gate Input 3 Selection" newline hexmask.long.byte 0x3C 8.--13. 1. "FOURTHANDI3PUT2,Fourth AND Gate Input 2 Selection" hexmask.long.byte 0x3C 0.--5. 1. "FOURTHANDI3PUT1,Fourth AND Gate Input 1 Selection" line.long 0x40 "L2S4SEL0,Level2 MUX state 4 selection 0 register" hexmask.long.byte 0x40 24.--29. 1. "FIRSTANDI4PUT4,First AND Gate Input 4 Selection" hexmask.long.byte 0x40 16.--21. 1. "FIRSTANDI4PUT3,First AND Gate Input 3 Selection" newline hexmask.long.byte 0x40 8.--13. 1. "FIRSTANDI4PUT2,First AND Gate Input 2 Selection" hexmask.long.byte 0x40 0.--5. 1. "FIRSTANDI4PUT1,First AND Gate Input 1 Selection" line.long 0x44 "L2S4SEL1,Level2 MUX state 4 selection 1 register" hexmask.long.byte 0x44 24.--29. 1. "SECO4DANDINPUT4,Second AND Gate Input 4 Selection" hexmask.long.byte 0x44 16.--21. 1. "SECO4DANDINPUT3,Second AND Gate Input 3 Selection" newline hexmask.long.byte 0x44 8.--13. 1. "SECO4DANDINPUT2,Second AND Gate Input 2 Selection" hexmask.long.byte 0x44 0.--5. 1. "SECO4DANDINPUT1,Second AND Gate Input 1 Selection" line.long 0x48 "L2S4SEL2,Level2 MUX state 4 selection 2 register" hexmask.long.byte 0x48 24.--29. 1. "THIRDANDI4PUT4,Third AND Gate Input 4 Selection" hexmask.long.byte 0x48 16.--21. 1. "THIRDANDI4PUT3,Third AND Gate Input 3 Selection" newline hexmask.long.byte 0x48 8.--13. 1. "THIRDANDI4PUT2,Third AND Gate Input 2 Selection" hexmask.long.byte 0x48 0.--5. 1. "THIRDANDI4PUT1,Third AND Gate Input 1 Selection" line.long 0x4C "L2S4SEL3,Level2 MUX state 4 selection 3 register" hexmask.long.byte 0x4C 24.--29. 1. "FOURTHANDI4PUT4,Fourth AND Gate Input 4 Selection" hexmask.long.byte 0x4C 16.--21. 1. "FOURTHANDI4PUT3,Fourth AND Gate Input 3 Selection" newline hexmask.long.byte 0x4C 8.--13. 1. "FOURTHANDI4PUT2,Fourth AND Gate Input 2 Selection" hexmask.long.byte 0x4C 0.--5. 1. "FOURTHANDI4PUT1,Fourth AND Gate Input 1 Selection" line.long 0x50 "L2S5SEL0,Level2 MUX state 5 selection 0 register" hexmask.long.byte 0x50 24.--29. 1. "FIRSTANDI5PUT4,First AND Gate Input 4 Selection" hexmask.long.byte 0x50 16.--21. 1. "FIRSTANDI5PUT3,First AND Gate Input 3 Selection" newline hexmask.long.byte 0x50 8.--13. 1. "FIRSTANDI5PUT2,First AND Gate Input 2 Selection" hexmask.long.byte 0x50 0.--5. 1. "FIRSTANDI5PUT1,First AND Gate Input 1 Selection" line.long 0x54 "L2S5SEL1,Level2 MUX state 5 selection 1 register" hexmask.long.byte 0x54 24.--29. 1. "SECO5DANDINPUT4,Second AND Gate Input 4 Selection" hexmask.long.byte 0x54 16.--21. 1. "SECO5DANDINPUT3,Second AND Gate Input 3 Selection" newline hexmask.long.byte 0x54 8.--13. 1. "SECO5DANDINPUT2,Second AND Gate Input 2 Selection" hexmask.long.byte 0x54 0.--5. 1. "SECO5DANDINPUT1,Second AND Gate Input 1 Selection" line.long 0x58 "L2S5SEL2,Level2 MUX state 5 selection 2 register" hexmask.long.byte 0x58 24.--29. 1. "THIRDANDI5PUT4,Third AND Gate Input 4 Selection" hexmask.long.byte 0x58 16.--21. 1. "THIRDANDI5PUT3,Third AND Gate Input 3 Selection" newline hexmask.long.byte 0x58 8.--13. 1. "THIRDANDI5PUT2,Third AND Gate Input 2 Selection" hexmask.long.byte 0x58 0.--5. 1. "THIRDANDI5PUT1,Third AND Gate Input 1 Selection" line.long 0x5C "L2S5SEL3,Level2 MUX state 5 selection 3 register" hexmask.long.byte 0x5C 24.--29. 1. "FOURTHANDI5PUT4,Fourth AND Gate Input 4 Selection" hexmask.long.byte 0x5C 16.--21. 1. "FOURTHANDI5PUT3,Fourth AND Gate Input 3 Selection" newline hexmask.long.byte 0x5C 8.--13. 1. "FOURTHANDI5PUT2,Fourth AND Gate Input 2 Selection" hexmask.long.byte 0x5C 0.--5. 1. "FOURTHANDI5PUT1,Fourth AND Gate Input 1 Selection" line.long 0x60 "L2S6SEL0,Level2 MUX state 6 selection 0 register" hexmask.long.byte 0x60 24.--29. 1. "FIRSTANDI6PUT4,First AND Gate Input 4 Selection" hexmask.long.byte 0x60 16.--21. 1. "FIRSTANDI6PUT3,First AND Gate Input 3 Selection" newline hexmask.long.byte 0x60 8.--13. 1. "FIRSTANDI6PUT2,First AND Gate Input 2 Selection" hexmask.long.byte 0x60 0.--5. 1. "FIRSTANDI6PUT1,First AND Gate Input 1 Selection" line.long 0x64 "L2S6SEL1,Level2 MUX state 6 selection 1 register" hexmask.long.byte 0x64 24.--29. 1. "SECO6DANDINPUT4,Second AND Gate Input 4 Selection" hexmask.long.byte 0x64 16.--21. 1. "SECO6DANDINPUT3,Second AND Gate Input 3 Selection" newline hexmask.long.byte 0x64 8.--13. 1. "SECO6DANDINPUT2,Second AND Gate Input 2 Selection" hexmask.long.byte 0x64 0.--5. 1. "SECO6DANDINPUT1,Second AND Gate Input 1 Selection" line.long 0x68 "L2S6SEL2,Level2 MUX state 6 selection 2 register" hexmask.long.byte 0x68 24.--29. 1. "THIRDANDI6PUT4,Third AND Gate Input 4 Selection" hexmask.long.byte 0x68 16.--21. 1. "THIRDANDI6PUT3,Third AND Gate Input 3 Selection" newline hexmask.long.byte 0x68 8.--13. 1. "THIRDANDI6PUT2,Third AND Gate Input 2 Selection" hexmask.long.byte 0x68 0.--5. 1. "THIRDANDI6PUT1,Third AND Gate Input 1 Selection" line.long 0x6C "L2S6SEL3,Level2 MUX state 6 selection 3 register" hexmask.long.byte 0x6C 24.--29. 1. "FOURTHANDI6PUT4,Fourth AND Gate Input 4 Selection" hexmask.long.byte 0x6C 16.--21. 1. "FOURTHANDI6PUT3,Fourth AND Gate Input 3 Selection" newline hexmask.long.byte 0x6C 8.--13. 1. "FOURTHANDI6PUT2,Fourth AND Gate Input 2 Selection" hexmask.long.byte 0x6C 0.--5. 1. "FOURTHANDI6PUT1,Fourth AND Gate Input 1 Selection" line.long 0x70 "L2S7SEL0,Level2 MUX state 7 selection 0 register" hexmask.long.byte 0x70 24.--29. 1. "FIRSTANDI7PUT4,First AND Gate Input 4 Selection" hexmask.long.byte 0x70 16.--21. 1. "FIRSTANDI7PUT3,First AND Gate Input 3 Selection" newline hexmask.long.byte 0x70 8.--13. 1. "FIRSTANDI7PUT2,First AND Gate Input 2 Selection" hexmask.long.byte 0x70 0.--5. 1. "FIRSTANDI7PUT1,First AND Gate Input 1 Selection" line.long 0x74 "L2S7SEL1,Level2 MUX state 7 selection 1 register" hexmask.long.byte 0x74 24.--29. 1. "SECO7DANDINPUT4,Second AND Gate Input 4 Selection" hexmask.long.byte 0x74 16.--21. 1. "SECO7DANDINPUT3,Second AND Gate Input 3 Selection" newline hexmask.long.byte 0x74 8.--13. 1. "SECO7DANDINPUT2,Second AND Gate Input 2 Selection" hexmask.long.byte 0x74 0.--5. 1. "SECO7DANDINPUT1,Second AND Gate Input 1 Selection" line.long 0x78 "L2S7SEL2,Level2 MUX state 7 selection 2 register" hexmask.long.byte 0x78 24.--29. 1. "THIRDANDI7PUT4,Third AND Gate Input 4 Selection" hexmask.long.byte 0x78 16.--21. 1. "THIRDANDI7PUT3,Third AND Gate Input 3 Selection" newline hexmask.long.byte 0x78 8.--13. 1. "THIRDANDI7PUT2,Third AND Gate Input 2 Selection" hexmask.long.byte 0x78 0.--5. 1. "THIRDANDI7PUT1,Third AND Gate Input 1 Selection" line.long 0x7C "L2S7SEL3,Level2 MUX state 7 selection 3 register" hexmask.long.byte 0x7C 24.--29. 1. "FOURTHANDI7PUT4,Fourth AND Gate Input 4 Selection" hexmask.long.byte 0x7C 16.--21. 1. "FOURTHANDI7PUT3,Fourth AND Gate Input 3 Selection" newline hexmask.long.byte 0x7C 8.--13. 1. "FOURTHANDI7PUT2,Fourth AND Gate Input 2 Selection" hexmask.long.byte 0x7C 0.--5. 1. "FOURTHANDI7PUT1,Fourth AND Gate Input 1 Selection" line.long 0x80 "IOIC0,Input/output inversion control for state 0 register" bitfld.long 0x80 8. "OUTOR,Output OR GATE Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x80 7. "OUTAND4,Output of AND Gate 4 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" newline bitfld.long 0x80 6. "OUTAND3,Output of AND Gate 3 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x80 5. "OUTAND2,Output of AND Gate 2 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" newline bitfld.long 0x80 4. "OUTAND1,Output of AND Gate 1 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x80 3. "I0AND4,Input 1 AND Gate 4 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" newline bitfld.long 0x80 2. "I0AND3,Input 1 AND Gate 3 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" bitfld.long 0x80 1. "I0AND2,Input 1 AND Gate 2 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" newline bitfld.long 0x80 0. "I0AND1,Input 1 AND Gate 1 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" line.long 0x84 "IOIC1,Input/output inversion control for state 1 register" bitfld.long 0x84 8. "OUTOR,Output OR GATE Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x84 7. "OUTAND4,Output of AND Gate 4 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" newline bitfld.long 0x84 6. "OUTAND3,Output of AND Gate 3 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x84 5. "OUTAND2,Output of AND Gate 2 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" newline bitfld.long 0x84 4. "OUTAND1,Output of AND Gate 1 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x84 3. "I1AND4,Input 1 AND Gate 4 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" newline bitfld.long 0x84 2. "I1AND3,Input 1 AND Gate 3 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" bitfld.long 0x84 1. "I1AND2,Input 1 AND Gate 2 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" newline bitfld.long 0x84 0. "I1AND1,Input 1 AND Gate 1 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" line.long 0x88 "IOIC2,Input/output inversion control for state 2 register" bitfld.long 0x88 8. "OUTOR,Output OR GATE Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x88 7. "OUTAND4,Output of AND Gate 4 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" newline bitfld.long 0x88 6. "OUTAND3,Output of AND Gate 3 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x88 5. "OUTAND2,Output of AND Gate 2 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" newline bitfld.long 0x88 4. "OUTAND1,Output of AND Gate 1 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x88 3. "I2AND4,Input 1 AND Gate 4 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" newline bitfld.long 0x88 2. "I2AND3,Input 1 AND Gate 3 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" bitfld.long 0x88 1. "I2AND2,Input 1 AND Gate 2 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" newline bitfld.long 0x88 0. "I2AND1,Input 1 AND Gate 1 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" line.long 0x8C "IOIC3,Input/output inversion control for state 3 register" bitfld.long 0x8C 8. "OUTOR,Output OR GATE Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x8C 7. "OUTAND4,Output of AND Gate 4 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" newline bitfld.long 0x8C 6. "OUTAND3,Output of AND Gate 3 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x8C 5. "OUTAND2,Output of AND Gate 2 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" newline bitfld.long 0x8C 4. "OUTAND1,Output of AND Gate 1 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x8C 3. "I3AND4,Input 1 AND Gate 4 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" newline bitfld.long 0x8C 2. "I3AND3,Input 1 AND Gate 3 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" bitfld.long 0x8C 1. "I3AND2,Input 1 AND Gate 2 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" newline bitfld.long 0x8C 0. "I3AND1,Input 1 AND Gate 1 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" line.long 0x90 "IOIC4,Input/output inversion control for state 4 register" bitfld.long 0x90 8. "OUTOR,Output OR GATE Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x90 7. "OUTAND4,Output of AND Gate 4 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" newline bitfld.long 0x90 6. "OUTAND3,Output of AND Gate 3 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x90 5. "OUTAND2,Output of AND Gate 2 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" newline bitfld.long 0x90 4. "OUTAND1,Output of AND Gate 1 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x90 3. "I4AND4,Input 1 AND Gate 4 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" newline bitfld.long 0x90 2. "I4AND3,Input 1 AND Gate 3 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" bitfld.long 0x90 1. "I4AND2,Input 1 AND Gate 2 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" newline bitfld.long 0x90 0. "I4AND1,Input 1 AND Gate 1 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" line.long 0x94 "IOIC5,Input/output inversion control for state 5 register" bitfld.long 0x94 8. "OUTOR,Output OR GATE Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x94 7. "OUTAND4,Output of AND Gate 4 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" newline bitfld.long 0x94 6. "OUTAND3,Output of AND Gate 3 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x94 5. "OUTAND2,Output of AND Gate 2 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" newline bitfld.long 0x94 4. "OUTAND1,Output of AND Gate 1 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x94 3. "I5AND4,Input 1 AND Gate 4 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" newline bitfld.long 0x94 2. "I5AND3,Input 1 AND Gate 3 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" bitfld.long 0x94 1. "I5AND2,Input 1 AND Gate 2 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" newline bitfld.long 0x94 0. "I5AND1,Input 1 AND Gate 1 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" line.long 0x98 "IOIC6,Input/output inversion control for state 6 register" bitfld.long 0x98 8. "OUTOR,Output OR GATE Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x98 7. "OUTAND4,Output of AND Gate 4 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" newline bitfld.long 0x98 6. "OUTAND3,Output of AND Gate 3 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x98 5. "OUTAND2,Output of AND Gate 2 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" newline bitfld.long 0x98 4. "OUTAND1,Output of AND Gate 1 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x98 3. "I6AND4,Input 1 AND Gate 4 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" newline bitfld.long 0x98 2. "I6AND3,Input 1 AND Gate 3 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" bitfld.long 0x98 1. "I6AND2,Input 1 AND Gate 2 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" newline bitfld.long 0x98 0. "I6AND1,Input 1 AND Gate 1 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" line.long 0x9C "IOIC7,Input/output inversion control for state 7 register" bitfld.long 0x9C 8. "OUTOR,Output OR GATE Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x9C 7. "OUTAND4,Output of AND Gate 4 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" newline bitfld.long 0x9C 6. "OUTAND3,Output of AND Gate 3 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x9C 5. "OUTAND2,Output of AND Gate 2 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" newline bitfld.long 0x9C 4. "OUTAND1,Output of AND Gate 1 Control" "0: Output is used directly (without inversion) for..,1: Output is inverted for this event" bitfld.long 0x9C 3. "I7AND4,Input 1 AND Gate 4 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" newline bitfld.long 0x9C 2. "I7AND3,Input 1 AND Gate 3 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" bitfld.long 0x9C 1. "I7AND2,Input 1 AND Gate 2 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" newline bitfld.long 0x9C 0. "I7AND1,Input 1 AND Gate 1 Control" "0: Input 1 is used directly (without inversion) for..,1: Input 1 is inverted for this event" line.long 0xA0 "SCTRL,Sequence control register" bitfld.long 0xA0 28.--30. "S4ST2,Sequence 4 End State" "0: State 0 is the Stop state for sequence 4,1: State 1 is the Stop state for sequence 4,2: State 2 is the Stop state for sequence 4,3: State 3 is the Stop state for sequence 4,4: State 4 is the Stop state for sequence 4,5: State 5 is the Stop state for sequence 4,6: State 6 is the Stop state for sequence 4,7: State 7 is the Stop state for sequence 4" bitfld.long 0xA0 25.--27. "S4ST1,Sequence 4 Start State" "0: State 0 is the Start state for sequence 4,1: State 1 is the Start state for sequence 4,2: State 2 is the Start state for sequence 4,3: State 3 is the Start state for sequence 4,4: State 4 is the Start state for sequence 4,5: State 5 is the Start state for sequence 4,6: State 6 is the Start state for sequence 4,7: State 7 is the Start state for sequence 4" newline bitfld.long 0xA0 24. "S4ST0,Sequence 4 Enable/Disable" "0: Sequence 4 is disabled,1: Sequence 4 is enabled" bitfld.long 0xA0 20.--22. "S3ST2,Sequence 3 End State" "0: State 0 is the Stop state for sequence 3,1: State 1 is the Stop state for sequence 3,2: State 2 is the Stop state for sequence 3,3: State 3 is the Stop state for sequence 3,4: State 4 is the Stop state for sequence 3,5: State 5 is the Stop state for sequence 3,6: State 6 is the Stop state for sequence 3,7: State 7 is the Stop state for sequence 3" newline bitfld.long 0xA0 17.--19. "S3ST1,Sequence 3 Start State(1)" "0: State 0 is the Start state for sequence 3,1: State 1 is the Start state for sequence 3,2: State 2 is the Start state for sequence 3,3: State 3 is the Start state for sequence 3,4: State 4 is the Start state for sequence 3,5: State 5 is the Start state for sequence 3,6: State 6 is the Start state for sequence 3,7: State 7 is the Start state for sequence 3" bitfld.long 0xA0 16. "S3ST0,Sequence 3 Enable/Disable(2)" "0: Sequence 3 is disabled,1: Sequence 3 is enabled" newline bitfld.long 0xA0 12.--14. "S2ST2,Sequence 2 End State" "0: State 0 is the Stop state for sequence 2,1: State 1 is the Stop state for sequence 2,2: State 2 is the Stop state for sequence 2,3: State 3 is the Stop state for sequence 2,4: State 4 is the Stop state for sequence 2,5: State 5 is the Stop state for sequence 2,6: State 6 is the Stop state for sequence 2,7: State 7 is the Stop state for sequence 2" bitfld.long 0xA0 9.--11. "S2ST1,Sequence 2 Start State" "0: State 0 is the Start state for sequence 2,1: State 1 is the Start state for sequence 2,2: State 2 is the Start state for sequence 2,3: State 3 is the Start state for sequence 2,4: State 4 is the Start state for sequence 2,5: State 5 is the Start state for sequence 2,6: State 6 is the Start state for sequence 2,7: State 7 is the Start state for sequence 2" newline bitfld.long 0xA0 8. "S2ST0,Sequence 2 Enable/Disable(2)" "0: Sequence 2 is disabled,1: Sequence 2 is enabled" bitfld.long 0xA0 4.--6. "S1ST2,Sequence 1 End State" "0: State 0 is the Stop state for sequence 1,1: State 1 is the Stop state for sequence 1,2: State 2 is the Stop state for sequence 1,3: State 3 is the Stop state for sequence 1,4: State 4 is the Stop state for sequence 1,5: State 5 is the Stop state for sequence 1,6: State 6 is the Stop state for sequence 1,7: State 7 is the Stop state for sequence 1" newline bitfld.long 0xA0 1.--3. "S1ST1,Sequence 1 Start State" "0: State 0 (Always),?,?,?,?,?,?,?" bitfld.long 0xA0 0. "S1ST0,Sequence 1 Enable/Disable(2)" "0: Sequence 1 is disabled,1: Sequence 1 is enabled" line.long 0xA4 "S0GC,State 0 GoTo control register" bitfld.long 0xA4 5.--7. "NF,Next State on False Condition" "0: GoTo State 0,1: GoTo State 1,2: GoTo State 2,3: GoTo State 3,4: GoTo State 4,5: GoTo State 5,6: GoTo State 6,7: GoTo State 7" bitfld.long 0xA4 4. "FE,GOTO Control of State Under False Condition" "0: Disable GoTo control,1: Enable GoTo control" newline bitfld.long 0xA4 1.--3. "NT,Next State on True Condition" "0: GoTo State 0,1: GoTo State 1,2: GoTo State 2,3: GoTo State 3,4: GoTo State 4,5: GoTo State 5,6: GoTo State 6,7: GoTo State 7" bitfld.long 0xA4 0. "TE,GoTo Control of State Under True Condition" "0: Disable GoTo control,1: Enable GoTo control" line.long 0xA8 "S1GC,State 1 GoTo control register" bitfld.long 0xA8 5.--7. "NF,Next State on False Condition" "0: GoTo State 0,1: GoTo State 1,2: GoTo State 2,3: GoTo State 3,4: GoTo State 4,5: GoTo State 5,6: GoTo State 6,7: GoTo State 7" bitfld.long 0xA8 4. "FE,GOTO Control of State Under False Condition" "0: Disable GoTo control,1: Enable GoTo control" newline bitfld.long 0xA8 1.--3. "NT,Next State on True Condition" "0: GoTo State 0,1: GoTo State 1,2: GoTo State 2,3: GoTo State 3,4: GoTo State 4,5: GoTo State 5,6: GoTo State 6,7: GoTo State 7" bitfld.long 0xA8 0. "TE,GoTo Control of State Under True Condition" "0: Disable GoTo control,1: Enable GoTo control" line.long 0xAC "S2GC,State 2 GoTo control register" bitfld.long 0xAC 5.--7. "NF,Next State on False Condition" "0: GoTo State 0,1: GoTo State 1,2: GoTo State 2,3: GoTo State 3,4: GoTo State 4,5: GoTo State 5,6: GoTo State 6,7: GoTo State 7" bitfld.long 0xAC 4. "FE,GOTO Control of State Under False Condition" "0: Disable GoTo control,1: Enable GoTo control" newline bitfld.long 0xAC 1.--3. "NT,Next State on True Condition" "0: GoTo State 0,1: GoTo State 1,2: GoTo State 2,3: GoTo State 3,4: GoTo State 4,5: GoTo State 5,6: GoTo State 6,7: GoTo State 7" bitfld.long 0xAC 0. "TE,GoTo Control of State Under True Condition" "0: Disable GoTo control,1: Enable GoTo control" line.long 0xB0 "S3GC,State 3 GoTo control register" bitfld.long 0xB0 5.--7. "NF,Next State on False Condition" "0: GoTo State 0,1: GoTo State 1,2: GoTo State 2,3: GoTo State 3,4: GoTo State 4,5: GoTo State 5,6: GoTo State 6,7: GoTo State 7" bitfld.long 0xB0 4. "FE,GOTO Control of State Under False Condition" "0: Disable GoTo control,1: Enable GoTo control" newline bitfld.long 0xB0 1.--3. "NT,Next State on True Condition" "0: GoTo State 0,1: GoTo State 1,2: GoTo State 2,3: GoTo State 3,4: GoTo State 4,5: GoTo State 5,6: GoTo State 6,7: GoTo State 7" bitfld.long 0xB0 0. "TE,GoTo Control of State Under True Condition" "0: Disable GoTo control,1: Enable GoTo control" line.long 0xB4 "S4GC,State 4 GoTo control register" bitfld.long 0xB4 5.--7. "NF,Next State on False Condition" "0: GoTo State 0,1: GoTo State 1,2: GoTo State 2,3: GoTo State 3,4: GoTo State 4,5: GoTo State 5,6: GoTo State 6,7: GoTo State 7" bitfld.long 0xB4 4. "FE,GOTO Control of State Under False Condition" "0: Disable GoTo control,1: Enable GoTo control" newline bitfld.long 0xB4 1.--3. "NT,Next State on True Condition" "0: GoTo State 0,1: GoTo State 1,2: GoTo State 2,3: GoTo State 3,4: GoTo State 4,5: GoTo State 5,6: GoTo State 6,7: GoTo State 7" bitfld.long 0xB4 0. "TE,GoTo Control of State Under True Condition" "0: Disable GoTo control,1: Enable GoTo control" line.long 0xB8 "S5GC,State 5 GoTo control register" bitfld.long 0xB8 5.--7. "NF,Next State on False Condition" "0: GoTo State 0,1: GoTo State 1,2: GoTo State 2,3: GoTo State 3,4: GoTo State 4,5: GoTo State 5,6: GoTo State 6,7: GoTo State 7" bitfld.long 0xB8 4. "FE,GOTO Control of State Under False Condition" "0: Disable GoTo control,1: Enable GoTo control" newline bitfld.long 0xB8 1.--3. "NT,Next State on True Condition" "0: GoTo State 0,1: GoTo State 1,2: GoTo State 2,3: GoTo State 3,4: GoTo State 4,5: GoTo State 5,6: GoTo State 6,7: GoTo State 7" bitfld.long 0xB8 0. "TE,GoTo Control of State Under True Condition" "0: Disable GoTo control,1: Enable GoTo control" line.long 0xBC "S6GC,State 6 GoTo control register" bitfld.long 0xBC 5.--7. "NF,Next State on False Condition" "0: GoTo State 0,1: GoTo State 1,2: GoTo State 2,3: GoTo State 3,4: GoTo State 4,5: GoTo State 5,6: GoTo State 6,7: GoTo State 7" bitfld.long 0xBC 4. "FE,GOTO Control of State Under False Condition" "0: Disable GoTo control,1: Enable GoTo control" newline bitfld.long 0xBC 1.--3. "NT,Next State on True Condition" "0: GoTo State 0,1: GoTo State 1,2: GoTo State 2,3: GoTo State 3,4: GoTo State 4,5: GoTo State 5,6: GoTo State 6,7: GoTo State 7" bitfld.long 0xBC 0. "TE,GoTo Control of State Under True Condition" "0: Disable GoTo control,1: Enable GoTo control" line.long 0xC0 "S7GC,State 7 GoTo control register" bitfld.long 0xC0 5.--7. "NF,Next State on False Condition" "0: GoTo State 0,1: GoTo State 1,2: GoTo State 2,3: GoTo State 3,4: GoTo State 4,5: GoTo State 5,6: GoTo State 6,7: GoTo State 7" bitfld.long 0xC0 4. "FE,GOTO Control of State Under False Condition" "0: Disable GoTo control,1: Enable GoTo control" newline bitfld.long 0xC0 1.--3. "NT,Next State on True Condition" "0: GoTo State 0,1: GoTo State 1,2: GoTo State 2,3: GoTo State 3,4: GoTo State 4,5: GoTo State 5,6: GoTo State 6,7: GoTo State 7" bitfld.long 0xC0 0. "TE,GoTo Control of State Under True Condition" "0: Disable GoTo control,1: Enable GoTo control" line.long 0xC4 "SS,SLU status register" bitfld.long 0xC4 25. "IPM5,Interrupt priority match 5" "0: No match,1: Match occurred" bitfld.long 0xC4 24. "IPM4,Interrupt priority match 5" "0: No match,1: Match occurred" newline bitfld.long 0xC4 23. "IPM3,Interrupt priority match 5" "0: No match,1: Match occurred" bitfld.long 0xC4 22. "IPM2,Interrupt priority match 5" "0: No match,1: Match occurred" newline bitfld.long 0xC4 21. "IPM1,Interrupt priority match 5" "0: No match,1: Match occurred" bitfld.long 0xC4 20. "IPM0,Interrupt priority match 5" "0: No match,1: Match occurred" newline bitfld.long 0xC4 17.--19. "SAS4,Sequence 4 Active State" "0: State0 is the active state,1: State1 is the active state,2: State2 is the active state,3: State3 is the active state,4: State4 is the active state,5: State5 is the active state,6: State6 is the active state,7: State7 is the active state" bitfld.long 0xC4 14.--16. "SAS3,Sequence 3 Active State" "0: State0 is the active state,1: State1 is the active state,2: State2 is the active state,3: State3 is the active state,4: State4 is the active state,5: State5 is the active state,6: State6 is the active state,7: State7 is the active state" newline bitfld.long 0xC4 11.--13. "SAS2,Sequence 2 Active State" "0: State0 is the active state,1: State1 is the active state,2: State2 is the active state,3: State3 is the active state,4: State4 is the active state,5: State5 is the active state,6: State6 is the active state,7: State7 is the active state" bitfld.long 0xC4 8.--10. "SAS1,Sequence 1 Active State" "0: State0 is the active state,1: State1 is the active state,2: State2 is the active state,3: State3 is the active state,4: State4 is the active state,5: State5 is the active state,6: State6 is the active state,7: State7 is the active state" newline bitfld.long 0xC4 7. "SH7,State Hit 7" "0: State not hit,1: State hit" bitfld.long 0xC4 6. "SH6,State Hit 6" "0: State not hit,1: State hit" newline bitfld.long 0xC4 5. "SH5,State Hit 5" "0: State not hit,1: State hit" bitfld.long 0xC4 4. "SH4,State Hit 4" "0: State not hit,1: State hit" newline bitfld.long 0xC4 3. "SH3,State Hit 3" "0: State not hit,1: State hit" bitfld.long 0xC4 2. "SH2,State Hit 2" "0: State not hit,1: State hit" newline bitfld.long 0xC4 1. "SH1,State Hit 1" "0: State not hit,1: State hit" bitfld.long 0xC4 0. "SH0,State Hit 0" "0: State not hit,1: State hit" group.long 0x15C++0x97 line.long 0x0 "SE,STLA enable register" bitfld.long 0x0 1. "DIV,Div Option" "0: Use Div4 option when multiple up to four..,1: Use a Div1 option when only one sequence.." bitfld.long 0x0 0. "SED,STLA Enable/Disable" "0: STLA is disabled,1: STLA is enabled" line.long 0x4 "S0TA0,State 0 true action 0 register" hexmask.long.word 0x4 16.--27. 1. "ACTION2,Action 2 to be performed for State n true condition" hexmask.long.word 0x4 0.--11. 1. "ACTION1,Action 1 to be performed for State n true condition" line.long 0x8 "S0TA1,State 0 true action 1 register" hexmask.long.word 0x8 16.--27. 1. "ACTION4,Action 4 to be performed for State n true condition" hexmask.long.word 0x8 0.--11. 1. "ACTION3,Action 3 to be performed for State n true condition" line.long 0xC "S1TA0,State 1 true action 0 register" hexmask.long.word 0xC 16.--27. 1. "ACTION2,Action 2 to be performed for State n true condition" hexmask.long.word 0xC 0.--11. 1. "ACTION1,Action 1 to be performed for State n true condition" line.long 0x10 "S1TA1,State 1 true action 1 register" hexmask.long.word 0x10 16.--27. 1. "ACTION4,Action 4 to be performed for State n true condition" hexmask.long.word 0x10 0.--11. 1. "ACTION3,Action 3 to be performed for State n true condition" line.long 0x14 "S2TA0,State 2 true action 0 register" hexmask.long.word 0x14 16.--27. 1. "ACTION2,Action 2 to be performed for State n true condition" hexmask.long.word 0x14 0.--11. 1. "ACTION1,Action 1 to be performed for State n true condition" line.long 0x18 "S2TA1,State 2 true action 1 register" hexmask.long.word 0x18 16.--27. 1. "ACTION4,Action 4 to be performed for State n true condition" hexmask.long.word 0x18 0.--11. 1. "ACTION3,Action 3 to be performed for State n true condition" line.long 0x1C "S3TA0,State 3 true action 0 register" hexmask.long.word 0x1C 16.--27. 1. "ACTION2,Action 2 to be performed for State n true condition" hexmask.long.word 0x1C 0.--11. 1. "ACTION1,Action 1 to be performed for State n true condition" line.long 0x20 "S3TA1,State 3 true action 1 register" hexmask.long.word 0x20 16.--27. 1. "ACTION4,Action 4 to be performed for State n true condition" hexmask.long.word 0x20 0.--11. 1. "ACTION3,Action 3 to be performed for State n true condition" line.long 0x24 "S4TA0,State 4 true action 0 register" hexmask.long.word 0x24 16.--27. 1. "ACTION2,Action 2 to be performed for State n true condition" hexmask.long.word 0x24 0.--11. 1. "ACTION1,Action 1 to be performed for State n true condition" line.long 0x28 "S4TA1,State 4 true action 1 register" hexmask.long.word 0x28 16.--27. 1. "ACTION4,Action 4 to be performed for State n true condition" hexmask.long.word 0x28 0.--11. 1. "ACTION3,Action 3 to be performed for State n true condition" line.long 0x2C "S5TA0,State 5 true action 0 register" hexmask.long.word 0x2C 16.--27. 1. "ACTION2,Action 2 to be performed for State n true condition" hexmask.long.word 0x2C 0.--11. 1. "ACTION1,Action 1 to be performed for State n true condition" line.long 0x30 "S5TA1,State 5 true action 1 register" hexmask.long.word 0x30 16.--27. 1. "ACTION4,Action 4 to be performed for State n true condition" hexmask.long.word 0x30 0.--11. 1. "ACTION3,Action 3 to be performed for State n true condition" line.long 0x34 "S6TA0,State 6 true action 0 register" hexmask.long.word 0x34 16.--27. 1. "ACTION2,Action 2 to be performed for State n true condition" hexmask.long.word 0x34 0.--11. 1. "ACTION1,Action 1 to be performed for State n true condition" line.long 0x38 "S6TA1,State 6 true action 1 register" hexmask.long.word 0x38 16.--27. 1. "ACTION4,Action 4 to be performed for State n true condition" hexmask.long.word 0x38 0.--11. 1. "ACTION3,Action 3 to be performed for State n true condition" line.long 0x3C "S7TA0,State 7 true action 0 register" hexmask.long.word 0x3C 16.--27. 1. "ACTION2,Action 2 to be performed for State n true condition" hexmask.long.word 0x3C 0.--11. 1. "ACTION1,Action 1 to be performed for State n true condition" line.long 0x40 "S7TA1,State 7 true action 1 register" hexmask.long.word 0x40 16.--27. 1. "ACTION4,Action 4 to be performed for State n true condition" hexmask.long.word 0x40 0.--11. 1. "ACTION3,Action 3 to be performed for State n true condition" line.long 0x44 "S0FA0,State 0 false action 0 register" hexmask.long.word 0x44 16.--27. 1. "ACTION2,Action 2 to be performed for State n false condition" hexmask.long.word 0x44 0.--11. 1. "ACTION1,Action 1 to be performed for State n false condition" line.long 0x48 "S0FA1,State 0 false action 1 register" hexmask.long.word 0x48 16.--27. 1. "ACTION4,Action 4 to be performed for State n false condition" hexmask.long.word 0x48 0.--11. 1. "ACTION3,Action 3 to be performed for State n false condition" line.long 0x4C "S1FA0,State 1 false action 0 register" hexmask.long.word 0x4C 16.--27. 1. "ACTION2,Action 2 to be performed for State n false condition" hexmask.long.word 0x4C 0.--11. 1. "ACTION1,Action 1 to be performed for State n false condition" line.long 0x50 "S1FA1,State 1 false action 1 register" hexmask.long.word 0x50 16.--27. 1. "ACTION4,Action 4 to be performed for State n false condition" hexmask.long.word 0x50 0.--11. 1. "ACTION3,Action 3 to be performed for State n false condition" line.long 0x54 "S2FA0,State 2 false action 0 register" hexmask.long.word 0x54 16.--27. 1. "ACTION2,Action 2 to be performed for State n false condition" hexmask.long.word 0x54 0.--11. 1. "ACTION1,Action 1 to be performed for State n false condition" line.long 0x58 "S2FA1,State 2 false action 1 register" hexmask.long.word 0x58 16.--27. 1. "ACTION4,Action 4 to be performed for State n false condition" hexmask.long.word 0x58 0.--11. 1. "ACTION3,Action 3 to be performed for State n false condition" line.long 0x5C "S3FA0,State 3 false action 0 register" hexmask.long.word 0x5C 16.--27. 1. "ACTION2,Action 2 to be performed for State n false condition" hexmask.long.word 0x5C 0.--11. 1. "ACTION1,Action 1 to be performed for State n false condition" line.long 0x60 "S3FA1,State 3 false action 1 register" hexmask.long.word 0x60 16.--27. 1. "ACTION4,Action 4 to be performed for State n false condition" hexmask.long.word 0x60 0.--11. 1. "ACTION3,Action 3 to be performed for State n false condition" line.long 0x64 "S4FA0,State 4 false action 0 register" hexmask.long.word 0x64 16.--27. 1. "ACTION2,Action 2 to be performed for State n false condition" hexmask.long.word 0x64 0.--11. 1. "ACTION1,Action 1 to be performed for State n false condition" line.long 0x68 "S4FA1,State 4 false action 1 register" hexmask.long.word 0x68 16.--27. 1. "ACTION4,Action 4 to be performed for State n false condition" hexmask.long.word 0x68 0.--11. 1. "ACTION3,Action 3 to be performed for State n false condition" line.long 0x6C "S5FA0,State 5 false action 0 register" hexmask.long.word 0x6C 16.--27. 1. "ACTION2,Action 2 to be performed for State n false condition" hexmask.long.word 0x6C 0.--11. 1. "ACTION1,Action 1 to be performed for State n false condition" line.long 0x70 "S5FA1,State 5 false action 1 register" hexmask.long.word 0x70 16.--27. 1. "ACTION4,Action 4 to be performed for State n false condition" hexmask.long.word 0x70 0.--11. 1. "ACTION3,Action 3 to be performed for State n false condition" line.long 0x74 "S6FA0,State 6 false action 0 register" hexmask.long.word 0x74 16.--27. 1. "ACTION2,Action 2 to be performed for State n false condition" hexmask.long.word 0x74 0.--11. 1. "ACTION1,Action 1 to be performed for State n false condition" line.long 0x78 "S6FA1,State 6 false action 1 register" hexmask.long.word 0x78 16.--27. 1. "ACTION4,Action 4 to be performed for State n false condition" hexmask.long.word 0x78 0.--11. 1. "ACTION3,Action 3 to be performed for State n false condition" line.long 0x7C "S7FA0,State 7 false action 0 register" hexmask.long.word 0x7C 16.--27. 1. "ACTION2,Action 2 to be performed for State n false condition" hexmask.long.word 0x7C 0.--11. 1. "ACTION1,Action 1 to be performed for State n false condition" line.long 0x80 "S7FA1,State 7 false action 1 register" hexmask.long.word 0x80 16.--27. 1. "ACTION4,Action 4 to be performed for State n false condition" hexmask.long.word 0x80 0.--11. 1. "ACTION3,Action 3 to be performed for State n false condition" line.long 0x84 "ETMEXTIN0TGC,ETMEXTIN_n trigger group register" bitfld.long 0x84 5. "CL2CORE1,CL2CORE1" "0: Disable ETM external trigger for Cluster2 Core1,1: Enable ETM external trigger for Cluster2 Core1" bitfld.long 0x84 4. "CL2CORE0,CL2CORE0" "0: Disable ETM external trigger for Cluster2 Core0,1: Enable ETM external trigger for Cluster2 Core0" newline bitfld.long 0x84 3. "CL1CORE1,CL1CORE1" "0: Disable ETM external trigger for Cluster1 Core1,1: Enable ETM external trigger for Cluster1 Core1" bitfld.long 0x84 2. "CL1CORE0,CL1CORE0" "0: Disable ETM external trigger for Cluster1 Core0,1: Enable ETM external trigger for Cluster1 Core0" newline bitfld.long 0x84 1. "CL0CORE1,CL0CORE1" "0: Disable ETM external trigger for Cluster0 Core1,1: Enable ETM external trigger for Cluster0 Core1" bitfld.long 0x84 0. "CL0CORE0,CL0CORE0" "0: Disable ETM external trigger for Cluster0 Core0,1: Enable ETM external trigger for Cluster0 Core0" line.long 0x88 "ETMEXTIN1TGC,ETMEXTIN_n trigger group register" bitfld.long 0x88 5. "CL2CORE1,CL2CORE1" "0: Disable ETM external trigger for Cluster2 Core1,1: Enable ETM external trigger for Cluster2 Core1" bitfld.long 0x88 4. "CL2CORE0,CL2CORE0" "0: Disable ETM external trigger for Cluster2 Core0,1: Enable ETM external trigger for Cluster2 Core0" newline bitfld.long 0x88 3. "CL1CORE1,CL1CORE1" "0: Disable ETM external trigger for Cluster1 Core1,1: Enable ETM external trigger for Cluster1 Core1" bitfld.long 0x88 2. "CL1CORE0,CL1CORE0" "0: Disable ETM external trigger for Cluster1 Core0,1: Enable ETM external trigger for Cluster1 Core0" newline bitfld.long 0x88 1. "CL0CORE1,CL0CORE1" "0: Disable ETM external trigger for Cluster0 Core1,1: Enable ETM external trigger for Cluster0 Core1" bitfld.long 0x88 0. "CL0CORE0,CL0CORE0" "0: Disable ETM external trigger for Cluster0 Core0,1: Enable ETM external trigger for Cluster0 Core0" line.long 0x8C "ETMEXTIN2TGC,ETMEXTIN_n trigger group register" bitfld.long 0x8C 5. "CL2CORE1,CL2CORE1" "0: Disable ETM external trigger for Cluster2 Core1,1: Enable ETM external trigger for Cluster2 Core1" bitfld.long 0x8C 4. "CL2CORE0,CL2CORE0" "0: Disable ETM external trigger for Cluster2 Core0,1: Enable ETM external trigger for Cluster2 Core0" newline bitfld.long 0x8C 3. "CL1CORE1,CL1CORE1" "0: Disable ETM external trigger for Cluster1 Core1,1: Enable ETM external trigger for Cluster1 Core1" bitfld.long 0x8C 2. "CL1CORE0,CL1CORE0" "0: Disable ETM external trigger for Cluster1 Core0,1: Enable ETM external trigger for Cluster1 Core0" newline bitfld.long 0x8C 1. "CL0CORE1,CL0CORE1" "0: Disable ETM external trigger for Cluster0 Core1,1: Enable ETM external trigger for Cluster0 Core1" bitfld.long 0x8C 0. "CL0CORE0,CL0CORE0" "0: Disable ETM external trigger for Cluster0 Core0,1: Enable ETM external trigger for Cluster0 Core0" line.long 0x90 "ETMEXTIN3TGC,ETMEXTIN_n trigger group register" bitfld.long 0x90 5. "CL2CORE1,CL2CORE1" "0: Disable ETM external trigger for Cluster2 Core1,1: Enable ETM external trigger for Cluster2 Core1" bitfld.long 0x90 4. "CL2CORE0,CL2CORE0" "0: Disable ETM external trigger for Cluster2 Core0,1: Enable ETM external trigger for Cluster2 Core0" newline bitfld.long 0x90 3. "CL1CORE1,CL1CORE1" "0: Disable ETM external trigger for Cluster1 Core1,1: Enable ETM external trigger for Cluster1 Core1" bitfld.long 0x90 2. "CL1CORE0,CL1CORE0" "0: Disable ETM external trigger for Cluster1 Core0,1: Enable ETM external trigger for Cluster1 Core0" newline bitfld.long 0x90 1. "CL0CORE1,CL0CORE1" "0: Disable ETM external trigger for Cluster0 Core1,1: Enable ETM external trigger for Cluster0 Core1" bitfld.long 0x90 0. "CL0CORE0,CL0CORE0" "0: Disable ETM external trigger for Cluster0 Core0,1: Enable ETM external trigger for Cluster0 Core0" line.long 0x94 "INTR_EN,Interrupt enable register" bitfld.long 0x94 0. "INTR_EN,Interrupt enable bit" "0: Disable interrupt,1: Enable interrupt on action" rgroup.long 0x1F4++0x3 line.long 0x0 "INTR_STATUS,Interrupt status register" bitfld.long 0x0 0. "INTR_STA,Interrupt status bit" "0: Interrupt is not set,1: Interrupt is set" wgroup.long 0x1F8++0x3 line.long 0x0 "INTR_CLEAR,Interrupt clear register" bitfld.long 0x0 0. "INTR_CLR,Interrupt clear bit" "0: Writing 0 has no effect,1: Writing 1 clears the interrupt" group.long 0x200++0x8B line.long 0x0 "CCTRL0,Counter control 0 register" bitfld.long 0x0 8. "LOAD,Load Enable/Disable" "0,1" bitfld.long 0x0 7. "SW_RESET,Reset" "0: Software reset is disabled,1: Software reset" newline bitfld.long 0x0 4.--6. "PRESCALING,Prescaling" "0: No scaling divide by 1,1: Divide by 4,2: Divide by 16,3: Divide by 32,?,?,?,?" bitfld.long 0x0 1. "MODE,Mode Select" "0: Counter,1: Timer" newline bitfld.long 0x0 0. "ENABLE,Enable" "0: Counter disabled,1: Counter enabled" line.long 0x4 "CCTRL1,Counter control 1 register" bitfld.long 0x4 8. "LOAD,Load Enable/Disable" "0,1" bitfld.long 0x4 7. "SW_RESET,Reset" "0: Software reset is disabled,1: Software reset" newline bitfld.long 0x4 4.--6. "PRESCALING,Prescaling" "0: No scaling divide by 1,1: Divide by 4,2: Divide by 16,3: Divide by 32,?,?,?,?" bitfld.long 0x4 1. "MODE,Mode Select" "0: Counter,1: Timer" newline bitfld.long 0x4 0. "ENABLE,Enable" "0: Counter disabled,1: Counter enabled" line.long 0x8 "CCTRL2,Counter control 2 register" bitfld.long 0x8 8. "LOAD,Load Enable/Disable" "0,1" bitfld.long 0x8 7. "SW_RESET,Reset" "0: Software reset is disabled,1: Software reset" newline bitfld.long 0x8 4.--6. "PRESCALING,Prescaling" "0: No scaling divide by 1,1: Divide by 4,2: Divide by 16,3: Divide by 32,?,?,?,?" bitfld.long 0x8 1. "MODE,Mode Select" "0: Counter,1: Timer" newline bitfld.long 0x8 0. "ENABLE,Enable" "0: Counter disabled,1: Counter enabled" line.long 0xC "CCTRL3,Counter control 3 register" bitfld.long 0xC 8. "LOAD,Load Enable/Disable" "0,1" bitfld.long 0xC 7. "SW_RESET,Reset" "0: Software reset is disabled,1: Software reset" newline bitfld.long 0xC 4.--6. "PRESCALING,Prescaling" "0: No scaling divide by 1,1: Divide by 4,2: Divide by 16,3: Divide by 32,?,?,?,?" bitfld.long 0xC 1. "MODE,Mode Select" "0: Counter,1: Timer" newline bitfld.long 0xC 0. "ENABLE,Enable" "0: Counter disabled,1: Counter enabled" line.long 0x10 "CCTRL4,Counter control 4 register" bitfld.long 0x10 8. "LOAD,Load Enable/Disable" "0,1" bitfld.long 0x10 7. "SW_RESET,Reset" "0: Software reset is disabled,1: Software reset" newline bitfld.long 0x10 4.--6. "PRESCALING,Prescaling" "0: No scaling divide by 1,1: Divide by 4,2: Divide by 16,3: Divide by 32,?,?,?,?" bitfld.long 0x10 1. "MODE,Mode Select" "0: Counter,1: Timer" newline bitfld.long 0x10 0. "ENABLE,Enable" "0: Counter disabled,1: Counter enabled" line.long 0x14 "CCTRL5,Counter control 5 register" bitfld.long 0x14 8. "LOAD,Load Enable/Disable" "0,1" bitfld.long 0x14 7. "SW_RESET,Reset" "0: Software reset is disabled,1: Software reset" newline bitfld.long 0x14 4.--6. "PRESCALING,Prescaling" "0: No scaling divide by 1,1: Divide by 4,2: Divide by 16,3: Divide by 32,?,?,?,?" bitfld.long 0x14 1. "MODE,Mode Select" "0: Counter,1: Timer" newline bitfld.long 0x14 0. "ENABLE,Enable" "0: Counter disabled,1: Counter enabled" line.long 0x18 "CCTRL6,Counter control 6 register" bitfld.long 0x18 8. "LOAD,Load Enable/Disable" "0,1" bitfld.long 0x18 7. "SW_RESET,Reset" "0: Software reset is disabled,1: Software reset" newline bitfld.long 0x18 4.--6. "PRESCALING,Prescaling" "0: No scaling divide by 1,1: Divide by 4,2: Divide by 16,3: Divide by 32,?,?,?,?" bitfld.long 0x18 1. "MODE,Mode Select" "0: Counter,1: Timer" newline bitfld.long 0x18 0. "ENABLE,Enable" "0: Counter disabled,1: Counter enabled" line.long 0x1C "CCTRL7,Counter control 7 register" bitfld.long 0x1C 8. "LOAD,Load Enable/Disable" "0,1" bitfld.long 0x1C 7. "SW_RESET,Reset" "0: Software reset is disabled,1: Software reset" newline bitfld.long 0x1C 4.--6. "PRESCALING,Prescaling" "0: No scaling divide by 1,1: Divide by 4,2: Divide by 16,3: Divide by 32,?,?,?,?" bitfld.long 0x1C 1. "MODE,Mode Select" "0: Counter,1: Timer" newline bitfld.long 0x1C 0. "ENABLE,Enable" "0: Counter disabled,1: Counter enabled" line.long 0x20 "CCTRL8,Counter control 8 register" bitfld.long 0x20 8. "LOAD,Load Enable/Disable" "0,1" bitfld.long 0x20 7. "SW_RESET,Reset" "0: Software reset is disabled,1: Software reset" newline bitfld.long 0x20 4.--6. "PRESCALING,Prescaling" "0: No scaling divide by 1,1: Divide by 4,2: Divide by 16,3: Divide by 32,?,?,?,?" bitfld.long 0x20 1. "MODE,Mode Select" "0: Counter,1: Timer" newline bitfld.long 0x20 0. "ENABLE,Enable" "0: Counter disabled,1: Counter enabled" line.long 0x24 "CCTRL9,Counter control 9 register" bitfld.long 0x24 8. "LOAD,Load Enable/Disable" "0,1" bitfld.long 0x24 7. "SW_RESET,Reset" "0: Software reset is disabled,1: Software reset" newline bitfld.long 0x24 4.--6. "PRESCALING,Prescaling" "0: No scaling divide by 1,1: Divide by 4,2: Divide by 16,3: Divide by 32,?,?,?,?" bitfld.long 0x24 1. "MODE,Mode Select" "0: Counter,1: Timer" newline bitfld.long 0x24 0. "ENABLE,Enable" "0: Counter disabled,1: Counter enabled" line.long 0x28 "CCTRL10,Counter control 10 register" bitfld.long 0x28 8. "LOAD,Load Enable/Disable" "0,1" bitfld.long 0x28 7. "SW_RESET,Reset" "0: Software reset is disabled,1: Software reset" newline bitfld.long 0x28 4.--6. "PRESCALING,Prescaling" "0: No scaling divide by 1,1: Divide by 4,2: Divide by 16,3: Divide by 32,?,?,?,?" bitfld.long 0x28 1. "MODE,Mode Select" "0: Counter,1: Timer" newline bitfld.long 0x28 0. "ENABLE,Enable" "0: Counter disabled,1: Counter enabled" line.long 0x2C "CCTRL11,Counter control 11 register" bitfld.long 0x2C 8. "LOAD,Load Enable/Disable" "0,1" bitfld.long 0x2C 7. "SW_RESET,Reset" "0: Software reset is disabled,1: Software reset" newline bitfld.long 0x2C 4.--6. "PRESCALING,Prescaling" "0: No scaling divide by 1,1: Divide by 4,2: Divide by 16,3: Divide by 32,?,?,?,?" bitfld.long 0x2C 1. "MODE,Mode Select" "0: Counter,1: Timer" newline bitfld.long 0x2C 0. "ENABLE,Enable" "0: Counter disabled,1: Counter enabled" line.long 0x30 "CCTRL12,Counter control 12 register" bitfld.long 0x30 8. "LOAD,Load Enable/Disable" "0,1" bitfld.long 0x30 7. "SW_RESET,Reset" "0: Software reset is disabled,1: Software reset" newline bitfld.long 0x30 4.--6. "PRESCALING,Prescaling" "0: No scaling divide by 1,1: Divide by 4,2: Divide by 16,3: Divide by 32,?,?,?,?" bitfld.long 0x30 1. "MODE,Mode Select" "0: Counter,1: Timer" newline bitfld.long 0x30 0. "ENABLE,Enable" "0: Counter disabled,1: Counter enabled" line.long 0x34 "CCTRL13,Counter control 13 register" bitfld.long 0x34 8. "LOAD,Load Enable/Disable" "0,1" bitfld.long 0x34 7. "SW_RESET,Reset" "0: Software reset is disabled,1: Software reset" newline bitfld.long 0x34 4.--6. "PRESCALING,Prescaling" "0: No scaling divide by 1,1: Divide by 4,2: Divide by 16,3: Divide by 32,?,?,?,?" bitfld.long 0x34 1. "MODE,Mode Select" "0: Counter,1: Timer" newline bitfld.long 0x34 0. "ENABLE,Enable" "0: Counter disabled,1: Counter enabled" line.long 0x38 "CCTRL14,Counter control 14 register" bitfld.long 0x38 8. "LOAD,Load Enable/Disable" "0,1" bitfld.long 0x38 7. "SW_RESET,Reset" "0: Software reset is disabled,1: Software reset" newline bitfld.long 0x38 4.--6. "PRESCALING,Prescaling" "0: No scaling divide by 1,1: Divide by 4,2: Divide by 16,3: Divide by 32,?,?,?,?" bitfld.long 0x38 1. "MODE,Mode Select" "0: Counter,1: Timer" newline bitfld.long 0x38 0. "ENABLE,Enable" "0: Counter disabled,1: Counter enabled" line.long 0x3C "CCTRL15,Counter control 15 register" bitfld.long 0x3C 8. "LOAD,Load Enable/Disable" "0,1" bitfld.long 0x3C 7. "SW_RESET,Reset" "0: Software reset is disabled,1: Software reset" newline bitfld.long 0x3C 4.--6. "PRESCALING,Prescaling" "0: No scaling divide by 1,1: Divide by 4,2: Divide by 16,3: Divide by 32,?,?,?,?" bitfld.long 0x3C 1. "MODE,Mode Select" "0: Counter,1: Timer" newline bitfld.long 0x3C 0. "ENABLE,Enable" "0: Counter disabled,1: Counter enabled" line.long 0x40 "CCMP0,Counter compare 0 register" hexmask.long 0x40 0.--31. 1. "COMPARE_VAL,Compare value" line.long 0x44 "CCMP1,Counter compare 1 register" hexmask.long 0x44 0.--31. 1. "COMPARE_VAL,Compare value" line.long 0x48 "CCMP2,Counter compare 2 register" hexmask.long 0x48 0.--31. 1. "COMPARE_VAL,Compare value" line.long 0x4C "CCMP3,Counter compare 3 register" hexmask.long 0x4C 0.--31. 1. "COMPARE_VAL,Compare value" line.long 0x50 "CCMP4,Counter compare 4 register" hexmask.long 0x50 0.--31. 1. "COMPARE_VAL,Compare value" line.long 0x54 "CCMP5,Counter compare 5 register" hexmask.long 0x54 0.--31. 1. "COMPARE_VAL,Compare value" line.long 0x58 "CCMP6,Counter compare 6 register" hexmask.long 0x58 0.--31. 1. "COMPARE_VAL,Compare value" line.long 0x5C "CCMP7,Counter compare 7 register" hexmask.long 0x5C 0.--31. 1. "COMPARE_VAL,Compare value" line.long 0x60 "CCMP8,Counter compare 8 register" hexmask.long 0x60 0.--31. 1. "COMPARE_VAL,Compare value" line.long 0x64 "CCMP9,Counter compare 9 register" hexmask.long 0x64 0.--31. 1. "COMPARE_VAL,Compare value" line.long 0x68 "CCMP10,Counter compare 10 register" hexmask.long 0x68 0.--31. 1. "COMPARE_VAL,Compare value" line.long 0x6C "CCMP11,Counter compare 11 register" hexmask.long 0x6C 0.--31. 1. "COMPARE_VAL,Compare value" line.long 0x70 "CCMP12,Counter compare 12 register" hexmask.long 0x70 0.--31. 1. "COMPARE_VAL,Compare value" line.long 0x74 "CCMP13,Counter compare 13 register" hexmask.long 0x74 0.--31. 1. "COMPARE_VAL,Compare value" line.long 0x78 "CCMP14,Counter compare 14 register" hexmask.long 0x78 0.--31. 1. "COMPARE_VAL,Compare value" line.long 0x7C "CCMP15,Counter compare 15 register" hexmask.long 0x7C 0.--31. 1. "COMPARE_VAL,Compare value" line.long 0x80 "CCOMS,Counter compare status register" bitfld.long 0x80 15. "CC15,Counter 15 Compare" "0: Counter status is not true,1: Counter status is true" bitfld.long 0x80 14. "CC14,Counter 14 Compare" "0: Counter status is not true,1: Counter status is true" newline bitfld.long 0x80 13. "CC13,Counter 13 Compare" "0: Counter status is not true,1: Counter status is true" bitfld.long 0x80 12. "CC12,Counter 12 Compare" "0: Counter status is not true,1: Counter status is true" newline bitfld.long 0x80 11. "CC11,Counter 11 Compare" "0: Counter status is not true,1: Counter status is true" bitfld.long 0x80 10. "CC10,Counter 10 Compare" "0: Counter status is not true,1: Counter status is true" newline bitfld.long 0x80 9. "CC9,Counter 9 Compare" "0: Counter status is not true,1: Counter status is true" bitfld.long 0x80 8. "CC8,Counter 8 Compare" "0: Counter status is not true,1: Counter status is true" newline bitfld.long 0x80 7. "CC7,Counter 7 Compare" "0: Counter status is not true,1: Counter status is true" bitfld.long 0x80 6. "CC6,Counter 6 Compare" "0: Counter status is not true,1: Counter status is true" newline bitfld.long 0x80 5. "CC5,Counter 5 Compare" "0: Counter status is not true,1: Counter status is true" bitfld.long 0x80 4. "CC4,Counter 4 Compare" "0: Counter status is not true,1: Counter status is true" newline bitfld.long 0x80 3. "CC3,Counter 3 Compare" "0: Counter status is not true,1: Counter status is true" bitfld.long 0x80 2. "CC2,Counter 2 Compare" "0: Counter status is not true,1: Counter status is true" newline bitfld.long 0x80 1. "CC1,Counter 1 Compare" "0: Counter status is not true,1: Counter status is true" bitfld.long 0x80 0. "CC0,Counter 0 Compare" "0: Counter status is not true,1: Counter status is true" line.long 0x84 "COS,Counter overflow status register" bitfld.long 0x84 15. "CO15,Counter 15 Overflow" "0: Counter did not overflow,1: Counter overflow occurred" bitfld.long 0x84 14. "CO14,Counter 14 Overflow" "0: Counter did not overflow,1: Counter overflow occurred" newline bitfld.long 0x84 13. "CO13,Counter 13 Overflow" "0: Counter did not overflow,1: Counter overflow occurred" bitfld.long 0x84 12. "CO12,Counter 12 Overflow" "0: Counter did not overflow,1: Counter overflow occurred" newline bitfld.long 0x84 11. "CO11,Counter 11 Overflow" "0: Counter did not overflow,1: Counter overflow occurred" bitfld.long 0x84 10. "CO10,Counter 10 Overflow" "0: Counter did not overflow,1: Counter overflow occurred" newline bitfld.long 0x84 9. "CO9,Counter 9 Overflow" "0: Counter did not overflow,1: Counter overflow occurred" bitfld.long 0x84 8. "CO8,Counter 8 Overflow" "0: Counter did not overflow,1: Counter overflow occurred" newline bitfld.long 0x84 7. "CO7,Counter 7 Overflow" "0: Counter did not overflow,1: Counter overflow occurred" bitfld.long 0x84 6. "CO6,Counter 6 Overflow" "0: Counter did not overflow,1: Counter overflow occurred" newline bitfld.long 0x84 5. "CO5,Counter 5 Overflow" "0: Counter did not overflow,1: Counter overflow occurred" bitfld.long 0x84 4. "CO4,Counter 4 Overflow" "0: Counter did not overflow,1: Counter overflow occurred" newline bitfld.long 0x84 3. "CO3,Counter 3 Overflow" "0: Counter did not overflow,1: Counter overflow occurred" bitfld.long 0x84 2. "CO2,Counter 2 Overflow" "0: Counter did not overflow,1: Counter overflow occurred" newline bitfld.long 0x84 1. "CO1,Counter 1 Overflow" "0: Counter did not overflow,1: Counter overflow occurred" bitfld.long 0x84 0. "CO0,Counter 0 Overflow" "0: Counter did not overflow,1: Counter overflow occurred" line.long 0x88 "CCAPS,Counter capture status register" bitfld.long 0x88 15. "CC15,Counter 15 Captured" "0: Counter not captured,1: Counter captured" bitfld.long 0x88 14. "CC14,Counter 14 Captured" "0: Counter not captured,1: Counter captured" newline bitfld.long 0x88 13. "CC13,Counter 13 Captured" "0: Counter not captured,1: Counter captured" bitfld.long 0x88 12. "CC12,Counter 12 Captured" "0: Counter not captured,1: Counter captured" newline bitfld.long 0x88 11. "CC11,Counter 11 Captured" "0: Counter not captured,1: Counter captured" bitfld.long 0x88 10. "CC10,Counter 10 Captured" "0: Counter not captured,1: Counter captured" newline bitfld.long 0x88 9. "CC9,Counter 9 Captured" "0: Counter not captured,1: Counter captured" bitfld.long 0x88 8. "CC8,Counter 8 Captured" "0: Counter not captured,1: Counter captured" newline bitfld.long 0x88 7. "CC7,Counter 7 Captured" "0: Counter not captured,1: Counter captured" bitfld.long 0x88 6. "CC6,Counter 6 Captured" "0: Counter not captured,1: Counter captured" newline bitfld.long 0x88 5. "CC5,Counter 5 Captured" "0: Counter not captured,1: Counter captured" bitfld.long 0x88 4. "CC4,Counter 4 Captured" "0: Counter not captured,1: Counter captured" newline bitfld.long 0x88 3. "CC3,Counter 3 Captured" "0: Counter not captured,1: Counter captured" bitfld.long 0x88 2. "CC2,Counter 2 Captured" "0: Counter not captured,1: Counter captured" newline bitfld.long 0x88 1. "CC1,Counter 1 Captured" "0: Counter not captured,1: Counter captured" bitfld.long 0x88 0. "CC0,Counter 0 Captured" "0: Counter not captured,1: Counter captured" group.long 0x2A0++0x1B line.long 0x0 "TRC_ID,Trace ID register" hexmask.long.byte 0x0 0.--6. 1. "TRACE_ID,Trace ID value" line.long 0x4 "TS_EN,Timestamp Enable register" bitfld.long 0x4 0. "TS_EN,Timestamp enable" "0: TS packet generation disabled.,1: TS packet generation enabled." line.long 0x8 "TS_WIN_CNT,Timestamp window counter register" hexmask.long 0x8 0.--31. 1. "WIND_COUNTER,Timestamp window counter value" line.long 0xC "TS_CLK_SCL,Timestamp clock scaler register" hexmask.long.word 0xC 0.--8. 1. "CLK_SCALER,Clock scaler value" line.long 0x10 "AL_EN,Alignment message enable register" bitfld.long 0x10 0. "AL_EN,Alignment Synchronization (A-Sync) enable" "0: A-Sync packet generation disabled.,1: A-Sync packet generation enabled." line.long 0x14 "AL_WIN_CNT,Alignment message window counter register" hexmask.long 0x14 0.--31. 1. "AL_WIND_COUNTER,Alignment synchronization messages window counter value" line.long 0x18 "AL_CLK_SCL,Alignment window counter clock scaler register" hexmask.long.word 0x18 0.--8. 1. "AL_CLK_SCALER,Clock scaler value" group.long 0x400++0x7 line.long 0x0 "PPCTIOUT0TGC,Packet probe CTI trigger group 0 register" bitfld.long 0x0 13. "MAINNOCPP_13,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" bitfld.long 0x0 12. "MAINNOCPP_12,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" newline bitfld.long 0x0 11. "MAINNOCPP_11,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" bitfld.long 0x0 10. "MAINNOCPP_10,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" newline bitfld.long 0x0 9. "MAINNOCPP_9,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" bitfld.long 0x0 8. "MAINNOCPP_8,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" newline bitfld.long 0x0 7. "MAINNOCPP_7,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" bitfld.long 0x0 6. "MAINNOCPP_6,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" newline bitfld.long 0x0 5. "MAINNOCPP_5,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" bitfld.long 0x0 4. "MAINNOCPP_4,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" newline bitfld.long 0x0 3. "MAINNOCPP_3,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" bitfld.long 0x0 2. "MAINNOCPP_2,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" newline bitfld.long 0x0 1. "MAINNOCPP_1,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" bitfld.long 0x0 0. "MAINNOCPP_0,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" line.long 0x4 "PPCTIOUT1TGC,Packet probe CTI trigger group 1 register" bitfld.long 0x4 13. "MAINNOCPP_13,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" bitfld.long 0x4 12. "MAINNOCPP_12,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" newline bitfld.long 0x4 11. "MAINNOCPP_11,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" bitfld.long 0x4 10. "MAINNOCPP_10,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" newline bitfld.long 0x4 9. "MAINNOCPP_9,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" bitfld.long 0x4 8. "MAINNOCPP_8,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" newline bitfld.long 0x4 7. "MAINNOCPP_7,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" bitfld.long 0x4 6. "MAINNOCPP_6,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" newline bitfld.long 0x4 5. "MAINNOCPP_5,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" bitfld.long 0x4 4. "MAINNOCPP_4,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" newline bitfld.long 0x4 3. "MAINNOCPP_3,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" bitfld.long 0x4 2. "MAINNOCPP_2,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" newline bitfld.long 0x4 1. "MAINNOCPP_1,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" bitfld.long 0x4 0. "MAINNOCPP_0,CTI trigger output selection for main NoC packet probe" "0: Packet probe not selected,1: Packet probe selected" group.long 0xFA0++0x7 line.long 0x0 "CLAIM_TAG_SET,Claim TAG set register" hexmask.long.byte 0x0 0.--3. 1. "CLAIM_SET,Claim set" line.long 0x4 "CLAIM_TAG_CLR,Claim TAG clear register" hexmask.long.byte 0x4 0.--3. 1. "CLAIM_CLEAR,Claim clear" wgroup.long 0xFB0++0x3 line.long 0x0 "LAR,Lock Access register" hexmask.long 0x0 0.--31. 1. "SW_KEY,Software lock key value" rgroup.long 0xFB4++0xB line.long 0x0 "LSR,Lock status register" bitfld.long 0x0 2. "NTT,nTT" "0: Lock Access register (LAR) register is 32-bit..,?" bitfld.long 0x0 1. "SLK,SLK returns the SW lock status." "0: Accesses permitted.,1: Write access to control registers is blocked.." newline bitfld.long 0x0 0. "SLI,SLK returns the SW lock status." "0: Software lock is not implemented returned for..,1: Software lock is implemented returned for all.." line.long 0x4 "AUTH_STAT,Authentication status register" bitfld.long 0x4 6.--7. "SNID,Secure non-invasive debug" "0: Functionality not implemented.,?,?,?" bitfld.long 0x4 4.--5. "SID,Secure invasive debug" "0: Functionality not implemented.,?,?,?" newline bitfld.long 0x4 2.--3. "NSNID,Non-secure non-invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." bitfld.long 0x4 0.--1. "NSID,Non-secure invasive debug" "?,?,2: Implemented but disabled.,3: Implemented and enabled." line.long 0x8 "DEV_ARCH,Device architecture register" hexmask.long.word 0x8 21.--31. 1. "ARCHITECT,Define the Architect of the component" bitfld.long 0x8 20. "PRES,Presence" "?,1: Device Architecture register is present." newline hexmask.long.byte 0x8 16.--19. 1. "ARCH_REVISION,Architecture revision" hexmask.long.word 0x8 0.--15. 1. "ARCH_ID,Architecture ID" rgroup.long 0xFC8++0x37 line.long 0x0 "DEV_ID,Device ID register" hexmask.long 0x0 0.--31. 1. "FUTURE_USE,Reserved for future use" line.long 0x4 "DEV_TYPE,Device type register" hexmask.long.byte 0x4 4.--7. 1. "SUB,Minor classification" hexmask.long.byte 0x4 0.--3. 1. "MAJOR,Major classification" line.long 0x8 "PID4,Peripheral ID4 register" hexmask.long.byte 0x8 4.--7. 1. "SIZE,Size" hexmask.long.byte 0x8 0.--3. 1. "DES_2,DES_2" line.long 0xC "PID5,Peripheral ID5 register" hexmask.long 0xC 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x10 "PID6,Peripheral ID6 register" hexmask.long 0x10 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x14 "PID7,Peripheral ID7 register" hexmask.long 0x14 0.--31. 1. "FUTURE_USE,Reserved for Future Use." line.long 0x18 "PID0,Peripheral ID0 register" hexmask.long.byte 0x18 4.--7. 1. "PART_0M,Part 0M" hexmask.long.byte 0x18 0.--3. 1. "PART_0L,Part 0L" line.long 0x1C "PID1,Peripheral ID1 register" hexmask.long.byte 0x1C 4.--7. 1. "DES_0,DES_0" hexmask.long.byte 0x1C 0.--3. 1. "PART_1,Part 1" line.long 0x20 "PID2,Peripheral ID2 register" hexmask.long.byte 0x20 4.--7. 1. "REVISION,Revision" bitfld.long 0x20 3. "JEDEC,JEDEC" "?,1: Indicates that a JEDEC assigned value is used." newline bitfld.long 0x20 0.--2. "DES_1,DES 1" "?,?,2: ST JEP106 identification code bit[6:4].,?,?,?,?,?" line.long 0x24 "PID3,Peripheral ID3 register" hexmask.long.byte 0x24 4.--7. 1. "REVAND,REVAND" hexmask.long.byte 0x24 0.--3. 1. "CMOD,CMOD" line.long 0x28 "CID0,CS ID0 register" hexmask.long.byte 0x28 0.--7. 1. "PRMB0,Preamble 0" line.long 0x2C "CID1,CS ID1 register" hexmask.long.byte 0x2C 4.--7. 1. "CLASS,Class" hexmask.long.byte 0x2C 0.--3. 1. "PRMB1,Preamble 1" line.long 0x30 "CID2,CS ID2 register" hexmask.long.byte 0x30 0.--7. 1. "PRMB2,Preamble 2" line.long 0x34 "CID3,CS ID3 register" hexmask.long.byte 0x34 0.--7. 1. "PRMB3,Preamble 3" tree.end tree "SWT_SYS (Software Watchdog Timer)" base ad:0x0 tree "SWT_SYS_0" base ad:0x70F40000 group.long 0x0++0xF line.long 0x0 "CR,SWT Control Register" bitfld.long 0x0 31. "MAP0,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 30. "MAP1,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 29. "MAP2,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 28. "MAP3,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 27. "MAP4,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 26. "MAP5,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 25. "MAP6,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 24. "MAP7,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 9.--10. "SMD,SMD" "0: Fixed Service Sequence the watchdog is serviced..,1: Keyed Service Sequence the watchdog is serviced..,2: Reserved-do not use. Writing this value can..,3: Reserved-do not use. Writing this value can.." bitfld.long 0x0 8. "RIA,RIA" "0: Invalid access to the SWT generates a bus error,1: Invalid access to the SWT causes a system reset.." newline bitfld.long 0x0 7. "WND,WND" "0: Regular mode service sequence can be done at any..,1: Windowed mode the service sequence is only valid.." bitfld.long 0x0 6. "ITR,ITR" "0: Generate a reset on a time-out,1: Generate an interrupt on an initial time-out.." newline bitfld.long 0x0 5. "HLK,This bit is only cleared at reset." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." bitfld.long 0x0 4. "SLK,This bit is cleared by writing the unlock sequence to the service register." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." newline bitfld.long 0x0 3. "CSL,Selects the clock that drives the internal timer." "0: System clock,1: Oscillator clock" bitfld.long 0x0 2. "STP,Allows the watchdog timer to be stopped when the device enters stop mode." "0: SWT counter continues to run in stop mode,1: SWT counter is stopped in stop mode" newline bitfld.long 0x0 1. "FRZ,Allows the watchdog timer to be stopped when the device enters debug mode." "0: SWT counter continues to run in debug mode,1: SWT counter is stopped in debug mode" bitfld.long 0x0 0. "WEN,WEN" "0: SWT is disabled,1: SWT is enabled" line.long 0x4 "IR,SWT Interrupt Register" bitfld.long 0x4 0. "TIF,The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect." "0: No interrupt request.,1: Interrupt request due to an initial time-out." line.long 0x8 "TO,SWT Time-Out Register" hexmask.long 0x8 0.--31. 1. "WTO,An internal 32-bit down counter is loaded with this value when the service sequence is written or when the SWT is enabled." line.long 0xC "WN,SWT Window Register" hexmask.long 0xC 0.--31. 1. "WST,When window mode is enabled the service sequence can only be written when the internal down counter is less than this value." wgroup.long 0x10++0x3 line.long 0x0 "SR,SWT Service Register" hexmask.long.word 0x0 0.--15. 1. "WSC,This field is used to service the watchdog and to clear the soft lock bit (SWT_CR[SLK]). If the SWT_CR[SMD]=01 two pseudorandom key values are written to service the watchdog refer to Section 1.4.1.1: SWT Control Register (SWT_CR) for details." rgroup.long 0x14++0x3 line.long 0x0 "CO,SWT Counter Output Register" hexmask.long 0x0 0.--31. 1. "CNT,When the watchdog is disabled (SWT_CR[WEN]=0) this field shows the value of the internal down counter. When the watchdog is enabled (SWT_CR[WEN]=1) this field is cleared (the value is 0x0000_0000). Values in this field can lag behind the internal.." group.long 0x18++0x3 line.long 0x0 "SK,SWT Service Key Register" hexmask.long.word 0x0 0.--15. 1. "SK,This field is the previous (or initial) service key value used in keyed service mode. If SWT_CR[SMD]=01 the next key value to be written to the SWT_SR is (17*SK+3) mod 2^16." tree.end tree "SWT_SYS_1" base ad:0x72140000 group.long 0x0++0xF line.long 0x0 "CR,SWT Control Register" bitfld.long 0x0 31. "MAP0,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 30. "MAP1,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 29. "MAP2,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 28. "MAP3,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 27. "MAP4,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 26. "MAP5,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 25. "MAP6,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 24. "MAP7,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 9.--10. "SMD,SMD" "0: Fixed Service Sequence the watchdog is serviced..,1: Keyed Service Sequence the watchdog is serviced..,2: Reserved-do not use. Writing this value can..,3: Reserved-do not use. Writing this value can.." bitfld.long 0x0 8. "RIA,RIA" "0: Invalid access to the SWT generates a bus error,1: Invalid access to the SWT causes a system reset.." newline bitfld.long 0x0 7. "WND,WND" "0: Regular mode service sequence can be done at any..,1: Windowed mode the service sequence is only valid.." bitfld.long 0x0 6. "ITR,ITR" "0: Generate a reset on a time-out,1: Generate an interrupt on an initial time-out.." newline bitfld.long 0x0 5. "HLK,This bit is only cleared at reset." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." bitfld.long 0x0 4. "SLK,This bit is cleared by writing the unlock sequence to the service register." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." newline bitfld.long 0x0 3. "CSL,Selects the clock that drives the internal timer." "0: System clock,1: Oscillator clock" bitfld.long 0x0 2. "STP,Allows the watchdog timer to be stopped when the device enters stop mode." "0: SWT counter continues to run in stop mode,1: SWT counter is stopped in stop mode" newline bitfld.long 0x0 1. "FRZ,Allows the watchdog timer to be stopped when the device enters debug mode." "0: SWT counter continues to run in debug mode,1: SWT counter is stopped in debug mode" bitfld.long 0x0 0. "WEN,WEN" "0: SWT is disabled,1: SWT is enabled" line.long 0x4 "IR,SWT Interrupt Register" bitfld.long 0x4 0. "TIF,The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect." "0: No interrupt request.,1: Interrupt request due to an initial time-out." line.long 0x8 "TO,SWT Time-Out Register" hexmask.long 0x8 0.--31. 1. "WTO,An internal 32-bit down counter is loaded with this value when the service sequence is written or when the SWT is enabled." line.long 0xC "WN,SWT Window Register" hexmask.long 0xC 0.--31. 1. "WST,When window mode is enabled the service sequence can only be written when the internal down counter is less than this value." wgroup.long 0x10++0x3 line.long 0x0 "SR,SWT Service Register" hexmask.long.word 0x0 0.--15. 1. "WSC,This field is used to service the watchdog and to clear the soft lock bit (SWT_CR[SLK]). If the SWT_CR[SMD]=01 two pseudorandom key values are written to service the watchdog refer to Section 1.4.1.1: SWT Control Register (SWT_CR) for details." rgroup.long 0x14++0x3 line.long 0x0 "CO,SWT Counter Output Register" hexmask.long 0x0 0.--31. 1. "CNT,When the watchdog is disabled (SWT_CR[WEN]=0) this field shows the value of the internal down counter. When the watchdog is enabled (SWT_CR[WEN]=1) this field is cleared (the value is 0x0000_0000). Values in this field can lag behind the internal.." group.long 0x18++0x3 line.long 0x0 "SK,SWT Service Key Register" hexmask.long.word 0x0 0.--15. 1. "SK,This field is the previous (or initial) service key value used in keyed service mode. If SWT_CR[SMD]=01 the next key value to be written to the SWT_SR is (17*SK+3) mod 2^16." tree.end tree "SWT_SYS_2" base ad:0x70F44000 group.long 0x0++0xF line.long 0x0 "CR,SWT Control Register" bitfld.long 0x0 31. "MAP0,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 30. "MAP1,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 29. "MAP2,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 28. "MAP3,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 27. "MAP4,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 26. "MAP5,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 25. "MAP6,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" bitfld.long 0x0 24. "MAP7,Always program to ‘FF’ or a response transfer error can be generated during watchdog access" "0,1" newline bitfld.long 0x0 9.--10. "SMD,SMD" "0: Fixed Service Sequence the watchdog is serviced..,1: Keyed Service Sequence the watchdog is serviced..,2: Reserved-do not use. Writing this value can..,3: Reserved-do not use. Writing this value can.." bitfld.long 0x0 8. "RIA,RIA" "0: Invalid access to the SWT generates a bus error,1: Invalid access to the SWT causes a system reset.." newline bitfld.long 0x0 7. "WND,WND" "0: Regular mode service sequence can be done at any..,1: Windowed mode the service sequence is only valid.." bitfld.long 0x0 6. "ITR,ITR" "0: Generate a reset on a time-out,1: Generate an interrupt on an initial time-out.." newline bitfld.long 0x0 5. "HLK,This bit is only cleared at reset." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." bitfld.long 0x0 4. "SLK,This bit is cleared by writing the unlock sequence to the service register." "0: SWT_CR SWT_TO SWT_WN and SWT_SK are read/write..,1: SWT_CR SWT_TO SWT_WN and SWT_SK are read-only.." newline bitfld.long 0x0 3. "CSL,Selects the clock that drives the internal timer." "0: System clock,1: Oscillator clock" bitfld.long 0x0 2. "STP,Allows the watchdog timer to be stopped when the device enters stop mode." "0: SWT counter continues to run in stop mode,1: SWT counter is stopped in stop mode" newline bitfld.long 0x0 1. "FRZ,Allows the watchdog timer to be stopped when the device enters debug mode." "0: SWT counter continues to run in debug mode,1: SWT counter is stopped in debug mode" bitfld.long 0x0 0. "WEN,WEN" "0: SWT is disabled,1: SWT is enabled" line.long 0x4 "IR,SWT Interrupt Register" bitfld.long 0x4 0. "TIF,The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect." "0: No interrupt request.,1: Interrupt request due to an initial time-out." line.long 0x8 "TO,SWT Time-Out Register" hexmask.long 0x8 0.--31. 1. "WTO,An internal 32-bit down counter is loaded with this value when the service sequence is written or when the SWT is enabled." line.long 0xC "WN,SWT Window Register" hexmask.long 0xC 0.--31. 1. "WST,When window mode is enabled the service sequence can only be written when the internal down counter is less than this value." wgroup.long 0x10++0x3 line.long 0x0 "SR,SWT Service Register" hexmask.long.word 0x0 0.--15. 1. "WSC,This field is used to service the watchdog and to clear the soft lock bit (SWT_CR[SLK]). If the SWT_CR[SMD]=01 two pseudorandom key values are written to service the watchdog refer to Section 1.4.1.1: SWT Control Register (SWT_CR) for details." rgroup.long 0x14++0x3 line.long 0x0 "CO,SWT Counter Output Register" hexmask.long 0x0 0.--31. 1. "CNT,When the watchdog is disabled (SWT_CR[WEN]=0) this field shows the value of the internal down counter. When the watchdog is enabled (SWT_CR[WEN]=1) this field is cleared (the value is 0x0000_0000). Values in this field can lag behind the internal.." group.long 0x18++0x3 line.long 0x0 "SK,SWT Service Key Register" hexmask.long.word 0x0 0.--15. 1. "SK,This field is the previous (or initial) service key value used in keyed service mode. If SWT_CR[SMD]=01 the next key value to be written to the SWT_SR is (17*SK+3) mod 2^16." tree.end tree.end tree "SYSCONF (System Configuration Module)" base ad:0x0 tree "SYSCONF_0" base ad:0x704F8000 group.long 0x0++0x7 line.long 0x0 "GCR_0," bitfld.long 0x0 16. "ENABLE_PLL,Enable input for the PLL part." "0,1" bitfld.long 0x0 15. "ENABLE_DEL15,Enable input for the corresponding Delay Block." "0,1" bitfld.long 0x0 14. "ENABLE_DEL14,Enable input for the corresponding Delay Block." "0,1" bitfld.long 0x0 13. "ENABLE_DEL13,Enable input for the corresponding Delay Block." "0,1" bitfld.long 0x0 12. "ENABLE_DEL12,Enable input for the corresponding Delay Block." "0,1" newline bitfld.long 0x0 11. "ENABLE_DEL11,Enable input for the corresponding Delay Block." "0,1" bitfld.long 0x0 10. "ENABLE_DEL10,Enable input for the corresponding Delay Block." "0,1" bitfld.long 0x0 9. "ENABLE_DEL9,Enable input for the corresponding Delay Block." "0,1" bitfld.long 0x0 8. "ENABLE_DEL8,Enable input for the corresponding Delay Block." "0,1" bitfld.long 0x0 7. "ENABLE_DEL7,Enable input for the corresponding Delay Block." "0,1" newline bitfld.long 0x0 6. "ENABLE_DEL6,Enable input for the corresponding Delay Block." "0,1" bitfld.long 0x0 5. "ENABLE_DEL5,Enable input for the corresponding Delay Block." "0,1" bitfld.long 0x0 4. "ENABLE_DEL4,Enable input for the corresponding Delay Block." "0,1" bitfld.long 0x0 3. "ENABLE_DEL3,Enable input for the corresponding Delay Block." "0,1" bitfld.long 0x0 2. "ENABLE_DEL2,Enable input for the corresponding Delay Block." "0,1" newline bitfld.long 0x0 1. "ENABLE_DEL1,Enable input for the corresponding Delay Block." "0,1" bitfld.long 0x0 0. "ENABLE_DEL0,Enable input for the corresponding Delay Block." "0,1" line.long 0x4 "GCR_1," bitfld.long 0x4 15. "BYPASS15_EN,Bypass Enable input for the corresponding Delay Block15." "0,1" bitfld.long 0x4 14. "BYPASS14_EN,Bypass Enable input for the corresponding Delay Block14." "0,1" bitfld.long 0x4 13. "BYPASS13_EN,Bypass Enable input for the corresponding Delay Block13." "0,1" bitfld.long 0x4 12. "BYPASS12_EN,Bypass Enable input for the corresponding Delay Block12." "0,1" bitfld.long 0x4 11. "BYPASS11_EN,Bypass Enable input for the corresponding Delay Block11." "0,1" newline bitfld.long 0x4 10. "BYPASS10_EN,Bypass Enable input for the corresponding Delay Block10." "0,1" bitfld.long 0x4 9. "BYPASS9_EN,Bypass Enable input for the corresponding Delay Block9." "0,1" bitfld.long 0x4 8. "BYPASS8_EN,Bypass Enable input for the corresponding Delay Block8." "0,1" bitfld.long 0x4 7. "BYPASS7_EN,Bypass Enable input for the corresponding Delay Block7." "0,1" bitfld.long 0x4 6. "BYPASS6_EN,Bypass Enable input for the corresponding Delay Block6." "0,1" newline bitfld.long 0x4 5. "BYPASS5_EN,Bypass Enable input for the corresponding Delay Block5." "0,1" bitfld.long 0x4 4. "BYPASS4_EN,Bypass Enable input for the corresponding Delay Block4." "0,1" bitfld.long 0x4 3. "BYPASS3_EN,Bypass Enable input for the corresponding Delay Block3." "0,1" bitfld.long 0x4 2. "BYPASS2_EN,Bypass Enable input for the corresponding Delay Block2." "0,1" bitfld.long 0x4 1. "BYPASS1_EN,Bypass Enable input for the corresponding Delay Block1." "0,1" newline bitfld.long 0x4 0. "BYPASS0_EN,Bypass Enable input for the corresponding Delay Block 0." "0,1" group.long 0xC++0x3 line.long 0x0 "GCR_3," bitfld.long 0x0 12. "SWAP_CL1_C3D2,cluster 1 RWW3 complementary array is swapped with cluster1 RWW2 direct array" "0,1" bitfld.long 0x0 8. "SWAP_CL1_C2D3,cluster 1 RWW2 complementary array is swapped with cluster1 RWW3 direct array" "0,1" bitfld.long 0x0 4. "SWAP_CL1_C1D0,cluster 1 RWW1 complementary array is swapped with cluster1 RWW0 direct array" "0,1" bitfld.long 0x0 0. "SWAP_CL1_C0D1,cluster 1 RWW0 complementary array is swapped with cluster1 RWW1 direct array" "0,1" group.long 0x14++0x7 line.long 0x0 "GCR_5," bitfld.long 0x0 21. "EXTPPI_CL2_CORE1_SWT1,EXTPPI_CL2_CORE1_SWT1" "0,1" bitfld.long 0x0 20. "EXTPPI_CL2_CORE1_SWT0,EXTPPI_CL2_CORE1_SWT0" "0,1" bitfld.long 0x0 19. "EXTPPI_CL2_CORE1_ME,EXTPPI_CL2_CORE1_ME" "0,1" bitfld.long 0x0 18. "EXTPPI_CL2_CORE0_SWT1,EXTPPI_CL2_CORE0_SWT1" "0,1" bitfld.long 0x0 17. "EXTPPI_CL2_CORE0_SWT0,EXTPPI_CL2_CORE0_SWT0" "0,1" newline bitfld.long 0x0 16. "EXTPPI_CL2_CORE0_ME,EXTPPI_CL2_CORE0_ME" "0,1" bitfld.long 0x0 13. "EXTPPI_CL1_CORE1_SWT1,Enable input for the corresponding Delay Block." "0,1" bitfld.long 0x0 12. "EXTPPI_CL1_CORE1_SWT0,EXTPPI_CL1_CORE1_SWT0" "0,1" bitfld.long 0x0 11. "EXTPPI_CL1_CORE1_ME,EXTPPI_CL1_CORE1_ME" "0,1" bitfld.long 0x0 10. "EXTPPI_CL1_CORE0_SWT1,EXTPPI_CL1_CORE0_SWT1" "0,1" newline bitfld.long 0x0 9. "EXTPPI_CL1_CORE0_SWT0,EXTPPI_CL1_CORE0_SWT0" "0,1" bitfld.long 0x0 8. "EXTPPI_CL1_CORE0_ME,EXTPPI_CL1_CORE0_ME" "0,1" bitfld.long 0x0 5. "EXTPPI_CL0_CORE1_SWT1,Enable input for the corresponding Delay Block." "0,1" bitfld.long 0x0 4. "EXTPPI_CL0_CORE1_SWT0,EXTPPI_CL0_CORE1_SWT0" "0,1" bitfld.long 0x0 3. "EXTPPI_CL0_CORE1_ME,EXTPPI_CL0_CORE1_ME" "0,1" newline bitfld.long 0x0 2. "EXTPPI_CL0_CORE0_SWT1,EXTPPI_CL0_CORE0_SWT1" "0,1" bitfld.long 0x0 1. "EXTPPI_CL0_CORE0_SWT0,EXTPPI_CL0_CORE0_SWT0" "0,1" bitfld.long 0x0 0. "EXTPPI_CL0_CORE0_ME,EXTPPI_CL0_CORE0_ME" "0,1" line.long 0x4 "GCR_6," hexmask.long.word 0x4 0.--15. 1. "MISC_CONFIG,misc configuration register" rgroup.long 0x200++0x3 line.long 0x0 "GSR_0," bitfld.long 0x0 0. "PLL_LOCKP,This signal goes high after the PLL attains the fine lock state" "0,1" tree.end tree "SYSCONF_4" base ad:0x71CF8000 group.long 0x0++0x27 line.long 0x0 "GCR_0," hexmask.long.byte 0x0 26.--31. 1. "ETH_0_MISC_CONFIG,misc configuration for ethernet_0" bitfld.long 0x0 24. "ETH0_RMII_CLK_SEL,RMII Clock input Select" "0,1" bitfld.long 0x0 20. "ETH0_MII_RXCLK_SEL,MII Rx Clock input Select" "0,1" bitfld.long 0x0 16. "ETH0_MII_TXCLK_SEL,MII Tx Clock input Select" "0,1" newline bitfld.long 0x0 12. "ETH0_RGMII_TXCLK_SEL,RGMII Tx clock input Select" "0,1" bitfld.long 0x0 8. "ETH0_RGMII_TXCLK_DOS,RGMII Tx clock output option select" "0,1" bitfld.long 0x0 4. "ETH0_PHY_CLK_SEL,PHY clock select" "0,1" bitfld.long 0x0 2. "ETH0_PHY_INTF_SEL_2,PHY interface select" "0,1" newline bitfld.long 0x0 1. "ETH0_PHY_INTF_SEL_1,PHY interface select" "0,1" bitfld.long 0x0 0. "ETH0_PHY_INTF_SEL_0,PHY interface select" "0,1" line.long 0x4 "GCR_1," hexmask.long.byte 0x4 26.--31. 1. "ETH_1_MISC_CONFIG,misc configuration for ethernet_1" bitfld.long 0x4 24. "ETH1_RMII_CLK_SEL,RMII Clock input Select" "0,1" bitfld.long 0x4 4. "ETH1_PHY_CLK_SEL,PHY clock select" "0,1" bitfld.long 0x4 2. "ETH1_PHY_INTF_SEL_2,PHY interface select" "0,1" newline bitfld.long 0x4 1. "ETH1_PHY_INTF_SEL_1,PHY interface select" "0,1" bitfld.long 0x4 0. "ETH1_PHY_INTF_SEL_0,PHY interface select" "0,1" line.long 0x8 "GCR_2," hexmask.long 0x8 0.--31. 1. "INSTR_ADDR_CLUSTER0_CORE0,INSTR_ADDR_Cluster0_Core0" line.long 0xC "GCR_3," hexmask.long 0xC 0.--31. 1. "INSTR_ADDR_CLUSTER0_CORE1,INSTR_ADDR_Cluster0_Core1" line.long 0x10 "GCR_4," hexmask.long 0x10 0.--31. 1. "INSTR_ADDR_CLUSTER1_CORE0,INSTR_ADDR_Cluster1_Core0" line.long 0x14 "GCR_5," hexmask.long 0x14 0.--31. 1. "INSTR_ADDR_CLUSTER1_CORE1,INSTR_ADDR_Cluster1_Core1" line.long 0x18 "GCR_6," hexmask.long 0x18 0.--31. 1. "INSTR_ADDR_CLUSTER2_CORE0,INSTR_ADDR_Cluster2_Core0" line.long 0x1C "GCR_7," hexmask.long 0x1C 0.--31. 1. "INSTR_ADDR_CLUSTER2_CORE1,INSTR_ADDR_Cluster2_Core1" line.long 0x20 "GCR_8," hexmask.long 0x20 7.--31. 1. "SGMII_0_MISC_CFG,misc configuration for sgmii_0" bitfld.long 0x20 6. "SGMII_0_PHY_PLL_EN,pll_enable" "0,1" bitfld.long 0x20 5. "SGMII_0_PLL_MULT_1,pll_multiplier" "0,1" bitfld.long 0x20 4. "SGMII_0_PLL_MULT_0,pll_multiplier" "0,1" newline bitfld.long 0x20 3. "SGMII_0_RX_DATA_REV,-" "0,1" bitfld.long 0x20 2. "SGMII_0_TX_DATA_REV,-" "0,1" bitfld.long 0x20 1. "SGMII_0_MAC_LPBK_1,MAC loopback" "0,1" bitfld.long 0x20 0. "SGMII_0_MAC_LPBK_0,MAC loopback" "0,1" line.long 0x24 "GCR_9," hexmask.long 0x24 7.--31. 1. "SGMII_1_MISC_CONFIG,misc configuration for sgmii_1" bitfld.long 0x24 6. "SGMII_1_PHY_PLL_EN,pll_enable" "0,1" bitfld.long 0x24 5. "SGMII_1_PLL_MULT_1,pll_multiplier" "0,1" bitfld.long 0x24 4. "SGMII_1_PLL_MULT_0,pll_multiplier" "0,1" newline bitfld.long 0x24 3. "SGMII_1_RX_DATA_REV,-" "0,1" bitfld.long 0x24 2. "SGMII_1_TX_DATA_REV,-" "0,1" bitfld.long 0x24 1. "SGMII_1_MAC_LPBK_1,MAC loopback" "0,1" bitfld.long 0x24 0. "SGMII_1_MAC_LPBK_0,MAC loopback" "0,1" rgroup.long 0x200++0x7 line.long 0x0 "GSR_0," hexmask.long.word 0x0 1.--15. 1. "SGMII_0_MISC_STATUS,sgmii 0 misc status register" bitfld.long 0x0 0. "SGMII_0_PLL_LOCKP,This signal goes high after the PLL attains the fine lock state" "0,1" line.long 0x4 "GSR_1," hexmask.long.word 0x4 1.--15. 1. "SGMII_1_MISC_STATUS,sgmii 1 misc status register" bitfld.long 0x4 0. "SGMII_1_PLL_LOCKP,This signal goes high after the PLL attains the fine lock state" "0,1" tree.end tree "SYSCONF_5" base ad:0x722F8000 group.long 0x0++0x7 line.long 0x0 "GCR_0," bitfld.long 0x0 4. "B_OBE,B_OBE is used to enable or disabled RESET_B output buffer via SW (when the output buffer is enabled then a logical level 0 is forced on the pad) reset value is set by RESET_CFG[B_HW_SW] DCF bit (Default value = HW control (0)" "0,1" bitfld.long 0x0 0. "A_OBE,A_OBE is used to enable or disabled RESET_A output buffer via SW (when the output buffer is enabled then a logical level 0 is forced on the pad) reset value is set by RESET_CFG[A_HW_SW] DCF bit (Default value = HW control (0)" "0,1" line.long 0x4 "GCR_1," bitfld.long 0x4 31. "LPGPIODO31,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 30. "LPGPIODO30,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 29. "LPGPIODO29,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 28. "LPGPIODO28,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 27. "LPGPIODO27,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 26. "LPGPIODO26,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 25. "LPGPIODO25,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 24. "LPGPIODO24,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 23. "LPGPIODO23,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 22. "LPGPIODO22,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" newline bitfld.long 0x4 21. "LPGPIODO21,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 20. "LPGPIODO20,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 19. "LPGPIODO19,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 18. "LPGPIODO18,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 17. "LPGPIODO17,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 16. "LPGPIODO16,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 15. "LPGPIODO15,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 14. "LPGPIODO14,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 13. "LPGPIODO13,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 12. "LPGPIODO12,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" newline bitfld.long 0x4 11. "LPGPIODO11,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 10. "LPGPIODO10,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 9. "LPGPIODO9,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 8. "LPGPIODO8,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 7. "LPGPIODO7,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 6. "LPGPIODO6,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 5. "LPGPIODO5,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 4. "LPGPIODO4,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 3. "LPGPIODO3,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 2. "LPGPIODO2,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" newline bitfld.long 0x4 1. "LPGPIODO1,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" bitfld.long 0x4 0. "LPGPIODO0,Low Power GPIO Pad Data Out. This bit stores the data to be driven out on the external LP GPIO pad controlled by this register" "0,1" rgroup.long 0x200++0x3 line.long 0x0 "GSR_0," bitfld.long 0x0 31. "LPGPIODI31,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 30. "LPGPIODI30,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 29. "LPGPIODI29,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 28. "LPGPIODI28,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 27. "LPGPIODI27,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 26. "LPGPIODI26,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 25. "LPGPIODI25,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 24. "LPGPIODI24,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 23. "LPGPIODI23,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 22. "LPGPIODI22,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" newline bitfld.long 0x0 21. "LPGPIODI21,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 20. "LPGPIODI20,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 19. "LPGPIODI19,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 18. "LPGPIODI18,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 17. "LPGPIODI17,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 16. "LPGPIODI16,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 15. "LPGPIODI15,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 14. "LPGPIODI14,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 13. "LPGPIODI13,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 12. "LPGPIODI12,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" newline bitfld.long 0x0 11. "LPGPIODI11,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 10. "LPGPIODI10,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 9. "LPGPIODI9,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 8. "LPGPIODI8,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 7. "LPGPIODI7,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 6. "LPGPIODI6,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 5. "LPGPIODI5,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 4. "LPGPIODI4,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 3. "LPGPIODI3,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 2. "LPGPIODI2,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" newline bitfld.long 0x0 1. "LPGPIODI1,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" bitfld.long 0x0 0. "LPGPIODI0,Low Power GPIO Pad Data In. This bit stores the value of the external LP GPIO pad associated with this register." "0,1" tree.end tree.end tree "TNDCM (Trace and Debug Control Module)" base ad:0x7100C000 group.long 0x0++0x3 line.long 0x0 "CR,Control Register" bitfld.long 0x0 28. "HOST_DEBUG_EN,It is used to enable host based debugging. By default when debugger is not connected debug and trace logic remains in reset. Setting this bit to HIGH will bring the debug and trace resources out-of-reset. When any CPU or non-CPU Bus Master.." "0: When debugger is not connected then host based..,1: When debugger is not connected then host based.." newline bitfld.long 0x0 25. "MASK_DEBUG_FAULTS,It is used to mask the faults which are originated due to safety faults in Debug-n-Trace logic interfering with functional logic." "0: Faults are not masked,1: Faults are masked" newline bitfld.long 0x0 17. "FUNC_RST,Force Functional reset" "0: Do not force functional reset,1: Force functional reset" newline bitfld.long 0x0 16. "DEST_RST,Force Destructive reset" "0: Do not force destructive reset,1: Force destructive reset" newline bitfld.long 0x0 12. "SECDAP_SWD_O_PAD_EN,Secondary DAP Serial Wire debug output PAD enable. Output PAD is active only in 3-pin mode." "0: Secondary DAP SWD Output PAD is not forced,1: Secondary DAP SWD Output PAD is forced to enable" newline bitfld.long 0x0 11. "SECDAP_SWD_TCK_TMS_PAD_EN,Secondary DAP Serial Wire debug IO PAD enable" "0: Secondary DAP SWD PADs are not forced,1: Secondary DAP SWD PADs are forced to enable" newline bitfld.long 0x0 10. "MAINDAP_TDO_PAD_EN,MainDAP TDO PAD enable." "0: Main DAP TDO PAD is not forced,1: Main DAP TDO PAD is forced to enable" newline bitfld.long 0x0 9. "MAINDAP_TDI_PAD_EN,Main DAP TDI PAD enable" "0: Main DAP TDI PAD is not forced,1: Main DAP TDI PAD is forced to enable" newline bitfld.long 0x0 8. "MAINDAP_JCOMP_TCK_TMS_PAD_EN,Main DAP nTRST (JCOMP) TCK and TMS PADs enable" "0: Main DAP PAD are not forced,1: Main DAP PADs are forced to enable" newline bitfld.long 0x0 3. "EVTI1_PAD_EN,EVTI_n[1] input enable is forced on pad" "0: EVTI_n[1] disabled on pads,1: EVTI_n[1] enabled on pads" newline bitfld.long 0x0 2. "EVTI0_PAD_EN,EVTI_n[0] input enable is forced on pad" "0: EVTI_n[0] disabled on pads,1: EVTI_n[0] enabled on pads" newline bitfld.long 0x0 1. "EVTO1_PAD_EN,Output enable for EVTO_n[1] pad" "0: EVTO_n[1] pad output not enabled,1: EVTO_n[1] pad output enabled" newline bitfld.long 0x0 0. "EVTO0_PAD_EN,Output enable for EVTO_n[0] pad" "0: EVTO_n[0] pad output not enabled,1: EVTO_n[0] pad output enabled" rgroup.long 0x8++0x3 line.long 0x0 "SR,Status Register" bitfld.long 0x0 24. "LP_DBG_EN_PD0,Status of Low Power debug Enable bit after reserving in STANDBY (PD0) domain" "0: Low power debug is not enabled or the enable bit..,1: Low power debug is enabled and preserved in PD0" newline hexmask.long.byte 0x0 20.--23. 1. "DEVICE_CURRENT_MODE,Current mode status" newline bitfld.long 0x0 17. "SEC_DAP_ACT,Status of External Tool connected to Secondary DAP" "0: External Tool is not connected to Secondary DAP,1: External Tool is connected to Secondary DAP" newline bitfld.long 0x0 16. "MAIN_DAP_ACT,Status of External Tool connected to Main DAP" "0: External Tool is not connected to Main DAP,1: External Tool is connected to Main DAP" newline bitfld.long 0x0 12. "SELFTEST_DONE,Status of SelfTest completion." "0: SelfTest is not completed,1: SelfTest is completed" newline bitfld.long 0x0 9. "FUNC_RST_STATUS,Status of Functional reset (phase3) out form RGM_PER" "0: Reset is asserted,1: Reset is deasserted" newline bitfld.long 0x0 8. "DEST_RST_STATUS,Status of Destructive reset out form RGM_PER" "0: Reset is asserted,1: Reset is deasserted" newline bitfld.long 0x0 4.--6. "LIFE_CYCLE_STATE,Life Cycle Status" "0: FAIL_ANALYSIS,?,2: PROD_OEM,3: CUST_DELIV,?,?,?,7: IN_FIELD" newline bitfld.long 0x0 3. "HDE_PD0,Status of HDE signal after preserving it in STANDBY domain" "0: HSM debug is not enabled. HSM\qs Ctx-M4..,1: HSM debug is enabled. HSM\qs Ctx-M4.." newline bitfld.long 0x0 2. "MDE_PD0,Status of MDE signal after preserving it in STANDBY power domain" "0: Main debug is not enabled. Debug resources are..,1: Main debug is enabled. Debug resources are.." newline bitfld.long 0x0 1. "HDE,Status of HDE (HSM Debug Enable) signal from HSM" "0: HSM debug is not enabled,1: HSM debug is enabled" newline bitfld.long 0x0 0. "MDE,Status of MDE (Main Debug Enable) signal from HSM" "0: Main debug is not enabled,1: Main debug is enabled" group.long 0xC++0xB line.long 0x0 "LOWPOWER_CR,Low Power Control Register" bitfld.long 0x0 15. "STANDBY_STOP_EXIT_ACK,Standby or Stop mode exit acknowledge" "0: Standby or Stop mode exit is not acknowledged by..,1: Standby or Stop mode exit is acknowledged by the.." newline bitfld.long 0x0 14. "STANDBY_STOP_ENTRY_ACK,Standby or Stop mode entry acknowledge" "0: Standby or Stop mode entry is not acknowledged..,1: Standby or Stop mode entry is acknowledged by.." newline bitfld.long 0x0 13. "SMARTPOWER_EXIT_ACK,Smart Power mode exit acknowledge" "0: Smart power mode exit is not acknowledged by the..,1: Smart power mode exit is acknowledged by the.." newline bitfld.long 0x0 12. "SMARTPOWER_ENTRY_ACK,Smart Power mode entry acknowledge" "0: Smart power mode entry is not acknowledged by..,1: Smart power mode entry is acknowledged by the.." newline bitfld.long 0x0 10. "STANDBY_STOP_SYNC_EXIT,Standby or Stop mode exit request status" "0: Standby or Stop mode exit is not pending,1: Standby or Stop mode exit pending" newline bitfld.long 0x0 9. "STANDBY_STOP_SYNC_ENTRY,Standby or Stop mode entry request status" "0: Standby or Stop mode entry is not pending,1: Standby or Stop mode entry is pending" newline bitfld.long 0x0 8. "SMARTPOWER_SYNC_EXIT,Smart Power mode exit request status" "0: Smartpower mode exit is not pending,1: Smartpower mode exit is pending" newline bitfld.long 0x0 7. "SMARTPOWER_SYNC_ENTRY,Smart Power mode entry request status" "0: Smartpower mode entry is not pending,1: Smartpower mode entry is pending" newline bitfld.long 0x0 2. "SEC_WR_EN,Write enable to capture the value of security signals in Standby (PD0) domain" "0: Write operation to save the value of debug..,1: Save the value of debug authentication security.." newline bitfld.long 0x0 1. "LP_WR_EN,Write enable to capture the value of LP_DBG_EN bit in Standby (PD0) domain" "0: Write operation to save the LP_DBG_EN bit is..,1: Save the LP_DBG_EN bit value in StandBy(PD0).." newline bitfld.long 0x0 0. "LP_DBG_EN,Low Power Debug Enable" "0: Low power debug disabled,1: Low power debug enabled" line.long 0x4 "TND_CLKEN_CR,Trace n Debug Clocks Enable Register" bitfld.long 0x4 2. "CLOCK_EN2,Enable signal for clock mapped to it as shown in TnD configuration chapter." "0: Clock is not enabled,1: Clock is enabled" newline bitfld.long 0x4 1. "CLOCK_EN1,Enable signal for clock mapped to it as shown in TnD configuration chapter." "0: Clock is not enabled,1: Clock is enabled" newline bitfld.long 0x4 0. "CLOCK_EN0,Enable signal for clock mapped to it as shown in TnD configuration chapter." "0: Clock is not enabled,1: Clock is enabled" line.long 0x8 "TND_SWD_PAD_IMP_SEL,SWD PADs Impedance Selection Register" bitfld.long 0x8 6.--7. "DAP1_TDO_IMP_SEL,DAP1 TDO PAD impedance selection bits" "?,1: PAD programmed with 45 Ohm board impedance,2: PAD programmed with 50 Ohm board impedance,3: PAD programmed with 55 Ohm board impedance" newline bitfld.long 0x8 4.--5. "DAP1_TMS_IMP_SEL,DAP1 TMS PAD impedance selection bits" "?,1: PAD programmed with 45 Ohm board impedance,2: PAD programmed with 50 Ohm board impedance,3: PAD programmed with 55 Ohm board impedance" newline bitfld.long 0x8 2.--3. "DAP0_TDO_IMP_SEL,DAP0 TDO PAD impedance selection bits" "?,1: PAD programmed with 45 Ohm board impedance,2: PAD programmed with 50 Ohm board impedance,3: PAD programmed with 55 Ohm board impedance" newline bitfld.long 0x8 0.--1. "DAP0_TMS_IMP_SEL,DAP0 TMS PAD impedance selection bits" "?,1: PAD programmed with 45 Ohm board impedance,2: PAD programmed with 50 Ohm board impedance,3: PAD programmed with 55 Ohm board impedance" group.long 0x80++0x7 line.long 0x0 "PASSWORD_CONFIG,Password Configuration Register" hexmask.long.byte 0x0 0.--3. 1. "SLOT,Slot index is used by the security module to select the password." line.long 0x4 "PASSWORD_CTRL,Password Control Register" bitfld.long 0x4 1. "FINISHED,Externals tool should set this bit on completion of password writing in PASSWORD register." "0: Password writing is either progressing or not..,1: Password writing is finished." newline bitfld.long 0x4 0. "START_WRITE,Externals tool should set this bit before starting the password writing in PASSWORD register." "0: Password writing is not started,1: Password writing is started" wgroup.long 0x88++0x3 line.long 0x0 "PASSWORD_DATA,Password Register" hexmask.long 0x0 0.--31. 1. "PASSWORD_DATA,A part of Password written by external tool." group.long 0x100++0xF line.long 0x0 "MAINDAP_DATA_EXCHANGE_CTRL1,Main DAP Data Exchange Control 1 Register" bitfld.long 0x0 4. "DEBUGGER_READ,Externals tool should set DEBUGGER_READ bit after reading the MAINDAP_HOST_DATA register." "0: MAINDAP_HOST_DATA register is not read by the..,1: Set by the external tool after reading the.." newline bitfld.long 0x0 0. "DEBUGGER_WRITE,Externals tool should set DEBUGGER_WRITE bit after writing into MAINDAP_TOOL_DATA register." "0: MAINDAP_TOOL_DATA register is not written,1: Set by external tool when MAINDAP_TOOL_DATA.." line.long 0x4 "MAINDAP_DATA_EXCHANGE_CTRL2,Main DAP Data Exchange Control 2 Register" bitfld.long 0x4 4. "HOST_WRITE,Host should set HOST_WRITE bit after writing into MAINDAP_HOST_DATA register." "0: MAINDAP_HOST_DATA register is not written,1: Set by the Host when MAINDAP_HOST_DATA register.." newline bitfld.long 0x4 0. "HOST_READ,Host should set HOST_READ bit after reading the MAINDAP_TOOL_DATA register." "0: MAINDAP_TOOL_DATA register is not read by the..,1: Set by Host after reading the MAINDAP_TOOL_DATA.." line.long 0x8 "MAINDAP_TOOL_DATA,Main DAP Tool Data Exchange Register" hexmask.long 0x8 0.--31. 1. "TOOL_WRITE_HOST_READ,Data written by external tool." line.long 0xC "MAINDAP_HOST_DATA,Main DAP Host Data Exchange Register" hexmask.long 0xC 0.--31. 1. "HOST_WRITE_TOOL_READ,Data written by device host microcontroller." group.long 0x200++0xF line.long 0x0 "SECDAP_DATA_EXCHANGE_CTRL1,Secondary DAP Data Exchange Control 1 Register" bitfld.long 0x0 4. "DEBUGGER_READ,Externals tool should set DEBUGGER_READ bit after reading the SECDAP_HOST_DATA register." "0: SECDAP_HOST_DATA register is not read by the..,1: Set by the external tool after reading the.." newline bitfld.long 0x0 0. "DEBUGGER_WRITE,Externals tool should set DEBUGGER_WRITE bit after writing into SECDAP_TOOL_DATA register." "0: SECDAP_TOOL_DATA register is not written,1: Set by external tool when SECDAP_TOOL_DATA.." line.long 0x4 "SECDAP_DATA_EXCHANGE_CTRL2,Secondary DAP Data Exchange Control 2 Register" bitfld.long 0x4 4. "HOST_WRITE,Host should set HOST_WRITE bit after writing into SECDAP_HOST_DATA register." "0: SECDAP_HOST_DATA register is not written,1: Set by the Host when SECDAP_HOST_DATA register.." newline bitfld.long 0x4 0. "HOST_READ,Host should set HOST_READ bit after reading the SECDAP_TOOL_DATA register." "0: SECDAP_TOOL_DATA register is not read by the Host.,1: Set by Host after reading the SECDAP_TOOL_DATA.." line.long 0x8 "SECDAP_TOOL_DATA,Secondary DAP Tool Data Exchange Register" hexmask.long 0x8 0.--31. 1. "TOOL_WRITE_HOST_READ,Data written by external tool." line.long 0xC "SECDAP_HOST_DATA,Secondary DAP Host Data Exchange Register" hexmask.long 0xC 0.--31. 1. "HOST_WRITE_TOOL_READ,Data written by device host microcontroller." group.long 0x300++0x7 line.long 0x0 "MAINDAP_IDENT_DATA,Main DAP Identification Data Register" hexmask.long 0x0 0.--31. 1. "MAINDAP_DATA,Data written by Main DAP external tool." line.long 0x4 "SECDAP_IDENT_DATA,Secondary DAP Identification Data Register" hexmask.long 0x4 0.--31. 1. "SECDAP_DATA,Data written by Secondary DAP external tool." group.long 0x400++0x3 line.long 0x0 "INTR_EN,Interrupt Enable Register" bitfld.long 0x0 12. "SECDAP_DEBUGGER_READ_INTR_EN,Interrupt enable for SECONDARY DAP DEBUGGER READ bit" "0: Interrupt will not be occurred on setting the..,1: Interrupt will be occurred on setting the.." newline bitfld.long 0x0 8. "SECDAP_DEBUGGER_WRITE_INTR_EN,Interrupt enable on SECONDARY DAP DEBUGGER WRITE bit" "0: Interrupt will not be occurred on setting the..,1: Interrupt will be occurred on setting the.." newline bitfld.long 0x0 4. "MAINDAP_DEBUGGER_READ_INTR_EN,Interrupt enable for MAIN DAP DEBUGGER READ bit" "0: Interrupt will not be occurred on setting the..,1: Interrupt will be occurred on setting the.." newline bitfld.long 0x0 0. "MAINDAP_DEBUGGER_WRITE_INTR_EN,Interrupt enable on MAIN DAP DEBUGGER WRITE bit" "0: Interrupt will not be occurred on setting the..,1: Interrupt will be occurred on setting the.." rgroup.long 0x404++0x3 line.long 0x0 "INTR_STATUS,Interrupt Status Register" bitfld.long 0x0 12. "SECDAP_DEBUGGER_READ_INTR_STATUS,Interrupt status of DEBUGGER_READ bit of SECDAP_DATA_" "0: Interrupt is not occurred,1: Interrupt is occurred" newline bitfld.long 0x0 8. "SECDAP_DEBUGGER_WRITE_INTR_STATUS,Interrupt status of DEBUGGER_WRITE bit of SECDAP_DATA_" "0: Interrupt is not occurred,1: Interrupt is occurred" newline bitfld.long 0x0 4. "MAINDAP_DEBUGGER_READ_INTR_STATUS,Interrupt status of DEBUGGER_READ bit of MAINDAP_DATA_" "0: Interrupt is not occurred,1: Interrupt is occurred" newline bitfld.long 0x0 0. "MAINDAP_DEBUGGER_WRITE_INTR_STATUS,Interrupt status of DEBUGGER_WRITE bit of MAINDAP_DATA_" "0: Interrupt is not occurred,1: Interrupt is occurred" wgroup.long 0x408++0x3 line.long 0x0 "INTR_CLR,Interrupt Clear Register" bitfld.long 0x0 12. "SECDAP_DEBUGGER_READ_INTR_CLR,DEBUGGER_READ interrupt clear bit of SECDAP_DATA_EXCHANGE" "0: Interrupt will not be cleared,1: Interrupt will be cleared" newline bitfld.long 0x0 8. "SECDAP_DEBUGGER_WRITE_INTR_CLR,DEBUGGER_WRITE interrupt clear bit of SECDAP_DATA_EXCHANGE" "0: Interrupt will not be cleared,1: Interrupt will be cleared" newline bitfld.long 0x0 4. "MAINDAP_DEBUGGER_READ_INTR_CLR,DEBUGGER_READ interrupt clear bit of MAINDAP_DATA_EXCHANGE" "0: Interrupt will not be cleared,1: Interrupt will be cleared" newline bitfld.long 0x0 0. "MAINDAP_DEBUGGER_WRITE_INTR_CLR,DEBUGGER_WRITE interrupt clear bit of MAINDAP_DATA_EXCHANGE" "0: Interrupt will not be cleared,1: Interrupt will be cleared" group.long 0xFA0++0x7 line.long 0x0 "CLAIMSET,Claim Tag Set register" bitfld.long 0x0 3. "SET3,A bit programmable register bank that sets the claim tag value." "0: Has no effect.,1: Sets the bit" newline bitfld.long 0x0 2. "SET2,A bit programmable register bank that sets the claim tag value." "0: Has no effect.,1: Sets the bit" newline bitfld.long 0x0 1. "SET1,A bit programmable register bank that sets the claim tag value." "0: Has no effect.,1: Sets the bit" newline bitfld.long 0x0 0. "SET0,A bit programmable register bank that sets the claim tag value." "0: Has no effect.,1: Sets the bit" line.long 0x4 "CLAIMCLR,Claim Tag Clear register" bitfld.long 0x4 3. "CLR3,A bit-programmable register bank that clears the claim tag value." "0: Has no effect.,1: Clears the bit" newline bitfld.long 0x4 2. "CLR2,A bit-programmable register bank that clears the claim tag value." "0: Has no effect.,1: Clears the bit" newline bitfld.long 0x4 1. "CLR1,A bit-programmable register bank that clears the claim tag value." "0: Has no effect.,1: Clears the bit" newline bitfld.long 0x4 0. "CLR0,A bit-programmable register bank that clears the claim tag value." "0: Has no effect.,1: Clears the bit" rgroup.long 0xFB8++0x7 line.long 0x0 "AUTHSTATUS,Authentication status register" bitfld.long 0x0 10.--11. "HNID,Hypervisor non-invasive debug" "0: Functionality not implemented.,?,?,?" newline bitfld.long 0x0 8.--9. "HID,Hypervisor invasive debug" "0: Functionality not implemented.,?,?,?" newline bitfld.long 0x0 6.--7. "SNID,Secure non-invasive debug" "0: Functionality not implemented.,?,?,?" newline bitfld.long 0x0 4.--5. "SID,Secure invasive debug" "0: Functionality not implemented.,?,?,?" newline bitfld.long 0x0 2.--3. "NSNID,Non-secure non-invasive debug" "0: Functionality not implemented.,?,?,?" newline bitfld.long 0x0 0.--1. "NSID,Non-secure invasive debug" "0: Functionality not implemented.,?,?,?" line.long 0x4 "DEV_ARCH,Device architecture register" hexmask.long.word 0x4 21.--31. 1. "ARCHITECT,Define the Architect of the component" newline bitfld.long 0x4 20. "PRESENT,Presence" "?,1: Device Architecture register is present." newline hexmask.long.byte 0x4 16.--19. 1. "ARCHREVISION,Architecture revision" newline hexmask.long.word 0x4 0.--15. 1. "ARCHID,Architecture ID" rgroup.long 0xFC8++0x37 line.long 0x0 "DEV_ID,Device ID Register" line.long 0x4 "DEV_TYPE,Device Type Identifier Register" hexmask.long.byte 0x4 4.--7. 1. "SUB,Minor classification" newline hexmask.long.byte 0x4 0.--3. 1. "MAJOR,Major classification" line.long 0x8 "PID4,Peripheral ID4 register" hexmask.long.byte 0x8 4.--7. 1. "SIZE,Size" newline hexmask.long.byte 0x8 0.--3. 1. "DES_2,DES_2" line.long 0xC "PID5,Peripheral ID5 register" line.long 0x10 "PID6,Peripheral ID6 register" line.long 0x14 "PID7,Peripheral ID7 register" line.long 0x18 "PID0,Peripheral ID0 register" hexmask.long.byte 0x18 0.--7. 1. "PART_0,Part Number" line.long 0x1C "PID1,Peripheral ID1 register" hexmask.long.byte 0x1C 4.--7. 1. "DES_0,DES_0" newline hexmask.long.byte 0x1C 0.--3. 1. "PART_1,Part 1" line.long 0x20 "PID2,Peripheral ID2 register" hexmask.long.byte 0x20 4.--7. 1. "REVISION,Revision" newline bitfld.long 0x20 3. "JEDEC,JEDEC" "?,1: Indicates that a JEDEC assigned value is used." newline bitfld.long 0x20 0.--2. "DES_1,DES 1" "?,?,2: ST JEP106 identification code bit[6:4].,?,?,?,?,?" line.long 0x24 "PID3,Peripheral ID3 register" hexmask.long.byte 0x24 4.--7. 1. "REVAND,REVAND" newline hexmask.long.byte 0x24 0.--3. 1. "CMOD,CMOD" line.long 0x28 "CID0,Component Identification 0 Register" hexmask.long.byte 0x28 0.--7. 1. "PRMBL_0,Preamble 0" line.long 0x2C "CID1,Component Identification 1 Register" hexmask.long.byte 0x2C 4.--7. 1. "CLASS,Class" newline hexmask.long.byte 0x2C 0.--3. 1. "PRMBL_1,Preamble 1" line.long 0x30 "CID2,Component Identification 2 Register" hexmask.long.byte 0x30 0.--7. 1. "PRMBL_2,Preamble 2" line.long 0x34 "CID3,Component Identification 3 Register" hexmask.long.byte 0x34 0.--7. 1. "PRMBL_3,Preamble 3" tree.end tree "VMID (Virtual Machine Identifier)" base ad:0x0 tree "VMID_0" base ad:0x71000000 group.long 0x0++0x1F line.long 0x0 "VMID_REG_0_1,Virtual Machine ID wrapper 0.1 register" bitfld.long 0x0 24. "VMID_EN1,VMID_EN bit for bus master 1" "0: Reset values 0x00 will be propagated to VMID bus.,1: VMID_1 (VMID_0Plus1[7:0]) bits will be.." hexmask.long.byte 0x0 16.--23. 1. "VMID_1,VMID bits for bus master 1." newline bitfld.long 0x0 8. "VMID_EN0,VMID_EN bit for bus master 0" "0: Reset values 0x00 will be propagated to VMID bus.,1: VMID_0 bits will be propagated to VMID bus." hexmask.long.byte 0x0 0.--7. 1. "VMID_0,VMID bits for bus master 0." line.long 0x4 "VMID_REG_2_3,Virtual Machine ID wrapper 2.3 register" bitfld.long 0x4 24. "VMID_EN3,VMID_EN bit for bus master 3" "0: Reset values 0x00 will be propagated to VMID bus.,1: VMID_3(VMID_2Plus1[7:0]) bits will be propagated.." hexmask.long.byte 0x4 16.--23. 1. "VMID_3,VMID bits for bus master 3." newline bitfld.long 0x4 8. "VMID_EN2,VMID_EN bit for bus master 2" "0: Reset values 0x00 will be propagated to VMID bus.,1: VMID_2 bits will be propagated to VMID bus." hexmask.long.byte 0x4 0.--7. 1. "VMID_2,VMID bits for bus master 2." line.long 0x8 "VMID_REG_4_5,Virtual Machine ID wrapper 4.5 register" bitfld.long 0x8 24. "VMID_EN5,VMID_EN bit for bus master 5" "0: Reset values 0x00 will be propagated to VMID bus.,1: VMID_5 (VMID_4Plus1[7:0]) bits will be.." hexmask.long.byte 0x8 16.--23. 1. "VMID_5,VMID bits for bus master 5." newline bitfld.long 0x8 8. "VMID_EN4,VMID_EN bit for bus master 4" "0: Reset values 0x00 will be propagated to VMID bus.,1: VMID_4 bits will be propagated to VMID bus." hexmask.long.byte 0x8 0.--7. 1. "VMID_4,VMID bits for bus master 4." line.long 0xC "VMID_REG_6_7,Virtual Machine ID wrapper 6.7 register" bitfld.long 0xC 24. "VMID_EN7,VMID_EN bit for bus master 7" "0: Reset values 0x00 will be propagated to VMID bus.,1: VMID_7 (VMID_6Plus1[7:0]) bits will be.." hexmask.long.byte 0xC 16.--23. 1. "VMID_7,VMID bits for bus master 7." newline bitfld.long 0xC 8. "VMID_EN6,VMID_EN bit for bus master 6" "0: Reset values 0x00 will be propagated to VMID bus.,1: VMID_6 bits will be propagated to VMID bus." hexmask.long.byte 0xC 0.--7. 1. "VMID_6,VMID bits for bus master 6." line.long 0x10 "VMID_REG_8_9,Virtual Machine ID wrapper 8.9 register" bitfld.long 0x10 24. "VMID_EN9,VMID_EN bit for bus master 9" "0: Reset values 0x00 will be propagated to VMID bus.,1: VMID_9 (VMID_8Plus1[7:0]) bits will be.." hexmask.long.byte 0x10 16.--23. 1. "VMID_9,VMID bits for bus master 9." newline bitfld.long 0x10 8. "VMID_EN8,VMID_EN bit for bus master 8" "0: Reset values 0x00 will be propagated to VMID bus.,1: VMID_8 bits will be propagated to VMID bus." hexmask.long.byte 0x10 0.--7. 1. "VMID_8,VMID bits for bus master 8." line.long 0x14 "VMID_REG_10_11,Virtual Machine ID wrapper 10.11 register" bitfld.long 0x14 24. "VMID_EN11,VMID_EN bit for bus master 11" "0: Reset values 0x00 will be propagated to VMID bus.,1: VMID_11 (VMID_10Plus1[7:0]) bits will be.." hexmask.long.byte 0x14 16.--23. 1. "VMID_11,VMID bits for bus master 11." newline bitfld.long 0x14 8. "VMID_EN10,VMID_EN bit for bus master 10" "0: Reset values 0x00 will be propagated to VMID bus.,1: VMID_10 bits will be propagated to VMID bus." hexmask.long.byte 0x14 0.--7. 1. "VMID_10,VMID bits for bus master 10." line.long 0x18 "VMID_REG_12_13,Virtual Machine ID wrapper 12.13 register" bitfld.long 0x18 24. "VMID_EN13,VMID_EN bit for bus master 13" "0: Reset values 0x00 will be propagated to VMID bus.,1: VMID_13 (VMID_12Plus1[7:0]) bits will be.." hexmask.long.byte 0x18 16.--23. 1. "VMID_13,VMID bits for bus master 13." newline bitfld.long 0x18 8. "VMID_EN12,VMID_EN bit for bus master 12" "0: Reset values 0x00 will be propagated to VMID bus.,1: VMID_12 bits will be propagated to VMID bus." hexmask.long.byte 0x18 0.--7. 1. "VMID_12,VMID bits for bus master 12." line.long 0x1C "VMID_REG_14_15,Virtual Machine ID wrapper 14.15 register" bitfld.long 0x1C 8. "VMID_EN14,VMID_EN bit for bus master 14" "0: Reset values 0x00 will be propagated to VMID bus.,1: VMID_14 bits will be propagated to VMID bus." hexmask.long.byte 0x1C 0.--7. 1. "VMID_14,VMID bits for bus master 14." tree.end tree.end tree "WKPU (Wakeup Unit)" base ad:0x0 tree "WKPU_0" base ad:0x72348000 group.long 0x0++0x3 line.long 0x0 "NSR,NMI Status Flag Register" bitfld.long 0x0 31. "NIF0,NMI Status Flag 0" "0: No event has occurred on the pad.,1: An event as defined by NREE0 and NFEE0 has.." bitfld.long 0x0 30. "NOVF0,NMI Overrun Status Flag 0" "0: No overrun has occurred on NMI input 0.,1: An overrun has occurred on NMI input 0." newline bitfld.long 0x0 23. "NIF1,NMI Status Flag 1" "0: No event has occurred on the pad.,1: An event as defined by NREE1 and NFEE1 has.." bitfld.long 0x0 22. "NOVF1,NMI Overrun Status Flag 1" "0: No overrun has occurred on NMI input 1.,1: An overrun has occurred on NMI input 1." group.long 0x8++0x3 line.long 0x0 "NCR,NMI Configuration Register" bitfld.long 0x0 31. "NLOCK0,NMI Configuration Lock Register 0" "0,1" bitfld.long 0x0 29.--30. "NDSS0,NMI Destination Source Select 0" "0: Non-maskable interrupt,1: Writing this value has no effect,2: Writing this value has no effect,3: Reserved - No NMI critical interrupt or machine.." newline bitfld.long 0x0 28. "NWRE0,NMI Wakeup Request Enable 0" "0: NMI0 wakeup is disabled. System wakeup requests..,1: NMI0 wakeup is enabled. A set NIF0 bit or set.." bitfld.long 0x0 26. "NREE0,NMI Rising-edge Events Enable 0" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 25. "NFEE0,NMI Falling-edge Events Enable 0" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x0 24. "NFE0,NMI Filter Enable 0" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x0 23. "NLOCK1,NMI Configuration Lock Register 1" "0,1" bitfld.long 0x0 21.--22. "NDSS1,NMI Destination Source Select 1" "0: Non-maskable interrupt,1: Writing this value has no effect,2: Writing this value has no effect,3: Reserved - No NMI critical interrupt or machine.." newline bitfld.long 0x0 20. "NWRE1,NMI Wakeup Request Enable 1" "0: NMI1 wakeup is disabled. System wakeup requests..,1: NMI1 wakeup is enabled. A set NIF1 bit or set.." bitfld.long 0x0 18. "NREE1,NMI Rising-edge Events Enable 1" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 17. "NFEE1,NMI Falling-edge Events Enable 1" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x0 16. "NFE1,NMI Filter Enable 1" "0: Filter is disabled.,1: Filter is enabled." group.long 0x14++0xB line.long 0x0 "WISR,Wakeup/Interrupt Status Flag Register" bitfld.long 0x0 31. "EIF31,External Wakeup/Interrupt Status Flag 31" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 30. "EIF30,External Wakeup/Interrupt Status Flag 30" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 29. "EIF29,External Wakeup/Interrupt Status Flag 29" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 28. "EIF28,External Wakeup/Interrupt Status Flag 28" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 27. "EIF27,External Wakeup/Interrupt Status Flag 27" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 26. "EIF26,External Wakeup/Interrupt Status Flag 26" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 25. "EIF25,External Wakeup/Interrupt Status Flag 25" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 24. "EIF24,External Wakeup/Interrupt Status Flag 24" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 23. "EIF23,External Wakeup/Interrupt Status Flag 23" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 22. "EIF22,External Wakeup/Interrupt Status Flag 22" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 21. "EIF21,External Wakeup/Interrupt Status Flag 21" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 20. "EIF20,External Wakeup/Interrupt Status Flag 20" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 19. "EIF19,External Wakeup/Interrupt Status Flag 19" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 18. "EIF18,External Wakeup/Interrupt Status Flag 18" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 17. "EIF17,External Wakeup/Interrupt Status Flag 17" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 16. "EIF16,External Wakeup/Interrupt Status Flag 16" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 15. "EIF15,External Wakeup/Interrupt Status Flag 15" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 14. "EIF14,External Wakeup/Interrupt Status Flag 14" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 13. "EIF13,External Wakeup/Interrupt Status Flag 13" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 12. "EIF12,External Wakeup/Interrupt Status Flag 12" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 11. "EIF11,External Wakeup/Interrupt Status Flag 11" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 10. "EIF10,External Wakeup/Interrupt Status Flag 10" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 9. "EIF9,External Wakeup/Interrupt Status Flag 9" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 8. "EIF8,External Wakeup/Interrupt Status Flag 8" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 7. "EIF7,External Wakeup/Interrupt Status Flag 7" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 6. "EIF6,External Wakeup/Interrupt Status Flag 6" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 5. "EIF5,External Wakeup/Interrupt Status Flag 5" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 4. "EIF4,External Wakeup/Interrupt Status Flag 4" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 3. "EIF3,External Wakeup/Interrupt Status Flag 3" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 2. "EIF2,External Wakeup/Interrupt Status Flag 2" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 1. "EIF1,External Wakeup/Interrupt Status Flag 1" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 0. "EIF0,External Wakeup/Interrupt Status Flag 0" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." line.long 0x4 "IRER,Interrupt Request Enable Register" bitfld.long 0x4 31. "EIRE31,External Interrupt Request Enable 31" "0: Interrupt requests from the corresponding EIF31..,1: A set EIF31 bit causes an interrupt request." bitfld.long 0x4 30. "EIRE30,External Interrupt Request Enable 30" "0: Interrupt requests from the corresponding EIF30..,1: A set EIF30 bit causes an interrupt request." newline bitfld.long 0x4 29. "EIRE29,External Interrupt Request Enable 29" "0: Interrupt requests from the corresponding EIF29..,1: A set EIF29 bit causes an interrupt request." bitfld.long 0x4 28. "EIRE28,External Interrupt Request Enable 28" "0: Interrupt requests from the corresponding EIF28..,1: A set EIF28bit causes an interrupt request." newline bitfld.long 0x4 27. "EIRE27,External Interrupt Request Enable 27" "0: Interrupt requests from the corresponding EIF27..,1: A set EIF27 bit causes an interrupt request." bitfld.long 0x4 26. "EIRE26,External Interrupt Request Enable 26" "0: Interrupt requests from the corresponding EIF26..,1: A set EIF26 bit causes an interrupt request." newline bitfld.long 0x4 25. "EIRE25,External Interrupt Request Enable 25" "0: Interrupt requests from the corresponding EIF25..,1: A set EIF25 bit causes an interrupt request." bitfld.long 0x4 24. "EIRE24,External Interrupt Request Enable 24" "0: Interrupt requests from the corresponding EIF24..,1: A set EIF24 bit causes an interrupt request." newline bitfld.long 0x4 23. "EIRE23,External Interrupt Request Enable 23" "0: Interrupt requests from the corresponding EIF23..,1: A set EIF23 bit causes an interrupt request." bitfld.long 0x4 22. "EIRE22,External Interrupt Request Enable 22" "0: Interrupt requests from the corresponding EIF22..,1: A set EIF22bit causes an interrupt request." newline bitfld.long 0x4 21. "EIRE21,External Interrupt Request Enable 21" "0: Interrupt requests from the corresponding EIF21..,1: A set EIF21 bit causes an interrupt request." bitfld.long 0x4 20. "EIRE20,External Interrupt Request Enable 20" "0: Interrupt requests from the corresponding EIF20..,1: A set EIF20 bit causes an interrupt request." newline bitfld.long 0x4 19. "EIRE19,External Interrupt Request Enable 19" "0: Interrupt requests from the corresponding EIF19..,1: A set EIF19 bit causes an interrupt request." bitfld.long 0x4 18. "EIRE18,External Interrupt Request Enable 18" "0: Interrupt requests from the corresponding EIF18..,1: A set EIF18 bit causes an interrupt request." newline bitfld.long 0x4 17. "EIRE17,External Interrupt Request Enable 17" "0: Interrupt requests from the corresponding EIF17..,1: A set EIF17bit causes an interrupt request." bitfld.long 0x4 16. "EIRE16,External Interrupt Request Enable 16" "0: Interrupt requests from the corresponding EIF16..,1: A set EIF16 bit causes an interrupt request." newline bitfld.long 0x4 15. "EIRE15,External Interrupt Request Enable 15" "0: Interrupt requests from the corresponding EIF15..,1: A set EIF15 bit causes an interrupt request." bitfld.long 0x4 14. "EIRE14,External Interrupt Request Enable 14" "0: Interrupt requests from the corresponding EIF14..,1: A set EIF14 bit causes an interrupt request." newline bitfld.long 0x4 13. "EIRE13,External Interrupt Request Enable 13" "0: Interrupt requests from the corresponding EIF13..,1: A set EIF13 bit causes an interrupt request." bitfld.long 0x4 12. "EIRE12,External Interrupt Request Enable 12" "0: Interrupt requests from the corresponding EIF12..,1: A set EIF12 bit causes an interrupt request." newline bitfld.long 0x4 11. "EIRE11,External Interrupt Request Enable 11" "0: Interrupt requests from the corresponding EIF11..,1: A set EIF11 bit causes an interrupt request." bitfld.long 0x4 10. "EIRE10,External Interrupt Request Enable 10" "0: Interrupt requests from the corresponding EIF10..,1: A set EIF10 bit causes an interrupt request." newline bitfld.long 0x4 9. "EIRE9,External Interrupt Request Enable 9" "0: Interrupt requests from the corresponding EIF9..,1: A set EIF9 bit causes an interrupt request." bitfld.long 0x4 8. "EIRE8,External Interrupt Request Enable 8" "0: Interrupt requests from the corresponding EIF8..,1: A set EIF8 bit causes an interrupt request." newline bitfld.long 0x4 7. "EIRE7,External Interrupt Request Enable 7" "0: Interrupt requests from the corresponding EIF7..,1: A set EIF7 bit causes an interrupt request." bitfld.long 0x4 6. "EIRE6,External Interrupt Request Enable 6" "0: Interrupt requests from the corresponding EIF6..,1: A set EIF6 bit causes an interrupt request." newline bitfld.long 0x4 5. "EIRE5,External Interrupt Request Enable 5" "0: Interrupt requests from the corresponding EIF5..,1: A set EIF5 bit causes an interrupt request." bitfld.long 0x4 4. "EIRE4,External Interrupt Request Enable 4" "0: Interrupt requests from the corresponding EIF4..,1: A set EIF4 bit causes an interrupt request." newline bitfld.long 0x4 3. "EIRE3,External Interrupt Request Enable 3" "0: Interrupt requests from the corresponding EIF3..,1: A set EIF3 bit causes an interrupt request." bitfld.long 0x4 2. "EIRE2,External Interrupt Request Enable 2" "0: Interrupt requests from the corresponding EIF2..,1: A set EIF2 bit causes an interrupt request." newline bitfld.long 0x4 1. "EIRE1,External Interrupt Request Enable 1" "0: Interrupt requests from the corresponding EIF1..,1: A set EIF1 bit causes an interrupt request." bitfld.long 0x4 0. "EIRE0,External Interrupt Request Enable 0" "0: Interrupt requests from the corresponding EIF0..,1: A set EIF0 bit causes an interrupt request." line.long 0x8 "WRER,Wakeup Request Enable Register" bitfld.long 0x8 31. "WRE31,External Wakeup Request Enable 31" "0: System wakeup requests from the corresponding..,1: A set EIF31 bit causes a system wakeup request." bitfld.long 0x8 30. "WRE30,External Wakeup Request Enable 30" "0: System wakeup requests from the corresponding..,1: A set EIF30 bit causes a system wakeup request." newline bitfld.long 0x8 29. "WRE29,External Wakeup Request Enable 29" "0: System wakeup requests from the corresponding..,1: A set EIF29 bit causes a system wakeup request." bitfld.long 0x8 28. "WRE28,External Wakeup Request Enable 28" "0: System wakeup requests from the corresponding..,1: A set EIF28 bit causes a system wakeup request." newline bitfld.long 0x8 27. "WRE27,External Wakeup Request Enable 27" "0: System wakeup requests from the corresponding..,1: A set EIF27 bit causes a system wakeup request." bitfld.long 0x8 26. "WRE26,External Wakeup request.Enable 26" "0: System wakeup requests from the corresponding..,1: A set EIF26 bit causes a system wakeup request" newline bitfld.long 0x8 25. "WRE25,External Wakeup request.Enable 25" "0: System wakeup requests from the corresponding..,1: A set EIF25 bit causes a system wakeup request" bitfld.long 0x8 24. "WRE24,External Wakeup request.Enable 24" "0: System wakeup requests from the corresponding..,1: A set EIF24 bit causes a system wakeup request" newline bitfld.long 0x8 23. "WRE23,External Wakeup request.Enable 23" "0: System wakeup requests from the corresponding..,1: A set EIF23 bit causes a system wakeup request" bitfld.long 0x8 22. "WRE22,External Wakeup Request Enable 22" "0: System wakeup requests from the corresponding..,1: A set EIF22 bit causes a system wakeup request." newline bitfld.long 0x8 21. "WRE21,External Wakeup Request Enable 21" "0: System wakeup requests from the corresponding..,1: A set EIF21 bit causes a system wakeup request." bitfld.long 0x8 20. "WRE20,External Wakeup Request Enable 20" "0: System wakeup requests from the corresponding..,1: A set EIF20 bit causes a system wakeup request." newline bitfld.long 0x8 19. "WRE19,External Wakeup Request Enable 19" "0: System wakeup requests from the corresponding..,1: A set EIF19 bit causes a system wakeup request." bitfld.long 0x8 18. "WRE18,External Wakeup Request Enable 18" "0: System wakeup requests from the corresponding..,1: A set EIF18 bit causes a system wakeup request." newline bitfld.long 0x8 17. "WRE17,External Wakeup request.Enable 17" "0: System wakeup requests from the corresponding..,1: A set EIF17 bit causes a system wakeup request" bitfld.long 0x8 16. "WRE16,External Wakeup request.Enable 16" "0: System wakeup requests from the corresponding..,1: A set EIF16 bit causes a system wakeup request" newline bitfld.long 0x8 15. "WRE15,External Wakeup request.Enable 15" "0: System wakeup requests from the corresponding..,1: A set EIF15 bit causes a system wakeup request" bitfld.long 0x8 14. "WRE14,External Wakeup request.Enable 14" "0: System wakeup requests from the corresponding..,1: A set EIF14 bit causes a system wakeup request" newline bitfld.long 0x8 13. "WRE13,External Wakeup request.Enable 13" "0: System wakeup requests from the corresponding..,1: A set EIF13 bit causes a system wakeup request" bitfld.long 0x8 12. "WRE12,External Wakeup request.Enable 12" "0: System wakeup requests from the corresponding..,1: A set EIF12 bit causes a system wakeup request" newline bitfld.long 0x8 11. "WRE11,External Wakeup request.Enable 11" "0: System wakeup requests from the corresponding..,1: A set EIF11 bit causes a system wakeup request" bitfld.long 0x8 10. "WRE10,External Wakeup request.Enable 10" "0: System wakeup requests from the corresponding..,1: A set EIF10 bit causes a system wakeup request" newline bitfld.long 0x8 9. "WRE9,External Wakeup request.Enable 9" "0: System wakeup requests from the corresponding..,1: A set EIF9 bit causes a system wakeup request" bitfld.long 0x8 8. "WRE8,External Wakeup request.Enable 8." "0: System wakeup requests from the corresponding..,1: A set EIF8 bit causes a system wakeup request" newline bitfld.long 0x8 7. "WRE7,External Wakeup Request Enable 7" "0: System wakeup requests from the corresponding..,1: A set EIF7 bit causes a system wakeup request." bitfld.long 0x8 6. "WRE6,External Wakeup Request Enable 6" "0: System wakeup requests from the corresponding..,1: A set EIF6 bit causes a system wakeup request." newline bitfld.long 0x8 5. "WRE5,External Wakeup Request Enable 5" "0: System wakeup requests from the corresponding..,1: A set EIF5 bit causes a system wakeup request." bitfld.long 0x8 4. "WRE4,External Wakeup Request Enable 4" "0: System wakeup requests from the corresponding..,1: A set EIF4 bit causes a system wakeup request." newline bitfld.long 0x8 3. "WRE3,External Wakeup Request Enable 3" "0: System wakeup requests from the corresponding..,1: A set EIF3 bit causes a system wakeup request." bitfld.long 0x8 2. "WRE2,External Wakeup Request Enable 2" "0: System wakeup requests from the corresponding..,1: A set EIF2 bit causes a system wakeup request." newline bitfld.long 0x8 1. "WRE1,External Wakeup Request Enable 1" "0: System wakeup requests from the corresponding..,1: A set EIF1 bit causes a system wakeup request." bitfld.long 0x8 0. "WRE0,External Wakeup Request Enable 0" "0: System wakeup requests from the corresponding..,1: A set EIF0 bit causes a system wakeup request" group.long 0x28++0xF line.long 0x0 "WIREER,Wakeup/Interrupt Rising-Edge Event Enable Register" bitfld.long 0x0 31. "IREE31,External Interrupt Rising-edge Events Enable 31" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 30. "IREE30,External Interrupt Rising-edge Events Enable 30" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 29. "IREE29,External Interrupt Rising-edge Events Enable 29" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 28. "IREE28,External Interrupt Rising-edge Events Enable 28" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 27. "IREE27,External Interrupt Rising-edge Events Enable 27" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 26. "IREE26,External Interrupt Rising-edge Events Enable 26" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 25. "IREE25,External Interrupt Rising-edge Events Enable 25" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 24. "IREE24,External Interrupt Rising-edge Events Enable 24" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 23. "IREE23,External Interrupt Rising-edge Events Enable 23" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 22. "IREE22,External Interrupt Rising-edge Events Enable 22" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 21. "IREE21,External Interrupt Rising-edge Events Enable 21" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 20. "IREE20,External Interrupt Rising-edge Events Enable 20" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 19. "IREE19,External Interrupt Rising-edge Events Enable 19" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 18. "IREE18,External Interrupt Rising-edge Events Enable 18" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 17. "IREE17,External Interrupt Rising-edge Events Enable 17" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 16. "IREE16,External Interrupt Rising-edge Events Enable 16" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 15. "IREE15,External Interrupt Rising-edge Events Enable 15" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 14. "IREE14,External Interrupt Rising-edge Events Enable 14" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 13. "IREE13,External Interrupt Rising-edge Events Enable 13" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 12. "IREE12,External Interrupt Rising-edge Events Enable 12" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 11. "IREE11,External Interrupt Rising-edge Events Enable 11" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 10. "IREE10,External Interrupt Rising-edge Events Enable 10" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 9. "IREE9,External Interrupt Rising-edge Events Enable 9" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 8. "IREE8,External Interrupt Rising-edge Events Enable 8" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 7. "IREE7,External Interrupt Rising-edge Events Enable 7" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 6. "IREE6,External Interrupt Rising-edge Events Enable 6" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 5. "IREE5,External Interrupt Rising-edge Events Enable 5" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 4. "IREE4,External Interrupt Rising-edge Events Enable 4" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 3. "IREE3,External Interrupt Rising-edge Events Enable 3" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 2. "IREE2,External Interrupt Rising-edge Events Enable 2" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 1. "IREE1,External Interrupt Rising-edge Events Enable 1" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 0. "IREE0,External Interrupt Rising-edge Events Enable 0" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." line.long 0x4 "WIFEER,Wakeup/Interrupt Falling-Edge Event Enable Register" bitfld.long 0x4 31. "IFEE31,External Interrupt Falling-edge Events Enable 31" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 30. "IFEE30,External Interrupt Falling-edge Events Enable 30" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 29. "IFEE29,External Interrupt Falling-edge Events Enable 29" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 28. "IFEE28,External Interrupt Falling-edge Events Enable 28" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 27. "IFEE27,External Interrupt Falling-edge Events Enable 27" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 26. "IFEE26,External Interrupt Falling-edge Events Enable 26" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 25. "IFEE25,External Interrupt Falling-edge Events Enable 25" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 24. "IFEE24,External Interrupt Falling-edge Events Enable 24" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 23. "IFEE23,External Interrupt Falling-edge Events Enable 23" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 22. "IFEE22,External Interrupt Falling-edge Events Enable 22" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 21. "IFEE21,External Interrupt Falling-edge Events Enable 21" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 20. "IFEE20,External Interrupt Falling-edge Events Enable 20" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 19. "IFEE19,External Interrupt Falling-edge Events Enable 19" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 18. "IFEE18,External Interrupt Falling-edge Events Enable 18" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 17. "IFEE17,External Interrupt Falling-edge Events Enable 17" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 16. "IFEE16,External Interrupt Falling-edge Events Enable 16" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 15. "IFEE15,External Interrupt Falling-edge Events Enable 15" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 14. "IFEE14,External Interrupt Falling-edge Events Enable 14" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 13. "IFEE13,External Interrupt Falling-edge Events Enable 13" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 12. "IFEE12,External Interrupt Falling-edge Events Enable 12" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 11. "IFEE11,External Interrupt Falling-edge Events Enable 11" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 10. "IFEE10,External Interrupt Falling-edge Events Enable 10" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 9. "IFEE9,External Interrupt Falling-edge Events Enable 9" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 8. "IFEE8,External Interrupt Falling-edge Events Enable 8" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 7. "IFEE7,External Interrupt Falling-edge Events Enable 7" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 6. "IFEE6,External Interrupt Falling-edge Events Enable 6" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 5. "IFEE5,External Interrupt Falling-edge Events Enable 5" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 4. "IFEE4,External Interrupt Falling-edge Events Enable 4" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 3. "IFEE3,External Interrupt Falling-edge Events Enable 3" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 2. "IFEE2,External Interrupt Falling-edge Events Enable 2" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 1. "IFEE1,External Interrupt Falling-edge Events Enable 1" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 0. "IFEE0,External Interrupt Falling-edge Events Enable 0" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." line.long 0x8 "WIFER,Wakeup/Interrupt Filter Enable Register" bitfld.long 0x8 31. "IFE31,External Interrupt Filter Enable 31" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 30. "IFE30,External Interrupt Filter Enable 30" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 29. "IFE29,External Interrupt Filter Enable 29" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 28. "IFE28,External Interrupt Filter Enable 28" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 27. "IFE27,External Interrupt Filter Enable 27" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 26. "IFE26,External Interrupt Filter Enable 26" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 25. "IFE25,External Interrupt Filter Enable 25" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 24. "IFE24,External Interrupt Filter Enable 24" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 23. "IFE23,External Interrupt Filter Enable 23" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 22. "IFE22,External Interrupt Filter Enable 22" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 21. "IFE21,External Interrupt Filter Enable 21" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 20. "IFE20,External Interrupt Filter Enable 20" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 19. "IFE19,External Interrupt Filter Enable 19" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 18. "IFE18,External Interrupt Filter Enable 18" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 17. "IFE17,External Interrupt Filter Enable 17" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 16. "IFE16,External Interrupt Filter Enable 16" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 15. "IFE15,External Interrupt Filter Enable 15" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 14. "IFE14,External Interrupt Filter Enable 14" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 13. "IFE13,External Interrupt Filter Enable 13" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 12. "IFE12,External Interrupt Filter Enable 12" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 11. "IFE11,External Interrupt Filter Enable 11" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 10. "IFE10,External Interrupt Filter Enable 10" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 9. "IFE9,External Interrupt Filter Enable 9" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 8. "IFE8,External Interrupt Filter Enable 8" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 7. "IFE7,External Interrupt Filter Enable 7" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 6. "IFE6,External Interrupt Filter Enable 6" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 5. "IFE5,External Interrupt Filter Enable 5" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 4. "IFE4,External Interrupt Filter Enable 4" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 3. "IFE3,External Interrupt Filter Enable 3" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 2. "IFE2,External Interrupt Filter Enable 2" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 1. "IFE1,External Interrupt Filter Enable 1" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 0. "IFE0,External Interrupt Filter Enable 0" "0: Filter is disabled.,1: Filter is enabled." line.long 0xC "WIPUER,Wakeup/Interrupt Pull Enable Register" bitfld.long 0xC 31. "IPUE31,External Interrupt Pull Enable 31" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 30. "IPUE30,External Interrupt Pull Enable 30" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 29. "IPUE29,External Interrupt Pull Enable 29" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 28. "IPUE28,External Interrupt Pull Enable 28" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 27. "IPUE27,External Interrupt Pull Enable 27" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 26. "IPUE26,External Interrupt Pull Enable 26" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 25. "IPUE25,External Interrupt Pull Enable 25" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 24. "IPUE24,External Interrupt Pull Enable 24" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 23. "IPUE23,External Interrupt Pull Enable 23" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 22. "IPUE22,External Interrupt Pull Enable 22" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 21. "IPUE21,External Interrupt Pull Enable 21" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 20. "IPUE20,External Interrupt Pull Enable 20" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 19. "IPUE19,External Interrupt Pull Enable 19" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 18. "IPUE18,External Interrupt Pull Enable 18" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 17. "IPUE17,External Interrupt Pull Enable 17" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 16. "IPUE16,External Interrupt Pull Enable 16" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 15. "IPUE15,External Interrupt Pull Enable 15" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 14. "IPUE14,External Interrupt Pull Enable 14" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 13. "IPUE13,External Interrupt Pull Enable 13" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 12. "IPUE12,External Interrupt Pull Enable 12" "0: Pull is disabled.disabled.,1: Pull is enabled." newline bitfld.long 0xC 11. "IPUE11,External Interrupt Pull Enable 11" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 10. "IPUE10,External Interrupt Pull Enable 10" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 9. "IPUE9,External Interrupt Pull Enable 9" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 8. "IPUE8,External Interrupt Pull Enable 8" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 7. "IPUE7,External Interrupt Pull Enable 7" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 6. "IPUE6,External Interrupt Pull Enable 6" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 5. "IPUE5,External Interrupt Pull Enable 5" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 4. "IPUE4,External Interrupt Pull Enable 4" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 3. "IPUE3,External Interrupt Pull Enable 3" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 2. "IPUE2,External Interrupt Pull Enable 2" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 1. "IPUE1,External Interrupt Pull Enable 1" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 0. "IPUE0,External Interrupt Pull Enable 0" "0: Pull is disabled.,1: Pull is enabled." tree.end tree "WKPU_1" base ad:0x7234C000 group.long 0x14++0xB line.long 0x0 "WISR,Wakeup/Interrupt Status Flag Register" bitfld.long 0x0 31. "EIF31,External Wakeup/Interrupt Status Flag 31" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 30. "EIF30,External Wakeup/Interrupt Status Flag 30" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 29. "EIF29,External Wakeup/Interrupt Status Flag 29" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 28. "EIF28,External Wakeup/Interrupt Status Flag 28" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 27. "EIF27,External Wakeup/Interrupt Status Flag 27" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 26. "EIF26,External Wakeup/Interrupt Status Flag 26" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 25. "EIF25,External Wakeup/Interrupt Status Flag 25" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 24. "EIF24,External Wakeup/Interrupt Status Flag 24" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 23. "EIF23,External Wakeup/Interrupt Status Flag 23" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 22. "EIF22,External Wakeup/Interrupt Status Flag 22" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 21. "EIF21,External Wakeup/Interrupt Status Flag 21" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 20. "EIF20,External Wakeup/Interrupt Status Flag 20" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 19. "EIF19,External Wakeup/Interrupt Status Flag 19" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 18. "EIF18,External Wakeup/Interrupt Status Flag 18" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 17. "EIF17,External Wakeup/Interrupt Status Flag 17" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 16. "EIF16,External Wakeup/Interrupt Status Flag 16" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 15. "EIF15,External Wakeup/Interrupt Status Flag 15" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 14. "EIF14,External Wakeup/Interrupt Status Flag 14" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 13. "EIF13,External Wakeup/Interrupt Status Flag 13" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 12. "EIF12,External Wakeup/Interrupt Status Flag 12" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 11. "EIF11,External Wakeup/Interrupt Status Flag 11" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 10. "EIF10,External Wakeup/Interrupt Status Flag 10" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 9. "EIF9,External Wakeup/Interrupt Status Flag 9" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 8. "EIF8,External Wakeup/Interrupt Status Flag 8" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 7. "EIF7,External Wakeup/Interrupt Status Flag 7" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 6. "EIF6,External Wakeup/Interrupt Status Flag 6" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 5. "EIF5,External Wakeup/Interrupt Status Flag 5" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 4. "EIF4,External Wakeup/Interrupt Status Flag 4" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 3. "EIF3,External Wakeup/Interrupt Status Flag 3" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 2. "EIF2,External Wakeup/Interrupt Status Flag 2" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." newline bitfld.long 0x0 1. "EIF1,External Wakeup/Interrupt Status Flag 1" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." bitfld.long 0x0 0. "EIF0,External Wakeup/Interrupt Status Flag 0" "0: No event has occurred on the pad.,1: An event as defined by WIREER and WIFEER has.." line.long 0x4 "IRER,Interrupt Request Enable Register" bitfld.long 0x4 31. "EIRE31,External Interrupt Request Enable 31" "0: Interrupt requests from the corresponding EIF31..,1: A set EIF31 bit causes an interrupt request." bitfld.long 0x4 30. "EIRE30,External Interrupt Request Enable 30" "0: Interrupt requests from the corresponding EIF30..,1: A set EIF30 bit causes an interrupt request." newline bitfld.long 0x4 29. "EIRE29,External Interrupt Request Enable 29" "0: Interrupt requests from the corresponding EIF29..,1: A set EIF29 bit causes an interrupt request." bitfld.long 0x4 28. "EIRE28,External Interrupt Request Enable 28" "0: Interrupt requests from the corresponding EIF28..,1: A set EIF28bit causes an interrupt request." newline bitfld.long 0x4 27. "EIRE27,External Interrupt Request Enable 27" "0: Interrupt requests from the corresponding EIF27..,1: A set EIF27 bit causes an interrupt request." bitfld.long 0x4 26. "EIRE26,External Interrupt Request Enable 26" "0: Interrupt requests from the corresponding EIF26..,1: A set EIF26 bit causes an interrupt request." newline bitfld.long 0x4 25. "EIRE25,External Interrupt Request Enable 25" "0: Interrupt requests from the corresponding EIF25..,1: A set EIF25 bit causes an interrupt request." bitfld.long 0x4 24. "EIRE24,External Interrupt Request Enable 24" "0: Interrupt requests from the corresponding EIF24..,1: A set EIF24 bit causes an interrupt request." newline bitfld.long 0x4 23. "EIRE23,External Interrupt Request Enable 23" "0: Interrupt requests from the corresponding EIF23..,1: A set EIF23 bit causes an interrupt request." bitfld.long 0x4 22. "EIRE22,External Interrupt Request Enable 22" "0: Interrupt requests from the corresponding EIF22..,1: A set EIF22bit causes an interrupt request." newline bitfld.long 0x4 21. "EIRE21,External Interrupt Request Enable 21" "0: Interrupt requests from the corresponding EIF21..,1: A set EIF21 bit causes an interrupt request." bitfld.long 0x4 20. "EIRE20,External Interrupt Request Enable 20" "0: Interrupt requests from the corresponding EIF20..,1: A set EIF20 bit causes an interrupt request." newline bitfld.long 0x4 19. "EIRE19,External Interrupt Request Enable 19" "0: Interrupt requests from the corresponding EIF19..,1: A set EIF19 bit causes an interrupt request." bitfld.long 0x4 18. "EIRE18,External Interrupt Request Enable 18" "0: Interrupt requests from the corresponding EIF18..,1: A set EIF18 bit causes an interrupt request." newline bitfld.long 0x4 17. "EIRE17,External Interrupt Request Enable 17" "0: Interrupt requests from the corresponding EIF17..,1: A set EIF17bit causes an interrupt request." bitfld.long 0x4 16. "EIRE16,External Interrupt Request Enable 16" "0: Interrupt requests from the corresponding EIF16..,1: A set EIF16 bit causes an interrupt request." newline bitfld.long 0x4 15. "EIRE15,External Interrupt Request Enable 15" "0: Interrupt requests from the corresponding EIF15..,1: A set EIF15 bit causes an interrupt request." bitfld.long 0x4 14. "EIRE14,External Interrupt Request Enable 14" "0: Interrupt requests from the corresponding EIF14..,1: A set EIF14 bit causes an interrupt request." newline bitfld.long 0x4 13. "EIRE13,External Interrupt Request Enable 13" "0: Interrupt requests from the corresponding EIF13..,1: A set EIF13 bit causes an interrupt request." bitfld.long 0x4 12. "EIRE12,External Interrupt Request Enable 12" "0: Interrupt requests from the corresponding EIF12..,1: A set EIF12 bit causes an interrupt request." newline bitfld.long 0x4 11. "EIRE11,External Interrupt Request Enable 11" "0: Interrupt requests from the corresponding EIF11..,1: A set EIF11 bit causes an interrupt request." bitfld.long 0x4 10. "EIRE10,External Interrupt Request Enable 10" "0: Interrupt requests from the corresponding EIF10..,1: A set EIF10 bit causes an interrupt request." newline bitfld.long 0x4 9. "EIRE9,External Interrupt Request Enable 9" "0: Interrupt requests from the corresponding EIF9..,1: A set EIF9 bit causes an interrupt request." bitfld.long 0x4 8. "EIRE8,External Interrupt Request Enable 8" "0: Interrupt requests from the corresponding EIF8..,1: A set EIF8 bit causes an interrupt request." newline bitfld.long 0x4 7. "EIRE7,External Interrupt Request Enable 7" "0: Interrupt requests from the corresponding EIF7..,1: A set EIF7 bit causes an interrupt request." bitfld.long 0x4 6. "EIRE6,External Interrupt Request Enable 6" "0: Interrupt requests from the corresponding EIF6..,1: A set EIF6 bit causes an interrupt request." newline bitfld.long 0x4 5. "EIRE5,External Interrupt Request Enable 5" "0: Interrupt requests from the corresponding EIF5..,1: A set EIF5 bit causes an interrupt request." bitfld.long 0x4 4. "EIRE4,External Interrupt Request Enable 4" "0: Interrupt requests from the corresponding EIF4..,1: A set EIF4 bit causes an interrupt request." newline bitfld.long 0x4 3. "EIRE3,External Interrupt Request Enable 3" "0: Interrupt requests from the corresponding EIF3..,1: A set EIF3 bit causes an interrupt request." bitfld.long 0x4 2. "EIRE2,External Interrupt Request Enable 2" "0: Interrupt requests from the corresponding EIF2..,1: A set EIF2 bit causes an interrupt request." newline bitfld.long 0x4 1. "EIRE1,External Interrupt Request Enable 1" "0: Interrupt requests from the corresponding EIF1..,1: A set EIF1 bit causes an interrupt request." bitfld.long 0x4 0. "EIRE0,External Interrupt Request Enable 0" "0: Interrupt requests from the corresponding EIF0..,1: A set EIF0 bit causes an interrupt request." line.long 0x8 "WRER,Wakeup Request Enable Register" bitfld.long 0x8 31. "WRE31,External Wakeup Request Enable 31" "0: System wakeup requests from the corresponding..,1: A set EIF31 bit causes a system wakeup request." bitfld.long 0x8 30. "WRE30,External Wakeup Request Enable 30" "0: System wakeup requests from the corresponding..,1: A set EIF30 bit causes a system wakeup request." newline bitfld.long 0x8 29. "WRE29,External Wakeup Request Enable 29" "0: System wakeup requests from the corresponding..,1: A set EIF29 bit causes a system wakeup request." bitfld.long 0x8 28. "WRE28,External Wakeup Request Enable 28" "0: System wakeup requests from the corresponding..,1: A set EIF28 bit causes a system wakeup request." newline bitfld.long 0x8 27. "WRE27,External Wakeup Request Enable 27" "0: System wakeup requests from the corresponding..,1: A set EIF27 bit causes a system wakeup request." bitfld.long 0x8 26. "WRE26,External Wakeup request.Enable 26" "0: System wakeup requests from the corresponding..,1: A set EIF26 bit causes a system wakeup request" newline bitfld.long 0x8 25. "WRE25,External Wakeup request.Enable 25" "0: System wakeup requests from the corresponding..,1: A set EIF25 bit causes a system wakeup request" bitfld.long 0x8 24. "WRE24,External Wakeup request.Enable 24" "0: System wakeup requests from the corresponding..,1: A set EIF24 bit causes a system wakeup request" newline bitfld.long 0x8 23. "WRE23,External Wakeup request.Enable 23" "0: System wakeup requests from the corresponding..,1: A set EIF23 bit causes a system wakeup request" bitfld.long 0x8 22. "WRE22,External Wakeup Request Enable 22" "0: System wakeup requests from the corresponding..,1: A set EIF22 bit causes a system wakeup request." newline bitfld.long 0x8 21. "WRE21,External Wakeup Request Enable 21" "0: System wakeup requests from the corresponding..,1: A set EIF21 bit causes a system wakeup request." bitfld.long 0x8 20. "WRE20,External Wakeup Request Enable 20" "0: System wakeup requests from the corresponding..,1: A set EIF20 bit causes a system wakeup request." newline bitfld.long 0x8 19. "WRE19,External Wakeup Request Enable 19" "0: System wakeup requests from the corresponding..,1: A set EIF19 bit causes a system wakeup request." bitfld.long 0x8 18. "WRE18,External Wakeup Request Enable 18" "0: System wakeup requests from the corresponding..,1: A set EIF18 bit causes a system wakeup request." newline bitfld.long 0x8 17. "WRE17,External Wakeup request.Enable 17" "0: System wakeup requests from the corresponding..,1: A set EIF17 bit causes a system wakeup request" bitfld.long 0x8 16. "WRE16,External Wakeup request.Enable 16" "0: System wakeup requests from the corresponding..,1: A set EIF16 bit causes a system wakeup request" newline bitfld.long 0x8 15. "WRE15,External Wakeup request.Enable 15" "0: System wakeup requests from the corresponding..,1: A set EIF15 bit causes a system wakeup request" bitfld.long 0x8 14. "WRE14,External Wakeup request.Enable 14" "0: System wakeup requests from the corresponding..,1: A set EIF14 bit causes a system wakeup request" newline bitfld.long 0x8 13. "WRE13,External Wakeup request.Enable 13" "0: System wakeup requests from the corresponding..,1: A set EIF13 bit causes a system wakeup request" bitfld.long 0x8 12. "WRE12,External Wakeup request.Enable 12" "0: System wakeup requests from the corresponding..,1: A set EIF12 bit causes a system wakeup request" newline bitfld.long 0x8 11. "WRE11,External Wakeup request.Enable 11" "0: System wakeup requests from the corresponding..,1: A set EIF11 bit causes a system wakeup request" bitfld.long 0x8 10. "WRE10,External Wakeup request.Enable 10" "0: System wakeup requests from the corresponding..,1: A set EIF10 bit causes a system wakeup request" newline bitfld.long 0x8 9. "WRE9,External Wakeup request.Enable 9" "0: System wakeup requests from the corresponding..,1: A set EIF9 bit causes a system wakeup request" bitfld.long 0x8 8. "WRE8,External Wakeup request.Enable 8." "0: System wakeup requests from the corresponding..,1: A set EIF8 bit causes a system wakeup request" newline bitfld.long 0x8 7. "WRE7,External Wakeup Request Enable 7" "0: System wakeup requests from the corresponding..,1: A set EIF7 bit causes a system wakeup request." bitfld.long 0x8 6. "WRE6,External Wakeup Request Enable 6" "0: System wakeup requests from the corresponding..,1: A set EIF6 bit causes a system wakeup request." newline bitfld.long 0x8 5. "WRE5,External Wakeup Request Enable 5" "0: System wakeup requests from the corresponding..,1: A set EIF5 bit causes a system wakeup request." bitfld.long 0x8 4. "WRE4,External Wakeup Request Enable 4" "0: System wakeup requests from the corresponding..,1: A set EIF4 bit causes a system wakeup request." newline bitfld.long 0x8 3. "WRE3,External Wakeup Request Enable 3" "0: System wakeup requests from the corresponding..,1: A set EIF3 bit causes a system wakeup request." bitfld.long 0x8 2. "WRE2,External Wakeup Request Enable 2" "0: System wakeup requests from the corresponding..,1: A set EIF2 bit causes a system wakeup request." newline bitfld.long 0x8 1. "WRE1,External Wakeup Request Enable 1" "0: System wakeup requests from the corresponding..,1: A set EIF1 bit causes a system wakeup request." bitfld.long 0x8 0. "WRE0,External Wakeup Request Enable 0" "0: System wakeup requests from the corresponding..,1: A set EIF0 bit causes a system wakeup request" group.long 0x28++0xF line.long 0x0 "WIREER,Wakeup/Interrupt Rising-Edge Event Enable Register" bitfld.long 0x0 31. "IREE31,External Interrupt Rising-edge Events Enable 31" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 30. "IREE30,External Interrupt Rising-edge Events Enable 30" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 29. "IREE29,External Interrupt Rising-edge Events Enable 29" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 28. "IREE28,External Interrupt Rising-edge Events Enable 28" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 27. "IREE27,External Interrupt Rising-edge Events Enable 27" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 26. "IREE26,External Interrupt Rising-edge Events Enable 26" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 25. "IREE25,External Interrupt Rising-edge Events Enable 25" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 24. "IREE24,External Interrupt Rising-edge Events Enable 24" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 23. "IREE23,External Interrupt Rising-edge Events Enable 23" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 22. "IREE22,External Interrupt Rising-edge Events Enable 22" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 21. "IREE21,External Interrupt Rising-edge Events Enable 21" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 20. "IREE20,External Interrupt Rising-edge Events Enable 20" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 19. "IREE19,External Interrupt Rising-edge Events Enable 19" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 18. "IREE18,External Interrupt Rising-edge Events Enable 18" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 17. "IREE17,External Interrupt Rising-edge Events Enable 17" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 16. "IREE16,External Interrupt Rising-edge Events Enable 16" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 15. "IREE15,External Interrupt Rising-edge Events Enable 15" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 14. "IREE14,External Interrupt Rising-edge Events Enable 14" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 13. "IREE13,External Interrupt Rising-edge Events Enable 13" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 12. "IREE12,External Interrupt Rising-edge Events Enable 12" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 11. "IREE11,External Interrupt Rising-edge Events Enable 11" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 10. "IREE10,External Interrupt Rising-edge Events Enable 10" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 9. "IREE9,External Interrupt Rising-edge Events Enable 9" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 8. "IREE8,External Interrupt Rising-edge Events Enable 8" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 7. "IREE7,External Interrupt Rising-edge Events Enable 7" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 6. "IREE6,External Interrupt Rising-edge Events Enable 6" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 5. "IREE5,External Interrupt Rising-edge Events Enable 5" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 4. "IREE4,External Interrupt Rising-edge Events Enable 4" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 3. "IREE3,External Interrupt Rising-edge Events Enable 3" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 2. "IREE2,External Interrupt Rising-edge Events Enable 2" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." newline bitfld.long 0x0 1. "IREE1,External Interrupt Rising-edge Events Enable 1" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." bitfld.long 0x0 0. "IREE0,External Interrupt Rising-edge Events Enable 0" "0: Rising-edge event is disabled.,1: Rising-edge event is enabled." line.long 0x4 "WIFEER,Wakeup/Interrupt Falling-Edge Event Enable Register" bitfld.long 0x4 31. "IFEE31,External Interrupt Falling-edge Events Enable 31" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 30. "IFEE30,External Interrupt Falling-edge Events Enable 30" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 29. "IFEE29,External Interrupt Falling-edge Events Enable 29" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 28. "IFEE28,External Interrupt Falling-edge Events Enable 28" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 27. "IFEE27,External Interrupt Falling-edge Events Enable 27" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 26. "IFEE26,External Interrupt Falling-edge Events Enable 26" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 25. "IFEE25,External Interrupt Falling-edge Events Enable 25" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 24. "IFEE24,External Interrupt Falling-edge Events Enable 24" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 23. "IFEE23,External Interrupt Falling-edge Events Enable 23" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 22. "IFEE22,External Interrupt Falling-edge Events Enable 22" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 21. "IFEE21,External Interrupt Falling-edge Events Enable 21" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 20. "IFEE20,External Interrupt Falling-edge Events Enable 20" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 19. "IFEE19,External Interrupt Falling-edge Events Enable 19" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 18. "IFEE18,External Interrupt Falling-edge Events Enable 18" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 17. "IFEE17,External Interrupt Falling-edge Events Enable 17" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 16. "IFEE16,External Interrupt Falling-edge Events Enable 16" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 15. "IFEE15,External Interrupt Falling-edge Events Enable 15" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 14. "IFEE14,External Interrupt Falling-edge Events Enable 14" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 13. "IFEE13,External Interrupt Falling-edge Events Enable 13" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 12. "IFEE12,External Interrupt Falling-edge Events Enable 12" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 11. "IFEE11,External Interrupt Falling-edge Events Enable 11" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 10. "IFEE10,External Interrupt Falling-edge Events Enable 10" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 9. "IFEE9,External Interrupt Falling-edge Events Enable 9" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 8. "IFEE8,External Interrupt Falling-edge Events Enable 8" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 7. "IFEE7,External Interrupt Falling-edge Events Enable 7" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 6. "IFEE6,External Interrupt Falling-edge Events Enable 6" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 5. "IFEE5,External Interrupt Falling-edge Events Enable 5" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 4. "IFEE4,External Interrupt Falling-edge Events Enable 4" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 3. "IFEE3,External Interrupt Falling-edge Events Enable 3" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 2. "IFEE2,External Interrupt Falling-edge Events Enable 2" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." newline bitfld.long 0x4 1. "IFEE1,External Interrupt Falling-edge Events Enable 1" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." bitfld.long 0x4 0. "IFEE0,External Interrupt Falling-edge Events Enable 0" "0: Falling-edge event is disabled.,1: Falling-edge event is enabled." line.long 0x8 "WIFER,Wakeup/Interrupt Filter Enable Register" bitfld.long 0x8 31. "IFE31,External Interrupt Filter Enable 31" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 30. "IFE30,External Interrupt Filter Enable 30" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 29. "IFE29,External Interrupt Filter Enable 29" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 28. "IFE28,External Interrupt Filter Enable 28" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 27. "IFE27,External Interrupt Filter Enable 27" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 26. "IFE26,External Interrupt Filter Enable 26" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 25. "IFE25,External Interrupt Filter Enable 25" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 24. "IFE24,External Interrupt Filter Enable 24" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 23. "IFE23,External Interrupt Filter Enable 23" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 22. "IFE22,External Interrupt Filter Enable 22" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 21. "IFE21,External Interrupt Filter Enable 21" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 20. "IFE20,External Interrupt Filter Enable 20" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 19. "IFE19,External Interrupt Filter Enable 19" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 18. "IFE18,External Interrupt Filter Enable 18" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 17. "IFE17,External Interrupt Filter Enable 17" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 16. "IFE16,External Interrupt Filter Enable 16" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 15. "IFE15,External Interrupt Filter Enable 15" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 14. "IFE14,External Interrupt Filter Enable 14" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 13. "IFE13,External Interrupt Filter Enable 13" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 12. "IFE12,External Interrupt Filter Enable 12" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 11. "IFE11,External Interrupt Filter Enable 11" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 10. "IFE10,External Interrupt Filter Enable 10" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 9. "IFE9,External Interrupt Filter Enable 9" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 8. "IFE8,External Interrupt Filter Enable 8" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 7. "IFE7,External Interrupt Filter Enable 7" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 6. "IFE6,External Interrupt Filter Enable 6" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 5. "IFE5,External Interrupt Filter Enable 5" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 4. "IFE4,External Interrupt Filter Enable 4" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 3. "IFE3,External Interrupt Filter Enable 3" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 2. "IFE2,External Interrupt Filter Enable 2" "0: Filter is disabled.,1: Filter is enabled." newline bitfld.long 0x8 1. "IFE1,External Interrupt Filter Enable 1" "0: Filter is disabled.,1: Filter is enabled." bitfld.long 0x8 0. "IFE0,External Interrupt Filter Enable 0" "0: Filter is disabled.,1: Filter is enabled." line.long 0xC "WIPUER,Wakeup/Interrupt Pull Enable Register" bitfld.long 0xC 31. "IPUE31,External Interrupt Pull Enable 31" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 30. "IPUE30,External Interrupt Pull Enable 30" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 29. "IPUE29,External Interrupt Pull Enable 29" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 28. "IPUE28,External Interrupt Pull Enable 28" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 27. "IPUE27,External Interrupt Pull Enable 27" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 26. "IPUE26,External Interrupt Pull Enable 26" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 25. "IPUE25,External Interrupt Pull Enable 25" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 24. "IPUE24,External Interrupt Pull Enable 24" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 23. "IPUE23,External Interrupt Pull Enable 23" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 22. "IPUE22,External Interrupt Pull Enable 22" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 21. "IPUE21,External Interrupt Pull Enable 21" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 20. "IPUE20,External Interrupt Pull Enable 20" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 19. "IPUE19,External Interrupt Pull Enable 19" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 18. "IPUE18,External Interrupt Pull Enable 18" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 17. "IPUE17,External Interrupt Pull Enable 17" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 16. "IPUE16,External Interrupt Pull Enable 16" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 15. "IPUE15,External Interrupt Pull Enable 15" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 14. "IPUE14,External Interrupt Pull Enable 14" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 13. "IPUE13,External Interrupt Pull Enable 13" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 12. "IPUE12,External Interrupt Pull Enable 12" "0: Pull is disabled.disabled.,1: Pull is enabled." newline bitfld.long 0xC 11. "IPUE11,External Interrupt Pull Enable 11" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 10. "IPUE10,External Interrupt Pull Enable 10" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 9. "IPUE9,External Interrupt Pull Enable 9" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 8. "IPUE8,External Interrupt Pull Enable 8" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 7. "IPUE7,External Interrupt Pull Enable 7" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 6. "IPUE6,External Interrupt Pull Enable 6" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 5. "IPUE5,External Interrupt Pull Enable 5" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 4. "IPUE4,External Interrupt Pull Enable 4" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 3. "IPUE3,External Interrupt Pull Enable 3" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 2. "IPUE2,External Interrupt Pull Enable 2" "0: Pull is disabled.,1: Pull is enabled." newline bitfld.long 0xC 1. "IPUE1,External Interrupt Pull Enable 1" "0: Pull is disabled.,1: Pull is enabled." bitfld.long 0xC 0. "IPUE0,External Interrupt Pull Enable 0" "0: Pull is disabled.,1: Pull is enabled." tree.end tree.end tree "XBIC (Crossbar Integrity Checker)" base ad:0x0 tree "XBIC_0" base ad:0x723E0000 group.long 0x0++0x7 line.long 0x0 "MCR,Module Control Register" bitfld.long 0x0 31. "SE0,Slave Port Enable for EDC error detection" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." bitfld.long 0x0 30. "SE1,Slave Port Enable for EDC error detection" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." newline bitfld.long 0x0 29. "SE2,Slave Port Enable for EDC error detection" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." bitfld.long 0x0 28. "SE3,Slave Port Enable for EDC error detection" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." newline bitfld.long 0x0 27. "SE4,Slave Port Enable for EDC error detection" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." bitfld.long 0x0 26. "SE5,Slave Port Enable for EDC error detection" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." newline bitfld.long 0x0 25. "SE6,Slave Port Enable for EDC error detection" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." bitfld.long 0x0 24. "SE7,Slave Port Enable for EDC error detection" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." newline bitfld.long 0x0 23. "ME0,Master Port Enable for slave driven signal safety check" "0: Attribute integrity checking disabled for master..,1: Attribute integrity checking enabled for master.." bitfld.long 0x0 22. "ME1,Master Port Enable for slave driven signal safety check" "0: Attribute integrity checking disabled for master..,1: Attribute integrity checking enabled for master.." newline bitfld.long 0x0 21. "ME2,Master Port Enable for slave driven signal safety check" "0: Attribute integrity checking disabled for master..,1: Attribute integrity checking enabled for master.." bitfld.long 0x0 20. "ME3,Master Port Enable for slave driven signal safety check" "0: Attribute integrity checking disabled for master..,1: Attribute integrity checking enabled for master.." newline bitfld.long 0x0 19. "ME4,Master Port Enable for slave driven signal safety check" "0: Attribute integrity checking disabled for master..,1: Attribute integrity checking enabled for master.." bitfld.long 0x0 18. "ME5,Master Port Enable for slave driven signal safety check" "0: Attribute integrity checking disabled for master..,1: Attribute integrity checking enabled for master.." newline bitfld.long 0x0 17. "ME6,Master Port Enable for slave driven signal safety check" "0: Attribute integrity checking disabled for master..,1: Attribute integrity checking enabled for master.." bitfld.long 0x0 16. "ME7,Master Port Enable for slave driven signal safety check" "0: Attribute integrity checking disabled for master..,1: Attribute integrity checking enabled for master.." line.long 0x4 "EIR,Error Injection Register" bitfld.long 0x4 31. "EIE,Error Injection Enable" "0: Error injection disabled,1: Error injection enabled" bitfld.long 0x4 12.--14. "SLV,Target Slave Port" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "MST,Target Master ID" hexmask.long.byte 0x4 0.--7. 1. "SYN,Syndrome" rgroup.long 0x8++0x7 line.long 0x0 "ESR,Error Status Register" bitfld.long 0x0 31. "VLD,Error Status Valid" "0: No error detected other fields of the ESR and..,1: Error detected all fields of the ESR and EAR are.." bitfld.long 0x0 30. "DPSE0,Data phase slave port error" "0: No error on slave port 0,1: Data phase error on slave port 0" newline bitfld.long 0x0 29. "DPSE1,Data phase slave port error" "0: No error on slave port 1,1: Data phase error on slave port 1" bitfld.long 0x0 28. "DPSE2,Data phase slave port error" "0: No error on slave port 2,1: Data phase error on slave port 2" newline bitfld.long 0x0 27. "DPSE3,Data phase slave port error" "0: No error on slave port 3,1: Data phase error on slave port 3" bitfld.long 0x0 22. "DPME0,Data phase master port error" "0: No error on master port 0,1: Data phase error on master port 0" newline bitfld.long 0x0 21. "DPME1,Data phase master port error" "0: No error on master port 1,1: Data phase error on master port 1" bitfld.long 0x0 20. "DPME2,Data phase master port error" "0: No error on master port 2,1: Data phase error on master port 2" newline bitfld.long 0x0 19. "DPME3,Data phase master port error" "0: No error on master port 3,1: Data phase error on master port 3" bitfld.long 0x0 12.--14. "SLV,Slave Port" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "MST,Master ID" hexmask.long.byte 0x0 0.--7. 1. "SYN,Syndrome" line.long 0x4 "EAR,Error Address Register" hexmask.long 0x4 0.--31. 1. "ADDR,The address of the last transfer with an error." tree.end tree "XBIC_1" base ad:0x717E0000 group.long 0x0++0x7 line.long 0x0 "MCR,Module Control Register" bitfld.long 0x0 31. "SE0,Slave Port Enable for EDC error detection" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." bitfld.long 0x0 30. "SE1,Slave Port Enable for EDC error detection" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." newline bitfld.long 0x0 29. "SE2,Slave Port Enable for EDC error detection" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." bitfld.long 0x0 28. "SE3,Slave Port Enable for EDC error detection" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." newline bitfld.long 0x0 27. "SE4,Slave Port Enable for EDC error detection" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." bitfld.long 0x0 26. "SE5,Slave Port Enable for EDC error detection" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." newline bitfld.long 0x0 25. "SE6,Slave Port Enable for EDC error detection" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." bitfld.long 0x0 24. "SE7,Slave Port Enable for EDC error detection" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." newline bitfld.long 0x0 23. "ME0,Master Port Enable for slave driven signal safety check" "0: Attribute integrity checking disabled for master..,1: Attribute integrity checking enabled for master.." bitfld.long 0x0 22. "ME1,Master Port Enable for slave driven signal safety check" "0: Attribute integrity checking disabled for master..,1: Attribute integrity checking enabled for master.." newline bitfld.long 0x0 21. "ME2,Master Port Enable for slave driven signal safety check" "0: Attribute integrity checking disabled for master..,1: Attribute integrity checking enabled for master.." bitfld.long 0x0 20. "ME3,Master Port Enable for slave driven signal safety check" "0: Attribute integrity checking disabled for master..,1: Attribute integrity checking enabled for master.." newline bitfld.long 0x0 19. "ME4,Master Port Enable for slave driven signal safety check" "0: Attribute integrity checking disabled for master..,1: Attribute integrity checking enabled for master.." bitfld.long 0x0 18. "ME5,Master Port Enable for slave driven signal safety check" "0: Attribute integrity checking disabled for master..,1: Attribute integrity checking enabled for master.." newline bitfld.long 0x0 17. "ME6,Master Port Enable for slave driven signal safety check" "0: Attribute integrity checking disabled for master..,1: Attribute integrity checking enabled for master.." bitfld.long 0x0 16. "ME7,Master Port Enable for slave driven signal safety check" "0: Attribute integrity checking disabled for master..,1: Attribute integrity checking enabled for master.." line.long 0x4 "EIR,Error Injection Register" bitfld.long 0x4 31. "EIE,Error Injection Enable" "0: Error injection disabled,1: Error injection enabled" bitfld.long 0x4 12.--14. "SLV,Target Slave Port" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "MST,Target Master ID" hexmask.long.byte 0x4 0.--7. 1. "SYN,Syndrome" rgroup.long 0x8++0x7 line.long 0x0 "ESR,Error Status Register" bitfld.long 0x0 31. "VLD,Error Status Valid" "0: No error detected other fields of the ESR and..,1: Error detected all fields of the ESR and EAR are.." bitfld.long 0x0 30. "DPSE0,Data phase slave port error" "0: No error on slave port 0,1: Data phase error on slave port 0" newline bitfld.long 0x0 29. "DPSE1,Data phase slave port error" "0: No error on slave port 1,1: Data phase error on slave port 1" bitfld.long 0x0 28. "DPSE2,Data phase slave port error" "0: No error on slave port 2,1: Data phase error on slave port 2" newline bitfld.long 0x0 27. "DPSE3,Data phase slave port error" "0: No error on slave port 3,1: Data phase error on slave port 3" bitfld.long 0x0 22. "DPME0,Data phase master port error" "0: No error on master port 0,1: Data phase error on master port 0" newline bitfld.long 0x0 21. "DPME1,Data phase master port error" "0: No error on master port 1,1: Data phase error on master port 1" bitfld.long 0x0 20. "DPME2,Data phase master port error" "0: No error on master port 2,1: Data phase error on master port 2" newline bitfld.long 0x0 19. "DPME3,Data phase master port error" "0: No error on master port 3,1: Data phase error on master port 3" bitfld.long 0x0 12.--14. "SLV,Slave Port" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "MST,Master ID" hexmask.long.byte 0x0 0.--7. 1. "SYN,Syndrome" line.long 0x4 "EAR,Error Address Register" hexmask.long 0x4 0.--31. 1. "ADDR,The address of the last transfer with an error." tree.end tree.end AUTOINDENT.OFF